text
stringlengths 59
71.4k
|
|---|
//------------------------------------------------------------------------------
// Title : Synchronous Reset generation flip-flop pair
// Project : Tri-Mode ethernet MAC
//------------------------------------------------------------------------------
// File : reset_sync.v
// Author : Xilinx, Inc.
//------------------------------------------------------------------------------
// Description: Both flip-flops have the same asynchronous reset signal.
// Together the flops create a minimum of a 1 clock period
// duration pulse which is used for synchronous reset.
//
// The flops are placed, using RLOCs, into the same slice.
// -----------------------------------------------------------------------------
// (c) Copyright 2006-2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
`timescale 1ps/1ps
module reset_sync #(
parameter INITIALISE = 2'b11
)
(
input reset_in,
input clk,
input enable,
output reset_out
);
wire reset_stage1;
wire reset_stage2;
(* ASYNC_REG = "TRUE", RLOC = "X0Y0", SHREG_EXTRACT = "NO", INIT = "1" *)
FDPE #(
.INIT (INITIALISE[0])
) reset_sync1 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (1'b0),
.Q (reset_stage1)
);
(* ASYNC_REG = "TRUE", RLOC = "X0Y0", SHREG_EXTRACT = "NO", INIT = "1" *)
FDPE #(
.INIT (INITIALISE[1])
) reset_sync2 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (reset_stage1),
.Q (reset_stage2)
);
assign reset_out = reset_stage2;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_V
/**
* srdlrtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_pr_pp_pkg_s.v"
`celldefine
module sky130_fd_sc_lp__srdlrtp (
Q ,
RESET_B,
D ,
GATE ,
SLEEP_B
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input SLEEP_B;
// Local signals
wire buf_Q;
wire RESET;
wire kapwr;
wire vgnd ;
wire vpwr ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PKG$s `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, SLEEP_B, kapwr, vgnd, vpwr);
bufif1 bufif10 (Q , buf_Q, vpwr );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_V
|
module block_memory(
input clock, reset, enable,
input [4:0] row1, row2, // 0~29
input [4:0] col1, col2, // 0~9
input [1:0] func,
input [1:0] stage,
output [2:0] block1, block2,
output ready
);
`include "def.v"
localparam MAXROW = 30;
localparam READY = 2'b00;
reg write;
reg [4:0] cnt, addr1;
wire [4:0] addr2;
reg [1:0] state, next_state;
reg [1:0] rom_stage;
wire [29:0] rom_out, out1, out2;
reg [29:0] mem_out, last_out, w_data;
wire rom_enable, end_func, m_write;
assign ready = state == READY;
assign block1 = (out1 >> col1*3) & 3'b111;
assign block2 = (out2 >> col2*3) & 3'b111;
// memory control
assign addr2 = row2;
always @(*)
begin
case (state)
READY: addr1 = row1;
F_LOAD: addr1 = cnt;
default: begin
if (write)
addr1 = cnt;
else if (state == F_PULL)
addr1 = cnt+1;
else
addr1 = cnt-1;
end
endcase
end
assign m_write = state == READY ? enable && func == 2'b00 : write;
memory mem(clock, m_write, addr1, addr2, w_data, out1, out2);
assign rom_enable = state == F_LOAD;
stage_rom rom(clock, rom_enable, cnt, rom_stage, rom_out);
// counter
always @(posedge clock)
begin
if (reset) begin
cnt <= 5'b00000;
end else if (state == READY) begin
if (next_state == F_DROP)
cnt <= 5'd29;
else
cnt <= 5'd0;
end else if (write) begin
if (state == F_DROP)
cnt <= cnt - 1;
else
cnt <= cnt + 1;
end
end
// state control
always @(posedge clock)
begin
if (reset) state <= READY;
else state <= next_state;
end
assign end_func = state == F_DROP ? cnt == 5'b00000 && write : (cnt == MAXROW-1 && write);
always @(*)
begin
if (end_func)
next_state = READY;
else case (state)
READY: next_state = enable ? func : READY;
F_LOAD: next_state = F_LOAD;
F_PULL: next_state = F_PULL;
F_DROP: next_state = F_DROP;
default: next_state = 2'bxx;
endcase
end
// load stage
always @(posedge clock)
begin
if (reset)
rom_stage <= 2'b00;
else if (enable && func == F_LOAD && ready)
rom_stage <= stage;
end
// pull/drop
always @(posedge clock)
begin
if (~write)
case (state)
F_PULL: begin
if (cnt == 5'd29)
mem_out <= 30'b000000000000000000000000000000;
else
mem_out <= out1;
end
F_DROP: begin
if (cnt == 5'b00000)
mem_out <= 30'b000000000000000000000000000000;
else
mem_out <= out1;
end
default: mem_out <= 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
endcase
else
mem_out <= 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
end
always @(*)
begin
if (state == READY)
w_data = out1 &(30'b111111111111111111111111111111 ^ (3'b111 << col1*3));
else if (state == F_LOAD)
w_data = rom_out;
else
w_data = mem_out;
end
always @(posedge clock)
begin
if (ready)
write <= 1'b0;
else
write <= ~write;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& a) { in >> a.first >> a.second; return in; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2> a) { out << a.first << << a.second; return out; } template <typename T, typename T1> T amax(T& a, T1 b) { if (b > a) a = b; return a; } template <typename T, typename T1> T amin(T& a, T1 b) { if (b < a) a = b; return a; } const long long fx[] = {+1, -1, +0, +0}; const long long fy[] = {+0, +0, +1, -1}; const int32_t M = 1e9 + 7; const int32_t MM = 998244353; void solve() { long long n; cin >> n; vector<long long> a(n), b(n); for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) { cin >> b[i]; } vector<long long> points(n, 1); long long only_a = 0; long long pa = 0, push_back = 0; for (long long i = 0; i < n; i++) { if (a[i] == 1 && b[i] == 0) { only_a++; } if (a[i] == 1) pa++; if (b[i] == 1) push_back++; } if (pa > push_back) { cout << 1 << n ; return; } else if (only_a == 0 && pa <= push_back) { cout << -1 << n ; } else { long long diff = push_back - pa + 1; long long x = 1 + diff / only_a; if (diff % only_a != 0) x++; cout << x << n ; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) solve(); return 0; }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_ctlif #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
output reg irq,
output reg start,
input busy,
/* Address generator interface */
output reg [28:0] dma_base,
output reg [6:0] hmesh_last,
output reg [6:0] vmesh_last,
/* Register file interface */
output [6:0] cr_addr,
input [31:0] cr_di,
output [31:0] cr_do,
output cr_w_en,
/* Program memory interface */
output reg [1:0] cp_page,
output [8:0] cp_offset,
input [31:0] cp_di,
output [31:0] cp_do,
output cp_w_en,
/* Diagnostic registers */
input vnext,
input err_collision,
input err_stray,
input [10:0] pc,
input [31:0] wbm_adr_o,
input wbm_ack_i
);
reg [31:0] last_dma;
always @(posedge sys_clk)
if(wbm_ack_i)
last_dma <= wbm_adr_o;
reg old_busy;
always @(posedge sys_clk) begin
if(sys_rst)
old_busy <= 1'b0;
else
old_busy <= busy;
end
reg [13:0] vertex_counter;
reg [10:0] collision_counter;
reg [10:0] stray_counter;
wire csr_selected = csr_a[13:10] == csr_addr;
reg [31:0] csr_do_r;
reg csr_do_cont;
reg csr_do_regf;
reg csr_do_prog;
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do_r <= 32'd0;
csr_do_cont <= 1'b0;
csr_do_regf <= 1'b0;
csr_do_prog <= 1'b0;
irq <= 1'b0;
start <= 1'b0;
dma_base <= 29'd0;
hmesh_last <= 7'd0;
vmesh_last <= 7'd0;
cp_page <= 2'd0;
vertex_counter <= 14'd0;
collision_counter <= 11'd0;
stray_counter <= 11'd0;
end else begin
irq <= old_busy & ~busy;
if(vnext) vertex_counter <= vertex_counter + 14'd1;
if(err_collision) collision_counter <= collision_counter + 11'd1;
if(err_stray) stray_counter <= stray_counter + 11'd1;
csr_do_cont <= 1'b0;
csr_do_prog <= 1'b0;
csr_do_regf <= 1'b0;
start <= 1'b0;
/* Read control registers */
case(csr_a[3:0])
4'b0000: csr_do_r <= busy;
4'b0001: csr_do_r <= {dma_base, 3'b000};
4'b0010: csr_do_r <= hmesh_last;
4'b0011: csr_do_r <= vmesh_last;
4'b0100: csr_do_r <= cp_page;
4'b0101: csr_do_r <= vertex_counter;
4'b0110: csr_do_r <= collision_counter;
4'b0111: csr_do_r <= stray_counter;
4'b1000: csr_do_r <= last_dma;
4'b1001: csr_do_r <= pc;
default: csr_do_r <= 32'bx;
endcase
if(csr_selected) begin
/* Generate enables for the one-hot mux on csr_do */
csr_do_cont <= ~csr_a[8] & ~csr_a[9];
csr_do_regf <= csr_a[8];
csr_do_prog <= csr_a[9];
/* Write control registers */
if(
csr_we /* if this is a write cycle */
& ~csr_a[8] /* which is not for register file */
& ~csr_a[9] /* nor for program memory */
)
begin
/* then it is for control registers */
case(csr_a[2:0])
3'b000: begin
start <= csr_di[0];
vertex_counter <= 14'd0;
collision_counter <= 11'd0;
stray_counter <= 11'd0;
end
3'b001: dma_base <= csr_di[31:3];
3'b010: hmesh_last <= csr_di[6:0];
3'b011: vmesh_last <= csr_di[6:0];
3'b100: cp_page <= csr_di[1:0];
default:;
endcase
end
end
end
end
/*
* Program memory and register file have synchronous read,
* so we must use some tricks to move the registers into them.
*/
assign csr_do =
({32{csr_do_cont}} & csr_do_r)
|({32{csr_do_prog}} & cp_di)
|({32{csr_do_regf}} & cr_di);
assign cp_offset = csr_a[8:0];
assign cp_w_en = csr_selected & csr_a[9] & csr_we;
assign cp_do = csr_di;
assign cr_addr = csr_a[6:0];
assign cr_w_en = csr_selected & ~csr_a[9] & csr_a[8] & csr_we;
assign cr_do = csr_di;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool sortin(const pair<long long int, long long int> &e, const pair<long long int, long long int> &f) { return (e.first < f.first); } long long int i, j, k, l, m, n, c, p, q, ts, mn = 10e17; long long int a[200002], b[200002], x[200002]; int main() { { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); }; cin >> n; cin >> m; l = n - m; string s, t, u, v; cin >> s; cin >> t; v = s; for (long long int i = 0; i <= n - 1; i++) u += a ; for (long long int i = 0; i <= n - 1; i++) { if (!l) break; if (s[i] == t[i]) u[i] = s[i], v[i] = . , l--; else u[i] = a ; } if (l) { for (long long int i = 0; i <= n - 1; i++) { if (v[i] == . ) continue; if (c % 2) u[i] = s[i], v[i] = . ; else u[i] = t[i], v[i] = . ; c++; if (c % 2 == 0) l--; if (!l) break; } } if (l) { cout << -1; return 0; } for (long long int i = 0; i <= n - 1; i++) { if (v[i] == . ) { if (s[i] != u[i]) p++; if (t[i] != u[i]) q++; continue; } if (s[i] == a ) { u[i] = b ; if (t[i] == b ) u[i] = c ; } else if (t[i] == a ) { u[i] = b ; if (s[i] == b ) u[i] = c ; } if (s[i] != u[i]) p++; if (t[i] != u[i]) q++; } if (p != m || q != m) { cout << -1; return 0; } cout << u; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, i, m, s = 0, d = 0; cin >> n >> m; long long a[n], b[n], c[n]; for (i = 0; i < n; i++) { cin >> a[i] >> b[i]; s += a[i]; c[i] = a[i] - b[i]; } sort(c, c + n); for (i = 0; i < n; i++) if (s > m) { s = s - c[n - 1 - i]; d++; } if (s > m) cout << -1; else cout << d; } int main() { long long a; solve(); return 0; }
|
`default_nettype none
`timescale 1ns / 1ps
// The receiver core provides a ITU V.4-compatible bit-serial interface.
// The receiver is broadly broken up into three parts: the Wishbone B4
// slave interface, the transmitter, and the receiver.
//
// This module defines the V.4-compatible receiver.
//
// Note that if both eedd_i and eedc_i are low, the receiver never
// sees any edges to transition with, and therefore can be used to
// disable the receiver.
//
// eedd_i eedc_i Results
// 0 0 Disable receiver.
// 0 1 Receiver clocks on RXC input only. [1]
// 1 0 Receiver clocks on RXD input only. [2]
// 1 1 Receiver clocks on any edge it can find. [1, 2]
//
// Note 1: Only the rising edge of RXC is recognized.
// Note 2: Both rising AND falling edges of RXD are recognized.
module receiver(
input clk_i,
input reset_i,
// These inputs correspond to fields found in the register
// set of the receiver. Register set not included.
input [5:0] bits_i,
input [BRW:0] baud_i,
input eedd_i, // Enable Edge Detect on Data
input eedc_i, // Enable Edge Detect on Clock
// Inputs from external hardware
input rxd_i,
input rxc_i,
// Outputs to receiver FIFO.
output [SRW:0] dat_o,
output idle_o,
// Test outputs.
output sample_to
);
parameter SHIFT_REG_WIDTH = 16;
parameter BAUD_RATE_WIDTH = 32;
parameter SRW = SHIFT_REG_WIDTH - 1;
parameter BRW = BAUD_RATE_WIDTH - 1;
reg [SRW:0] shiftRegister;
reg [BRW:0] sampleCtr;
reg [5:0] bitsLeft;
reg d0, d1, c0, c1;
wire edgeDetected = (eedd_i & (d0 ^ d1)) | (eedc_i & (~c1 & c0));
wire sampleBit = ~idle_o && (sampleCtr == 0);
wire [SRW:0] shiftRegister_rev;
genvar i;
generate
for(i = 0; i <= SRW; i = i + 1) begin
assign shiftRegister_rev[i] = shiftRegister[SRW-i];
end
endgenerate
assign idle_o = (bitsLeft == 0);
assign dat_o = shiftRegister;
always @(posedge clk_i) begin
shiftRegister <= shiftRegister;
bitsLeft <= bitsLeft;
sampleCtr <= sampleCtr;
d1 <= d0;
d0 <= rxd_i;
c1 <= c0;
c0 <= rxc_i;
if(reset_i) begin
shiftRegister <= ~(0);
bitsLeft <= 0;
sampleCtr <= baud_i;
d0 <= 1;
d1 <= 1;
end
else begin
if(edgeDetected) begin
if(idle_o) begin
bitsLeft <= bits_i;
end
sampleCtr <= {1'b0, baud_i[BRW:1]};
end
else if(sampleBit) begin
sampleCtr <= baud_i;
bitsLeft <= bitsLeft - 1;
shiftRegister <= {d0, shiftRegister[SRW:1]};
end
else if(idle_o) begin
sampleCtr <= baud_i;
end
else begin
sampleCtr <= sampleCtr - 1;
end
end
end
assign sample_to = sampleBit;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + c - 0 ; c = getchar(); } return x * f; } int w, h, n, l, r; char opt[3]; set<int> a, b; multiset<int> f, g; int main() { w = read(), h = read(), n = read(); a.insert(0), b.insert(0); a.insert(w), b.insert(h); f.insert(w), g.insert(h); for (int i = 1; i <= n; i++) { scanf( %s , opt + 1); int x = read(); if (opt[1] == V ) { r = (*a.lower_bound(x)); l = (*(--a.lower_bound(x))); f.erase(f.find(r - l)); f.insert(r - x), f.insert(x - l); a.insert(x); } else { r = (*b.lower_bound(x)); l = (*(--b.lower_bound(x))); g.erase(g.find(r - l)); g.insert(r - x), g.insert(x - l); b.insert(x); } printf( %I64d n , 1LL * (*(--f.end())) * (*(--g.end()))); } return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 200MHz
* Reset: Push button, active high
*/
input wire clk_200mhz_p,
input wire clk_200mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_200mhz_ibufg;
// Internal 125 MHz clock
wire clk_mmcm_out;
wire clk_int;
wire rst_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS
clk_200mhz_ibufgds_inst(
.I(clk_200mhz_p),
.IB(clk_200mhz_n),
.O(clk_200mhz_ibufg)
);
// MMCM instance
// 200 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(8),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(5.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_200mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
fpga_core #(
.TARGET("XILINX")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* Ethernet: 1000BASE-T GMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_gtx_clk(phy_gtx_clk),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRBP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFRBP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRBP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCIN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__FAHCIN_BEHAVIORAL_PP_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCIN_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; inline long long add(long long a, long long b) { a = (a + b); if (a >= 1000000007) a -= 1000000007; return a; } inline long long sub(long long a, long long b) { a = a - b; if (a < 0) a += 1000000007; return a; } inline long long mul(long long a, long long b) { a = (a * b) % 1000000007; return a; } const long long N = 1e6 + 5; vector<long long> arr1(N, 0); void pre() { for (long long i = 2; i < N; i++) { if (arr1[i] == 0) { for (long long j = i; j < N; j += i) { if (arr1[j] == 0) arr1[j] = i; } } } } void mymain() { long long n; cin >> n; vector<long long> arr(n); for (long long& i : arr) cin >> i; long long ans = 1; vector<long long> dp(n + 1, 1); for (long long i = 1; i <= n; i++) { for (long long j = 2; j * i <= n; j++) { long long k = j * i; if (arr[k - 1] > arr[i - 1]) { dp[k] = max(dp[k], dp[i] + 1); } } } for (long long i : dp) ans = max(i, ans); cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long t = 1; cin >> t; pre(); for (long long tt = 0; tt < t; tt++) { mymain(); } return 0; }
|
// File: read_pointerTBV.v
// Generated by MyHDL 0.10
// Date: Mon Aug 27 20:10:12 2018
`timescale 1ns/10ps
module read_pointerTBV (
);
// myHDL -> Verilog Testbench for `read_pointer` module
reg clk = 0;
reg rst_n = 0;
reg rd = 0;
reg fifo_empty = 0;
wire [4:0] rptr;
wire fifo_rd;
wire read_pointer0_0_fifo_rd_i;
reg [4:0] read_pointer0_0_rptr_i = 0;
always @(rd, fifo_rd, fifo_empty, rst_n, rptr, clk) begin: READ_POINTERTBV_PRINT_DATA
$write("%h", rd);
$write(" ");
$write("%h", fifo_empty);
$write(" ");
$write("%h", rptr);
$write(" ");
$write("%h", fifo_rd);
$write(" ");
$write("%h", clk);
$write(" ");
$write("%h", rst_n);
$write("\n");
end
assign read_pointer0_0_fifo_rd_i = ((!fifo_empty) && rd);
always @(posedge clk, negedge rst_n) begin: READ_POINTERTBV_READ_POINTER0_0_POINTERUPDATE
if (rst_n) begin
read_pointer0_0_rptr_i <= 0;
end
else if (read_pointer0_0_fifo_rd_i) begin
read_pointer0_0_rptr_i <= (read_pointer0_0_rptr_i + 1);
end
else begin
read_pointer0_0_rptr_i <= read_pointer0_0_rptr_i;
end
end
assign fifo_rd = read_pointer0_0_fifo_rd_i;
assign rptr = read_pointer0_0_rptr_i;
initial begin: READ_POINTERTBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: READ_POINTERTBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
case (i)
'h0: begin
rd <= 1;
end
'ha: begin
rd <= 0;
end
'hc: begin
rd <= 1;
end
'he: begin
fifo_empty <= 1;
end
'h10: begin
rst_n <= 1;
end
'h12: begin
rst_n <= 0;
end
'h14: begin
$finish;
end
default: begin
// pass
end
endcase
i = i + 1;
@(posedge clk);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long INFF = 0x3f3f3f3f3f3f3f3fll; const long long M = 1e9 + 7; const long long maxn = 2e5 + 7; const double eps = 0.00000001; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <typename T> inline T abs(T a) { return a > 0 ? a : -a; } void exgcd(long long a, long long b, long long &d, long long &x, long long &y) { if (!b) { d = a; x = 1; y = 0; } else { exgcd(b, a % b, d, y, x); y -= a / b * x; } } int n, m; int i, j; bool used[maxn]; vector<int> v[maxn]; int num[maxn], fa[maxn], mx; int pp = 1; void print(int mx) { if (fa[mx]) print(fa[mx]); long long a, b, t; for (i = 0; i < v[mx].size(); i++) { exgcd(pp, m, t, a, b); printf( %I64d , (v[mx][i] / t * a % m + m) % m); pp = v[mx][i]; } } int main() { scanf( %d%d , &n, &m); for (i = 0; i < n; i++) scanf( %d , &j), used[j] = 1; for (i = 1; i < m; i++) if (!used[i]) v[gcd(i, m)].push_back(i); for (i = 1; i < m; i++) { if ((num[i] += v[i].size()) > num[mx]) mx = i; for (j = i << 1; j < m; j += i) if (num[j] < num[i]) num[j] = num[i], fa[j] = i; } printf( %d n , num[mx] + !used[0]); print(mx); if (!used[0]) puts( 0 ); else puts( ); }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2E5 + 10; const int P = 1E9 + 7; int n, q; struct node { int l, r, id; } qu[MAXN]; int a[MAXN], pri[1100], cnt; int num[1000001]; long long ans[MAXN]; long long bin[MAXN]; vector<int> dir[1000001]; vector<int> rec[MAXN]; int pow(int a, int n) { long long b = a; long long ret = 1; while (n) { if (n & 1) ret = ret * b % P; b = b * b % P; n >>= 1; } return ret; } bool cmp(node n1, node n2) { if (n1.l != n2.l) return n1.l < n2.l; else return n1.r < n2.r; } bool prime(int p) { for (int i = 0; pri[i] * pri[i] <= p; i++) if (!(p % pri[i])) return false; return true; } void init() { pri[cnt = 0] = 2; for (int i = 3; i < 100000; i++) if (prime(i)) pri[++cnt] = i; cnt++; for (int i = 0; i < MAXN; i++) rec[i].clear(); for (int i = 0; i < MAXN; i++) bin[i] = 1; for (int i = 0; i < 1000001; i++) dir[i].clear(); memset(num, 0, sizeof(num)); } int exgcd(long long a, long long b, long long &x, long long &y) { if (a == 0) { x = 0; y = 1; return b; } else { long long tx, ty; long long d = exgcd(b % a, a, tx, ty); x = ty - (b / a) * tx; y = tx; return d; } } int inverse(int k) { long long a = k, b = P, x, y; exgcd(a, b, x, y); return (x % P + P) % P; } int main() { int temp, l, u, v; init(); scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); scanf( %d , &q); for (int i = 0; i < q; i++) { scanf( %d%d , &qu[i].l, &qu[i].r); qu[i].id = i; } sort(qu, qu + q, cmp); for (int i = 1; i <= n; i++) { for (int j = 0; pri[j] * pri[j] <= a[i]; j++) { while (a[i] % pri[j] == 0) { a[i] /= pri[j]; if (dir[pri[j]].empty()) temp = pri[j] - 1; else temp = pri[j]; dir[pri[j]].push_back(i); rec[i].push_back(pri[j]); for (int k = i; k <= n; k += k & -k) bin[k] = bin[k] * temp % P; } } if (a[i] != 1) { if (dir[a[i]].empty()) temp = a[i] - 1; else temp = a[i]; dir[a[i]].push_back(i); rec[i].push_back(a[i]); for (int k = i; k <= n; k += k & -k) bin[k] = bin[k] * temp % P; } } l = 1; for (int i = 0; i < q; i++) { for (; l < qu[i].l; l++) { for (int j = 0; j < rec[l].size(); j++) { u = rec[l][j]; if (num[u] < dir[u].size() - 1) v = dir[u][++num[u]]; else v = n + 1; temp = (long long)(u - 1) * inverse(u) % P; for (int k = v; k <= n; k += k & -k) bin[k] = bin[k] * temp % P; } } temp = qu[i].id; ans[temp] = 1; for (int k = qu[i].l - 1; k > 0; k -= k & -k) ans[temp] = ans[temp] * bin[k] % P; ans[temp] = inverse(ans[temp]); for (int k = qu[i].r; k > 0; k -= k & -k) { ans[temp] = ans[temp] * bin[k] % P; } } for (int i = 0; i < q; i++) printf( %lld n , ans[i]); }
|
#include <bits/stdc++.h> using namespace std; priority_queue<long long, vector<long long>, greater<long long>> q; int a[100005]; int main() { int n, x; long long b = 0, s; scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 1; i <= n; ++i) { scanf( %d , &x); s = 0; q.push(a[i] + b); while (!q.empty() && q.top() <= b + x) { s += q.top() - b; q.pop(); } printf( %I64d , s + (long long)q.size() * x); b += x; } return 0; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n", $time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_usr_addr_fifo.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Mon Aug 28 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module instantiates the block RAM based FIFO to store the user
// address and the command information. Also calculates potential bank/row
// conflicts by comparing the new address with last address issued.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_usr_addr_fifo #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter CS_BITS = 0,
parameter ROW_WIDTH = 14
)
(
input clk0,
input rst0,
input [2:0] app_af_cmd,
input [30:0] app_af_addr,
input app_af_wren,
input ctrl_af_rden,
output [2:0] af_cmd,
output [30:0] af_addr,
output af_empty,
output app_af_afull
);
wire [35:0] fifo_data_out;
reg rst_r;
always @(posedge clk0)
rst_r <= rst0;
//***************************************************************************
assign af_cmd = fifo_data_out[33:31];
assign af_addr = fifo_data_out[30:0];
//***************************************************************************
FIFO36 #
(
.ALMOST_EMPTY_OFFSET (13'h0007),
.ALMOST_FULL_OFFSET (13'h000F),
.DATA_WIDTH (36),
.DO_REG (1),
.EN_SYN ("TRUE"),
.FIRST_WORD_FALL_THROUGH ("FALSE")
)
u_af
(
.ALMOSTEMPTY (),
.ALMOSTFULL (app_af_afull),
.DO (fifo_data_out[31:0]),
.DOP (fifo_data_out[35:32]),
.EMPTY (af_empty),
.FULL (),
.RDCOUNT (),
.RDERR (),
.WRCOUNT (),
.WRERR (),
.DI ({app_af_cmd[0],app_af_addr}),
.DIP ({2'b00,app_af_cmd[2:1]}),
.RDCLK (clk0),
.RDEN (ctrl_af_rden),
.RST (rst_r),
.WRCLK (clk0),
.WREN (app_af_wren)
);
endmodule
|
#include <bits/stdc++.h> #define int long long #define ld long double #define vc vector #define s second #define f first //#include prettyprint.hpp using namespace std; typedef pair <int, int> pii; int n, m; int t(int a){ return a+n; } int mod=998244353; vc< vc <int> > anz, suf, pref; bool g (int a, int b){ if (a<0 || b<0) return false; if (a >n || b >=m) return false; return true; } int h (int a, int b){ if (a<0 || a>n) return 1; return 0; } int an(int a ,int b){ return g(a, b)? anz[a][b] : h(a, b); } int su(int a ,int b){ return g(a, b)? suf[a][b] : h(a, b); } int pre(int a ,int b){ return g(a, b)? pref[a][b] : h(a, b); } int plu (int & a, int b){ return a =(a+b)%mod; } int mult (int a, int b){ return a*b % mod; } int calc_inst(int i, int j){ int s1 = mult(mult(an(i, j), an(n-i+1, j-1)), su(n-i, m-j)); int s2 = mult(mult(an(i, j), an(i+1, m-j-1)), pre(i, m-j+1)); return plu(s1, s2); } int do_calc(){ anz = suf = pref = vc <vc <int> > (n+1, vc <int > (m+1)); vc <vc <int > > b (n+1, vc <int> (m)), c (n+1, vc <int> (m)); anz[0][0] = 1; for (int i=1; i<=n; i++){ anz[i][0] = anz[i-1][0]; for (int j=1; j<m; j++){ anz[i][j] = (anz[i][j-1]+anz[i-1][j])%mod; } } for (int i=1; i<=n; i++){ for (int j=1; j<m; j++){ b[i][j] = anz[i][j]*anz[n-i+1][j-1] % mod; suf[i][j] = (suf[i-1][j]+b[i][j])%mod; } } for (int i=1; i<n; i++){ for (int k=m-1; k>=2; k--){ c[i][k] = anz[n-i][k]*anz[n-i+1][m-k-1]%mod; pref[i][k]=(pref[i][k+1]+c[i][k])%mod; } } int ret = 0; for (int i=1; i<=n; i++){ for (int j=1; j<m; j++){ plu(ret, calc_inst(i, j)); } } return ret; } void do_test(){ cin >> n >> m; int res= do_calc(); //a1 = very_balanced(); // cout << res << n ; //swap(n, m); // a2 = very_balanced(); // res1=do_calc(); //assert(a1 == a2); //a1 = (n-1)*(m-1); res = 2*res%mod; // cout << res1 << res1 << << res2 << a << a1 << << a2 << << endl; cout << res << n ; //cout << a << endl; } signed main(){ ios_base::sync_with_stdio(false); do_test(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_SYMBOL_V
`define SKY130_FD_SC_HD__EDFXTP_SYMBOL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__edfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int flag[13], change[13]; bool is_leap(int y) { if (y % 100 == 0) return y % 400 == 0; else return y % 4 == 0; } int main() { memset(flag, 0, sizeof(flag)); memset(change, 0, sizeof(change)); int y; cin >> y; while (1) { bool last = is_leap(y); y++; bool now = is_leap(y); if (last && (!now)) for (int i = 1; i <= 12; i++) change[i] = (change[i] + 1 + (i <= 2)) % 7; else if ((!last) && now) for (int i = 1; i <= 12; i++) change[i] = (change[i] + 1 + (i >= 3)) % 7; else for (int i = 1; i <= 12; i++) change[i] = (change[i] + 1) % 7; bool ok = true; for (int i = 1; i <= 12; i++) if (flag[i] != change[i]) { ok = false; break; } if (ok) break; } cout << y << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); ios::sync_with_stdio(0); long long n; cin >> n; long long num = 1e5 + 3; long long pos[num]; for (int i = 0; i < n; ++i) { long long a; cin >> a; pos[a] = i + 1; } long long m; cin >> m; long long counta = 0, countb = 0; for (int j = 0; j < m; ++j) { long long b; cin >> b; counta += pos[b]; countb += n - pos[b] + 1; } cout << counta << << countb; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, ans = 0, pot; long long a, b, c, e; cin >> n; if (n <= 2) { cout << n; return 0; } for (long long i = n - 1e3; i <= n; i++) { a = i; b = i - 1; e = a * b; for (long long j = max(1LL, i - 50); j <= i - 2; j++) { c = j; pot = (e * c) / gcd(e, c); ans = max(ans, pot); } } cout << ans; return 0; }
|
#include <bits/stdc++.h> int const MAX = 1e5 + 5; using namespace std; char ans[50][50]; void place(long long s, long long e, long long c, long long cnt) { int f = 0; for (long long i = s; i < e; i += 2) { for (long long j = 0; j < 50; j += 2) { if (cnt == 0) { f = 1; break; } ans[i][j] = c; cnt--; } if (f == 1) break; } return; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long a, b, c, d; cin >> a >> b >> c >> d; a--, b--, c--, d--; for (long long i = 0; i < 10; i++) for (long long j = 0; j < 50; j++) ans[i][j] = A ; for (long long i = 10; i < 20; i++) for (long long j = 0; j < 50; j++) ans[i][j] = B ; for (long long i = 20; i < 30; i++) for (long long j = 0; j < 50; j++) ans[i][j] = C ; for (long long i = 30; i < 50; i++) for (long long j = 0; j < 50; j++) ans[i][j] = D ; cout << 50 << << 50 << endl; place(1, 10, B , b); place(11, 20, A , a); place(21, 30, D , d); place(31, 50, C , c); for (long long i = 0; i < 50; i++) { for (long long j = 0; j < 50; j++) cout << ans[i][j]; cout << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_1_V
`define SKY130_FD_SC_LP__A2BB2O_1_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_1 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_1 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 300005; int n, k, pos[N]; long long c[N], ans; vector<int> v; priority_queue<pair<long long, int> > q; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %lld , &c[i]); for (int i = 1; i <= n + k; i++) { if (i <= n) q.push(make_pair(c[i], i)); if (k < i) { int x = q.top().second; long long w = q.top().first; q.pop(); ans += w * ((long long)i - (long long)x); v.push_back(x); } } printf( %lld n , ans); for (int i = 0; i < v.size(); i++) pos[v[i]] = i + k + 1; for (int i = 1; i <= n; i++) printf( %d , pos[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; const long long mod = 1e9 + 7; const long long N = 222; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long n, k; vector<long long> adj[N]; long long dp[N][N], dp2[N][N], a[N]; void input() { cin >> n >> k; k++; for (long long i = (1); i <= (n); i++) cin >> a[i]; for (long long i = (1); i <= (n - 1); i++) { long long x, y; cin >> x >> y; ; adj[x].push_back(y); adj[y].push_back(x); } } void dfs(long long cur = 1, long long prev = 0) { for (long long i : adj[cur]) if (i != prev) dfs(i, cur); for (long long p = (k); p >= (0); p--) { if (p >= (k + 1) / 2) { long long mx = -inf; for (long long i : adj[cur]) if (i != prev) { dp2[cur][p] += dp2[i][p - 1]; mx = max(mx, dp[i][p - 1] - dp2[i][p - 1]); } dp[cur][p] = dp2[cur][p] + mx; } else { long long mx = -inf; if (!p) mx = a[cur]; for (long long i : adj[cur]) if (i != prev) { dp[cur][p] += dp2[i][(k - p) - 1]; if (p) mx = max(mx, dp[i][p - 1] - dp2[i][(k - p) - 1]); } dp[cur][p] += mx; dp2[cur][p] = max(dp[cur][p], dp2[cur][p + 1]); } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); input(); dfs(); cout << dp2[1][0]; }
|
#include <bits/stdc++.h> using namespace std; int n, m, a[105], rev[105], b[105]; long double ans = 0, cnt = 0, f[2][35][35], g[31][31]; void dfs(int u) { if (!u) { for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) if (a[i] > a[j]) ans++; cnt++; return; } for (int i = 1; i <= n; i++) { for (int j = i; j <= n; j++) { for (int k = i; k <= (i + j) / 2; k++) swap(a[k], a[j - (k - i)]); dfs(u - 1); for (int k = i; k <= (i + j) / 2; k++) swap(a[k], a[j - (k - i)]); } } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); long double kk = n * (n + 1) / 2.0; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) if (a[i] > a[j]) f[0][i][j] = 1; for (int o = 1; o <= m; o++) { int p = o & 1; memset(f[p], 0, sizeof(f[p])); for (int i = 1; i <= n; i++) { for (int j = i; j <= n; j++) { for (int k = 1; k <= n; k++) b[k] = k; for (int k = i; k <= (j + i) / 2; k++) swap(b[k], b[j - k + i]); for (int x = 1; x <= n; x++) for (int y = x + 1; y <= n; y++) if (b[x] < b[y]) f[p][b[x]][b[y]] += f[p ^ 1][x][y] / kk; else f[p][b[y]][b[x]] += (1 - f[p ^ 1][x][y]) / kk; } } } long double ans = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) ans += f[m & 1][i][j]; printf( %.10lf n , (double)ans); return 0; }
|
#include <bits/stdc++.h> #pragma warning(disable : 4786) #pragma warning(disable : 4996) using namespace std; int c[200005], d[200005]; int main() { int n; scanf( %d , &n); int val = 0; int lb, ub; lb = -1000000000; ub = 1000000000; for (int i = 1; i <= n; i++) { scanf( %d %d , &c[i], &d[i]); if (d[i] == 1) { lb = ((lb) > (1900 - val) ? (lb) : (1900 - val)); } else { ub = ((ub) < (1899 - val) ? (ub) : (1899 - val)); } val += c[i]; } if (lb > ub) { printf( Impossible n ); return 0; } val = ub; for (int i = 1; i <= n; i++) { val += c[i]; } if (val >= 100000000) printf( Infinity n ); else printf( %d n , val); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; vector<string> v(100005); long long int n, m; long long int check(string s, string str) { long long int count = 0; for (long long int i = 0; i < s.size(); i++) { if (str[i] != s[i]) count++; } return count; } bool ok(string s) { for (long long int i = 0; i < n; i++) { long long int x = check(s, v[i]); if (x > 1) return false; } return true; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t; cin >> t; while (t--) { cin >> n >> m; string ans = -1 ; for (long long int i = 0; i < n; i++) { cin >> v[i]; } for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < v[i].size(); j++) { for (char k = a ; k <= z ; k++) { string str = v[i]; str[j] = k; if (ok(str)) { ans = str; } } } } cout << ans << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_PP_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd1 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; void read(int &x) { register int c = getchar(); x = 0; for (; c < 48 || c > 57; c = getchar()) ; for (; c > 47 && c < 58; c = getchar()) x = (x << 1) + (x << 3) + c - 48; } queue<int> y[300005], v; int main() { int n, q, w = 0, x, z = 0, t = 0; read(n); read(q); while (q--) { read(x); if (x == 1) { read(x); v.push(x); y[x].push(t++); } else if (x == 2) { read(x); z += y[x].size(); while (!y[x].empty()) y[x].pop(); } else { read(x); while (x > w) { if (!y[v.front()].empty() && y[v.front()].front() < x) { y[v.front()].pop(); z++; } ++w; v.pop(); } } printf( %d n , t - z); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int c = 0, f = 0; for (int i = 0; i < n; i++) { if (s[i] == x ) c++; else if (s[i] != x && c < 3) c = 0; if (c > 2) { while (1) { f++; c--; if (c < 3) break; } } } cout << f; }
|
#include <bits/stdc++.h> namespace myland { using namespace std; namespace _abbr {} using namespace _abbr; namespace _constant { const double EPS(1e-8); const double PI(acos(-1.0)); const int INF(0x3f3f3f3f); const long long INFL(0x3f3f3f3f3f3f3f3fll); const int MOD(1e9 + 7); const int dx[] = {-1, 0, 1, 0, -1, 1, 1, -1}, dy[] = {0, 1, 0, -1, 1, 1, -1, -1}; } // namespace _constant using namespace _constant; namespace _solve {} using namespace _solve; namespace _calculate { bool odd(long long x) { return x & 1; } bool even(long long x) { return (x & 1) ^ 1; } bool posi(long long x) { return x > 0; } bool nega(long long x) { return x < 0; } bool zero(long long x) { return x == 0; } bool prime(long long x) { if (x < 2) return 0; for (int i = 2; i * i <= x; i++) if (x % i == 0) return 0; return 1; } long long droot(long long x) { return 1 + (x - 1) % 9; } long long upd(long long a, long long b) { return a % b ? a / b + 1 : a / b; }; long long random(long long a, long long b) { return a + rand() * rand() % (b - a + 1); }; long long bitn(long long x) { long long c = 0; while (x) c++, x >>= 1; return c; } template <class T> T sqr(T x) { return x * x; } long long qpow(long long a, long long n, long long mod = MOD) { long long res(1); while (n) { if (n & 1) (res *= a) %= mod; (a *= a) %= mod; n >>= 1; } return res % mod; } long long inv(long long a, long long mod = MOD) { return qpow(a, mod - 2); } template <class T> void tomin(T& a, T b) { if (b < a) a = b; } template <class T> void tomax(T& a, T b) { if (b > a) a = b; } } // namespace _calculate using namespace _calculate; namespace _simple_algo { long long sol(const string& s) { long long x = 0; for (char c : s) x = x * 10 + c - 48; return x; } string los(long long x) { string s = ; if (x == 0) return 0 ; while (x) s = char(x % 10 + 48) + s, x /= 10; return s; } bool pal(const string& s) { int l = s.size(); for (int i = 0, j = l - 1; i < j; i++, j--) if (s[i] != s[j]) return 0; return 1; } } // namespace _simple_algo using namespace _simple_algo; namespace _io { template <class T> void rd(T& x) { cin >> x; } string srd() { string s; cin >> s; return s; } long long rd() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } void rd(int& x) { x = rd(); } void rd(long long& x) { x = rd(); } template <class A, class B> void rd(pair<A, B>& p) { cin >> p.first >> p.second; } template <class A, class B> void rd(A& a, B& b) { rd(a), rd(b); } template <class A, class B, class C> void rd(A& a, B& b, C& c) { rd(a, b); rd(c); } template <class T> void wt(const T& x) { cout << x << endl; } template <class T> void wt(const T& x, char c) { cout << x << c; } template <class T> void wt(const T& x, const string& s) { cout << x << s; } template <class T> void wt(const T& x, int rnd) { cout << fixed << setprecision(rnd) << x << endl; } template <class T> void wt(const vector<T>& v) { for (T x : v) wt(x, ); wt( ); } template <class A, class B> void wt(const pair<A, B>& make_pair) { cout << make_pair.first << << make_pair.second << endl; } } // namespace _io using namespace _io; } // namespace myland using namespace myland; int n(rd()), m(rd()), r(rd()); int s[50], b[50]; int main() { for (int i = 1; i <= n; i++) rd(s[i]); for (int i = 1; i <= m; i++) rd(b[i]); sort((s + 1), (s + n + 1)); sort((b + 1), (b + m + 1)); int t = r / s[1]; if (s[1] < b[m]) { r -= t * s[1]; r += t * b[m]; } wt(r); }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e9 + 7; int main() { int n, k; cin >> n >> k; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int difference; int ans = 0; for (int i = 0; i < n - 1; i++) { if (a[i] + a[i + 1] < k) { difference = k - (a[i] + a[i + 1]); ans += difference; a[i + 1] = a[i + 1] + difference; } } cout << ans; cout << endl; ; for (int i = 0; i < n; i++) cout << a[i] << ; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_onchip_memory2 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "DE0_NANO_SOC_QSYS_onchip_memory2.hex";
output [ 31: 0] readdata;
input [ 15: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 40000,
the_altsyncram.numwords_a = 40000,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 16;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; using i64 = long long; int n, p[666][666], quad[666]; bool alive[666]; i64 x[666], y[666], px[666], py[666]; int gopos[666][666], goneg[666][666], f[666], id[666]; i64 dp[666][666][4], ans; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lld%lld , &x[i], &y[i]); } for (int i = 1; i <= n; i++) { auto getquad = [&](int px, int py) { if (px == 0 && py == 0) return 0; if (py < 0 || (py == 0 && px < 0)) return 1; return 2; }; for (int j = 1; j <= n; j++) { px[j] = x[j] - x[i]; py[j] = y[j] - y[i]; p[i][j] = j; quad[j] = getquad(px[j], py[j]); } for (int j = 1; j <= n; j++) { px[j + n] = x[i] - x[j]; py[j + n] = y[i] - y[j]; p[i][j + n] = j + n; quad[j + n] = getquad(px[j + n], py[j + n]); } sort(p[i] + 1, p[i] + 2 * n + 1, [&](int a, int b) { return quad[a] != quad[b] ? quad[a] < quad[b] : (px[a] * py[b] < px[b] * py[a]); }); for (int j = 1; j <= 2 * n; j++) if (p[i][j] > n) p[i][j] = n - p[i][j]; } for (int i = 1; i <= n; i++) { int m = 0; for (int j = 1; j <= n; j++) { if (y[j] > y[i] || (y[j] == y[i] && x[j] >= x[i])) alive[j] = 1; else alive[j] = 0; px[j] = x[j] - x[i]; py[j] = y[j] - y[i]; if (alive[j] && j != i) { f[++m] = j; } } sort(f + 1, f + m + 1, [&](int a, int b) { return px[a] * py[b] < px[b] * py[a]; }); f[0] = i; for (int i = 0; i <= m; i++) id[f[i]] = i; memset(gopos, -1, sizeof(gopos)); memset(goneg, -1, sizeof(goneg)); for (int i = 0; i <= m; i++) { int nxtpos = -1; for (int j = 4 * n; j >= 1; j--) { int aj = (j - 1) % (2 * n) + 1; int u = p[f[i]][aj]; if (u > 0 && alive[u] && nxtpos >= 0) { gopos[i][id[u]] = nxtpos; } if (u < 0 && alive[-u] && nxtpos >= 0) { goneg[i][id[-u]] = nxtpos; } if (u > 0 && alive[u] && u != f[i]) { nxtpos = id[u]; } } } memset(dp, 0, sizeof(dp)); dp[0][1][0] = 1; for (int i = 0; i <= m; i++) { int u = goneg[i][0]; for (int j = 0; j < m - 1; j++) { int v = gopos[i][u]; for (int k = 0; k <= 3; k++) { dp[i][v][k] += dp[i][u][k]; } u = v; } for (int j = i + 1; j <= m; j++) { ans += dp[i][j][3]; int nxt = goneg[j][i]; if (nxt > j) { for (int k = 0; k <= 2; k++) { dp[j][nxt][k + 1] += dp[i][j][k]; } } } } } printf( %lld n , ans); }
|
//----------------------------------------------------------------------------
// Wishbone SRAM controller
//----------------------------------------------------------------------------
module wb_sram32 #(
parameter adr_width = 19,
parameter latency = 2 // 0 .. 7
) (
input clk,
input reset,
// Wishbone interface
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
input wb_we_i,
input [31:0] wb_adr_i,
input [3:0] wb_sel_i,
input [31:0] wb_dat_i,
output reg [31:0] wb_dat_o,
// SRAM connection
output reg [adr_width-1:0] sram_adr,
inout [31:0] sram_dat,
output reg [1:0] sram_be_n, // Byte Enable
output reg sram_ce_n, // Chip Enable
output reg sram_oe_n, // Output Enable
output reg sram_we_n // Write Enable
);
//----------------------------------------------------------------------------
//
//----------------------------------------------------------------------------
// Wishbone handling
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
wire wb_wr_word = wb_stb_i & wb_cyc_i & wb_we_i & (wb_sel_i == 4'b1111) & ~wb_ack_o;
wire wb_wr_byte = wb_stb_i & wb_cyc_i & wb_we_i & (wb_sel_i != 4'b1111) & ~wb_ack_o;
// Translate wishbone address to sram address
wire [adr_width-1:0] adr = wb_adr_i[adr_width+1:2];
// Tri-State-Driver
reg [31:0] wdat;
reg wdat_oe;
assign sram_dat = wdat_oe ? wdat : 32'bz;
// Merged data for byte enables writes
wire [31:0] merged_dat = {(wb_sel_i[3] ? wb_dat_i[31:24] : sram_dat[31:24]),
(wb_sel_i[2] ? wb_dat_i[23:16] : sram_dat[23:16]),
(wb_sel_i[1] ? wb_dat_i[15: 8] : sram_dat[15: 8]),
(wb_sel_i[0] ? wb_dat_i[ 7: 0] : sram_dat[ 7: 0])};
// Latency countdown
reg [2:0] lcount;
//----------------------------------------------------------------------------
// State Machine
//----------------------------------------------------------------------------
parameter s_idle = 0;
parameter s_read = 1;
parameter s_read_modify_write = 2;
parameter s_write = 3;
reg [2:0] state;
always @(posedge clk)
begin
if (reset) begin
state <= s_idle;
lcount <= 0;
wb_ack_o <= 0;
end else begin
case (state)
s_idle: begin
wb_ack_o <= 0;
if (wb_rd) begin
sram_ce_n <= 0;
sram_oe_n <= 0;
sram_we_n <= 1;
sram_adr <= adr;
sram_be_n <= 2'b00;
wdat_oe <= 0;
lcount <= latency;
state <= s_read;
end else if (wb_wr_word) begin
sram_ce_n <= 0;
sram_oe_n <= 1;
sram_we_n <= 0;
sram_adr <= adr;
sram_be_n <= 2'b00;
wdat <= wb_dat_i;
wdat_oe <= 1;
lcount <= latency;
state <= s_write;
end else if (wb_wr_byte) begin
sram_ce_n <= 0;
sram_oe_n <= 0;
sram_we_n <= 1;
sram_adr <= adr;
sram_be_n <= 2'b00;
wdat_oe <= 0;
lcount <= latency;
state <= s_read_modify_write;
end else begin
sram_ce_n <= 1;
sram_oe_n <= 1;
sram_we_n <= 1;
wdat_oe <= 0;
end
end
s_read: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
sram_ce_n <= 1;
sram_oe_n <= 1;
sram_we_n <= 1;
wb_dat_o <= sram_dat;
wb_ack_o <= 1;
state <= s_idle;
end
end
s_read_modify_write: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
sram_ce_n <= 0;
sram_oe_n <= 1;
sram_we_n <= 0;
sram_adr <= adr;
sram_be_n <= 2'b00;
wdat <= merged_dat;
wdat_oe <= 1;
lcount <= latency;
state <= s_write;
end
end
s_write: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
sram_ce_n <= 1;
sram_oe_n <= 1;
sram_we_n <= 1;
wb_ack_o <= 1; // XXX We could acknoledge write XXX
state <= s_idle; // XXX requests 1 cycle ahead XXX
end
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:28:30 03/06/2016
// Design Name: summed
// Module Name: C:/XilinxP/Practica1/summed_test.v
// Project Name: Practica1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: summed
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
// Test para Sumador medio de 1 bit, Practica 1
module summed_test;
// Inputs
reg xi;
reg yi;
// Outputs
wire Si;
wire Co;
// Instantiate the Unit Under Test (UUT)
summed uut (
.xi(xi),
.yi(yi),
.Si(Si),
.Co(Co)
);
initial begin
$display("...");
// Initialize Inputs
xi = 0;
yi = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
xi = 0; yi = 0; //00
#50;
$display("xi = %b, yi = %b, Si = %b, Co = %b", xi, yi, Si, Co);
xi = 0; yi = 1; //01
#50;
$display("xi = %b, yi = %b, Si = %b, Co = %b", xi, yi, Si, Co);
xi = 1; yi = 0; //10
#50;
$display("xi = %b, yi = %b, Si = %b, Co = %b", xi, yi, Si, Co);
xi = 1; yi = 1; //11
#50;
$display("xi = %b, yi = %b, Si = %b, Co = %b", xi, yi, Si, Co);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, c = 0; cin >> n >> m; int a[n], i; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (i = 0; i < m; i++) if (a[i] <= 0) c = c + a[i]; cout << abs(c); }
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module MC6502ProcessorStatusRegister(
clk,
rst_x,
i_c,
i_set_c,
i_i,
i_set_i,
i_v,
i_set_v,
i_d,
i_set_d,
i_n,
i_set_n,
i_z,
i_set_z,
i_b,
i_set_b,
o_psr);
input clk;
input rst_x;
input i_c;
input i_set_c;
input i_i;
input i_set_i;
input i_v;
input i_set_v;
input i_d;
input i_set_d;
input i_n;
input i_set_n;
input i_z;
input i_set_z;
input i_b;
input i_set_b;
output [7:0] o_psr;
reg r_n;
reg r_v;
reg r_b;
reg r_d;
reg r_i;
reg r_z;
reg r_c;
assign o_psr = { r_n, r_v, 1'b1, r_b, r_d, r_i, r_z, r_c };
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_n <= 1'b0;
r_v <= 1'b0;
r_b <= 1'b0;
r_d <= 1'b0;
r_i <= 1'b0;
r_z <= 1'b0;
r_c <= 1'b0;
end else begin
if (i_set_c) begin
r_c <= i_c;
end
if (i_set_i) begin
r_i <= i_i;
end
if (i_set_v) begin
r_v <= i_v;
end
if (i_set_d) begin
r_d <= i_d;
end
if (i_set_n) begin
r_n <= i_n;
end
if (i_set_z) begin
r_z <= i_z;
end
if (i_set_b) begin
r_b <= i_b;
end
end
end
endmodule // MC6502ProcessorStatusRegister
|
#include <bits/stdc++.h> using namespace std; const int N = 105; const int oo = 1000000000; long long n, k; long long a[N], b[N], c[N]; long long module = 1000000007; void print(vector<vector<long long> > mat) { for (int j = 0; j < mat.size(); j++) { for (int k = 0; k < mat[j].size(); k++) cout << mat[j][k] << ; cout << endl; } } vector<vector<long long> > mul(vector<vector<long long> > mat1, vector<vector<long long> > mat2) { vector<vector<long long> > res; for (int i = 0; i < mat1.size(); i++) { vector<long long> row; for (int k = 0; k < mat2[0].size(); k++) { long long temp = 0; for (int j = 0; j < mat1[0].size(); j++) { temp = (temp + mat1[i][j] * mat2[j][k] % module) % module; } row.push_back(temp); } res.push_back(row); } return res; } vector<vector<long long> > pow(vector<vector<long long> > mat, long long t) { vector<vector<long long> > res; if (t == 0) { for (int i = 0; i < 16; i++) { vector<long long> row; for (int j = 0; j < 16; j++) { if (i == j) row.push_back(1); else row.push_back(0); } res.push_back(row); } return res; } res = pow(mat, t / 2); res = mul(res, res); if (t % 2 == 0) return res; else return mul(mat, res); } int main() { cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i] >> b[i] >> c[i]; vector<vector<long long> > base; vector<long long> row; row.push_back(1); base.push_back(row); for (int i = 1; i < 16; i++) { row.resize(0); row.push_back(0); base.push_back(row); } base.push_back(row); for (int i = 1; i <= n; i++) { long long dist = 0; if (i == n) dist = k - a[i]; else dist = b[i] - a[i]; vector<vector<long long> > mat; for (int j = 0; j < 16; j++) { vector<long long> row; for (int k = 0; k < 16; k++) { if (j <= c[i] && k <= c[i] && (k == j || k == j - 1 || k == j + 1)) row.push_back(1); else row.push_back(0); } mat.push_back(row); } base = mul(pow(mat, dist), base); } cout << base[0][0]; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> vector<T>& operator--(vector<T>& v) { for (auto& i : v) --i; return v; } template <typename T> vector<T>& operator++(vector<T>& v) { for (auto& i : v) ++i; return v; } template <typename T> istream& operator>>(istream& is, vector<T>& v) { for (auto& i : v) is >> i; return is; } template <typename T> ostream& operator<<(ostream& os, vector<T>& v) { for (auto& i : v) os << i << ; return os; } template <typename T, typename U> istream& operator>>(istream& is, pair<T, U>& p) { is >> p.first >> p.second; return is; } template <typename T, typename U> ostream& operator<<(ostream& os, pair<T, U>& p) { os << p.first << << p.second; return os; } template <typename T, typename U> pair<T, U> operator-(pair<T, U> a, pair<T, U> b) { return make_pair(a.first - b.first, a.second - b.second); } template <typename T, typename U> pair<T, U> operator+(pair<T, U> a, pair<T, U> b) { return make_pair(a.first + b.first, a.second + b.second); } template <typename T, typename U> void umin(T& a, U b) { if (a > b) a = b; } template <typename T, typename U> void umax(T& a, U b) { if (a < b) a = b; } int main() { int T; cin >> T; while (T--) { long long a, b, p, q; cin >> a >> b >> p >> q; long long t = min(b - a + 1, (long long)sqrt(b - a) + 5); vector<pair<long long, int>> v; auto g = [&](long long x) { return p * x * 2 % (q * 2); }; auto f = [&](long long x) { return abs(g(x) - q); }; 42; ; for (int i = 0; i < t; ++i) { v.emplace_back(g(i), i); } long long ans = a; sort(v.begin(), v.end()); 42; ; for (long long i = a; i + t <= b + 1; i += t) { long long need = (q - g(i) + q * 2) % (q * 2); int ind = (lower_bound((v).begin(), (v).end(), (make_pair(need, -1))) - (v).begin()); for (int j = ind - 3; j <= ind + 3; ++j) { int k = (j + v.size()) % v.size(); long long fn = f(i + v[k].second); if (fn < f(ans) || (fn == f(ans) && i + v[k].second < ans)) ans = i + v[k].second; } ind = (upper_bound((v).begin(), (v).end(), (make_pair(need, -1))) - (v).begin()); for (int j = ind - 3; j <= ind + 3; ++j) { int k = (j + v.size()) % v.size(); long long fn = f(i + v[k].second); if (fn < f(ans) || (fn == f(ans) && i + v[k].second < ans)) ans = i + v[k].second; } } for (long long i = b; i >= max(b - t - 5, a); --i) { long long fn = f(i); if (fn < f(ans) || (fn == f(ans) && i < ans)) ans = i; } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; cin >> n >> m; vector<long long> a(n); vector<long long> b(n); for (long long i = 0; i < n; i++) cin >> a[i]; for (long long i = 0; i < n; i++) cin >> b[i]; sort(b.begin(), b.end()); long long ans = m - 1; for (long long i = 0; i < n; i++) { long long z; if (b[i] > a[0]) z = (b[i] - a[0]) % m; else z = (m + b[i] - a[0]) % m; vector<long long> temp; temp = a; for (long long i = 0; i < n; i++) temp[i] = (temp[i] + z) % m; sort(temp.begin(), temp.end()); if (temp == b) ans = min(ans, z); } cout << ans << endl; return 0; }
|
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_ecc_top.v
//
// Description:
//
// Specifications:
//
// Structure:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_0_axi_ctrl_addr_decode #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 32,
// Number of Registers
parameter integer C_NUM_REG = 5,
parameter integer C_NUM_REG_WIDTH = 3,
// Number of Registers
parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,
parameter C_REG_RDWR_ARRAY = 5'b00101
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire [C_ADDR_WIDTH-1:0] axaddr ,
// Slave Interface Write Data Ports
output wire [C_NUM_REG_WIDTH-1:0] reg_decode_num
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
function [C_ADDR_WIDTH-1:0] calc_bit_mask (
input [C_NUM_REG*C_ADDR_WIDTH-1:0] addr_decode_array
);
begin : func_calc_bit_mask
integer i;
reg [C_ADDR_WIDTH-1:0] first_addr;
reg [C_ADDR_WIDTH-1:0] bit_mask;
calc_bit_mask = {C_ADDR_WIDTH{1'b0}};
first_addr = addr_decode_array[C_ADDR_WIDTH+:C_ADDR_WIDTH];
for (i = 2; i < C_NUM_REG; i = i + 1) begin
bit_mask = first_addr ^ addr_decode_array[C_ADDR_WIDTH*i +: C_ADDR_WIDTH];
calc_bit_mask = calc_bit_mask | bit_mask;
end
end
endfunction
function integer lsb_mask_index (
input [C_ADDR_WIDTH-1:0] mask
);
begin : my_lsb_mask_index
lsb_mask_index = 0;
while ((lsb_mask_index < C_ADDR_WIDTH-1) && ~mask[lsb_mask_index]) begin
lsb_mask_index = lsb_mask_index + 1;
end
end
endfunction
function integer msb_mask_index (
input [C_ADDR_WIDTH-1:0] mask
);
begin : my_msb_mask_index
msb_mask_index = C_ADDR_WIDTH-1;
while ((msb_mask_index > 0) && ~mask[msb_mask_index]) begin
msb_mask_index = msb_mask_index - 1;
end
end
endfunction
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_ADDR_BIT_MASK = calc_bit_mask(C_REG_ADDR_ARRAY);
localparam P_MASK_LSB = lsb_mask_index(P_ADDR_BIT_MASK);
localparam P_MASK_MSB = msb_mask_index(P_ADDR_BIT_MASK);
localparam P_MASK_WIDTH = P_MASK_MSB - P_MASK_LSB + 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
integer i;
(* rom_extract = "no" *)
reg [C_NUM_REG_WIDTH-1:0] reg_decode_num_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(*) begin
reg_decode_num_i = {C_NUM_REG_WIDTH{1'b0}};
for (i = 1; i < C_NUM_REG; i = i + 1) begin : decode_addr
if ((axaddr[P_MASK_MSB:P_MASK_LSB] == C_REG_ADDR_ARRAY[i*C_ADDR_WIDTH+P_MASK_LSB+:P_MASK_WIDTH])
&& C_REG_RDWR_ARRAY[i] ) begin
reg_decode_num_i = i[C_NUM_REG_WIDTH-1:0];
end
end
end
assign reg_decode_num = reg_decode_num_i;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; struct Seller { long long first, second, diff; } a[200005]; bool cmp(Seller p, Seller q) { return (p.diff > q.diff); } int main() { long long n, m, i, j, ans = 0; cin >> n >> m; for (i = 0; i < n; i++) cin >> a[i].first; for (i = 0; i < n; i++) cin >> a[i].second; for (i = 0; i < n; i++) { a[i].diff = (a[i].second - a[i].first); } sort(a, a + n, cmp); for (i = 0; i < m; i++) ans += a[i].first; for (i = m; i < n; i++) ans += min(a[i].first, a[i].second); cout << ans << endl; }
|
`default_nettype none
`include "processor.h"
module dispatch_general_register(
//System
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Write Port
input wire iWR_VALID,
input wire [4:0] iWR_ADDR,
input wire [31:0] iWR_DATA,
//Read Port0
input wire [4:0] iRD0_ADDR,
output wire [31:0] oRD0_DATA,
//Read Port1
input wire [4:0] iRD1_ADDR,
output wire [31:0] oRD1_DATA,
//Debug Module
output wire [31:0] oDEBUG_REG_OUT_GR0,
output wire [31:0] oDEBUG_REG_OUT_GR1,
output wire [31:0] oDEBUG_REG_OUT_GR2,
output wire [31:0] oDEBUG_REG_OUT_GR3,
output wire [31:0] oDEBUG_REG_OUT_GR4,
output wire [31:0] oDEBUG_REG_OUT_GR5,
output wire [31:0] oDEBUG_REG_OUT_GR6,
output wire [31:0] oDEBUG_REG_OUT_GR7,
output wire [31:0] oDEBUG_REG_OUT_GR8,
output wire [31:0] oDEBUG_REG_OUT_GR9,
output wire [31:0] oDEBUG_REG_OUT_GR10,
output wire [31:0] oDEBUG_REG_OUT_GR11,
output wire [31:0] oDEBUG_REG_OUT_GR12,
output wire [31:0] oDEBUG_REG_OUT_GR13,
output wire [31:0] oDEBUG_REG_OUT_GR14,
output wire [31:0] oDEBUG_REG_OUT_GR15,
output wire [31:0] oDEBUG_REG_OUT_GR16,
output wire [31:0] oDEBUG_REG_OUT_GR17,
output wire [31:0] oDEBUG_REG_OUT_GR18,
output wire [31:0] oDEBUG_REG_OUT_GR19,
output wire [31:0] oDEBUG_REG_OUT_GR20,
output wire [31:0] oDEBUG_REG_OUT_GR21,
output wire [31:0] oDEBUG_REG_OUT_GR22,
output wire [31:0] oDEBUG_REG_OUT_GR23,
output wire [31:0] oDEBUG_REG_OUT_GR24,
output wire [31:0] oDEBUG_REG_OUT_GR25,
output wire [31:0] oDEBUG_REG_OUT_GR26,
output wire [31:0] oDEBUG_REG_OUT_GR27,
output wire [31:0] oDEBUG_REG_OUT_GR28,
output wire [31:0] oDEBUG_REG_OUT_GR29,
output wire [31:0] oDEBUG_REG_OUT_GR30,
output wire [31:0] oDEBUG_REG_OUT_GR31
);
integer i;
reg [31:0] b_ram0[0:31];
reg [31:0] b_ram1[0:31];
//RAM0
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 32; i = i + 1)begin
b_ram0[i] <= 32'h0;
end
end
else if(iRESET_SYNC)begin
for(i = 0; i < 32; i = i + 1)begin
b_ram0[i] <= 32'h0;
end
end
else begin
if(iWR_VALID)begin
b_ram0[iWR_ADDR] <= iWR_DATA;
end
end
end//General Register Write Back
//RAM1
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 32; i = i + 1)begin
b_ram1[i] <= 32'h0;
end
end
else if(iRESET_SYNC)begin
for(i = 0; i < 32; i = i + 1)begin
b_ram1[i] <= 32'h0;
end
end
else begin
if(iWR_VALID)begin
b_ram1[iWR_ADDR] <= iWR_DATA;
end
end
end//General Register Write Back
assign oRD0_DATA = b_ram0[iRD0_ADDR];
assign oRD1_DATA = b_ram1[iRD1_ADDR];
//Debug Module Enable
`ifdef MIST1032ISA_STANDARD_DEBUGGER
assign oDEBUG_REG_OUT_GR0 = b_ram0[0];
assign oDEBUG_REG_OUT_GR1 = b_ram0[1];
assign oDEBUG_REG_OUT_GR2 = b_ram0[2];
assign oDEBUG_REG_OUT_GR3 = b_ram0[3];
assign oDEBUG_REG_OUT_GR4 = b_ram0[4];
assign oDEBUG_REG_OUT_GR5 = b_ram0[5];
assign oDEBUG_REG_OUT_GR6 = b_ram0[6];
assign oDEBUG_REG_OUT_GR7 = b_ram0[7];
assign oDEBUG_REG_OUT_GR8 = b_ram0[8];
assign oDEBUG_REG_OUT_GR9 = b_ram0[9];
assign oDEBUG_REG_OUT_GR10 = b_ram0[10];
assign oDEBUG_REG_OUT_GR11 = b_ram0[11];
assign oDEBUG_REG_OUT_GR12 = b_ram0[12];
assign oDEBUG_REG_OUT_GR13 = b_ram0[13];
assign oDEBUG_REG_OUT_GR14 = b_ram0[14];
assign oDEBUG_REG_OUT_GR15 = b_ram0[15];
assign oDEBUG_REG_OUT_GR16 = b_ram0[16];
assign oDEBUG_REG_OUT_GR17 = b_ram0[17];
assign oDEBUG_REG_OUT_GR18 = b_ram0[18];
assign oDEBUG_REG_OUT_GR19 = b_ram0[19];
assign oDEBUG_REG_OUT_GR20 = b_ram0[20];
assign oDEBUG_REG_OUT_GR21 = b_ram0[21];
assign oDEBUG_REG_OUT_GR22 = b_ram0[22];
assign oDEBUG_REG_OUT_GR23 = b_ram0[23];
assign oDEBUG_REG_OUT_GR24 = b_ram0[24];
assign oDEBUG_REG_OUT_GR25 = b_ram0[25];
assign oDEBUG_REG_OUT_GR26 = b_ram0[26];
assign oDEBUG_REG_OUT_GR27 = b_ram0[27];
assign oDEBUG_REG_OUT_GR28 = b_ram0[28];
assign oDEBUG_REG_OUT_GR29 = b_ram0[29];
assign oDEBUG_REG_OUT_GR30 = b_ram0[30];
assign oDEBUG_REG_OUT_GR31 = b_ram0[31];
`else
//Disable
assign oDEBUG_REG_OUT_GR0 = 32'h0;
assign oDEBUG_REG_OUT_GR1 = 32'h0;
assign oDEBUG_REG_OUT_GR2 = 32'h0;
assign oDEBUG_REG_OUT_GR3 = 32'h0;
assign oDEBUG_REG_OUT_GR4 = 32'h0;
assign oDEBUG_REG_OUT_GR5 = 32'h0;
assign oDEBUG_REG_OUT_GR6 = 32'h0;
assign oDEBUG_REG_OUT_GR7 = 32'h0;
assign oDEBUG_REG_OUT_GR8 = 32'h0;
assign oDEBUG_REG_OUT_GR9 = 32'h0;
assign oDEBUG_REG_OUT_GR10 = 32'h0;
assign oDEBUG_REG_OUT_GR11 = 32'h0;
assign oDEBUG_REG_OUT_GR12 = 32'h0;
assign oDEBUG_REG_OUT_GR13 = 32'h0;
assign oDEBUG_REG_OUT_GR14 = 32'h0;
assign oDEBUG_REG_OUT_GR15 = 32'h0;
assign oDEBUG_REG_OUT_GR16 = 32'h0;
assign oDEBUG_REG_OUT_GR17 = 32'h0;
assign oDEBUG_REG_OUT_GR18 = 32'h0;
assign oDEBUG_REG_OUT_GR19 = 32'h0;
assign oDEBUG_REG_OUT_GR20 = 32'h0;
assign oDEBUG_REG_OUT_GR21 = 32'h0;
assign oDEBUG_REG_OUT_GR22 = 32'h0;
assign oDEBUG_REG_OUT_GR23 = 32'h0;
assign oDEBUG_REG_OUT_GR24 = 32'h0;
assign oDEBUG_REG_OUT_GR25 = 32'h0;
assign oDEBUG_REG_OUT_GR26 = 32'h0;
assign oDEBUG_REG_OUT_GR27 = 32'h0;
assign oDEBUG_REG_OUT_GR28 = 32'h0;
assign oDEBUG_REG_OUT_GR29 = 32'h0;
assign oDEBUG_REG_OUT_GR30 = 32'h0;
assign oDEBUG_REG_OUT_GR31 = 32'h0;
`endif
endmodule // dispatch_general_register
`default_nettype wire
|
//#############################################################################
//# Function: Gray to binary encoder #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_gray2bin #(parameter DW = 32) // width of data inputs
(
input [DW-1:0] in, //gray encoded input
output [DW-1:0] out //binary encoded output
);
reg [DW-1:0] bin;
wire [DW-1:0] gray;
integer i,j;
assign gray[DW-1:0] = in[DW-1:0];
assign out[DW-1:0] = bin[DW-1:0];
always @*
begin
bin[DW-1] = gray[DW-1];
for (i=0; i<(DW-1); i=i+1)
begin
bin[i] = 1'b0;
for (j=i; j<DW; j=j+1)
bin[i] = bin[i] ^ gray [j];
end
end
endmodule // oh_gray2bin
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_2_V
`define SKY130_FD_SC_LP__SDFXTP_2_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_2 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_2_V
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : chip_top.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/chip.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
//File Include : system header file
`include "../sys_include.h"
`include "cpu.h"
module if_stage (
input wire clk, //
input wire reset, //
input wire [`WordDataBus] spm_rd_data, //
output wire [`WordAddrBus] spm_addr, //
output wire spm_as_n, //
output wire spm_rw, //
output wire [`WordDataBus] spm_wr_data, //
input wire [`WordDataBus] bus_rd_data, //
input wire bus_rdy_n, //
input wire bus_grant_n, //
output wire bus_req_n, //
output wire [`WordAddrBus] bus_addr, //
output wire bus_as_n, //
output wire bus_rw, //
output wire [`WordDataBus] bus_wr_data, //
input wire stall, //
input wire flush, //
input wire [`WordAddrBus] new_pc, //
input wire br_taken, //
input wire [`WordAddrBus] br_addr, //
output wire busy, //
output wire [`WordAddrBus] if_pc, //
output wire [`WordDataBus] if_insn, //
output wire if_en //
);
wire [`WordDataBus] insn; //
bus_if bus_if (
.clk (clk), //
.reset (reset), //
.stall (stall), //
.flush (flush), //
.busy (busy), //
.addr (if_pc), //
.as_n (`ENABLE_N), //
.rw (`READ), //
.wr_data (`WORD_DATA_W'h0), //
.rd_data (insn), //
.spm_rd_data (spm_rd_data), //
.spm_addr (spm_addr), //
.spm_as_n (spm_as_n), //
.spm_rw (spm_rw), //
.spm_wr_data (spm_wr_data), //
.bus_rd_data (bus_rd_data), //
.bus_rdy_n (bus_rdy_n), //
.bus_grant_n (bus_grant_n), //
.bus_req_n (bus_req_n), //
.bus_addr (bus_addr), //
.bus_as_n (bus_as_n), //
.bus_rw (bus_rw), //
.bus_wr_data (bus_wr_data) //
);
if_reg if_reg (
.clk (clk), //
.reset (reset), //
.insn (insn), //
.stall (stall), //
.flush (flush), //
.new_pc (new_pc), //
.br_taken (br_taken), //
.br_addr (br_addr), //
.if_pc (if_pc), //
.if_insn (if_insn), //
.if_en (if_en) //
);
endmodule
|
`include "mrfm.vh"
module biquad_2stage (input clock, input reset, input strobe_in,
input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data,
input wire [15:0] sample_in, output reg [15:0] sample_out, output wire [63:0] debugbus);
wire [3:0] coeff_addr, coeff_wr_addr;
wire [3:0] data_addr, data_wr_addr;
reg [3:0] cur_offset, data_addr_int, data_wr_addr_int;
wire [15:0] coeff, coeff_wr_data, data, data_wr_data;
wire coeff_wr;
reg data_wr;
wire [30:0] product;
wire [33:0] accum;
wire [15:0] scaled_accum;
wire [7:0] shift;
reg [3:0] phase;
wire enable_mult, enable_acc, latch_out, select_input;
reg done, clear_acc;
setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr));
setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out(shift),.changed());
ram16 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data),
.rd_addr(coeff_addr),.rd_data(coeff));
ram16 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data),
.rd_addr(data_addr),.rd_data(data));
mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() );
acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(),
.addend(product),.sum(accum) );
shifter shifter (.in(accum),.out(scaled_accum),.shift(shift));
assign data_wr_data = select_input ? sample_in : scaled_accum;
assign enable_mult = 1'b1;
always @(posedge clock)
if(reset)
cur_offset <= #1 4'd0;
else if(latch_out)
cur_offset <= #1 cur_offset + 4'd1;
assign data_addr = data_addr_int + cur_offset;
assign data_wr_addr = data_wr_addr_int + cur_offset;
always @(posedge clock)
if(reset)
done <= #1 1'b0;
else if(latch_out)
done <= #1 1'b1;
else if(strobe_in)
done <= #1 1'b0;
always @(posedge clock)
if(reset)
phase <= #1 4'd0;
else if(strobe_in)
phase <= #1 4'd0;
else if(!done)
phase <= #1 phase + 4'd1;
assign coeff_addr = phase;
always @(phase)
case(phase)
4'd01 : data_addr_int = 4'd00; 4'd02 : data_addr_int = 4'd01; 4'd03 : data_addr_int = 4'd02;
4'd04 : data_addr_int = 4'd03; 4'd05 : data_addr_int = 4'd04;
4'd07 : data_addr_int = 4'd03; 4'd08 : data_addr_int = 4'd04; 4'd09 : data_addr_int = 4'd05;
4'd10 : data_addr_int = 4'd06; 4'd11 : data_addr_int = 4'd07;
default : data_addr_int = 4'd00;
endcase // case(phase)
always @(phase)
case(phase)
4'd0 : data_wr_addr_int = 4'd2;
4'd8 : data_wr_addr_int = 4'd5;
4'd14 : data_wr_addr_int = 4'd8;
default : data_wr_addr_int = 4'd0;
endcase // case(phase)
always @(phase)
case(phase)
4'd0, 4'd8, 4'd14 : data_wr = 1'b1;
default : data_wr = 1'b0;
endcase // case(phase)
assign select_input = (phase == 4'd0);
always @(phase)
case(phase)
4'd0, 4'd1, 4'd2, 4'd3, 4'd9, 4'd15 : clear_acc = 1'd1;
default : clear_acc = 1'b0;
endcase // case(phase)
assign enable_acc = ~clear_acc;
assign latch_out = (phase == 4'd14);
always @(posedge clock)
if(reset)
sample_out <= #1 16'd0;
else if(latch_out)
sample_out <= #1 scaled_accum;
////////////////////////////////////////////////////////
// Debug
wire [3:0] debugmux;
setting_reg #(`FR_MRFM_DEBUG) sr_debugmux(.clock(clock),.reset(reset),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out(debugmux),.changed());
assign debugbus[15:0] = debugmux[0] ? {coeff_addr,data_addr,data_wr_addr,cur_offset} : {phase,data_addr_int,data_wr_addr_int,cur_offset};
assign debugbus[31:16] = debugmux[1] ? scaled_accum : {clock, strobe_in, data_wr, enable_mult, enable_acc, clear_acc, latch_out,select_input,done, data_addr_int};
assign debugbus[47:32] = debugmux[2] ? sample_out : coeff;
assign debugbus[63:48] = debugmux[3] ? sample_in : data;
endmodule // biquad_2stage
|
module router(clock,
ID,
// input links
in_data_n, in_data_s, in_data_e, in_data_w,
in_srcdst_n, in_srcdst_s, in_srcdst_e, in_srcdst_w,
in_active_n, in_active_s, in_active_e, in_active_w,
in_hops_n, in_hops_s, in_hops_e, in_hops_w,
// output links
out_data_n, out_data_s, out_data_e, out_data_w,
out_srcdst_n, out_srcdst_s, out_srcdst_e, out_srcdst_w,
out_active_n, out_active_s, out_active_e, out_active_w,
out_hops_n, out_hops_s, out_hops_e, out_hops_w,
// injection port
in_data_inj, in_srcdst_inj, in_active_inj,
in_accepted_inj,
// ejection port
out_data_ej, out_srcdst_ej, out_active_ej);
`include "config.vh"
input clock;
input [ADDRBITS2-1:0] ID;
input [LINKWIDTH-1:0] in_data_n, in_data_s, in_data_e, in_data_w;
input [ADDRBITS2-1:0] in_srcdst_n, in_srcdst_s, in_srcdst_e, in_srcdst_w;
input in_active_n, in_active_s, in_active_e, in_active_w;
input [HOPBITS-1:0] in_hops_n, in_hops_s, in_hops_e, in_hops_w;
output reg [LINKWIDTH-1:0] out_data_n, out_data_s, out_data_e, out_data_w;
output reg [ADDRBITS2-1:0] out_srcdst_n, out_srcdst_s, out_srcdst_e, out_srcdst_w;
output reg out_active_n, out_active_s, out_active_e, out_active_w;
output reg [HOPBITS-1:0] out_hops_n, out_hops_s, out_hops_e, out_hops_w;
input [LINKWIDTH-1:0] in_data_inj;
input [ADDRBITS2-1:0] in_srcdst_inj;
input in_active_inj;
output in_accepted_inj;
output reg [LINKWIDTH-1:0] out_data_ej;
output reg [ADDRBITS2-1:0] out_srcdst_ej;
output reg out_active_ej;
// --------------------------------------------------------------------
// route computation
wire [4:0] desired_n, desired_s, desired_e, desired_w, desired_i;
wire [HOPBITS-1:0] hop_n, hop_s, hop_e, hop_w, hop_i;
RC rc_n(.ID(ID), .active(in_active_n), .srcdst(in_srcdst_n), .desired(desired_n));
RC rc_s(.ID(ID), .active(in_active_s), .srcdst(in_srcdst_s), .desired(desired_s));
RC rc_e(.ID(ID), .active(in_active_e), .srcdst(in_srcdst_e), .desired(desired_e));
RC rc_w(.ID(ID), .active(in_active_w), .srcdst(in_srcdst_w), .desired(desired_w));
RC rc_i(.ID(ID), .active(in_active_inj), .srcdst(in_srcdst_inj), .desired(desired_i));
INC inc_n(.in(in_hops_n), .out(hop_n));
INC inc_s(.in(in_hops_s), .out(hop_s));
INC inc_e(.in(in_hops_e), .out(hop_e));
INC inc_w(.in(in_hops_w), .out(hop_w));
assign in_hops_i = 0;
// pipeline registers
reg [4:0] desired_n_reg, desired_s_reg, desired_e_reg, desired_w_reg, desired_i_reg;
reg [ADDRBITS2-1:0] srcdst_n_reg, srcdst_s_reg, srcdst_e_reg, srcdst_w_reg, srcdst_i_reg;
reg [HOPBITS-1:0] hop_n_reg, hop_s_reg, hop_e_reg, hop_w_reg;
always @(posedge clock) begin
desired_n_reg <= desired_n;
desired_s_reg <= desired_s;
desired_e_reg <= desired_e;
desired_w_reg <= desired_w;
desired_i_reg <= desired_i;
srcdst_n_reg <= in_srcdst_n;
srcdst_s_reg <= in_srcdst_s;
srcdst_e_reg <= in_srcdst_e;
srcdst_w_reg <= in_srcdst_w;
srcdst_i_reg <= in_srcdst_inj;
hop_n_reg <= hop_n;
hop_s_reg <= hop_s;
hop_e_reg <= hop_e;
hop_w_reg <= hop_w;
end
// --------------------------------------------------------------------
// arbitration
wire [4:0] ctln, ctls, ctle, ctlw, ctli;
wire [HOPBITS-1:0] _out_hops_n, _out_hops_s, _out_hops_e, _out_hops_w;
wire [ADDRBITS2-1:0] _out_srcdst_n, _out_srcdst_s, _out_srcdst_e, _out_srcdst_w;
ARB arb(.n(desired_n_reg), .s(desired_s_reg), .e(desired_e_reg), .w(desired_w_reg), .i(desired_i_reg),
.nh(hop_n_reg), .sh(hop_s_reg), .eh(hop_e_reg), .wh(hop_w_reg), .ih(0),
.ctln(ctln), .ctls(ctls), .ctle(ctle), .ctlw(ctlw), .ctli(ctli));
// early forwarding of srcdst/hops
XB_RT xbrt(.ctln(ctln), .ctls(ctls), .ctle(ctle), .ctlw(ctlw), .ctli(ctli),
.srcdst_n(srcdst_n_reg), .srcdst_s(srcdst_s_reg), .srcdst_e(srcdst_e_reg), .srcdst_w(srcdst_w_reg), .srcdst_i(srcdst_i_reg),
.hop_n(hop_n_reg), .hop_s(hop_s_reg), .hop_e(hop_e_reg), .hop_w(hop_w_reg), .hop_i(0),
.out_srcdst_n(_out_srcdst_n), .out_srcdst_s(_out_srcdst_s), .out_srcdst_e(_out_srcdst_e), .out_srcdst_w(_out_srcdst_w),
.out_hop_n(_out_hops_n), .out_hop_s(_out_hops_s), .out_hop_e(_out_hops_e), .out_hop_w(_out_hops_w));
// pipeline registers
reg [4:0] ctln_reg, ctls_reg, ctle_reg, ctlw_reg, ctli_reg;
reg [LINKWIDTH-1:0] data_n_reg, data_s_reg, data_e_reg, data_w_reg, data_i_reg;
always @(posedge clock) begin
out_srcdst_n <= _out_srcdst_n;
out_srcdst_s <= _out_srcdst_s;
out_srcdst_e <= _out_srcdst_e;
out_srcdst_w <= _out_srcdst_w;
out_hops_n <= _out_hops_n;
out_hops_s <= _out_hops_s;
out_hops_e <= _out_hops_e;
out_hops_w <= _out_hops_w;
ctln_reg <= ctln;
ctls_reg <= ctls;
ctle_reg <= ctle;
ctlw_reg <= ctlw;
ctli_reg <= ctli;
data_n_reg <= in_data_n;
data_s_reg <= in_data_s;
data_e_reg <= in_data_e;
data_w_reg <= in_data_w;
data_i_reg <= in_data_inj;
end
// -------------------------------------------------------------------
// crossbar traversal
wire [LINKWIDTH-1:0] _out_data_n, _out_data_s, _out_data_e, _out_data_w, _out_data_ej;
XB xb(.ctln(ctln_reg), .ctls(ctls_reg), .ctle(ctle_reg), .ctlw(ctlw_reg), .ctli(ctli_reg),
.data_n(data_n_reg), .data_s(data_s_reg), .data_e(data_e_reg), .data_w(data_w_reg), .data_i(data_i_reg),
.out_data_n(_out_data_n), .out_data_s(_out_data_s), .out_data_e(_out_data_e), .out_data_w(_out_data_w), .out_data_i(_out_data_ej));
// pipeline regs
always @(posedge clock) begin
out_data_n <= _out_data_n;
out_data_s <= _out_data_s;
out_data_e <= _out_data_e;
out_data_w <= _out_data_w;
out_data_ej <= _out_data_ej;
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module generates the clocks needed for the I/O devices on *
* Altera's DE-series boards. *
* *
******************************************************************************/
module niosII_system_up_clocks_1 (
// Inputs
CLOCK_50,
reset,
// Bidirectional
// Outputs
SDRAM_CLK,
VGA_CLK,
sys_clk,
sys_reset_n
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
// Bidirectionals
// Outputs
output SDRAM_CLK;
output VGA_CLK;
output sys_clk;
output sys_reset_n;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam SYS_CLK_MULT = 1;
localparam SYS_CLK_DIV = 1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 2: 0] sys_mem_clks;
wire clk_locked;
wire video_in_clk;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign sys_reset_n = clk_locked;
assign sys_clk = sys_mem_clks[0];
assign SDRAM_CLK = sys_mem_clks[1];
assign VGA_CLK = sys_mem_clks[2];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altpll DE_Clock_Generator_System (
// Inputs
.inclk ({1'b0, CLOCK_50}),
// Outputs
.clk (sys_mem_clks),
.locked (clk_locked),
// Unused
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ()
);
defparam
DE_Clock_Generator_System.clk0_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk0_duty_cycle = 50,
DE_Clock_Generator_System.clk0_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk0_phase_shift = "0",
DE_Clock_Generator_System.clk1_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk1_duty_cycle = 50,
DE_Clock_Generator_System.clk1_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk1_phase_shift = "-3000",
DE_Clock_Generator_System.clk2_divide_by = 2,
DE_Clock_Generator_System.clk2_duty_cycle = 50,
DE_Clock_Generator_System.clk2_multiply_by = 1,
DE_Clock_Generator_System.clk2_phase_shift = "20000",
DE_Clock_Generator_System.compensate_clock = "CLK0",
DE_Clock_Generator_System.gate_lock_signal = "NO",
DE_Clock_Generator_System.inclk0_input_frequency = 20000,
DE_Clock_Generator_System.intended_device_family = "Cyclone II",
DE_Clock_Generator_System.invalid_lock_multiplier = 5,
DE_Clock_Generator_System.lpm_type = "altpll",
DE_Clock_Generator_System.operation_mode = "NORMAL",
DE_Clock_Generator_System.pll_type = "FAST",
DE_Clock_Generator_System.port_activeclock = "PORT_UNUSED",
DE_Clock_Generator_System.port_areset = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkloss = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkswitch = "PORT_UNUSED",
DE_Clock_Generator_System.port_fbin = "PORT_UNUSED",
DE_Clock_Generator_System.port_inclk0 = "PORT_USED",
DE_Clock_Generator_System.port_inclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_locked = "PORT_USED",
DE_Clock_Generator_System.port_pfdena = "PORT_UNUSED",
DE_Clock_Generator_System.port_pllena = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanaclr = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanclk = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandata = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandataout = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandone = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanread = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanwrite = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk0 = "PORT_USED",
DE_Clock_Generator_System.port_clk1 = "PORT_USED",
DE_Clock_Generator_System.port_clk2 = "PORT_USED",
DE_Clock_Generator_System.port_clk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout1 = "PORT_UNUSED",
DE_Clock_Generator_System.valid_lock_multiplier = 1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S18KAPWR_SYMBOL_V
`define SKY130_FD_SC_LP__DLYBUF4S18KAPWR_SYMBOL_V
/**
* dlybuf4s18kapwr: Delay Buffer 4-stage 0.18um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s18kapwr (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S18KAPWR_SYMBOL_V
|
`include "v2k_typedef_yee_inc.v"
module v2k_typedef_yee
(/*AUTOARG*/
// Outputs
sub2_out_pixel, ready, sub1_to_sub2_and_top,
// Inputs
sub1_in_pixel, reset, pixel_ff, cp
);
//-----------------------
// Output definitions
//
output logic_t sub1_to_sub2_and_top; // Explicit output port
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output logic_t ready; // From itest_sub2 of v2k_typedef_yee_sub2.v
output pixel24_t sub2_out_pixel; // From itest_sub2 of v2k_typedef_yee_sub2.v
// End of automatics
//-----------------------
// Input definitions
//
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input logic_t cp; // To itest_sub1 of v2k_typedef_yee_sub1.v, ...
input pixel24_t pixel_ff; // To itest_sub2 of v2k_typedef_yee_sub2.v
input logic_t reset; // To itest_sub1 of v2k_typedef_yee_sub1.v, ...
input pixel24_t sub1_in_pixel; // To itest_sub1 of v2k_typedef_yee_sub1.v
// End of automatics
//-----------------------
// Wire definitions
//
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
pixel24_t sub1_out_pixel; // From itest_sub1 of v2k_typedef_yee_sub1.v
logic_t sub1_to_sub2; // From itest_sub1 of v2k_typedef_yee_sub1.v
// End of automatics
//-----------------------
// Module instantiations
//
v2k_typedef_yee_sub1 itest_sub1
(/*AUTOINST*/
// Outputs
.sub1_out_pixel (sub1_out_pixel),
.sub1_to_sub2 (sub1_to_sub2),
.sub1_to_sub2_and_top (sub1_to_sub2_and_top),
// Inputs
.sub1_in_pixel (sub1_in_pixel),
.cp (cp),
.reset (reset));
/*v2k_typedef_yee_sub2 AUTO_TEMPLATE (
.sub2_in_pixel (sub1_out_pixel),
)
*/
v2k_typedef_yee_sub2 itest_sub2
(/*AUTOINST*/
// Outputs
.sub2_out_pixel (sub2_out_pixel),
.ready (ready),
// Inputs
.sub2_in_pixel (sub1_out_pixel), // Templated
.cp (cp),
.reset (reset),
.sub1_to_sub2 (sub1_to_sub2),
.sub1_to_sub2_and_top (sub1_to_sub2_and_top),
.pixel_ff (pixel_ff));
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BO_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__A21BO_BEHAVIORAL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BO_BEHAVIORAL_V
|
#include <bits/stdc++.h> std::mt19937 rng( (int)std::chrono::steady_clock::now().time_since_epoch().count()); const int MOD = 1e9 + 7; const int ms = 220; int c = 1; int to[ms][20]; int fail[ms]; int cost[ms]; int addString(const std::vector<int> &str) { int on = 0; for (auto ch : str) { if (to[on][ch] == 0) { to[on][ch] = c++; } on = to[on][ch]; } return on; } void buildAho() { std::queue<int> que; que.push(0); while (!que.empty()) { int on = que.front(); que.pop(); cost[on] += cost[fail[on]]; for (int i = 0; i < 20; i++) { if (to[on][i]) { fail[to[on][i]] = on == 0 ? 0 : to[fail[on]][i]; que.push(to[on][i]); } else { to[on][i] = to[fail[on]][i]; } } } } int l[ms], r[ms]; int dp[ms][ms][505]; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); int n, m, k; std::cin >> n >> m >> k; { int len; std::cin >> len; while (len > 0) { std::cin >> l[ms - len]; len--; } l[ms - 1]--; for (int i = ms - 1; l[i] < 0; i--) { l[i] += m; l[i - 1]--; } } { int len; std::cin >> len; while (len > 0) { std::cin >> r[ms - len]; len--; } } while (n--) { int len; std::cin >> len; std::vector<int> str(len); for (auto &v : str) std::cin >> v; int v; std::cin >> v; cost[addString(str)] += v; } buildAho(); { for (int i = 0; i < c; i++) { for (int j = 0; j <= k; j++) { dp[0][i][j] = 1; } } for (int i = 1; i < ms; i++) { for (int j = 0; j < c; j++) { for (int val = 0; val <= k; val++) { for (int ch = 0; ch < m; ch++) { int newState = to[j][ch]; int newCost = val - cost[newState]; if (newCost >= 0) { dp[i][j][val] = (dp[i][j][val] + dp[i - 1][newState][newCost]) % MOD; } } } } } } int ans = 0; { bool wtf = false; int st = 0; int sum = k; for (int on = 0; on < ms; on++) { if (!wtf && r[on] == 0) { continue; } for (int i = (wtf ? 0 : 1); i < r[on]; i++) { int newState = to[st][i]; int newCost = sum - cost[newState]; if (newCost >= 0) { ans = (ans + dp[ms - on - 1][newState][newCost]) % MOD; } } st = to[st][r[on]]; sum -= cost[st]; if (wtf) { for (int i = 1; i < m; i++) { int newState = to[0][i]; int newCost = k - cost[newState]; if (newCost >= 0) { ans = (ans + dp[ms - on - 1][newState][newCost]) % MOD; } } } wtf = true; } if (sum >= 0) { ans = (ans + 1) % MOD; } } { bool wtf = false; int st = 0; int sum = k; for (int on = 0; on < ms; on++) { if (!wtf && l[on] == 0) { continue; } for (int i = (wtf ? 0 : 1); i < l[on]; i++) { int newState = to[st][i]; int newCost = sum - cost[newState]; if (newCost >= 0) { ans = (ans - dp[ms - on - 1][newState][newCost]) % MOD; } } st = to[st][l[on]]; sum -= cost[st]; if (wtf) { for (int i = 1; i < m; i++) { int newState = to[0][i]; int newCost = k - cost[newState]; if (newCost >= 0) { ans = (ans - dp[ms - on - 1][newState][newCost]) % MOD; } } } wtf = true; } if (wtf && sum >= 0) { ans = (ans - 1 + MOD) % MOD; } } ans = (ans % MOD + MOD) % MOD; std::cout << ans << std::endl; }
|
#include <bits/stdc++.h> using namespace std; template <class T1> void deb(T1 e) { cout << e << endl; } template <class T1, class T2> void deb(T1 e1, T2 e2) { cout << e1 << << e2 << endl; } template <class T1, class T2, class T3> void deb(T1 e1, T2 e2, T3 e3) { cout << e1 << << e2 << << e3 << endl; } template <class T1, class T2, class T3, class T4> void deb(T1 e1, T2 e2, T3 e3, T4 e4) { cout << e1 << << e2 << << e3 << << e4 << endl; } template <class T1, class T2, class T3, class T4, class T5> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5) { cout << e1 << << e2 << << e3 << << e4 << << e5 << endl; } template <class T1, class T2, class T3, class T4, class T5, class T6> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5, T6 e6) { cout << e1 << << e2 << << e3 << << e4 << << e5 << << e6 << endl; } string st; long long cum1[500010], cum2[500010], cum3[500010], cumhelp3[500010]; bool okay(char ch) { return ch == A || ch == E || ch == I || ch == O || ch == U || ch == Y ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; int mini, i, j, n, baki1, baki2; cin >> st; for (i = 0; i < st.size(); i++) { if (!okay(st[i])) continue; baki1 = i; baki2 = st.size() - i - 1; mini = min(baki1, baki2); mini++; cum1[1]++; cum1[mini + 1]--; if (baki1 > baki2) swap(baki1, baki2); if (baki2 > baki1) { cum2[baki1 + 2] += mini; cum2[baki2 + 2] -= mini; } mini--; cumhelp3[st.size() - mini + 2]--; cum3[st.size() - mini + 1] += mini; } double ans = 0; for (i = 1; i <= st.size(); i++) { cum1[i] += cum1[i - 1]; cum2[i] += cum2[i - 1]; cumhelp3[i] += cumhelp3[i - 1]; cum3[i] += cum3[i - 1] + cumhelp3[i]; } for (i = 1; i <= st.size(); i++) { cum1[i] *= (long long)i; ans += (double)(cum1[i] + cum2[i] + cum3[i]) / (double)i; } cout << fixed << setprecision(12) << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_TB_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_TB_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_clkbufkapwr.v"
module top();
// Inputs are registered
reg A;
reg KAPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 KAPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 KAPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 KAPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 KAPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_clkbufkapwr dut (.A(A), .KAPWR(KAPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_TB_V
|
#include <bits/stdc++.h> using namespace std; int p[5005], c[5005]; int day[5005]; bool out[5005], vi[5005]; int last = 0; int match[5005]; vector<int> DSK[5005]; bool DFS(int u) { if (vi[u] == true) return false; vi[u] = true; for (int i = 0; i < DSK[u].size(); i++) { int w = DSK[u][i]; if (match[w] == -1 || DFS(match[w])) { match[w] = u; return true; } } return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) cin >> p[i]; for (int i = 1; i <= n; i++) cin >> c[i]; int d; cin >> d; for (int i = 1; i <= d; i++) { cin >> day[i]; out[day[i]] = true; } for (int i = 1; i <= n; i++) if (!out[i]) DSK[p[i]].push_back(c[i]); fill(match + 1, match + 1 + m, -1); for (int i = d; i >= 1; i--) { memset(vi, false, sizeof vi); while (DFS(last)) { last++; memset(vi, false, sizeof vi); } DSK[p[day[i]]].push_back(c[day[i]]); day[i] = last; } for (int i = 1; i <= d; i++) cout << day[i] << n ; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.72)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Regional Clock Buffer
// /___/ /\ Filename : BUFR.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:06 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 04/04/2005 - Add SIM_DEVICE paramter to support Virtex5. CE pin has 4 clock
// latency for Virtex 4 and none for Virtex5
// 07/25/05 - Updated names to Virtex5
// 08/31/05 - Add ce_en to sensitivity list of i_in which make ce asynch.
// 05/23/06 - Add count =0 and first_rise=1 when CE = 0 (CR232206).
// 07/19/06 - Add wire declaration for undeclared wire signals.
// 04/01/09 - CR 517236 -- Added VIRTEX6 support
// 11/13/09 - Added VIRTEX7
// 01/20/10 - Change VIRTEX7 to internal_name (CR545223)
// 02/23/10 - Use assign for o_out (CR543271)
// 06/09/10 - Change internal_name to 7_SERIES
// 08/18/10 - Change 7_SERIES to 7SERIES (CR571653)
// 08/09/11 - Add 7SERIES to ce_en logic (CR620544)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/15/12 - Match with hardware (CR 650440)
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFR (O, CE, CLR, I);
output O;
input CE;
input CLR;
input I;
parameter BUFR_DIVIDE = "BYPASS";
parameter SIM_DEVICE = "7SERIES";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
integer count, period_toggle, half_period_toggle;
reg first_rise, half_period_done;
reg notifier;
reg o_out_divide = 0;
wire o_out;
reg ce_enable1, ce_enable2, ce_enable3, ce_enable4;
tri0 GSR = glbl.GSR;
wire i_in, ce_in, clr_in, gsr_in, ce_en, i_ce;
buf buf_i (i_in, I);
buf buf_ce (ce_in, CE);
buf buf_clr (clr_in, CLR);
buf buf_gsr (gsr_in, GSR);
buf buf_o (O, o_out);
initial begin
case (BUFR_DIVIDE)
"BYPASS" : period_toggle = 0;
"1" : begin
period_toggle = 1;
half_period_toggle = 1;
end
"2" : begin
period_toggle = 2;
half_period_toggle = 2;
end
"3" : begin
period_toggle = 4;
half_period_toggle = 2;
end
"4" : begin
period_toggle = 4;
half_period_toggle = 4;
end
"5" : begin
period_toggle = 6;
half_period_toggle = 4;
end
"6" : begin
period_toggle = 6;
half_period_toggle = 6;
end
"7" : begin
period_toggle = 8;
half_period_toggle = 6;
end
"8" : begin
period_toggle = 8;
half_period_toggle = 8;
end
default : begin
$display("Attribute Syntax Error : The attribute BUFR_DIVIDE on BUFR instance %m is set to %s. Legal values for this attribute are BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8.", BUFR_DIVIDE);
#1 $finish;
end
endcase // case(BUFR_DIVIDE)
case (SIM_DEVICE)
"VIRTEX4" : ;
"VIRTEX5" : ;
"VIRTEX6" : ;
"7SERIES" : ;
default : begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on BUFR instance %m is set to %s. Legal values for this attribute are VIRTEX4 or VIRTEX5 or VIRTEX6 or 7SERIES.", SIM_DEVICE);
#1 $finish;
end
endcase
end // initial begin
always @(gsr_in or clr_in)
if (gsr_in == 1'b1 || clr_in == 1'b1) begin
assign o_out_divide = 1'b0;
assign count = 0;
assign first_rise = 1'b1;
assign half_period_done = 1'b0;
if (gsr_in == 1'b1) begin
assign ce_enable1 = 1'b0;
assign ce_enable2 = 1'b0;
assign ce_enable3 = 1'b0;
assign ce_enable4 = 1'b0;
end
end
else if (gsr_in == 1'b0 || clr_in == 1'b0) begin
deassign o_out_divide;
deassign count;
deassign first_rise;
deassign half_period_done;
if (gsr_in == 1'b0) begin
deassign ce_enable1;
deassign ce_enable2;
deassign ce_enable3;
deassign ce_enable4;
end
end
always @(negedge i_in)
begin
ce_enable1 <= ce_in;
ce_enable2 <= ce_enable1;
ce_enable3 <= ce_enable2;
ce_enable4 <= ce_enable3;
end
assign ce_en = ((SIM_DEVICE == "VIRTEX5") || (SIM_DEVICE == "VIRTEX6") || (SIM_DEVICE == "7SERIES")) ? ce_in : ce_enable4;
assign i_ce = i_in & ce_en;
generate
case (SIM_DEVICE)
"VIRTEX4" : begin
always @(i_in or ce_en)
if (ce_en == 1'b1) begin
if (i_in == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0)
count = count + 1;
end // if (ce_in == 1'b1)
else begin
count = 0;
first_rise = 1;
end
end
"VIRTEX5","VIRTEX6","7SERIES" : begin
always @(i_ce)
begin
if (i_ce == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0) begin
count = count + 1;
end // if (ce_in == 1'b1)
end
end
endcase
endgenerate
assign o_out = (period_toggle == 0) ? i_in : o_out_divide;
//*** Timing Checks Start here
always @(notifier) begin
o_out_divide <= 1'bx;
end
`ifdef XIL_TIMING
specify
(CLR => O) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$width (posedge CLR, 0:0:0, 0, notifier);
$width (posedge I, 0:0:0, 0, notifier);
$width (negedge I, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // BUFR
`endcelldefine
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,abm,mmx,tune=native ) using namespace std; const int64_t INF = (int64_t)(2e18); const int maxn = 500 * 1000 + 100; chrono::time_point<chrono::steady_clock> cl; double current_time() { return (double)(chrono::steady_clock::now() - cl).count() / 1e9; } void no() { cout << 0 ; exit(0); } void inf() { cout << inf ; exit(0); } void ans(long long a) { cout << a; exit(0); } int32_t main() { cl = chrono::steady_clock::now(); ios_base::sync_with_stdio(false); cout << fixed << setprecision(10); cin.tie(nullptr); long long x, y, z; cin >> x >> y >> z; if (x == y && y != z) no(); if (x != y && y == z) ans(1); if (x == z && y != z) no(); if (x == y && y == z) { if (x == 1) inf(); if (x != 1) ans(2); } if (x > y) no(); if (y > z) no(); bool flag = false; if (x == 1ll) { flag = true; long long zz = z; while (z > 1) { if (z % y != 0) flag = false; z /= y; } z = zz; } vector<int> a; long long zcp = z; while (zcp > 0) { a.push_back(zcp % y); zcp /= y; } long long cur = 0; long long curx = 1; for (auto& it : a) { cur += it * curx; curx *= x; } int res = 0; if (cur == y) ++res; if (flag) ++res; cout << bool(res); return 0; }
|
#include <bits/stdc++.h> using namespace std; map<string, string> m; int main() { int n; string j, x; cin >> n; while (n--) { cin >> j >> x; if (m.count(j) == 0) m[x] = j; else { m[x] = m[j]; m.erase(j); } } cout << m.size() << endl; map<string, string>::iterator it; for (it = m.begin(); it != m.end(); it++) { cout << it->second << << it->first << endl; } return 0; }
|
//-----------------------------------------------------------------------------
// Pretend to be an ISO 14443 tag. We will do this by alternately short-
// circuiting and open-circuiting the antenna coil, with the tri-state
// pins.
//
// We communicate over the SSP, as a bitstream (i.e., might as well be
// unframed, though we still generate the word sync signal). The output
// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
// -> ARM) is us using the A/D as a fancy comparator; this is with
// (software-added) hysteresis, to undo the high-pass filter.
//
// At this point only Type A is implemented. This means that we are using a
// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
//
// Jonathan Westhues, October 2006
//-----------------------------------------------------------------------------
module hi_simulate(
ck_1356meg,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
dbg,
mod_type
);
input ck_1356meg;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
output dbg;
input [2:0] mod_type;
// The comparator with hysteresis on the output from the peak detector.
reg after_hysteresis;
assign adc_clk = ck_1356meg;
always @(negedge adc_clk)
begin
if(& adc_d[7:5]) after_hysteresis = 1'b1; // if (adc_d >= 224)
else if(~(| adc_d[7:5])) after_hysteresis = 1'b0; // if (adc_d <= 31)
end
// Divide 13.56 MHz to produce various frequencies for SSP_CLK
// and modulation.
reg [7:0] ssp_clk_divider;
always @(posedge adc_clk)
ssp_clk_divider <= (ssp_clk_divider + 1);
reg ssp_clk;
always @(negedge adc_clk)
begin
if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
// Get bit every at 53KHz (every 8th carrier bit of 424kHz)
ssp_clk <= ssp_clk_divider[7];
else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
// Get next bit at 212kHz
ssp_clk <= ssp_clk_divider[5];
else
// Get next bit at 424Khz
ssp_clk <= ssp_clk_divider[4];
end
// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
// this is arbitrary, because it's just a bitstream.
// One nasty issue, though: I can't make it work with both rx and tx at
// once. The phase wrt ssp_clk must be changed. TODO to find out why
// that is and make a better fix.
reg [2:0] ssp_frame_divider_to_arm;
always @(posedge ssp_clk)
ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
reg [2:0] ssp_frame_divider_from_arm;
always @(negedge ssp_clk)
ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
reg ssp_frame;
always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
if(mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION) // not modulating, so listening, to ARM
ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
else
ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
// Synchronize up the after-hysteresis signal, to produce DIN.
reg ssp_din;
always @(posedge ssp_clk)
ssp_din = after_hysteresis;
// Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.
reg modulating_carrier;
always @(*)
if (mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION)
modulating_carrier <= 1'b0; // no modulation
else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_BPSK)
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
else
modulating_carrier <= 1'b0; // yet unused
// Load modulation. Toggle only one of these, since we are already producing much deeper
// modulation than a real tag would.
assign pwr_hi = 1'b0; // HF antenna connected to GND
assign pwr_oe3 = 1'b0; // 10k Load
assign pwr_oe1 = modulating_carrier; // 33 Ohms Load
assign pwr_oe4 = modulating_carrier; // 33 Ohms Load
// This is all LF and doesn't matter
assign pwr_lo = 1'b0;
assign pwr_oe2 = 1'b0;
assign dbg = ssp_din;
endmodule
|
module konamiacceptor (
clk,
reset_,
up_,
down_,
left_,
right_,
segment_,
digit_enable_
);
input clk;
input reset_;
input up_;
input down_;
input left_;
input right_;
output [6:0] segment_;
output [3:0] digit_enable_;
// Konami code acceptor states
parameter START = 4'd0; // Initial state; waiting for first input
parameter UP_1 = 4'd1; // User pressed (and released) d-pad up
parameter UP_2 = 4'd2;
parameter DOWN_1 = 4'd3;
parameter DOWN_2 = 4'd4;
parameter LEFT_1 = 4'd5;
parameter RIGHT_1 = 4'd6;
parameter LEFT_2 = 4'd7;
parameter ACCEPT = 4'd9; // Input sequence accepted; user gets 40 lives
parameter REJECT = 4'd10; // Input sequence rejected; user gets 3 lives
reg [3:0] state; // FSM state value (one of the above values)
reg [24:0] timeout_ctr; // If no input for a while, then we REJECT
reg [1:0] down_shift; // Down key shift register to capture key-press events
reg [1:0] up_shift;
reg [1:0] left_shift;
reg [1:0] right_shift;
wire down_debounced; // Debounced d-pad down
wire up_debounced; // Debounced d-pad up
wire left_debounced; // Debounced d-pad left
wire right_debounced; // Debounced d-pad right
wire [6:0] digit_0; // 7-segment digit values
wire [6:0] digit_1;
wire [6:0] digit_2;
wire [6:0] digit_3;
assign timeout = &timeout_ctr; // Same as timeout_ctr == 8'hff_ffff
// Key-up event when key was down (1) now is up (0)
assign down_released = down_shift == 2'b10;
assign up_released = up_shift == 2'b10;
assign left_released = left_shift == 2'b10;
assign right_released = right_shift == 2'b10;
// Debouncers for d-pad inputs (prevents microscopic changes to key values
// from causing errors--see notes)
debouncer down_debouncer(
.clk(clk),
.reset_(reset_),
.raw(~down_),
.debounced(down_debounced)
);
debouncer up_debouncer(
.clk(clk),
.reset_(reset_),
.raw(~up_),
.debounced(up_debounced)
);
debouncer left_debouncer(
.clk(clk),
.reset_(reset_),
.raw(~left_),
.debounced(left_debounced)
);
debouncer right_debouncer(
.clk(clk),
.reset_(reset_),
.raw(~right_),
.debounced(right_debounced)
);
// Digit coder converts state to a 7-segment displayed value
konamicoder coder (
.digit_0(digit_3),
.digit_1(digit_2),
.digit_2(digit_1),
.digit_3(digit_0),
.state(state)
);
// Drives the seven segment display with digit values (see notes)
displaydriver display (
.clk(clk),
.reset_(reset_),
.digit_0(digit_0),
.digit_1(digit_1),
.digit_2(digit_2),
.digit_3(digit_3),
.segment_(segment_),
.digit_enable_(digit_enable_)
);
// Timeout counter generation; REJECT on timout
always@ (posedge clk or negedge reset_)
if (!reset_)
timeout_ctr <= 25'd0;
else if (up_released || down_released || left_released || right_released)
timeout_ctr <= 25'd0;
else
timeout_ctr <= timeout_ctr + 25'd1;
// Down key shift register (for key press event generation)
always@ (posedge clk or negedge reset_)
if (!reset_)
down_shift <= 2'd0;
else
down_shift <= {down_shift[0], down_debounced};
// Up key shift register (for key press event generation)
always@ (posedge clk or negedge reset_)
if (!reset_)
up_shift <= 2'd0;
else
up_shift <= {up_shift[0], up_debounced};
// Left key shift register (for key press event generation)
always@ (posedge clk or negedge reset_)
if (!reset_)
left_shift <= 2'd0;
else
left_shift <= {left_shift[0], left_debounced};
// Right key shift register (for key press event generation)
always@ (posedge clk or negedge reset_)
if (!reset_)
right_shift <= 2'd0;
else
right_shift <= {right_shift[0], right_debounced};
// State transition register
always@ (posedge clk or negedge reset_)
if (!reset_)
state <= START;
// Initial state; wait for user to press UP
else if (state == START && up_released)
state <= UP_1;
// Up pressed once; wait for user to press up again
else if (state == UP_1 && up_released)
state <= UP_2;
else if (state == UP_1 && (timeout || down_released || left_released || right_released))
state <= REJECT;
// Up pressed twice; wait for user to press down
else if (state == UP_2 && down_released)
state <= DOWN_1;
else if (state == UP_2 && (timeout || up_released || left_released || right_released))
state <= REJECT;
// Down pressed once; wait for user to press down again
else if (state == DOWN_1 && down_released)
state <= DOWN_2;
else if (state == DOWN_1 && (timeout || up_released || left_released || right_released))
state <= REJECT;
// Down pressed twice; wait for user to press left
else if (state == DOWN_2 && left_released)
state <= LEFT_1;
else if (state == DOWN_2 && (timeout || up_released || down_released || right_released))
state <= REJECT;
// Left pressed once; wait for user to press right
else if (state == LEFT_1 && right_released)
state <= RIGHT_1;
else if (state == LEFT_1 && (timeout || left_released || up_released || down_released))
state <= REJECT;
// Right pressed once; wait for user to press left
else if (state == RIGHT_1 && left_released)
state <= LEFT_2;
else if (state == RIGHT_1 && (timeout || up_released || down_released || right_released))
state <= REJECT;
// Left pressed again; wait for user to press right again
else if (state == LEFT_2 && right_released)
state <= ACCEPT;
else if (state == LEFT_2 && (timeout || up_released || down_released || left_released))
state <= REJECT;
// In the ACCEPT or REJECT state; wait for user to press any direction, then return to start
else if ((state == ACCEPT || state == REJECT) && (up_released || down_released || left_released || right_released))
state <= START;
endmodule
|
#include <bits/stdc++.h> using namespace std; map<string, string> mp; map<string, int> stn; void Print(string cur) { string res = / ; while (cur != / ) { string tmp = cur; while (int(tmp.size()) && ( 0 <= tmp[tmp.size() - 1] && tmp[tmp.size() - 1] <= 9 )) tmp.erase(tmp.begin() + tmp.size() - 1); res = / + tmp + res; cur = mp[cur]; } cout << res << endl; } int main() { int n; string s, cur = / ; cin >> n; for (int cn = 0; cn < int(n); cn++) { cin >> s; if (s == pwd ) { Print(cur); } else { cin >> s; int ssize = s.size(); string acc = ; int st = 0; if (s[0] == . ) { cur = mp[cur]; st = 3; } if (s[0] == / ) { cur = / ; st = 1; } acc = ; for (int i = st; i < ssize; i++) { if (s[i] == / ) { if (acc == .. ) { cur = mp[cur]; } else { stn[acc]++; stringstream ss; string nw; ss << stn[acc]; ss >> nw; acc += nw; mp[acc] = cur; cur = acc; } acc = ; } else { acc += s[i]; } } if (acc.size()) { if (acc == .. ) { cur = mp[cur]; } else { stn[acc]++; stringstream ss; string nw; ss << stn[acc]; ss >> nw; acc += nw; mp[acc] = cur; cur = acc; } } } } }
|
//move some stuff to minitests/ncy0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [255:0] din, output [255:0] dout);
clb_N5FFMUX # (.LOC("SLICE_X22Y100"), .N(0))
clb_N5FFMUX_0 (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y101"), .N(1))
clb_N5FFMUX_1 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[8 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y102"), .N(2))
clb_N5FFMUX_2 (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[16 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y103"), .N(3))
clb_N5FFMUX_3 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[24 +: 8]));
endmodule
module clb_N5FFMUX (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X22Y100";
parameter N=-1;
parameter DEF_A=1;
wire lutdo, lutco, lutbo, lutao;
wire lut7bo, lut7ao;
wire lut8o;
reg [3:0] ffds;
wire lutdo5, lutco5, lutbo5, lutao5;
//wire lutno5 [3:0] = {lutao5, lutbo5, lutco5, lutdo5};
wire lutno5 [3:0] = {lutdo5, lutco5, lutbo5, lutao5};
always @(*) begin
/*
ffds[3] = lutdo5;
ffds[2] = lutco5;
ffds[1] = lutbo5;
ffds[0] = lutao5;
*/
/*
ffds[3] = din[6];
ffds[2] = din[6];
ffds[1] = din[6];
ffds[0] = din[6];
*/
if (DEF_A) begin
//Default poliarty A
ffds[3] = lutdo5;
ffds[2] = lutco5;
ffds[1] = lutbo5;
ffds[0] = lutao5;
ffds[N] = din[6];
end else begin
//Default polarity B
ffds[3] = din[6];
ffds[2] = din[6];
ffds[1] = din[6];
ffds[0] = din[6];
ffds[N] = lutno5[N];
end
end
(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
MUXF8 mux8 (.O(), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7b (.O(lut7bo), .I0(lutdo), .I1(lutco), .S(din[6]));
(* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7a (.O(lut7ao), .I0(lutbo), .I1(lutao), .S(din[6]));
(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_DEAD_0000_0001)
) lutd (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutdo5),
.O6(lutdo));
(* LOC=LOC, BEL="D5FF" *)
FDPE ffd (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[3]));
(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_BEEF_0000_0001)
) lutc (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutco5),
.O6(lutco));
(* LOC=LOC, BEL="C5FF" *)
FDPE ffc (
.C(clk),
.Q(dout[2]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[2]));
(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_CAFE_0000_0001)
) lutb (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutbo5),
.O6(lutbo));
(* LOC=LOC, BEL="B5FF" *)
FDPE ffb (
.C(clk),
.Q(dout[3]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[1]));
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_1CE0_0000_0001)
) luta (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutao5),
.O6(lutao));
(* LOC=LOC, BEL="A5FF" *)
FDPE ffa (
.C(clk),
.Q(dout[4]),
.CE(din[0]),
.PRE(din[1]),
//D can only come from O5 or AX
//AX is used by MUXF7:S
.D(ffds[0]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O221AI_PP_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m; struct AA { int p, s; } c[110]; int st[110]; bool cmp1(AA a, AA b) { if (a.p == b.p) return a.s < b.s; return a.p < b.p; } bool vis[110]; int work1() { int ret = 0; sort(c, c + n, cmp1); sort(st, st + m); for (int i = 0; i < n; i++) { if (i == m) break; if (c[i].p == 1) break; if (c[i].s > st[m - 1 - i]) break; ret += st[m - 1 - i] - c[i].s; } return ret; } int work2() { int ret = 0; sort(c, c + n, cmp1); sort(st, st + m); memset(vis, 0, sizeof(vis)); for (int i = 0; i < n; i++) if (c[i].p == 1) { bool fg = true; for (int j = 0; j < m; j++) if (!vis[j] && st[j] > c[i].s) { vis[j] = true; fg = false; break; } if (fg) return 0; } for (int i = 0; i < n; i++) if (c[i].p == 0) { bool fg = true; for (int j = 0; j < m; j++) if (!vis[j] && st[j] >= c[i].s) { vis[j] = true; ret += st[j] - c[i].s; fg = false; break; } if (fg) return 0; } for (int j = 0; j < m; j++) if (!vis[j]) ret += st[j]; return ret; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) { char s[10]; scanf( %s , s); if (s[0] == A ) c[i].p = 0; else c[i].p = 1; scanf( %d , &c[i].s); } for (int i = 0; i < m; i++) scanf( %d , &st[i]); cout << max(work1(), work2()); }
|
#include <bits/stdc++.h> using namespace std; int n, m, i, j; int main() { ios::sync_with_stdio(false); cin >> n; cout << 3 * n / 2 << n ; for (i = 2; i <= n; i += 2) cout << i << ; for (i = 1; i <= n; i += 2) cout << i << ; for (i = 2; i <= n; i += 2) cout << i << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double pi = acos(-1); const int N = 2e5; long long gi() { long long w = 0; bool q = 1; char c = getchar(); while ((c < 0 || c > 9 ) && c != - ) c = getchar(); if (c == - ) q = 0, c = getchar(); while (c >= 0 && c <= 9 ) w = w * 10 + c - 0 , c = getchar(); return q ? w : -w; } int main() { long long n = gi(), m = gi(), a = gi(), d = gi(), last = 0, k, x, y, ans = 0, u = d / a + 1; while (m--) { k = gi(); x = max(last / a + 1, 1LL); y = min(k / a, n); if (x <= y) { ans += (y - x) / u + 1; last = (x + (y - x) / u * u) * a + d; } if (last < k) last = k + d, ans++; } x = max(last / a + 1, 1LL); if (x <= n) ans += (n - x) / u + 1; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int t, n; string s; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> t; while (t--) { cin >> s; n = s.length(); int m = n, M = -1; for (int i = 0; i < n; i++) { if (s[i] == 1 ) { m = min(m, i); M = max(M, i); } } if (m > M) { cout << 0 << endl; } else { int cnt = 0; for (int i = m; i < M; i++) { cnt += (s[i] == 0 ); } cout << cnt << endl; } } }
|
#include <bits/stdc++.h> using namespace std; int A[100][10000]; int d[100][10000]; int main() { int n, m; cin >> n >> m; string str; getline(cin, str); for (int i = 0; i < n; i++) { getline(cin, str); for (int j = 0; j < str.size(); j++) if (str[j] == 1 ) A[i][j] = 1; else A[i][j] = 0; } for (int i = 0; i < n; i++) { int prev = 1000001; int prev2 = 100000; for (int j = m - 1; j >= 0; j--) if (A[i][j]) { prev = -(m - j); break; } if (prev == 1000001) { cout << -1 << endl; return 0; } bool first = true; for (int j = 0; j < m; j++) { if (A[i][j]) { if (first) { prev2 = j + 1 + m - 1; first = false; } d[i][j] = 0; prev = j; } else d[i][j] = j - prev; } for (int j = m - 1; j >= 0; j--) { d[i][j] = min(d[i][j], prev2 - j); if (A[i][j]) prev2 = j; } } int mindall = 1000000; for (int i = 0; i < m; i++) { int mind = 0; for (int j = 0; j < n; j++) { mind += d[j][i]; } mindall = min(mindall, mind); } cout << mindall << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBP_BEHAVIORAL_PP_V
|
#include<bits/stdc++.h> #define fo(i,a,b) for(int i=a;i<=b;i++) #define fd(i,a,b) for(int i=a;i>=b;i--) using namespace std; typedef long long LL; typedef pair<int,int> pr; const int maxn=505; int n,m; char mp[maxn][maxn]; int T; int main() { scanf( %d ,&T); while (T--) { scanf( %d %d ,&n,&m); fo(i,1,n) scanf( %s ,mp[i]+1); fo(i,1,n) if (i%3==1) fo(j,1,m) mp[i][j]= X ; fo(i,1,n) if (i%3==1 && i+3<=n) { bool pd=0; fo(j,1,m) if (mp[i+1][j]== X ) { mp[i+2][j]= X ; pd=1; break; } if (pd) continue; fo(j,1,m) if (mp[i+2][j]== X ) { mp[i+1][j]= X ; pd=1; break; } if (pd) continue; mp[i+1][1]=mp[i+2][1]= X ; } if (n%3==0) { fo(j,1,m) if (mp[n][j]== X ) mp[n-1][j]= X ; } fo(i,1,n) printf( %s n ,mp[i]+1); } }
|
#include <bits/stdc++.h> using namespace std; const long long MX = 1e5 + 10; long long A[MX]; long long cnt[MX]; vector<long long> pos[MX]; long long ans[MX]; void init(long long n) { for (long long i = 0; i <= n + 2; i++) cnt[i] = 0; for (long long i = 0; i <= n + 2; i++) pos[i].clear(); for (long long i = 0; i <= n + 2; i++) ans[i] = -1; } void salida(long long n, long long val) { for (long long i = 0; i < n; i++) if (ans[i] == -1) ans[i] = val; cout << YES n ; for (long long i = 0; i < n; i++) cout << ans[i] << ; cout << n ; } void solve() { long long n, fijo, tot, x; cin >> n >> fijo >> tot; long long nfijo = tot - fijo; init(n); set<long long> s; for (long long i = 0; i < n; i++) { cin >> x; A[i] = x; cnt[x]++; pos[x].push_back(i); s.insert(x); } long long maxNum = n + 1; priority_queue<pair<long long, long long> > pq; for (long long i = 1; i <= maxNum; i++) { if (cnt[i] != 0) pq.push({cnt[i], i}); } while (!pq.empty() && fijo != 0) { long long cn = pq.top().first; long long val = pq.top().second; pq.pop(); cnt[val]--; if (cnt[val] != 0) pq.push({cnt[val], val}); long long sz = pos[val].size(); ans[pos[val][sz - 1]] = val; pos[val].erase(pos[val].begin() + sz - 1); fijo--; } if (fijo > 0) { cout << NO n ; return; } long long numExtra = -1; for (long long i = 1; i <= maxNum; i++) { if (s.find(i) == s.end()) numExtra = i; } if (nfijo == 0) { salida(n, numExtra); return; } long long falta = 0; for (long long i = 1; i <= maxNum; i++) falta += cnt[i]; long long mxSize = pq.top().first; vector<long long> posi; while (!pq.empty()) { long long val = pq.top().second; pq.pop(); for (long long xx : pos[val]) posi.push_back(xx); } if (mxSize <= falta - mxSize) { long long sz = posi.size(); long long mid = sz / 2; for (long long i = 0; i < sz; i++) { if (nfijo == 0) break; long long cur = i; long long nxt = (i + mid) % sz; ans[posi[cur]] = A[posi[nxt]]; nfijo--; } salida(n, numExtra); } else { reverse(posi.begin(), posi.end()); long long mxPos = falta - mxSize; if (mxPos * 2 < nfijo) { cout << NO n ; return; } long long sz = posi.size(); for (long long i = 0; i < sz; i++) { if (nfijo == 0) break; long long cur = i; long long nxt = i + mxPos; if (nfijo == 0) break; ans[posi[cur]] = A[posi[nxt]]; nfijo--; if (nfijo == 0) break; ans[posi[nxt]] = A[posi[cur]]; nfijo--; } salida(n, numExtra); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout.precision(10); cout << fixed; long long t; cin >> t; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int c = 0, m = 0, y = 0, w = 0, g = 0, b = 0, d, e; cin >> d >> e; char arr[d][e]; for (int i = 0; i < d; i++) { for (int j = 0; j < e; j++) { cin >> arr[i][j]; if (arr[i][j] == M ) { m++; } else if (arr[i][j] == C ) { c++; } else if (arr[i][j] == Y ) { y++; } else if (arr[i][j] == W ) { w++; } else if (arr[i][j] == G ) { g++; } else if (arr[i][j] == B ) { b++; } } } if (y == 0 && c == 0 && m == 0) { cout << #Black&White ; } else { cout << #Color ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 300100; const int K = 1001000; vector<int> v[K]; int a[N], s[N]; int l[N], r[N]; int q[N], id[N]; int main() { int n, k; scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } s[0] = a[0] % k; v[0].push_back(-1); v[s[0]].push_back(0); for (int i = 1; i < n; i++) { s[i] = (s[i - 1] + a[i]) % k; v[s[i]].push_back(i); } int c = 0; for (int i = 0; i < n; i++) { while (c && a[q[c - 1]] < a[i]) c--; l[i] = 0; if (c) { l[i] = q[c - 1] + 1; } q[c++] = i; } c = 0; for (int i = n - 1; i >= 0; i--) { while (c && a[q[c - 1]] <= a[i]) c--; r[i] = n - 1; if (c) { r[i] = q[c - 1] - 1; } q[c++] = i; } long long ans = 0; for (int i = 0; i < n; i++) { if (i - l[i] >= r[i] - i) { for (int j = i; j <= r[i]; j++) { int x = (s[j] - a[i]) % k; if (x < 0) { x += k; } int ll = l[i] - 1, rr = i - 1; if (j == i) rr = i - 2; ans += upper_bound(v[x].begin(), v[x].end(), rr) - lower_bound(v[x].begin(), v[x].end(), ll); } } else { for (int j = l[i]; j <= i; j++) { int x = (a[i] + s[j - 1]) % k; if (x < 0) { x += k; } int ll = i, rr = r[i]; if (j == i) ll = i + 1; ans += upper_bound(v[x].begin(), v[x].end(), rr) - lower_bound(v[x].begin(), v[x].end(), ll); } } } printf( %lld n , ans); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVPWRVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__TAPVPWRVGND_BEHAVIORAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvpwrvgnd (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVPWRVGND_BEHAVIORAL_PP_V
|
// File: SIPO_TBV.v
// Generated by MyHDL 0.10
// Date: Wed Sep 5 07:52:49 2018
`timescale 1ns/10ps
module SIPO_TBV (
);
// myHDL -> Verilog Testbench for `SIPO` module
reg clk = 0;
wire rst;
reg SerialIn = 0;
wire [3:0] BusOut;
wire [11:0] SerialVals;
reg [3:0] SIPO0_0_Buffer = 0;
assign rst = 1'd0;
assign SerialVals = 12'd3024;
always @(rst, BusOut, SerialIn, clk) begin: SIPO_TBV_PRINT_DATA
$write("%h", SerialIn);
$write(" ");
$write("%h", BusOut);
$write(" ");
$write("%h", clk);
$write(" ");
$write("%h", rst);
$write("\n");
end
always @(posedge clk, negedge rst) begin: SIPO_TBV_SIPO0_0_LOGIC
if (rst) begin
SIPO0_0_Buffer <= 0;
end
else begin
SIPO0_0_Buffer <= {SIPO0_0_Buffer[4-1:0], SerialIn};
end
end
assign BusOut = SIPO0_0_Buffer;
initial begin: SIPO_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: SIPO_TBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
if ((i < 12)) begin
SerialIn <= SerialVals[i];
end
else if ((i == 12)) begin
// pass
end
else if ((i > 12)) begin
$finish;
end
i = i + 1;
@(posedge clk);
end
$finish;
end
endmodule
|
module j1soc#(
//parameter bootram_file = "../../firmware/hello_world/j1.mem" // For synthesis
parameter bootram_file = "../firmware/Hello_World/j1.mem" // For simulation
)(
uart_tx, ledout,
sys_clk_i, sys_rst_i, mosi ,miso, sck, ss, SDA, SCL, pwm, adelante, atras, rs, e , data, tx_channel, rx_channel, rx_busy, tx_busy
);
// entradas y salidas fisicas
input sys_clk_i, sys_rst_i;
output uart_tx;
output ledout;
//spi
input mosi;
output miso;
output sck;
output ss;
// I2C
inout SDA;
output SCL;
//pwm
output [2:0] pwm ;
// Direccion
output [1:0] adelante ;
output [1:0] atras ;
//LCD
output rs;
output e;
output [7:0] data;
//posicion
output SCL;
inout SDA;
wire SDA_oen, SDA_out ;
// Uart 2
input rx_channel; // Canal de lectura
output tx_channel; // Canal de escritura (tranmision)
output tx_busy; // Canal de transmision esta ocupado
output rx_busy ; // Canal de lectura esta ocupado
assign SDA = (SDA_oen) ? SDA_out : 1'bz;
assign SDA_in = SDA;
//------------------------------------ regs and wires-------------------------------
wire j1_io_rd;//********************** J1
wire j1_io_wr;//********************** J1
wire [15:0] j1_io_addr;//************* J1
reg [15:0] j1_io_din;//************** J1
wire [15:0] j1_io_dout;//************* J1
reg [1:14]cs; // CHIP-SELECT //cantidad de modulos
wire [15:0] mult_dout;
wire [15:0] div_dout;
wire uart_dout; // misma señal que uart_busy from uart.v
wire [15:0] dp_ram_dout;
wire [15:0] spi_master_dout;
wire [15:0] crc_7_dout;
wire [15:0] crc_16_dout;
wire [15:0] pwm_dout;
wire [15:0] lcd_dout;
wire [15:0] posicion_dout;
wire [15:0] timmer_dout;
wire [15:0] distancia_dout;
wire [15:0] direccion;
wire [15:0] uart_2;
//------------------------------------ regs and wires-------------------------------
j1 #(bootram_file) cpu0(sys_clk_i, sys_rst_i, j1_io_din, j1_io_rd, j1_io_wr, j1_io_addr, j1_io_dout);
peripheral_mult per_m ( .clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_din), .cs(cs[1]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(mult_dout) );
peripheral_div per_d (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_din), .cs(cs[2]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(div_dout));
peripheral_uart per_u (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_din), .cs(cs[3]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(uart_dout), .uart_tx(uart_tx), .ledout(ledout));
dpRAM_interface dpRm(.clk(sys_clk_i), .d_in(j1_io_dout), .cs(cs[4]), .addr(j1_io_addr[7:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(dp_ram_dout));
peripheral_spi_master per_spi (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[5]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(spi_master_dout) , .mosi(mosi) ,.miso(miso), .sck(sck), .ss(ss) ); //se instancia el peripheral de spi
peripheral_crc_7 per_crc_7 (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[6]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(crc_7_dout) ); //se instancia el peripheral de crc_7
peripheral_crc_16 per_crc_16 (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[7]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(crc_16_dout) ); //se instancia el peripheral de crc_16
peripheral_pwm per_pwm (.clk(sys_clk_i),.rst(sys_rst_i),.d_in(j1_io_dout),.d_out(pwm_out),.cs(cs[8]),.addr(j1_io_addr[3:0]),.rd(j1_io_rd),.wr(j1_io_wr),.pwm(pwm));
LCD_Peripheral per_lcd (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[9]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(lcd_out), .rs(lcd_rs), .e(lcd_e), .data(lcd_data), .int_cnt(int_cnt), .en_cnt(en_cnt), .limit_cnt(limit_cnt) );
position_peripheral (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[10]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(posicion_out), .clk_freq(clk_freq), .counter_rst(counter_rst), .counter_en (counter_en), . int_en(int_en), .int_limit(int_limit), .SCL(SCL), .SDA_out(SDA_out), .SDA_oen(SDA_oen), .counter_count(counter_count), .clk_frame(clk_frame), .int_o(int_o), .SDA_in(SDA_in));
peripheral_timmer (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[11]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr),.d_out( timmer_out ));
peripheral_distancia (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[12]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr),.d_out( distancia_out ));
peripheral_direccion per_dir (.clk(sys_clk_i),.rst(sys_rst_i),.d_in(j1_io_dout),.d_out(pwm_out),.cs(cs[13]),.addr(j1_io_addr[3:0]),.rd(j1_io_rd),.wr(j1_io_wr),.adelante(adelante),.atras(atras));
peripheral_uart_2 per_uart (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_din), .cs(cs[14]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(d_out), .rx_channel(rx_channel), .tx_channel(tx_channel), .tx_busy(tx_busy), .rx_busy(rx_busy) ) ;
// ============== Chip_Select (Addres decoder) ======================== // se hace con los 8 bits mas significativos de j1_io_addr
always @*
begin
case (j1_io_addr[15:8]) // direcciones - chip_select
8'h67: cs= 14'b10000000000000; //mult
8'h68: cs= 14'b01000000000000; //div
8'h69: cs= 14'b00100000000000; //uart
8'h70: cs= 14'b00010000000000; //dp_ram
8'h72: cs= 14'b00001000000000; //spi
8'h74: cs= 14'b00000100000000; //crc_7
8'h76: cs= 14'b00000010000000; //crc_16
8'h60: cs= 14'b00000001000000; //pwm
8'h61: cs= 14'b00000000100000; //lcd
8'h62: cs= 14'b00000000010000; //posicion
8'h63: cs= 14'b00000000001000; //timmer
8'h64: cs= 14'b00000000000100; //distancia
8'h65: cs= 14'b00000000000010; //direccion
8'h65: cs= 14'b00000000000001; //Segunda Uart
default: cs= 14'b0000000000000;
endcase
end
// ============== Chip_Select (Addres decoder) ======================== //
// ============== MUX ======================== // se encarga de lecturas del J1
always @*
begin
case (cs)
14'b10000000000000: j1_io_din = mult_dout;
14'b01000000000000: j1_io_din = div_dout;
14'b00100000000000: j1_io_din = uart_dout;
14'b00010000000000: j1_io_din = dp_ram_dout;
14'b00001000000000: j1_io_din = spi_master_dout;
14'b00000100000000: j1_io_din = crc_7_dout;
14'b00000010000000: j1_io_din = crc_16_dout;
14'b00000001000000: j1_io_din = pwm_dout;
14'b00000000100000: j1_io_din = lcd_dout;
14'b00000000010000: j1_io_din = posicion_dout;
14'b00000000001000: j1_io_din = timmer_dout;
14'b00000000000100: j1_io_din = distancia_dout;
14'b00000000000010: j1_io_din = direccion;
14'b00000000000001: j1_io_din = uart_2;
default: j1_io_din = 16'h0666;
endcase
end
// ============== MUX ======================== //
endmodule // top
|
#include <bits/stdc++.h> using namespace std; long long int dp[5005][5005]; int main() { long long int n, m, k; cin >> n >> m >> k; long long int arr[n + 1]; long long int sum[n + 1]; for (int i = 1; i <= n; i++) cin >> arr[i]; sum[1] = 0; for (int i = 1; i <= m; i++) sum[1] += arr[i]; for (int i = 2; i <= n - m + 1; i++) sum[i] = sum[i - 1] + arr[i + m - 1] - arr[i - 1]; long long int res = -1; for (int i = 1; i <= n - m + 1; i++) dp[1][i] = max(dp[1][i - 1], sum[i]); for (int i = 2; i <= k; i++) { for (int j = 1; j <= n - m + 1; j++) { if (j > m * (i - 1)) dp[i][j] = max(dp[i][j - 1], dp[i - 1][j - m] + sum[j]); } } cout << dp[k][n - m + 1] << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXBP_TB_V
`define SKY130_FD_SC_HS__DFXBP_TB_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 D = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 D = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 D = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21AI_2_V
`define SKY130_FD_SC_LS__O21AI_2_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21ai_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21AI_2_V
|
#include <bits/stdc++.h> long long R = 7 + 1e9, NUMTESTCASE; const int NN = 10 + 2e6; const double pi = acos(-1.0); int di[4] = {1, 0, -1, 0}, dj[4] = {0, 1, 0, -1}, DI[8] = {1, 1, 0, -1, -1, -1, 0, 1}, DJ[8] = {0, 1, 1, 1, 0, -1, -1, -1}; using namespace std; int n, ti = 1, timein[NN], timeout[NN], lev[NN], parn[NN], Hash[NN], m, segtree[NN]; vector<int> G[NN]; void DFS(int ver, int par, int cnt) { int in = ti++; for (int u : G[ver]) if (u != par) DFS(u, ver, cnt + 1); Hash[ver] = ++m; lev[Hash[ver]] = cnt; parn[Hash[ver]] = par; timein[Hash[ver]] = in; timeout[Hash[ver]] = ti++; } bool isgra(int ver, int par) { return (timein[par] <= timein[ver] && timeout[par] >= timeout[ver]); } unordered_map<int, unordered_map<int, int> > memo; int com_par(int u, int v) { if (isgra(v, u)) return u; if (isgra(u, v)) return v; auto it1 = memo.find(u); if (it1 != memo.end()) { auto it2 = it1->second.find(v); if (it2 != it1->second.end()) return it2->second; } return memo[u][v] = memo[v][u] = com_par(u, parn[v]); } void build(int pos, int st, int en) { if (st == en) { segtree[pos] = st; return; } build(2 * pos, st, (st + en) / 2); build(2 * pos + 1, (st + en) / 2 + 1, en); segtree[pos] = com_par(segtree[2 * pos], segtree[2 * pos + 1]); } int seg_com_par(int pos, int st, int en, int u, int v) { if (en < u || st > v) return -1; if (st >= u && en <= v) return segtree[pos]; int flag1 = seg_com_par(2 * pos, st, (st + en) / 2, u, v); int flag2 = seg_com_par(2 * pos + 1, (st + en) / 2 + 1, en, u, v); int res; if (flag1 != -1 && flag2 != -1) res = com_par(flag1, flag2); else if (flag1 != -1) res = flag1; else res = flag2; return res; } int dis(int v, int u) { if (u > v) swap(u, v); return lev[v] + lev[u] - 2 * lev[seg_com_par(1, 1, m, u, v)]; } int main() { cin >> n; int u, v; for (int i = (1); i <= (n - 1); ++i) { scanf( %d%d , &u, &v); G[u].push_back(v); G[v].push_back(u); } DFS(1, -1, 0); parn[Hash[1]] = 1; for (int i = (1); i <= (n); ++i) parn[i] = Hash[parn[i]]; build(1, 1, m); int x, y, a, b, k, q; cin >> q; while (q--) { scanf( %d%d%d%d%d , &x, &y, &a, &b, &k); x = Hash[x]; y = Hash[y]; a = Hash[a]; b = Hash[b]; int flag = 0, ab = dis(a, b), axyb = 1 + dis(a, x) + dis(y, b), ayxb = 1 + dis(a, y) + dis(x, b); if (ab % 2 == k % 2 && ab <= k) flag = 1; if (axyb % 2 == k % 2 && axyb <= k) flag = 1; if (ayxb % 2 == k % 2 && ayxb <= k) flag = 1; printf(flag ? YES n : NO n ); } return 0; }
|
module reversed_gate (clk, ctrl, din, sel, dout);
input clk;
input [4:0] ctrl;
input [15:0] din;
input [3:0] sel;
output reg [31:0] dout;
always @(posedge clk)
case ((({(32)-((ctrl)*(sel))})+(1))-(2))
0:
dout[1:0] <= din;
1:
dout[2:1] <= din;
2:
dout[3:2] <= din;
3:
dout[4:3] <= din;
4:
dout[5:4] <= din;
5:
dout[6:5] <= din;
6:
dout[7:6] <= din;
7:
dout[8:7] <= din;
8:
dout[9:8] <= din;
9:
dout[10:9] <= din;
10:
dout[11:10] <= din;
11:
dout[12:11] <= din;
12:
dout[13:12] <= din;
13:
dout[14:13] <= din;
14:
dout[15:14] <= din;
15:
dout[16:15] <= din;
16:
dout[17:16] <= din;
17:
dout[18:17] <= din;
18:
dout[19:18] <= din;
19:
dout[20:19] <= din;
20:
dout[21:20] <= din;
21:
dout[22:21] <= din;
22:
dout[23:22] <= din;
23:
dout[24:23] <= din;
24:
dout[25:24] <= din;
25:
dout[26:25] <= din;
26:
dout[27:26] <= din;
27:
dout[28:27] <= din;
28:
dout[29:28] <= din;
29:
dout[30:29] <= din;
30:
dout[31:30] <= din;
31:
dout[31:31] <= din;
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_TB_V
`define SKY130_FD_SC_LS__NOR3B_TB_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor3b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C_N = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C_N = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__nor3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 110; int N; struct notlaptop { int speed, ram, hdd, cost; notlaptop(int a, int b, int c, int d) { speed = a; ram = b; hdd = c; cost = d; } notlaptop()<% %> }; notlaptop ar[MAXN]; int main() { scanf( %d , &N); for (int i = 0; i < N; i++) { int a, b, c, d; cin >> a >> b >> c >> d; ar[i] = notlaptop(a, b, c, d); } int bcost = 1e9, res = -1; for (int i = 0; i < N; i++) { bool outdated = false; for (int j = 0; j < N; j++) { if (ar[i].speed < ar[j].speed and ar[i].ram < ar[j].ram and ar[i].hdd < ar[j].hdd) { outdated = true; break; } } if (!outdated) { if (ar[i].cost < bcost) { bcost = ar[i].cost, res = i + 1; } } } cout << res << n ; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: demux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple demultiplexer
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module demux
#(
parameter C_OUTPUTS = 12,
parameter C_WIDTH = 1
)
(
input [C_WIDTH-1:0] WR_DATA,// Inputs
input [clog2s(C_OUTPUTS)-1:0] WR_SEL,// Selector
output [C_OUTPUTS*C_WIDTH-1:0] RD_DATA// Outputs
);
genvar i;
reg [C_OUTPUTS*C_WIDTH-1:0] _rOut;
assign RD_DATA = _rOut;
always @(*) begin
_rOut = 0;
_rOut[C_WIDTH*WR_SEL +: C_WIDTH] = WR_DATA;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, a, b, c, d, e, f, g, h; cin >> n; vector<long long int> values(n), kalues(n), malues; for (int i = 0; i < n; i++) { cin >> values[i]; cin >> kalues[i]; kalues[i]--; malues.push_back(values[i]); malues.push_back(kalues[i]); } sort(values.begin(), values.end()); sort(kalues.begin(), kalues.end()); sort(malues.begin(), malues.end()); long long int mini = -5, year = -1; malues.erase(unique(malues.begin(), malues.end()), malues.end()); for (int i = 0; i < 2 * n; i++) { long long int helebele = lower_bound(kalues.begin(), kalues.end(), malues[i]) - kalues.begin(); helebele += n - (upper_bound(values.begin(), values.end(), malues[i]) - values.begin()); if (mini < n - helebele) mini = n - helebele, year = malues[i]; } cout << year << << mini << endl; }
|
#include <bits/stdc++.h> using namespace std; long long n, a = 0; int main() { cin >> n; n = abs(n); while ((a * (a + 1)) / 2 < n || ((a * (a + 1)) / 2) % 2 != n % 2) a++; cout << a; return 0; }
|
/*
* Milkymist VJ SoC fjmem flasher
* Copyright (C) 2010 Michael Walle <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
module fjmem #(
parameter adr_width = 24
) (
input sys_clk,
input sys_rst,
/* flash */
output [adr_width-1:0] flash_adr,
inout [15:0] flash_d,
output flash_oe_n,
output flash_we_n,
/* debug output */
output fjmem_update
);
wire jtag_tck;
wire jtag_rst;
wire jtag_update;
wire jtag_shift;
wire jtag_tdi;
wire jtag_tdo;
fjmem_core #(
.adr_width(adr_width)
) core (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
/* jtag */
.jtag_tck(jtag_tck),
.jtag_rst(jtag_rst),
.jtag_update(jtag_update),
.jtag_shift(jtag_shift),
.jtag_tdi(jtag_tdi),
.jtag_tdo(jtag_tdo),
/* flash */
.flash_adr(flash_adr),
.flash_d(flash_d),
.flash_oe_n(flash_oe_n),
.flash_we_n(flash_we_n),
/* debug */
.fjmem_update(fjmem_update)
);
fjmem_jtag jtag (
.jtag_tck(jtag_tck),
.jtag_rst(jtag_rst),
.jtag_update(jtag_update),
.jtag_shift(jtag_shift),
.jtag_tdi(jtag_tdi),
.jtag_tdo(jtag_tdo)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int n, k, a[303], flipped[303]; int query(int l, int r) { cout << ? << l << << r << endl; cin >> l; fflush(stdin); return l; } void flip(int l, int r) { for (int i = l; i < r + 1; i++) { flipped[i] ^= 1; } } void sol(int l, int r, int segk, bool f) { if (l > r) return; int lc = 0, rc = 0; for (int i = 1; i < l; i++) lc += a[i] ^ flipped[i]; for (int i = r + 1; i < n + 1; i++) rc += a[i] ^ flipped[i]; if (l == r) a[l] = flipped[l] ^ segk; else if (f) { while (1) { int q = query(l, r - 1); if (lc + n - r - rc + r - l + 1 - segk == q) { segk = r - l + 1 - segk; rc = n - r - rc; flip(l, n); } else { int g = (q + 1 + lc + segk - r - rc) / 2; a[r] = flipped[r] ^ g; lc = l - 1 - lc; segk = r - l - segk + 2 * g; flip(1, r - 1); sol(l, r, segk, !f); return; } } } else { while (1) { int q = query(l + 1, r); if (l - 1 - lc + rc + r - l + 1 - segk == q) { segk = r - l + 1 - segk; lc = l - 1 - lc; flip(1, r); } else { int g = (q + rc + l + segk - n - lc) / 2; a[l] = flipped[l] ^ g; rc = n - r - rc; segk = r - l - segk + g; flip(l + 1, n); sol(l + 1, r - 1, segk - (a[r] ^ flipped[r]), !f); return; } } } } void disp() { cout << ! ; for (int i = 1; i < n + 1; i++) cout << a[i]; cout << endl; } void solve() { cin >> n >> k; sol(1, n, k, 1); disp(); } signed main() { int t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1000000000; const long long INFLL = INF * INF; long long pot2[100]; vector<long long> czek_all(long long l, long long r, long long k) { vector<long long> wynik; long long x = r - l + 1; long long res = INFLL; for (int i = (1); i <= (pot2[x] - 1); ++i) { vector<long long> v; long long a = i, ile = 0; long long tmp = 0; for (int j = (0); j <= ((x)-1); ++j) { if (a % 2 == 1) { v.push_back(l + j); tmp = tmp ^ (l + j); ile++; } a /= 2; } if (tmp < res && ile <= k) { res = tmp; wynik = v; } } return wynik; } void jebaj() { pot2[0] = 1; for (int i = (0); i <= ((60) - 1); ++i) pot2[i + 1] = pot2[i] * 2; long long l, r, k; cin >> l >> r >> k; if (k == 1) { cout << l << n << 1 << n << l << n ; return; } if (r - l < 8) { vector<long long> v = czek_all(l, r, k); long long kk = 0; for (__typeof((v).begin()) it = ((v).begin()); it != (v).end(); ++it) kk = kk ^ (*it); cout << kk << n ; cout << (int)((v).size()) << n ; for (__typeof((v).begin()) it = ((v).begin()); it != (v).end(); ++it) cout << *it << ; cout << n ; return; } long long a = l; while (a % 4 > 0) { a++; } if (k >= 4) { cout << 0 << n << 4 << n ; for (int i = (0); i <= ((4) - 1); ++i) { cout << a << ; a++; } cout << n ; return; } if (k == 2) { cout << 1 << n << 2 << n ; cout << a << << a + 1 << n ; return; } int h = 0; while (pot2[h] <= l) h++; long long pot = pot2[h]; if (pot >= r) { cout << 1 << n << 2 << n ; cout << a << << a + 1 << n ; return; } long long x = pot + pot2[h - 1]; if (x <= r) { cout << 0 << n << 3 << n ; cout << pot - 1 << << x << << (x ^ (pot - 1)) << n ; return; } cout << 1 << n << 2 << n ; cout << a << << a + 1 << n ; return; return; } int main() { ios_base::sync_with_stdio(0); int t; t = 1; for (int i = (0); i <= ((t)-1); ++i) { jebaj(); } }
|
#include <bits/stdc++.h> using namespace std; template <class T> bool setmax(T &_a, T _b) { if (_b > _a) { _a = _b; return true; } return false; } template <class T> bool setmin(T &_a, T _b) { if (_b < _a) { _a = _b; return true; } return false; } template <class T> T gcd(T _a, T _b) { return _b == 0 ? _a : gcd(_b, _a % _b); } const int MAXN = 1010; bool vis[MAXN]; vector<int> es[MAXN]; int n; int que[MAXN], lst[MAXN], d[MAXN], ss, tt; void bfs(int start) { ss = tt = 1; que[1] = start; vis[start] = true; d[start] = 0; while (ss <= tt) { int x = que[ss++]; for (int y : es[x]) if (!vis[y]) { vis[y] = true; d[y] = d[x] + 1; que[++tt] = y; } } } int solve_component(int start) { bfs(start); int len = tt; for (int i = int(1); i <= int(len); ++i) lst[i] = que[i]; int ans = -1; for (int k = int(1); k <= int(len); ++k) { for (int i = int(1); i <= int(len); ++i) vis[lst[i]] = false; bfs(lst[k]); bool ok = true; for (int i = int(1); i <= int(tt); ++i) { int x = que[i]; for (int y : es[x]) if (abs(d[x] - d[y]) != 1) ok = false; } if (ok) setmax(ans, d[que[tt]]); } return ans; } int main() { int m; scanf( %d%d , &n, &m); for (int i = int(1); i <= int(n); ++i) es[i].clear(); for (int i = int(1); i <= int(m); ++i) { int x, y; scanf( %d%d , &x, &y); es[x].push_back(y), es[y].push_back(x); } memset(vis, false, sizeof(vis)); int ans = 0; for (int i = int(1); i <= int(n); ++i) if (!vis[i]) { int tmp = solve_component(i); if (tmp < 0) { ans = -1; break; } ans += tmp; } printf( %d n , ans); return 0; }
|
// The four D flip-flops (DFFs) in a Cyclone V/10GX Adaptive Logic Module (ALM)
// act as one-bit memory cells that can be placed very flexibly (wherever there's
// an ALM); each flop is represented by a MISTRAL_FF cell.
//
// The flops in these chips are rather flexible in some ways, but in practice
// quite crippled by FPGA standards.
//
// What the flops can do
// ---------------------
// The core flop acts as a single-bit memory that initialises to zero at chip
// reset. It takes in data on the rising edge of CLK if ENA is high,
// and outputs it to Q. The ENA (clock enable) pin can therefore be used to
// capture the input only if a condition is true.
//
// The data itself is zero if SCLR (synchronous clear) is high, else it comes
// from SDATA (synchronous data) if SLOAD (synchronous load) is high, or DATAIN
// if SLOAD is low.
//
// If ACLR (asynchronous clear) is low then Q is forced to zero, regardless of
// the synchronous inputs or CLK edge. This is most often used for an FPGA-wide
// power-on reset.
//
// An asynchronous set that sets Q to one can be emulated by inverting the input
// and output of the flop, resulting in ACLR forcing Q to zero, which then gets
// inverted to produce one. Likewise, logic can operate on the falling edge of
// CLK if CLK is inverted before being passed as an input.
//
// What the flops *can't* do
// -------------------------
// The trickiest part of the above capabilities is the lack of configurable
// initialisation state. For example, it isn't possible to implement a flop with
// asynchronous clear that initialises to one, because the hardware initialises
// to zero. Likewise, you can't emulate a flop with asynchronous set that
// initialises to zero, because the inverters mean the flop initialises to one.
//
// If the input design requires one of these cells (which appears to be rare
// in practice) then synth_intel_alm will fail to synthesize the design where
// other Yosys synthesis scripts might succeed.
//
// This stands in notable contrast to e.g. Xilinx flip-flops, which have
// configurable initialisation state and native synchronous/asynchronous
// set/clear (although not at the same time), which means they can generally
// implement a much wider variety of logic.
// DATAIN: synchronous data input
// CLK: clock input (positive edge)
// ACLR: asynchronous clear (negative-true)
// ENA: clock-enable
// SCLR: synchronous clear
// SLOAD: synchronous load
// SDATA: synchronous load data
//
// Q: data output
//
// Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements.
(* abc9_box, lib_whitebox *)
module MISTRAL_FF(
input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA,
output reg Q
);
`ifdef cyclonev
specify
if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;
if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;
if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 618;
$setup(DATAIN, posedge CLK, /* -196 */ 0);
$setup(ENA, posedge CLK, /* -196 */ 0);
$setup(SCLR, posedge CLK, /* -196 */ 0);
$setup(SLOAD, posedge CLK, /* -196 */ 0);
$setup(SDATA, posedge CLK, /* -196 */ 0);
if (ACLR === 1'b0) (ACLR => Q) = 282;
endspecify
`endif
`ifdef cyclone10gx
specify
// TODO (long-term): investigate these numbers.
// It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.
if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219;
if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219;
if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219;
$setup(DATAIN, posedge CLK, 268);
$setup(ENA, posedge CLK, 268);
$setup(SCLR, posedge CLK, 268);
$setup(SLOAD, posedge CLK, 268);
$setup(SDATA, posedge CLK, 268);
if (ACLR === 1'b0) (ACLR => Q) = 0;
endspecify
`endif
initial begin
// Altera flops initialise to zero.
Q = 0;
end
always @(posedge CLK, negedge ACLR) begin
// Asynchronous clear
if (!ACLR) Q <= 0;
// Clock-enable
else if (ENA) begin
// Synchronous clear
if (SCLR) Q <= 0;
// Synchronous load
else if (SLOAD) Q <= SDATA;
else Q <= DATAIN;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cout.tie(0), cin.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<string> ar(n); long long cnt = 0; vector<vector<int>> dp(n + 1, vector<int>(m + 1, 0)); for (int i = 0; i < n; i++) { cin >> ar[i]; for (int j = 0; j < m; j++) { dp[i][j] = (ar[i][j] == * ); cnt += (ar[i][j] == * ); } } for (int i = 0; i < n; i++) { for (int j = 1; j < m; j++) { dp[i][j] += dp[i][j - 1]; } } // 1st Sol. : from base to head but with binary search on answer - O(N^3 . Log(N)). // 2nd Sol. : let * in position [i, j] be the head of k-tree and try to go downward - O(N^3). for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (ar[i][j] == * ) { int rows = i + 1; int cols_left = j - 1; int cols_right = j + 1; int temp = 0; bool ok = true; while (rows < n && ok) { int cur = dp[rows][cols_right]; if (cols_left - 1 >= 0) { cur -= dp[rows][cols_left - 1]; } if (cur == cols_right - cols_left + 1) { temp++; rows++; cols_left--; cols_right++; } else { ok = false; } } cnt += temp; } } } cout << cnt << n ; } }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.