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#include <bits/stdc++.h> using namespace std; const int maxn = 3e8; int l, r, cnt, ans1, pre1[20000005]; bitset<maxn> pre; int max1, max2; int main() { cin >> l >> r; pre[1] = pre[0] = 1; ans1 = 1; for (int yui = 2; yui <= r; yui++) { if (pre[yui] == 0) { cnt++; pre1[cnt] = yui; if (yui % 4 == 1) ans1++; } if (yui == l - 1) max1 = ans1; if (yui == r) max2 = ans1; for (int j = 1; j <= cnt && pre1[j] * yui <= r; j++) { pre[yui * pre1[j]] = 1; if (yui % pre1[j] == 0) break; } } cout << max2 - max1; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21O_SYMBOL_V
`define SKY130_FD_SC_MS__A21O_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long x, long long y) { if (x == 0) return y; return gcd(y % x, x); } int main() { int t; long long r, b, k; scanf( %d , &t); while (t--) { scanf( %I64d%I64d%I64d , &r, &b, &k); long long Gcd = gcd(r, b); r /= Gcd; b /= Gcd; if (r <= (k - 1) * b + 1 && b <= (k - 1) * r + 1) printf( OBEY n ); else printf( REBEL n ); } }
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Write-back Mux ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// CPU's write-back stage of the pipeline ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_wbmux.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.3 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.2 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:23 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_wbmux(
// Clock and reset
clk, rst,
// Internal i/f
wb_freeze, rfwb_op,
muxin_a, muxin_b, muxin_c, muxin_d,
muxout, muxreg, muxreg_valid
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Internal i/f
//
input wb_freeze;
input [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
input [width-1:0] muxin_a;
input [width-1:0] muxin_b;
input [width-1:0] muxin_c;
input [width-1:0] muxin_d;
output [width-1:0] muxout;
output [width-1:0] muxreg;
output muxreg_valid;
//
// Internal wires and regs
//
reg [width-1:0] muxout;
reg [width-1:0] muxreg;
reg muxreg_valid;
//
// Registered output from the write-back multiplexer
//
always @(posedge clk or posedge rst) begin
if (rst) begin
muxreg <= #1 32'd0;
muxreg_valid <= #1 1'b0;
end
else if (!wb_freeze) begin
muxreg <= #1 muxout;
muxreg_valid <= #1 rfwb_op[0];
end
end
//
// Write-back multiplexer
//
always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
`else
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
`endif
2'b00: muxout = muxin_a;
2'b01: begin
muxout = muxin_b;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_b %h", muxin_b);
// synopsys translate_on
`endif
end
2'b10: begin
muxout = muxin_c;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_c %h", muxin_c);
// synopsys translate_on
`endif
end
2'b11: begin
muxout = muxin_d + 32'h8;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_d %h", muxin_d + 4'h8);
// synopsys translate_on
`endif
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Bus { long long s, t; }; bool cmp(Bus &a, Bus &b) { return a.t < b.t; } long long n, m, it[4 * 111111], tmp = 1, l, r; Bus bus[111111]; vector<long long> positions; void update(int idx, int l, int r, int pos, long long val) { if (pos < l || pos > r) return; if (l == r) { it[idx] = val; return; } int m = (l + r) / 2; update(2 * idx, l, m, pos, val); update(2 * idx + 1, m + 1, r, pos, val); it[idx] = (it[2 * idx] + it[2 * idx + 1]) % 1000000007; } long long get(int idx, int l, int r, int u, int v) { if (v < l || r < u) return 0; if (u <= l && r <= v) return it[idx]; int m = (l + r) / 2; long long ret = (get(2 * idx, l, m, u, v) + get(2 * idx + 1, m + 1, r, u, v)) % 1000000007; return ret; } int main() { cin >> n >> m; for (int i = 0; i < m; i++) cin >> bus[i].s >> bus[i].t; sort(bus, bus + m, cmp); positions.push_back(0); for (int i = 0; i < m; i++) if (bus[i].t != positions[positions.size() - 1]) positions.push_back(bus[i].t); if (n != positions[positions.size() - 1]) positions.push_back(n); update(1, 0, positions.size() - 1, 0, 1); for (int i = 0; i < m; i++) { l = lower_bound(positions.begin(), positions.end(), bus[i].s) - positions.begin(); r = upper_bound(positions.begin(), positions.end(), bus[i].t) - positions.begin() - 1; tmp = get(1, 0, positions.size() - 1, l, r); update(1, 0, positions.size() - 1, r, tmp); } cout << get(1, 0, positions.size() - 1, positions.size() - 1, positions.size() - 1); }
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100000 + 2; const int MAX_M = 100000 + 2; int weight[MAX_N]; struct Edge { int v, x; } E[MAX_M * 10]; int tot; template <int N> struct AdjList { int l[N]; inline void addEdge(int u, int v) { E[tot] = (Edge){v, l[u]}; l[u] = tot++; } void init() { memset(l, -1, sizeof l); } }; AdjList<MAX_N> adj; namespace BCC { const int N = MAX_N; const int M = MAX_M; set<int> p2c[N]; set<pair<int, int> > c2e[N]; map<pair<int, int>, int> e2c; pair<int, int> S[M], tmp; int cut[N], dep[N], low[N], ori[N + N]; int *l; Edge *E; int n, bcc_cnt, top; void dfs(int u, int D, int ind); void Pop(pair<int, int> y); int rebuild(AdjList<N + N> &adj); void init(int _n, int *_l, Edge *_E) { n = _n; l = _l; E = _E; for (int i = 0; i < n; i++) dep[i] = cut[i] = -1; for (int i = 0; i < n; i++) p2c[i].clear(), c2e[i].clear(); e2c.clear(); bcc_cnt = top = 0; for (int i = 0; i < n; i++) if (dep[i] == -1) { dfs(i, 0, -1); } } void dfs(int u, int D, int ind) { dep[u] = low[u] = D; int child = 0; for (int i = l[u]; ~i; i = E[i].x) { if (ind == (i ^ 1)) continue; int v = E[i].v; S[top++] = {u, v}; if (dep[v] >= 0) { if (dep[v] > dep[u]) top--; low[u] = min(low[u], dep[v]); continue; } child++; dfs(v, D + 1, i); low[u] = min(low[u], low[v]); if (low[v] >= dep[u]) { cut[u] = 1; Pop(pair<int, int>(u, v)); } } if (child == 1 && ind < 0) cut[u] = -1; } void Pop(pair<int, int> y) { do { tmp = S[--top]; p2c[tmp.first].insert(bcc_cnt); p2c[tmp.second].insert(bcc_cnt); if (tmp.first > tmp.second) swap(tmp.first, tmp.second); c2e[bcc_cnt].insert(tmp); e2c[tmp] = bcc_cnt; } while (top && S[top] != y); bcc_cnt++; } int rebuild(AdjList<N + N> &adj) { int c = bcc_cnt; for (int i = 0; i < n; i++) if (cut[i] != -1) { cut[i] = c++; ori[c - 1] = i; } adj.init(); set<int>::iterator it; for (int u = 0; u < n; u++) { if (cut[u] == -1) continue; for (it = p2c[u].begin(); it != p2c[u].end(); it++) { adj.addEdge(cut[u], *it); adj.addEdge(*it, cut[u]); } } return c; } }; // namespace BCC namespace Solve { const int N = MAX_N + MAX_N; const int inf = 1e9; AdjList<N> adj2; multiset<int> value[N]; int n, m; int dep[N], top[N], fa[N], heavy[N], siz[N]; int ID[N]; int *l; Edge *E; void Label(int u, int anc); void dfs(int u); int query(int a, int b); struct segTree { int Min[N << 1]; inline int getID(int l, int r) { return l + r | l != r; } void up(int l, int r) { int mid = l + r >> 1; Min[getID(l, r)] = min(Min[getID(l, mid)], Min[getID(mid + 1, r)]); } void build(int l, int r) { int o = getID(l, r); if (l == r) { if (value[l].empty()) { puts( empty bug ); Min[o] = inf; } else { Min[o] = *value[l].begin(); } } else { int mid = l + r >> 1; build(l, mid); build(mid + 1, r); up(l, r); } } void update(int l, int r, int ql, int preValue, int nowValue) { if (l == r) { auto it = value[l].lower_bound(preValue); if (it == value[l].end()) { puts( delete bug ); return; } value[l].erase(it); value[l].insert(nowValue); Min[getID(l, r)] = *value[l].begin(); } else { int mid = l + r >> 1; if (ql <= mid) update(l, mid, ql, preValue, nowValue); else update(mid + 1, r, ql, preValue, nowValue); up(l, r); } } int getMin(int l, int r, int ql, int qr) { if (ql <= l && r <= qr) { return Min[getID(l, r)]; } int mid = l + r >> 1; if (qr <= mid) return getMin(l, mid, ql, qr); if (ql > mid) return getMin(mid + 1, r, ql, qr); return min(getMin(l, mid, ql, qr), getMin(mid + 1, r, ql, qr)); } } segs; void dfs(int u) { siz[u] = 1; heavy[u] = -1; for (int i = l[u], v; ~i; i = E[i].x) { v = E[i].v; if (fa[u] != v) { dep[v] = dep[u] + 1; fa[v] = u; dfs(v); siz[u] += siz[v]; if (heavy[u] == -1 || siz[heavy[u]] < siz[v]) { heavy[u] = v; } } } } void Label(int u, int anc) { ID[u] = m++; top[u] = anc; if (~heavy[u]) Label(heavy[u], anc); for (int i = l[u], v; ~i; i = E[i].x) { v = E[i].v; if (v != fa[u] && v != heavy[u]) { Label(v, v); } } } int query(int a, int b) { int ret = inf; while (top[a] != top[b]) { if (dep[top[a]] < dep[top[b]]) { swap(a, b); } ret = min(ret, segs.getMin(0, m - 1, ID[top[a]], ID[a])); a = fa[top[a]]; } if (dep[a] < dep[b]) { swap(a, b); } ret = min(ret, segs.getMin(0, m - 1, ID[b], ID[a])); if (b < BCC::bcc_cnt && fa[b] != -1) { ret = min(ret, weight[BCC::ori[fa[b]]]); } return ret; } void init(int _n, Edge *_E, int _m) { n = _n; for (int u = 0; u < n; u++) value[u].clear(); l = adj2.l; E = _E; dep[0] = -1; fa[0] = -1; m = 0; dfs(0); Label(0, 0); for (int u = 0; u < _m; u++) { if (BCC::cut[u] == -1) { value[ID[*BCC::p2c[u].begin()]].insert(weight[u]); } else { value[ID[BCC::cut[u]]].insert(weight[u]); value[ID[fa[BCC::cut[u]]]].insert(weight[u]); } } segs.build(0, m - 1); } void modify(int u, int pre, int now) { if (u >= BCC::bcc_cnt && fa[u] != -1) { modify(fa[u], pre, now); } segs.update(0, m - 1, ID[u], pre, now); } void gao(int q) { char op; int a, b, w, x, y; while (q--) { scanf( %c %d %d , &op, &a, &b); if (op == C ) { a--; x = BCC::cut[a]; if (x == -1) { if (BCC::p2c[a].size() != 1) { puts( build bug ); } x = *BCC::p2c[a].begin(); } modify(x, weight[a], b); weight[a] = b; } else { a--; b--; if (a == b) { printf( %d n , weight[a]); continue; } x = BCC::cut[a]; y = BCC::cut[b]; if (x == -1) { if (BCC::p2c[a].size() != 1) { puts( build bug ); } x = *BCC::p2c[a].begin(); } if (y == -1) { if (BCC::p2c[b].size() != 1) { puts( build bug ); } y = *BCC::p2c[b].begin(); } printf( %d n , query(x, y)); } } } }; // namespace Solve int main() { int n, m, q, u, v, w; scanf( %d%d%d , &n, &m, &q); for (int i = 0; i < n; i++) { scanf( %d , weight + i); } tot = 0; adj.init(); for (int i = 0; i < m; i++) { scanf( %d%d , &u, &v); u--; v--; adj.addEdge(u, v); adj.addEdge(v, u); } BCC::init(n, adj.l, E); int bcc_cnt = BCC::rebuild(Solve::adj2); Solve::init(bcc_cnt, E, n); Solve::gao(q); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_SYMBOL_V
`define SKY130_FD_SC_LP__BUSDRIVER2_SYMBOL_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdriver2 (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_SYMBOL_V
|
module memtest00(clk, setA, setB, y);
input clk, setA, setB;
output y;
reg mem [1:0];
always @(posedge clk) begin
if (setA) mem[0] <= 0; // this is line 9
if (setB) mem[0] <= 1; // this is line 10
end
assign y = mem[0];
endmodule
// ----------------------------------------------------------
module memtest01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
input clk, wr_en;
input [3:0] wr_addr, rd_addr;
input [7:0] wr_value;
output reg [7:0] rd_value;
reg [7:0] data [15:0];
always @(posedge clk)
if (wr_en)
data[wr_addr] <= wr_value;
always @(posedge clk)
rd_value <= data[rd_addr];
endmodule
// ----------------------------------------------------------
module memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
input clk, setA, setB;
input [1:0] addr;
input [2:0] bit;
output reg y1, y2;
output y3, y4;
reg [7:0] mem1 [3:0];
(* mem2reg *)
reg [7:0] mem2 [3:0];
always @(posedge clk) begin
if (setA) begin
mem1[0] <= 10;
mem1[1] <= 20;
mem1[2] <= 30;
mem2[0] <= 17;
mem2[1] <= 27;
mem2[2] <= 37;
end
if (setB) begin
mem1[0] <= 1;
mem1[1] <= 2;
mem1[2] <= 3;
mem2[0] <= 71;
mem2[1] <= 72;
mem2[2] <= 73;
end
y1 <= mem1[addr][bit];
y2 <= mem2[addr][bit];
end
assign y3 = mem1[addr][bit];
assign y4 = mem2[addr][bit];
endmodule
// ----------------------------------------------------------
module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
input clk, wr_enable;
input [3:0] wr_addr, wr_data, rd_addr;
output reg [3:0] rd_data;
reg [3:0] memory [0:15];
always @(posedge clk) begin
if (wr_enable)
memory[wr_addr] <= wr_data;
rd_data <= memory[rd_addr];
end
endmodule
// ----------------------------------------------------------
module memtest04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
input clk, wr_enable;
input [3:0] wr_addr, wr_data, rd_addr;
output [3:0] rd_data;
reg rd_addr_buf;
reg [3:0] memory [0:15];
always @(posedge clk) begin
if (wr_enable)
memory[wr_addr] <= wr_data;
rd_addr_buf <= rd_addr;
end
assign rd_data = memory[rd_addr_buf];
endmodule
// ----------------------------------------------------------
module memtest05(clk, addr, wdata, rdata, wen);
input clk;
input [1:0] addr;
input [7:0] wdata;
output reg [7:0] rdata;
input [3:0] wen;
reg [7:0] mem [0:3];
integer i;
always @(posedge clk) begin
for (i = 0; i < 4; i = i+1)
if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];
rdata <= mem[addr];
end
endmodule
// ----------------------------------------------------------
module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
(* gentb_constant=0 *) wire rst;
reg [7:0] test [0:7];
integer i;
always @(posedge clk) begin
if (rst) begin
for (i=0; i<8; i=i+1)
test[i] <= 0;
end else begin
test[0][2] <= din[1];
test[0][5] <= test[0][2];
test[idx][3] <= din[idx];
test[idx][6] <= test[idx][2];
test[idx][idx] <= !test[idx][idx];
end
end
assign dout = test[idx];
endmodule
module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
(* gentb_constant=0 *) wire rst;
reg [7:0] test [0:7];
integer i;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (i=0; i<8; i=i+1)
test[i] <= 0;
end else begin
test[0][2] <= din[1];
test[0][5] <= test[0][2];
test[idx][3] <= din[idx];
test[idx][6] <= test[idx][2];
test[idx][idx] <= !test[idx][idx];
end
end
assign dout = test[idx];
endmodule
// ----------------------------------------------------------
module memtest07(clk, addr, woffset, wdata, rdata);
input clk;
input [1:0] addr;
input [3:0] wdata;
input [1:0] woffset;
output reg [7:0] rdata;
reg [7:0] mem [0:3];
integer i;
always @(posedge clk) begin
mem[addr][woffset +: 4] <= wdata;
rdata <= mem[addr];
end
endmodule
// ----------------------------------------------------------
module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y);
reg [3:0] mem [0:15] [0:15];
always @(posedge clk) begin
y <= mem[a][b];
mem[a][b] <= c;
end
endmodule
// ----------------------------------------------------------
module memtest09 (
input clk,
input [3:0] a_addr, a_din, b_addr, b_din,
input a_wen, b_wen,
output reg [3:0] a_dout, b_dout
);
reg [3:0] memory [10:35];
always @(posedge clk) begin
if (a_wen)
memory[10 + a_addr] <= a_din;
a_dout <= memory[10 + a_addr];
end
always @(posedge clk) begin
if (b_wen && (10 + a_addr != 20 + b_addr || !a_wen))
memory[20 + b_addr] <= b_din;
b_dout <= memory[20 + b_addr];
end
endmodule
// ----------------------------------------------------------
module memtest10(input clk, input [5:0] din, output [5:0] dout);
reg [5:0] queue [0:3];
integer i;
always @(posedge clk) begin
queue[0] <= din;
for (i = 1; i < 4; i=i+1) begin
queue[i] <= queue[i-1];
end
end
assign dout = queue[3];
endmodule
// ----------------------------------------------------------
module memtest11(clk, wen, waddr, raddr, wdata, rdata);
input clk, wen;
input [1:0] waddr, raddr;
input [7:0] wdata;
output [7:0] rdata;
reg [7:0] mem [3:0];
assign rdata = mem[raddr];
always @(posedge clk) begin
if (wen)
mem[waddr] <= wdata;
else
mem[waddr] <= mem[waddr];
end
endmodule
// ----------------------------------------------------------
module memtest12 (
input clk,
input [1:0] adr,
input [1:0] din,
output reg [1:0] q
);
reg [1:0] ram [3:0];
always@(posedge clk)
{ram[adr], q} <= {din, ram[adr]};
endmodule
// ----------------------------------------------------------
module memtest13 (
input clk, rst,
input [1:0] a1, a2, a3, a4, a5, a6,
input [3:0] off1, off2,
input [31:5] din1,
input [3:0] din2, din3,
output reg [3:0] dout1, dout2,
output reg [31:5] dout3
);
reg [31:5] mem [0:3];
always @(posedge clk) begin
if (rst) begin
mem[0] <= 0;
mem[1] <= 0;
mem[2] <= 0;
mem[3] <= 0;
end else begin
mem[a1] <= din1;
mem[a2][14:11] <= din2;
mem[a3][5 + off1 +: 4] <= din3;
dout1 <= mem[a4][12:9];
dout2 <= mem[a5][5 + off2 +: 4];
dout3 <= mem[a6];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFBBP_BLACKBOX_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBP_BLACKBOX_V
|
//
// Copyright (c) 2002 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Synth of basic latch form
//
//
module basiclatch ( clk, d, q);
input clk, d;
output q;
reg q;
always @ (clk or d)
if(~clk)
q = d;
endmodule
module tbench ;
reg clk, d;
basiclatch u_reg (clk,d,q);
initial
begin
clk = 0;
d = 0;
#1 ;
if(q !== 0)
begin
$display("FAILED - initial value not 0");
$finish;
end
#1 ;
clk = 1;
# 1;
d = 1;
# 1;
if(q !== 0)
begin
$display("FAILED - Didn't latch initial 0");
$finish;
end
#1
clk = 0;
# 1;
if(q !== 1)
begin
$display("FAILED - Didn't pass 1 after latch dropped");
$finish;
end
#1
clk = 1;
# 1;
d = 0;
# 1;
if(q !== 1)
begin
$display("FAILED - Didn't latch 1 after latch dropped");
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct ty { int d[4][11], a; } t[400005], ans; int n, m, q, x, y, a[11][100005], co[42], col, fa1, fa2, fa[42]; int find(int x) { if (x == fa[x]) return x; return fa[x] = find(fa[x]); } ty update(ty x, ty y) { ty z; for (int i = 1; i <= n; i++) { fa[x.d[3][i]] = x.d[3][i]; fa[x.d[2][i]] = x.d[2][i]; fa[y.d[2][i] + 20] = y.d[2][i] + 20; fa[y.d[3][i] + 20] = y.d[3][i] + 20; } z.a = x.a + y.a; int col = 0; memset(co, 0, sizeof(co)); for (int i = 1; i <= n; i++) if (x.d[1][i] == y.d[0][i]) { fa1 = find(x.d[3][i]); fa2 = find(y.d[2][i] + 20); if (fa1 != fa2) { z.a--; fa[fa2] = fa1; } } for (int i = 1; i <= n; i++) { z.d[0][i] = x.d[0][i]; z.d[1][i] = y.d[1][i]; fa1 = find(x.d[2][i]); if (!co[fa1]) co[fa1] = ++col; z.d[2][i] = co[fa1]; fa1 = find(y.d[3][i] + 20); if (!co[fa1]) co[fa1] = ++col; z.d[3][i] = co[fa1]; } return z; } void build(int o, int l, int r) { if (l == r) { t[o].a = 0; int col = 0; for (int i = 1; i <= n; i++) { t[o].d[0][i] = t[o].d[1][i] = a[i][l]; if (a[i][l] != a[i - 1][l]) { t[o].a++; col++; } t[o].d[2][i] = t[o].d[3][i] = col; } return; } int mid = (l + r) >> 1; build(o * 2, l, mid); build(o * 2 + 1, mid + 1, r); t[o] = update(t[o * 2], t[o * 2 + 1]); } ty find(int o, int l, int r, int L, int R) { if (l == L && r == R) return t[o]; int mid = (l + r) >> 1; if (R <= mid) return find(o * 2, l, mid, L, R); else if (L > mid) return find(o * 2 + 1, mid + 1, r, L, R); else return update(find(o * 2, l, mid, L, mid), find(o * 2 + 1, mid + 1, r, mid + 1, R)); } int main() { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= n; i++) for (int r = 1; r <= m; r++) scanf( %d , &a[i][r]); build(1, 1, m); for (int i = 1; i <= q; i++) { scanf( %d%d , &x, &y); ans = find(1, 1, m, x, y); printf( %d n , ans.a); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; vector<string> N(a), M(b); for (auto& i : N) cin >> i; for (auto& i : M) cin >> i; int q; cin >> q; while (q--) { int n; cin >> n; cout << N[(n - 1) % a] << M[(n - 1) % b] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int G = 2520; const int B = 41; const int MAXN = B * G; unsigned char S[G][B], ps[B + 1][G][4], mp[256]; string e; void Pre() { mp[ A ] = 0; mp[ G ] = 1; mp[ T ] = 2; mp[ C ] = 3; } void build(int g) { for (int i = 0; i < 4; i++) { ps[0][g][i] = 0; for (int j = 0; j < B; j++) ps[j + 1][g][i] = ps[j][g][i] + (S[g][j] == i); } } void chng(int p, char c) { S[p % G][p / G] = c; build(p % G); } inline int nxt(int x, int y) { if (x % G <= y) return (x + (y - x % G)) / G; else return (x + (G + y - x % G)) / G; } inline int get(int g, int l, int r, int x) { return ps[r][g][x] - ps[l][g][x]; } int t(int i) { return e[i % e.size()]; } int main() { ios::sync_with_stdio(false); cin.tie(0); Pre(); string s; cin >> s; for (int i = 0; i < s.size(); i++) S[i % G][i / G] = mp[s[i]]; for (int i = 0; i < G; i++) build(i); int q; cin >> q; while (q--) { int type; cin >> type; if (type == 1) { int x; char c; cin >> x >> c; x--; chng(x, mp[c]); } else { int l, r; cin >> l >> r >> e; l--; int ans = 0; for (int i = 0; i < G; i++) { ans += get(i, nxt(l, i), nxt(r, i), mp[t((i - l % G + G) % G)]); } cout << ans << endl; } } }
|
#include <bits/stdc++.h> using namespace std; long long power(long long x, long long y, long long p); inline int D() { int t; scanf( %d , &t); return t; } inline long long llD() { long long t; scanf( %lld , &t); return t; } const int N = 1e6 + 5; long long arr[N], cost[N]; int main() { long long n = llD(), k = llD(), l = 1, r = 0, mid = -1; for (int i = 0; i < n; ++i) r += pow(2, i); while (mid != k) { mid = (l + r) / 2; if (mid > k) r = mid - 1, --n; else if (mid < k) l = mid + 1, --n; } printf( %lld , n); } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; }
|
`timescale 1ns/10ps
`include "pipeconnect.h"
module dc_ctrl(input wire clk,
input wire rst,
input wire `REQ dc_ctrl_req,
output wire `RES dc_ctrl_res);
parameter debug = 0;
wire [31:0] addr, q;
reg r_ = 0;
always @(posedge clk) r_ <= rst ? 1'b0 : dc_ctrl_req`R;
assign addr = dc_ctrl_req`A;
assign dc_ctrl_res`RD = r_ ? q : 0;
assign dc_ctrl_res`HOLD = 0;
dcache dc(.clock (clk),
.clken (1),
.address(addr[12:2]),
.wren (dc_ctrl_req`W),
.data (dc_ctrl_req`WD),
.byteena(dc_ctrl_req`WBE),
.q (q));
`ifdef SIMULATE_MAIN
pipechecker check("dc_ctrl", clk, dc_ctrl_req, dc_ctrl_res);
// Debugging
always @(posedge clk) if (debug) begin
if (dc_ctrl_res`HOLD)
$display("%5d D$: Stall x_load %d x_store %d m_stall %d opcode %2x",
$time, dc_ctrl_req`R, dc_ctrl_req`W);
else begin
if (dc_ctrl_req`R)
$display("%5d D$: load [%x]", $time, dc_ctrl_req`A);
if (r_)
$display("%5d D$: load -> %x", $time, dc_ctrl_res`RD);
if (dc_ctrl_req`W)
$display("%5d D$: store %x->[%x] (bytena %x)",
$time, dc_ctrl_req`WD, addr, dc_ctrl_req`WBE);
end
end
`endif
endmodule
|
// Copyright (c) 2013, Simon Que
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
// A dual-port multiplexed SPI bus interface.
module SPIBus(
// Primary SPI bus.
input main_nss,
input main_sck,
input main_mosi,
output main_miso,
// Secondary SPI bus.
input alt_nss,
input alt_sck,
input alt_mosi,
output alt_miso,
// Output SPI bus.
output reg nss,
output reg sck,
output reg mosi,
input miso
);
// Each bus is granted access when its select is asserted and the other bus'
// select is not asserted.
wire alt_bus_enabled = (alt_nss == 'b0) & (main_nss == 'b1);
wire main_bus_enabled = (alt_nss == 'b1) & (main_nss == 'b0);
// Multiplex the two SPI buses.
// nSS should be allowed to assert only if only one bus is asserting it.
// This avoids undefined behavior when the main bus interrupts the secondary
// bus.
always @ (*) begin
if (alt_bus_enabled) begin
nss <= 'b0;
sck <= alt_sck;
mosi <= alt_mosi;
end else if (main_bus_enabled) begin
nss <= 'b0;
sck <= main_sck;
mosi <= main_mosi;
end else begin
nss <= 'b1;
sck <= 0;
mosi <= 0;
end
end
assign main_miso = (main_nss == 'b0) ? miso : 'bz;
assign alt_miso = (alt_nss == 'b0) ? miso : 'bz;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_datamem #(
parameter cache_depth = 13,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output reg busy,
/* from fragment FIFO */
input frag_pipe_stb_i,
output reg frag_pipe_ack_o,
input [fml_depth-1-1:0] frag_dadr,
input [cache_depth-1:0] frag_tadra, /* < texel cache addresses (in bytes) */
input [cache_depth-1:0] frag_tadrb,
input [cache_depth-1:0] frag_tadrc,
input [cache_depth-1:0] frag_tadrd,
input [5:0] frag_x_frac,
input [5:0] frag_y_frac,
input frag_miss_a,
input frag_miss_b,
input frag_miss_c,
input frag_miss_d,
/* from fetch unit */
input fetch_pipe_stb_i,
output reg fetch_pipe_ack_o,
input [255:0] fetch_dat,
/* to downstream pipeline */
output reg pipe_stb_o,
input pipe_ack_i,
output reg [fml_depth-1-1:0] dadr_f, /* in 16-bit words */
output [15:0] tcolora,
output [15:0] tcolorb,
output [15:0] tcolorc,
output [15:0] tcolord,
output reg [5:0] x_frac_f,
output reg [5:0] y_frac_f
);
reg req_ce;
reg req_valid;
reg [cache_depth-1:0] frag_tadra_r;
reg [cache_depth-1:0] frag_tadrb_r;
reg [cache_depth-1:0] frag_tadrc_r;
reg [cache_depth-1:0] frag_tadrd_r;
reg frag_miss_a_r;
reg frag_miss_b_r;
reg frag_miss_c_r;
reg frag_miss_d_r;
always @(posedge sys_clk) begin
if(req_ce) begin
req_valid <= frag_pipe_stb_i;
frag_tadra_r <= frag_tadra;
frag_tadrb_r <= frag_tadrb;
frag_tadrc_r <= frag_tadrc;
frag_tadrd_r <= frag_tadrd;
frag_miss_a_r <= frag_miss_a;
frag_miss_b_r <= frag_miss_b;
frag_miss_c_r <= frag_miss_c;
frag_miss_d_r <= frag_miss_d;
dadr_f <= frag_dadr;
x_frac_f <= frag_x_frac;
y_frac_f <= frag_y_frac;
end
end
reg retry;
wire [cache_depth-1:0] adra = retry ? frag_tadra_r : frag_tadra;
wire [cache_depth-1:0] adrb = retry ? frag_tadrb_r : frag_tadrb;
wire [cache_depth-1:0] adrc = retry ? frag_tadrc_r : frag_tadrc;
wire [cache_depth-1:0] adrd = retry ? frag_tadrd_r : frag_tadrd;
reg [1:0] wa_sel;
reg [cache_depth-1:0] wa;
always @(*) begin
case(wa_sel)
2'd0: wa = frag_tadra_r;
2'd1: wa = frag_tadrb_r;
2'd2: wa = frag_tadrc_r;
default: wa = frag_tadrd_r;
endcase
end
reg we;
tmu2_qpram #(
.depth(cache_depth)
) qpram (
.sys_clk(sys_clk),
.raa(adra),
.rda(tcolora),
.rab(adrb),
.rdb(tcolorb),
.rac(adrc),
.rdc(tcolorc),
.rad(adrd),
.rdd(tcolord),
.we(we),
.wa(wa),
.wd(fetch_dat)
);
reg [3:0] missmask;
reg missmask_init;
reg missmask_we;
always @(posedge sys_clk) begin
if(missmask_init) begin
missmask <= 4'b1111;
if(missmask_we) begin
case(wa_sel)
2'd0: missmask <= 4'b1110;
2'd1: missmask <= 4'b1101;
2'd2: missmask <= 4'b1011;
default: missmask <= 4'b0111;
endcase
end
end else if(missmask_we) begin
case(wa_sel)
2'd0: missmask <= missmask & 4'b1110;
2'd1: missmask <= missmask & 4'b1101;
2'd2: missmask <= missmask & 4'b1011;
default: missmask <= missmask & 4'b0111;
endcase
end
end
reg [1:0] state;
reg [1:0] next_state;
parameter RUNNING = 2'd0;
parameter COMMIT = 2'd1;
parameter STROBE = 2'd2;
always @(posedge sys_clk) begin
if(sys_rst)
state <= RUNNING;
else
state <= next_state;
end
always @(*) begin
next_state = state;
busy = 1'b0;
frag_pipe_ack_o = 1'b0;
fetch_pipe_ack_o = 1'b0;
pipe_stb_o = 1'b0;
req_ce = 1'b0;
retry = 1'b0;
wa_sel = 2'd0;
we = 1'b0;
missmask_init = 1'b0;
missmask_we = 1'b0;
case(state)
RUNNING: begin
frag_pipe_ack_o = 1'b1;
req_ce = 1'b1;
missmask_init = 1'b1;
if(req_valid) begin
busy = 1'b1;
pipe_stb_o = 1'b1;
if(frag_miss_a_r | frag_miss_b_r | frag_miss_c_r | frag_miss_d_r) begin
frag_pipe_ack_o = 1'b0;
req_ce = 1'b0;
pipe_stb_o = 1'b0;
fetch_pipe_ack_o = 1'b1;
if(fetch_pipe_stb_i) begin
if(frag_miss_a_r)
wa_sel = 2'd0;
else if(frag_miss_b_r)
wa_sel = 2'd1;
else if(frag_miss_c_r)
wa_sel = 2'd2;
else
wa_sel = 2'd3;
missmask_we = 1'b1;
we = 1'b1;
end
next_state = COMMIT;
end else if(~pipe_ack_i) begin
frag_pipe_ack_o = 1'b0;
req_ce = 1'b0;
retry = 1'b1;
end
end
end
COMMIT: begin
busy = 1'b1;
retry = 1'b1;
if((frag_miss_a_r & missmask[0]) | (frag_miss_b_r & missmask[1]) | (frag_miss_c_r & missmask[2]) | (frag_miss_d_r & missmask[3])) begin
fetch_pipe_ack_o = 1'b1;
if(fetch_pipe_stb_i) begin
if(frag_miss_a_r & missmask[0])
wa_sel = 2'd0;
else if(frag_miss_b_r & missmask[1])
wa_sel = 2'd1;
else if(frag_miss_c_r & missmask[2])
wa_sel = 2'd2;
else
wa_sel = 2'd3;
missmask_we = 1'b1;
we = 1'b1;
end
end else
next_state = STROBE;
end
STROBE: begin
busy = 1'b1;
retry = 1'b1;
pipe_stb_o = 1'b1;
if(pipe_ack_i) begin
retry = 1'b0;
req_ce = 1'b1;
frag_pipe_ack_o = 1'b1;
next_state = RUNNING;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 10, M = 2e5 + 10; struct upd { int r, s, t, id; } t; vector<upd> v[M]; struct edge { int x, y; } e[M]; int ans[M], n, m, qi, f[N][N]; signed main() { int x; scanf( %d %d %d , &n, &m, &qi); for (register int i = (1); i <= (m); ++i) scanf( %d %d , &e[i].x, &e[i].y); for (register int i = (1); i <= (qi); ++i) scanf( %d %d %d %d , &x, &t.r, &t.s, &t.t), t.id = i, v[x].push_back(t); int p = qi; memset(f, 0x3f, sizeof(f)); for (register int i = (m); i >= (1); --i) { int x = e[i].x, y = e[i].y; f[x][y] = f[y][x] = i; for (register int j = (1); j <= (n); ++j) f[x][j] = min(f[x][j], f[y][j]), f[y][j] = min(f[y][j], f[x][j]); int l = v[i].size() - 1; for (register int j = (0); j <= (l); ++j) ans[v[i][j].id] = (f[v[i][j].s][v[i][j].t] <= v[i][j].r); } for (register int i = (1); i <= (qi); ++i) printf(ans[i] ? Yes n : No n ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211A_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O211A_BEHAVIORAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire C1 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211A_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int n, n1, n2, mn, mx; int A[100001]; int main() { cin >> n >> n1 >> n2; for (int i = 0; i < n; i++) { cin >> A[i]; } sort(A, A + n); mn = min(n1, n2); mx = max(n1, n2); double s1 = 0; double s2 = 0; int nr = 0; int k = 0; for (int i = n - 1; k < mn; i--, k++) { s1 = s1 + A[i]; nr = i; } k = 0; for (int i = nr - 1; k < mx; i--, k++) { s2 = s2 + A[i]; } cout << fixed << s1 / mn + s2 / mx << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; long long int t, n, m, a[1000005] = {0}, d[1000005], b[1000005]; stack<long long int> s; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int i, j, k, x, y; cin >> n >> m; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i < n; i++) d[i] = abs(a[i + 1] - a[i]); for (i = 1; i < n; i++) { while (!s.empty() && d[s.top()] < d[i]) s.pop(); a[i] = (s.empty()) ? 0 : s.top(); s.push(i); } while (!s.empty()) s.pop(); for (i = n - 1; i >= 1; i--) { while (!s.empty() && d[s.top()] <= d[i]) s.pop(); b[i] = (s.empty()) ? n : s.top(); s.push(i); } while (m--) { long long int l, r; cin >> l >> r; long long int ans = 0; for (i = l; i < r; i++) { x = i - max(a[i], l - 1); y = min(b[i], r) - i; ans += (x * y * d[i]); } cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> inline T read() { T s = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { s = (s << 3) + (s << 1) + ch - 48; ch = getchar(); } return s * f; } template <typename T> inline void print(T x) { if (x < 0) putchar( - ), x = -x; if (x > 9) print(x / 10); putchar(x % 10 + 0 ); } const int N = 2e5 + 100; const int mod = 1e9 + 7; long long h[N], w[N], sum[N]; struct Segment { static const int maxn = 2e5 + 100; struct star { long long lsum, rsum, sum; } s[maxn << 2]; void pushup(int node, int l, int r) { int mid = l + r >> 1; s[node].lsum = max(s[node << 1].lsum, h[l] + sum[mid - 1] - sum[l - 1] + s[node << 1 | 1].lsum - h[mid + 1] + w[mid]); s[node].lsum = max(s[node].lsum, h[l] + h[mid + 1] + sum[mid] - sum[l - 1]); s[node].rsum = max(s[node << 1 | 1].rsum, h[r] + sum[r - 1] - sum[mid] + s[node << 1].rsum - h[mid] + w[mid]); s[node].rsum = max(s[node].rsum, h[r] + h[mid] + sum[r - 1] - sum[mid - 1]); s[node].sum = max(s[node << 1].rsum + s[node << 1 | 1].lsum - h[mid] - h[mid + 1] + w[mid], max(s[node << 1].sum, s[node << 1 | 1].sum)); s[node].sum = max(s[node].sum, max(s[node].lsum, s[node].rsum)); s[node].sum = max(s[node].sum, h[r] + h[l] + sum[r - 1] - sum[l - 1]); s[node].sum = max( s[node].sum, max(s[node << 1].rsum - h[mid] + h[mid + 1] + w[mid], s[node << 1 | 1].lsum - h[mid + 1] + h[mid] + w[mid])); s[node].sum = max(s[node].sum, h[mid] + h[mid + 1] + w[mid]); } void build(int node, int l, int r) { if (l == r) { s[node].lsum = s[node].rsum = h[l]; s[node].sum = 0; return; } int mid = l + r >> 1; build(node << 1, l, mid); build(node << 1 | 1, mid + 1, r); pushup(node, l, r); } star query(int node, int l, int r, int L, int R) { if (L == l && R == r) { return s[node]; } int mid = l + r >> 1; if (R <= mid) return query(node << 1, l, mid, L, R); else if (L > mid) return query(node << 1 | 1, mid + 1, r, L, R); else { star lnode = query(node << 1, l, mid, L, mid); star rnode = query(node << 1 | 1, mid + 1, r, mid + 1, R); star now; now.lsum = max(lnode.lsum, h[L] + sum[mid - 1] - sum[L - 1] + rnode.lsum - h[mid + 1] + w[mid]); now.lsum = max(now.lsum, h[L] + h[mid + 1] + sum[mid] - sum[L - 1]); now.rsum = max(rnode.rsum, h[R] + sum[R - 1] - sum[mid] + lnode.rsum - h[mid] + w[mid]); now.rsum = max(now.rsum, h[R] + h[mid] + sum[R - 1] - sum[mid - 1]); now.sum = max(lnode.rsum + rnode.lsum - h[mid] - h[mid + 1] + w[mid], max(lnode.sum, rnode.sum)); now.sum = max(now.sum, max(now.lsum, now.rsum)); now.sum = max(now.sum, h[L] + h[R] + sum[R - 1] - sum[L - 1]); now.sum = max(now.sum, max(lnode.rsum - h[mid] + h[mid + 1] + w[mid], rnode.lsum - h[mid + 1] + h[mid] + w[mid])); now.sum = max(now.sum, h[mid] + h[mid + 1] + w[mid]); return now; } } } tree; int main() { int n = read<int>(), m = read<int>(); for (int i = 1; i <= n; ++i) { w[i] = read<long long>(); w[i + n] = w[i]; sum[i] = sum[i - 1] + w[i]; } for (int i = 1; i <= n; ++i) { h[i] = read<long long>(); h[i] = h[i] + h[i]; h[i + n] = h[i]; } for (int i = n + 1; i <= n + n; ++i) { sum[i] = sum[i - 1] + w[i]; } tree.build(1, 1, n + n); for (int i = 1; i <= m; ++i) { int l = read<int>(), r = read<int>(); int lc, rc; if (r >= l) lc = r + 1, rc = l + n - 1; else lc = r + 1, rc = l - 1; printf( %lld n , tree.query(1, 1, n + n, lc, rc).sum); } }
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#include <bits/stdc++.h> using namespace std; int n, a[210], m; priority_queue<int> q; priority_queue<int, deque<int>, greater<int> > q2; int main() { while (scanf( %d%d , &n, &m) != EOF) { for (int i = 0; i < n; ++i) scanf( %d , &a[i]); int ans = a[0]; for (int i = 0; i < n; ++i) { for (int j = i; j < n; ++j) { for (int k = 0; k < n; ++k) { if (k >= i && k <= j) q2.push(a[k]); else q.push(a[k]); } for (int k = 0; k < m; ++k) { if (q.empty() || q2.empty()) break; int s = q2.top(); int l = q.top(); if (s >= l) break; q2.pop(); q.pop(); q2.push(l); q.push(s); } int sum = 0; while (!q2.empty()) { sum += q2.top(); q2.pop(); } ans = max(ans, sum); while (!q.empty()) { q.pop(); } } } printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T> inline void upmax(T& a, T b) { if (a < b) a = b; } template <class T> inline void upmin(T& a, T b) { if (a > b) a = b; } const int maxn = 307; const int maxm = 100007; const int mod = 1000000007; const int inf = 0x7fffffff; const double eps = 1e-7; typedef int arr[maxn]; typedef int adj[maxm]; inline int fcmp(double a, double b) { if (fabs(a - b) <= eps) return 0; if (a < b - eps) return -1; return 1; } inline int add(int a, int b) { return ((long long)a + b) % mod; } inline int mul(int a, int b) { return ((long long)a * b) % mod; } inline int dec(int a, int b) { return add(a, mod - b % mod); } inline int Pow(int a, int b) { int t = 1; while (b) { if (b & 1) t = mul(t, a); a = mul(a, a), b >>= 1; } return t; } template <typename Type> inline Type RD() { char c = getchar(); Type x = 0, flag = 1; while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) flag = -1; else x = c - 0 ; while (isdigit(c = getchar())) x = x * 10 + c - 0 ; return x * flag; } inline char rdch() { char c = getchar(); while (!isalpha(c)) c = getchar(); return c; } int n, m, k; double C[maxn][maxn], f[maxm]; void input() { n = RD<int>(), m = RD<int>(), k = RD<int>(); for (int i = 0, _ = n; i <= _; i++) { C[i][0] = 1; for (int j = 1, _ = i; j <= _; j++) C[i][j] = C[i - 1][j] + C[i - 1][j - 1]; } f[0] = 1; for (int i = 1, _ = k; i <= _; i++) f[i] = f[i - 1] * (k - i + 1) / (m - i + 1); } void solve() { double ans = 0; for (int i = 0, _ = n; i <= _; i++) { for (int j = 0, _ = n; j <= _; j++) { ans += C[n][i] * C[n][j] * f[(i + j) * n - i * j]; if (ans > 1e99) break; } if (ans > 1e99) break; } if (ans > 1e99) ans = 1e99; printf( %.10lf n , ans); } int main() { input(); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int Maxn = 100 * 1000 + 5; int n; vector<int> arr[Maxn]; int main() { scanf( %d , &n); int x, k; for (int i = 0; i < n; i++) { scanf( %d%d , &x, &k); arr[k - 1].push_back(x); } for (int i = 0; i < Maxn; i++) { int num = -1; for (int j = 0; j < (int)arr[i].size(); j++) { if (arr[i][j] > num + 1) { printf( NO n ); return 0; } if (arr[i][j] == num + 1) num++; } } printf( YES n ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR3_BEHAVIORAL_PP_V
|
module key_expansion(key_in, rk_delayed_out, round_cnt, rk_last_out, clk, input_sel, sbox_sel, last_out_sel, bit_out_sel, rcon_en);
input [7:0] key_in;
output [7:0] rk_delayed_out;
output [7:0] rk_last_out;
input [3:0] round_cnt;
input clk;
input input_sel, sbox_sel, last_out_sel, bit_out_sel;
input [7:0] rcon_en;
reg [7:0] r15, r14, r13, r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0, r_redun;
wire [7:0] rcon_sbox_o, sbox_o, rcon_o, sbox_in, mux_in_o, mux_bit_o, rcon_num;
function [7:0] rcon;
input [3:0] x;
casex (x)
4'b0000: rcon = 8'h01;
4'b0001: rcon = 8'h02;
4'b0010: rcon = 8'h04;
4'b0011: rcon = 8'h08;
4'b0100: rcon = 8'h10;
4'b0101: rcon = 8'h20;
4'b0110: rcon = 8'h40;
4'b0111: rcon = 8'h80;
4'b1000: rcon = 8'h1b;
4'b1001: rcon = 8'h36;
default: rcon = 8'h01;
endcase
endfunction
assign rcon_num = rcon(round_cnt);
assign rcon_sbox_o = sbox_o ^ rcon_o;
assign rcon_o = rcon_en & rcon_num;
assign rk_delayed_out = r12;
mux2_1 mux_in (rk_last_out, key_in, mux_in_o, input_sel);
mux2_1 mux_sbox (r13, r_redun, sbox_in, sbox_sel);
mux2_1 mux_bit ((r4 ^ rk_last_out), r4, mux_bit_o, bit_out_sel);
mux2_1 mux_last_out (r0, ( r0 ^ rcon_sbox_o), rk_last_out, last_out_sel);
bSbox sbox (sbox_in, sbox_o);
always @ (posedge clk)
begin
r15 <= mux_in_o;
r14 <= r15;
r13 <= r14;
r12 <= r13;
r11 <= r12;
r10 <= r11;
r9 <= r10;
r8 <= r9;
r7 <= r8;
r6 <= r7;
r5 <= r6;
r4 <= r5;
r3 <= mux_bit_o;
r2 <= r3;
r1 <= r2;
r0 <= r1;
end
always @ (posedge clk)
begin
if (rcon_en == 8'hff)
begin
r_redun <= r12;
end
end
endmodule
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#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } const long long N = 2e5 + 10; const long long mod = 1e9 + 7; struct Trie { Trie *child[2]; long long cnt; }; Trie *createNode() { Trie *node = (Trie *)malloc(sizeof(Trie)); memset(node->child, NULL, sizeof node->child); node->cnt = 0; return node; } void insert(Trie *root, long long x) { for (long long i = 30; i >= 0; --i) { long long val = (1LL << i); long long bit = 0; if (val & x) bit = 1; if (!root->child[bit]) root->child[bit] = createNode(); root = root->child[bit]; root->cnt++; } } void erase(Trie *root, long long x) { for (long long i = 30; i >= 0; --i) { long long val = (1LL << i); long long bit = 0; if (val & x) bit = 1; if (!root->child[bit]) root->child[bit] = createNode(); root = root->child[bit]; root->cnt--; } } long long query(Trie *root, long long x) { long long ans = 0; for (long long i = 30; i >= 0; --i) { long long val = (1 << i); long long bit = 0; if (val & x) bit = 1; if (root->child[bit] && root->child[bit]->cnt > 0) { root = root->child[bit]; } else { assert(root->child[bit ^ 1] && root->child[bit ^ 1]->cnt > 0); ans += val; root = root->child[bit ^ 1]; } } return ans; } void solve() { long long n; cin >> n; long long a[n], b[n]; for (long long i = 0; i < n; ++i) cin >> a[i]; for (long long i = 0; i < n; ++i) cin >> b[i]; Trie *root = createNode(); for (long long i = 0; i < n; ++i) { insert(root, b[i]); } vector<long long> ans; for (long long i = 0; i < n; ++i) { long long x = query(root, a[i]); ans.push_back(x); erase(root, a[i] ^ x); } for (long long i = 0; i < n; ++i) cout << ans[i] << ; cout << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(NULL); ; long long t = 1; while (t--) solve(); }
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#include <bits/stdc++.h> using namespace std; inline char gc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } inline long long read() { long long x = 0; char ch = getchar(); bool positive = 1; for (; !isdigit(ch); ch = getchar()) if (ch == - ) positive = 0; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return positive ? x : -x; } inline void write(long long a) { if (a < 0) { a = -a; putchar( - ); } if (a >= 10) write(a / 10); putchar( 0 + a % 10); } inline void writeln(long long a) { write(a); puts( ); } inline void wri(long long a) { write(a); putchar( ); } long long t, n, nl[100010], ml[100010], nll[100010], mll[100010]; int main() { n = read(); for (int i = 1; i <= n; i++) { nl[i] = read(); } for (int i = 1; i <= n; i++) { ml[i] = read(); } for (int i = 1; i < n; i++) { nll[i] = nl[i + 1] - nl[i]; mll[i] = ml[i + 1] - ml[i]; } sort(nll + 1, nll + n); sort(mll + 1, mll + n); int pd = 0; for (int i = 1; i < n; i++) { if (nll[i] != mll[i]) pd = 1; } if (pd == 0 && nl[1] == ml[1] && nl[n] == ml[n]) { puts( Yes ); } else { puts( No ); } return 0; }
|
`ifndef _alu
`define _alu
module alu(
input [3:0] ctl,
input [31:0] a, b,
output reg [31:0] out,
output zero);
wire [31:0] sub_ab;
wire [31:0] add_ab;
wire oflow_add;
wire oflow_sub;
wire oflow;
wire slt;
assign zero = (0 == out);
assign sub_ab = a - b;
assign add_ab = a + b;
// overflow occurs (with 2's complement numbers) when
// the operands have the same sign, but the sign of the result is
// different. The actual sign is the opposite of the result.
// It is also dependent on wheter addition or subtraction is performed.
assign oflow_add = (a[31] == b[31] && add_ab[31] != a[31]) ? 1 : 0;
assign oflow_sub = (a[31] == b[31] && sub_ab[31] != a[31]) ? 1 : 0;
assign oflow = (ctl == 4'b0010) ? oflow_add : oflow_sub;
// set if less than, 2s compliment 32-bit numbers
assign slt = oflow_sub ? ~(a[31]) : a[31];
always @(*) begin
case (ctl)
4'b0010: out <= add_ab; // a + b
4'b0000: out <= a & b; // and
4'b1100: out <= ~(a | b); // nor
4'b0001: out <= a | b; // or
4'b0111: out <= {{31{1'b0}}, slt}; // set if less than
4'b0110: out <= sub_ab; // a - b
4'b1101: out <= a ^ b; // xor
default: out <= 0;
endcase
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5, MOD = 1e9 + 7; long long k, p, q; string ans; set<long long> s; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> k; if (k < 25) { cout << -1 << endl; return 0; } char str[5] = { a , e , i , o , u }; for (long long i = 1; i * i <= k; i++) { if (k % i == 0) { if (i >= 5 && k / i >= 5) { p = i; q = k / i; break; } } } if (p == 0 && q == 0) { cout << -1 << endl; return 0; } for (long long i = 0; i < p; i++) { for (long long j = 0; j < q; j++) cout << str[(i + j) % 5]; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mxn = 105; const long long mxm = 1; const long long INF = 0x3f3f3f3f; const long long mod = 1e9 + 7; const double eps = 1e-7; long long a[mxn]; signed main(void) { long long q; cin >> q; while (q--) { long long n; cin >> n; long long ct1 = 0, ct2 = 0, ct0 = 0, ans = 0; for (long long i = 1; i <= n; i++) { cin >> a[i]; a[i] = a[i] % 3; if (a[i] == 1) ct1++; if (a[i] == 2) ct2++; if (a[i] == 0) ct0++; } ans = ct0; if (ct1 >= ct2) { ans += ct2; ct1 -= ct2; ans += ct1 / 3; } else { ans += ct1; ct2 -= ct1; ans += ct2 / 3; } cout << ans << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A41OI_FUNCTIONAL_PP_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41OI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e9 + 5; long long n, k; bool valid(long long x) { long long maxi = (x)*k - ((x - 1) * ((x + 2) / 2.0)); if (maxi >= n) return true; else return false; } long long binary() { long long lo = 0, mid, hi = k; while (hi - lo > 0) { mid = (hi + lo) / 2; if (valid(mid)) hi = mid; else lo = mid + 1; } if (hi == lo) return lo; else return -1; } int main() { scanf( %I64d %I64d , &n, &k); long long ans = binary(); long long maxi = k; maxi += (ans - 1) * k - ((ans - 1) * ((ans + 2) / 2)); if (ans & 1 && ans != 1) maxi--; if (maxi >= n) printf( %I64d , ans); else printf( -1 ); return 0; }
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Debounce_Index.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Debounce_Index
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Debounce_Index
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Debounce_Index
(
CLK_IN,
reset,
enb,
In,
Out
);
input CLK_IN;
input reset;
input enb;
input In;
output Out;
wire [7:0] Debouce_Count_out1; // uint8
wire Count_Up_Down_out1;
// <S5>/Debouce_Count
assign Debouce_Count_out1 = 8'd25;
// <S5>/Count_Up_Down
Count_Up_Down u_Count_Up_Down (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.u(In),
.count_debounce(Debouce_Count_out1), // uint8
.y(Count_Up_Down_out1)
);
assign Out = Count_Up_Down_out1;
endmodule // Debounce_Index
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_rep.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_rep.v //
// Description : Instantiates replay buffer primitives; Single Port Replay //
// Buffer //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_rep.v //
// pcie_bram_7vx_rep_8k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_rep #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [8:0] addr_i, // write address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input wen0_i, // write enable
input wen1_i, // write enable
output [127:0] rdata_o, // read data
output [15:0] rdop_o // read parity
);
pcie3_7x_0_pcie_bram_7vx_rep_8k # (
.IMPL_TARGET(IMPL_TARGET),
.NO_DECODE_LOGIC(NO_DECODE_LOGIC),
.INTERFACE_SPEED(INTERFACE_SPEED),
.COMPLETION_SPACE(COMPLETION_SPACE)
)
U0
(
.clk_i (clk_i),
.reset_i (reset_i),
.addr_i (addr_i[8:0]),
.wdata_i (wdata_i[127:0]),
.wdip_i (wdip_i[15:0]),
.wen_i ({wen1_i, wen0_i}),
.rdata_o (rdata_o[127:0]),
.rdop_o (rdop_o[15:0])
);
endmodule // pcie_bram_7x_rep
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_testbench_utilities.v ////
//// ////
//// This file is part of the "uart16550" project ////
//// http://www.opencores.org/projects/uart16550/ ////
//// ////
//// Author(s): ////
//// - (Tadej Markovic) ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
`include "uart_defines.v"
`include "uart_testbench_defines.v"
`include "wb_model_defines.v"
module testbench_utilities;
// Basic system TASKs
//###################
// DO_RESET
task do_reset;
begin
testbench.wb_reset = 1'b1;
#1;
`UTILS_MSG("RESET signal asynchronously set.");
end
endtask // do_reset
// RELEASE_RESET
task release_reset;
begin
@(posedge testbench.wb_clk);
#1;
testbench.wb_reset = 1'b0;
`UTILS_MSG("RESET signal released synchronously to WB clk.");
end
endtask // release_reset
// DISABLE_CLK_GENERATORS
task disable_clk_generators;
input wb_clk_disable;
input rx_clk_disable;
input tx_clk_disable;
input tx_clk_divided_disable;
begin
`UTILS_MSG("Following clocks are DISABLED:");
if (wb_clk_disable)
begin
testbench.wb_clk_en = 1'b0;
`UTILS_MSG("- WB_clk");
end
if (rx_clk_disable)
begin
testbench.i_uart_device.rx_clk_en = 1'b0;
`UTILS_MSG("- RX_clk");
end
if (tx_clk_disable)
begin
testbench.i_uart_device.tx_clk_en = 1'b0;
`UTILS_MSG("- TX_clk");
end
if (tx_clk_divided_disable)
begin
testbench.i_uart_device.tx_clk_divided_en = 1'b0;
`UTILS_MSG("- TX_clk_divided");
end
if (~wb_clk_disable && ~rx_clk_disable && ~tx_clk_disable && ~tx_clk_divided_disable)
begin
`UTILS_MSG("- NO clocks DISABLED");
end
end
endtask // disable_clk_generators
// ENABLE_CLK_GENERATORS
task enable_clk_generators;
input wb_clk_enable;
input rx_clk_enable;
input tx_clk_enable;
input tx_clk_divided_enable;
begin
`UTILS_MSG("Following clocks are ENABLED:");
if (wb_clk_enable)
begin
testbench.wb_clk_en = 1'b1;
`UTILS_MSG("- WB_clk");
end
if (rx_clk_enable)
begin
testbench.i_uart_device.rx_clk_en = 1'b1;
`UTILS_MSG("- RX_clk");
end
if (tx_clk_enable)
begin
testbench.i_uart_device.tx_clk_en = 1'b1;
`UTILS_MSG("- TX_clk");
end
if (tx_clk_divided_enable)
begin
testbench.i_uart_device.tx_clk_divided_en = 1'b1;
`UTILS_MSG("- TX_clk_divided");
end
if (~wb_clk_enable && ~rx_clk_enable && ~tx_clk_enable && ~tx_clk_divided_enable)
begin
`UTILS_MSG("- NO clocks ENABLED");
end
end
endtask // enable_clk_generators
// SET_DEVICE_TX_RX_CLK_PERIOD
task set_device_tx_rx_clk_period;
input [31:0] clk_period;
begin
testbench.i_uart_device.T_clk_period = clk_period;
`UTILS_VAL1("UART DEVICE TX/RX clock period:", clk_period);
end
endtask // set_device_tx_rx_clk_period
// SET_DEVICE_TX_CLK_DELAY
task set_device_tx_clk_delay;
input [31:0] tx_clk_delay;
begin
testbench.i_uart_device.T_clk_delay = tx_clk_delay;
`UTILS_VAL1("UART DEVICE TX clock delay:", tx_clk_delay);
end
endtask // set_device_tx_clk_delay
// SET_DEVICE_TX_RX_CLK_DIVISOR
task set_device_tx_rx_clk_divisor;
input [31:0] clk_divisor;
begin
testbench.i_uart_device.T_divisor = clk_divisor;
`UTILS_VAL1("UART DEVICE TX/RX clock divisor:", clk_divisor);
end
endtask // set_device_tx_rx_clk_divisor
// SET_WB_CLK_PERIOD
task set_wb_clock_period;
input [31:0] clk_period;
begin
testbench.T_wb_clk_period = clk_period;
testbench.i_uart_device.T_clk_period = clk_period;
`UTILS_VAL1("WB & UART DEVICE TX/RX clock period:", clk_period);
end
endtask // set_wb_clock_period
// WB_CLK_FOLLOWS_DEVICE_RX_CLK
task wb_clk_follows_device_rx_clk;
input [31:0] time_delay_i;
integer time_delay;
begin
time_delay = time_delay_i;
@(posedge testbench.wb_clk);
testbench.wb_clk_en = 1'b0;
@(posedge testbench.i_uart_device.rx_clk);
#time_delay testbench.wb_clk = 1'b1;
testbench.wb_clk_en = 1'b1;
`UTILS_VAL1("WB followed UART DEVICE rising edge RX clock for time delay:", time_delay);
end
endtask // wb_clk_follows_device_rx_clk
// DEVICE_RX_CLK_FOLLOWS_WB_CLK
task device_rx_clk_follows_wb_clk;
input [31:0] time_delay_i;
integer time_delay;
begin
time_delay = time_delay_i;
@(posedge testbench.i_uart_device.rx_clk);
testbench.i_uart_device.rx_clk_en = 1'b0;
@(posedge testbench.wb_clk);
#time_delay testbench.i_uart_device.rx_clk = 1'b1;
testbench.i_uart_device.rx_clk_en = 1'b1;
`UTILS_VAL1("UART DEVICE RX followed WB rising edge clock for time delay:", time_delay);
end
endtask // device_rx_clk_follows_wb_clk
// Utility tasks
//##############
// WAIT_FOR_NUM_OF_WB_CLK
task wait_for_num_of_wb_clk;
input [31:0] num_of_clk;
integer count;
begin
count = 0;
`UTILS_VAL1("Waiting for following number of WB CLK periods:", num_of_clk);
while (count < num_of_clk)
begin
@(testbench.wb_clk);
count = count + 1'b1;
#1;
end
`UTILS_MSG("Waiting expired.");
end
endtask // wait_for_num_of_wb_clk
// WAIT_RX_FIFO_FULL_REGARDLESS_INT
task wait_rx_fifo_full_regardless_int;
integer count;
begin
count = 0;
`UTILS_MSG("Waiting for RX FIFO to get full regardless of interrupt.");
fork
begin:fifo_full_loop
while (testbench.i_uart_top.regs.receiver.fifo_rx.count <
testbench.i_uart_top.regs.receiver.fifo_rx.fifo_depth) // While RX fifo not full
begin
@(testbench.wb_clk);
end
disable counter;
`UTILS_MSG("RX FIFO got full.");
end
begin:counter
while (count < testbench.max_wait_cnt)
begin
@(testbench.wb_clk);
count = count + 1'b1;
#1;
end
disable fifo_full_loop;
`UTILS_ERROR("WAIT counter exceeded max value.");
end
join
end
endtask // wait_rx_fifo_full_regardless_int
// WAIT_RX_FIFO_FULL_UNLESS_INT
task wait_rx_fifo_full_unless_int;
integer count;
begin
count = 0;
`UTILS_MSG("Waiting for RX FIFO to get full unless interrupt occures before.");
fork
begin:fifo_full_loop
while (testbench.i_uart_top.regs.receiver.fifo_rx.count <
testbench.i_uart_top.regs.receiver.fifo_rx.fifo_depth) // While RX fifo not full
begin
@(testbench.wb_clk);
end
disable counter;
disable int_loop;
`UTILS_MSG("RX FIFO got full.");
end
begin:int_loop
if (testbench.ier_reg[3:0] == 4'h0)
begin
`UTILS_MSG("All interrupts are disabled.");
end
else
begin
`UTILS_MSG("Interrupts are enabled in IE Register.");
`UTILS_VAL1("IER:", testbench.ier_reg);
@(testbench.int_aserted);
`UTILS_MSG("Interrupt is asserted. The pending interrupt of highest priority is in II Register.");
`UTILS_VAL1("IIR:", testbench.iir_reg);
disable counter;
disable fifo_full_loop;
end
end
begin:counter
while (count < testbench.max_wait_cnt)
begin
@(testbench.wb_clk);
count = count + 1'b1;
#1;
end
disable int_loop;
disable fifo_full_loop;
`UTILS_ERROR("WAIT counter exceeded max value.");
end
join
end
endtask // wait_rx_fifo_full_unless_int
// UART Initialize TASKs
//######################
// POSSIBLE INITIALIZE TASKS - NOW FEW STEPS ARE MADE IN EACH testcase!!!
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2 * 100 * 1000 + 10; string s, t; int d[N]; int LastSeen[N]; void input() { cin >> s >> t; return; } void PrePros() { int keep = (int)(t.size()) - 1, pnt = (int)(s.size()) - 1; while (keep >= 0) { if (s[pnt] == t[keep]) { LastSeen[keep] = pnt; keep--; } pnt--; } LastSeen[t.size()] = s.size(); t.push_back( * ); return; } void solve() { PrePros(); int lastfound = 0; for (int i = 0; i < s.size(); i++) { d[i] = LastSeen[lastfound] - i; if (s[i] == t[lastfound]) lastfound++; } return; } void output() { int ans = 0; for (int i = 0; i < s.size(); i++) ans = max(ans, d[i]); cout << ans << endl; return; } int main() { input(); solve(); output(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__OR4B_PP_BLACKBOX_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1100; long long x, y; int n; int main() { std::ios::sync_with_stdio(false); while (cin >> n) { long long x1, x2, y1, y2; x1 = y1 = 1000000000; x2 = y2 = -1000000000; for (int i = 0; i < n; ++i) { cin >> x >> y; if (x < x1) x1 = x; if (y < y1) y1 = y; if (x > x2) x2 = x; if (y > y2) y2 = y; } unsigned long long s = max(abs(x2 - x1), abs(y2 - y1)); cout << s * s << endl; } return 0; }
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: write_data_path.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This is top level of write path .
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_write_data_path #(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3",
parameter ADDR_WIDTH = 32,
parameter START_ADDR = 32'h00000000,
parameter BL_WIDTH = 6,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter EYE_TEST = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
output cmd_rdy_o,
input cmd_valid_i,
input cmd_validB_i,
input cmd_validC_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input mode_load_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
// input [5:0] port_data_counts_i,// connect to data port fifo counts
input memc_cmd_full_i,
input data_rdy_i,
output data_valid_o,
output last_word_wr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o,
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o,
output data_wr_end_o
);
wire data_valid;
reg cmd_rdy;
assign data_valid_o = data_valid;// & data_rdy_i;
mig_7series_v4_0_wr_data_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_BURST_LEN (MEM_BURST_LEN),
.BL_WIDTH (BL_WIDTH),
.START_ADDR (START_ADDR),
.nCK_PER_CLK (nCK_PER_CLK),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
wr_data_gen(
.clk_i (clk_i ),
.rst_i (rst_i[9:5]),
.prbs_fseed_i (prbs_fseed_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done_i),
.data_mode_i (data_mode_i ),
.cmd_rdy_o (cmd_rdy_o ),
.cmd_valid_i (cmd_valid_i ),
.cmd_validB_i (cmd_validB_i ),
.cmd_validC_i (cmd_validC_i ),
.last_word_o (last_word_wr_o ),
// .port_data_counts_i (port_data_counts_i),
// .m_addr_i (m_addr_i ),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (addr_i ),
.bl_i (bl_i ),
.memc_cmd_full_i (memc_cmd_full_i),
.data_rdy_i (data_rdy_i ),
.data_valid_o ( data_valid ),
.data_o (data_o ),
.data_wr_end_o (data_wr_end_o),
.data_mask_o (data_mask_o)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_PP_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_PP_V
|
/*
Distributed under the MIT license.
Copyright (c) 2016 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ()
* Description:
* Listens for configuration command updates.
* This will parse out configuration commands. Currently it only listens for
* a few specific configuration values including:
* -max payload size
* -BAR0 - 5 Addresses
* Changes:
* 3/24/2016: Initial Version
*/
`include "pcie_defines.v"
`define MAX_READ_COUNT 5
module config_parser (
input rst,
input clk,
input i_en,
output reg o_finished,
// Host (CFG) Interface
input [31:0] i_cfg_do,
input i_cfg_rd_wr_done,
output reg [9:0] o_cfg_dwaddr,
output reg o_cfg_rd_en,
//AXI Stream Input
output reg [31:0] o_bar_addr0,
output reg [31:0] o_bar_addr1,
output reg [31:0] o_bar_addr2,
output reg [31:0] o_bar_addr3,
output reg [31:0] o_bar_addr4,
output reg [31:0] o_bar_addr5
);
//Local Parameters
localparam IDLE = 4'h0;
localparam PREP_ADDR = 4'h1;
localparam WAIT_STATE = 4'h2;
localparam READ_DATA = 4'h3;
localparam READ_NEXT = 4'h4;
//Registers/Wires
reg [3:0] state;
reg [3:0] index;
wire [9:0] w_cfg_addr[0:`MAX_READ_COUNT];
//Submodules
//Asynchronous Logic
//Get Header Size
assign w_cfg_addr[0] = `BAR_ADDR0 >> 2;
assign w_cfg_addr[1] = `BAR_ADDR1 >> 2;
assign w_cfg_addr[2] = `BAR_ADDR2 >> 2;
assign w_cfg_addr[3] = `BAR_ADDR3 >> 2;
assign w_cfg_addr[4] = `BAR_ADDR4 >> 2;
assign w_cfg_addr[5] = `BAR_ADDR5 >> 2;
//Synchronous Logic
always @ (posedge clk) begin
o_cfg_rd_en <= 0;
if (rst) begin
state <= IDLE;
index <= 0;
o_cfg_dwaddr <= w_cfg_addr[0];
o_bar_addr0 <= 0;
o_bar_addr1 <= 0;
o_bar_addr2 <= 0;
o_bar_addr3 <= 0;
o_bar_addr4 <= 0;
o_bar_addr5 <= 0;
o_finished <= 0;
end
else begin
case (state)
IDLE: begin
o_finished <= 0;
index <= 0;
if (i_en) begin
state <= PREP_ADDR;
end
end
PREP_ADDR: begin
case (index)
0: begin
//o_cfg_dwaddr <= `BAR_ADDR0 >> 2;
o_cfg_dwaddr <= 4;
end
1: begin
//o_cfg_dwaddr <= `BAR_ADDR1 >> 2;
o_cfg_dwaddr <= 5;
end
2: begin
//o_cfg_dwaddr <= `BAR_ADDR2 >> 2;
o_cfg_dwaddr <= 6;
end
3: begin
//o_cfg_dwaddr <= `BAR_ADDR3 >> 2;
o_cfg_dwaddr <= 7;
end
4: begin
//o_cfg_dwaddr <= `BAR_ADDR4 >> 2;
o_cfg_dwaddr <= 8;
end
5: begin
//o_cfg_dwaddr <= `BAR_ADDR5 >> 2;
o_cfg_dwaddr <= 9;
end
endcase
state <= WAIT_STATE;
end
WAIT_STATE: begin
o_cfg_rd_en <= 1;
if (i_cfg_rd_wr_done) begin
state <= READ_DATA;
end
end
READ_DATA: begin
o_cfg_rd_en <= 1;
if (i_cfg_rd_wr_done) begin
case (index)
0: begin
o_bar_addr0 <= i_cfg_do;
end
1: begin
o_bar_addr1 <= i_cfg_do;
end
2: begin
o_bar_addr2 <= i_cfg_do;
end
3: begin
o_bar_addr3 <= i_cfg_do;
end
4: begin
o_bar_addr4 <= i_cfg_do;
end
5: begin
o_bar_addr5 <= i_cfg_do;
end
default: begin
end
endcase
state <= READ_NEXT;
end
end
READ_NEXT: begin
if (!i_cfg_rd_wr_done) begin
if (index < `MAX_READ_COUNT + 1) begin
state <= PREP_ADDR;
index <= index + 1;
end
else begin
o_finished <= 1;
if (!i_en) begin
state <= IDLE;
end
end
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; float r, p, m; float a[100 * 1000]; int main() { cin >> m >> r; p = r * sqrt(2); a[0] = 2 * r; a[1] = 2 * r + p; for (int i = (2), _end = (m); i < _end; ++i) { a[i] = 2 * p; a[i] += 2 * r * (i - 1); } float sum = 0; sum += a[0] * m; for (int i = (1), _end = (m); i < _end; ++i) { sum += 2 * (m - i) * a[i]; } sum = sum / (m * m); printf( %.9f n , sum); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:20:57 09/06/2015
// Design Name:
// Module Name: FSM_Mult_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_Mult_Function(
//INPUTS
input wire clk,
input wire rst,
input wire beg_FSM, //Be gin the multiply operation
input wire ack_FSM, //Is used in the last state, is an aknowledge signal
//ZERO PHASE EVALUATION SIGNALS
input wire zero_flag_i,
//Sgf_Operation *EVALUATION SIGNALS
input wire Mult_shift_i,
//round decoder EVALUATION SIGNALS
input wire round_flag_i,
//Adder round EV LUATION Signals
input wire Add_Overflow_i,
///////////////////////Load Signals/////////////////////////////////////7
//Oper Start_in load signal
output reg load_0_o,
/*Zero flag, Exp operation underflow, Sgf operation first reg, sign result reg*/
output reg load_1_o,
//Exp operation result,
output reg load_2_o,
//Exp operation Overflow, Sgf operation second reg
output reg load_3_o,
//Adder round register
output reg load_4_o,
//Final result registers
output reg load_5_o,
//Barrel shifter registers
output reg load_6_o,
/////////////////////Multiplexers selector control signals////////////
//Sixth Phase control signals
output reg ctrl_select_a_o,
output reg ctrl_select_b_o,
output reg [1:0] selector_b_o,
output reg ctrl_select_c_o,
//////////////////////Module's control signals/////////////////////////
//Exp operation control signals
output reg exp_op_o,
//Barrel shifter control signals
output reg shift_value_o,
//Internal reset signal
output reg rst_int,
//Ready Signal
output reg ready
);
////////States///////////
//Zero Phase
parameter [3:0] start = 4'd0,//A
load_operands = 4'd1, //B) loads both operands to registers
extra64_1 = 4'd2,
add_exp = 4'd3, //C) Add both operands, evaluate underflow
subt_bias = 4'd4, //D) Subtract bias to the result, evaluate overflow, evaluate zero
mult_overf= 4'd5, //E) Evaluate overflow in Sgf multiplication for normalization case
mult_norn = 4'd6, //F) Overflow normalization, right shift significant and increment exponent
mult_no_norn = 4'd7, //G)No_normalization sgf
round_case = 4'd8, //H) Rounding evaluation. Positive= adder rounding, Negative,=Final load
adder_round = 4'd9, //I) add a 1 to the significand in case of rounding
round_norm = 4'd10, //J) Evaluate overflow in adder for normalization, Positive = normalization, same that F
final_load = 4'd11, //K) Load output registers
ready_flag = 4'd12; //L) Ready flag, wait for ack signal
//State registers
reg [3:0] state_reg, state_next;
//State registers reset and standby logic
always @(posedge clk, posedge rst)
if(rst)
state_reg <= start;
else
state_reg <= state_next;
//Transition and Output Logic
always @*
begin
//STATE DEFAULT BEHAVIOR
state_next = state_reg; //If no changes, keep the value of the register unaltered
load_0_o=0;
/*Zero flag, Exp operation underflow, Sgf operation first reg, sign result reg*/
load_1_o=0;
//Exp operation result,
load_2_o=0;
//Exp operation Overflow, Sgf operation second reg
load_3_o=0;
//Adder round register
load_4_o=0;
//Final result registers
load_5_o=0;
load_6_o=0;
//////////////////////Multiplexers selector control signals////////////
//Sixth Phase control signals
ctrl_select_a_o=0;
ctrl_select_b_o=0;
selector_b_o=2'b0;
ctrl_select_c_o=0;
//////////////////////Module's control signals/////////////////////////
//Exp operation control signals
exp_op_o=0;
//Barrel shifter control signals
shift_value_o=0;
//Internal reset signal
rst_int=0;
//Ready Signal
ready=0;
case(state_reg)
start:
begin
rst_int = 1;
if(beg_FSM)
state_next = load_operands; //Jump to the first state of the machine
end
//First Phase
load_operands:
begin
load_0_o = 1;
state_next = extra64_1;
end
extra64_1:
begin
state_next = add_exp;
end
//Zero Check
add_exp:
begin
load_1_o = 1;
load_2_o = 1;
ctrl_select_a_o = 1;
ctrl_select_b_o = 1;
selector_b_o = 2'b01;
state_next = subt_bias;
end
subt_bias:
begin
load_2_o = 1;
load_3_o = 1;
exp_op_o = 1;
if(zero_flag_i)
state_next = ready_flag;
else
state_next = mult_overf;
end
mult_overf:
begin
if(Mult_shift_i) begin
ctrl_select_b_o =1;
selector_b_o =2'b10;
state_next = mult_norn;
end
else
state_next = mult_no_norn;
end
//Ninth Phase
mult_norn:
begin
shift_value_o =1;
load_6_o = 1;
load_2_o = 1;
load_3_o = 1;
//exp_op_o = 1;
state_next = round_case;
end
mult_no_norn:
begin
shift_value_o =0;
load_6_o = 1;
state_next = round_case;
end
round_case:
begin
if(round_flag_i) begin
ctrl_select_c_o =1;
state_next = adder_round;
end
else
state_next = final_load;
end
adder_round:
begin
load_4_o = 1;
ctrl_select_b_o = 1;
selector_b_o = 2'b01;
state_next = round_norm;
end
round_norm:
begin
load_6_o = 1;
if(Add_Overflow_i)begin
shift_value_o =1;
load_2_o = 1;
load_3_o = 1;
state_next = final_load;
end
else begin
shift_value_o =0;
state_next = final_load;
end
end
final_load:
begin
load_5_o =1;
state_next = ready_flag;
end
ready_flag:
begin
ready = 1;
if(ack_FSM) begin
state_next = start;end
end
default:
begin
state_next =start;end
endcase
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Tick Timer ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// TT according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// None ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_tt(
// RISC Internal Interface
clk, rst, du_stall,
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
intr
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input du_stall; // DU stall
input spr_cs; // SPR CS
input spr_write; // SPR Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
output intr; // Interrupt output
`ifdef OR1200_TT_IMPLEMENTED
//
// TT Mode Register bits (or no register)
//
`ifdef OR1200_TT_TTMR
reg [31:0] ttmr; // TTMR bits
`else
wire [31:0] ttmr; // No TTMR register
`endif
//
// TT Count Register bits (or no register)
//
`ifdef OR1200_TT_TTCR
reg [31:0] ttcr; // TTCR bits
`else
wire [31:0] ttcr; // No TTCR register
`endif
//
// Internal wires & regs
//
wire ttmr_sel; // TTMR select
wire ttcr_sel; // TTCR select
wire match; // Asserted when TTMR[TP]
// is equal to TTCR[27:0]
wire restart; // Restart counter when asserted
wire stop; // Stop counter when asserted
reg [31:0] spr_dat_o; // SPR data out
//
// TT registers address decoder
//
assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
//
// Write to TTMR or update of TTMR[IP] bit
//
`ifdef OR1200_TT_TTMR
always @(posedge clk or posedge rst)
if (rst)
ttmr <= 32'b0;
else if (ttmr_sel && spr_write)
ttmr <= #1 spr_dat_i;
else if (ttmr[`OR1200_TT_TTMR_IE])
ttmr[`OR1200_TT_TTMR_IP] <= #1 ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
`else
assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3
`endif
//
// Write to or increment of TTCR
//
`ifdef OR1200_TT_TTCR
always @(posedge clk or posedge rst)
if (rst)
ttcr <= 32'b0;
else if (restart)
ttcr <= #1 32'b0;
else if (ttcr_sel && spr_write)
ttcr <= #1 spr_dat_i;
else if (!stop)
ttcr <= #1 ttcr + 32'd1;
`else
assign ttcr = 32'b0;
`endif
//
// Read TT registers
//
always @(spr_addr or ttmr or ttcr)
case (spr_addr[`OR1200_TTOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_TT_READREGS
`OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
`endif
default: spr_dat_o = ttcr;
endcase
//
// A match when TTMR[TP] is equal to TTCR[27:0]
//
assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
//
// Restart when match and TTMR[M]==0x1
//
assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
//
assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
//
// Generate an interrupt request
//
assign intr = ttmr[`OR1200_TT_TTMR_IP];
`else
//
// When TT is not implemented, drive all outputs as would when TT is disabled
//
assign intr = 1'b0;
//
// Read TT registers
//
`ifdef OR1200_TT_READREGS
assign spr_dat_o = 32'b0;
`endif
`endif
endmodule
|
// File: RingCounter_TBV.v
// Generated by MyHDL 0.10
// Date: Wed Sep 5 07:53:29 2018
`timescale 1ns/10ps
module RingCounter_TBV (
);
// myHDL -> verilog Testbench for `RingCounter` module
reg clk = 0;
reg rst = 0;
wire [3:0] q;
reg [1:0] Dir = 2'b10;
wire [3:0] seed;
reg [3:0] RingCounter0_0_q_i = 3;
assign seed = 4'd3;
always @(q, rst, Dir, clk, seed) begin: RINGCOUNTER_TBV_PRINT_DATA
$write("%h", seed);
$write(" ");
$write("%h", Dir);
$write(" ");
$write("%h", q);
$write(" ");
$write("%h", clk);
$write(" ");
$write("%h", rst);
$write("\n");
end
always @(posedge clk, negedge rst) begin: RINGCOUNTER_TBV_RINGCOUNTER0_0_RCSTATEMACHINE
if (rst) begin
RingCounter0_0_q_i <= seed;
end
else if ((Dir == 2'b00)) begin
RingCounter0_0_q_i <= {RingCounter0_0_q_i[(4 - 1)-1:0], RingCounter0_0_q_i[(4 - 1)]};
end
else if ((Dir == 2'b01)) begin
RingCounter0_0_q_i <= RingCounter0_0_q_i;
end
else if ((Dir == 2'b10)) begin
RingCounter0_0_q_i <= {RingCounter0_0_q_i[0], RingCounter0_0_q_i[4-1:1]};
end
end
assign q = RingCounter0_0_q_i;
initial begin: RINGCOUNTER_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: RINGCOUNTER_TBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
if ((i == (2 * 4))) begin
Dir <= 2'b00;
end
else if ((i == (3 * 4))) begin
rst <= 1;
end
else if ((i == ((3 * 4) + 1))) begin
rst <= 0;
end
else if ((i == ((3 * 4) + 2))) begin
Dir <= 2'b01;
end
if ((i == (5 * 4))) begin
$finish;
end
i = i + 1;
@(posedge clk);
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O2BB2A_BEHAVIORAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int M = 2e5 + 10; struct Edge { int u, v, cap, flow = 0; Edge(int u, int v, int cap) : u(u), v(v), cap(cap) {} }; class Dinic { public: vector<Edge> edges; vector<vector<int>> G; int n, m = 0, s, t; vector<int> H, ptr; queue<int> q; Dinic(int n, int s, int t) : n(n), s(s), t(t) { G.resize(n + 1); H = ptr = vector<int>(n + 1); } void add(int u, int v, int cap) { edges.emplace_back(u, v, cap); edges.emplace_back(v, u, 0); G[u].push_back(m++); G[v].push_back(m++); } bool bfs() { while (!q.empty()) { int u = q.front(); q.pop(); for (int v : G[u]) { int to = edges[v].v; int gap = edges[v].cap - edges[v].flow; if (H[to] != -1 or gap < 1) continue; H[to] = H[u] + 1, q.push(to); } } return H[t] != -1; } int dfs(int u, int X) { if (!X) return 0; if (u == t) return X; for (int &i = ptr[u]; i < (int)(G[u]).size(); ++i) { int v = G[u][i], to = edges[v].v; int gap = edges[v].cap - edges[v].flow; if (H[to] != (H[u] + 1) or gap < 1) continue; int Y = dfs(to, min(X, gap)); if (!Y) continue; edges[v].flow += Y; edges[v ^ 1].flow -= Y; return Y; } return 0; } int flow() { int ans = 0; while (true) { fill(H.begin(), H.end(), -1); H[s] = 0, q.push(s); if (!bfs()) break; fill(ptr.begin(), ptr.end(), 0); while (int X = dfs(s, (int)(1e18))) ans += X; } return ans; } }; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; vector<pair<int, pair<int, int>>> edges; vector<int> cand; for (int i = 0; i < m; ++i) { int u, v, w; cin >> u >> v >> w; edges.push_back({w, {u, v}}); cand.push_back(w); } sort((cand).begin(), (cand).end()); cand.erase(unique((cand).begin(), (cand).end()), cand.end()); int lo = 0, hi = (int)(cand).size() - 1, mid, ans = -1; int s = 0, t = 2 * n + 1; while (lo <= hi) { mid = (lo + hi) >> 1; Dinic dinic(2 * n + 2, s, t); for (int i = 1; i <= n; ++i) { dinic.add(s, i, 1); dinic.add(i + n, t, 1); } for (auto [w, p] : edges) if (w <= cand[mid]) dinic.add(p.first, p.second + n, 1); int x = dinic.flow(); if (x == n) hi = mid - 1, ans = cand[mid]; else lo = mid + 1; } cout << ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__DLRTN_FUNCTIONAL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_hdll__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_hdll__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET;
wire GATE ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (GATE , GATE_N );
sky130_fd_sc_hdll__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_FUNCTIONAL_V
|
`timescale 1ns/10ps
module dummy_master(
input wire clock // K5 PLL1 input clock (50 MHz)
,input wire reset
// Memory access
,input mem_waitrequest
,output reg [1:0] mem_id = 1
,output reg [29:0] mem_address = 0
,output reg mem_read = 0
,output reg mem_write = 0
,output reg [31:0] mem_writedata = 0
,output reg [3:0] mem_writedatamask = 0
,input [31:0] mem_readdata
,input [1:0] mem_readdataid
,output reg [31:0] errors = 0
);
reg [18:0] wp = 0, rp = 0, vp = 0;
reg [31:0] data = 0;
reg [32:0] lfsr = 0;
reg mismatch_pre = 0, mismatch = 0;
always @(posedge clock) if (reset) begin
wp <= 0;
rp <= 0;
vp <= 0;
lfsr <= 0;
errors <= 0;
mem_read <= 0;
mem_write <= 0;
mismatch_pre <= 0;
mismatch <= 0;
end else begin
mem_id <= 1;
lfsr <= {lfsr[31:0], ~lfsr[32] ^ lfsr[19]};
if (mem_readdataid == 1) begin
// Delay to help fMAX
mismatch_pre <= mem_readdata != {vp,~vp[3:0]};
mismatch <= mismatch_pre;
if (mismatch)
errors <= errors + 1;
vp <= vp + 1;
end
if (~mem_waitrequest) begin
mem_read <= 0;
mem_write <= 0;
if (~lfsr[4]) begin
mem_writedata <= {wp, ~wp[3:0]};
mem_writedatamask <= /*lfsr[4:1]*/ ~0;
mem_write <= 1;
mem_address <= wp;
wp <= wp + 1;
end else begin
mem_read <= 1;
mem_address <= rp;
rp <= rp + 4;
end
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/22/06 - CR#226003 - Added integer, real parameter type
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUF (O, IO, I, T);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O;
inout IO;
input I, T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
buf B1 (O, IO);
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => IO)= (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
module cov_miss_fifo
import bsg_cache_non_blocking_pkg::*;
(
input clk_i
, input reset_i
, input v_i
, input ready_o
, input v_o
, input yumi_i
, input bsg_cache_non_blocking_miss_fifo_op_e yumi_op_i
, input scan_not_dq_i
, input read_write_same_addr
, input v_r
, input empty
, input rptr_valid
, input enque
, input rollback_i
);
covergroup cg_output_taken @ (negedge clk_i iff v_r & yumi_i & ~rollback_i);
coverpoint yumi_op_i;
coverpoint read_write_same_addr;
coverpoint enque;
cross yumi_op_i, read_write_same_addr, enque;
endgroup
covergroup cg_input_output @ (negedge clk_i);
coverpoint v_i;
coverpoint ready_o;
coverpoint v_o;
coverpoint yumi_i;
cross v_i, ready_o, v_o, yumi_i {
ignore_bins n_v_o =
binsof(v_o) intersect {1'b0} &&
binsof(yumi_i) intersect {1'b1};
}
endgroup
covergroup cg_output_not_valid @ (negedge clk_i iff ~rollback_i & ~v_r);
coverpoint empty;
coverpoint scan_not_dq_i;
coverpoint rptr_valid;
coverpoint enque;
cross empty, scan_not_dq_i, rptr_valid, enque {
ignore_bins ig0 =
binsof(empty) intersect {1'b1} &&
binsof(scan_not_dq_i) intersect {1'b0} &&
binsof(rptr_valid) intersect {1'b1};
ignore_bins ig1 =
binsof(empty) intersect {1'b1} &&
binsof(scan_not_dq_i) intersect {1'b1} &&
binsof(enque) intersect {1'b1};
}
endgroup
initial begin
cg_output_taken ot = new;
cg_input_output io = new;
cg_output_not_valid onv = new;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_BLACKBOX_V
`define SKY130_FD_SC_HS__A2111O_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int tc; cin >> tc; while (tc--) { int n, m, x1, y1, x2, y2, w, h; cin >> n >> m >> x1 >> y1 >> x2 >> y2 >> w >> h; int right = n - x2; int left = x1; int up = m - y2; int down = y1; int mn = 1e9; int w1 = x2 - x1; int h1 = y2 - y1; if (w1 + w <= n) { mn = min(mn, max(0, w - right)); mn = min(mn, max(0, w - left)); } if (h1 + h <= m) { mn = min(mn, max(0, h - up)); mn = min(mn, max(0, h - down)); } if (mn == 1e9) mn = -1; cout << mn << n ; } return 0; }
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 9: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 9: 0] data_out;
wire [ 9: 0] out_port;
wire [ 9: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {10 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[9 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if"
// that should not work.
//
// The given generate loops should attempt to access invalid bits of mask and
// trigger errors.
// is defined by SIZE. However since the loop range is larger, this only works
// if short-circuited evaluation of the generate loop is in place.
// This file ONLY is placed into the Public Domain, for any use, without
// warranty, 2012 by Jeremy Bennett.
`define MAX_SIZE 3
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Set the parameters, so that we use a size less than MAX_SIZE
test_gen
#(.SIZE (2),
.MASK (2'b11))
i_test_gen (.clk (clk));
// This is only a compilation test, so we can immediately finish
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule // t
module test_gen
#( parameter
SIZE = `MAX_SIZE,
MASK = `MAX_SIZE'b0)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
// Generate blocks that all have errors in applying short-circuting to
// generate "if" conditionals.
// Attempt to access invalid bits of MASK in different ways
generate
genvar g;
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < (SIZE + 1)) && MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < SIZE) && MASK[g + 1]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
// Attempt to short-circuit bitwise AND
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < (SIZE)) & MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
// Attempt to short-circuit bitwise OR
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if (!((g >= SIZE) | ~MASK[g])) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, i, j, res = 0, k, v1, v2; cin >> n; vector<long long> v; for (i = 0; i < n; i++) { cin >> j; v.emplace_back(j); } if (n == 1) { cout << v[0] << n ; return 0; } else if (n == 2) { cout << (v[0] | v[1]) << n ; return 0; } for (i = 0; i < n; i++) { for (j = i + 1; j < n; j++) { v2 = v[i] | v[j]; for (k = j + 1; k < n; k++) { v1 = v2 | v[k]; res = max(res, v1); } } } cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, s = 0, i, x, vs = 0; vector<int> a; cin >> n; for (i = 0; i < n; i++) { cin >> x; a.push_back(x); vs += x; } sort(a.begin(), a.end(), std::greater<int>()); if (n == 1) cout << a[0] << endl; else if (n == 2) cout << 2 * vs << endl; else { while (a.size() > 1) { s += vs; s += a.back(); vs -= a.back(); a.pop_back(); } s += a[0]; cout << s << endl; } }
|
module ram_wb_b3(
wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_rty_o, wb_dat_o,
wb_clk_i, wb_rst_i);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input [1:0] wb_bte_i;
input [2:0] wb_cti_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
output [dw-1:0] wb_dat_o;
input wb_clk_i;
input wb_rst_i;
// Memory parameters
parameter mem_size_bytes = 32'h0000_5000; // 20KBytes
parameter mem_adr_width = 15; //(log2(mem_size_bytes));
parameter bytes_per_dw = (dw/8);
parameter adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
parameter mem_words = (mem_size_bytes/bytes_per_dw);
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
// Register to address internal memory array
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
wire [31:0] wr_data;
// Register to indicate if the cycle is a Wishbone B3-registered feedback
// type access
reg wb_b3_trans;
wire wb_b3_trans_start, wb_b3_trans_stop;
// Register to use for counting the addresses when doing burst accesses
reg [mem_adr_width-adr_width_for_num_word_bytes-1:0] burst_adr_counter;
reg [2:0] wb_cti_i_r;
reg [1:0] wb_bte_i_r;
wire using_burst_adr;
wire burst_access_wrong_wb_adr;
// Wire to indicate addressing error
wire addr_err;
// Logic to detect if there's a burst access going on
assign wb_b3_trans_start = ((wb_cti_i == 3'b001)|(wb_cti_i == 3'b010)) &
wb_stb_i & !wb_b3_trans;
assign wb_b3_trans_stop = ((wb_cti_i == 3'b111) &
wb_stb_i & wb_b3_trans & wb_ack_o) | wb_err_o;
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_b3_trans <= 0;
else if (wb_b3_trans_start)
wb_b3_trans <= 1;
else if (wb_b3_trans_stop)
wb_b3_trans <= 0;
// Burst address generation logic
always @(/*AUTOSENSE*/wb_ack_o or wb_b3_trans or wb_b3_trans_start
or wb_bte_i_r or wb_cti_i_r or wb_adr_i or adr)
if (wb_b3_trans_start)
// Kick off burst_adr_counter, this assumes 4-byte words when getting
// address off incoming Wishbone bus address!
// So if dw is no longer 4 bytes, change this!
burst_adr_counter = wb_adr_i[mem_adr_width-1:2];
else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
// Incrementing burst
begin
if (wb_bte_i_r == 2'b00) // Linear burst
burst_adr_counter = adr + 1;
if (wb_bte_i_r == 2'b01) // 4-beat wrap burst
burst_adr_counter[1:0] = adr[1:0] + 1;
if (wb_bte_i_r == 2'b10) // 8-beat wrap burst
burst_adr_counter[2:0] = adr[2:0] + 1;
if (wb_bte_i_r == 2'b11) // 16-beat wrap burst
burst_adr_counter[3:0] = adr[3:0] + 1;
end // if ((wb_cti_i_r == 3'b010) & wb_ack_o_r)
always @(posedge wb_clk_i)
wb_bte_i_r <= wb_bte_i;
// Register it locally
always @(posedge wb_clk_i)
wb_cti_i_r <= wb_cti_i;
assign using_burst_adr = wb_b3_trans;
assign burst_access_wrong_wb_adr = (using_burst_adr &
(adr != wb_adr_i[mem_adr_width-1:2]));
// Address registering logic
always@(posedge wb_clk_i)
if(wb_rst_i)
adr <= 0;
else if (using_burst_adr)
adr <= burst_adr_counter;
else if (wb_cyc_i & wb_stb_i)
adr <= wb_adr_i[mem_adr_width-1:2];
/* Memory initialisation.
If not Verilator model, always do load, otherwise only load when called
from SystemC testbench.
*/
parameter memory_file = "sram.vmem";
`ifdef verilator
task do_readmemh;
// verilator public
$readmemh(memory_file, mem);
endtask // do_readmemh
`else
initial
begin
$readmemh(memory_file, mem);
end
`endif // !`ifdef verilator
assign wb_rty_o = 0;
// mux for data to ram, RMW on part sel != 4'hf
assign wr_data[31:24] = wb_sel_i[3] ? wb_dat_i[31:24] : wb_dat_o[31:24];
assign wr_data[23:16] = wb_sel_i[2] ? wb_dat_i[23:16] : wb_dat_o[23:16];
assign wr_data[15: 8] = wb_sel_i[1] ? wb_dat_i[15: 8] : wb_dat_o[15: 8];
assign wr_data[ 7: 0] = wb_sel_i[0] ? wb_dat_i[ 7: 0] : wb_dat_o[ 7: 0];
wire ram_we;
assign ram_we = wb_we_i & wb_ack_o;
assign wb_dat_o = mem[adr];
// Write logic
always @ (posedge wb_clk_i)
begin
if (ram_we)
mem[adr] <= wr_data;
end
// Ack Logic
reg wb_ack_o_r;
assign wb_ack_o = wb_ack_o_r & wb_stb_i &
!(burst_access_wrong_wb_adr | addr_err);
always @ (posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o_r <= 1'b0;
else if (wb_cyc_i) // We have bus
begin
if (addr_err & wb_stb_i)
begin
wb_ack_o_r <= 1;
end
else if (wb_cti_i == 3'b000)
begin
// Classic cycle acks
if (wb_stb_i)
begin
if (!wb_ack_o_r)
wb_ack_o_r <= 1;
else
wb_ack_o_r <= 0;
end
end // if (wb_cti_i == 3'b000)
else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010))
begin
// Increment/constant address bursts
if (wb_stb_i)
wb_ack_o_r <= 1;
else
wb_ack_o_r <= 0;
end
else if (wb_cti_i == 3'b111)
begin
// End of cycle
if (!wb_ack_o_r)
wb_ack_o_r <= wb_stb_i;
else
wb_ack_o_r <= 0;
end
end // if (wb_cyc_i)
else
wb_ack_o_r <= 0;
//
// Error signal generation
//
// Error when out of bounds of memory - skip top byte of address in case
// this is mapped somewhere other than 0x00.
assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1:mem_adr_width]);
// OR in other errors here...
assign wb_err_o = wb_ack_o_r & wb_stb_i &
(burst_access_wrong_wb_adr | addr_err);
//
// Access functions
//
// Function to access RAM (for use by Verilator).
function [31:0] get_mem32;
// verilator public
input [aw-1:0] addr;
get_mem32 = mem[addr];
endfunction // get_mem32
// Function to access RAM (for use by Verilator).
function [7:0] get_mem8;
// verilator public
input [aw-1:0] addr;
reg [31:0] temp_word;
begin
temp_word = mem[{addr[aw-1:2],2'd0}];
// Big endian mapping.
get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
(addr[1:0]==2'b01) ? temp_word[23:16] :
(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
end
endfunction // get_mem8
// Function to write RAM (for use by Verilator).
function set_mem32;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
mem[addr] = data;
endfunction // set_mem32
endmodule // ram_wb_b3
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 2; const int mod = 100003; const int INF = 0x3f3f3f; int n, m, x, y; int vis[N]; struct node { int x, r, i, v; } tar[N]; bool cmp1(node &x, node &y) { return x.x < y.x; } bool cmp2(node &x, node &y) { return x.i < y.i; } int find(int x) { int l, mid, r; l = 1, r = n; while (r - l > 1) { mid = (l + r) / 2; if (tar[mid].x == x) return mid; if (tar[mid].x < x) l = mid; if (tar[mid].x > x) r = mid; } return l; } bool chk(int p, int x, int y) { if ((tar[p].x - x) * (tar[p].x - x) + y * y <= tar[p].r * tar[p].r) return true; else return false; } int main() { ios::sync_with_stdio(false); cin >> n; memset(vis, 0, sizeof(vis)); ; for (int i = 1; i <= n; i++) { cin >> tar[i].x >> tar[i].r; tar[i].v = -1; tar[i].i = i; } sort(tar + 1, tar + 1 + n, cmp1); cin >> m; int pos; int sum = 0; for (int i = 1; i <= m; i++) { cin >> x >> y; pos = find(x); if (tar[pos - 1].v == -1 && chk(pos - 1, x, y)) { tar[pos - 1].v = i; sum++; } if (tar[pos].v == -1 && chk(pos, x, y)) { tar[pos].v = i; sum++; } if (tar[pos + 1].v == -1 && chk(pos + 1, x, y)) { tar[pos + 1].v = i; sum++; } } sort(tar + 1, tar + 1 + n, cmp2); cout << sum << endl; for (int i = 1; i <= n; i++) { cout << tar[i].v << ; } return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file Color_ROM.v when simulating
// the core, Color_ROM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module Color_ROM(
clka,
addra,
douta
);
input clka;
input [11 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("Color_ROM.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4000),
.C_READ_DEPTH_B(4000),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4000),
.C_WRITE_DEPTH_B(4000),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3e")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTN_4_V
`define SKY130_FD_SC_LS__DLXTN_4_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxtn_4 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxtn_4 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTN_4_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; void init_ios() { ios_base::sync_with_stdio(0); cin.tie(0); } const int N = (1 << 19); int n, m, jump[N][20]; pair<int, int> a[N], drz[2 * N]; void add(int v, int val, int ind) { v += N; if (val < drz[v].first) return; drz[v] = {val, ind}; while (v > 1) { v /= 2; if (drz[2 * v].first > drz[2 * v + 1].first) drz[v] = drz[2 * v]; else drz[v] = drz[2 * v + 1]; } } pair<int, int> get(int p, int q) { p += N; q += N; pair<int, int> res; if (drz[p].first > drz[q].first) res = drz[p]; else res = drz[q]; while (p / 2 != q / 2) { if (p % 2 == 0 && drz[p + 1].first > res.first) res = drz[p + 1]; if (q % 2 == 1 && drz[q - 1].first > res.first) res = drz[q - 1]; p /= 2; q /= 2; } return res; } int get_id(int id, int hm) { for (int i = 0; i < 20; ++i) if (hm & (1 << i)) id = jump[id][i]; return id; } int query(int x, int y) { int id = get(0, x).second; if (id == 0) return -1; if (a[id].second >= y) return 1; int x1 = 1, x2 = n - 1, x3; while (x2 - x1 > 1) { x3 = (x1 + x2) / 2; int id2 = get_id(id, x3); if (id2 == 0 || a[id2].second >= y) x2 = x3; else x1 = x3; } int id2 = get_id(id, x1); if (id2 != 0 && a[id2].second >= y) return 1 + x1; id2 = get_id(id, x2); if (id2 != 0 && a[id2].second >= y) return 1 + x2; return -1; } int main() { init_ios(); cin >> n >> m; for (int i = 1; i <= n; ++i) { cin >> a[i].first >> a[i].second; add(a[i].first, a[i].second, i); } for (int l = 0; l < 20; ++l) { for (int i = 1; i <= n; ++i) { if (l == 0) { pair<int, int> p = get(a[i].first, a[i].second); jump[i][l] = p.second; } else { jump[i][l] = jump[jump[i][l - 1]][l - 1]; } } } while (m--) { int x, y; cin >> x >> y; cout << query(x, y) << n ; } }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:47:18 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_stub.v
// Design : system_zed_hdmi_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zed_hdmi,Vivado 2016.4" *)
module system_zed_hdmi_0_0(clk, clk_x2, clk_100, active, hsync, vsync, rgb888,
hdmi_clk, hdmi_hsync, hdmi_vsync, hdmi_d, hdmi_de, hdmi_scl, hdmi_sda)
/* synthesis syn_black_box black_box_pad_pin="clk,clk_x2,clk_100,active,hsync,vsync,rgb888[23:0],hdmi_clk,hdmi_hsync,hdmi_vsync,hdmi_d[15:0],hdmi_de,hdmi_scl,hdmi_sda" */;
input clk;
input clk_x2;
input clk_100;
input active;
input hsync;
input vsync;
input [23:0]rgb888;
output hdmi_clk;
output hdmi_hsync;
output hdmi_vsync;
output [15:0]hdmi_d;
output hdmi_de;
output hdmi_scl;
inout hdmi_sda;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: one_hot_mux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A mux module, where the output select is a one-hot bus
// Author: Dustin Richmond
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module one_hot_mux
#(parameter C_DATA_WIDTH = 1,
parameter C_SELECT_WIDTH = 2,
parameter C_AGGREGATE_WIDTH = C_SELECT_WIDTH*C_DATA_WIDTH
)
(
input [C_SELECT_WIDTH-1:0] ONE_HOT_SELECT,
input [C_AGGREGATE_WIDTH-1:0] ONE_HOT_INPUTS,
output [C_DATA_WIDTH-1:0] ONE_HOT_OUTPUT);
`include "functions.vh"
genvar i;
wire [C_DATA_WIDTH-1:0] wOneHotInputs[(1<<C_SELECT_WIDTH):1];
reg [C_DATA_WIDTH-1:0] _rOneHotOutput;
assign ONE_HOT_OUTPUT = _rOneHotOutput;
generate
for( i = 0 ; i < C_SELECT_WIDTH; i = i + 1 ) begin : gen_input_array
assign wOneHotInputs[(1<<i)] = ONE_HOT_INPUTS[C_DATA_WIDTH*i +: C_DATA_WIDTH];
end
if(C_SELECT_WIDTH == 1) begin
always @(*) begin
_rOneHotOutput = wOneHotInputs[1];
end
end else if(C_SELECT_WIDTH == 2) begin
always @(*) begin
case(ONE_HOT_SELECT)
2'b01: _rOneHotOutput = wOneHotInputs[1];
2'b10: _rOneHotOutput = wOneHotInputs[2];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end else if( C_SELECT_WIDTH == 4) begin
always @(*) begin
case(ONE_HOT_SELECT)
4'b0001: _rOneHotOutput = wOneHotInputs[1];
4'b0010: _rOneHotOutput = wOneHotInputs[2];
4'b0100: _rOneHotOutput = wOneHotInputs[4];
4'b1000: _rOneHotOutput = wOneHotInputs[8];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end else if( C_SELECT_WIDTH == 8) begin
always @(*) begin
case(ONE_HOT_SELECT)
8'b00000001: _rOneHotOutput = wOneHotInputs[1];
8'b00000010: _rOneHotOutput = wOneHotInputs[2];
8'b00000100: _rOneHotOutput = wOneHotInputs[4];
8'b00001000: _rOneHotOutput = wOneHotInputs[8];
8'b00010000: _rOneHotOutput = wOneHotInputs[16];
8'b00100000: _rOneHotOutput = wOneHotInputs[32];
8'b01000000: _rOneHotOutput = wOneHotInputs[64];
8'b10000000: _rOneHotOutput = wOneHotInputs[128];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long int n; cin >> n; vector<long long int> v(n); for (int i = 0; i < n; i++) cin >> v[i]; sort(v.begin(), v.end()); if (n == 1) { int q; cin >> q; for (int i = 0; i < q; i++) { long long int l, r; cin >> l >> r; cout << r - l + 1 << ; } return 0; } vector<long long int> use(n - 1); for (int i = 1; i < n; i++) { use[i - 1] = v[i] - v[i - 1]; } sort(use.begin(), use.end()); vector<long long int> pref(n - 1); pref[0] = use[0]; for (int i = 1; i < n - 1; i++) { pref[i] = pref[i - 1] + use[i]; } int q; cin >> q; for (int i = 0; i < q; i++) { long long int l, r; cin >> l >> r; long long int ans = 0; long long int val = r - l + 1; long long int where = upper_bound(use.begin(), use.end(), val) - use.begin(); if (where) ans = ans + pref[where - 1]; long long int extra = (val) * (n - 1 - where); ans = ans + extra; ans = ans + val; cout << ans << ; } }
|
#include <bits/stdc++.h> using namespace std; void solve(); void precalc(); int main() { string s = change me please ; int t = 1; while (t--) solve(); return 0; } void solve() { int n; cin >> n; vector<int> a(n), h(n); for (int i = 0; i < n; ++i) cin >> a[i] >> h[i]; int ans = 0; for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) if (a[i] == h[j]) ++ans; cout << ans; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* This file is based on "Asynchronous FIFO" by Alex Claros F.,
* itself based on the article "Asynchronous FIFO in Virtex-II FPGAs"
* by Peter Alfke.
*/
module asfifo_graycounter #(
parameter width = 2
) (
output reg [width-1:0] gray_count,
input ce,
input rst,
input clk
);
reg [width-1:0] binary_count;
always @(posedge clk, posedge rst) begin
if(rst) begin
binary_count <= {width{1'b0}} + 1;
gray_count <= {width{1'b0}};
end else if(ce) begin
binary_count <= binary_count + 1;
gray_count <= {binary_count[width-1],
binary_count[width-2:0] ^ binary_count[width-1:1]};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> graph[200000]; int color[200000], black, white, maxDist, farNode; void solve(int node, int par, int dis) { if (dis > maxDist) farNode = node, maxDist = dis; for (auto &v : graph[node]) { if (v == par) continue; solve(v, node, dis + (color[node] != color[v])); } } int main() { ios ::sync_with_stdio(false); cin.tie(); int n, a, b, firstNode; cin >> n; for (int i = 0; i < n; i++) cin >> color[i]; for (int i = 0; i < n - 1; i++) { cin >> a >> b; a--, b--; graph[a].push_back(b); graph[b].push_back(a); } solve(0, -1, 1); maxDist = 1; solve(farNode, -1, 1); cout << (maxDist) / 2; return 0; }
|
#include <bits/stdc++.h> int main() { int x, y, s; scanf( %d %d %d , &x, &y, &s); if (s >= 0) { y = y + s; if (y % x) printf( %d , y % x); else printf( %d , x); } else if (s < 0) { double p = abs(s); p = ceil(p / x); y = y + s + (p * x); if (y % x) printf( %d , y % x); else printf( %d , x); } }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const int mod = 1e9 + 7; int n, l[N], t[N]; long long r; int main() { scanf( %d%lld , &n, &r); for (int i = 0; i < n; i++) scanf( %d , l + i); for (int i = 0; i < n; i++) { scanf( %d , t + i); if (t[i] < l[i]) return puts( -1 ); } vector<long long> out; long long cur = 0, time = 0; long long ans = 0; for (int i = 0; i < n; i++) { int x = min((long long)l[i], cur); cur -= x; l[i] -= x; t[i] -= x; time += x; x = l[i] + l[i]; time += min(x, t[i]); int d = x - t[i]; if (d <= 0) continue; int need = (d + r - 1) / r; ans += need; long long lo = time - d; for (int j = 0; j < need; j++) { if (out.size() > 100000) break; out.push_back(lo); lo += r; } cur = need * r - d; } printf( %lld n , ans); if (ans <= 100000) { for (int i = 0; i < ans; i++) printf( %lld , out[i]); } }
|
#include <bits/stdc++.h> using namespace std; const int MaxK = 53, MaxN = 2000005; int N, K; char A[MaxN]; char B[MaxN]; int id(char c) { return ( a <= c && c <= z ) ? c - a : c - A + 26; } namespace KuhnMunkres { const int MAX_N = 505; const int INF = 100000000; const int BASE = 1000; int n; int graph[MAX_N][MAX_N]; bool usedX[MAX_N]; bool usedY[MAX_N]; int linkTo[MAX_N]; int labelX[MAX_N]; int labelY[MAX_N]; bool findPath(int i) { usedX[i] = true; for (int j = 0; j < n; j++) if (!usedY[j] && labelX[i] + labelY[j] == graph[i][j] && linkTo[j] == -1) { usedY[j] = true; linkTo[j] = i; return true; } for (int j = 0; j < n; j++) if (!usedY[j] && labelX[i] + labelY[j] == graph[i][j]) { usedY[j] = true; if (linkTo[j] == -1 || findPath(linkTo[j])) { linkTo[j] = i; return true; } } return false; } int KuhnMunkres() { memset(linkTo, -1, sizeof(linkTo)); memset(labelX, 0, sizeof(labelX)); memset(labelY, 0, sizeof(labelY)); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) labelX[i] = max(labelX[i], graph[i][j]); for (int k = 0; k < n; k++) while (true) { memset(usedX, 0, sizeof(usedX)); memset(usedY, 0, sizeof(usedY)); if (findPath(k)) break; int delta = INF; for (int i = 0; i < n; i++) if (usedX[i]) for (int j = 0; j < n; j++) if (!usedY[j]) delta = min(delta, labelX[i] + labelY[j] - graph[i][j]); if (delta == 0 || delta == INF) break; for (int i = 0; i < n; i++) if (usedX[i]) labelX[i] -= delta; for (int i = 0; i < n; i++) if (usedY[i]) labelY[i] += delta; } int maxTotal = 0; for (int i = 0; i < n; i++) maxTotal += labelX[i] + labelY[i]; return maxTotal; } }; // namespace KuhnMunkres int main() { cin.sync_with_stdio(false); cin >> N >> K; cin >> A; cin >> B; KuhnMunkres::n = K; for (int i = 0; i < N; i++) { int u = id(A[i]); int v = id(B[i]); KuhnMunkres::graph[u][v]++; } cout << KuhnMunkres::KuhnMunkres() << endl; int array[MaxK]; for (int i = 0; i < K; i++) { array[KuhnMunkres::linkTo[i]] = i; } for (int i = 0; i < K; i++) { int b = array[i]; if (b < 26) cout << (char)( a + b); else cout << (char)( A + b - 26); } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, K, a[100100], f[30030][205][4][2]; bool vis[30030][205][4][2]; void work() { memset(f, -127, sizeof(f)); for (int i = 1; i <= n; i++) { f[i][1][0][0] = -a[i]; f[i][1][2][0] = a[i]; vis[i][1][0][0] = 1; vis[i][1][2][0] = 1; } for (int i = 1; i < n; i++) for (int j = 1; j <= min(K, i); j++) for (int k = 0; k <= 3; k++) for (int l = 0; l <= 1; l++) { if (!vis[i][j][k][l]) continue; int v = f[i][j][k][l], sign = 0; if (k == 0) sign = -2; if (k == 3) sign = 2; if (j == 1) { if (k == 0) sign = -1; if (k == 2) sign = 1; } if (j == K) { if (k == 0 || k == 2) sign = -1; else sign = 1; } if (!l) { vis[i + 1][j][k][l] = 1; f[i + 1][j][k][l] = max(f[i + 1][j][k][l], v + sign * a[i + 1]); } vis[i + 1][j][k][1] = 1; f[i + 1][j][k][1] = max(f[i + 1][j][k][1], v); for (int w = 0; w <= 1; w++) { int s = (w << 1) | ((k & 2) == 0); sign = 0; if (s == 0) sign = -2; if (s == 3) sign = 2; if (j + 1 == K) { if (s == 0 || s == 2) sign = -1; else sign = 1; } vis[i + 1][j + 1][s][0] = 1; f[i + 1][j + 1][s][0] = max(f[i + 1][j + 1][s][0], v + sign * a[i + 1]); } } int ans = 0; for (int i = 0; i <= 3; i++) ans = max(ans, max(f[n][K][i][1], f[n][K][i][0])); cout << ans; } int main() { cin >> n >> K; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); work(); }
|
`include "project_defines.v"
module bipolar_micro_stepper #(
parameter CLOCK_DIV = 16
)(
input clk,
input rst,
//Control
input i_go,
output o_busy,
input i_stop,
//Position
input [31:0] i_current_position,
output [31:0] o_current_position,
input [7:0] i_step_pos,
output [7:0] o_step_pos,
output [31:0] o_step_count,
output reg o_move_strobe,
//Step Modifiers
input i_continuous,
input i_direction,
input [31:0] i_steps,
input [31:0] i_micro_step_hold,
//Counts
input [31:0] i_current_period,
//Pins
output o_hbridge0_l,
output o_hbridge0_r,
output o_hbridge1_l,
output o_hbridge1_r
);
//Local Parameters
localparam IDLE = 4'h0;
localparam PREPARE_STEP = 4'h1;
localparam PROCESS_STEP = 4'h2;
localparam FINISHED = 4'h3;
localparam PWM_PERIOD = 256;
localparam PWM_STEP_POS_MAX = 16;
//Registers/Wires
reg [3:0] state = IDLE;
reg direction;
reg continuous;
reg [31:0] step_pos;
wire [31:0] in_steps;
wire [31:0] in_micro_steps;
reg [31:0] current_period_count;
reg [31:0] current_position;
reg [31:0] step_count;
reg [31:0] total_step_count;
reg [31:0] micro_step_count ;
reg [31:0] final_micro_step_count ;
wire [3:0] step_path [7:0];
wire [7:0] micro_step_duty [15:0];
wire [31:0] step_inc_map [3:0];
wire [31:0] max_pos_map [3:0];
wire [1:0] micro_step_hbridge_pwm [7:0];
wire [7:0] micro_step_hbridge_dir;
reg micro_step_pwm_en;
wire [31:0] micro_step_pwm_duty;
wire [31:0] micro_step_pwm_period;
wire micro_step_pwm;
wire [31:0] micro_current_period;
reg [31:0] micro_current_period_count;
reg [3:0] hbridge_map;
reg [31:0] pwm_step_pos;
wire pwm_direction;
wire [31:0] steps_left;
wire [31:0] pwm_period;
wire [31:0] ms_step_pwm_duty;
//Submodules
pwm micro_pwm(
.clk (clk ),
.rst (rst ),
.en (micro_step_pwm_en ),
.period (pwm_period ),
.duty_cycle (ms_step_pwm_duty ),
.out (micro_step_pwm )
);
assign pwm_period = PWM_PERIOD << CLOCK_DIV;
assign ms_step_pwm_duty = micro_step_pwm_duty << CLOCK_DIV;
//Asynchronous Logic
assign o_busy = (i_go | (state != IDLE));
assign o_step_pos = step_pos;
assign o_current_position = current_position;
assign steps_left = total_step_count - step_count;
assign step_path[0] = 4'b1000;
assign step_path[1] = 4'b1010;
assign step_path[2] = 4'b0010;
assign step_path[3] = 4'b0110;
assign step_path[4] = 4'b0100;
assign step_path[5] = 4'b0101;
assign step_path[6] = 4'b0001;
assign step_path[7] = 4'b1001;
assign micro_step_duty[0] = 8'h00;
assign micro_step_duty[1] = 8'h18;
assign micro_step_duty[2] = 8'h31;
assign micro_step_duty[3] = 8'h4A;
assign micro_step_duty[4] = 8'h61;
assign micro_step_duty[5] = 8'h78;
assign micro_step_duty[6] = 8'h8D;
assign micro_step_duty[7] = 8'hA1;
assign micro_step_duty[8] = 8'hB4;
assign micro_step_duty[9] = 8'hC5;
assign micro_step_duty[10] = 8'hD4;
assign micro_step_duty[11] = 8'hE0;
assign micro_step_duty[12] = 8'hEB;
assign micro_step_duty[13] = 8'hF4;
assign micro_step_duty[14] = 8'hFA;
assign micro_step_duty[15] = 8'hFD;
assign micro_step_hbridge_pwm[0] = 2'h0;
assign micro_step_hbridge_pwm[1] = 2'h1;
assign micro_step_hbridge_pwm[2] = 2'h3;
assign micro_step_hbridge_pwm[3] = 2'h2;
assign micro_step_hbridge_pwm[4] = 2'h1;
assign micro_step_hbridge_pwm[5] = 2'h0;
assign micro_step_hbridge_pwm[6] = 2'h2;
assign micro_step_hbridge_pwm[7] = 2'h3;
assign micro_step_hbridge_dir[0] = 1'b0; //pos neutral
assign micro_step_hbridge_dir[1] = 1'b1; //pos pos
assign micro_step_hbridge_dir[2] = 1'b0; //neutral pos
assign micro_step_hbridge_dir[3] = 1'b1; //neg pos
assign micro_step_hbridge_dir[4] = 1'b0; //neg neutral
assign micro_step_hbridge_dir[5] = 1'b1; //neg neg
assign micro_step_hbridge_dir[6] = 1'b0; //neutral neg
assign micro_step_hbridge_dir[7] = 1'b1; //pos neg
assign o_hbridge0_l = hbridge_map[3];
assign o_hbridge0_r = hbridge_map[2];
assign o_hbridge1_l = hbridge_map[1];
assign o_hbridge1_r = hbridge_map[0];
assign micro_step_pwm_duty = {24'h0, micro_step_duty[pwm_step_pos]};
assign in_steps = {8'h0, i_steps[31:8]};
assign in_micro_steps = {28'h0, i_steps[7:4]};
assign pwm_direction = (micro_step_hbridge_dir[step_pos] ~^ direction);
assign micro_current_period = (i_current_period >> 4); //divide the step period by 16 so that there is enough time to execute each of the micro step
assign o_step_count = step_count;
//Synchronous Logig
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
step_pos <= 0;
current_position <= 0;
current_period_count <= 0;
step_count <= 0;
total_step_count <= 0;
final_micro_step_count <= 0;
micro_step_count <= 0;
micro_step_pwm_en <= 0;
hbridge_map <= 4'b0000;
direction <= 0;
continuous <= 0;
o_move_strobe <= 0;
end
else begin
o_move_strobe <= 0;
if (micro_current_period_count < micro_current_period) begin
micro_current_period_count <= micro_current_period_count + 1;
end
case (state)
IDLE: begin
hbridge_map <= 4'b0000;
current_position <= i_current_position;
step_pos <= i_step_pos;
current_period_count <= 0;
step_count <= 0;
micro_step_count <= 0;
if (i_go) begin
hbridge_map <= step_path[step_pos];
total_step_count <= in_steps;
final_micro_step_count <= in_micro_steps;
direction <= i_direction;
continuous <= i_continuous;
state <= PREPARE_STEP;
end
end
PREPARE_STEP: begin
if (i_stop || (step_count >= total_step_count)) begin
//we are above the amount of steps given to us, we are done
state <= FINISHED;
end
else begin
current_period_count <= 0;
micro_current_period_count<= 0;
micro_step_pwm_en <= 0;
hbridge_map <= step_path[step_pos];
o_move_strobe <= 1;
state <= PROCESS_STEP;
if (pwm_direction) begin
pwm_step_pos <= 0;
end
else begin
pwm_step_pos <= PWM_STEP_POS_MAX - 1;
end
end
end
PROCESS_STEP: begin
micro_step_pwm_en <= 1;
//Micro Step Count
if (micro_current_period_count >= micro_current_period) begin
o_move_strobe <= 1;
if (pwm_direction) begin
pwm_step_pos <= pwm_step_pos + 1;
end
else begin
pwm_step_pos <= pwm_step_pos - 1;
end
micro_current_period_count <= 0;
end
//Full Step Period Count
if (current_period_count < i_current_period) begin
current_period_count <= current_period_count + 1;
if ((current_period_count + i_micro_step_hold) < i_current_period) begin
hbridge_map[micro_step_hbridge_pwm[step_pos]] <= micro_step_pwm;
end
else begin
hbridge_map <= step_path[step_pos];
end
end
else begin
state <= PREPARE_STEP;
hbridge_map <= step_path[step_pos];
if (direction) begin
//Positive
if (step_pos >= 7) begin
step_pos <= 0;
end
else begin
step_pos <= step_pos + 1;
end
end
else begin
//Negative
if (step_pos == 0) begin
step_pos <= 7;
end
else begin
step_pos <= step_pos - 1;
end
end
if (step_count < total_step_count) begin
micro_step_count <= PWM_STEP_POS_MAX;
end
else if (final_micro_step_count > 0) begin
micro_step_count <= final_micro_step_count;
final_micro_step_count <= 0;
end
else begin
state <= FINISHED;
end
if (!continuous) begin
step_count <= step_count + 1;
end
end
end
FINISHED: begin
hbridge_map <= 4'b0000;
if (!i_go) begin
state <= IDLE;
end
end
default: begin
state <= FINISHED;
end
endcase
if (i_stop) begin
state <= IDLE;
end
end
end
endmodule
|
/*
* freq_gen_tb.v: Test bench for freq_gen.v
* author: Till Mahlburg
* year: 2019
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 1000
`endif
`ifndef M_1000
`define M_1000 1000
`endif
`ifndef D
`define D 1
`endif
`ifndef O_1000
`define O_1000 1000
`endif
module freq_gen_tb ();
reg RST;
reg PWRDWN;
reg period_stable;
reg [31:0] ref_period_length_1000;
reg clk;
wire out;
wire [31:0] out_period_length_1000;
/* resets the high counter module used for frequency checks */
wire [31:0] highs_counted;
integer pass_count;
integer fail_count;
/* adjust according to the number of test cases */
localparam total = 6;
freq_gen dut (
.M_1000(`M_1000),
.D(`D),
.O_1000(`O_1000),
.RST(RST),
.PWRDWN(PWRDWN),
.ref_period_1000(ref_period_length_1000),
.clk(clk),
.out(out),
.out_period_length_1000(out_period_length_1000),
.period_stable(period_stable));
high_counter high_counter (
.clk(out),
.rst(~period_stable),
.count(highs_counted));
initial begin
$dumpfile("freq_gen_tb.vcd");
$dumpvars(0, freq_gen_tb);
RST = 0;
PWRDWN = 0;
period_stable = 0;
clk = 0;
ref_period_length_1000 = 20 * 1000;
pass_count = 0;
fail_count = 0;
#10;
RST = 1;
#10;
if (out === 1'b0) begin
$display("PASSED: RST");
pass_count = pass_count + 1;
end else begin
$display("FAILED: RST");
fail_count = fail_count + 1;
end
period_stable = 1;
RST = 0;
#((ref_period_length_1000 / 1000.0) + 11);
if (out === 1'b1) begin
$display("PASSED: rising edge detection");
pass_count = pass_count + 1;
end else begin
$display("FAILED: rising edge detection");
fail_count = fail_count + 1;
end
#(`WAIT_INTERVAL - ((ref_period_length_1000 / 1000.0) + 11));
/* use 1.0 to calculate floating point numbers */
if ($floor(`WAIT_INTERVAL / highs_counted) == $floor((ref_period_length_1000 / 1000.0) * ((`D * (`O_1000 / 1000.0) * 1.0) / (`M_1000 / 1000.0)))) begin
$display("PASSED: ref period = 20");
pass_count = pass_count + 1;
end else begin
$display("FAILED: ref period = 20");
fail_count = fail_count + 1;
end
period_stable = 0;
ref_period_length_1000 = 10 * 1000;
#`WAIT_INTERVAL;
period_stable = 1;
#`WAIT_INTERVAL;
if ($floor(`WAIT_INTERVAL / highs_counted) == $floor((ref_period_length_1000 / 1000.0) * ((`D * (`O_1000 / 1000.0) * 1.0) / (`M_1000 / 1000.0)))) begin
$display("PASSED: ref period = 10");
pass_count = pass_count + 1;
end else begin
$display("FAILED: ref period = 10");
fail_count = fail_count + 1;
end
period_stable = 0;
ref_period_length_1000 = 5600;
#`WAIT_INTERVAL;
period_stable = 1;
#`WAIT_INTERVAL;
if ($floor(`WAIT_INTERVAL / highs_counted) == $floor((ref_period_length_1000 / 1000.0) * ((`D * (`O_1000 / 1000.0) * 1.0) / (`M_1000 / 1000.0)))) begin
$display("PASSED: ref period = 5.6");
pass_count = pass_count + 1;
end else begin
$display("FAILED: ref period = 5.6");
fail_count = fail_count + 1;
end
if ($floor((`WAIT_INTERVAL + (ref_period_length_1000 / 1000.0)) / highs_counted) == $floor(out_period_length_1000 / 1000.0)) begin
$display("PASSED: period length output");
pass_count = pass_count + 1;
end else begin
$display("FAILED: period length output");
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always #((ref_period_length_1000 / 1000.0) / 2.0) clk <= ~clk;
endmodule
|
/*
-------------------------------------------------------------------------------
-- Title : PS/2 interface
-- Project :
-------------------------------------------------------------------------------
-- File : ps2.v
-- Author(s) : Daniel Quintero <>
-- : Stefan Kristiansson <>
-- : @Wenri <>
-- Created : 2003-04-14
-- Last update: 2014-06-10
-- Platform : verilog 2001
-------------------------------------------------------------------------------
-- Description: PS/2 generic UART for mice/keyboard
-------------------------------------------------------------------------------
-- This code is distributed under the terms and conditions of the
-- GNU General Public License
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2003-04-14 1.0 daniel Created
-- 2011-05-24 x.0 Stefan Bugfixes/improvements and conversion to verilog
-------------------------------------------------------------------------------
*/
module ps2(
input wire clk_i, // Global clk
input wire rst_i, // Global Asinchronous reset
output wire [7:0] data_o, // Data in
input wire [7:0] data_i, // Data out
input wire ibf_clr_i, // Ifb flag clear input
input wire obf_set_i, // Obf flag set input
output wire ibf_o, // Received data available
output wire obf_o, // Data ready to sent
output wire frame_err_o, // Error receiving data
output wire parity_err_o, // Error in received data parity
output wire busy_o, // uart busy
inout wire err_clr_i, // Clear error flags
output wire wdt_o, // Watchdog timer out every 400uS
inout wire ps2_clk_io, // PS2 Clock line
inout wire ps2_data_io // PS2 Data line
);
parameter [2:0]
idle = 3'd1,
write_request = 3'd2,
start = 3'd3,
data = 3'd4,
parity = 3'd5,
stop = 3'd6;
parameter [2:0]
stable = 3'd1,
rise = 3'd2,
fall = 3'd3,
wait_stable = 3'd4;
//parameter DEBOUNCE_TIMEOUT = 200; // clks to debounce the ps2_clk signal
parameter DEBOUNCE_BITS = 8;
//parameter WATCHDOG_TIMEOUT = 19200 / DEBOUNCE_TIMEOUT; // clks to wait 400uS
parameter WATCHDOG_BITS = 8;
reg [2:0] state;
reg [2:0] debounce_state;
reg [DEBOUNCE_BITS-1:0] debounce_cnt;
wire debounce_cao;
reg [1:0] ps2_clk_r; // PS2 clock input registered
wire ps2_clk_syn; // PS2 clock input syncronized
reg ps2_clk_clean; // PS2 clock debounced and clean
wire ps2_clk_fall; // PS2 clock fall edge
wire ps2_clk_rise; // PS2 clock rise edge
reg [1:0] ps2_data_r; // PS2 data input registered
wire ps2_data_syn; // PS2 data input syncronized
reg ps2_clk_out; // PS2 clock output
reg ps2_data_out; // PS2 clock output
reg writing; // read / write cycle flag
reg [2:0] shift_cnt;
wire shift_cao; // Shift counter carry out
reg [8:0] shift_reg;
wire shift_in_read; // Shift register to right
wire shift_in_write; // Shift register to right
wire shift_load; // Shift register parallel load
wire shift_calc_parity; // Shift register set parity
reg [WATCHDOG_BITS-1:0] wdt_cnt;
wire wdt_rst; // watchdog reset
wire wdt_cao; // watchdog carry out
wire shift_parity; // Current parity of shift_reg
reg ibf; // IBF, In Buffer Full
wire obf; // OBF, Out Buffer Full
reg parity_err; // Parity error
reg frame_err; // Frame error
reg [7:0] data_i_reg;
reg [7:0] data_o_reg;
reg obf_set;
// Syncronize input signals
always @(posedge clk_i or negedge rst_i) begin
if (!rst_i) begin // asynchronous reset (active low)
ps2_clk_r <= 0;
ps2_data_r <= 0;
end else begin
ps2_clk_r <= {ps2_clk_io, ps2_clk_r[1]};
ps2_data_r <= {ps2_data_io, ps2_data_r[1]};
end
end
assign ps2_clk_syn = ps2_clk_r[0];
assign ps2_data_syn = ps2_data_r[0];
// clk debounce timer
always @(posedge clk_i or negedge rst_i)
if (!rst_i) // asynchronous reset (active low)
debounce_cnt <= 0;
else
if (ps2_clk_fall | ps2_clk_rise | debounce_cao)
debounce_cnt <= 0;
else
debounce_cnt <= debounce_cnt + 1;
assign debounce_cao = debounce_cnt[DEBOUNCE_BITS-1];
// PS2 clock debounce and edge detector
always @(posedge clk_i or negedge rst_i) begin
if (!rst_i) begin
debounce_state <= stable;
ps2_clk_clean <= 1'b0;
end else begin
case (debounce_state)
stable: begin
if (ps2_clk_clean != ps2_clk_syn) begin
if (ps2_clk_syn)
debounce_state <= rise;
else
debounce_state <= fall;
end
end
wait_stable: begin
if (debounce_cao)
debounce_state <= stable;
end
rise: begin
debounce_state <= wait_stable;
ps2_clk_clean <= 1'b1;
end
fall: begin
debounce_state <= wait_stable;
ps2_clk_clean <= 1'b0;
end
//default:
endcase
end
end
assign ps2_clk_fall = (debounce_state == fall);
assign ps2_clk_rise = (debounce_state == rise);
// PS2 watchdog
always @(posedge clk_i or negedge rst_i)
if (!rst_i) // asynchronous reset (active low)
wdt_cnt <= 0;
else
if (wdt_rst | wdt_cao)
wdt_cnt <= 0;
else if (debounce_cao)
wdt_cnt <= wdt_cnt + 1;
assign wdt_cao = wdt_cnt[WATCHDOG_BITS-1];
assign wdt_rst = ps2_clk_fall;
// Shift register
always @(posedge clk_i or negedge rst_i)
if (!rst_i) // asynchronous reset (active low)
shift_reg <= 0;
else
if (shift_load) begin
shift_reg[7:0] <= data_i_reg;
shift_reg[8] <= 1'b0;
end else if (shift_calc_parity) begin
shift_reg[8] <= ~shift_parity;
end else if (!writing) begin
if (shift_in_read) begin
shift_reg[7:0] <= shift_reg[8:1];
shift_reg[8] <= ps2_data_syn;
end
end else if (writing) begin
if (shift_in_write) begin
shift_reg[7:0] <= shift_reg[8:1];
shift_reg[8] <= 1'b1;
end
end
// Shift counter
always @(posedge clk_i or negedge rst_i)
if (!rst_i) // asynchronous reset (active low)
shift_cnt <= 0;
else
if (state == start)
shift_cnt <= 0;
else if (ps2_clk_fall & (state == data))
shift_cnt <= shift_cnt + 1;
assign shift_cao = (&shift_cnt);
// Odd Parity generator
assign shift_parity = (shift_reg[0] ^
shift_reg[1] ^
shift_reg[2] ^
shift_reg[3] ^
shift_reg[4] ^
shift_reg[5] ^
shift_reg[6] ^
shift_reg[7]);
// Main State Machine
always @(posedge clk_i or negedge rst_i)
if (!rst_i) begin // asynchronous reset (active low)
state <= idle;
writing <= 1'b0;
end else
case (state)
// Waiting for clk
idle: begin
if (obf_set & !writing) begin
state <= write_request;
writing <= 1'b1;
end else if (ps2_clk_fall)
state <= start;
end
// Write request, clk low
write_request: begin
if (wdt_cao)
state <= start;
end
// Clock 1, start bit
start: begin
if (wdt_cao) begin
writing <= 1'b0;
state <= idle;
end else if (ps2_clk_fall)
state <= data;
end
// Clocks 2-9, Data bits (LSB first)
data: begin
if (wdt_cao) begin
writing <= 1'b0;
state <= idle;
end else if (ps2_clk_fall & shift_cao)
state <= parity;
end
// Clock 10, Parity bit
parity: begin
if (wdt_cao) begin
writing <= 1'b0;
state <= idle;
end else if (ps2_clk_fall)
state <= stop;
end
// Clock 11, Stop bit
stop: begin
if (writing) begin
// ack
if ((ps2_clk_fall & !ps2_data_syn) | wdt_cao) begin
state <= idle;
writing <= 1'b0;
end
end else begin
data_o_reg <= shift_reg[7:0];
state <= idle;
end
end
//default:
endcase
// State flags
always @(posedge clk_i or negedge rst_i)
if (!rst_i) begin // asynchronous reset (active low)
ibf <= 1'b0;
parity_err <= 1'b0;
frame_err <= 1'b0;
end else begin
// Parity error flag
if (err_clr_i)
parity_err <= 1'b0;
else if (!writing & state == stop) begin
if (shift_reg[8] != ~shift_parity)
parity_err <= 1'b1;
end
// Frame error flag
if (err_clr_i)
frame_err <= 1'b0;
else if ((state == start | state == data | state == parity) &
wdt_cao)
frame_err <= 1'b1;
// Input Buffer full flag
if (ibf_clr_i)
ibf <= 1'b0;
else if (!writing & state == stop)
if (shift_reg[8] == ~shift_parity)
ibf <= 1'b1;
end
assign obf = writing;
// Shift register control
assign shift_load = (obf_set & state == write_request);
assign shift_calc_parity = (state == start & writing);
assign shift_in_read = (state == data | state == start) ? ps2_clk_fall : 1'b0;
assign shift_in_write = (state == data | state == parity) ? ps2_clk_fall : 1'b0;
// PS2 Registered outputs
always @(posedge clk_i or negedge rst_i)
if (!rst_i) begin // asynchronous reset (active low)
ps2_data_out <= 1'b1;
ps2_clk_out <= 1'b1;
end else begin
// PS2 Data out
if (writing) begin
if (state == write_request | state == start)
ps2_data_out <= 1'b0;
else if (state == data | state == parity)
ps2_data_out <= shift_reg[0];
else
ps2_data_out <= 1'b1;
end
// PS2 Clk out
if (state == write_request)
ps2_clk_out <= 1'b0;
else
ps2_clk_out <= 1'b1;
end
always @(posedge clk_i or negedge rst_i)
if (!rst_i) begin
data_i_reg <= 0;
obf_set <= 1'b0;
end else if (obf_set_i) begin
data_i_reg <= data_i;
obf_set <= 1'b1;
end else if (state == write_request)
obf_set <= 1'b0;
assign data_o = data_o_reg;
assign ibf_o = ibf;
assign obf_o = obf;
assign busy_o = !(state == idle & !writing);
assign parity_err_o = parity_err;
assign frame_err_o = frame_err;
assign wdt_o = wdt_cao;
assign ps2_clk_io = (!ps2_clk_out) ? 1'b0 : 1'bz;
assign ps2_data_io = (!ps2_data_out) ? 1'b0 : 1'bz;
endmodule
|
#include <bits/stdc++.h> using namespace std; int getint() { unsigned int c; int x = 0; while (((c = getchar()) - 0 ) >= 10) { if (c == - ) return -getint(); if (!~c) exit(0); } do { x = (x << 3) + (x << 1) + (c - 0 ); } while (((c = getchar()) - 0 ) < 10); return x; } int n, k; int in[222]; int main() { int i, j, tcc, tc = 1 << 28; for (tcc = 0; tcc < tc; tcc++) { n = getint(), k = getint(); for (i = 0; i < n; i++) in[i] = getint(); int s, t; int res = in[0]; for (s = 0; s < n; s++) for (t = s; t < n; t++) { int sum = 0; vector<int> with; for (i = s; i <= t; i++) sum += in[i], with.push_back(in[i]); vector<int> other; for (i = 0; i < s; i++) other.push_back(in[i]); for (i = t + 1; i < n; i++) other.push_back(in[i]); sort(other.begin(), other.end(), greater<int>()); sort(with.begin(), with.end()); res = max(res, sum); int lm = min(other.size(), with.size()); lm = min(lm, k); for (i = 0; i < lm; i++) { sum += other[i]; sum -= with[i]; res = max(res, sum); } } cout << res << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 77; long long a[N], f[N], l, r; int n, k; bool check(int mid) { for (int i = 1; i <= n; i++) f[i] = 0; f[0] = 1; int pl = 1, pr; for (int i = 1; i <= n; i++) { while (a[i] - a[pl] > mid) pl++; pr = i - k + 1; for (int j = pl; j <= pr; j++) { if (f[j - 1]) { f[i] = 1; break; } else pl++; } } return f[n]; } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); r = max(a[i], r); } for (int i = 1; i <= n; i++) f[i] = 0x3f3f3f3f; sort(a + 1, a + 1 + n); while (l <= r) { int mid = (l + r) / 2; if (check(mid)) r = mid - 1; else l = mid + 1; } printf( %lld , l); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O2111A_BEHAVIORAL_PP_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o2111a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111A_BEHAVIORAL_PP_V
|
`define WIDTH_P 4
`define ELS_P 3
`include "bsg_defines.v"
/********************************** TEST RATIONALE *************************
1. STATE SPACE
Since the values of data inputs have little influence on the functioning
of DUT, they are kept constant and not varied. The select input should be
a one hot code and is varied from 00..1 to 10..0.
2. PARAMETERIZATION
The parameter WIDTH_P is the width of the data input and ELS_P is the
number of inputs to the mux which in this case is equal to the width of the
select input. Since the DUT deals with the data inputs of different widths
similarly, an arbitrary set of tests that include edge cases would suffice.
So a minimum set of tests might be WIDTH_P = 1,2,3,4 and ELS_P = 2,3,4.
***************************************************************************/
module test_bsg
#(
parameter cycle_time_p = 20,
parameter width_p = `WIDTH_P, // width of test input
parameter els_p = `ELS_P,
parameter reset_cycles_lo_p=0,
parameter reset_cycles_hi_p=5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("===========================================================");
$display("testing with ...");
$display("WIDTH_P: %d", width_p);
$display("ELS_P : %d\n", els_p);
end
logic [els_p-1:0][width_p-1:0] test_input_data;
logic [els_p-1:0] test_input_sel;
logic [width_p-1:0] test_output;
logic [`BSG_SAFE_CLOG2(els_p)-1:0] addr;
genvar i;
for(i=0; i<=els_p; ++i)
assign test_input_data[i] = width_p'(i);
always_ff @(posedge clk)
begin
if(reset)
test_input_sel <= els_p'(1);
else
begin
test_input_sel <= (test_input_sel << 1);
if(~|test_input_sel)
begin
$display("=============================================================\n");
$finish;
end
assert (test_output==width_p'(addr))
else $error("mismatch on input %x", test_input_sel);
end
/*$display("test_input_sel: %b, test_output: %b\n"
, test_input_sel, test_output);*/
end
bsg_encode_one_hot #( .width_p(els_p)
) encode_one_hot
( .i (test_input_sel)
, .addr_o(addr)
, .v_o ()
);
bsg_mux_one_hot #( .width_p (width_p)
, .els_p (els_p)
, .harden_p()
) DUT
( .data_i (test_input_data)
, .sel_one_hot_i(test_input_sel)
, .data_o (test_output)
);
/*bsg_nonsynth_ascii_writer #( .width_p (width_p)
, .values_p (2)
, .filename_p ("output.log")
, .fopen_param_p("a+")
, .format_p ("w")
) ascii_writer
( .clk (clk)
, .reset_i(reset)
, .valid_i(1'b1)
, .data_i ({test_output,
width_p'(addr)}
)
);*/
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lights_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/15.0/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2015/02/08 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
`timescale 1 ns / 1 ps
module boxcar_filter_tb();
parameter DATA_WIDTH = 8;
reg clk;
reg signed [DATA_WIDTH-1:0] din;
wire signed [DATA_WIDTH-1:0] dout;
boxcar_filter #(
.DATA_WIDTH(DATA_WIDTH)
)
DUT (
.clk(clk),
.din(din),
.dout(dout)
);
parameter CLK_PERIOD = 8;
initial begin
clk = 1;
din = 0;
#(CLK_PERIOD) din = 1;
#(CLK_PERIOD) din = -1;
#(CLK_PERIOD) din = 10;
#(CLK_PERIOD) din = -2;
#(CLK_PERIOD) din = -5;
#(CLK_PERIOD) din = -6;
#(CLK_PERIOD) din = 0;
#(CLK_PERIOD) din = -1;
#(CLK_PERIOD) din = 10;
#(CLK_PERIOD) din = -2;
#(CLK_PERIOD) din = 1;
#(CLK_PERIOD) din = -1;
#(CLK_PERIOD) din = 10;
#(CLK_PERIOD) din = -2;
#(CLK_PERIOD) din = -5;
#(CLK_PERIOD) din = -6;
#(CLK_PERIOD) din = 0;
#(CLK_PERIOD) din = -1;
#(CLK_PERIOD) din = 10;
#(CLK_PERIOD) din = -2;
#(CLK_PERIOD) din = 1;
#(CLK_PERIOD) din = -1;
#(CLK_PERIOD) din = 10;
#(CLK_PERIOD) din = -2;
#(CLK_PERIOD) din = -5;
#(CLK_PERIOD) din = -6;
#(CLK_PERIOD) din = 0;
#(CLK_PERIOD) din = -1;
#(CLK_PERIOD) din = 10;
#(CLK_PERIOD) din = -2;
$finish;
end
always #(CLK_PERIOD/2) clk = ~clk;
endmodule
|
//Listing 10.1
module ps2_tx
(
input wire clk, reset,
input wire wr_ps2,
input wire [7:0] din,
inout wire ps2d, ps2c,
output reg tx_idle, tx_done_tick
);
// symbolic state declaration
localparam [2:0]
idle = 3'b000,
rts = 3'b001,
start = 3'b010,
data = 3'b011,
stop = 3'b100;
// signal declaration
reg [2:0] state_reg, state_next;
reg [7:0] filter_reg;
wire [7:0] filter_next;
reg f_ps2c_reg;
wire f_ps2c_next;
reg [3:0] n_reg, n_next;
reg [8:0] b_reg, b_next;
reg [13:0] c_reg, c_next;
wire par, fall_edge;
reg ps2c_out, ps2d_out;
reg tri_c, tri_d;
// body
//=================================================
// filter and falling-edge tick generation for ps2c
//=================================================
always @(posedge clk, posedge reset)
if (reset)
begin
filter_reg <= 0;
f_ps2c_reg <= 0;
end
else
begin
filter_reg <= filter_next;
f_ps2c_reg <= f_ps2c_next;
end
assign filter_next = {ps2c, filter_reg[7:1]};
assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
(filter_reg==8'b00000000) ? 1'b0 :
f_ps2c_reg;
assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
//=================================================
// FSMD
//=================================================
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
c_reg <= 0;
n_reg <= 0;
b_reg <= 0;
end
else
begin
state_reg <= state_next;
c_reg <= c_next;
n_reg <= n_next;
b_reg <= b_next;
end
// odd parity bit
assign par = ~(^din);
// FSMD next-state logic
always @*
begin
state_next = state_reg;
c_next = c_reg;
n_next = n_reg;
b_next = b_reg;
tx_done_tick = 1'b0;
ps2c_out = 1'b1;
ps2d_out = 1'b1;
tri_c = 1'b0;
tri_d = 1'b0;
tx_idle = 1'b0;
case (state_reg)
idle:
begin
tx_idle = 1'b1;
if (wr_ps2)
begin
b_next = {par, din};
c_next = 14'h3fff; // 2^13-1
state_next = rts;
end
end
rts: // request to send
begin
ps2c_out = 1'b0;
tri_c = 1'b1;
c_next = c_reg - 1'b1;
if (c_reg==0)
state_next = start;
end
start: // assert start bit
begin
ps2d_out = 1'b0;
tri_d = 1'b1;
if (fall_edge)
begin
n_next = 4'h8;
state_next = data;
end
end
data: // 8 data + 1 parity
begin
ps2d_out = b_reg[0];
tri_d = 1'b1;
if (fall_edge)
begin
b_next = {1'b0, b_reg[8:1]};
if (n_reg == 0)
state_next = stop;
else
n_next = n_reg - 1'b1;
end
end
stop: // assume floating high for ps2d
if (fall_edge)
begin
state_next = idle;
tx_done_tick = 1'b1;
end
endcase
end
// tri-state buffers
assign ps2c = (tri_c) ? ps2c_out : 1'bz;
assign ps2d = (tri_d) ? ps2d_out : 1'bz;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [6:0] mem1d;
reg [6:0] mem2d [5:0];
reg [6:0] mem3d [4:0][5:0];
integer i,j,k;
// Four different test cases for out of bounds
// =
// <=
// Continuous assigns
// Output pin interconnect (also covers cont assigns)
// Each with both bit selects and array selects
initial begin
mem1d[0] = 1'b0;
i=7;
mem1d[i] = 1'b1;
if (mem1d[0] !== 1'b0) $stop;
//
for (i=0; i<8; i=i+1) begin
for (j=0; j<8; j=j+1) begin
for (k=0; k<8; k=k+1) begin
mem1d[k] = k[0];
mem2d[j][k] = j[0]+k[0];
mem3d[i][j][k] = i[0]+j[0]+k[0];
end
end
end
for (i=0; i<5; i=i+1) begin
for (j=0; j<6; j=j+1) begin
for (k=0; k<7; k=k+1) begin
if (mem1d[k] !== k[0]) $stop;
if (mem2d[j][k] !== j[0]+k[0]) $stop;
if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop;
end
end
end
end
integer wi;
wire [31:0] wd = cyc;
reg [31:0] reg2d[6:0];
always @ (posedge clk) reg2d[wi[2:0]] <= wd;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd);
`endif
cyc <= cyc + 1;
if (cyc<10) begin
wi <= 0;
end
else if (cyc==10) begin
wi <= 1;
end
else if (cyc==11) begin
if (reg2d[0] !== 10) $stop;
wi <= 6;
end
else if (cyc==12) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
wi <= 7; // Will be ignored
end
else if (cyc==13) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==14) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; long long arr[t], sum = 0; for (int i = 0; i < t; ++i) { cin >> arr[i]; sum += arr[i]; } if (sum != 0) { cout << YES << endl; cout << 1 << endl; cout << 1 << << t << endl; return 0; } if (t == 1) { if (arr[0] != 0) { cout << YES << endl; cout << 1 << endl; cout << 1 << endl; } else cout << NO << endl; } else { for (int i = 0; i < t; i++) { sum += arr[i]; if (sum != 0) { cout << YES << endl; cout << 2 << endl; cout << 1 << << i + 1 << endl; cout << i + 2 << << t << endl; return 0; } } cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 1e6 + 10; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3f; inline int read() { static char buf[1000000], *p1 = buf, *p2 = buf; register int x = false; register char ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; register bool sgn = false; while (ch != - && (ch < 0 || ch > 9 )) ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; if (ch == - ) sgn = true, ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; while (ch >= 0 && ch <= 9 ) x = (x << 1) + (x << 3) + (ch ^ 48), ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; return sgn ? -x : x; } long long fpow(long long a, int b, int mod) { long long res = 1; for (; b > 0; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long a[N]; double ans[N]; long long sum[N]; int s[N]; int idx = 1; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); sum[i] = sum[i - 1] + a[i]; } for (int i = 1; i <= n; i++) { while (idx > 1 && (sum[i] - sum[s[idx]]) * (i - s[idx - 1]) <= (sum[i] - sum[s[idx - 1]]) * (i - s[idx])) idx--; s[++idx] = i; } for (int i = 2; i <= idx; i++) { double res = 1.0 * (sum[s[i]] - sum[s[i - 1]]) / (s[i] - s[i - 1]); for (int j = 1; j <= s[i] - s[i - 1]; j++) { printf( %.10f n , res); } } return 0; }
|
`default_nettype none
// ============================================================================
module oserdes_test #
(
parameter DATA_WIDTH = 8,
parameter DATA_RATE = "SDR",
parameter ERROR_HOLD =
)
(
// "Hi speed" clock and reset
input wire CLK,
input wire RST,
// OSERDES clocks
input wire CLK1,
input wire CLK2,
// Data pin
inout wire IO_DAT,
// Error indicator
output wire O_ERROR
);
// ============================================================================
// Generate CLK2 and CLKDIV for OSERDES using BUFRs
localparam CLKDIV_DIVIDE =
(DATA_RATE == "SDR" && DATA_WIDTH == 2) ? "2" :
(DATA_RATE == "SDR" && DATA_WIDTH == 3) ? "3" :
(DATA_RATE == "SDR" && DATA_WIDTH == 4) ? "4" :
(DATA_RATE == "SDR" && DATA_WIDTH == 5) ? "5" :
(DATA_RATE == "SDR" && DATA_WIDTH == 6) ? "6" :
(DATA_RATE == "SDR" && DATA_WIDTH == 7) ? "7" :
(DATA_RATE == "SDR" && DATA_WIDTH == 8) ? "8" :
(DATA_RATE == "DDR" && DATA_WIDTH == 4) ? "4" :
(DATA_RATE == "DDR" && DATA_WIDTH == 6) ? "6" :
(DATA_RATE == "DDR" && DATA_WIDTH == 8) ? "8" : "BYPASS";
wire CLKX;
wire CLKDIV;
BUFIO io_buf (.I((DATA_RATE == "DDR") ? CLK2 : CLK1), .O(CLKX));
BUFR #
(
.BUFR_DIVIDE (CLKDIV_DIVIDE)
)
bufr_clkdiv
(
.I (CLK1),
.O (CLKDIV),
.CLR (RST),
.CE (1'd1)
);
// The clock enable signal for the "hi speed" clock domain.
reg clkdiv_r;
wire ce;
always @(posedge CLK)
clkdiv_r <= CLKDIV;
assign ce = clkdiv_r && !CLKDIV;
// ============================================================================
// Data source
reg lfsr_stb;
wire [7:0] lfsr_dat;
lfsr lfsr
(
.CLK (CLK),
.RST (RST),
.CE (ce),
.O (lfsr_dat)
);
always @(posedge CLK)
if (RST)
lfsr_stb <= 1'b0;
else
lfsr_stb <= ce;
// Synchronize generated data wordst to the CLKDIV
reg [7:0] ser_dat;
always @(posedge CLKDIV)
ser_dat <= lfsr_dat;
// ============================================================================
// OSERDES
// OSERDES reset generator (required for it to work properly!)
reg [3:0] ser_rst_sr;
initial ser_rst_sr <= 4'hF;
always @(posedge CLKDIV or posedge RST)
if (RST) ser_rst_sr <= 4'hF;
else ser_rst_sr <= ser_rst_sr >> 1;
wire ser_rst = ser_rst_sr[0];
// OSERDES
wire ser_oq;
wire ser_tq;
OSERDESE2 #
(
.DATA_RATE_OQ (DATA_RATE),
.DATA_WIDTH (DATA_WIDTH),
.DATA_RATE_TQ ((DATA_RATE == "DDR" && DATA_WIDTH == 4) ? "DDR" : "SDR"),
.TRISTATE_WIDTH ((DATA_RATE == "DDR" && DATA_WIDTH == 4) ? 4 : 1)
)
oserdes
(
.CLK (CLKX),
.CLKDIV (CLKDIV),
.RST (ser_rst),
.OCE (1'b1),
.D1 (ser_dat[0]),
.D2 (ser_dat[1]),
.D3 (ser_dat[2]),
.D4 (ser_dat[3]),
.D5 (ser_dat[4]),
.D6 (ser_dat[5]),
.D7 (ser_dat[6]),
.D8 (ser_dat[7]),
.OQ (ser_oq),
.TCE (1'b1),
.T1 (1'b0), // All 0 to keep OBUFT always on.
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TQ (ser_tq)
);
// ============================================================================
// IOB
wire iob_i;
OBUFT obuf
(
.I (ser_oq),
.T (ser_tq),
.O (IO_DAT)
);
IBUF ibuf
(
.I (IO_DAT),
.O (iob_i)
);
// ============================================================================
// Reference data serializer
reg [7:0] ref_sr;
wire ref_o;
always @(posedge CLK)
if (RST)
ref_sr <= 0;
else if (ce)
ref_sr <= lfsr_dat;
else
ref_sr <= ref_sr >> 1;
assign ref_o = ref_sr[0];
// ============================================================================
// Data comparator
comparator #
(
.ERROR_COUNT (16),
.ERROR_HOLD (ERROR_HOLD)
)
comparator
(
.CLK (CLK),
.RST (RST),
.I_DAT_REF (ref_o),
.I_DAT_IOB (iob_i),
.O_ERROR (O_ERROR)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 505, MOD = 1e9 + 7; struct node { node *ch[20], *fail; int cnt, id; node(node* son = NULL) { for (int i = 0; i <= 19; i++) ch[i] = son; fail = son; cnt = id = 0; } } nil, *null = &nil, *root = null, *nd[maxn]; typedef node* P_node; queue<P_node> que; void Build() { root->fail = root; root->id = 0; nd[0] = root; for (int i = 0; i <= 19; i++) if (root->ch[i] != null) { P_node v = root->ch[i]; que.push(v); v->fail = root; } else root->ch[i] = root; while (!que.empty()) { P_node p = que.front(); que.pop(); for (int i = 0; i <= 19; i++) if (p->ch[i] != null) { P_node v = p->ch[i]; que.push(v); v->fail = p->fail->ch[i]; v->cnt += v->fail->cnt; } else p->ch[i] = p->fail->ch[i]; } } int a[maxn], b[maxn], c[maxn], n, m, K, tot; int f[2][205][705][2][2]; int Calc(int a[]) { memset(f, 0, sizeof(f)); f[0][0][0][0][0] = 1; for (int i = 0, o = 0; i <= a[0] - 1; i++, o ^= 1) { memset(f[o ^ 1], 0, sizeof(f[o ^ 1])); for (int j = 0; j <= tot; j++) for (int k = 0; k <= K; k++) for (int t1 = 0; t1 <= 1; t1++) for (int t2 = 0; t2 <= 1; t2++) if (f[o][j][k][t1][t2]) { for (int t = 0; t <= (t2 ? m - 1 : a[i + 1]); t++) { int v = (t1 | (t > 0)) ? nd[j]->ch[t]->id : 0; (f[o ^ 1][v][k + nd[v]->cnt][t1 | (t > 0)] [t2 | (t < a[i + 1])] += f[o][j][k][t1][t2]) %= MOD; } } } int res = 0; for (int i = 0; i <= tot; i++) for (int j = 0; j <= K; j++) for (int k = 0; k <= 1; k++) for (int t = 0; t <= 1; t++) (res += f[a[0] & 1][i][j][k][t]) %= MOD; return res; } int main() { scanf( %d%d%d , &n, &m, &K); scanf( %d , &a[0]); for (int i = 1; i <= a[0]; i++) scanf( %d , &a[i]); scanf( %d , &b[0]); for (int i = 1; i <= b[0]; i++) scanf( %d , &b[i]); a[a[0]]--; for (int i = a[0]; i >= 1; i--) if (a[i] < 0) a[i] += m, a[i - 1]--; nil = node(null); for (int i = 1; i <= n; i++) { int t, x; scanf( %d , &t); P_node now = root; while (t--) { scanf( %d , &x); if (now->ch[x] == null) { now = now->ch[x] = new node(null); now->id = ++tot; nd[tot] = now; } else now = now->ch[x]; } scanf( %d , &x); now->cnt += x; } Build(); printf( %d n , ((Calc(b) - Calc(a)) % MOD + MOD) % MOD); return 0; }
|
#include <bits/stdc++.h> #pragma optimize( , off) #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) #pragma comment(linker, /STACK:36777216 ) const int mod = 1000000007; using namespace std; template <class T> void smin(T& a, T val) { if (a > val) a = val; } template <class T> void smax(T& a, T val) { if (a < val) a = val; } template <typename T> inline std::ostream& operator<<(std::ostream& os, const std::vector<T>& v) { bool first = true; os << [ ; for (auto i : v) { if (!first) os << , ; os << i; first = false; } return os << ] ; } const int N = 1e3 + 10; int n, cnt; std::vector<pair<int, int> > v; bool used[N]; void dfs(int x) { used[x] = 1; for (int i = 0; i < n; ++i) { if (!used[i]) { if (v[x].first == v[i].first or v[x].second == v[i].second) { dfs(i); } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; for (int i = 0; i < n; ++i) { int x, y; cin >> x >> y; v.push_back({x, y}); } for (int i = 0; i < n; ++i) { if (!used[i]) { dfs(i); cnt++; } } cout << max(cnt - 1, 0); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; int m; int sum = 0; int a[100005]; int rec[100005] = {0}; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> a[i]; } for (int i = 0; i < m; i++) { int ss = a[i]; if (rec[ss] == 0) { rec[ss]++; sum++; if (sum == n) { cout << 1; for (int j = 1; j <= n; j++) { rec[j]--; if (rec[j] == 0) { sum--; } } } else { cout << 0; } } else { rec[ss]++; cout << 0; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a >> b; int res = -1, pos = -1, j = 0; for (int i = 0; i < b.size(); i++) { if (a[j] != b[i]) { pos = j; if (res != -1 || a[j + 1] != b[i]) { res = 0; break; } res = 1; j++; } j++; } if (res == -1) res = 1, pos = a.size() - 1; if (res) { vector<int> v; v.push_back(pos); while (pos > 0 && a[--pos] == a[v[0]]) v.push_back(pos); cout << v.size() << endl; for (int i = v.size() - 1; i >= 0; i--) cout << v[i] + 1 << ; cout << endl; } else cout << 0 << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_1_V
`define SKY130_FD_SC_MS__SDFRTN_1_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog wrapper for sdfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtn_1 (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_1_V
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
module qa_wrapper
#(
parameter WDTH = 32
)
(
input wire clk,
input wire reset,
input wire [WDTH-1:0] in_data,
input wire in_nd,
output wire [WDTH-1:0] out_data,
output wire out_nd
);
// Separate the input stream into a sample stream and a message stream.
wire [WDTH-1:0] in_samples;
wire in_samples_nd;
wire [`MSG_WIDTH-1:0] in_msg;
wire in_msg_nd;
wire splitter_error;
wire rst_n;
assign rst_n = ~reset;
sample_msg_splitter #(WDTH) sample_msg_splitter_0
(.clk(clk),
.rst_n(rst_n),
.in_data(in_data),
.in_nd(in_nd),
.out_samples(in_samples),
.out_samples_nd(in_samples_nd),
.out_msg(in_msg),
.out_msg_nd(in_msg_nd),
.error(splitter_error)
);
// The qa module contains the actual blocks that we want to test.
wire [WDTH-1:0] out_samples;
wire out_samples_nd;
wire [`MSG_WIDTH-1:0] out_msg;
wire out_msg_nd;
wire contents_error;
wire [WDTH-1:0] in_samples_shifted;
assign in_samples_shifted = {in_samples[WDTH-3:WDTH/2-1], 1'b0, in_samples[WDTH/2-2: 0], 1'b0};
// FIXME We should be able to turn off the meta info flow.
reg in_m;
wire out_m;
qa_contents #(WDTH, 1) qa_contents_0
(.clk(clk),
.rst_n(rst_n),
.in_data(in_samples_shifted),
.in_nd(in_samples_nd),
.in_m(in_m),
.in_msg(in_msg),
.in_msg_nd(in_msg_nd),
.out_data(out_samples),
.out_nd(out_samples_nd),
.out_m(out_m),
.out_msg(out_msg),
.out_msg_nd(out_msg_nd),
.error(contents_error)
);
// The samples and messages are merged into common stream.
wire combiner_error;
wire [WDTH-1:0] out_samples_shifted;
assign out_samples_shifted = {2'b0, out_samples[WDTH-1 :WDTH/2+1], out_samples[WDTH/2-1 :1]};
wire [WDTH-1:0] almostout_data;
wire almostout_nd;
message_stream_combiner #(2, 1, WDTH, `COMBINER_BUFFER_LENGTH, `LOG_COMBINER_BUFFER_LENGTH, `MAX_PACKET_LENGTH, `MSG_LENGTH_WIDTH) message_stream_combiner_0
(.clk(clk),
.rst_n(rst_n),
.in_data({out_samples_shifted, out_msg}),
.in_nd({out_samples_nd, out_msg_nd}),
.out_data(almostout_data),
.out_nd(almostout_nd),
.error(combiner_error)
);
wire error;
assign error = splitter_error | contents_error | combiner_error;
assign out_nd = (error)?1'b1:almostout_nd;
assign out_data = (error)?`ERRORCODE:almostout_data;
endmodule
|
`define MSG_REQ 1'b1
`define MSG_RESP 1'b0
`define CMD_PA 4'b0000
`define CMD_CL 4'b0001
`define CMD_W 4'b0010
`define CMD_R 4'b0011
`define CMD_S 4'b0100
`define CMD_F 4'b0101
`define CMD_IN 4'b0110
`define CMD_CPD 4'b1000
`define CMD_CPR 4'b1001
`define CMD_CPF 4'b1010
`define CMD_CPS 4'b1011
`define CMD_EN 4'b0001
`define CMD_OK 4'b0010
`define CMD_PE 4'b0011
`define CMD_NO 4'b0100
module iobus(
input clk_sys,
input clk_uart,
input rxd,
output txd,
output zg,
input zw,
input rcl,
output dpa,
input rs,
input rf,
input rok,
input rpe,
input rqb,
input rpn,
input [0:3] rnb,
input [0:15] rad,
input [0:15] rdt,
output dw,
output dr,
output din,
output dok,
output den,
output dpe,
output dpn,
output [0:3] dnb,
output [0:15] dad,
output [0:15] ddt,
input [0:15] w,
input [0:3] rotary_pos,
input [0:9] indicators,
output [0:3] rotary_out,
output rotary_trig,
output [0:15] keys,
output keys_trig,
output [0:3] fn,
output fn_v,
output fn_trig
);
parameter CLK_UART_HZ;
parameter UART_BAUD;
// --- UART --------------------------------------------------------------
wire uart_tx_ready;
wire uart_rx_ready;
wire uart_tx_send;
wire [0:7] uart_rx_byte;
wire [0:7] uart_tx_byte;
uart #(
.baud(UART_BAUD),
.clk_speed(CLK_UART_HZ)
) UART_IOB(
.clk(clk_uart),
.rx_byte(uart_rx_byte),
.rx_ready(uart_rx_ready),
.rxd(rxd),
.send(uart_tx_send),
.tx_byte(uart_tx_byte),
.tx_ready(uart_tx_ready),
.txd(txd)
);
// -----------------------------------------------------------------------
// --- TO FPGA -----------------------------------------------------------
// -----------------------------------------------------------------------
// --- Message receiver --------------------------------------------------
wire rx_ready;
wire rx_r, rx_w, rx_in, rx_pa, rx_ok, rx_pe, rx_en;
wire rx_cpd, rx_cpr, rx_cpf, rx_cps;
wire [0:7] rx_a1;
wire [0:15] rx_a2;
wire [0:15] rx_a3;
msg_rx MSG_RX(
.clk_sys(clk_sys),
.data_in(uart_rx_byte),
.data_in_ready(uart_rx_ready),
.ready(rx_ready),
.r(rx_r),
.w(rx_w),
.in(rx_in),
.pa(rx_pa),
.ok(rx_ok),
.pe(rx_pe),
.en(rx_en),
.cpd(rx_cpd),
.cpr(rx_cpr),
.cpf(rx_cpf),
.cps(rx_cps),
.a1(rx_a1),
.a2(rx_a2),
.a3(rx_a3)
);
// --- PA interrupt driver -----------------------------------------------
assign dpa = rx_ready & rx_pa;
// --- CP input driver ---------------------------------------------------
drv_cp_in DRV_CP_IN(
.ready(rx_ready),
.cpd(rx_cpd),
.cpr(rx_cpr),
.cpf(rx_cpf),
.a1(rx_a1),
.a3(rx_a3),
.rotary_out(rotary_out),
.rotary_trig(rotary_trig),
.keys(keys),
.keys_trig(keys_trig),
.fn(fn),
.fn_v(fn_v),
.fn_trig(fn_trig)
);
// --- CP output driver --------------------------------------------------
wire send_cp = rx_ready & rx_cps;
// --- Bus timeout -------------------------------------------------------
reg [0:4] timeout_cnt = 5'b0;
always @ (posedge clk_sys) begin
if (rok) begin
timeout_cnt <= 5'd0;
end else if (dw | dr | din) begin
if (timeout_cnt != 5'b11111) begin
timeout_cnt <= timeout_cnt + 1'd1;
end
end else begin
timeout_cnt <= 5'd0;
end
end
wire timeout = (timeout_cnt == 5'b11111);
// --- Bus request driver ------------------------------------------------
wire [0:15] ddt_req;
drv_bus_req DRV_BUS_REQ(
.clk_sys(clk_sys),
.ready(rx_ready),
.r(rx_r),
.w(rx_w),
.in(rx_in),
.a1(rx_a1),
.a2(rx_a2),
.a3(rx_a3),
.zw(zw),
.zg(zg),
.ans_any(rok | timeout),
.dw(dw),
.dr(dr),
.din(din),
.dpn(dpn),
.dnb(dnb),
.dad(dad),
.ddt(ddt_req)
);
// --- Bus response driver -----------------------------------------------
wire io_req = (rs | rf) & ~rad[15];
wire [0:15] ddt_resp;
drv_bus_resp DRV_BUS_RESP(
.clk_sys(clk_sys),
.ready(rx_ready),
.ok(rx_ok),
.en(rx_en),
.pe(rx_pe),
.a3(rx_a3),
.req(io_req),
.dok(dok),
.den(den),
.dpe(dpe),
.ddt(ddt_resp)
);
// -----------------------------------------------------------------------
// --- FROM FPGA ---------------------------------------------------------
// -----------------------------------------------------------------------
// --- Bus command encoder -----------------------------------------------
wire [0:7] enc_cmd;
msg_cmd_enc MSG_CMD_ENC(
.cmd(enc_cmd),
.f(rf),
.s(rs),
.r(dr),
.w(dw),
.in(din),
.ok(rok),
.timeout(timeout),
.pe(rpe)
);
// --- Bus receiver ------------------------------------------------------
wire send_req = io_req;
wire send_resp = (rok | timeout) & (dw | dr | din);
wire tx_ena_bus;
wire tx_trig_bus;
wire [0:7] tx_bus_cmd;
wire [0:7] tx_bus_a1;
wire [0:15] tx_bus_a2;
wire [0:15] tx_bus_a3;
recv_bus RECV_BUS(
.clk_sys(clk_sys),
.send_req(send_req),
.send_resp(send_resp),
.tx_ena_bus(tx_ena_bus),
.tx_trig_bus(tx_trig_bus),
.rqb(rqb),
.rpn(rpn),
.rnb(rnb),
.rad(rad),
.rdt(rdt),
.enc_cmd(enc_cmd),
.tx_bus_cmd(tx_bus_cmd),
.tx_bus_a1(tx_bus_a1),
.tx_bus_a2(tx_bus_a2),
.tx_bus_a3(tx_bus_a3)
);
// --- CP status receiver ------------------------------------------------
wire tx_ena_cp;
wire tx_trig_cp;
wire [0:7] tx_cp_cmd;
wire [0:15] tx_cp_a2;
wire [0:15] tx_cp_a3;
recv_cp RECV_CP(
.clk_sys(clk_sys),
.send_cp(send_cp),
.tx_ena_cp(tx_ena_cp),
.w(w),
.indicators(indicators),
.rotary_pos(rotary_pos),
.tx_trig_cp(tx_trig_cp),
.tx_cp_cmd(tx_cp_cmd),
.tx_cp_a2(tx_cp_a2),
.tx_cp_a3(tx_cp_a3)
);
// --- Reset receiver ----------------------------------------------------
wire tx_ena_cl;
wire tx_trig_cl;
wire [0:7] tx_reset_cmd;
recv_cl RECV_CL(
.clk_sys(clk_sys),
.rcl(rcl),
.tx_ena_cl(tx_ena_cl),
.tx_trig_cl(tx_trig_cl),
.tx_reset_cmd(tx_reset_cmd)
);
// --- Mesage sender -----------------------------------------------------
wire [0:7] tx_cmd = tx_bus_cmd | tx_cp_cmd | tx_reset_cmd;
wire [0:7] tx_a1 = tx_bus_a1;
wire [0:15] tx_a2 = tx_bus_a2 | tx_cp_a2;
wire [0:15] tx_a3 = tx_bus_a3 | tx_cp_a3;
msg_tx MSG_TX(
.clk_sys(clk_sys),
.uart_data(uart_tx_byte),
.uart_send(uart_tx_send),
.uart_ready(uart_tx_ready),
.trig({tx_trig_cl, tx_trig_cp, tx_trig_bus}),
.ena({tx_ena_cl, tx_ena_cp, tx_ena_bus}),
.cmd(tx_cmd),
.a1(tx_a1),
.a2(tx_a2),
.a3(tx_a3)
);
// -----------------------------------------------------------------------
assign ddt = ddt_req | ddt_resp;
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
#include <bits/stdc++.h> using namespace std; template <class T> typename T::value_type arr_sum(const T& v, int n) { typename T::value_type sum = 0; for (int i = 0; i < n; ++i) sum += v[i]; return sum; } struct Sync_stdio { Sync_stdio() { cin.tie(NULL); ios_base::sync_with_stdio(false); } } _sync_stdio; int main() { int n, m; cin >> n >> m; vector<int> left; vector<int> right(n); for (int i = 0; i < n; ++i) { int t; cin >> t; left.push_back(t); } sort(left.begin(), left.end()); for (int i = 0, j = n / 2; i < n; ++i, j = (j + 1) % n) { right[i] = left[j]; } int res = 0; for (int i = 0; i < n; ++i) { if (left[i] == right[i]) { ++res; } } cout << n - res << n ; for (int i = 0; i < n; ++i) { cout << left[i] << << right[i] << n ; } }
|
#include <bits/stdc++.h> int main() { int t, a, b, c, d, k, i, pen, pencil; scanf( %d , &t); for (i = 0; i < t; i++) { scanf( %d %d %d %d %d , &a, &b, &c, &d, &k); if (a % c != 0) { pen = (a / c) + 1; } if (a % c == 0) { pen = (a / c); } if (b % d != 0) { pencil = (b / d) + 1; } if (b % d == 0) { pencil = (b / d); } if (pen + pencil <= k) { printf( %d %d n , pen, pencil); } else { printf( -1 n ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; struct custom_hash { size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return x + FIXED_RANDOM; } }; void solve() { long long n; cin >> n; for (long long i = 2; i * i <= n; i++) { if (n % i == 0) { cout << n / i << << n - (n / i) << n ; return; } } cout << 1 << << n - 1 << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, i, x, ans; int main() { cin >> n >> m; x = 1; for (i = 1; i <= m; i++) x = x * 2 % 1000000009; ans = 1; for (i = 1; i <= n; i++) ans = ans * (x - i) % 1000000009; cout << ans; return 0; }
|
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