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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211O_SYMBOL_V
`define SKY130_FD_SC_LP__A211O_SYMBOL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a211o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int infinity = 1e9; int N, M; int A[509][509]; int P[509][509]; int squaresum(int cx, int cy, int k) { int ax = cx - k / 2; int ay = cy - k / 2; int bx = cx + k / 2; int by = cy + k / 2; return P[bx][by] - P[ax - 1][by] - P[bx][ay - 1] + P[ax - 1][ay - 1]; } bool goodk(int i, int j, int k) { k /= 2; return ((i - k >= 1) && (i + k <= N) && (j - k >= 1) && (j + k <= M)); } int main() { scanf( %d %d , &N, &M); for (int i = 1; i <= N; i++) for (int j = 1; j <= M; j++) scanf( %d , &A[i][j]); for (int i = 1; i <= N; i++) for (int j = 1; j <= M; j++) P[i][j] = P[i - 1][j] + P[i][j - 1] - P[i - 1][j - 1] + A[i][j]; int ans = -infinity; for (int i = 2; i <= N - 1; i++) for (int j = 2; j <= M - 1; j++) { int spiral = A[i][j]; for (int k = 3; goodk(i, j, k); k += 2) { spiral = squaresum(i, j, k) - spiral - A[i - k / 2 + 1][j - k / 2]; ans = max(ans, spiral); } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool graf[100][100]; int n, m; bool visited[100]; bool spoken[100]; int stupid; int tab[100]; int main() { ios::sync_with_stdio(false); cin >> n >> m; for (int i = 0; i < n; i++) { int x; cin >> x; if (x == 0) stupid++; for (int j = 0; j < x; j++) { cin >> tab[j]; tab[j]--; spoken[tab[j]] = true; } for (int j = 0; j < x; j++) { for (int q = j + 1; q < x; q++) { graf[tab[j]][tab[q]] = true; graf[tab[q]][tab[j]] = true; } } } queue<int> q; int add = 0; for (int i = 0; i < m; i++) { if (!spoken[i] || visited[i]) continue; q.push(i); visited[i] = true; add++; while (!q.empty()) { int v = q.front(); q.pop(); for (int j = 0; j < m; j++) { if (graf[v][j] && !visited[j]) { visited[j] = true; q.push(j); } } } } if (add > 0) add--; stupid += add; cout << stupid << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:14:47 01/16/2015
// Design Name:
// Module Name: vga_640_480_stripes
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_640_480_stripes(
input wire clk,
input wire clr,
output reg hsync,
output reg vsync,
output reg [9:0] hc,
output reg [9:0] vc,
output reg vidon
);
parameter hpixels = 10'b1100100000, //800
vlines = 10'b1000001001, //521
hbp = 10'b0010010000, //144
hfp = 10'b1100010000, //784
vbp = 10'b0000011111, //31
vfp = 10'b0111111111; //511
reg vsenable; //enable for the vertical counter
//horizontal sync signal counter
always @(posedge clk or posedge clr)
begin
if(clr==1)
hc<=0;
else
begin
if(hc==hpixels-1)
begin //the counter has reached the end of pixel count
hc<=0;
vsenable <=1;//enable the vertical counter to inc
end
else
begin
hc<=hc+1;
vsenable <= 0;
end
end
end
//generate hsync pulse, SP=96, when 0<hc<96, SP is low...
always @ (*)
begin
if(hc<96)
hsync=0;
else
hsync=1;
end
//vertical sync signal counter
always @ (posedge clk or posedge clr)
begin
if(clr==1)
vc<=0;
else
if(vsenable==1)
begin
if(vc==vlines-1)//reset when the number of lines is reached
vc<=0;
else
vc<=vc+1;
end
end
//generate vsync pulse
always @(*)
begin
if(vc<2)
vsync=0;
else
vsync=1;
end
//enable video out when within the porches
always@(*)
begin
if((hc<hfp)&&(hc>hbp)&&(vc<vfp)&&(vc>vbp))
vidon = 1;
else
vidon = 0;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221O_BEHAVIORAL_V
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* IQ joiner
*/
module iq_join #
(
parameter WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI stream inputs
*/
input wire [WIDTH-1:0] input_i_tdata,
input wire input_i_tvalid,
output wire input_i_tready,
input wire [WIDTH-1:0] input_q_tdata,
input wire input_q_tvalid,
output wire input_q_tready,
/*
* AXI stream output
*/
output wire [WIDTH-1:0] output_i_tdata,
output wire [WIDTH-1:0] output_q_tdata,
output wire output_tvalid,
input wire output_tready
);
reg [WIDTH-1:0] i_data_reg = 0;
reg [WIDTH-1:0] q_data_reg = 0;
reg i_valid_reg = 0;
reg q_valid_reg = 0;
assign input_i_tready = ~i_valid_reg | (output_tready & output_tvalid);
assign input_q_tready = ~q_valid_reg | (output_tready & output_tvalid);
assign output_i_tdata = i_data_reg;
assign output_q_tdata = q_data_reg;
assign output_tvalid = i_valid_reg & q_valid_reg;
always @(posedge clk) begin
if (rst) begin
i_data_reg <= 0;
q_data_reg <= 0;
i_valid_reg <= 0;
q_valid_reg <= 0;
end else begin
if (input_i_tready & input_i_tvalid) begin
i_data_reg <= input_i_tdata;
i_valid_reg <= 1;
end else if (output_tready & output_tvalid) begin
i_valid_reg <= 0;
end
if (input_q_tready & input_q_tvalid) begin
q_data_reg <= input_q_tdata;
q_valid_reg <= 1;
end else if (output_tready & output_tvalid) begin
q_valid_reg <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, color[510]; bool g[510][510]; vector<int> nbr[510]; bool dfs(int x, int c) { color[x] = c; for (int i = 0; i < nbr[x].size(); i++) { int y = nbr[x][i]; if (color[y] == c) return 0; if (color[y] == 0 && dfs(y, 3 - c) == 0) return 0; } return 1; } int main() { cin >> n >> m; for (int i = 1; i <= m; i++) { int x, y; cin >> x >> y; g[x][y] = g[y][x] = 1; } for (int i = 1; i < n; i++) for (int j = i + 1; j <= n; j++) if (g[i][j] == 0) { nbr[i].push_back(j); nbr[j].push_back(i); } for (int i = 1; i <= n; i++) { if (color[i] || nbr[i].size() == 0) continue; if (dfs(i, 1) == 0) { puts( No ); return 0; } } for (int i = 1; i < n; i++) for (int j = i + 1; j <= n; j++) if (color[i] + color[j] == 3 && g[i][j]) { puts( No ); return 0; } puts( Yes ); for (int i = 1; i <= n; i++) { if (color[i] == 0) cout << b ; else if (color[i] == 1) cout << a ; else if (color[i] == 2) cout << c ; } return 0; }
|
// Check that the signedness of methods on the built-in enum type is handled
// correctly when calling the method with parenthesis.
module test;
bit failed = 1'b0;
`define check(x) \
if (!(x)) begin \
$display("FAILED(%0d): ", `__LINE__, `"x`"); \
failed = 1'b1; \
end
int unsigned x = 10;
int y = 10;
int z;
enum shortint {
A = -1,
B = -2,
C = -3
} es;
enum bit [15:0] {
X = 65535,
Y = 65534,
Z = 65533
} eu;
initial begin
es = B;
eu = Y;
// These all evaluate as signed
`check($signed(eu.first()) < 0)
`check(es.first() < 0)
`check($signed(eu.last()) < 0)
`check(es.last() < 0)
`check($signed(eu.prev()) < 0)
`check(es.prev() < 0)
`check($signed(eu.next()) < 0)
`check(es.next() < 0)
// These all evaluate as unsigned
`check(eu.first() > 0)
`check({es.first()} > 0)
`check($unsigned(es.first()) > 0)
`check(es.first() > 16'h0)
`check(eu.last() > 0)
`check({es.last()} > 0)
`check($unsigned(es.last()) > 0)
`check(es.last() > 16'h0)
`check(eu.prev() > 0)
`check({es.prev()} > 0)
`check($unsigned(es.prev()) > 0)
`check(es.prev() > 16'h0)
`check(eu.next() > 0)
`check({es.next()} > 0)
`check($unsigned(es.next()) > 0)
`check(es.next() > 16'h0)
// In arithmetic expressions if one operand is unsigned all operands are
// considered unsigned
z = eu.first() + x;
`check(z === 65545)
z = eu.first() + y;
`check(z === 65545)
z = eu.last() + x;
`check(z === 65543)
z = eu.last() + y;
`check(z === 65543)
z = eu.prev() + x;
`check(z === 65545)
z = eu.prev() + y;
`check(z === 65545)
z = eu.next() + x;
`check(z === 65543)
z = eu.next() + y;
`check(z === 65543)
z = es.first() + x;
`check(z === 65545)
z = es.first() + y;
`check(z === 9)
z = es.last() + x;
`check(z === 65543)
z = es.last() + y;
`check(z === 7)
z = es.prev() + x;
`check(z === 65545)
z = es.prev() + y;
`check(z === 9)
z = es.next() + x;
`check(z === 65543)
z = es.next() + y;
`check(z === 7)
// For ternary operators if one operand is unsigned the result is unsigend
z = x ? eu.first() : x;
`check(z === 65535)
z = x ? eu.first() : y;
`check(z === 65535)
z = x ? eu.last() : x;
`check(z === 65533)
z = x ? eu.last() : y;
`check(z === 65533)
z = x ? eu.prev() : x;
`check(z === 65535)
z = x ? eu.prev() : y;
`check(z === 65535)
z = x ? eu.next() : x;
`check(z === 65533)
z = x ? eu.next() : y;
`check(z === 65533)
z = x ? es.first() : x;
`check(z === 65535)
z = x ? es.first() : y;
`check(z === -1)
z = x ? es.last() : x;
`check(z === 65533)
z = x ? es.last() : y;
`check(z === -3)
z = x ? es.prev() : x;
`check(z === 65535)
z = x ? es.prev() : y;
`check(z === -1)
z = x ? es.next() : x;
`check(z === 65533)
z = x ? es.next() : y;
`check(z === -3)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { double x, y, t, val; } pnt[2050]; struct Edge { int u, v, next; } edge[2050 * 2050]; int head[2050], tot = 0; void add(int u, int v) { edge[tot].u = u; edge[tot].v = v; edge[tot].next = head[u]; head[u] = tot++; } double Dist(node x, node y) { return sqrt((x.x - y.x) * (x.x - y.x) + (x.y - y.y) * (x.y - y.y)); } int ru[2050]; double Max(double x, double y) { if (x > y) return x; return y; } int mark[2050]; int n; double dis[2050]; double spfa(int x) { for (int i = 1; i <= n; i++) { mark[i] = false; dis[i] = 0; } queue<int> Q; Q.push(x); dis[x] = pnt[x].val; mark[x] = true; while (!Q.empty()) { int k = Q.front(); Q.pop(); mark[k] = false; for (int i = head[k]; i != -1; i = edge[i].next) { if (dis[edge[i].v] < dis[k] + pnt[edge[i].v].val) { dis[edge[i].v] = dis[k] + pnt[edge[i].v].val; if (mark[edge[i].v] == false) { Q.push(edge[i].v); mark[edge[i].v] = true; } } } } double maxn = dis[x]; for (int i = 1; i <= n; i++) { if (dis[i] > maxn) { maxn = dis[i]; } } return maxn; } int main() { int i, j; while (scanf( %d , &n) != EOF) { for (i = 1; i <= n; i++) { scanf( %lf%lf%lf%lf , &pnt[i].x, &pnt[i].y, &pnt[i].t, &pnt[i].val); } memset(head, -1, sizeof(head)); memset(ru, 0, sizeof(ru)); tot = 0; for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { if (i == j) continue; if (Dist(pnt[i], pnt[j]) + pnt[i].t <= pnt[j].t) { add(i, j); ru[j]++; } } } double maxn = 0; for (i = 1; i <= n; i++) { if (ru[i] == 0) { maxn = Max(maxn, spfa(i)); } } printf( %.7f n , maxn); } return 0; }
|
#include <bits/stdc++.h> int main() { int arr[1001] = {0}; int n, i, others, temp; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &temp); arr[temp]++; } for (i = 0; i < 1001; i++) { if (!arr[i]) continue; others = n - arr[i]; if (arr[i] - others > 1) { puts( NO ); getchar(); getchar(); return 0; } } puts( YES ); getchar(); getchar(); return 0; }
|
module cpu(CLK, RESET, EN_L, Iin, Din, PC, NextPC, DataA, DataB, DataC, DataD, MW);
input CLK;
input RESET;
input EN_L;
input [15:0] Iin;
input [7:0] Din;
output [7:0] PC;
output [7:0] NextPC;
output [7:0] DataA;
output [7:0] DataB;
output [7:0] DataC;
output [7:0] DataD;
output MW;
// comment the two lines out below if you use a submodule to generate PC/NextPC
reg [7:0] PC;
reg [7:0] NextPC;
wire MW;
// ADD YOUR CODE BELOW THIS LINE
wire [2:0] SA;
wire [2:0] SB;
wire [2:0] DR;
wire LD;
wire [7:0] DataA;
wire [7:0] DataB;
wire [7:0] DataC;
wire [7:0] DataD;
wire [7:0] ALUB;
wire [7:0] IMM_EXT;
wire [5:0] IMM;
wire MB;
wire [2:0] FS;
wire MD;
wire HALT;
wire H;
wire [5:0] OFF;
wire MP;
wire [2:0] BS;
wire N;
wire Z;
wire [7:0] OFF_EXT;
registerFile regfile(
.SA(SA),
.SB(SB),
.DR(DR),
.D_IN(DataC),
.LD(LD),
.RESET(RESET),
.DataA(DataA),
.DataB(DataB),
.CLK(CLK)
);
decoder hyperwave(
.INST(Iin),
.DR(DR),
.SA(SA),
.SB(SB),
.IMM(IMM),
.MB(MB),
.FS(FS),
.MD(MD),
.LD(LD),
.MW(MW),
.BS(BS),
.OFF(OFF),
.HALT(HALT)
);
alu aluminum(
.A(DataA),
.B(ALUB),
.OP(FS),
.N(N),
.Z(Z),
.Y(DataD),
.C(),
.V(),
.HEX0(),
.HEX1(),
.HEX2(),
.HEX3(),
.HEX4(),
.HEX5(),
.HEX6(),
.HEX7()
);
signExtend theExtendables(
.IN(IMM),
.OUT(IMM_EXT)
);
eight_to_one_mux #(.WIDTH(1)) brancher(
.A(Z),
.B(~Z),
.C(~N),
.D(N),
.E(1'b0),
.F(1'b0),
.G(1'b0),
.H(1'b0),
.SEL(BS),
.Y(MP)
);
halt_logic halting_problem(
.CLK(CLK),
.HALT(HALT),
.EN_L(EN_L),
.H(H)
);
assign OFF_EXT[7] = OFF[5];
assign OFF_EXT[6:1] = OFF;
assign OFF_EXT[0] = 1'b0;
assign ALUB = MB ? IMM_EXT : DataB;
assign DataC = MD ? Din : DataD;
always @(posedge CLK) begin
if (RESET) begin
PC = 8'b0;
end else begin
PC = NextPC;
end
end
always @(*) begin
if (H) begin
NextPC = PC;
end else if (MP) begin
NextPC = PC + 8'd2 + OFF_EXT;
end else begin
NextPC = PC + 8'd2;
end
end
// ADD YOUR CODE ABOVE THIS LINE
endmodule
|
module test_serial_device(reset, clk, data, tx, rts, cts, end_flag);
input reset;
input clk;
output tx;
output [7:0] data;
output rts;
input cts;
output end_flag;
reg tx;
reg [7:0] data;
wire rts;
reg end_flag;
reg [7:0] buffer;
reg [3:0] data_cnt;
reg [4:0] multi_cnt;
reg sending;
reg start_bit;
reg stop_bit;
reg stop_bit_running;
assign rts = ~sending;
always @(negedge reset) begin
buffer <= 8'b0;
data <= 8'b0;
multi_cnt <= 8'b0;
sending <= 1'b0;
end_flag <= 1'b0;
tx <= 1'b1;
end
always @(posedge clk) begin
if (reset) begin
if (sending) begin
multi_cnt <= multi_cnt + 5'b1;
if (multi_cnt == 5'b11111) begin
if (start_bit) begin
tx <= 1'b0;
start_bit <= 1'b0;
end else if (stop_bit) begin
if (stop_bit_running) begin
sending <= 1'b0;
data[7:0] <= data[7:0] + 8'b1;
if (data[7:0] == 8'b11111111) begin
end_flag <= 1'b1;
end
end else begin
tx <= 1'b1;
stop_bit_running <= 1'b1;
end
end else begin
tx <= buffer[0];
buffer[7:0] <= { 1'b0, buffer[7:1] };
data_cnt <= data_cnt + 3'b1;
if (data_cnt == 3'b111) begin
stop_bit <= 1'b1;
stop_bit_running <= 1'b0;
end
end
end
end else begin
if (cts) begin
sending <= 1'b1;
multi_cnt <= 5'b0;
start_bit <= 1'b1;
stop_bit <= 1'b0;
stop_bit_running <= 1'b0;
data_cnt <= 3'b0;
buffer[7:0] <= data[7:0];
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tt, c = 0; cin >> tt; while (tt) { int n = tt; set<int> data; while (n % 2 == 0) { data.insert(2); n = n / 2; } for (int i = 3; i <= sqrt(n); i = i + 2) { while (n % i == 0) { data.insert(i); n = n / i; } } if (n > 2) data.insert(n); if (data.size() == 2) { c++; } tt--; } cout << c << endl; cerr << Time : << (float)clock() / CLOCKS_PER_SEC << s << endl; return 0; }
|
// hub
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
`include "hub_mem.v"
module hub
(
input clk_cog,
input ena_bus,
input nres,
input [7:0] bus_sel,
input bus_r,
input bus_e,
input bus_w,
input [1:0] bus_s,
input [15:0] bus_a,
input [31:0] bus_d,
output reg [31:0] bus_q,
output bus_c,
output [7:0] bus_ack,
output reg [7:0] cog_ena,
output [7:0] ptr_w,
output [27:0] ptr_d,
output reg [7:0] cfg
);
// latch bus signals from cog[n]
reg rc;
reg ec;
reg wc;
reg [1:0] sc;
reg [15:0] ac;
reg [31:0] dc;
always @(posedge clk_cog)
if (ena_bus)
rc <= bus_r;
always @(posedge clk_cog or negedge nres)
if (!nres)
ec <= 1'b0;
else if (ena_bus)
ec <= bus_e;
always @(posedge clk_cog)
if (ena_bus)
wc <= bus_w;
always @(posedge clk_cog)
if (ena_bus)
sc <= bus_s;
always @(posedge clk_cog)
if (ena_bus)
ac <= bus_a;
always @(posedge clk_cog)
if (ena_bus)
dc <= bus_d;
// connect hub memory to signals from cog[n-1]
wire mem_w = ec && ~&sc && wc;
wire [3:0] mem_wb = sc[1] ? 4'b1111 // wrlong
: sc[0] ? ac[1] ? 4'b1100 : 4'b0011 // wrword
: 4'b0001 << ac[1:0]; // wrbyte
wire [31:0] mem_d = sc[1] ? dc // wrlong
: sc[0] ? {2{dc[15:0]}} // wrword
: {4{dc[7:0]}}; // wrbyte
wire [31:0] mem_q;
hub_mem hub_mem_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.w (mem_w),
.wb (mem_wb),
.a (ac[15:2]),
.d (mem_d),
.q (mem_q) );
// latch bus signals from cog[n-1]
reg rd;
reg ed;
reg [1:0] sd;
reg [1:0] ad;
always @(posedge clk_cog)
if (ena_bus)
rd <= !rc && ac[15];
always @(posedge clk_cog or negedge nres)
if (!nres)
ed <= 1'b0;
else if (ena_bus)
ed <= ec;
always @(posedge clk_cog)
if (ena_bus)
sd <= sc;
always @(posedge clk_cog)
if (ena_bus)
ad <= ac[1:0];
// set bus output according to cog[n-2]
wire [31:0] ramq = !rd ? mem_q : {mem_q[03], mem_q[07], mem_q[21], mem_q[12], // unscramble rom data if cog loading
mem_q[06], mem_q[19], mem_q[04], mem_q[17],
mem_q[20], mem_q[15], mem_q[08], mem_q[11],
mem_q[00], mem_q[14], mem_q[30], mem_q[01],
mem_q[23], mem_q[31], mem_q[16], mem_q[05],
mem_q[09], mem_q[18], mem_q[25], mem_q[02],
mem_q[28], mem_q[22], mem_q[13], mem_q[27],
mem_q[29], mem_q[24], mem_q[26], mem_q[10]};
always @(posedge clk_cog)
bus_q <= sd[1] ? sd[0] ? {29'b0, sys_q} // cogid/coginit/locknew
: ramq // rdlong
: sd[0] ? ramq >> {ad[1], 4'b0} & 32'h0000FFFF // rdword
: ramq >> {ad[1:0], 3'b0} & 32'h000000FF; // rdbyte
assign bus_c = sys_c;
// generate bus acknowledge for cog[n-2]
assign bus_ack = ed ? {bus_sel[1:0], bus_sel[7:2]} : 8'b0;
// sys common logic
//
// ac in dc in num sys_q sys_c
// -----------------------------------------------------------------------------------------
// 000 CLKSET config(8) - - -
// 001 COGID - - [n-1] -
// 010 COGINIT ptr(28),newx,id(3) id(3)/newx id(3)/newx all
// 011 COGSTOP -,id(3) id(3) id(3) -
// 100 LOCKNEW - newx newx all
// 101 LOCKRET -,id(3) id(3) id(3) -
// 110 LOCKSET -,id(3) id(3) id(3) lock_state[id(3)]
// 111 LOCKCLR -,id(3) id(3) id(3) lock_state[id(3)]
wire sys = ec && (&sc);
wire [7:0] enc = ac[2] ? lock_e : cog_e;
wire all = &enc; // no free cogs/locks
wire [2:0] newx = &enc[3:0] ? &enc[5:4] ? enc[6] ? 3'b111 // x1111111 -> 111
: 3'b110 // x0111111 -> 110
: enc[4] ? 3'b101 // xx011111 -> 101
: 3'b100 // xxx01111 -> 100
: &enc[1:0] ? enc[2] ? 3'b011 // xxxx0111 -> 011
: 3'b010 // xxxxx011 -> 010
: enc[0] ? 3'b001 // xxxxxx01 -> 001
: 3'b000; // xxxxxxx0 -> 000
wire [2:0] num = ac[2:0] == 3'b010 && dc[3] || ac[2:0] == 3'b100 ? newx : dc[2:0];
wire [7:0] num_dcd = 1'b1 << num;
// cfg
always @(posedge clk_cog or negedge nres)
if (!nres)
cfg <= 8'b0;
else if (ena_bus && sys && ac[2:0] == 3'b000)
cfg <= dc[7:0];
// cogs
reg [7:0] cog_e;
wire cog_start = sys && ac[2:0] == 3'b010 && !(dc[3] && all);
always @(posedge clk_cog or negedge nres)
if (!nres)
cog_e <= 8'b00000001;
else if (ena_bus && sys && ac[2:1] == 2'b01)
cog_e <= cog_e & ~num_dcd | {8{!ac[0]}} & num_dcd;
always @(posedge clk_cog or negedge nres)
if (!nres)
cog_ena <= 8'b0;
else if (ena_bus)
cog_ena <= cog_e & ~({8{cog_start}} & num_dcd);
assign ptr_w = {8{cog_start}} & num_dcd;
assign ptr_d = dc[31:4];
// locks
reg [7:0] lock_e;
reg [7:0] lock_state;
always @(posedge clk_cog or negedge nres)
if (!nres)
lock_e <= 8'b0;
else if (ena_bus && sys && ac[2:1] == 2'b10)
lock_e <= lock_e & ~num_dcd | {8{!ac[0]}} & num_dcd;
always @(posedge clk_cog)
if (ena_bus && sys && ac[2:1] == 2'b11)
lock_state <= lock_state & ~num_dcd | {8{!ac[0]}} & num_dcd;
wire lock_mux = lock_state[dc[2:0]];
// output
reg [2:0] sys_q;
reg sys_c;
always @(posedge clk_cog)
if (ena_bus && sys)
sys_q <= ac[2:0] == 3'b001 ? { bus_sel[7] || bus_sel[6] || bus_sel[5] || bus_sel[0], // cogid
bus_sel[7] || bus_sel[4] || bus_sel[3] || bus_sel[0],
bus_sel[6] || bus_sel[4] || bus_sel[2] || bus_sel[0] }
: num; // others
always @(posedge clk_cog)
if (ena_bus && sys)
sys_c <= ac[2:1] == 2'b11 ? lock_mux // lockset/lockclr
: all; // others
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
tpub p1 (.clk(clk), .i(32'd1));
tpub p2 (.clk(clk), .i(32'd2));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
$c("publicTop();");
`endif
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task publicTop;
// verilator public
// We have different optimizations if only one of something, so try it out.
$write("Hello in publicTop\n");
endtask
endmodule
module tpub (
input clk,
input [31:0] i);
reg [23:0] var_long;
reg [59:0] var_quad;
reg [71:0] var_wide;
reg var_bool;
// verilator lint_off BLKANDNBLK
reg [11:0] var_flop;
// verilator lint_on BLKANDNBLK
reg [23:0] got_long /*verilator public*/;
reg [59:0] got_quad /*verilator public*/;
reg [71:0] got_wide /*verilator public*/;
reg got_bool /*verilator public*/;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
// cyc==1 is in top level
if (cyc==2) begin
publicNoArgs;
publicSetBool(1'b1);
publicSetLong(24'habca);
publicSetQuad(60'h4444_3333_2222);
publicSetWide(72'h12_5678_9123_1245_2352);
var_flop <= 12'habe;
end
if (cyc==3) begin
if (1'b1 != publicGetSetBool(1'b0)) $stop;
if (24'habca != publicGetSetLong(24'h1234)) $stop;
if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop;
if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop;
end
if (cyc==4) begin
publicGetBool(got_bool);
if (1'b0 != got_bool) $stop;
publicGetLong(got_long);
if (24'h1234 != got_long) $stop;
publicGetQuad(got_quad);
if (60'h123_4567_89ab != got_quad) $stop;
publicGetWide(got_wide);
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
end
//
`ifdef VERILATOR_PUBLIC_TASKS
if (cyc==11) begin
$c("publicNoArgs();");
$c("publicSetBool(true);");
$c("publicSetLong(0x11bca);");
$c("publicSetQuad(VL_ULL(0x66655554444));");
$c("publicSetFlop(0x321);");
//Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);");
end
if (cyc==12) begin
$c("got_bool = publicGetSetBool(true);");
$c("got_long = publicGetSetLong(0x11bca);");
$c("got_quad = publicGetSetQuad(VL_ULL(0xaaaabbbbcccc));");
end
if (cyc==13) begin
$c("{ bool gb; publicGetBool(gb); got_bool=gb; }");
if (1'b1 != got_bool) $stop;
$c("publicGetLong(got_long);");
if (24'h11bca != got_long) $stop;
$c("{ vluint64_t qq; publicGetQuad(qq); got_quad=qq; }");
if (60'haaaa_bbbb_cccc != got_quad) $stop;
$c("{ WData gw[3]; publicGetWide(gw); VL_ASSIGN_W(72,got_wide,gw); }");
if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop;
//Below doesn't work, because we're calling it inside the loop that sets var_flop
// if (12'h321 != var_flop) $stop;
end
if (cyc==14) begin
if ($c32("publicInstNum()") != i) $stop;
end
`endif
end
end
task publicEmpty;
// verilator public
begin end
endtask
task publicNoArgs;
// verilator public
$write("Hello in publicNoArgs\n");
endtask
task publicSetBool;
// verilator public
input in_bool;
var_bool = in_bool;
endtask
task publicSetLong;
// verilator public
input [23:0] in_long;
reg [23:0] not_long;
begin
not_long = ~in_long; // Test that we can have local variables
var_long = ~not_long;
end
endtask
task publicSetQuad;
// verilator public
input [59:0] in_quad;
var_quad = in_quad;
endtask
task publicSetFlop;
// verilator public
input [11:0] in_flop;
var_flop = in_flop;
endtask
task publicSetWide;
// verilator public
input [71:0] in_wide;
var_wide = in_wide;
endtask
task publicGetBool;
// verilator public
output out_bool;
out_bool = var_bool;
endtask
task publicGetLong;
// verilator public
output [23:0] out_long;
out_long = var_long;
endtask
task publicGetQuad;
// verilator public
output [59:0] out_quad;
out_quad = var_quad;
endtask
task publicGetWide;
// verilator public
output [71:0] out_wide;
out_wide = var_wide;
endtask
function publicGetSetBool;
// verilator public
input in_bool;
begin
publicGetSetBool = var_bool;
var_bool = in_bool;
end
endfunction
function [23:0] publicGetSetLong;
// verilator public
input [23:0] in_long;
begin
publicGetSetLong = var_long;
var_long = in_long;
end
endfunction
function [59:0] publicGetSetQuad;
// verilator public
input [59:0] in_quad;
begin
publicGetSetQuad = var_quad;
var_quad = in_quad;
end
endfunction
function [71:0] publicGetSetWide;
// Can't be public, as no wide return types in C++
input [71:0] in_wide;
begin
publicGetSetWide = var_wide;
var_wide = in_wide;
end
endfunction
`ifdef VERILATOR_PUBLIC_TASKS
function [31:0] publicInstNum;
// verilator public
publicInstNum = i;
endfunction
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void gg(T &res) { res = 0; T fh = 1; char ch = getchar(); while ((ch > 9 || ch < 0 ) && ch != - ) ch = getchar(); if (ch == - ) fh = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) res = res * 10 + ch - 0 , ch = getchar(); res *= fh; } inline int gi() { int x; gg(x); return x; } inline long long gl() { long long x; gg(x); return x; } const int MAXN = 610; const int MAXM = 200010; const int INF = 1e9; const int BIG = 1e7; int bt = 1, b[MAXN], NEXT[MAXM], to[MAXM], val[MAXM]; inline void add(int x, int y, int z) { NEXT[++bt] = b[x]; b[x] = bt; to[bt] = y; val[bt] = z; NEXT[++bt] = b[y]; b[y] = bt; to[bt] = x; val[bt] = 0; } int T, dis[MAXN], q[MAXN]; bool fc() { for (int i = 1; i <= T; i++) dis[i] = 0; dis[0] = 1; int l = 1, r = 0; q[++r] = 0; while (l <= r) { int x = q[l++]; for (int i = b[x]; i; i = NEXT[i]) { if (!val[i] || dis[to[i]]) continue; dis[to[i]] = dis[x] + 1; if (to[i] == T) return 1; q[++r] = to[i]; } } return 0; } int dfs(int x, int M) { if (x == T) return M; int ans = 0; for (int i = b[x]; i; i = NEXT[i]) { if (!val[i] || dis[x] + 1 != dis[to[i]]) continue; int r = dfs(to[i], min(val[i], M - ans)); val[i] -= r; val[i ^ 1] += r; if ((ans += r) == M) return ans; } dis[x] = -1; return ans; } int main() { int n = gi(); T = n + n + 1; for (int i = 1; i <= n; i++) for (int t = gi(); t--;) add(i, n + gi(), INF); long long ans = 0; for (int i = 1; i <= n; i++) { int x = BIG - gi(); ans -= x; add(0, i, x); add(n + i, T, BIG); } while (fc()) ans += dfs(0, INF); printf( %I64d , ans); return 0; }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
assign valid_test_expr = ~((^test_expr) ^ (^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if ((^(test_expr)) != 1'b1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression does not exhibit odd parity");
end
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @(posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
reg [width-1:0] prev_test_expr;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_SANITY_ON) begin //sanity coverage
if (test_expr != prev_test_expr) begin
ovl_cover_t("test_expr_change covered");
end
prev_test_expr <= test_expr;
end //sanity coverage
end // OVL_COVER_NONE
end
else begin
`ifdef OVL_INIT_REG
prev_test_expr <= {width{1'b0}};
`endif
end
end //always
`endif // OVL_COVER_ON
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long s = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) f *= c == - ? -1 : 1, c = getchar(); while (c >= 0 && c <= 9 ) s = s * 10 + c - 0 , c = getchar(); return s * f; } struct edge { int from, nxt, to; long long val; }; struct graph { edge e[1000005 << 1]; int head[2000005], ind[2000005], tot; inline void addedge(int u, int v, long long w) { ind[v]++; e[++tot] = (edge){u, head[u], v, w}, head[u] = tot; } } G; class SCC : public graph { stack<int> s; int pre[2000005], low[2000005], dfn; bool vis[2000005]; void dfs(int u) { pre[u] = low[u] = ++dfn; s.push(u); for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to; if (!pre[v]) dfs(v), low[u] = min(low[u], low[v]); else if (!scc[v]) low[u] = min(low[u], pre[v]); } if (low[u] == pre[u]) { int x; cnt++; do x = s.top(), s.pop(), scc[x] = cnt; while (x != u); } } public: int cnt, scc[2000005]; inline void tarjan(int n) { for (int i = 1; i <= n; i++) if (!pre[i]) dfs(i); } inline void init() { memset(head, 0, sizeof(head)); memset(pre, 0, sizeof(pre)); memset(low, 0, sizeof(low)); memset(scc, 0, sizeof(scc)); tot = dfn = cnt = 0; while (!s.empty()) s.pop(); } } G1; inline long long calc(long long x) { long long t = sqrt(2 * x + 0.25) - 0.5; return x + t * x - (t + 1) * (t + 2) * t / 6; } int n, m, s; long long val[2000005], dis[2000005]; bool vis[2000005]; queue<int> q; int main() { n = read(), m = read(); for (register int i = (1); i <= (m); i++) { int u = read(), v = read(); long long w = read(); G1.addedge(u, v, w); } G1.tarjan(n); s = G1.scc[read()]; for (register int i = (1); i <= (m); i++) { edge e = G1.e[i]; int u = G1.scc[e.from], v = G1.scc[e.to]; if (u == v) val[u] += calc(e.val); else G.addedge(u, v, e.val); } int N = G1.cnt; memset(dis, -1, sizeof(dis)); q.push(s), dis[s] = val[s], vis[s] = 1; while (!q.empty()) { int u = q.front(); q.pop(); vis[u] = 0; for (int i = G.head[u]; i; i = G.e[i].nxt) { edge e = G.e[i]; int v = e.to; if (dis[v] < dis[u] + e.val + val[v]) { dis[v] = dis[u] + e.val + val[v]; if (!vis[v]) q.push(v), vis[v] = 1; } } } for (register int i = (1); i <= (N); i++) dis[0] = max(dis[0], dis[i]); cout << dis[0]; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long GCD(long long a, long long b) { if (b == 0) return a; return (a % b == 0 ? b : GCD(b, a % b)); } long long POW(long long base, long long exp) { long long val; val = 1; while (exp > 0) { if (exp % 2 == 1) { val = (val * base) % 1000000007; } base = (base * base) % 1000000007; exp = exp / 2; } return val; } int a[100005]; int pos[100005]; int main() { int n, i, c, mx; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (i = 1; i <= n; i++) { pos[a[i]] = i; } mx = 0; for (i = 1; i <= n; i++) { c = 1; while (i < n && pos[i + 1] > pos[i]) { i++; c++; } mx = max(mx, c); } printf( %d n , n - mx); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e5 + 7; const long long inf = 0x3f3f3f3f3f3f3f; const long long mod = 20000311; int n; vector<int> a(100), b(100); vector<int> step[100], ves[100]; void solve(int n) { int st = 0; for (int i = 0; i < step[n].size(); i++) { ves[i].clear(); for (int j = st; j < st + step[n][i]; j++) ves[i].push_back(a[j]); st += step[n][i]; } a.clear(); for (int i = step[n].size() - 1; i >= 0; i--) for (auto j : ves[i]) a.push_back(j); } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i], b[a[i]] = i; if (n == 1) { cout << 0 << n ; return 0; } step[1].push_back(b[1]), step[1].push_back(n - b[1]); solve(1); int flag = n % 2 == 0; for (int go = 2; go + flag <= n; go++) { if (go % 2 == 0) { for (int i = 1; i < go; i++) step[go].push_back(1); int cnt = 1; while (a[cnt] != go) cnt++; if (cnt - go + 2) step[go].push_back(cnt - go + 2); if (n - cnt - 1) step[go].push_back(n - cnt - 1); solve(go); } else { int cnt = n - 1; while (a[cnt] != go) cnt--; if (cnt) step[go].push_back(cnt); if (n - go + 1 - cnt) step[go].push_back(n - go + 1 - cnt); for (int i = 1; i < go; i++) step[go].push_back(1); solve(go); } } int tot = 0, st = 1; if (b[1] == 0) st = 2; cout << n - flag - st + 1 << n ; for (int i = st; i <= n - flag; i++) { cout << step[i].size() << ; for (auto j : step[i]) cout << j << ; cout << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41OI_M_V
`define SKY130_FD_SC_LP__A41OI_M_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41oi_m (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41oi_m (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41OI_M_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = (int)1010; set<int> ans; int n, m; char a[MAXN][MAXN]; int posk[MAXN]; int posG[MAXN]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; if (a[i][j] == S ) { posk[i] = j; } if (a[i][j] == G ) { posG[i] = j; } } } for (int i = 0; i < n; i++) { if (posG[i] > posk[i]) { cout << -1; return 0; } else { ans.insert((int)posG[i] - posk[i] + 1); } } cout << ans.size(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; string s[55]; vector<int> getRow(int x) { vector<int> R; for (int i = 1; i <= m; i++) if (s[x][i] == # ) R.push_back(i); return R; } vector<int> getCol(int x) { vector<int> C; for (int i = 1; i <= n; i++) if (s[i][x] == # ) C.push_back(i); return C; } int Viz[55]; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) { string t; cin >> t; s[i] = . + t + . ; } int nope = 0; for (int i = 1; i <= n && !nope; i++) { if (!Viz[i]) { vector<int> V, R; int ok = 0; for (int j = 1; j <= m; j++) { if (s[i][j] == # ) { R.push_back(j); if (!ok) V = getCol(j), ok = 1; else { vector<int> U = getCol(j); if (U != V) nope = 1; } } } for (int j : V) { Viz[j] = 1; vector<int> Row = getRow(j); if (R != Row) { nope = 1; } } } } if (nope) cout << No ; else cout << Yes ; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> inline ostream& operator<<(ostream& os, const pair<T1, T2>& p) { return os << ( << p.first << , << p.se << ) ; } template <typename T1, typename T2> inline ostream& operator<<(ostream& os, const map<T1, T2>& c) { bool first = true; os << [ ; for (typeof((c).begin()) it = (c).begin(); it != (c).end(); ++it) { if (!first) os << , ; os << *it; first = false; } return os << ] ; } template <typename T> inline ostream& operator<<(ostream& os, const vector<T>& v) { bool first = true; os << [ ; for (long long i = (0); i <= (((int)(v).size()) - 1); i += (1)) { if (!first) os << , ; os << v[i]; first = false; } return os << ] ; } template <typename T> inline ostream& operator<<(ostream& os, const set<T>& c) { bool first = true; os << [ ; for (typeof((c).begin()) it = (c).begin(); it != (c).end(); ++it) { if (!first) os << , ; os << *it; first = false; } return os << ] ; } const int dx4[] = {-1, 0, 0, +1}; const int dx8[] = {-1, -1, -1, 0, 0, +1, +1, +1}; const int dy4[] = {0, -1, +1, 0}; const int dy8[] = {-1, 0, +1, -1, +1, -1, 0, +1}; unsigned long long m; bool first; vector<int> r, l; int main() { int(n); scanf( %d , &(n)); cin >> m; cerr << ( m ) << = << (m) << endl; m--; r.push_back(n); n--; for (long long i = (0); i <= (n - 1); i += (1)) if (m & (1LL << i)) r.push_back(n - i); else l.push_back(n - i); bool first = true; for (long long i = (((int)(l).size()) - 1); i >= (0); i -= (1)) { if (!first) cout << ; first = false; cout << l[i]; } for (long long i = (0); i <= (((int)(r).size()) - 1); i += (1)) { if (!first) cout << ; first = false; cout << r[i]; } cout << endl; return 0; }
|
module Computer_ControlUnit_InstructionMemory(
output reg [WORD_WIDTH-1:0] INSTR_out,
input [COUNTER_WIDTH-1:0] COUNTER_in
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SB_WIDTH+SA_WIDTH+11;
parameter COUNTER_WIDTH = 4;
always@(COUNTER_in)
begin
case(COUNTER_in)
//16'h0000: INSTR_out = 16'b000_0000_000_000_000; //
16'h0000: INSTR_out = 16'b100_1100_000_000_011; // LDI R0 <- 3
16'h0001: INSTR_out = 16'b100_1100_001_000_111; // LDI R1 <- 7
16'h0002: INSTR_out = 16'b000_0000_010_000_XXX; // MOVA R2 <- R0
16'h0003: INSTR_out = 16'b000_1100_011_XXX_001; // MOVB R3 <- R1
16'h0004: INSTR_out = 16'b000_0010_100_000_001; // ADD R4 <- R0;R1
16'h0005: INSTR_out = 16'b000_0101_101_011_100; // SUB R5 <- R3;R4
16'h0006: INSTR_out = 16'b110_0000_000_101_011; // BRZ R5;3
16'h0007: INSTR_out = 16'b110_0001_000_101_011; // BRN R5;3
16'h000A: INSTR_out = 16'b111_0000_110_000_001; // JMP R0;
default: INSTR_out = 16'b0;
endcase
end
endmodule
|
/**
* testbench.v
*
*/
module testbench();
localparam width_p = 32;
localparam ring_width_p = width_p + 1;
localparam rom_addr_width_p = 32;
logic clk;
logic reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(10)
) clock_gen (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
logic v_li;
logic [width_p-1:0] a_li;
logic signed_li;
logic ready_lo;
logic v_lo;
logic [width_p-1:0] z_lo;
logic yumi_li;
bsg_fpu_i2f #(
.e_p(8)
,.m_p(23)
) dut (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_li)
,.a_i(a_li)
,.signed_i(signed_li)
,.ready_o(ready_lo)
,.v_o(v_lo)
,.z_o(z_lo)
,.yumi_i(yumi_li)
);
logic tr_v_li;
logic [ring_width_p-1:0] tr_data_li;
logic tr_ready_lo;
logic tr_v_lo;
logic [ring_width_p-1:0] tr_data_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [ring_width_p+4-1:0] rom_data;
logic done_lo;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(tr_v_li)
,.data_i(tr_data_li)
,.ready_o(tr_ready_lo)
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(done_lo)
,.error_o()
);
assign {signed_li, a_li} = tr_data_lo;
bsg_fpu_trace_rom #(
.width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
) rom (
.addr_i(rom_addr)
,.data_o(rom_data)
);
assign tr_data_li = {
1'b0
, z_lo
};
assign v_li = tr_v_lo;
assign tr_yumi_li = tr_v_lo & ready_lo;
assign tr_v_li = v_lo;
assign yumi_li = v_lo & tr_ready_lo;
initial begin
wait(done_lo);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[100][40]; char b[100][40]; int at[1445], use[100], ok[100], idx[100], pos[100], sum[100], cnt; int dp[43205], ans_dd, ans_hh, ans_mm; int pt[43205][100]; void run_to(int t) { while (1) { int next_dd = ans_dd; int next_hh = ans_hh; int next_mm = ans_mm; if (++next_mm == 60) { next_mm = 0; if (++next_hh == 24) { next_hh = 0; next_dd++; } } if ((next_dd - 1) * cnt + at[next_hh * 60 + next_mm] >= t) break; ans_dd = next_dd; ans_hh = next_hh; ans_mm = next_mm; } } void output(int t, int i, int cnt) { if (~i) { int x = pt[t][i]; if (~x) { output(t - use[idx[x]], i - 1, cnt + 1); run_to(t - use[idx[x]] + 1); printf( %d %d %02d:%02d , x + 1, ans_dd, ans_hh, ans_mm); run_to(t); printf( %d %02d:%02d n , ans_dd, ans_hh, ans_mm); } else { output(t, i - 1, cnt); } } else { printf( %d n , cnt); } } int main() { int m, n, all, hh, mm; scanf( %d%d%d , &m, &n, &all); for (int i = 0; i < m; i++) scanf( %s , a[i]); for (int i = 0; i < m; i++) scanf( %d , use + i); for (int i = 0; i < 4; i++) { scanf( %d:%d- , &hh, &mm); int st = hh * 60 + mm; scanf( %d:%d , &hh, &mm); int ed = hh * 60 + mm; for (int x = st; x <= ed; x++) at[x] = -1; } for (int x = 0; x < 1440; x++) if (~at[x]) at[x] = cnt++; all *= at[1440] = cnt; for (int x = 1439; ~x; x--) if (at[x] < 0) at[x] = at[x + 1]; for (int i = 0; i < n; i++) { scanf( %s , b[i]); for (idx[i] = 0; idx[i] < m; idx[i]++) if (!strcmp(b[i], a[idx[i]])) break; if (idx[i] != m) ok[i] = 1; scanf( %d%d:%d%d , pos + i, &hh, &mm, sum + i); pos[i] = (pos[i] - 1) * cnt + at[hh * 60 + mm]; } for (int i = 0; i < n; i++) { int k = -1; for (int j = 0; j < n; j++) if (ok[j] && (k < 0 || pos[j] < pos[k])) k = j; for (int x = all; ~x; x--) pt[x][i] = -1; for (int x = all; ~x; x--) { int t = x + use[idx[k]]; if (t <= pos[k] && sum[k] + dp[x] > dp[t]) { dp[t] = sum[k] + dp[x]; pt[t][i] = k; } } ok[k] = 0; } int x = max_element(dp, dp + all + 1) - dp; printf( %d n , dp[x]); output(x, n - 1, 0); }
|
#include <bits/stdc++.h> int main() { int t, a, b, i, temp; scanf( %d , &t); for (i = 1; i <= t; i++) { scanf( %d %d , &a, &b); if (b > a) { temp = a; a = b; b = temp; } while ((a * a) < 2 * a * b) { a++; } printf( %d n , a * a); } }
|
// Certain arithmetic operations between a signal of width n and a constant can be directly mapped
// to a single k-LUT (where n <= k). This is preferable to normal alumacc techmapping process
// because for many targets, arithmetic techmapping creates hard logic (such as carry cells) which often
// cannot be optimized further.
//
// TODO: Currently, only comparisons with 1-bit output are mapped. Potentially, all arithmetic cells
// with n <= k inputs should be techmapped in this way, because this shortens the critical path
// from n to 1 by avoiding carry chains.
(* techmap_celltype = "$lt $le $gt $ge" *)
module _90_lut_cmp_ (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_CONSTMSK_A_ = 0;
parameter _TECHMAP_CONSTVAL_A_ = 0;
parameter _TECHMAP_CONSTMSK_B_ = 0;
parameter _TECHMAP_CONSTVAL_B_ = 0;
function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
input integer width;
input integer operation;
input integer swap;
input integer sign;
input integer operand;
integer n, i_var, i_cst, lhs, rhs, o_bit;
begin
gen_lut = width'b0;
for (n = 0; n < (1 << width); n++) begin
if (sign)
i_var = n[width-1:0];
else
i_var = n;
i_cst = operand;
if (swap) begin
lhs = i_cst;
rhs = i_var;
end else begin
lhs = i_var;
rhs = i_cst;
end
if (operation == 0)
o_bit = (lhs < rhs);
if (operation == 1)
o_bit = (lhs <= rhs);
if (operation == 2)
o_bit = (lhs > rhs);
if (operation == 3)
o_bit = (lhs >= rhs);
gen_lut = gen_lut | (o_bit << n);
end
end
endfunction
generate
localparam operation =
_TECHMAP_CELLTYPE_ == "$lt" ? 0 :
_TECHMAP_CELLTYPE_ == "$le" ? 1 :
_TECHMAP_CELLTYPE_ == "$gt" ? 2 :
_TECHMAP_CELLTYPE_ == "$ge" ? 3 :
-1;
if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
wire _TECHMAP_FAIL_ = 1;
else if (&_TECHMAP_CONSTMSK_B_)
\$lut #(
.WIDTH(A_WIDTH),
.LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })
) _TECHMAP_REPLACE_ (
.A(A),
.Y(Y)
);
else if (&_TECHMAP_CONSTMSK_A_)
\$lut #(
.WIDTH(B_WIDTH),
.LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })
) _TECHMAP_REPLACE_ (
.A(B),
.Y(Y)
);
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long cnt, prime[100], pcnt; long long flg; long long gcd(long long a, long long b) { if (!b) return a; return gcd(b, a % b); } long long search(long long a, long long b) { if (!b) return 0; long long d = gcd(a, b); a /= d; b /= d; long long minn = 1ll << 60; for (int i = 1; i <= cnt; i++) if (a % prime[i] == 0) minn = min(minn, b % prime[i]); if (minn == 1ll << 60) return b; return minn + search(a, b - minn); } int main() { long long a, b; scanf( %I64d%I64d , &a, &b); long long A = a; for (long long i = 2; i * i <= A; i++) { if (a % i == 0) { while (a % i == 0) { a /= i; } prime[++cnt] = i; } } if (a > prime[cnt]) prime[++cnt] = a; if (a == A) { printf( %I64d , A > b ? b : b % A + (b - b % A) / A); return 0; } long long ans = search(A, b); printf( %I64d , ans); }
|
// Nexys2 version of rautanoppa, teknohog's hwrng
`include "main_pll.v"
`include "../common_hdl/hwrandom_core.v"
`include "../common_hdl/uart_transmitter.v"
`include "../common_hdl/ringosc.v"
`ifdef DISPLAY
`include "raw7seg.v"
module hwrandom (osc_clk, TxD, reset, segment, anode, disp_switch);
`else
module hwrandom (osc_clk, TxD, reset);
`endif
input reset;
input osc_clk;
wire clk;
output TxD;
parameter comm_clk_frequency = 50_000_000;
main_pll pll_blk (.CLKIN_IN(osc_clk), .CLK0_OUT(clk));
// 73, 101 are good for Nexys2 500k, 137 is too much, 131 seems best
parameter NUM_RINGOSCS = 131;
`ifdef DISPLAY
wire [31:0] disp_word;
hwrandom_core #(.NUM_RINGOSCS(NUM_RINGOSCS), .comm_clk_frequency(comm_clk_frequency)) hwc (.clk(clk), .TxD(TxD), .reset(reset), .disp_word(disp_word));
// Debug: show something in 7seg at slow sampling
output [7:0] segment;
output [3:0] anode;
input disp_switch;
wire [7:0] segment_data;
// inverted signals, so 1111.. to turn it off
assign segment = disp_switch? segment_data : {8{1'b1}};
raw7seg disp(.clk(clk), .segment(segment_data), .anode(anode), .word(disp_word));
`else
hwrandom_core #(.NUM_RINGOSCS(NUM_RINGOSCS), .comm_clk_frequency(comm_clk_frequency)) hwc (.clk(clk), .TxD(TxD), .reset(reset));
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; long long b[200005]; int main() { int t; cin>>t; while(t--) { map<long long ,int >q; int n; scanf( %d ,&n); for(int i=1;i<=n+2;i++) { scanf( %lld ,&b[i]); q[b[i]]++; } sort(b+1,b+1+2+n); long long sum=0; for(int i=1;i<=n+1;i++) { sum+=b[i]; } long long c=sum-b[n+2]; q[b[n+2]]--; if(q[c]) { q[c]--; for(auto x:q) { for(int i=0;i<x.second;i++) { cout<<x.first<< ; } } cout<<endl; } else { long long s=0; for(int i=1;i<=n;i++) { s+=b[i]; } if(b[n+1]==s) { for(int i=1;i<=n;i++) { cout<<b[i]<< ; } cout<<endl; } else cout<<-1<<endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int i, n, fl = 0; cin >> n; int *a = new int[n]; for (i = 0; i < n; ++i) { cin >> a[i]; } sort(a, a + n); for (i = 1; i < n; ++i) { if (a[i] == a[i - 1]) { fl = 1; break; } } if (fl == 1) { cout << YES n ; } else { cout << NO n ; } } }
|
#include <bits/stdc++.h> using namespace std; long long mod_factorial[100005]; long long mod_inv_factorial[100005]; long long binpow(long long a, long long b) { long long res = 1LL; while (b) { if (b & 1) { res = (res * a); } a = (a * a); b >>= 1; } return res; } long long binpowmod(long long a, long long b, long long p) { long long res = 1LL; while (b) { if (b & 1) { res = (res * 1LL * a) % 1000000007; } a = (a * 1LL * a) % 1000000007; b >>= 1; } return res; } long long mod_inverse(long long a) { return binpowmod(a, 1000000007 - 2, 1000000007); } void precomputefact() { mod_factorial[0] = 1; for (int i = 1; i <= 1e5; i++) { mod_factorial[i] = (i * 1LL * mod_factorial[i - 1]) % 1000000007; } mod_inv_factorial[0] = 1; for (int i = 1; i <= 1e5; i++) { mod_inv_factorial[i] = ((mod_inv_factorial[i - 1]) * 1LL * mod_inverse(i)) % 1000000007; } } long long modbinomial(long long n, long long k, long long p) { long long ans = mod_factorial[n] * mod_inv_factorial[n - k] % 1000000007 * mod_inv_factorial[k] % 1000000007; return ans; } void solve() { int n; cin >> n; vector<pair<int, int>> temp; function<bool(pair<int, int>, pair<int, int>)> comp = [](pair<int, int> a, pair<int, int> b) { if (a.first < b.first) { return true; } else if (a.first == b.first) { if (a.second > b.second) { return true; } } return false; }; for (int i = 0; i < n; i++) { int l, r; cin >> l >> r; temp.push_back(make_pair(l, r)); } sort(temp.begin(), temp.end(), comp); for (int i = 0; i < temp.size(); i++) { int f = temp[i].first; int s = temp[i].second; if (f == s) { cout << f << << s << << f << n ; } else { if (f == temp[i + 1].first) { cout << f << << s << << temp[i + 1].second + 1 << n ; } else if (s == temp[i + 1].second) { cout << f << << s << << temp[i + 1].first - 1 << n ; } } } cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long testcase; cin >> testcase; while (testcase--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, _m, ans = 0; map<string, int> m; string s[1010], u[1010], v[1010]; int main() { cin >> n >> _m; for (int i = 1; i <= n; i++) cin >> s[i]; sort(s + 1, s + n + 1); for (int i = 1; i <= n; i++) m[s[i]] = i - 1; for (int i = 1; i <= _m; i++) cin >> u[i] >> v[i]; for (int i = 1; i <= (1 << n); i++) { bool flag = 1; for (int j = 1; j <= _m; j++) if (((i - 1) & (1 << m[u[j]])) && ((i - 1) & (1 << m[v[j]]))) flag = 0; if (flag && __builtin_popcount(ans) < __builtin_popcount(i - 1)) ans = i - 1; } cout << __builtin_popcount(ans) << n ; for (int i = 1; i <= n; i++) if (ans & (1 << (i - 1))) cout << s[i] << n ; return 0; }
|
//----------------------------------------------------------------------------
// bfm_system_tb.v - module
//----------------------------------------------------------------------------
//
// ***************************************************************************
// ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
// ** **
// ** Xilinx, Inc. **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
// ** FOR A PARTICULAR PURPOSE. **
// ** **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: bfm_system_tb.v
// Version: 1.00.a
// Description: Testbench logic.
// Date: Tue Jun 24 19:32:08 2014 (by Create and Import Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------
`timescale 1 ns / 100 fs
//testbench defines
`define RESET_PERIOD 200
`define CLOCK_PERIOD 10
`define INIT_DELAY 400
//user slave defines
`define SLAVE_BASE_ADDR 32'h30000000
`define SLAVE_REG_OFFSET 32'h00000000
`define SLAVE_RESET_ADDR 32'h00000100
`define SLAVE_SOFT_RESET 32'h0000000A
//Response type defines
`define RESPONSE_OKAY 2'b00
//AMBA 4 defines
`define MAX_BURST_LENGTH 1
`define PROT_BUS_WIDTH 3
`define ADDR_BUS_WIDTH 32
`define RESP_BUS_WIDTH 2
module bfm_system_tb
(
); // bfm_system_tb
// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_NUM_REG = 4;
parameter C_SLV_DWIDTH = 32;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------
// -- Testbench nets declartions added here, as needed for testbench logic
reg rst_n;
reg sys_clk;
integer number_of_bytes;
integer i;
integer j;
reg [C_SLV_DWIDTH-1 : 0] test_data;
reg [`ADDR_BUS_WIDTH-1 : 0] mtestAddr;
reg [`PROT_BUS_WIDTH-1 : 0] mtestProtection;
reg [C_SLV_DWIDTH-1 : 0] rd_data;
reg [`RESP_BUS_WIDTH-1 : 0] response;
//----------------------------------------------------------------------------
// Instantiate bfm_system
//----------------------------------------------------------------------------
bfm_system
dut(.sys_reset(rst_n),.sys_clk(sys_clk));
//----------------------------------------------------------------------------
// Reset block
//----------------------------------------------------------------------------
initial begin
rst_n = 1'b0;
#`RESET_PERIOD rst_n = 1'b1;
end
//----------------------------------------------------------------------------
// Simple Clock Generator
//----------------------------------------------------------------------------
initial sys_clk = 1'b0;
always #`CLOCK_PERIOD sys_clk = !sys_clk;
//----------------------------------------------------------------------------
// Simple testbench logic
//----------------------------------------------------------------------------
initial begin
//Wait for end of reset
wait(rst_n == 0) @(posedge sys_clk);
wait(rst_n == 1) @(posedge sys_clk);
#`INIT_DELAY mtestProtection = 0;
$display("----------------------------------------------------");
$display("Full Registers write followed by a full Registers read");
$display("----------------------------------------------------");
number_of_bytes = (C_SLV_DWIDTH/8);
for( i = 0 ; i <4; i = i+1) begin
for(j = 0 ; j < number_of_bytes ; j = j+1)
test_data[j*8 +: 8] = j+(i*number_of_bytes);
mtestAddr = `SLAVE_BASE_ADDR + `SLAVE_REG_OFFSET + i*number_of_bytes;
$display("Writing to Slave Register addr=0x%h",mtestAddr, " data=0x%h",test_data);
SINGLE_WRITE(mtestAddr,test_data,mtestProtection,4'b1111, response);
end
for( i = 0 ; i <4; i = i+1) begin
for(j=0 ; j < number_of_bytes ; j = j+1)
test_data[j*8 +: 8] = j+(i*number_of_bytes);
mtestAddr = `SLAVE_BASE_ADDR + `SLAVE_REG_OFFSET + i*number_of_bytes;
SINGLE_READ(mtestAddr,rd_data,mtestProtection,response);
$display("Reading from Slave Register addr=0x%h",mtestAddr, " data=0x%h",rd_data);
COMPARE_DATA(test_data,rd_data);
end
$display("----------------------------------------------------");
$display("Soft Reseting of peripheral and Full Register read");
$display("----------------------------------------------------");
test_data = `SLAVE_SOFT_RESET;
mtestAddr = `SLAVE_BASE_ADDR + `SLAVE_RESET_ADDR;
SINGLE_WRITE(mtestAddr,test_data,mtestProtection,4'b1111, response);
test_data = 0;
for( i = 0 ; i <4; i = i+1) begin
for(j=0 ; j < number_of_bytes ; j = j+1)
mtestAddr = `SLAVE_BASE_ADDR + `SLAVE_REG_OFFSET + i*number_of_bytes;
SINGLE_READ(mtestAddr,rd_data,mtestProtection,response);
$display("Reading from Slave Register addr=0x%h",mtestAddr, " data=0x%h",rd_data);
COMPARE_DATA(test_data,rd_data);
end
$display("----------------------------------------------------");
$display("Peripheral Verification Completed Successfully");
$display("----------------------------------------------------");
end
//----------------------------------------------------------------------------
// SINGLE_WRITE : SINGLE_WRITE(Address, Data,protection,strobe,response)
//----------------------------------------------------------------------------
task automatic SINGLE_WRITE;
input [`ADDR_BUS_WIDTH-1 : 0] address;
input [C_SLV_DWIDTH-1 : 0] data;
input [`PROT_BUS_WIDTH-1 : 0] prot;
input [3:0] strobe;
output[`RESP_BUS_WIDTH-1 : 0] response;
begin
fork
dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.SEND_WRITE_ADDRESS(address,prot);
dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.SEND_WRITE_DATA(strobe, data);
dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.RECEIVE_WRITE_RESPONSE(response);
join
CHECK_RESPONSE_OKAY(response);
end
endtask
//----------------------------------------------------------------------------
// SINGLE_READ : SINGLE_READ(Address, Data,Protection,strobe,respone)
//----------------------------------------------------------------------------
task automatic SINGLE_READ;
input [`ADDR_BUS_WIDTH-1 : 0] address;
output [C_SLV_DWIDTH-1 : 0] data;
input [`PROT_BUS_WIDTH-1 : 0] prot;
output[`RESP_BUS_WIDTH-1 : 0] response;
begin
dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.SEND_READ_ADDRESS(address,prot);
dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.RECEIVE_READ_DATA(data,response);
CHECK_RESPONSE_OKAY(response);
end
endtask
//----------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY(response)
//----------------------------------------------------------------------------
//Description: This task check if the return response is equal to OKAY
//----------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH FAILED! Response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h", response);
$stop;
end
end
endtask
//----------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_DATA(expected,actual)
//----------------------------------------------------------------------------
//Description: This task checks if the actual data is equal to the expected data
//----------------------------------------------------------------------
task automatic COMPARE_DATA;
input [(C_SLV_DWIDTH*(`MAX_BURST_LENGTH+1))-1:0] expected;
input [(C_SLV_DWIDTH*(`MAX_BURST_LENGTH+1))-1:0] actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH FAILED! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
$stop;
end
if (actual !== expected) begin
$display("TESTBENCH FAILED! Data expected is not equal to actual.","\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
$stop;
end
end
endtask
endmodule
|
`timescale 1 ns / 1 ps
module axis_accumulator #
(
parameter integer S_AXIS_TDATA_WIDTH = 16,
parameter integer M_AXIS_TDATA_WIDTH = 32,
parameter integer CNTR_WIDTH = 16,
parameter AXIS_TDATA_SIGNED = "FALSE",
parameter CONTINUOUS = "FALSE"
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] cfg_data,
// Slave side
output wire s_axis_tready,
input wire [S_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [M_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [M_AXIS_TDATA_WIDTH-1:0] int_tdata_reg, int_tdata_next;
reg [M_AXIS_TDATA_WIDTH-1:0] int_accu_reg, int_accu_next;
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
reg int_tvalid_reg, int_tvalid_next;
reg int_tready_reg, int_tready_next;
wire [M_AXIS_TDATA_WIDTH-1:0] sum_accu_wire;
wire int_comp_wire, int_tvalid_wire;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_tdata_reg <= {(M_AXIS_TDATA_WIDTH){1'b0}};
int_tvalid_reg <= 1'b0;
int_tready_reg <= 1'b0;
int_accu_reg <= {(M_AXIS_TDATA_WIDTH){1'b0}};
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
end
else
begin
int_tdata_reg <= int_tdata_next;
int_tvalid_reg <= int_tvalid_next;
int_tready_reg <= int_tready_next;
int_accu_reg <= int_accu_next;
int_cntr_reg <= int_cntr_next;
end
end
assign int_comp_wire = int_cntr_reg < cfg_data;
assign int_tvalid_wire = int_tready_reg & s_axis_tvalid;
generate
if(AXIS_TDATA_SIGNED == "TRUE")
begin : SIGNED
assign sum_accu_wire = $signed(int_accu_reg) + $signed(s_axis_tdata);
end
else
begin : UNSIGNED
assign sum_accu_wire = int_accu_reg + s_axis_tdata;
end
endgenerate
generate
if(CONTINUOUS == "TRUE")
begin : CONTINUOUS
always @*
begin
int_tdata_next = int_tdata_reg;
int_tvalid_next = int_tvalid_reg;
int_tready_next = int_tready_reg;
int_accu_next = int_accu_reg;
int_cntr_next = int_cntr_reg;
if(~int_tready_reg & int_comp_wire)
begin
int_tready_next = 1'b1;
end
if(int_tvalid_wire & int_comp_wire)
begin
int_cntr_next = int_cntr_reg + 1'b1;
int_accu_next = sum_accu_wire;
end
if(int_tvalid_wire & ~int_comp_wire)
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_accu_next = {(M_AXIS_TDATA_WIDTH){1'b0}};
int_tdata_next = sum_accu_wire;
int_tvalid_next = 1'b1;
end
if(m_axis_tready & int_tvalid_reg)
begin
int_tvalid_next = 1'b0;
end
end
end
else
begin : STOP
always @*
begin
int_tdata_next = int_tdata_reg;
int_tvalid_next = int_tvalid_reg;
int_tready_next = int_tready_reg;
int_accu_next = int_accu_reg;
int_cntr_next = int_cntr_reg;
if(~int_tready_reg & int_comp_wire)
begin
int_tready_next = 1'b1;
end
if(int_tvalid_wire & int_comp_wire)
begin
int_cntr_next = int_cntr_reg + 1'b1;
int_accu_next = sum_accu_wire;
end
if(int_tvalid_wire & ~int_comp_wire)
begin
int_tready_next = 1'b0;
int_tdata_next = sum_accu_wire;
int_tvalid_next = 1'b1;
end
if(m_axis_tready & int_tvalid_reg)
begin
int_tvalid_next = 1'b0;
end
end
end
endgenerate
assign s_axis_tready = int_tready_reg;
assign m_axis_tdata = int_tdata_reg;
assign m_axis_tvalid = int_tvalid_reg;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx2,tune=native ) #pragma GCC optimize( unroll-loops ) using namespace std; using ll = long long; using ld = long double; using vi = vector<int>; using vvi = vector<vi>; using pi = pair<ll, ll>; const int mod = 1e9 + 7; const ll inf = 1e18; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); ll n, k, mn[40][100100], sm[40][100100], p[40][100100]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; for (int i = 0; i < n; i++) cin >> p[0][i]; for (int i = 0; i < n; i++) cin >> mn[0][i], sm[0][i] = mn[0][i]; for (int i = 1; i < 34; i++) { for (int j = 0; j < n; j++) { p[i][j] = p[i - 1][p[i - 1][j]]; sm[i][j] = sm[i - 1][j] + sm[i - 1][p[i - 1][j]]; mn[i][j] = min(mn[i - 1][j], mn[i - 1][p[i - 1][j]]); } } for (int i = 0; i < n; i++) { ll u = i, m = LLONG_MAX, s = 0; for (int j = 34; j--;) { if (k & (1ll << j)) { m = min(m, mn[j][u]); s = s + sm[j][u]; u = p[j][u]; } } cout << s << << m << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; const int inf = 0x3f3f3f3f; const int mod = 1e9 + 7; int n, m, k, t, mx, mi, x, y, dx, dy, idx, cnt, tot, sum, res, flag, st; vector<int> e[maxn]; void dfs(int u, int pre, int dep, int op) { if (dep > mx) { mx = dep; idx = u; } if (u == y && op) { if (dep <= dx) { flag = 1; return; } } for (int v : e[u]) { if (v == pre) continue; dfs(v, u, dep + 1, op); } } int main() { scanf( %d , &t); while (t--) { flag = 0; scanf( %d %d %d %d %d , &n, &x, &y, &dx, &dy); for (int i = 1; i <= n; i++) { e[i].clear(); } for (int i = 1; i < n; i++) { int u, v; scanf( %d %d , &u, &v); e[u].push_back(v); e[v].push_back(u); } mx = 0; dfs(x, 0, 0, 1); if (flag) { puts( Alice ); continue; } mx = 0; dfs(idx, 0, 0, 0); if (2 * dx >= mx || dy <= 2 * dx) { puts( Alice ); } else { puts( Bob ); } } return 0; }
|
//
// fixed for 9.1 jan 21 2010 cruben
//
`include "timescale.v"
`include "i2c_master_defines.v"
module i2c_opencores
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
scl_pad_io, sda_pad_io, spi_miso_pad_i
);
parameter dedicated_spi = 0;
// Common bus signals
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
// Slave signals
input [2:0] wb_adr_i; // WISHBONE address input
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
input wb_we_i; // WISHBONE write enable input
input wb_stb_i; // WISHBONE strobe input
//input wb_cyc_i; // WISHBONE cycle input
output wb_ack_o; // WISHBONE acknowledge output
output wb_inta_o; // WISHBONE interrupt output
// I2C signals
inout scl_pad_io; // I2C clock io
inout sda_pad_io; // I2C data io
// SPI MISO
input spi_miso_pad_i;
wire wb_cyc_i; // WISHBONE cycle input
// Wire tri-state scl/sda
wire scl_pad_i;
wire scl_pad_o;
wire scl_pad_io;
wire scl_padoen_o;
assign wb_cyc_i = wb_stb_i;
assign scl_pad_i = scl_pad_io;
assign scl_pad_io = scl_padoen_o ? (dedicated_spi ? 1'b1 : 1'bZ) : scl_pad_o;
wire sda_pad_i;
wire sda_pad_o;
wire sda_pad_io;
wire sda_padoen_o;
assign sda_pad_i = sda_pad_io;
assign sda_pad_io = sda_padoen_o ? (dedicated_spi ? 1'b1 : 1'bZ) : sda_pad_o;
// Avalon doesn't have an asynchronous reset
// set it to be inactive and just use synchronous reset
// reset level is a parameter, 0 is the default (active-low reset)
wire arst_i;
assign arst_i = 1'b1;
// Connect the top level I2C core
i2c_master_top #(.dedicated_spi(dedicated_spi)) i2c_master_top_inst
(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o),
.spi_miso_pad_i(spi_miso_pad_i)
);
endmodule
|
module multiplexor_2x1#(parameter BIT_WIDTH = 32)
(input control,
input[BIT_WIDTH - 1:0] in0,
input[BIT_WIDTH - 1:0] in1,
output[BIT_WIDTH - 1:0] out);
wire neg_control;
wire[BIT_WIDTH - 1:0] out0;
wire[BIT_WIDTH - 1:0] out1;
genvar i;
not (neg_control, control);
generate
for (i = 0; i < 32; i = i + 1)
begin : mux_bit
and (out0[i], neg_control, in0[i]);
and (out1[i], control, in1[i]);
or (out[i], out0[i], out1[i]);
end
endgenerate
endmodule
module multiplexor_4x1#(parameter BIT_WIDTH = 32)
(input[1:0] control,
input[BIT_WIDTH - 1:0] in0,
input[BIT_WIDTH - 1:0] in1,
input[BIT_WIDTH - 1:0] in2,
input[BIT_WIDTH - 1:0] in3,
output[BIT_WIDTH - 1:0] out);
wire[BIT_WIDTH - 1:0] multiplexor0_out;
wire[BIT_WIDTH - 1:0] multiplexor1_out;
multiplexor_2x1 multiplexor0(control[0], in0, in1, multiplexor0_out);
multiplexor_2x1 multiplexor1(control[0], in2, in3, multiplexor1_out);
multiplexor_2x1 multiplexor_out(control[1], multiplexor0_out,
multiplexor1_out, out);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; const int N = 1e6 + 6; struct segt { vector<int> t; int d; segt(vector<int> &a) { int n = a.size(); for (d = 2; d < n; d <<= 1) ; t.assign(d * 2, 0); for (int i = 0; i < n; ++i) t[i + d] = a[i]; for (int i = d - 1; i; --i) t[i] = min(t[i * 2], t[i * 2 + 1]); } int rmq(int i, int j) { int res = 1e9; for (i += d, j += d; i <= j; ++i >>= 1, --j >>= 1) { if (i & 1) res = min(res, t[i]); if (~j & 1) res = min(res, t[j]); } return res; } }; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n; vector<pair<int, int>> s; set<int> u; for (int i = 0; i < n; ++i) { int l, r; cin >> l >> r; s.push_back({l, r}); u.insert(l); u.insert(r); u.insert(r + 1); } vector<int> t((u).begin(), (u).end()); vector<int> f(t.size()); for (auto p : s) { int l = p.first; int r = p.second; f[lower_bound((t).begin(), (t).end(), l) - t.begin()]++; f[lower_bound((t).begin(), (t).end(), r + 1) - t.begin()]--; } for (int i = 1; i < f.size(); ++i) f[i] += f[i - 1]; segt q(f); for (int k = 0; k < n; ++k) { int l = s[k].first; int r = s[k].second; int i = lower_bound((t).begin(), (t).end(), l) - t.begin(); int j = lower_bound((t).begin(), (t).end(), r) - t.begin(); if (q.rmq(i, j) != 1) { cout << k + 1 << endl; return 0; } } cout << -1 << endl; return 0; }
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* PL allocator
*
* Allocates new virtual-channels for newly arrived packets.
*
* Supported PL allocation architectures:
*
* (A) "fifo_free_pool" - Free PL pool is organised as a FIFO, at most one PL
* may be allocated per output port per clock cycle
*
* In this case we just need P x PV:1 arbiters
*
* (B) "unrestricted" - Peh/Dally style PL allocation.
* Takes place in two stages:
*
* stage 1. Each waiting packet determines which PL it will request.
* (v:1 arbitration). Can support PL alloc. mask here (from
* packet header or static or dynamic..)
*
*
* stage 2. Access to each output PL is arbitrated (PV x PV:1 arbiters)
*
*/
module LAG_pl_allocator (req, output_port, // PL request, for which port?
pl_new, pl_new_valid, // newly allocated PL ids
pl_allocated, // which PLs were allocated on this cycle?
pl_alloc_status, // which PLs are free?
clk, rst_n);
parameter buf_len=4;
parameter xs=4;
parameter ys=4;
parameter np=5;
parameter nv=4;
parameter alloc_stages = 1;
//-----
input [np-1:0][nv-1:0] req;
input output_port_t output_port [np-1:0][nv-1:0];
output [np-1:0][nv-1:0][nv-1:0] pl_new;
output [np-1:0][nv-1:0] pl_new_valid;
output [np-1:0][nv-1:0] pl_allocated;
input [np-1:0][nv-1:0] pl_alloc_status;
input clk, rst_n;
generate
LAG_pl_unrestricted_allocator
#(.np(np), .nv(nv), .xs(xs), .ys(ys), .buf_len(buf_len),
.alloc_stages(alloc_stages)
) unrestricted
(
.req,
.output_port,
.pl_status(pl_alloc_status),
.pl_new,
.pl_new_valid,
.pl_allocated,
.clk, .rst_n
);
endgenerate
endmodule // LAG_pl_allocator
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: fr_cycle_shifter.v
//
// The fr-cycle shifter shifts the input data by X number of full-rate-cycles, where X is specified by the shift_by port.
// datain is a bus that combines data of multiple full rate cycles, in specific time order. For example,
// in a quarter-rate system, the datain bus must be ordered as {T3, T2, T1, T0}, where Ty represents the y'th fr-cycle
// data item, of width DATA_WIDTH. The following illustrates outputs at the dataout port for various values of shift_by.
// "__" means don't-care.
//
// shift_by dataout in current cycle dataout in next clock cycle
// 00 {T3, T2, T1, T0} {__, __, __, __}
// 01 {T2, T1, T0, __} {__, __, __, T3}
// 10 {T1, T0, __, __} {__, __, T3, T2}
// 11 {T0, __, __, __} {__, T3, T2, T1}
//
// In full-rate or half-rate systems, only the least-significant bit of shift-by has an effect
// (i.e. you can only shift by 0 or 1 fr-cycle).
// In quarter-rate systems, all bits of shift_by are used (i.e. you can shift by 0, 1, 2, or 3 fr-cycles).
//
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module ddr3_s4_uniphy_p0_fr_cycle_shifter(
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH*RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] shift_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true")
datain_r <= {FULL_DATA_WIDTH{1'b1}};
else
datain_r <= {FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
endmodule
|
#include <bits/stdc++.h> using namespace std; FILE* in = stdin; FILE* out = stdout; const int MAX = 100001; int n, k; int a[MAX]; int color[256]; void solve() { memset(color, -1, sizeof(color)); color[0] = 0; for (int i = 0; i < n; i++) { if (color[a[i]] != -1) continue; int left = -1; for (int c = 0;; c++) { if (color[a[i] - c] != -1) { left = a[i] - c; break; } } if (color[left] + k - 1 >= a[i]) { for (int c = left + 1; c <= a[i]; c++) color[c] = color[left]; continue; } int at = a[i]; if (at - k + 1 > left) { for (int c = at - k + 1; c <= at; c++) color[c] = at - k + 1; continue; } for (int c = left + 1; c <= a[i]; c++) color[c] = left + 1; } for (int i = 0; i < n; i++) fprintf(out, %d%c , color[a[i]], i + 1 == n ? n : ); } int main(void) { fscanf(in, %d %d , &n, &k); for (int i = 0; i < n; i++) fscanf(in, %d , &a[i]); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int testcases; cin >> testcases; while (testcases--) { long long int n, m; cin >> n >> m; char a[n][m]; for (long long int(i) = 0; (i) < (n); (i)++) { for (long long int(j) = 0; (j) < (m); (j)++) cin >> a[i][j]; } long long int cnt = 0; for (long long int j = 0; j < m - 1; j++) { if (a[n - 1][j] == D ) cnt++; } for (long long int(i) = 0; (i) < (n - 1); (i)++) { if (a[i][m - 1] == R ) cnt++; } cout << cnt << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t[90]; bool ans = false; cin >> n; for (int i = 0; i < n; i++) { cin >> t[i]; } if (t[0] > 15) { cout << 15; ans = true; } for (int i = 0; i < n - 1 && ans == false; i++) { t[i] += 15; if (t[i] < t[i + 1]) { cout << t[i]; ans = true; } } t[n - 1] += 15; if (t[n - 1] >= 90 && ans == false) { cout << 90; } if (t[n - 1] < 90 && ans == false) { cout << t[n - 1]; } }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; int main() { int n; scanf( %d , &n); if (n % 2 == 0) { printf( -1 n ); return 0; } for (int i = 0; i < n; ++i) { printf( %d , i); } printf( n ); for (int i = 0; i < n; ++i) { printf( %d , (i + 1) % n); } printf( n ); for (int i = 0; i < n; ++i) { printf( %d , (2 * i + 1) % n); } printf( n ); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/07 13:20:30
// Design Name:
// Module Name: _3bit_binary_multiplier_control_unit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module _3bit_binary_multiplier_control_unit
(
input start,
input clk,
input cnt_done,
input lsb,
output start_process,
output reg add,
output reg shift,
output reg count_up,
output reg done
// ,output state
);
reg [2:0] state, nextState;
parameter off = 0, on = 1, process = 2, finish = 3;
assign start_process = start;
initial begin
state = off;
end
// update state
always @(posedge clk) begin
state <= nextState;
end
//compute mealy output and state
always @(start or lsb or cnt_done or state) begin
add = 0;
case (state)
off: begin
if (start) nextState = on;
else nextState = off;
end
on: begin
if (lsb) begin
nextState = process;
add = 1;
end
else begin
nextState = process;
end
end
process: begin
if (cnt_done) nextState = finish;
else nextState = on;
end
finish: begin
nextState = off;
end
default: begin
nextState = off;
end
endcase
end
// compute Moore output
always @(state) begin
shift = 0;
count_up = 0;
done = 0;
case (state)
process: begin
shift = 1;
count_up = 1;
end
finish: begin
done = 1;
end
default: begin
shift = 0;
count_up = 0;
done = 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; struct column { int a[13]; int x; }; column c[2001]; bool cmp(column p, column q) { return p.x > q.x; } int s[13][4096], f[13][4096]; int mian() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) scanf( %d , &c[j].a[i]); for (int j = 1; j <= m; j++) { c[j].x = 0; for (int i = 1; i <= n; i++) c[j].x = max(c[j].x, c[j].a[i]); } sort(c + 1, c + 1 + m, cmp); m = min(m, n); for (int i = 1; i <= m; i++) for (int j = 0; j < (1 << n); j++) { s[i][j] = 0; for (int p = 0; p < n; p++) { int sum = 0; for (int l = 1, k = p + 1; l <= n; l++, k = (k == n) ? 1 : (k + 1)) if (j & (1 << l - 1)) sum += c[i].a[k]; s[i][j] = max(s[i][j], sum); } } for (int i = 1; i <= m; i++) for (int j = 0; j < (1 << n); j++) { f[i][j] = f[i - 1][j]; for (int k = j; k; k = (k - 1) & j) f[i][j] = max(f[i][j], f[i - 1][j ^ k] + s[i][k]); } printf( %d n , f[m][(1 << n) - 1]); return 0; } int t; int main() { for (scanf( %d , &t); t; t--) mian(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFSBP_SYMBOL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int inf = 0x3f3f3f3f; int n, k, a[510][510]; int main() { while (~scanf( %d%d , &n, &k)) { int top = 1, ans = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j < k; j++) { a[i][j] = top++; } } for (int i = 1; i <= n; i++) { for (int j = k; j <= n; j++) { if (j == k) ans += top; a[i][j] = top++; } } printf( %d n , ans); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { printf( %d , a[i][j]); if (j == n) putchar( n ); else putchar( ); } } } }
|
//----------------------------------------------------------------------------
//-- Ejemplo 2 de puertas tri-estado
//-- Hay 3 biestables con sus salidas conectas a un bus de 1 bit
//-- Este bus se saca por un led, para conocer su estado
//-- Con un registro de desplazamiento se selecciona que registro
//-- se conecta al bus a traves de su puerta triestado correspondiente
//-- Se hace de forma que cada vez se secciona una
//----------------------------------------------------------------------------
//-- (C) BQ. November 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
`default_nettype none
`include "divider.vh"
module tristate2 (
input wire clk, //-- Entrada de reloj
output wire led0); //-- Led a controlar
//-- Parametro: periodo de parpadeo
parameter DELAY = `T_1s;
//-- Cable con la señal de tiempo
wire clk_delay;
//-- Bus de 1 bit
wire bus;
//-- Señal de reset
reg rstn = 0;
//-- Registro de desplazamiento
reg [3:0] sreg;
//-- Definir los 3 bistables a conectar al bus, cada uno con un
//-- valor inicial cualquiera
reg reg0;
always @(posedge clk)
reg0 <= 1'b1;
reg reg1;
always @(posedge clk)
reg1 <= 1'b0;
reg reg2;
always @(posedge clk)
reg2 <= 1'b1;
//-- Conectar los biestables al bus, a traves de puertas triestado
assign bus = (sreg[0]) ? reg0 : 1'bz;
assign bus = (sreg[1]) ? reg1 : 1'bz;
assign bus = (sreg[2]) ? reg2 : 1'bz;
//-- Conectar el bus al led
assign led0 = bus;
//-- Registros de desplazamiento
always @(posedge clk)
if (!rstn)
sreg <= 4'b0001;
else if (clk_delay)
sreg <= {sreg[2:0],sreg[3]};
//-- Inicializador
always @(posedge clk)
rstn <= 1'b1;
//-- Divisor para temporizacion
dividerp1 #(DELAY)
CH0 (
.clk(clk),
.clk_out(clk_delay)
);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) const char nl = n ; using namespace std; using ll = long long; using vi = vector<int>; using vl = vector<ll>; using pii = pair<int, int>; using pll = pair<ll, ll>; using str = string; str to_string(char c) { return str(1, c); } str to_string(bool b) { return b ? true : false ; } str to_string(const char* second) { return (str)second; } str to_string(str second) { return second; } template <class A> str to_string(complex<A> c) { stringstream ss; ss << c; return ss.str(); } str to_string(vector<bool> v) { str res = { ; for (int i = 0; i < (int)v.size(); i++) res += char( 0 + v[i]); res += } ; return res; } template <size_t SZ> str to_string(bitset<SZ> b) { str res = ; for (int i = 0; i < b.size(); i++) res += char( 0 + b[i]); return res; } template <class A, class B> str to_string(pair<A, B> p); template <class T> str to_string(T v) { bool fst = 1; str res = { ; for (const auto& x : v) { if (!fst) res += , ; fst = 0; res += to_string(x); } res += } ; return res; } template <class A, class B> str to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } void DBG() { cerr << ] << endl; } template <class H, class... T> void DBG(H h, T... t) { cerr << to_string(h); if (sizeof...(t)) cerr << , ; DBG(t...); } string c; int n; int dp[26][26]; signed main() { cin.tie(nullptr); ios_base::sync_with_stdio(false); cin >> n; for (int i = 0; i < 26; i++) { for (int j = 0; j < 26; j++) { dp[i][j] = -1e9; } } int ans = 0; for (int i = 0; i < n; i++) { cin >> c; int m = c.length(); int a = c[0] - a ; int b = c[m - 1] - a ; for (int j = 0; j < 26; j++) { dp[j][b] = max(dp[j][b], dp[j][a] + m); } dp[a][b] = max(dp[a][b], m); } for (int i = 0; i < 26; i++) { ans = max(ans, dp[i][i]); } cout << ans << nl; }
|
/*
* dat_i_arbiter - arbitrate data coming into the CPU
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module dat_i_arbiter(
// Clock
input wire clock_i,
// Output
output wire [7:0] D,
// Lower Rom module
input [7:0] l_rom,
input l_rom_e,
// Lower Rom module
input [7:0] u_rom,
input u_rom_e,
// Ram module
input [7:0] ram,
input ram_e,
// Extended Ram modules
input [7:0] eram,
input u_ram_e,
// Standard 8255 PIO
input [7:0] pio8255,
input pio8255_e,
// Printer IO
input [7:0] io,
input io_e,
// FDC IO
input [7:0] fdc,
input fdc_e
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
// Assignments ================================================================================
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Other logic ================================================================================
//always @(negedge clock_i)
assign D = (l_rom_e) ? l_rom :
(u_rom_e) ? u_rom :
(u_ram_e) ? eram :
(ram_e) ? ram :
(pio8255_e) ? pio8255 :
(io_e) ? io :
(fdc_e) ? fdc :
8'd255;
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// read_rs1 O 64
// read_rs1_port2 O 64
// read_rs2 O 64
// CLK I 1 clock
// RST_N I 1 reset
// read_rs1_rs1 I 5
// read_rs1_port2_rs1 I 5
// read_rs2_rs2 I 5
// write_rd_rd I 5
// write_rd_rd_val I 64 reg
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_write_rd I 1
//
// Combinational paths from inputs to outputs:
// read_rs1_rs1 -> read_rs1
// read_rs1_port2_rs1 -> read_rs1_port2
// read_rs2_rs2 -> read_rs2
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkGPR_RegFile(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
read_rs1_rs1,
read_rs1,
read_rs1_port2_rs1,
read_rs1_port2,
read_rs2_rs2,
read_rs2,
write_rd_rd,
write_rd_rd_val,
EN_write_rd);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// value method read_rs1
input [4 : 0] read_rs1_rs1;
output [63 : 0] read_rs1;
// value method read_rs1_port2
input [4 : 0] read_rs1_port2_rs1;
output [63 : 0] read_rs1_port2;
// value method read_rs2
input [4 : 0] read_rs2_rs2;
output [63 : 0] read_rs2;
// action method write_rd
input [4 : 0] write_rd_rd;
input [63 : 0] write_rd_rd_val;
input EN_write_rd;
// signals for module outputs
wire [63 : 0] read_rs1, read_rs1_port2, read_rs2;
wire RDY_server_reset_request_put, RDY_server_reset_response_get;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule regfile
wire [63 : 0] regfile$D_IN,
regfile$D_OUT_1,
regfile$D_OUT_2,
regfile$D_OUT_3;
wire [4 : 0] regfile$ADDR_1,
regfile$ADDR_2,
regfile$ADDR_3,
regfile$ADDR_4,
regfile$ADDR_5,
regfile$ADDR_IN;
wire regfile$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset_loop,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_write_rd,
WILL_FIRE_RL_rl_reset_loop,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_write_rd;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// value method read_rs1
assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_3 ;
// value method read_rs1_port2
assign read_rs1_port2 =
(read_rs1_port2_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_2 ;
// value method read_rs2
assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 64'd0 : regfile$D_OUT_1 ;
// action method write_rd
assign CAN_FIRE_write_rd = 1'd1 ;
assign WILL_FIRE_write_rd = EN_write_rd ;
// submodule f_reset_rsps
FIFO20 #(.guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule regfile
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'h0),
.hi(5'd31)) regfile(.CLK(CLK),
.ADDR_1(regfile$ADDR_1),
.ADDR_2(regfile$ADDR_2),
.ADDR_3(regfile$ADDR_3),
.ADDR_4(regfile$ADDR_4),
.ADDR_5(regfile$ADDR_5),
.ADDR_IN(regfile$ADDR_IN),
.D_IN(regfile$D_IN),
.WE(regfile$WE),
.D_OUT_1(regfile$D_OUT_1),
.D_OUT_2(regfile$D_OUT_2),
.D_OUT_3(regfile$D_OUT_3),
.D_OUT_4(),
.D_OUT_5());
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ;
// rule RL_rl_reset_loop
assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
assign WILL_FIRE_RL_rl_reset_loop = CAN_FIRE_RL_rl_reset_loop ;
// register rg_state
always@(EN_server_reset_request_put or
WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start)
case (1'b1)
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_reset_loop ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = EN_server_reset_request_put ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule regfile
assign regfile$ADDR_1 = read_rs2_rs2 ;
assign regfile$ADDR_2 = read_rs1_port2_rs1 ;
assign regfile$ADDR_3 = read_rs1_rs1 ;
assign regfile$ADDR_4 = 5'h0 ;
assign regfile$ADDR_5 = 5'h0 ;
assign regfile$ADDR_IN = write_rd_rd ;
assign regfile$D_IN = write_rd_rd_val ;
assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkGPR_RegFile
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module memory_dp_48x4096 (
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [5 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [47 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [11 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [47 : 0] doutb;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(8),
.C_ALGORITHM(0),
.C_PRIM_TYPE(3),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("memory_dp_48x4096.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(6),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_WIDTH_A(48),
.C_READ_WIDTH_A(48),
.C_WRITE_DEPTH_A(4096),
.C_READ_DEPTH_A(4096),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(6),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(48),
.C_READ_WIDTH_B(48),
.C_WRITE_DEPTH_B(4096),
.C_READ_DEPTH_B(4096),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("6"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 27.3621 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(enb),
.regceb(1'D0),
.web(6'B0),
.addrb(addrb),
.dinb(48'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(48'B0),
.s_axi_wstrb(6'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; long double f; int i; cin >> n; long long int m = n; for (i = 1; n / pow(10, i) >= 1; ++i) ; i--; f = n / pow(10, i); if (ceil(f) == f) f++; f = ceil(f); n = f * pow(10, i); cout << n - m; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[1005][1005], q, opr, xi; int row_sum[1005], col_sum[1005], total_row_add, total_col_add; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) scanf( %d , &a[i][j]); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (i != j) { row_sum[i] = (row_sum[i] + a[i][j]) % 2; col_sum[j] = (col_sum[j] + a[i][j]) % 2; } int ans = 0; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { if (i == j) ans = (ans + a[i][j] * a[i][j]) % 2; else ans = (ans + a[i][j] * a[j][i]) % 2; } scanf( %d , &q); while (q--) { scanf( %d , &opr); if (opr == 1) { scanf( %d , &xi); xi--; ans ^= 1; row_sum[xi] += n - 1; row_sum[xi] %= 2; ans = (ans + 2 * (col_sum[xi] + total_col_add)) % 2; col_sum[xi] = (col_sum[xi] + 1) % 2; total_col_add = (total_col_add + 1) % 2; } else if (opr == 2) { scanf( %d , &xi); xi--; ans ^= 1; col_sum[xi] += n - 1; col_sum[xi] %= 2; ans = (ans + 2 * (row_sum[xi] + total_row_add)) % 2; row_sum[xi] = (row_sum[xi] + 1) % 2; total_row_add = (total_row_add + 1) % 2; } else { printf( %d , ans); } } printf( n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDLCLKP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDLCLKP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDLCLKP_BLACKBOX_V
|
module adsr32( clk, GATE, A, D, S, R, sout/*, SEG */);
output reg [31:0] sout; // This is the accumulator/integrator for attack, decay and release
input wire clk; // 50 MHz
input wire GATE; // GATE signal
input wire [31:0] A; // attack rate
input wire [31:0] D; // decay rate
input wire [31:0] S; // sustain level
input wire [31:0] R; // release rate
reg [2:0] state; // state 0,1,2,3,4,5 - IDLE,ATTACK,DECAY,SUSTAIN,RELEASE
//output [7:0] SEG;
initial begin
state = 3'b000;
sout = 0;
end
////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////
// This is a state machine of 5 states, IDLE, ATTACK, DECAY, SUSTAIN and RELEASE.
parameter IDLE = 3'b000;
parameter ATTACK = 3'b001;
parameter DECAY = 3'b010;
parameter SUSTAIN = 3'b011;
parameter RELEASE = 3'b100;
always @ ( posedge clk )
begin
case ( state )
IDLE: //ждем
begin
// переходим из IDLE в 01 (attack)
//смена стейта
state <= ( GATE == 1'b1 ) ? ATTACK : IDLE;
end
ATTACK: //атака
begin
if ( GATE == 1'b1 ) begin
if ( (sout + A) <= {1'b0,{32{1'b1}}} ) begin //если не достигли максимума - прибавляем
sout <= sout + A; // на значение A
end else begin // иначе переполнение
sout <= {32{1'b1}}; // ставим максимальное значение
end
end
//смена стейта
if ( GATE == 1'b0 ) begin
state <= RELEASE; // если GATE в ноле, значит переходим в state 4 (release)
end else begin
// GATE в единице
if ( (sout + A) > {1'b0,{32{1'b1}}} ) begin //если не достигли максимума - прибавляем
state <= DECAY; // переходим в state 2 (decay)
end
end
end
DECAY: //спад
begin
if ( GATE == 1'b1 ) begin
//GATE активно? спадаем
if ((sout-D) > S) begin
sout <= sout - D;
end else begin
sout <= S;
end
end
if ( GATE == 1'b1 ) begin
if ( sout == S) begin
state <= SUSTAIN;
end
end else if ( GATE == 1'b0 ) begin
state <= RELEASE;
end
end
SUSTAIN: //в удержании стоим, пока не спал GATE
begin
if ( GATE == 1'b0 ) state <= RELEASE; // Go to state 4, RELEASE
end
RELEASE:
begin
if ( GATE == 1'b0 ) begin //при RELEASE снова нажата GATE - переходим в ATTACK
if ( sout > R ) begin // если значение больше, то вычитаем
sout <= (sout - R);
end else begin //иначе, утухли совсем и перешли в стейт IDLE
sout <= 0;
end
end else if ( GATE == 1'b1 ) begin
//если в режиме релиза пришел следующий гейт - ИГНОРИМ ХВОСТ
sout <= 0;
end
//
if ( GATE == 1'b1 ) begin
state <= ATTACK;
end else begin ///////
if ( sout == 0 ) begin
state <= IDLE;
end
end
end
endcase
end
/*
reg [6:0] SEG_buf;
always @ (state)
begin
case(state)
3'h0: SEG_buf <= 7'b0111111;
3'h1: SEG_buf <= 7'b0000110;
3'h2: SEG_buf <= 7'b1011011;
3'h3: SEG_buf <= 7'b1001111;
3'h4: SEG_buf <= 7'b1100110;
3'h5: SEG_buf <= 7'b1101101;
3'h6: SEG_buf <= 7'b1111101;
3'h7: SEG_buf <= 7'b0000111;
default: SEG_buf <= 7'b0111111;
endcase
end
assign SEG = {1'b0,SEG_buf}; */
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const int mx = 999999; int n, k, q; long long f[6], dp[N]; int main() { scanf( %d , &k); for (int i = 0; i < 6; ++i) scanf( %d , &f[i]); for (int i = 1; i <= mx; ++i) { int tmp = i, ct = 0; while (tmp) { int x = tmp % 10; if (x % 3 == 0) dp[i] += f[ct] * (x / 3); ct++; tmp /= 10; } } for (int i = 0, x = 3; i < 6; ++i, x = x * 10) { int tmp = min(3 * (k - 1), mx / x); for (int j = 1; j <= tmp; tmp -= j, j <<= 1) for (int w = mx; w >= j * x; --w) dp[w] = max(dp[w], dp[w - j * x] + j * f[i]); if (tmp) { for (int w = mx; w >= tmp * x; --w) dp[w] = max(dp[w], dp[w - tmp * x] + tmp * f[i]); } } scanf( %d , &q); while (q--) { int x; scanf( %d , &x); printf( %lld n , dp[x]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b; cin >> a >> b; if (a > b || (b - a) % 2) { cout << -1; return 0; } if (a == b) { if (a == 0) cout << 0; else cout << 1 << n << a; } else if (((a + (b - a) / 2) ^ ((b - a) / 2)) == a) { cout << 2 << n << a + (b - a) / 2 << << (b - a) / 2; } else cout << 3 << endl << a << << (b - a) / 2 << << (b - a) / 2; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S4S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLYMETAL6S4S_BEHAVIORAL_PP_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlymetal6s4s (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S4S_BEHAVIORAL_PP_V
|
/*
* Copyright 2013-2021 Robert Newgard
*
* This file is part of fcs.
*
* fcs is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* fcs is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with fcs. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "fcs32_1.v"
`include "fcs32_brev.v"
module uut_1_bitp
(
output wire [31:0] res_o,
output wire [31:0] exp_o,
output wire [31:0] obs_o,
output wire val_o,
input wire [31:0] data_i,
input wire sof_i,
input wire eof_i,
input wire bstb_i,
input wire bclk_i
);
/* -----------------------------------------------------------
parameters
------------------------------------------------------------*/
localparam LO = 1'b0;
localparam HI = 1'b1;
localparam [31:0] ZEROS = {32{LO}};
localparam [31:0] ONES = {32{HI}};
localparam FIRST = 4;
localparam LAST = 34;
/* -----------------------------------------------------------
net declarations
------------------------------------------------------------*/
reg dat_z1;
reg bgn_z1;
reg end_z1;
reg [31:0] exp_z2;
reg [31:0] fcs_z2;
reg end_z2;
reg [31:0] exp_z3;
reg [31:0] fcs_z3;
reg val_z3;
reg [31:0] exp[FIRST:LAST];
reg [31:0] crc[FIRST:LAST];
reg val[FIRST:LAST];
integer bit_cnt;
/* -----------------------------------------------------------
input assignments
------------------------------------------------------------*/
/* -----------------------------------------------------------
Pipeline
------------------------------------------------------------*/
always @ (posedge bclk_i) begin
if (bstb_i == HI) begin
bit_cnt <= 0;
end else begin
bit_cnt <= bit_cnt + 1;
end
bgn_z1 <= LO;
end_z1 <= LO;
dat_z1 <= data_i[bit_cnt + 24];
if (bit_cnt == 7) begin
end_z1 <= eof_i;
end else if (bit_cnt == 0) begin
bgn_z1 <= sof_i;
end
end_z2 <= end_z1;
if (end_z1 == HI) begin
exp_z2[31:0] <= data_i[31:0];
end
if (bgn_z1 == HI) begin
fcs_z2[31:0] <= fcs32_1(dat_z1, ONES[31:0]);
end else begin
fcs_z2[31:0] <= fcs32_1(dat_z1, fcs_z2[31:0]);
end
val_z3 <= end_z2;
exp_z3[31:0] <= exp_z2[31:0];
if (end_z2 == HI) begin
fcs_z3[31:0] <= fcs32_brev(fcs_z2[31:0]);
end
end
generate
genvar i;
for (i = FIRST ; i <= LAST ; i = i + 1) begin : ppln_delay
always @ (posedge bclk_i) begin
if (i == FIRST) begin
exp[i][31:0] <= exp_z3[31:0];
crc[i][31:0] <= fcs_z3[31:0];
val[i] <= val_z3;
end else begin
exp[i][31:0] <= exp[i - 1][31:0];
crc[i][31:0] <= crc[i - 1][31:0];
val[i] <= val[i - 1];
end
end
end
endgenerate
/* -----------------------------------------------------------
output assignments
------------------------------------------------------------*/
always @ (*) begin
res_o[31:0] = fcs_z2[31:0];
exp_o[31:0] = exp[LAST][31:0];
obs_o[31:0] = crc[LAST][31:0];
val_o = val[LAST];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int M, tp, xx, lll, cc, ndl = 0, N, dl, nf, nef, T; struct bl { long long int type; long long int l, c, x; }; bl t; vector<bl> B; vector<long long int> C; map<long long int, long long int> MP; ifstream in( input.txt ); long long int find_bl(long long int n) { if (MP.count(n) == 0) { long long int num = (lower_bound(C.begin(), C.end(), n) - C.begin()); t = B[num]; if (t.type == 1) { T = t.x; MP[n] = T; return T; } else { nf = n - C[num - 1]; nef = (nf % t.l == 0) ? t.l : (nf % t.l); T = find_bl(nef); MP[n] = T; return T; } } else return MP[n]; } int main() { cin >> M; for (int i = 1; i <= M; i++) { cin >> tp; t.type = tp; if (tp == 1) { cin >> xx; t.x = xx; B.push_back(t); C.push_back(ndl + 1); ndl++; } else { cin >> lll >> cc; t.l = lll; t.c = cc; B.push_back(t); C.push_back(ndl + (lll * cc)); ndl += lll * cc; } } cin >> N; for (int i = 1; i <= N; i++) { cin >> xx; cout << find_bl(xx) << ; } }
|
#include <bits/stdc++.h> using namespace std; struct node { int l, r, mx, pre, suf; }; vector<node> T; vector<pair<int, int> > ht; int n, m, a[100055], root[100055], first, second, z; int init(int l, int r) { int ind = T.size(); if (l == r) { T.push_back({-1, -1, 1, 1, 1}); return ind; } int mid = (l + r) >> 1; T.push_back({-1, -1, r - l + 1, r - l + 1, r - l + 1}); T[ind].l = init(l, mid); T[ind].r = init(mid + 1, r); return ind; } int update(int k, int l, int r, int tar) { int ind = T.size(); if (l == r) { T.push_back({-1, -1, 0, 0, 0}); return ind; } int mid = (l + r) >> 1, left, right; T.push_back({-1, -1, 0, 0, 0}); if (tar <= mid) { left = update(T[k].l, l, mid, tar); right = T[k].r; } else if (tar > mid) { left = T[k].l; right = update(T[k].r, mid + 1, r, tar); } T[ind] = {left, right, max(max(T[left].mx, T[right].mx), T[left].suf + T[right].pre), T[left].pre, T[right].suf}; if (T[left].pre == mid - l + 1) T[ind].pre = T[left].pre + T[right].pre; if (T[right].suf == r - mid) T[ind].suf = T[right].suf + T[left].suf; return ind; } node longest(int k, int l, int r, int tl, int tr) { if (tl <= l && r <= tr) { return T[k]; } int mid = (l + r) >> 1; if (mid < tl) return longest(T[k].r, mid + 1, r, tl, tr); if (tr <= mid) return longest(T[k].l, l, mid, tl, tr); node rans = longest(T[k].r, mid + 1, r, mid + 1, tr); node lans = longest(T[k].l, l, mid, tl, mid); node ret = (node){0, 0, 0, 0, 0}; ret.mx = max(max(rans.mx, lans.mx), lans.suf + rans.pre); ret.pre = lans.pre; if (lans.pre == mid - tl + 1) ret.pre = lans.pre + rans.pre; ret.suf = rans.suf; if (rans.suf == tr - mid) ret.suf = rans.suf + lans.suf; return ret; } void DEBUG(int k, int l, int r) { if (l == r) return; int mid = (l + r) >> 1; DEBUG(T[k].l, l, mid); DEBUG(T[k].r, mid + 1, r); } int main() { T.reserve(1000000); scanf( %d , &n); ht.push_back({0, 0}); for (int i = 1; i <= n; i++) { scanf( %d , a + i); ht.push_back({a[i], i}); } sort(ht.begin(), ht.end()); root[1] = init(1, n); for (int i = 2; i <= n; i++) root[i] = update(root[i - 1], 1, n, ht[i - 1].second); for (int i = 1; i <= n; i++) { } scanf( %d , &m); while (m--) { scanf( %d%d%d , &first, &second, &z); int l = 1, r = n + 1; while (l < r - 1) { int mid = (l + r) >> 1; node res = longest(root[mid], 1, n, first, second); if (res.mx >= z) l = mid; else r = mid; } printf( %d n , ht[l]); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return x * f; } int n, m; int a[55], b[55]; int aa[55], bb[55]; int main() { n = read(), m = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= n; i++) b[i] = read(); for (int i = 2; i <= n; i++) aa[i] = a[i] - a[i - 1], bb[i] = b[i] - b[i - 1]; aa[1] = m - a[n] + a[1]; bb[1] = m - b[n] + b[1]; for (int j = 0; j < n; j++) { bool flag = 0; for (int i = 1; i <= n; i++) { int x = i, y = x + j; if (y > n) y -= n; if (aa[x] != bb[y]) { flag = 1; break; } } if (!flag) { printf( YES n ); return 0; } } printf( NO n ); return 0; return 0; }
|
#include <bits/stdc++.h> using namespace std; char a[10][10]; int main(void) { for (int i = 0; i < 8; i++) { cin >> a[i]; } int b = 10, w = 10; for (int i = 0; i < 8; i++) { for (int j = 0; j < 8; j++) { if (a[i][j] == B ) { int f = 0; for (int k = i + 1; k < 8; k++) { if (a[k][j] != . ) f = 1; } if (!f) b = min(8 - i - 1, b); } if (a[i][j] == W ) { int f = 0; for (int k = i - 1; k >= 0; k--) { if (a[k][j] != . ) f = 1; } if (!f) w = min(i, w); } } } if (b < w) cout << B ; else cout << A ; }
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 13.1
// \ \ Application : xaw2verilog
// / / Filename : main_pll.v
// /___/ /\ Timestamp : 06/03/2011 01:58:13
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st /home/teknohog/dcm2/ipcore_dir/./main_pll.xaw /home/teknohog/dcm2/ipcore_dir/./main_pll
//Design Name: main_pll
//Device: xc3s500e-4fg320
//
// Module main_pll
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// kramble manually tweaked for 100MHz CLKIN_IN, programmable CLKFX_OUT and 100Mhz CLK0_OUT
// NB SPEED_MHZ resolution is 5MHz as CLKFX_DIVIDE(100) seemed excessive so using CLKFX_DIVIDE(20)
`timescale 1ns / 1ps
module main_pll # (parameter SPEED_MHZ = 25 )
(CLKIN_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT,
CLKFX_OUT,
CLKDV_OUT,
LOCKED_OUT);
input CLKIN_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output CLKFX_OUT;
output CLKDV_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLKFX_BUF;
wire CLKDV_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(8.0), .CLKFX_DIVIDE(20),
.CLKFX_MULTIPLY(SPEED_MHZ/5), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(10.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLRTP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SRDLRTP_PP_SYMBOL_V
/**
* srdlrtp: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLRTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 222222; const int inf = 1e9 + 7; vector<int> adj[MAXN], radj[MAXN]; int vis[MAXN], q[MAXN], qn, C; int cost[MAXN], mn[MAXN], cnt[MAXN]; void dfs(int u) { vis[u] = 1; for (auto v : adj[u]) { if (vis[v] == 1) continue; dfs(v); } q[qn++] = u; } void rdfs(int u) { vis[u] = C; for (int i = 0; i < radj[u].size(); i++) { int v = radj[u][i]; if (vis[v] == 0) rdfs(v); } } void SCC(int n) { for (int i = 1; i <= n; i++) vis[i] = 0; qn = C = 0; for (int i = 1; i <= n; i++) { if (!vis[i]) { dfs(i); } } for (int i = 1; i <= n; i++) vis[i] = 0; for (int i = qn - 1; i >= 0; i--) { int cc = q[i]; if (!vis[cc]) { C++; rdfs(cc); } } } int main() { int n, m, u, v; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , cost + i); scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d%d , &u, &v); adj[u].push_back(v); radj[v].push_back(u); } SCC(n); for (int i = 1; i <= C; i++) { mn[i] = inf; cnt[i] = 0; } for (int i = 1; i <= n; i++) { int cc = vis[i]; if (mn[cc] == cost[i]) cnt[cc]++; if (mn[cc] > cost[i]) mn[cc] = cost[i], cnt[cc] = 1; } long long ansc = 0, ansn = 1; for (int i = 1; i <= C; i++) { ansc += mn[i]; ansn = (1LL * ansn * cnt[i]) % inf; } printf( %lld %lld n , ansc, ansn); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); while (t--) { int n, m; scanf( %d%d , &n, &m); int x, ans = 0; for (int i = 0; i < n; i++) { scanf( %d , &x); ans += x; } if (ans == m) printf( YES n ); else printf( NO n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int max_n = 20010; int lf[max_n]; int rf[max_n]; int main() { long long sum = 0; int n; int x, y; memset(lf, 0, sizeof(lf)); memset(rf, 0, sizeof(rf)); scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d%d , &x, &y); ++lf[y - x + 1000]; ++rf[x + y]; } for (int i = 0; i <= 2050; ++i) { sum += (lf[i] * (lf[i] - 1)) / 2; } for (int i = 0; i <= 2050; ++i) { sum += (rf[i] * (rf[i] - 1)) / 2; } printf( %I64d n , sum); return 0; }
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module onchip_memory2_0 (
// inputs:
address,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../onchip_memory2_0.hex";
output [ 7: 0] readdata;
input [ 16: 0] address;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 7: 0] writedata;
wire [ 7: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 100000,
the_altsyncram.numwords_a = 100000,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 8,
the_altsyncram.widthad_a = 17;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "onchip_memory2_0.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 100000,
// the_altsyncram.numwords_a = 100000,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 8,
// the_altsyncram.widthad_a = 17;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, s, ans; int ar[5005]; int cnt[5005]; int ar2[5005]; vector<pair<pair<int, int>, pair<int, int> > > v; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) ar[i] = 1000000000; for (int i = 0; i < m; i++) { int t, l, r, x; scanf( %d%d%d%d , &t, &l, &r, &x); if (t == 1) for (int j = l; j <= r; j++) cnt[j] += x; else { for (int j = l; j <= r; j++) ar[j] = min(ar[j], x - cnt[j]); } v.push_back(pair<pair<int, int>, pair<int, int> >(pair<int, int>(t, x), pair<int, int>(l, r))); } for (int i = 1; i <= n; i++) if (max(ar[i], -ar[i]) > 1000000000) { printf( NO n ); exit(0); } for (int i = 1; i <= n; i++) ar2[i] = ar[i]; for (int i = 0; i < m; i++) { int t = v[i].first.first; int x = v[i].first.second; int l = v[i].second.first; int r = v[i].second.second; if (t == 1) { for (int j = l; j <= r; j++) ar2[j] += x; } else { int mx = -1000000000; for (int j = l; j <= r; j++) mx = max(mx, ar2[j]); if (mx != x) { printf( NO n ); exit(0); } } } printf( YES n ); for (int i = 1; i <= n; i++) printf( %d , ar[i]); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; long long a[1111], b[1111]; int main() { cin >> n; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= n; ++i) cin >> b[i]; long long ans = 0; for (int i = 1; i <= n; ++i) { long long cur1 = 0, cur2 = 0; for (int j = i; j <= n; ++j) { cur1 = cur1 | a[j]; cur2 = cur2 | b[j]; ans = max(ans, cur1 + cur2); } } cout << ans; return 0; }
|
`timescale 1ns / 1ps
/*
Group Members: Kevin Ingram and Warren Seto
Lab Name: Traffic Light Controller (Lab 3)
Project Name: eng312_proj3
Design Name: Traffic_Test_D_eng312_proj3.v
Design Description: Verilog Test Bench to Implement Test D (11 AM)
*/
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire[4:0] count1;
wire[3:0] count2;
wire[1:0] count3;
// Counter Modules
nsCounter clock1(clk, count1); // Count a total of 32 seconds
ewCounter clock2(clk, count2); // Counts a total of 16 seconds
yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @ (clk) begin
if ($time % 6 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 15 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v1_x_ddr_if_post_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v1_9_ddr_if_post_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input [3:0] empty_in,
input rd_en_in,
input [WIDTH-1:0] d_in, // write data from controller
output empty_out,
output byte_rd_en,
output [WIDTH-1:0] d_out // write data to OUT_FIFO
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
(((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx);
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1];
(* keep = "true", max_fanout = 3 *) reg [4:0] my_empty /* synthesis syn_maxfan = 3 */;
(* keep = "true", max_fanout = 3 *) reg [1:0] my_full /* synthesis syn_maxfan = 3 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
wire [WIDTH-1:0] mem_out;
(* keep = "true", max_fanout = 10 *) wire wr_en /* synthesis syn_maxfan = 10 */;
task updt_ptrs;
input rd;
input wr;
reg [1:0] next_rd_ptr;
reg [1:0] next_wr_ptr;
begin
next_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
next_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
casez ({rd, wr, my_empty[1], my_full[1]})
4'b00zz: ; // No access, do nothing
4'b0100: begin
// Write when neither empty, nor full; check for full
wr_ptr <= #TCQ next_wr_ptr;
my_full[0] <= #TCQ (next_wr_ptr == rd_ptr);
my_full[1] <= #TCQ (next_wr_ptr == rd_ptr);
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0110: begin
// Write when empty; no need to check for full
wr_ptr <= #TCQ next_wr_ptr;
my_empty <= #TCQ 5'b00000;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b1000: begin
// Read when neither empty, nor full; check for empty
rd_ptr <= #TCQ next_rd_ptr;
my_empty[0] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[1] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[2] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[3] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[4] <= #TCQ (next_rd_ptr == wr_ptr);
end
4'b1001: begin
// Read when full; no need to check for empty
rd_ptr <= #TCQ next_rd_ptr;
my_full[0] <= #TCQ 1'b0;
my_full[1] <= #TCQ 1'b0;
end
4'b1100, 4'b1101, 4'b1110: begin
// Read and write when empty, full, or neither empty/full; no need
// to check for empty or full conditions
rd_ptr <= #TCQ next_rd_ptr;
wr_ptr <= #TCQ next_wr_ptr;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0101, 4'b1010: ;
// Read when empty, Write when full; Keep all pointers the same
// and don't change any of the flags (i.e. ignore the read/write).
// This might happen because a faulty DQS_FOUND calibration could
// result in excessive skew between when the various IN_FIFO's
// first become not empty. In this case, the data going to each
// post-FIFO/IN_FIFO should be read out and discarded
// synthesis translate_off
default: begin
// Covers any other cases, in particular for simulation if
// any signals are X's
$display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b",
$time, rd, wr, my_empty[1], my_full[1]);
rd_ptr <= #TCQ 2'bxx;
wr_ptr <= #TCQ 2'bxx;
end
// synthesis translate_on
endcase
end
endtask
assign d_out = my_empty[4] ? d_in : mem_out;//mem[rd_ptr];
// The combined IN_FIFO + post FIFO is only "empty" when both are empty
assign empty_out = empty_in[0] & my_empty[0];
assign byte_rd_en = !empty_in[3] || !my_empty[3];
always @(posedge clk)
if (rst) begin
my_empty <= #TCQ 5'b11111;
my_full <= #TCQ 2'b00;
rd_ptr <= #TCQ 'b0;
wr_ptr <= #TCQ 'b0;
end else begin
// Special mode: If IN_FIFO has data, and controller is reading at
// the same time, then operate post-FIFO in "passthrough" mode (i.e.
// don't update any of the read/write pointers, and route IN_FIFO
// data to post-FIFO data)
if (my_empty[1] && !my_full[1] && rd_en_in && !empty_in[1]) ;
else
// Otherwise, we're writing to FIFO when IN_FIFO is not empty,
// and reading from the FIFO based on the rd_en_in signal (read
// enable from controller). The functino updt_ptrs should catch
// an illegal conditions.
updt_ptrs(rd_en_in, !empty_in[1]);
end
assign wr_en = (!empty_in[2] & ((!rd_en_in & !my_full[0]) |
(rd_en_in & !my_empty[2])));
always @ (posedge clk)
begin
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
end
assign mem_out = mem[rd_ptr];
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Dual-port RAM with dual write-capable port */
module tmu2_tdpram #(
parameter depth = 11, /* < log2 of the capacity in words */
parameter width = 32
) (
input sys_clk,
input [depth-1:0] a,
input we,
input [width-1:0] di,
output reg [width-1:0] do,
input [depth-1:0] a2,
input we2,
input [width-1:0] di2,
output reg [width-1:0] do2
);
reg [width-1:0] ram[0:(1 << depth)-1];
always @(posedge sys_clk) begin
if(we)
ram[a] <= di;
do <= ram[a];
end
always @(posedge sys_clk) begin
if(we2)
ram[a2] <= di2;
do2 <= ram[a2];
end
// synthesis translate_off
/*
* For some reason, in Verilog the result of an undefined multiplied by zero
* seems to be undefined.
* This causes problems with pixels that texcache won't fetch because some fractional
* parts are zero: the blend unit yields an undefined result on those, instead of ignoring
* the contribution of the undefined pixel.
* Work around this by initializing the memories.
*/
integer i;
initial begin
for(i=0;i<(1 << depth);i=i+1)
ram[i] = 0;
end
// synthesis translate_on
endmodule
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 5
*/
// Testbench for behavioral model for the circular FIFO
// Import the modules that will be tested for in this testbench
`include "FIFO.syn.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f fifo.f +gui
module tb_fifo();
/**
* Depth = number of rows for the register file
*
* The construct base**exponent is not synthesizable for our
* tool and technology library set up. It should be with the latest
* version of Verilog, Verilog 2005
*/
parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
// Width of the register file
parameter WIDTH = 8;
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the FIFO queue
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_out & emp & full_cb output signals
wire [7:0] d_out;
wire empty_cb,full_cb;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// push, pop, reset, & clk
reg push_cb,pop_cb,rst,clock;
// data_in
reg [WIDTH-1:0] d_in;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of SIPO() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
FIFO fifo_cb (
// instance_name(signal name),
// Signal name can be the same as the instance name
d_out,empty_cb,full_cb,d_in,push_cb,pop_cb,rst,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/FIFO.sdf",fifo_cb,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
rst=1'd1; // Reset
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd45;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd231;
// Push 8...
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd230;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd37;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd174;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd235;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd39;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd201;
// Pop 8...
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
// Try push and pull
/*
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd18;
*/
// Push 3 in
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd18;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
/*
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd74;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd138;
// Pop 3 out
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
*/
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
ErosionDilationBin
:Function
Erosion or Dilation for binary images.
It will give the first output after pipe_stage cycles while in_enable enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-24
Copyright (C) 2015 Tianyu Dai (dtysky) <>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
`define full_win_width window_width * window_width
module ErosionDilationBin(
clk,
rst_n,
mode,
template,
in_enable,
in_data,
out_ready,
out_data);
/*
::description
This module's working mode.
::range
0 for Pipeline, 1 for Req-ack
*/
parameter[0 : 0] work_mode = 0;
/*
::description
The width(and height) of window.
::range
2 - 15
*/
parameter[3 : 0] window_width = 3;
/*
::description
Stage of pipe.
::range
Depend on width of window, log2(window_width^2)
*/
parameter pipe_stage = 3;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Operation's mode.
::range
0 for Erosion, 1 for Dilation.
*/
input mode;
/*
::description
Template for operation.
*/
input[window_width * window_width - 1 : 0] template;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [window_width * window_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output out_data;
reg[`full_win_width - 1 : 0] reg_in_data;
reg[3 : 0] con_enable;
function pre_now_pix(input pix, mode, template);
pre_now_pix = pix ^ mode | ~template;
endfunction
genvar i, j;
generate
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_enable <= 0;
else if(con_enable == pipe_stage)
con_enable <= con_enable;
else
con_enable <= con_enable + 1;
end
assign out_ready = con_enable == pipe_stage? 1 : 0;
for (i = 0; i < `full_win_width; i = i + 1) begin
if(work_mode == 0) begin
always @(*)
reg_in_data[i] = in_data[i];
end else begin
always @(posedge in_enable)
reg_in_data[i] = in_data[i];
end
end
for (i = 0; i < pipe_stage; i = i + 1) begin : pipe
reg[(`full_win_width >> i + 1) - 1 : 0] res;
for (j = 0; j < `full_win_width >> i + 1; j = j + 1) begin
if(i == 0) begin
if(j == 0 && ((`full_win_width >> i) % 2 != 0)) begin
always @(posedge clk)
res[j] <=
pre_now_pix(reg_in_data[`full_win_width - 1], mode, template[`full_win_width - 1]) &
pre_now_pix(reg_in_data[2 * j], mode, template[2 * j]) &
pre_now_pix(reg_in_data[2 * j + 1], mode, template[2 * j + 1]);
end else begin
always @(posedge clk)
res[j] <=
pre_now_pix(reg_in_data[2 * j], mode, template[2 * j]) &
pre_now_pix(reg_in_data[2 * j + 1], mode, template[2 * j + 1]);
end
end else begin
if(j == 0 && ((`full_win_width >> i) % 2 != 0)) begin
always @(posedge clk)
res[j] <= pipe[i - 1].res[(`full_win_width >> i) - 1] & pipe[i - 1].res[2 * j] & pipe[i - 1].res[2 * j + 1];
end else begin
always @(posedge clk)
res[j] <= pipe[i - 1].res[2 * j] & pipe[i - 1].res[2 * j + 1];
end
end
end
end
assign out_data = out_ready ? pipe[pipe_stage - 1].res[0] ^ mode : 0;
endgenerate
endmodule
`undef full_win_width
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Detect_Change.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Detect_Change
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_Acceleration_To_Velocity/Set_Acceleration/Detect_Change
// Hierarchy Level: 7
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Detect_Change
(
CLK_IN,
reset,
enb_1_2000_0,
x,
y
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input signed [17:0] x; // sfix18_En8
output y;
reg signed [17:0] Delay_out1; // sfix18_En8
wire signed [18:0] Add_sub_cast; // sfix19_En8
wire signed [18:0] Add_sub_cast_1; // sfix19_En8
wire signed [18:0] Add_out1; // sfix19_En8
wire Compare_To_Zero2_out1;
// <S30>/Delay
always @(posedge CLK_IN)
begin : Delay_process
if (reset == 1'b1) begin
Delay_out1 <= 18'sb000000000000000000;
end
else if (enb_1_2000_0) begin
Delay_out1 <= x;
end
end
// <S30>/Add
assign Add_sub_cast = x;
assign Add_sub_cast_1 = Delay_out1;
assign Add_out1 = Add_sub_cast - Add_sub_cast_1;
// <S30>/Compare To Zero2
assign Compare_To_Zero2_out1 = (Add_out1 != 19'sb0000000000000000000 ? 1'b1 :
1'b0);
assign y = Compare_To_Zero2_out1;
endmodule // controllerHdl_Detect_Change
|
#include <bits/stdc++.h> using namespace std; int fir[5000]; int sec[5000]; int init(int x, int y) { printf( ? %d %d n , x, y); fflush(stdout); scanf( %d , &x); return x; } void print(int sch, const vector<int> &ans) { printf( ! n ); fflush(stdout); printf( %d n , sch); fflush(stdout); for (int i = 0; i < ans.size(); i++) printf( %d , ans[i]); fflush(stdout); } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) fir[i] = init(0, i); for (int i = 0; i < n; i++) sec[i] = init(i, 0); vector<int> ans; int sch = 0; for (int i = 0; i < n; i++) { bool t = true; int col[5000], p[5000], b[5000]; b[0] = i; memset(col, 0, sizeof col); for (int j = 0; j < n; j++) { int x = sec[j] ^ b[0]; if (x >= n || col[x]) { t = false; break; } p[j] = x; col[x]++; } if (t) { memset(col, 0, sizeof col); col[i]++; for (int j = 1; j < n; j++) { int x = fir[j] ^ p[0]; if (x >= n || col[x]) { t = false; break; } b[j] = x; col[x]++; } } if (t) { for (int j = 0; j < n; j++) if (j != b[p[j]]) t = false; } if (t) { if (!sch) { for (int j = 0; j < n; j++) ans.push_back(p[j]); } sch++; } } print(sch, ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; const long long mod = 998244353; long long qpow(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % mod; a = a * a % mod; b /= 2; } return ans; } long long b[maxn], inv[maxn]; long long C(long long n, long long m) { if (m > n) return 0; return b[n] * inv[m] % mod * inv[n - m] % mod; } long long Lucas(long long n, long long m) { if (m == 0) return 1; return C(n % mod, m % mod) * Lucas(n / mod, m / mod) % mod; } long long S(long long n, long long m) { long long ans = 0; for (int k = 0; k <= m; k++) { if (k & 1) ans = (ans - C(m, k) * qpow(m - k, n) % mod + mod) % mod; else ans = (ans + C(m, k) * qpow(m - k, n) % mod) % mod; } return ans; } int main() { int n, m; cin >> n >> m; if (m >= n) cout << 0 << endl; else { b[0] = 1; inv[0] = 1; for (int i = 1; i <= n; i++) b[i] = b[i - 1] * i % mod, inv[i] = qpow(b[i], mod - 2) % mod; long long ans = S(n, n - m) * C(n, n - m) % mod; if (m == 0) cout << ans << endl; else cout << ans * 2 % mod << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long maps[105][105]; int main() { long long a, b, c, d, i, j, k, l, t, n, m; scanf( %lld , &t); while (t--) { scanf( %lld , &a); for (i = 2; i * i <= a; i++) { if (a % i) { b = a % i; c = a - b; break; } } printf( %lld %lld n , i, c); } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; vector<int> v[maxn], w[maxn]; long long a[maxn]; bool d[maxn]; long long c[maxn][5]; long long n, m; bool mark[maxn][2]; void dfs1(long long i) { c[i][0] = 1; mark[i][0] = 1; for (long long y = 0; y < v[i].size(); y++) { if (!mark[v[i][y]][0]) { dfs1(v[i][y]); } } } void dfs2(long long i) { mark[i][1] = 1; c[i][1] = 1; if (a[i] == 1) return; for (long long y = 0; y < w[i].size(); y++) { if (!mark[w[i][y]][1]) { dfs2(w[i][y]); } } } int main() { ios_base::sync_with_stdio(false); cin >> n >> m; for (long long y = 1; y <= n; y++) { cin >> a[y]; if (a[y] == 1) { v[100000 + 1].push_back(y); } if (a[y] == 2) { w[100000 + 1].push_back(y); } } while (m--) { long long i, j; cin >> i >> j; v[i].push_back(j); w[j].push_back(i); } dfs1(100000 + 1); dfs2(100000 + 1); for (long long y = 1; y <= n; y++) { cout << (c[y][0] && c[y][1]) << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int MAXK = 1 << 12; const int P = 7340033; const int G = 3; const int MAXH = 30; int dp[MAXH + 7][MAXK + 7], buff[MAXK + 7]; int qpow(int a, int b) { if (b == 0) return 1; if (a == 0) return 0; int aux = qpow(1LL * a * a % P, b >> 1); if (b & 1) aux = 1LL * aux * a % P; return aux; } inline int inv(int x) { return qpow(x, P - 2); } void NTT(int *a, int N, int dir) { int t = 0; for (int i = (0); i <= (N - 1); ++i) { if (t < i) swap(a[t], a[i]); for (int j = (N >> 1); (t ^= j) < j; j >>= 1) ; } for (int i = 2; i <= N; i <<= 1) { int wn = qpow(G, (P - 1) / i); for (int j = 0; j < N; j += i) { int w = 1, t; for (int k = 0; k < (i >> 1); k++, w = 1LL * w * wn % P) { t = 1LL * w * a[j + k + (i >> 1)] % P; a[j + k + (i >> 1)] = a[j + k] - t; a[j + k] = a[j + k] + t; if (a[j + k + (i >> 1)] < 0) a[j + k + (i >> 1)] += P; if (a[j + k] >= P) a[j + k] -= P; } } } if (dir == -1) { for (int i = 1; i < (N >> 1); i++) swap(a[i], a[N - i]); int INV_N = inv(N); for (int i = (0); i <= (N - 1); ++i) a[i] = 1LL * a[i] * INV_N % P; } } void pre() { dp[0][0] = 1; for (int i = (1); i <= (MAXH); ++i) { memset(buff, 0, sizeof(buff)); for (int j = (0); j <= (1000); ++j) buff[j] = dp[i - 1][j]; NTT(buff, MAXK, 1); for (int j = (0); j <= (MAXK); ++j) buff[j] = qpow(buff[j], 4); NTT(buff, MAXK, -1); for (int j = (1); j <= (1000); ++j) dp[i][j] = buff[j - 1]; dp[i][0] = 1; } } inline int height(int N) { int h = 0; while (N > 1 && N & 1) { ++h; N = (N - 1) >> 1; } return h; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); pre(); int Q; cin >> Q; while (Q--) { int n, k; cin >> n >> k; cout << dp[height(n)][k] << n ; } return 0; }
|
// AJ, Beck, and Ray
// SRAM testbench
// 4/21/15
`include "SRAM2Kby16.v"
module SRAMtest();
// localize variables
wire clk, WrEn;
wire [10:0] adx;
wire [15:0] data;
// declare an instance of the module
SRAM2Kby16 SRAM (clk, adx, WrEn, data);
// Running the GUI part of simulation
SRAMtester tester (clk, adx, WrEn, data);
// file for gtkwave
initial
begin
$dumpfile("SRAMtest.vcd");
$dumpvars(1, SRAM);
end
endmodule
module SRAMtester (clk, adx, WrEn, data);
output reg [10:0] adx;
inout [15:0] data;
output reg clk, WrEn;
reg [15:0] out;
parameter d = 20;
// generate a clock
always #(d/2) clk = ~clk;
assign data = WrEn ? 16'bZ : out;
initial // Response
begin
$display("clk \t WrEn \t adx \t\t data \t\t out Time ");
#d;
clk = 0;
end
reg [31:0] i;
initial // Stimulus
begin
$monitor("%b \t %b \t %b \t %b", clk, WrEn, adx, data, $time);
WrEn = 1; adx = 0; out = 0;
#(10*d)
WrEn = 0;
for(i = 0; i < 128; i = i + 1) begin
adx = i;
out = 127 - i;
#d;
end
WrEn = 1;
for(i = 0; i < 128; i = i + 1) begin
adx = i;
#d;
end
#(2*d); // end bias
$stop;
$finish;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_databuf_ca.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
//
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_databuf_ca(/*AUTOARG*/
// Outputs
sctag_cpx_data_buf_pa,
// Inputs
sctag_cpx_data_pa
);
output [144:0] sctag_cpx_data_buf_pa;
input [144:0] sctag_cpx_data_pa;
assign sctag_cpx_data_buf_pa = sctag_cpx_data_pa;
endmodule
|
#include <bits/stdc++.h> using namespace std; int fen[100100]; int n, ans = -1, a[100100]; int calc(int ind) { int ans = 0; for (int i = ind; i >= 1; i -= i & (-i)) ans ^= fen[i]; return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; memset(fen, 0, sizeof(fen)); cin >> n; for (int i = 2; i <= n; i++) { int t; int p = 0; set<int> s; for (int j = 2; j * (j + 1) / 2 <= i; j++) { int k = i - j * (j + 1) / 2; if (k % j != 0) continue; k /= j; t = calc(k + j) ^ calc(k); if (i == n and ans == -1 and !t) ans = j; s.insert(t); } while (s.count(p)) p++; for (int j = i; j <= n; j += j & (-j)) fen[j] ^= p; } cout << ans; return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.1 (win64) Build Fri Apr 14 18:55:03 MDT 2017
// Date : Mon Aug 14 17:02:30 2017
// Host : ACER-BLUES running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// d:/Design_Project/E_elements/Project_BipedRobot/Project_BipedRobot.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_stub.v
// Design : clk_wiz_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_wiz_1(clk_txd, clk_rxd, resetn, locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_txd,clk_rxd,resetn,locked,clk_in1" */;
output clk_txd;
output clk_rxd;
input resetn;
output locked;
input clk_in1;
endmodule
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; typedef pair<int, int> pii; typedef pair<ll, ll> pll; const int MAXN = 2e5; const int MAXM = 5e6; int N; pii A[MAXN+10]; pii B[MAXM+10], C[MAXM+10]; int main() { scanf( %d , &N); for(int i=1; i<=N; i++) scanf( %d , &A[i].first), A[i].second=i; sort(A+1, A+N+1); N=min(N, 10000); for(int i=1; i<=N; i++) { for(int j=i-1; j>=1; j--) { int t=A[i].first-A[j].first; if(B[t]==pii(0, 0)) { B[t]={j, i}; } } } for(int i=N; i>=1; i--) { for(int j=i+1; j<=N; j++) { int t=A[j].first-A[i].first; if(C[t]==pii(0, 0)) { C[t]={i, j}; } } } for(int i=0; i<=MAXM; i++) { if(B[i]==pii(0, 0)) continue; if(C[i]==pii(0, 0)) continue; if(B[i].second<C[i].first) { printf( YES n ); printf( %d %d %d %d n , A[B[i].first].second, A[C[i].second].second, A[B[i].second].second, A[C[i].first].second); return 0; } } printf( NO n ); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
q0, q1, q2, q3, q4, q5, q6a, q6b,
// Inputs
clk, d, rst0_n
);
input clk;
input d;
// OK -- from primary
input rst0_n;
output wire q0;
Flop flop0 (.q(q0), .rst_n(rst0_n), .clk(clk), .d(d));
// OK -- from flop
reg rst1_n;
always @ (posedge clk) rst1_n <= rst0_n;
output wire q1;
Flop flop1 (.q(q1), .rst_n(rst1_n), .clk(clk), .d(d));
// Bad - logic
wire rst2_bad_n = rst0_n | rst1_n;
output wire q2;
Flop flop2 (.q(q2), .rst_n(rst2_bad_n), .clk(clk), .d(d));
// Bad - logic in submodule
wire rst3_bad_n;
Sub sub (.z(rst3_bad_n), .a(rst0_n), .b(rst1_n));
output wire q3;
Flop flop3 (.q(q3), .rst_n(rst3_bad_n), .clk(clk), .d(d));
// OK - bit selection
reg [3:0] rst4_n;
always @ (posedge clk) rst4_n <= {4{rst0_n}};
output wire q4;
Flop flop4 (.q(q4), .rst_n(rst4_n[1]), .clk(clk), .d(d));
// Bad - logic, but waived
// verilator lint_off CDCRSTLOGIC
wire rst5_waive_n = rst0_n & rst1_n;
// verilator lint_on CDCRSTLOGIC
output wire q5;
Flop flop5 (.q(q5), .rst_n(rst5_waive_n), .clk(clk), .d(d));
// Bad - for graph test - logic feeds two signals, three destinations
wire rst6_bad_n = rst0_n ^ rst1_n;
wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); // $c prevents optimization
wire rst6b_bad_n = rst6_bad_n ^ $c1("1");
output wire q6a;
output wire q6b;
Flop flop6a (.q(q6a), .rst_n(rst6a_bad_n), .clk(clk), .d(d));
Flop flop6v (.q(q6b), .rst_n(rst6b_bad_n), .clk(clk), .d(d));
initial begin
$display("%%Error: Not a runnable test");
$stop;
end
endmodule
module Flop (
input clk,
input d,
input rst_n,
output q);
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) q <= 1'b0;
else q <= d;
end
endmodule
module Sub (input a, b,
output z);
assign z = a|b;
endmodule
|
#include <bits/stdc++.h> using namespace std; int val{0}; struct Triplet { char letter; int onePosn; int otherPosn; }; int findContinuous(string s) { int j{0}; for (auto i = 0; i < s.length() - 2; i++) { if (s[i] == Q && s[i + 1] == A && s[i + 2] == Q ) { j++; } } return j; } int findLastQ(string s) { int j{0}; for (auto i = 0; i < s.length() - 1; i++) { if (s[i] == Q && s[i + 1] == A ) { for (int k = i + 2; k < s.length(); k++) { if (s[k] == Q ) { j++; } } } } return j; } int findFirstQ(string s) { int j{0}; for (auto i = 0; i < s.length() - 1; i++) { if (s[i] == A && s[i + 1] == Q ) { for (int k = 0; k < i; k++) { if (s[k] == Q ) { j++; } } } } return j; } int findDisjoint(string s) { int j{0}; for (auto i = 0; i < s.length(); i++) { int before{0}; int after{0}; if (s[i] == A ) { for (int k = 0; k < i; k++) { if (s[k] == Q ) { before++; } } for (int k = i + 1; k < s.length(); k++) { if (s[k] == Q ) { after++; } } j += before * after; } } return j; } int main() { string s; cin >> s; int n = findDisjoint(s); cout << n; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100100; int segTree[N * 4], n, x, y, z, l, r, val; map<int, int> TMp, NMp; vector<pair<int, int>> vv; vector<int> v, numm[N]; struct Query { int type, tim, num, ind; }; Query q[N]; void update(int i, int j, int pos) { if (i > r || j < l) return; if (i == j) { if (val == 0) segTree[pos] = 0; else segTree[pos] += val; return; } int mid = (i + j) / 2; update(i, mid, pos * 2); update(mid + 1, j, pos * 2 + 1); segTree[pos] = segTree[pos * 2] + segTree[pos * 2 + 1]; } int get(int i, int j, int pos) { if (i > r || j < l) { return 0; } if (l <= i && r >= j) { return segTree[pos]; } int mid = (i + j) / 2; return get(i, mid, pos * 2) + get(mid + 1, j, pos * 2 + 1); } int main() { scanf( %d , &n); int c = 1; for (int i = 0; i < n; i++) { scanf( %d%d%d , &x, &y, &z); if (NMp[z] == 0) { NMp[z] = c; c++; } numm[NMp[z]].push_back(i); q[i].type = x; q[i].tim = y; q[i].num = NMp[z]; q[i].ind = i; v.push_back(y); } sort(v.begin(), v.end()); int co = 1; for (int i = 0; i < v.size(); i++) { if (TMp[v[i]] == 0) { TMp[v[i]] = co; co++; } } for (int j = 1; j < c; j++) { for (int i = 0; i < numm[j].size(); i++) { int x = numm[j][i]; if (q[x].type == 1) { l = TMp[q[x].tim]; r = TMp[q[x].tim]; val = 1; update(1, N, 1); } else if (q[x].type == 2) { l = TMp[q[x].tim]; r = TMp[q[x].tim]; val = -1; update(1, N, 1); } else if (q[x].type == 3) { l = 1; r = TMp[q[x].tim]; int ans = get(1, N, 1); vv.push_back(make_pair(q[x].ind, ans)); } } for (int i = 0; i < numm[j].size(); i++) { l = TMp[q[numm[j][i]].tim]; r = TMp[q[numm[j][i]].tim]; val = 0; update(1, N, 1); } } sort(vv.begin(), vv.end()); for (int i = 0; i < vv.size(); i++) { printf( %d n , vv[i].second); } return 0; }
|
/***********************************************************************
*
* Copyright (C) 2011 Adrian Wise
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
***********************************************************************
*
* This is a testbench exercising gate-level modelling of DTL gates,
* distilled down (as a test-case) from a much larger design.
* The gates can only pull down strongly to ground and have a weak
* pull-up.
*
**********************************************************************/
`timescale 1 ns / 100 ps
module dtl_inv (op, in1);
output op;
input in1;
not (strong0, pull1) #16 not1 (op, in1);
endmodule // dtl_inv
module sr_latch (p, n);
inout p;
inout n;
dtl_inv u_p1
( .in1 ( n ) ,
.op ( p ) );
dtl_inv u_n1
( .in1 ( p ) ,
.op ( n ) );
endmodule // sr_latch
module dut (pp, nn);
inout [1:0] pp;
inout [1:0] nn;
sr_latch u_l1 (pp[0], nn[0]);
endmodule // dut
module top;
reg pass;
reg x;
wire [1:0] pp;
wire [1:0] nn;
dtl_inv u_pp0(.in1(~x), .op(pp[0]));
dtl_inv u_nn0(.in1( x), .op(nn[0]));
dut u_d1 (pp, nn);
initial begin
pass = 1'b1;
x <= 2'd0;
#100;
$display("Expect: x = 0, pp = z0, nn = z1 p=0, n=1");
$display("Actual: x = %b, pp = %b, nn = %b p=%b, n=%b", x, pp, nn,
u_d1.u_l1.p, u_d1.u_l1.n);
if (x !== 1'b0) begin
$display("Failed: expected x to be 0, got %b", x);
pass = 1'b0;
end
if (pp !== 2'bz0) begin
$display("Failed: expected pp to be z0, got %b", pp);
pass = 1'b0;
end
if (nn !== 2'bz1) begin
$display("Failed: expected nn to be z0, got %b", nn);
pass = 1'b0;
end
if (u_d1.u_l1.p !== 1'b0) begin
$display("Failed: expected p to be 0, got %b", u_d1.u_l1.p);
pass = 1'b0;
end
if (u_d1.u_l1.n !== 1'b1) begin
$display("Failed: expected n to be 1, got %b", u_d1.u_l1.n);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule // top
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 100; int len, S, T; bool o[N * 40][15]; char str[N]; long long n, Ans; struct matrix { long long f[4][4]; matrix() { memset(f, 63, sizeof(f)); } } Trans, bin[70], X; void cmin(long long& x, long long y) { x = x < y ? x : y; } matrix operator*(matrix a, matrix b) { matrix c; for (int i = 0; i < 4; ++i) for (int j = 0; j < 4; ++j) for (int k = 0; k < 4; ++k) cmin(c.f[i][j], a.f[i][k] + b.f[k][j]); return c; } int bfs() { queue<int> q, d; q.push(S), d.push(1); while (!q.empty()) { int u = q.front(), dis = d.front(); q.pop(), d.pop(); if (!o[u * 4 + T][dis + 1]) return dis + 1; for (int i = 0; i < 4; ++i) { int v = u * 4 + i; q.push(v), d.push(dis + 1); } } return 233; } int main() { scanf( %lld , &n); scanf( %s , str + 1); len = strlen(str + 1); for (int i = 1; i <= len; ++i) for (int k = 1, tp = 0; i + k - 1 <= len && k <= 10; ++k) tp = tp * 4 + str[i + k - 1] - A , o[tp][k] = 1; for (int i = 0; i < 4; ++i) for (int j = 0; j < 4; ++j) S = i, T = j, Trans.f[i][j] = bfs() - 1; bin[0] = Trans; for (int i = 1; i < 62; ++i) bin[i] = bin[i - 1] * bin[i - 1]; memset(X.f, 0, sizeof(X.f)); for (int i = 61; ~i; --i) { matrix tmp = X * bin[i]; long long mn = 2e18; for (int j = 0; j < 4; ++j) for (int k = 0; k < 4; ++k) cmin(mn, tmp.f[j][k]); if (mn < n) X = tmp, Ans += 1ll << i; } ++Ans; printf( %lld , Ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, flag = 0; vector<int> A, B; map<int, int> store; store.clear(); scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a); if (store[a] < 2) { if (store[a] == 0) { A.push_back(a); store[a] = 1; } else { flag = 1; B.push_back(a); store[a] = 2; } } } sort(A.begin(), A.end()); sort(B.begin(), B.end()); reverse(B.begin(), B.end()); int ans = A.size() + B.size(); if (flag) if (A[A.size() - 1] == B[0]) ans--; cout << ans << endl; for (int i = 0; i < A.size(); i++) { cout << A[i] << ; } for (int i = 0; i < B.size(); i++) { if (i == 0 && B[i] == A[A.size() - 1]) continue; cout << B[i] << ; } cout << endl; return 0; }
|
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