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//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: n64adv_top
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: Cyclone IV: EP4CE10E22
// Cyclone 10 LP: 10CL010YE144
// Tool versions: Altera Quartus Prime
//
// Revision: 1.33
// Features: see repository readme
//
//////////////////////////////////////////////////////////////////////////////////
module n64adv_top (
// N64 Video Input
VCLK,
nVDSYNC,
VD_i,
// System CLK, Controller and Reset
SYS_CLK,
CTRL_i,
nRST,
// Video Output to ADV712x
CLK_ADV712x,
nCSYNC_ADV712x,
// nBLANK_ADV712x,
VD_o, // video component data vector
// Sync / Debug / Filter AddOn Output
nCSYNC,
nVSYNC_or_F2,
nHSYNC_or_F1,
// Jumper VGA Sync / Filter AddOn
UseVGA_HVSync, // (J1) use Filter out if '0'; use /HS and /VS if '1'
nFilterBypass, // (J1) bypass filter if '0'; set filter as output if '1'
// (only applicable if UseVGA_HVSync is '0')
// Jumper Video Output Type and Scanlines
nEN_RGsB, // (J2) generate RGsB if '0'
nEN_YPbPr, // (J2) generate RGsB if '0' (no RGB, no RGsB (overrides nEN_RGsB))
SL_str, // (J3) Scanline strength (only for line multiplication and not for 480i bob-deint.)
n240p, // (J4) no linemultiplication for 240p if '0' (beats n480i_bob)
n480i_bob // (J4) bob de-interlacing of 480i material if '0'
);
parameter [3:0] hdl_fw_main = 4'd1;
parameter [7:0] hdl_fw_sub = 8'd67;
`include "vh/n64adv_vparams.vh"
input VCLK;
input nVDSYNC;
input [color_width_i-1:0] VD_i;
input SYS_CLK;
input CTRL_i;
inout nRST;
output CLK_ADV712x;
output nCSYNC_ADV712x;
// output nBLANK_ADV712x;
output [3*color_width_o-1:0] VD_o;
output nCSYNC;
output nVSYNC_or_F2;
output nHSYNC_or_F1;
input UseVGA_HVSync;
input nFilterBypass;
input nEN_RGsB;
input nEN_YPbPr;
input [1:0] SL_str;
input n240p;
input n480i_bob;
// input registering
wire VCLK_w = VCLK;
wire nVDSYNC_w;
wire [6:0] VD_w;
register_sync #(
.reg_width(8),
.reg_preset(8'h00)
) inp_vregs_u(
.clk(VCLK_w),
.clk_en(1'b1),
.nrst(1'b1),
.reg_i({nVDSYNC,VD_i}),
.reg_o({nVDSYNC_w,VD_w})
);
// housekeeping of clocks and resets
wire [1:0] MANAGE_VPLL;
wire VCLK_PLL_LOCKED;
wire [1:0] VCLK_Tx_select_w;
wire nVRST, VCLK_Tx_w, nVRST_Tx_w;
wire [2:0] CLKs_controller, nSRST;
n64adv_clk_n_rst_hk clk_n_rst_hk_u(
.VCLK(VCLK_w),
.SYS_CLK(SYS_CLK),
.nRST(nRST),
.nVRST(nVRST),
.VCLK_PLL_LOCKED(VCLK_PLL_LOCKED),
.VCLK_select(VCLK_Tx_select_w),
.VCLK_Tx(VCLK_Tx_w),
.nVRST_Tx(nVRST_Tx_w),
.CLKs_controller(CLKs_controller),
.nSRST(nSRST)
);
// controller module
wire [12:0] PPUState;
wire [ 7:0] JumperCfgSet = {UseVGA_HVSync,~nFilterBypass,n240p,~n480i_bob,~SL_str,~nEN_YPbPr,(nEN_YPbPr & ~nEN_RGsB)}; // (~nEN_YPbPr | nEN_RGsB) ensures that not both jumpers are set and passed through the NIOS II
wire USE_VPLL;
wire [68:0] PPUConfigSet;
wire OSD_VSync;
wire [24:0] OSDWrVector;
wire [ 1:0] OSDInfo;
n64adv_controller #({hdl_fw_main,hdl_fw_sub}) n64adv_controller_u(
.CLKs(CLKs_controller),
.nRST(nRST),
.nSRST(nSRST),
.CTRL(CTRL_i),
.PPUState({PPUState[12:10],VCLK_PLL_LOCKED,PPUState[8:0]}),
.JumperCfgSet(JumperCfgSet),
.USE_VPLL(USE_VPLL),
.PPUConfigSet(PPUConfigSet),
.OSD_VSync(OSD_VSync),
.OSDWrVector(OSDWrVector),
.OSDInfo(OSDInfo),
.VCLK(VCLK_w),
.nVDSYNC(nVDSYNC_w),
.VD_VSi(VD_w[3]),
.nVRST(nVRST)
);
// picture processing module
n64adv_ppu_top n64adv_ppu_u(
.VCLK(VCLK_w),
.nVRST(nVRST),
.nVDSYNC(nVDSYNC_w),
.VD_i(VD_w),
.PPUState(PPUState),
.ConfigSet(PPUConfigSet),
.OSDCLK(CLKs_controller[0]),
.OSD_VSync(OSD_VSync),
.OSDWrVector(OSDWrVector),
.OSDInfo(OSDInfo),
.USE_VPLL(USE_VPLL),
.VCLK_Tx_select(VCLK_Tx_select_w),
.VCLK_Tx(VCLK_Tx_w),
.nVRST_Tx(nVRST_Tx_w),
// .nBLANK(nBLANK_ADV712x),
.VD_o(VD_o),
.nCSYNC({nCSYNC,nCSYNC_ADV712x}),
.UseVGA_HVSync(UseVGA_HVSync),
.nVSYNC_or_F2(nVSYNC_or_F2),
.nHSYNC_or_F1(nHSYNC_or_F1)
);
assign CLK_ADV712x = VCLK_Tx_w;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXBP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFXBP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXBP_SYMBOL_V
|
// Emulate CSOC Scan Chain and IOs
module csoc #(
parameter NREGS = 1918
)(
input clk_i,
input rstn_i,
input uart_read_i,
output uart_write_o,
input [7:0] data_i,
output [7:0] data_o,
input xtal_a_i,
output xtal_b_o,
output clk_o,
input test_tm_i,
input test_se_i
);
reg [NREGS-1:0] ffs_chain, ffs_chain_nxt;
reg uart_write, uart_write_nxt;
reg [7:0] data_or, data_or_nxt;
reg xtal_b, xtal_b_nxt;
reg clk_or, clk_or_nxt;
always @(posedge clk_i or negedge rstn_i) begin
if (!rstn_i) begin
uart_write <= 0;
data_or <= 0;
ffs_chain <= 0;
xtal_b <= 0;
clk_or <= 0;
end
else begin
data_or <= data_or_nxt;
uart_write <= uart_write_nxt;
clk_or <= clk_or_nxt;
xtal_b <= xtal_b_nxt;
ffs_chain <= ffs_chain_nxt;
end
end
always @(*) begin
uart_write_nxt = uart_write;
clk_or_nxt = clk_or;
xtal_b_nxt = xtal_b;
if (test_se_i) begin
ffs_chain_nxt = {data_i[0], ffs_chain[NREGS-1:1]};
data_or_nxt = {7'h0, ffs_chain[0]};
end
else begin
ffs_chain_nxt = ffs_chain;
data_or_nxt = data_or;
end
end
assign uart_write_o = uart_write;
assign data_o = data_or;
assign clk_o = xtal_a_i;
assign xtal_b_o = ~ xtal_a_i;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A32O_FUNCTIONAL_PP_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32O_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int N, M, cnt[101]; int main() { int N, M, cnt[101] = {0}; scanf( %d%d , &N, &M); for (int i = 0; i < N; i++) { int t; scanf( %d , &t); int now = M - t; int ans = i; for (int j = 1; j <= 100; j++) { int get = min(now / j, cnt[j]); now -= get * j; ans -= get; } cnt[t]++; printf( %d%c , ans, i == N - 1 ? 10 : 32); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4BB_2_V
`define SKY130_FD_SC_LP__NOR4BB_2_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4bb_2 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4bb_2 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4BB_2_V
|
#include <bits/stdc++.h> using namespace std; int n, k, a[10010]; long long ans; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); for (int i = 1; i <= k; i++) ans += a[i]; printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> bool compare(int a, int b) { return a < b; } void swapped(char s1, char s2) { char temp = s1; s1 = s2; s2 = temp; } long long int modd(long long int n, long long int k) { return (k + (n % k)) % k; } bool i(long long first) { return first && (!(first & (first - 1))); } bool p(long long n) { long long i, flag = 1; for (i = 2; i <= sqrt(n); i++) { if (n % i == 0) { flag = 0; break; } } if (flag == 1) { return true; } else { return false; } return 0; } using namespace std; void solve() { long long n; cin >> n; if (n == 1) { cout << FastestFinger << n ; return; } if (n == 2) { cout << Ashishgup << n ; return; } if (i(n)) { cout << FastestFinger << n ; return; } if (n & 1) { cout << Ashishgup << n ; return; } n /= 2; if (p(n)) { cout << FastestFinger << n ; return; } else { cout << Ashishgup << n ; return; } } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool upmin(T &x, T y) { return y < x ? x = y, 1 : 0; } template <typename T> inline bool upmax(T &x, T y) { return x < y ? x = y, 1 : 0; } const long double eps = 1e-9; const long double pi = acos(-1); const int oo = 1 << 30; const long long loo = 1ll << 60; const int mods = 1e9 + 7; const int inv2 = (mods + 1) >> 1; const int MAXN = 510005; const int INF = 0x3f3f3f3f; namespace FastIO { constexpr int SIZE = (1 << 21) + 1; int num = 0, f; char ibuf[SIZE], obuf[SIZE], que[65], *iS, *iT, *oS = obuf, *oT = obuf + SIZE - 1, c; inline void flush() { fwrite(obuf, 1, oS - obuf, stdout); oS = obuf; } inline void putc(char c) { *oS++ = c; if (oS == oT) flush(); } inline void getc(char &c) { for (c = (iS == iT ? (iT = ((iS = ibuf) + fread(ibuf, 1, SIZE, stdin)), (iS == iT ? EOF : *iS++)) : *iS++); !isalpha(c) && c != EOF; c = (iS == iT ? (iT = ((iS = ibuf) + fread(ibuf, 1, SIZE, stdin)), (iS == iT ? EOF : *iS++)) : *iS++)) ; } inline void reads(char *st) { char c; int n = 0; getc(st[++n]); for (c = (iS == iT ? (iT = ((iS = ibuf) + fread(ibuf, 1, SIZE, stdin)), (iS == iT ? EOF : *iS++)) : *iS++); isalpha(c); c = (iS == iT ? (iT = ((iS = ibuf) + fread(ibuf, 1, SIZE, stdin)), (iS == iT ? EOF : *iS++)) : *iS++)) st[++n] = c; st[n + 1] = 0 ; } template <class I> inline void read(I &x) { for (f = 1, c = (iS == iT ? (iT = ((iS = ibuf) + fread(ibuf, 1, SIZE, stdin)), (iS == iT ? EOF : *iS++)) : *iS++); c < 0 || c > 9 ; c = (iS == iT ? (iT = ((iS = ibuf) + fread(ibuf, 1, SIZE, stdin)), (iS == iT ? EOF : *iS++)) : *iS++)) if (c == - ) f = -1; for (x = 0; c >= 0 && c <= 9 ; c = (iS == iT ? (iT = ((iS = ibuf) + fread(ibuf, 1, SIZE, stdin)), (iS == iT ? EOF : *iS++)) : *iS++)) x = (x << 3) + (x << 1) + (c & 15); x *= f; } template <class I> inline void print(I x) { if (x < 0) putc( - ), x = -x; if (!x) putc( 0 ); while (x) que[++num] = x % 10 + 48, x /= 10; while (num) putc(que[num--]); } struct Flusher_ { ~Flusher_() { flush(); } } io_Flusher_; } // namespace FastIO using FastIO ::print; using FastIO ::putc; using FastIO ::read; using FastIO ::reads; char st[1005], ST[1005]; long long f[1005][1005], K; int ch[MAXN][26], num = 0, n, m, nodenum = 1, a[MAXN]; pair<int, int> flag[MAXN]; void solve(int x) { if (!x) return; for (int i = 25; i >= 0; --i) solve(ch[x][i]); if (flag[x].first) a[++num] = x; } void insert(int l, int r) { int nw = 1; for (int i = l; i <= r; ++i) { if (!ch[nw][st[i] - a ]) ch[nw][st[i] - a ] = ++nodenum; nw = ch[nw][st[i] - a ]; } flag[nw] = make_pair(l, r); } long long check(int x) { int len = 0; for (int i = flag[a[x]].first; i <= flag[a[x]].second; ++i) ST[++len] = st[i]; for (int i = 0; i <= n; ++i) for (int j = 0; j <= m; ++j) f[i][j] = 0; f[0][0] = 1; for (int i = 0; i < n; ++i) { int id = len; for (int j = 1; j <= len && i + j - 1 <= n; ++j) if (st[i + j] < ST[j]) { id = INF; break; } else if (st[i + j] > ST[j]) { id = j; break; } if (i + id <= n) { for (int j = 0; j < m; ++j) if (f[i + id][j + 1] < loo) f[i + id][j + 1] += f[i][j]; } for (int j = 1; j <= m; ++j) if (f[i + 1][j] < loo) f[i + 1][j] += f[i][j]; } return f[n][m]; } signed main() { read(n), read(m), read(K), reads(st); for (int i = 1; i <= n; ++i) for (int j = i; j <= n; ++j) insert(i, j); solve(1); int l = 1, r = num; while (l < r) { int mid = (l + r) >> 1; if (check(mid) >= K) r = mid; else l = mid + 1; } for (int i = flag[a[l]].first; i <= flag[a[l]].second; ++i) putc(st[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b = 0; cin >> a; if (a == 0) { cout << 0 ; return 0; } b = a + 1; if (b % 2 == 0) { cout << b / 2; } else cout << b; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module start_for_Loop_lojbC_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module start_for_Loop_lojbC (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_Loop_lojbC_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_start_for_Loop_lojbC_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long md = 1000000007; long long bexp(long long a, long long b) { if (b == 0) return 1; if (b == 1) return a; long long r = bexp(a, b / 2); r = r * r; if (b % 2 == 0) return r; else return r * a; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int test_case = 1; cin >> test_case; while (test_case--) { long long n, i, j, m, k; cin >> n; long long a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } long long pr = -1; long long ans = 0; for (i = 0; i < n; i++) { if (a[i] != 0) { if (pr == -1) { pr = i; } else { ans += i - pr - 1; pr = i; } } } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, A, B, C, T; int temp[1005]; int main() { cin >> n >> A >> B >> C >> T; long long ans = 0; for (int i = 1; i <= n; i++) cin >> temp[i]; ans = n * A; if (C > B) { for (int i = 1; i <= n; i++) ans += (C - B) * (T - temp[i]); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; int main() { ios::sync_with_stdio(false); cin.tie(0); int k; cin >> k; int sum = (1 << 18) - 1; cout << 3 3 n ; cout << sum << << (1 << 17) << << 0 << n ; cout << k << << sum << << 0 << n ; cout << 0 << << k << << k << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, v[100010], c[100010], l[100010], r, mx = 0; map<long long, long long> dp, path, acp; vector<long long> ans, vt[3 * 100010]; void getdp(long long x) { long long i, ss; dp.clear(); path.clear(); acp.clear(); for (i = 0; i < vt[x].size(); i++) { dp[l[vt[x][i]]] = dp[l[vt[x][i]] + c[vt[x][i]]] = -1000000000000000000; path[l[vt[x][i]]] = path[l[vt[x][i]] + c[vt[x][i]]] = -1; acp[vt[x][i]] = -1; } dp[0] = 0; for (ss = 0; ss < vt[x].size(); ss++) { i = vt[x][ss]; if (l[i] == 0) { if (v[i] > dp[l[i] + c[i]] || path[l[i] + c[i]] == -1) { dp[l[i] + c[i]] = v[i]; path[l[i] + c[i]] = i; acp[i] = -1; } } else { if (path[l[i]] == -1) { continue; } if (dp[l[i]] + v[i] > dp[l[i] + c[i]] || path[l[i] + c[i]] == -1) { dp[l[i] + c[i]] = dp[l[i]] + v[i]; path[l[i] + c[i]] = i; acp[i] = path[l[i]]; } } } i = path[x]; if (dp[x] > mx) { mx = dp[x]; ans.clear(); while (i != -1) { ans.push_back(i); i = acp[i]; } } return; } int main() { long long i, j, mx = 0; scanf( %lld , &n); for (i = 0; i < n; i++) { scanf( %lld%lld%lld%lld , &v[i], &c[i], &l[i], &r); vt[c[i] + l[i] + r].push_back(i); } for (i = 0; i <= 300000; i++) { if (vt[i].empty()) { continue; } getdp(i); } sort(ans.begin(), ans.end()); printf( %lld n , (long long)ans.size()); for (i = 0; i < ans.size(); i++) { printf( %lld , ans[i] + 1); } puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; using INT = long long; int a[200100], b[200100]; map<int, int> mp[2]; int arr[200100]; map<int, int> vst; int main() { int n, st; cin >> n >> st; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } int m, ed; cin >> m >> ed; for (int i = 1; i <= m; i++) { scanf( %d , &b[i]); } int d = 1; int ans = 1; for (int j = 1; j <= 30; j++) { mp[0].clear(); mp[1].clear(); int x = (1 << j); int nn = 0; for (int i = 1; i <= n; i++) { int r = a[i] % x; mp[0][r]++; ans = max(ans, mp[0][r]); arr[++nn] = r; } for (int i = 1; i <= m; i++) { int r = b[i] % x; mp[1][r]++; ans = max(ans, mp[1][r] + mp[0][(r + x / 2) % x]); arr[++nn] = r; } } for (int i = 1; i <= n; i++) vst[a[i]] = 1; for (int i = 1; i <= m; i++) if (vst[b[i]]) ans = max(ans, 2); cout << ans << endl; }
|
module wavegrp_info (
wf_wr_en,
wr_wf_tag,
wr_wg_wf_count,
wr_wfid,
halt,
halt_wfid,
rd_wfid,
rd_wgid,
rd_wf_count,
clk,
rst
);
input clk;
input rst;
input wf_wr_en;
input [14:0] wr_wf_tag;
input [3:0] wr_wg_wf_count;
input [5:0] wr_wfid;
input [5:0] rd_wfid;
input halt;
input [5:0] halt_wfid;
output [5:0] rd_wgid;
output [3:0] rd_wf_count;
reg [5:0] rd_wgid;
reg [3:0] rd_wf_count;
reg [879:0] write_data;
reg [39:0] write_en;
reg cam_hit;
reg [21:0] cam_data;
wire [879:0] regfile_out;
regfile #(22) wg_cnt_store[39:0] (
write_data, write_en, regfile_out, clk, rst
);
//assign regfile_out = write_data;
integer i;
//always @(wf_wr_en or wr_wfid or wr_wf_tag /*or regfile_out*/)
always @(*)
begin
cam_hit = 1'b0;
cam_data = 22'b0;
if (wf_wr_en) begin
for(i = 0; i < 40; i=i+1) begin
if(/*!cam_hit && */regfile_out[(i*22)+21] &&
(regfile_out[((i*22)+20)-:11] == wr_wf_tag[14-:11]))
begin
cam_data = regfile_out[((i*22)+21)-:22];
cam_hit = 1'b1;
end
end
end
end
//always @(halt or halt_wfid or cam_hit /*or cam_data*/ or wf_wr_en or wr_wf_tag or wr_wfid or wr_wg_wf_count /*or regfile_out*/) begin
always @(*) begin
write_en = 40'b0;
write_data = regfile_out;
if(halt) begin
write_data[(halt_wfid*22)+21-:22] = 22'd0;
write_en[halt_wfid] = 1'b1;
end
if (wf_wr_en) begin
if(cam_hit == 1'b1) begin
write_data[(wr_wfid*22)+21-:22] = cam_data;
write_en[wr_wfid] = 1'b1;
end
else begin
write_data[(wr_wfid*22)+21-:22] = {
1'b1, wr_wf_tag[14-:11], wr_wfid, wr_wg_wf_count
};
write_en[wr_wfid] = 1'b1;
end
end
end
always @(rd_wfid or regfile_out)
begin
rd_wgid = regfile_out[(rd_wfid*22)+9-:6];
rd_wf_count = regfile_out[(rd_wfid*22)+3-:4];
end
endmodule
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) #pragma comment(linker, /STACK:336777216 ) using namespace std; int IT_MAX = 1 << 18; const long long MOD = 1000000007; const int INF = 0x3f3f3f3f; const long long LL_INF = 0x3f3f3f3f3f3f3f3f; const double PI = acos(-1); const double ERR = 1e-10; int ans[100050]; void aa1(int x) { if (x == 2) { ans[1] = 2; ans[2] = 1; return; } int i; for (i = 2; i <= 30; i++) if ((1 << i) > x + 2) break; int v = i - 1; if (x + 2 == (1 << v)) { for (int i = 1; i <= x; i++) ans[i] = x + 1 - i; return; } int nx; for (i = (1 << v); i <= x; i++) { int t = (1 << (v + 1)) - 1 - i; ans[i] = t; ans[t] = i; nx = t; } aa1(nx - 1); } void aa2(int N) { int v = 1; while (v * 2 <= N) v *= 2; int i; for (i = 2; i < v; i += 2) { ans[i] = i + 1; ans[i + 1] = i; } vector<int> Vu; for (i = v; i <= N; i++) Vu.push_back(i); if (Vu.back() % 2 == 0) swap(Vu[Vu.size() - 2], Vu.back()); ans[Vu.back()] = 1; ans[1] = Vu.back(); Vu.pop_back(); for (i = 0; i < Vu.size(); i++) ans[Vu[i]] = Vu[(i + 1) % Vu.size()]; } int main() { int N; scanf( %d , &N); if (N % 2 == 1) printf( NO n ); else { printf( YES n ); aa1(N); for (int i = 1; i <= N; i++) printf( %d , ans[i]); printf( n ); } if (N <= 5) printf( NO n ); else { int t = 1; while (t * 2 <= N) t *= 2; if (t == N) return !printf( NO n ); if (t + 1 == N) { ans[N - 1] = N; ans[N] = N - 1; aa2(N - 2); } else aa2(N); printf( YES n ); for (int i = 1; i <= N; i++) printf( %d , ans[i]); printf( n ); } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:30:52 01/30/2011
// Design Name: MiniAlu
// Module Name: D:/Proyecto/RTL/Dev/MiniALU/TestBench.v
// Project Name: MiniALU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MiniAlu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`include "Defintions.v"
module TestBench;
// Inputs
reg Clock;
reg Reset;
// Outputs
wire [7:0] oLed;
wire wHS, wVS, vga_red, vga_green, vga_blue;
// Instantiate the Unit Under Test (UUT)
/*MiniAlu uut (
.Clock(Clock),
.Reset(Reset),
.oLed(oLed)
);*/
Bichillo semiCLK(
.Clock(Clock),
.Reset(Reset),
.VGA_HSYNC(wHS),
.VGA_VSYNC(wVS),
.VGA_RED(vga_red),
.VGA_GREEN(vga_green),
.VGA_BLUE(vga_blue)
);
/*
RAM_SINGLE_READ_PORT # (3,24,640*480) VideoMemory
(
.Clock( Clock ),
.iWriteEnable( EnableALU ),
.iReadAddress(wHS*wVS+wHS ),
.iWriteAddress( ),
.iDataIn( ),
.oDataOut({oVGA_R,oVGA_G,oVGA_B})
);*/
/* VGA_Controller vga (
.Clock(Clock),
.Enable(1'b1),
.Reset(Reset),
.iPixel({oVGA_R,oVGA_G,oVGA_B}),
.oHorizontalSync(wHS),
.oVerticalSync(wVS),
.oRed(vga_red),
.oGreen(vga_green),
.oBlue(vga_blue),
.oQHS (wHS)
.oQVS (wVS)
);*/
always
begin
#5 Clock = ! Clock;
end
initial begin
$dumpfile("signals.vcd");
$dumpvars;
// Initialize Inputs
Clock = 0;
Reset = 0;
// Wait 100 ns for global reset to finish
#100;
Reset = 1;
#50
Reset = 0;
// Add stimulus here
#18000000
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; set<string> g; g.insert(s); int n = s.size(); for (int k = 0; k < s.size(); k++) { string s1 = ; s1 += s[n - 1]; for (int i = 0; i < s.size() - 1; i++) { s1 += s[i]; } s = s1; g.insert(s); } cout << g.size(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long n, k; cin >> n >> k; if (k == n) { cout << Alice n ; continue; } if (k > n || k % 3 != 0) { if (n % 3 == 0) { cout << Bob n ; } else { cout << Alice n ; } continue; } long long z = n % (k + 1); if (z % 3 == 0 && z != k) { cout << Bob n ; } else { cout << Alice n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; vector<int> a[1000001]; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; ++i) { int g; scanf( %d , &g); while (g--) { int p; scanf( %d , &p); a[p].push_back(i); } } sort(a, a + m + 1); int t = 1, ans = 1; for (int i = 2; i <= m; ++i) { if (a[i] == a[i - 1]) ans = (long long)ans * ++t % mod; else t = 1; } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_PP_SYMBOL_V
`define SKY130_FD_SC_HD__FILL_PP_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fill (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_PP_SYMBOL_V
|
`timescale 1ns/1ps
module tb_cocotb #(
parameter DATA_WIDTH = 32, //This is the output bus
parameter ADDR_WIDTH = 32,
parameter INTERRUPT_WIDTH = 32
)(
//Virtual Host Interface Signals
input clk,
input rst,
input [31:0] test_id,
input CMD_EN,
output CMD_ERROR,
output CMD_ACK,
output [31:0] CMD_STATUS,
output CMD_INTERRUPT,
input [ADDR_WIDTH - 1:0] CMD_ADR,
input CMD_WR_RD, //1 = WRITE, 0 = READ
input [3:0] CMD_BYTE_EN,
input [31:0] CMD_WR_DATA,
output [31:0] CMD_RD_DATA,
//***************** AXI Bus ************************************************
//bus write addr path
output [3:0] AXIS_AWID, //Write ID
output [ADDR_WIDTH - 1:0] AXIS_AWADDR, //Write Addr Path Address
output [7:0] AXIS_AWLEN, //Write Addr Path Burst Length
output [2:0] AXIS_AWSIZE, //Write Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output [1:0] AXIS_AWBURST, //Write Addr Path Burst Type
// 0 = Fixed
// 1 = Incrementing
// 2 = wrap
output [1:0] AXIS_AWLOCK, //Write Addr Path Lock (atomic) information
// 0 = Normal
// 1 = Exclusive
// 2 = Locked
output [3:0] AXIS_AWCACHE, //Write Addr Path Cache Type
output [2:0] AXIS_AWPROT, //Write Addr Path Protection Type
output AXIS_AWVALID, //Write Addr Path Address Valid
input AXIS_AWREADY, //Write Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus write data
output [3:0] AXIS_WID, //Write ID
output [DATA_WIDTH - 1: 0] AXIS_WDATA, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
output [(DATA_WIDTH >> 3) - 1:0] AXIS_WSTRB, //Write Strobe (a 1 in the write is associated with the byte to write)
output AXIS_WLAST, //Write Last transfer in a write burst
output AXIS_WVALID, //Data through this bus is valid
input AXIS_WREADY, //Slave is ready for data
//Write Response Channel
input [3:0] AXIS_BID, //Response ID (this must match awid)
input [1:0] AXIS_BRESP, //Write Response
// 0 = OKAY
// 1 = EXOKAY
// 2 = SLVERR
// 3 = DECERR
input AXIS_BVALID, //Write Response is:
// 1 = Available
// 0 = Not Available
output AXIS_BREADY, //WBM Ready
//bus read addr path
output [3:0] AXIS_ARID, //Read ID
output [ADDR_WIDTH - 1:0] AXIS_ARADDR, //Read Addr Path Address
output [7:0] AXIS_ARLEN, //Read Addr Path Burst Length
output [2:0] AXIS_ARSIZE, //Read Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output [1:0] AXIS_ARBURST, //Read Addr Path Burst Type
output [1:0] AXIS_ARLOCK, //Read Addr Path Lock (atomic) information
output [3:0] AXIS_ARCACHE, //Read Addr Path Cache Type
output [2:0] AXIS_ARPROT, //Read Addr Path Protection Type
output AXIS_ARVALID, //Read Addr Path Address Valid
input AXIS_ARREADY, //Read Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus read data
input [3:0] AXIS_RID, //Write ID
input [DATA_WIDTH - 1: 0] AXIS_RDATA, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
input [1:0] AXIS_RRESP,
input [(DATA_WIDTH >> 3) - 1:0] AXIS_RSTRB, //Write Strobe (a 1 in the write is associated with the byte to write)
input AXIS_RLAST, //Write Last transfer in a write burst
input AXIS_RVALID, //Data through this bus is valid
output AXIS_RREADY, //WBM is ready for data
// 1 = WBM Ready
// 0 = Slave Ready
input [INTERRUPT_WIDTH - 1:0] i_interrupts
);
//Local Parameters
localparam INVERT_AXI_RESET = 0;
localparam DEFAULT_TIMEOUT = 32'd100000000; //1 Second at 100MHz
//Registers/Wires
reg r_rst;
wire [INTERRUPT_WIDTH - 1:0] w_interrupts;
assign AXIS_AWLEN = 0;
assign AXIS_AWBURST = 1;
assign AXIS_AWPROT = 0;
assign AXIS_ARBURST = 1;
assign AXIS_ARPROT = 0;
//Submodules
axi_lite_master #(
.INVERT_AXI_RESET (INVERT_AXI_RESET ),
.ADDR_WIDTH (ADDR_WIDTH ),
.INTERRUPT_WIDTH (INTERRUPT_WIDTH ),
.DEFAULT_TIMEOUT (DEFAULT_TIMEOUT )
) am (
.clk (clk ),
.rst (r_rst ),
//************* User Facing Side *******************************************
.i_cmd_en (CMD_EN ),
.o_cmd_error (CMD_ERROR ),
.o_cmd_ack (CMD_ACK ),
.o_cmd_status (CMD_STATUS ),
.i_cmd_addr (CMD_ADR ),
.i_cmd_wr_rd (CMD_WR_RD ),
.i_cmd_byte_en (CMD_BYTE_EN ),
.i_cmd_data (CMD_WR_DATA ),
.o_cmd_data (CMD_RD_DATA ),
.o_cmd_interrupt (CMD_INTERRUPT ),
//***************** AXI Bus ************************************************
//bus write addr path
.o_awid (AXIS_AWID ),
.o_awaddr (AXIS_AWADDR ),
.o_awsize (AXIS_AWSIZE ),
.o_awvalid (AXIS_AWVALID ),
.i_awready (AXIS_AWREADY ),
//bus write data
.o_wid (AXIS_WID ),
.o_wdata (AXIS_WDATA ),
.o_wstrobe (AXIS_WSTRB ),
.o_wlast (AXIS_WLAST ),
.o_wvalid (AXIS_WVALID ),
.i_wready (AXIS_WREADY ),
//Write Response Channel
.i_bid (AXIS_BID ),
.i_bresp (AXIS_BRESP ),
.i_bvalid (AXIS_BVALID ),
.o_bready (AXIS_BREADY ),
//bus read addr path
.o_arid (AXIS_ARID ),
.o_araddr (AXIS_ARADDR ),
.o_arlen (AXIS_ARLEN ),
.o_arsize (AXIS_ARSIZE ),
.o_arvalid (AXIS_ARVALID ),
.i_arready (AXIS_ARREADY ),
//bus read data
.i_rid (AXIS_RID ),
.i_rdata (AXIS_RDATA ),
.i_rresp (AXIS_RRESP ),
.i_rstrobe (AXIS_RSTRB ),
.i_rlast (AXIS_RLAST ),
.i_rvalid (AXIS_RVALID ),
.o_rready (AXIS_RREADY ),
//nterrupts
.i_interrupts (i_interrupts )
);
//There is a timing thing in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, min, max; std::cin >> n >> m >> min >> max; int a[m]; int maxHit = 0; int minHit = 0; for (int i = 0; i < m; ++i) { std::cin >> a[i]; if (a[i] == min) { minHit = 1; } else if (a[i] == max) { maxHit = 1; } if (a[i] > max || a[i] < min) { std::cout << Incorrect ; return 0; } } if (minHit != 1 && maxHit != 1) { if (n - m < 2) { std::cout << Incorrect ; } else { std::cout << Correct ; } } else if (minHit != 1 || maxHit != 1) { if (n - m < 1) { std::cout << Incorrect ; } else { std::cout << Correct ; } } else { std::cout << Correct ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2B_1_V
`define SKY130_FD_SC_HS__OR2B_1_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2b_1 (
X ,
A ,
B_N ,
VPWR,
VGND
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2b_1 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2B_1_V
|
//*****************************************************************************
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
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// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : infrastructure.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:09 $
// \ \ / \ Date Created : Mon Mar 2 2009
// \___\/\___\
//
//Device : Spartan-6
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : Clock generation/distribution and reset synchronization
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ns/1ps
module infrastructure #
(
parameter C_INCLK_PERIOD = 5000,
parameter C_RST_ACT_LOW = 1,
parameter C_INPUT_CLK_TYPE = "DIFFERENTIAL",
parameter C_CLKOUT0_DIVIDE = 1,
parameter C_CLKOUT1_DIVIDE = 1,
parameter C_CLKOUT2_DIVIDE = 16,
parameter C_CLKOUT3_DIVIDE = 8,
parameter C_CLKFBOUT_MULT = 2,
parameter C_DIVCLK_DIVIDE = 1
)
(
input sys_clk_p,
input sys_clk_n,
input sys_clk,
input sys_rst_i,
output clk0,
output rst0,
output async_rst,
output sysclk_2x,
output sysclk_2x_180,
output mcb_drp_clk,
output pll_ce_0,
output pll_ce_90,
output pll_lock
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on PLL/DCM lock status)
localparam RST_SYNC_NUM = 25;
localparam CLK_PERIOD_NS = C_INCLK_PERIOD / 1000.0;
localparam CLK_PERIOD_INT = C_INCLK_PERIOD/1000;
wire clk_2x_0;
wire clk_2x_180;
wire clk0_bufg;
wire clk0_bufg_in;
wire mcb_drp_clk_bufg_in;
wire clkfbout_clkfbin;
wire locked;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
reg powerup_pll_locked;
reg syn_clk0_powerup_pll_locked;
wire sys_rst;
wire bufpll_mcb_locked;
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
assign sys_rst = C_RST_ACT_LOW ? ~sys_rst_i: sys_rst_i;
assign clk0 = clk0_bufg;
assign pll_lock = bufpll_mcb_locked;
generate
if (C_INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM ("TRUE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (C_INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
/*
IBUFG u_ibufg_sys_clk
(
.I (sys_clk),
.O (sys_clk_ibufg)
);
*/
assign sys_clk_ibufg = sys_clk;
end
endgenerate
//***************************************************************************
// Global clock generation and distribution
//***************************************************************************
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (CLK_PERIOD_NS),
.CLKIN2_PERIOD (CLK_PERIOD_NS),
.CLKOUT0_DIVIDE (C_CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (C_CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (C_CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (C_CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (180.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.SIM_DEVICE ("SPARTAN6"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (C_DIVCLK_DIVIDE),
.CLKFBOUT_MULT (C_CLKFBOUT_MULT),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.005000)
)
u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (sys_rst),
.CLKFBDCM (),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (clk_2x_0),
.CLKOUT1 (clk_2x_180),
.CLKOUT2 (clk0_bufg_in),
.CLKOUT3 (mcb_drp_clk_bufg_in),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (locked)
);
BUFG U_BUFG_CLK0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);
BUFGCE U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in),
.CE (locked)
);
always @(posedge mcb_drp_clk , posedge sys_rst)
if(sys_rst)
powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
powerup_pll_locked <= 1'b1;
always @(posedge clk0_bufg , posedge sys_rst)
if(sys_rst)
syn_clk0_powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
syn_clk0_powerup_pll_locked <= 1'b1;
//***************************************************************************
// Reset synchronization
// NOTES:
// 1. shut down the whole operation if the PLL hasn't yet locked (and
// by inference, this means that external SYS_RST_IN has been asserted -
// PLL deasserts LOCKED as soon as SYS_RST_IN asserted)
// 2. asynchronously assert reset. This was we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers).
// reset deassertion is synchronous.
// 3. asynchronous reset only look at pll_lock from PLL during power up. After
// power up and pll_lock is asserted, the powerup_pll_locked will be asserted
// forever until sys_rst is asserted again. PLL will lose lock when FPGA
// enters suspend mode. We don't want reset to MCB get
// asserted in the application that needs suspend feature.
//***************************************************************************
assign async_rst = sys_rst | ~powerup_pll_locked;
// synthesis attribute max_fanout of rst0_sync_r is 10
assign rst_tmp = sys_rst | ~syn_clk0_powerup_pll_locked;
always @(posedge clk0_bufg or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
BUFPLL_MCB BUFPLL_MCB1
( .IOCLK0 (sysclk_2x),
.IOCLK1 (sysclk_2x_180),
.LOCKED (locked),
.GCLK (mcb_drp_clk),
.SERDESSTROBE0 (pll_ce_0),
.SERDESSTROBE1 (pll_ce_90),
.PLLIN0 (clk_2x_0),
.PLLIN1 (clk_2x_180),
.LOCK (bufpll_mcb_locked)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int cnt = 0, count = 0; for (int i = 0; i < n; i++) { if (s[i] == 8 ) cnt++; } while (cnt) { n = n - 1; cnt = cnt - 1; if (n / 10 > 0) { count++; n = n - 10; } } cout << count; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32OI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A32OI_FUNCTIONAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32OI_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; int n; struct Data { int s, id; bool operator<(const Data &a) const { return s < a.s; } } da[N]; int a[N], b[N]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { int s; scanf( %d , &s); da[i] = Data{s, i}; } sort(da, da + n); for (int i = 0; i < (n + 2) / 3; i++) { a[da[i].id] = i; b[da[i].id] = da[i].s - i; } int x = (n + 2) / 3; for (int i = x; i < min(x + x, n); i++) { a[da[i].id] = 0; b[da[i].id] = da[i].s; } for (int i = x + x; i < n; i++) { a[da[i].id] = da[i].s - (n - i - 1); b[da[i].id] = n - i - 1; } puts( YES ); for (int i = 0; i < n; i++) { printf( %d%c , a[i], n [i == n - 1]); } for (int i = 0; i < n; i++) { printf( %d%c , b[i], n [i == n - 1]); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14.03.2017 23:31:58
// Design Name:
// Module Name: frequency_analyzer_synch
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module frequency_analyzer_synch #
(
parameter integer CLOCK = 100000000,
parameter integer FREQUENCY = 2000
)
(
input wire clock,
input wire reset,
input wire enable,
output reg start_analyzer_0,
output reg stop_analyzer_0,
output reg start_analyzer_1,
output reg stop_analyzer_1
);
localparam integer frequency_ticks = CLOCK / FREQUENCY;
localparam integer signal_delay = 40;
integer clock_counter;
always @(posedge clock)
begin
if(!reset)
clock_counter <= 0;
else if(enable)
begin
clock_counter <= clock_counter + 1;
if(clock_counter >= frequency_ticks + frequency_ticks + signal_delay)
clock_counter <= 0;
end
end
always @(posedge clock)
begin
if(!reset)
begin
start_analyzer_0 <= 0;
stop_analyzer_0 <= 0;
start_analyzer_1 <= 0;
stop_analyzer_1 <= 0;
end
else if(enable)
begin
if(clock_counter < signal_delay)
begin
start_analyzer_0 <= 1;
stop_analyzer_0 <= 0;
start_analyzer_1 <= 0;
stop_analyzer_1 <= 0;
end
else if(clock_counter >= signal_delay && clock_counter < frequency_ticks)
begin
start_analyzer_0 <= 0;
stop_analyzer_0 <= 0;
start_analyzer_1 <= 0;
stop_analyzer_1 <= 0;
end
else if(clock_counter >= frequency_ticks && clock_counter < frequency_ticks + signal_delay)
begin
start_analyzer_0 <= 0;
stop_analyzer_0 <= 1;
start_analyzer_1 <= 1;
stop_analyzer_1 <= 0;
end
else if(clock_counter >= frequency_ticks + signal_delay && clock_counter < frequency_ticks + frequency_ticks)
begin
start_analyzer_0 <= 0;
stop_analyzer_0 <= 0;
start_analyzer_1 <= 0;
stop_analyzer_1 <= 0;
end
else if(clock_counter >= frequency_ticks + frequency_ticks)
begin
start_analyzer_0 <= 1;
stop_analyzer_0 <= 0;
start_analyzer_1 <= 0;
stop_analyzer_1 <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double eps = 1e-8; char ans[1024]; int K, X, N, M; char st[64], ed[64]; long long num[64]; void printAns(char from, char to, int all, int len) { int pos = 1; if (from == A ) pos = 0; for (int i = 0; i < len; i++) ans[i] = B ; for (int i = 0; i < all; i++) ans[pos + 2 * i] = A , ans[pos + 2 * i + 1] = C ; ans[0] = from; ans[len - 1] = to; ans[len] = 0 ; printf( %s n , ans); } int main() { scanf( %d%d%d%d , &K, &X, &N, &M); for (char s1 = A ; s1 <= C ; s1++) { for (char e1 = A ; e1 <= C ; e1++) { if (N == 1 && s1 != e1) continue; for (char s2 = A ; s2 <= C ; s2++) { for (char e2 = A ; e2 <= C ; e2++) { if (M == 1 && s2 != e2) continue; long long tn = N - (s1 != A ) - (e1 != C ); long long tm = M - (s2 != A ) - (e2 != C ); long long inN = tn / 2; long long inM = tm / 2; st[1] = s1, ed[1] = e1; st[2] = s2, ed[2] = e2; for (long long i = 0; i <= inN; i++) { for (long long k = 0; k <= inM; k++) { if (N == 2 && s1 == A && e1 == C && i == 0) continue; if (M == 2 && s2 == A && e2 == C && k == 0) continue; num[1] = i; num[2] = k; for (int g = 3; g <= K; g++) { st[g] = st[g - 2], ed[g] = ed[g - 1]; num[g] = num[g - 1] + num[g - 2] + (ed[g - 2] == A && st[g - 1] == C ); } if (num[K] == X) { printAns(s1, e1, i, N); printAns(s2, e2, k, M); return 0; } } } } } } } printf( Happy new year! n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n, m; int a[maxn]; int b[maxn]; int ans[maxn]; int main() { cin >> n >> m; int num = 0; for (int i = 0; i < m; i++) { scanf( %d , a + i); if (b[a[i]] == 0) num++; b[a[i]]++; if (num == n) { ans[i] = 1; num = 0; for (int j = 1; j <= n; j++) { b[j]--; if (b[j] > 0) num++; } } else { ans[i] = 0; } } for (int i = 0; i < m; i++) { printf( %d , ans[i]); } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int w, m; long long x = 1; bool f = 1; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> w >> m; while (m && f) { if ((m - 1) % w == 0 || m % w == 0 || (m + 1) % w == 0) { if ((m - 1) % w == 0 || m % w == 0) m /= w; else m = (m + 1) / w; } else f = 0; } if (f) cout << YES ; else cout << NO ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A21O_FUNCTIONAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long int A[n]; for (int i = 0; i < n; i++) { cin >> A[i]; } sort(A, A + n); long long ans = 0; for (int i = 0; i < n / 2; i++) { ans += (A[i] + A[n - i - 1]) * (A[i] + A[n - 1 - i]); } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_PP_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlygate4sd2 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int mod = int(1e6 + 3); vector<vector<int> > v; char second[600000]; int n, m; int main() { scanf( %d%d n , &n, &m); v.resize(n); for (int i = 0; i < n; ++i) { gets(second); v[i].resize(m); for (int j = 0; j < m; ++j) { v[i][j] = (second[j] == . ) ? -1 : second[j] - 0 ; } } int res = 1; for (int i = 0; i < n; ++i) { int dir = -1; for (int j = 0; j < m; ++j) if (v[i][j] != -1) { dir = (v[i][j] > 2) ? 1 : 0; if (j & 1) dir = 1 - dir; break; } if (dir != -1) { for (int j = 0; j < m; ++j) if (v[i][j] != -1) { int d2 = (v[i][j] > 2) ? 1 : 0; if (j & 1) d2 = 1 - d2; if (dir != d2) res = 0; } } else if (dir == -1) res = (res * 2) % mod; } for (int j = 0; j < m; ++j) { int dir = -1; for (int i = 0; i < n; ++i) if (v[i][j] != -1) { dir = (v[i][j] > 1 && v[i][j] < 4) ? 1 : 0; if (i & 1) dir = 1 - dir; break; } if (dir != -1) { for (int i = 0; i < n; ++i) if (v[i][j] != -1) { int d2 = (v[i][j] > 1 && v[i][j] < 4) ? 1 : 0; if (i & 1) d2 = 1 - d2; if (dir != d2) res = 0; } } else if (dir == -1) res = (res * 2) % mod; } printf( %d n , res); return 0; }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant synthesizable I2C Slave model ////
//// ////
//// ////
//// Authors: Richard Herveille () www.asics.ws ////
//// John Sheahan () ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001,2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_slave_model.v,v 1.7 2006-09-04 09:08:51 rherveille Exp $
//
// $Date: 2006-09-04 09:08:51 $
// $Revision: 1.7 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.6 2005/02/28 11:33:48 rherveille
// Fixed Tsu:sta timing check.
// Added Thd:sta timing check.
//
// Revision 1.5 2003/12/05 11:05:19 rherveille
// Fixed slave address MSB='1' bug
//
// Revision 1.4 2003/09/11 08:25:37 rherveille
// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
//
// Revision 1.3 2002/10/30 18:11:06 rherveille
// Added timing tests to i2c_model.
// Updated testbench.
//
// Revision 1.2 2002/03/17 10:26:38 rherveille
// Fixed some race conditions in the i2c-slave model.
// Added debug information.
// Added headers.
//
`include "timescale.v"
module i2c_slave_model (scl, sda);
//
// parameters
//
parameter I2C_ADR = 7'b001_0000;
//
// input && outpus
//
input scl;
inout sda;
//
// Variable declaration
//
wire debug = 1'b1;
reg [7:0] mem [3:0]; // initiate memory
reg [7:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data output
reg sta, d_sta;
reg sto, d_sto;
reg [7:0] sr; // 8bit shift register
reg rw; // read/write direction
wire my_adr; // my address called ??
wire i2c_reset; // i2c-statemachine reset
reg [2:0] bit_cnt; // 3bit downcounter
wire acc_done; // 8bits transfered
reg ld; // load downcounter
reg sda_o; // sda-drive level
wire sda_dly; // delayed version of sda
// statemachine declaration
parameter idle = 3'b000;
parameter slave_ack = 3'b001;
parameter get_mem_adr = 3'b010;
parameter gma_ack = 3'b011;
parameter data = 3'b100;
parameter data_ack = 3'b101;
reg [2:0] state; // synopsys enum_state
//
// module body
//
initial
begin
sda_o = 1'b1;
state = idle;
end
// generate shift register
always @(posedge scl)
sr <= #1 {sr[6:0],sda};
//detect my_address
assign my_adr = (sr[7:1] == I2C_ADR);
// FIXME: This should not be a generic assign, but rather
// qualified on address transfer phase and probably reset by stop
//generate bit-counter
always @(posedge scl)
if(ld)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
//generate access done signal
assign acc_done = !(|bit_cnt);
// generate delayed version of sda
// this model assumes a hold time for sda after the falling edge of scl.
// According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
// with regards to scl. If the data changes coincident with the clock, the
// acknowledge is missed
// Fix by Michael Sosnoski
assign #1 sda_dly = sda;
//detect start condition
always @(negedge sda)
if(scl)
begin
sta <= #1 1'b1;
d_sta <= #1 1'b0;
sto <= #1 1'b0;
if(debug)
$display("DEBUG i2c_slave; start condition detected at %t", $time);
end
else
sta <= #1 1'b0;
always @(posedge scl)
d_sta <= #1 sta;
// detect stop condition
always @(posedge sda)
if(scl)
begin
sta <= #1 1'b0;
sto <= #1 1'b1;
if(debug)
$display("DEBUG i2c_slave; stop condition detected at %t", $time);
end
else
sto <= #1 1'b0;
//generate i2c_reset signal
assign i2c_reset = sta || sto;
// generate statemachine
always @(negedge scl or posedge sto)
if (sto || (sta && !d_sta) )
begin
state <= #1 idle; // reset statemachine
sda_o <= #1 1'b1;
ld <= #1 1'b1;
end
else
begin
// initial settings
sda_o <= #1 1'b1;
ld <= #1 1'b0;
case(state) // synopsys full_case parallel_case
idle: // idle state
if (acc_done && my_adr)
begin
state <= #1 slave_ack;
rw <= #1 sr[0];
sda_o <= #1 1'b0; // generate i2c_ack
#2;
if(debug && rw)
$display("DEBUG i2c_slave; command byte received (read) at %t", $time);
if(debug && !rw)
$display("DEBUG i2c_slave; command byte received (write) at %t", $time);
if(rw)
begin
mem_do <= #1 mem[mem_adr];
if(debug)
begin
#2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr);
#2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]);
end
end
end
slave_ack:
begin
if(rw)
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
state <= #1 get_mem_adr;
ld <= #1 1'b1;
end
get_mem_adr: // wait for memory address
if(acc_done)
begin
state <= #1 gma_ack;
mem_adr <= #1 sr; // store memory address
sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address
if(debug)
#1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
end
gma_ack:
begin
state <= #1 data;
ld <= #1 1'b1;
end
data: // receive or drive data
begin
if(rw)
sda_o <= #1 mem_do[7];
if(acc_done)
begin
state <= #1 data_ack;
mem_adr <= #2 mem_adr + 8'h1;
sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read
if(rw)
begin
#3 mem_do <= mem[mem_adr];
if(debug)
#5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr);
end
if(!rw)
begin
mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory
if(debug)
#2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
end
end
end
data_ack:
begin
ld <= #1 1'b1;
if(rw)
if(sr[0]) // read operation && master send NACK
begin
state <= #1 idle;
sda_o <= #1 1'b1;
end
else
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
begin
state <= #1 data;
sda_o <= #1 1'b1;
end
end
endcase
end
// read data from memory
always @(posedge scl)
if(!acc_done && rw)
mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation
// generate tri-states
assign sda = sda_o ? 1'bz : 1'b0;
//
// Timing checks
//
wire tst_sto = sto;
wire tst_sta = sta;
specify
specparam normal_scl_low = 4700,
normal_scl_high = 4000,
normal_tsu_sta = 4700,
normal_thd_sta = 4000,
normal_tsu_sto = 4000,
normal_tbuf = 4700,
fast_scl_low = 1300,
fast_scl_high = 600,
fast_tsu_sta = 1300,
fast_thd_sta = 600,
fast_tsu_sto = 600,
fast_tbuf = 1300;
$width(negedge scl, normal_scl_low); // scl low time
$width(posedge scl, normal_scl_high); // scl high time
$setup(posedge scl, negedge sda &&& scl, normal_tsu_sta); // setup start
$setup(negedge sda &&& scl, negedge scl, normal_thd_sta); // hold start
$setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // setup stop
$setup(posedge tst_sta, posedge tst_sto, normal_tbuf); // stop to start time
endspecify
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX = 11; int n, l; int main() { scanf( %d , &n); while (n) { int a = n % 10; int b = n % 100; int c = n % 1000; if (a == 1) n /= 10; else if (b == 14) n /= 10; else if (c == 144) n /= 100; l++; if (l > 1000) { printf( NO n ); return 0; } } printf( YES n ); return 0; }
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.92
// \ \ Application: MIG
// / / Filename: phy_ck_iob.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:02 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock forwarding to memory
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_ck_iob.v,v 1.1 2011/06/02 07:18:02 mishra Exp $
**$Date: 2011/06/02 07:18:02 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_ck_iob.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_ck_iob #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter WRLVL = "OFF", // Enable write leveling
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter REFCLK_FREQ = 300.0, // IODELAY Reference Clock freq (MHz)
parameter IODELAY_GRP = "IODELAY_MIG" // May be assigned unique name
// when mult IP cores in design
)
(
input clk_mem, // full rate core clock
input clk, // half rate core clock
input rst, // half rate core clk reset
output ddr_ck_p, // forwarded diff. clock to memory
output ddr_ck_n // forwarded diff. clock to memory
);
wire ck_p_odelay;
wire ck_p_oq;
wire ck_p_out;
//*****************************************************************
// Note on generation of Control/Address signals - there are
// several possible configurations that affect the configuration
// of the OSERDES and possible ODELAY for each output (this will
// also affect the CK/CK# outputs as well
// 1. DDR3, write-leveling: This is the simplest case. Use
// OSERDES without the ODELAY. Initially clock/control/address
// will be offset coming out of FPGA from DQ/DQS, but DQ/DQS
// will be adjusted so that DQS-CK alignment is established
// 2. DDR2 or DDR3 (no write-leveling): Both DQS and DQ will use
// ODELAY to delay output of OSERDES. To match this,
// CK/control/address must also delay their outputs using ODELAY
// (with delay = 0)
//*****************************************************************
OBUFDS u_obuf_ck
(
.O (ddr_ck_p),
.OB (ddr_ck_n),
.I (ck_p_out)
);
OSERDESE1 #
(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("BUF"),
.DATA_WIDTH (4),
.DDR3_DATA (0),
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.INTERFACE_TYPE ("DEFAULT"),
.ODELAY_USED (0),
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (1)
)
u_oserdes_ck_p
(
.OCBEXTEND (),
.OFB (),
.OQ (ck_p_oq),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TQ (),
.CLK (clk_mem),
.CLKDIV (clk),
.CLKPERF (),
.CLKPERFDELAY (),
.D1 (1'b0),
.D2 (1'b1),
.D3 (1'b0),
.D4 (1'b1),
.D5 (),
.D6 (),
.ODV (1'b0),
.OCE (1'b1),
.RST (rst),
// Connect SHIFTIN1, SHIFTIN2 to 0 for simulation purposes
// (for all other OSERDES used in design, these are no-connects):
// ensures that CK/CK# outputs are not X at start of simulation
// Certain DDR2 memory models may require that CK/CK# be valid
// throughout simulation
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TFB (),
.TCE (1'b1),
.WC (1'b0)
);
generate
if ((DRAM_TYPE == "DDR3") && (WRLVL == "ON")) begin: gen_ck_wrlvl
//*******************************************************
// CASE1: DDR3, write-leveling
//*******************************************************
assign ck_p_out = ck_p_oq;
end else begin: gen_ck_nowrlvl
//*******************************************************
// CASE2: No write leveling (DDR2 or DDR3)
//*******************************************************
assign ck_p_out = ck_p_odelay;
(* IODELAY_GROUP = IODELAY_GRP *) IODELAYE1 #
(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("O"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (REFCLK_FREQ),
.SIGNAL_PATTERN ("CLOCK")
)
u_iodelay_ck_p
(
.DATAOUT (ck_p_odelay),
.C (1'b0),
.CE (1'b0),
.DATAIN (),
.IDATAIN (),
.INC (1'b0),
.ODATAIN (ck_p_oq),
.RST (1'b0),
.T (),
.CNTVALUEIN (),
.CNTVALUEOUT (),
.CLKIN (),
.CINVCTRL (1'b0)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { unsigned long long n, sum = 0; cin >> n; if (n % 2 == 0) { if ((n / 2) % 2 == 0) cout << 0 << endl; else cout << 1 << endl; } else { if ((n / 2) % 2 == 0) cout << 1 << endl; else cout << 0 << endl; } return 0; }
|
//======================================================================
//
// tb_csprng_fifo.v
// ----------------
// Testbench for the csprng fifo module in the trng.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_csprng_fifo();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg [511 : 0] tb_sprng_data;
reg tb_sprng_data_valid;
reg tb_discard;
wire tb_more_data;
wire tb_rnd_syn;
wire [31 : 0] tb_rnd_data;
reg tb_rnd_ack;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
trng_csprng_fifo dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.csprng_data(tb_csprng_data),
.csprng_data_valid(tb_csprng_data_valid),
.discard(tb_discard),
.more_data(tb_more_data),
.rnd_syn(tb_rnd_syn),
.rnd_data(tb_rnd_data),
.rnd_ack(tb_rnd_ack)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state();
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
$display("------------");
$display("Inputs:");
$display("test_mode = 0x%01x, seed = 0x%01x, enable = 0x%01x",
dut.test_mode, dut.seed_reg, dut.enable_reg);
$display("num_rounds = 0x%02x, num_blocks = 0x%016x",
dut.num_rounds_reg, dut.num_blocks);
$display("seed_syn = 0x%01x, seed_ack = 0x%01x, seed_data = 0x%064x",
dut.seed_syn, dut.seed_ack, dut.seed_data);
$display("");
$display("Internal states:");
$display("cipher_key = 0x%032x", dut.cipher_key_reg);
$display("cipher_iv = 0x%08x, cipher_ctr = 0x%08x",
dut.cipher_iv_reg, dut.cipher_ctr_reg);
$display("cipher_block = 0x%064x", dut.cipher_block_reg);
$display("csprng_ctrl = 0x%02x", dut.csprng_ctrl_reg);
$display("");
$display("Cipher states:");
$display("cipher init: 0x%01x, cipher next: 0x%01x",
dut.cipher.init, dut.cipher.next);
$display("cipher ctrl: 0x%01x, qr ctr: 0x%01x, dr ctr: 0x%02x",
dut.cipher.chacha_ctrl_reg, dut.cipher.qr_ctr_reg, dut.cipher.dr_ctr_reg);
$display("cipher ready: 0x%01x, cipher data out valid: 0x%01x",
dut.cipher.ready, dut.cipher.data_out_valid);
$display("cipher data out: 0x%064x", dut.cipher.data_out);
$display("");
$display("Cipher states:");
$display("mux ctr: 0x%02x, fifo ctr: 0x%02x, fifo_wr_ptr = 0x%02x, fifo_rd_ptr = 0x%02x",
dut.fifo.mux_data_ptr_reg, dut.fifo.fifo_ctr_reg, dut.fifo.wr_ptr_reg, dut.fifo.rd_ptr_reg,);
$display("fifo wr ctrl: 0x%02x, fifo rd ctrl: 0x%02x", dut.fifo.wr_ctrl_reg, dut.fifo.rd_ctrl_reg);
$display("");
$display("Outputs:");
$display("rnd_syn = 0x%01x, rnd_ack = 0x%01x, rnd_data = 0x%08x",
dut.rnd_syn, dut.rnd_ack, dut.rnd_data);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(2 * CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [11 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results();
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_cs = 0;
tb_we = 0;
tb_address = 8'h00;
tb_write_data = 32'h00000000;
tb_discard = 0;
tb_test_mode = 0;
tb_seed_syn = 0;
tb_seed_data = {16{32'h00000000}};
tb_rnd_ack = 0;
tb_debug_update = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// tc1_test_init_cipher()
//
// TC1: Test that the DUT automatically starts initialize when
// enable is set.
//----------------------------------------------------------------
task tc1_test_init_cipher();
begin
$display("*** TC1: Test automatic init of cipher started.");
// tb_num_blocks = 64'h0000000000000004;
tb_seed_data = {8{64'haaaaaaaa55555555}};
// tb_num_rounds = 5'h08;
tb_rnd_ack = 1;
#(200 * CLK_PERIOD);
$display("*** TC1: Test automatic init of cipher done.");
end
endtask // tc1_test_init_cipher
//----------------------------------------------------------------
// csprng_test
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : csprng_fifo_test
$display(" -= Testbench for csprng_fifo started =-");
$display(" ======================================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
// Test code goes here.
tc1_test_init_cipher();
display_test_results();
$display("");
$display("*** The csprng fifo simulation is done. ***");
$finish;
end // csprng_fifo_test
endmodule // tb_csprng_fifo
//======================================================================
// EOF tb_csprng_fifo
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S2S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLYMETAL6S2S_FUNCTIONAL_PP_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S2S_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> const int inf = 1039074182; using namespace std; int n; long long a[100005]; void fi() { cout << sjfnb n ; exit(0); } void se() { cout << cslnb n ; exit(0); } int main() { cin >> n; for (int i = 0; i < n; i++) { scanf( %I64d , a + i); } if (n == 1) { if (a[0] & 1) { fi(); } else { se(); } } sort(a, a + n); int equals = 0; for (int i = 0; i < n - 1; i++) { equals += (a[i] == a[i + 1]); } if (equals >= 2) se(); for (int i = 0; i < n - 1; i++) { if (a[i] == a[i + 1] && (a[i] == 0 || (i && a[i] - 1 == a[i - 1]))) se(); } long long sum = 0; for (int i = 0; i < n; i++) { sum += a[i]; } if ((sum - 1LL * n * (n - 1) / 2) & 1) fi(); else se(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int f(int a, int b) { int ans = 1; for (int i = 0; i < b; i++) ans *= a; return ans; } int main() { int a, b, sgn, n, ans = 1999; scanf( %d %d %d , &a, &b, &n); sgn = (a < 0) ^ (b < 0); a = abs(a); b = abs(b); if (sgn == 1 && n % 2 == 0 && b != 0) printf( No solution n ); else if (a == 0 && b == 0) printf( 0 n ); else if (a == 0) printf( No solution n ); else if (b % a != 0) printf( No solution n ); else { b /= a; for (int i = 0;; i++) { int k = f(i, n); if (k == b) { ans = i * (sgn == 1 ? -1 : 1); break; } if (k > b) { printf( No solution n ); break; } } if (ans != 1999) printf( %d n , ans); } return 0; }
|
`begin_keywords "1364-2005"
module top;
reg svar;
reg sarr [1:0];
reg sout, stmp;
wire wsarr [1:0];
wire wsbslv, wspslv, wsuplv, wsdolv;
wire wsbstr, wspstr, wsuptr, wsdotr;
wire wsbs = svar[0];
wire wsps = svar[0:0];
wire wsup = svar[0+:1];
wire wsdo = svar[0-:1];
wire wsabs = sarr[0][0];
wire wsaps = sarr[0][0:0];
wire wsaup = sarr[0][0+:1];
wire wsado = sarr[0][0-:1];
assign wsbslv[0] = svar;
assign wspslv[0:0] = svar;
assign wsuplv[0+:1] = svar;
assign wsdolv[0-:1] = svar;
assign wsarr[0][0] = svar;
assign wsarr[0][0:0] = svar;
assign wsarr[0][0+:1] = svar;
assign wsarr[0][0-:1] = svar;
tran(wsbstr[0], wsarr[1]);
tran(wspstr[0:0], wsarr[1]);
tran(wsuptr[0+:1], wsarr[1]);
tran(wsdotr[0-:1], wsarr[1]);
submod1 s1 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]);
submod2 s2 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]);
submod3 s3 (wsbstr[0], wspstr[0:0], wsuptr[0+:1], wsdotr[0-:1]);
task stask;
input a;
reg local;
begin
local = a[0];
local = a[0:0];
local = a[0+:1];
local = a[0-:1];
end
endtask
initial begin
stmp = svar[0];
stmp = svar[0:0];
stmp = svar[0+:1];
stmp = svar[0-:1];
stmp = sarr[0][0];
stmp = sarr[0][0:0];
stmp = sarr[0][0+:1];
stmp = sarr[0][0-:1];
sout[0] = 1'b0;
sout[0:0] = 1'b0;
sout[0+:1] = 1'b0;
sout[0-:1] = 1'b0;
sarr[0][0] = 1'b0;
sarr[0][0:0] = 1'b0;
sarr[0][0+:1] = 1'b0;
sarr[0][0-:1] = 1'b0;
end
endmodule
module submod1(arg1, arg2, arg3, arg4);
input arg1, arg2, arg3, arg4;
wire arg1, arg2, arg3, arg4;
initial $display("In submod1 with %b, %b, %b, %b", arg1, arg2, arg3, arg4);
endmodule
module submod2(arg1, arg2, arg3, arg4);
output arg1, arg2, arg3, arg4;
wire arg1, arg2, arg3, arg4;
initial $display("In submod2 with %b, %b, %b, %b", arg1, arg2, arg3, arg4);
endmodule
module submod3(arg1, arg2, arg3, arg4);
inout arg1, arg2, arg3, arg4;
wire arg1, arg2, arg3, arg4;
initial $display("In submod3 with %b, %b, %b, %b", arg1, arg2, arg3, arg4);
endmodule
`end_keywords
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_1_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_1_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog wrapper for lsbuflv2hv_isosrchvaon with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1 (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
LVPWR ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input LVPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1 (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_1_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 2e5 + 10; int n, k; long long fac[maxn + 10], afac[maxn + 10]; long long qpow(long long a, long long b) { long long ret = 1LL; while (b) { if (b & 1) ret = ret * a % mod; a = a * a % mod; b >>= 1; } return ret; } long long inv(long long x) { return qpow(x, mod - 2); } void Pre() { fac[0] = 1LL; for (int i = 1; i <= maxn; i++) fac[i] = fac[i - 1] * (long long)i % mod; afac[maxn] = inv(fac[maxn]); for (int i = maxn; i >= 1; --i) afac[i - 1] = afac[i] * i % mod; } long long C(long long n, long long m) { if (m > n) return 0; return fac[n] * afac[n - m] % mod * afac[m] % mod; } void solve() { vector<pair<int, int> > h; int l, r; for (int i = 1; i <= n; i++) { scanf( %d %d , &l, &r); h.push_back(make_pair(l - 1, 1)); h.push_back(make_pair(r, -1)); } sort(h.begin(), h.end()); long long cnt = 0LL, ans = 0LL; int pos = h[0].first; for (int i = 0; i < h.size(); i++) { long long tmp = C(cnt, k) * (h[i].first - pos) % mod; ans = (ans + tmp) % mod; cnt += 1LL * h[i].second; pos = h[i].first; } printf( %I64d n , ans); } int main() { Pre(); while (scanf( %d %d , &n, &k) != EOF) { solve(); } return 0; }
|
/*******************************************************************************
*
* NetFPGA-10G http://www.netfpga.org
*
* File:
* tx_queue.v
*
* Library:
* hw/osnt/pcores/osnt_10g_interface_v1_11_a
*
* Module:
* tx_queue
*
* Author:
* James Hongyi Zeng
*
* Description:
* AXI-MAC converter: TX side
*
* Copyright notice:
* Copyright (C) 2010, 2011 The Board of Trustees of The Leland Stanford
* Junior University
*
* Licence:
* This file is part of the NetFPGA 10G development base package.
*
* This file is free code: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 2.1 as
* published by the Free Software Foundation.
*
* This package is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with the NetFPGA source package. If not, see
* http://www.gnu.org/licenses/.
*
*/
module tx_queue
#(
parameter AXI_DATA_WIDTH = 64 //Only 64 is supported right now.
)
(
// AXI side
input [AXI_DATA_WIDTH-1:0] tdata,
input [AXI_DATA_WIDTH/8-1:0] tstrb,
input tvalid,
input tlast,
output tready,
input clk,
input reset,
// MAC side
output [63:0] tx_data,
output reg [ 7:0] tx_data_valid,
output reg tx_start,
input tx_ack,
input clk156,
// Timestamp
input [63:0] stamp_counter
);
localparam IDLE = 0;
localparam WAIT_FOR_ACK = 1;
localparam SEND_PKT = 2;
localparam IFG = 3;
wire [3:0] tx_data_valid_encoded;
reg [7:0] tx_data_valid_decoded;
reg [3:0] tstrb_encoded;
wire eop_axi;
wire eop_mac;
wire fifo_almost_full;
wire fifo_empty, info_fifo_empty;
reg fifo_rd_en, info_fifo_rd_en;
reg info_fifo_wr_en;
reg [2:0] state, state_next;
reg eop_axi_delay, tlast_delay;
reg [4:0] word; // add for mario
reg [AXI_DATA_WIDTH-1:0] tdata_aux;
reg [AXI_DATA_WIDTH/8-1:0] tstrb_aux;
reg tvalid_aux;
reg tlast_aux;
reg [63:0] timestamp;
assign tready = ~fifo_almost_full;
assign eop_axi = tlast_aux;
// Instantiate clock domain crossing FIFO
FIFO36_72 #(
.SIM_MODE("FAST"),
.ALMOST_FULL_OFFSET(9'hA),
.ALMOST_EMPTY_OFFSET(9'hA),
.DO_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.EN_SYN("FALSE"),
.FIRST_WORD_FALL_THROUGH("TRUE")
) tx_fifo (
.ALMOSTEMPTY(),
.ALMOSTFULL(fifo_almost_full),
.DBITERR(),
.DO(tx_data),
.DOP({eop_mac, tx_data_valid_encoded}),
.ECCPARITY(),
.EMPTY(fifo_empty),
.FULL(),
.RDCOUNT(),
.RDERR(),
.SBITERR(),
.WRCOUNT(),
.WRERR(),
.DI(tdata_aux), // add for mario
/*.DI(tdata),*/
.DIP({eop_axi , tstrb_encoded}),
.RDCLK(clk156),
.RDEN(fifo_rd_en),
.RST(reset),
.WRCLK(clk),
.WREN(tvalid_aux & tready)
);
small_async_fifo
#(
.DSIZE (1),
.ASIZE (9),
.ALMOST_FULL_SIZE(500)
) tx_info_fifo
(
.wdata(1'b0),
.winc(info_fifo_wr_en), //Only 1 cycle per packet!
.wclk(clk),
.rdata(),
.rinc(info_fifo_rd_en),
.rclk(clk156),
.rempty(info_fifo_empty),
.r_almost_empty(),
.wfull(),
.w_almost_full(),
.rrst_n(~reset),
.wrst_n(~reset)
);
/* Add for Mario for include timestamp here*/
always @(posedge clk) begin
if (tvalid==1'b1) begin
if (word==5 && tdata[63:16]==48'hFFFFFFFFFFFF) begin
tdata_aux[63:56]<=timestamp[23:16]; //TS tx 6
tdata_aux[55:48]<=timestamp[31:24]; //TS tx 5
tdata_aux[47:40]<=timestamp[39:32]; //TS tx 4
tdata_aux[39:32]<=timestamp[47:40]; //TS tx 3
tdata_aux[31:24]<=timestamp[55:48]; //TS tx 2
tdata_aux[23:16]<=timestamp[63:53]; //TS tx 1*/
tdata_aux[15:0] <= tdata[15:0];
end
else if (word==6 && tdata[15:0]==16'hFFFF) begin
tdata_aux[63:16] <= tdata[63:16];
tdata_aux[15:8]<=timestamp[7:0]; //TS tx 8
tdata_aux[7:0]<=timestamp[15:8]; //TS tx 7
end
else begin
tdata_aux <= tdata;
end
word = word + 1;
end
if (tstrb !=8'hFF) begin
word = 0;
timestamp <=stamp_counter;
end
tstrb_aux <= tstrb;
tvalid_aux <=tvalid;
tlast_aux <=tlast;
end
/* End include for mario*/
// Encoder to map 8bit strobe to 4 bit
always @* begin
case (tx_data_valid_encoded)
4'h0: tx_data_valid_decoded = 8'h1;
4'h1: tx_data_valid_decoded = 8'h3;
4'h2: tx_data_valid_decoded = 8'h7;
4'h3: tx_data_valid_decoded = 8'hF;
4'h4: tx_data_valid_decoded = 8'h1F;
4'h5: tx_data_valid_decoded = 8'h3F;
4'h6: tx_data_valid_decoded = 8'h7F;
4'h7: tx_data_valid_decoded = 8'hFF;
default: tx_data_valid_decoded = 8'h0;
endcase
case (tstrb_aux)
8'h1: tstrb_encoded = 4'h0;
8'h3: tstrb_encoded = 4'h1;
8'h7: tstrb_encoded = 4'h2;
8'hF: tstrb_encoded = 4'h3;
8'h1F: tstrb_encoded = 4'h4;
8'h3F: tstrb_encoded = 4'h5;
8'h7F: tstrb_encoded = 4'h6;
8'hFF: tstrb_encoded = 4'h7;
default: tstrb_encoded = 4'h8;
endcase
end
always @* begin
state_next = state;
fifo_rd_en = 1'b0;
info_fifo_rd_en = 1'b0;
tx_start = 1'b0;
tx_data_valid = tx_data_valid_decoded;
case(state)
IDLE: begin
tx_data_valid = 8'b0;
if(~info_fifo_empty) begin
info_fifo_rd_en = 1'b1;
tx_start = 1'b1;
state_next = WAIT_FOR_ACK;
end
end
WAIT_FOR_ACK: begin
if(tx_ack) begin
fifo_rd_en = 1'b1;
state_next = SEND_PKT;
end
end
SEND_PKT: begin
fifo_rd_en = 1'b1;
if(eop_mac) begin
state_next = IDLE;
end
end
IFG: begin
state_next = IDLE;
tx_data_valid = 8'b0;
end
endcase
end
always @(posedge clk156) begin
if(reset) begin
state <= IDLE;
end
else begin
state <= state_next;
end
end
always @(posedge clk) begin
info_fifo_wr_en <= tlast_aux & tvalid_aux & tready;
end
endmodule
|
#include <bits/stdc++.h> long long quickpow(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % 1000000007; b >>= 1, a = a * a % 1000000007; } return ans; } using namespace std; const long long N = 1e3 + 7; const long long maxn = 2e3 + 9; long long n, m; char s[maxn]; long long cnt[27]; bool check(long long x, long long y) { for (long long i = 0; i <= 25; i++) { y -= cnt[i] / x; } return y <= 0; } void solve() { long long n, k; cin >> n >> k; scanf( %s , s + 1); memset(cnt, 0, sizeof(cnt)); for (long long i = 1; i <= n; i++) { cnt[s[i] - a ]++; } long long ans = 1; for (long long i = 1; i <= k; i++) { if (k % i == 0) { long long l = 1, r = n; while (r >= l) { long long mid = (l + r) >> 1; if (check(mid, i)) { l = mid + 1; } else { r = mid - 1; } } ans = max(ans, r * i); } } cout << ans << endl; } signed main() { long long _; cin >> _; while (_--) solve(); }
|
#include <bits/stdc++.h> using namespace std; string s[3]; int a[200][200]; int n; int main() { char card, team; int tm, player; cin >> s[0] >> s[1]; cin >> n; for (int i = 0; i < n; i++) { cin >> tm >> team >> player >> card; if (card == y ) a[team][player]++; else a[team][player] += 2; if (a[team][player] >= 2) { if (team == a ) cout << s[1]; else cout << s[0]; cout << << player << << tm << endl; a[team][player] -= 9000; } } }
|
#include <bits/stdc++.h> long long n, m, Q; long long T; std::vector<long long> req, l, r; std::vector<long long> fill(std::vector<long long>& req) { std::vector<long long> ans(m + 1); long long tem = T; for (long long i = m; i; i--) { ans[i] = 0; if (i < m) ans[i] = ans[i + 1]; if (~req[i]) ans[i] = req[i]; tem -= ans[i]; } if (tem < 0) return std::vector<long long>(); for (long long i = m, last = m + 1; tem && ~i; i--) { if (~req[i]) { long long mx = (i < m) ? (last - 1 - i) * (req[i] - ans[i + 1]) : 0; if (mx <= tem) { for (long long j = i + 1; j < last; j++) ans[j] = req[i]; tem -= mx; } else { for (long long j = i + 1; j < last; j++) ans[j] += (tem / (last - 1 - i)) + ((tem % (last - 1 - i)) >= (j - i)); tem = 0; } last = i; } } if (tem) return std::vector<long long>(); return ans; } long long q[100001], h, t; bool check(std::vector<long long> a, std::vector<long long> b) { long long n = (long long)a.size() - 1, m = (long long)b.size() - 1; h = t = 0; for (long long i = 2; i <= n; i++) a[i] += a[i - 1]; for (long long i = 2; i <= m; i++) b[i] += b[i - 1]; for (long long i = 1; i <= n; i++) a[i] -= 1ll * i * m; for (long long i = 1; i <= m; i++) b[i] -= 1ll * i * n; for (long long i = 1; i <= m; i++) { while (h < t - 1 && (1ll * (b[q[t]] - b[i]) * (q[t] - q[t - 1]) >= 1ll * (b[q[t - 1]] - b[q[t]]) * (i - q[t]))) --t; q[++t] = i; } for (long long i = 1; i <= n; i++) { while (h < t - 1 && (b[q[t]] + q[t] * i) >= (b[q[t - 1]] + q[t - 1] * i)) --t; if (b[q[t]] + q[t] * i < a[n] - a[i]) return 0; } return 1; } bool judge(long long x, long long y = -1) { std::vector<long long> Req = req; if (~y) { for (long long i = 1; i <= x; i++) Req[i] = y; } std::vector<long long> now = fill(Req); if (now.empty()) return 0; if (now[1] != now[x]) { for (long long i = 1; i <= x; i++) if (~req[i] && req[i] != now[1]) return 0; for (long long i = 1; i <= x; i++) Req[i] = now[1]; now = fill(Req); if (now.empty()) return 0; } std::reverse(now.begin() + 1, now.end()); return check(l, now) & check(now, r); } signed main() { scanf( %lld%lld , &n, &m); l.resize(n + 1), r.resize(n + 1); for (long long i = 1; i <= n; i++) scanf( %lld%lld , &l[i], &r[i]); std::sort(l.begin() + 1, l.end()); std::sort(r.begin() + 1, r.end()); req.resize(m + 1); for (long long i = 1; i <= m; i++) req[i] = -1; req[0] = 0x7f7f7f7f; scanf( %lld , &Q); for (long long i = 1, a, b; i <= Q; i++) { scanf( %lld%lld , &a, &b); req[a] = b; } scanf( %lld , &T); long long l = 1, r = m, mid, ans = -1; while (l <= r) { mid = (l + r) >> 1; if (judge(mid)) ans = mid, l = mid + 1; else r = mid - 1; } if (!~ans) { printf( -1 -1 ); return 0; } for (long long i = 1; i <= ans; i++) if (~req[i]) { printf( %lld %lld n , ans, req[i]); return 0; } l = fill(req)[1], r = n; long long ans1; while (l <= r) { mid = (l + r) >> 1; if (judge(ans, mid)) ans1 = mid, l = mid + 1; else r = mid - 1; } printf( %lld %lld n , ans, ans1); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S4S_TB_V
`define SKY130_FD_SC_LP__DLYMETAL6S4S_TB_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlymetal6s4s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__dlymetal6s4s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S4S_TB_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: HW_SW.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module HW_SW (
address,
clock,
q);
input [7:0] address;
input clock;
output [127:0] q;
wire [127:0] sub_wire0;
wire [127:0] q = sub_wire0[127:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({128{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "HV_SW.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=HVSW",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 128,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "HVSW"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "HV_SW.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "128"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "HV_SW.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=HVSW"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_a 0 0 128 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HW_SW_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_SYMBOL_V
`define SKY130_FD_SC_HDLL__A222OI_SYMBOL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a222oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
input C2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_SYMBOL_V
|
module I2CFSM (
input Reset_n_i,
input Clk_i,
input In0_i,
input In1_i,
input In2_i,
input In3_i,
input In4_i,
input In5_i,
input In6_i,
input In7_i,
output Out0_o,
output Out1_o,
output Out2_o,
output Out3_o,
output Out4_o,
output Out5_o,
output Out6_o,
output Out7_o,
output Out8_o,
output Out9_o,
output Out10_o,
output Out11_o,
output Out12_o,
output Out13_o,
output Out14_o,
input CfgMode_i,
input CfgClk_i,
input CfgShift_i,
input CfgDataIn_i,
output CfgDataOut_o
);
wire [7:0] Input_s;
wire [14:0] Output_s;
wire ScanEnable_s;
wire ScanClk_s;
wire ScanDataIn_s;
wire ScanDataOut_s;
TRFSM #(
.InputWidth(8),
.OutputWidth(15),
.StateWidth(5),
.UseResetRow(0),
.NumRows0(5),
.NumRows1(10),
.NumRows2(10),
.NumRows3(5),
.NumRows4(5),
.NumRows5(0),
.NumRows6(0),
.NumRows7(0),
.NumRows8(0),
.NumRows9(0)
) TRFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Input_i(Input_s),
.Output_o(Output_s),
.CfgMode_i(CfgMode_i),
.CfgClk_i(CfgClk_i),
.CfgShift_i(CfgShift_i),
.CfgDataIn_i(CfgDataIn_i),
.CfgDataOut_o(CfgDataOut_o),
.ScanEnable_i(ScanEnable_s),
.ScanClk_i(ScanClk_s),
.ScanDataIn_i(ScanDataIn_s),
.ScanDataOut_o(ScanDataOut_s)
);
assign Input_s = { In7_i, In6_i, In5_i, In4_i, In3_i, In2_i, In1_i, In0_i };
assign Out0_o = Output_s[0];
assign Out1_o = Output_s[1];
assign Out2_o = Output_s[2];
assign Out3_o = Output_s[3];
assign Out4_o = Output_s[4];
assign Out5_o = Output_s[5];
assign Out6_o = Output_s[6];
assign Out7_o = Output_s[7];
assign Out8_o = Output_s[8];
assign Out9_o = Output_s[9];
assign Out10_o = Output_s[10];
assign Out11_o = Output_s[11];
assign Out12_o = Output_s[12];
assign Out13_o = Output_s[13];
assign Out14_o = Output_s[14];
assign ScanEnable_s = 1'b0;
assign ScanClk_s = 1'b0;
assign ScanDataIn_s = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<int, int> get_pair(int a, int b) { if (a > b) swap(a, b); return {a, b}; } template <class Cap, class Cost> struct mcf_graph { private: int _n; struct _edge { int to, rev; Cap cap; Cost cost; }; vector<pair<int, int>> pos; vector<vector<_edge>> g; vector<Cost> h; vector<Cost> dist; vector<int> pv, pe; vector<bool> vis; void norm(int s, int t) { h.resize(_n, numeric_limits<Cost>::max()); h[s] = 0; int ch = 1; int it = _n; while (ch-- && it--) { for (int i = 0; i < _n; i++) { if (h[i] == numeric_limits<Cost>::max()) continue; for (auto e : g[i]) { if (e.cap == 0) continue; if (h[i] + e.cost < h[e.to]) { h[e.to] = h[i] + e.cost; ch = 1; } } } assert(it >= 0); } for (int i = 0; i < _n; i++) h[i] -= h[t]; } bool dijkstra(int s, int t) { pv.clear(); pe.clear(); vis.clear(); dist.clear(); dist.resize(_n, numeric_limits<Cost>::max()); pv.resize(_n, -1); pe.resize(_n, -1); vis.resize(_n, false); priority_queue<pair<Cost, int>, vector<pair<Cost, int>>, greater<pair<Cost, int>>> pq; pq.push({0, s}); dist[s] = 0; while (!pq.empty()) { int x = pq.top().second; pq.pop(); if (vis[x]) continue; vis[x] = true; if (x == t) break; for (int i = 0; i < int(g[x].size()); ++i) { auto e = g[x][i]; if (vis[e.to] || e.cap == 0) continue; Cost cost = e.cost + h[x] - h[e.to]; if (dist[e.to] <= dist[x] + cost) continue; dist[e.to] = dist[x] + cost; pv[e.to] = x; pe[e.to] = i; pq.push({dist[e.to], e.to}); } } if (vis[t] == false) return false; for (int i = 0; i < _n; ++i) { if (!vis[i]) continue; h[i] -= dist[t] - dist[i]; } return true; } public: mcf_graph() {} mcf_graph(int n) : _n(n), g(n) {} int add_edge(int from, int to, Cap cap, Cost cost) { assert(from >= 0 && from < _n); assert(to >= 0 && to < _n); int m = int(pos.size()); pos.push_back({from, int(g[from].size())}); int from_id = int(g[from].size()); int to_id = int(g[to].size()); if (from == to) to_id++; g[from].push_back(_edge{to, to_id, cap, cost}); g[to].push_back(_edge{from, from_id, 0, -cost}); return m; } struct edge { int from, to; Cap cap, flow; Cost cost; }; edge get_edge(int i) { int m = int(pos.size()); assert(0 <= i && i < m); auto _e = g[pos[i].first][pos[i].second]; auto _re = g[_e.to][_e.rev]; return edge{ pos[i].first, _e.to, _e.cap + _re.cap, _re.cap, _e.cost, }; } vector<edge> edges() { int m = int(pos.size()); vector<edge> result(m); for (int i = 0; i < m; ++i) result[i] = get_edge(i); return result; } pair<Cap, Cost> flow(int s, int t, bool neg = false) { return flow(s, t, numeric_limits<Cap>::max(), neg); } pair<Cap, Cost> flow(int s, int t, Cap flow_limit, bool neg = false) { return slope(s, t, flow_limit, neg).back(); } vector<pair<Cap, Cost>> slope(int s, int t, bool neg = false) { return slope(s, t, numeric_limits<Cap>::max(), neg); } vector<pair<Cap, Cost>> slope(int s, int t, Cap flow_limit, bool neg = false) { assert(s >= 0 && s < _n); assert(t >= 0 && t < _n); assert(s != t); h.clear(); if (!neg) h.resize(_n, 0); else norm(s, t); Cap flow = 0; Cost cost = 0, prev = -1; vector<pair<Cap, Cost>> result; result.push_back({flow, cost}); while (flow < flow_limit) { if (dijkstra(s, t) == false) break; Cap c = flow_limit - flow; for (int i = t; i != s; i = pv[i]) { c = min(c, g[pv[i]][pe[i]].cap); } for (int i = t; i != s; i = pv[i]) { auto &e = g[pv[i]][pe[i]]; e.cap -= c; g[e.to][e.rev].cap += c; } Cost d = -h[s]; flow += c; cost += c * d; if (prev == d) result.pop_back(); result.push_back({flow, cost}); prev = d; } return result; } }; pair<vector<int>, vector<int>> bi_color(vector<pair<int, int>> &edges, map<int, int> &id) { int n = int(id.size()); vector<vector<int>> g(n); for (auto e : edges) { int u = id[e.first]; int v = id[e.second]; g[u].push_back(v); g[v].push_back(u); } vector<int> x, y; vector<int> col(n); for (int i = 0; i < n; i++) { if (col[i] > 0) continue; queue<int> q; col[i] = 1; q.push(i); x.push_back(i); while (!q.empty()) { auto u = q.front(); q.pop(); for (auto v : g[u]) { if (col[v] == 0) { col[v] = 3 - col[u]; q.push(v); if (col[v] == 1) x.push_back(v); else y.push_back(v); } else assert(col[v] == 3 - col[u]); } } } return {x, y}; } void solve() { int n, k; cin >> n >> k; vector<int> arr(1 << n); for (int i = 0; i < (1 << n); i++) cin >> arr[i]; int max_edge = min((2 * n) * k + 12, n * (1 << (n - 1))); map<pair<int, int>, bool> vis; vector<pair<int, int>> edges; using node = pair<int, pair<int, int>>; priority_queue<node> pq; vector<vector<pair<int, int>>> ord(1 << n); for (int i = 0; i < (1 << n); i++) { for (int j = 0; j < n; j++) { ord[i].push_back({arr[i] + arr[i ^ (1 << j)], i ^ (1 << j)}); } sort(ord[i].begin(), ord[i].end()); reverse(ord[i].begin(), ord[i].end()); pq.push({ord[i][0].first, {i, 0}}); } while (!pq.empty()) { auto a = pq.top(); pq.pop(); auto cost = a.first; int u = a.second.first, i = a.second.second; if (vis.find(get_pair(u, ord[u][i].second)) == vis.end()) { vis[get_pair(u, ord[u][i].second)] = true; edges.push_back({u, ord[u][i].second}); } if (int(edges.size()) == max_edge) { break; } if (i + 1 < n) { pq.push({ord[u][i + 1].first, {u, i + 1}}); } } assert(int(edges.size()) == max_edge); map<int, int> id; for (int i = 0, j = 0; i < max_edge; i++) { int a = edges[i].first; int b = edges[i].second; if (id.find(a) == id.end()) id[a] = j++; if (id.find(b) == id.end()) id[b] = j++; } int _n = int(id.size()); mcf_graph<int, long long> g(_n + 3); int _s = _n, _t = _n + 1; long long inf = 1e16; auto info = bi_color(edges, id); for (int i = 0; i < int(info.first.size()); i++) { g.add_edge(_s, info.first[i], 1, 0); } for (int i = 0; i < int(info.second.size()); i++) { g.add_edge(info.second[i], _t, 1, 0); } map<int, int> first; for (auto xx : info.first) first[xx] = true; for (int i = 0; i < max_edge; i++) { int a = id[edges[i].first]; int b = id[edges[i].second]; if (first[b]) swap(a, b); g.add_edge(a, b, 1, -(arr[edges[i].first] + arr[edges[i].second])); } auto tt = g.flow(_s, _t, k, true); cout << -tt.second << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( Ofast ) using namespace std; long long int n, res[200005], cnt = 0, ans[200005]; vector<long long int> g[200005]; vector<long long int> v[200005]; map<long long int, long long int> c; queue<long long int> q; void dfs1(long long int node, long long int color) { c[node] = color; for (auto it : g[node]) { if (!c[it]) { dfs1(it, color % 2 + 1); } } } void dfs2(long long int node, long long int p) { for (auto it : g[node]) { if (it != p) { dfs2(it, node); } } for (auto it : g[node]) { if (c[it] != c[node] && res[it] == 0 && res[node] == 0) { cnt++; res[it] = cnt; res[node] = cnt; q.push(it); q.push(node); } } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> n; for (long long int i = 1; i < n; i++) { long long int x, y; cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } dfs1(1, 1); dfs2(1, 1); while (!q.empty()) { long long int x = q.front(); q.pop(); for (auto it : g[x]) { if (res[it] == 0) { res[it] = res[x]; q.push(it); } } } for (long long int i = 1; i <= n; i++) { v[res[i]].push_back(i); } long long int mn = 0; for (long long int i = 1; i <= cnt; i++) { mn += (v[i].size() - 1) * 2; for (long long int j = 0; j < v[i].size(); j++) { ans[v[i][j]] = v[i][(j + 1) % v[i].size()]; } } cout << mn << n ; for (long long int i = 1; i <= n; i++) { cout << ans[i] << ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_1_V
`define SKY130_FD_SC_LS__SDFRBP_1_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_1_V
`define SKY130_FD_SC_LS__OR4B_1_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_1 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_1 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { long n, e = 0, aw = 0, k = 0; cin >> n; long a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; k = max(a[i], k); e += a[i]; } aw = k * n - e; while (aw <= e) { k++; aw = k * n - e; } cout << k; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_TB_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_TB_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlygate4sd3.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__dlygate4sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:38:39 10/29/2012
// Design Name:
// Module Name: IP_RAM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Êý¾Ý´æ´¢Æ÷Ä£¿é
// ÊäÈëÐźţºdatain,addr,clk,we
// Êä³öÐźţºdataout
// datainΪ½«ÒªÏò´æ´¢Æ÷ÖÐдÈëµÄÊý¾Ý£¬addrΪÊý¾ÝдÈëµØÖ·
// clkΪʱÖÓÐźţ¬weΪдʹÄÜÐźÅ
// ÔÚclkÉÏÉýÑص½À´Ê±Èç¹ûweÐźÅΪ1£¬ÔòdatainµÄÊý¾Ý½«»áдÈë´æ´¢Æ÷ÖÐ
// dataout»á¸ù¾ÝaddrµÄµØÖ·Öµ´Ó´æ´¢Æ÷ÖжÁ³öÊý¾ÝÊä³ö
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IP_RAM(we,addr,datain,clk,dataout
);
input [31:0] datain;
input [31:0] addr;
input clk,we;
output [31:0] dataout;
reg [31:0] ram [0:31];
assign dataout=ram[addr[6:2]];
always @(posedge clk)begin
if(we)ram[addr[6:2]]=datain;
end
integer i;
initial begin
for(i=0;i<32;i=i+1)
ram[i]=0;
ram[5'h00]=126;//32'h00000001;
ram[5'h01]=32'h00000001;
ram[5'h14]=32'h00000001;
ram[5'h15]=32'h00000027;
ram[5'h16]=32'h00000079;
ram[5'h17]=32'h00000115;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[1000000], prime[1000000]; vector<long long> v[3000000]; int main() { ios::sync_with_stdio(false); cin.tie(), cout.tie(); long long e; for (long long i = 3; i * i <= 1000000; i += 2) if (a[i] == 0) for (long long j = i * i; j <= 1000000; j = j + (i * 2)) a[j] = 1; prime[0] = 2; for (long long i = 3, j = 1; i <= 1000000; i += 2) if (a[i] == 0) { prime[j++] = i; e = j; } long long n; cin >> n; long long b, c = 0, d = 1, f = 0, g = 0, h; for (long long i = 0; i < n; i++) { cin >> b; for (long long j = 0;; j++) { c = 0; if (prime[j] > sqrt(b)) { break; } if (b % prime[j] == 0) { while (b % prime[j] == 0) { c++; b /= prime[j]; } } v[prime[j]].push_back(c); g = max(g, prime[j]); } if (b > 1) { g = max(g, b); v[b].push_back(1); } } for (long long i = 0; i < 210000; i++) { long long y = prime[i]; if (v[y].size() == n - 1) { sort(v[y].begin(), v[y].end()); long long x = v[y][0]; d = d * (pow(y, x)); } if (v[y].size() == n) { sort(v[y].begin(), v[y].end()); long long x = v[y][1]; d = d * (pow(y, x)); } } cout << d << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1510; int n, arr[N], m; int main() { scanf( %d , &n); int ans = 0; for (int i = 0; i < n; i++) { scanf( %d , &arr[i]); for (int j = 0; j < i; j++) { if (arr[i] < arr[j]) ans ^= 1; } } scanf( %d , &m); while (m--) { int l, r; scanf( %d%d , &l, &r); int cur = (r - l) * (r - l + 1) / 2; ans ^= (cur & 1); if (!ans) puts( even ); else puts( odd ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 500 + 5; int n, m, mod, h[MaxN], tmp, tot[3]; long long f[MaxN << 1][MaxN]; char ch; void read(int &num) { ch = 0; while (ch < 0 || ch > 9 ) ch = getchar(); num = ch - 0 ; } int main() { scanf( %d%d%d , &n, &m, &mod); for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) { read(tmp); if (tmp) h[j]++; } for (int i = 1; i <= n; i++) tot[h[i]]++; f[tot[1]][tot[0]] = 1; for (int j = tot[0]; j >= 0; j--) for (int i = tot[1] + tot[0]; i >= 0; i--) { if (i >= 2) f[i - 2][j] = (f[i - 2][j] + f[i][j] * (i * (i - 1)) / 2) % mod; if (j >= 1) f[i][j - 1] = (f[i][j - 1] + f[i][j] * i * j) % mod; if (j >= 2) f[i + 2][j - 2] = (f[i + 2][j - 2] + f[i][j] * (j * (j - 1)) / 2) % mod; } cout << f[0][0]; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; char* c = new char[k]; for (int i = 0; i < k; i++) { c[i] = a + i; } for (int i = 0; i < n; i++) { cout << c[i % k]; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221O_TB_V
`define SKY130_FD_SC_HS__A221O_TB_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a221o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 B2 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 B2 = 1'b0;
#380 C1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 C1 = 1'b1;
#500 B2 = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 C1 = 1'bx;
#640 B2 = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__a221o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221O_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; n = n / 2520; cout << n; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:45:25 12/01/2014
// Design Name:
// Module Name: RegistroWithMuxInputBorrar
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RegistroWithMuxInput#(parameter Width = 4)
(CLK,EnableRegisterIn,reset,SELCoeffX,SELCoeffY,Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,Coeff06,Coeff07,Coeff08,Coeff09,
Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,Coeff19,OffsetIn,OutCoeffX,OutCoeffY,OffsetOut);
input signed [Width-1:0] Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,Coeff06,Coeff07,Coeff08,
Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,Coeff19,OffsetIn;
input CLK,EnableRegisterIn,reset;
input [3:0] SELCoeffX,SELCoeffY;
output reg signed [Width-1:0] OutCoeffX = 0;
output reg signed [Width-1:0] OutCoeffY = 0; //OffsetOut
output signed [Width-1:0] OffsetOut;
reg signed [Width-1:0] AuxCoeff00,AuxCoeff01,AuxCoeff02,AuxCoeff03,AuxCoeff04,AuxCoeff05,AuxCoeff06,
AuxCoeff07,AuxCoeff08,AuxCoeff09,AuxCoeff10,AuxCoeff11,AuxCoeff12,AuxCoeff13,AuxCoeff14,AuxCoeff15,AuxCoeff16,
AuxCoeff17,AuxCoeff18,AuxCoeff19,AuxCoeff20;
always @(posedge CLK)
if (reset) begin
AuxCoeff00 <= 0;
AuxCoeff01 <= 0;
AuxCoeff02 <= 0;
AuxCoeff03 <= 0;
AuxCoeff04 <= 0;
AuxCoeff05 <= 0;
AuxCoeff06 <= 0;
AuxCoeff07 <= 0;
AuxCoeff08 <= 0;
AuxCoeff09 <= 0;
AuxCoeff10 <= 0;
AuxCoeff11 <= 0;
AuxCoeff12 <= 0;
AuxCoeff13 <= 0;
AuxCoeff14 <= 0;
AuxCoeff15 <= 0;
AuxCoeff16 <= 0;
AuxCoeff17 <= 0;
AuxCoeff18 <= 0;
AuxCoeff19 <= 0;
AuxCoeff20 <= 0;
end else if (EnableRegisterIn) begin
AuxCoeff00 <= Coeff00;
AuxCoeff01 <= Coeff01;
AuxCoeff02 <= Coeff02;
AuxCoeff03 <= Coeff03;
AuxCoeff04 <= Coeff04;
AuxCoeff05 <= Coeff05;
AuxCoeff06 <= Coeff06;
AuxCoeff07 <= Coeff07;
AuxCoeff08 <= Coeff08;
AuxCoeff09 <= Coeff09;
AuxCoeff10 <= Coeff10;
AuxCoeff11 <= Coeff11;
AuxCoeff12 <= Coeff12;
AuxCoeff13 <= Coeff13;
AuxCoeff14 <= Coeff14;
AuxCoeff15 <= Coeff15;
AuxCoeff16 <= Coeff16;
AuxCoeff17 <= Coeff17;
AuxCoeff18 <= Coeff18;
AuxCoeff19 <= Coeff19;
AuxCoeff20 <= OffsetIn;
end
assign OffsetOut = AuxCoeff20;
always @(SELCoeffX, AuxCoeff00,AuxCoeff01,AuxCoeff02,AuxCoeff03,AuxCoeff04,AuxCoeff05,AuxCoeff06,
AuxCoeff07,AuxCoeff08,AuxCoeff09)
case (SELCoeffX)
5'd00: OutCoeffX <= AuxCoeff00;
5'd01: OutCoeffX <= AuxCoeff01;
5'd02: OutCoeffX <= AuxCoeff02;
5'd03: OutCoeffX <= AuxCoeff03;
5'd04: OutCoeffX <= AuxCoeff04;
5'd05: OutCoeffX <= AuxCoeff05;
5'd06: OutCoeffX <= AuxCoeff06;
5'd07: OutCoeffX <= AuxCoeff07;
5'd08: OutCoeffX <= AuxCoeff08;
5'd09: OutCoeffX <= AuxCoeff09;
default : OutCoeffX <= 0;
endcase
always @(SELCoeffY,AuxCoeff10,AuxCoeff11,AuxCoeff12,AuxCoeff13,AuxCoeff14,AuxCoeff15,AuxCoeff16,
AuxCoeff17,AuxCoeff18,AuxCoeff19)
case (SELCoeffY)
5'd00: OutCoeffY <= AuxCoeff10;
5'd01: OutCoeffY <= AuxCoeff11;
5'd02: OutCoeffY <= AuxCoeff12;
5'd03: OutCoeffY <= AuxCoeff13;
5'd04: OutCoeffY <= AuxCoeff14;
5'd05: OutCoeffY <= AuxCoeff15;
5'd06: OutCoeffY <= AuxCoeff16;
5'd07: OutCoeffY <= AuxCoeff17;
5'd08: OutCoeffY <= AuxCoeff18;
5'd09: OutCoeffY <= AuxCoeff19;
default : OutCoeffY <= 0;
endcase
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera MAX10 devices Input Buffer Primitive */
module fiftyfivenm_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // fiftyfivenm_io_ibuf
/* Altera MAX10 devices Output Buffer Primitive */
module fiftyfivenm_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // fiftyfivenm_io_obuf
/* Altera MAX10 4-input non-fracturable LUT Primitive */
module fiftyfivenm_lcell_comb
(output combout, cout,
input dataa, datab, datac, datad, cin);
/* Internal parameters which define the behaviour
of the LUT primitive.
lut_mask define the lut function, can be expressed in 16-digit bin or hex.
sum_lutc_input define the type of LUT (combinational | arithmetic).
dont_touch for retiming || carry options.
lpm_type for WYSIWYG */
parameter lut_mask = 16'hFFFF;
parameter dont_touch = "off";
parameter lpm_type = "fiftyfivenm_lcell_comb";
parameter sum_lutc_input = "datac";
reg [1:0] lut_type;
reg cout_rt;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
wire cin_w;
assign dataa_w = dataa;
assign datab_w = datab;
assign datac_w = datac;
assign datad_w = datad;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
initial begin
if (sum_lutc_input == "datac") lut_type = 0;
else
if (sum_lutc_input == "cin") lut_type = 1;
else begin
$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
$finish();
end
end
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
if (lut_type == 0) begin // logic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
datac_w, datad_w);
end
else if (lut_type == 1) begin // arithmetic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
cin_w, datad_w);
end
cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
end
assign combout = combout_rt & 1'b1;
assign cout = cout_rt & 1'b1;
endmodule // fiftyfivenm_lcell_comb
/* Altera D Flip-Flop Primitive */
module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
// Timing simulation is not covered
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q_tmp;
wire reset;
reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
always @(posedge clk, posedge aload) begin
if(reset) q_tmp <= 0;
else q_tmp <= d;
end
assign q = q_tmp;
endmodule // dffeas
/* MAX10 altpll clearbox model */
(* blackbox *)
module fiftyfivenm_pll
(inclk,
fbin,
fbout,
clkswitch,
areset,
pfdena,
scanclk,
scandata,
scanclkena,
configupdate,
clk,
phasecounterselect,
phaseupdown,
phasestep,
clkbad,
activeclock,
locked,
scandataout,
scandone,
phasedone,
vcooverrange,
vcounderrange);
parameter operation_mode = "normal";
parameter pll_type = "auto";
parameter compensate_clock = "clock0";
parameter inclk0_input_frequency = 0;
parameter inclk1_input_frequency = 0;
parameter self_reset_on_loss_lock = "off";
parameter switch_over_type = "auto";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
parameter lock_high = 0;
parameter lock_low = 0;
parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter clk0_divide_by = 0;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 0;
parameter clk1_divide_by = 0;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 0;
parameter clk2_divide_by = 0;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 0;
parameter clk3_divide_by = 0;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 0;
parameter clk4_divide_by = 0;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// Advanced user parameters
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "unused";
parameter clk1_counter = "unused";
parameter clk2_counter = "unused";
parameter clk3_counter = "unused";
parameter clk4_counter = "unused";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter m_test_source = -1;
parameter c0_test_source = -1;
parameter c1_test_source = -1;
parameter c2_test_source = -1;
parameter c3_test_source = -1;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0;
parameter lpm_type = "fiftyfivenm_pll";
parameter phase_counter_select_width = 3;
input [1:0] inclk;
input fbin;
input clkswitch;
input areset;
input pfdena;
input [phase_counter_select_width - 1:0] phasecounterselect;
input phaseupdown;
input phasestep;
input scanclk;
input scanclkena;
input scandata;
input configupdate;
output [4:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output scandataout;
output scandone;
output fbout;
output phasedone;
output vcooverrange;
output vcounderrange;
endmodule // cycloneive_pll
|
#include <bits/stdc++.h> using namespace std; int pos, ans, a[20], b[20], cnt[12]; bool check(int pos, bool Ls, bool Rs) { if (pos == 0) return true; if (!Ls && !Rs) return true; int l = Ls ? a[pos] : 0, r = Rs ? b[pos] : 9; for (int i = l; i <= r; i++) if (cnt[i]) { cnt[i]--; if (check(pos - 1, Ls && i == l, Rs && i == r)) { cnt[i]++; return true; } cnt[i]++; } return false; } void dfs(int cur, int total) { if (cur == 9) { cnt[cur] = total; ans += check(pos, 1, 1); return; } for (int i = 0; i <= total; i++) { cnt[cur] = i; dfs(cur + 1, total - i); cnt[cur] = 0; } } int digit(long long x, int d[]) { register int pos = 0; if (x == 0) d[++pos] = 0; while (x) { d[++pos] = x % 10; x /= 10; } return pos; } int main() { long long l, r; cin >> l >> r; digit(l, a); pos = digit(r, b); ans = 0; dfs(0, pos); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int t, n, m; long long a, k, ak; char c; unordered_map<long long, bool> ma; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> t; for (int ti = 1; ti <= t; ++ti) { ma.clear(); cin >> n >> m; k = (1ll << m) - n; for (int i = 1; i <= n; ++i) { a = 0; for (int j = m - 1; j >= 0; --j) { cin >> c; a |= (c == 1 ? (1ll << j) : 0ll); } ma[a] = 1; } a = (k - 1) / 2; ak = k = a + 1; for (pair<long long, bool> tw : ma) { if (tw.first <= a) --ak; } while (ak < k) { if (!ma[++a]) ++ak; } for (int i = m - 1; i >= 0; --i) { cout << (a & (1ll << i) ? 1 : 0); } cout << n ; } return 0; }
|
`include "logfunc.h"
module pfmonitor_wp (
input clk
,input reset
,input logic coretopfm_dec_valid
,output logic coretopfm_dec_retry
,input SC_pcsign_type coretopfm_dec_pcsign
,input SC_robid_type coretopfm_dec_rid
,input SC_decwidth_type coretopfm_dec_decmask
,input logic coretopfm_retire_valid
,output logic coretopfm_retire_retry
,input PF_entry_type coretopfm_retire_pfentry
,input SC_robid_type coretopfm_retire_d0_rid
,input PF_delta_type coretopfm_retire_d0_val
,input SC_robid_type coretopfm_retire_d1_rid
,input PF_delta_type coretopfm_retire_d1_val
`ifdef SCMEM_PFRETIRE_4
,input SC_robid_type coretopfm_retire_d2_rid
,input PF_delta_type coretopfm_retire_d2_val
,input SC_robid_type coretopfm_retire_d3_rid
,input PF_delta_type coretopfm_retire_d3_val
`endif
,output logic pfmtocore_pred_valid
,input logic pfmtocore_pred_retry
,output PF_entry_type pfmtocore_pred_pfentry
,output SC_robid_type pfmtocore_pred_d0_rid
,output PF_delta_type pfmtocore_pred_d0_val
,output PF_weigth_type pfmtocore_pred_d0_w
,output SC_robid_type pfmtocore_pred_d1_rid
,output PF_delta_type pfmtocore_pred_d1_val
,output PF_weigth_type pfmtocore_pred_d1_w
,output SC_robid_type pfmtocore_pred_d2_rid
,output PF_delta_type pfmtocore_pred_d2_val
,output PF_weigth_type pfmtocore_pred_d2_w
,output SC_robid_type pfmtocore_pred_d3_rid
,output PF_delta_type pfmtocore_pred_d3_val
,output PF_weigth_type pfmtocore_pred_d3_w
);
pfmonitor pfm (
.clk (clk)
,.reset (reset)
,.coretopfm_dec_valid (coretopfm_dec_valid)
,.coretopfm_dec_retry (coretopfm_dec_retry)
,.coretopfm_dec ({coretopfm_dec_pcsign
,coretopfm_dec_rid
,coretopfm_dec_decmask})
,.coretopfm_retire_valid (coretopfm_retire_valid)
,.coretopfm_retire_retry (coretopfm_retire_retry)
,.coretopfm_retire ({coretopfm_retire_pfentry
,coretopfm_retire_d0_rid
,coretopfm_retire_d0_val
,coretopfm_retire_d1_rid
,coretopfm_retire_d1_val
,coretopfm_retire_d2_rid
,coretopfm_retire_d2_val
,coretopfm_retire_d3_rid
,coretopfm_retire_d3_val})
,.pfmtocore_pred_valid (pfmtocore_pred_valid)
,.pfmtocore_pred_retry (pfmtocore_pred_retry)
,.pfmtocore_pred ({pfmtocore_pred_pfentry
,pfmtocore_pred_d0_rid
,pfmtocore_pred_d0_val
,pfmtocore_pred_d0_w
,pfmtocore_pred_d1_rid
,pfmtocore_pred_d1_val
,pfmtocore_pred_d1_w
,pfmtocore_pred_d2_rid
,pfmtocore_pred_d2_val
,pfmtocore_pred_d2_w
,pfmtocore_pred_d3_rid
,pfmtocore_pred_d3_val
,pfmtocore_pred_d3_w})
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_1_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_1_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog wrapper for lsbufhv2lv_simple with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__lsbufhv2lv_simple.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple_1 (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbufhv2lv_simple base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbufhv2lv_simple base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_1_V
|
//****************************************************************************************************
//*----------------Copyright (c) 2016 C-L-G.FPGA1988.Roger Wang. All rights reserved------------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : clk_gen_module.v
//Project Name : gt0000
//Description : The system auxiliary module.
//Github Address : https://github.com/C-L-G/gt0000/trunk/ic/digital/rtl/clk_gen_module/clk_gen_module.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 29-08-2016 17:00(1th Fri,July,2016)
//First Author : Roger Wang
//Modify Date : 29-08-2016 14:20(1th Sun,July,2016)
//Last Author : Roger Wang
//Version Number : 001
//Last Commit : 29-08-2016 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//dd.mm.yyyy - Author - Your log of change
//****************************************************************************************************
//02.09.2016 - Roger Wang - Move the div logic from gen top to this module.
//*---------------------------------------------------------------------------------------------------
`timescale 1ns/1ps
module clk_div_module(
src_clk ,//01 In
div_rst_n ,//01 In
div_clk_0 ,//01 Out
div_clk_1 //01 Out
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
//************************************************************************************************
// 2.input and output declaration
//************************************************************************************************
input src_clk ;//the clk = 200MHz
input div_rst_n ;//the reset signal : low active
output div_clk_0 ;//the div 2 clock = 100MHz
output div_clk_1 ;//the div 4 clock = 50MHz
//************************************************************************************************
// 3.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the system led module wire
//------------------------------------------------------------------------------------------------
reg [01:00] clk_div_cnt ;//led count
//************************************************************************************************
// 4.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the system led module assignment
//------------------------------------------------------------------------------------------------
always @(posedge src_clk or negedge div_rst_n) begin : DIV_CNT_ADD
if(!div_rst_n)
begin
`ifndef SYNTHESIS
$display("The initial value of clk div count is 0.");
`endif
clk_div_cnt <= 'd0;
end
else
begin
clk_div_cnt <= clk_div_cnt + 1'b1;
end
end
assign div_clk_0 = clk_div_cnt[0];
assign div_clk_1 = clk_div_cnt[1];
//************************************************************************************************
// 5.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 5.1 the xxx module
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 5.2 the xxx module
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 5.3 the xxx module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Mopdule
//****************************************************************************************************
|
#include <bits/stdc++.h> #define ll long long using namespace std; int main() { ios_base::sync_with_stdio(0) ; cin.tie(0) ; cout.tie(0) ; int t; cin>>t; while(t--) { ll n,x,s=0,a=1; cin>>n>>x; ll arr[n]; for(int i=0; i<n; i++) { cin>>arr[i]; } int mn=100000000,gg=mn,ind=-1; for(int i=0; i<n; i++) { int y=arr[i],cnt=0; while(!(y%x)) { y/=x; cnt++; } if(cnt<mn) { mn=cnt; ind=i; } } for(int i=0; i<n; i++) { if(i<ind) gg=mn+1; else gg=mn; s+=arr[i]; a=1; while(((arr[i]%x)==0)&&(gg--)) { a*=x; arr[i]/=x; s+=a*arr[i]; } } cout<<s<< n ; } }
|
// $Id: c_rr_arbiter_base.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// round-robin arbiter basic block
//==============================================================================
module c_rr_arbiter_base
(mask, req, gnt);
// number of input ports
parameter num_ports = 32;
// priority mask
input [0:num_ports-1] mask;
// vector of requests
input [0:num_ports-1] req;
// vector of grants
output [0:num_ports-1] gnt;
wire [0:num_ports-1] gnt;
wire [0:num_ports-1] req_qual;
assign req_qual = req & mask;
wire [0:num_ports-1] gnt_qual;
c_lod
#(.width(num_ports))
gnt_qual_lod
(.data_in(req_qual),
.data_out(gnt_qual));
wire [0:num_ports-1] req_unqual;
assign req_unqual = req;
wire [0:num_ports-1] gnt_unqual;
c_lod
#(.width(num_ports))
gnt_unqual_lod
(.data_in(req_unqual),
.data_out(gnt_unqual));
assign gnt = (|req_qual) ? gnt_qual : gnt_unqual;
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: template_periph_8b.v
//
// *Module Description:
// 8 bit peripheral template.
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module template_periph_8b (
// OUTPUTs
per_dout, // Peripheral data output
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0090;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 2;
// Register addresses offset
parameter [DEC_WD-1:0] CNTRL1 = 'h0,
CNTRL2 = 'h1,
CNTRL3 = 'h2,
CNTRL4 = 'h3;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1),
CNTRL2_D = (BASE_REG << CNTRL2),
CNTRL3_D = (BASE_REG << CNTRL3),
CNTRL4_D = (BASE_REG << CNTRL4);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr==(CNTRL1 >>1))}}) |
(CNTRL2_D & {DEC_SZ{(reg_addr==(CNTRL2 >>1))}}) |
(CNTRL3_D & {DEC_SZ{(reg_addr==(CNTRL3 >>1))}}) |
(CNTRL4_D & {DEC_SZ{(reg_addr==(CNTRL4 >>1))}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// CNTRL1 Register
//-----------------
reg [7:0] cntrl1;
wire cntrl1_wr = CNTRL1[0] ? reg_hi_wr[CNTRL1] : reg_lo_wr[CNTRL1];
wire [7:0] cntrl1_nxt = CNTRL1[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl1 <= 8'h00;
else if (cntrl1_wr) cntrl1 <= cntrl1_nxt;
// CNTRL2 Register
//-----------------
reg [7:0] cntrl2;
wire cntrl2_wr = CNTRL2[0] ? reg_hi_wr[CNTRL2] : reg_lo_wr[CNTRL2];
wire [7:0] cntrl2_nxt = CNTRL2[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl2 <= 8'h00;
else if (cntrl2_wr) cntrl2 <= cntrl2_nxt;
// CNTRL3 Register
//-----------------
reg [7:0] cntrl3;
wire cntrl3_wr = CNTRL3[0] ? reg_hi_wr[CNTRL3] : reg_lo_wr[CNTRL3];
wire [7:0] cntrl3_nxt = CNTRL3[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl3 <= 8'h00;
else if (cntrl3_wr) cntrl3 <= cntrl3_nxt;
// CNTRL4 Register
//-----------------
reg [7:0] cntrl4;
wire cntrl4_wr = CNTRL4[0] ? reg_hi_wr[CNTRL4] : reg_lo_wr[CNTRL4];
wire [7:0] cntrl4_nxt = CNTRL4[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) cntrl4 <= 8'h00;
else if (cntrl4_wr) cntrl4 <= cntrl4_nxt;
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] cntrl1_rd = {8'h00, (cntrl1 & {8{reg_rd[CNTRL1]}})} << (8 & {4{CNTRL1[0]}});
wire [15:0] cntrl2_rd = {8'h00, (cntrl2 & {8{reg_rd[CNTRL2]}})} << (8 & {4{CNTRL2[0]}});
wire [15:0] cntrl3_rd = {8'h00, (cntrl3 & {8{reg_rd[CNTRL3]}})} << (8 & {4{CNTRL3[0]}});
wire [15:0] cntrl4_rd = {8'h00, (cntrl4 & {8{reg_rd[CNTRL4]}})} << (8 & {4{CNTRL4[0]}});
wire [15:0] per_dout = cntrl1_rd |
cntrl2_rd |
cntrl3_rd |
cntrl4_rd;
endmodule // template_periph_8b
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/08 19:17:16
// Design Name:
// Module Name: timing_signal_generator
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
* top module
* @parameter clr_n
*/
module timing_signal_generator
#(parameter CYCLE = 5, LEN = 4)
(
input clr_n,
input on,
input off,
input [3:0] power,
output [(LEN-1):0] T
);
// power[1]: Hz select
// power[0]: on/off
wire [(LEN-1):0] clk_group, Tp;
clock_generator #(.CYCLE(CYCLE), .LEN(LEN)) CLK (
.clk(clk_group));
timing_signal #(.LEN(LEN)) SIG (
.clk(clk_group[power[3:1]]&power[0]),
.clr_n(clr_n),
.Tp(Tp));
control_unit #(.LEN(LEN)) UNIT (
.on(on),
.off(off),
.clr_n(clr_n),
.Tp(Tp),
.T(T));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int64_t N = 1e5 + 1; int64_t crt_node = 0, maxi = 0; vector<int64_t> previous; vector<vector<int64_t>> adj; void dfs(int64_t node, int64_t pere, int64_t len) { previous[node] = pere; if (len > maxi) { crt_node = node; maxi = len; } for (int64_t i : adj[node]) { if (i != pere) dfs(i, node, len + 1); } } bool ok = true; vector<int64_t> level, path; void hedgehog(int64_t node, int64_t pere) { int64_t k = 0; for (int64_t i : adj[node]) { if (i != pere) { hedgehog(i, node); if (k == 0) k = level[i]; else if (k != level[i]) ok = false; } } if (adj[node].size() == 1) level[node] = 1; else if (adj[node].size() < 3 or (adj[node].size() == 3 and path[path.size() / 2] != node)) ok = false; else level[node] = k + 1; } int32_t main() { ios::sync_with_stdio(false); cin.tie(nullptr); int64_t n, k; cin >> n >> k; if (n == 1) { cout << No ; return 0; } adj.resize(n + 1); for (int64_t i = 1; i < n; ++i) { int64_t u, v; cin >> u >> v; adj[u].emplace_back(v); adj[v].emplace_back(u); } previous.resize(n + 1); dfs(1, 0, 0); int64_t a = crt_node; maxi = 0; fill(previous.begin(), previous.end(), 0ll); dfs(crt_node, 0, 0); int64_t b = crt_node; while (b) { path.emplace_back(b); b = previous[b]; } level.resize(n + 1); hedgehog(path[path.size() / 2], 0); if (level[path[path.size() / 2]] != k + 1) ok = false; cout << (ok ? Yes : No ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, w; int v[100010]; long long mark[100010]; bool test(long long x) { memset(mark, 0, sizeof mark); long long qnt = 0; long long sum = 0; for (int i = 0; i < n; ++i) { if (qnt > m) return false; sum -= mark[i]; long long val = v[i] + sum; if (val < x) { qnt += x - val; mark[min(i + w, n)] += x - val; sum += x - val; } } return qnt <= m; } long long bs(long long lo, long long hi) { while (hi - lo > 1) { long long mid = (hi + lo) / 2; if (test(mid)) { lo = mid; } else hi = mid; } if (test(hi)) return hi; return lo; } int main(void) { cin >> n >> m >> w; for (int i = 0; i < n; ++i) { cin >> v[i]; } cout << bs(0, 1000000000000000LL) << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SRSDFRTN_FUNCTIONAL_PP_V
/**
* srsdfrtn: Scan flop with sleep mode, inverted reset, inverted
* clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nr_pp_pkg_s/sky130_fd_sc_lp__udp_dff_nr_pp_pkg_s.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__srsdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$NR_pp$PKG$s `UNIT_DELAY dff0 (buf_Q , mux_out, CLK_N, RESET, SLEEP_B, KAPWR, VGND, VPWR);
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d , &n); scanf( %d , &m); int f[n], b[m], a[m]; map<int, int> x; for (int i = 0; i < n; i++) { scanf( %d , &f[i]); if (x.find(f[i]) != x.end()) x[f[i]] = -1; else x[f[i]] = i; } for (int i = 0; i < m; i++) scanf( %d , &b[i]); sort(f, f + n); bool y = 0, z = 0; for (int i = 0; i < m; i++) { if (x.find(b[i]) != x.end()) { if (x[b[i]] == -1) { z = 1; } else { a[i] = x[b[i]]; } } else { printf( Impossible ); y = 1; break; } } if (!y) { if (z) { printf( Ambiguity ); } else { printf( Possible n ); for (int i = 0; i < m; i++) { printf( %d , a[i] + 1); printf( ); } } } }
|
#include <bits/stdc++.h> int n, m, k; int main() { long long ans = 1; scanf( %d%d%d , &n, &m, &k); if (k == n) { int mid = k / 2 + (k & 1); for (int i = 0; i < mid; ++i) ans = (ans * m) % 1000000007; printf( %I64d , ans); } else if (!(k % 2) && k < n) printf( %d , m); else if (k == 1 || k > n) { for (int i = 0; i < n; ++i) ans = (ans * m) % 1000000007; printf( %I64d , ans); } else { printf( %d , m * m); } }
|
#include <bits/stdc++.h> using namespace std; long long n, arr[55] = {}, sm = 0, dp[55][2] = {}; long long rec(int ind, bool dt) { if (ind == n - 1) { if (dt) return 0; else return arr[ind]; } if (dp[ind][dt] != -1) return dp[ind][dt]; if (dt) return dp[ind][dt] = min(rec(ind + 1, dt) + arr[ind], rec(ind + 1, !dt)); else return dp[ind][dt] = max(rec(ind + 1, dt), rec(ind + 1, !dt) + arr[ind]); } int main() { cin >> n; for (int i = 0; i < 55; i++) { dp[i][0] = -1; dp[i][1] = -1; } for (int i = 0; i < n; i++) { cin >> arr[i]; sm += arr[i]; } long long ans = rec(0, 0); cout << (sm - ans) << << ans << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSBP_1_V
`define SKY130_FD_SC_HS__SDFSBP_1_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfsbp_1 (
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfsbp_1 (
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
SET_B
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSBP_1_V
|
`define ADDER_WIDTH 017
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module hx8kdemo (
input clk,
output ser_tx,
input ser_rx,
output [7:0] leds,
output flash_csb,
output flash_clk,
inout flash_io0,
inout flash_io1,
inout flash_io2,
inout flash_io3,
output debug_ser_tx,
output debug_ser_rx,
output debug_flash_csb,
output debug_flash_clk,
output debug_flash_io0,
output debug_flash_io1,
output debug_flash_io2,
output debug_flash_io3
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
wire flash_io0_oe, flash_io0_do, flash_io0_di;
wire flash_io1_oe, flash_io1_do, flash_io1_di;
wire flash_io2_oe, flash_io2_do, flash_io2_di;
wire flash_io3_oe, flash_io3_do, flash_io3_di;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) flash_io_buf [3:0] (
.PACKAGE_PIN({flash_io3, flash_io2, flash_io1, flash_io0}),
.OUTPUT_ENABLE({flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}),
.D_OUT_0({flash_io3_do, flash_io2_do, flash_io1_do, flash_io0_do}),
.D_IN_0({flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di})
);
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign leds = gpio;
always @(posedge clk) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= gpio;
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc soc (
.clk (clk ),
.resetn (resetn ),
.ser_tx (ser_tx ),
.ser_rx (ser_rx ),
.flash_csb (flash_csb ),
.flash_clk (flash_clk ),
.flash_io0_oe (flash_io0_oe),
.flash_io1_oe (flash_io1_oe),
.flash_io2_oe (flash_io2_oe),
.flash_io3_oe (flash_io3_oe),
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
.flash_io3_do (flash_io3_do),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
assign debug_ser_tx = ser_tx;
assign debug_ser_rx = ser_rx;
assign debug_flash_csb = flash_csb;
assign debug_flash_clk = flash_clk;
assign debug_flash_io0 = flash_io0_di;
assign debug_flash_io1 = flash_io1_di;
assign debug_flash_io2 = flash_io2_di;
assign debug_flash_io3 = flash_io3_di;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> t1, t2; long long a, b, n, k, q, day, val, p, t; void update1(long long i, long long l, long long r, long long qi, long long qx) { if (l + 1 == r) { t1[i] += qx; t1[i] = min(t1[i], a); return; } long long m = (r + l) >> 1; if (qi < m) { update1(2 * i + 1, l, m, qi, qx); } else { update1(2 * i + 2, m, r, qi, qx); } t1[i] = t1[2 * i + 1] + t1[2 * i + 2]; } void update2(long long i, long long l, long long r, long long qi, long long qx) { if (l + 1 == r) { t2[i] += qx; t2[i] = min(t2[i], b); return; } long long m = (r + l) >> 1; if (qi < m) { update2(2 * i + 1, l, m, qi, qx); } else { update2(2 * i + 2, m, r, qi, qx); } t2[i] = t2[2 * i + 1] + t2[2 * i + 2]; } long long get1(long long i, long long l, long long r, long long ql, long long qr) { if (r <= ql || qr <= l) { return 0; } if (ql <= l && r <= qr) { return t1[i]; } long long m = (r + l) / 2; return get1(2 * i + 1, l, m, ql, qr) + get1(2 * i + 2, m, r, ql, qr); } long long get2(long long i, long long l, long long r, long long ql, long long qr) { if (r <= ql || qr <= l) { return 0; } if (ql <= l && r <= qr) { return t2[i]; } long long m = (r + l) / 2; return get2(2 * i + 1, l, m, ql, qr) + get2(2 * i + 2, m, r, ql, qr); } void Not_Stable() { cin >> n >> k >> a >> b >> q; t1.resize(4 * n); t2.resize(4 * n); long long x, y, z; for (long long i = 0; i < q; i++) { cin >> x >> y; if (x == 1) { cin >> z; update1(0, 0, n, y - 1, z); update2(0, 0, n, y - 1, z); } else { cout << get2(0, 0, n, 0, y - 1) + get1(0, 0, n, y - 1 + k, n) << endl; } } } int32_t main() { ios_base::sync_with_stdio(false), cin.tie(nullptr); ; long long g = 1; while (g--) Not_Stable(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_TB_V
`define SKY130_FD_SC_MS__MAJ3_TB_V
/**
* maj3: 3-input majority vote.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__maj3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__maj3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_TB_V
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; //#define rep(i,a,b) for(int i=a;i<b;i++); void solve(){ ll n; cin>>n; string s; cin>>s; vector<ll>v; for(int i=0;i<n;i++){ if (s[i]== * ){ v.push_back(i); } } if (v.size()<=1 or v.size()==n){ cout<<0<<endl; } else{ ll mid=v.size()/2; ll ans=0; for(int i=0;i<v.size();i++){ ans+=abs(v[i]-v[mid]); } if (v.size()%2==0){ ll t1=v.size()/2; ll t2=v.size()/2-1; ll d1=t1*(t1+1)/2; ll d2=t2*(t2+1)/2; ans-=(d1+d2); } else{ ll t1=v.size()/2; ll d1=t1*(t1+1)/2; ans-=(2*d1); } cout<<ans<<endl; } } int main(){ int t=1; cin>>t; while(t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; int n, a, b, k, tt; int tree1[800000], tree2[800000]; void updata1(int L, int R, int ro, int x, int v) { if (x < L || x > R) return; if (L == R && L == x) { tree1[ro] = min(v + tree1[ro], b); return; } int Mid = (L + R) / 2; updata1(L, Mid, ro * 2, x, v); updata1(Mid + 1, R, ro * 2 + 1, x, v); tree1[ro] = tree1[ro * 2] + tree1[ro * 2 + 1]; } void updata2(int L, int R, int ro, int x, int v) { if (x < L || x > R) return; if (L == R && L == x) { tree2[ro] = min(v + tree2[ro], a); return; } int Mid = (L + R) / 2; updata2(L, Mid, ro * 2, x, v); updata2(Mid + 1, R, ro * 2 + 1, x, v); tree2[ro] = tree2[ro * 2] + tree2[ro * 2 + 1]; } int quary1(int ro, int L, int R, int l, int r) { if (r < L || l > R) return 0; if (l <= L && R <= r) return tree1[ro]; int Mid = (L + R) / 2; int x1 = quary1(ro * 2, L, Mid, l, r), x2 = quary1(ro * 2 + 1, Mid + 1, R, l, r); return x1 + x2; } int quary2(int ro, int L, int R, int l, int r) { if (r < L || l > R) return 0; if (l <= L && R <= r) return tree2[ro]; int Mid = (L + R) / 2; int x1 = quary2(ro * 2, L, Mid, l, r), x2 = quary2(ro * 2 + 1, Mid + 1, R, l, r); return x1 + x2; } int main() { scanf( %d%d%d%d%d , &n, &k, &a, &b, &tt); for (int i = 1; i <= tt; i++) { int a1, b1, c1; scanf( %d , &a1); if (a1 == 1) { scanf( %d%d , &b1, &c1); updata1(1, n, 1, b1, c1); updata2(1, n, 1, b1, c1); } else if (a1 == 2) { scanf( %d , &b1); printf( %d n , quary1(1, 1, n, 1, b1 - 1) + quary2(1, 1, n, b1 + k, n)); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m; cin >> n >> m; long long a[n + 1]; for (int i = 1; i <= n; i++) cin >> a[i]; long long v, x, add = 0, y, q; int t; while (m--) { cin >> t; if (t == 1) { cin >> v >> x; a[v] = x - add; } else if (t == 2) { cin >> y; add += y; } else { cin >> q; cout << a[q] + add << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 7; inline void rvi(vector<int>& v, int n) { int temp; for (int i = 0; i < n; i++) { cin >> temp; v.push_back(temp); } } inline void rvll(vector<long long int>& v, int n) { long long int temp; for (int i = 0; i < n; i++) { cin >> temp; v.push_back(temp); } } inline void prvi(vector<int>& a) { for (int i = 0; i < a.size(); i++) { cout << a[i] << ; } cout << endl; } inline void prvll(vector<long long int>& a) { for (int i = 0; i < a.size(); i++) { cout << a[i] << ; } cout << endl; } inline void prmii(map<int, int>& m) { for (auto x : m) { cout << x.first << << x.second << endl; } } inline vector<long long int> prefixsum(vector<int>& a) { vector<long long int> b; b.push_back(a[0]); for (int i = 1; i < a.size(); i++) { b.push_back(a[i] + b[i - 1]); } return b; } inline vector<long long int> suffixsum(vector<int>& a) { vector<long long int> b((a.size())); b[(a.size()) - 1] = a[(a.size()) - 1]; for (int i = (a.size()) - 1 - 1; i >= 0; i--) { b[i] = a[i] + b[i + 1]; } return b; } inline vector<long long int> prefixsum(vector<long long int>& a) { vector<long long int> b; b.push_back(a[0]); for (int i = 1; i < a.size(); i++) { b.push_back(a[i] + b[i - 1]); } return b; } inline vector<long long int> suffixsum(vector<long long int>& a) { vector<long long int> b((a.size())); b[(a.size()) - 1] = a[(a.size()) - 1]; for (int i = (a.size()) - 1 - 1; i >= 0; i--) { b[i] = a[i] + b[i + 1]; } return b; } void solve(); int main() { solve(); return 0; } void solve() { int t; cin >> t; while (t--) { int d; cin >> d; double a, b; if (d * d - 4 * d < 0) { cout << N n ; } else { a = (d + sqrt(d * d - 4 * d)) / 2; b = d - a; printf( Y %.10lf %.10lf n , a, b); } } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; auto chk = [&](int x, int y) { return 0 <= x && x < n && 0 <= y && y < m; }; vector<int> nxt(n * m, -1), deg(n * m), dp(n * m), dp2(n * m); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { char c; cin >> c; int x = i, y = j; if (c == L ) --y; if (c == R ) ++y; if (c == U ) --x; if (c == D ) ++x; if (chk(x, y)) { nxt[i * m + j] = x * m + y; deg[x * m + y] += 1; } } } for (int i = 0; i < n * m; ++i) dp2[i] = i; queue<int> q; for (int i = 0; i < n * m; ++i) if (deg[i] == 0) q.push(i); while (!q.empty()) { int u = q.front(); q.pop(); if (nxt[u] != -1) { int v = nxt[u]; if (dp[v] < dp[u] + 1) { dp[v] = dp[u] + 1; dp2[v] = dp2[u]; } if (--deg[v] == 0) q.push(v); } } int ans = 0; for (int i = 0; i < n * m; ++i) { if (deg[i] == 0) continue; int p = nxt[i]; vector<int> loop; while (p != i) { loop.push_back(p); p = nxt[p]; } loop.push_back(i); for (int j : loop) dp[j] += loop.size() - 1, deg[j] = 0; } int mx = -1, x = -1, y = -1; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (dp[i * m + j] > mx) { mx = dp[i * m + j]; x = dp2[i * m + j] / m; y = dp2[i * m + j] % m; } } } cout << x + 1 << << y + 1 << << mx + 1 << endl; } }
|
// megafunction wizard: %LPM_COUNTER%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: dummy_cnt.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2.16 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dummy_cnt (
aclr,
clock,
q);
input aclr;
input clock;
output [7:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Direction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "8"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dummy_cnt.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dummy_cnt.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dummy_cnt.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dummy_cnt.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dummy_cnt_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dummy_cnt_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> inline int abs(int n) { return n < 0 ? -n : n; } bool board[20][20]; int dx[] = {-3, -2, -2, -1, -1, 0, 0, 1, 1, 2, 2, 3}; int dy[] = {0, 1, -1, 2, -2, 3, -3, 2, -2, 1, -1, 0}; int dfs(int p, int n, int m) { int mx = p, t, cnt = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (!board[i][j]) { board[i][j] = true; for (int k = 0; k < 12; k++) { int ic = i + dx[k], jc = j + dy[k]; if (ic >= 0 && ic < n && jc >= 0 && jc < m && !board[ic][jc]) { board[ic][jc] = true; t = dfs(p + 2, n, m); mx < t && (mx = t); if (mx == ((m * n) | 1) - 1) return mx; board[ic][jc] = false; } } board[i][j] = false; cnt++; if (m * n - cnt <= mx) return mx; } } } return mx; } int ans[] = {0, 0, 0, 0, 2, 4}; int main() { int m, n; scanf( %d%d , &m, &n); if (m < 10 && n < 10) { printf( %d n , dfs(0, n, m)); } else if (m == 1) { printf( %d n , n / 6 * 6 + ans[n % 6]); } else if (n == 1) { printf( %d n , m / 6 * 6 + ans[m % 6]); } else { printf( %lld n , (((long long)(m)*n) | 1) - 1); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_BLACKBOX_V
`define SKY130_FD_SC_HS__INV_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__inv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_BLACKBOX_V
|
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