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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_BEHAVIORAL_V
|
`timescale 1ns/10ps
module soc_system_sdram_pll(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("100.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("143.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("143.000000 MHz"),
.phase_shift1("-3758 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; struct Edge { int to, cap, flow; }; struct Graph { int n; vector<vector<int> > e; vector<Edge> edges; vector<int> d, c; Graph() {} Graph(int _n) { n = _n; e.resize(n); } void addEdge(int from, int to, int cap) { e[from].push_back(edges.size()); edges.push_back(Edge({to, cap, 0})); e[to].push_back(edges.size()); edges.push_back(Edge({from, 0, 0})); } bool bfs() { d.assign(n, INF); c.assign(n, 0); vector<int> q(n); int qL = 0, qR = 0; d[0] = 0; q[qR++] = 0; while (qL < qR) { int v = q[qL++]; for (int i = 0; i < (int)e[v].size(); i++) { Edge cur = edges[e[v][i]]; if (d[cur.to] > d[v] + 1 && cur.flow < cur.cap) { d[cur.to] = d[v] + 1; q[qR++] = cur.to; } } } return d[n - 1] != INF; } int dfs(int v, int flow) { if (v == n - 1) return flow; if (flow == 0) return 0; for (int &i = c[v]; i < (int)e[v].size(); i++) { Edge cur = edges[e[v][i]]; if (d[cur.to] != d[v] + 1) continue; int pushed = dfs(cur.to, min(flow, cur.cap - cur.flow)); if (pushed > 0) { edges[e[v][i]].flow += pushed; edges[e[v][i] ^ 1].flow -= pushed; return pushed; } } return 0; } long long flow() { long long flow = 0; while (bfs()) { while (int pushed = dfs(0, INF)) { flow += pushed; } } return flow; } }; int main() { int n, m, h; while (cin >> n >> h >> m) { vector<int> l(m), r(m), x(m), c(m); for (int i = 0; i < m; i++) { cin >> l[i] >> r[i] >> x[i] >> c[i]; x[i]++; l[i]--; r[i]--; } Graph gr(1 + n * (h + 1) + m + 1); int sz = gr.n; long long sum = 0; for (int i = 0; i < n; i++) { for (int j = 1; j <= h; j++) { gr.addEdge(1 + i * (h + 1) + (j - 1), 1 + i * (h + 1) + j, INF); gr.addEdge(1 + i * (h + 1) + j, sz - 1, 2 * j - 1); sum += 2 * j - 1; } } for (int i = 0; i < m; i++) { if (x[i] > h) continue; for (int t = l[i]; t <= r[i]; t++) { gr.addEdge(1 + n * (h + 1) + i, 1 + t * (h + 1) + x[i], INF); } gr.addEdge(0, 1 + n * (h + 1) + i, c[i]); } cout << sum - gr.flow() << endl; } }
|
#include <bits/stdc++.h> using namespace std; int val_of_op[200]; int n; struct T { string Name, Expr; bool danger; int num[5]; int sum(int a0 = 0, int a1 = 0, int a2 = 0, int a3 = 0) { return num[a0] + num[a1] + num[a2] + num[a3]; } } macro[1000]; void Eliminate_Space(string &s) { int p; while ((p = s.find( )) != string::npos) s.erase(s.begin() + p); } bool isDigit(char c) { return c >= 0 && c <= 9 ; } bool isLetter(char c) { return c >= a && c <= z || c >= A && c <= Z ; } stack<int> Ope, Num; void Pop(int n) { int y = Num.top(); Num.pop(); int x = Num.top(); Num.pop(); int z = Ope.top(); Ope.pop(); if (x != -1 && macro[x].danger || y != -1 && macro[y].danger) macro[n].danger = 1; if (z == 2 && y != -1 && macro[y].sum(1, 2)) macro[n].danger = 1; if (z == 3) if (y != -1 && macro[y].sum(1, 2) || x != -1 && macro[x].sum(1, 2)) macro[n].danger = 1; if (z == 4) if (x != -1 && macro[x].sum(1, 2) || y != -1 && macro[y].sum(1, 2, 3, 4)) macro[n].danger = 1; Num.push(x); } void doit(int n, string &s) { while (!Ope.empty()) Ope.pop(); while (!Num.empty()) Num.pop(); int p = 0; while (p < ((int)(s).size())) { if (s[p] == ( ) { Ope.push(-1); p++; continue; } if (s[p] == ) ) { while (Ope.top() != -1) Pop(n + 1); Ope.pop(); if (Num.top() != -1 && macro[Num.top()].danger) macro[n + 1].danger = 1; Num.top() = -1; p++; continue; } if (val_of_op[s[p]]) { while (!Ope.empty() && val_of_op[s[p]] <= 2 && Ope.top() >= 3) Pop(n + 1); Ope.push(val_of_op[s[p]]); p++; continue; } string a; while (p < ((int)(s).size()) && (isDigit(s[p]) || isLetter(s[p]))) a.push_back(s[p++]); int i = -1; for (int j = (1); j <= (n); j++) if (macro[j].Name == a) i = j; Num.push(i); } while (!Ope.empty()) macro[n + 1].num[Ope.top()]++, Pop(n + 1); if (Num.top() != -1 && macro[Num.top()].danger) macro[n + 1].danger = 1; } int main() { val_of_op[ + ] = 1, val_of_op[ - ] = 2, val_of_op[ * ] = 3, val_of_op[ / ] = 4; cin >> n; getline(cin, macro[1].Name); for (int i = (1); i <= (n); i++) { getline(cin, macro[i].Name, e ); getline(cin, macro[i].Name, e ); cin >> macro[i].Name; getline(cin, macro[i].Expr); Eliminate_Space(macro[i].Expr); doit(i - 1, macro[i].Expr); } string Expr; getline(cin, Expr); Eliminate_Space(Expr); doit(n, Expr); if (macro[n + 1].danger) puts( Suspicious ); else puts( OK ); return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_a_e
//
// Generated
// by: wig
// on: Wed Jun 7 16:54:20 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_a_e.v,v 1.4 2006/06/22 07:19:59 wig Exp $
// $Date: 2006/06/22 07:19:59 $
// $Log: inst_a_e.v,v $
// Revision 1.4 2006/06/22 07:19:59 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_a_e
//
// No user `defines in this module
module inst_a_e
//
// Generated Module inst_a
//
(
p_mix_test1_go,
unsplice_a1_no3, // leaves 3 unconnected
unsplice_a2_all128, // full 128 bit port
unsplice_a3_up100, // connect 100 bits from 0
unsplice_a4_mid100, // connect mid 100 bits
unsplice_a5_midp100, // connect mid 100 bits
unsplice_bad_a,
unsplice_bad_b,
widemerge_a1,
widesig_o,
widesig_r_0,
widesig_r_1,
widesig_r_10,
widesig_r_11,
widesig_r_12,
widesig_r_13,
widesig_r_14,
widesig_r_15,
widesig_r_16,
widesig_r_17,
widesig_r_18,
widesig_r_19,
widesig_r_2,
widesig_r_20,
widesig_r_21,
widesig_r_22,
widesig_r_23,
widesig_r_24,
widesig_r_25,
widesig_r_26,
widesig_r_27,
widesig_r_28,
widesig_r_29,
widesig_r_3,
widesig_r_30,
widesig_r_4,
widesig_r_5,
widesig_r_6,
widesig_r_7,
widesig_r_8,
widesig_r_9
);
// Generated Module Outputs:
output p_mix_test1_go;
output [127:0] unsplice_a1_no3;
output [127:0] unsplice_a2_all128;
output [127:0] unsplice_a3_up100;
output [127:0] unsplice_a4_mid100;
output [127:0] unsplice_a5_midp100;
output [127:0] unsplice_bad_a;
output [127:0] unsplice_bad_b;
output [31:0] widemerge_a1;
output [31:0] widesig_o;
output widesig_r_0;
output widesig_r_1;
output widesig_r_10;
output widesig_r_11;
output widesig_r_12;
output widesig_r_13;
output widesig_r_14;
output widesig_r_15;
output widesig_r_16;
output widesig_r_17;
output widesig_r_18;
output widesig_r_19;
output widesig_r_2;
output widesig_r_20;
output widesig_r_21;
output widesig_r_22;
output widesig_r_23;
output widesig_r_24;
output widesig_r_25;
output widesig_r_26;
output widesig_r_27;
output widesig_r_28;
output widesig_r_29;
output widesig_r_3;
output widesig_r_30;
output widesig_r_4;
output widesig_r_5;
output widesig_r_6;
output widesig_r_7;
output widesig_r_8;
output widesig_r_9;
// Generated Wires:
wire p_mix_test1_go;
wire [127:0] unsplice_a1_no3;
wire [127:0] unsplice_a2_all128;
wire [127:0] unsplice_a3_up100;
wire [127:0] unsplice_a4_mid100;
wire [127:0] unsplice_a5_midp100;
wire [127:0] unsplice_bad_a;
wire [127:0] unsplice_bad_b;
wire [31:0] widemerge_a1;
wire [31:0] widesig_o;
wire widesig_r_0;
wire widesig_r_1;
wire widesig_r_10;
wire widesig_r_11;
wire widesig_r_12;
wire widesig_r_13;
wire widesig_r_14;
wire widesig_r_15;
wire widesig_r_16;
wire widesig_r_17;
wire widesig_r_18;
wire widesig_r_19;
wire widesig_r_2;
wire widesig_r_20;
wire widesig_r_21;
wire widesig_r_22;
wire widesig_r_23;
wire widesig_r_24;
wire widesig_r_25;
wire widesig_r_26;
wire widesig_r_27;
wire widesig_r_28;
wire widesig_r_29;
wire widesig_r_3;
wire widesig_r_30;
wire widesig_r_4;
wire widesig_r_5;
wire widesig_r_6;
wire widesig_r_7;
wire widesig_r_8;
wire widesig_r_9;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [7:0] s_port_offset_01;
wire [7:0] s_port_offset_02;
wire [1:0] s_port_offset_02b;
wire test1; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] test2;
wire [3:0] test3;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_test1_go = test1; // __I_O_BIT_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_1(test1), // Use internally test1
.port_2(test2[0]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[0]), // Bus combining o.k.
.port_o(s_port_offset_01),
.port_o02[10:3](s_port_offset_02), // __W_PORT// __E_CANNOT_COMBINE_SPLICES
.port_o02[1:0](s_port_offset_02b) // __W_PORT// __E_CANNOT_COMBINE_SPLICES
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_2(test2[1]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[1]), // Bus combining o.k.
.port_ab_1(test1), // Use internally test1
.port_i(s_port_offset_01),
.port_i02[10:3](s_port_offset_02), // __W_PORT// __E_CANNOT_COMBINE_SPLICES
.port_i02[2:1](s_port_offset_02b) // __W_PORT// __E_CANNOT_COMBINE_SPLICES
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_2(test2[3]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[2]) // Bus combining o.k.
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_2(test2[4]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[3]) // Bus combining o.k.
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_2(test2), // Bus with hole in the middleNeeds input to be happy
.port_3(test3) // Bus combining o.k.
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of inst_a_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; long long dp[300300]; int a[300300], h[300300], d[300300]; vector<int> ans; inline void calc(int i) { int mn = min(a[i], a[i + 1]); if (!mn) return; ans.push_back(i); a[i] -= mn, a[i + 1] -= mn; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= 2; i++) dp[i] = a[i], d[i] = 1; for (int i = 3; i <= n; i++) { if (dp[i - 2] + a[i] < dp[i - 3] + max(a[i], a[i - 1])) dp[i] = dp[i - 2] + a[i], d[i] = 1; else dp[i] = dp[i - 3] + max(a[i], a[i - 1]), d[i] = 2; } for (int i = n - (dp[n] >= dp[n - 1]); i > 0; i -= d[i] + 1) { h[i] = h[i - d[i] + 1] = 1; } for (int i = 1; i <= n; i++) if (h[i]) { if (h[i + 1]) calc(i); calc(i - 1), calc(i); } printf( %d n , ans.size()); for (int x : ans) printf( %d n , x); }
|
`timescale 100 ps/100 ps
module circuit_under_test (
clk,
rst,
testVector,
resultVector,
injectionVector
);
input clk;
input rst;
input[7:0] testVector;
output[7:0] resultVector;
input[104:0] injectionVector;
fir_inj toplevel_instance (
.x_in(testVector [7:0]),
.clk(clk),
.y(resultVector [7:0]),
.p_desc0_p_O_FD(injectionVector[0]),
.p_desc1_p_O_FD(injectionVector[1]),
.p_desc2_p_O_FD(injectionVector[2]),
.p_desc3_p_O_FD(injectionVector[3]),
.p_desc4_p_O_FD(injectionVector[4]),
.p_desc5_p_O_FD(injectionVector[5]),
.p_desc6_p_O_FD(injectionVector[6]),
.p_desc7_p_O_FD(injectionVector[7]),
.p_desc8_p_O_FD(injectionVector[8]),
.p_desc9_p_O_FD(injectionVector[9]),
.p_desc10_p_O_FD(injectionVector[10]),
.p_desc11_p_O_FD(injectionVector[11]),
.p_desc12_p_O_FD(injectionVector[12]),
.p_desc13_p_O_FD(injectionVector[13]),
.p_desc14_p_O_FD(injectionVector[14]),
.p_desc15_p_O_FD(injectionVector[15]),
.p_desc16_p_O_FD(injectionVector[16]),
.p_desc17_p_O_FD(injectionVector[17]),
.p_desc18_p_O_FD(injectionVector[18]),
.p_desc19_p_O_FD(injectionVector[19]),
.p_desc20_p_O_FD(injectionVector[20]),
.p_desc21_p_O_FD(injectionVector[21]),
.p_desc22_p_O_FD(injectionVector[22]),
.p_desc23_p_O_FD(injectionVector[23]),
.p_desc24_p_O_FD(injectionVector[24]),
.p_desc25_p_O_FD(injectionVector[25]),
.p_desc26_p_O_FD(injectionVector[26]),
.p_desc27_p_O_FD(injectionVector[27]),
.p_desc28_p_O_FD(injectionVector[28]),
.p_desc29_p_O_FD(injectionVector[29]),
.p_desc30_p_O_FD(injectionVector[30]),
.p_desc31_p_O_FD(injectionVector[31]),
.p_desc32_p_O_FD(injectionVector[32]),
.p_x_14_pipe_0_Z_p_O_FD(injectionVector[33]),
.p_x_14_pipe_9_Z_p_O_FD(injectionVector[34]),
.p_x_14_pipe_10_Z_p_O_FD(injectionVector[35]),
.p_x_14_pipe_11_Z_p_O_FD(injectionVector[36]),
.p_x_14_pipe_12_Z_p_O_FD(injectionVector[37]),
.p_x_14_pipe_13_Z_p_O_FD(injectionVector[38]),
.p_x_14_pipe_14_Z_p_O_FD(injectionVector[39]),
.p_x_14_pipe_15_Z_p_O_FD(injectionVector[40]),
.p_x_14_pipe_16_Z_p_O_FD(injectionVector[41]),
.p_x_14_pipe_17_Z_p_O_FD(injectionVector[42]),
.p_x_9_pipe_1_Z_p_O_FD(injectionVector[43]),
.p_x_9_pipe_2_Z_p_O_FD(injectionVector[44]),
.p_x_9_pipe_3_Z_p_O_FD(injectionVector[45]),
.p_x_9_pipe_4_Z_p_O_FD(injectionVector[46]),
.p_x_9_pipe_5_Z_p_O_FD(injectionVector[47]),
.p_x_9_pipe_6_Z_p_O_FD(injectionVector[48]),
.p_x_9_pipe_7_Z_p_O_FD(injectionVector[49]),
.p_x_9_pipe_8_Z_p_O_FD(injectionVector[50]),
.p_x_15_pipe_0_0_15_Z_p_O_FD(injectionVector[51]),
.p_x_15_pipe_0_0_16_Z_p_O_FD(injectionVector[52]),
.p_x_15_pipe_0_0_17_Z_p_O_FD(injectionVector[53]),
.p_x_15_pipe_0_0_18_Z_p_O_FD(injectionVector[54]),
.p_x_15_pipe_0_0_19_Z_p_O_FD(injectionVector[55]),
.p_x_15_pipe_0_0_20_Z_p_O_FD(injectionVector[56]),
.p_x_15_pipe_0_0_21_Z_p_O_FD(injectionVector[57]),
.p_x_15_pipe_0_0_22_Z_p_O_FD(injectionVector[58]),
.p_x_15_pipe_0_0_23_Z_p_O_FD(injectionVector[59]),
.p_x_15_pipe_0_0_24_Z_p_O_FD(injectionVector[60]),
.p_x_15_pipe_0_0_25_Z_p_O_FD(injectionVector[61]),
.p_x_15_pipe_0_0_26_Z_p_O_FD(injectionVector[62]),
.p_x_15_pipe_0_0_27_Z_p_O_FD(injectionVector[63]),
.p_x_15_pipe_0_0_28_Z_p_O_FD(injectionVector[64]),
.p_x_15_pipe_0_0_29_Z_p_O_FD(injectionVector[65]),
.p_x_16_pipe_0_0_0_Z_p_O_FD(injectionVector[66]),
.p_x_16_pipe_0_0_1_Z_p_O_FD(injectionVector[67]),
.p_x_16_pipe_0_0_2_Z_p_O_FD(injectionVector[68]),
.p_x_16_pipe_0_0_3_Z_p_O_FD(injectionVector[69]),
.p_x_16_pipe_0_0_4_Z_p_O_FD(injectionVector[70]),
.p_x_16_pipe_0_0_5_Z_p_O_FD(injectionVector[71]),
.p_x_16_pipe_0_0_6_Z_p_O_FD(injectionVector[72]),
.p_x_16_pipe_0_0_7_Z_p_O_FD(injectionVector[73]),
.p_x_16_pipe_0_0_8_Z_p_O_FD(injectionVector[74]),
.p_x_16_pipe_0_0_9_Z_p_O_FD(injectionVector[75]),
.p_x_16_pipe_0_0_10_Z_p_O_FD(injectionVector[76]),
.p_x_16_pipe_0_0_11_Z_p_O_FD(injectionVector[77]),
.p_x_16_pipe_0_0_12_Z_p_O_FD(injectionVector[78]),
.p_x_16_pipe_0_0_13_Z_p_O_FD(injectionVector[79]),
.p_x_16_pipe_0_0_14_Z_p_O_FD(injectionVector[80]),
.p_desc33_p_O_FD(injectionVector[81]),
.p_desc34_p_O_FD(injectionVector[82]),
.p_desc35_p_O_FD(injectionVector[83]),
.p_desc36_p_O_FD(injectionVector[84]),
.p_desc37_p_O_FD(injectionVector[85]),
.p_desc38_p_O_FD(injectionVector[86]),
.p_desc39_p_O_FD(injectionVector[87]),
.p_desc40_p_O_FD(injectionVector[88]),
.p_desc41_p_O_FD(injectionVector[89]),
.p_desc42_p_O_FD(injectionVector[90]),
.p_desc43_p_O_FD(injectionVector[91]),
.p_desc44_p_O_FD(injectionVector[92]),
.p_desc45_p_O_FD(injectionVector[93]),
.p_desc46_p_O_FD(injectionVector[94]),
.p_desc47_p_O_FD(injectionVector[95]),
.p_desc48_p_O_FD(injectionVector[96]),
.p_desc49_p_O_FD(injectionVector[97]),
.p_desc50_p_O_FD(injectionVector[98]),
.p_desc51_p_O_FD(injectionVector[99]),
.p_desc52_p_O_FD(injectionVector[100]),
.p_desc53_p_O_FD(injectionVector[101]),
.p_desc54_p_O_FD(injectionVector[102]),
.p_desc55_p_O_FD(injectionVector[103]),
.p_desc56_p_O_FD(injectionVector[104]));
endmodule
|
Require Import NArith.
Require FMapList.
Require Import OrderedType.
Require Import Word.
Require Import ContractSem.
Module AbstractExamples (W : Word).
Module C := (ContractSem.Make W).
Import C.
(**** Now we are able to specify contractsin terms of how they behave over
many invocations, returns from calls and even reentrancy! ***)
(* Example 0: a contract that always fails *)
CoFixpoint always_fail :=
ContractAction ContractFail
(Respond (fun _ => always_fail)
(fun _ => always_fail)
always_fail).
(* Example 1: a contract that always returns *)
CoFixpoint always_return x :=
ContractAction (ContractReturn x)
(Respond (fun (_ : call_env) => always_return x)
(fun (_ : return_result) => always_return x)
(always_return x)).
(* Example 2: a contract that calls something and then returns, but fails on reentrancy *)
Section FailOnReentrance.
Variable something_to_call : call_arguments.
CoFixpoint call_but_fail_on_reentrance (depth : nat) :=
match depth with
| O =>
Respond
(fun _ =>
ContractAction (ContractCall something_to_call)
(call_but_fail_on_reentrance (S O)))
(fun _ => ContractAction ContractFail (call_but_fail_on_reentrance O))
(ContractAction ContractFail (call_but_fail_on_reentrance O))
| S O => (* now the callee responds or reenters *)
Respond
(fun _ => ContractAction ContractFail (call_but_fail_on_reentrance (S O)))
(fun retval => ContractAction (ContractReturn retval.(return_data)) (call_but_fail_on_reentrance O))
(ContractAction ContractFail (call_but_fail_on_reentrance O))
| S (S n) =>
Respond
(fun _ => ContractAction ContractFail (call_but_fail_on_reentrance (S (S n))))
(fun retval => ContractAction ContractFail (call_but_fail_on_reentrance (S n)))
(ContractAction ContractFail (call_but_fail_on_reentrance (S n)))
end.
End FailOnReentrance.
(******* Example 3.
When re-entrance happens to the contract at example 2. ***)
Section Example3.
Variable e : call_env.
Variable a : call_arguments.
Let example3_world :=
WorldCall e :: WorldCall e :: nil.
Let example2_contract :=
call_but_fail_on_reentrance a 0.
Let example3_history := specification_run example3_world example2_contract.
Eval compute in example3_history.
(*
= ActionByWorld (WorldCall e)
:: ActionByContract (ContractCall a)
:: ActionByWorld (WorldCall e)
:: ActionByContract ContractFail :: nil
: history
*)
End Example3.
Section Example0Continue.
Definition spec_example_0 : response_to_world :=
Respond
(fun _ => always_fail)
(fun _ => always_fail)
always_fail.
Variable example0_address : address.
Definition example0_program :=
PUSH1 (word_of_N 0) ::
JUMP :: nil.
Definition example0_account_state (bal : word) :=
{| account_address := example0_address ;
account_storage := empty_storage ;
account_code := example0_program ;
account_balance := bal ;
account_ongoing_calls := nil |}.
Require Coq.Setoids.Setoid.
Lemma always_fail_eq :
forall act continuation,
always_fail = ContractAction act continuation ->
act = ContractFail /\
continuation = Respond (fun _ => always_fail)
(fun _ => always_fail)
always_fail.
Proof.
intros ? ?.
rewrite <- (contract_action_expander_eq always_fail) at 1.
intro H.
inversion H.
auto.
Qed.
(** learned from https://github.com/uwplse/verdi/blob/master/PROOF_ENGINEERING.md **)
Ltac always_fail_tac :=
match goal with
[ H: always_fail = ContractAction ?act ?continuation |- _ ] =>
apply always_fail_eq in H; destruct H; subst
end.
(* should be moved to Word *)
Axiom smaller_word_of_N :
forall x y,
x < 100000 ->
y < 100000 ->
word_smaller (word_of_N x) (word_of_N y) = (N.ltb x y).
Theorem example0_spec_impl_match :
forall bal,
account_state_responds_to_world
(example0_account_state bal) spec_example_0 (fun _ _ => True).
Proof.
cofix.
intro bal.
apply AccountStep.
{
intros ? ? ?.
split; [solve [auto] | ].
intros _ ?.
always_fail_tac.
intros steps.
case steps as [ | steps]; [ try left; auto | ].
case steps as [ | steps]; [ try left; auto | ].
simpl.
assert (H : word_mod (word_of_N 0) (word_of_N 256) = word_of_N 0) by admit.
rewrite H.
simpl.
auto.
simpl.
rewrite N_of_word_of_N.
{ cbn.
right.
eexists.
eexists.
eexists.
eauto.
}
compute.
auto.
}
{
unfold respond_to_return_correctly.
intros rr venv continuation act.
unfold example0_account_state.
unfold build_venv_returned.
simpl.
congruence.
}
{
unfold respond_to_fail_correctly.
intros venv continuation act.
unfold example0_account_state.
unfold build_venv_fail.
simpl.
congruence.
}
Admitted.
End Example0Continue.
Section Example1Continue.
(*** prove that example 1 has an implementation *)
Definition return_result_nil : list byte := nil.
Definition action_example_1 :=
always_return return_result_nil.
Definition spec_example_1 : response_to_world :=
Respond
(fun _ => action_example_1)
(fun _ => action_example_1)
action_example_1.
Variable example1_address : address.
Definition example1_program : list instruction :=
PUSH1 word_zero ::
PUSH1 word_zero ::
RETURN ::
nil.
Definition example1_account_state bal :=
{| account_address := example1_address ;
account_storage := empty_storage ;
account_code := example1_program ;
account_balance := bal ;
account_ongoing_calls := nil |}.
Lemma always_return_def :
forall x,
always_return x =
ContractAction (ContractReturn x)
(Respond (fun (_ : call_env) => always_return x)
(fun (_ : return_result) => always_return x)
(always_return x)).
Proof.
intro x.
rewrite <- (contract_action_expander_eq (always_return x)) at 1.
auto.
Qed.
Lemma always_return_eq :
forall act continuation x,
always_return x = ContractAction act continuation ->
act = ContractReturn x /\
continuation = Respond (fun _ => always_return x)
(fun _ => always_return x)
(always_return x).
Proof.
intros ? ? ?.
rewrite always_return_def at 1.
intro H.
inversion H; subst.
auto.
Qed.
(** learned from https://github.com/uwplse/verdi/blob/master/PROOF_ENGINEERING.md **)
Ltac always_return_tac :=
match goal with
[ H: always_return ?x = ContractAction ?act ?continuation |- _ ] =>
apply always_return_eq in H; destruct H; subst
end.
Theorem example1_spec_impl_match :
forall bal,
account_state_responds_to_world
(example1_account_state bal) spec_example_1 (fun _ _ => True).
Proof.
cofix.
intro bal.
apply AccountStep.
{ (* call case *)
unfold respond_to_call_correctly.
intros.
split; [solve [auto] | ].
intros _.
intro H.
intro steps.
case steps as [|steps]; [left; auto | ].
case steps as [|steps]; [left; auto | ].
case steps as [|steps]; [left; auto | ].
unfold action_example_1 in H.
always_return_tac.
right.
simpl.
f_equal.
f_equal.
simpl.
assert (Z : word_mod word_zero (word_of_N 256) = word_zero).
{
admit.
}
rewrite Z.
rewrite cut_memory_zero_nil.
eexists.
eexists.
eexists.
auto.
split; [eauto | ].
apply example1_spec_impl_match.
}
{
intros ? ? ? ?.
simpl.
congruence.
}
{
intros ? ? ?.
simpl.
congruence.
}
Admitted.
End Example1Continue.
End AbstractExamples.
|
#include <bits/stdc++.h> using namespace std; const int MAX = 300 + 5; int n, m, p; int grid[MAX][MAX]; int dp[MAX][MAX]; vector<pair<int, int> > pos[MAX * MAX]; vector<int> col[MAX]; int main() { scanf( %d %d %d , &n, &m, &p); for (int i = int(0); i < int(n); i++) { for (int j = int(0); j < int(m); j++) { scanf( %d , &grid[i][j]); if (grid[i][j] == 1) { dp[i][j] = i + j; } else { dp[i][j] = 1 << 30; } pos[grid[i][j]].emplace_back(i, j); } } bool visited[MAX]; for (int i = int(1); i < int(p); i++) { memset(visited, false, sizeof visited); for (int c = int(0); c < int(m); c++) { col[c].clear(); } for (auto &each : pos[i + 1]) { col[each.second].push_back(each.first); } for (auto &each : pos[i]) { visited[each.first] = true; } for (int r = int(0); r < int(n); r++) { if (visited[r]) { int best = 1 << 30; for (int c = int(0); c < int(m); c++) { best++; if (grid[r][c] == i) { best = min(best, dp[r][c]); } for (auto &each : col[c]) { dp[each][c] = min(dp[each][c], best + abs(each - r)); } } best = 1 << 30; for (int c = int(m - 1); c >= int(0); c--) { best++; if (grid[r][c] == i) { best = min(best, dp[r][c]); } for (auto &each : col[c]) { dp[each][c] = min(dp[each][c], best + abs(each - r)); } } } } } printf( %d n , dp[pos[p][0].first][pos[p][0].second]); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool pal(string s) { string b = s; reverse(b.begin(), b.end()); return b == s; } int main() { string s; cin >> s; for (int i = 0; i <= s.size(); ++i) { for (char a = a ; a <= z ; ++a) { string b = s.substr(0, i) + a + s.substr(i); if (pal(b)) { cout << b << endl; return 0; } } } cout << NA << endl; return 0; }
|
`timescale 1ns / 1ps
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
//wire [31:0] abusW;
//wire [31:0] bbusW;
//assign abus = abusW;
//assign bbus = bbusW;
assign abus = Aselect[0] ? 32'b0 : 32'bz;//in case it's the 0
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](//32 wide register
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
/*assign abus = Aselect[0] ? 32'b0 : 32'bz;//in case it's the 0
assign bbus = Bselect[0] ? 32'b0 : 32'bz;*/
/*always @(posedge Aselect[0]) begin
abus = 32'b0;
end
always @(posedge Bselect[0]) begin
end*/
endmodule
//negedge sensitive flipflop module flip flop module
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;//the select write bit for this register
input Bselect;//the select read bit for this register
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
reg [31:0] data;
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect ? data : 32'bz;
assign bbus = Bselect ? data : 32'bz;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_4_V
`define SKY130_FD_SC_LS__FILL_DIODE_4_V
/**
* fill_diode: Fill diode.
*
* Verilog wrapper for fill_diode with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill_diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_diode_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_diode_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill_diode base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_4_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e2 + 10; char a[maxn], b[maxn], t[maxn]; int main() { int n; char c[1]; scanf( %d , &n); gets(c); scanf( %s , a + 1); int d = 0; while (d <= n) { d++; if (n % d == 0) { for (int i = 1; i <= d; i++) { b[i] = a[d - i + 1]; } for (int j = d + 1; j <= n; j++) { b[j] = a[j]; } for (int i = 1; i <= n; i++) a[i] = b[i]; } } for (int i = 1; i <= n; i++) printf( %c , b[i]); return 0; }
|
module lru_stats
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(ways_p)
,localparam lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
)
(
input clk_i
,input reset_i
,input stat_mem_v_i
,input stat_mem_w_i
,input [lg_ways_lp-1:0] chosen_way_i
);
localparam ctr_width_lp = 17;
localparam max_ctr_lp = 2**ctr_width_lp; // Max amounts of traces used in python scripts
// Statistic of lru_way picked
integer hit_counter [ways_p-1:0];
logic [ways_p-1:0] counter_en_li;
bsg_decode_with_v
#(.num_out_p(ways_p))
bdwv
(.i(chosen_way_i)
,.v_i(stat_mem_v_i & stat_mem_w_i)
,.o(counter_en_li)
);
for (genvar i = 0; i < ways_p; i++)
begin
always_ff @(posedge clk_i)
begin
if (reset_i)
hit_counter[i] <= 0;
else
begin
if (counter_en_li[i])
hit_counter[i] <= hit_counter[i] + 1;
end
end
end
final
begin
// display statistic
$display("######## Hit Statistic: ########");
for (integer counter_index = 0; counter_index < ways_p; counter_index++)
begin
$display("Hit counter[%d]: %d ", counter_index, hit_counter[counter_index]);
end
end
endmodule
`BSG_ABSTRACT_MODULE(lru_stats)
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:50:33 01/10/2017
// Design Name: barrel_shifter
// Module Name: /home/aaron/Git Repos/CSE311/lab1/barrel_shifter_tb.v
// Project Name: lab1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: barrel_shifter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module barrel_shifter_tb;
// Inputs
reg [7:0] d_in;
reg [2:0] shift_amount;
// Outputs
wire [7:0] d_out;
// Instantiate the Unit Under Test (UUT)
barrel_shifter uut (
.d_in(d_in),
.shift_amount(shift_amount),
.d_out(d_out)
);
initial begin
// Initialize Inputs
d_in = 0;
shift_amount = 0;
// Wait 100 ns for global reset to finish
#100;
// Test to shift left by 1
d_in = 8'b01000000;
shift_amount = 1'd1;
#100;
// New Test for shift left by 2
d_in = 8'b00010000;
shift_amount = 3'b010;
#100;
// Final Test to shift left by 4
d_in = 8'b00100000;
shift_amount = 3'b100;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4BB_2_V
`define SKY130_FD_SC_HDLL__AND4BB_2_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4bb_2 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4bb_2 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4BB_2_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_gen_reset.v
*
* Date : 2012-11
*
* Description : Module that generates FPGA_RESETs and synchronizes RESETs to the
* respective clocks.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_gen_reset(
por_rst_n,
sys_rst_n,
rst_out_n,
m_axi_gp0_clk,
m_axi_gp1_clk,
s_axi_gp0_clk,
s_axi_gp1_clk,
s_axi_hp0_clk,
s_axi_hp1_clk,
s_axi_hp2_clk,
s_axi_hp3_clk,
s_axi_acp_clk,
m_axi_gp0_rstn,
m_axi_gp1_rstn,
s_axi_gp0_rstn,
s_axi_gp1_rstn,
s_axi_hp0_rstn,
s_axi_hp1_rstn,
s_axi_hp2_rstn,
s_axi_hp3_rstn,
s_axi_acp_rstn,
fclk_reset3_n,
fclk_reset2_n,
fclk_reset1_n,
fclk_reset0_n,
fpga_acp_reset_n,
fpga_gp_m0_reset_n,
fpga_gp_m1_reset_n,
fpga_gp_s0_reset_n,
fpga_gp_s1_reset_n,
fpga_hp_s0_reset_n,
fpga_hp_s1_reset_n,
fpga_hp_s2_reset_n,
fpga_hp_s3_reset_n
);
input por_rst_n;
input sys_rst_n;
input m_axi_gp0_clk;
input m_axi_gp1_clk;
input s_axi_gp0_clk;
input s_axi_gp1_clk;
input s_axi_hp0_clk;
input s_axi_hp1_clk;
input s_axi_hp2_clk;
input s_axi_hp3_clk;
input s_axi_acp_clk;
output reg m_axi_gp0_rstn;
output reg m_axi_gp1_rstn;
output reg s_axi_gp0_rstn;
output reg s_axi_gp1_rstn;
output reg s_axi_hp0_rstn;
output reg s_axi_hp1_rstn;
output reg s_axi_hp2_rstn;
output reg s_axi_hp3_rstn;
output reg s_axi_acp_rstn;
output rst_out_n;
output fclk_reset3_n;
output fclk_reset2_n;
output fclk_reset1_n;
output fclk_reset0_n;
output fpga_acp_reset_n;
output fpga_gp_m0_reset_n;
output fpga_gp_m1_reset_n;
output fpga_gp_s0_reset_n;
output fpga_gp_s1_reset_n;
output fpga_hp_s0_reset_n;
output fpga_hp_s1_reset_n;
output fpga_hp_s2_reset_n;
output fpga_hp_s3_reset_n;
reg [31:0] fabric_rst_n;
reg r_m_axi_gp0_rstn;
reg r_m_axi_gp1_rstn;
reg r_s_axi_gp0_rstn;
reg r_s_axi_gp1_rstn;
reg r_s_axi_hp0_rstn;
reg r_s_axi_hp1_rstn;
reg r_s_axi_hp2_rstn;
reg r_s_axi_hp3_rstn;
reg r_s_axi_acp_rstn;
assign rst_out_n = por_rst_n & sys_rst_n;
assign fclk_reset0_n = !fabric_rst_n[0];
assign fclk_reset1_n = !fabric_rst_n[1];
assign fclk_reset2_n = !fabric_rst_n[2];
assign fclk_reset3_n = !fabric_rst_n[3];
assign fpga_acp_reset_n = !fabric_rst_n[24];
assign fpga_hp_s3_reset_n = !fabric_rst_n[23];
assign fpga_hp_s2_reset_n = !fabric_rst_n[22];
assign fpga_hp_s1_reset_n = !fabric_rst_n[21];
assign fpga_hp_s0_reset_n = !fabric_rst_n[20];
assign fpga_gp_s1_reset_n = !fabric_rst_n[17];
assign fpga_gp_s0_reset_n = !fabric_rst_n[16];
assign fpga_gp_m1_reset_n = !fabric_rst_n[13];
assign fpga_gp_m0_reset_n = !fabric_rst_n[12];
task fpga_soft_reset;
input[31:0] reset_ctrl;
begin
fabric_rst_n[0] = reset_ctrl[0];
fabric_rst_n[1] = reset_ctrl[1];
fabric_rst_n[2] = reset_ctrl[2];
fabric_rst_n[3] = reset_ctrl[3];
fabric_rst_n[12] = reset_ctrl[12];
fabric_rst_n[13] = reset_ctrl[13];
fabric_rst_n[16] = reset_ctrl[16];
fabric_rst_n[17] = reset_ctrl[17];
fabric_rst_n[20] = reset_ctrl[20];
fabric_rst_n[21] = reset_ctrl[21];
fabric_rst_n[22] = reset_ctrl[22];
fabric_rst_n[23] = reset_ctrl[23];
fabric_rst_n[24] = reset_ctrl[24];
end
endtask
always@(negedge por_rst_n or negedge sys_rst_n) fabric_rst_n = 32'h01f3_300f;
always@(posedge m_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
m_axi_gp0_rstn = 1'b0;
else
m_axi_gp0_rstn = 1'b1;
end
always@(posedge m_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
m_axi_gp1_rstn = 1'b0;
else
m_axi_gp1_rstn = 1'b1;
end
always@(posedge s_axi_gp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_gp0_rstn = 1'b0;
else
s_axi_gp0_rstn = 1'b1;
end
always@(posedge s_axi_gp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_gp1_rstn = 1'b0;
else
s_axi_gp1_rstn = 1'b1;
end
always@(posedge s_axi_hp0_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp0_rstn = 1'b0;
else
s_axi_hp0_rstn = 1'b1;
end
always@(posedge s_axi_hp1_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp1_rstn = 1'b0;
else
s_axi_hp1_rstn = 1'b1;
end
always@(posedge s_axi_hp2_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp2_rstn = 1'b0;
else
s_axi_hp2_rstn = 1'b1;
end
always@(posedge s_axi_hp3_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_hp3_rstn = 1'b0;
else
s_axi_hp3_rstn = 1'b1;
end
always@(posedge s_axi_acp_clk or negedge (por_rst_n & sys_rst_n))
begin
if (!(por_rst_n & sys_rst_n))
s_axi_acp_rstn = 1'b0;
else
s_axi_acp_rstn = 1'b1;
end
always@(*) begin
if ((por_rst_n!= 1'b0) && (por_rst_n!= 1'b1) && (sys_rst_n != 1'b0) && (sys_rst_n != 1'b1)) begin
$display(" Error:processing_system7_bfm_v2_0_gen_reset. PS_PORB and PS_SRSTB must be driven to known state");
$finish();
end
end
endmodule
|
#include <bits/stdc++.h> int64_t f(int64_t a, int64_t b, int64_t c, int64_t l) { int64_t total = 0; for (int64_t la = 0ll; la <= l; ++la) { int64_t x = std::min(a - b - c + la, l - la); if (x >= 0) total += (x + 1) * (x + 2) / 2ll; } return total; } int main() { int64_t a, b, c, l; std::cin >> a >> b >> c >> l; int64_t total = (l + 1) * (l + 2) * (l + 3) / 6ll; total -= f(a, b, c, l); total -= f(b, a, c, l); total -= f(c, a, b, l); std::cout << total << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> g[100001]; long long v[100001]; pair<long long, long long> r[100001]; int mark[100001]; void dfs(int s) { mark[s] = 1; r[s] = pair<long long, long long>(0, 0); for (int i = 0; i < g[s].size(); i++) { if (!mark[g[s][i]]) { dfs(g[s][i]); r[s].first = min(r[s].first, r[g[s][i]].first); r[s].second = max(r[s].second, r[g[s][i]].second); } } long long k = v[s] - r[s].first - r[s].second; if (k > 0) r[s].second = r[s].second + k; else r[s].first += k; } int main() { int n; memset(mark, 0, sizeof mark); cin >> n; int a, b; for (int i = 0; i < n - 1; i++) { cin >> a >> b; g[a - 1].push_back(b - 1); g[b - 1].push_back(a - 1); } for (int i = 0; i < n; i++) cin >> v[i]; dfs(0); long long ans = -r[0].first + r[0].second; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int matrix[n][n], sum = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> matrix[i][j]; } } int j = 0; for (int i = 0; i < n; i++) { sum += matrix[i][i]; } for (int i = n - 1; i >= 0; i--) { sum += matrix[i][j]; j++; } int ind = (n - 1) / 2; for (auto it : matrix) sum += it[ind]; for (int i = 0; i < n; i++) sum += matrix[ind][i]; cout << sum - (3 * matrix[ind][ind]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 35000 + 10; const int MAXK = 55; int tree[MAXN << 2], info[MAXN << 2]; int dp[MAXK][MAXN]; int nums[MAXN]; int pre[MAXN], cur[MAXN]; void build(int node, int start, int end, int i) { if (start == end) { tree[node] = dp[i][start - 1]; info[node] = 0; return; } int mid = (start + end) >> 1; build((node << 1), start, mid, i); build(((node << 1) | 1), mid + 1, end, i); tree[node] = max(tree[(node << 1)], tree[((node << 1) | 1)]); info[node] = 0; } void update(int node, int start, int end, int i, int j, int val) { if (end < i || j < start) return; if (i <= start && end <= j) { tree[node] += val; info[node] += val; return; } int mid = (start + end) >> 1; if (info[node] != 0) { update((node << 1), start, mid, start, mid, info[node]); update(((node << 1) | 1), mid + 1, end, mid + 1, end, info[node]); info[node] = 0; } update((node << 1), start, mid, i, j, val); update(((node << 1) | 1), mid + 1, end, i, j, val); tree[node] = max(tree[(node << 1)], tree[((node << 1) | 1)]); } int query(int node, int start, int end, int i, int j) { if (end < i || j < start) return INT_MIN; if (i <= start && end <= j) { return tree[node]; } int mid = (start + end) >> 1; if (info[node] != 0) { update((node << 1), start, mid, start, mid, info[node]); update(((node << 1) | 1), mid + 1, end, mid + 1, end, info[node]); info[node] = 0; } return max(query((node << 1), start, mid, i, j), query(((node << 1) | 1), mid + 1, end, i, j)); } int main() { int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) { scanf( %d , &nums[i]); pre[i] = cur[nums[i]]; cur[nums[i]] = i; } for (int i = 1; i <= k; i++) { build(1, 1, n, i - 1); for (int j = i; j <= n; j++) { update(1, 1, n, pre[j] + 1, j, 1); dp[i][j] = query(1, 1, n, 1, j); } } cout << dp[k][n] << endl; }
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-13; const long double PI = acos(-1); const int INF = (int)1e9; const long long INFF = (long long)1e18; const int mod = (int)1e9 + 7; const int MXN = (int)2e5 + 7; char s[MXN]; int cnt[MXN]; int num[MXN], num2[MXN], a[MXN]; bool check() { for (int i = 0; i < 1 << 6; i++) num2[i] = num[i]; for (int i = 0; i < 6; i++) { for (int j = 0; j < 1 << 6; j++) { if (j & (1 << i)) num2[j] += num2[j ^ (1 << i)]; } } for (int i = 0; i < 1 << 6; i++) { int sum = 0; for (int j = 0; j < 6; j++) if (i & (1 << j)) sum += cnt[j]; if (sum < num2[i]) return false; } return true; } char ans[MXN]; int main() { scanf( %s , s + 1); int l = strlen(s + 1); for (int i = 1; s[i]; i++) { cnt[s[i] - a ]++; a[i] = (1 << 6) - 1; } int m; scanf( %d , &m); while (m--) { int p; scanf( %d %s , &p, s + 1); a[p] = 0; for (int i = 1; s[i]; i++) a[p] ^= (1 << (s[i] - a )); } for (int i = 1; i <= l; i++) { num[a[i]]++; } for (int i = 1; i <= l; i++) { num[a[i]]--; for (int j = 0; j < 6; j++) { if (!cnt[j] || !(a[i] & (1 << j))) continue; cnt[j]--; if (check()) { ans[i] = j + a ; break; } else { cnt[j]++; } } if (!ans[i]) { puts( Impossible ); return 0; } } printf( %s n , ans + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 3 * 1e18; long long mi[5], ma[5], low[5], high[5]; long long resx, resy, resz; long long div2(long long x, long long y) { if (x > 0 && y > 0 || x < 0 && y < 0) { long long f = 0; if (x % 2 && y % 2) f = 1; if (x > 0 && y > 0) return x / 2 + y / 2 + f; else return x / 2 + y / 2 - f; } else return (x + y) / 2; } void update(long long s, long long d) { resy = div2(s, d); resz = div2(s, -d); } bool check(long long x) { for (int i = 1; i <= 4; i++) { low[i] = ma[i] - x; high[i] = mi[i] + x; if (low[i] > high[i]) return false; } long long x1 = div2(low[1], -high[2]); long long y1 = div2(high[1], -low[2]); long long x2 = div2(low[3], -high[4]); long long y2 = div2(high[3], -low[4]); long long x3 = max(x1, x2); long long y3 = min(y1, y2); if (x3 > y3) return false; for (long long i = x3; i <= y3; i++) { resx = i; long long s1 = max(low[1] - i, low[2] + i); long long s2 = min(high[1] - i, high[2] + i); long long d1 = max(low[3] - i, low[4] + i); long long d2 = min(high[3] - i, high[4] + i); if (s1 > s2 || d1 > d2) continue; if (s1 < s2) { if ((s1 & 1) == (d1 & 1)) update(s1, d1); else update(s1 + 1, d1); return true; } else if (d1 < d2) { if ((s1 & 1) == (d1 & 1)) update(s1, d1); else update(s1, d1 + 1); return true; } else { if ((s1 & 1) == (d1 & 1)) { update(s1, d1); return true; } } } return false; } int main() { int T; cin >> T; while (T--) { int n; scanf( %d , &n); for (int i = 1; i <= 4; i++) { mi[i] = inf; ma[i] = -inf; } for (int i = 0; i < n; i++) { long long x, y, z; scanf( %I64d%I64d%I64d , &x, &y, &z); mi[1] = min(mi[1], x + y + z); ma[1] = max(ma[1], x + y + z); mi[2] = min(mi[2], -x + y + z); ma[2] = max(ma[2], -x + y + z); mi[3] = min(mi[3], x + y - z); ma[3] = max(ma[3], x + y - z); mi[4] = min(mi[4], -x + y - z); ma[4] = max(ma[4], -x + y - z); } long long L = -1, R = inf; while (R - L > 1) { long long M = (L + R) >> 1; if (check(M)) R = M; else L = M; } check(R); printf( %I64d %I64d %I64d n , resx, resy, resz); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long int n, i; cin >> n; long int a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); long long int sum = 0, j = 0; for (i = 0, j = n - 1; i < j; i++, j--) { sum = sum + ((a[i] + a[j]) * (a[i] + a[j])); } cout << sum; return 0; }
|
#include <bits/stdc++.h> using namespace std; int64_t dfs(int64_t idx, int64_t p, vector<vector<int64_t>>& g, vector<int64_t>& parents, int64_t& c1, int64_t& c2) { int64_t n = g.size() - 1; parents[idx] = p; int64_t res = 1; int64_t mx = 0; for (auto& x : g[idx]) { if (x != p) { int64_t a = dfs(x, idx, g, parents, c1, c2); res += a; mx = max(mx, a); } } mx = max(mx, n - res); if (mx <= n / 2) { if (c1 == -1) { c1 = idx; } else { c2 = idx; } } return res; } int64_t leaf(int64_t idx, int64_t p, vector<vector<int64_t>>& g) { if (g[idx].size() == 1) { return idx; } else { auto res = -1; for (auto& e : g[idx]) { if (e != p) { res = leaf(e, idx, g); if (res != -1) { return res; } } } } return -1; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int64_t tc; cin >> tc; while (tc--) { int64_t n; cin >> n; vector<vector<int64_t>> g(n + 1); for (int64_t i = 0; i < n - 1; i++) { int64_t a; int64_t b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } int64_t c1 = -1; int64_t c2 = -1; vector<int64_t> p(n + 1); dfs(1, 0, g, p, c1, c2); if (c2 == -1) { int64_t rm = g[c1][0]; cout << c1 << << rm << endl; cout << c1 << << rm << endl; } else { if (p[c2] != c1) { swap(c1, c2); } int64_t rm = leaf(c2, c1, g); cout << rm << << p[rm] << endl; cout << rm << << c1 << endl; } } return 0; }
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_MUX4SEL_0 (
dout
);
output wire [32-1 : 0] dout;
xlconstant #(
.CONST_VAL(32'd2500),
.CONST_WIDTH(32)
) inst (
.dout(dout)
);
endmodule
|
module system_pll(REFERENCECLK,
PLLOUTCORE,
PLLOUTGLOBAL,
RESET);
input REFERENCECLK;
input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
output PLLOUTCORE;
output PLLOUTGLOBAL;
SB_PLL40_CORE system_pll_inst(.REFERENCECLK(REFERENCECLK),
.PLLOUTCORE(PLLOUTCORE),
.PLLOUTGLOBAL(PLLOUTGLOBAL),
.EXTFEEDBACK(),
.DYNAMICDELAY(),
.RESETB(RESET),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(),
.SDI(),
.SDO(),
.SCLK());
//\\ Fin=12, Fout=66;
defparam system_pll_inst.DIVR = 4'b0000;
defparam system_pll_inst.DIVF = 7'b1010111;
defparam system_pll_inst.DIVQ = 3'b100;
defparam system_pll_inst.FILTER_RANGE = 3'b001;
defparam system_pll_inst.FEEDBACK_PATH = "SIMPLE";
defparam system_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
defparam system_pll_inst.FDA_FEEDBACK = 4'b0000;
defparam system_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
defparam system_pll_inst.FDA_RELATIVE = 4'b0000;
defparam system_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
defparam system_pll_inst.PLLOUT_SELECT = "GENCLK";
defparam system_pll_inst.ENABLE_ICEGATE = 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NOR2_PP_SYMBOL_V
/**
* nor2: 2-input NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, m, k, w; char ax[500005]; char bx[500005]; int Next[500005], next2[500005]; int sig[500005][2]; int hh[500005][2]; bool tepan() { int i, j, a, b; for (i = 1; i <= n; i++) { if (sig[i][0] == m) { w = max(1, i - k + 1); w = min(w, n - 2 * k + 1); return 1; } } return 0; } void kmp() { int i, j = 0, a, b; for (i = 2; i <= m; i++) { while (j && bx[i] != bx[j + 1]) j = Next[j]; if (bx[i] == bx[j + 1]) j++; Next[i] = j; } j = 0; for (i = 1; i <= n; i++) { while (j && ax[i] != bx[j + 1]) j = Next[j]; if (bx[j + 1] == ax[i]) j++; sig[i][0] = j; } next2[m + 1] = m + 1; next2[m] = m + 1; j = m + 1; for (i = m - 1; i; i--) { while (j != m + 1 && bx[i] != bx[j - 1]) j = next2[j]; if (bx[i] == bx[j - 1]) j--; next2[i] = j; } j = m + 1; for (i = n; i; i--) { while (j != m + 1 && ax[i] != bx[j - 1]) j = next2[j]; if (bx[j - 1] == ax[i]) j--; sig[i][1] = j; } } int main() { scanf( %d%d%d , &n, &m, &k); int i, j, a, b; scanf( %s%s , ax + 1, bx + 1); kmp(); if (k >= m && tepan()) { printf( Yes n%d %d , w, n - k + 1); return 0; } for (i = 1; i <= n - k + 1; i++) hh[sig[i][1]][1] = i; for (i = n; i >= k; i--) hh[sig[i][0]][0] = i; for (i = n; i; i--) { if (hh[i][0]) hh[Next[i]][0] = min(hh[Next[i]][0], hh[i][0]); } for (i = 1; i <= n; i++) if (hh[i][1]) hh[next2[i]][1] = max(hh[next2[i]][1], hh[i][1]); int x; if (k >= m) x = m; else x = k + 1; for (i = 1; i < x; i++) { if (m - i > k) continue; j = 1 + i; if (hh[i][0] && hh[j][1] && hh[i][0] < hh[j][1]) { printf( Yes n%d %d , hh[i][0] - k + 1, hh[j][1]); return 0; } } printf( No ); return 0; }
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_wr_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 write requests from 4 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_wr_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_ack1,
prt_ack2,
prt_ack3,
prt_ack4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack1 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack2 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack3 = 1'b1;
// state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
if(prt_ack)begin
prt_ack4 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_ack_low:begin
state = wait_ack_low;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, ans = -1; cin >> n; int a[n], l[n], r[n]; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0, des = 0; i < n; ++i) { ++des; l[i] = des = min(des, a[i]); } for (int i = n - 1, des = 0; i >= 0; --i) { ++des; r[i] = des = min(des, a[i]); } for (int i = 0; i < n; ++i) ans = max(ans, min(l[i], r[i])); cout << ans << endl; }
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ()
// sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Implements a fixed-point parameterized pipelined square root
// operation on an unsigned input of any bit length. The number of
// stages in the pipeline is equal to the number of output bits in the
// computation. This pipelien sustains a throughput of one computation
// per clock cycle.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module sqrt_pipelined
(
input clk, // clock
input reset_n, // asynchronous reset
input start, // optional start signal
input [INPUT_BITS-1:0] radicand, // unsigned radicand
output reg data_valid, // optional data valid signal
output reg [OUTPUT_BITS-1:0] root // unsigned root
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
INPUT_BITS = 16; // number of input bits (any integer)
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits
reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation
reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values
reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values
wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values
// This is the first stage of the pipeline.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
start_gen[0] <= 0;
radicand_gen[INPUT_BITS-1:0] <= 0;
root_gen[INPUT_BITS-1:0] <= 0;
end
else begin
start_gen[0] <= start;
if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin
radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];
root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];
end
else begin
radicand_gen[INPUT_BITS-1:0] <= radicand;
root_gen[INPUT_BITS-1:0] <= 0;
end
end
end
// Main generate loop to create the masks and pipeline stages.
generate
genvar i;
// Generate all the mask values. These are built up in the
// following fashion:
// LAST MASK: 0x00...001
// 0x00...004 Increasing # OUTPUT_BITS
// 0x00...010 |
// 0x00...040 v
// ...
// FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS
//
// Note that the first mask used can either be of the 0x1... or
// 0x4... variety. This is purely determined by the number of
// computation stages. However, the last mask used will always be
// 0x1 and the second to last mask used will always be 0x4.
for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4
if (i % 2) // i is odd, this is a 4 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);
else // i is even, this is a 1 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);
end
// Generate all the pipeline stages to compute the square root of
// the input radicand stream. The general approach is to compare
// the current values of the root plus the mask to the
// radicand. If root/mask sum is greater than the radicand,
// subtract the mask and the root from the radicand and store the
// radicand for the next stage. Additionally, the root is
// increased by the value of the mask and stored for the next
// stage. If this test fails, then the radicand and the root
// retain their value through to the next stage. The one weird
// thing is that the mask indices appear to be incremented by one
// additional position. This is not the case, however, because the
// first mask is used in the first stage (always block after the
// generate statement).
for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline
always @ (posedge clk or negedge reset_n) begin : pipeline_stage
if (!reset_n) begin
start_gen[i+1] <= 0;
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
end
else begin
start_gen[i+1] <= start_gen[i];
if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] -
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] -
root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];
end
else begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;
end
end
end
end
endgenerate
// This is the final stage which just implements a rounding
// operation. This stage could be tacked on as a combinational logic
// stage, but who cares about latency, anyway? This is NOT a true
// rounding stage. In order to add convergent rounding, you need to
// increase the input bit width by 2 (increase the number of
// pipeline stages by 1) and implement rounding in the module that
// instantiates this one.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
data_valid <= 0;
root <= 0;
end
else begin
data_valid <= start_gen[OUTPUT_BITS-1];
if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;
else
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct rangeincrease { int l, r; }; rangeincrease actions[100001]; rangeincrease inprogress[100001]; int actionL = 0; int nums[100001]; int opened = 0; int main() { int n; int i; cin >> n; for (i = 1; i <= n; i++) { cin >> nums[i]; } for (i = 1; i <= n; i++) { while (nums[i] > opened) { opened++; inprogress[opened].l = i; } while (nums[i] < opened) { inprogress[opened].r = i - 1; actionL++; actions[actionL].l = inprogress[opened].l; actions[actionL].r = inprogress[opened].r; opened--; } } while (opened > 0) { inprogress[opened].r = n; actionL++; actions[actionL].l = inprogress[opened].l; actions[actionL].r = inprogress[opened].r; opened--; } cout << actionL << endl; for (i = 1; i <= actionL; i++) { cout << actions[i].l << << actions[i].r << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long st = 1, mod = 998244353; int n; cin >> n; vector<long long> ans(n + 1); ans[n] = 10; ans[n - 1] = 20; for (int i = n - 2; i >= 1; i--) { ans[i] = ans[i + 1] + 9; } for (int i = n - 1; i >= 1; i--) { ans[i] = ((ans[i] * 9) % mod * st) % mod; st = (10 * st) % mod; } for (int i = 1; i <= n; i++) cout << ans[i] << ; cout << endl; } int main() { ios_base::sync_with_stdio(false); solve(); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 08/13/2017 11:49:08 AM
// Design Name:
// Module Name: VICTIM_CACHE
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module VICTIM_CACHE #(
parameter BLOCK_WIDTH = 512 ,
parameter TAG_WIDTH = 26 ,
parameter MEMORY_LATENCY = "HIGH_LATENCY" ,
localparam MEMORY_DEPTH = 4 ,
localparam ADDRESS_WIDTH = clog2(MEMORY_DEPTH-1)
) (
input CLK ,
input [TAG_WIDTH - 1 : 0] WRITE_TAG_ADDRESS ,
input [BLOCK_WIDTH - 1 : 0] WRITE_DATA ,
input WRITE_ENABLE ,
input [TAG_WIDTH - 1 : 0] READ_TAG_ADDRESS ,
input READ_ENBLE ,
output READ_HIT ,
output [BLOCK_WIDTH - 1 : 0] READ_DATA
);
reg [TAG_WIDTH - 1 : 0] tag [MEMORY_DEPTH - 1 : 0] ;
reg [BLOCK_WIDTH - 1 : 0] memory [MEMORY_DEPTH - 1 : 0] ;
reg valid [MEMORY_DEPTH - 1 : 0] ;
reg read_hit_out_reg_1 ;
reg [BLOCK_WIDTH - 1 : 0] data_out_reg_1 ;
reg [ADDRESS_WIDTH - 1 : 0] record_counter ;
wire full ;
wire empty ;
assign full = ( record_counter == (MEMORY_DEPTH - 1) ) ;
assign empty = ( record_counter == 0 ) ;
integer i;
initial
begin
for (i = 0; i < MEMORY_DEPTH; i = i + 1)
tag [ i ] = {TAG_WIDTH{1'b0}};
for (i = 0; i < MEMORY_DEPTH; i = i + 1)
memory [ i ] = {BLOCK_WIDTH{1'b0}};
for (i = 0; i < MEMORY_DEPTH; i = i + 1)
valid [ i ] = 1'b0;
record_counter = {ADDRESS_WIDTH{1'b0}} ;
read_hit_out_reg_1 = 1'b0 ;
data_out_reg_1 = {BLOCK_WIDTH{1'b0}} ;
end
always @(posedge CLK)
begin
if (WRITE_ENABLE & !full)
begin
tag [ record_counter ] <= WRITE_TAG_ADDRESS ;
memory [ record_counter ] <= WRITE_DATA ;
valid [ record_counter ] <= 1'b1 ;
record_counter <= record_counter + 1 ;
end
if (WRITE_ENABLE & full)
begin
for (i = 0; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
valid [ i ] <= valid [ i + 1 ] ;
end
tag [ record_counter ] <= WRITE_TAG_ADDRESS ;
memory [ record_counter ] <= WRITE_DATA ;
valid [ record_counter ] <= 1'b1 ;
end
if (READ_ENBLE & !empty)
begin
if( (tag [ 0 ] == READ_TAG_ADDRESS) & valid [ 0 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 0 ] ;
record_counter <= record_counter - 1 ;
for (i = 0; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else if( (tag [ 1 ] == READ_TAG_ADDRESS) & valid [ 1 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 1 ] ;
record_counter <= record_counter - 1 ;
for (i = 1; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else if( (tag [ 2 ] == READ_TAG_ADDRESS) & valid [ 2 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 2 ] ;
record_counter <= record_counter - 1 ;
for (i = 2; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else if( (tag [ 3 ] == READ_TAG_ADDRESS) & valid [ 3 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 3 ] ;
record_counter <= record_counter - 1 ;
for (i = 3; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else
begin
read_hit_out_reg_1 <= 1'b0 ;
data_out_reg_1 <= {BLOCK_WIDTH{1'b0}} ;
end
end
if (READ_ENBLE & empty)
begin
read_hit_out_reg_1 <= 1'b0 ;
data_out_reg_1 <= {BLOCK_WIDTH{1'b0}} ;
end
end
generate
if (MEMORY_LATENCY == "LOW_LATENCY")
begin
assign READ_HIT = read_hit_out_reg_1 ;
assign READ_DATA = data_out_reg_1 ;
end
else
begin
reg read_hit_out_reg_2 = 1'b0 ;
reg [BLOCK_WIDTH - 1 :0] data_out_reg_2 = {BLOCK_WIDTH{1'b0}} ;
initial
begin
read_hit_out_reg_2 <= 1'b0 ;
data_out_reg_2 <= {BLOCK_WIDTH{1'b0}} ;
end
always @(posedge CLK)
begin
if (READ_ENBLE)
begin
read_hit_out_reg_2 <= read_hit_out_reg_1 ;
data_out_reg_2 <= data_out_reg_1 ;
end
end
assign READ_HIT = read_hit_out_reg_2 ;
assign READ_DATA = data_out_reg_2 ;
end
endgenerate
function integer clog2;
input integer depth;
for (clog2 = 0; depth > 0; clog2 = clog2 + 1)
depth = depth >> 1;
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t;
typedef logic [3:0] mc_t;
typedef mc_t tocast_t;
typedef struct packed {
logic [15:0] data;
} packed_t;
packed_t pdata;
assign pdata.data = 16'h1234;
logic [7:0] logic8bit;
assign logic8bit = $bits(logic8bit)'(pdata >> 8);
mc_t o;
logic [15:0] allones = 16'hffff;
parameter FOUR = 4;
// bug925
localparam [6:0] RESULT = 7'((6*9+92)%96);
logic signed [14:0] samp0 = 15'h0000;
logic signed [14:0] samp1 = 15'h0000;
logic signed [14:0] samp2 = 15'h6000;
logic signed [11:0] coeff0 = 12'h009;
logic signed [11:0] coeff1 = 12'h280;
logic signed [11:0] coeff2 = 12'h4C5;
logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11));
// verilator lint_off WIDTH
logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11));
// verilator lint_on WIDTH
logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector
(27'(coeff1 * samp1) >>> 11) +
(27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings
initial begin
if (logic8bit != 8'h12) $stop;
if (4'shf > 4'sh0) $stop;
if (signed'(4'hf) > 4'sh0) $stop;
if (4'hf < 4'h0) $stop;
if (unsigned'(4'shf) < 4'h0) $stop;
if (4'(allones) !== 4'hf) $stop;
if (6'(allones) !== 6'h3f) $stop;
if ((4)'(allones) !== 4'hf) $stop;
if ((4+2)'(allones) !== 6'h3f) $stop;
if ((4-2)'(allones) !== 2'h3) $stop;
if ((FOUR+2)'(allones) !== 6'h3f) $stop;
if (50 !== RESULT) $stop;
o = tocast_t'(4'b1);
if (o != 4'b1) $stop;
if (15'h6cec != outa) $stop;
if (27'h7ffecec != mida) $stop;
if (27'h7ffecec != midb) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// Copyright (c) 2015 CERN
// @author Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for variable initialization.
module vhdl_var_init_test;
logic init;
logic [7:0] slv;
bit b;
int i;
vhdl_var_init dut(init, slv, b, i);
initial begin
init = 0;
#1 init = 1;
#1;
if(slv !== 8'b01000010) begin
$display("FAILED 1");
$finish();
end
if(b !== false) begin
$display("FAILED 2");
$finish();
end
if(i !== 42) begin
$display("FAILED 3");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline string toString(T a) { ostringstream os( ); os << a; return os.str(); } template <typename T> inline long long toLong(T a) { long long res; istringstream os(a); os >> res; return res; } template <typename T> inline int toInt(T a) { int res; istringstream os(a); os >> res; return res; } template <typename T> inline double toDouble(T a) { double res; istringstream os(a); os >> res; return res; } template <typename T> inline T SQ(T a) { return a * a; } template <typename T> inline T GCD(T a, T b) { if (b == 0) return a; else return GCD(b, a % b); } template <typename T> inline T LCM(T a, T b) { long long res = a * b; res /= GCD(a, b); return res; } template <typename T> inline unsigned long long BIGMOD(T a, T b, T m) { if (b == 0) return 1; else if (b % 2 == 0) return SQ(BIGMOD(a, b / 2, m)) % m; else return (a % m * BIGMOD(a, b - 1, m)) % m; } template <typename T> inline vector<string> PARSE(T str) { vector<string> res; string s; istringstream os(str); while (os >> s) res.push_back(s); return res; } template <typename T> inline unsigned long long DIST(T A, T B) { unsigned long long res = (A.x - B.x) * (A.x - B.x) + (A.y - B.y) * (A.y - B.y); return res; } template <typename T> inline long long CROSS(T A, T B, T C) { return (B.x - A.x) * (C.y - A.y) - (C.x - A.x) * (B.y - A.y); } template <typename T> inline double cosAngle(T a, T b, T c) { double res = a * a + b * b - c * c; res = res / (2 * a * b); res = acos(res); return res; } template <typename T> inline T POWER(T base, int po) { T res = 1; if (base == 0) return 0; for (int i = (0); i < (po); i++) res *= base; return res; } template <typename T> inline bool IS_ON(T mask, T pos) { return mask & (1 << pos); } template <typename T> inline int OFF(T mask, T pos) { return mask ^ (1 << pos); } template <typename T> inline int ON(T mask, T pos) { return mask | (1 << pos); } template <typename T> inline bool INSIDE_GRID(int R, int C, int ro, int clm) { if (R >= 0 && C >= 0 && R < ro && C < clm) return 1; return 0; } template <typename T> inline void PRINT_GRID(T GRID, int ro, int clm) { cout << GRID << : << GRID << endl; for (int i = (0); i < (ro); i++) { for (int j = (0); j < (clm); j++) cout << GRID[i][j] << ; puts( ); } } long long arr[500005]; vector<pair<long long, int> > inp; int main() { ios_base::sync_with_stdio(0); cin.tie(); ; int n; cin >> n; for (int i = (0); i < (n); i++) { cin >> arr[i]; inp.push_back(make_pair(arr[i], i)); } sort((inp).begin(), (inp).end()); long long hell = 0; for (int i = (0); i < (n); i++) { hell = max(inp[i].first, hell + 1); arr[inp[i].second] = hell; } for (int i = (0); i < (n); i++) cout << arr[i] << ; return 0; }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* The internal logic cell simulation library.
*
* This Verilog library contains simple simulation models for the internal
* logic cells (_NOT_, _AND_, ...) that are generated by the default technology
* mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
*
*/
module _NOT_(A, Y);
input A;
output Y;
assign Y = ~A;
endmodule
module _AND_(A, B, Y);
input A, B;
output Y;
assign Y = A & B;
endmodule
module _OR_(A, B, Y);
input A, B;
output Y;
assign Y = A | B;
endmodule
module _XOR_(A, B, Y);
input A, B;
output Y;
assign Y = A ^ B;
endmodule
module _MUX_(A, B, S, Y);
input A, B, S;
output reg Y;
always @* begin
if (S)
Y = B;
else
Y = A;
end
endmodule
module _DFF_N_(D, Q, C);
input D, C;
output reg Q;
always @(negedge C) begin
Q <= D;
end
endmodule
module _DFF_P_(D, Q, C);
input D, C;
output reg Q;
always @(posedge C) begin
Q <= D;
end
endmodule
module _DFF_NN0_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
endmodule
module _DFF_NN1_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
endmodule
module _DFF_NP0_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
endmodule
module _DFF_NP1_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module _DFF_PN0_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
endmodule
module _DFF_PN1_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
endmodule
module _DFF_PP0_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
endmodule
module _DFF_PP1_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
endmodule
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`include "consts.vh"
module control_processor (
input clk,
input reset,
input stall,
input [31:0] inst,
input [31:0] pc,
input enable,
output reg [31:0] pcr_data,
input [31:0] pcr_write_data,
input [4:0] pcr,
input [1:0] cmd,
output interrupt,
output reg [31:0] ptbr,
output reg [31:0] evec,
output vm_enable,
output flush_tlb
);
wire [2:0] command = {1'b0, cmd};
wire [11:0] imm12 = inst[21:10];
wire [31:0] sext_imm = imm12[11] ? {20'hFFFFF, imm12} : {20'b0, imm12};
reg [23:0] status; /* top 8 bits are IP */
reg [7:0] interrupts_pending;
reg [31:0] epc;
reg [31:0] badvaddr;
/* evec */
reg [31:0] count;
reg [31:0] compare;
reg [31:0] cause;
/* ptbr */
reg [31:0] k0;
reg [31:0] k1;
reg [31:0] tohost;
reg [31:0] fromhost;
/* Upon reset, only the supervisor bit is set. S64 and U64 are hard-wired
* to zero, as are EC, EV, and EF. */
localparam SR_WRITE_MASK = (`SR_IM | `SR_VM | `SR_S | `SR_PS | `SR_ET);
reg [31:0] write_data;
always @ (*) begin
if (!stall && enable)
case (command)
`F3_MTPCR: write_data = pcr_write_data;
`F3_SETPCR: write_data = pcr_data | sext_imm;
`F3_CLEARPCR: write_data = pcr_data | ~(sext_imm);
default: write_data = 32'b0;
endcase
end
always @ (posedge clk) begin
if (reset)
interrupts_pending <= 8'b0;
if (reset)
status <= (`SR_S);
else if (!stall && enable && pcr == `PCR_STATUS)
status <= write_data & SR_WRITE_MASK;
if (reset)
epc <= 32'h0;
else if (!stall && enable && pcr == `PCR_EPC)
epc <= write_data;
else if (interrupt)
epc <= pc;
if (reset)
badvaddr <= 32'h0;
if (reset)
evec <= 32'h0;
else if (!stall && enable && pcr == `PCR_EVEC)
evec <= write_data & 32'hFFFFFFFC;
if (reset)
count <= 32'h0;
else if (!stall && enable && pcr == `PCR_COUNT)
count <= write_data;
if (reset) begin
compare <= 32'h0;
end else if (!stall && enable && pcr == `PCR_COMPARE) begin
compare <= write_data;
interrupts_pending[`IRQ_TIMER] = 0;
end
if (reset)
cause <= 32'h0;
if (reset)
ptbr <= 32'h0;
else if (!stall && enable && pcr == `PCR_PTBR)
ptbr <= write_data;
if (reset)
k0 <= 32'h0;
else if (!stall && enable && pcr == `PCR_K0)
k0 <= write_data;
if (reset)
k1 <= 32'h0;
else if (!stall && enable && pcr == `PCR_K1)
k1 <= write_data;
if (reset)
tohost <= 32'h0;
else if (!stall && enable && pcr == `PCR_TOHOST)
tohost <= write_data;
if (reset)
fromhost <= 32'h0;
else if (!stall && enable && pcr == `PCR_FROMHOST)
fromhost <= write_data;
end
/* The old value of a PCR is returned on a write */
always @ (*) begin
if (enable)
case (pcr)
`PCR_STATUS: pcr_data = {interrupts_pending, status};
`PCR_EPC: pcr_data = epc;
`PCR_BADVADDR: pcr_data = badvaddr;
`PCR_EVEC: pcr_data = evec;
`PCR_COUNT: pcr_data = count;
`PCR_COMPARE: pcr_data = compare;
`PCR_PTBR: pcr_data = ptbr;
`PCR_K0: pcr_data = k0;
`PCR_K1: pcr_data = k1;
`PCR_TOHOST: pcr_data = tohost;
`PCR_FROMHOST: pcr_data = fromhost;
default: pcr_data = 32'h0;
endcase
else
pcr_data = 32'h0;
end
/* Timer interrupt */
always @ (posedge clk) begin
count <= count + 1;
end
always @ (*) begin
if (count == compare)
interrupts_pending[`IRQ_TIMER] = 1;
end
wire interrupt_mask = status[23:16];
assign interrupt = ((status & `SR_ET) && (interrupt_mask & interrupts_pending));
/* Virtual memory */
assign flush_tlb = (!stall && enable && pcr == `PCR_PTBR);
assign vm_enable = status[8];
endmodule
|
#include<iostream> using namespace std; int main() { int t; cin>>t; while(t--){ int a,b; cin>>a>>b; if(a==0&&b==0) cout<< 0 n ; else if(a==0&&b!=0) cout<<2*b-1<<endl; else if(a!=0&&b==0) cout<<2*a-1<<endl; else{ if(a>b){ int x=(2*b)+(2*(a-b)-1); cout<<x<<endl; } else if(a<b){ int x=(2*a)+(2*(b-a)-1); cout<<x<<endl; } else if(a==b) cout<<2*a<<endl; } } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:18:58 01/29/2016
// Design Name:
// Module Name: latch_EX_MEM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module latch_EX_MEM
#(
parameter B=32, W=5
)
(
input wire clk,
input wire reset,
inout wire ena,
/* Data signals INPUTS */
//input wire [B-1:0] add_result_in,
input wire [B-1:0] alu_result_in,
input wire [B-1:0] r_data2_in,
input wire [W-1:0] mux_RegDst_in,
//input wire [B-1:0] pc_jump_in,
/* Data signals OUTPUTS */
//output wire [B-1:0]add_result_out,
output wire [B-1:0]alu_result_out,
output wire [B-1:0]r_data2_out,
output wire [W-1:0]mux_RegDst_out,
//output wire [B-1:0] pc_jump_out,
/* Control signals INPUTS*/
//input wire zero_in,
//Write back
input wire wb_RegWrite_in,
input wire wb_MemtoReg_in,
//Memory
//input wire m_Jump_in,
//input wire m_Branch_in,
//input wire m_BranchNot_in,
//input wire m_MemRead_in,
input wire m_MemWrite_in,
//Other
input [5:0] opcode_in,
/* Control signals OUTPUTS */
//output wire zero_out,
//Write back
output wire wb_RegWrite_out,
output wire wb_MemtoReg_out,
//Memory
//output wire m_Jump_out,
//output wire m_Branch_out,
//output wire m_BranchNot_out,
//output wire m_MemRead_out,
output wire m_MemWrite_out,
//Other
output wire [5:0] opcode_out
);
/* Data REGISTERS */
//reg [B-1:0] add_result_reg;
reg [B-1:0] alu_result_reg;
reg [B-1:0] r_data2_reg;
reg [W-1:0] mux_RegDst_reg;
//reg [B-1:0] pc_jump_reg;
/* Control REGISTERS */
//reg zero_reg;
//Write back
reg wb_RegWrite_reg;
reg wb_MemtoReg_reg;
//Memory
//reg m_Jump_reg;
//reg m_Branch_reg;
//reg m_BranchNot_reg;
//reg m_MemRead_reg;
reg m_MemWrite_reg;
//other
reg [5:0] opcode_reg;
always @(posedge clk)
begin
if (reset)
begin
//add_result_reg <= 0;
alu_result_reg <= 0;
r_data2_reg <= 0;
mux_RegDst_reg <= 0;
//pc_jump_reg <= 0;
//zero_reg <= 0;
wb_RegWrite_reg <= 0;
wb_MemtoReg_reg <= 0;
//m_Jump_reg <= 0;
//m_Branch_reg <= 0;
//m_BranchNot_reg <= 0;
//m_MemRead_reg <= 0;
m_MemWrite_reg <= 0;
opcode_reg <= 0;
end
else
if(ena==1'b1)
begin
/* Data signals write to ID_EX register */
//add_result_reg <= add_result_in;
alu_result_reg <= alu_result_in;
r_data2_reg <= r_data2_in;
mux_RegDst_reg <= mux_RegDst_in;
//pc_jump_reg <= pc_jump_in;
/* Control signals write to ID_EX register */
//zero_reg <= zero_in;
//Write back
wb_RegWrite_reg <= wb_RegWrite_in;
wb_MemtoReg_reg <= wb_MemtoReg_in;
//Memory
//m_Jump_reg <= m_Jump_in;
//m_Branch_reg <= m_Branch_in;
//m_BranchNot_reg <= m_BranchNot_in;
//m_MemRead_reg <= m_MemRead_in;
m_MemWrite_reg <= m_MemWrite_in;
//Other
opcode_reg <= opcode_in;
end
end
/* Data signals read from ID_EX register */
//assign add_result_out = add_result_reg;
assign alu_result_out = alu_result_reg;
assign r_data2_out = r_data2_reg;
assign mux_RegDst_out = mux_RegDst_reg;
//assign pc_jump_out = pc_jump_reg;
/* Control signals read from ID_EX register */
//assign zero_out = zero_reg;
//Write back
assign wb_RegWrite_out = wb_RegWrite_reg;
assign wb_MemtoReg_out = wb_MemtoReg_reg;
//Memory
//assign m_Jump_out = m_Jump_reg;
//assign m_Branch_out = m_Branch_reg;
//assign m_BranchNot_out = m_BranchNot_reg;
//assign m_MemRead_out = m_MemRead_reg;
assign m_MemWrite_out = m_MemWrite_reg;
assign opcode_out = opcode_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } string str; cin >> str; bool flag = 0; int start = 0; set<int> s; for (int i = 0; i < str.length(); i++) { if (!flag && str[i] == 0 && a[i] != i + 1) { cout << NO << endl; return 0; } if (flag && str[i] == 0 ) { s.insert(a[i]); for (int j = start; j <= i + 1; j++) { if (s.find(j) == s.end()) { cout << NO << endl; return 0; } } s.clear(); flag = 0; } if (str[i] == 1 ) { s.insert(a[i]); if (!flag) { start = i + 1; } flag = 1; } } cout << YES << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_TB_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_TB_V
/**
* lpflow_inputisolatch: Latching input isolator with inverted enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_inputisolatch.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SLEEP_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SLEEP_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP_B = 1'bx;
#600 D = 1'bx;
end
sky130_fd_sc_hd__lpflow_inputisolatch dut (.D(D), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_TB_V
|
#include <bits/stdc++.h> using namespace std; const int mxn = 2000; int x[mxn]; int main() { int n, a, b; cin >> n >> a >> b; for (int(i) = (0); (i) < (n); (i)++) cin >> x[i]; sort(x, x + n); cout << x[n - a] - x[n - a - 1]; }
|
#include <bits/stdc++.h> using namespace std; using namespace std; const int N = 1e6 + 100; const int inf = 1e9 + 100; int n, w, m, a[N], seg[N << 2]; long long fen[N]; void change(int dex, int val, int v = 1, int s = 0, int e = N) { if (dex < s || e <= dex) { return; } if (e - s == 1) { seg[v] = val; return; } int mid = (s + e) >> 1, lc = v << 1, rc = lc | 1; change(dex, val, lc, s, mid); change(dex, val, rc, mid, e); seg[v] = max(seg[lc], seg[rc]); } int get_max(int l, int r, int v = 1, int s = 0, int e = N) { if (r <= s || e <= l) return -inf; if (l <= s && e <= r) return seg[v]; int mid = (s + e) >> 1, lc = v << 1, rc = lc | 1; return max(get_max(l, r, lc, s, mid), get_max(l, r, rc, mid, e)); } void add(int dex, long long val) { for (++dex; dex < N; dex += dex & -dex) fen[dex] += val; } long long get(int dex) { long long res = 0; for (; dex; dex ^= dex & -dex) res += fen[dex]; return res; } void ADD(int l, int r, long long x) { add(l, x); add(r, -x); } void act(int i) { ADD(i, i + 1, max(i + m < w || i >= w ? 0 : -inf, get_max(i + m - w, i + 1))); } void get_line() { int maxi = 0; cin >> m; for (int i = 0; i < m; i++) { cin >> a[i]; change(i, a[i]); maxi = max(maxi, a[i]); } for (int i = 0; i < m; i++) { act(i); } for (int i = 0; i < m && w - i - 1 >= m; i++) { act(w - i - 1); } if (2 * m < w) { ADD(m, w - m, maxi); } for (int i = 0; i < m; i++) { change(i, 0); } } int main() { cin >> n >> w; for (int i = 0; i < n; i++) { get_line(); } for (int i = 0; i < w; i++) { cout << get(i + 1) << ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_2_V
`define SKY130_FD_SC_MS__FA_2_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_2_V
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// interrupt controller for Z80
module timer(
input wire clk_24mhz,
input wire clk_z80,
input wire [2:0] rate, // z80 clocked
// 3'b000 -- 37500/1
// 3'b001 -- 37500/2
// 3'b010 -- 37500/4
// 3'b011 -- 37500/8
// 3'b100 -- 37500/16
// 3'b101 -- 37500/64
// 3'b110 -- 37500/256
// 3'b111 -- 37500/1024
output reg int_stb
);
reg [ 2:0] ctr5;
reg [16:0] ctr128k;
reg ctrsel;
reg int_sync1,int_sync2,int_sync3;
always @(posedge clk_24mhz)
begin
if( !ctr5[2] )
ctr5 <= ctr5 + 3'd1;
else
ctr5 <= 3'd0;
end
//
initial
ctr128k = 'd0;
always @(posedge clk_24mhz)
begin
if( ctr5[2] )
ctr128k <= ctr128k + 17'd1;
end
always @*
case( rate )
3'b000: ctrsel = ctr128k[6];
3'b001: ctrsel = ctr128k[7];
3'b010: ctrsel = ctr128k[8];
3'b011: ctrsel = ctr128k[9];
3'b100: ctrsel = ctr128k[10];
3'b101: ctrsel = ctr128k[12];
3'b110: ctrsel = ctr128k[14];
3'b111: ctrsel = ctr128k[16];
endcase
// generate interrupt signal in clk_z80 domain
always @(posedge clk_z80)
begin
int_sync3 <= int_sync2;
int_sync2 <= int_sync1;
int_sync1 <= ctrsel;
end
always @(posedge clk_z80)
if( !int_sync2 && int_sync3 )
int_stb <= 1'b1;
else
int_stb <= 1'b0;
endmodule
|
`timescale 1 ns / 1 ps
module audio_direct_v1_1 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S_AXI
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 5
)
(
// Users to add ports here
input wire sel_direct,
input wire audio_in,
output wire audio_out,
output wire audio_shutdown,
output wire pdm_clk,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S_AXI
input wire s_axi_aclk,
input wire s_axi_aresetn,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] s_axi_awaddr,
input wire [2 : 0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [C_S_AXI_DATA_WIDTH-1 : 0] s_axi_wdata,
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [1 : 0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] s_axi_araddr,
input wire [2 : 0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [C_S_AXI_DATA_WIDTH-1 : 0] s_axi_rdata,
output wire [1 : 0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready
);
wire pdm_clk_o1, pdm_clk_o2;
wire audio_out_o1, audio_out_o2;
wire pwm_sdaudio_o1, pwm_sdaudio_o2;
wire pwm_audio_i, pwm_audio_o;
// Instantiation of Axi Bus Interface S_AXI
d_axi_pdm_v1_2_S_AXI # (
.C_S_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH)
) d_axi_pdm_v1_2_S_AXI_inst (
.pdm_m_clk_o(pdm_clk_o2),
.pdm_m_data_i(audio_in),
.pdm_lrsel_o(), // no connection required
.pwm_audio_t(audio_out_o2),
.pwm_sdaudio_o(pwm_sdaudio_o2),
.pwm_audio_o(pwm_audio_o),
.pwm_audio_i(pwm_audio_i),
.S_AXI_ACLK(s_axi_aclk),
.S_AXI_ARESETN(s_axi_aresetn),
.S_AXI_AWADDR(s_axi_awaddr),
.S_AXI_AWPROT(s_axi_awprot),
.S_AXI_AWVALID(s_axi_awvalid),
.S_AXI_AWREADY(s_axi_awready),
.S_AXI_WDATA(s_axi_wdata),
.S_AXI_WSTRB(s_axi_wstrb),
.S_AXI_WVALID(s_axi_wvalid),
.S_AXI_WREADY(s_axi_wready),
.S_AXI_BRESP(s_axi_bresp),
.S_AXI_BVALID(s_axi_bvalid),
.S_AXI_BREADY(s_axi_bready),
.S_AXI_ARADDR(s_axi_araddr),
.S_AXI_ARPROT(s_axi_arprot),
.S_AXI_ARVALID(s_axi_arvalid),
.S_AXI_ARREADY(s_axi_arready),
.S_AXI_RDATA(s_axi_rdata),
.S_AXI_RRESP(s_axi_rresp),
.S_AXI_RVALID(s_axi_rvalid),
.S_AXI_RREADY(s_axi_rready)
);
// Add user logic here
audio_direct_path audio_direct_path_inst(
.clk_i(s_axi_aclk),
.en_i(sel_direct),
.pdm_audio_i(audio_in),
.pdm_m_clk_o(pdm_clk_o1),
.pwm_audio_o(audio_out_o1),
.done_o(), // no connection required
.pwm_audio_shutdown(pwm_sdaudio_o1)
);
// User logic ends
assign pdm_clk = sel_direct ? pdm_clk_o1:pdm_clk_o2;
assign audio_shutdown = sel_direct ? pwm_sdaudio_o1:pwm_sdaudio_o2;
assign audio_out = sel_direct ? audio_out_o1:audio_out_o2; // audio_shutdown is negative logic
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isprime(long long n) { if (n == 1) return false; if (n == 2) return true; for (long long i = 2; i <= sqrt(n); i++) { if (n % i == 0) { return false; } } return true; } long long poww(long long b, long long e) { if (e == 0) return 1; else if (e % 2 == 0) { long long a = pow(b, e / 2); return a * a; } else { long long a = pow(b, e / 2); return b * a * a; } } long long powm(long long x, long long y, long long m = 1000000007) { x = x % m; long long res = 1; while (y) { if (y & 1) res = res * x; res %= m; y = y >> 1; x = x * x; x %= m; } return res; } long long modInverse(long long a, long long m = 1000000007) { return powm(a, m - 2, m); } void print(vector<long long> v) { for (long long i = 0; i < v.size(); i++) { cout << v[i] << ; } } void print(long long arr[]) { long long size = *(&arr + 1) - arr; for (long long i = 0; i < size; i++) { cout << arr[i] << ; } } string to_bin(long long n) { string res = ; long long i = 0; while (n > 0) { if (n % 2 == 1) { res = res + 1 ; } else { res = res + 0 ; } n /= 2; i++; } reverse(res.begin(), res.end()); return res; } long long to_dec(string second) { long long n = second.size(), ans = 0, temp = 1; for (long long i = n - 1; i >= 0; i--) { long long x = second[i] - 0 ; ans += x * temp; temp *= 2; } return ans; } void result(bool first) { if (first) cout << YES << endl; else cout << NO << endl; } void solve() { long long a, b, p; cin >> a >> b >> p; string second; cin >> second; reverse(second.begin(), second.end()); long long n = second.length(); long long ind = 1; long long maxi; for (long long i = 1; i < n; i++) { char ch = second[i]; if (second[i] == B ) { if (p >= b) { p -= b; if (i != n - 1) { while (second[i + 1] == B ) { i++; } } ind = i + 1; } else break; } else if (second[i] == A ) { if (p >= a) { p -= a; if (i != n - 1) { while (second[i + 1] == A ) { i++; } } ind = i + 1; } else break; } } long long ans = n - ind + 1; cout << ans << endl; } int32_t main() { ios_base::sync_with_stdio(); cin.tie(0); cout.tie(0); long long tests; cin >> tests; while (tests--) solve(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A2BB2OI_BLACKBOX_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; int n[t], sum = 0; for (int i = 0; i < t; i++) { cin >> n[i]; } for (int i = 0; i < t; i++) { if (n[i] % 2 == 0) { sum = (n[i] / 2) - 1; } else { sum = n[i] / 2; } cout << sum << endl; } }
|
`default_netype none
module memory_resource_controller #(
parameter P_MEM_ADDR_N = 22
)(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//IF0
input wire iIF0_ARBIT_REQ,
output wire oIF0_ARBIT_ACK,
input wire iIF0_ARBIT_FINISH,
input wire iIF0_ENA,
output wire oIF0_BUSY,
input wire iIF0_RW,
input wire [P_MEM_ADDR_N-1:0] iIF0_ADDR,
input wire [31:0] iIF0_DATA,
output wire oIF0_VALID,
input wire iIF0_BUSY,
output wire [31:0] oIF0_DATA,
//IF1
input wire iIF1_ARBIT_REQ,
output wire oIF1_ARBIT_ACK,
input wire iIF1_ARBIT_FINISH,
input wire iIF1_ENA,
output wire oIF1_BUSY,
input wire iIF1_RW,
input wire [P_MEM_ADDR_N-1:0] iIF1_ADDR,
input wire [31:0] iIF1_DATA,
output wire oIF1_VALID,
input wire iIF1_BUSY,
output wire [31:0] oIF1_DATA,
//Memory Controller
output wire oMEM_ENA,
input wire iMEM_BUSY,
output wire oMEM_RW,
output wire [P_MEM_ADDR_N-1:0] oMEM_ADDR,
output wire [31:0] oMEM_DATA,
input wire iMEM_VALID,
output wire oMEM_BUSY,
input wire [31:0] iMEM_DATA
);
localparam L_PARAM_STT_IDLE = 2'h0;
localparam L_PARAM_STT_ACK = 2'h1;
localparam L_PARAM_STT_WORK = 2'h2;
reg [1:0] b_state;
reg b_authority;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_STT_IDLE;
end
else if(iRESET_SYNC)begin
b_state <= L_PARAM_STT_IDLE;
end
else begin
case(b_state)
L_PARAM_STT_IDLE:
begin
if(iIF0_ARBIT_REQ || iIF1_ARBIT_REQ)begin
b_state <= L_PARAM_STT_ACK;
end
end
L_PARAM_STT_ACK:
begin
b_state <= L_PARAM_STT_WORK;
end
L_PARAM_STT_WORK:
begin
if(func_if_finish_check(b_authority, iIF0_ARBIT_FINISH, iIF1_ARBIT_FINISH))begin
b_state <= L_PARAM_STT_IDLE;
end
end
default:
begin
b_state <= L_PARAM_STT_IDLE;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_authority <= 1'b0;
end
else if(iRESET_SYNC)begin
b_authority <= 1'b0;
end
else begin
if(b_state == L_PARAM_STT_IDLE)begin
b_authority <= func_priority_encoder(b_authority, iIF0_ARBIT_REQ, iIF1_ARBIT_REQ);
end
end
end
function func_if_finish_check;
input func_now;
input func_if0_finish;
input func_if1_finish;
begin
if(!func_now && func_if0_finish)begin
func_if_finish_check = 1'b1;
end
else if(func_now && func_if1_finish)begin
func_if_finish_check = 1'b1;
end
else begin
func_if_finish_check = 1'b0;
end
end
endfunction
//Interface
function func_priority_encoder;
input func_now;
input func_if0_req;
input func_if1_req;
begin
case(func_now)
1'b0:
begin
if(func_if1_req)begin
func_priority_encoder = 1'b1;
end
else if(func_if0_req)begin
func_priority_encoder = 1'b0;
end
else begin
func_priority_encoder = 1'b0;
end
end
1'b1:
begin
if(func_if0_req)begin
func_priority_encoder = 1'b0;
end
else if(func_if1_req)begin
func_priority_encoder = 1'b1;
end
else begin
func_priority_encoder = 1'b0;
end
end
endcase
end
endfunction
reg b_if2mem_ena;
reg b_if2mem_rw;
reg [P_MEM_ADDR_N-1:0] b_if2mem_addr;
reg [31:0] b_if2mem_data;
reg b_mem2if0_valid;
reg [31:0] b_mem2if0_data;
reg b_mem2if1_valid;
reg [31:0] b_mem2if1_data;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_if2mem_ena <= 1'b0;
b_if2mem_rw <= 1'b0;
b_if2mem_addr <= {P_MEM_ADDR_N{1'b0}};
b_if2mem_data <= 32'h0;
b_mem2if0_valid <= 1'b0;
b_mem2if0_data <= 32'h0;
b_mem2if1_valid <= 1'b0;
b_mem2if1_data <= 32'h0;
end
else if(b_state != L_PARAM_STT_WORK || iRESET_SYNC)begin
b_if2mem_ena <= 1'b0;
b_if2mem_rw <= 1'b0;
b_if2mem_addr <= {P_MEM_ADDR_N{1'b0}};
b_if2mem_data <= 32'h0;
b_mem2if0_valid <= 1'b0;
b_mem2if0_data <= 32'h0;
b_mem2if1_valid <= 1'b0;
b_mem2if1_data <= 32'h0;
end
else begin
case(b_authority)
1'b0:
begin
b_if2mem_ena <= iIF0_ENA;
b_if2mem_rw <= iIF0_RW;
b_if2mem_addr <= iIF0_ADDR;
b_if2mem_data <= iIF0_DATA;
b_mem2if0_valid <= iMEM_VALID;
b_mem2if0_data <= iMEM_DATA;
b_mem2if1_valid <= 1'b0;
b_mem2if1_data <= 32'h0;
end
1'b1:
begin
b_if2mem_ena <= iIF1_ENA;
b_if2mem_rw <= iIF1_RW;
b_if2mem_addr <= iIF1_ADDR;
b_if2mem_data <= iIF1_DATA;
b_mem2if0_valid <= 1'b0;
b_mem2if0_data <= 32'h0;
b_mem2if1_valid <= iMEM_VALID;
b_mem2if1_data <= iMEM_DATA;
end
endcase
end
end
assign oIF0_ARBIT_ACK = (b_state == L_PARAM_STT_ACK) && !b_authority;
assign oIF1_ARBIT_ACK = (b_state == L_PARAM_STT_ACK) && b_authority;
assign oIF0_VALID = b_mem2if0_valid;
assign oIF0_DATA = b_mem2if0_data;
assign oIF1_VALID = b_mem2if1_valid;
assign oIF1_DATA = b_mem2if1_data;
assign oMEM_ENA = b_if2mem_ena;
assign oMEM_RW = b_if2mem_rw;
assign oMEM_ADDR = b_if2mem_addr;
assign oMEM_DATA = b_if2mem_data;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int prime[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31}; vector<int> next(vector<int>& a, int p, int k) { vector<int> result; for (long long mul = 1; mul <= (long long)k; mul *= p) { for (int i = 0; i < a.size(); ++i) { long long newN = (long long)a[i] * mul; if (newN <= k) { result.push_back((int)newN); } } } return result; } int main() { ios_base::sync_with_stdio(false); int k; cin >> k; int treshold = 2 * k * k; vector<int> p; vector<int> a; a.push_back(1); int need = (k / 2); if (k % 2 == 1) need++; p.push_back(prime[0]); int ppp = 1; for (int i = 0; i < p.size(); ++i) { int old = a.size(); a = next(a, p[i], 2 * k * k); if (a.size() - old >= need && a.size() >= k) break; else p.push_back(prime[ppp++]); } vector<int> result; vector<int> h(p.size()); int i = a.size() - 1; for (int ch = (int)p.size() - 1; ch >= 0; ch--) { for (; h[ch] < need && i >= 0; --i) { if (a[i] % p[ch] == 0) { result.push_back(a[i]); for (int pp = 0; pp < p.size(); ++pp) { if (a[i] % p[pp] == 0) ++h[pp]; } a[i] = 31; } } } while (result.size() < k) { if (i < 0) i = (a.size() - 1); if (a[i] != 31) { result.push_back(a[i]); a[i] = 31; } i--; } for (int i = 0; i < result.size(); ++i) cout << result[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; double __begin; template <typename T1, typename T2, typename T3> struct triple { T1 a; T2 b; T3 c; triple(){}; triple(T1 _a, T2 _b, T3 _c) : a(_a), b(_b), c(_c) {} }; template <typename T1, typename T2, typename T3> bool operator<(const triple<T1, T2, T3>& t1, const triple<T1, T2, T3>& t2) { if (t1.a != t2.a) return t1.a < t2.a; else if (t1.b != t2.b) return t1.b < t2.b; else return t1.c < t2.c; } template <typename T1, typename T2, typename T3> inline std::ostream& operator<<(std::ostream& os, const triple<T1, T2, T3>& t) { return os << ( << t.a << , << t.b << , << t.c << ) ; } inline int bits_count(int v) { v = v - ((v >> 1) & 0x55555555); v = (v & 0x33333333) + ((v >> 2) & 0x33333333); return ((v + (v >> 4) & 0xF0F0F0F) * 0x1010101) >> 24; } inline int bits_count(long long v) { int t = v >> 32; int p = (v & ((1LL << 32) - 1)); return bits_count(t) + bits_count(p); } unsigned int reverse_bits(register unsigned int x) { x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); return ((x >> 16) | (x << 16)); } inline int sign(int x) { return x > 0; } inline bool isPowerOfTwo(int x) { return (x != 0 && (x & (x - 1)) == 0); } template <typename T1, typename T2> inline std::ostream& operator<<(std::ostream& os, const std::pair<T1, T2>& p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> inline std::ostream& operator<<(std::ostream& os, const std::vector<T>& v) { bool first = true; os << [ ; for (unsigned int i = 0; i < v.size(); i++) { if (!first) os << , ; os << v[i]; first = false; } return os << ] ; } template <typename T> inline std::ostream& operator<<(std::ostream& os, const std::set<T>& v) { bool first = true; os << [ ; for (typename std::set<T>::const_iterator ii = v.begin(); ii != v.end(); ++ii) { if (!first) os << , ; os << *ii; first = false; } return os << ] ; } template <typename T1, typename T2> inline std::ostream& operator<<(std::ostream& os, const std::map<T1, T2>& v) { bool first = true; os << [ ; for (typename std::map<T1, T2>::const_iterator ii = v.begin(); ii != v.end(); ++ii) { if (!first) os << , ; os << *ii; first = false; } return os << ] ; } template <typename T, typename T2> void printarray(T a[], T2 sz, T2 beg = 0) { for (T2 i = beg; i < sz; i++) cout << a[i] << ; cout << endl; } inline long long mulmod(long long x, long long n, long long _mod) { long long res = 0; while (n) { if (n & 1) res = (res + x) % _mod; x = (x + x) % _mod; n >>= 1; } return res; } inline long long powmod(long long x, long long n, long long _mod) { long long res = 1; while (n) { if (n & 1) res = (res * x) % _mod; x = (x * x) % _mod; n >>= 1; } return res; } inline long long gcd(long long a, long long b) { long long t; while (b) { a = a % b; t = a; a = b; b = t; } return a; } inline int gcd(int a, int b) { int t; while (b) { a = a % b; t = a; a = b; b = t; } return a; } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline long long gcd(long long a, long long b, long long c) { return gcd(gcd(a, b), c); } inline int gcd(int a, int b, int c) { return gcd(gcd(a, b), c); } template <class T> inline void cinarr(T& a, int n) { for (int i = 0; i < n; ++i) cin >> a[i]; } int main() { int n, c_mx = -1, c_mn = 1e9, ans = 0; scanf( %d , &n); vector<int> a(n), p(n), s(n); for (int i = 0; i < (n); ++i) scanf( %d , &a[i]); for (int i = 0; i < (n); ++i) { if (a[i] > c_mx) c_mx = a[i]; p[i] = c_mx; } for (int i = (n)-1; i >= (0); --i) { if (a[i] < c_mn) c_mn = a[i]; s[i] = c_mn; } for (int i = 0; i < (n - 1); ++i) ans += (p[i] <= s[i + 1]); printf( %d , ans + 1); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Input Buffer with Offset Calibration and VREF Tuning
// /___/ /\ Filename : IBUFE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFE3 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter IBUF_LOW_PWR = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0,
parameter USE_IBUFDISABLE = "FALSE"
)(
output O,
input I,
input IBUFDISABLE,
input [3:0] OSC,
input OSC_EN,
input VREF
);
// define constants
localparam MODULE_NAME = "IBUFE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam USE_IBUFDISABLE_FALSE = 0;
localparam USE_IBUFDISABLE_TRUE = 1;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE;
wire IBUF_LOW_PWR_BIN;
wire [6:0] SIM_INPUT_BUFFER_OFFSET_BIN;
wire USE_IBUFDISABLE_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire O_out;
reg O_OSC_in;
wire O_delay;
wire IBUFDISABLE_in;
wire I_in;
wire OSC_EN_in;
wire VREF_in;
wire [3:0] OSC_in;
wire IBUFDISABLE_delay;
wire I_delay;
wire OSC_EN_delay;
wire VREF_delay;
wire [3:0] OSC_delay;
assign #(out_delay) O = O_delay;
// inputs with no timing checks
assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE;
assign #(in_delay) I_delay = I;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign #(in_delay) VREF_delay = VREF;
assign O_delay = O_out;
assign IBUFDISABLE_in = IBUFDISABLE_delay;
assign I_in = I_delay;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
assign VREF_in = VREF_delay;
integer OSC_int = 0;
generate
case (USE_IBUFDISABLE_REG)
"TRUE" : begin
assign O_out = (IBUFDISABLE_in == 0)? (OSC_EN_in) ? O_OSC_in : I_in : (IBUFDISABLE_in == 1 && OSC_EN_in != 1)? 1'b0 : 1'bx;
end
"FALSE" : begin
assign O_out = (OSC_EN_in) ? O_OSC_in : I_in;
end
endcase
endgenerate
always @ (OSC_in or OSC_EN_in) begin
OSC_int = OSC_in[2:0] * 5;
if (OSC_in[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in == 1'b1) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0)
O_OSC_in <= ~O_OSC_in;
end
end
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
IBUF_LOW_PWR_TRUE;
assign SIM_INPUT_BUFFER_OFFSET_BIN = SIM_INPUT_BUFFER_OFFSET_REG;
assign USE_IBUFDISABLE_BIN =
(USE_IBUFDISABLE_REG == "FALSE") ? USE_IBUFDISABLE_FALSE :
(USE_IBUFDISABLE_REG == "TRUE") ? USE_IBUFDISABLE_TRUE :
USE_IBUFDISABLE_FALSE;
initial begin
#1;
trig_attr = ~trig_attr;
end
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int)< 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0)
O_OSC_in <= 1'bx;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin
$display("Error: [Unisim %s-103] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IBUF_LOW_PWR_REG != "TRUE") &&
(IBUF_LOW_PWR_REG != "FALSE"))) begin
$display("Error: [Unisim %s-101] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_IBUFDISABLE_REG != "FALSE") &&
(USE_IBUFDISABLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-104] USE_IBUFDISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_IBUFDISABLE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const long long INF = (1ll << 45); long long bit[1000006]; void update(long long from, long long val) { for (long long i = from; i < 1000006; i += i & -i) bit[i] += val; } long long query(long long from) { if (from == 0) return 0; long long cnt = 0; for (long long i = from; i > 0; i -= i & -i) cnt += bit[i]; return cnt; } long long query(long long l, long long r) { return query(r) - query(l - 1); } struct Node { Node *lc, *rc; long long mx, tag; Node() : lc(NULL), rc(NULL), mx(-INF), tag(0) {} void pull() { mx = max(lc->mx, rc->mx); } }; const long long N = 1000002; Node* Build(long long L, long long R) { Node* node = new Node(); if (L == R) { node->mx = -N + L; return node; } long long mid = (L + R) >> 1; node->lc = Build(L, mid); node->rc = Build(mid + 1, R); node->pull(); return node; } void push(Node* node, long long L, long long R) { if (L == R) node->tag = 0; if (node->tag == 0) return; node->lc->mx += node->tag; node->rc->mx += node->tag; node->lc->tag += node->tag; node->rc->tag += node->tag; node->tag = 0; return; } void modify(Node* node, long long L, long long R, long long l, long long r, long long val) { if (l > R || L > r) return; else if (l <= L && R <= r) { node->mx += val; node->tag += val; return; } push(node, L, R); long long mid = (L + R) >> 1; modify(node->lc, L, mid, l, r, val); modify(node->rc, mid + 1, R, l, r, val); node->pull(); return; } long long query(Node* node, long long L, long long R, long long l, long long r) { if (l > R || L > r) return -INF; else if (l <= L && R <= r) return node->mx; push(node, L, R); long long mid = (L + R) >> 1; return max(query(node->lc, L, mid, l, r), query(node->rc, mid + 1, R, l, r)); } long long n, x[N][2]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; Node* root = Build(1, N); string in; long long v1, v2; for (long long i = 1; i < n + 1; ++i) { cin >> in; if (in == ? ) { cin >> v1; cout << query(root, 1, N, 1, v1) + (N - v1) - query(v1 + 1, 1000006 - 1) << n ; } else if (in == + ) { cin >> v1 >> v2; x[i][0] = v1; x[i][1] = v2; modify(root, 1, N, 1, x[i][0], x[i][1]); update(v1, v2); } else if (in == - ) { cin >> v1; modify(root, 1, N, 1, x[v1][0], -x[v1][1]); update(x[v1][0], -x[v1][1]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int maxn = 1e5 + 7; int n, x; int main() { cin >> n >> x; int ans = 0, num = 0; if (n == 2 && x == 0) { puts( NO ); return 0; } puts( YES ); if (n == 1) printf( %d , x); else if (n == 2) printf( %d %d , 0, x); else if (n == 3) { int t1 = 1 << 18; int t2 = 1 << 19; int t3 = x ^ t1 ^ t2; printf( %d %d %d , t1, t2, t3); } else { for (int i = 1;; i++) { if (i == x) continue; ans ^= i; printf( %d , i); num++; if (num == n - 3) break; } int t1 = 1 << 18; int t2 = 1 << 19; int t3 = x ^ ans ^ t1 ^ t2; printf( %d %d %d , t1, t2, t3); ans ^= t1 ^ t2 ^ t3; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_2_V
`define SKY130_FD_SC_LS__O221A_2_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221a_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_2_V
|
`timescale 1ns / 1ps
////////////////////////////////////
//Zachary Karpinski
//Karpentium Processor
//
//instruction_register.v
//
//A load/store register for the instuctions with the control table
// ls clr function
// d 1 clear register
// 0 0 store
// 1 0 load
//
///////////////////////////////////
module instruction_register(clk,in,out,opcode,ls,enable,clr);
input clk,clr,ls,enable; //clock,clear,load line,enable line
input [15:0] in; //input data
output [15:0] out; //output data
output [3:0] opcode; //first 4 bits of instruction (OPCODE)
reg [15:0] instr; //stored instruction
initial begin instr = 16'dZ; end
always @(posedge(clk))
begin
if(clr) begin
instr = 16'dZ;
end
else if (ls) begin
instr = in;
end
else begin
instr = instr;
end
end
assign opcode = instr[15:12];
assign out = (enable) ? instr : 16'hZZ;
//Clear instruction before load
//Helps with controller indentifying sucessful instruction
always @(posedge(ls))
begin
instr = 16'dZ;
end
endmodule
|
#include <bits/stdc++.h> #define ll long long #define real long double #define fr(i,l,n) for(ll i=l;i<n;i++) #define br cout<< n #define al(fu) (fu).begin(), (fu).end() #define prl(c) cout<<(c)<< n #define prv(v) {fr(qz,0,v.size()) cout<<(v)[qz]<< ; br;} #define alr(fu) (fu).rbegin(), (fu).rend() #define mod 1000000007LL #define mod1 998244353LL #define nfi 1000000000000000013LL #define skoree ios::sync_with_stdio(0); cin.tie(0) #define danet(b) cout<<(b? YES : NO ) #define Danet(b) cout<<(b? Yes : No ) using namespace std; char aq(char a){ if(a== 0 ) return 1 ; else return 0 ; } int main(){ skoree; ll o0o; cin>>o0o; while(o0o--){ ll n; cin>>n; vector<string> a(n),b(n); fr(i,0,n) cin>>a[i]; fr(i,0,n) cin>>b[i]; fr(i,0,n) if(a[0][i]!=b[0][i]){ fr(j,0,n) a[j][i]=aq(a[j][i]); } bool bb=1; fr(i,1,n) if(a[i]!=b[i]){ fr(j,0,n) a[i][j]=aq(a[i][j]); if(a[i]!=b[i]) bb=0; } danet(bb);br; } return 0; } /* */
|
#include <bits/stdc++.h> using namespace std; string s, s2, t1, t2; int main() { long long n, l, r, i, j; cin >> s; n = s.length(); char mx = a ; for (i = n - 1; i >= 0; i--) { if (s[i] - mx >= 0) { mx = s[i]; l = i; } } s2 += mx; r = l; for (i = mx - a ; i >= 0; i--) { char aa = a + i; l = r; for (j = l + 1; j < n; j++) { if (s[j] == aa) { s2 += s[j]; r = j; } } } cout << s2 << endl; }
|
// $Id: c_dff.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// configurable register
//==============================================================================
module c_dff
(clk, reset, active, d, q);
`include "c_constants.v"
// width of register
parameter width = 32;
// offset (left index) of register
parameter offset = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
parameter [offset:(offset+width)-1] reset_value = {width{1'b0}};
input clk;
input reset;
input active;
// data input
input [offset:(offset+width)-1] d;
// data output
output [offset:(offset+width)-1] q;
reg [offset:(offset+width)-1] q;
generate
case(reset_type)
`RESET_TYPE_ASYNC:
always @(posedge clk, posedge reset)
if(reset)
q <= reset_value;
else if(active)
q <= d;
`RESET_TYPE_SYNC:
always @(posedge clk)
if(reset)
q <= reset_value;
else if(active)
q <= d;
endcase
endgenerate
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:54:28 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_stub.v
// Design : system_zybo_hdmi_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zybo_hdmi,Vivado 2016.4" *)
module system_zybo_hdmi_0_0(clk_125, clk_25, hsync, vsync, active, rgb, tmds,
tmdsb, hdmi_cec, hdmi_hpd, hdmi_out_en)
/* synthesis syn_black_box black_box_pad_pin="clk_125,clk_25,hsync,vsync,active,rgb[23:0],tmds[3:0],tmdsb[3:0],hdmi_cec,hdmi_hpd,hdmi_out_en" */;
input clk_125;
input clk_25;
input hsync;
input vsync;
input active;
input [23:0]rgb;
output [3:0]tmds;
output [3:0]tmdsb;
input hdmi_cec;
input hdmi_hpd;
output hdmi_out_en;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e12; const int INF1 = 1e7; const int maxn = 100000 + 10; int n, m, k; int fd, u, v, w; struct node { int to, cost, fd; } a[maxn], b[maxn]; bool cmp(node f, node g) { return f.fd < g.fd; } bool cmp1(node f, node g) { return f.fd > g.fd; } int ecnt = 0, ecnt1 = 0; long long dp[maxn * 10], dp1[maxn * 10]; int d[maxn], d1[maxn]; int mx = 0; int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= m; i++) { scanf( %d%d%d%d , &fd, &u, &v, &w); if (v == 0) { a[ecnt].to = u, a[ecnt].cost = w, a[ecnt].fd = fd; ecnt++; } if (u == 0) { b[ecnt1].to = v, b[ecnt1].cost = w, b[ecnt1].fd = fd; ecnt1++; } mx = max(mx, fd); } sort(a, a + ecnt, cmp); sort(b, b + ecnt1, cmp1); for (int i = 1; i <= n; i++) d[i] = INF1, d1[i] = INF1; int cnt = 0; int tmp = -1; for (int i = 0; i < ecnt; i++) { v = a[i].to; if (d[v] == INF1) { cnt++; } d[v] = min(d[v], a[i].cost); if (cnt == n) { tmp = i; break; } } if (tmp == -1) { printf( -1 n ); return 0; } for (int i = 1; i <= n; i++) dp[a[tmp].fd] += d[i]; for (int i = tmp + 1; i < ecnt; i++) { v = a[i].to; dp[a[i].fd] = dp[a[i - 1].fd]; dp[a[i].fd] = dp[a[i].fd] - d[v]; d[v] = min(d[v], a[i].cost); dp[a[i].fd] += d[v]; } cnt = 0; tmp = -1; for (int i = 0; i < ecnt1; i++) { v = b[i].to; if (d1[v] == INF1) { cnt++; } d1[v] = min(d1[v], b[i].cost); if (cnt == n) { tmp = i; break; } } if (tmp == -1) { printf( -1 n ); return 0; } for (int i = 1; i <= n; i++) dp1[b[tmp].fd] += d1[i]; for (int i = tmp + 1; i < ecnt1; i++) { v = b[i].to; dp1[b[i].fd] = dp1[b[i - 1].fd]; dp1[b[i].fd] = dp1[b[i].fd] - d1[v]; d1[v] = min(d1[v], b[i].cost); dp1[b[i].fd] += d1[v]; } for (int i = 1; i <= mx; i++) { if (dp[i] == 0) dp[i] = dp[i - 1]; } for (int i = mx; i >= 1; i--) { if (dp1[i] == 0) dp1[i] = dp1[i + 1]; } long long ans = INF; for (int i = 0; i < ecnt; i++) { if (dp[a[i].fd] != 0) { if (a[i].fd + k + 1 <= mx && dp1[a[i].fd + k + 1] != 0) ans = min(ans, dp[a[i].fd] + dp1[a[i].fd + k + 1]); } } if (ans == INF) printf( -1 n ); else printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = (1e6) + 7; const int inf = (1e9) + 7; const long long LLinf = (1e18) + 7; const long double eps = 1e-9; const long long mod = 1e9 + 7; const int maxlog = 31; stack<pair<int, int> > stos; int tab[maxn]; int lewo[maxn]; int prawo[maxn]; int le[maxn][maxlog]; int pr[maxn][maxlog]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 1; i < n + 1; i++) { cin >> tab[i]; while (((int)(stos).size()) && stos.top().first < tab[i]) stos.pop(); if (((int)(stos).size())) lewo[i] = stos.top().second; stos.push({tab[i], i}); } while (((int)(stos).size())) stos.pop(); for (int i = n; i > 0; i--) { while (((int)(stos).size()) && stos.top().first <= tab[i]) stos.pop(); if (((int)(stos).size())) prawo[i] = stos.top().second; else prawo[i] = n + 1; stos.push({tab[i], i}); } for (int bit = 0; bit < maxlog; bit++) { int curr = 0; for (int i = 1; i < n + 1; i++) { if (tab[i] & (1 << bit)) curr = i; le[i][bit] = curr; } curr = n + 1; for (int i = n; i > 0; i--) { if (tab[i] & (1 << bit)) curr = i; pr[i][bit] = curr; } } long long res = 0LL; for (int i = 1; i < n + 1; i++) { int l = 0; int p = n + 1; for (int bit = 0; bit < maxlog; bit++) { if (tab[i] & (1 << bit)) continue; l = max(l, le[i][bit]); p = min(p, pr[i][bit]); } if (l - lewo[i] > 0) res += (l - lewo[i]) * (long long)(prawo[i] - i); if (prawo[i] - p > 0) res += (prawo[i] - p) * (long long)(i - lewo[i]); if (prawo[i] - p > 0 && l - lewo[i] > 0) res -= (prawo[i] - p) * (long long)(l - lewo[i]); } cout << res; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DFBBP_BEHAVIORAL_PP_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; struct edge { int to, index; edge(int t = 0, int i = 0) { to = t; index = i; } }; vector<edge> g[N]; int num[N], ans[N], dep[N], fa[18][N], n, m; void add(int from, int to, int index) { g[from].push_back(edge(to, index)); } void dfs(int x, int ffa, int d) { fa[0][x] = ffa; dep[x] = d; for (int i = 0; i < g[x].size(); i++) { int y = g[x][i].to; if (y == ffa) continue; dfs(y, x, d + 1); } } void init() { m = 0; while (n >= (1 << m)) m++; for (int i = 1; i <= m; i++) { for (int j = 1; j <= n; j++) { if (fa[i - 1][j] < 0) fa[i][j] = -1; else { fa[i][j] = fa[i - 1][fa[i - 1][j]]; } } } } int LCA(int x, int y) { if (dep[x] < dep[y]) swap(x, y); for (int i = m; i >= 0; i--) { if ((dep[x] - dep[y]) & (1 << i)) x = fa[i][x]; } if (x == y) return x; for (int i = m; i >= 0; i--) { if (fa[i][x] != fa[i][y]) { x = fa[i][x]; y = fa[i][y]; } } return fa[0][x]; } void dfs2(int x, int fa, int z) { for (int i = 0; i < g[x].size(); i++) { int y = g[x][i].to; if (y == fa) continue; dfs2(y, x, g[x][i].index); num[x] += num[y]; } ans[z] = num[x]; } int main() { int x, y, rt; scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %d%d , &x, &y); add(x, y, i); add(y, x, i); } dfs(1, -1, 0); init(); int TA; scanf( %d , &TA); while (TA--) { scanf( %d%d , &x, &y); rt = LCA(x, y); num[x]++; num[y]++; num[rt] -= 2; } dfs2(1, -1, 0); for (int i = 1; i < n; i++) printf( %d , ans[i]); printf( n ); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } int time = INT_MAX, check = 0; for (int i = 0; i < n; i++) { check = 0; int no = a[i]; for (int j = 0; j < no; j++) { int item; cin >> item; check += item * 5; } check += no * 15; time = min(time, check); } cout << time; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n == 1) cout << 1 << << 1 << n << 1; else cout << 2 * (n - 1) << << 2 << n << 1 << << 2; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int x, y; cin >> x >> y; int tx = x - y; int ty = x + y; x = tx; y = ty; if (x < 0) cout << -1 n ; else { int l = 1, r = 1e9 + 5; while (r - l > 1) { int mid = (l + r) / 2; if ((1LL * y * (mid - 1) + mid - 1) / mid <= x) l = mid; else r = mid; } long double ans = y; ans /= l; ans /= 2.0; cout << setprecision(19) << fixed << ans << n ; } return 0; }
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:200000000 ) using namespace std; template <typename T> inline T Abs(T x) { return (x >= 0) ? x : -x; } template <typename T> inline T sqr(T x) { return x * x; } template <typename T> string toStr(T x) { stringstream st; st << x; string s; st >> s; return s; } const int INF = (int)1E9; const long long INF64 = (long long)1E18; const long double EPS = 1E-9; const long double PI = 3.1415926535897932384626433832795; map<pair<long long, long long>, long long> d; long long solve(long long n, long long t) { if (d.count(make_pair(n, t))) return d[make_pair(n, t)]; if (n == 0) return d[make_pair(n, t)] = 0; long long l = 1, p = 0; while (2 * l <= n) { l *= 2; p++; } if (t == 1) return d[make_pair(n, t)] = p + 1; if (n <= 2) return d[make_pair(n, t)] = 0; long long ans = solve(l / 2 - 1, t); if (t % 2 == 0) ans += solve(l / 2 - 1, t / 2); if (n != l && t % 2 == 0) ans += solve(n - l, t / 2); return d[make_pair(n, t)] = ans; } int main() { long long n, t; cin >> n >> t; long long ans = solve(n + 1, t); if (t == 1) ans--; cout << ans << endl; return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_data_in #(
// parameters
parameter SINGLE_ENDED = 0,
parameter DEVICE_TYPE = 0,
parameter IODELAY_ENABLE = 1,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
input rx_clk,
input rx_data_in_p,
input rx_data_in_n,
output rx_data_p,
output rx_data_n,
// delay-data interface
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
input delay_clk,
input delay_rst,
output delay_locked);
// internal parameters
localparam NONE = -1;
localparam VIRTEX7 = 0;
localparam ULTRASCALE_PLUS = 2;
localparam ULTRASCALE = 3;
localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0;
localparam IODELAY_CTRL_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE" :
(DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
localparam IODELAY_DEVICE_TYPE = (IODELAY_ENABLE == 1) ? DEVICE_TYPE : NONE;
localparam IODELAY_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS" :
(DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
// internal signals
wire rx_data_ibuf_s;
wire rx_data_idelay_s;
wire [ 8:0] up_drdata_s;
// delay controller
generate
if (IODELAY_CTRL_ENABLED == 0) begin
assign delay_locked = 1'b1;
end else begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL #(.SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)) i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
end
endgenerate
// receive data interface, ibuf -> idelay -> iddr
generate
if (SINGLE_ENDED == 1) begin
IBUF i_rx_data_ibuf (
.I (rx_data_in_p),
.O (rx_data_ibuf_s));
end else begin
IBUFDS i_rx_data_ibuf (
.I (rx_data_in_p),
.IB (rx_data_in_n),
.O (rx_data_ibuf_s));
end
endgenerate
// idelay
generate
if (IODELAY_DEVICE_TYPE == VIRTEX7) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (up_clk),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end
endgenerate
generate
if ((IODELAY_DEVICE_TYPE == ULTRASCALE) || (IODELAY_DEVICE_TYPE == ULTRASCALE_PLUS)) begin
assign up_drdata = up_drdata_s[8:4];
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE3 #(
.SIM_DEVICE (IODELAY_SIM_DEVICE),
.DELAY_SRC ("IDATAIN"),
.DELAY_TYPE ("VAR_LOAD"),
.REFCLK_FREQUENCY (200.0),
.DELAY_FORMAT ("COUNT"))
i_rx_data_idelay (
.CASC_RETURN (1'b0),
.CASC_IN (1'b0),
.CASC_OUT (),
.CE (1'b0),
.CLK (up_clk),
.INC (1'b0),
.LOAD (up_dld),
.CNTVALUEIN ({up_dwdata, 4'd0}),
.CNTVALUEOUT (up_drdata_s),
.DATAIN (1'b0),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.RST (1'b0),
.EN_VTC (~up_dld));
end
endgenerate
generate
if (IODELAY_DEVICE_TYPE == NONE) begin
assign rx_data_idelay_s = rx_data_ibuf_s;
assign up_drdata = 5'd0;
end
endgenerate
// iddr
generate
if ((DEVICE_TYPE == ULTRASCALE) || (DEVICE_TYPE == ULTRASCALE_PLUS)) begin
IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
.R (1'b0),
.C (rx_clk),
.CB (~rx_clk),
.D (rx_data_idelay_s),
.Q1 (rx_data_p),
.Q2 (rx_data_n));
end
endgenerate
generate
if (DEVICE_TYPE == VIRTEX7) begin
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (rx_clk),
.D (rx_data_idelay_s),
.Q1 (rx_data_p),
.Q2 (rx_data_n));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
//////////////////////////////////////////////////////////////////////
//// ////
//// speedCtrlMux.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module speedCtrlMux (directCtrlRate, directCtrlPol, sendPacketRate, sendPacketPol, sendPacketSel, fullSpeedRate, fullSpeedPol);
input directCtrlRate;
input directCtrlPol;
input sendPacketRate;
input sendPacketPol;
input sendPacketSel;
output fullSpeedRate;
output fullSpeedPol;
wire directCtrlRate;
wire directCtrlPol;
wire sendPacketRate;
wire sendPacketPol;
wire sendPacketSel;
reg fullSpeedRate;
reg fullSpeedPol;
always @(directCtrlRate or directCtrlPol or sendPacketRate or sendPacketPol or sendPacketSel)
begin
if (sendPacketSel == 1'b1)
begin
fullSpeedRate <= sendPacketRate;
fullSpeedPol <= sendPacketPol;
end
else
begin
fullSpeedRate <= directCtrlRate;
fullSpeedPol <= directCtrlPol;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, ar[110]; while (cin >> n) { for (int i = 0; i < n; i++) { cin >> ar[i]; } if ((n % 2 == 1) && (ar[0] % 2 == 1) && (ar[n - 1] % 2 == 1)) cout << Yes << endl; else cout << No << endl; } }
|
/*=============================================================================
Testbench for Serial SPI Bus EEPROM Simulation Model
=============================================================================*/
`include "M95XXX_Parameters.v"
//This defines the parameter file for M95080-W6, "W" or "G" F6SP36% process
//Any other M95xxx memory should define here the proper M95xxx parameter file
//=====================================
module M95XXX_SIM;
wire c,d,q,s,w,hold,vcc,vss;
//-------------------------------------
M95XXX U_M95XXX(
.C(c),
.D(d),
.Q(q),
.S(s),
.W(w),
.HOLD(hold),
.VCC(vcc),
.VSS(vss)
);
//-------------------------------------
M95XXX_DRV M95XXX_Driver(
.C(c),
.D(d),
.Q(q),
.S(s),
.W(w),
.HOLD(hold),
.VCC(vcc),
.VSS(vss)
);
//-------------------------------------
M95XXX_Macro_mux M95XXX_Macro_mux();
integer index;
reg [8*3:0] string;
reg [8*4:0] string2;
initial begin
if (!`VALID_PRT)
begin
$display("\n#2#############################################");
$display("### NO VAILED MEMORY SIZE CHOOSEN ###");
$display("##############################################\n");
$stop;
end
if (`M1Kb_var)
string = "010";
else if (`M2Kb_var)
string = "020";
else if (`M4Kb_var)
string = "040";
else if (`M8Kb_var)
string = "080";
else if (`M16Kb_var)
string = "160";
else if (`M32Kb_var)
string = "320";
else if (`M64Kb_var)
string = "640";
else if (`M128Kb_var)
string = "128";
else if (`M256Kb_var)
string = "256";
else if (`M512Kb_var)
string = "512";
else if (`M1Mb_var)
string = "M01";
else if (`M2Mb_var)
string = "M02";
else
string = "XXX";
if (`A125_var)
string2 = "A125";
else if (`A145_var)
string2 = "A145";
else
string2 = "XXXX";
if (`VALID_PRT) begin
$display("\n################################################################################");
if (`A125_var || `A145_var) begin
$display("### The Selected Model is a AUTOMOTIVE memory, referenced as M95%3s-%4s ###",string,string2);
if (`W_var)
$display("### Minimum operating voltage range: W=2.5V/145C ###");
else if (`R_var)
$display("### Minimum operating voltage range: R=1.8V/125C ###");
end
else
if (`W_var) begin
if (`IDPAGE)
$display("### The Selected Model is a STANDARD memory, referenced as M95%3s-DW ###",string);
else
$display("### The Selected Model is a STANDARD memory, referenced as M95%3s-W ###",string);
$display("### Minimum operating voltage range: W=2.5V ###");
end
else if (`R_var) begin
if (`IDPAGE)
$display("### The Selected Model is a STANDARD memory, referenced as M95%3s-DR ###",string);
else
$display("### The Selected Model is a STANDARD memory, referenced as M95%3s-R ###",string);
$display("### Minimum operating voltage range: R=1.8V ###");
end
else if (`F_var) begin
if (`IDPAGE)
$display("### The Selected Model is a STANDARD memory, referenced as M95%3s-DF ###",string);
else
$display("### The Selected Model is a STANDARD memory, referenced as M95%3s-F ###",string);
$display("### Minimum operating voltage range: F=1.7V ###");
end
end
$display("### Operating voltage selected: VCC=%1f V ",`Vcc);
if (`M1Kb_var)
$display("### Memory Capacity: 1 Kb ###");
else if (`M2Kb_var)
$display("### Memory Capacity: 2 Kb ###");
else if (`M4Kb_var)
$display("### Memory Capacity: 4 Kb ###");
else if (`M8Kb_var)
$display("### Memory Capacity: 8 Kb ###");
else if (`M16Kb_var)
$display("### Memory Capacity: 16 Kb ###");
else if (`M32Kb_var)
$display("### Memory Capacity: 32 Kb ###");
else if (`M64Kb_var)
$display("### Memory Capacity: 64 Kb ###");
else if (`M128Kb_var)
$display("### Memory Capacity: 128 Kb ###");
else if (`M256Kb_var)
$display("### Memory Capacity: 256 Kb ###");
else if (`M512Kb_var)
$display("### Memory Capacity: 512 Kb ###");
else if (`M1Mb_var)
$display("### Memory Capacity: 1 Mb ###");
else if (`M2Mb_var)
$display("### Memory Capacity: 2 Mb ###");
else begin
$display("\n###############################################");
$display("### 1 NO VAILED MEMORY SIZE CHOOSEN ###");
$display("##############################################\n");
$stop;
end
$display("################################################################################\n");
/* for(index = 0; index < `MEM_SIZE; index = index + 1)
U_M95080.memory[index] = 8'hff;
$writememh("memory_hex.txt", U_M95080.memory);
*/
$display("%t: NOTE: Load memory with Initial content.",$realtime);
$readmemh("M95XXX_Initial.dat",U_M95XXX.memory);
$display("%t: NOTE: Initial Load End.\n",$realtime);
if (`IDPAGE)
begin
$display("%t: NOTE: Load ID memory with Initial content.",$realtime);
$readmemh("M95XXX_ID_Initial.dat",U_M95XXX.memory_id);
$display("%t: NOTE: Initial ID Load End.\n",$realtime);
end
end
//-------------------------------------
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: counter.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple up-counter. The maximum value is the largest expected
// value. The counter will not pass the SAT_VALUE. If the SAT_VALUE > MAX_VALUE,
// the counter will roll over and never stop. On RST_IN, the counter
// synchronously resets to the RST_VALUE
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module counter
#(parameter C_MAX_VALUE = 10,
parameter C_SAT_VALUE = 10,
parameter C_RST_VALUE = 0)
(
input CLK,
input RST_IN,
input ENABLE,
output [clog2s(C_MAX_VALUE+1)-1:0] VALUE
);
wire wEnable;
reg [clog2s(C_MAX_VALUE+1)-1:0] wCtrValue;
reg [clog2s(C_MAX_VALUE+1)-1:0] rCtrValue;
/* verilator lint_off WIDTH */
assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue);
/* verilator lint_on WIDTH */
assign VALUE = rCtrValue;
always @(posedge CLK) begin
if(RST_IN) begin
rCtrValue <= C_RST_VALUE[clog2s(C_MAX_VALUE+1)-1:0];
end else if(wEnable) begin
rCtrValue <= rCtrValue + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; const int sz = 1 << 13; vector<int> gos[5001]; int rev[5001]; template <class T> class Dinic { struct _edge { int x, y; T c, rc; _edge(int x, int y, T c, T rc) : x(x), y(y), c(c), rc(rc) {} }; int s, e; int n; vector<T> nowFlow; vector<vector<int>> edge; vector<_edge> es; vector<int> dist; vector<int> it; T inf; int bfs() { for (int i = 0; i < n; ++i) dist[i] = -1; queue<int> q; dist[s] = 0; q.push(s); while (!q.empty()) { int x = q.front(); q.pop(); for (int i : edge[x]) { if (i < 0) { i = ~i; if (dist[es[i].x] != -1) continue; if (es[i].rc > 0) { dist[es[i].x] = dist[x] + 1; q.push(es[i].x); } } else { if (dist[es[i].y] != -1) continue; if (es[i].c > 0) { dist[es[i].y] = dist[x] + 1; q.push(es[i].y); } } } } return dist[e] != -1; } T dfs(int x, T f) { if (x == e) return f; for (int &i = it[x]; i < edge[x].size(); ++i) { int y; T c; if (edge[x][i] < 0) y = es[~edge[x][i]].x, c = es[~edge[x][i]].rc; else y = es[edge[x][i]].y, c = es[edge[x][i]].c; if (dist[x] + 1 != dist[y]) continue; if (c == 0) continue; c = dfs(y, min(f, c)); if (c > 0) { if (edge[x][i] < 0) { es[~edge[x][i]].c += c; es[~edge[x][i]].rc -= c; nowFlow[~edge[x][i]] -= c; } else { es[edge[x][i]].c -= c; es[edge[x][i]].rc += c; nowFlow[edge[x][i]] += c; } return c; } } return 0; } int matchdfs(int x) { if (::n + ::sz <= x && x < ::n + ::sz + ::m) return x - ::n - sz + 1; for (int &i = it[x]; i < edge[x].size(); ++i) { int y; T c; if (edge[x][i] < 0) y = es[~edge[x][i]].x, c = -nowFlow[~edge[x][i]]; else y = es[edge[x][i]].y, c = nowFlow[edge[x][i]]; if (c <= 0) continue; if (edge[x][i] < 0) ++nowFlow[~edge[x][i]]; else --nowFlow[edge[x][i]]; return matchdfs(y); } return 0; } public: void init(int N) { n = N; inf = 0; edge.clear(); edge.resize(n); dist.resize(n); it.resize(n); nowFlow.clear(); es.clear(); } int addEdge(int x, int y, T C, T RC) { inf = max(inf, C + RC); int idx = es.size(); es.emplace_back(x, y, C, RC); nowFlow.push_back(0); edge[x].push_back(idx); edge[y].push_back(~idx); return idx; } T findMaximumFlow(int source, int sink) { s = source; e = sink; T flow = 0; while (bfs()) { for (int i = 0; i < n; ++i) it[i] = 0; while (1) { T ret = dfs(s, inf); if (ret == 0) break; flow += ret; } } return flow; } T getFlow(int idx) { return nowFlow[idx]; } void findMatching() { for (int i = 0; i < n; ++i) it[i] = 0; for (int i = 1; i <= ::n; ++i) { int r = matchdfs(i); if (r) { gos[i].push_back(r); rev[r] = i; --i; } } } }; struct weapon { int type; int l, r; vector<int> ps; void scan() { cin >> type; if (type == 0) { int k, x; cin >> k; for (int i = 0; i < k; ++i) { cin >> x; ps.push_back(x); } } else if (type == 1) { cin >> l >> r; } else { for (int i = 0; i < 3; ++i) { int x; cin >> x; ps.push_back(x); } } } } wps[5001]; Dinic<int> dinic; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 1; i <= n; ++i) { wps[i].scan(); } dinic.init(n + sz + m + 10); int S = 0, E = n + sz + m + 9; for (int i = sz + m - 1; i > 1; --i) { dinic.addEdge(n + (i >> 1), n + i, m, 0); } for (int i = 1; i <= n; ++i) { dinic.addEdge(S, i, wps[i].type == 2 ? 2 : 1, 0); if (wps[i].type == 1) { int s = sz + wps[i].l - 1, e = sz + wps[i].r - 1; while (s <= e) { if ((s & 1) == 1) dinic.addEdge(i, n + (s++), 1, 0); if ((e & 1) == 0) dinic.addEdge(i, n + (e--), 1, 0); s >>= 1; e >>= 1; } } else { for (int j : wps[i].ps) dinic.addEdge(i, n + sz + j - 1, 1, 0); } } for (int i = 0; i < m; ++i) { dinic.addEdge(n + sz + i, E, 1, 0); } int ans = dinic.findMaximumFlow(S, E); printf( %d n , ans); dinic.findMatching(); for (int i = 1; i <= n; ++i) { if (wps[i].type != 2) continue; if (gos[i].size() != 1) continue; for (int j = 0; j < 3; ++j) { if (gos[i][0] == wps[i].ps[j]) continue; gos[rev[wps[i].ps[j]]].clear(); rev[wps[i].ps[j]] = i; gos[i].push_back(wps[i].ps[j]); break; } } for (int i = 1; i <= n; ++i) { for (int j : gos[i]) { printf( %d %d n , i, j); } } }
|
#include <bits/stdc++.h> #include<cmath> using namespace std; int main(){ long long t; cin>>t; while(t--){ int a,b,n; long long ans=0; cin>>a>>b>>n; int ar[a+1],br[b+1],arr[2][n]; memset(ar,0,sizeof(ar)); memset(br,0,sizeof(br)); for(int i=0;i<n;i++){ cin>>arr[0][i]; ar[arr[0][i]]++; } for(int i=0;i<n;i++){ cin>>arr[1][i]; br[arr[1][i]]++; } for(int i=0;i<n-1;i++){ ans+=n-i-1 -ar[arr[0][i]]+1 -br[arr[1][i]]+1; ar[arr[0][i]]--; br[arr[1][i]]--; } cout<<ans<<endl; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Nov 01 12:03:22 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
probe29, probe30)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[7:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [8:0]probe19;
input [7:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [0:0]probe24;
input [7:0]probe25;
input [3:0]probe26;
input [0:0]probe27;
input [0:0]probe28;
input [0:0]probe29;
input [7:0]probe30;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { int t; cin >> t; while (t--) { long long n, x, sum = 0, ans = 0, cur; cin >> n >> x; priority_queue<long long> nums; for (int i = 0; i < n; ++i) { cin >> cur; nums.push(cur - x); } for (int i = 0; i < n && sum >= 0; ++i) { sum += nums.top(); nums.pop(); if (sum < 0) break; ++ans; } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n, m, k; vector<int> ini[100005]; vector<int> mat[100005]; int maior[100005]; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int a; cin >> a; mat[i].push_back(a); ini[i].push_back(0); maior[i] = 0x3f3f3f3f; } for (int j = 0; j < m; j++) for (int i = 1; i < n; i++) { if (mat[i][j] >= mat[i - 1][j]) { ini[i][j] = ini[i - 1][j]; if (maior[i] > ini[i][j]) maior[i] = ini[i][j]; } else { ini[i][j] = i; } } cin >> k; for (int i = 0; i < k; i++) { int l, r; cin >> l >> r; bool flag = false; if (maior[r - 1] <= l - 1 or l == r) cout << Yes << endl; else cout << No << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int k; cin >> k; k += 2000; cout << 2000 << n ; cout << -1 << ; for (int i = 0; i < 1999; i++) { if (k > 1000000) { cout << 1000000 << ; k -= 1000000; } else { cout << k << ; k = 0; } } cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool chk[5000050]; int ara[5000050], sum[5000050]; void sieve() { int i, j, k, x, y, z; for (i = 2; i <= 5000000; i++) if (!chk[i]) { for (j = i; j <= 5000000; j += i) { x = 0; k = j; while (k % i == 0) { x++; k /= i; } chk[j] = true; ara[j] += x; } } sum[2] = ara[2]; for (i = 3; i <= 5000000; i++) sum[i] = sum[i - 1] + ara[i]; } int main() { sieve(); int i, t, n, m, k, ans; scanf( %d , &t); for (i = 0; i < t; i++) { scanf( %d %d , &m, &n); ans = sum[m] - sum[n]; printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 100004; unordered_map<string, int> mp; unordered_set<int> st[M]; vector<int> g[M]; string s[M]; int m = 0; int getid(string &t) { if (mp.count(t)) return mp[t]; else { s[++m] = t; return mp[t] = m; } } int val[M]; struct P { int v, s0, s1; } sv[M]; P dfs(int u, int p) { if (g[u].empty()) return P{p, 0, 0}; else if (sv[u].v != -1) return sv[u]; P win = P{-1, -1, -1}, lose = P{-1, -1, -1}; for (int v : g[u]) { P nw = dfs(v, p ^ 1); int s0 = nw.s0, s1 = nw.s1; if (p == 0) { s0 += val[v]; if (nw.v == 1 && (s0 > win.s0 || s0 == win.s0 && s1 < win.s1)) win = P{1, s0, s1}; if (nw.v == 0 && (s0 > lose.s0 || s0 == lose.s0 && s1 < lose.s1)) lose = P{0, s0, s1}; } else { s1 += val[v]; if (nw.v == 0 && (s1 > win.s1 || s1 == win.s1 && s0 < win.s0)) win = P{0, s0, s1}; if (nw.v == 1 && (s1 > lose.s1 || s1 == lose.s1 && s0 < lose.s0)) lose = P{1, s0, s1}; } } if (win.v != -1) return sv[u] = win; else return sv[u] = lose; } int main() { int n; memset(sv, -1, sizeof(sv)); cin >> n; string t; for (int i = 0; i < n; i++) { cin >> t; for (int j = 0; j < t.size(); j++) { string u = ; for (int k = j; k < t.size(); k++) { u += t[k]; int x = getid(u); st[x].insert(i); } } } for (int i = 0; i <= m; i++) { for (char ch = a ; ch <= z ; ch++) { string t = s[i] + ch; if (mp.count(t)) { int x = mp[t]; g[i].push_back(x); } t = string( ) + ch + s[i]; if (mp.count(t)) { int x = mp[t]; g[i].push_back(x); } } int sum = 0, mx = 0; for (char ch : s[i]) { int x = ch - a + 1; mx = max(mx, x); sum += x; } val[i] = sum * mx + st[i].size(); } P p = dfs(0, 0); puts(p.v ? First : Second ); printf( %d %d n , p.s0, p.s1); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_2_V
`define SKY130_FD_SC_LP__CLKBUF_2_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_2_V
|
#include <bits/stdc++.h> using namespace std; const int MX = 100 + 3; int n, m, k; bool mat[MX][MX], tmp[MX][MX]; void solve1() { int q = (1 << m); int cnt = 0; int ans = 20; for (int z = 0; z < q; z++) { cnt = 0; memset(tmp, false, sizeof(tmp)); for (int j = 0; j < m; j++) { if (z & (1 << j)) tmp[0][j] = true; if (tmp[0][j] != mat[0][j]) cnt++; } for (int i = 1; i < n; i++) { int p = 0; for (int j = 0; j < m; j++) { tmp[i][j] = !tmp[i - 1][j]; if (tmp[i][j] != mat[i][j]) p++; } p = min(p, m - p); cnt += p; } ans = min(cnt, ans); } if (ans > k) cout << -1 << endl; else cout << ans << endl; exit(0); } void swp() { for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) tmp[i][j] = mat[i][j]; for (int i = 0; i < m; i++) for (int j = 0; j < n; j++) mat[i][j] = tmp[j][i]; swap(n, m); } void solve2() { int ans = 20; int cnt = 0; if (n > k) { for (int i = 0; i < n; i++) { cnt = 0; memset(tmp, false, sizeof(tmp)); for (int j = 0; j < m; j++) tmp[i][j] = mat[i][j]; for (int k = 0; k < n; k++) { if (k != i) { int p = 0; for (int j = 0; j < m; j++) { tmp[k][j] = !tmp[i][j]; if (tmp[k][j] != mat[k][j]) p++; } p = min(p, m - p); cnt += p; } } ans = min(ans, cnt); } } else { swp(); memset(tmp, false, sizeof(tmp)); for (int i = 0; i < n; i++) { cnt = 0; for (int j = 0; j < m; j++) tmp[i][j] = mat[i][j]; for (int k = 0; k < n; k++) { if (k != i) { int p = 0; for (int j = 0; j < m; j++) { tmp[k][j] = !tmp[i][j]; if (tmp[k][j] != mat[k][j]) p++; } p = min(p, m - p); cnt += p; } } ans = min(ans, cnt); } } if (ans <= k) cout << ans << endl; else cout << -1 << endl; exit(0); } int main() { cin >> n >> m >> k; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> mat[i][j]; if (n <= k && m <= k) solve1(); else solve2(); return 0; }
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#include <bits/stdc++.h> typedef struct smirror { int left, right, score; } mirror; int max(int a, int b) { return a > b ? a : b; } int shoot_in(double x, mirror a[]) { for (int i = 1; i <= a[0].score; ++i) if (a[i].left <= x && x <= a[i].right) return i; return -1; } int deal(int n, mirror A[], mirror B[], int hl, int hr) { int counter = 1, hx = hl, tag, score0 = 0; int h0; if (n % 2 == 1) h0 = hl + hr + (n - 1) * 100; else h0 = n * 100 + hl - hr; bool ba[105], bb[105]; memset(ba, 0, sizeof(ba)); memset(bb, 0, sizeof(bb)); double d; for (counter = 1; counter <= n; counter++) { d = (hx * 100000) / (1.0 * h0); if (counter % 2 == 1) { tag = shoot_in(d, B); if (tag >= 0 && !bb[tag]) { score0 += B[tag].score; bb[tag] = 1; } else { score0 = 0; break; } } else { tag = shoot_in(d, A); if (tag >= 0 && !ba[tag]) { score0 += A[tag].score; ba[tag] = 1; } else { score0 = 0; break; } } hx += 100; } return score0; } int main() { mirror mi[2][105]; int num[2] = {0, 0}, hl, hr, n; scanf( %d%d%d , &hl, &hr, &n); while (n--) { int score, set = 1; char t; scanf( %d %c , &score, &t); if (t == T ) set = 0; ++num[set]; scanf( %d %d , &mi[set][num[set]].left, &mi[set][num[set]].right); mi[set][num[set]].score = score; } mi[0][0].score = num[0], mi[1][0].score = num[1]; int ans = 0; for (int i = 1; i <= num[0] + num[1]; ++i) ans = max(ans, deal(i, mi[0], mi[1], hl, hr)); for (int i = 1; i <= num[0] + num[1]; ++i) ans = max(ans, deal(i, mi[1], mi[0], 100 - hl, 100 - hr)); printf( %d n , ans); return 0; }
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module ememory # (parameter AW = 32, // address width
parameter PW = 104, // packet width
parameter IDW = 12, // ID width
parameter DEPTH = 65536, // memory depth
parameter NAME = "emem", // instance name
parameter WAIT = 0, // enable random wait
parameter MON = 0 // enable monitor monitor
)
(// clk,reset
input clk,
input nreset,
input [IDW-1:0] coreid,
// incoming read/write
input access_in,
input [PW-1:0] packet_in,
output ready_out, //pushback
// back to mesh (readback data)
output reg access_out,
output [PW-1:0] packet_out,
input ready_in //pushback
);
//derived parameters
localparam DW = AW; //always the same
parameter MAW = $clog2(DEPTH);
//###############
//# LOCAL WIRES
//##############
wire [MAW-1:0] addr;
wire [63:0] din;
wire [63:0] dout;
wire en;
wire mem_rd;
reg [7:0] wen;
reg write_out;
reg [1:0] datamode_out;
reg [4:0] ctrlmode_out;
reg [AW-1:0] dstaddr_out;
wire [AW-1:0] srcaddr_out;
wire [AW-1:0] data_out;
reg [2:0] align_addr;
wire [DW-1:0] din_aligned;
wire [63:0] dout_aligned;
wire ready_random; //TODO: make random
wire ready_all;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
packet2emesh #(.AW(AW),
.PW(PW))
p2e (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
//Access-in
assign en = access_in & ready_all & ready_all;
assign mem_rd = (access_in & ~write_in & ready_all);
//Pushback Circuit (pass through problems?)
assign ready_all = (ready_random | ready_in);
assign readt_out = ready_all;// & access_in
//Address-in (shifted by three bits, 64 bit wide memory)
assign addr[MAW-1:0] = dstaddr_in[MAW+2:3];
//Shift up
assign din_aligned[DW-1:0] = (datamode_in[1:0]==2'b00) ? {(4){data_in[7:0]}} :
(datamode_in[1:0]==2'b01) ? {(2){data_in[15:0]}} :
data_in[31:0];
//Data-in (hardoded width)
assign din[63:0] =(datamode_in[1:0]==2'b11) ? {srcaddr_in[31:0],din_aligned[31:0]}:
{din_aligned[31:0],din_aligned[31:0]};
//Write mask
//TODO: make module
always@*
casez({write_in, datamode_in[1:0],dstaddr_in[2:0]})
//Byte
6'b100000 : wen[7:0] = 8'b00000001;
6'b100001 : wen[7:0] = 8'b00000010;
6'b100010 : wen[7:0] = 8'b00000100;
6'b100011 : wen[7:0] = 8'b00001000;
6'b100100 : wen[7:0] = 8'b00010000;
6'b100101 : wen[7:0] = 8'b00100000;
6'b100110 : wen[7:0] = 8'b01000000;
6'b100111 : wen[7:0] = 8'b10000000;
//Short
6'b10100? : wen[7:0] = 8'b00000011;
6'b10101? : wen[7:0] = 8'b00001100;
6'b10110? : wen[7:0] = 8'b00110000;
6'b10111? : wen[7:0] = 8'b11000000;
//Word
6'b1100?? : wen[7:0] = 8'b00001111;
6'b1101?? : wen[7:0] = 8'b11110000;
//Double
6'b111??? : wen[7:0] = 8'b11111111;
default : wen[7:0] = 8'b00000000;
endcase // casez ({write, datamode_in[1:0],addr_in[2:0]})
//Single ported memory
defparam mem.DW=64;
defparam mem.DEPTH=DEPTH;
oh_memory_sp mem(
// Inputs
.clk (clk),
.en (en),
.we (write_in),
.wem ({
{(8){wen[7]}},
{(8){wen[6]}},
{(8){wen[5]}},
{(8){wen[4]}},
{(8){wen[3]}},
{(8){wen[2]}},
{(8){wen[1]}},
{(8){wen[0]}}
}
),
.addr (addr[MAW-1:0]),
.din (din[63:0]),
.dout (dout[63:0]),
.vdd (1'b1),
.vddm (1'b1),
.memrepair(8'b0),
.memconfig(8'b0),
.bist_en (1'b0),
.bist_we (1'b0),
.bist_wem (64'b0),
.bist_addr({(MAW){1'b0}}),
.bist_din (64'b0)
);
//Outgoing transaction
always @ (posedge clk or negedge nreset)
if(!nreset)
access_out <=1'b0;
else
begin
access_out <= mem_rd;
write_out <= 1'b1;
align_addr[2:0] <= dstaddr_in[2:0];
datamode_out[1:0] <= datamode_in[1:0];
ctrlmode_out[4:0] <= ctrlmode_in[4:0];
dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
end
//Data alignment for readback
emesh_rdalign emesh_rdalign (// Outputs
.data_out (dout_aligned[63:0]),
// Inputs
.datamode (datamode_out[1:0]),
.addr (align_addr[2:0]),
.data_in (dout[63:0]));
assign srcaddr_out[AW-1:0] = (datamode_out[1:0]==2'b11) ? dout[63:32] : 32'b0;
assign data_out[31:0] = dout_aligned[31:0];
//Concatenate
emesh2packet #(.AW(AW),
.PW(PW))
e2p (
/*AUTOINST*/
// Outputs
.packet_out (packet_out[PW-1:0]),
// Inputs
.write_out (write_out),
.datamode_out (datamode_out[1:0]),
.ctrlmode_out (ctrlmode_out[4:0]),
.dstaddr_out (dstaddr_out[AW-1:0]),
.data_out (data_out[AW-1:0]),
.srcaddr_out (srcaddr_out[AW-1:0]));
`ifdef TARGET_SIM
generate
if(MON)
begin
emesh_monitor #(.PW(PW),
.INDEX(1),
.NAME(NAME),
.IDW(IDW)
)
emesh_monitor (.dut_access (access_in & write_in),
.dut_packet (packet_in[PW-1:0]),
.ready_in (ready_random),
/*AUTOINST*/
// Inputs
.clk (clk),
.nreset (nreset),
.coreid (coreid[IDW-1:0]));
end // if (MON)
endgenerate
`endif
//Random wait generator //TODO: make this a module
generate
if(WAIT)
begin
reg [8:0] ready_counter;
always @ (posedge clk or negedge nreset)
if(!nreset)
ready_counter[8:0] <= 'b0;
else
ready_counter[8:0] <= ready_counter+1'b1;
assign ready_random = (|ready_counter[5:0]);//(|ready_counter[3:0]);//1'b0;
end
else
begin
assign ready_random = 1'b0;
end // else: !if(WAIT)
endgenerate
endmodule // emesh_memory
// Local Variables:
// verilog-library-directories:("." "../dv" )
// End:
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#include <bits/stdc++.h> using namespace std; const int N = 300000; const long long INF = (1 << 30) - 1; int n; long long a[N + 9], sum[N + 9]; void into() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %lld , &a[i]); sum[i] = a[i] + sum[i - 1]; } } int ans; void Get_ans(int l, int r) { if (l <= 0 || r > n) return; for (; 2333;) { if ((a[l] ^ a[r]) == sum[r - 1] - sum[l]) ++ans; int le = 1, ri = n, len = n + 1; for (int mid; le <= ri;) { mid = le + ri >> 1; int nl = l - mid, nr = r + mid; if (nl <= 0 || nr > n) { len = mid; ri = mid - 1; continue; } sum[nr] - sum[nl - 1] - sum[r - 1] + sum[l] >= sum[r - 1] - sum[l] ? (len = mid, ri = mid - 1) : le = mid + 1; } l -= len; r += len; if (l <= 0 || r > n) return; if (sum[r - 1] - sum[l] > INF) return; } } void Get_ans() { for (int i = 1; i <= n; ++i) Get_ans(i - 1, i + 1); for (int i = 1; i < n; ++i) Get_ans(i - 1, i + 2); } void work() { Get_ans(); } void outo() { printf( %d n , ans); } int main() { int T = 1; for (; T--;) { into(); work(); outo(); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 4010; int n, a, b; vector<pair<int, int>> ans; deque<int> s[3]; inline void print() { if (n == 1248) for (pair<int, int> p : ans) printf( %d %d n , p.first, p.second); } inline void move(int tp, int c) { if (!c) return; if (tp == 0 && c > a) print(), puts( NO ), exit(0); if (tp == 1 && c > b) print(), puts( NO ), exit(0); if (c > s[tp].size()) print(), puts( NO ), exit(0); if (c + s[tp + 1].size() > n) print(), puts( NO ), exit(0); ans.push_back(make_pair(tp + 1, c)); for (int i = c - 1; i >= 0; --i) s[tp + 1].push_front(s[tp][i]); for (int i = c - 1; i >= 0; --i) s[tp].pop_front(); } inline bool judge(int tp, int c) { if (tp == 0 && c > a) return false; if (tp == 1 && c > b) return false; return true; } int main() { scanf( %d%d%d , &n, &a, &b); for (int i = 1, x; i <= n; ++i) scanf( %d , &x), s[0].push_back(x); while (s[2].size() != n) { if (!s[0].size() && !s[1].size()) print(), puts( NO ), exit(0); for (int i = 1; i < s[1].size(); ++i) if (s[1][i - 1] < s[1][i] - 1) print(), puts( NO ), exit(0); int flag = 0; for (int i = 0; i < s[0].size(); ++i) { if (s[0][i] == (n - s[2].size())) { for (int j = 0; j <= i; ++j) move(0, 1); flag = 1; } if (i < s[0].size() && s[0][i] + 1 < s[0][i + 1]) break; } if (flag) continue; for (int i = 0; i < s[1].size(); ++i) { if (s[1][i] == (n - s[2].size())) { move(1, i + 1); flag = 1; } } if (flag) continue; int l = 0, cnt = 1, r = s[0].size() - 1; vector<int> st; st.push_back(l); for (int i = 1; i < s[0].size(); ++i) { if (s[0][i - 1] + 1 < s[0][i]) { r = i - 1; break; } if (s[0][i] < s[0][i - 1]) ++cnt, st.push_back(i); } int mn = s[0][0], mx = s[0][0]; for (int i = l; i <= r; ++i) mn = min(mn, s[0][i]), mx = max(mx, s[0][i]); if (mx - mn + 1 > r - l + 1) move(0, r - l + 1); else { int mxlen = 0; for (int i = 0; i < st.size(); ++i) mxlen = max(mxlen, (i < st.size() - 1 ? st[i + 1] : r + 1) - st[i]); if (mxlen <= a && r - l + 1 <= b) { for (int i = 0; i < st.size(); ++i) move(0, (i < st.size() - 1 ? st[i + 1] : r + 1) - st[i]); } else { if (r - l + 1 > b) { if (cnt == 1) for (int i = 1; i <= r - l + 1; ++i) move(0, 1); else if (cnt > 2) move(0, r - l + 1); else { for (int i = l; i <= r; ++i) { if (judge(0, i - l + 1) && judge(0, r - i)) { if (i == st[1] - 1) continue; if (i != r) { if (i < st[1] - 1 && max(st[1] - i, r - l + 1 - (st[1] - i)) > b) continue; if (i >= st[1] && max(i - st[1] + 1, r - l + 1 - (i - st[1] + 1)) > b) continue; } if (i == r) { if (mxlen > a) continue; } move(0, i - l + 1); move(0, r - i); flag = 1; break; } } if (!flag) print(), puts( NO ), exit(0); } } else { if (cnt == 1) for (int i = 1; i <= r - l + 1; ++i) move(0, 1); else if (cnt > 2) print(), puts( NO ), exit(0); else { for (int i = l; i <= r; ++i) { if (judge(0, i - l + 1) && judge(0, r - i)) { move(0, i - l + 1); move(0, r - i); flag = 1; break; } } if (!flag) print(), puts( NO ), exit(0); } } } } } puts( YES ); printf( %d n , ans.size()); for (pair<int, int> p : ans) printf( %d %d n , p.first, p.second); return 0; }
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// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_dm_decoder(ck, reset_n, code, pattern);
parameter AFI_RATIO = "";
input ck;
input reset_n;
input [2:0] code;
output [2 * AFI_RATIO - 1 : 0] pattern;
reg [2:0] code_R;
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
code_R <= 3'b000;
end
else begin
code_R <= code;
end
end
assign pattern[0] = code_R[2];
assign pattern[1] = code_R[1];
generate
if (AFI_RATIO == 2) begin
assign pattern[2] = code_R[2] ^ code_R[0];
assign pattern[3] = code_R[1] ^ code_R[0];
end else if (AFI_RATIO == 4) begin
assign pattern[2] = code_R[2] ^ code_R[0];
assign pattern[3] = code_R[1] ^ code_R[0];
assign pattern[4] = code_R[2];
assign pattern[5] = code_R[1];
assign pattern[6] = code_R[2] ^ code_R[0];
assign pattern[7] = code_R[1] ^ code_R[0];
end
endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<long long, long long>; const long long INF = 2e18; template <class A, class B> ostream &operator<<(ostream &os, const pair<A, B> &p) { os << ( << p.first << , << p.second << ) ; return os; } template <class A> ostream &operator<<(ostream &os, const vector<A> &v) { os << { ; for (long long i = 0; i < (long long)v.size(); i++) if (i == 0) os << v[i]; else os << , << v[i]; os << } ; return os; } void dprint(string s) { cout << n ; } template <class T, class... U> void dprint(string s, T t, U... u) { long long w = s.find( , ); cout << [ << s.substr(0, w) << : << t << ] ; dprint(s.substr(w + 2, (long long)s.size() - w - 1), u...); } const long long N = 1e6 + 5; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; cin >> s; vector<pair<char, long long>> v; for (long long i = 0; i < (long long)(s).size();) { char c = s[i]; long long cnt = 0; while (s[i] == c and i < (long long)(s).size()) cnt++, i++; v.push_back({c, cnt}); } if ((long long)(v).size() % 2) { bool ok = 1; for (long long i = 0; i < (long long)(v).size() / 2; i++) { if (v[i].first == v[(long long)(v).size() - 1 - i].first and v[i].second + v[(long long)(v).size() - 1 - i].second >= 3) ; else ok = 0; } if (v[(long long)(v).size() / 2].second == 1) ok = 0; if (ok) cout << v[(long long)(v).size() / 2].second + 1; else cout << 0; } else { cout << 0; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long int k, v, n, m, ans, sum, sum1, l, r, i, j, mx, mn, c, z, x, y, a[111111], d[111111], t[111111]; string s, sos, ss; char ch; bool used[111111]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; cout << (n - 1) / 2; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O211AI_BEHAVIORAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o211ai (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_BEHAVIORAL_V
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#include <bits/stdc++.h> int main(int argc, char const *argv[]) { int n, i; scanf( %d , &n); getchar(); char row[n]; for (i = 0; i < n; ++i) { row[i] = getchar(); } if (n == 1 && row[0] == 0 ) { printf( No n ); return 0; } for (i = 1; i < n; ++i) { if (row[i] == 1 && row[i - 1] == 1 ) { printf( No n ); return 0; } } int cantCero = 0; if (row[0] == 0 ) { cantCero++; } for (i = 1; i < n; ++i) { if (row[i] == 0 ) { if (row[i - 1] == 0 ) { cantCero++; } else { cantCero = 1; } if (cantCero == 2 && (i == 1 || i == n - 1)) { printf( No n ); return 0; } if (cantCero == 3) { printf( No n ); return 0; } } else { cantCero = 0; } } printf( Yes n ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 105; bool dmy[MAXN][MAXN][MAXN]; void dfs(int d, int m, int y, int bd, int bm, int by) { if (dmy[bd][bm][by]) return; dmy[bd][bm][by] = true; if (bm > 12) return; if (bd > 31) return; if (!(by % 4) && bm == 2 && bd > 29) return; if ((by % 4) && bm == 2 && bd >= 29) return; if (y - by == 18) { if (bm < m) { puts( YES ); exit(0); } else { if (bm == m && bd <= d) { puts( YES ); exit(0); } } } if (y - by > 18) { puts( YES ); exit(0); } dfs(d, m, y, by, bd, bm); dfs(d, m, y, bm, by, bd); dfs(d, m, y, bd, by, bm); dfs(d, m, y, by, bm, bd); dfs(d, m, y, bm, bd, by); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int d, m, y, bd, bm, by; string s; cin >> s; d = (s[0] - 0 ) * 10 + (s[1] - 0 ); m = (s[3] - 0 ) * 10 + (s[4] - 0 ); y = (s[6] - 0 ) * 10 + (s[7] - 0 ); cin >> s; bd = (s[0] - 0 ) * 10 + (s[1] - 0 ); bm = (s[3] - 0 ) * 10 + (s[4] - 0 ); by = (s[6] - 0 ) * 10 + (s[7] - 0 ); dfs(d, m, y, by, bd, bm); dfs(d, m, y, bm, by, bd); dfs(d, m, y, bd, by, bm); dfs(d, m, y, by, bm, bd); dfs(d, m, y, bm, bd, by); dfs(d, m, y, bd, bm, by); puts( NO ); return 0; }
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// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
// web: http://www.terasic.com/
// email:
//
// ============================================================================
//Date: Thu Jul 11 11:26:45 2013
// ============================================================================
`define ENABLE_ADC
`define ENABLE_AUD
`define ENABLE_CLOCK2
`define ENABLE_CLOCK3
`define ENABLE_CLOCK4
`define ENABLE_CLOCK
`define ENABLE_DRAM
`define ENABLE_FAN
`define ENABLE_FPGA
`define ENABLE_GPIO
`define ENABLE_HEX
//`define ENABLE_HPS
`define ENABLE_IRDA
`define ENABLE_KEY
`define ENABLE_LEDR
`define ENABLE_PS2
`define ENABLE_SW
`define ENABLE_TD
`define ENABLE_VGA
module DE1_SOC_golden_top(
/* Enables ADC - 3.3V */
`ifdef ENABLE_ADC
output ADC_CONVST,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
`endif
/* Enables AUD - 3.3V */
`ifdef ENABLE_AUD
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
`endif
/* Enables CLOCK2 */
`ifdef ENABLE_CLOCK2
input CLOCK2_50,
`endif
/* Enables CLOCK3 */
`ifdef ENABLE_CLOCK3
input CLOCK3_50,
`endif
/* Enables CLOCK4 */
`ifdef ENABLE_CLOCK4
input CLOCK4_50,
`endif
/* Enables CLOCK */
`ifdef ENABLE_CLOCK
input CLOCK_50,
`endif
/* Enables DRAM - 3.3V */
`ifdef ENABLE_DRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
/* Enables FAN - 3.3V */
`ifdef ENABLE_FAN
output FAN_CTRL,
`endif
/* Enables FPGA - 3.3V */
`ifdef ENABLE_FPGA
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
`endif
/* Enables GPIO - 3.3V */
`ifdef ENABLE_GPIO
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
`endif
/* Enables HEX - 3.3V */
`ifdef ENABLE_HEX
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
`endif
/* Enables HPS */
`ifdef ENABLE_HPS
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N, //1.5V
output HPS_DDR3_CK_P, //1.5V
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif
/* Enables IRDA - 3.3V */
`ifdef ENABLE_IRDA
input IRDA_RXD,
output IRDA_TXD,
`endif
/* Enables KEY - 3.3V */
`ifdef ENABLE_KEY
input [3:0] KEY,
`endif
/* Enables LEDR - 3.3V */
`ifdef ENABLE_LEDR
output [9:0] LEDR,
`endif
/* Enables PS2 - 3.3V */
`ifdef ENABLE_PS2
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
`endif
/* Enables SW - 3.3V */
`ifdef ENABLE_SW
input [9:0] SW,
`endif
/* Enables TD - 3.3V */
`ifdef ENABLE_TD
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
`endif
/* Enables VGA - 3.3V */
`ifdef ENABLE_VGA
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS
`endif
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLXTP_BLACKBOX_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxtp (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTP_BLACKBOX_V
|
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