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#pragma GCC optimize( -Ofast , -funroll-all-loops ) #pragma GCC optimize(2) #pragma GCC optimize(3, Ofast , inline ) #include<bits/stdc++.h> using namespace std; typedef long long ll; int _; int n; int a[30010]; void solve(){ cin >> _; while(_--){ cin >> n; int cnt0 = 0, cnt1 = 0, cnt2 = 0; for(int i = 1; i <= n; i++){ cin >> a[i]; if(a[i] % 3 == 0){ cnt0++; } else if(a[i] % 3 == 1){ cnt1++; } else{ cnt2++; } } int need = n/3; if(cnt0 == need && cnt1 == need && cnt2 == need){ cout << 0 << n ; } else if(cnt0 > need && cnt1 > need && cnt2 < need){ cout << (cnt0-need)*2 + (cnt1-need) << n ; } else if(cnt0 < need && cnt1 > need && cnt2 > need){ cout << (cnt1-need)*2+(cnt2-need) << n ; } else if(cnt0 > need && cnt1 < need && cnt2 > need){ cout << (cnt0-need) + (cnt2-need)*2 << n ; } else if(cnt0 > need && cnt1 < need && cnt2 < need){ cout << (need-cnt1) + (need-cnt2)*2 << n ; } else if(cnt0 < need && cnt1 > need && cnt2 < need){ cout << (need-cnt2) + 2*(need-cnt0) << n ; } else if(cnt0 < need && cnt1 < need && cnt2 > need){ cout << (need-cnt0) + 2*(need-cnt1) << n ; } else if(cnt0 == need){ if(cnt1 > need && cnt2 < need){ cout << (cnt1-need) << n ; } else{ cout << 2*(cnt2-need) << n ; } } else if(cnt1 == need){ if(cnt0 > need && cnt2 < need){ cout << 2*(cnt0-need) << n ; } else{ cout << (cnt2-need) << n ; } } else if(cnt2 == need){ if(cnt0 > need && cnt1 < need){ cout << (cnt0 - need) << n ; } else{ cout << 2*(cnt1 - need) << n ; } } } return ; } int main(){ ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; void swap(int &a, int &b) { int temp = a; a = b; b = temp; } int main() { int n; cin >> n; int x[n], y[n], min_x = INT_MAX, max_y = INT_MIN; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i]; if (x[i] < min_x) min_x = x[i]; if (y[i] > max_y) max_y = y[i]; } int k = 0, res = -1; while (k < n) { if (x[k] == min_x) { if (y[k] == max_y) { res = k + 1; break; } } k++; } cout << res << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3_TB_V
`define SKY130_FD_SC_HD__NOR3_TB_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:45:01 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_xlconstant_0_0/RAT_xlconstant_0_0_stub.v
// Design : RAT_xlconstant_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module RAT_xlconstant_0_0(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[9:0]" */;
output [9:0]dout;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__O21AI_PP_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o21ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 201; set<int> graph[N]; map<pair<int, int>, int> edges; pair<int, int> bfs(int node) { int dist[N] = {0}; int vis[N] = {0}; queue<pair<int, int> > q; q.push({0, node}); while (!q.empty()) { int top = q.front().second; q.pop(); if (vis[top]) continue; vis[top] = true; for (set<int>::iterator it = graph[top].begin(); it != graph[top].end(); it++) { int to = *it; if (vis[to]) continue; dist[to] = dist[top] + 1; q.push({dist[to], to}); } } pair<int, int> temp = {node, 0}; for (int i = 1; i <= N; i++) { if (dist[i] > temp.second) { temp.second = dist[i]; temp.first = i; } } return temp; } int find_dia(int node) { pair<int, int> temp = bfs(node); temp = bfs(temp.first); return temp.second; } int main(void) { int n; cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; graph[u].insert(v); graph[v].insert(u); edges[{u, v}] = 1; } int ans = 0; for (map<pair<int, int>, int>::iterator it = edges.begin(); it != edges.end(); it++) { int u = (*it).first.first; int v = (*it).first.second; graph[u].erase(v); graph[v].erase(u); ans = max(ans, find_dia(v) * find_dia(u)); graph[u].insert(v); graph[v].insert(u); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int G = 3; const int MOD = 998244353; const int N = (1 << 15) + 5; int rev[N], w[N], inv_n; int bigMod(int a, int e, int mod) { if (e == -1) e = mod - 2; int ret = 1; while (e) { if (e & 1) ret = (long long)ret * a % mod; a = (long long)a * a % mod; e >>= 1; } return ret; } void prepare(int &n) { int sz = abs(31 - __builtin_clz(n)); int r = bigMod(G, (MOD - 1) / n, MOD); inv_n = bigMod(n, MOD - 2, MOD), w[0] = w[n] = 1; for (int i = 1; i < n; ++i) w[i] = (long long)w[i - 1] * r % MOD; for (int i = 1; i < n; ++i) rev[i] = (rev[i >> 1] >> 1) | ((i & 1) << (sz - 1)); } void ntt(int *a, int n, int dir) { for (int i = 1; i < n - 1; ++i) { if (i < rev[i]) swap(a[i], a[rev[i]]); } for (int m = 2; m <= n; m <<= 1) { for (int i = 0; i < n; i += m) { for (int j = 0; j < (m >> 1); ++j) { int &u = a[i + j], &v = a[i + j + (m >> 1)]; int t = (long long)v * w[dir ? n - n / m * j : n / m * j] % MOD; v = u - t < 0 ? u - t + MOD : u - t; u = u + t >= MOD ? u + t - MOD : u + t; } } } if (dir) for (int i = 0; i < n; ++i) a[i] = (long long)a[i] * inv_n % MOD; } int f_a[N], f_b[N]; vector<long long> multiply(vector<long long> a, vector<long long> b) { int sz = 1, n = a.size(), m = b.size(); while (sz < n + m - 1) sz <<= 1; prepare(sz); for (int i = 0; i < sz; ++i) f_a[i] = i < n ? a[i] : 0; for (int i = 0; i < sz; ++i) f_b[i] = i < m ? b[i] : 0; ntt(f_a, sz, 0); ntt(f_b, sz, 0); for (int i = 0; i < sz; ++i) f_a[i] = (long long)f_a[i] * f_b[i] % MOD; ntt(f_a, sz, 1); return vector<long long>(f_a, f_a + n + m - 1); } int n, k, q; long long a[N], b[N]; vector<long long> get(int lo, int hi) { if (lo == hi) return {b[lo], 1}; int mid = lo + hi >> 1; vector<long long> one = get(lo, mid); vector<long long> two = get(mid + 1, hi); return multiply(one, two); } int main() { cin >> n >> k; for (int i = 1; i <= n; ++i) scanf( %lld , a + i); cin >> q; while (q--) { long long cmd, x, l, r, p; scanf( %lld %lld %lld %lld , &cmd, &x, &l, &r); if (cmd == 1) { for (int i = 1; i <= n; ++i) { b[i] = a[i]; if (i == l) b[i] = r; } } else { scanf( %lld , &p); for (int i = 1; i <= n; ++i) { b[i] = a[i]; if (l <= i and i <= r) b[i] += p; } } for (int i = 1; i <= n; ++i) { b[i] = x - b[i], b[i] %= MOD; if (b[i] < 0) b[i] += MOD; } vector<long long> yo = get(1, n); printf( %lld n , yo[n - k]); } return 0; }
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_receiveFIFODataOut (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 8: 0] in_port;
input reset_n;
wire clk_en;
wire [ 8: 0] data_in;
wire [ 8: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {9 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10, inf = 15e8; int A[maxn], B[maxn], C[maxn], ANSA, ANSB, n, l, r; vector<int> ed; vector<pair<int, int> > v[maxn]; int SZ[maxn], MX; bool mark[maxn]; pair<int, int> val[2 * maxn]; void dfsS(int u, int par = -1) { SZ[u] = 1; for (pair<int, int> p : v[u]) { if (p.first != par && !mark[p.first]) dfsS(p.first, u), SZ[u] += SZ[p.first]; } } int dfsC(int u, int ss, int par = -1) { for (pair<int, int> p : v[u]) { if (p.first != par && !mark[p.first] && SZ[p.first] >= ss) return dfsC(p.first, ss, u); } return u; } void prep() { for (int i = 0; i < 2 * MX; i++) { val[i] = {-inf, -inf}; } } pair<int, int> ask(int f, int s) { s = min(s, MX - 1); f += MX; s += MX; pair<int, int> ans = {-inf, -inf}; while (f < s) { if (f & 1) ans = max(ans, val[f++]); if (s & 1) ans = max(ans, val[--s]); f >>= 1; s >>= 1; } return ans; } void add(int pos, pair<int, int> p) { pos += MX; while (pos > 0) { val[pos] = max(val[pos], p); pos >>= 1; } } void dfsadd(int u, int ln, int sm, int par) { add(ln, {sm, u}); for (pair<int, int> p : v[u]) { if (p.first != par && !mark[p.first]) dfsadd(p.first, ln + 1, sm + p.second, u); } } void dfsask(int u, int ln, int sm, int par) { pair<int, int> X = ask(max(0, l - ln), max(0, r - ln + 1)); if (X.first + sm >= 0) ANSA = X.second, ANSB = u; for (pair<int, int> p : v[u]) { if (p.first != par && !mark[p.first]) dfsask(p.first, ln + 1, sm + p.second, u); } } void solve(int u) { dfsS(u); MX = SZ[u] + 5; prep(); u = dfsC(u, SZ[u] / 2); add(0, {0, u}); mark[u] = 1; for (pair<int, int> p : v[u]) { if (!mark[p.first]) dfsask(p.first, 1, p.second, u), dfsadd(p.first, 1, p.second, u); } for (pair<int, int> p : v[u]) { if (!mark[p.first]) solve(p.first); } } bool okay(int num) { memset(mark, 0, sizeof mark); for (int i = 1; i <= n; i++) { v[i].clear(); } for (int i = 0; i < n - 1; i++) { v[A[i]].push_back({B[i], C[i] >= ed[num] ? 1 : -1}); v[B[i]].push_back({A[i], C[i] >= ed[num] ? 1 : -1}); } ANSA = ANSB = -1; solve(1); return ANSA != -1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> l >> r; for (int i = 0; i < n - 1; i++) { cin >> A[i] >> B[i] >> C[i]; ed.push_back(C[i]); } sort(ed.begin(), ed.end()); int l = 0, r = n - 2, ansa = -1, ansb = -1; while (l <= r) { int mid = (l + r) / 2; if (okay(mid)) ansa = ANSA, ansb = ANSB, l = mid + 1; else r = mid - 1; } cout << ansa << << ansb << endl; return 0; }
|
`ifndef ALU_V
`define ALU_V
`include "adder.v"
`include "multiplier.v"
`include "divider.v"
`include "shifter.v"
`define OP_NOP 4'b0000
`define OP_ADD 4'b0001
`define OP_SUB 4'b0010
`define OP_MUL 4'b0011
`define OP_DIV 4'b0100
`define OP_LEFT_SHIFTL 4'b0101
`define OP_LEFT_SHIFTA 4'b0110
`define OP_RIGHT_SHIFTL 4'b0111
`define OP_RIGHT_SHIFTA 4'b1000
// Simple single cycle adder
module alu(
input clk,
input reset,
input [31:0] i_a, // 1st operand
input [31:0] i_b, // 2nd operand
input [3:0] i_cmd, // command
output [31:0] o_result,
output o_valid, // result is valid
output o_ready // ready to take input
);
reg [31:0] reg_result;
reg reg_valid = 1'b0;
// ALU state machine macros
`define ST_RESET 2'h0
`define ST_READY 2'h1
`define ST_BUSY 2'h2
// begin in reset state
reg [1:0] reg_status = `ST_RESET;
// Synchronous reset
always @(posedge clk && reset) begin
reg_status <= `ST_READY;
end
// Assign outputs
assign o_ready = ((reg_status == `ST_READY) && !reset);
assign o_valid = (reg_valid && (reg_status == `ST_READY));
assign o_result = reg_result; //o_valid ? reg_result : 32'hx; // Ternary operator
// instants of various components of alu
// Adder
reg adder_cin;
wire adder_cout;
wire[31:0] adder_result;
adder alu_adder(.i_a(i_a), .i_b(i_b), .i_cin(adder_cin), .o_result(adder_result), .o_cout(adder_cout));
// Subtractor
reg subtractor_cin;
wire subtractor_cout;
wire[31:0] subtractor_result;
adder alu_subtractor(.i_a(i_a), .i_b(~i_b), .i_cin(subtractor_cin), .o_result(subtractor_result), .o_cout(subtractor_cout));
// Multiplier
reg multiplier_start = 1'b0;
wire[`WIDTH + `WIDTH - 1:0] multiplier_result;
wire multiplier_ready;
multiplier mul(
.start(multiplier_start),
.clk(clk),
.multiplier(i_a),
.multiplicand(i_b),
.product(multiplier_result),
.ready(multiplier_ready));
// Divider
reg divider_start = 1'b0;
wire[`WIDTH-1:0] divider_quotient, divider_remainder;
wire divider_ready;
divider div(
.start(divider_start),
.clk(clk),
.dividend(i_b),
.divisor(i_a),
.quotient(divider_quotient),
.remainder(divider_remainder),
.ready(divider_ready));
// Shifter
reg[`OPS-1:0] shifter_ops;
wire[`WIDTH-1:0] shifter_result;
reg shifter_start = 1'b0;
shifter shift(
.i_data(i_a),
.i_shift(i_b[`SHIFT_WIDTH-1:0]),
.i_op(shifter_ops),
.i_start(shifter_start),
.o_result(shifter_result));
// Main processing loop
always @(posedge clk && !reset) begin
case (reg_status)
`ST_READY: begin
reg_status <= `ST_BUSY;
case (i_cmd)
`OP_ADD: begin
adder_cin = 1'b0;
reg_result = adder_result;
end
`OP_SUB: begin
subtractor_cin = 1'b1;
reg_result = subtractor_result;
end
`OP_MUL: begin
multiplier_start = 1'b1;
reg_result = multiplier_result[`WIDTH-1:0];
end
`OP_DIV: begin
divider_start = 1'b1;
reg_result = divider_quotient;
end
`OP_LEFT_SHIFTL: begin
shifter_ops = `LEFT_SHIFTL;
shifter_start = 1'b1;
reg_result = shifter_result;
end
`OP_LEFT_SHIFTA: begin
shifter_ops = `LEFT_SHIFTA;
shifter_start = 1'b1;
reg_result = shifter_result;
end
`OP_RIGHT_SHIFTL: begin
shifter_ops = `RIGHT_SHIFTL;
shifter_start = 1'b1;
reg_result = shifter_result;
end
`OP_RIGHT_SHIFTA: begin
shifter_ops = `RIGHT_SHIFTA;
shifter_start = 1'b1;
reg_result = shifter_result;
end
endcase
end
`ST_BUSY: begin
if (divider_ready == 1'b1 && multiplier_ready == 1'b1) begin
reg_valid <= 1'b1;
reg_status <= `ST_READY;
end
shifter_start = 1'b0;
if (divider_ready == 1'b0)
divider_start = 1'b0;
if (multiplier_ready == 1'b0)
multiplier_start = 1'b0;
end
default: begin
$display("should not happen");
$finish;
end
endcase
end
endmodule
`endif
|
module top;
reg pass;
reg [7:0] vec;
integer off;
time delay;
event trig;
initial begin
pass = 1'b1;
delay = 1;
// Assign before the vector (constant delay).
vec = 8'hff;
off = -1;
vec[off] <= #1 1'b0;
#2 if (vec !== 8'hff) begin
$display("Failed the before vector (C) test, expected 8'hff, got %h",
vec);
pass = 1'b0;
end
// Assign after the vector (constant delay).
vec = 8'hff;
off = 8;
vec[off] <= #1 1'b0;
#2 if (vec !== 8'hff) begin
$display("Failed the after vector (C) test, expected 8'hff, got %h",
vec);
pass = 1'b0;
end
// Assign before the vector (variable delay).
vec = 8'hff;
off = -1;
vec[off] <= #(delay) 1'b0;
#2 if (vec !== 8'hff) begin
$display("Failed the before vector (V) test, expected 8'hff, got %h",
vec);
pass = 1'b0;
end
// Assign after the vector (variable delay).
vec = 8'hff;
off = 8;
vec[off] <= #(delay) 1'b0;
#2 if (vec !== 8'hff) begin
$display("Failed the after vector (V) test, expected 8'hff, got %h",
vec);
pass = 1'b0;
end
// Assign before the vector (event trigger).
vec = 8'hff;
off = -1;
vec[off] <= @(trig) 1'b0;
->trig;
#1 if (vec !== 8'hff) begin
$display("Failed the before vector (E) test, expected 8'hff, got %h",
vec);
pass = 1'b0;
end
// Assign after the vector (event trigger).
vec = 8'hff;
off = 8;
vec[off] <= @(trig) 1'b0;
->trig;
#1 if (vec !== 8'hff) begin
$display("Failed the after vector (V) test, expected 8'hff, got %h",
vec);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : four_port_ddr_ctrl.v
// Version : 0.1
// Author : Vipin.K
//
// Description: The four port DDR controller.
// Port 0 : System to DDR DMA controller
// Port 1 : User DDR PIO interface
// Port 2 : User stream arbitrator
// Port 3 : Ethernet
//--------------------------------------------------------------------------------
module four_port_ddr_ctrl(
input i_clk,
input i_rst,
//to ddr controller
output reg app_wdf_wren,
output reg [255:0]app_wdf_data,
output reg [31:0] app_wdf_mask,
output reg app_wdf_end,
output reg [31:0] app_addr,
output reg [2:0] app_cmd,
output reg app_en,
input app_rdy,
input app_wdf_rdy,
input [255:0] app_rd_data,
input app_rd_data_end,
input app_rd_data_valid,
//port0
input [255:0] i_port0_wr_data,
input [31:0] i_port0_wr_data_be,
input i_port0_wr_data_valid,
input [31:0] i_port0_wr_addr,
output reg o_port0_wr_ack,
input i_port0_rd,
input [31:0] i_port0_rd_addr,
output [255:0] o_port0_rd_data,
output reg o_port0_rd_ack,
output reg o_port0_rd_data_valid,
//port1
input [255:0] i_port1_wr_data,
input [31:0] i_port1_wr_data_be,
input i_port1_wr_data_valid,
input [31:0] i_port1_wr_addr,
input i_port1_rd,
output [255:0] o_port1_rd_data,
input [31:0] i_port1_rd_addr,
output reg o_port1_rd_data_valid,
output reg o_port1_wr_ack,
output reg o_port1_rd_ack,
//port2
input [255:0] i_port2_wr_data,
input [31:0] i_port2_wr_data_be,
input i_port2_wr_data_valid,
input [31:0] i_port2_wr_addr,
input i_port2_rd,
output [255:0] o_port2_rd_data,
input [31:0] i_port2_rd_addr,
output reg o_port2_rd_data_valid,
output reg o_port2_wr_ack,
output reg o_port2_rd_ack,
//port3
input [255:0] i_port3_wr_data,
input [31:0] i_port3_wr_data_be,
input i_port3_wr_data_valid,
input [31:0] i_port3_wr_addr,
input i_port3_rd,
output [255:0] o_port3_rd_data,
input [31:0] i_port3_rd_addr,
output reg o_port3_rd_data_valid,
output reg o_port3_wr_ack,
output reg o_port3_rd_ack
);
reg [1:0] cur_srvd_port;
reg [255:0] wr_data;
reg [31:0] wr_be;
reg [31:0] wr_addr;
reg [31:0] rd_addr;
reg data_avail;
reg rd_req;
reg rd_ack;
wire wr_ack;
wire [1:0] expected_buff;
reg track_buff_wr;
reg [1:0] track_data;
reg [2:0] state;
reg go_idle_flag;
reg app_wr_done;
reg app_en_done;
wire some_other_request;
assign o_port0_rd_data = app_rd_data;
assign o_port1_rd_data = app_rd_data;
assign o_port2_rd_data = app_rd_data;
assign o_port3_rd_data = app_rd_data;
assign some_other_request = i_port0_wr_data_valid|i_port1_wr_data_valid|i_port2_wr_data_valid|i_port3_wr_data_valid|i_port0_rd|i_port1_rd|i_port2_rd|i_port3_rd;
assign wr_ack = (((data_avail & app_wdf_rdy & app_rdy)|(data_avail & app_wr_done & app_rdy)|(data_avail & app_wdf_rdy & app_en_done)) & (state == WR_DATA1))|(data_avail & app_wdf_rdy & (state == WR_DATA2));
//assign wr_ack = (data_avail & app_wdf_rdy & app_rdy & (state == WR_DATA1))|(data_avail & app_wdf_rdy & (state == WR_DATA2));
localparam IDLE = 'd0,
WR_DATA1 = 'd1,
WR_DATA2 = 'd2,
RD_CMD = 'd3;
always @(*)
begin
case(cur_srvd_port)
2'b00:begin
data_avail <= i_port0_wr_data_valid;
wr_data <= i_port0_wr_data;
wr_be <= i_port0_wr_data_be;
wr_addr <= i_port0_wr_addr;
rd_addr <= i_port0_rd_addr;
rd_req <= i_port0_rd;
end
2'b01:begin
data_avail <= i_port1_wr_data_valid;
wr_data <= i_port1_wr_data;
wr_be <= i_port1_wr_data_be;
wr_addr <= i_port1_wr_addr;
rd_addr <= i_port1_rd_addr;
rd_req <= i_port1_rd;
end
2'b10:begin
data_avail <= i_port2_wr_data_valid;
wr_data <= i_port2_wr_data;
wr_be <= i_port2_wr_data_be;
wr_addr <= i_port2_wr_addr;
rd_addr <= i_port2_rd_addr;
rd_req <= i_port2_rd;
end
2'b11:begin
data_avail <= i_port3_wr_data_valid;
wr_data <= i_port3_wr_data;
wr_be <= i_port3_wr_data_be;
wr_addr <= i_port3_wr_addr;
rd_addr <= i_port3_rd_addr;
rd_req <= i_port3_rd;
end
endcase
end
always @(*)
begin
o_port0_wr_ack <= 1'b0;
o_port1_wr_ack <= 1'b0;
o_port2_wr_ack <= 1'b0;
o_port3_wr_ack <= 1'b0;
o_port0_rd_ack <= 1'b0;
o_port1_rd_ack <= 1'b0;
o_port2_rd_ack <= 1'b0;
o_port3_rd_ack <= 1'b0;
case(cur_srvd_port)
2'b00:begin
o_port0_rd_ack <= rd_ack;
o_port0_wr_ack <= wr_ack;
end
2'b01:begin
o_port1_rd_ack <= rd_ack;
o_port1_wr_ack <= wr_ack;
end
2'b10:begin
o_port2_rd_ack <= rd_ack;
o_port2_wr_ack <= wr_ack;
end
2'b11:begin
o_port3_rd_ack <= rd_ack;
o_port3_wr_ack <= wr_ack;
end
endcase
end
always @(posedge i_clk)
begin
if(i_rst)
begin
state <= IDLE;
app_wdf_wren <= 1'b0;
track_buff_wr <= 1'b0;
cur_srvd_port <= 2'b00;
app_wdf_end <= 1'b0;
app_en <= 1'b0;
app_wr_done <= 1'b0;
app_en_done <= 1'b0;
end
else
begin
case(state)
IDLE:begin
track_buff_wr <= 1'b0;
if(data_avail)
begin
state <= WR_DATA1;
app_wr_done <= 1'b1;
app_en_done <= 1'b1;
end
else if(rd_req)
begin
app_en <= 1'b1;
app_addr <= rd_addr;
app_cmd <= 3'b001;
track_data <= cur_srvd_port;
track_buff_wr <= 1'b1;
state <= RD_CMD;
rd_ack <= 1'b1;
end
else if(some_other_request)
cur_srvd_port <= cur_srvd_port + 1'b1;
end
WR_DATA1:begin
if(app_wdf_rdy)
begin
app_wdf_wren <= 1'b0;
app_wr_done <= 1'b1;
end
if(app_rdy)
begin
app_en <= 1'b0;
app_wdf_end <= 1'b0;
app_en_done <= 1'b1;
end
if((data_avail & app_wdf_rdy & app_rdy)|(data_avail & app_wr_done & app_rdy)|(data_avail & app_wdf_rdy & app_en_done))
begin
app_wdf_wren <= 1'b1;
app_wdf_data <= wr_data;
app_wdf_mask <= wr_be;
app_addr <= wr_addr;
state <= WR_DATA2;
app_wr_done <= 1'b0;
app_en_done <= 1'b0;
end
else if(app_wr_done & app_en_done)
begin
state <= IDLE;
end
end
WR_DATA2:begin
if(data_avail & app_wdf_rdy)
begin
app_wdf_wren <= 1'b1;
app_wdf_end <= 1'b1;
app_wdf_data <= wr_data;
app_wdf_mask <= wr_be;
app_en <= 1'b1;
app_cmd <= 3'b000;
state <= WR_DATA1;
end
else if(app_wdf_rdy)
begin
app_wdf_wren <= 1'b0;
end
end
RD_CMD:begin
track_buff_wr <= 1'b0;
rd_ack <= 1'b0;
if(app_rdy)
begin
app_en <= 1'b0;
track_buff_wr <= 1'b1;
track_data <= cur_srvd_port;
state <= IDLE;
end
end
endcase
end
end
always @(*)
begin
o_port0_rd_data_valid = 1'b0;
o_port1_rd_data_valid = 1'b0;
o_port2_rd_data_valid = 1'b0;
o_port3_rd_data_valid = 1'b0;
case(expected_buff)
2'b00:begin
o_port0_rd_data_valid = app_rd_data_valid;
end
2'b01:begin
o_port1_rd_data_valid = app_rd_data_valid;
end
2'b10:begin
o_port2_rd_data_valid = app_rd_data_valid;
end
2'b11:begin
o_port3_rd_data_valid = app_rd_data_valid;
end
endcase
end
track_fifo track_fifo (
.s_aclk(i_clk), // input s_aclk
.s_aresetn(~i_rst), // input s_aresetn
.s_axis_tvalid(track_buff_wr), // input s_axis_tvalid
.s_axis_tready(), // output s_axis_tready fifo_rdy
.s_axis_tdata({6'h00,track_data}), // input [7 : 0] s_axis_tdata
.m_axis_tvalid(), // output m_axis_tvalid
.m_axis_tready(app_rd_data_valid), // input m_axis_tready
.m_axis_tdata(expected_buff) // output [7 : 0] m_axis_tdata
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; string s[n]; map<string, int> m; set<string> k; int count = 0; for (int i = 0; i < n; i++) { cin >> s[i]; k.insert(s[i]); } for (int i = 0; i < n; i++) { if (m[s[i]] >= 1) { count++; int j = 0; while (k.find(s[i]) != k.end()) { s[i][3] = j + 0 ; j++; } } m[s[i]]++; k.insert(s[i]); } cout << count << endl; for (int i = 0; i < n; i++) cout << s[i] << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKMUX2_TB_V
`define SKY130_FD_SC_HDLL__CLKMUX2_TB_V
/**
* clkmux2: Clock mux.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkmux2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A0 = 1'b1;
#180 A1 = 1'b1;
#200 S = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A0 = 1'b0;
#320 A1 = 1'b0;
#340 S = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 S = 1'b1;
#540 A1 = 1'b1;
#560 A0 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 S = 1'bx;
#680 A1 = 1'bx;
#700 A0 = 1'bx;
end
sky130_fd_sc_hdll__clkmux2 dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKMUX2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_2_V
`define SKY130_FD_SC_HS__A2111O_2_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2111o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2111o_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_2_V
|
#include <bits/stdc++.h> using namespace std; const int block_size = 320; const long long mod = 1e9 + 7; const long long inf = 1e9 + 7; const long double eps = 1e-9; const double PI = atan(1) * 4; template <typename T> inline int sign(const T &a) { if (a < 0) return -1; if (a > 0) return 1; return 0; } string to_string(string s) { return + s + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto &x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } template <typename T, typename S> inline bool upmin(T &a, const S &b) { return a > b ? a = b, 1 : 0; } template <typename T, typename S> inline bool upmax(T &a, const S &b) { return a < b ? a = b, 1 : 0; } template <typename T> inline void in(T &x) { x = 0; T f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= f; } long long twop(int x) { return 1LL << x; } template <typename T> T MOD(T a, T m) { a %= m; if (a < 0) a += m; return a; } template <typename T> T inverse(T a, T m) { a = MOD(a, m); if (a <= 1) return a; return MOD((1 - inverse(m, a) * m) / a, m); } template <typename A, typename B> inline void in(A &x, B &y) { in(x); in(y); } template <typename A, typename B, typename C> inline void in(A &x, B &y, C &z) { in(x); in(y); in(z); } template <typename A, typename B, typename C, typename D> inline void in(A &x, B &y, C &z, D &d) { in(x); in(y); in(z); in(d); } template <typename T> T sqr(T x) { return x * x; } long long gcd(long long a, long long b) { while (b != 0) { a %= b; swap(a, b); } return a; } long long fast(long long a, long long b, long long mod) { long long ans = 1; while (b) { if (b & 1) { b--; ans = ans * a % mod; } else { a = a * a % mod; b /= 2; } } return ans % mod; } pair<long long, long long> operator-(const pair<long long, long long> &a, const pair<long long, long long> &b) { return make_pair(a.first - b.first, a.second - b.second); } long long cp(pair<long long, long long> o, pair<long long, long long> a, pair<long long, long long> b) { a = a - o; b = b - o; return a.first * b.second - a.second * b.first; } pair<long long, long long> process(pair<long long, long long> diff) { long long g = abs(gcd(diff.first, diff.second)); diff.first /= g; diff.second /= g; return diff; } template <int maxn, typename NUM> struct BIT { NUM s[maxn]; void init() { memset(s, 0, sizeof(s)); } BIT() { init(); } void update(int a, NUM value) { a++; while (a < maxn) { s[a] += value; a += ((a) & (-(a))); } } NUM query(int a) { NUM ans = 0; a++; while (a) { ans += s[a]; a -= ((a) & (-(a))); } return ans; } NUM query(int a, int b) { if (b < a) return 0; return query(b) - query(a - 1); } }; BIT<300010, long long> bit; namespace SOLVE { vector<vector<pair<long long, long long>>> vec; bool cmp(const pair<pair<long long, long long>, long long> &a, const pair<pair<long long, long long>, long long> &b) { return a.first.second < b.first.second; } long long ans[300010]; void main() { int n; in(n); vec.resize(n + 1); for (long long i = 1; i < n + 1; i++) { int c; in(c); vector<pair<long long, long long>> v; for (long long j = 0; j < c; j++) { pair<long long, long long> x; in(x.first, x.second); v.push_back(x); } v.push_back(v[0]); for (long long j = 1; j < c + 1; j++) { vec[i].push_back(process(v[j] - v[j - 1])); } } int q; in(q); vector<pair<pair<long long, long long>, long long>> query(q); for (long long i = 0; i < q; i++) { in(query[i].first.first, query[i].first.second); query[i].second = i; } sort(begin(query), end(query), cmp); int cur = 0; map<pair<long long, long long>, int> occ; for (auto q : query) { while (cur < q.first.second) { ++cur; for (auto v : vec[cur]) { bit.update(occ[v], -1); bit.update(cur, 1); occ[v] = cur; } } ans[q.second] = bit.query(q.first.first, q.first.second); } {}; for (long long i = 0; i < q; i++) cout << ans[i] << endl; } } // namespace SOLVE signed main() { int t = 1; while (t--) { SOLVE::main(); } return 0; }
|
#include <bits/stdc++.h> int main(void) { int t, h, m; scanf( %d , &t); while (t--) { scanf( %d%d , &h, &m); printf( %d n , (23 - h) * 60 + (60 - m)); } return 0; }
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* Buffer GMII cycles and convert to TBI - send SGMII autoneg cycles
*/
module sgmii_tx_buf
(
input clk_125mhz,
input rst,
input tbi_tx_clk,
input sgmii_autoneg_start,
input sgmii_autoneg_ack,
input sgmii_autoneg_idle,
input sgmii_autoneg_done,
input [7:0] gmii_txd,
input gmii_tx_en,
input gmii_tx_err,
output [7:0] tx_byte,
output tx_is_k
);
parameter LINK_TIMER = 16'd40000;
//
// TX buffer write
//
wire [8:0] fifo_in = {gmii_tx_err, gmii_txd};
wire fifo_push = gmii_tx_en && sgmii_autoneg_done;
wire [8:0] fifo_out;
wire fifo_pop;
wire fifo_empty;
sgmii_fifo sgmii_fifo
(
.rst_in(rst),
.clk_in(clk_125mhz),
.clk_out(tbi_tx_clk),
.fifo_in(fifo_in),
.push(fifo_push),
.full(),
.fifo_out(fifo_out),
.pop(fifo_pop),
.empty(fifo_empty)
);
//
// Autogen sequence
//
reg [4:0] autoneg_state;
wire [4:0] autoneg_state_next = autoneg_state + 5'd1;
reg [15:0] autoneg_cnt;
reg [8:0] autoneg_out;
reg autoneg_done;
always @ (posedge tbi_tx_clk or posedge rst)
if (rst)
begin
autoneg_state <= 5'd0;
autoneg_cnt <= 16'd0;
autoneg_out <= 9'd0;
autoneg_done <= 1'b0;
end
else
case (autoneg_state)
// LinkTimer x CFG1/2 of zero
5'd0:
begin
autoneg_done <= 1'b0;
if (!sgmii_autoneg_start) autoneg_cnt <= 16'd0;
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b1, 8'hBC};
end
5'd1:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'hB5};
end
5'd2:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'h00};
end
5'd3:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'h00};
end
5'd4:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b1, 8'hBC};
end
5'd5:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'h42};
end
5'd6:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'h00};
autoneg_cnt <= autoneg_cnt + 16'd1;
end
5'd7:
begin
autoneg_state <= (autoneg_cnt == LINK_TIMER) ? autoneg_state_next : 5'd0;
autoneg_out <= {1'b0, 8'h00};
end
// Send non-ACK with CONFIG_REG
5'd8:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b1, 8'hBC};
end
5'd9:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'hB5};
end
5'd10:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'h01};
end
5'd11:
begin
autoneg_state <= (!sgmii_autoneg_start) ? 5'd0 : autoneg_state_next;
autoneg_out <= {1'b0, 8'h00};
end
5'd12:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b1, 8'hBC};
end
5'd13:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'h42};
end
5'd14:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'h01};
end
5'd15:
begin
autoneg_state <= (sgmii_autoneg_ack) ? autoneg_state_next : 5'd8;
autoneg_out <= {1'b0, 8'h00};
end
// Send ACK with CONFIG_REG
5'd16:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b1, 8'hBC};
end
5'd17:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'hB5};
end
5'd18:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'h01};
end
5'd19:
begin
autoneg_state <= (!sgmii_autoneg_start) ? 5'd0 : autoneg_state_next;
autoneg_out <= {1'b0, 8'h40};
end
5'd20:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b1, 8'hBC};
end
5'd21:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'h42};
end
5'd22:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'h01};
autoneg_cnt <= autoneg_cnt + 12'd1;
end
5'd23:
begin
autoneg_state <= (sgmii_autoneg_idle) ? autoneg_state_next : 5'd16;
autoneg_out <= {1'b0, 8'h40};
end
// Send IDLE
5'd24:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b1, 8'hBC};
end
5'd25:
begin
autoneg_state <= (!sgmii_autoneg_start) ? 5'd0 : autoneg_state_next;
autoneg_out <= {1'b0, 8'hC5};
end
5'd26:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b1, 8'hBC};
end
5'd27:
begin
autoneg_state <= autoneg_state_next;
autoneg_out <= {1'b0, 8'h50};
end
5'd28:
begin
autoneg_done <= 1'b1;
if (!sgmii_autoneg_start || !sgmii_autoneg_ack || !sgmii_autoneg_ack)
autoneg_state <= 5'd0;
end
default: autoneg_state <= 5'd0;
endcase
//
// Encapsulation
//
reg [2:0] encap_state;
reg [8:0] encap_out;
assign fifo_pop = (encap_state == 3'd5);
always @ (posedge tbi_tx_clk or posedge rst)
if (rst)
encap_state <= 3'd0;
else if (autoneg_state == 5'd27)
encap_state <= 3'd0;
else
case (encap_state)
3'd3: encap_state <= (!fifo_empty) ? 3'd4 : 3'd0;
3'd5: encap_state <= (fifo_empty) ? 3'd6 : 3'd5;
3'd6: encap_state <= 3'd0;
default: encap_state <= encap_state + 3'd1;
endcase
always @ (posedge tbi_tx_clk or posedge rst)
if (rst)
encap_out <= 9'd0;
else
case (encap_state)
3'd0: encap_out <= {1'b1, 8'hBC};
3'd1: encap_out <= {1'b0, 8'hC5};
3'd2: encap_out <= {1'b1, 8'hBC};
3'd3: encap_out <= {1'b0, 8'h50};
3'd4: encap_out <= {1'b1, 8'hFB};
3'd5: encap_out <= (fifo_empty) ? {1'b1, 8'hFD} :
(fifo_out[8]) ? {1'b1, 8'hFE} : {1'b0, fifo_out[7:0]};
3'd6: encap_out <= {1'b1, 8'hF7};
default: encap_out <= 9'd0;
endcase
//
// TBI out
//
assign tx_byte = (autoneg_done) ? encap_out[7:0] : autoneg_out[7:0];
assign tx_is_k = (autoneg_done) ? encap_out[8] : autoneg_out[8];
endmodule
|
#include <bits/stdc++.h> using namespace std; int cnt[1005]; vector<long long int> csum; string str; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; int m; cin >> n >> m; long long int x; cin >> x; csum.push_back(x); for (int i = 1; i < n; i++) { cin >> x; long long int y = x + csum[i - 1]; csum.push_back(y); } for (int i = 0; i < m; i++) { long long int y; cin >> y; int lo = lower_bound(csum.begin(), csum.end(), y) - csum.begin(); if (lo + 1 == 1) { cout << lo + 1 << << y << endl; continue; } cout << lo + 1 << << y - csum[lo - 1] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; t = 1; while (t--) { int n, k, mx = 0, mn = 101, j; cin >> n >> k; int a[n]; for (int i = 0; i < n; i += 1) { cin >> a[i]; mx = max(mx, a[i]); mn = min(mn, a[i]); } if (mx - mn > k) cout << NO ; else { cout << YES << n ; for (int i = 0; i < n; i += 1) { for (j = 0; j < a[i] - 1; j++) { cout << (j % k) + 1 << ; } cout << (j % k) + 1 << n ; } } } return 0; }
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_1g
*/
module test_eth_mac_1g;
// Parameters
parameter DATA_WIDTH = 8;
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_PTP_TS_ENABLE = 0;
parameter TX_PTP_TS_WIDTH = 96;
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE;
parameter TX_PTP_TAG_WIDTH = 16;
parameter RX_PTP_TS_ENABLE = 0;
parameter RX_PTP_TS_WIDTH = 96;
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1;
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg [DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg [TX_USER_WIDTH-1:0] tx_axis_tuser = 0;
reg [DATA_WIDTH-1:0] gmii_rxd = 0;
reg gmii_rx_dv = 0;
reg gmii_rx_er = 0;
reg [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts = 0;
reg [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts = 0;
reg rx_clk_enable = 1;
reg tx_clk_enable = 1;
reg rx_mii_select = 0;
reg tx_mii_select = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire tx_axis_tready;
wire [DATA_WIDTH-1:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_axis_tuser;
wire [DATA_WIDTH-1:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts;
wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
wire tx_axis_ptp_ts_valid;
wire tx_start_packet;
wire tx_error_underflow;
wire rx_start_packet;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
tx_axis_tdata,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
tx_ptp_ts,
rx_ptp_ts,
rx_clk_enable,
tx_clk_enable,
rx_mii_select,
tx_mii_select,
ifg_delay
);
$to_myhdl(
tx_axis_tready,
rx_axis_tdata,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
gmii_txd,
gmii_tx_en,
gmii_tx_er,
tx_axis_ptp_ts,
tx_axis_ptp_ts_tag,
tx_axis_ptp_ts_valid,
tx_start_packet,
tx_error_underflow,
rx_start_packet,
rx_error_bad_frame,
rx_error_bad_fcs
);
// dump file
$dumpfile("test_eth_mac_1g.lxt");
$dumpvars(0, test_eth_mac_1g);
end
eth_mac_1g #(
.DATA_WIDTH(DATA_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.TX_PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.TX_USER_WIDTH(TX_USER_WIDTH),
.RX_USER_WIDTH(RX_USER_WIDTH)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.tx_ptp_ts(tx_ptp_ts),
.rx_ptp_ts(rx_ptp_ts),
.tx_axis_ptp_ts(tx_axis_ptp_ts),
.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.rx_clk_enable(rx_clk_enable),
.tx_clk_enable(tx_clk_enable),
.rx_mii_select(rx_mii_select),
.tx_mii_select(tx_mii_select),
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue <= @ event_identifier constant
// D: There is a dependency here between this and event keyword and ->
module main ;
reg [3:0] value1 ;
event event_ident ;
initial
begin
# 5 -> event_ident ;
end
initial
begin
if(value1 !== 4'bxxxx)
$display("FAILED - always reg_lvalue <= @ event_identifier constant\n");
#10 ;
if(value1 != 4'h5)
$display("FAILED - always reg_lvalue <= @ event_identifier constant\n");
else
begin
$display("PASSED\n");
$finish ;
end
end
always value1 <= @ event_ident 4'h5;
endmodule
|
#include<bits/stdc++.h> #define For(i,x,y) for (register int i=(x);i<=(y);i++) #define FOR(i,x,y) for (register int i=(x);i<(y);i++) #define Dow(i,x,y) for (register int i=(x);i>=(y);i--) #define Debug(v) for (auto i:v) cout<<i<< ;puts( ) #define mp make_pair #define fi first #define se second #define pb push_back #define ep emplace_back #define siz(x) ((int)(x).size()) #define all(x) (x).begin(),(x).end() #define fil(a,b) memset((a),(b),sizeof(a)) using namespace std; typedef long long ll; typedef unsigned long long ull; typedef pair<int,int> pa; typedef pair<ll,ll> PA; typedef vector<int> poly; inline ll read(){ ll x=0,f=1;char c=getchar(); while ((c< 0 ||c> 9 )&&(c!= - )) c=getchar(); if (c== - ) f=-1,c=getchar(); while (c>= 0 &&c<= 9 ) x=x*10+c- 0 ,c=getchar(); return x*f; } const int N = 5010; int n,p[N]; pa a[N]; inline pa operator - (pa a,pa b){ return mp(a.fi-b.fi,a.se-b.se); } inline bool check(pa a,pa b,pa c){ pa A=a-b,B=c-b; return (1ll*A.fi*B.fi+1ll*A.se*B.se)>0; } int main(){ n=read(); For(i,1,n) a[i].fi=read(),a[i].se=read(),p[i]=i; For(i,3,n){ Dow(j,i,3) if (!check(a[p[j-2]],a[p[j-1]],a[p[j]])){ swap(p[j],p[j-1]); } } For(i,1,n) printf( %d ,p[i]); }
|
// a barrel shifter to satisfy the single clock cycle constraint
// and yet support the multibit shift operation
// @requires: A 32-bit data input, a 32-bit control input;
// @returns: A 32-bit left shifted output to support shift by 7
module shiftll (busSLL, busA, sel, zSLL, oSLL, cSLL, nSLL);
output [31:0] busSLL;
input [31:0] busA, sel;
output zSLL, nSLL;
output reg oSLL, cSLL;
assign busSLL = busA << sel[2:0];
assign zSLL = ~|busSLL[31:0];
assign nSLL = busSLL[31];
always @(*) begin
if (sel[2:0] == 3'b0) begin
cSLL = 1'b0;
oSLL = 1'b0;
end else if (sel[2:0] == 3'b1) begin
cSLL = busSLL[31];
oSLL = busSLL[31];
end else if (sel[2:0] == 3'b10) begin
cSLL = busSLL[30];
oSLL = |busSLL[31:30];
end else if (sel[2:0] == 3'b11) begin
cSLL = busSLL[29];
oSLL = |busSLL[31:29];
end else if (sel[2:0] == 3'b100) begin
cSLL = busSLL[28];
oSLL = |busSLL[31:28];
end else if (sel[2:0] == 3'b101) begin
cSLL = busSLL[27];
oSLL = |busSLL[31:27];
end else if (sel[2:0] == 3'b110) begin
cSLL = busSLL[26];
oSLL = |busSLL[31:26];
end else begin
cSLL = busSLL[25];
oSLL = |busSLL[31:25];
end
end
endmodule
|
/*
* lattice gas autmaton progation
*/
module cppg
(
input CLK,
input RST_X,
input PPGRD,
input PPGCL,
input [9:0] C_VRAMADR_X,
input [13:0] C_VRAMADR_Y,
input [9:0] dsizx,
input [9:0] dsizy,
input rdata_valid,
input vram_ack,
input [63:0] rdata,
output [63:0] calc_data,
output reg [7:0] addr_x
);
/* address for x */
reg [8:0] addr_y;
always @ ( negedge RST_X or posedge CLK ) begin
if ( ~RST_X )
addr_x <= 8'd0;
else if ( PPGCL == 0 && PPGRD == 0 )
addr_x <= 8'd0;
else if ( addr_x == ( dsizx[7:0] ))
addr_x <= 8'd0;
else if ( PPGRD && rdata_valid )
addr_x <= addr_x + 8'd1;
else if ( PPGCL )
addr_x <= C_VRAMADR_X[7:0] + 8'd1;
end
wire [1:0] C_BLT;
modulus3 u_modulus3( C_VRAMADR_Y[8:0], C_BLT );
/* Xilinx Block Memory */
wire blt0_we;
wire blt1_we;
wire blt2_we;
wire [7:0] blt0_addr;
wire [7:0] blt1_addr;
wire [7:0] blt2_addr;
wire [63:0] blt00_out;
wire [63:0] blt01_out;
wire [63:0] blt02_out;
wire [63:0] blt10_out;
wire [63:0] blt11_out;
wire [63:0] blt12_out;
wire [63:0] blt20_out;
wire [63:0] blt21_out;
wire [63:0] blt22_out;
/* address generator */
function [7:0] GEN_ADDR;
input [1:0] I;
input CL;
input RD;
input [7:0] C_X;
begin
if ( RD == 1 )
GEN_ADDR = C_X;
else if ( CL == 1 && I == 2'd0 )
GEN_ADDR = C_X - 1;
else if ( CL == 1 && I == 2'd1 )
GEN_ADDR = C_X;
else if ( CL == 1 && I == 2'd2 )
GEN_ADDR = C_X + 1;
else
GEN_ADDR = C_X;
end
endfunction
assign blt0_addr = GEN_ADDR( 2'd0, PPGCL, PPGRD, addr_x );
assign blt1_addr = GEN_ADDR( 2'd1, PPGCL, PPGRD, addr_x );
assign blt2_addr = GEN_ADDR( 2'd2, PPGCL, PPGRD, addr_x );
// BLT0
bram_64_256depth BLT00
(
.addra (blt0_addr),
.dina (rdata),
.wea (blt0_we),
.ssra (~RST_X),
.clka (CLK),
.douta (blt00_out)
);
bram_64_256depth BLT01
(
.addra (blt1_addr),
.dina (rdata),
.wea (blt0_we),
.ssra (~RST_X),
.clka (CLK),
.douta (blt01_out)
);
bram_64_256depth BLT02
(
.addra (blt2_addr),
.dina (rdata),
.wea (blt0_we),
.ssra (~RST_X),
.clka (CLK),
.douta (blt02_out)
);
// BLT1
bram_64_256depth BLT10
(
.addra (blt0_addr),
.dina (rdata),
.wea (blt1_we),
.ssra (~RST_X),
.clka (CLK),
.douta (blt10_out)
);
bram_64_256depth BLT11
(
.addra (blt1_addr),
.dina (rdata),
.wea (blt1_we),
.ssra (~RST_X),
.clka (CLK),
.douta (blt11_out)
);
bram_64_256depth BLT12
(
.addra (blt2_addr),
.dina (rdata),
.wea (blt1_we),
.ssra (~RST_X),
.clka (CLK),
.douta (blt12_out)
);
// BLT2
bram_64_256depth BLT20
(
.addra (blt0_addr),
.dina (rdata),
.wea (blt2_we),
.ssra (~RST_X),
.clka (CLK),
.douta (blt20_out)
);
bram_64_256depth BLT21
(
.addra (blt1_addr),
.dina (rdata),
.wea (blt2_we),
.ssra (~RST_X),
.clka (CLK),
.douta (blt21_out)
);
bram_64_256depth BLT22
(
.addra (blt2_addr),
.dina (rdata),
.wea (blt2_we),
.ssra (~RST_X),
.clka (CLK),
.douta (blt22_out)
);
/* write enable generator
* - use when writing rdata to (BLT00, BLT01, BLT02), ...
*/
function GEN_EN;
input [1:0] C_BLT;
input [1:0] J;
input RD;
input valid;
begin
GEN_EN = ( C_BLT == J ) ? ( RD && valid ): 0;
end
endfunction
assign blt0_we = GEN_EN( C_BLT, 2'd0, PPGRD, rdata_valid );
assign blt1_we = GEN_EN( C_BLT, 2'd1, PPGRD, rdata_valid );
assign blt2_we = GEN_EN( C_BLT, 2'd2, PPGRD, rdata_valid );
/* propagation calc module */
// set blt[0-2][0-2]_out to BLT0, BLT1, BLT2 by C_BLT
function [63:0] GET_V;
input [1:0] J;
input [1:0] C_BLT;
input [63:0] blt0; // j - 1
input [63:0] blt1; // j
input [63:0] blt2; // j + 1
begin
if ( C_BLT == 2'd0 && J == 2'd0 )
GET_V = blt2;
else if ( C_BLT == 2'd0 && J == 2'd1 )
GET_V = blt0;
else if ( C_BLT == 2'd0 && J == 2'd2 )
GET_V = blt1;
else if ( C_BLT == 2'd1 && J == 2'd0 )
GET_V = blt1;
else if ( C_BLT == 2'd1 && J == 2'd1 )
GET_V = blt2;
else if ( C_BLT == 2'd1 && J == 2'd2 )
GET_V = blt0;
else if ( C_BLT == 2'd2 && J == 2'd0 )
GET_V = blt0;
else if ( C_BLT == 2'd2 && J == 2'd1 )
GET_V = blt1;
else if ( C_BLT == 2'd2 && J == 2'd2 )
GET_V = blt2;
else
GET_V = 64'd0;
end
endfunction
ltcppg u_ltcppg
(
.v0 ( GET_V( 2'd0, C_BLT, blt00_out, blt10_out, blt20_out) ),
.v1 ( GET_V( 2'd0, C_BLT, blt01_out, blt11_out, blt21_out) ),
.v2 ( GET_V( 2'd0, C_BLT, blt02_out, blt12_out, blt22_out) ),
.v3 ( GET_V( 2'd1, C_BLT, blt00_out, blt10_out, blt20_out) ),
.v4 ( GET_V( 2'd1, C_BLT, blt01_out, blt11_out, blt21_out) ),
.v5 ( GET_V( 2'd1, C_BLT, blt02_out, blt12_out, blt22_out) ),
.v6 ( GET_V( 2'd2, C_BLT, blt00_out, blt10_out, blt20_out) ),
.v7 ( GET_V( 2'd2, C_BLT, blt01_out, blt11_out, blt21_out) ),
.v8 ( GET_V( 2'd2, C_BLT, blt02_out, blt12_out, blt22_out) ),
.out_data ( calc_data )
);
endmodule
|
//
// Paul Gao 02/2021
//
// This module handles the flow control (with incoming token clock) of
// source-synchronous communication interface.
//
// data_i and data_o are both synchronous to clk_i and have zero-cycle latency.
//
module bsg_link_source_sync_upstream_sync
#(parameter `BSG_INV_PARAM(width_p )
,parameter lg_fifo_depth_p = 3
,parameter lg_credit_to_token_decimation_p = 0
,parameter bypass_twofer_fifo_p = 0
)
(// control signals
input io_clk_i
,input io_link_reset_i
,input async_token_reset_i
// input from core
,input io_v_i
,input [width_p-1:0] io_data_i
,output io_ready_and_o
// output to PHY
,output io_v_o
,output [width_p-1:0] io_data_o
,input token_clk_i
);
logic io_fifo_v, io_fifo_ready;
logic [width_p-1:0] io_fifo_data;
// MBT: we insert a two-element fifo here to
// decouple the async fifo logic which can be on the critical
// path in some cases. possibly this is being overly conservative
// and may introduce too much latency. but certainly in the
// case of the bsg_comm_link code, it is necessary.
// fixme: possibly make it a parameter as to whether we instantiate
// this fifo
if (bypass_twofer_fifo_p == 0)
begin: twofer
bsg_two_fifo
#(.width_p(width_p)
) twofer_fifo
(.clk_i (io_clk_i)
,.reset_i(io_link_reset_i)
,.ready_o(io_ready_and_o)
,.data_i (io_data_i)
,.v_i (io_v_i)
,.v_o (io_fifo_v)
,.data_o (io_fifo_data)
,.yumi_i (io_fifo_v & io_fifo_ready)
);
end
else
begin: no_twofer
// keep async_fifo isolated when reset is asserted
assign io_fifo_v = io_v_i;
assign io_fifo_data = io_data_i;
assign io_ready_and_o = (io_link_reset_i)? 1'b1 : io_fifo_ready;
end
// asserted when fifo has valid data and token credit is available
logic io_v_n;
assign io_v_o = (io_link_reset_i)? '0 : io_v_n;
assign io_data_o = (io_link_reset_i | ~io_v_n)? '0 : io_fifo_data;
// we need to track whether the credits are coming from
// posedge or negedge tokens.
// high bit indicates which counter we are grabbing from
logic [lg_credit_to_token_decimation_p+1-1:0] io_token_alternator_r;
// Increase token alternator when dequeue from async fifo
bsg_counter_clear_up
#(.max_val_p({(lg_credit_to_token_decimation_p+1){1'b1}})
,.init_val_p(0) // this will start us on the posedge token
,.disable_overflow_warning_p(1) // Allow overflow for this counter
)
token_alt
(.clk_i (io_clk_i)
,.reset_i(io_link_reset_i)
,.clear_i(1'b0)
,.up_i (io_v_n)
,.count_o(io_token_alternator_r)
);
// high bit set means we have exceeded number of posedge credits
// and are doing negedge credits
wire io_on_negedge_token = io_token_alternator_r[lg_credit_to_token_decimation_p];
logic io_negedge_credits_avail, io_posedge_credits_avail;
wire io_credit_avail = io_on_negedge_token
? io_negedge_credits_avail
: io_posedge_credits_avail;
// we send if we have both data to send and credits to send with
assign io_v_n = io_credit_avail & io_fifo_v;
assign io_fifo_ready = (io_link_reset_i)? 1'b1 : io_credit_avail;
wire io_negedge_credits_deque = io_v_n & io_on_negedge_token;
wire io_posedge_credits_deque = io_v_n & ~io_on_negedge_token;
// **********************************************
// token channel
//
// these are tokens coming from off chip that need to
// cross into the io clock domain.
//
// note that we are a little unconventional here; we use the token
// itself as a clock. this because we don't know the phase of the
// token signal coming in.
//
// we count both edges of the token separately, and assume that they
// will alternate in lock-step. we use two separate counters to do this.
//
// an alternative would be to use
// dual-edged flops, but they are not available in most ASIC libraries
// and although you can synthesize these out of XOR'd flops, they
// violate the async maxim that all signals crossing clock boundaries
// must come from a launch flop.
bsg_async_credit_counter
#(// half the credits will be positive edge tokens
.max_tokens_p(2**(lg_fifo_depth_p-1-lg_credit_to_token_decimation_p))
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.count_negedge_p(1'b0)
// we enable extra margin in case downstream module wants more tokens
,.extra_margin_p(0)
,.start_full_p(1)
,.use_async_w_reset_p(1'b1)
) pos_credit_ctr
(
.w_clk_i (token_clk_i)
,.w_inc_token_i(1'b1)
,.w_reset_i(async_token_reset_i)
// the I/O clock domain is responsible for tabulating tokens
,.r_clk_i (io_clk_i )
,.r_reset_i (io_link_reset_i )
,.r_dec_credit_i (io_posedge_credits_deque)
,.r_infinite_credits_i(1'b0 )
,.r_credits_avail_o (io_posedge_credits_avail)
);
bsg_async_credit_counter
#(// half the credits will be negative edge tokens
.max_tokens_p(2**(lg_fifo_depth_p-1-lg_credit_to_token_decimation_p))
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.count_negedge_p(1'b1)
// we enable extra margin in case downstream module wants more tokens
,.extra_margin_p(0)
,.start_full_p(1)
,.use_async_w_reset_p(1'b1)
) neg_credit_ctr
(
.w_clk_i (token_clk_i)
,.w_inc_token_i(1'b1)
,.w_reset_i(async_token_reset_i)
// the I/O clock domain is responsible for tabulating tokens
,.r_clk_i (io_clk_i )
,.r_reset_i (io_link_reset_i )
,.r_dec_credit_i (io_negedge_credits_deque)
,.r_infinite_credits_i(1'b0 )
,.r_credits_avail_o (io_negedge_credits_avail)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_source_sync_upstream_sync)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__TAPMET1_FUNCTIONAL_PP_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapmet1 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 100005; const long long M = 998244353; long long pow1(long long a, long long b) { int res = 1; while (b > 0) { if (b & 1) { res = (res * a) % M; } a = (a * a) % M; b >>= 1; } return res % M; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long T; T = 1; cin >> T; while (T--) { long long n, m; cin >> n >> m; long long ans[n][m]; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { long long num; cin >> num; if (num % 2 != (i + j) % 2) ans[i][j] = num + 1; else ans[i][j] = num; cout << ans[i][j] << ; } cout << n ; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_0_V
`define SKY130_FD_SC_LP__A2BB2O_0_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_0 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_0 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_0_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`include "verilated.v"
module t;
`verilator_file_descriptor file;
integer chars;
reg [1*8:1] letterl;
reg [8*8:1] letterq;
reg [16*8:1] letterw;
reg [16*8:1] letterz;
real r;
string s;
reg [7:0] v_a,v_b,v_c,v_d;
reg [31:0] v_worda;
reg [31:0] v_wordb;
`ifdef TEST_VERBOSE
`define verbose 1'b1
`else
`define verbose 1'b0
`endif
initial begin
// Display formatting
`ifdef verilator
if (file != 0) $stop;
$fwrite(file, "Never printed, file closed\n");
if (!$feof(file)) $stop;
`endif
`ifdef AUTOFLUSH
// The "w" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_autoflush/t_sys_file_autoflush.log","w");
`else
// The "w" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_basic/t_sys_file_basic_test.log","w");
`endif
if ($feof(file)) $stop;
$fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667);
$fwrite(file, "[%0t] %s\n", $time, "Hello2");
$fflush(file);
$fclose(file);
`ifdef verilator
if (file != 0) $stop(1); // Also test arguments to stop
$fwrite(file, "Never printed, file closed\n");
`endif
begin
// Check for opening errors
// The "r" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_basic/DOES_NOT_EXIST","r");
if (|file) $stop; // Should not exist, IE must return 0
end
begin
// Check quadword access; a little strange, but it's legal to open "."
file = $fopen(".","r");
$fclose(file);
end
begin
// Check read functions w/string
s = "t/t_sys_file_basic_input.dat";
file = $fopen(s,"r");
if ($feof(file)) $stop;
$fclose(file);
end
begin
// Check read functions
file = $fopen("t/t_sys_file_basic_input.dat","r");
if ($feof(file)) $stop;
// $fgetc
if ($fgetc(file) != "h") $stop;
if ($fgetc(file) != "i") $stop;
if ($fgetc(file) != "\n") $stop;
// $fgets
chars = $fgets(letterl, file);
if (`verbose) $write("c=%0d l=%s\n", chars, letterl);
if (chars != 1) $stop;
if (letterl != "l") $stop;
chars = $fgets(letterq, file);
if (`verbose) $write("c=%0d q=%x=%s", chars, letterq, letterq); // Output includes newline
if (chars != 5) $stop;
if (letterq != "\0\0\0quad\n") $stop;
letterw = "5432109876543210";
chars = $fgets(letterw, file);
if (`verbose) $write("c=%0d w=%s", chars, letterw); // Output includes newline
if (chars != 10) $stop;
if (letterw != "\0\0\0\0\0\0widestuff\n") $stop;
// $sscanf
if ($sscanf("x","")!=0) $stop;
if ($sscanf("z","z")!=0) $stop;
chars = $sscanf("blabcdefghijklmnop",
"%s", letterq);
if (`verbose) $write("c=%0d sa=%s\n", chars, letterq);
if (chars != 1) $stop;
if (letterq != "ijklmnop") $stop;
chars = $sscanf("xa=1f xb=12898971238912389712783490823_237904689_02348923",
"xa=%x xb=%x", letterq, letterw);
if (`verbose) $write("c=%0d xa=%x xb=%x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h1f) $stop;
if (letterw != 128'h38971278349082323790468902348923) $stop;
chars = $sscanf("ba=10 bb=110100101010010101012 note_the_two ",
"ba=%b bb=%b%s", letterq, letterw, letterz);
if (`verbose) $write("c=%0d xa=%x xb=%x z=%0s\n", chars, letterq, letterw, letterz);
if (chars != 3) $stop;
if (letterq != 64'h2) $stop;
if (letterw != 128'hd2a55) $stop;
if (letterz != {"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0","2"}) $stop;
chars = $sscanf("oa=23 ob=125634123615234123681236",
"oa=%o ob=%o", letterq, letterw);
if (`verbose) $write("c=%0d oa=%x ob=%x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h13) $stop;
if (letterw != 128'h55ce14f1a9c29e) $stop;
chars = $sscanf("r=0.1 d=-236123",
"r=%g d=%d", r, letterq);
if (`verbose) $write("c=%0d d=%d\n", chars, letterq);
if (chars != 2) $stop;
if (r != 0.1) $stop;
if (letterq != 64'hfffffffffffc65a5) $stop;
s = "r=0.2 d=-236124";
chars = $sscanf(s, "r=%g d=%d", r, letterq);
if (`verbose) $write("c=%0d d=%d\n", chars, letterq);
if (chars != 2) $stop;
if (r != 0.2) $stop;
if (letterq != 64'hfffffffffffc65a4) $stop;
// $fscanf
if ($fscanf(file,"")!=0) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "xa=%x xb=%x", letterq, letterw);
if (`verbose) $write("c=%0d xa=%0x xb=%0x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h1f) $stop;
if (letterw != 128'h23790468902348923) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "ba=%b bb=%b %s", letterq, letterw, letterz);
if (`verbose) $write("c=%0d ba=%0x bb=%0x z=%0s\n", chars, letterq, letterw, letterz);
if (chars != 3) $stop;
if (letterq != 64'h2) $stop;
if (letterw != 128'hd2a55) $stop;
if (letterz != "\0\0\0\0note_the_two") $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "oa=%o ob=%o", letterq, letterw);
if (`verbose) $write("c=%0d oa=%0x ob=%0x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h13) $stop;
if (letterw != 128'h1573) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "d=%d", letterq);
if (`verbose) $write("c=%0d d=%0x\n", chars, letterq);
if (chars != 1) $stop;
if (letterq != 64'hfffffffffffc65a5) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "%c%s", letterl, letterw);
if (`verbose) $write("c=%0d q=%c s=%s\n", chars, letterl, letterw);
if (chars != 2) $stop;
if (letterl != "f") $stop;
if (letterw != "\0\0\0\0\0redfishblah") $stop;
chars = $fscanf(file, "%c", letterl);
if (`verbose) $write("c=%0d l=%x\n", chars, letterl);
if (chars != 1) $stop;
if (letterl != "\n") $stop;
// msg1229
v_a = $fgetc(file);
v_b = $fgetc(file);
v_c = $fgetc(file);
v_d = $fgetc(file);
v_worda = { v_d, v_c, v_b, v_a };
if (v_worda != "4321") $stop;
v_wordb[7:0] = $fgetc(file);
v_wordb[15:8] = $fgetc(file);
v_wordb[23:16] = $fgetc(file);
v_wordb[31:24] = $fgetc(file);
if (v_wordb != "9876") $stop;
if ($fgetc(file) != "\n") $stop;
$fclose(file);
end
$write("*-* All Finished *-*\n");
$finish(0); // Test arguments to finish
end
function sync;
input [7:0] cexp;
reg [7:0] cgot;
begin
cgot = $fgetc(file);
if (`verbose) $write("sync=%x='%c'\n", cgot,cgot);
sync = (cgot == cexp);
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; const double one = 1.0; const double PI = 3.14159265; const long long maxn = 2e3 + 10; const long long maxx = 1e6 + 10; const long double eps = 1e-14; const long long max_len = 1e6 + 1; const long long mod1 = 1000000007; const long long mod2 = 998244353; long long dp[maxn][maxn]; void solve() { long long n, k; cin >> n >> k; vector<long long> vl(n + 2); for (long long i = 1; i < long long(n + 1); i++) cin >> vl[i]; for (long long i = 0; i < long long(n + 1); i++) { for (long long j = 0; j < long long(n + 1); j++) dp[i][j] = 0; } for (long long i = 1; i < long long(n + 1); i++) { for (long long j = 0; j < long long(i + 1); j++) { dp[i][j] = max(dp[i][j], dp[i - 1][j] + (i - j == vl[i])); if (j > 0) dp[i][j] = max(dp[i - 1][j - 1], dp[i][j]); } } long long ans = 1000000000000000000; for (long long j = 0; j < long long(n + 1); j++) { if (dp[n][j] >= k) ans = min(ans, j); } if (ans >= 1000000000000000000) ans = -1; cout << ans << endl; return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cerr.tie(0); long long t; cin >> t; while (t--) solve(); return 0; }
|
module simd_tb;
//wires
reg clk;
reg rst;
reg issue_alu_select, exec_rd_scc_value, rfa_queue_entry_serviced;
reg [5:0] issue_wfid;
reg [11:0] issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg1, issue_dest_reg2;
reg [15:0] issue_imm_value0;
reg [31:0] issue_imm_value1, issue_opcode, sgpr_rd_data, exec_rd_m0_value,
issue_instr_pc;
reg [63:0] exec_rd_exec_value, exec_rd_vcc_value;
reg [2047:0] vgpr_source1_data, vgpr_source2_data, vgpr_source3_data;
wire vgpr_source1_rd_en, vgpr_source2_rd_en, vgpr_source3_rd_en, vgpr_wr_en,
exec_rd_en, exec_wr_vcc_en, sgpr_rd_en, sgpr_wr_en, issue_alu_ready,
vgpr_instr_done, rfa_queue_entry_valid;
wire [5:0] exec_rd_wfid, exec_wr_vcc_wfid, vgpr_instr_done_wfid;
wire [8:0] sgpr_rd_addr, sgpr_wr_addr;
wire [9:0] vgpr_source1_addr, vgpr_source2_addr, vgpr_source3_addr,
vgpr_dest_addr;
wire [31:0] tracemon_retire_pc;
wire [63:0] vgpr_wr_mask, exec_wr_vcc_value, sgpr_wr_data;
wire [2047:0] vgpr_dest_data;
//instantiation of dut
simd simd(
.issue_source_reg1(issue_source_reg1),
.issue_source_reg2(issue_source_reg2),
.issue_source_reg3(issue_source_reg3), //TODO implement this.
.issue_dest_reg1(issue_dest_reg1),
.issue_dest_reg2(issue_dest_reg2), //TODO implement this
.issue_imm_value0(issue_imm_value0),
.issue_imm_value1(issue_imm_value1),
.issue_opcode(issue_opcode),
.issue_wfid(issue_wfid),
.issue_alu_select(issue_alu_select),
.vgpr_source1_data(vgpr_source1_data),
.vgpr_source2_data(vgpr_source2_data),
.vgpr_source3_data(vgpr_source3_data), //TODO implement this
.sgpr_rd_data(sgpr_rd_data),
.exec_rd_exec_value(exec_rd_exec_value),
.exec_rd_vcc_value(exec_rd_vcc_value),
.exec_rd_m0_value(exec_rd_m0_value), //TODO implement this
.exec_rd_scc_value(exec_rd_scc_value),
.issue_instr_pc(issue_instr_pc),
.rfa_queue_entry_serviced(rfa_queue_entry_serviced),
.vgpr_source1_rd_en(vgpr_source1_rd_en),
.vgpr_source2_rd_en(vgpr_source2_rd_en),
.vgpr_source3_rd_en(vgpr_source3_rd_en), //TODO
.vgpr_source1_addr(vgpr_source1_addr),
.vgpr_source2_addr(vgpr_source2_addr),
.vgpr_source3_addr(vgpr_source3_addr), //TODO implement
.vgpr_dest_addr(vgpr_dest_addr),
.vgpr_dest_data(vgpr_dest_data),
.vgpr_wr_en(vgpr_wr_en),
.vgpr_wr_mask(vgpr_wr_mask),
.exec_rd_wfid(exec_rd_wfid),
.exec_rd_en(exec_rd_en),
.exec_wr_vcc_wfid(exec_wr_vcc_wfid),
.exec_wr_vcc_en(exec_wr_vcc_en),
.exec_wr_vcc_value(exec_wr_vcc_value),
.sgpr_rd_en(sgpr_rd_en),
.sgpr_rd_addr(sgpr_rd_addr),
.sgpr_wr_addr(sgpr_wr_addr), //TODO
.sgpr_wr_en(sgpr_wr_en), //TODO
.sgpr_wr_data(sgpr_wr_data), //TODO
.issue_alu_ready(issue_alu_ready),
.vgpr_instr_done_wfid(vgpr_instr_done_wfid),
.vgpr_instr_done(vgpr_instr_done),
.rfa_queue_entry_valid(rfa_queue_entry_valid),
.tracemon_retire_pc(tracemon_retire_pc),
.clk(clk),
.rst(rst)
);
//stimulii
initial begin
forever #5 clk = ~clk;
end
initial begin
#3 clk = 1'b0;
#16 rst = 1'b1;
issue_alu_select = 1'b0;
rfa_queue_entry_serviced = 1'b0;
#10 rst = 1'b0;
#2000;
$finish;
end
initial begin
#31;
$display("ISSUING AND\n");
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_source_reg3 = {32{1'bx}};
issue_dest_reg1 = {2'b10,10'd31};
issue_dest_reg2 = {12{1'bx}};
issue_imm_value0 = {16{1'bx}};
issue_imm_value1 = {32{1'bx}};
issue_opcode = {`ALU_VOP2_FORMAT, 12'h0, 12'h01B}; //AND
issue_wfid = 6'd15;
issue_alu_select = 1'b1;
sgpr_rd_data = {32{1'bx}};
exec_rd_exec_value = 64'hffff_ffff_ffff_ff0f;
exec_rd_vcc_value = {64{1'bx}};
exec_rd_m0_value = {32{1'bx}};
exec_rd_scc_value = 1'bx;
issue_instr_pc = 32'hdead_f00d;
rfa_queue_entry_serviced = 1'b0;
vgpr_source1_data = {64{32'h0000_ffff}};
vgpr_source2_data = {64{32'h00ff_f0f0}};
vgpr_source3_data = {64{32'hx}};
#10;
issue_alu_select = 1'b0;
#40;
$display("ISSUING ADD\n");
issue_alu_select = 1'b1;
issue_wfid = 6'd15;
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_dest_reg1 = {2'b10,10'd31};
issue_imm_value0 = {32{1'bx}};
issue_imm_value1 = {16{1'bx}};
issue_opcode = {`ALU_VOP2_FORMAT, 12'h0, 12'h025}; //ADD
sgpr_rd_data = {32{1'bx}};
issue_instr_pc = 32'hdead_f00d;
exec_rd_exec_value = 64'hffff_ffff_ffff_ffff;
exec_rd_vcc_value = {64{1'bx}};
vgpr_source1_data = {64{32'h8000_0708}};
vgpr_source2_data = {64{32'h80ff_f0f0}};
//1|00ff_f7f7
#10;
issue_alu_select = 1'b0;
#10;
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
#60;
$display("ISSUING MUL");
issue_alu_select = 1'b1;
issue_wfid = 6'd15;
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_dest_reg1 = {2'b10,10'd31};
issue_imm_value0 = {32{1'bx}};
issue_imm_value1 = {16{1'bx}};
issue_opcode = {`ALU_VOP3A_FORMAT, 12'h0, 12'h16B}; //MUL_LO
sgpr_rd_data = {32{1'bx}};
issue_instr_pc = 32'hdead_f00d;
exec_rd_exec_value = 64'hffff_ffff_ffff_ffff;
exec_rd_vcc_value = {64{1'bx}};
vgpr_source1_data = {64{32'h0000_0007}};
vgpr_source2_data = {64{32'h0000_0005}};
//1|0000_0023
#10;
issue_alu_select = 1'b0;
#100;
if (rfa_queue_entry_valid)
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
#100;
if (rfa_queue_entry_valid)
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
end
//monitors
initial begin
if ($test$plusargs("print_outputs")) begin
$monitor($time, ": issue_alu_select = %b, issue_alu_ready = %b \n \
rfa_queue_entry_serviced = %h, rfa_queue_entry_valid = %h \n \
vgpr_dest_data = %h",
issue_alu_select, issue_alu_ready,
rfa_queue_entry_serviced, rfa_queue_entry_valid,
vgpr_dest_data[31:0]
);
// $monitor("$time: vgpr_dest_data = %h", vgpr_dest_data);
//$monitor("$time: rfa_queue_entry_serviced = %b", rfa_queue_entry_serviced);
end
end
//waveforms
initial begin
if ($test$plusargs("dump_waveforms")) begin
$vcdpluson(0,simd_tb);
//$vcdpluson(<level>,scope,<signal>);
//Lots of options for dumping waves
//(both system calls and run time arguments)
// http://read.pudn.com/downloads97/sourcecode/others/399556/vcs_0123.pdf
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 101000; int n, z[N], a[N], b[N]; set<pair<int, int> > Set; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } for (int i = 0; i < n; i++) { scanf( %d , &b[i]); } vector<int> ans; for (int i = 0; i < n; i++) { z[i] = a[i] - b[i]; if (i) z[i] += z[i - 1]; Set.insert(make_pair(z[i], i)); } int line = 0; for (int i = 0; i < n; i++) { if (Set.begin()->first >= line) { ans.push_back(i + 1); } line = z[i]; } line = 0; Set.clear(); for (int i = n - 1; i >= 0; i--) { z[i] = a[i] - b[(i + n - 1) % n]; if (i != n - 1) z[i] += z[i + 1]; Set.insert(make_pair(z[i], i)); } for (int i = n - 1; i >= 0; i--) { if (Set.begin()->first >= line) { ans.push_back(i + 1); } line = z[i]; } sort(ans.begin(), ans.end()); ans.erase(unique(ans.begin(), ans.end()), ans.end()); printf( %d n , (int)ans.size()); for (__typeof((ans).begin()) it = (ans).begin(); it != (ans).end(); it++) { printf( %d , *it); } puts( ); return 0; }
|
`timescale 1 ns / 1 ps
module axi_cfg_register #
(
parameter integer CFG_DATA_WIDTH = 1024,
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer CFG_DATA_DEFAULT = 0
)
(
// System signals
input wire aclk,
input wire aresetn,
// Configuration bits
output wire [CFG_DATA_WIDTH-1:0] cfg_data,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, // AXI4-Lite slave: Write strobe
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready // AXI4-Lite slave: Read data ready
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_LSB = clogb2(AXI_DATA_WIDTH/8 - 1);
localparam integer CFG_SIZE = CFG_DATA_WIDTH/AXI_DATA_WIDTH;
localparam integer CFG_WIDTH = CFG_SIZE > 1 ? clogb2(CFG_SIZE-1) : 1;
reg int_awready_reg, int_awready_next;
reg int_wready_reg, int_wready_next;
reg int_bvalid_reg, int_bvalid_next;
reg int_arready_reg, int_arready_next;
reg int_rvalid_reg, int_rvalid_next;
reg [AXI_DATA_WIDTH-1:0] int_rdata_reg, int_rdata_next;
wire [AXI_DATA_WIDTH-1:0] int_data_mux [CFG_SIZE-1:0];
wire [CFG_DATA_WIDTH-1:0] int_data_wire;
wire [CFG_SIZE-1:0] int_ce_wire;
wire int_wvalid_wire;
genvar j, k;
assign int_wvalid_wire = s_axi_awvalid & s_axi_wvalid;
generate
for(j = 0; j < CFG_SIZE; j = j + 1)
begin : WORDS
assign int_data_mux[j] = int_data_wire[j*AXI_DATA_WIDTH+AXI_DATA_WIDTH-1:j*AXI_DATA_WIDTH];
assign int_ce_wire[j] = int_wvalid_wire & (s_axi_awaddr[ADDR_LSB+CFG_WIDTH-1:ADDR_LSB] == j);
for(k = 0; k < AXI_DATA_WIDTH; k = k + 1)
begin : BITS
FDRE #(
.INIT(1'b0)
) FDRE_inst (
.CE(int_ce_wire[j] & s_axi_wstrb[k/8]),
.C(aclk),
.R(~aresetn),
.D(s_axi_wdata[k]),
.Q(int_data_wire[j*AXI_DATA_WIDTH + k])
);
end
end
endgenerate
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awready_reg <= 1'b0;
int_wready_reg <= 1'b0;
int_bvalid_reg <= 1'b0;
int_arready_reg <= 1'b0;
int_rvalid_reg <= 1'b0;
int_rdata_reg <= {(AXI_DATA_WIDTH){CFG_DATA_DEFAULT}};
end
else
begin
int_awready_reg <= int_awready_next;
int_wready_reg <= int_wready_next;
int_bvalid_reg <= int_bvalid_next;
int_arready_reg <= int_arready_next;
int_rvalid_reg <= int_rvalid_next;
int_rdata_reg <= int_rdata_next;
end
end
always @*
begin
int_awready_next = int_awready_reg;
int_wready_next = int_wready_reg;
int_bvalid_next = int_bvalid_reg;
if(int_wvalid_wire & ~int_awready_reg)
begin
int_awready_next = 1'b1;
int_wready_next = 1'b1;
end
if(int_awready_reg)
begin
int_awready_next = 1'b0;
int_wready_next = 1'b0;
int_bvalid_next = 1'b1;
end
if(s_axi_bready & int_bvalid_reg)
begin
int_bvalid_next = 1'b0;
end
end
always @*
begin
int_arready_next = int_arready_reg;
int_rvalid_next = int_rvalid_reg;
int_rdata_next = int_rdata_reg;
if(s_axi_arvalid)
begin
int_arready_next = 1'b1;
int_rvalid_next = 1'b1;
int_rdata_next = int_data_mux[s_axi_araddr[ADDR_LSB+CFG_WIDTH-1:ADDR_LSB]];
end
if(int_arready_reg)
begin
int_arready_next = 1'b0;
end
if(s_axi_rready & int_rvalid_reg)
begin
int_rvalid_next = 1'b0;
end
end
assign cfg_data = int_data_wire;
assign s_axi_bresp = 2'd0;
assign s_axi_rresp = 2'd0;
assign s_axi_awready = int_awready_reg;
assign s_axi_wready = int_wready_reg;
assign s_axi_bvalid = int_bvalid_reg;
assign s_axi_arready = int_arready_reg;
assign s_axi_rdata = int_rdata_reg;
assign s_axi_rvalid = int_rvalid_reg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4B_TB_V
`define SKY130_FD_SC_LS__NAND4B_TB_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ls__nand4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4B_TB_V
|
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : adc_deser
// Author : Caleb Fangmeier
// Description : Deserializer unit for the frontend ADCs. The deserializer is
// always running, but under idle condition, no deserialized samples are
// written into the input buffer. When a sample should be taken, the
// read_enable signal should be placed high synchronous with the internal ADC
// clock (10MHz). The actual sample from this time will be available eight
// samples later, at which point the value is placed into the output buffer.
//
// Care must be taken to ensure that the internal buffers are not overused.
// They are only 128 samples deep to accomodate 1 sample for each channel of
// the APC128 readout chip.
//
// $Id$
//-------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module adc_deser (
input wire clk, // 133 MHz
input wire reset,
//--------------------------------------------------------------------------
//------------------------CONTROL INTERFACE---------------------------------
//--------------------------------------------------------------------------
input wire read_enable,
input wire buffer_rdreq,
output wire buffer_empty,
output wire [9:0] buffer_data_a,
output wire [9:0] buffer_data_b,
output wire [9:0] buffer_data_c,
output wire [9:0] buffer_data_d,
//--------------------------------------------------------------------------
//---------------------------HW INTERFACE-----------------------------------
//--------------------------------------------------------------------------
input wire adc_fco,
input wire adc_dco,
input wire adc_dat_a,
input wire adc_dat_b,
input wire adc_dat_c,
input wire adc_dat_d
);
//----------------------------------------------------------------------------
// Parameters
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Registers
//----------------------------------------------------------------------------
reg [9:0] input_shifter[3:0];
reg [3:0] negedge_sample;
reg [7:0] sample_delay_shifter;
//----------------------------------------------------------------------------
// Wires
//----------------------------------------------------------------------------
wire [39:0] buffer_q;
wire [39:0] buffer_data;
//----------------------------------------------------------------------------
// Assignments
//----------------------------------------------------------------------------
assign buffer_data = {input_shifter[0], input_shifter[1],
input_shifter[2], input_shifter[3]};
assign buffer_data_a = buffer_q[39:30];
assign buffer_data_b = buffer_q[29:20];
assign buffer_data_c = buffer_q[19:10];
assign buffer_data_d = buffer_q[9:0];
//----------------------------------------------------------------------------
// Clocked Logic
//----------------------------------------------------------------------------
always @( posedge adc_fco or negedge reset ) begin
if ( ~reset ) begin
sample_delay_shifter <= 8'd0;
end
else begin
sample_delay_shifter <= {sample_delay_shifter[6:0], read_enable};
end
end
always @( negedge adc_dco ) begin
negedge_sample[0] = adc_dat_a;
negedge_sample[1] = adc_dat_b;
negedge_sample[2] = adc_dat_c;
negedge_sample[3] = adc_dat_d;
end
always @( posedge adc_dco ) begin
input_shifter[0] = {input_shifter[0][7:0], negedge_sample[0], adc_dat_a};
input_shifter[1] = {input_shifter[1][7:0], negedge_sample[1], adc_dat_b};
input_shifter[2] = {input_shifter[2][7:0], negedge_sample[2], adc_dat_c};
input_shifter[3] = {input_shifter[3][7:0], negedge_sample[3], adc_dat_d};
end
//----------------------------------------------------------------------------
// Instantiations
//----------------------------------------------------------------------------
adc_data_buffer adc_data_buffer_inst (
.aclr ( reset ),
.data ( buffer_data ),
.q ( buffer_q ),
.wrclk ( adc_fco ),
.rdclk ( clk ),
.wrreq ( sample_delay_shifter[7] ),
.rdreq ( buffer_rdreq ),
.wrfull ( ),
.rdempty ( buffer_empty )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long M = 100 + 19; long long d[M][M][M], n, m, k; char c; struct tuplee { long long x, y, z; }; vector<tuplee> v1, v2; long long go(long long x1, long long y1, long long z1, long long x2, long long y2, long long z2) { if (x1 > x2 || y1 > y2 || z1 > z2 || d[x1][y1][z1] == 0) return 0; if (x1 == x2 && y1 == y2 && z1 == z2) return 1; return go(x1 + 1, y1, z1, x2, y2, z2) + go(x1, y1 + 1, z1, x2, y2, z2) + go(x1, y1, z1 + 1, x2, y2, z2); } inline bool is_bad(long long x, long long y, long long z) { tuplee T; v1.clear(); v2.clear(); if (d[x - 1][y][z]) T.x = x - 1, T.y = y, T.z = z, v1.push_back(T); if (d[x][y - 1][z]) T.x = x, T.y = y - 1, T.z = z, v1.push_back(T); if (d[x][y][z - 1]) T.x = x, T.y = y, T.z = z - 1, v1.push_back(T); if (d[x + 1][y][z]) T.x = x + 1, T.y = y, T.z = z, v2.push_back(T); if (d[x][y + 1][z]) T.x = x, T.y = y + 1, T.z = z, v2.push_back(T); if (d[x][y][z + 1]) T.x = x, T.y = y, T.z = z + 1, v2.push_back(T); if (v1.empty() || v2.empty()) return false; for (long long i = (0); i <= (v1.size() - 1); i++) { for (long long j = (0); j <= (v2.size() - 1); j++) { if (go(v1[i].x, v1[i].y, v1[i].z, v2[j].x, v2[j].y, v2[j].z) == 1) return true; } } return false; } int main() { ios::sync_with_stdio(false); scanf( %lld%lld%lld , &n, &m, &k); long long ct = 0; for (long long i1 = (1); i1 <= (n); i1++) for (long long i2 = (1); i2 <= (m); i2++) for (long long i3 = (1); i3 <= (k); i3++) scanf( %c , &c), d[i1][i2][i3] = (c - 0 ); for (long long i1 = (1); i1 <= (n); i1++) for (long long i2 = (1); i2 <= (m); i2++) for (long long i3 = (1); i3 <= (k); i3++) { if (d[i1][i2][i3] && is_bad(i1, i2, i3)) ct++; } printf( %lld , ct); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int fx[] = {+1, -1, +0, +0, +1, +1, -1, -1, +0}; int fy[] = {+0, +0, +1, -1, +1, -1, +1, -1, +0}; template <typename T> inline T GCD(T a, T b) { a = abs(a); b = abs(b); while (b) { a = a % b; swap(a, b); } return a; } template <typename T> inline T LCM(T x, T y) { T tp = GCD(x, y); if ((x / tp) * 1. * y > 9e18) return 9e18; return (x / tp) * y; } template <typename T> inline T BigMod(T A, T B, T M) { T ret = 1; while (B) { if (B & 1) ret = (ret * A) % M; A = (A * A) % M; B = B >> 1; } return ret; } template <typename T> inline T ModInv(T A, T M) { return BigMod(A, M - 2, M); } template <typename T> bool scani(T &n) { n = 0; bool got = false; bool negative = false; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) negative = true; c = getchar(); } while (c >= 0 && c <= 9 ) { got = true; n = n * 10 + c - 48; c = getchar(); } if (negative) n = ~(n - 1); return got; } template <typename T> void write(T n, bool line = true) { if (n < 0) { putchar( - ); n = -n; } if (!n) { putchar( 0 ); if (line) putchar( n ); return; } char buff[22]; int len = 0; while (n) buff[len++] = n % 10 + 48, n /= 10; for (int i = len - 1; i >= 0; i--) putchar(buff[i]); if (line) putchar( n ); } int scans(char *a) { int i = 0; char c = 0; while (c < 33) c = getchar(); while (c > 33) { a[i++] = c; c = getchar(); } a[i] = 0; return i; } int main() { int a, b, c, d, e, f; cin >> a >> b >> c >> d >> e; write(min(min(min(a / 1, b / 1), min(c / 2, d / 7)), e / 4)); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = int(1e9) + 7; const int maxn = 200010; int n; long long a[maxn]; long long fact[maxn]; long long ans; void read() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %I64d , &a[i]); } long long exp(long long x) { long long s = 1, times = mod - 2; while (times) { if (times & 1) s = s * x % mod; x = x * x % mod; times >>= 1; } return s; } long long calc(int x, int y) { return (fact[x] * exp(fact[y] * fact[x - y] % mod) % mod); } void solve() { if (n == 1) { ans = a[1]; return; } if (n & 1) { for (int i = 1; i < n; ++i) a[i] += ((i & 1) ? a[i + 1] : -a[i + 1]); --n; } fact[0] = 1; for (int i = 1; i <= n; ++i) fact[i] = fact[i - 1] * i % mod; ans = 0; if (n % 4 == 0) { for (int i = 1; i <= n; ++i) { long long tmp = calc(n / 2 - 1, (i - 1) / 2) * a[i] % mod; if (i & 1) ans = (ans + tmp) % mod; else ans = (ans - tmp + mod) % mod; } } else { for (int i = 1; i <= n; ++i) ans = (ans + calc(n / 2 - 1, (i - 1) / 2) * a[i] % mod) % mod; } } int main() { read(); solve(); while (ans < 0) ans += mod; printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k; int arr[200005]; int brr[200005]; priority_queue<int, vector<int>, greater<int> > q; stack<int> s; int vis[200005]; int main() { while (cin >> n >> k) { while (!q.empty()) q.pop(); while (!s.empty()) s.pop(); memset(vis, 0, sizeof(vis)); int kmax = 0; for (int i = 0; i < k; i++) { scanf( %d , &arr[i]); vis[arr[i]] = 1; kmax = max(kmax, arr[i]); } for (int i = 1; i <= kmax; i++) { if (vis[i] == 0) { q.push(i); } } int indexb = 0; for (int i = 0; i < k; i++) { if (s.empty()) { s.push(arr[i]); } else if (arr[i] > s.top()) { while (!s.empty() && arr[i] > s.top()) { brr[indexb++] = s.top(); s.pop(); } s.push(arr[i]); } else { s.push(arr[i]); } } bool flag = true; for (int i = 0; i < indexb; i++) { if (brr[i] != i + 1) flag = false; } if (flag == false) { cout << -1 << endl; continue; } stack<int> choosing; for (int i = 0; i < k; i++) printf( %d%c , arr[i], i == k - 1 ? : ); int cnt = 0; while (!s.empty()) { while (!q.empty() && q.top() < s.top()) { choosing.push(q.top()); q.pop(); } s.pop(); while (!choosing.empty()) { printf( %d , choosing.top()); cnt++; if (cnt == kmax - k && kmax == n) printf( n ); else printf( ); choosing.pop(); } } for (int i = n; i >= kmax + 1; i--) { printf( %d%c , i, i == kmax + 1 ? n : ); } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A2111O_BEHAVIORAL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, C1, B1, and0_out, D1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_BEHAVIORAL_V
|
`timescale 1ns/1ps
module sort_module #(
parameter K = 128,
parameter SORT_WIDTH=32,
parameter PRI_POS_START = 0,
parameter PRI_POS_END = 32
)(
input clk,
input reset,
input sort_en,
input place_en,
input wren,
input order,
input [SORT_WIDTH-1:0] data_in, //we bring [key,val,delta_val,priority,pointer to data, length of dataset] in single clk cycle
output [SORT_WIDTH-1:0] dataout_sig,
//signals to check for mutual exclusion between accumulator and update module
input [31:0] accum_key,
//output [K-1:0] is_equal,
//output [K*32-1:0] sort_keys,
//output reg [K-1:0] mask_reg,
input shift_out,
output [31:0] threshold
);
//reg [K-1:0] mask_reg_next;
wire [SORT_WIDTH-1:0] prev_data[K-1:0];
wire [K-1:0] i_am_lower;
wire [K-1:0] is_equal;
wire write_en;
assign write_en = wren & sort_en;
//assign dataout_sig = prev_data[K-1];
/*
generate
for(i=0;i<K;i=i+1) begin:equal
//assign is_equal[i] = (accum_key==prev_data[i][31:0])?1'b1:1'b0;
assign sort_keys[32*(i+1)-1:32*i] = prev_data[i][31:0];
end
endgenerate
*/
/*
always@(*)
begin
if(mask_reg==0)
mask_reg_next = {K{1'b1}};
else if(shift_out)
mask_reg_next = mask_reg>>1;
else
mask_reg_next = mask_reg;
end
always@(posedge clk)
begin
if(reset)
mask_reg <= {K{1'b1}};
else
mask_reg <= mask_reg_next;
end
*/
//assign threshold = next_data[K-1][63:32];//dataout_sig[63:32];
//assign threshold = prev_data[K-1][63:32];//dataout_sig[63:32];
assign threshold = prev_data[K-1][31:0];//dataout_sig[63:32];
genvar i;
generate
for(i=0;i<K;i=i+1) begin:sort
if(i==0) begin
sort_cell #(
.SORT_WIDTH(SORT_WIDTH),
.PRI_POS_START(PRI_POS_START),
.PRI_POS_END(PRI_POS_END)
) scell (
.clk (clk),
.reset (reset),
//.prev_data ({SORT_WIDTH{1'b1}}),
// multfact, size, ptr, pri , deltav, val, key
//Forward shift path
//.prev_data ({32'h7F800000,32'h0}), //deltav is set to + infinity for single-precision floating point
.prev_data (32'h7F800000), //deltav is set to + infinity for single-precision floating point
.data_out (prev_data[0]),
.datain (data_in),
.place_en (place_en),
.wren (write_en),
.order (order),
.left_is_lower (1'b0),
.i_am_lower (i_am_lower[0])
);
end
else if(i==K-1) begin //last cell
sort_cell #(
.SORT_WIDTH(SORT_WIDTH),
.PRI_POS_START(PRI_POS_START),
.PRI_POS_END(PRI_POS_END)
) scell (
.clk (clk),
.reset (reset),
//Forward shift path
.prev_data (prev_data[i-1]),
.data_out (prev_data[i]),
.datain (data_in),
.place_en (place_en),
.wren (write_en),
.order (order),
.left_is_lower (i_am_lower[i-1]),
.i_am_lower (i_am_lower[i])
);
end
else begin
sort_cell #(
.SORT_WIDTH(SORT_WIDTH),
.PRI_POS_START(PRI_POS_START),
.PRI_POS_END(PRI_POS_END)
) scell (
.clk (clk),
.reset (reset),
//Forward shift path
.prev_data (prev_data[i-1]),
.data_out (prev_data[i]),
.datain (data_in),
.place_en (place_en),
.wren (write_en),
.order (order),
.left_is_lower (i_am_lower[i-1]),
.i_am_lower (i_am_lower[i])
);
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); double a[1001][1001], x, y, z1, z2, z3, z4; long long t, n, i, j; for (i = 0; i < 1001; i++) { if (i == 0) a[0][0] = 0.0; else a[i][0] = 1.0; a[0][i] = 0.0; z1 = (double)i; z2 = z1 + 1.0; a[i][1] = z1 / z2; z2 = z1 + 2.0; if (i == 0) continue; else if (i == 1) a[i][2] = 1.0 / 3.0; else a[i][2] = z1 / z2 + (2.0 / (z2 * (z2 - 1.0))); } for (i = 1; i < 1001; i++) { for (j = 3; j < 1001; j++) { z1 = (double)i; z2 = (double)(j); z3 = z1 + z2; a[i][j] = z1 / z3; z4 = (z2 / z3) * ((z2 - 1.0) / (z3 - 1.0)) * (((z2 - 2.0) / (z3 - 2.0)) * a[i][j - 3] + ((z1) / (z3 - 2.0)) * a[i - 1][j - 2]); a[i][j] += z4; } } cin >> i >> j; printf( %.10lf , a[i][j]); }
|
#include <bits/stdc++.h> using namespace std; int n, q, a[2000000], f[2000000], fst[2000000], nx[2000000]; int main() { srand(time(0)); scanf( %d %d , &n, &q); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (; q--;) { long long b; cin >> b; int answer = 2e9, j = 1; long long sum = 0; for (int i = 1; i <= n; i++) { sum += a[i]; while (sum > b) { sum -= a[j]; j++; } nx[i] = j - 1; } f[0] = 0; for (int i = 1; i <= n; i++) f[i] = f[nx[i]] + 1; for (int i = 1; i <= n; i++) if (f[i] == 1) fst[i] = i; else fst[i] = fst[nx[i]]; sum = a[1]; if (sum > b) { printf( %d n , answer); continue; } int it = 1; long long rightpart = a[1]; for (int i = 2; i < n; i++) { if (sum + a[i] > b) break; sum += a[i]; rightpart += a[i]; it = i; } for (int i = n; i >= 2; i--) { sum += a[i]; while (it > 0 && sum > b) { sum -= a[it]; rightpart -= a[it]; it--; } if (sum > b) break; if (fst[i - 1] <= it) answer = min(answer, f[i - 1]); else answer = min(answer, f[i - 1] + 1); } printf( %d n , answer); }; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3_FUNCTIONAL_PP_V
|
/*
DCPU16 Verilog Implementation
Copyright (C) 2012 Shawn Tan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version. This program is
distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU Lesser General Public
License along with this program. If not, see
<http://www.gnu.org/licenses/>. */
module dcpu16_regs (/*AUTOARG*/
// Outputs
rrd,
// Inputs
rwd, rra, rwa, rwe, rst, ena, clk
);
output [15:0] rrd; // read data
input [15:0] rwd; // write data
input [2:0] rra, // read address
rwa; // write address
input rwe; // write-enable
input rst,
ena,
clk;
reg [15:0] file [0:7]; // A, B, C, X, Y, Z, I, J
reg [2:0] r;
assign rrd = file[rra];
always @(posedge clk)
if (ena) begin
r <= rra;
if (rwe) begin
file[rwa] <= rwd;
end
end
endmodule // dcpu16_regs
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:33:15 11/16/2015
// Design Name:
// Module Name: ControlUnit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ControlUnit(
input [5:0] Special,
input [5:0] instructionCode,
output reg RegDst,
output reg Branch,
output reg BranchType,
output reg MemtoReg,
output reg [3:0]MemWrite,
output reg ALUSrc,
output reg ALUShiftImm,
output reg RegWrite,
output reg LoadImm,
output reg ZeroEx,
output reg [1:0] memReadWidth, // 0:Word 1:Halfword 2:Byte
output reg [3:0] aluOperation
);
always @* begin
case (Special)
'b100000:begin //LB
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 2;
end
'b100001:begin //LH
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 1;
end
'b100011:begin //LW
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b100111:begin //LWU
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b100100:begin //LBU
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 2;
end
'b100101:begin //LHU
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 1;
end
'b101000:begin //SB
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 4'd1;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 0;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b101001:begin //SH
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 4'b0011;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 0;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b101011:begin //SW
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 4'b1111;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 0;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b001000:begin //ADDI
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b001100:begin //ANDI
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 1;
aluOperation<= 5;
memReadWidth<= 0;
end
'b001101:begin //ORI
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 1;
aluOperation<= 6;
memReadWidth<= 0;
end
'b001110:begin //XORI
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 1;
aluOperation<= 7;
memReadWidth<= 0;
end
'b001010:begin //SLTI
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 9;
memReadWidth<= 0;
end
'b001111:begin //LUI
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 1;
ZeroEx <= 0;
aluOperation<= 0;
memReadWidth<= 0;
end
'b000100:begin //BEQ
RegDst <= 0;
Branch <= 1;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 0;
ALUShiftImm <= 0;
RegWrite <= 0;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 4;
memReadWidth<= 0;
end
'b000101:begin //BNE
RegDst <= 0;
Branch <= 1;
BranchType <= 1;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 0;
ALUShiftImm <= 0;
RegWrite <= 0;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 4;
memReadWidth<= 0;
end
default:begin //Tipo R
RegDst <= 1;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 0;
ALUShiftImm <=((instructionCode==0) ||(instructionCode==2)||(instructionCode==3));
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
memReadWidth<= 0;
case(instructionCode)
6'b000000: aluOperation <= 0; //SLL
6'b000010: aluOperation <= 1; //SRL
6'b000011: aluOperation <= 2; //SRA
6'b000110: aluOperation <= 1; //SRLV
6'b000111: aluOperation <= 2; //SRAV
6'b000100: aluOperation <= 0; //SLLV
6'b100000: aluOperation <= 3; //ADD
6'b100010: aluOperation <= 4; //SUB
6'b100100: aluOperation <= 5; //AND
6'b100101: aluOperation <= 6; //OR
6'b100110: aluOperation <= 7; //XOR
6'b100111: aluOperation <= 8; //NOR
6'b101010: aluOperation <= 9; //SLT
default: aluOperation <= 'hF;
endcase
end
endcase;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll N = 2e5 + 10; const ll inf = 1e18; const ll MOD = 1e9 + 100; int n; int main() { int t; cin >> t; while (t--) { cin >> n; if (n < 4) printf( -1 n ); else { deque<int> q; q = {3, 1, 4, 2}; for (int i = 5; i <= n; i++) { if (i % 2) { q.push_back(i); } else q.push_front(i); } for (int i = 0; i < q.size(); i++) printf( %d , q[i]); printf( n ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long test; test = 1; while (test--) { long long n; cin >> n; long long a[n], b[n]; for (long long i = 0; i < n; i++) cin >> a[i]; for (long long i = 0; i < n; i++) cin >> b[i]; long long aalone = 0, balone = 0; for (long long i = 0; i < n; i++) { if (a[i] == 1 && b[i] == 0) aalone++; else if (a[i] == 0 && b[i] == 1) balone++; } if (aalone == 0) cout << -1 ; else { if ((balone + 1) % aalone == 0) cout << (balone + 1) / aalone; else { cout << (balone + 1) / aalone + 1; } } } }
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; int n; int a[10001], c[10001], d[10001]; int ans = 0; char str[101]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , str); if (str[0] == M ) a[i] = 1; scanf( %d %d , &c[i], &d[i]); } for (int i = 1; i <= 366; i++) { int x = 0, y = 0; for (int j = 1; j <= n; j++) { if (c[j] <= i && i <= d[j]) { if (a[j]) ++x; else ++y; } } ans = max(ans, min(x, y)); } printf( %d n , ans * 2); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[100005]; int main() { int t; cin >> t; while (t--) { int k1 = 0, k2 = 0; string s; cin >> s; if (s[0] == 0 ) k2++; if (s[0] == 1 ) k1++; for (int i = 1; i < s.size(); i++) { if (s[i - 1] != s[i]) { if (s[i] == 1 ) k1++; if (s[i] == 0 ) k2++; } } if (k1 > 3) cout << 2 << endl; else if (k1 == 0) cout << 1 << endl; else if (k2 == 0) cout << 0 << endl; else if (k2 > 2) cout << 2 << endl; else cout << k2 << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n; long long c; int last, l, r; int q[200010]; long long a[400010], ans[200010]; int main() { scanf( %d%lld , &n, &c); for (int i = 1; i < 2 * n; i++) scanf( %lld , &a[i]), a[i] += a[i - 1]; for (int i = 1; i <= n; i++) { while (last < i && a[2 * i - 1] - a[2 * last] >= c) last++; while (l <= r && a[2 * i - 1] - a[2 * q[l]] >= c) l++; if (last) ans[i] = ans[last - 1] + c; if (l <= r) ans[i] = max(ans[i], a[2 * i - 1] + ans[q[l]] - a[2 * q[l]]); while (l <= r && ans[i] - a[2 * i] >= ans[q[r]] - a[2 * q[r]]) r--; q[++r] = i; } printf( %lld n , ans[n]); }
|
#include <bits/stdc++.h> const int N = 1e4 + 5; int ans, n; double f[2][N]; signed main() { scanf( %d%lf , &n, &f[1][1]); for (int i = 1; i <= n; i++) for (int j = 1; j <= i; j++) { if (f[i & 1][j] >= 1.0) { f[i & 1 ^ 1][j] += (f[i & 1][j] - 1.0) / 2.0; f[i & 1 ^ 1][j + 1] += (f[i & 1][j] - 1.0) / 2.0; ans++; } f[i & 1][j] = 0; } printf( %d , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__FA_PP_BLACKBOX_V
/**
* fa: Full adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXBP_TB_V
`define SKY130_FD_SC_HS__SEDFXBP_TB_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sedfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 DE = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 DE = 1'b0;
#300 SCD = 1'b0;
#320 SCE = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SCE = 1'b1;
#440 SCD = 1'b1;
#460 DE = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SCE = 1'bx;
#560 SCD = 1'bx;
#580 DE = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sedfxbp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXBP_TB_V
|
#include <bits/stdc++.h> using namespace std; int n; int m, q; int a[3]; string dday; int days[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; string tostring(int x) { string temp = ; for (int i = 0; i < 2; i++) { temp = (char)( 0 + x % 10) + temp; x /= 10; } return temp; } bool solve() { sort(a, a + 3); do { if (a[1] > 12) continue; if (a[2] % 4 == 0) { if (a[1] == 2 && a[0] > 29) continue; } else if (a[1] == 2 && a[0] > 28) continue; if (a[1] != 2 && a[0] > days[a[1] - 1]) continue; a[2] += 18; if (a[2] > 100) continue; string temp = tostring(a[2]); temp.push_back( . ); temp += tostring(a[1]); temp.push_back( . ); temp += tostring(a[0]); if (temp <= dday) { return true; } a[2] -= 18; } while (next_permutation(a, a + 3)); return false; } int main() { scanf( %d.%d.%d , &a[0], &a[1], &a[2]); dday = tostring(a[2]); dday.push_back( . ); dday += tostring(a[1]); dday.push_back( . ); dday += tostring(a[0]); scanf( %d.%d.%d , &a[0], &a[1], &a[2]); if (solve()) cout << YES n ; else cout << NO n ; }
|
#include <bits/stdc++.h> using namespace std; int const INF = numeric_limits<int>::max(); long long const LLINF = numeric_limits<long long>::max(); long double const EPS = 1e-9; int n, m, k, q; int const N = 505; int a[N][N]; struct qu { int x, y, t; }; bool operator<(const qu& a, const qu& b) { return a.t < b.t; } qu qq[N * N]; bool check() { int ans = 0; vector<int> d(m, -1), d1(m), d2(m); stack<int> st; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) if (a[i][j] == 0) d[j] = i; while (!st.empty()) st.pop(); for (int j = 0; j < m; ++j) { while (!st.empty() && d[st.top()] <= d[j]) st.pop(); d1[j] = st.empty() ? -1 : st.top(); st.push(j); } while (!st.empty()) st.pop(); for (int j = m - 1; j >= 0; --j) { while (!st.empty() && d[st.top()] <= d[j]) st.pop(); d2[j] = st.empty() ? m : st.top(); st.push(j); } for (int j = 0; j < m; ++j) ans = max(ans, min((i - d[j]), (d2[j] - d1[j] - 1))); } return ans >= k; } int main() { ios::sync_with_stdio(false); cin >> n >> m >> k >> q; for (int i = 0; i < q; i++) { cin >> qq[i].x >> qq[i].y >> qq[i].t; qq[i].x--; qq[i].y--; a[qq[i].x][qq[i].y] = 1; } if (!check()) { cout << -1 << endl; return 0; } sort(qq, qq + q); int l = 0, r = q - 1; while (r - l > 1) { int mid = (l + r) / 2; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { a[i][j] = 0; } } for (int i = 0; i <= mid; i++) { a[qq[i].x][qq[i].y] = 1; } if (check()) { r = mid; } else { l = mid; } } while (r >= l) { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { a[i][j] = 0; } } for (int i = 0; i <= l; i++) { a[qq[i].x][qq[i].y] = 1; } if (check()) { break; } else { l++; } } cout << qq[l].t << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = (1 << 18); struct segment { private: static const int maxn = (1 << 18); int arr[2 * maxn]; int private_sum(int node, int first, int last, int a, int b) { if (first >= a && last <= b) return arr[node]; if (a >= last || b <= first) return 0; int mid = (first + last) / 2; return private_sum(2 * node, first, mid, a, b) + private_sum(2 * node + 1, mid, last, a, b); } public: void add(int ja, int megh) { ja += maxn; while (ja > 0) { arr[ja] += megh; ja /= 2; } } int sum(int first, int last) { return private_sum(1, maxn, 2 * maxn, maxn + first, maxn + last); } int nth(int n) { int node = 1, zir = maxn; while (zir > 1) { if (n < zir / 2 - arr[2 * node]) { node *= 2; } else { n -= zir / 2 - arr[2 * node]; node = 2 * node + 1; } zir /= 2; } return node - maxn; } } p_fir, p_sec, s; int a[maxn], b[maxn], out[maxn]; void find_ab(int x, int n) { int fir = a[x], sec = b[x]; p_fir.add(fir, 1); p_sec.add(sec, 1); a[x] -= p_fir.sum(0, fir); b[x] -= p_sec.sum(0, sec); } void find_out(int n) { for (int i = 0; i < n; i++) { find_ab(i, n); } int bgh = 0; for (int i = n - 1; i >= 0; i--) { out[i] = bgh + a[i] + b[i]; if (out[i] >= n - i) { bgh = 1; out[i] -= (n - i); } else bgh = 0; } for (int i = 0; i < n; i++) { out[i] = s.nth(out[i]); s.add(out[i], 1); } } int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; find_out(n); for (int i = 0; i < n; i++) cout << out[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n = 0; string s; long long int res = 0ll; cin >> n; cin >> s; res = (1ll * n * (n + 1)) / 2ll - 1ll * n; for (int i = 0; i + 1 < n; ++i) { if (s[i] != s[i + 1]) { int j; for (j = i + 1; j < n; ++j) { if (s[i] == s[j]) break; } res -= (j - i - 1); } } reverse(s.begin(), s.end()); for (int i = 0; i + 1 < n; ++i) { if (s[i] != s[i + 1]) { int j; for (j = i + 1; j < n; ++j) { if (s[i] == s[j]) break; } res -= (j - i - 2); } } cout << res; }
|
/*
* Copyright (c) 2001 Stephen Rowland
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module dummy;
reg [7:0] decode_vec;
wire [7:0] data1;
wire [7:0] data2;
// icarus cant handle this statement
assign data1 = (decode_vec[8'h02>>1] ) ? 8'h55 : 8'h00;
assign data2 = (decode_vec[8'h01 ] ) ? 8'h55 : 8'h00;
initial
begin
#0;
$monitor("%h %h %h", decode_vec, data1, data2);
decode_vec = 8'h02;
#10;
decode_vec = 8'h80;
#10;
decode_vec = 8'h02;
#10;
$finish(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int min1(long long int a) { long long int mx = 0, mi = 10; while (a) { mx = max(mx, a % 10); mi = min(mi, a % 10); a /= 10; } return mi * mx; } int main() { int t; cin >> t; while (t--) { long long int a, k; cin >> a >> k; long long int tem = min1(a); while (--k && tem != 0) { a = a + tem; tem = min1(a); } cout << a << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND2B_PP_BLACKBOX_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_PP_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : qdr_rld_of_pre_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : QDRII+ SRAM / RLDRAM II SDRAM
//Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
/******************************************************************************
**$Id: qdr_rld_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $
**$Date: 2011/06/02 08:35:07 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/qdr_rld_of_pre_fifo.v,v $
******************************************************************************/
`timescale 1 ps / 1 ps
module mig_7series_v2_0_qdr_rld_of_pre_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input full_in, // FULL flag from OUT_FIFO
input wr_en_in, // write enable from controller
input [WIDTH-1:0] d_in, // write data from controller
output wr_en_out, // write enable to OUT_FIFO
output [WIDTH-1:0] d_out // write data to OUT_FIFO
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
((DEPTH == 3) || (DEPTH == 4)) ? 2 :
(((DEPTH == 5) || (DEPTH == 6) ||
(DEPTH == 7) || (DEPTH == 8)) ? 3 : 'bx);
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1];
reg [6:0] my_empty /* synthesis syn_maxfan = 3 syn_keep=1 */;
reg [3:0] my_full /* synthesis syn_maxfan = 3 syn_keep=1 */;
reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 syn_keep=1 */;
reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 syn_keep=1 */;
wire [PTR_BITS-1:0] nxt_rd_ptr;
wire [PTR_BITS-1:0] nxt_wr_ptr;
wire [WIDTH-1:0] mem_out;
wire wr_en;
wire wr_en_1;
assign d_out = my_empty[0] ? d_in : mem_out;
assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in);
assign wr_en = wr_en_in & (full_in ? !my_full[1] : !my_empty[2]);
assign wr_en_1 = wr_en_in & (full_in ? !my_full[2] : !my_empty[4]);
always @ (posedge clk)
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
assign mem_out = mem[rd_ptr];
assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst)
rd_ptr <= 'b0;
else if ((!my_empty[6]) & (!full_in))
rd_ptr <= nxt_rd_ptr;
end
always @ (posedge clk)
begin
if (rst)
my_empty <= 7'b1111111;
else if (my_empty[3] & !my_full[3] & full_in & wr_en_in)
my_empty <= 7'b0000000;
else if (!my_empty[3] & !my_full[3] & !full_in & !wr_en_in) begin
my_empty[0] <= (nxt_rd_ptr == wr_ptr);
my_empty[1] <= (nxt_rd_ptr == wr_ptr);
my_empty[2] <= (nxt_rd_ptr == wr_ptr);
my_empty[3] <= (nxt_rd_ptr == wr_ptr);
my_empty[4] <= (nxt_rd_ptr == wr_ptr);
my_empty[5] <= (nxt_rd_ptr == wr_ptr);
my_empty[6] <= (nxt_rd_ptr == wr_ptr);
end
end
assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst)
wr_ptr <= 'b0;
else if (wr_en_1)
wr_ptr <= nxt_wr_ptr;
end
always @ (posedge clk)
begin
if (rst)
my_full <= 4'b0000;
else if (!my_empty[5] & my_full[0] & !full_in & !wr_en_in)
my_full <= 4'b0000;
else if (!my_empty[5] & !my_full[0] & full_in & wr_en_in) begin
my_full[0] <= (nxt_wr_ptr == rd_ptr);
my_full[1] <= (nxt_wr_ptr == rd_ptr);
my_full[2] <= (nxt_wr_ptr == rd_ptr);
my_full[3] <= (nxt_wr_ptr == rd_ptr);
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__INPUTISO0P_BEHAVIORAL_PP_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__inputiso0p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire sleepn ;
wire and0_out_X;
// Name Output Other arguments
not not0 (sleepn , SLEEP );
and and0 (and0_out_X, A, sleepn );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0P_BEHAVIORAL_PP_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.2
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module dut_top (
aresetn,
aclk,
in_fifo_V_dout,
in_fifo_V_empty_n,
in_fifo_V_read,
out_fifo_V_din,
out_fifo_V_full_n,
out_fifo_V_write
);
parameter RESET_ACTIVE_LOW = 1;
input aresetn ;
input aclk ;
input [32 - 1:0] in_fifo_V_dout ;
input in_fifo_V_empty_n ;
output in_fifo_V_read ;
output [32 - 1:0] out_fifo_V_din ;
input out_fifo_V_full_n ;
output out_fifo_V_write ;
wire aresetn;
wire sig_dut_ap_rst;
dut dut_U(
.ap_rst(sig_dut_ap_rst),
.ap_clk(aclk),
.in_fifo_V_dout(in_fifo_V_dout),
.in_fifo_V_empty_n(in_fifo_V_empty_n),
.in_fifo_V_read(in_fifo_V_read),
.out_fifo_V_din(out_fifo_V_din),
.out_fifo_V_full_n(out_fifo_V_full_n),
.out_fifo_V_write(out_fifo_V_write)
);
dut_ap_rst_if #(
.RESET_ACTIVE_LOW(RESET_ACTIVE_LOW))
ap_rst_if_U(
.dout(sig_dut_ap_rst),
.din(aresetn));
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() {} int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; long long k = 1; vector<long long> v; while (1) { long long tmp = ((1 << k) - 1) * (1 << (k - 1)); if (tmp > 100001) break; v.push_back(tmp); k++; } while (t--) { long long n; cin >> n; for (int i = (int)v.size() - 1; i > -1; i--) { if (n % v[i] == 0) { cout << v[i] << n ; break; } } } return 0; }
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// This module records profiling information. It is connected to the desired
// pipeline ports that are needed to be profiled.
// cntl_in signal determines when a profiling register is updated.
// incr_in signal determines the increment value for each counter.
// NUM_COUNTERS of profiling registers are instantiated. When the profile_shift
// signal is high, profiling registers are shifted out DAISY_WIDTH bits (64-bits) at a time.
//
module acl_profiler
(
clock,
resetn,
enable,
profile_shift,
incr_cntl,
incr_val,
daisy_out
);
parameter COUNTER_WIDTH=64;
parameter INCREMENT_WIDTH=32;
parameter NUM_COUNTERS=4;
parameter TOTAL_INCREMENT_WIDTH=INCREMENT_WIDTH * NUM_COUNTERS;
parameter DAISY_WIDTH=64;
input clock;
input resetn;
input enable;
input profile_shift;
input [NUM_COUNTERS-1:0] incr_cntl;
input [TOTAL_INCREMENT_WIDTH-1:0] incr_val;
output [DAISY_WIDTH-1:0] daisy_out;
// if there are NUM_COUNTER counters, there are NUM_COUNTER-1 connections between them
wire [NUM_COUNTERS-2:0][DAISY_WIDTH-1:0] shift_wire;
wire [31:0] data_out [0:NUM_COUNTERS-1];// for debugging, always 32-bit for ease of modelsim
genvar n;
generate
for(n=0; n<NUM_COUNTERS; n++)
begin : counter_n
if(n == 0)
acl_profile_counter #(
.COUNTER_WIDTH( COUNTER_WIDTH ),
.INCREMENT_WIDTH( INCREMENT_WIDTH ),
.DAISY_WIDTH( DAISY_WIDTH )
) counter (
.clock( clock ),
.resetn( resetn ),
.enable( enable ),
.shift( profile_shift ),
.incr_cntl( incr_cntl[n] ),
.shift_in( shift_wire[n] ),
.incr_val( incr_val[ ((n+1)*INCREMENT_WIDTH-1) : (n*INCREMENT_WIDTH) ] ),
.data_out( data_out[ n ] ),
.shift_out( daisy_out )
);
else if(n == NUM_COUNTERS-1)
acl_profile_counter #(
.COUNTER_WIDTH( COUNTER_WIDTH ),
.INCREMENT_WIDTH( INCREMENT_WIDTH ),
.DAISY_WIDTH( DAISY_WIDTH )
) counter (
.clock( clock ),
.resetn( resetn ),
.enable( enable ),
.shift( profile_shift ),
.incr_cntl( incr_cntl[n] ),
.shift_in( {DAISY_WIDTH{1'b0}} ),
.incr_val( incr_val[ ((n+1)*INCREMENT_WIDTH-1) : (n*INCREMENT_WIDTH) ] ),
.data_out( data_out[ n ] ),
.shift_out( shift_wire[n-1] )
);
else
acl_profile_counter #(
.COUNTER_WIDTH( COUNTER_WIDTH ),
.INCREMENT_WIDTH( INCREMENT_WIDTH ),
.DAISY_WIDTH( DAISY_WIDTH )
) counter (
.clock( clock ),
.resetn( resetn ),
.enable( enable ),
.shift( profile_shift ),
.incr_cntl( incr_cntl[n] ),
.shift_in( shift_wire[n] ),
.incr_val( incr_val[ ((n+1)*INCREMENT_WIDTH-1) : (n*INCREMENT_WIDTH) ] ),
.data_out( data_out[ n ] ),
.shift_out( shift_wire[n-1] )
);
end
endgenerate
endmodule
module acl_profile_counter
(
clock,
resetn,
enable,
shift,
incr_cntl,
shift_in,
incr_val,
data_out,
shift_out
);
parameter COUNTER_WIDTH=64;
parameter INCREMENT_WIDTH=32;
parameter DAISY_WIDTH=64;
input clock;
input resetn;
input enable;
input shift;
input incr_cntl;
input [DAISY_WIDTH-1:0] shift_in;
input [INCREMENT_WIDTH-1:0] incr_val;
output [31:0] data_out;// for debugging, always 32-bit for ease of modelsim
output [DAISY_WIDTH-1:0] shift_out;
reg [COUNTER_WIDTH-1:0] counter;
always@(posedge clock or negedge resetn)
begin
if( !resetn )
counter <= { COUNTER_WIDTH{1'b0} };
else if(shift) // shift by DAISY_WIDTH bits
counter <= {counter, shift_in};
else if(enable && incr_cntl) // increment counter
counter <= counter + incr_val;
end
assign data_out = counter;
assign shift_out = {counter, shift_in} >> COUNTER_WIDTH;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 5e5 + 5; int main() { ios::sync_with_stdio(0); cin.tie(0); int T; cin >> T; while (T--) { int n, m; cin >> n >> m; if (n % m == 0) cout << YES n ; else cout << NO n ; } }
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
// *********************************************************************************************************************
// IMPORTANT
// This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design.
// However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this
// core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any
// modifications you may choose to make.
// *********************************************************************************************************************
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_ultrascale_rx_userclk #(
parameter integer P_CONTENTS = 0,
parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
)(
input wire gtwiz_reset_clk_freerun_in,
input wire gtwiz_userclk_rx_srcclk_in,
input wire gtwiz_userclk_rx_reset_in,
output wire gtwiz_userclk_rx_usrclk_out,
output wire gtwiz_userclk_rx_usrclk2_out,
output reg gtwiz_userclk_rx_active_out = 1'b0
);
// -------------------------------------------------------------------------------------------------------------------
// Local parameters
// -------------------------------------------------------------------------------------------------------------------
// Convert integer parameters with known, limited legal range to a 3-bit local parameter values
localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
// ------
wire gtwiz_userclk_rx_active_o;
reg gtwiz_userclk_rx_active_r = 1'b0;
// ------
// -------------------------------------------------------------------------------------------------------------------
// Receiver user clocking network conditional generation, based on parameter values in module instantiation
// -------------------------------------------------------------------------------------------------------------------
generate if (1) begin: gen_gtwiz_userclk_rx_main
// Use BUFG_GT instance(s) to drive RXUSRCLK and RXUSRCLK2, inferred for integral source to RXUSRCLK frequency ratio
if (P_CONTENTS == 0) begin
// Drive RXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to RXUSRCLK
// frequency ratio
BUFG_GT bufg_gt_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_rx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK_DIV),
.I (gtwiz_userclk_rx_srcclk_in),
.O (gtwiz_userclk_rx_usrclk_out)
);
// If RXUSRCLK and RXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
// RXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the RXUSRCLK2 frequency.
if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1) begin
assign gtwiz_userclk_rx_usrclk2_out = gtwiz_userclk_rx_usrclk_out;
end
else begin
BUFG_GT bufg_gt_usrclk2_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_rx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK2_DIV),
.I (gtwiz_userclk_rx_srcclk_in),
.O (gtwiz_userclk_rx_usrclk2_out)
);
end
// Indicate active helper block functionality when the BUFG_GT divider is not held in reset
always @(posedge gtwiz_reset_clk_freerun_in) begin
if (gtwiz_userclk_rx_reset_in)
gtwiz_userclk_rx_active_r <= 1'b0;
else
gtwiz_userclk_rx_active_r <= 1'b1;
end
aurora_64b66b_25p4G_cdc_sync
# (
.c_cdc_type (1), // 0 Pulse synchronizer, 1 level synchronizer 2 level synchronizer with ACK
.c_flop_input (0), // 1 Adds one flop stage to the input prmry_in signal
.c_reset_state (0), // 1 Reset needed for sync flops
.c_single_bit (1), // 1 single bit input.
.c_mtbf_stages (5) // Number of sync stages needed
) rx_active_out_i
(
.prmry_aclk (1'b0),
.prmry_rst_n (1'b1),
.prmry_in (gtwiz_userclk_rx_active_r),
.prmry_vect_in ('d0),
.scndry_aclk (gtwiz_userclk_rx_usrclk2_out),
.scndry_rst_n (1'b1),
.prmry_ack (),
.scndry_out (gtwiz_userclk_rx_active_o),
.scndry_vect_out ()
);
always @(posedge gtwiz_userclk_rx_usrclk2_out) begin
gtwiz_userclk_rx_active_out <= gtwiz_userclk_rx_active_o;
end
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
`define SIMULATION
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:55:11 12/07/2015
// Design Name: Peripheral_clk_generator
// Module Name: C:/WINDOWS/system32/Timer/Periph_gen_clk_tst.v
// Project Name: Timer
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Peripheral_clk_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Periph_int_clk_tst;
// Inputs
reg clk;
reg rst;
reg start;
reg [15:0] d_in;
reg cs;
reg [3:0] addr;
reg rd;
reg wr;
// Outputs
wire [15:0] d_out;
// Instantiate the Unit Under Test (UUT)
Peripheral_clk_interruptor uut (
.clk(clk),
.rst(rst),
.d_in(d_in),
.cs(cs),
.addr(addr),
.rd(rd),
.wr(wr),
.d_out(d_out)
);
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
reg [20:0] i;
event reset_trigger;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
d_in = 16'd0035;
cs = 1;
start = 0;
addr = 16'h0000;
rd = 0;
wr = 1;
end
initial begin // Process for clk
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin // Reset the system, Start the image capture process
forever begin
@ (reset_trigger);
@ (posedge clk);
start = 0;
@ (posedge clk);
start = 1;
for(i=0; i<2; i=i+1) begin
@ (posedge clk);
end
start = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0005; //envio A
addr = 16'h0000;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0002; //envio B
addr = 16'h0001;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0001; //envio init
addr = 16'h0002;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0000; //recibo dato
addr = 16'h0002;
cs=0; rd=1; wr=0;
end
end
initial begin: TEST_CASE
$dumpfile("peripheral_mult_TB.vcd");
$dumpvars(1, uut);
#10 -> reset_trigger;
#((PERIOD*DUTY_CYCLE)*200) $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, t, i, j, a[300006], q; int main() { scanf( %lld , &t); while (t--) { long long ans = 0; memset(a, 0, sizeof a); scanf( %lld%lld , &n, &q); for (i = 1; i <= n; i++) { scanf( %lld , &a[i]); } long long flag = 0; for (i = 1; i <= n; i++) { if (a[i] > a[i - 1] && a[i] > a[i + 1] && flag == 0) { ans += a[i]; flag = 1; } else if (a[i] < a[i - 1] && a[i] < a[i + 1] && flag == 1) { ans -= a[i]; flag = 0; } } printf( %lld n , ans); } }
|
#include <bits/stdc++.h> using namespace std; int n, k, d[2][100005], q1[100005], q2[100005], x, y, st, en; char s[2][100005]; int main() { cin >> n >> k; cin >> s[0]; cin >> s[1]; d[0][0] = 1; for (en = 1; st < en;) { x = q1[st]; y = q2[st++]; if (y >= n - k) { cout << YES ; return 0; } if (s[x][y - 1] == - && d[x][y - 1] == 0 && y > 0 && y > d[x][y]) { d[x][y - 1] = d[x][y] + 1; q1[en] = x; q2[en++] = y - 1; } if (s[x][y + 1] == - && d[x][y + 1] == 0) { d[x][y + 1] = d[x][y] + 1; q1[en] = x; q2[en++] = y + 1; } if (s[1 - x][y + k] == - && d[1 - x][y + k] == 0) { d[1 - x][y + k] = d[x][y] + 1; q1[en] = 1 - x; q2[en++] = y + k; } } cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; struct sl { int SC, LC, TS, TL; double p; } a[1005]; struct csl { long double score, tim; } f[1005][1561], ans; double a1, a2, p; int n, m, z, x, y; inline bool cmp(sl x, sl y) { return x.TL * x.p * (1 - y.p) < y.TL * y.p * (1 - x.p); } inline csl Max(csl x, int l, int k, int t) { csl y; y.score = y.tim = 0; if (t == 1) { y.score = f[l - 1][k - a[l].TS].score + a[l].SC; y.tim = f[l - 1][k - a[l].TS].tim + a[l].TS; } else { y.score = f[l - 1][k - a[l].TS - a[l].TL].score + a[l].SC + a[l].LC * (1 - a[l].p); y.tim = a[l].p * (f[l - 1][k - a[l].TS - a[l].TL].tim + a[l].TS) + k * (1 - a[l].p); } if (x.score + eps < y.score || (abs(x.score - y.score) < eps && x.tim > y.tim)) return y; else return x; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) { scanf( %d%d%d%d%lf , &a[i].SC, &a[i].LC, &a[i].TS, &a[i].TL, &a[i].p); } sort(a + 1, a + n + 1, cmp); for (int i = 1; i <= n; ++i) { for (int j = 0; j <= m; ++j) { f[i][j] = f[i - 1][j]; if (j >= a[i].TS) f[i][j] = Max(f[i][j], i, j, 1); if (j >= a[i].TS + a[i].TL) f[i][j] = Max(f[i][j], i, j, 2); } } for (int i = 0; i <= m; ++i) if (ans.score + eps < f[n][i].score || (abs(ans.score - f[n][i].score) < eps && ans.tim > f[n][i].tim)) ans = f[n][i]; printf( %.10lf %.10lf , (double)ans.score, (double)ans.tim); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_PP_SYMBOL_V
`define SKY130_FD_SC_LS__OR4B_PP_SYMBOL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; long long DP[N]; int n; int a[N]; int freq[N]; long long solve(int num) { if (num < 1) return 0; if (DP[num] != -1) return DP[num]; return DP[num] = max((long long)num * freq[num] + solve(num - 2), solve(num - 1)); } int main() { memset(DP, -1, sizeof DP); scanf( %d , &n); int mx = 0; for (int i = 0; i < n; ++i) { scanf( %d , a + i); ++freq[a[i]]; if (a[i] > mx) mx = a[i]; } printf( %lld n , solve(mx)); }
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( O3 ) #pragma GCC optimize( O2 ) #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { for (long long i = 0; i < v.size(); ++i) os << v[i] << ; return os; } template <typename T> ostream& operator<<(ostream& os, const set<T>& v) { for (auto it : v) os << it << ; return os; } template <typename T, typename S> ostream& operator<<(ostream& os, const pair<T, S>& v) { os << v.first << << v.second; return os; } const long long mod = 1e9 + 7; const long long inf = 2e18; const long long ninf = -2e18; long long pow(long long a, long long b, long long m) { long long ans = 1; while (b) { if (b & 1) ans = (ans * a) % m; b /= 2; a = (a * a) % m; } return ans; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); time_t t1, t2; t1 = clock(); long long n, m, ta, tb, k; cin >> n >> m >> ta >> tb >> k; vector<long long> arra(n); for (long long i = 0; i < n; i++) { cin >> arra[i]; } vector<long long> arrb(m); for (long long i = 0; i < m; i++) { cin >> arrb[i]; } if (n <= k || m <= k) { cout << -1 << n ; return 0; } long long ans = -1; for (long long i = 0; i <= k; i++) { long long curr = arra[i] + ta; long long req = lower_bound(arrb.begin(), arrb.end(), curr) - arrb.begin(); long long rem = k - i; if (req + rem > m - 1) { ans = inf; break; } long long ap = arrb[req + rem] + tb; ans = max(ap, ans); } if (ans != inf) { cout << ans << n ; } else cout << -1 << n ; t2 = clock(); cerr << n << t2 - t1 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int ar[n + 5]; int br[n + 5]; int mark[200005]; memset(mark, 0, sizeof mark); for (int i = 0; i < n; i++) { cin >> ar[i]; br[i] = ar[i]; } sort(br, br + n, greater<int>()); int sum = 0; int cr[n + 5]; int c = 0; for (int i = 0; i < k; i++) { sum += br[i]; for (int j = 0; j < n; j++) { if (br[i] == ar[j]) { ar[j] = 0; cr[c++] = j; } } } sort(cr, cr + k); cout << sum << endl; if (k == 1) cout << n << endl; else { for (int i = 0; i < k; i++) { if (i == 0) { cout << cr[i] + 1 << ; } else if (i == k - 1) { int p = cr[i] - cr[i - 1]; p += n - cr[i] - 1; cout << p << endl; } else { cout << cr[i] - cr[i - 1] << ; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10, C = 30; int nex[N][C], p, n, par[N], dfa[N][C]; string s, t; vector<pair<int, char> > adj_matrix[N]; long long ans; void dfs(int v, int p, int state) { if (state == (int)t.size()) ans++; for (auto pa : adj_matrix[v]) { int u = pa.first; char c = pa.second; if (u == p) continue; dfs(u, v, nex[state][c - a ]); } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; int cur = n + 1; for (int i = 1; i < n; i++) { cin >> p; p--; cin >> s; int j = 0, lp = p; while (j + 1 < s.size()) { adj_matrix[lp].push_back({cur, s[j]}); lp = cur; j++; cur++; } adj_matrix[lp].push_back({i, s[j]}); } cin >> t; nex[0][t[0] - a ] = 1; int l = 0; for (int i = 1; i <= (int)t.size(); i++) { for (int j = 0; j < 28; j++) { if (i < (int)t.size()) { if (j == (t[i] - a )) nex[i][j] = i + 1; else nex[i][j] = nex[l][j]; } else nex[i][j] = nex[l][j]; } if (i < (int)t.size()) l = nex[l][t[i] - a ]; } dfs(0, 0, 0); cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; int main() { int x = 0, y = 0; int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { char ch; cin >> ch; if (ch == * ) { x ^= i; y ^= j; } } } cout << x + 1 << << y + 1 << endl; return 0; }
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:10 $
// \ \ / \ Date Created: 05/12/10
// \___\/\___\
//
//Device: 7 Series
//Design Name: ddr_prbs_gen
// Overview:
// Implements a "pseudo-PRBS" generator. Basically this is a standard
// PRBS generator (using an linear feedback shift register) along with
// logic to force the repetition of the sequence after 2^PRBS_WIDTH
// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design
// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains
// are supported in this code
// Parameter Requirements:
// 1. PRBS_WIDTH = 8 or 10
// 2. PRBS_WIDTH >= 2*nCK_PER_CLK
// Output notes:
// The output of this module consists of 2*nCK_PER_CLK bits, these contain
// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note
// that prbs_o[0] contains the bit value for the "earliest" bit time.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $
**$Date: 2011/06/02 08:35:10 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_0_ddr_prbs_gen #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter PRBS_WIDTH = 64 // LFSR shift register length
)
(
input clk_i, // input clock
input clk_en_i, // clock enable
input rst_i, // synchronous reset
input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed
input phy_if_empty, // IN_FIFO empty flag
input prbs_rdlvl_start, // PRBS read lveling start
output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data
);
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Number of internal clock cycles before the PRBS sequence will repeat
localparam PRBS_SEQ_LEN_CYCLES = 128;
localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);
reg phy_if_empty_r;
reg reseed_prbs_r;
reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
//***************************************************************************
always @(posedge clk_i) begin
phy_if_empty_r <= #TCQ phy_if_empty;
end
//***************************************************************************
// Generate PRBS reset signal to ensure that PRBS sequence repeats after
// every 2**PRBS_WIDTH samples. Basically what happens is that we let the
// LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1
// samples have past. Once that extra cycle is finished, we reseed the LFSR
always @(posedge clk_i)
begin
if (rst_i || ~clk_en_i) begin
sample_cnt_r <= #TCQ 'b0;
reseed_prbs_r <= #TCQ 1'b0;
end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
// The rollver count should always be [(power of 2) - 1]
sample_cnt_r <= #TCQ sample_cnt_r + 1;
// Assert PRBS reset signal so that it is simultaneously with the
// last sample of the sequence
if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)
reseed_prbs_r <= #TCQ 1'b1;
else
reseed_prbs_r <= #TCQ 1'b0;
end
end
always @ (posedge clk_i)
begin
//reset it to a known good state to prevent it locks up
if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4];
end
else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30];
lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1];
lfsr_q[29:9] <= #TCQ lfsr_q[28:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_174x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_174x128 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input [173:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [173:0] q;
output rdempty;
output wrempty;
output wrfull;
output [6:0] wrusedw;
wire sub_wire0;
wire [6:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire [173:0] sub_wire4;
wire rdempty = sub_wire0;
wire [6:0] wrusedw = sub_wire1[6:0];
wire wrfull = sub_wire2;
wire wrempty = sub_wire3;
wire [173:0] q = sub_wire4[173:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.wrempty (sub_wire3),
.q (sub_wire4)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.rdusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 174,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "174"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "174"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "174"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 174 0 INPUT NODEFVAL data[173..0]
// Retrieval info: USED_PORT: q 0 0 174 0 OUTPUT NODEFVAL q[173..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
// Retrieval info: CONNECT: @data 0 0 174 0 data 0 0 174 0
// Retrieval info: CONNECT: q 0 0 174 0 @q 0 0 174 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module contact_discoverydEe_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 1;
parameter AWIDTH = 9;
parameter MEM_SIZE = 300;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module contact_discoverydEe(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd1;
parameter AddressRange = 32'd300;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
contact_discoverydEe_ram contact_discoverydEe_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; const int N = 1e5 + 5; int n; long long x, y, ans; bool comp[N]; vector<long long> primes; long long add(long long a, long long b) { return (a + b) % MOD; } long long mul(long long a, long long b) { return (a * b) % MOD; } long long fastexp(long long a, long long b) { if (b == 0) return 1; long long x = fastexp(a, b >> 1); x = mul(x, x); if (b & 1) x = mul(x, a); return x; } int main() { scanf( %lld%lld , &x, &y); if (y % x != 0) { printf( 0 n ); return 0; } y /= x; comp[1] = 1; for (int i = 2; i * i <= N; i++) { if (comp[i]) continue; for (int j = i * i; j < N; j += i) { comp[j] = i; } } long long z = y; for (int i = 2; i < N; i++) { if (comp[i]) continue; if (z % i) continue; while (z % i == 0) { z /= i; } primes.push_back(i); } if (z > 1) primes.push_back(z); z = primes.size(); for (int i = 0; i < (1 << z); i++) { long long a = 1, b = 0; for (int j = 0; j < z; j++) { if ((i >> j) & 1) { b++; a *= primes[j]; } } a = y / a; if (b & 1) { ans = add(ans, MOD - fastexp(2, a - 1)); } else { ans = add(ans, fastexp(2, a - 1)); } } printf( %lld n , ans); }
|
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
);
wire [15:0] wIP,wIP_temp;
reg rWriteEnable,rBranchTaken;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg signed [15:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination, wDestOpAnterior0, wDestOpAnterior1;
wire [15:0] wSourceData0,wSourceData1,wIPInitialValue,wImmediateValue;
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0 ),
.oDataOut1( wSourceData1 )
);
assign wSourceData0 = (wSourceAddr0 == wDestination) ? rResult : wSourceData0 ;
assign wSourceData1 = (wSourceAddr1 == wDestination) ? rResult : wSourceData1 ;
);
assign wIPInitialValue = (Reset) ? 8'b0 : wDestination;
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1 ),
.Q( oLed )
);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
$display("%dns ADD %x + %x = %x",$time,wSourceData0,wSourceData1,rResult);
end
//-------------------------------------
`CMP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= -wSourceData1;
$display("%dns CMP %x = %x",$time,wSourceData1,rResult);
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
`SMUL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData0*wSourceData1;
rBranchTaken <= 1'b0;
end
//-------------------------------------
`IMUL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
arrayMUL(wSourceData0,wSourceData1,rResult);
rBranchTaken <= 1'b0;
end
//-------------------------------------
`gIMUL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
arrayMUL_GEN(wSourceData0,wSourceData1,rResult);
rBranchTaken <= 1'b0;
end
//-------------------------------------
`IMUL2:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
muxMUL(wSourceData0,wSourceData1,rResult);
end
//-------------------------------------
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int Set(int N, int pos) { return N |= (1LL << pos); } int Reset(int N, int pos) { return N &= ~(1LL << pos); } bool Check(int N, int pos) { return N & (1LL << pos); } int dx[] = {0, 0, 1, -1, 1, -1, 1, -1}, dy[] = {1, -1, 0, 0, 1, -1, -1, 1}; inline void cn(long &n) { n = 0; long ch = getchar(); int sign = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) sign = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) n = (n << 3) + (n << 1) + ch - 0 , ch = getchar(); n = n * sign; } template <class T> void cmin(T &a, T b) { if (b < a) a = b; } template <class T> void cmax(T &a, T b) { if (b > a) a = b; } template <class T> int len(const T &c) { return (int)c.size(); } template <class T> int len(char c[]) { return (int)strlen(c); } long stoi(string s) { long n = 0; for (int i(0), _n(len(s)); i < _n; ++i) n = n * 10 + (s[i] - 48); return n; } int main() { ios_base::sync_with_stdio(false); long m, t, r, w, k, ww, res = 0, ls; cin >> m >> t >> r; vector<int> v, tem; int f = 1; for (int i(0), _n(m); i < _n; ++i) { cin >> w; ls = -100000000000000000LL; if (!f) continue; for (int j = len(v) - 1; j >= 0; j--) { if (v[j] >= w) tem.push_back(v[j]); else break; } if (len(tem) < r) { k = r - len(tem); ww = w; for (int j(0), _n(k); j < _n; ++j) { if (ww + t - 1 >= w) { res++; tem.push_back(ww + t - 1); ww -= 1; } else { f = 0; break; } } } v = tem; tem.clear(); sort(v.begin(), v.end()); } if (f == 0) res = -1; cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct obj { int x, y, ind; obj(int x, int y, int ind) : x(x), y(y), ind(ind) {} obj() {} }; int main() { vector<obj> s; int n, x, y; scanf( %d , &n); for (int i = (1); i <= (n); ++i) { scanf( %d%d , &x, &y); s.push_back(obj(x, y, i)); } sort(s.begin(), s.end(), [](obj a, obj b) { if (a.x / 1000 == b.x / 1000) { if (a.x / 1000 % 2 == 0) return a.y < b.y; else return a.y > b.y; } return a.x / 1000 < b.x / 1000; }); for (auto v : s) printf( %d , v.ind); return 0; }
|
#include <bits/stdc++.h> using namespace std; using PII = pair<int, int>; PII a[300005]; int idx[300005]; map<int, int> mp; int main() { int n; ; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d %d , &a[i].first, &a[i].second); idx[i] = i; } sort(idx, idx + n, [&](int l, int r) { if (a[l].first != a[r].first) return a[l].first > a[r].first; else return a[l].second < a[r].second; }); bool f = false; for (int i = 0; i < n; ++i) { auto it = mp.upper_bound(a[idx[i]].second); if (it != mp.begin()) { f = true; --it; printf( %d %d n , it->second + 1, idx[i] + 1); break; } else { mp[a[idx[i]].second] = idx[i]; } } if (!f) puts( -1 -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T updmax(T& a, T b) { return a = max(a, b); } template <class T> inline T updmin(T& a, T b) { return a = min(a, b); } class Solution { public: void solve() { long long n; string s; cin >> n >> s; vector<int> a(n, 0); vector<int> cnt(n, 0); int x = 0; long long ret = (n * (n + 1)) / 2 - n; for (int i = 0; i < n; i++) { a[i] = x; cnt[x]++; if (i == n - 1 || s[i] != s[i + 1]) x++; } if (x != 1) { for (int i = 0; i < x; i++) { if (i == 0 || i == x - 1) ret -= cnt[i]; else ret -= 2 * cnt[i]; } ret += x - 1; } cout << ret << n ; return; }; }; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); Solution solution; solution.solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long x[300009]; int main() { long long n; cin >> n; for (int i = 0; i < n; i++) cin >> x[i]; sort(x, x + n); long long a = x[0], b = 1, ans = 0; for (int i = 1; i < n; i++) { ans = (ans + x[i] * (2 * b - 1) - a) % 1000000007; a = (2 * a + x[i]) % 1000000007; b = 2 * b % 1000000007; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t; cin >> t; while (t--) { long long int n; cin >> n; string s; cin >> s; long long int oc = 0, zc = 0, fpos = -1, lpos; for (int i = 0; i < (int)n; i++) { if (s[i] == 0 ) zc++; else { oc++; if (fpos == -1) { fpos = i; } lpos = i; } } if (oc == 0) cout << n << n ; else if (zc == 0) cout << 2 * n << n ; else { if (s[0] == 1 ) { cout << 2 * n << n ; } else { cout << 2 * max((n - fpos), (lpos + 1)) << n ; } } } }
|
`timescale 1 ns / 1 ps
module PmodAD1_v1_0 #
(
// Users to add parameters here
// 2x89KSPS with these parameters
parameter INCLUDE_DEBUG_INTERFACE = 0,
parameter AD1_CLOCKS_PER_BIT = 20,//1 bit per 200ns
parameter AD1_CLOCKS_BEFORE_DATA = 60,//600ns
parameter AD1_CLOCKS_AFTER_DATA = 500,//5us
parameter AD1_CLOCKS_BETWEEN_TRANSACTIONS = 400,//4us
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
input Pmod_out_pin10_i,
output Pmod_out_pin10_o,
output Pmod_out_pin10_t,
input Pmod_out_pin1_i,
output Pmod_out_pin1_o,
output Pmod_out_pin1_t,
input Pmod_out_pin2_i,
output Pmod_out_pin2_o,
output Pmod_out_pin2_t,
input Pmod_out_pin3_i,
output Pmod_out_pin3_o,
output Pmod_out_pin3_t,
input Pmod_out_pin4_i,
output Pmod_out_pin4_o,
output Pmod_out_pin4_t,
input Pmod_out_pin7_i,
output Pmod_out_pin7_o,
output Pmod_out_pin7_t,
input Pmod_out_pin8_i,
output Pmod_out_pin8_o,
output Pmod_out_pin8_t,
input Pmod_out_pin9_i,
output Pmod_out_pin9_o,
output Pmod_out_pin9_t,
output wire [1:0] led,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
wire ad1_cs;
wire ad1_sdin0;
wire ad1_sdin1;
wire ad1_sclk;
// Instantiation of Axi Bus Interface S00_AXI
PmodAD1_v1_0_S00_AXI # (
.INCLUDE_DEBUG_INTERFACE(INCLUDE_DEBUG_INTERFACE),
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
.AD1_CLOCKS_PER_BIT(AD1_CLOCKS_PER_BIT),//1 bit per 200ns
.AD1_CLOCKS_BEFORE_DATA(AD1_CLOCKS_BEFORE_DATA),//600ns
.AD1_CLOCKS_AFTER_DATA(AD1_CLOCKS_AFTER_DATA),//5us
.AD1_CLOCKS_BETWEEN_TRANSACTIONS(AD1_CLOCKS_BETWEEN_TRANSACTIONS)//4us
) PmodAD1_v1_0_S00_AXI_inst (
.ad1_cs (ad1_cs ),
.ad1_sdin0 (ad1_sdin0),
.ad1_sdin1 (ad1_sdin1),
.ad1_sclk (ad1_sclk ),
.led(led),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
pmod_bridge_0 PmodAD1_pmod_bridge_0_0
(.in0_I(),
.in0_O(ad1_cs),
.in0_T(1'b0),
.in1_I(ad1_sdin0),
.in1_O(),
.in1_T(1'b1),
.in2_I(ad1_sdin1),
.in2_O(),
.in2_T(1'b1),
.in3_I(),
.in3_O(ad1_sclk),
.in3_T(1'b0),
.out0_I(Pmod_out_pin1_i),
.out0_O(Pmod_out_pin1_o),
.out0_T(Pmod_out_pin1_t),
.out1_I(Pmod_out_pin2_i),
.out1_O(Pmod_out_pin2_o),
.out1_T(Pmod_out_pin2_t),
.out2_I(Pmod_out_pin3_i),
.out2_O(Pmod_out_pin3_o),
.out2_T(Pmod_out_pin3_t),
.out3_I(Pmod_out_pin4_i),
.out3_O(Pmod_out_pin4_o),
.out3_T(Pmod_out_pin4_t),
.out4_I(Pmod_out_pin7_i),
.out4_O(Pmod_out_pin7_o),
.out4_T(Pmod_out_pin7_t),
.out5_I(Pmod_out_pin8_i),
.out5_O(Pmod_out_pin8_o),
.out5_T(Pmod_out_pin8_t),
.out6_I(Pmod_out_pin9_i),
.out6_O(Pmod_out_pin9_o),
.out6_T(Pmod_out_pin9_t),
.out7_I(Pmod_out_pin10_i),
.out7_O(Pmod_out_pin10_o),
.out7_T(Pmod_out_pin10_t)
);
// Add user logic here
// User logic ends
endmodule
|
#include <bits/stdc++.h> using namespace std; int arr[100007]; int main() { int i, n, k, distinct, r; map<int, int> M; while (scanf( %d%d , &n, &k) == 2) { bool flag = true; M.clear(); distinct = 0; for (i = 0; i < n; i++) { scanf( %d , &arr[i]); if (M[arr[i]] == 0) { M[arr[i]]++; distinct++; } else if (flag) { M[arr[i]]++; } if (distinct == k && flag) { r = i; flag = false; } } if (distinct < k) puts( -1 -1 ); else { i = 0; while (M[arr[i]] > 1) { M[arr[i]]--; i++; } if (i > r) i = r; printf( %d %d n , i + 1, r + 1); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; bitset<1000001> L, R; vector<int> H1, H2, V1, V2, res; multiset<int> AA, BB; int A[1000], B[1000]; bool solve(int *A, int s, int e, int S) { int m = (s + e) >> 1; if (s == e || S == 0) { if (S) res.push_back(A[m]); return true; } for (int i = 0; i <= S; i++) L[i] = R[i] = 0; L[0] = R[0] = 1; for (int i = s; i <= m; i++) L |= L << A[i]; for (int i = e; i > m; i--) R |= R << A[i]; for (int i = 0; i <= S; i++) if (L[i] && R[S - i]) { solve(A, s, m, i); solve(A, m + 1, e, S - i); return true; } return false; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ((void)0); ((void)0); ((void)0); int T, N, M; for (cin >> T; T--;) { int H = 0, V = 0, x = 0, y = 0; cin >> N; AA.clear(); BB.clear(); for (int i = 0; i < N; i++) { cin >> A[i]; H += A[i]; AA.insert(A[i]); } cin >> M; for (int i = 0; i < M; i++) { cin >> B[i]; V += B[i]; BB.insert(B[i]); } if ((H & 1) || (V & 1) || N != M || N == 1 || M == 1) { cout << No n ; continue; } sort(A, A + N); sort(B, B + M); res.clear(); if (!solve(A, 0, N - 1, H / 2)) { cout << No n ; continue; } H1.clear(); H2.clear(); for (auto v : res) { H1.push_back(v); AA.erase(AA.find(v)); } for (auto v : AA) H2.push_back(v); res.clear(); if (!solve(B, 0, M - 1, V / 2)) { cout << No n ; continue; } V1.clear(); V2.clear(); for (auto v : res) { V1.push_back(v); BB.erase(BB.find(v)); } for (auto v : BB) V2.push_back(v); if (V1.size() > V2.size()) swap(V1, V2); if (H1.size() < H2.size()) swap(H1, H2); reverse(V1.begin(), V1.end()); reverse(V2.begin(), V2.end()); cout << Yes n ; for (auto &v : V1) v *= -1; for (auto &h : H2) H1.push_back(-h); for (auto v : V2) V1.push_back(v); for (int i = 0; i < N; i++) { y += V1[i]; cout << x << << y << n ; x += H1[i]; cout << x << << y << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { if (b > a) swap(a, b); if (a % b == 0) return b; else return gcd(b, a % b); } long long int a, b, k, k1, k2; int main() { cin >> a >> b; k = (a * b) / gcd(a, b); k1 = k / a; k2 = k / b; if (abs(k1 - k2) == 1) cout << Equal ; else if (k1 > k2) cout << Dasha ; else cout << Masha ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, t, ans = 0, i, a, b, m, x, y; cin >> t; while (t > 0) { cin >> n; vector<int> res; long long es = 0, os = 0; if ((n / 2) % 2 == 0) { cout << YES << endl; for (i = 0; i < n / 2; i++) { res.push_back(2 * (i + 1)); es += 2 * (i + 1); } for (i = 0; i < n / 2; i++) { res.push_back(2 * (i + 1) - 1); os += 2 * (i + 1) - 1; } res[n - 1] += es - os; for (i = 0; i < n; i++) cout << res[i] << ; cout << endl; } else cout << NO << endl; t--; } }
|
#include <bits/stdc++.h> using namespace std; int a1, a2, b1, b2; bool sol(int a, int b) { if (b + 1 < a) return 0; if (b > (a + 1) * 2) return 0; return 1; } int main() { cin >> a1 >> a2 >> b1 >> b2; if (sol(a1, b2) || sol(a2, b1)) cout << YES ; else cout << NO ; return 0; }
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#include <bits/stdc++.h> using namespace std; int st[100100][20]; vector<int> graph[100100], ind[100100]; int lev[100100]; int t[100100], l[100100], lg[100100]; int s[100100]; void blg(int n) { lg[0] = -1; for (int i = 0; i < n; ++i) lg[i + 1] = lg[i] + !(i & (i + 1)); } void dfs(int u, int p, int l) { st[u][0] = p; for (int i = 1; (1 << i) <= l; ++i) st[u][i] = st[st[u][i - 1]][i - 1]; lev[u] = l; for (int v : graph[u]) if (v != p) dfs(v, u, l + 1); } int getParent(int u, int d) { if (lev[u] < d) return -1; for (int i = d; i; i -= i & -i) u = st[u][lg[i & -i]]; return u; } int LCA(int u, int v) { if (lev[u] < lev[v]) v = getParent(v, lev[v] - lev[u]); if (lev[u] > lev[v]) u = getParent(u, lev[u] - lev[v]); int r = lev[u], l = 0, m; while (l < r) { m = (l + r) / 2; if (getParent(u, m) == getParent(v, m)) r = m; else l = m + 1; } return getParent(u, l); } int solve(int u, int p) { int y = l[u] - t[u]; for (int j = 0; j < graph[u].size(); ++j) { int v = graph[u][j]; if (v != p) { y += s[ind[u][j]] = solve(v, u); } } return y; } int main() { int n, k, x, y; cin >> n; blg(n); for (int i = 1; i < n; ++i) { scanf( %d%d , &x, &y); graph[x].push_back(y), graph[y].push_back(x); ind[x].push_back(i); ind[y].push_back(i); } dfs(1, 1, 0); cin >> k; while (k--) { scanf( %d%d , &x, &y); t[LCA(x, y)] += 2; l[x]++, l[y]++; } solve(1, 0); for (int i = 1; i < n; ++i) cout << s[i] << ; }
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#include <bits/stdc++.h> using namespace std; const double pi = 2 * acos(0); unsigned long long int binpow(unsigned long long int b, unsigned long long int n) { if (n == 0) return 1; if (n == 1) return b; if (n & 1) return binpow(b, n - 1) * b; else return binpow(b * b, n / 2); } long long int bigmod(long long int b, long long int n, long long int m) { if (n == 0) return 1; if (n % 2 == 0) { long long int x = bigmod(b, n / 2, m) % m; return (x * x) % m; } else return ((b % m) * bigmod(b, n - 1, m) % m) % m; } void start() {} long long int to_num(string &s) { stringstream second; second << s; long long int n; second >> n; return n; } long long int get(long long int n) { long long int s = 0; while (n) { s += (n % 10); n /= 10; } return s; } void solve() { long long int n, cn = 0; cin >> n; string s = to_string(n), tmp = ; for (long long int i = 0; i < s.size() - 1; i++) { tmp += 9 ; } if (n < 10) { cout << n << n ; return; } cn = (s.size() - 1) * 9; long long int left = n - to_num(tmp); cn += get(left); cout << cn << n ; } int main(int argc, char const *argv[]) { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); start(); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int ax[4], ay[4], bx[4], by[4]; int xmin = 1000, xmax = -1000, ymin = 1000, ymax = -1000; bool f() { for (int i = 0; i < 4; i++) { if (bx[i] >= xmin && bx[i] <= xmax && by[i] >= ymin && by[i] <= ymax) { return 1; } } double X = ((double)bx[0] + (double)bx[3]) / 2, Y = ((double)by[0] + (double)by[3]) / 2; if (X >= xmin && X <= xmax && Y >= ymin && Y <= ymax) { return 1; } return 0; } void rotat() { int X, Y; xmin = ymin = 1000; xmax = ymax = -1000; for (int i = 0; i < 4; i++) { X = ax[i] + ay[i]; Y = ax[i] - ay[i]; ax[i] = X; ay[i] = Y; X = bx[i] + by[i]; Y = bx[i] - by[i]; bx[i] = X; by[i] = Y; swap(ax[i], bx[i]); swap(by[i], ay[i]); xmin = min(xmin, ax[i]); xmax = max(xmax, ax[i]); ymin = min(ymin, ay[i]); ymax = max(ymax, ay[i]); } } int main() { for (int i = 0; i < 4; i++) { cin >> ax[i] >> ay[i]; xmin = min(xmin, ax[i]); xmax = max(xmax, ax[i]); ymin = min(ymin, ay[i]); ymax = max(ymax, ay[i]); } for (int i = 0; i < 4; i++) { cin >> bx[i] >> by[i]; } if (f()) { cout << Yes n ; return 0; } rotat(); if (f()) { cout << Yes n ; return 0; } cout << No n ; return 0; }
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// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: async_dpram_40W_32D.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module async_dpram_40W_32D (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [39:0] data;
input [4:0] rdaddress;
input rdclock;
input [4:0] wraddress;
input wrclock;
input wren;
output [39:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [39:0] sub_wire0;
wire [39:0] q = sub_wire0[39:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (wrclock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.clock1 (rdclock),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({40{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.numwords_b = 32,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 40,
altsyncram_component.width_b = 40,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1280"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "40"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "40"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "40"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "40"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "MLAB"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "40"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "40"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 40 0 INPUT NODEFVAL "data[39..0]"
// Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL "q[39..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL "rdaddress[4..0]"
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL "wraddress[4..0]"
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 rdaddress 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 40 0 data 0 0 40 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 40 0 @q_b 0 0 40 0
// Retrieval info: GEN_FILE: TYPE_NORMAL async_dpram_40W_32D.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_dpram_40W_32D.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_dpram_40W_32D.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_dpram_40W_32D.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_dpram_40W_32D_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL async_dpram_40W_32D_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
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