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#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int main() { int n, l[300], c[300]; cin >> n; for (int i = 0; i < n; i++) cin >> l[i]; for (int i = 0; i < n; i++) cin >> c[i]; unordered_map<int, int> um; for (int i = 0; i < n; i++) if (um.find(l[i]) != um.end()) um[l[i]] = min(um[l[i]], c[i]); else um.emplace(l[i], c[i]); for (int i = 0; i < n; i++) { vector<pair<int, int>> ve; for (auto& elem : um) { int g = gcd(elem.first, l[i]); if (um.find(g) != um.end()) um[g] = min(um[g], elem.second + c[i]); else ve.emplace_back(g, elem.second + c[i]); } for (auto& elem : ve) um.insert(elem); } cout << (um[1] ?: -1) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; map<string, int> hsh; int check(string str, int l, int r) { int pos = 0, cur = 0; for (int i = r; i >= l; i--) { if (str[i] == ( ) cur++; else if (str[i] == ) ) cur--; else if (cur == 0 && pos == 0 && (str[i] == * || str[i] == / )) pos = i; else if (cur == 0 && (str[i] == + || str[i] == - )) { int lft = check(str, l, i - 1), rgt = check(str, i + 1, r); if (lft == 2 || rgt == 2) return 2; if (str[i] == + ) return 3; else if (str[i] == - ) { if (rgt == 3) return 2; else return 3; } } } if (pos) { int lft = check(str, l, pos - 1), rgt = check(str, pos + 1, r); if (lft == 2 || rgt == 2) return 2; if (str[pos] == * ) { if (lft == 3 || rgt == 3) return 2; else return 4; } else if (str[pos] == / ) { if (lft == 3 || rgt == 3 || rgt == 4) return 2; else return 4; } } else if (str[l] == ( && str[r] == ) ) { if (check(str, l + 1, r - 1) == 2) return 2; else return 1; } else { string res = ; for (int i = l; i <= r; i++) res += str[i]; if (hsh[res]) return hsh[res]; else return 1; } } int main() { int n; string s, exp, ques; cin >> n; for (int i = 0; i < n; i++) { cin >> s; if (s == # ) cin >> s; cin >> s; getline(cin, exp); ques = ; for (int j = 0; j < exp.length(); j++) if (exp[j] != ) ques += exp[j]; hsh[s] = check(ques, 0, ques.length() - 1); } getline(cin, exp); ques = ; for (int i = 0; i < exp.length(); i++) if (exp[i] != ) ques += exp[i]; if (check(ques, 0, ques.length() - 1) == 2) cout << Suspicious << endl; else cout << OK << endl; return 0; }
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#include <bits/stdc++.h> #pragma optimize( -O3 ) using namespace std; const long long mod = 998244353; int n, m, u, v; pair<vector<int>, int> adj[1000006]; int alr[1000006]; long long ans = 0, cr = 0; bool check(int i, int j) { if ((int)adj[i].first.size() != (int)adj[j].first.size()) return false; int x = (int)adj[i].first.size(); int in1 = 0, in2 = 0; while (in1 < x && in2 < x) { if (adj[i].first[in1] == adj[j].second) { in1++; continue; } if (adj[j].first[in2] == adj[i].second) { in2++; continue; } if (adj[i].first[in1] != adj[j].first[in2]) return false; in1++; in2++; } return true; } bool check2(int i, int j) { if ((int)adj[i].first.size() != (int)adj[j].first.size()) return false; int x = (int)adj[i].first.size(); int in1 = 0; while (in1 < x) { if (adj[i].first[in1] != adj[j].first[in1]) return false; in1++; } return true; } void dfs(int i) { for (auto &x : adj[i].first) { if (x < i) continue; if (check(i, x)) ans++; } } void solve() { cin >> n >> m; for (long long i = (long long)0; i != (long long)m; i = i + 1) { cin >> u >> v; u--; v--; adj[u].first.push_back(v); adj[v].first.push_back(u); } for (long long i = (long long)0; i != (long long)n; i = i + 1) { adj[i].second = i; sort(adj[i].first.begin(), adj[i].first.end()); } for (long long i = (long long)0; i != (long long)n; i = i + 1) { dfs(i); }; sort(adj, adj + n); for (long long i = (long long)0; i != (long long)n; i = i + 1) ; for (long long i = (long long)1; i != (long long)n; i = i + 1) { if (check2(i, i - 1)) { cr++; ; ans += 1ll * cr; } else { cr = 0; } } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; t = 1; while (t--) { solve(); } }
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#if !defined(ONLINE_JUDGE) #include prettyprint.hpp #include debug.h #else #include <bits/stdc++.h> using namespace std; #define deb(...) 1729 #define dbg(...) 29 #define cer(x) 13 #endif const bool testcase = 1; typedef long long int ll; const ll mod1 = 1000000007; const ll mod2 = 998244353; #define fast ios_base::sync_with_stdio(0);cin.tie(NULL) #define test int T_T = 1; if(testcase){cin>>T_T;}while(T_T--) #define all(ve) ve.begin(),ve.end() const ll N = 1e7 + 7; std::vector<ll> spf, prime; std::vector<bool> isp; void sieve(ll MAXN) { spf.resize(MAXN); spf[1] = 1; for (int i=2; i<MAXN; i++) spf[i] = i; for (int i=4; i<MAXN; i+=2) spf[i] = 2; for (int i=3; i*i<MAXN; i++) { if (spf[i] == i) { for (int j=i*i; j<MAXN; j+=i) { if (spf[j]==j) spf[j] = i; } } } } void linearSieve(ll n) { spf.resize(n); isp.resize(n,true); isp[0] = isp[1] = 0; isp[2] = 1; for (int i = 2; i <= n; ++i) { if(isp[i]) { prime.push_back(i); spf[i] = i; } for (int j = 0; j < prime.size() && prime[j] <= spf[i] && prime[j] * i <= N; ++j) { isp[i*prime[j]] = 0; spf[i*prime[j]] = prime[j]; } } } map<ll,ll> getFactor(ll x) { map<ll,ll> ret; while (x != 1) { ret[spf[x]]++; x = x / spf[x]; } return ret; } // SOLVE void solve() { // cout << N << n ; // dbg(spf); ll n, k; cin >> n >> k; std::vector<ll> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; // dbg(a[i]); map<ll,ll> pf = getFactor(a[i]); // dbg(pf); ll cur = 1; for(auto [u, v]: pf) { if(v & 1) { cur = cur * u; } } a[i] = cur; } set<ll> st; ll ans = 0; for (int i = 0; i < n; ++i) { if(st.find(a[i]) != st.end()) { ans++; st.clear(); } st.insert(a[i]); // while(!st.count()) } if(st.size()) { ans++; } cout << ans << n ; } //MAIN int main(){ fast; #ifndef ONLINE_JUDGE // for getting input from input.txt freopen( input.txt , r , stdin); // for writing output to output.txt freopen( output.txt , w , stdout); // for debug in error.txt freopen( error.txt , w , stderr); #endif sieve(N); test { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int min(int a, int b) { if (a > b) return b; else return a; } int main() { int tc; cin >> tc; while (tc--) { long long int n; cin >> n; vector<int> a(n + 1, 0); vector<int> ans(n + 1, 0); for (int i = 1; i <= n; i++) { cin >> a[i]; } vector<int> ones; vector<int> zeros; ; string s; cin >> s; int one = 0; for (int i = 0; i < n; i++) { if (s[i] == 1 ) { ones.push_back(a[i + 1]); } else zeros.push_back(a[i + 1]); } int k = ones.size(); int max = n - k; sort(ones.begin(), ones.end()); sort(zeros.begin(), zeros.end()); map<int, int> m; map<int, int> p; int j = n; for (int i = k - 1; i >= 0; i--) { m[ones[i]] = j; j--; } for (int i = 0; i < max; i++) { p[zeros[i]] = i + 1; } for (int i = 1; i <= n; i++) { if (s[i - 1] == 0 ) { ans[i] = p[a[i]]; } else { ans[i] = m[a[i]]; } } for (int i = 1; i <= n; i++) cout << ans[i] << ; cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 100007; long long i, j, k, n, m, t, x, y, ans; long long pw2[32]; long long a[MAXN]; void calPowerTwo() { long long i, j, k; pw2[0] = 1; for (i = 1; i < 32; i++) { pw2[i] = pw2[i - 1] * 2; } } int main() { calPowerTwo(); while (cin >> n) { for (i = 0; i < n; i++) { cin >> a[i]; } ans = 0; for (i = 0; i < n - 1; i++) { ans += a[i]; k = 0; while (i + pw2[k] < n) { k++; } k--; a[i + pw2[k]] += a[i]; a[i] = 0; cout << ans << endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long M = 1e9, I = 1e18; const int mxn = 1e5; int t, n; string s, pr, ans; bool fl; void solve() { fl = 0; ans = ; cin >> n; cin >> pr; ans = pr; for (int i = 1; i < n - 2; i++) { cin >> s; if (pr[1] != s[0]) { fl = 1; ans += s[0]; } ans += s[1]; pr = s; } if (!fl) ans = a + ans; cout << ans << endl; } int main() { cin >> t; while (t--) solve(); }
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#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 5; const int MOD = 1e9 + 7; vector<int> g[N + N]; int mat[N][N], p[N + N], sub[N + N], vis[N + N]; int ans[N + N], instack[N + N], go = true, ct = 0; vector<pair<int, int>> extime; void putNumbers(int node) { vis[node] = 1; instack[node] = true; ct++; for (auto it : g[node]) { if (!vis[it]) { putNumbers(it); } else if (instack[it]) go = false; } instack[node] = false; extime.push_back({ct, node}); ct++; } void getAns(int node) { vis[node] = 1; ans[node] = max(ans[node], 1); for (auto it : g[node]) if (!vis[it]) { ans[it] = max(ans[it], ans[node] + 1); } } int root(int u) { while (p[u] != u) { p[u] = p[p[u]]; u = p[u]; } return u; } void merge(int uu, int vv) { int u = root(uu), v = root(vv); if (u == v) return; if (sub[u] < sub[v]) swap(u, v); p[v] = u; sub[u] += sub[v]; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m, i, j; cin >> n >> m; for (i = 1; i <= n + m; i++) { p[i] = i; sub[i] = 1; } for (i = 1; i <= n; i++) { string s; cin >> s; for (j = 0; j < m; j++) { if (s[j] == < ) mat[i][j + 1] = -1; else if (s[j] == = ) { merge(i, n + j + 1); mat[i][j + 1] = 0; } else mat[i][j + 1] = 1; } } for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) { int u = root(i), v = root(n + j); if (mat[i][j] < 0) { if (u == v) { cout << No n ; return 0; } g[u].push_back(v); } if (mat[i][j] > 0) { if (u == v) { cout << No n ; return 0; } g[v].push_back(u); } } for (i = 1; i <= n + m; i++) if (!vis[i] && p[i] == i) { putNumbers(i); if (!go) { cout << No n ; return 0; } } sort(extime.begin(), extime.end()); reverse(extime.begin(), extime.end()); memset(vis, 0, sizeof(vis)); for (auto it : extime) if (!vis[it.second]) { getAns(it.second); } cout << Yes n ; for (i = 1; i <= n + m; i++) { cout << ans[root(i)] << ; if (i == n) cout << n ; } cout << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, c; cin >> n >> c; vector<long long> a(n); multiset<long long> p; for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) { long long x; cin >> x; p.insert(x); } long long np = a[c - 1] + *p.rbegin(), ans = 1; auto it = p.end(); it--; p.erase(it); for (long long i = 0; i < n; i++) { if (i == c - 1) continue; long long x = np - a[i]; auto f = p.upper_bound(x); if (f != p.begin()) { f--; p.erase(f); } else { ans++; } } cout << ans << n ; return 0; }
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#include <bits/stdc++.h> int main() { int n; scanf( %i , &n); printf( %li , (long int)n / 2 * 3); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_1_V
`define SKY130_FD_SC_HD__AND4B_1_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4b_1 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4b_1 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_1_V
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#include <bits/stdc++.h> using namespace std; double ans = 1; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); if (k >= m) printf( 1 n ); else if (n + k < m) printf( 0 n ); else { for (int i = 1; i <= k + 1; i++) ans = ans * (m - i + 1) / (n + i); ans = 1.0 - ans; printf( %.6lf , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { string s; int i, j, k, p, len, n; cin >> n >> k >> s; int arr[30] = {0}; char x = a ; for (i = 0; i < 26; i++) { x = a + i; p = 0; for (j = 0; j < n; j++) { if (s[j] == x) p++; else p = 0; if (p == k) { arr[i]++; p = 0; } } } p = 0; for (i = 0; i < 26; i++) { p = max(p, arr[i]); } cout << p << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; struct operacion { string name; int x; operacion() {} operacion(string name, int x) : name(name), x(x) {} }; int n; priority_queue<int, vector<int>, greater<int> > q; vector<operacion> v; int main() { ios::sync_with_stdio(false); cin >> n; for (int cas = 0; cas < n; cas++) { string name; cin >> name; if (name == insert ) { int x; cin >> x; v.push_back(operacion(name, x)); q.push(x); } else if (name == getMin ) { int x; cin >> x; while (int(q.size()) > 0 and q.top() < x) { v.push_back(operacion( removeMin , 0)); q.pop(); } if (int(q.size()) == 0 or q.top() != x) { v.push_back(operacion( insert , x)); q.push(x); } v.push_back(operacion( getMin , x)); } else if (name == removeMin ) { if (int(q.size()) == 0) { v.push_back(operacion( insert , 1)); q.push(1); } v.push_back(operacion( removeMin , 0)); q.pop(); } } cout << int(v.size()) << endl; for (int i = 0; i < int(v.size()); i++) { cout << v[i].name; if (v[i].name != removeMin ) cout << << v[i].x; cout << endl; } }
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/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
test_recFNToRecFN#(
parameter inExpWidth = 3,
parameter inSigWidth = 3,
parameter outExpWidth = 3,
parameter outSigWidth = 3
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
parameter maxNumErrors = 20;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam inFormatWidth = inExpWidth + inSigWidth;
localparam outFormatWidth = outExpWidth + outSigWidth;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [(`floatControlWidth - 1):0] control;
reg [2:0] roundingMode;
reg [(inFormatWidth - 1):0] in;
reg [(outFormatWidth - 1):0] expectOut;
reg [4:0] expectExceptionFlags;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [inFormatWidth:0] recIn;
fNToRecFN#(inExpWidth, inSigWidth) fNToRecFN_in(in, recIn);
wire [outFormatWidth:0] recExpectOut;
fNToRecFN#(outExpWidth, outSigWidth)
fNToRecFN_expectOut(expectOut, recExpectOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [outFormatWidth:0] recOut;
wire [4:0] exceptionFlags;
recFNToRecFN#(inExpWidth, inSigWidth, outExpWidth, outSigWidth)
recFNToRecFN(control, recIn, roundingMode, recOut, exceptionFlags);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire sameOut;
sameRecFN#(outExpWidth, outSigWidth)
same_recOut(recOut, recExpectOut, sameOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer errorCount, count, partialCount;
initial begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$fwrite(
'h80000002,
"Testing 'recF%0dToRecF%0d'",
inFormatWidth,
outFormatWidth
);
if ($fscanf('h80000000, "%h %h", control, roundingMode) < 2) begin
$fdisplay('h80000002, ".\n--> Invalid test-cases input.");
`finish_fail;
end
$fdisplay(
'h80000002,
", control %H, rounding mode %0d:",
control,
roundingMode
);
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
errorCount = 0;
count = 0;
partialCount = 0;
begin :TestLoop
while (
$fscanf(
'h80000000, "%h %h %h", in, expectOut, expectExceptionFlags
) == 3
) begin
#1;
partialCount = partialCount + 1;
if (partialCount == 10000) begin
count = count + 10000;
$fdisplay('h80000002, "%0d...", count);
partialCount = 0;
end
if (
!sameOut || (exceptionFlags !== expectExceptionFlags)
) begin
if (errorCount == 0) begin
$display(
"Errors found in 'recF%0dToRecF%0d', control %H, rounding mode %0d:",
inFormatWidth,
outFormatWidth,
control,
roundingMode
);
end
$write("%H => %H %H", recIn, recOut, exceptionFlags);
if (
(outFormatWidth > 64)
|| (inFormatWidth + outFormatWidth > 160)
) begin
$write("\n\t");
end else begin
$write(" ");
end
$display(
"expected %H %H", recExpectOut, expectExceptionFlags);
errorCount = errorCount + 1;
if (errorCount == maxNumErrors) disable TestLoop;
end
#1;
end
end
count = count + partialCount;
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
if (errorCount) begin
$fdisplay(
'h80000002,
"--> In %0d tests, %0d errors found.",
count,
errorCount
);
`finish_fail;
end else if (count == 0) begin
$fdisplay('h80000002, "--> Invalid test-cases input.");
`finish_fail;
end else begin
$display(
"In %0d tests, no errors found in 'recF%0dToRecF%0d', control %H, rounding mode %0d.",
count,
inFormatWidth,
outFormatWidth,
control,
roundingMode
);
end
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$finish;
end
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_recF16ToRecF32;
test_recFNToRecFN#(5, 11, 8, 24) test_recF16ToRecF32();
endmodule
module test_recF16ToRecF64;
test_recFNToRecFN#(5, 11, 11, 53) test_recF16ToRecF64();
endmodule
module test_recF16ToRecF128;
test_recFNToRecFN#(5, 11, 15, 113) test_recF16ToRecF128();
endmodule
module test_recF32ToRecF16;
test_recFNToRecFN#(8, 24, 5, 11) test_recF32ToRecF16();
endmodule
module test_recF32ToRecF64;
test_recFNToRecFN#(8, 24, 11, 53) test_recF32ToRecF64();
endmodule
module test_recF32ToRecF128;
test_recFNToRecFN#(8, 24, 15, 113) test_recF32ToRecF128();
endmodule
module test_recF64ToRecF16;
test_recFNToRecFN#(11, 53, 5, 11) test_recF64ToRecF16();
endmodule
module test_recF64ToRecF32;
test_recFNToRecFN#(11, 53, 8, 24) test_recF64ToRecF32();
endmodule
module test_recF64ToRecF128;
test_recFNToRecFN#(11, 53, 15, 113) test_recF64ToRecF128();
endmodule
module test_recF128ToRecF16;
test_recFNToRecFN#(15, 113, 5, 11) test_recF128ToRecF16();
endmodule
module test_recF128ToRecF32;
test_recFNToRecFN#(15, 113, 8, 24) test_recF128ToRecF32();
endmodule
module test_recF128ToRecF64;
test_recFNToRecFN#(15, 113, 11, 53) test_recF128ToRecF64();
endmodule
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#include <bits/stdc++.h> const int maxn = 1005; int p[maxn], d[maxn], l[maxn][2], nl, ti; int main() { int n, h, r, c; scanf( %d%d%d , &n, &h, &r); for (int i = 0; i != n; ++i) scanf( %d%d , p + i, d + i); c = h; while (true) { c += r; if (c > h) c = h; if (c <= 0) break; int t = 0, pos = -1; for (int i = 0; i != n; ++i) if (c * 100 <= h * p[i] && t < d[i]) t = d[i], pos = i + 1; if (~pos) { r -= t; l[nl][0] = ti; l[nl++][1] = pos; d[pos - 1] = -1; } else if (r >= 0) { puts( NO ); return 0; } ti++; } puts( YES ); printf( %d %d n , ti, nl); for (int i = 0; i != nl; ++i) printf( %d %d n , l[i][0], l[i][1]); return 0; }
|
/*
* NAME
*
* regr - register of data that can be held or cleared
*
* DESCRIPTION
*
* The regr (register) module can be used to store data in the current
* cylcle so it will be output on the next cycle. Signals are also
* provided to hold the data or clear it. The hold and clear signals
* are both synchronous with the clock.
*
* The first example creates a 8-bit register. The clear and hold
* signals are taken from elsewhere.
*
* wire [7:0] data_s1;
* wire [7:0] data_s2;
*
* regr #(.N(8)) r1(.clk(clk), .clear(clear), .hold(hold),
* .in(data_s1), .out(data_s2))
*
* Multiple signals can be grouped together using array notation.
*
* regr #(.N(8)) r1(.clk(clk), .clear(clear), .hold(hold),
* .in({x1, x2}), .out({y1, y2}))
*/
`ifndef _regr
`define _regr
module regr (
input clk,
input clear,
input hold,
input wire [N-1:0] in,
output reg [N-1:0] out);
parameter N = 1;
always @(posedge clk) begin
if (clear)
out <= {N{1'b0}};
else if (hold)
out <= out;
else
out <= in;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; char st1[100010], st2[100010]; int a1[100010], a2[100010], b1[100010], b2[100010]; int n; int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || 9 < ch) { if (ch == - ) f = -1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int main() { scanf( %s%s , st1 + 1, st2 + 1); for (int i = 1; st1[i] != 0; i++) { if (st1[i] == A ) a1[i] = a1[i - 1] + 1; b1[i] = b1[i - 1] + (st1[i] != A ); } for (int i = 1; st2[i] != 0; i++) { if (st2[i] == A ) a2[i] = a2[i - 1] + 1; b2[i] = b2[i - 1] + (st2[i] != A ); } n = read(); while (n--) { int l1 = read(), r1 = read(), l2 = read(), r2 = read(), ok = 1; int s1 = b1[r1] - b1[l1 - 1], s2 = b2[r2] - b2[l2 - 1]; int x1 = min(r1 - l1 + 1, a1[r1]), x2 = min(r2 - l2 + 1, a2[r2]); if (s1 > s2 || (s1 + s2) % 2 == 1 || x1 < x2) ok = 0; if (s1 == s2 && x1 % 3 != x2 % 3 || s1 == 0 && x1 == x2 && s1 != s2) ok = 0; printf( %d , ok); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSBP_2_V
`define SKY130_FD_SC_LS__DFSBP_2_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSBP_2_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2011 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer i;
reg [63:0] b;
real r, r2;
integer cyc=0;
realtime uninit;
initial if (uninit != 0.0) $stop;
sub_cast_bug374 sub (.cyc5(cyc[4:0]), .*);
initial begin
// rtoi truncates
if ($rtoi(36.7) != 36) $stop;
if ($rtoi(36.5) != 36) $stop;
if ($rtoi(36.4) != 36) $stop;
// casting rounds
if ((integer '(36.7)) != 37) $stop;
if ((integer '(36.5)) != 37) $stop;
if ((integer '(36.4)) != 36) $stop;
// assignment rounds
// verilator lint_off REALCVT
i = 36.7; if (i != 37) $stop;
i = 36.5; if (i != 37) $stop;
i = 36.4; if (i != 36) $stop;
r = 10'd38; if (r!=38.0) $stop;
// verilator lint_on REALCVT
// operators
if ((-(1.5)) != -1.5) $stop;
if ((+(1.5)) != 1.5) $stop;
if (((1.5)+(1.25)) != 2.75) $stop;
if (((1.5)-(1.25)) != 0.25) $stop;
if (((1.5)*(1.25)) != 1.875) $stop;
if (((1.5)/(1.25)) != 1.2) $stop;
//
if (((1.5)==(2)) != 1'b0) $stop; // note 2 becomes real 2.0
if (((1.5)!=(2)) != 1'b1) $stop;
if (((1.5)> (2)) != 1'b0) $stop;
if (((1.5)>=(2)) != 1'b0) $stop;
if (((1.5)< (2)) != 1'b1) $stop;
if (((1.5)<=(2)) != 1'b1) $stop;
if (((1.5)==(1.5)) != 1'b1) $stop;
if (((1.5)!=(1.5)) != 1'b0) $stop;
if (((1.5)> (1.5)) != 1'b0) $stop;
if (((1.5)>=(1.5)) != 1'b1) $stop;
if (((1.5)< (1.5)) != 1'b0) $stop;
if (((1.5)<=(1.5)) != 1'b1) $stop;
if (((1.6)==(1.5)) != 1'b0) $stop;
if (((1.6)!=(1.5)) != 1'b1) $stop;
if (((1.6)> (1.5)) != 1'b1) $stop;
if (((1.6)>=(1.5)) != 1'b1) $stop;
if (((1.6)< (1.5)) != 1'b0) $stop;
if (((1.6)<=(1.5)) != 1'b0) $stop;
//
if (((0.0)?(2.0):(1.1)) != 1.1) $stop;
if (((1.5)?(2.0):(1.1)) != 2.0) $stop;
//
if (!1.7) $stop;
if (!(!0.0)) $stop;
if (1.8 && 0.0) $stop;
if (!(1.8 || 0.0)) $stop;
//
i=0;
for (r=1.0; r<2.0; r=r+0.1) i++;
if (i!=10) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
end
else if (cyc<90) begin
if ($time != {32'h0, $rtoi($realtime)}) $stop;
if ($itor(cyc) != cyc) $stop;
//Unsup: if ((real `($time)) != $realtime) $stop;
r = $itor(cyc*2);
i = $rtoi(r);
if (i!=cyc*2) $stop;
//
r = $itor(cyc)/1.5;
b = $realtobits(r);
r2 = $bitstoreal(b);
if (r != r2) $stop;
//
// Trust the integer math as a comparison
r = $itor(cyc);
if ($rtoi(-r) != -cyc) $stop;
if ($rtoi(+r) != cyc) $stop;
if ($rtoi(r+2.0) != (cyc+2)) $stop;
if ($rtoi(r-2.0) != (cyc-2)) $stop;
if ($rtoi(r*2.0) != (cyc*2)) $stop;
if ($rtoi(r/2.0) != (cyc/2)) $stop;
r2 = (2.0/(r-60)); // When zero, result indeterminate, but no crash
//
r2 = $itor(cyc);
case (r)
(r2-1.0): $stop;
r2: ;
default: $stop;
endcase
//
r = $itor(cyc);
if ((r==50.0) != (cyc==50)) $stop;
if ((r!=50.0) != (cyc!=50)) $stop;
if ((r> 50.0) != (cyc> 50)) $stop;
if ((r>=50.0) != (cyc>=50)) $stop;
if ((r< 50.0) != (cyc< 50)) $stop;
if ((r<=50.0) != (cyc<=50)) $stop;
//
if ($rtoi((r-50.0) ? 10.0 : 20.0)
!= (((cyc-50)!=0) ? 10 : 20)) $stop;
//
if ((!(r-50.0)) != (!((cyc-50) != 0))) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub_cast_bug374(input clk, input [4:0] cyc5);
integer i;
always @(posedge clk) begin
i <= integer'(cyc5);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i; long long sum = 0, z = 0, s = 0, m = 0, mm = 0; cin >> n; vector<long long> a(n); for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < (n - 1); i++) { if (i % 2 == 0) sum = sum + abs(a[i + 1] - a[i]); else sum = max(z, sum - abs(a[i + 1] - a[i])); m = max(m, sum); } for (i = 1; i < (n - 1); i++) { if (i % 2 == 1) s = s + abs(a[i + 1] - a[i]); else s = max(z, s - abs(a[i + 1] - a[i])); m = max(s, m); } cout << m; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9643_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pn_type);
// adc interface
input adc_clk;
input [13:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input adc_pn_type;
// internal registers
reg adc_pn_en = 'd0;
reg [13:0] adc_data_in = 'd0;
reg [13:0] adc_data_d = 'd0;
reg [29:0] adc_pn_data = 'd0;
reg adc_pn_en_d = 'd0;
reg adc_pn_match_d_1 = 'd0;
reg adc_pn_match_d_0 = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
// internal signals
wire [29:0] adc_pn_data_in_s;
wire adc_pn_match_d_1_s;
wire adc_pn_match_d_0_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire [29:0] adc_pn_data_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// PN23 function
function [29:0] pn23;
input [29:0] din;
reg [29:0] dout;
begin
dout[29] = din[22] ^ din[17];
dout[28] = din[21] ^ din[16];
dout[27] = din[20] ^ din[15];
dout[26] = din[19] ^ din[14];
dout[25] = din[18] ^ din[13];
dout[24] = din[17] ^ din[12];
dout[23] = din[16] ^ din[11];
dout[22] = din[15] ^ din[10];
dout[21] = din[14] ^ din[ 9];
dout[20] = din[13] ^ din[ 8];
dout[19] = din[12] ^ din[ 7];
dout[18] = din[11] ^ din[ 6];
dout[17] = din[10] ^ din[ 5];
dout[16] = din[ 9] ^ din[ 4];
dout[15] = din[ 8] ^ din[ 3];
dout[14] = din[ 7] ^ din[ 2];
dout[13] = din[ 6] ^ din[ 1];
dout[12] = din[ 5] ^ din[ 0];
dout[11] = din[ 4] ^ din[22] ^ din[17];
dout[10] = din[ 3] ^ din[21] ^ din[16];
dout[ 9] = din[ 2] ^ din[20] ^ din[15];
dout[ 8] = din[ 1] ^ din[19] ^ din[14];
dout[ 7] = din[ 0] ^ din[18] ^ din[13];
dout[ 6] = din[22] ^ din[12];
dout[ 5] = din[21] ^ din[11];
dout[ 4] = din[20] ^ din[10];
dout[ 3] = din[19] ^ din[ 9];
dout[ 2] = din[18] ^ din[ 8];
dout[ 1] = din[17] ^ din[ 7];
dout[ 0] = din[16] ^ din[ 6];
pn23 = dout;
end
endfunction
// PN9 function
function [29:0] pn9;
input [29:0] din;
reg [29:0] dout;
begin
dout[29] = din[ 8] ^ din[ 4];
dout[28] = din[ 7] ^ din[ 3];
dout[27] = din[ 6] ^ din[ 2];
dout[26] = din[ 5] ^ din[ 1];
dout[25] = din[ 4] ^ din[ 0];
dout[24] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[23] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[22] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[21] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[20] = din[ 8] ^ din[ 0];
dout[19] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[18] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[17] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[16] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[15] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[14] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[13] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[12] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[11] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[10] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[ 9] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 8] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 7] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 6] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 5] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 4] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 3] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 2] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 1] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 0] = din[ 6] ^ din[ 8] ^ din[ 0];
pn9 = dout;
end
endfunction
// pn sequence checking algorithm is commonly used in most applications.
// if oos is asserted (pn is out of sync):
// the next sequence is generated from the incoming data.
// if 16 sequences match consecutively, oos is cleared (de-asserted).
// if oos is de-asserted (pn is in sync)
// the next sequence is generated from the current sequence.
// if 64 sequences mismatch consecutively, oos is set (asserted).
// if oos is de-asserted, any spurious mismatches sets the error register.
// ideally, processor should make sure both oos == 0x0 and err == 0x0.
assign adc_pn_data_in_s[29:15] = {adc_pn_data[29], adc_data_d};
assign adc_pn_data_in_s[14:0] = {adc_pn_data[14], adc_data_in};
assign adc_pn_match_d_1_s = (adc_pn_data_in_s[28:15] == adc_pn_data[28:15]) ? 1'b1 : 1'b0;
assign adc_pn_match_d_0_s = (adc_pn_data_in_s[13:0] == adc_pn_data[13:0]) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_pn_data_in_s == 30'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d_1 & adc_pn_match_d_0 & adc_pn_match_z;
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn running sequence
always @(posedge adc_clk) begin
adc_pn_en <= ~adc_pn_en;
adc_data_in <= {~adc_data[13], adc_data[12:0]};
adc_data_d <= adc_data_in;
if (adc_pn_en == 1'b1) begin
if (adc_pn_type == 1'b0) begin
adc_pn_data <= pn9(adc_pn_data_s);
end else begin
adc_pn_data <= pn23(adc_pn_data_s);
end
end
end
// pn oos and counters (64 to clear and set).
always @(posedge adc_clk) begin
adc_pn_en_d <= adc_pn_en;
adc_pn_match_d_1 <= adc_pn_match_d_1_s;
adc_pn_match_d_0 <= adc_pn_match_d_0_s;
adc_pn_match_z <= adc_pn_match_z_s;
adc_pn_err <= adc_pn_en_d & adc_pn_err_s;
if (adc_pn_en_d == 1'b1) begin
if (adc_pn_update_s == 1'b1) begin
if (adc_pn_oos_count >= 16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const long long M = 1e9 + 7, P = 1e7 + 19; const int N = 200005; int nt = 1, k, n, Q, x, y, tot, op; long long pm(long long x, long long p) { long long res = 1; while (p) { if (p & 1) res = res * x % M; p >>= 1; x = x * x % M; } return res; } struct node { int l, r, v, w; } q[N << 2]; int qc[N]; vector<int> a; long long f[50][2000]; void cdq(int l, int r, int d, vector<int> a) { if (d > 1) { for (int i = 1; i <= k; i++) f[d][i] = f[d - 1][i]; } for (int i = 0; i < (int)a.size(); ++i) if (q[a[i]].l <= l && r <= q[a[i]].r) { for (int j = k; j >= q[a[i]].w; j--) { f[d][j] = max(f[d][j], f[d][j - q[a[i]].w] + q[a[i]].v); } } if (l == r) { long long res = 0; for (int i = k; i >= 1; i--) { res = (res * P + f[d][i]) % M; } for (int i = 1; i <= qc[l]; i++) { printf( %I64d n , res); } return; } int mid = l + r >> 1; vector<int> la, ra; for (int i = 0; i < (int)a.size(); ++i) { if (q[a[i]].l <= l && r <= q[a[i]].r) continue; if (q[a[i]].r <= mid) { la.push_back(a[i]); } else if (q[a[i]].l > mid) { ra.push_back(a[i]); } else { la.push_back(a[i]); ra.push_back(a[i]); } } cdq(l, mid, d + 1, la); cdq(mid + 1, r, d + 1, ra); } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d%d , &x, &y); q[++tot] = (node){1, 0, x, y}; } scanf( %d , &Q); while (Q--) { scanf( %d , &op); if (op == 1) { ++tot; ++nt; scanf( %d%d , &x, &y); q[tot] = (node){nt, 0, x, y}; } else if (op == 2) { scanf( %d , &x); q[x].r = nt; ++nt; } else { qc[nt]++; } } for (int i = 1; i <= tot; i++) { a.push_back(i); if (q[i].r == 0) q[i].r = nt; } cdq(1, nt, 1, a); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; stack<pair<int, int> > S; S.push(make_pair(0, -1)); vector<pair<int, int> > ans; for (int i = 0; i <= n; i++) { int a; if (i < n) cin >> a; else a = 0; while (S.top().first > a) { pair<int, int> last = S.top(); S.pop(); ans.push_back(make_pair(last.second, i - 1)); last.first--; if (last.first > S.top().first) S.push(last); } if (S.top().first != a) S.push(make_pair(a, i)); } cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) cout << ans[i].first + 1 << << ans[i].second + 1 << endl; }
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#include <bits/stdc++.h> long n, m, x, y, i, a[1000], z; double aa, bb, sum; int main() { scanf( %ld%ld , &n, &m); for (i = 1; i <= n; i++) scanf( %ld , &a[i]); sum = 0; for (i = 1; i <= m; i++) { scanf( %ld%ld%ld , &x, &y, &z); aa = a[x] + a[y]; bb = z; if (aa / bb > sum) { sum = aa / bb; } } printf( %0.15lf , sum); }
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#include <bits/stdc++.h> using namespace std; int main() { long long int x, y; double f, s; cin >> x >> y; f = y * (log10(x)); s = x * (log10(y)); if (abs(f - s) < pow(10, -8)) cout << = ; else if (f < s) cout << < ; else if (f > s) cout << > ; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, i, x1, y1, x2, y2, j, k, sum = 0; int a[101][101]; memset(a, 0, sizeof(a)); scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d%d%d%d , &x1, &y1, &x2, &y2); for (k = x1; k <= x2; k++) for (j = y1; j <= y2; j++) a[k][j]++; } for (i = 1; i <= 100; i++) for (j = 1; j <= 100; j++) sum += a[i][j]; printf( %d n , sum); return 0; }
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:1000000000,1000000000 ) using namespace std; const long long inf = 1e18 + 7; const long long mod = 1e9 + 7; const double eps = 1e-9; const double PI = 2 * acos(0.0); const double E = 2.71828; int f[1 << 24], sum[1 << 24], n, k, a[24], b[2]; int main(void) { scanf( %d , &n); for (long long(i) = 0; (i) < (long long)(n); (i)++) scanf( %d , &a[i]); scanf( %d , &k); b[0] = b[1] = -1; for (long long(i) = 0; (i) < (long long)(k); (i)++) scanf( %d , &b[i]); f[0] = 1; for (long long(i) = 0; (i) < (long long)(1 << n); (i)++) { if (i) sum[i] = sum[i & (i - 1)] + a[__builtin_ctz(i)]; if (sum[i] == b[0] || sum[i] == b[1]) continue; for (long long j = i; j; j &= j - 1) { f[i] += f[i ^ (j & -j)]; if (f[i] >= mod) f[i] -= mod; } } printf( %d n , f[(1 << n) - 1]); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, tx, ty, ans, fa[2055]; bool vis[2055]; int find(const int i) { return fa[i] == i ? i : fa[i] = find(fa[i]); } void merge(const int i, const int j) { fa[i] = j; } int main() { scanf( %d , &n); for (int i = 1; i <= 2010; ++i) { fa[i] = i; } for (int i = 1; i <= n; ++i) { scanf( %d %d , &tx, &ty); ty += 1005; if (!vis[tx]) { ++ans; vis[tx] = true; } if (!vis[ty]) { ++ans; vis[ty] = true; } tx = find(tx); ty = find(ty); if (tx != ty) { --ans; merge(tx, ty); } } --ans; printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int freq[200005]; int arr[1005]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) cin >> arr[i]; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) freq[arr[i] + arr[j]]++; int ans = 0; for (int i = 0; i < 2e5 + 5; i++) ans = max(ans, freq[i]); cout << ans; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_PP_BLACKBOX_V
/**
* lpflow_inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_PP_BLACKBOX_V
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///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by UASC hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Dispatcher State Machine
// File : der_smdisp.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Included by dex_sm.v
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module der_smdisp
(
input de_clk,
input de_rstn,
input en_3d,
input cmdrdy,
input sup_done,
input abort_cmd,
input dex_busy,
input [3:0] opc_1,
input [3:0] opc_15,
input [3:0] opc_2,
input pc_last, // Last push from the pixel cache.
input cmd_done_3d,
output reg go_sup,
output reg load_15, // Transfer parameters from L1 to L1.5
output reg load_actvn, // Transfer parameters from L1.5 to L2 or L1 to L2.
output reg load_actv_3d, // Transfer parameters from L1.5 to L2, in 3D engine.
output reg goline,
output reg goblt,
output reg pal_load,
output reg tc_inv_cmd,
output reg cmdack,
output reg cmdcpyclr
);
//////////////////////////////////////////////////////////////////
// DISPATCHER STATE MACHINE
// DEFINE PARAMETERS
//
reg abort_cmd_flag;
reg abort_cmd_ack;
reg sup_done_flag;
reg sup_done_ack;
reg goline_ii;
reg goblt_ii;
reg goline_i;
reg goblt_i;
reg dex_3d_busy;
`ifdef RTL_ENUM
enum {
IDLE =3'b000,
DECODE =3'b001,
DECODE2 =3'b010,
WAIT_SUP =3'b011,
DECODE3 =3'b100,
WAIT_3D =3'b101,
BUSY =3'b110,
NOOP_ST =3'b111
} d_cs;
`else
parameter
IDLE =3'b000,
DECODE =3'b001,
DECODE2 =3'b010,
WAIT_SUP =3'b011,
DECODE3 =3'b100,
WAIT_3D =3'b101,
BUSY =3'b110,
NOOP_ST =3'b111;
reg [2:0] d_cs;
`endif
parameter
NOOP = 4'h0,
BLT = 4'h1,
LINE = 4'h2,
ELINE = 4'h3,
P_LINE = 4'h5,
RXFER = 4'h6,
WXFER = 4'h7,
LINE_3D = 4'h8,
TRIAN_3D = 4'h9,
LD_TEX = 4'hA,
LD_TPAL = 4'hB,
busy_0 = 3'b001,
busy_15 = 3'b010,
busy_2 = 3'b100;
// Delay goblt and goline for data delay.
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
goblt_ii <= 1'b0;
goline_ii <= 1'b0;
goblt <= 1'b0;
goline <= 1'b0;
end
else begin
goblt <= goblt_ii;
goblt_ii <= goblt_i;
goline <= goline_ii;
goline_ii <= goline_i;
end
end
// Capture abort and sup_done.
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
abort_cmd_flag <= 1'b0;
sup_done_flag <= 1'b0;
dex_3d_busy <= 1'b0;
end
else begin
if(abort_cmd) abort_cmd_flag <= 1'b1;
else if(abort_cmd_ack) abort_cmd_flag <= 1'b0;
if(sup_done) sup_done_flag <= 1'b1;
else if(sup_done_ack) sup_done_flag <= 1'b0;
if(load_actv_3d) dex_3d_busy <= 1'b1;
else if(pc_last) dex_3d_busy <= 1'b0;
end
end
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
go_sup <= 1'b0;
load_15 <= 1'b0;
cmdack <= 1'b0;
load_actvn <= 1'b1;
load_actv_3d <= 1'b0;
cmdcpyclr <= 1'b0;
goline_i <= 1'b0;
goblt_i <= 1'b0;
pal_load <= 1'b0;
tc_inv_cmd <= 1'b0;
abort_cmd_ack <= 1'b0;
sup_done_ack <= 1'b0;
d_cs <= IDLE;
end
else begin
go_sup <= 1'b0;
load_15 <= 1'b0;
cmdack <= 1'b0;
load_actvn <= 1'b1;
load_actv_3d <= 1'b0;
cmdcpyclr <= 1'b0;
goline_i <= 1'b0;
goblt_i <= 1'b0;
pal_load <= 1'b0;
tc_inv_cmd <= 1'b0;
abort_cmd_ack <= 1'b0;
sup_done_ack <= 1'b0;
case(d_cs)
// No commands in pipe.
// Wait for command ready.
IDLE: if(!cmdrdy)d_cs <= IDLE;
// NOOP, or obsolete RXFER, WXFER.
else if((opc_1==NOOP) || (opc_1==RXFER) || (opc_1==WXFER)) begin
cmdack <= 1'b1; // Free Level 1.
d_cs <= NOOP_ST; // Kill one cycle.
end
// 2D Command.
// 3D Command, load L15, and start setup engine.
else if(((opc_1==TRIAN_3D) || (opc_1==LINE_3D)) & en_3d) begin
go_sup <= 1'b1; // Start setup.
load_15 <= 1'b1; // Load Level 15.
cmdack <= 1'b1; // Free Level 1.
d_cs <= WAIT_SUP; // Go wait for setup.
end
// 2D Command.
else begin
if(opc_1 == BLT) begin goblt_i <= 1'b1; cmdack <= 1'b1; end
if(opc_1 == LINE) begin goline_i <= 1'b1; cmdack <= 1'b1; end
if(opc_1 == ELINE) begin goline_i <= 1'b1; cmdack <= 1'b1; end
if(opc_1 == P_LINE) begin goline_i <= 1'b1; cmdack <= 1'b1; end
if((opc_1 == LD_TEX) & en_3d) cmdack <= 1'b1;
if((opc_1 == LD_TPAL) & en_3d) cmdack <= 1'b1;
if(en_3d) begin // if 3D Core, L15 is included.
load_15 <= 1'b1;
d_cs <= DECODE;
end else begin // else just L2 is included.
load_actvn <= 1'b1;
d_cs <= DECODE2;
end
end
DECODE: begin // Not a 3D command transfer 1.5 to 2.0
d_cs <= DECODE2;
load_actvn <= 1'b0;
end
DECODE2: d_cs <= BUSY;
WAIT_SUP: begin // Wait for setup, no 3D in progress.
if(abort_cmd_flag) begin
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
abort_cmd_ack <= 1'b1;
end
// SUP done no 3D in progress.
else if(sup_done_flag && !dex_3d_busy) begin
d_cs <= DECODE3;
load_actvn <= 1'b0;
load_actv_3d <= 1'b1;
sup_done_ack <= 1'b1;
end
else d_cs <= WAIT_SUP;
end
DECODE3: d_cs <= WAIT_3D;
WAIT_3D: begin // 3D in progress, another setup can be started.
if(!dex_3d_busy) begin
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
end
else if(!cmdrdy || dex_3d_busy)d_cs <= WAIT_3D;
// if another 3D command start setup.
else if((opc_1==TRIAN_3D) || (opc_1==LINE_3D)) begin
go_sup <= 1'b1; // Start setup.
load_15 <= 1'b1; // Load Level 15.
cmdack <= 1'b1; // Free Level 1.
d_cs <= WAIT_SUP; // Go wait for setup.
end
else d_cs <= WAIT_3D;
end
BUSY: begin
if(opc_2 == LD_TEX && !dex_3d_busy) begin // texture load command done
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
tc_inv_cmd <= 1'b1;
end
else if(opc_2==LD_TPAL && !dex_3d_busy) begin // palette load command done.
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
pal_load <= 1'b1;
end
else if(opc_2==LD_TEX && dex_3d_busy)d_cs <= BUSY;
else if(opc_2==LD_TPAL && dex_3d_busy)d_cs <= BUSY;
else if((opc_2== NOOP) || !dex_busy) begin
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
end
else d_cs <= BUSY;
end
NOOP_ST: d_cs <= IDLE;
endcase
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_clk (/*AUTOARG*/
// Outputs
passed,
// Inputs
fastclk, clk, reset_l
);
input fastclk;
input clk;
input reset_l;
output passed; reg passed; initial passed = 0;
// surefire lint_off STMINI
// surefire lint_off CWECSB
// surefire lint_off NBAJAM
reg _ranit; initial _ranit=0;
// surefire lint_off UDDSMX
reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT
wire [7:0] clk_clocks_d1r;
wire [7:0] clk_clocks_d1sr;
wire [7:0] clk_clocks_cp2_d1r;
wire [7:0] clk_clocks_cp2_d1sr;
// verilator lint_off MULTIDRIVEN
reg [7:0] int_clocks; initial int_clocks = 0;
// verilator lint_on MULTIDRIVEN
reg [7:0] int_clocks_copy;
// verilator lint_off GENCLK
reg internal_clk; initial internal_clk = 0;
reg reset_int_;
// verilator lint_on GENCLK
always @ (posedge clk) begin
//$write("CLK1 %x\n", reset_l);
if (!reset_l) begin
clk_clocks <= 0;
int_clocks <= 0;
internal_clk <= 1'b1;
reset_int_ <= 0;
end
else begin
internal_clk <= ~internal_clk;
if (!_ranit) begin
_ranit <= 1;
$write("[%0t] t_clk: Running\n",$time);
reset_int_ <= 1;
end
end
end
reg [7:0] sig_rst;
always @ (posedge clk or negedge reset_l) begin
//$write("CLK2 %x sr=%x\n", reset_l, sig_rst);
if (!reset_l) begin
sig_rst <= 0;
end
else begin
sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB
end
end
always @ (posedge clk) begin
//$write("CLK3 %x cc=%x sr=%x\n", reset_l, clk_clocks, sig_rst);
if (!reset_l) begin
clk_clocks <= 0;
end
else begin
clk_clocks <= clk_clocks + 8'd1;
if (clk_clocks == 4) begin
if (sig_rst !== 4) $stop;
if (clk_clocks_d1r !== 3) $stop;
if (int_clocks !== 2) $stop;
if (int_clocks_copy !== 2) $stop;
if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
passed <= 1'b1;
$write("[%0t] t_clk: Passed\n",$time);
end
end
end
reg [7:0] resetted;
always @ (posedge clk or negedge reset_int_) begin
//$write("CLK4 %x\n", reset_l);
if (!reset_int_) begin
resetted <= 0;
end
else begin
resetted <= resetted + 8'd1;
end
end
always @ (int_clocks) begin
int_clocks_copy = int_clocks;
end
always @ (negedge internal_clk) begin
int_clocks <= int_clocks + 8'd1;
end
t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_d1r), .q2(clk_clocks_d1sr));
t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr));
t_clk_two two (/*AUTOINST*/
// Inputs
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
initial begin
fork :fork_label
#100 disable fork_label;
#200 begin
$display("FAILED -- shouldn't get here");
$finish;
end
join
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; long long dp[1000000 + 9] = {0}; long long a1[1000000 + 9] = {0}; long long a2[1000000 + 9] = {0}; long long a3[1000000 + 9] = {0}; long long a4[1000000 + 9] = {0}; long long a5[1000000 + 9] = {0}; long long a6[1000000 + 9] = {0}; long long a7[1000000 + 9] = {0}; long long a8[1000000 + 9] = {0}; long long a9[1000000 + 9] = {0}; int main() { long long a, b, c = 0, d, e, i, j, k, l = 0; for (i = 1; i <= 1000000; i++) { a = i; xx: c = 1; while (a) { b = a % 10; a /= 10; if (b > 0) c *= b; } if (c > 9 && dp[c] == 0) { a = c; goto xx; } else { if (dp[c] == 0) dp[i] = c; else dp[i] = dp[c]; } } for (i = 1; i <= 1000000; i++) { a1[i] += a1[i - 1]; a2[i] += a2[i - 1]; a3[i] += a3[i - 1]; a4[i] += a4[i - 1]; a5[i] += a5[i - 1]; a6[i] += a6[i - 1]; a7[i] += a7[i - 1]; a8[i] += a8[i - 1]; a9[i] += a9[i - 1]; if (dp[i] == 1) a1[i]++; if (dp[i] == 2) a2[i]++; if (dp[i] == 3) a3[i]++; if (dp[i] == 4) a4[i]++; if (dp[i] == 5) a5[i]++; if (dp[i] == 6) a6[i]++; if (dp[i] == 7) a7[i]++; if (dp[i] == 8) a8[i]++; if (dp[i] == 9) a9[i]++; } cin >> a; while (a--) { cin >> c >> d >> e; l = 0; if (e == 1) { l = a1[d] - a1[c - 1]; } if (e == 2) { l = a2[d] - a2[c - 1]; } if (e == 3) { l = a3[d] - a3[c - 1]; } if (e == 4) { l = a4[d] - a4[c - 1]; } if (e == 5) { l = a5[d] - a5[c - 1]; } if (e == 6) { l = a6[d] - a6[c - 1]; } if (e == 7) { l = a7[d] - a7[c - 1]; } if (e == 8) { l = a8[d] - a8[c - 1]; } if (e == 9) { l = a9[d] - a9[c - 1]; } cout << l << endl; } }
|
/*
* NAME
* ----
*
* SPI_slave.v - SPI slave
*
* DESCRIPTION
* -----------
*
* This module controls the SPI to bus communication.
*
* Refer to the documentation (doc/) for a more detailed
* description of the timing singals used here.
* Look for the section titled "Timing diagram of SPI"
*
* The following SPI settings used by this module:
*
* MSB first
* CPOL = 0
* CPHA = 0
* SS_L (enable on low)
*
* The following describes the required signals in general.
* Notice that the NSS transitions after the SCK has stopped.
* This is also configuration specific with CPOL=0 and CPHA=0.
*
* --+ +--
* NSS |___________ ... ____________|
* +--+ +--+ +--+ +--+
* SCK ____| |__| | ... | |__| |_____
*
*
* AUTHOR
* ------
*
* Jeremiah Mahler <>
*
*/
module spi_ctl(
input nss,
mosi,
sck,
output miso,
output reg [6:0] address_bus,
inout [7:0] data_bus,
output reg read_n,
output reg write_n);
// sample count
reg [8:0] count;
reg mosi_sample;
// drive the data bus for a write, high Z otherwise
reg [7:0] write_data_bus;
assign data_bus = (~(write_n | ~read_n)) ? write_data_bus : 8'bz;
// read register and next read register
reg [7:0] r_reg;
wire [7:0] r_next;
// r_next is the next PROPAGATE value
assign r_next = {r_reg[6:0], mosi_sample};
assign miso = r_reg[7];
// This tedious code is much easier to understand
// along with timing digrams given in the documentation (doc/).
// Look for the section titled "Timing diagram of SPI"
// There are two diagrams, one for the read cycle and one
// for the write cycle. This code implements both of these.
// This acts as a "one shot" used to indicate the start of a transaction
reg start;
always @(negedge nss, posedge sck) begin
if (sck)
start <= 1'b0;
else
start <= 1'b1;
end
// SAMPLE
always @(posedge sck, posedge nss) begin
// defaults
count <= 1;
if (nss) begin
// end of second byte
read_n <= 1'b1; // disable
end else begin
// SAMPLE
mosi_sample <= mosi;
if (start) begin
count <= 1;
read_n <= 1'b1; // disable
end else begin
count <= count + 1;
end
if (7 == count) begin
// end of first byte
// we got the 7-bit address and rw bit
address_bus <= {r_reg[5:0], mosi};
// if (READ)
if (r_reg[6] == 1'b1)
read_n <= 1'b0; // enable
end else if (15 == count && read_n == 1'b1) begin
// (WRITE), got the second byte, setup to write it to the bus
write_data_bus <= {r_reg[6:0], mosi};
// can't use r_next here because we need mosi
end
end
end
// PROPAGATE
always @(negedge sck, posedge nss) begin
// defaults
r_reg <= 8'h00;
if (nss) begin
// end of second byte
write_n <= 1'b1; // disable
end else begin
r_reg <= r_next;
if (1 == count) begin
write_n <= 1'b1; // disable
end else if (8 == count) begin
// if (READ), load the data to be sent back
if (1'b0 == read_n)
r_reg <= data_bus;
end else if (16 == count) begin
// end of second byte
// if (WRITE), enable write.
// (the enabled device will drive the bus)
if (read_n == 1'b1)
write_n <= 1'b0; // enable
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T bigmod(T p, T e, T M) { long long ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return (T)ret; } template <class T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> inline T lcm(T a, T b) { return (a / gcd(a, b)) * b; } template <class T> inline T modinverse(T a, T M) { return bigmod(a, M - 2, M); } template <class T> inline T bpow(T p, T e) { long long ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p); p = (p * p); } return (T)ret; } template <class T> inline T gethash(T h[], T power[], int l, int r) { if (r < l) return (T)0; return h[l] - h[r + 1] * power[r - l + 1]; } struct data { data() {} bool friend operator<(data a, data b) { return 0; } }; int n, m, k; long long N, M, K; int a[200005]; long long ans[200005]; vector<int> adj[200005]; int subtree[200005]; bool bad[200005]; int tot = 0; int cnt[200005]; unordered_set<int> st; unordered_set<int>::iterator it; unordered_map<int, int> mm[200005]; int _gcd(int a, int b) { if (a == 0) return b; if (b == 0) return a; int p = _gcd(b, a % b); return p; } void dfs(int u, int p) { subtree[u] = 1; tot++; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v == p || bad[v]) continue; dfs(v, u); subtree[u] += subtree[v]; } } int getcenter(int u, int p) { for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v == p || bad[v]) continue; if (subtree[v] > tot / 2) return getcenter(v, u); } return u; } void query(int u, int p, int g) { g = _gcd(g, a[u]); for (it = st.begin(); it != st.end(); it++) { int x = *it; int gc = _gcd(g, x); ans[gc] += cnt[x]; } for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v == p || bad[v]) continue; query(v, u, g); } } void update(int u, int p, int g) { g = _gcd(a[u], g); st.insert(g); cnt[g]++; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v == p || bad[v]) continue; update(v, u, g); } } void decompose(int u, int p) { tot = 0; dfs(u, p); int c = getcenter(u, p); ans[a[c]]++; cnt[a[c]] = 1; st.insert(a[c]); bad[c] = 1; for (int i = 0; i < adj[c].size(); i++) { int v = adj[c][i]; if (v == p || bad[v]) continue; query(v, c, 0); update(v, c, a[c]); } for (it = st.begin(); it != st.end(); it++) { int x = *it; cnt[x] = 0; } st.clear(); for (int i = 0; i < adj[c].size(); i++) { int v = adj[c][i]; if (v == p || bad[v]) continue; decompose(v, c); } } int main() { int t, tc = 1; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = 1; i < n; i++) { int u, v; scanf( %d %d , &u, &v); adj[u].push_back(v); adj[v].push_back(u); } decompose(1, -1); for (int i = 1; i <= 200000; i++) { if (ans[i]) { printf( %d %lld n , i, ans[i]); } } return 0; }
|
module vesa_tpg(
clock,
reset,
dout_ready,
dout_valid,
dout_data,
dout_sop,
dout_eop,
bpp // 3'b000 = 18bpp, 3'b001 = 24bpp
);
parameter MAX_BPC = 8;
input clock;
input reset;
input dout_ready;
output dout_valid;
output [MAX_BPC*3-1:0] dout_data;
output dout_sop;
output dout_eop;
wire [1:0] dout_empty;
input [2:0] bpp;
assign dout_empty = 0;
parameter WIDTH=1920;
parameter HEIGHT=1080;
localparam CTRL_PKT_NUM=3;
localparam CTRL_PKT_HEADER=24'd15;
localparam DATA_PKT_HEADER=24'd0;
///////////////////////
reg [11:0] dot_cnt;
reg [11:0] line_cnt;
///////////////////////
// Catch ready signal
reg dout_ready_reg;
always @(posedge clock or posedge reset) begin
if (reset)
dout_ready_reg <= 0;
else
dout_ready_reg <= dout_ready;
end
///////////////////////
// valid is always 1 but masked by dout_ready_reg
assign dout_valid = dout_ready_reg;
///////////////////////
// State Machine
//reg out;
reg [1:0] pkt_state;
localparam STATE_CTRL_PKT_SOP = 0;
localparam STATE_CTRL_PKT_DAT = 1;
localparam STATE_DATA_PKT_SOP = 2;
localparam STATE_DATA_PKT_DAT = 3;
wire ctrl_pkt_sop = (pkt_state == STATE_CTRL_PKT_SOP ) ? 1 : 0 ;
wire ctrl_pkt_eop = ((pkt_state == STATE_CTRL_PKT_DAT) & (dot_cnt==(CTRL_PKT_NUM-1)) ) ? 1 : 0 ;
wire data_pkt_sop = (pkt_state == STATE_DATA_PKT_SOP ) ? 1 : 0 ;
wire data_pkt_eop = ((pkt_state == STATE_DATA_PKT_DAT) & (dot_cnt==(WIDTH-1)) & (line_cnt==(HEIGHT-1)) ) ? 1 : 0 ;
always @ (posedge clock or posedge reset) begin
if (reset) pkt_state <= STATE_CTRL_PKT_SOP;
else
case (pkt_state) // state transitions
STATE_CTRL_PKT_SOP: if (dout_ready_reg) pkt_state <= STATE_CTRL_PKT_DAT;
STATE_CTRL_PKT_DAT: if (dout_ready_reg & ctrl_pkt_eop) pkt_state <= STATE_DATA_PKT_SOP;
STATE_DATA_PKT_SOP: if (dout_ready_reg) pkt_state <= STATE_DATA_PKT_DAT;
STATE_DATA_PKT_DAT: if (dout_ready_reg & data_pkt_eop) pkt_state <= STATE_CTRL_PKT_SOP;
default : pkt_state <= STATE_CTRL_PKT_DAT;
endcase
end
///////////////////////
/////////////////////////
// sop and eop signals
assign dout_sop = (ctrl_pkt_sop | data_pkt_sop) & dout_ready_reg;
assign dout_eop = (ctrl_pkt_eop | data_pkt_eop) & dout_ready_reg;
always @(posedge clock or posedge reset) begin
if (reset) begin
dot_cnt <= 0;
end
else begin
if (dout_ready_reg)
if ((pkt_state == STATE_DATA_PKT_DAT) ) begin
if ( dot_cnt < (WIDTH-1) )
dot_cnt <= dot_cnt + 1;
else
dot_cnt <= 0;
end
else if ((pkt_state == STATE_CTRL_PKT_DAT) )begin // control packet
if ( dot_cnt < (CTRL_PKT_NUM-1) )
dot_cnt <= dot_cnt + 1;
else
dot_cnt <= 0;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
line_cnt <= 0;
end
else begin
if (dout_ready_reg ) begin
if (pkt_state == STATE_DATA_PKT_DAT) begin
if ( dot_cnt == (WIDTH-1) ) begin
if ( line_cnt < (HEIGHT-1) )
line_cnt <= line_cnt+1;
else
line_cnt <= 0;
end
end
else
line_cnt <= 0;
end
end
end
reg [MAX_BPC*3-1:0] ctrl_data;
wire [MAX_BPC-1:0] r_data;
wire [MAX_BPC-1:0] g_data;
wire [MAX_BPC-1:0] b_data;
wire [MAX_BPC*3-1:0] image_data={r_data, g_data, b_data};
///////////////////////
// Making Image Data
// Generate VESA ramp 6bpc
wire r_line_active_18bpp = line_cnt[7:6] == 2'b00;
wire g_line_active_18bpp = line_cnt[7:6] == 2'b01;
wire b_line_active_18bpp = line_cnt[7:6] == 2'b10;
wire w_line_active_18bpp = line_cnt[7:6] == 2'b11;
wire [MAX_BPC-1:0] r_data_18bpp = {{6{r_line_active_18bpp}} & dot_cnt[5:0] | {6{w_line_active_18bpp}} & dot_cnt[5:0], {MAX_BPC-6{1'b0}}};
wire [MAX_BPC-1:0] g_data_18bpp = {{6{g_line_active_18bpp}} & dot_cnt[5:0] | {6{w_line_active_18bpp}} & dot_cnt[5:0], {MAX_BPC-6{1'b0}}};
wire [MAX_BPC-1:0] b_data_18bpp = {{6{b_line_active_18bpp}} & dot_cnt[5:0] | {6{w_line_active_18bpp}} & dot_cnt[5:0], {MAX_BPC-6{1'b0}}};
// Generate VESA ramp 8bpc
wire r_line_active_24bpp = line_cnt[7:6] == 2'b00;
wire g_line_active_24bpp = line_cnt[7:6] == 2'b01;
wire b_line_active_24bpp = line_cnt[7:6] == 2'b10;
wire w_line_active_24bpp = line_cnt[7:6] == 2'b11;
wire [MAX_BPC-1:0] r_data_24bpp = {{8{r_line_active_24bpp}} & dot_cnt[7:0] | {8{w_line_active_24bpp}} & dot_cnt[7:0], {MAX_BPC-8{1'b0}}};
wire [MAX_BPC-1:0] g_data_24bpp = {{8{g_line_active_24bpp}} & dot_cnt[7:0] | {8{w_line_active_24bpp}} & dot_cnt[7:0], {MAX_BPC-8{1'b0}}};
wire [MAX_BPC-1:0] b_data_24bpp = {{8{b_line_active_24bpp}} & dot_cnt[7:0] | {8{w_line_active_24bpp}} & dot_cnt[7:0], {MAX_BPC-8{1'b0}}};
// Combiner
assign r_data = 16'd0 | {16{bpp == 3'b001}} & r_data_24bpp | {16{bpp == 3'b000}} & r_data_18bpp;
assign g_data = 16'd0 | {16{bpp == 3'b001}} & g_data_24bpp | {16{bpp == 3'b000}} & g_data_18bpp;
assign b_data = 16'd0 | {16{bpp == 3'b001}} & b_data_24bpp | {16{bpp == 3'b000}} & b_data_18bpp;
///////////////////////
// Making Final Output Data
reg [MAX_BPC*3-1:0] dout_data;
always @(pkt_state or ctrl_data or image_data ) begin
case (pkt_state)
STATE_CTRL_PKT_SOP: dout_data = CTRL_PKT_HEADER;
STATE_CTRL_PKT_DAT: dout_data = ctrl_data;
STATE_DATA_PKT_SOP: dout_data = DATA_PKT_HEADER;
default: dout_data = image_data;
endcase
end
wire [15:0] w_width = WIDTH;
wire [15:0] w_height = HEIGHT;
always @(dot_cnt[3:0]) begin
case (dot_cnt[3:0])
4'd0 : ctrl_data = {{MAX_BPC-4{1'b0}}, w_width[ 7: 4], {MAX_BPC-4{1'b0}}, w_width[11: 8], {MAX_BPC-4{1'b0}}, w_width[15:12]};
4'd1 : ctrl_data = {{MAX_BPC-4{1'b0}}, w_height[11: 8], {MAX_BPC-4{1'b0}}, w_height[15:12], {MAX_BPC-4{1'b0}}, w_width[ 3: 0]};
4'd2 : ctrl_data = {{MAX_BPC-4{1'b0}}, 4'b0011, {MAX_BPC-4{1'b0}}, w_height[ 3: 0], {MAX_BPC-4{1'b0}}, w_height[ 7: 4]};
default : ctrl_data = {MAX_BPC*3{1'bx}};
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRBP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFRBP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 1, logN = 21 + 1, mod = 1e9 + 7; int fl(int n) { int ans = 0; while (n /= 2) ++ans; return ans; } int ord2(int n) { int ans = 0; while (n % 2 == 0) { n >>= 1; ++ans; } return ans; } long long binpow(long long a, long long s) { long long ans = 1; while (s) { if (s & 1) ans = ans * a % mod; a = a * a % mod; s >>= 1; } return ans; } long long inv(long long a) { return binpow(a, mod - 2); } long long f[N], finv[N]; void init() { f[0] = 1; finv[0] = 1; for (long long i = 1; i < N; ++i) { f[i] = f[i - 1] * i % mod; finv[i] = inv(f[i]); } } int n, logn; int cnt[logN]; long long solve(int k) { for (int i = 0; i < logn; ++i) cnt[i] = 0; for (int i = 1; i <= n; ++i) { int ord = ord2(i); if (ord < k) ++cnt[ord]; else if (ord >= k) { if (i % 3) ++cnt[k]; else ++cnt[ord + 1]; } } long long ans = 1; for (int i = 0; i < logn; ++i) ans = ans * cnt[i] % mod; ans = ans * f[cnt[0] - 1] % mod; int sum = cnt[0] - 1; for (int i = 1; i < logn; ++i) { ans = ans * (f[sum + cnt[i]] * finv[sum + 1] % mod) % mod; sum += cnt[i]; } return ans; } int main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); init(); cin >> n; logn = fl(n) + 1; long long ans = 0; for (int i = 0; i < logn; ++i) ans = (ans + solve(i)) % mod; cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, root; vector<int> adj[N]; bool ok; int dfs(int v, int p = -1) { int ret = 0; int cnt = 2; if (v == root) cnt++; for (int u : adj[v]) { if (u == p) continue; int res = dfs(u, v); if (res) ret = 2; if (res == 2) cnt--; } if (cnt <= 0) { ok = false; } if (adj[v].size() == 3) ret = max(1, ret); if (adj[v].size() > 3) ret = 2; return ret; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int a, b; scanf( %d%d , &a, &b); a--; b--; adj[a].push_back(b); adj[b].push_back(a); } ok = true; root = 0; for (int i = 0; i < n; i++) if (adj[root].size() < adj[i].size()) root = i; dfs(root); if (!ok && adj[root].size() == 3) { ok = true; for (int u : adj[root]) { if (adj[u].size() == 3) { root = u; break; } } dfs(root); } if (ok) puts( Yes ); else puts( No ); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool dp[1005][1005]; vector<int> v; int b[1005], A[1005]; int Find(int A[], int x) { int root = x, tmp; while (A[root] >= 0) root = A[root]; while (x != root) { tmp = x; x = A[x]; A[tmp] = root; } return root; } void Union(int A[], int a, int b) { int x = Find(A, a), y = Find(A, b), tmp; if (x != y) { if (A[x] > A[y]) { tmp = x; x = y; y = tmp; } A[x] += A[y]; A[y] = x; } } int main() { int n, x, i, j, c = 1, r; memset(A, -1, sizeof A); cin >> n >> x; for (i = 1; i <= n; i++) cin >> b[i]; i = x; while (b[i]) { c++; i = b[i]; } for (i = 1; i <= n; i++) if (b[i]) Union(A, i, b[i]); r = Find(A, x); for (i = 1; i <= n; i++) if (A[i] < 0 && i != r) v.push_back(-A[i]); dp[0][0] = true; for (i = 1; i <= v.size(); i++) for (j = 0; j <= n; j++) if (v[i - 1] > j) dp[i][j] = dp[i - 1][j]; else dp[i][j] = dp[i - 1][j] | dp[i - 1][j - v[i - 1]]; for (i = 0; i <= n; i++) if (dp[v.size()][i]) cout << i + c << endl; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Oct 17 02:50:46 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top RAT_slice_12_3_0 -prefix
// RAT_slice_12_3_0_ RAT_slice_7_3_1_stub.v
// Design : RAT_slice_7_3_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "xlslice,Vivado 2016.4" *)
module RAT_slice_12_3_0(Din, Dout)
/* synthesis syn_black_box black_box_pad_pin="Din[17:0],Dout[4:0]" */;
input [17:0]Din;
output [4:0]Dout;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A211OI_PP_BLACKBOX_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using vi = vector<int>; int n, m, p, nm; vector<char> g; vector<bool> vis; vector<int> s, cnt; vector<queue<int>> ex; queue<int> q; bool isEmpty(int v) { if (v < 0) return false; int i = v / m, j = v % m; if (i < 0 || i >= n) return false; if (j < 0 || j >= m) return false; return (g[v] == . ); } int dist(int u, int v) { int x1 = u / m, y1 = u % m; int x2 = v / m, y2 = v % m; return abs(x1 - x2) + abs(y1 - y2); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m >> p; nm = n * m; g.resize(nm); s.resize(p); cnt.resize(p); ex.resize(p); for (int& e : s) cin >> e; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int v = i * m + j; char c; cin >> c; g[v] = c; if (c != . && c != # ) { int pl = c - 1 ; cnt[pl]++; ex[pl].push(v); } } } bool found = true; while (found) { found = false; for (int cur = 0; cur < p; cur++) { int dis = 0; while (dis != s[cur] && !ex[cur].empty()) { queue<int> tmp; while (!ex[cur].empty()) { int u = ex[cur].front(); ex[cur].pop(); for (int mul : {-m, -1, m, 1}) { int to = u + mul; if (to / m != u / m && to % m != u % m) continue; if (!isEmpty(to)) continue; g[to] = cur + 1 ; cnt[cur]++; found = true; tmp.push(to); } } ex[cur] = tmp; dis++; } } } for (int i : cnt) cout << i << ; cout << endl; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dbginit_inst.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////;
// dbginit_inst.v
//
// Description: dbginit_inst Monitor
////////////////////////////////////////////////////////
module dbginit_inst (
rst,
clk,
dbginit,
actual,
expected,
cnt_val,
mon_num
);
parameter CMP_SZ = 1;
input rst;
input clk;
input dbginit; // dbginit signal
input [CMP_SZ-1:0] actual; // actual value of signal monitored
input [CMP_SZ-1:0] expected; // expected value on dbginit
input [10:0] cnt_val; // monitor num for failure tracking
input [31:0] mon_num; // monitor num for failure tracking
reg same;
reg sig_same;
reg diff;
reg [31:0] cntr;
reg check_done;
reg start_mon;
initial
begin
same = 0;
diff = 0;
cntr = 0;
check_done = 0;
sig_same = 0;
start_mon = 0;
end
always @(dbginit)
begin
if ( !$test$plusargs("dbginit_mon_off")) begin
if (rst & !dbginit) begin
same <= 0;
diff <= 0;
start_mon <= 1;
if (actual == expected)
same <= 1;
else
diff <= 1;
end else begin
same <= 0;
diff <= 0;
start_mon <= 0;
end
end
end
always @(posedge clk)
begin
if ( !$test$plusargs("dbginit_mon_off")) begin
if (rst & start_mon) begin
cntr <= (!dbginit) ? cntr +1 : 0;
if ((cntr == cnt_val) & !check_done) begin
check_done <= 1;
if ((actual != expected) && (!sig_same)) begin
$display("ERROR : Signal value not as expected after dbginit ; expected= %h ,actual=%h \n", expected,actual);
finish_test("RTL doesnt reset signals on DBGINIT", mon_num);
end else begin
if (same == 1'b1)
$display("****NOTE : Value did not change before and after debuginit for Monitor#%d ******\n",mon_num);
end
end
// for cases where signal toggles and starts changing again
if (same || diff ) begin
if (actual == expected)
sig_same <= 1;
end
end else begin
cntr <= 0;
check_done <= 0;
sig_same <= 0;
end
end
end
//=====================================================================
// This task allows some more clocks and kills the test
//=====================================================================
task finish_test;
input [512:0] message;
input [31:0] id;
begin
$display("%0d ERROR: DBGINIT Monitor : %s MONITOR NUMBER : %d", $time, message,mon_num);
@(posedge clk);
$error ("dbginit_inst", "DBGINIT monitor exited") ;
end
endtask
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTN_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLRTN_BEHAVIORAL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTN_BEHAVIORAL_V
|
module Bit_OP_16bit(F, A, BS, S);
input[15:0] A;
input[3:0] BS;
input S;
output reg[15:0] F;
always @(A) begin
case (BS[3:0])
4'b0000: begin F = {A[15:1],S}; //Bit 0
end
4'b0001: begin F = {A[15:2],S,A[0]}; //Bit 1
end
4'b0010: begin F = {A[15:3],S,A[1:0]}; //Bit 2
end
4'b0011: begin F = {A[15:4],S,A[2:0]}; //Bit 3
end
4'b0100: begin F = {A[15:5],S,A[3:0]}; //Bit 4
end
4'b0101: begin F = {A[15:6],S,A[4:0]}; //Bit 5
end
4'b0110: begin F = {A[15:7],S,A[5:0]}; //Bit 6
end
4'b0111: begin F = {A[15:8],S,A[6:0]}; //Bit 7
end
4'b1000: begin F = {A[15:9],S,A[7:0]}; //Bit 8
end
4'b1001: begin F = {A[15:10],S,A[8:0]}; //Bit 9
end
4'b1010: begin F = {A[15:11],S,A[9:0]}; //Bit 10
end
4'b1011: begin F = {A[15:12],S,A[10:0]}; //Bit 11
end
4'b1100: begin F = {A[15:13],S,A[11:0]}; //Bit 12
end
4'b1101: begin F = {A[15:14],S,A[12:0]}; //Bit 13
end
4'b1110: begin F = {A[15],S,A[13:0]}; //Bit 14
end
4'b1111: begin F = {S,A[14:0]}; //Bit 15
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O22AI_BEHAVIORAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_BEHAVIORAL_PP_V
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 14015 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w16384,
w16383,
w32,
w33,
w4,
w37,
w2368,
w14015;
assign w1 = i_data0;
assign w14015 = w16383 - w2368;
assign w16383 = w16384 - w1;
assign w16384 = w1 << 14;
assign w2368 = w37 << 6;
assign w32 = w1 << 5;
assign w33 = w1 + w32;
assign w37 = w33 + w4;
assign w4 = w1 << 2;
assign o_data0 = w14015;
//multiplier_block area estimate = 6350.09758873383;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; double p; bool in_memo[200 + 1][230 + 1][2][1 << 8]; double memo[200 + 1][230 + 1][2][1 << 8]; double E(int k, int lead_count, bool lead_parity, int mask) { double& ans = memo[k][lead_count][lead_parity][mask]; if (not in_memo[k][lead_count][lead_parity][mask]) { if (k == 0) { ans = mask ? __builtin_ctz(mask) : 8 + (lead_parity ? 0 : lead_count); } else { ans = p / 100 * E(k - 1, bool((mask & (1 << 7)) >> 7) == lead_parity ? lead_count + 1 : 1, (mask & (1 << 7)) >> 7, (mask * 2) & 0b11111111) + (100 - p) / 100 * E(k - 1, mask == 0b11111111 ? (lead_parity ? lead_count : 1) : lead_count, lead_parity ^ (mask == 0b11111111), (mask + 1) & 0b11111111); } in_memo[k][lead_count][lead_parity][mask] = true; } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int x, k; cin >> x >> k >> p; memset(in_memo, false, sizeof in_memo); cout << fixed << setprecision(7) << E(k, __builtin_ctz((x >> 8) & 1 ? (x >> 8) + 1 : x >> 8), (x >> 8) & 1, x & 0b11111111) << n ; return 0; }
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lights_nios2_qsys_0_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
lights_nios2_qsys_0_jtag_debug_module_tck the_lights_nios2_qsys_0_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
lights_nios2_qsys_0_jtag_debug_module_sysclk the_lights_nios2_qsys_0_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic lights_nios2_qsys_0_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam lights_nios2_qsys_0_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// lights_nios2_qsys_0_jtag_debug_module_phy.sld_instance_index = 0,
// lights_nios2_qsys_0_jtag_debug_module_phy.sld_ir_width = 2,
// lights_nios2_qsys_0_jtag_debug_module_phy.sld_mfg_id = 70,
// lights_nios2_qsys_0_jtag_debug_module_phy.sld_sim_action = "",
// lights_nios2_qsys_0_jtag_debug_module_phy.sld_sim_n_scan = 0,
// lights_nios2_qsys_0_jtag_debug_module_phy.sld_sim_total_length = 0,
// lights_nios2_qsys_0_jtag_debug_module_phy.sld_type_id = 34,
// lights_nios2_qsys_0_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<int, int> T[4 * 200005]; void update(int n, int b, int e, int p, int v) { if (b == p && e == p) { T[n] = make_pair(v, p); } else { int m = (b + e) / 2; if (p <= m) update(2 * n, b, m, p, v); else update(2 * n + 1, m + 1, e, p, v); T[n] = max(T[2 * n], T[2 * n + 1]); } } pair<int, int> query(int n, int b, int e, int l, int r) { if (b == l && e == r) { return T[n]; } else { int m = (b + e) / 2; if (m >= r) return query(2 * n, b, m, l, r); if (l > m) return (query(2 * n + 1, m + 1, e, l, r)); return max(query(2 * n, b, m, l, m), query(2 * n + 1, m + 1, e, m + 1, r)); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<pair<pair<int, int>, int> > arr(n); vector<pair<int, int> > ori(n); int a, b; for (int i = 0; i < n; i++) { cin >> a >> b; arr[i] = make_pair(make_pair(a, b), i); ori[i] = make_pair(a, b); } sort(arr.begin(), arr.end()); priority_queue<pair<int, int> > q; vector<int> result1(n); vector<int> result2(n); int index = 0; map<int, int> comp; for (int i = 1; i <= n; i++) { while (index < n && arr[index].first.first == i) { q.push(make_pair(-1 * arr[index].first.second, arr[index].second)); index++; } pair<int, int> current = q.top(); q.pop(); result1[current.second] = i; comp[i] = current.second; } for (int i = 0; i < n; i++) { result2[i] = result1[i]; } bool one = true; for (int i = 1; i <= n; i++) { int l = ori[comp[i]].first; int r = ori[comp[i]].second; pair<int, int> res = query(1, 0, 200005, l, r); if (res.first >= i) { one = false; result2[comp[i]] = result1[comp[res.second]]; result2[comp[res.second]] = result1[comp[i]]; break; } update(1, 0, 200005, i, r); } if (one) { cout << YES << n ; for (int i = 0; i < n; i++) { cout << result1[i] << ; } cout << n ; } else { cout << NO << n ; for (int i = 0; i < n; i++) { cout << result1[i] << ; } cout << n ; for (int i = 0; i < n; i++) { cout << result2[i] << ; } cout << n ; } return 0; }
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: vconv
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: Cyclone IV and Cyclone 10 LP devices
// Tool versions: Altera Quartus Prime
// Description:
//
// Dependencies: vh/n64a_params.vh
//
// Features: conversion RGB to YPbPr on demand
// outputs 8bit vectors for ADV7125 / ADV7123
//
//////////////////////////////////////////////////////////////////////////////////
module vconv(
VCLK,
nRST,
nEN_YPbPr, // enables color transformation on '0'
vdata_valid_i,
vdata_i,
vdata_valid_o,
vdata_o
);
`include "vh/n64adv_vparams.vh"
localparam coeff_width = 20;
input VCLK;
input nRST;
input nEN_YPbPr;
input vdata_valid_i;
input [`VDATA_O_FU_SLICE] vdata_i;
output reg vdata_valid_o = 1'b0;
output [`VDATA_O_FU_SLICE] vdata_o;
// pre-assignments
wire [3:0] S_i = vdata_i[`VDATA_O_SY_SLICE];
wire unsigned [color_width_o-1:0] R_i = vdata_i[`VDATA_O_RE_SLICE];
wire unsigned [color_width_o-1:0] G_i = vdata_i[`VDATA_O_GR_SLICE];
wire unsigned [color_width_o-1:0] B_i = vdata_i[`VDATA_O_BL_SLICE];
reg [3:0] S_o = 4'h0;
reg unsigned [color_width_o-1:0] V1_o = {color_width_o{1'b0}};
reg unsigned [color_width_o-1:0] V2_o = {color_width_o{1'b0}};
reg unsigned [color_width_o-1:0] V3_o = {color_width_o{1'b0}};
// start of rtl
// delay Sync along with the pipeline stages of the video conversion
reg vdata_valid[0:2];
reg [3:0] S[0:2];
reg [color_width_o-1:0] R[0:2], G[0:2], B[0:2];
integer idx;
initial begin
for (idx = 0; idx < 3; idx = idx+1) begin
vdata_valid[idx] = 1'b0;
S[idx] = 4'h0;
R[idx] = {color_width_o{1'b0}};
G[idx] = {color_width_o{1'b0}};
B[idx] = {color_width_o{1'b0}};
end
end
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
for (idx = 0; idx < 3; idx = idx+1) begin
vdata_valid[idx] = 1'b0;
S[idx] <= 4'h0;
R[idx] <= {color_width_o{1'b0}};
G[idx] <= {color_width_o{1'b0}};
B[idx] <= {color_width_o{1'b0}};
end
end else begin
for (idx = 1; idx < 3; idx = idx+1) begin
vdata_valid[idx] <= vdata_valid[idx-1];
S[idx] <= S[idx-1];
R[idx] <= R[idx-1];
G[idx] <= G[idx-1];
B[idx] <= B[idx-1];
end
vdata_valid[0] <= vdata_valid_i;
S[0] <= S_i;
R[0] <= R_i;
G[0] <= G_i;
B[0] <= B_i;
end
// Transformation to YPbPr
// =======================
// Transformation Rec. 601:
// Y = 0.299 R + 0.587 G + 0.114 B
// Pb = -0.168736 R - 0.331264 G + 0.5 B + 2^9
// Pr = 0.5 R - 0.418688 G - 0.08132 B + 2^9
localparam msb_vo = color_width_o+coeff_width-1; // position of MSB after altmult_add (Pb and Pr neg. parts are shifted to that)
localparam lsb_vo = coeff_width; // position of LSB after altmult_add (Pb and Pr neg. parts are shifted to that)
localparam fyr = 20'd313524;
localparam fyg = 20'd615514;
localparam fyb = 20'd119538;
reg [color_width_o+coeff_width+1:0] Y_addmult = {(color_width_o+coeff_width+2){1'b0}};
reg [color_width_o+coeff_width-1:0] R4Y_scaled = {(color_width_o+coeff_width){1'b0}};
reg [color_width_o+coeff_width-1:0] G4Y_scaled = {(color_width_o+coeff_width){1'b0}};
reg [color_width_o+coeff_width-1:0] B4Y_scaled = {(color_width_o+coeff_width){1'b0}};
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
Y_addmult <= {(color_width_o+coeff_width+2){1'b0}};
R4Y_scaled <= {(color_width_o+coeff_width){1'b0}};
G4Y_scaled <= {(color_width_o+coeff_width){1'b0}};
B4Y_scaled <= {(color_width_o+coeff_width){1'b0}};
end else begin
Y_addmult <= R4Y_scaled + G4Y_scaled + B4Y_scaled;
R4Y_scaled <= fyr * (* multstyle = "dsp" *) R[0];
G4Y_scaled <= fyg * (* multstyle = "dsp" *) G[0];
B4Y_scaled <= fyb * (* multstyle = "dsp" *) B[0];
end
localparam fpbr = 20'd353865;
localparam fpbg = 20'd694711;
reg [color_width_o+coeff_width :0] Pb_nPart_addmult = {(color_width_o+coeff_width+1){1'b0}};
reg [color_width_o+coeff_width-1:0] R4Pb_scaled = {(color_width_o+coeff_width){1'b0}};
reg [color_width_o+coeff_width-1:0] G4Pb_scaled = {(color_width_o+coeff_width){1'b0}};
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
Pb_nPart_addmult <= {(color_width_o+coeff_width+1){1'b0}};
R4Pb_scaled <= {(color_width_o+coeff_width){1'b0}};
G4Pb_scaled <= {(color_width_o+coeff_width){1'b0}};
end else begin
Pb_nPart_addmult <= R4Pb_scaled + G4Pb_scaled;
R4Pb_scaled <= fpbr * (* multstyle = "dsp" *) R[0];
G4Pb_scaled <= fpbg * (* multstyle = "dsp" *) G[0];
end
wire [color_width_o+1:0] Pb_addmult = {1'b0,B[2],1'b0}- Pb_nPart_addmult[msb_vo+1:lsb_vo-1];
localparam fprg = 20'd878052;
localparam fprb = 20'd170524;
reg [color_width_o+coeff_width :0] Pr_nPart_addmult = {(color_width_o+coeff_width+1){1'b0}};
reg [color_width_o+coeff_width-1:0] G4Pr_scaled = {(color_width_o+coeff_width){1'b0}};
reg [color_width_o+coeff_width-1:0] B4Pr_scaled = {(color_width_o+coeff_width){1'b0}};
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
Pr_nPart_addmult <= {(color_width_o+coeff_width+1){1'b0}};
G4Pr_scaled <= {(color_width_o+coeff_width){1'b0}};
B4Pr_scaled <= {(color_width_o+coeff_width){1'b0}};
end else begin
Pr_nPart_addmult <= G4Pr_scaled + B4Pr_scaled;
G4Pr_scaled <= fprg * (* multstyle = "dsp" *) G[0];
B4Pr_scaled <= fprb * (* multstyle = "dsp" *) B[0];
end
wire [color_width_o+1:0] Pr_addmult = {1'b0,R[2],1'b0}- Pr_nPart_addmult[msb_vo+1:lsb_vo-1];
// get final results:
wire [color_width_o-1:0] Y_tmp = Y_addmult[msb_vo:lsb_vo] + Y_addmult[lsb_vo-1];
wire [color_width_o :0] Pb_tmp = Pb_addmult[color_width_o+1:1] + Pb_addmult[0];
wire [color_width_o :0] Pr_tmp = Pr_addmult[color_width_o+1:1] + Pr_addmult[0];
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
vdata_valid_o <= 1'b0;
S_o <= 4'h0;
V1_o <= {color_width_o{1'b0}};
V2_o <= {color_width_o{1'b0}};
V3_o <= {color_width_o{1'b0}};
end else begin
vdata_valid_o <= vdata_valid[2];
if (!nEN_YPbPr) begin
S_o <= S[2];
V1_o <= {~Pr_tmp[color_width_o],Pr_tmp[color_width_o-1:1]};
V2_o <= Y_tmp;
V3_o <= {~Pb_tmp[color_width_o],Pb_tmp[color_width_o-1:1]};
end else begin
S_o <= S[2];
V1_o <= R[2];
V2_o <= G[2];
V3_o <= B[2];
end
end
// post-assignment
assign vdata_o = {S_o,V1_o,V2_o,V3_o};
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Wojtek Gumua
//
// Create Date: 15:47:33 06/07/2015
// Design Name:
// Module Name: processor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module processor(
input clk100
//input [7:0] sw,
//output [7:0] led
);
wire [7:0] PC_addr;
wire [7:0] alu_res;
wire jmp_out;
wire [7:0] data_out;
d_mem data_memory (
.address(alu_res),
.data(data_out)
);
wire [31:0] inst_out;
i_mem inst_memory (
.address(PC_addr),
.data(inst_out)
);
// dekodowanie polecenia
reg [1:0] pc_op = 2'b0;
reg [1:0] alu_op = 2'b0;
reg [2:0] rx_op = 3'b0;
reg imm_op = 1'b0;
reg [2:0] ry_op = 2'b0;
reg rd_op = 1'b0;
reg [2:0] d_op = 3'b0;
reg [7:0] imm = 8'b0;
always @(posedge clk100)
begin
pc_op <= inst_out[25:24];
alu_op <= inst_out[21:20];
rx_op <= inst_out[18:16];
imm_op <= inst_out[15];
ry_op <= inst_out[14:12];
rd_op <= inst_out[11];
d_op <= inst_out[10:8];
imm <= inst_out[7:0];
end
wire [7:0] dekoder_out;
demux8x1 dekoder (
.address(d_op),
.in(1'b1),
.out(dekoder_out)
);
wire [7:0] rd_mux_out;
mux2x8 rd_mux (
.address(rd_op),
.in0(alu_res),
.in1(data_out),
.out(rd_mux_out)
);
wire [7:0] pc_mux_out;
wire [7:0] inc_addr;
assign inc_addr = PC_addr + 8'b1;
mux2x8 pc_mux (
.address(jmp_out),
.in0(alu_res),
.in1(inc_addr),
.out(pc_mux_out)
);
//definicje rejestrow
wire [7:0] R0_out;
wire [7:0] R1_out;
wire [7:0] R2_out;
wire [7:0] R3_out;
wire [7:0] R4_out;
wire [7:0] R5_out;
wire [7:0] R6_out;
register R0 (
.clk(clk100),
.ce(dekoder_out[0]),
.d(rd_mux_out),
.q(R0_out)
);
register R1 (
.clk(clk100),
.ce(dekoder_out[1]),
.d(rd_mux_out),
.q(R1_out)
);
register R2 (
.clk(clk100),
.ce(dekoder_out[2]),
.d(rd_mux_out),
.q(R2_out)
);
register R3 (
.clk(clk100),
.ce(dekoder_out[3]),
.d(rd_mux_out),
.q(R3_out)
);
register R4 (
.clk(clk100),
.ce(dekoder_out[4]),
.d(rd_mux_out),
.q(R4_out)
);
register R5 (
.clk(clk100),
.ce(dekoder_out[5]),
.d(rd_mux_out),
.q(R5_out)
);
register R6 (
.clk(clk100),
.ce(dekoder_out[6]),
.d(8'b0),
.q(R6_out)
);
register PC (
.clk(clk100),
.ce(1'b1),
.d(pc_mux_out),
.q(PC_addr)
);
wire [7:0] rx_mux_out;
mux8x8 rx_mux (
.address(rx_op),
.in0(R0_out),
.in1(R1_out),
.in2(R2_out),
.in3(R3_out),
.in4(R4_out),
.in5(R5_out),
.in6(R6_out),
.in7(PC_addr),
.out(rx_mux_out)
);
wire [7:0] ry_mux_out;
mux8x8 ry_mux (
.address(ry_op),
.in0(R0_out),
.in1(R1_out),
.in2(R2_out),
.in3(R3_out),
.in4(R4_out),
.in5(R5_out),
.in6(R6_out),
.in7(PC_addr),
.out(ry_mux_out)
);
wire [7:0] imm_mux_out;
mux2x8 imm_mux (
.address(imm_op),
.in0(ry_mux_out),
.in1(imm),
.out(imm_mux_out)
);
wire [7:0] alu_sum;
wire [7:0] alu_and;
wire [7:0] alu_cmp;
ALU alu (
.input_x(rx_mux_out),
.input_y(imm_mux_out),
.output_sum(alu_sum),
.output_and(alu_and),
.output_cmp(alu_cmp)
);
mux8x8 alu_mux ( //4x8!!
.address({1'b0, alu_op}),
.in0(alu_and),
.in1(alu_sum),
.in2(alu_cmp),
.in3(imm_mux_out),
.in4(8'b0),
.in5(8'b0),
.in6(8'b0),
.in7(8'b0),
.out(alu_res)
);
jump_select jump_switch (
.cmp_res(alu_cmp),
.pc_op(pc_op),
.out(jmp_out)
);
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring unsigned divider ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_uu.v,v 1.3 2003/09/17 13:08:53 rherveille Exp $
//
// $Date: 2003/09/17 13:08:53 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: div_uu.v,v $
// Revision 1.3 2003/09/17 13:08:53 rherveille
// Fixed a bug in the remainder output. Changed a hard value into the required parameter.
// Fixed a bug in the testbench.
//
// Revision 1.2 2002/10/31 13:54:58 rherveille
// Fixed a bug in the remainder output of div_su.v
//
// Revision 1.1.1.1 2002/10/29 20:29:10 rherveille
//
//
//
//synopsys translate_off
`timescale 1ns/10ps
//synopsys translate_on
module zet_div_uu(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width -1:0] z; // divident
input [d_width -1:0] d; // divisor
output [d_width -1:0] q; // quotient
output [d_width -1:0] s; // remainder
output div0;
output ovf;
reg [d_width-1:0] q;
reg [d_width-1:0] s;
reg div0;
reg ovf;
//
// functions
//
function [z_width:0] gen_s;
input [z_width:0] si;
input [z_width:0] di;
begin
if(si[z_width])
gen_s = {si[z_width-1:0], 1'b0} + di;
else
gen_s = {si[z_width-1:0], 1'b0} - di;
end
endfunction
function [d_width-1:0] gen_q;
input [d_width-1:0] qi;
input [z_width:0] si;
begin
gen_q = {qi[d_width-2:0], ~si[z_width]};
end
endfunction
function [d_width-1:0] assign_s;
input [z_width:0] si;
input [z_width:0] di;
reg [z_width:0] tmp;
begin
if(si[z_width])
tmp = si + di;
else
tmp = si;
assign_s = tmp[z_width-1:z_width-d_width];
end
endfunction
//
// variables
//
reg [d_width-1:0] q_pipe [d_width-1:0];
reg [z_width:0] s_pipe [d_width:0];
reg [z_width:0] d_pipe [d_width:0];
reg [d_width:0] div0_pipe, ovf_pipe;
//
// perform parameter checks
//
// synopsys translate_off
initial
begin
if(d_width !== z_width / 2)
$display("div.v parameter error (d_width != z_width/2).");
end
// synopsys translate_on
integer n0, n1, n2, n3;
// generate divisor (d) pipe
always @(d)
d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
always @(posedge clk)
if(ena)
for(n0=1; n0 <= d_width; n0=n0+1)
d_pipe[n0] <= d_pipe[n0-1];
// generate internal remainder pipe
always @(z)
s_pipe[0] <= z;
always @(posedge clk)
if(ena)
for(n1=1; n1 <= d_width; n1=n1+1)
s_pipe[n1] <= gen_s(s_pipe[n1-1], d_pipe[n1-1]);
// generate quotient pipe
always @(posedge clk)
q_pipe[0] <= 0;
always @(posedge clk)
if(ena)
for(n2=1; n2 < d_width; n2=n2+1)
q_pipe[n2] <= gen_q(q_pipe[n2-1], s_pipe[n2]);
// flags (divide_by_zero, overflow)
always @(z or d)
begin
ovf_pipe[0] <= !(z[z_width-1:d_width] < d);
div0_pipe[0] <= ~|d;
end
always @(posedge clk)
if(ena)
for(n3=1; n3 <= d_width; n3=n3+1)
begin
ovf_pipe[n3] <= ovf_pipe[n3-1];
div0_pipe[n3] <= div0_pipe[n3-1];
end
// assign outputs
always @(posedge clk)
if(ena)
ovf <= ovf_pipe[d_width];
always @(posedge clk)
if(ena)
div0 <= div0_pipe[d_width];
always @(posedge clk)
if(ena)
q <= gen_q(q_pipe[d_width-1], s_pipe[d_width]);
always @(posedge clk)
if(ena)
s <= assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22AI_SYMBOL_V
`define SKY130_FD_SC_HS__O22AI_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o22ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int k[5] = {3, 4, 5, 4, 3}; int st[5] = {0, 0, 0, 1, 2}; int dx[] = {0, -1, -1, 0, 1, 1}; int dy[] = {-1, -1, 0, 1, 1, 0}; int x[32], y[32]; int id[32][32]; char a[32][32]; char f[1 << 20]; int prep() { memset(id, 0xff, sizeof(id)); int n = 0; for (int i = 0; i < (5); ++i) for (int j = 0; j < (k[i]); ++j) x[n] = i, y[n] = st[i] + j, id[i][st[i] + j] = n++; int res = 0; for (int i = 0; i < (5); ++i) for (int j = 0; j < (k[i]); ++j) if (a[i][st[i] + j] == O ) res |= 1 << id[i][st[i] + j]; return res; } int main() { for (int i = 0; i < (5); ++i) { gets(a[i]); for (int j = 0; j < (k[i]); ++j) a[i][st[i] + j] = a[i][2 * j + 5 - k[i]]; a[i][st[i] + k[i]] = 0; } int need = prep(); for (int m = 0; m < ((1 << 19)); ++m) { for (int i = 0; i < (19); ++i) if (m & (1 << i)) { for (int q = 0; q < (6); ++q) { int xx = x[i], yy = y[i], d = 1 << i; for (;;) { f[m] |= 1 - f[m ^ d]; if (f[m]) goto end; xx += dx[q], yy += dy[q]; if (xx < 0 || xx >= 5 || yy - st[xx] < 0 || yy - st[xx] >= k[xx] || (~m & (1 << id[xx][yy]))) break; d |= 1 << id[xx][yy]; } } } end:; } if (f[need]) puts( Karlsson ); else puts( Lillebror ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long n, m; vector<long> clauses[100000 + 1]; vector<long> variables[100000 + 1]; long long ans[2] = {0}; bool check_clauses[100000 + 1] = {false}; long long dp_path[100000 + 1][2][2]; long long dp_cycle[100000 + 1][2][2][2]; void path_component(long start_clause) { long cur_clause = 0, nxt_clause = 0, variable = 0; long long temp[2]; if (clauses[start_clause].size() == 1) { variable = abs(clauses[start_clause][0]); if (variables[variable].size() == 1) { if ((ans[0] == 0) && (ans[1] == 0)) { ans[1] = 1; ans[0] = 1; } else { temp[1] = (ans[1] + ans[0]) % 1000000007; temp[0] = (ans[1] + ans[0]) % 1000000007; ans[1] = temp[1]; ans[0] = temp[0]; } return; } nxt_clause = (abs(variables[variable][0]) != start_clause) ? abs(variables[variable][0]) : abs(variables[variable][1]); if ((long long)variables[variable][0] * (long long)variables[variable][1] > 0) { dp_path[nxt_clause][1][1] = 0; dp_path[nxt_clause][1][0] = 1; dp_path[nxt_clause][0][1] = 0; dp_path[nxt_clause][0][0] = 1; } else { dp_path[nxt_clause][1][1] = 1; dp_path[nxt_clause][1][0] = 0; dp_path[nxt_clause][0][1] = 1; dp_path[nxt_clause][0][0] = 0; } cur_clause = nxt_clause; } else { if ((variables[abs(clauses[start_clause][0])].size() == 2) && (variables[abs(clauses[start_clause][1])].size() == 2)) return; variable = (variables[abs(clauses[start_clause][0])].size() == 1) ? abs(clauses[start_clause][0]) : abs(clauses[start_clause][1]); cur_clause = start_clause; dp_path[start_clause][1][1] = 1; dp_path[start_clause][1][0] = 0; dp_path[start_clause][0][1] = 0; dp_path[start_clause][0][0] = 1; } if (check_clauses[start_clause]) return; check_clauses[start_clause] = true; check_clauses[cur_clause] = true; while (true) { if (clauses[cur_clause].size() == 1) { if ((ans[0] == 0) && (ans[1] == 0)) { ans[0] = (dp_path[cur_clause][0][0] + dp_path[cur_clause][1][0]) % 1000000007; ans[1] = (dp_path[cur_clause][0][1] + dp_path[cur_clause][1][1]) % 1000000007; } else { temp[0] = ((ans[1] * ((dp_path[cur_clause][0][1] + dp_path[cur_clause][1][1]) % 1000000007)) % 1000000007 + (ans[0] * ((dp_path[cur_clause][0][0] + dp_path[cur_clause][1][0]) % 1000000007)) % 1000000007) % 1000000007; temp[1] = ((ans[1] * ((dp_path[cur_clause][0][0] + dp_path[cur_clause][1][0]) % 1000000007)) % 1000000007 + (ans[0] * ((dp_path[cur_clause][0][1] + dp_path[cur_clause][1][1]) % 1000000007)) % 1000000007) % 1000000007; ans[0] = temp[0]; ans[1] = temp[1]; } return; } variable = (abs(clauses[cur_clause][0]) != variable) ? abs(clauses[cur_clause][0]) : abs(clauses[cur_clause][1]); if (variables[variable].size() == 1) { long long dp_temp[2][2]; dp_temp[0][1] = dp_path[cur_clause][0][1]; dp_temp[0][0] = dp_path[cur_clause][0][0]; dp_temp[1][1] = (dp_path[cur_clause][0][0] + 2 * dp_path[cur_clause][1][1]) % 1000000007; dp_temp[1][0] = (dp_path[cur_clause][0][1] + 2 * dp_path[cur_clause][1][0]) % 1000000007; if ((ans[0] == 0) && (ans[1] == 0)) { ans[0] = (dp_temp[0][0] + dp_temp[1][0]) % 1000000007; ans[1] = (dp_temp[0][1] + dp_temp[1][1]) % 1000000007; } else { temp[0] = ((ans[1] * ((dp_temp[0][1] + dp_temp[1][1]) % 1000000007)) % 1000000007 + (ans[0] * ((dp_temp[0][0] + dp_temp[1][0]) % 1000000007)) % 1000000007) % 1000000007; temp[1] = ((ans[1] * ((dp_temp[0][0] + dp_temp[1][0]) % 1000000007)) % 1000000007 + (ans[0] * ((dp_temp[0][1] + dp_temp[1][1]) % 1000000007)) % 1000000007) % 1000000007; ans[0] = temp[0]; ans[1] = temp[1]; } return; } nxt_clause = (abs(variables[variable][0]) != cur_clause) ? abs(variables[variable][0]) : abs(variables[variable][1]); check_clauses[nxt_clause] = true; if ((long long)variables[variable][0] * (long long)variables[variable][1] > 0) { dp_path[nxt_clause][0][1] = (dp_path[cur_clause][1][1] + dp_path[cur_clause][0][1]) % 1000000007; dp_path[nxt_clause][0][0] = (dp_path[cur_clause][1][0] + dp_path[cur_clause][0][0]) % 1000000007; dp_path[nxt_clause][1][1] = (dp_path[cur_clause][1][0] + dp_path[cur_clause][0][1]) % 1000000007; dp_path[nxt_clause][1][0] = (dp_path[cur_clause][1][1] + dp_path[cur_clause][0][0]) % 1000000007; } else { dp_path[nxt_clause][1][1] = (dp_path[cur_clause][1][0] + dp_path[cur_clause][0][0]) % 1000000007; dp_path[nxt_clause][1][0] = (dp_path[cur_clause][1][1] + dp_path[cur_clause][0][1]) % 1000000007; dp_path[nxt_clause][0][1] = (dp_path[cur_clause][1][1] + dp_path[cur_clause][0][0]) % 1000000007; dp_path[nxt_clause][0][0] = (dp_path[cur_clause][1][0] + dp_path[cur_clause][0][1]) % 1000000007; } cur_clause = nxt_clause; } } void cycle_component(long start_clause) { long cur_clause = 0, nxt_clause = 0, variable = 0; long long temp[2]; if (clauses[start_clause].size() == 1) return; if ((variables[abs(clauses[start_clause][0])].size() == 1) || (variables[abs(clauses[start_clause][1])].size() == 1)) return; if (check_clauses[start_clause]) return; check_clauses[start_clause] = true; variable = abs(clauses[start_clause][0]); nxt_clause = (abs(variables[variable][0]) != start_clause) ? abs(variables[variable][0]) : abs(variables[variable][1]); if (nxt_clause == start_clause) { if ((long long)variables[variable][0] * (long long)variables[variable][1] > 0) { if ((ans[0] == 0) && (ans[1] == 0)) { ans[1] = 1; ans[0] = 1; } else { temp[1] = (ans[1] + ans[0]) % 1000000007; temp[0] = (ans[1] + ans[0]) % 1000000007; ans[1] = temp[1]; ans[0] = temp[0]; } } else { if ((ans[0] == 0) && (ans[1] == 0)) { ans[1] = 2; ans[0] = 0; } else { temp[1] = 2 * ans[0]; temp[0] = 2 * ans[1]; ans[1] = temp[1]; ans[0] = temp[0]; } } return; } if ((long long)variables[variable][0] * (long long)variables[variable][1] > 0) { dp_cycle[nxt_clause][1][1][1] = 0; dp_cycle[nxt_clause][1][1][0] = 1; dp_cycle[nxt_clause][1][0][1] = 0; dp_cycle[nxt_clause][1][0][0] = 0; dp_cycle[nxt_clause][0][1][1] = 0; dp_cycle[nxt_clause][0][1][0] = 0; dp_cycle[nxt_clause][0][0][1] = 0; dp_cycle[nxt_clause][0][0][0] = 1; } else { dp_cycle[nxt_clause][1][1][1] = 0; dp_cycle[nxt_clause][1][1][0] = 0; dp_cycle[nxt_clause][1][0][1] = 1; dp_cycle[nxt_clause][1][0][0] = 0; dp_cycle[nxt_clause][0][1][1] = 1; dp_cycle[nxt_clause][0][1][0] = 0; dp_cycle[nxt_clause][0][0][1] = 0; dp_cycle[nxt_clause][0][0][0] = 0; } cur_clause = nxt_clause; while (true) { check_clauses[cur_clause] = true; variable = (abs(clauses[cur_clause][0]) != variable) ? abs(clauses[cur_clause][0]) : abs(clauses[cur_clause][1]); nxt_clause = (abs(variables[variable][0]) != cur_clause) ? abs(variables[variable][0]) : abs(variables[variable][1]); if (nxt_clause == start_clause) { long long dp_temp[2][2]; if ((long long)variables[variable][0] * (long long)variables[variable][1] > 0) { dp_temp[0][1] = (dp_cycle[cur_clause][1][1][1] + dp_cycle[cur_clause][1][0][1] + dp_cycle[cur_clause][0][1][1] + dp_cycle[cur_clause][0][0][1]) % 1000000007; dp_temp[0][0] = (dp_cycle[cur_clause][1][1][0] + dp_cycle[cur_clause][1][0][0] + dp_cycle[cur_clause][0][1][0] + dp_cycle[cur_clause][0][0][0]) % 1000000007; dp_temp[1][1] = (dp_cycle[cur_clause][1][1][1] + dp_cycle[cur_clause][1][0][0] + dp_cycle[cur_clause][0][1][0] + dp_cycle[cur_clause][0][0][1]) % 1000000007; dp_temp[1][0] = (dp_cycle[cur_clause][1][1][0] + dp_cycle[cur_clause][1][0][1] + dp_cycle[cur_clause][0][1][1] + dp_cycle[cur_clause][0][0][0]) % 1000000007; } else { dp_temp[1][1] = (dp_cycle[cur_clause][1][1][1] + dp_cycle[cur_clause][1][0][0] + dp_cycle[cur_clause][0][1][1] + dp_cycle[cur_clause][0][0][0]) % 1000000007; dp_temp[1][0] = (dp_cycle[cur_clause][1][1][0] + dp_cycle[cur_clause][1][0][1] + dp_cycle[cur_clause][0][1][0] + dp_cycle[cur_clause][0][0][1]) % 1000000007; dp_temp[0][1] = (dp_cycle[cur_clause][1][1][1] + dp_cycle[cur_clause][1][0][1] + dp_cycle[cur_clause][0][1][0] + dp_cycle[cur_clause][0][0][0]) % 1000000007; dp_temp[0][0] = (dp_cycle[cur_clause][1][1][0] + dp_cycle[cur_clause][1][0][0] + dp_cycle[cur_clause][0][1][1] + dp_cycle[cur_clause][0][0][1]) % 1000000007; } if ((ans[0] == 0) && (ans[1] == 0)) { ans[0] = (dp_temp[0][0] + dp_temp[1][0]) % 1000000007; ans[1] = (dp_temp[0][1] + dp_temp[1][1]) % 1000000007; } else { temp[0] = ((ans[1] * ((dp_temp[0][1] + dp_temp[1][1]) % 1000000007)) % 1000000007 + (ans[0] * ((dp_temp[0][0] + dp_temp[1][0]) % 1000000007)) % 1000000007) % 1000000007; temp[1] = ((ans[1] * ((dp_temp[0][0] + dp_temp[1][0]) % 1000000007)) % 1000000007 + (ans[0] * ((dp_temp[0][1] + dp_temp[1][1]) % 1000000007)) % 1000000007) % 1000000007; ans[0] = temp[0]; ans[1] = temp[1]; } return; } if ((long long)variables[variable][0] * (long long)variables[variable][1] > 0) { for (long i = 0; i <= 1; i++) { dp_cycle[nxt_clause][i][0][1] = (dp_cycle[cur_clause][i][0][1] + dp_cycle[cur_clause][i][1][1]) % 1000000007; dp_cycle[nxt_clause][i][0][0] = (dp_cycle[cur_clause][i][0][0] + dp_cycle[cur_clause][i][1][0]) % 1000000007; dp_cycle[nxt_clause][i][1][1] = (dp_cycle[cur_clause][i][0][1] + dp_cycle[cur_clause][i][1][0]) % 1000000007; dp_cycle[nxt_clause][i][1][0] = (dp_cycle[cur_clause][i][0][0] + dp_cycle[cur_clause][i][1][1]) % 1000000007; } } else { for (long i = 0; i <= 1; i++) { dp_cycle[nxt_clause][i][1][1] = (dp_cycle[cur_clause][i][0][0] + dp_cycle[cur_clause][i][1][0]) % 1000000007; dp_cycle[nxt_clause][i][1][0] = (dp_cycle[cur_clause][i][0][1] + dp_cycle[cur_clause][i][1][1]) % 1000000007; dp_cycle[nxt_clause][i][0][1] = (dp_cycle[cur_clause][i][0][0] + dp_cycle[cur_clause][i][1][1]) % 1000000007; dp_cycle[nxt_clause][i][0][0] = (dp_cycle[cur_clause][i][0][1] + dp_cycle[cur_clause][i][1][0]) % 1000000007; } } cur_clause = nxt_clause; } } int main() { cin >> n >> m; for (long i = 1; i <= n; i++) { long k; cin >> k; clauses[i].resize(k); for (long j = 0; j < k; j++) { cin >> clauses[i][j]; if (clauses[i][j] < 0) variables[-clauses[i][j]].push_back(-i); else variables[clauses[i][j]].push_back(i); } } for (long i = 1; i <= n; i++) { path_component(i); } for (long i = 1; i <= n; i++) { cycle_component(i); } for (long i = 1; i <= m; i++) { if (variables[i].size() == 0) { ans[0] = (ans[0] * 2) % 1000000007; ans[1] = (ans[1] * 2) % 1000000007; } } ans[0] = ans[0] % 1000000007; ans[1] = ans[1] % 1000000007; cout << ans[1] << endl; return 0; }
|
module uart_tx #(parameter CLOCK_FREQ = 12_000_000, BAUD_RATE = 115_200)
(
input clock,
input [7:0] read_data,
input read_clock_enable,
input reset, /* active low */
output reg ready, /* ready to read new data */
output reg tx,
output reg uart_clock);
reg [9:0] data;
localparam CLOCKS_PER_BIT = CLOCK_FREQ / BAUD_RATE / 2;
reg [24:0] divider;
reg new_data;
reg state;
reg [3:0] bit_pos; /* which is the next bit we transmit */
localparam IDLE = 1'h0, DATA = 1'h1;
always @(negedge reset or posedge clock) begin
if (~reset) begin
uart_clock <= 0;
divider <= 0;
end
else if (divider >= CLOCKS_PER_BIT) begin
divider <= 0;
uart_clock <= ~uart_clock;
end
else
divider <= divider + 1;
end
always @(negedge clock or negedge reset) begin
if (~reset) begin
ready <= 0;
new_data <= 0;
end
else begin
if (state == IDLE) begin
if (~new_data)
if (~ready)
ready <= 1;
else if (read_clock_enable) begin
/* stop bit */
data[0] <= 0;
data[8:1] <= read_data;
/* start bit */
data[9] <= 1;
new_data <= 1;
ready <= 0;
end
end
else
new_data <= 0;
end
end
always @(negedge uart_clock or negedge reset) begin
if (~reset) begin
state <= IDLE;
end
else begin
case (state)
IDLE: begin
tx <= 1;
if (new_data) begin
state <= DATA;
bit_pos <= 0;
end
end
DATA: begin
tx <= data[bit_pos];
if (bit_pos == 9)
state <= IDLE;
else
bit_pos <= bit_pos + 1;
end
endcase
end
end
endmodule
|
module dummy;
parameter [TSTBITS-1:0] // synopsys enum tstate_info
TIDLE = 3'b000,
TCN1 = 3'b001,
TCN2 = TCN1+1, // must be numbered consecutively
TCN3 = TCN2+1,
TCN4 = TCN3+1,
TCN5 = TCN4+1,
IOCLR = TCN5+1,
TUNU1 = 3'b111;
// state and output logic
always @ (`ifdef SIMFSM
ireset or
`endif
/*AUTOSENSE*/fooc2_qual or foocr_we or ioclrinst or tstate) begin
ioclrtmout = 1'b0;
case (tstate)
TIDLE: begin
if (foocr_we)
ntstate = TCN1;
else
ntstate = TIDLE;
end
TCN1,TCN2,TCN3,TCN4,TCN5: begin
if (ioclrinst | fooc2_qual)
ntstate = TIDLE;
else
ntstate = tstate + 1;
end
IOCLR: begin
ntstate = TIDLE;
ioclrtmout = 1'b1;
end
TUNU1: begin
ntstate = TIDLE;
`ifdef SIMFSM
if (~ireset)
$display("ERROR: entered unused state at %t",$time);
`endif
end
default: begin
ntstate = 'bx;
ioclrtmout = 1'bx;
`ifdef SIMFSM
if (~ireset)
$display("ERROR: entered unknown state at %t",$time);
`endif
end
endcase // case(tstate)
end // always @ (...
endmodule // dummy
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
module write_cycle_tb;
reg RESET;
reg CLK14M;
wire CLK;
reg AS20;
reg DS20;
reg RW20;
reg [31:0] A;
reg [31:0] D_OUT;
reg [1:0] SIZ;
wire [1:0] DSACK;
wire RAMOE;
wire [1:0] RAS;
wire [3:0] CAS;
wire [31:0] D = RW20 ? {32{1'bz}} : D_OUT;
`include "common.vinc"
// Instantiate the Unit Under Test (UUT)
ramcpld uut (
.CLKCPU(CLK),
.RESET(RESET),
.AS20(AS20),
.DS20(DS20),
.RW20(RW20),
.DSACK(DSACK),
.PUNT (PUNT),
.SIZ(SIZ),
.A(A[23:0]),
.D (D[31:24]),
.IDEINT ( 1'b0 ),
.RAMOE (RAMOE),
.CAS (CAS),
.RAS (RAS),
.RAM_MUX(RAM_MUX)
);
integer i;
initial begin
$dumpfile("write_cycle.vcd");
$dumpvars(0, write_cycle_tb);
RESET = 1;
#10;
// Initialize Inputs
CLK14M = 0;
RESET = 0;
// Wait 100 ns for global reset to finish
#142;
RESET = 1;
#142;
SIZ = 2'b10;
// autoconfig the devices.
write(32'h00E8004a, 32'h9_0000000);
write(32'h00E80048, 32'hE_0000000);
write(32'h00E8004a, 32'h0_0000000);
write(32'h00E80048, 32'h2_0000000);
busidle();
for( i = 32'h200000; i < 32'h00210000; i++ ) begin
write(i, 0);
busidle();
read(i);
busidle();
end
#;
$finish;
end
assign CLK = CLK14M;
always begin
#71; CLK14M = ~CLK14M;
end
PULLUP PUNT_pullup (
.O(PUNT) // Pullup output (connect directly to top-level port)
);
PULLUP DSACK0_pullup (
.O(DSACK[0])
);
PULLUP DSACK1_pullup (
.O(DSACK[1])
);
endmodule
|
#include <bits/stdc++.h> const int maxn = int(1e5) + 7, mod = int(1e9) + 7; bool not_prime[maxn]; std::map<int, int> cnt[maxn]; std::vector<int> factor[maxn]; long long qpow(long long p, long long q) { long long ret = 1; while (q) { if (q & 1) ret = ret * p % mod; p = p * p % mod; q >>= 1; } return ret; } void init() { for (int i = 2; i < maxn; i++) { for (int j = 2; i * j < maxn; j++) factor[i * j].push_back(i); if (!not_prime[i]) { for (int j = 1; i * j < maxn; j++) { int num = i * j; not_prime[num] = true; cnt[num][i] = j; } } } } int f[maxn], m; int calc(int x, int y) { int ret = m / y, a = x / y, b = m / y; std::vector<int> buf; for (auto &it : cnt[a]) { buf.push_back(it.first); } int len = int(buf.size()); for (int i = 1; i < 1 << len; i++) { int tmp = 1; for (int j = 0; j < len; j++) { if ((i >> j) & 1) { tmp = -tmp * buf[j]; } } ret += b / tmp; } return ret; } int main() { init(); std::cin >> m; int inv_m = int(qpow(m, mod - 2)), ans = 1; for (int i = 2; i <= m; i++) { f[i] = 1; for (auto &k : factor[i]) { f[i] = int((f[i] + 1ll * calc(i, k) * f[k] % mod * inv_m % mod) % mod); } f[i] = int(1ll * f[i] * qpow((1 - 1ll * (m / i) * inv_m % mod + mod) % mod, mod - 2) % mod); ans = int((ans + 1ll * f[i] * inv_m % mod) % mod); } std::cout << ans << std::endl; return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1024000000,1024000000 ) using namespace std; int main() { cin.tie(0); ios::sync_with_stdio(false); int n, w; cin >> w >> n; if (w <= 3) { cout << YES << endl; return 0; } while (n > 0) { if (n % w > 1 && n % w < w - 1) { cout << NO << endl; return 0; } n = (n + 1) / w; } cout << YES << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_1_V
`define SKY130_FD_SC_LP__A311OI_1_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311oi_1 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_1_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// Parameterized FIFO with input and output registers and ACL pipeline
// protocol ports.
//
//===----------------------------------------------------------------------===//
module acl_fifo (
clock,
resetn,
data_in,
data_out,
valid_in,
valid_out,
stall_in,
stall_out,
usedw,
empty,
full,
almost_full);
function integer my_local_log;
input [31:0] value;
for (my_local_log=0; value>0; my_local_log=my_local_log+1)
value = value>>1;
endfunction
parameter DATA_WIDTH = 32;
parameter DEPTH = 256;
parameter NUM_BITS_USED_WORDS = DEPTH == 1 ? 1 : my_local_log(DEPTH-1);
parameter ALMOST_FULL_VALUE = 0;
input clock, stall_in, valid_in, resetn;
output stall_out, valid_out;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output [NUM_BITS_USED_WORDS-1:0] usedw;
output empty, full, almost_full;
// add a register stage prior to the acl_fifo.
//reg [DATA_WIDTH-1:0] data_input /* synthesis preserve */;
//reg valid_input /* synthesis preserve */;
//always@(posedge clock or negedge resetn)
//begin
// if (~resetn)
// begin
// data_input <= {DATA_WIDTH{1'bx}};
// valid_input <= 1'b0;
// end
// else if (~valid_input | ~full)
// begin
// valid_input <= valid_in;
// data_input <= data_in;
// end
//end
scfifo scfifo_component (
.clock (clock),
.data (data_in),
.rdreq ((~stall_in) & (~empty)),
.sclr (),
.wrreq (valid_in & (~full)),
.empty (empty),
.full (full),
.q (data_out),
.aclr (~resetn),
.almost_empty (),
.almost_full (almost_full),
.usedw (usedw));
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = DEPTH,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = DATA_WIDTH,
scfifo_component.lpm_widthu = NUM_BITS_USED_WORDS,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON",
scfifo_component.almost_full_value = ALMOST_FULL_VALUE;
assign stall_out = full;
assign valid_out = ~empty;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> ans; void solve(long long n) { long long step = 0; while (n != 1) { if (n % 2 == 0) { if (n % 6 != 0) { ans.push_back(-1); return; } n /= 6; if (n == 0) { ans.push_back(-1); return; } } else { n *= 2; if (n % 6 != 0) { ans.push_back(-1); return; } } ++step; } ans.push_back(step); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { long long n; cin >> n; solve(n); } for (int i = (0); i < (ans.size()); ++i) cout << ans[i] << endl; return 0; }
|
/*****************************************************************************/
//
// Module : cae_clock.vpp
// Revision : $Revision: 1.4 $
// Last Modified On: $Date: 2011/09/29 17:44:03 $
// Last Modified By: $Author: mruff $
//
//-----------------------------------------------------------------------------
//
// Original Author : mruff
// Created On : Tue Sep 27 14:12:23 CDT 2011
//
//-----------------------------------------------------------------------------
//
// Description : Sample Custom Personality clock logic
//
//-----------------------------------------------------------------------------
//
// Copyright (c) 2007-2011 : created by Convey Computer Corp. This model is the
// confidential and proprietary property of Convey Computer Corp.
//
/*****************************************************************************/
/* $Id: cae_clock.vpp,v 1.4 2011/09/29 17:44:03 mruff Exp $ */
module cae_clock (
input clk,
input i_reset,
input ppll_reset,
output clk_per,
output ppll_locked,
output reset_per
);
`include "pdk_fpga_param.vh"
generate if (RATIO == 0) begin : gsync
assign clk_per = clk;
assign ppll_locked = 1'b1;
assign reset_per = i_reset;
end else begin : gasync
wire pll_clkout;
BUFG clk_per_bufg (.O(clk_per), .I(pll_clkout));
if (CNY_PDK_PLATFORM == "hc-1") begin : ghc1
PLL_BASE #(
.CLKIN_PERIOD (6.667), // 150 MHz
.DIVCLK_DIVIDE (1), // 150 MHz (Fpfd)
.CLKFBOUT_MULT (5), // 750 MHz (Fvco)
.CLKOUT0_DIVIDE(6) // 125 MHz
) pll (
.CLKIN(clk),
.RST(ppll_reset),
.CLKFBOUT(pll_clkfbout),
.CLKFBIN(pll_clkfbout),
.LOCKED(ppll_locked),
.CLKOUT0(pll_clkout),
.CLKOUT1(), .CLKOUT2(), .CLKOUT3(), .CLKOUT4(), .CLKOUT5()
);
end else begin : ghc1ex
MMCM_BASE #(
.CLKIN1_PERIOD (6.667), // 150 MHz
.DIVCLK_DIVIDE (1), // 150 MHz (Fpfd)
.CLKFBOUT_MULT_F (5), // 750 MHz (Fvco)
.CLKOUT0_DIVIDE_F(6) // 125 MHz
) pll (
.CLKIN1(clk),
.RST(ppll_reset),
.CLKFBOUT(pll_clkfbout),
.CLKFBIN(pll_clkfbout),
.LOCKED(ppll_locked),
.CLKOUT0(pll_clkout),
.PWRDWN(1'b0),
.CLKFBOUTB(),
.CLKOUT0B(), .CLKOUT1(), .CLKOUT1B(),
.CLKOUT2(), .CLKOUT2B(), .CLKOUT3(), .CLKOUT3B(),
.CLKOUT4(), .CLKOUT5(), .CLKOUT6()
);
end
(* KEEP = "true" *)(* TIG = "true" *) wire r_AsYnC_reset;
FDSE rst0 (.C(clk), .S(i_reset),
.CE(r_AsYnC_reset), .D(!r_AsYnC_reset), .Q(r_AsYnC_reset));
FD rst1 (.C(clk_per), .D(r_AsYnC_reset), .Q(r_reset_sync));
BUFG brst (.O(reset_per), .I(r_reset_sync));
end endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND_FUNCTIONAL_V
`define SKY130_FD_SC_LS__TAPVGND_FUNCTIONAL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvgnd ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; string s[1100]; int vis[1100]; int num[100]; int main() { ios::sync_with_stdio(false); int n, len, k; cin >> n >> len >> k; string st; cin >> st; for (int i = 0; i < st.size(); i++) { num[st[i] - a ]++; } int l = 0, r = 25; for (int i = k + 1; i <= n; i++) { for (int j = 1; j <= len; j++) { while (!num[r] && r > l) r--; s[i] += (char)(r + a ); num[r]--; } } int now = 0; int pos = 0; while (1) { for (int i = 1; i <= k; i++) { if (vis[i]) continue; if (pos >= 1 && i != k && (int)(s[i][pos - 1] - a ) < now) { for (int j = pos + 1; j <= len; j++) { while (!num[r] && r > l) r--; s[i] += (char)(r + a ); num[r]--; } vis[i] = 1; continue; } while (!num[l] && r > l) l++; s[i] += (char)(l + a ); num[l]--; if (i == k) { now = l; } } pos++; if (pos == len) break; } sort(s + 1, s + 1 + n); for (int i = 1; i <= n; i++) cout << s[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int N; vector<string> a; vector<int> big; vector<int> mark; string s; string t; int main() { cin >> N; string s1; for (int i = 0; i < N; i++) { cin >> s1; a.push_back(s1); } cin >> s; cin >> t; for (int i = 0; i < s.size(); i++) { string s1 = s.substr(i, 1); if (s1[0] <= Z ) { big.push_back(1); } else { big.push_back(0); } } for (int i = 0; i < s.length(); i++) mark.push_back(0); transform(s.begin(), s.end(), s.begin(), ::tolower); for (int i = 0; i < N; i++) transform(a[i].begin(), a[i].end(), a[i].begin(), ::tolower); for (int i = 0; i < N; i++) { int start = 0; while (s.substr(start).find(a[i]) != -1) { start += s.substr(start).find(a[i]) + 1; for (int j = start - 1; j <= start + a[i].length() - 2; j++) mark[j] = 1; } } string answ; for (int i = 0; i < s.length(); i++) { if (mark[i] == 0) answ.append(s.substr(i, 1)); else { if (s.substr(i, 1) == t) { if (t == a ) answ.append( b ); else answ.append( a ); } else { answ.append(t); } } } for (int i = 0; i < answ.length(); i++) { if (big[i]) { string s1 = answ.substr(i, 1); transform(s1.begin(), s1.end(), s1.begin(), ::toupper); string s2 = answ.substr(0, i); s2.append(s1); if (i + 1 < answ.length()) s2.append(answ.substr(i + 1)); answ = s2; } } cout << answ << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int columns[n + 1]; memset(columns, 0, sizeof(columns)); for (int i = 0; i < m; i++) { int tmp; cin >> tmp; columns[tmp]++; } int ans = 1001; for (int i = 1; i <= n; i++) { ans = min(ans, columns[i]); } cout << ans << endl; return 0; }
|
/*
* Bug report:
*
* From: Hendrik <>
* Subject: gEDA: Pass array element into module in iverilog 0.5
* To:
* Date: Mon, 10 Sep 2001 11:53:04 +0800
*/
module top;
reg [6:0] x[2:0];
speak i0 (x[0], x[1], x[2]);
initial
begin
#10 x[0] = 0;
x[1] = 0;
x[2] = 0;
#100 x[0] = 1;
#100 x[0] = 0;
x[1] = 1;
#100 x[1] = 0;
x[2] = 1;
#100 $finish;
end
endmodule
module speak(x1, x2, x3);
input [6:0] x1, x2, x3;
always #100
$display ("%d: x1=%d, x2=%d, x3=%d", $time, x1, x2, x3);
integer errors;
initial
begin
errors = 0;
#100 if (x1 !== 7'b0 || x2 !== 7'b0 || x3 !== 7'b0)
begin errors = errors + 1; $display("FAILED"); end
#100 if (x1 !== 7'b1 || x2 !== 7'b0 || x3 !== 7'b0)
begin errors = errors + 1; $display("FAILED"); end
#100 if (x1 !== 7'b0 || x2 !== 7'b1 || x3 !== 7'b0)
begin errors = errors + 1; $display("FAILED"); end
#100 if (x1 !== 7'b0 || x2 !== 7'b0 || x3 !== 7'b1)
begin errors = errors + 1; $display("FAILED"); end
if (errors === 0)
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__EINVP_PP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200005; int a[maxn]; long long s[maxn], ss[maxn]; pair<int, long long> que[maxn]; int tot; pair<int, long long> operator-(pair<int, long long> b, pair<int, long long> a) { pair<int, long long> c; c.first = b.first - a.first; c.second = b.second - a.second; return c; } bool operator>(pair<int, long long> b, pair<int, long long> a) { double x = 1.0 * a.second / a.first; double y = 1.0 * b.second / b.first; return x > y; } int main() { int i, j, n; cin >> n; for (int i = 1; i <= n; i++) { scanf( %d , &a[n - i + 1]); } for (i = 1; i <= n; i++) { s[i] = s[i - 1] + a[i]; ss[i] = ss[i - 1] + s[i]; } long long ans = 0; for (i = n; i >= 1; i--) { ans = max(ans, (long long)a[i]); while (tot > 1 && (que[tot - 1] - make_pair(i, ss[i])) > (que[tot - 2] - que[tot - 1])) { tot--; } que[tot++] = make_pair(i, ss[i]); if (tot == 1) { continue; } int le = 0, ri = tot - 2; int mid; while (le <= ri) { mid = (le + ri) / 2; double x = (que[mid].second - que[mid + 1].second) * 1.0 / (que[mid].first - que[mid + 1].first); if (x >= s[i - 1]) { ri = mid - 1; } else le = mid + 1; } ans = max(ans, que[le].second - ss[i - 1] - (que[le].first - i + 1) * s[i - 1]); } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const bool OJ = true; const long long inf = 1LL << 60; template <class T> ostream& operator<<(ostream& os, const vector<T>& v) { for (long long i = 0; i < (((long long)((v).size()))); i++) os << v[i] << ; return os; } template <class T> istream& operator>>(istream& is, vector<T>& v) { for (long long i = 0; i < (((long long)((v).size()))); i++) is >> v[i]; return is; } template <class A, class B> istream& operator>>(istream& is, tuple<A, B>& p) { is >> get<0>(p) >> get<1>(p); return is; } long long dp[100005][30]; string s; long long k; vector<tuple<char, char>> f; bool ok(char x, char y) { return !binary_search((f).begin(), (f).end(), make_tuple(x, y)); } long long solve(long long i, char prev) { if (i == ((long long)((s).size()))) return 0; long long& d = dp[i][prev - 26]; if (d != -1) return d; long long ans = inf; if (ok(prev, s[i])) { ans = min(ans, solve(i + 1, s[i])); } ans = min(ans, 1 + solve(i + 1, prev)); return d = ans; } void run() { cin >> s; cin >> k; f = vector<tuple<char, char>>(); for (long long i = 0; i < (k); i++) { string tmp; cin >> tmp; char x = tmp[0]; char y = tmp[1]; f.emplace_back(x, y); f.emplace_back(y, x); } sort((f).begin(), (f).end()); memset(dp, -1, sizeof(dp)); cout << solve(0, a + 28) << endl; } int main(int argc, char* argv[]) { run(); return 0; }
|
/*-------------------------------------------------------------------------
This confidential and proprietary software may be only used as authorized
by a licensing agreement from amfpga.
(C) COPYRIGHT 2013.www.amfpga.com ALL RIGHTS RESERVED
Filename : sdram_ov7670_vga.v
Author : Amfpga
Data : 2013-02-1
Version : 1.0
Description : sdram vga controller with ov7670 display.
Modification History :
Data By Version Change Description
===========================================================================
13/02/1
--------------------------------------------------------------------------*/
`timescale 1ns/1ns
module ov7670_controller2
(
//Global clock
input clk25Mhz, //25MHz
input resend, //Global Reset
//I2C Side
output OV7670_SIOC, //I2C CLOCK
inout OV7670_SIOD, //I2C DATA
output OV7670_RESET,
output OV7670_PWDN,
output OV7670_XCLK,
output reg Config_Done,//Config Done
output reg [7:0] LUT_INDEX, //LUT Index
output [7:0] I2C_RDATA //I2C Read Data
);
// LUT Data Number
parameter LUT_SIZE = 193;
wire iRST_N = ~resend;
assign OV7670_PWDN = 0;
assign OV7670_RESET = 1;
assign OV7670_XCLK = clk25Mhz;
///////////////////// I2C Control Clock ////////////////////////
// Clock Setting
parameter CLK_Freq = 25_000000; //25 MHz
parameter I2C_Freq = 10_000; //10 KHz
reg [15:0] mI2C_CLK_DIV; //CLK DIV
reg mI2C_CTRL_CLK; //I2C Control Clock
always@(posedge clk25Mhz or negedge iRST_N)
begin
if(!iRST_N)
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)/2)
mI2C_CLK_DIV <= mI2C_CLK_DIV + 1'd1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
//-------------------------------------
reg i2c_en_r0, i2c_en_r1;
always@(posedge clk25Mhz or negedge iRST_N)
begin
if(!iRST_N)
begin
i2c_en_r0 <= 0;
i2c_en_r1 <= 0;
end
else
begin
i2c_en_r0 <= mI2C_CTRL_CLK;
i2c_en_r1 <= i2c_en_r0;
end
end
wire i2c_negclk = (i2c_en_r1 & ~i2c_en_r0) ? 1'b1 : 1'b0; //negedge OV7670_SIOC transfer data
////////////////////// Config Control ////////////////////////////
// Internal Registers/Wires
//reg [23:0] mI2C_DATA; //I2C Data
wire mI2C_END; //I2C Transfer End
wire mI2C_ACK; //I2C Transfer ACK
//reg [7:0] LUT_INDEX; //LUT Index
reg [1:0] mSetup_ST; //State Machine
reg mI2C_GO; //I2C Transfer Start
reg mI2C_WR; //I2C Write / Read Data
always@(posedge clk25Mhz or negedge iRST_N) //25MHz mI2C_CTRL_CLK
begin
if(!iRST_N)
begin
Config_Done <= 0;
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
mI2C_WR <= 0;
end
else if(i2c_negclk)
begin
if(LUT_INDEX < LUT_SIZE)
begin
Config_Done <= 0;
case(mSetup_ST)
0: begin //IDLE State
if(~mI2C_END) //END Transfer
mSetup_ST <= 1;
else //Transfe ing
mSetup_ST <= 0;
mI2C_GO <= 1; //Go Transfer
if(LUT_INDEX < 8'd2)
mI2C_WR <= 0; //Read Data
else
mI2C_WR <= 1; //Write Data
end
1:
begin //Write data
if(mI2C_END)
begin
mI2C_WR <= 0;
mI2C_GO <= 0;
if(~mI2C_ACK) //ACK ACTIVE
mSetup_ST <= 2; //INDEX ++
else
mSetup_ST <= 0; //Repeat Transfer
end
end
2: begin //Address Add
LUT_INDEX <= LUT_INDEX + 8'd1;
mSetup_ST <= 0;
mI2C_GO <= 0;
mI2C_WR <= 0;
end
endcase
end
else
begin
Config_Done <= 1'b1;
LUT_INDEX <= LUT_INDEX;
mSetup_ST <= 0;
mI2C_GO <= 0;
mI2C_WR <= 0;
end
end
end
////////////////////////////////////////////////////////////////////
wire [15:0] LUT_DATA; //{ID-Address£¬SUB-Address£¬Data}
I2C_OV7670_RGB444_Config u_I2C_OV7725_RGB444_Config
(
.LUT_INDEX (LUT_INDEX),
.LUT_DATA (LUT_DATA)
);
////////////////////////////////////////////////////////////////////
I2C_Controller u_I2C_Controller
(
.iCLK (clk25Mhz),
.iRST_N (iRST_N),
.I2C_CLK (mI2C_CTRL_CLK), // Controller Work Clock
.I2C_EN (i2c_negclk), // I2C DATA ENABLE
.I2C_WDATA ({8'h42, LUT_DATA}),// DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.I2C_SCLK (OV7670_SIOC), // I2C CLOCK
.I2C_SDAT (OV7670_SIOD), // I2C DATA
.GO (mI2C_GO), // Go Transfer
.WR (mI2C_WR), // END transfor
.ACK (mI2C_ACK), // ACK
.END (mI2C_END), // END transfor
.I2C_RDATA (I2C_RDATA) // ID
);
////////////////////////////////////////////////////////////////////
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000000 + 7; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n; cin >> n; n -= 10; if (n >= 1 && n <= 11 && n != 10) { cout << 4; } else if (n == 10) { cout << 15; } else { cout << 0; } return 0; }
|
module Transmision (input rw, //rw=1 para transmitir
input clk,
input reset, //reset=0 para transmitir
input wire [7:0] din,
output busy,
output reg done,
output clk_blu,
output reg tx
);
wire clk_f;
Divisor_frecuencia div(.clk(clk), .clk_f(clk_f), .reset(reset));
parameter count = 8;
assign clk_blu = clk_f;
initial begin
tx <= 1'b1;
done=0;
end
reg [7:0] dato = 8'b11111111;
reg [2:0] bitcount = 0;
parameter ESTADO_INACTIVO = 2'b00;
parameter ESTADO_INICIO = 2'b01;
parameter ESTADO_DATO = 2'b10;
parameter ESTADO_FINAL = 2'b11;
reg [1:0] estado = ESTADO_INACTIVO;
always @(posedge clk_f) begin
//done <= ~done; //done??
if (reset)
tx <= 1'b1; //busy=0?
else begin
case (estado)
ESTADO_INACTIVO: begin
if(rw)
estado <= ESTADO_INICIO;
dato <= din;
bitcount <= 0;
done<=0;
tx <= 1'b1;
end
ESTADO_INICIO: begin
tx <= 1'b0;
estado <= ESTADO_DATO;
end
ESTADO_DATO: begin
if (bitcount == count-1)begin
tx<=dato[bitcount];
estado <= ESTADO_FINAL;
end
else begin
tx<=dato[bitcount];
bitcount <= bitcount + 1;
end
end
ESTADO_FINAL: begin
tx <= 1'b1;
done<=1;
estado <= ESTADO_INACTIVO;
end
default: begin
tx <= 1'b1;
estado <= ESTADO_INACTIVO;
end
endcase
end
end
assign busy = (estado != ESTADO_INACTIVO);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void print1d(vector<T> &a) { for (long long int i = 0; i < a.size(); i++) { cout << a[i] << ; } cout << endl; } vector<long long int> divisor(long long int n) { vector<long long int> a; for (long long int i = 1; i * i <= n; i++) { if (n % i == 0) { if (n / i == i) a.push_back(i); else { a.push_back(i); a.push_back(n / i); } } } return a; } bool sortsecond(const pair<long long int, long long int> &a, const pair<long long int, long long int> &b) { return a.second < b.second; } bool isPrime(long long int n) { for (long long int i = 2; i * i <= n; i++) { if (n % i == 0) return false; } return true; } vector<string> split_string(const string &s, const string &delimiter) { vector<string> token; string ans; size_t end_point, start_point = 0, delim_length = delimiter.length(); while ((end_point = s.find(delimiter, start_point)) != string::npos) { ans = s.substr(start_point, end_point - start_point); start_point = end_point + delim_length; token.push_back(ans); } token.push_back(s.substr(start_point)); return token; } bool is_vowel(const char &a) { switch (a) { case a : case e : case i : case o : case u : case y : case A : case E : case I : case O : case U : return true; break; default: return false; break; } } bool sortstring(const string &a, const string &b) { return a.length() < b.length(); } void convert(string &s) { for (long long int i = 0; i < s.length(); i++) { if (s[i] >= A && s[i] <= Z ) s[i] = s[i] - A + a ; if (s[i] == o ) s[i] = 0 ; else if (s[i] == l || s[i] == i ) s[i] = 1 ; } } const long long int K = 998244353; void solve() { long long int n; cin >> n; string s; cin >> s; long long int fir = 0; long long int las = 0; char c = s[0]; long long int k = 0; for (long long int i = 0; i < n; i++) { k = i; if (s[i] == c) fir++; else { break; } } c = s[n - 1]; for (long long int i = n - 1; i >= k; i--) { if (s[i] == c) las++; else break; } if (s[0] == s[n - 1]) cout << ((las + 1) * (fir + 1)) % K << endl; else cout << (fir + las + 1) % K << endl; return; } int32_t main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); ; solve(); return 0; }
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:53:52 2016
/////////////////////////////////////////////////////////////
module GeAr_N20_R5_P5_with_recovery ( clk, in1, in2, res, if_error_delayed,
co1, co2, co3 );
input [19:0] in1;
input [19:0] in2;
output [20:0] res;
input clk;
output if_error_delayed, co1, co2, co3;
wire if_error_1, if_error_delayed_1, if_error_2, if_error_delayed_2, n8,
n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50,
n51, n52, n53, n54, n55;
assign co3 = res[20];
DFFQX1TS if_error_delayed_1_reg ( .D(if_error_1), .CK(clk), .Q(
if_error_delayed_1) );
DFFQX1TS if_error_delayed_2_reg ( .D(if_error_2), .CK(clk), .Q(
if_error_delayed_2) );
OR2X1TS U17 ( .A(in2[5]), .B(if_error_delayed_1), .Y(n22) );
OR2X1TS U18 ( .A(in2[10]), .B(if_error_delayed_2), .Y(n11) );
OR2X1TS U19 ( .A(in1[10]), .B(if_error_delayed_2), .Y(n10) );
OAI21XLTS U20 ( .A0(n15), .A1(n14), .B0(n13), .Y(n16) );
NOR2XLTS U21 ( .A(n33), .B(n15), .Y(n17) );
NOR2XLTS U22 ( .A(n24), .B(n27), .Y(n29) );
OR2X1TS U23 ( .A(in1[5]), .B(if_error_delayed_1), .Y(n21) );
OAI21XLTS U24 ( .A0(n27), .A1(n26), .B0(n25), .Y(n28) );
OR2X1TS U25 ( .A(in1[0]), .B(in2[0]), .Y(n36) );
OR2X1TS U26 ( .A(if_error_delayed_2), .B(if_error_delayed_1), .Y(
if_error_delayed) );
NAND2X1TS U27 ( .A(in1[0]), .B(in2[0]), .Y(n45) );
OAI22X1TS U28 ( .A0(in1[5]), .A1(in2[5]), .B0(in1[8]), .B1(in2[8]), .Y(n9)
);
NOR2XLTS U29 ( .A(in2[6]), .B(in1[6]), .Y(n8) );
NOR2X1TS U30 ( .A(in1[7]), .B(in2[7]), .Y(n24) );
NOR4BX1TS U31 ( .AN(co1), .B(n9), .C(n8), .D(n24), .Y(if_error_1) );
NAND2X1TS U32 ( .A(n11), .B(n10), .Y(n12) );
AFHCINX2TS U33 ( .CIN(n12), .B(in1[11]), .A(in2[11]), .CO(n18) );
NOR2X1TS U34 ( .A(in1[12]), .B(in2[12]), .Y(n33) );
NOR2X1TS U35 ( .A(in1[13]), .B(in2[13]), .Y(n15) );
NAND2X1TS U36 ( .A(in1[12]), .B(in2[12]), .Y(n14) );
NAND2X1TS U37 ( .A(in1[13]), .B(in2[13]), .Y(n13) );
AOI21X1TS U38 ( .A0(n18), .A1(n17), .B0(n16), .Y(n19) );
AFHCINX2TS U39 ( .CIN(n19), .B(in1[14]), .A(in2[14]), .CO(n50) );
INVX2TS U40 ( .A(n20), .Y(res[20]) );
NAND2X1TS U41 ( .A(n22), .B(n21), .Y(n23) );
AFHCINX2TS U42 ( .CIN(n23), .B(in1[6]), .A(in2[6]), .CO(n30) );
NOR2X1TS U43 ( .A(in1[8]), .B(in2[8]), .Y(n27) );
NAND2X1TS U44 ( .A(in1[7]), .B(in2[7]), .Y(n26) );
NAND2X1TS U45 ( .A(in1[8]), .B(in2[8]), .Y(n25) );
AOI21X1TS U46 ( .A0(n30), .A1(n29), .B0(n28), .Y(n31) );
AFHCINX2TS U47 ( .CIN(n31), .B(in1[9]), .A(in2[9]), .CO(n55) );
INVX2TS U48 ( .A(n32), .Y(co2) );
OAI22X1TS U49 ( .A0(in1[10]), .A1(in2[10]), .B0(in1[13]), .B1(in2[13]), .Y(
n35) );
NOR2XLTS U50 ( .A(in2[11]), .B(in1[11]), .Y(n34) );
NOR4BX1TS U51 ( .AN(co2), .B(n35), .C(n34), .D(n33), .Y(if_error_2) );
CLKAND2X2TS U52 ( .A(n36), .B(n45), .Y(res[0]) );
AFHCINX2TS U53 ( .CIN(n37), .B(in1[9]), .A(in2[9]), .S(res[9]), .CO(co1) );
AFHCONX2TS U54 ( .A(in2[8]), .B(in1[8]), .CI(n38), .CON(n37), .S(res[8]) );
AFHCINX2TS U55 ( .CIN(n39), .B(in1[7]), .A(in2[7]), .S(res[7]), .CO(n38) );
AFHCONX2TS U56 ( .A(in2[6]), .B(in1[6]), .CI(n40), .CON(n39), .S(res[6]) );
AFHCINX2TS U57 ( .CIN(n41), .B(in1[5]), .A(in2[5]), .S(res[5]), .CO(n40) );
AFHCONX2TS U58 ( .A(in2[4]), .B(in1[4]), .CI(n42), .CON(n41), .S(res[4]) );
AFHCINX2TS U59 ( .CIN(n43), .B(in1[3]), .A(in2[3]), .S(res[3]), .CO(n42) );
AFHCONX2TS U60 ( .A(in2[2]), .B(in1[2]), .CI(n44), .CON(n43), .S(res[2]) );
AFHCINX2TS U61 ( .CIN(n45), .B(in1[1]), .A(in2[1]), .S(res[1]), .CO(n44) );
AFHCONX2TS U62 ( .A(in2[19]), .B(in1[19]), .CI(n46), .CON(n20), .S(res[19])
);
AFHCINX2TS U63 ( .CIN(n47), .B(in1[18]), .A(in2[18]), .S(res[18]), .CO(n46)
);
AFHCONX2TS U64 ( .A(in2[17]), .B(in1[17]), .CI(n48), .CON(n47), .S(res[17])
);
AFHCINX2TS U65 ( .CIN(n49), .B(in1[16]), .A(in2[16]), .S(res[16]), .CO(n48)
);
AFHCONX2TS U66 ( .A(in2[15]), .B(in1[15]), .CI(n50), .CON(n49), .S(res[15])
);
AFHCONX2TS U67 ( .A(in2[14]), .B(in1[14]), .CI(n51), .CON(n32), .S(res[14])
);
AFHCINX2TS U68 ( .CIN(n52), .B(in1[13]), .A(in2[13]), .S(res[13]), .CO(n51)
);
AFHCONX2TS U69 ( .A(in2[12]), .B(in1[12]), .CI(n53), .CON(n52), .S(res[12])
);
AFHCINX2TS U70 ( .CIN(n54), .B(in1[11]), .A(in2[11]), .S(res[11]), .CO(n53)
);
AFHCONX2TS U71 ( .A(in2[10]), .B(in1[10]), .CI(n55), .CON(n54), .S(res[10])
);
initial $sdf_annotate("GeAr_N20_R5_P5_with_recovery_syn.sdf");
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2006 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
// verilator lint_off MULTIDRIVEN
wire [31:0] outb0c0;
wire [31:0] outb0c1;
wire [31:0] outb1c0;
wire [31:0] outb1c1;
reg [7:0] lclmem [7:0];
ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1),
.outb1c0(outb1c0), .outb1c1(outb1c1)
);
global_mod #(32'hf00d) global_cell ();
global_mod #(32'hf22d) global_cell2 ();
input clk;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
`endif
if (cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf22d) $stop;
if ($root.t.global_cell.globali != 32'hf00d) $stop;
if ($root.t.global_cell2.globali != 32'hf22d) $stop;
if (outb0c0 != 32'h00) $stop;
if (outb0c1 != 32'h01) $stop;
if (outb1c0 != 32'h10) $stop;
if (outb1c1 != 32'h11) $stop;
end
if (cyc==3) begin
// Can we scope down and read and write vars?
ma0.mb0.mc0.out <= ma0.mb0.mc0.out + 32'h100;
ma0.mb0.mc1.out <= ma0.mb0.mc1.out + 32'h100;
ma0.mb1.mc0.out <= ma0.mb1.mc0.out + 32'h100;
ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100;
end
if (cyc==4) begin
// Can we do dotted's inside array sels?
ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12;
lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24;
if (outb0c0 != 32'h100) $stop;
if (outb0c1 != 32'h101) $stop;
if (outb1c0 != 32'h110) $stop;
if (outb1c1 != 32'h111) $stop;
end
if (cyc==5) begin
if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop;
if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop;
if (outb0c0 != 32'h1100) $stop;
if (outb0c1 != 32'h2101) $stop;
if (outb1c0 != 32'h2110) $stop;
if (outb1c1 != 32'h3111) $stop;
end
if (cyc==6) begin
if (outb0c0 != 32'h31100) $stop;
if (outb0c1 != 32'h02101) $stop;
if (outb1c0 != 32'h42110) $stop;
if (outb1c1 != 32'h03111) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef USE_INLINE_MID
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator no_inline_module*/
`else
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`define INLINE_MID_MODULE /*verilator public_module*/
`endif
`endif
module global_mod;
`INLINE_MODULE
parameter INITVAL = 0;
integer globali;
initial globali = INITVAL;
endmodule
module ma (
output wire [31:0] outb0c0,
output wire [31:0] outb0c1,
output wire [31:0] outb1c0,
output wire [31:0] outb1c1
);
`INLINE_MODULE
reg [7:0] rmtmem [7:0];
mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1));
mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1));
endmodule
module mb (
output wire [31:0] outc0,
output wire [31:0] outc1
);
`INLINE_MID_MODULE
parameter P2 = 0;
mc #(P2,0) mc0 (.out(outc0));
mc #(P2,1) mc1 (.out(outc1));
global_mod #(32'hf33d) global_cell2 ();
wire reach_up_clk = t.clk;
always @(reach_up_clk) begin
if (P2==0) begin // Only for mb0
if (outc0 !== t.ma0.mb0.mc0.out) $stop; // Top module name and lower instances
if (outc0 !== ma0.mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== ma .mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== mb.mc0.out) $stop; // This module name and lower instances
if (outc0 !== mb0.mc0.out) $stop; // Upper instance name and lower instances
if (outc0 !== mc0.out) $stop; // Lower instances
if (outc1 !== t.ma0.mb0.mc1.out) $stop; // Top module name and lower instances
if (outc1 !== ma0.mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== ma .mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== mb.mc1.out) $stop; // This module name and lower instances
if (outc1 !== mb0.mc1.out) $stop; // Upper instance name and lower instances
if (outc1 !== mc1.out) $stop; // Lower instances
end
end
endmodule
module mc (output reg [31:0] out);
`INLINE_MODULE
parameter P2 = 0;
parameter P3 = 0;
initial begin
out = {24'h0,P2[3:0],P3[3:0]};
//$write("%m P2=%0x p3=%0x out=%x\n",P2, P3, out);
end
// Can we look from the top module name down?
wire [31:0] reach_up_cyc = t.cyc;
always @ (posedge t.clk) begin
//$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc);
if (reach_up_cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf33d) $stop;
end
if (reach_up_cyc==4) begin
out[15:12] <= {P2[3:0]+P3[3:0]+4'd1};
end
if (reach_up_cyc==5) begin
// Can we set another instance?
if (P3==1) begin // Without this, there are two possible correct answers...
mc0.out[19:16] <= {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2};
$display("%m Set %x->%x %x %x %x %x",mc0.out, {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}, mc0.out[19:16],P2[3:0],P3[3:0],4'd2);
end
end
end
endmodule
|
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
/*ALU Module Includes*/
`include add_32.v
`include and_32.v
`include not_32.v
`include or_32.v
`include xor_32.v
`include shift_carry_right_32.v
`include shift_left_32.v
`include shift_right_32.v
`include compare_32.v
`include decrement_32.v
module ALU(
//32 bit ALU, will upgrade to 64 bit after tests are done.
//Values from register file to operate on
input [31:0] op_a;
input [31:0] op_b;
//op code, decoded from instruction
input [3:0] op_code; //4 bit opcode
//output from the ALU
output reg [31:0] out;
//Flags
output reg flag_carry;
output flag_overflow;
output flag_parity; //even parity of output, 1 valid, 0 invalid
output flag_neg; //output is negative
);
/*Wires*/
wire [31:0] to_out;
wire [31:0] w_and;
wire [31:0] w_or;
wire [31:0] w_xor;
wire [31:0] w_not;
wire [31:0] w_shl; //shift left
wire [31:0] w_shr; //shift right
wire [31:0] w_scr; //shift carry right
wire [31:0] w_cmp; //compare; 0 if true, -1 if less, 1 if greater
wire [31:0] w_add;
wire [31:0] w_sub;
wire [31:0] w_inc; //increment
wire [31:0] w_dec; //decrement
wire flg_carry_sub, flg_carry_add;
/*Instantiations of ALU Modules*/
//Add
add_32 add_32(
.reg_a(op_a),
.reg_b(op_b),
.out(w_add),
.flg_carry(flg_carry_add),
.carryin(1'b0)
);
//Subtract
add_32 sub_32(
.reg_a(op_a),
.reg_b(op_b),
.out(w_sub),
.flg_carry(flg_carry_sub),
.carryin(1'b1) //2's compliment, so need this to be a 1
);
//Increment
add_32 inc_32(
.reg_a(op_a),
.reg_b(32'b0001),
.out(w_inc),
.flg_carry(),
.carryin(1'b0)
);
//Decrement
add_32 dec_32(
.reg_a(op_a),
.reg_b('hFffF), //-1, 2's compliment
.out(w_dec),
.flg_carry(),
.carryin(1'b1) //2's compliment, so need this to be a 1
);
//AND
and_32 and_32(
.a(op_a), //input values
.b(op_b),
.out(w_and) //output value
);
//OR
or_32 or_32(
.a(op_a), //input values
.b(op_b),
.out(w_or) //output value
);
//XOR
xor_32 xor_32(
.a(op_a), //input values
.b(op_b),
.out(w_xor) //output value
);
//NOT
not_32 not_32(
.a(op_a), //input value
.out(w_not) //output value
);
always@*
case(op_code)
/*0*/ 4'b0000:begin //for NOP
out <= 0;
end
/*1*/ 4'b0001:begin //output AND operation
out <= w_and;
end
/*2*/ 4'b0010:begin //output OR operation
out <= w_or;
end
/*3*/ 4'b0011:begin //output XOR operation
out <= w_xor;
end
/*4*/ 4'b0100:begin //output NOT operation
out <= w_not;
end
/*5*/ 4'b0101:begin //output shift left operation
out <= w_shl;
end
/*6*/ 4'b0110:begin //output shift right operation
out <= w_shr;
end
/*7*/ 4'b0111:begin //output shift carry right operation
out <= w_scr;
end
/*8*/ 4'b1000:begin //output compare operation
out <= w_cmp;
end
/*9*/ 4'b1001:begin //output for ADD operation
out <= w_add;
flag_carry <= flg_carry_add;
end
/*10*/ 4'b1010:begin //output for SUBTRACT operation
out <= w_sub;
flag_carry <= flg_carry_sub;
end
/*11*/ 4'b1011:begin //output for INCREMENT operation
out <= w_inc;
end
/*12*/ 'b1100:begin //output for DECREMENT operation
out <= w_dec;
end
/*13*/ 4'b1101:begin
out <= 0;
end
/*14*/ 4'b1110:begin
out <= 0;
end
/*15*/ 4'b1111:begin
out <= 0;
end
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a[101] = {}, b = 0, c, d, x, y, i, max = -1, f = 0; cin >> x >> y; for (i = 1; i <= x; i++) { cin >> c; a[c]++; } for (i = 1; i <= 100; i++) { if (a[i] > max) max = a[i]; if (a[i] != 0) f++; } if (max % y == 0) b = max / y; else b = max / y + 1; cout << b * y * f - x; }
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#include <bits/stdc++.h> using namespace std; int main() { long long int n, net, i, flag, d; string str; cin >> n; net = 0; flag = 0; for (i = 0; i < n; i++) { cin >> d; cin >> str; if ((net == 0) && (str != South )) flag = 1; if ((net == 20000) && (str != North )) flag = 1; if (str == South ) net += d; else if (str == North ) net -= d; if (net > 20000 || net < 0) flag = 1; } if (net != 0) flag = 1; if (flag == 1) cout << NO n ; else cout << YES n ; return 0; }
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#include <bits/stdc++.h> const int N = 300010; const int MOD = 1e9 + 7; struct xxx { int id; char c; } s[N]; std::string a, b, c; int gap, n; int sa[N], lcp[N], rank[N], tmp[N], bucket[N], cnt[N][3], ans[N], dp[19][N], fw[N]; void update(int i, int v) { while (i < N) { fw[i] = (fw[i] + v) % MOD; i += i & -i; } } int query(int i) { int res = 0; while (i) { res = (res + fw[i]) % MOD; i -= i & -i; } if (res < 0) res += MOD; return res; } int rmq(int f, int t) { int k = 31 - __builtin_clz(t - f + 1); int x = dp[k][f]; int y = dp[k][t - (1 << k) + 1]; if (lcp[x] < lcp[y]) return x; return y; } void solve(int f, int t, int h) { if (t - f + 1 < 3) return; int m = rmq(f, t - 1); int c0 = cnt[t][0] - cnt[f - 1][0]; int c1 = cnt[t][1] - cnt[f - 1][1]; int c2 = cnt[t][2] - cnt[f - 1][2]; int v = lcp[m]; int num = 1ll * c0 * c1 % MOD * c2 % MOD; update(v + 1, -num); update(h + 1, num); solve(f, m, v); solve(m + 1, t, v); } bool cmp2(int i, int j) { i += gap; j += gap; if (i < n && j < n) return rank[i] < rank[j]; return i > j; } bool cmp(int i, int j) { if (rank[i] != rank[j]) return rank[i] < rank[j]; i += gap; j += gap; if (i < n && j < n) return rank[i] < rank[j]; return i > j; } int main() { std::cin >> a >> b >> c; int an = int(a.size()), bn = int(b.size()), cn = int(c.size()); for (int i = 0; i < an; ++i) s[i].id = 0, s[i].c = a[i]; for (int i = 0; i < bn; ++i) s[i + an + 1].id = 1, s[i + an + 1].c = b[i]; for (int i = 0; i < cn; ++i) s[i + an + bn + 2].id = 2, s[i + an + bn + 2].c = c[i]; s[an].c = 1; s[an + bn + 1].c = 2; n = an + bn + cn + 2; int rn = 255; for (int i = 0; i < n; ++i) { sa[i] = i; rank[i] = s[i].c; } for (gap = 1;; gap <<= 1) { int p = 0; for (int i = n - 1; i + gap >= n; --i) tmp[p++] = i; std::fill(bucket, bucket + rn, 0); for (int i = 0; i + gap < n; ++i) ++bucket[rank[i + gap]]; for (int i = 1; i < rn; ++i) bucket[i] += bucket[i - 1]; for (int i = 0; i + gap < n; ++i) tmp[--bucket[rank[i + gap]] + p] = i; std::fill(bucket, bucket + rn, 0); for (int i = 0; i < n; ++i) ++bucket[rank[i]]; for (int i = 1; i < rn; ++i) bucket[i] += bucket[i - 1]; for (int i = n - 1; i >= 0; --i) sa[--bucket[rank[tmp[i]]]] = tmp[i]; tmp[0] = 0; for (int i = 1; i < n; ++i) tmp[i] = tmp[i - 1] + cmp(sa[i - 1], sa[i]); for (int i = 0; i < n; ++i) rank[sa[i]] = tmp[i]; if (tmp[n - 1] == n - 1) break; rn = tmp[n - 1] + 1; } for (int i = 0, k = 0; i < n; ++i) { if (rank[i] == n - 1) continue; for (int j = sa[rank[i] + 1]; s[i + k].c == s[j + k].c;) ++k; lcp[rank[i]] = k; if (k) --k; } for (int i = 0; i < n - 1; ++i) dp[0][i] = i; for (int j = 1; 1 << j < n; ++j) for (int i = 0; i + (1 << j) - 1 < n - 1; ++i) { int x = dp[j - 1][i]; int y = dp[j - 1][i + (1 << (j - 1))]; dp[j][i] = lcp[x] < lcp[y] ? x : y; } assert(s[sa[0]].c == 1); assert(s[sa[1]].c == 2); for (int i = 2; i < n; ++i) { cnt[i][0] = cnt[i - 1][0]; cnt[i][1] = cnt[i - 1][1]; cnt[i][2] = cnt[i - 1][2]; ++cnt[i][s[sa[i]].id]; } int sz = std::min(an, std::min(bn, cn)); solve(2, n - 1, 0); for (int i = 1; i <= sz; ++i) std::cout << query(i) << ; }
|
module sha1_compression(
input [159:0] hash_state_in,
input [ 31:0] w,
input [ 6:0] round,
output [159:0] hash_state_out
);
reg [31:0] k;
reg [31:0] f;
wire [31:0] temp;
wire [31:0] a = hash_state_in[159:128];
wire [31:0] b = hash_state_in[127:96 ];
wire [31:0] c = hash_state_in[ 95:64 ];
wire [31:0] d = hash_state_in[ 63:32 ];
wire [31:0] e = hash_state_in[ 31:0 ];
assign temp = {a[26:0], a[31:27]} + f + e + k + w;
assign hash_state_out = {temp, a, {b[1:0], b[31:2]}, c, d};
always @ (round or b or c or d) begin
case (1'b1)
between(7'd0, round, 7'd19): begin k = 32'h5A827999; f = (b & c) | (~b & d); end
between(7'd20, round, 7'd39): begin k = 32'h6ED9EBA1; f = b ^ c ^ d; end
between(7'd40, round, 7'd59): begin k = 32'h8F1BBCDC; f = (b & c) | (b & d) | (c & d); end
between(7'd60, round, 7'd79): begin k = 32'hCA62C1D6; f = b ^ c ^ d; end
endcase
end
function reg between(
input [6:0] low,
input [6:0] value,
input [6:0] high
);
begin
between = value >= low && value <= high;
end
endfunction
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int i = 1, j = n, count = 0, k = 1; while (k <= (n - 1)) { count = count + ((i + j) % (n + 1)); if (k % 2 == 1) { i++; } else { j--; } k++; } cout << count; }
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#include <bits/stdc++.h> using namespace std; const int iinf = 1e9 + 10; const long long inf = 1ll << 60; const long long mod = 1e9 + 7; void GG() { cout << 0 n ; exit(0); } long long mpow(long long a, long long n, long long mo = mod) { long long re = 1; while (n > 0) { if (n & 1) re = re * a % mo; a = a * a % mo; n >>= 1; } return re; } long long inv(long long b, long long mo = mod) { if (b == 1) return b; return (mo - mo / b) * inv(mo % b, mo) % mo; } const int maxn = 1e6 + 5; long long dp[2003][22]; long long fac[200006], ifac[200006]; inline long long CC(int a, int b) { a = a + b; return fac[a] * ifac[b] % mod * ifac[a - b] % mod; } int R[2003], C[2003]; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); ; fac[0] = ifac[0] = 1; for (int i = 1; i <= 200006; ++i) { fac[i] = fac[i - 1] * i % mod; ifac[i] = inv(fac[i]); } int n, m, k, second; cin >> n >> m >> k >> second; vector<pair<int, int> > v; v.push_back({1, 1}); v.push_back({n, m}); for (int i = 0; i < k; ++i) { int r, c; cin >> r >> c; v.push_back({r, c}); } sort(v.begin(), v.end()); for (int i = 1; i <= (int)v.size() - 1; ++i) { R[i] = v[i].first, C[i] = v[i].second; dp[i][0] = CC(R[i] - 1, C[i] - 1); for (int fk = 0; fk < 21; ++fk) { for (int j = 1; j <= i - 1; ++j) { if (R[j] <= R[i] && C[j] <= C[i]) { dp[i][fk] -= dp[j][fk] * CC(R[i] - R[j], C[i] - C[j]) % mod; if (dp[i][fk] < 0) dp[i][fk] += mod; dp[i][fk + 1] += dp[j][fk] * CC(R[i] - R[j], C[i] - C[j]) % mod; if (dp[i][fk + 1] >= mod) dp[i][fk + 1] -= mod; } } } } long long re = 0; for (int fk = 0; fk < 22; ++fk) { re += dp[(int)v.size() - 1][fk] * second % mod; second = (second + 1) / 2; } cout << re * inv(CC(n - 1, m - 1)) % mod << n ; }
|
#include <bits/stdc++.h> using namespace std; void test_case() { int n; long long k; cin >> n >> k; int l, r[2] = {-1, -1}; long long curr[2] = {k, k}, ans[2] = {0, 0}, monsters; for (int i = 0; i < n; i++) { int old_r[2] = {r[0], r[1]}, tmp_r; long long old_curr[2] = {curr[0], curr[1]}, old_ans[2] = {ans[0], ans[1]}; cin >> l >> tmp_r >> monsters; ans[0] = -1; for (int j = 0; j < 2; j++) { if (old_ans[j] == -1) continue; if (old_curr[j] + (tmp_r - l) * k < monsters) continue; if (ans[0] != -1 && ans[0] < old_ans[j] + monsters) continue; ans[0] = old_ans[j] + monsters; if (old_curr[j] >= monsters) { r[0] = l; curr[0] = old_curr[j] - monsters; } else { int turns = (monsters - old_curr[j] + k - 1) / k; r[0] = l + turns; curr[0] = k * turns + old_curr[j] - monsters; } } ans[1] = -1; for (int j = 0; j < 2; j++) { if (old_ans[j] == -1) continue; if ((tmp_r - l + 1) * k < monsters) continue; if (old_r[j] == l) continue; if (ans[1] != -1 && ans[1] <= old_ans[j] + old_curr[j] + monsters) continue; ans[1] = old_ans[j] + old_curr[j] + monsters; int turns = (monsters + k - 1) / k; r[1] = l + turns - 1; curr[1] = k * turns - monsters; } } if (ans[0] == -1) cout << ans[1] << n ; else if (ans[1] == -1) cout << ans[0] << n ; else cout << min(ans[0], ans[1]) << n ; } int main(void) { ios::sync_with_stdio(0); cin.tie(0); int Case = 1; for (int i = 0; i < Case; i++) { test_case(); } return 0; }
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#include <bits/stdc++.h> using namespace std; char s[10][10]; int main() { int bl = 0, wh = 0; for (int i = 0; i < 8; i++) scanf( %s , s[i]); for (int i = 0; i < 8; i++) for (int j = 0; j < 8; j++) { if (s[i][j] == Q ) wh += 9; else if (s[i][j] == R ) wh += 5; else if (s[i][j] == B ) wh += 3; else if (s[i][j] == N ) wh += 3; else if (s[i][j] == P ) wh += 1; else if (s[i][j] == q ) bl += 9; else if (s[i][j] == r ) bl += 5; else if (s[i][j] == b ) bl += 3; else if (s[i][j] == n ) bl += 3; else if (s[i][j] == p ) bl += 1; } if (bl > wh) printf( Black n ); else if (bl == wh) printf( Draw n ); else printf( White n ); return 0; }
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#include <bits/stdc++.h> using namespace std; double dp[1 << 20][20], p[20][20]; bool mark[1 << 20][20]; int n; double mem(int mask, int winner) { if (!mask) return (winner == 1); if (mark[mask][winner]) return dp[mask][winner]; mark[mask][winner] = true; double &ret = dp[mask][winner]; for (int i = 1; i < n; i++) if (mask & (1 << i)) { double tmp = 0; tmp += p[i][winner] * mem(mask ^ (1 << i), i); tmp += p[winner][i] * mem(mask ^ (1 << i), winner); ret = max(ret, tmp); } return ret; } int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; i++) { p[i][0] = 1; for (int j = 1; j <= n; j++) cin >> p[i][j]; } n++; cout << setprecision(10) << fixed << mem((1 << n) - 2, 0) << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__AND3B_PP_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_PP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; const int N = 41, K = 11; bitset<40> a[N]; vector<int> steps[K]; int n, k; bool ok = true; void go(int pos, bitset<40> is_one, bitset<40> is_question) { if (pos == k) { if (is_question != 0) { ok = false; return; } int ones = is_one.count(); if (is_one != a[ones]) { ok = false; return; } return; } int ones = 0, zeros = 0, questions = 0; for (int i : steps[pos]) { if (is_question[i]) { questions++; } else if (is_one[i]) { ones++; } else { zeros++; } is_question[i] = 0; is_one[i] = 1; } for (int i = 0; i < zeros; i++) { is_one[steps[pos][i]] = 0; } go(pos + 1, is_one, is_question); for (int i = zeros; i < questions + zeros; i++) { is_one[steps[pos][i]] = 0; go(pos + 1, is_one, is_question); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int _ = 1; while (_--) { cin >> n >> k; for (int i = 0; i <= n; i++) { a[i] = 0; for (int j = 0; j < i; j++) { a[i][n - j - 1] = 1; } } for (int i = 0; i < k; i++) { int q; cin >> q; while (q--) { int x; cin >> x; steps[i].push_back(--x); } } bitset<40> is_one = 0; bitset<40> is_question = (1ll << n) - 1; go(0, is_one, is_question); cout << (n == 1 || ok ? ACCEPTED : REJECTED ) << endl; } }
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#include <bits/stdc++.h> namespace competitive_programming { inline namespace utility {} namespace debugging {} namespace io {} } // namespace competitive_programming namespace competitive_programming::utility { class timer { private: std::chrono::time_point<std::chrono::steady_clock> begin, end; public: timer() : begin(), end() {} ~timer() {} }; } // namespace competitive_programming::utility constexpr bool test_cases = true; void yes() { std::cout << YES n ; } void no() { std::cout << NO n ; } auto solve() -> void { int64_t x, y; std::cin >> x >> y; if (x - y < 2) no(); else yes(); } int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); std::cout.precision(10); std::cerr.precision(10); std::cout << std::fixed << std::boolalpha; std::cerr << std::fixed << std::boolalpha; competitive_programming::timer t; int32_t cases = 1; if (test_cases) std::cin >> cases; while (cases--) solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int flag = 0, i, k; string str, s; cin >> str; if (str.at(0) == - ) { flag = 1; str.erase(0, 1); } if (flag == 1) cout << ( ; cout << $ ; if ((int)str.find( . ) != -1) s = str.substr(0, str.find( . )); else s = str.substr(0); k = s.length() % 3; for (i = 0; i < s.length(); i++) { if (i % 3 == k && i != 0) cout << , ; cout << str.at(i); } cout << . ; if (str.find( . ) == -1) { cout << 00 ; goto jump; } s = str.substr(str.find( . ) + 1); s += 0 ; s = s.substr(0, 2); cout << s; jump: if (flag == 1) cout << ) ; cout << endl; return 0; }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_axis_dma_tx (
// dac interface
dac_clk,
dac_rst,
// dma interface
dma_clk,
dma_rst,
dma_frmcnt,
dma_ovf,
dma_unf,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00050062;
parameter PCORE_ID = 0;
// dac interface
input dac_clk;
output dac_rst;
// dma interface
input dma_clk;
output dma_rst;
output [31:0] dma_frmcnt;
input dma_ovf;
input dma_unf;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg [31:0] up_dma_frmcnt = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_preset_s;
wire up_dma_ovf_s;
wire up_dma_unf_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h10) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h10) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_resetn <= 'd0;
up_dma_frmcnt <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_dma_frmcnt <= up_wdata;
end
if (up_dma_ovf_s == 1'b1) begin
up_dma_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_dma_ovf <= up_dma_ovf & ~up_wdata[1];
end
if (up_dma_unf_s == 1'b1) begin
up_dma_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_dma_unf <= up_dma_unf & ~up_wdata[0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {31'd0, up_resetn};
8'h21: up_rdata <= up_dma_frmcnt;
8'h22: up_rdata <= {30'd0, up_dma_ovf, up_dma_unf};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_dac_rst_reg (.preset(up_preset_s), .clk(dac_clk), .rst(dac_rst));
ad_rst i_dma_rst_reg (.preset(up_preset_s), .clk(dma_clk), .rst(dma_rst));
// dma control & status
up_xfer_cntrl #(.DATA_WIDTH(32)) i_dma_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ( up_dma_frmcnt),
.d_rst (dma_rst),
.d_clk (dma_clk),
.d_data_cntrl ( dma_frmcnt));
up_xfer_status #(.DATA_WIDTH(2)) i_dma_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_dma_ovf_s,
up_dma_unf_s}),
.d_rst (dma_rst),
.d_clk (dma_clk),
.d_data_status ({ dma_ovf,
dma_unf}));
endmodule
// ***************************************************************************
// ***************************************************************************
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#include <bits/stdc++.h> using namespace std; void solve() { int n, t; while (cin >> n >> t) { int x, y; vector<pair<int, int> > a; vector<pair<int, int> > v; for (int i = 0; i < n; i++) { cin >> x >> y; a.push_back(make_pair(x, y)); } for (int i = 0; i < n; i++) { while (a[i].first < t) a[i].first += a[i].second; v.push_back(make_pair(a[i].first, i)); } sort(v.begin(), v.end()); cout << (v[0].second) + 1 << endl; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); solve(); }
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// DEFINES
`define BITS 8 // Bit width of the operands
`define B2TS 16 // Bit width of the operands
module bm_base_multiply(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out2,
out3,
out4,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input [`BITS-1:0] c_in;
input [`BITS-1:0] d_in;
input [`BITS-1:0] e_in;
input [`BITS-2:0] f_in;
output [`B2TS-1:0] out0;
output [`B2TS-1:0] out1;
output [`B2TS-1:0] out2;
output [14:0] out3;
output [14:0] out4;
reg [`B2TS-1:0] out0;
wire [`B2TS-1:0] out1;
reg [`B2TS-1:0] out2;
reg [14:0] out3;
wire [14:0] out4;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
always @(posedge clock)
begin
out0 <= a_in * b_in;
out2 <= temp_a & temp_b;
out3 <= e_in * f_in;
end
assign out1 = c_in * d_in;
assign out4 = f_in * e_in;
endmodule
/*---------------------------------------------------------*/
module a(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock)
begin
out <= a_in & b_in;
end
endmodule
/*---------------------------------------------------------*/
module b(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
a my_a(clock, a_in, b_in, temp);
always @(posedge clock)
begin
out <= a_in & temp;
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int MAXN = 60; long long h, n; int step[MAXN]; inline long long calc(long long high) { return (1ll << (high + 1)) - 1; } void solve() { long long tmp = (1ll << h) - 1 + n; int cnt = 0; while (tmp != 1) { if (tmp % 2 == 1) step[cnt++] = 1; else step[cnt++] = 0; tmp /= 2; } long long res = 0; int curdir = 0, dep = 0; for (int i = cnt - 1; i >= 0; i--) { if (curdir == step[i]) { dep++; res++; curdir ^= 1; } else { long long tmp = calc(h - dep - 1); res += tmp; curdir = step[i]; i++; } } cout << res << endl; } int main() { cin >> h >> n; solve(); return 0; }
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