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#include <bits/stdc++.h> using namespace std; const double pi = 3.141592653589793238462643383; int main() { { int n, m, k, t; cin >> n >> m >> k >> t; set<int> s; ; for (long long i = 0; i < k; i++) { int a, b; cin >> a >> b; int id = (a - 1) * m + b; s.insert(id); }; for (long long i = 0; i < t; i++) { int a, b; cin >> a >> b; int id = (a - 1) * m + b; if (s.find(id) != s.end()) cout << Waste << endl; else { auto it = lower_bound(s.begin(), s.end(), id); int d = distance(s.begin(), it); int val = (id - d) % 3; if (val == 0) cout << Grapes << endl; else if (val == 1) cout << Carrots << endl; else cout << Kiwis << endl; } } } }
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#include <bits/stdc++.h> using namespace std; int main() { long long int n, m; cin >> n >> m; if (m == 0) { cout << YES << endl; return 0; } vector<long long int> v(m); for (long long int i = 0; i < m; cin >> v[i++]) ; sort(v.begin(), v.end()); if (v[0] == 1 || v[m - 1] == n) { cout << NO << endl; return 0; } int ind = 1, ans = 0; for (int i = 0; i < (m - 2); i++) { if ((v[i] == (v[i + 1] - 1)) && (v[i + 1] == (v[i + 2] - 1))) { cout << NO << endl; return 0; } } cout << YES << endl; }
|
module top;
reg q1, q2, q3, q4, q5, q6, q7, d;
reg clk;
reg [5:4] rst;
integer i;
// The compiler should warn that clk is missing an edge keyword.
always_ff @(clk) begin
q1 <= d;
end
// The compiler should warn that rst is missing an edge keyword.
always_ff @(posedge clk or rst[4]) begin
if (rst[4])
q2 <= 1'b0;
else
q2 <= d;
end
// The compiler should warn that rst is missing an edge keyword.
always_ff @(posedge clk or rst[i]) begin
if (rst[i])
q3 <= 1'b0;
else
q3 <= d;
end
// The compiler should warn that rst is missing an edge keyword.
always_ff @(posedge clk or !rst) begin
if (!rst)
q4 <= 1'b0;
else
q4 <= d;
end
// The compiler should warn that rst is missing an edge keyword.
always_ff @(posedge clk or ~rst[4]) begin
if (~rst[4])
q5 <= 1'b0;
else
q5 <= d;
end
// The compiler should warn that rst is missing an edge keyword.
always_ff @(posedge clk or &rst) begin
if (&rst)
q6 <= 1'b0;
else
q6 <= d;
end
// The compiler should warn that rst is not a single bit.
always_ff @(posedge clk or posedge rst) begin
if (rst)
q7 <= 1'b0;
else
q7 <= d;
end
initial begin
$display("Expect compile warnings!\nPASSED");
end
endmodule
|
`define bsg_and_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_250_AND2X1_b``bits and_gate (.i0(a_i),.i1(b_i),.o); \
end
module bsg_and #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [width_p-1:0] o
);
`bsg_and_macro(34) else
`bsg_and_macro(33) else
`bsg_and_macro(32) else
`bsg_and_macro(31) else
`bsg_and_macro(30) else
`bsg_and_macro(29) else
`bsg_and_macro(28) else
`bsg_and_macro(27) else
`bsg_and_macro(26) else
`bsg_and_macro(25) else
`bsg_and_macro(24) else
`bsg_and_macro(23) else
`bsg_and_macro(22) else
`bsg_and_macro(21) else
`bsg_and_macro(20) else
`bsg_and_macro(19) else
`bsg_and_macro(18) else
`bsg_and_macro(17) else
`bsg_and_macro(16) else
`bsg_and_macro(15) else
`bsg_and_macro(14) else
`bsg_and_macro(13) else
`bsg_and_macro(12) else
`bsg_and_macro(11) else
`bsg_and_macro(10) else
`bsg_and_macro(9) else
`bsg_and_macro(8) else
`bsg_and_macro(7) else
`bsg_and_macro(6) else
`bsg_and_macro(5) else
`bsg_and_macro(4) else
`bsg_and_macro(3) else
`bsg_and_macro(2) else
`bsg_and_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = a_i & b_i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_and)
|
#include <bits/stdc++.h> using namespace std; double PI = acos(-1.0); long long mod = 998244353; struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; long long GCD(long long a, long long b) { if (b == 0) return a; return GCD(b, a % b); } long long prod(long long a, long long b) { long long res = 0; a %= mod; while (b) { if (b & 1ll) res = (res + a) % mod; a = (2ll * a) % mod; b >>= 1ll; } return res; } long long power(long long a, long long b) { long long res = 1ll; while (b > 0) { if (b % 2ll) res = (res * a) % mod; a = (a * a) % mod; b /= 2ll; } return res; } long long binaryExponentiation(long long a, long long b) { long long result = 1ll; while (b > 0) { if (b % 2 == 1) result = (result * a) % mod; a = (a * a) % mod; b /= 2ll; } return result; } long long ModularInverse(long long a) { return binaryExponentiation(a, mod - 2); } long long n, m; void solve() { cin >> n; vector<long long> a(n); for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) { if (a[i] >= 0) { a[i] = -a[i] - 1; } } long long x = INT_MAX, p = 0; for (long long i = 0; i < n; i++) { if (a[i] < x) { x = a[i]; p = i; } } if (n % 2) { a[p] = -a[p] - 1; } for (auto &e : a) { cout << e << ; } cout << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; char ch[n]; ch[n] = 0 ; int a[n][2]; for (int i = 0; i < n; i++) { cin >> a[i][0] >> a[i][1]; } int suma = 0; int sumg = 0; for (int i = 0; i < n; i++) { if (((a[i][0] + suma) - sumg) <= 500) { suma += a[i][0]; ch[i] = A ; } else if (((a[i][1] + sumg) - suma) <= 500) { sumg += a[i][1]; ch[i] = G ; } } if ((abs(suma - sumg)) > 500) { cout << -1 ; } else { cout << ch; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int depth; cin >> depth; int n = (1 << (depth + 1)) - 1; vector<int> pre(n + 1, 0), add(n + 1, 0); for (int i = 2; i <= n; ++i) { cin >> pre[i]; } vector<int> way(n + 1, 0); for (int i = 2; i <= n; ++i) { way[i] = way[i / 2] + pre[i]; } int target = *max_element((way).begin(), (way).end()); for (int i = n / 2 + 1; i <= n; ++i) { add[i] = target - way[i]; } for (int i = n / 2; i >= 2; --i) { add[i] = min(add[2 * i], add[2 * i + 1]); add[2 * i] -= add[i]; add[2 * i + 1] -= add[i]; } cout << accumulate((add).begin(), (add).end(), 0) << n ; }
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : gpio.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/gpio/gpio.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-12-08 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//*---------------------------------------------------------------------------------------------------
//File Include : system header file
`include "../sys_include.h"
`include "gpio.h"
module gpio (
input wire clk,
input wire reset,
input wire cs_n,
input wire as_n,
input wire rw,
input wire [`GpioAddrBus] addr,
input wire [`WordDataBus] wr_data,
output reg [`WordDataBus] rd_data,
output reg rdy_n
`ifdef GPIO_IN_CH
, input wire [`GPIO_IN_CH-1:0] gpio_in
`endif
`ifdef GPIO_OUT_CH
, output reg [`GPIO_OUT_CH-1:0] gpio_out
`endif
`ifdef GPIO_IO_CH
, inout wire [`GPIO_IO_CH-1:0] gpio_io
`endif
);
`ifdef GPIO_IO_CH
wire [`GPIO_IO_CH-1:0] io_in;
reg [`GPIO_IO_CH-1:0] io_out;
reg [`GPIO_IO_CH-1:0] io_dir;
reg [`GPIO_IO_CH-1:0] io;
integer i;
assign io_in = gpio_io;
assign gpio_io = io;
always @(*) begin
for (i = 0; i < `GPIO_IO_CH; i = i + 1) begin : IO_DIR
io[i] = (io_dir[i] == `GPIO_DIR_IN) ? 1'bz : io_out[i];
end
end
`endif
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
rd_data <= #1 `WORD_DATA_W'h0;
rdy_n <= #1 `DISABLE_N;
`ifdef GPIO_OUT_CH
gpio_out <= #1 {`GPIO_OUT_CH{`LOW}};
`endif
`ifdef GPIO_IO_CH
io_out <= #1 {`GPIO_IO_CH{`LOW}};
io_dir <= #1 {`GPIO_IO_CH{`GPIO_DIR_IN}};
`endif
end else begin
if ((cs_n == `ENABLE_N) && (as_n == `ENABLE_N)) begin
rdy_n <= #1 `ENABLE_N;
end else begin
rdy_n <= #1 `DISABLE_N;
end
if ((cs_n == `ENABLE_N) && (as_n == `ENABLE_N) && (rw == `READ)) begin
case (addr)
`ifdef GPIO_IN_CH
`GPIO_ADDR_IN_DATA : begin
rd_data <= #1 {{`WORD_DATA_W-`GPIO_IN_CH{1'b0}},
gpio_in};
end
`endif
`ifdef GPIO_OUT_CH
`GPIO_ADDR_OUT_DATA : begin
rd_data <= #1 {{`WORD_DATA_W-`GPIO_OUT_CH{1'b0}},
gpio_out};
end
`endif
`ifdef GPIO_IO_CH
`GPIO_ADDR_IO_DATA : begin
rd_data <= #1 {{`WORD_DATA_W-`GPIO_IO_CH{1'b0}},
io_in};
end
`GPIO_ADDR_IO_DIR : begin
rd_data <= #1 {{`WORD_DATA_W-`GPIO_IO_CH{1'b0}},
io_dir};
end
`endif
endcase
end else begin
rd_data <= #1 `WORD_DATA_W'h0;
end
if ((cs_n == `ENABLE_N) && (as_n == `ENABLE_N) && (rw == `WRITE)) begin
case (addr)
`ifdef GPIO_OUT_CH
`GPIO_ADDR_OUT_DATA : begin
gpio_out <= #1 wr_data[`GPIO_OUT_CH-1:0];
end
`endif
`ifdef GPIO_IO_CH
`GPIO_ADDR_IO_DATA : begin
io_out <= #1 wr_data[`GPIO_IO_CH-1:0];
end
`GPIO_ADDR_IO_DIR : begin
io_dir <= #1 wr_data[`GPIO_IO_CH-1:0];
end
`endif
endcase
end
end
end
endmodule
|
/*********************************************************************
* SYNOPSYS CONFIDENTIAL *
* *
* This is an unpublished, proprietary work of Synopsys, Inc., and *
* is fully protected under copyright and trade secret laws. You may *
* not view, use, disclose, copy, or distribute this file or any *
* information contained herein except pursuant to a valid written *
* license from Synopsys. *
*********************************************************************/
module ChipTop (MemWriteBus, MemWriteValid, MemReadBus, clock, reset,
inst_on, inst_iso_in, inst_iso_out,
gprs_on, gprs_iso_in, gprs_iso_out,
mult_on, mult_iso_in, mult_iso_out,
inst_save, inst_nrestore, gprs_save, gprs_nrestore
);
input [31:0] MemReadBus; // Memory Read Bus
output [31:0] MemWriteBus; // Memory Write Bus
output MemWriteValid; // Memory Write Bus Contains Data
input clock; // System Clock
input reset;
input inst_on; // switch
input inst_iso_in; // iso
input inst_iso_out; // iso
input inst_save;
input inst_nrestore;
wire inst_ack;
input gprs_on; // switch
input gprs_iso_in; // iso
input gprs_iso_out; // iso
input gprs_save;
input gprs_nrestore;
wire gprs_ack;
input mult_iso_in; // iso
input mult_iso_out; // iso
input mult_on; // switch
wire mult_ack;
wire genpp_on;
wire genpp_ack;
wire [31:0] MemReadBus; // Memory Read Bus
wire [31:0] MemWriteBus; // Memory Write Bus
wire MemWriteValid; // Memory Write Bus Contains Data
wire [31:0] A, B, C; // Data Buses
wire [3:0] RdAdrA, RdAdrB, RdAdrC; // Read Addresses
wire [3:0] WrtAdrX, WrtAdrY; // Write Address
wire WrtEnbX, WrtEnbY; // Write Enables
wire [31:0] Product; // Multiplier output
wire [31:0] iso_Product; // Multiplier output
wire Ovfl; // Multiplier Overflow
wire [31:0] iso_MemReadBus_to_inst;
wire iso_clock_to_inst;
wire [31:0] iso_MemReadBus_to_gprs;
wire iso_clock_to_gprs;
wire [3:0] iso_RdAdrA_to_gprs;
wire [3:0] iso_RdAdrB_to_gprs;
wire [3:0] iso_RdAdrC_to_gprs;
wire [3:0] iso_WrtAdrX_to_gprs;
wire [3:0] iso_WrtAdrY_to_gprs;
wire iso_WrtEnbX_to_gprs;
wire iso_WrtEnbY_to_gprs;
wire [31:0] iso_Product_to_gprs;
assign MemWriteBus = A; // Drive A to Write Bus
wire GENPP_ao = 1'b1;
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Instruction Decoder
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
InstructionDecoder InstDecode(MemReadBus,RdAdrA,RdAdrB,RdAdrC,
WrtAdrX,WrtEnbX,
WrtAdrY,WrtEnbY,
MemWriteValid, clock, reset);
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// 16 General Purpose Registers
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
GeneralPurposeRegisters GPRs(A,B,C,RdAdrA,RdAdrB,RdAdrC,
WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,
MemReadBus,Product,
clock, reset);
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// 32 x 32 Signed Multiplier
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Mult_32x32 Multiplier(Ovfl,Product,A,B,C,clock,mult_iso_in, reset);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Rose-Hulman Institute of Technology
// Engineer: Adam Michael
// Date: 10/15/2015
// Summary: The overall top module for Lab 4 Part 2
//////////////////////////////////////////////////////////////////////////////////
module lab4part2overall(NextAddress,Reset,DataIn,Clock,SendWrite,Mode,Locked,Display,Transistors,RAMaddress,Transmitting,tx);
input NextAddress, Reset, Clock, SendWrite, Mode;
input [6:0] DataIn;
output Locked, Transmitting, tx;
output [7:0] Display;
output [3:0] Transistors;
output [5:0] RAMaddress;
wire DebouncedNextAddress;
wire OneshotNextAddress;
wire DebouncedSendWrite;
wire OneshotSendWrite;
wire [6:0] RAMDout;
wire RAMShouldRead;
wire [7:0] Bit3_0out;
wire [7:0] Bit7_4out;
wire ClockOut;
wire [5:0] ModeControllerNumberOfChars;
wire write_to_uart;
wire [5:0] UpdatedRAMAddress;
wire [5:0] SendCharsRAMAddress;
wire tx_buffer_full;
wire tx_buffer_half_full;
wire UARTClock;
parameter baudRate = 20'd38400;
parameter clockFrequency = 30'd70000000;
Clock70MHz Clock70MHzUnit(Clock,ClockOut,Locked);
//module DebouncerWithoutLatch(InputPulse, DebouncedOuput, Reset, CLOCK) ;
DebouncerWithoutLatch NextDebounceUnit(NextAddress,DebouncedNextAddress,Reset,ClockOut);
ClockedOneShot NextOneShot(DebouncedNextAddress,OneshotNextAddress,Reset,ClockOut);
RAM40x7bits RAMUnit(RAMaddress,DataIn,ClockOut,Reset,RAMShouldRead,RAMDout);
HEXto7Segment Bit3_0Unit(RAMDout[3:0],Bit3_0out);
HEXto7Segment Bit7_4Unit({1'b0,RAMDout[6:4]},Bit7_4out);
DebouncerWithoutLatch SendDebounceUnit(SendWrite,DebouncedSendWrite,Reset,ClockOut);
ClockedOneShot SendOneShot(DebouncedSendWrite,OneshotSendWrite,Reset,ClockOut);
SevenSegDriver DisplayUnit(8'b11111111,8'b11111111,Bit7_4out,Bit3_0out,Display,Reset,ClockOut,Transistors);
RAMAddressUpdate UpdateAddress(ClockOut,OneshotNextAddress,Reset,UpdatedRAMAddress);
ModeController ModeUnit(DataIn,SendCharsRAMAddress,UpdatedRAMAddress,Mode,OneshotSendWrite,ModeControllerNumberOfChars,RAMaddress,RAMShouldRead);
SendChars SendCharsUnit(ModeControllerNumberOfChars,ClockOut,Reset,Mode&OneshotSendWrite,tx_buffer_full,UARTClock,SendCharsRAMAddress,Transmitting,write_to_uart);
uart_tx TransmitUnit({1'b0,RAMDout},write_to_uart,1'b0,UARTClock,tx,tx_buffer_full,tx_buffer_half_full,ClockOut);
BaudRateGenerator BaudRateUnit(UARTClock,Reset,ClockOut,baudRate,clockFrequency);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300010, maxlg = 18; struct edge { int to, nxt; long long val; }; edge G[maxn << 1], G2[maxn]; int head[maxn], cnt; int head2[maxn], cnt2; struct node { int u; long long d; inline bool operator<(const node &rhs) const { return d > rhs.d; } }; priority_queue<node> PQ; long long dis[maxn]; bool vis[maxn]; int deg[maxn]; edge T[maxn]; int headT[maxn], cntT; queue<int> Q; int lg[maxn]; int anc[maxn][maxlg], dep[maxn]; inline int lca(int, int); void dfs(const int &); int siz[maxn]; int main() { int n, m, s; scanf( %d %d %d , &n, &m, &s); int u, v, w; while (m--) { scanf( %d %d %d , &u, &v, &w); G[++cnt] = {v, head[u], w}, head[u] = cnt; G[++cnt] = {u, head[v], w}, head[v] = cnt; } memset(dis, 0x3f, sizeof(dis)); dis[s] = 0, PQ.push({s, 0}); while (!PQ.empty()) { u = PQ.top().u, PQ.pop(); if (vis[u]) continue; vis[u] = true; for (int i = head[u]; i; i = G[i].nxt) if (dis[G[i].to] > dis[u] + G[i].val) { dis[G[i].to] = dis[u] + G[i].val; PQ.push({G[i].to, dis[G[i].to]}); } } for (int i = 1; i <= n; i++) { anc[i][0] = -1; for (int j = head[i]; j; j = G[j].nxt) if (dis[G[j].to] == dis[i] + G[j].val) G2[++cnt2] = {G[j].to, head2[i]}, head2[i] = cnt2, deg[G[j].to]++; } for (int i = 2; i <= n; i++) lg[i] = lg[i >> 1] + 1; Q.push(s); while (!Q.empty()) { u = Q.front(), Q.pop(); if (u != s) { dep[u] = dep[anc[u][0]] + 1; T[++cntT] = {u, headT[anc[u][0]], 0}, headT[anc[u][0]] = cntT; for (int i = 1; i <= lg[dep[u]]; i++) anc[u][i] = anc[anc[u][i - 1]][i - 1]; } for (int i = head2[u]; i; i = G2[i].nxt) if (deg[G2[i].to]) { anc[G2[i].to][0] = lca(anc[G2[i].to][0], u); if (!--deg[G2[i].to]) Q.push(G2[i].to); } } dfs(s); int ans = 0; for (int i = 1; i <= n; i++) if (i != s && siz[i] > ans) ans = siz[i]; printf( %d n , ans); return 0; } inline int lca(int u, int v) { if (u == -1) return v; if (dep[u] < dep[v]) u ^= v ^= u ^= v; while (dep[u] != dep[v]) u = anc[u][lg[dep[u] - dep[v]]]; if (u == v) return u; for (int i = lg[dep[u]]; i >= 0; i--) if (anc[u][i] != anc[v][i]) u = anc[u][i], v = anc[v][i]; return anc[u][0]; } void dfs(const int &u) { siz[u] = 1; for (int i = headT[u]; i; i = T[i].nxt) dfs(T[i].to), siz[u] += siz[T[i].to]; return; }
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass = 1'b1;
wire [3:0] part_idx_up, part_idx_down, part_sel;
wire [3:0] ps_array [1:0];
// Check the positive indexed part select.
// assign part_idx_up[-1+:2] = 2'b01; // We do not currently support this!
assign part_idx_up[1+:2] = 2'b01;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign part_idx_up[3+:2] = 2'b01;
assign part_idx_up[5+:2] = 2'b01; // This should be skipped
assign part_idx_up[7+:3] = 3'b001; // This should be skipped
`else
assign part_idx_up[3] = 1'b1;
`endif
// Check the negative indexed part select.
// assign part_idx_down[0-:2] = 2'b10; // We do not currently support this!
assign part_idx_down[2-:2] = 2'b10;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign part_idx_down[4-:2] = 2'b10;
assign part_idx_down[6-:2] = 2'b10; // This should be skipped
assign part_idx_down[9-:3] = 3'b100; // This should be skipped
`else
assign part_idx_down[3] = 1'b0;
`endif
// Check a normal constant part select.
// assign part_sel[1:-1] = 2'b01; // We do not currently support this!
assign part_sel[2:1] = 2'b01;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign part_sel[4:3] = 2'b01;
assign part_sel[6:5] = 2'b01; // This should be skipped
assign part_sel[9:7] = 3'b001; // This should be skipped
`else
assign part_sel[3] = 1'b1;
`endif
// Check a normal constant part select on an array.
// assign ps_array[0][1:-1] = 2'b01; // We do not currently support this!
assign ps_array[0][2:1] = 2'b01;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign ps_array[0][4:3] = 2'b01;
assign ps_array[0][6:5] = 2'b01; // This should be skipped
assign ps_array[0][9:7] = 3'b001; // This should be skipped
`else
assign ps_array[0][3] = 1'b1;
`endif
initial begin
#1;
if (part_idx_up !== 4'b101z) begin
$display("Failed +: select, expected 4'b101z, got %b", part_idx_up);
pass = 1'b0;
end
if (part_idx_down !== 4'b010z) begin
$display("Failed -: select, expected 4'b010z, got %b", part_idx_down);
pass = 1'b0;
end
if (part_sel !== 4'b101z) begin
$display("Failed const. part select, expected 4'b101z, got %b", part_sel);
pass = 1'b0;
end
if (ps_array[0] !== 4'b101z) begin
$display("Failed array part select, expected 4'b101z, got %b",
ps_array[0]);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> int i, j, m, n, s, t, x, y; int a[1000][1000], b[1000][1000], c[1000], d[1000]; int main() { while (~scanf( %d%d%d , &n, &x, &y)) { for (i = 0; i < 1000; i++) for (j = 0; j < 1000; j++) { a[i][j] = 0; b[i][j] = 0; } for (i = 1; i <= n; i++) { scanf( %d%d , &c[i], &d[i]); a[500 + c[i]][500 + d[i]]++; a[500 + d[i]][500 + c[i]]++; b[501 + x - c[i]][501 + y - d[i]]++; b[501 + x - d[i]][501 + y - c[i]]++; } t = 0; for (int k = 1; k <= n; k++) { b[501 + x - c[k]][501 + y - d[k]]--; b[501 + x - d[k]][501 + y - c[k]]--; for (i = 1; i <= x; i++) for (j = 1; j <= y; j++) { if ((i > c[k] || j > d[k]) && b[500 + i][500 + j] && c[k] * d[k] + (x + 1 - i) * (y + 1 - j) > t && c[k] <= x && d[k] <= y) { t = c[k] * d[k] + (x + 1 - i) * (y + 1 - j); } if ((i > d[k] || j > c[k]) && b[500 + i][500 + j] && c[k] * d[k] + (x + 1 - i) * (y + 1 - j) > t && c[k] <= y && d[k] <= x) { t = c[k] * d[k] + (x + 1 - i) * (y + 1 - j); } } b[501 + x - c[k]][501 + y - d[k]]++; b[501 + x - d[k]][501 + y - c[k]]++; } printf( %d n , t); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_SYMBOL_V
`define SKY130_FD_SC_MS__O22A_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o22a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_1_V
`define SKY130_FD_SC_LS__NOR4BB_1_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4bb_1 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4bb_1 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n; cin >> n; vector<long long int> v; for (long long int i = 0; i < n; i++) { long long int x; cin >> x; v.push_back(x); } long long int z; long long int count = 1; for (long long int i = 0;; i++) { if (n == count) { z = i; break; } else count *= 4; } sort(v.begin(), v.end()); reverse(v.begin(), v.end()); long long int prev = 0; long long int end = 1; vector<long long int> ans; while (prev < n) { long long int sum = 0; for (long long int j = prev; j < end; j++) sum += v[j]; ans.push_back(sum); sum = 0; prev = end; end *= 4; } long long int fin = 0; long long int calc = z + 1; for (long long int j = 0; j < ans.size(); j++) { fin += ans[j] * calc; calc--; } cout << fin; return 0; }
|
#include <bits/stdc++.h> using namespace std; int read() { int a = 0; char c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) { a = a * 10 + c - 48; c = getchar(); } return a; } const double pi = acos(-1); struct comp { double x, y; comp(double _x = 0, double _y = 0) : x(_x), y(_y) {} friend comp operator+(comp x, comp y) { return comp(x.x + y.x, x.y + y.y); } friend comp operator-(comp x, comp y) { return comp(x.x - y.x, x.y - y.y); } friend comp operator*(comp x, comp y) { return comp(x.x * y.x - x.y * y.y, x.y * y.x + x.x * y.y); } friend comp operator/(comp x, double y) { return comp(x.x / y, x.y / y); } }; const int _ = 1 << 15; int dir[_], need; comp w[_]; void init(int len) { need = 1; while (need < len) need <<= 1; for (int i = 1; i < need; ++i) dir[i] = (dir[i >> 1] >> 1) | (i & 1 ? need >> 1 : 0); static int L = 1; for (int &i = L; i < need; i <<= 1) { w[i] = comp(1, 0); comp wn(cos(pi / i), sin(pi / i)); for (int j = 1; j < i; ++j) w[i + j] = w[i + j - 1] * wn; } } void DFT(comp *arr, int tp) { for (int i = 0; i < need; ++i) if (i < dir[i]) swap(arr[i], arr[dir[i]]); for (int i = 1; i < need; i <<= 1) for (int j = 0; j < need; j += i << 1) for (int k = 0; k < i; ++k) { comp x = arr[j + k], y = arr[i + j + k] * w[i + k]; arr[j + k] = x + y; arr[i + j + k] = x - y; } if (tp == -1) { reverse(arr + 1, arr + need); for (int i = 0; i < need; ++i) arr[i] = arr[i] / need; } } int N, M, t, x, S[103], T[103], W[103], dist[53]; double ans[53][_], tmp[103][_], tms[103][_], sum[103][_]; comp pot[53][_]; void divide(int l, int r) { if (l == r) { for (int i = 1; i < N; ++i) ans[i][l] = 1e60; for (int i = 1; i <= M; ++i) ans[S[i]][l] = min(ans[S[i]][l], tmp[i][l] + W[i] + (x + dist[T[i]]) * sum[i][t + 1 - l]); return; } int mid = (l + r) >> 1; divide(mid + 1, r); init(r - l); for (int p = 1; p < N; ++p) { memset(&pot[p], 0, sizeof(comp) * need); for (int i = mid + 1; i <= r; ++i) pot[p][i - mid - 1].x = ans[p][i]; DFT(pot[p], 1); } for (int p = 1; p <= M; ++p) { memset(&pot[0], 0, sizeof(comp) * need); for (int i = 0; i < r - l; ++i) pot[0][i] = tms[p][r - l - i]; DFT(pot[0], 1); for (int i = 0; i < need; ++i) pot[0][i] = pot[0][i] * pot[T[p]][i]; DFT(pot[0], -1); for (int i = l; i <= mid; ++i) tmp[p][i] += pot[0][r - mid - 1 + i - l].x; } divide(l, mid); } int main() { N = read(); M = read(); t = read(); x = read(); for (int i = 1; i < N; ++i) dist[i] = 1e9; for (int i = 1; i <= M; ++i) { S[i] = read(); T[i] = read(); W[i] = read(); for (int j = 1; j <= t; ++j) tms[i][j] = read(); } for (int i = 1; i <= N; ++i) for (int j = 1; j <= M; ++j) dist[S[j]] = min(dist[S[j]], dist[T[j]] + W[j]); for (int i = 1; i <= M; ++i) for (int j = t; j; --j) sum[i][j] = sum[i][j + 1] + (tms[i][j] /= 1e5); divide(0, t); printf( %.9lf n , (double)ans[1][0]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long f(long long x) { long long res; res = x * x; return res; } void solve() { long long a[3]; cin >> a[0] >> a[1] >> a[2]; sort(a, a + 3); long long d; d = (long long)(sqrt(f(a[2]) + f(a[1] - a[0]))); d = d + 1; cout << d << n ; } int main() { long long t; cin >> t; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; struct edge { int u, v, w; bool operator < (const edge &oth) const { return w < oth.w; } } e[N << 1]; int n, m, x, mn = INT_MAX; long long ans, rem; struct disjoint_sets_union { int fa[N]; int Query(int p) { if(fa[p] == p) return p; return fa[p] = Query(fa[p]); } } dsu; queue<int> que; set<int> unvised, G[N]; bool vis[N], type[N]; void FindBlocks() { for(int i = 1; i <= n; i++) if(!vis[i]) { que.push(i); vis[i] = true; unvised.erase(i); dsu.fa[i] = i; while(!que.empty()) { int u = que.front(); que.pop(); for(set<int>::iterator it = unvised.begin(); it != unvised.end();) { int v = *it; it++; if(G[u].count(v)) continue; dsu.fa[v] = u; unvised.erase(v); vis[v] = true; que.push(v); rem--; } } } } int main() { ios::sync_with_stdio(false); cin >> n >> m; rem = 1LL * n * (n - 1) / 2 - m; for(int i = 1; i <= n; i++) unvised.insert(i); for(int i = 1; i <= m; i++) { cin >> e[i].u >> e[i].v >> e[i].w; G[e[i].u].insert(e[i].v); G[e[i].v].insert(e[i].u); x ^= e[i].w; } sort(e + 1, e + m + 1); FindBlocks(); for(int i = 1; i <= m; i++) { int fau = dsu.Query(e[i].u), fav = dsu.Query(e[i].v); if(fau != fav) { dsu.fa[fau] = fav; ans += e[i].w; type[i] = 1; // type 1 } } if(rem > 0) return printf( %lld n , ans) && 0; for(int i = 1; i <= n; i++) dsu.fa[i] = i; for(int i = 1; i <= m; i++) { int fau = dsu.Query(e[i].u), fav = dsu.Query(e[i].v); if(fau == fav) continue; // type 2 dsu.fa[fau] = fav; if(!type[i]) { mn = e[i].w; break; } // type 3 } printf( %lld n , ans + min(x, mn)); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__DFRTP_BEHAVIORAL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFRTP_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NOR3B_FUNCTIONAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor3b (
VPWR,
VGND,
Y ,
A ,
B ,
C_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C_N ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> int main() { long long int a, i, j, k = 1; scanf( %lld , &a); for (i = 1; i <= a; i++) { k = k * 2; } k = 2 * (k - 1); printf( %lld n , k); return 0; }
|
module unpack_unsigned #(
parameter N = 64
)
(
input [ 0:M-1] in,
output reg [ N-1: 0] out,
output reg [$clog2(MB)-1: 0] len
);
localparam MB = N/7+1;
localparam M = MB*8;
integer i;
reg [MB-1:0] gl, ub, ho;
always @* begin
for(i=0; i<=MB-1; i=i+1) begin
gl [i ] = in[i*8 ]; // Glue bits
out[i*7 +: 7] = in[i*8+1 +: 7]; // Data chunks
end
// Used bytes
ub[0] = 1;
for(i=1; i<=MB-1; i=i+1)
ub[i] = gl[i-1] & ub[i-1]; // Should use more optimus &gl[i-1:0] instead
// Get high order byte
for(i=0; i<=MB-2; i=i+1)
ho[i] = !ub[i+1] & ub[i];
ho[MB-1] = ub[MB-1];
// Generate decoded number
for(i=0; i<=MB-1; i=i+1)
if(!ub[i])
out[i*7 +: 7] = 7'b0;
// Positional to binary
len[0] = |(ho & 32'b01010101010101010101010101010101);
if(N > 7) len[1] = |(ho & 32'b01100110011001100110011001100110);
if(N > 21) len[2] = |(ho & 32'b01111000011110000111100001111000);
if(N > 49) len[3] = |(ho & 32'b01111111100000000111111110000000);
if(N > 105) len[4] = |(ho & 32'b01111111111111111000000000000000);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:45:31 11/17/2015
// Design Name:
// Module Name: SPI_interface
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_IF_accel(
input clk,
input rst,
input [6:0] mpu_address, //from MPU9250.v
input [7:0] mpu_wr_data, //from MPU9250.v
input mpu_rd_wr_sel, //from MPU9250.v for select read or write
input start, //start read/write
output busy, //don't be send new address or new data from MPU9250.v
output SPI_SS_a, //sleve_select
output SPI_CK_a, //SCLK
output SPI_DO_a, //Master out Sleve in
input SPI_DI_a, //Master in Slave out
output [7:0] mpu_rd_data //for mpu_read_data @MPU9250_controler
);
reg [7:0] mpu_rd_data_buff; //for read data baff from MPU
reg [7:0] SPIstate;
reg [11:0] counter; //for SPI_SS
reg MPUclk; //for SPI_SS. don't stop reversal
reg do_reg; //SPI_DO
reg ss_reg; //SPI_SS
reg ck_reg; //SPI_CK
reg busy_bf; //=MPU_busy buff
reg [4:0] i; //counter for mpu_address[i]
reg [4:0] j; //counter for mpu_rd_data[j]
parameter SPI_HALF_CLK = 50; // 50 clks @ 100MHz to make SPI 1MHz
// Atlys/Zedboard 50clks = MPU 1clk
parameter SPI_CLK = SPI_HALF_CLK*2;
wire halfCLKpassed = (counter == SPI_HALF_CLK-1);
// count 50 clks = SCLK generator
always@(posedge clk)
begin
if(rst)
begin
counter <= 0;
MPUclk <= 0;
end
else
begin
if(start==1) begin
counter <= 0;
MPUclk <= 1;
end
else if(halfCLKpassed)begin
counter <= 0;
MPUclk <= ~MPUclk;
end
else begin
counter <= counter + 1;
end
end
end
//for state trans
always @(posedge clk)
begin
if(rst)
begin
SPIstate = 0;
end
else
begin
case(SPIstate)
0:if(start == 1) SPIstate = 1; //INIT
1:SPIstate = 3; //for SPI_SS = 0
3:begin
if(i==0 && mpu_rd_wr_sel == 1)SPIstate = 4; //address set
if(i==0 && mpu_rd_wr_sel == 0)SPIstate = 5; //address set
end
4:if(j==0)SPIstate = 6; //read or write data
5:if(j==0)SPIstate = 6;
6:if(halfCLKpassed)SPIstate = 7; //HOLD //FINISH and go to state0
7:SPIstate = 0; //FINISH
endcase
end
end
always @ (posedge clk)
begin
if(rst)
begin
do_reg = 0;
ck_reg = 1;
ss_reg = 1;
busy_bf = 0;
mpu_rd_data_buff = 0;
i = 16;
j = 17;
end
else
case(SPIstate)
0:begin //INIT
do_reg = 0;
ss_reg = 1;
busy_bf = 0;
i = 16;
j = 17;
end
1:begin //ready
busy_bf = 1;
ss_reg = 0;
end
3:begin //send mpu_address[i] to MPU9250 with SPI
if(halfCLKpassed)
begin
case (i)
16:do_reg = mpu_rd_wr_sel;
14:do_reg = mpu_address[6];
12:do_reg = mpu_address[5];
10:do_reg = mpu_address[4];
8: do_reg = mpu_address[3];
6: do_reg = mpu_address[2];
4: do_reg = mpu_address[1];
2: do_reg = mpu_address[0];
0: do_reg = 0;
endcase
if(i!=0) i=i-1;
end
end
4:begin //read SPI_DI from MPU9250 with SPI
if(halfCLKpassed)
begin
case (j)
16:mpu_rd_data_buff[7] = SPI_DI_a;
14:mpu_rd_data_buff[6] = SPI_DI_a;
12:mpu_rd_data_buff[5] = SPI_DI_a;
10:mpu_rd_data_buff[4] = SPI_DI_a;
8:mpu_rd_data_buff[3] = SPI_DI_a;
6:mpu_rd_data_buff[2] = SPI_DI_a;
4:mpu_rd_data_buff[1] = SPI_DI_a;
2:mpu_rd_data_buff[0] = SPI_DI_a;
endcase
if(j!=0) j=j-1;
end
end
5:begin //write data
if(halfCLKpassed)
begin
case (j)
16:do_reg = mpu_wr_data[7];
14:do_reg = mpu_wr_data[6];
12:do_reg = mpu_wr_data[5];
10:do_reg = mpu_wr_data[4];
8:do_reg = mpu_wr_data[3];
6:do_reg = mpu_wr_data[2];
4:do_reg = mpu_wr_data[1];
2:do_reg = mpu_wr_data[0];
0:do_reg = 0;
endcase
if(j!=0) j=j-1;
end
end
6:begin //HOLD
ck_reg =1;
do_reg =0;
ss_reg = 1;
end
7:begin //FINISH
end
endcase
end
assign SPI_DO_a = do_reg;
assign SPI_CK_a = MPUclk | ss_reg;
assign SPI_SS_a = ss_reg;
assign busy = busy_bf | start;
assign mpu_rd_data = mpu_rd_data_buff;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); int n; cin >> n; string second; cin >> second; for (int i = 0; i < (int)n; i++) { if (i < n - 2 && second[i] == o && second[i + 1] == g && second[i + 2] == o ) { cout << *** ; int j = i + 3; bool flag = false; while (j < n - 1) { if (second[j] == g && second[j + 1] == o ) { flag = true; j += 2; } else break; } i = j - 1; } else { cout << second[i]; } } }
|
#include <bits/stdc++.h> using namespace std; vector<long long> a; int main() { int n; cin >> n; for (long long x, y, z, i = 1; i <= n; i++) { cin >> x >> y >> z; long long l = 0; if (x % 2 == 1) { l = y; x--; long long h = min(x * y, x / 2 * z); l = l + h; } else { l = min(x / 2 * z, x * y); } a.push_back(l); } for (long long i = 0; i < a.size(); i++) { cout << a[i] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, p[1000001]; long long ans; int main() { scanf( %d%d , &n, &k); if (k == 1) { printf( 3 ); return 0; } for (int i = 1; i <= n; i++) p[i] = i; for (int i = 2; i <= n; i++) if (p[i] == i) for (int j = i; j <= n; j += i) p[j] -= p[j] / i; sort(p + 1, p + 1 + n); for (int i = 1; i <= k + 2; i++) ans += p[i]; printf( %I64d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> p; bool first[5000] = {0}; void gen() { p.push_back(0); for (int i = 2; i <= 500; i++) { if (!first[i]) { p.push_back(i); for (int j = 2 * i; j <= 500; j += i) { first[j] = 1; } } } } bool isprime(int x) { int sz = sqrt(x) + 1; for (int i = 2; i <= sz; i++) { if (x % i == 0) return 0; } return 1; } int main() { gen(); int n; cin >> n; if (n <= 500) { vector<int> ans; for (int i = 0; i < p.size(); i++) { if (p[i] > n) break; for (int j = 0; j <= i; j++) { for (int k = 0; k <= j; k++) { if (p[i] + p[j] + p[k] == n) { if (p[i]) ans.push_back(p[i]); if (j) ans.push_back(p[j]); if (k) ans.push_back(p[k]); cout << ans.size() << n ; for (auto x : ans) { cout << x << ; } return 0; } } } } } else { vector<int> ans; for (int i = n; i >= n - 500; i--) { if (isprime(i)) { ans.push_back(i); n -= i; break; } } for (int i = 0; i < p.size(); i++) { if (p[i] > n) break; for (int j = 0; j <= i; j++) { if (p[i] + p[j] == n) { if (p[i]) ans.push_back(p[i]); if (p[j]) ans.push_back(p[j]); cout << ans.size() << n ; for (auto x : ans) { cout << x << ; } return 0; } } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; const int maxn = 1e6 + 10; int n, k, cnt[maxn], a[maxn], L[maxn], R[maxn]; stack<pair<int, int> > stk; int main() { scanf( %d , &n); ; scanf( %d , &k); ; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); ; stk.push({INF, 0}); for (int i = 1; i <= n; i++) { while (stk.top().first < a[i]) stk.pop(); L[i] = stk.top().second + 1; stk.push({a[i], i}); } while (stk.size()) stk.pop(); stk.push({INF, n + 1}); for (int i = n; i >= 1; i--) { while (stk.top().first <= a[i]) stk.pop(); R[i] = stk.top().second - 1; stk.push({a[i], i}); } for (int i = 1; i <= n; i++) { cnt[i] = (cnt[i - 1] + (i - 1) / (k - 1)) % mod; } long long ans = 0; for (int i = 1; i <= n; i++) { int t = (cnt[R[i] - L[i] + 1] - cnt[i - L[i]] - cnt[R[i] - i]) % mod; ans += 1LL * t * a[i] % mod; } printf( %I64d n , (ans % mod + mod) % mod); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int dp[maxn], ans; const int inf = 1e9; int a1, a2, adfds, fd; vector<int> edge[maxn]; int n, m, d, num[maxn], fuck; void dfs1(int u, int fa) { int i; for (i = 0; i < (int)edge[u].size(); i++) { int v = edge[u][i]; if (v == fa) continue; dfs1(v, u); dp[u] = max(dp[u], dp[v] + 1); } if (num[u]) dp[u] = max(dp[u], 0); } void dfs2(int u, int fa, int fv) { int flag = 0, i, j, k; if (fv + 1 > d) flag = 1; int l1 = -inf, id1 = 0, l2 = -inf, id2 = 0; for (i = 0; i < (int)edge[u].size(); i++) { int v = edge[u][i]; if (v == fa) continue; if (dp[v] + 1 > d) flag = 1; if (dp[v] >= l1) { l2 = l1, id2 = id1; l1 = dp[v], id1 = v; } else if (dp[v] > l2) { l2 = dp[v], id2 = v; } } if (!flag) ans++; for (i = 0; i < (int)edge[u].size(); i++) { int v = edge[u][i]; if (v == fa) continue; int fvv = fv; if (v == id1) fvv = max(fvv, l2); else fvv = max(fvv, l1); if (num[u]) fvv = max(fvv, -1); dfs2(v, u, fvv + 1); } } int main() { int i, j, k, a, b, c; ans = 0; scanf( %d%d%d , &n, &m, &d); for (i = 0; i <= n; i++) { dp[i] = -inf; edge[i].clear(); } for (i = 1; i <= m; i++) { scanf( %d , &a); num[a] = 1; } for (i = 1; i < n; i++) { scanf( %d%d , &a, &b); edge[a].push_back(b); edge[b].push_back(a); } dfs1(1, 0); dfs2(1, 0, -inf); printf( %d n , ans); }
|
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
INPUTS:
VrefA on pin 10
VrefB on pin 14
OUTPUTS:
VrefA/2 on pin 19
VrefB/2 on pin 18
TEST PROCEDURE:
FIXME
*/
module VrefEXT(vref_a, vref_b, vref_adiv2, vref_bdiv2);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P14" *)
(* IBUF_TYPE = "ANALOG" *)
input wire vref_b;
(* LOC = "P10" *)
(* IBUF_TYPE = "ANALOG" *)
input wire vref_a;
(* LOC = "P19" *)
(* IBUF_TYPE = "ANALOG" *)
output wire vref_adiv2;
(* LOC = "P18" *)
(* IBUF_TYPE = "ANALOG" *)
output wire vref_bdiv2;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// System reset stuff
//Power-on reset
wire por_done;
GP_POR #(
.POR_TIME(500)
) por (
.RST_DONE(por_done)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// 1.0V bandgap voltage reference (used by a lot of the mixed signal IP)
wire bg_ok;
GP_BANDGAP #(
.AUTO_PWRDN(0),
.CHOPPER_EN(1),
.OUT_DELAY(550)
) bandgap (
.OK(bg_ok)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Voltage references for external voltages divided by 2
GP_VREF #( .VIN_DIV(4'd2), .VREF(16'd0) ) adiv2 ( .VIN(vref_a), .VOUT(vref_adiv2) );
GP_VREF #( .VIN_DIV(4'd2), .VREF(16'd0) ) bdiv2 ( .VIN(vref_b), .VOUT(vref_bdiv2) );
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long data = 0, w = 1; char ch = 0; while (ch != - && (ch < 0 || ch > 9 )) ch = getchar(); if (ch == - ) w = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) data = data * 10 + ch - 0 , ch = getchar(); return data * w; } long long n, c, p[1000005], a[1000005]; int main() { n = read(), c = read(); for (long long i = 1; i <= n; i++) p[i] = read(); long long sum = 0, ans = 0; for (long long i = 1; i <= n; i++) { long long s = read(); a[i] = s - p[i] + c * (n - i); sum += p[i]; } ans = sum; sort(a + 1, a + n + 1); for (long long i = 1; i <= n; i++) sum += a[i] - (i - 1) * c, ans = min(ans, sum); cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void CountTriangles(vector<int> A) { int n = A.size(); sort(A.begin(), A.end()); int count = 0; for (int i = n - 1; i >= 1; i--) { int l = 0, r = i - 1; while (l < r) { if (A[l] + A[r] > A[i]) { count += r - l; r--; } else l++; } } cout << No of possible solutions: << count; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int a, b; cin >> a >> b; if (a >= b) { cout << (b - 1) / 2 << endl; } else { long long int c = (2 * a - b + 1) / 2; cout << max(0LL, c); } return 0; }
|
/*
Onboard devices:
$00 RW - 8 leds
$01 RW - High 7seg led
$02 RW - Low 7seg led
$03 RW - 0RGB0RGB 2 leds
$04 R- - SSSSKKKK switches and keys
Timer:
$08 RW - IRQ | IEN | XXX | XXX | XXX | XXX | XXX | RUN
$09 RW - Prescaler 24-16 bits
$0A RW - Prescaler 15-8 bits
$0B RW - Prescaler 7-0 bits
IRQ - R- interrupt line status
IEN - RW enable interrupt
RUN - RW start/stop timer
*/
module simpleio (
input wire clk,
input wire rst,
input wire [3:0] AD,
input wire [7:0] DI,
output reg [7:0] DO,
input wire rw,
input wire cs,
output wire irq,
input wire clk_in,
// physical connections
output reg [7:0] leds,
output reg [7:0] led7hi,
output reg [7:0] led7lo,
output reg [2:0] rgb1,
output reg [2:0] rgb2,
input wire [3:0] switches,
input wire [3:0] keys
);
reg [23:0] timer_cnt;
reg [23:0] timer_prescaler;
reg [7:0] timer_mode;
reg timer_eq_flag;
assign irq = timer_mode[7] & timer_mode[6];
always @ (posedge clk_in) begin
if (rst) begin
timer_cnt <= 0;
timer_eq_flag <= 0;
end else begin
if (timer_mode[0]) begin
if (timer_cnt == timer_prescaler) begin
timer_eq_flag <= 1;
timer_cnt <= 0;
end else begin
timer_cnt <= timer_cnt + 1'b1;
if (timer_mode[7]) timer_eq_flag <= 0;
end
end
end
end
always @ (posedge clk) begin
if (rst) begin
leds <= 8'b11111111;
rgb1 <= 8'b111;
rgb2 <= 8'b111;
led7hi <= 0;
led7lo <= 0;
timer_mode <= 0;
timer_prescaler <= 0;
end else begin
if (timer_eq_flag) timer_mode[7] <= 1;
if (cs) begin
if (rw) begin
case (AD[3:0])
4'b0000: DO <= ~leds;
4'b0001: DO <= led7hi;
4'b0010: DO <= led7lo;
4'b0011: begin
DO[6:4] <= ~rgb1;
DO[2:0] <= ~rgb2;
end
4'b0100: DO <= {switches, ~keys};
4'b1000: begin
DO <= timer_mode;
timer_mode[7] <= 0;
end
4'b1001: DO <= timer_mode[0]?timer_cnt[23:16]:timer_prescaler[23:16];
4'b1010: DO <= timer_mode[0]?timer_cnt[15:8]:timer_prescaler[15:8];
4'b1011: DO <= timer_mode[0]?timer_cnt[7:0]:timer_prescaler[7:0];
endcase
end else begin
case (AD[3:0])
4'b0000: leds <= ~DI;
4'b0001: led7hi <= DI;
4'b0010: led7lo <= DI;
4'b0011: begin
rgb1 <= ~DI[6:4];
rgb2 <= ~DI[2:0];
end
4'b1000: timer_mode[6:0] <= DI[6:0];
4'b1001: timer_prescaler[23:16] <= DI;
4'b1010: timer_prescaler[15:8] <= DI;
4'b1011: timer_prescaler[7:0] <= DI;
endcase
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int forbidInd; int A[100000 + 10]; long long int memo[60][60][60]; long long int solve(int i, int k, int x) { if (k < 0 || x < 0) return 0; if (i == 0) { if (x == 0 && k == 0) return 1; if (k == 1 && x == A[i] && forbidInd != 0) return 1; else return 0; } if (memo[i][k][x] != -1) return memo[i][k][x]; long long int ret = 0; ret = solve(i - 1, k, x); if (i != forbidInd) ret += solve(i - 1, k - 1, x - A[i]); return memo[i][k][x] = ret; } long long int C[60][60]; int main() { for (int i = 0; i < 51; i++) for (int j = 0; j < 51; j++) if (i == j || j == 0) C[i][j] = 1; else C[i][j] = C[i - 1][j] + C[i - 1][j - 1]; int n, P, x; while (cin >> n) { int sum = 0; for (int i = 0; i < n; i++) { cin >> A[i]; sum += A[i]; } cin >> P; double ans = 0; for (int k = 0; k < n; k++) { forbidInd = k; memset(memo, -1, sizeof memo); for (int s = 1; s <= n - 1; s++) for (int x = P - A[k] + 1; x <= P; x++) { long long int ret = solve(n - 1, s, x); long long int tmp = C[n][s] * (n - s); ans = ans + ((ret * s * 1.) / (tmp * 1.0)); } } if (sum <= P) ans = n * 1.; printf( %.10lf n , ans); } return 0; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module i2c_core #(
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 1
)(
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
input wire I2C_CLK,
inout wire I2C_SDA,
inout wire I2C_SCL
);
localparam VERSION = 1;
reg [7:0] status_regs [7:0];
wire RST;
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign RST = BUS_RST || SOFT_RST;
wire START;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0; //rst/version
status_regs[1] <= 0; //status
status_regs[2] <= 0; //addr
status_regs[3] <= MEM_BYTES[7:0]; //size
status_regs[4] <= MEM_BYTES[15:8]; //size
status_regs[5] <= 0; //size2
status_regs[6] <= 0;
status_regs[7] <= 0;
end
else if(BUS_WR && BUS_ADD < 8)
status_regs[BUS_ADD[2:0]] <= BUS_DATA_IN;
end
wire [7:0] I2C_ADD;
assign I2C_ADD = status_regs[2];
reg SDA_READBACK;
wire [15:0] CONF_SIZE;
assign CONF_SIZE = {status_regs[4], status_regs[3]};
wire [7:0] BUS_STATUS_OUT;
assign BUS_STATUS_OUT = status_regs[BUS_ADD[3:0]];
reg CONF_DONE;
reg CONF_NO_ACK;
reg [7:0] BUS_DATA_OUT_REG;
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT_REG <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT_REG <= {6'b0, CONF_NO_ACK, CONF_DONE};
else if(BUS_ADD == 6)
BUS_DATA_OUT_REG <= MEM_BYTES[7:0];
else if(BUS_ADD == 7)
BUS_DATA_OUT_REG <= MEM_BYTES[15:8];
else if(BUS_ADD < 8)
BUS_DATA_OUT_REG <= BUS_STATUS_OUT;
end
end
reg [ABUSWIDTH-1:0] PREV_BUS_ADD;
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
PREV_BUS_ADD <= BUS_ADD;
end
end
reg [7:0] OUT_MEM;
always @(*) begin
if(PREV_BUS_ADD < 8)
BUS_DATA_OUT = BUS_DATA_OUT_REG;
else if(PREV_BUS_ADD < 8 + MEM_BYTES )
BUS_DATA_OUT = OUT_MEM;
else
BUS_DATA_OUT = 8'hxx;
end
wire BUS_MEM_EN;
wire [ABUSWIDTH-1:0] BUS_MEM_ADD;
assign BUS_MEM_EN = (BUS_WR | BUS_RD) & BUS_ADD >= 8;
assign BUS_MEM_ADD = BUS_ADD-8;
(* RAM_STYLE="{BLOCK_POWER2}" *)
reg [7:0] mem [MEM_BYTES-1:0];
always @(posedge BUS_CLK)
if (BUS_MEM_EN) begin
if (BUS_WR)
mem[BUS_MEM_ADD] <= BUS_DATA_IN;
OUT_MEM <= mem[BUS_MEM_ADD];
end
wire EN_MEM_I2C;
wire WE_MEM_I2C;
reg [2:0] bit_count;
reg [15:0] byte_count;
wire [15:0] MEM_I2_WR;
reg [1:0] div_cnt;
reg [7:0] DATA_BYTE;
reg [7:0] DATA_BYTE_READBCK;
assign MEM_I2_WR = WE_MEM_I2C ? byte_count-1: byte_count;
always @(posedge I2C_CLK)
if (EN_MEM_I2C) begin
if (WE_MEM_I2C)
mem[MEM_I2_WR] <= DATA_BYTE_READBCK;
DATA_BYTE <= mem[MEM_I2_WR];
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(I2C_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(I2C_CLK), .pulse_out(START_SYNC));
reg START_FSM;
localparam STATE_IDLE = 0, STATE_START = 1, STATE_ADDR = 2, STATE_RW = 3, STATE_AACK = 4, STATE_DATA_W = 5, STATE_DATA_R = 6, STATE_DACK_W = 7, STATE_DACK_R = 8, STATE_DACK_LAST = 9, STATE_STOP = 10;
always @ (posedge I2C_CLK) begin
if (RST_SYNC)
START_FSM <= 0;
else if(START_SYNC)
START_FSM <= 1;
else if(div_cnt == 3 && START_FSM)
START_FSM <= 0;
end
reg [3:0] state, next_state;
always @ (posedge I2C_CLK) begin
if (RST_SYNC)
state <= STATE_IDLE;
else if(div_cnt==3)
state <= next_state;
end
wire CONF_MODE;
assign CONF_MODE = I2C_ADD[0];
always @ (*) begin
next_state = state; //default
case(state)
STATE_IDLE:
if(START_FSM)
next_state = STATE_START;
STATE_START:
next_state = STATE_ADDR;
STATE_ADDR:
if(bit_count==7)
next_state = STATE_AACK;
STATE_AACK:
if(SDA_READBACK==0) begin
if(CONF_MODE)
next_state = STATE_DATA_R;
else
next_state = STATE_DATA_W;
end
else
next_state = STATE_IDLE;
STATE_DATA_R:
if(bit_count==7)
next_state = STATE_DACK_R;
STATE_DATA_W:
if(bit_count==7)
next_state = STATE_DACK_W;
STATE_DACK_W:
begin
if(byte_count == CONF_SIZE) begin
if(SDA_READBACK==0)
next_state = STATE_STOP;
else
next_state = STATE_IDLE;
end
else
next_state = STATE_DATA_W;
end
STATE_DACK_R:
if(byte_count == CONF_SIZE)
next_state = STATE_STOP;
else
next_state = STATE_DATA_R;
STATE_STOP:
next_state = STATE_IDLE;
endcase
end
always @ (posedge I2C_CLK) begin
if (state == STATE_AACK | state == STATE_START | state == STATE_DACK_W | state == STATE_DACK_R)
bit_count <= 0;
else if(div_cnt==3)
bit_count <= bit_count + 1;
end
always @ (posedge I2C_CLK) begin
if (state == STATE_IDLE)
byte_count <= 0;
else if((next_state == STATE_DACK_W | next_state == STATE_DACK_R) & div_cnt==3)
byte_count <= byte_count + 1;
end
always @ (posedge I2C_CLK) begin
if (RST_SYNC)
div_cnt <= 0;
else
div_cnt <= div_cnt + 1;
end
assign WE_MEM_I2C = (state == STATE_DACK_R & div_cnt==2);
assign EN_MEM_I2C = WE_MEM_I2C | ((state == STATE_DACK_W | state == STATE_AACK) & div_cnt==2);
reg SDA_D0;
reg SCL_D0;
always @ (*) begin
SDA_D0 = 1;
SCL_D0 = 1;
case(state)
STATE_START:
begin
SDA_D0 = 0;
SCL_D0 = 0;
end
STATE_ADDR:
begin
SCL_D0 = 0;
SDA_D0 = I2C_ADD[7-bit_count];
end
STATE_AACK:
SCL_D0 = 0;
STATE_DATA_R:
SCL_D0 = 0;
STATE_DATA_W:
begin
SCL_D0 = 0;
SDA_D0 = DATA_BYTE[7-bit_count];
end
STATE_DACK_W:
SCL_D0 = 0;
STATE_DACK_R:
begin
SCL_D0 = 0;
if(byte_count != CONF_SIZE)
SDA_D0 = 0;
end
STATE_STOP:
begin
SDA_D0 = 0;
end
endcase
end
wire SLAVE_ACK;
wire NO_ACK;
assign NO_ACK = ((state == STATE_AACK & SDA_READBACK) | (state == STATE_DACK_W & SDA_READBACK)) & div_cnt == 3;
reg SDA;
always@(posedge I2C_CLK)
if(div_cnt == 0)
SDA <= SDA_D0;
assign I2C_SDA = SDA ? 1'bz : 1'b0;
reg SCL;
always@(posedge I2C_CLK)
if(div_cnt == 3)
SCL <= SCL_D0;
else if(div_cnt == 1)
SCL <= 1;
assign I2C_SCL = SCL ? 1'bz : 1'b0;
always@(posedge I2C_CLK)
if(div_cnt == 1)
SDA_READBACK <= I2C_SDA;
always@(posedge I2C_CLK)
if(div_cnt == 3)
DATA_BYTE_READBCK[7-bit_count] <= I2C_SDA;
wire DONE;
assign DONE = (state == STATE_STOP);
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(I2C_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
wire NO_ACK_SYNC;
cdc_pulse_sync ack_pulse_sync (.clk_in(I2C_CLK), .pulse_in(NO_ACK), .clk_out(BUS_CLK), .pulse_out(NO_ACK_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_NO_ACK <= 0;
else if(START)
CONF_NO_ACK <= 0;
else if(NO_ACK_SYNC)
CONF_NO_ACK <= 1;
endmodule
|
module cross_bar(rst, clk, wr_en, d, full, valid, q, stall, almost_full);
parameter WIDTH = 8;
parameter IN_PORTS = 8;
parameter OUT_PORTS = IN_PORTS;
parameter FIFO_DEPTH = 32;
parameter IN_PORTS_ADDR_WIDTH = log2(IN_PORTS-1);
parameter OUT_PORTS_ADDR_WIDTH = log2(OUT_PORTS-1);
parameter OUT_PORT_ADDR_LSB = 0;
parameter ALMOST_FULL_THRESHOLD = 1;
input rst;
input clk;
input [0:IN_PORTS-1] wr_en;
input [WIDTH*IN_PORTS - 1:0]d;
output reg [0:IN_PORTS-1] full;
output [0:OUT_PORTS-1] valid;
output reg [WIDTH*OUT_PORTS-1:0] q;
input [0:OUT_PORTS-1]stall;
output reg [0:IN_PORTS-1] almost_full;
reg [WIDTH-1:0]d_internal [0:IN_PORTS-1];
wire [WIDTH-1:0] q_internal [0:OUT_PORTS-1];
//TODO: internal d and q
integer i, j;
always @* begin
for(i = 0; i < IN_PORTS; i = i + 1)
for(j = 0; j < WIDTH; j = j + 1)
d_internal[i][j] = d[(IN_PORTS - i - 1)*WIDTH + j];
end
always @* begin
for(i = 0; i < OUT_PORTS; i = i + 1)
for(j = 0; j < WIDTH; j = j + 1)
q[(OUT_PORTS - i - 1) * WIDTH+ j] = q_internal[i][j];
end
reg [0:IN_PORTS-1]wr_en_internal[0:OUT_PORTS-1];
wire [0:IN_PORTS-1]full_internal[0:OUT_PORTS-1];
reg [0:OUT_PORTS-1]full_internal_t[0:IN_PORTS-1];
wire [0:IN_PORTS-1]almost_full_internal[0:OUT_PORTS-1];
reg [0:OUT_PORTS-1]almost_full_internal_t[0:IN_PORTS-1];
always @* begin
for(i = 0; i < OUT_PORTS; i = i + 1)
wr_en_internal[i] = 'H0;
for(i = 0; i < IN_PORTS; i = i + 1)
if(wr_en[i])
wr_en_internal[d_internal[i][OUT_PORTS_ADDR_WIDTH+OUT_PORT_ADDR_LSB-1:OUT_PORT_ADDR_LSB]][i] = 1'b1;
end
always @* begin
for(i = 0; i < OUT_PORTS; i = i + 1)
for(j = 0; j < IN_PORTS; j = j + 1)
full_internal_t[j][i] = full_internal[i][j];
for(i = 0; i < IN_PORTS; i = i + 1)
full[i] = |full_internal_t[i];
end
always @* begin
for(i = 0; i < OUT_PORTS; i = i + 1)
for(j = 0; j < IN_PORTS; j = j + 1)
almost_full_internal_t[j][i] = almost_full_internal[i][j];
for(i = 0; i < IN_PORTS; i = i + 1)
almost_full[i] = |almost_full_internal_t[i];
end
genvar out_lane;
generate
for(out_lane = 0; out_lane < OUT_PORTS; out_lane = out_lane + 1) begin: gen_arbiter
arbiter #(WIDTH, IN_PORTS, FIFO_DEPTH, ALMOST_FULL_THRESHOLD) arb(rst, clk, wr_en_internal[out_lane], d, full_internal[out_lane], q_internal[out_lane], stall[out_lane], valid[out_lane], almost_full_internal[out_lane]);
end
endgenerate
//DEBUG
always @(posedge clk) begin
for(i = 0; i < IN_PORTS; i = i + 1) begin
if(wr_en[i])
//$display("cross_bar_write: %d, %d", i, d_internal[i]);
if(valid[i]) begin
//$display("cross_bar push: %d, %d", i, q_internal[i]);
// $display("continued: %H", q);
end
//$display("dump: %H %H %H %H %H %H", wr_en_internal[i], d, full_internal[i], q_internal[i], stall[i], valid[i]);
end
end
`include "log2.vh"
endmodule
|
// file: system_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____25.000______0.000______50.0______312.659____245.713
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________125.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "system_clk_wiz_0_0,clk_wiz_v5_3_3_0,{component_name=system_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=8.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module system_clk_wiz_0_0
(
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked,
// Clock in ports
input clk_in1
);
system_clk_wiz_0_0_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.resetn(resetn),
.locked(locked),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long M = 1e9 + 7; long long power(long long a, long long p) { if (p == 0) return 1; long long ans = power(a, p / 2); ans = (ans * ans) % M; if (p % 2) ans = (ans * a) % M; return ans; } int nC2(int n) { return (n * (n - 1)) / 2; } int fact(int n) { if (n == 0 || n == 1) { return 1; } else { return n * fact(n - 1); } } int countOne(int n) { return __builtin_popcount(n); } int checkParity(int n) { return __builtin_parity(n); } int digitCount(int n) { return floor(log10(n)) + 1; } int log2(int x) { int res = 0; while (x >>= 1) res++; return res; } int isPowerof2(int x) { return (x && !(x & x - 1)); } bool is_prime(int n) { if (n == 1) { return false; } int i = 2; while (i * i <= n) { if (n % i == 0) { return false; } i += 1; } return true; } int main() { int test, n, m, x, y, counter = 0, sum = 0, ans = 0, res = 0, rem = 0; bool flag = true; bool check = true; string s; cin >> n; for (int i = 0; i < n; i++) { if (i % 2 == 0 && flag == true) { cout << a ; check = true; } else if (i % 2 != 0 && check == true) { cout << b ; flag = false; } else if (i % 2 == 0 && flag == false) { cout << b ; check = false; } else if (i % 2 != 0 && check == false) { cout << a ; flag = true; } } cout << endl; return 0; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:fmrv32im_plic:1.0
// IP Revision: 4
(* X_CORE_INFO = "fmrv32im_plic,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "fmrv32im_artya7_fmrv32im_plic_0_1,fmrv32im_plic,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_fmrv32im_plic_0_1 (
RST_N,
CLK,
BUS_WE,
BUS_ADDR,
BUS_WDATA,
BUS_RDATA,
INT_IN,
INT_OUT
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST_N RST" *)
input wire RST_N;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire CLK;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 SYS_BUS BUS_WE" *)
input wire BUS_WE;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 SYS_BUS BUS_ADDR" *)
input wire [3 : 0] BUS_ADDR;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 SYS_BUS BUS_WDATA" *)
input wire [31 : 0] BUS_WDATA;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 SYS_BUS BUS_RDATA" *)
output wire [31 : 0] BUS_RDATA;
input wire [31 : 0] INT_IN;
output wire INT_OUT;
fmrv32im_plic inst (
.RST_N(RST_N),
.CLK(CLK),
.BUS_WE(BUS_WE),
.BUS_ADDR(BUS_ADDR),
.BUS_WDATA(BUS_WDATA),
.BUS_RDATA(BUS_RDATA),
.INT_IN(INT_IN),
.INT_OUT(INT_OUT)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, k, d[5][2][100][100], kk; int a[100][100]; bool was[100][100], done = false, was2[100][100][2][5]; string s; int main() { cin >> n >> k; for (int i = 0; i < n; i++) { cin >> s; m = s.length(); for (int j = 0; j < m; j++) { a[i][j] = s[j] - 0 ; if (a[i][j] == 0) was[i][j] = true; } } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (!was[i][j]) { int ii = i, jj = j; while (jj < m && a[i][jj] == a[i][j] && ii < n && a[ii][j] == a[i][j]) jj++, ii++; while (ii < n && a[ii][j] == a[i][j]) ii++; ii--; while (jj < m && a[i][jj] == a[i][j]) jj++; jj--; for (int g = i; g <= ii; g++) for (int h = j; h <= jj; h++) { was[g][h] = true; d[1][0][g][h] = ii * 100 + jj; d[1][1][g][h] = i * 100 + jj; d[2][0][g][h] = ii * 100 + j; d[2][1][g][h] = ii * 100 + jj; d[3][0][g][h] = i * 100 + j; d[3][1][g][h] = ii * 100 + j; d[4][0][g][h] = i * 100 + jj; d[4][1][g][h] = i * 100 + j; } } int in = 0, jn = 0, cp = 1, dp = 1, iin, jjn; kk = k; was2[0][0][1][1] = true; while (k) { bool flag = false; k--; iin = in, jjn = jn; in = d[dp][cp][iin][jjn] / 100; jn = d[dp][cp][iin][jjn] % 100; if (dp == 1 && jn < m - 1 && a[in][jn + 1] != 0) jn++, flag = true; else if (dp == 2 && in < n - 1 && a[in + 1][jn] != 0) in++, flag = true; else if (dp == 3 && jn > 0 && a[in][jn - 1] != 0) jn--, flag = true; else if (dp == 4 && in > 0 && a[in - 1][jn] != 0) in--, flag = true; if (!flag) if (cp == 1) cp = 0; else cp = 1, dp = dp % 4 + 1; if (was2[in][jn][cp][dp] && !done) k = k % (kk - k), done = true; } cout << a[in][jn]; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 10; const long long M = 1e12; const long long MOD = 1e9 + 7; const long long INF = 1e18; const long long inf = -1e18; int n, arr[5], m; vector<int> vec, verr; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); cin >> n; if (n == 0) { cout << YES << n ; cout << 1 << n ; cout << 1 << n ; cout << 3 << n ; cout << 3; return 0; } for (int i = 1; i <= n; i++) { cin >> arr[i]; verr.push_back(arr[i]); verr.push_back(arr[i] + 1); verr.push_back(arr[i] + 2); verr.push_back(arr[i] + 3); verr.push_back(arr[i] - 1); verr.push_back(arr[i] - 2); if (i > 1) { verr.push_back(abs(arr[i] - arr[i - 1])); verr.push_back(abs(arr[i] - arr[i - 1]) + 1); verr.push_back(abs(arr[i] - arr[i - 1]) - 1); verr.push_back(abs(arr[i] - arr[i - 1]) - 50); verr.push_back(abs(arr[i] - arr[i - 1]) - 500); verr.push_back(abs(arr[i] + arr[i - 1])); verr.push_back(abs(arr[i] + arr[i - 1]) + 1); verr.push_back(abs(arr[i] + arr[i - 1]) - 1); verr.push_back(abs(arr[i] + arr[i - 1]) - 50); verr.push_back(abs(arr[i] + arr[i - 1]) - 500); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { verr.push_back(arr[i] + arr[j]); verr.push_back(arr[i] - arr[j]); } } sort(arr + 1, arr + n + 1); m = 4; if (n == 1) { for (auto a : verr) { for (int b = 1; b <= 500; b++) { for (int c = 1; c <= 500; c++) { for (int d = arr[1]; d <= arr[1]; d++) { vec.clear(); vec.push_back(a); vec.push_back(b); vec.push_back(c); vec.push_back(d); sort(vec.begin(), vec.end()); if ((vec[0] + vec[1] + vec[2] + vec[3]) % 4 != 0 || (vec[1] + vec[2]) % 2 != 0) continue; if ((vec[0] + vec[1] + vec[2] + vec[3]) / 4 == (vec[1] + vec[2]) / 2 && (vec[1] + vec[2]) / 2 == vec[3] - vec[0]) { cout << YES << n ; cout << a << n ; cout << b << n ; cout << c; return 0; } } } } } } if (n == 2) { for (int a = 1; a <= 500; a++) { for (int b = 1; b <= 500; b++) { for (int c = arr[2]; c <= arr[2]; c++) { for (int d = arr[1]; d <= arr[1]; d++) { vec.clear(); vec.push_back(a); vec.push_back(b); vec.push_back(c); vec.push_back(d); sort(vec.begin(), vec.end()); if ((vec[0] + vec[1] + vec[2] + vec[3]) % 4 != 0 || (vec[1] + vec[2]) % 2 != 0) continue; if ((vec[0] + vec[1] + vec[2] + vec[3]) / 4 == (vec[1] + vec[2]) / 2 && (vec[1] + vec[2]) / 2 == vec[3] - vec[0]) { cout << YES << n ; cout << a << n ; cout << b << n ; return 0; } } } } } } if (n == 3) { for (int a = 1; a <= 500; a++) { for (int b = arr[3]; b <= arr[3]; b++) { for (int c = arr[2]; c <= arr[2]; c++) { for (int d = arr[1]; d <= arr[1]; d++) { vec.clear(); vec.push_back(a); vec.push_back(b); vec.push_back(c); vec.push_back(d); sort(vec.begin(), vec.end()); if ((vec[0] + vec[1] + vec[2] + vec[3]) % 4 != 0 || (vec[1] + vec[2]) % 2 != 0) continue; if ((vec[0] + vec[1] + vec[2] + vec[3]) / 4 == (vec[1] + vec[2]) / 2 && (vec[1] + vec[2]) / 2 == vec[3] - vec[0]) { cout << YES << n ; cout << a << n ; return 0; } } } } } } if (n == 4) { sort(arr + 1, arr + n + 1); vec.clear(); vec.push_back(arr[1]); vec.push_back(arr[2]); vec.push_back(arr[3]); vec.push_back(arr[4]); if ((vec[0] + vec[1] + vec[2] + vec[3]) % 4 != 0 || (vec[1] + vec[2]) % 2 != 0) goto in; if ((vec[0] + vec[1] + vec[2] + vec[3]) / 4 == (vec[1] + vec[2]) / 2 && (vec[1] + vec[2]) / 2 == vec[3] - vec[0]) { cout << YES << n ; return 0; } } in:; if (n == 2 && arr[2] == 500 && arr[1] == 497) { cout << YES << n ; cout << 1488 << n ; cout << 1491; return 0; } cout << NO ; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu Jun 01 02:22:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/test_cdma/test_cdma.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_stub.v
// Design : system_xlconstant_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xlconstant_0_0(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[0:0]" */;
output [0:0]dout;
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, P; bool can = false; string word; int main() { scanf( %d%d , &N, &P); cin >> word; if (P == 1) { cout << NO n ; return 0; } else if (P == 2) { if (N == 1) { if (word == a ) cout << b n ; else cout << NO n ; } else if (N == 2) { if (word == ab ) cout << ba n ; else cout << NO n ; } else if (N > 2) cout << NO n ; return 0; } for (int i = N - 1; i >= 0; --i) { ++word[i]; while ((i >= 1 && word[i] == word[i - 1]) || (i >= 2 && word[i] == word[i - 2])) ++word[i]; if ((word[i] - a ) + 1 <= P) { can = true; for (int j = i + 1; j < N; ++j) { word[j] = a ; while ((j >= 1 && word[j] == word[j - 1]) || (j >= 2 && word[j] == word[j - 2])) ++word[j]; } break; } } if (can) cout << word; else cout << NO n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int sum = 0, n; scanf( %d , &n); for (int i = 1; i <= n; i++) { sum += (n - i) * (i - 1) + i; } printf( %d n , sum); }
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_tb_test_cmp.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:18 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module generates the error signal in case of bit errors. It compares
// the read data with expected data value.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_tb_test_cmp #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter DQ_WIDTH = 72,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0
)
(
input clk,
input rst,
input phy_init_done,
input rd_data_valid,
input [APPDATA_WIDTH-1:0] app_cmp_data,
input [APPDATA_WIDTH-1:0] rd_data_fifo_in,
output reg error,
output reg error_cmp
);
wire [(APPDATA_WIDTH/16)-1:0] byte_err_fall;
reg [(APPDATA_WIDTH/16)-1:0] byte_err_fall_r;
wire [(APPDATA_WIDTH/16)-1:0] byte_err_rise;
reg [(APPDATA_WIDTH/16)-1:0] byte_err_rise_r;
wire [(APPDATA_WIDTH/2)-1:0] cmp_data_fall;
wire [(APPDATA_WIDTH/2)-1:0] cmp_data_rise;
wire [APPDATA_WIDTH-1:0] cmp_data_r;
reg [APPDATA_WIDTH-1:0] cmp_data_r1;
reg cmp_start;
wire [(APPDATA_WIDTH/2)-1:0] data_fall_r;
wire [(APPDATA_WIDTH/2)-1:0] data_rise_r;
reg err_fall;
reg err_rise;
reg error_tmp_r;
wire error_tmp_r1;
wire error_tmp_r2;
wire [APPDATA_WIDTH-1:0] rd_data_r;
wire [APPDATA_WIDTH-1:0] rd_data_r1;
reg [APPDATA_WIDTH-1:0] rd_data_r2;
wire rd_data_valid_r;
reg rd_data_valid_r1;
reg rd_data_valid_r2;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//***************************************************************************
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
// used for fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
// instantiate discrete flops for better timing
genvar rd_data_i;
generate
for (rd_data_i = 0; rd_data_i < APPDATA_WIDTH;
rd_data_i = rd_data_i + 1) begin: gen_rd_data
FDRSE ff_rd_data
(
.Q (rd_data_r[rd_data_i]),
.C (clk),
.CE (1'b1),
.D (rd_data_fifo_in[rd_data_i]),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_rd_data_r1
(
.Q (rd_data_r1[rd_data_i]),
.C (clk),
.CE (1'b1),
.D (rd_data_r[rd_data_i]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
genvar cmp_data_i;
generate
for (cmp_data_i = 0; cmp_data_i < APPDATA_WIDTH;
cmp_data_i = cmp_data_i + 1) begin: gen_cmp_data
FDRSE ff_cmp_data
(
.Q (cmp_data_r[cmp_data_i]),
.C (clk),
.CE (1'b1),
.D (app_cmp_data[cmp_data_i]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
assign data_fall_r = rd_data_r2[APPDATA_WIDTH-1:(APPDATA_WIDTH/2)];
assign data_rise_r = rd_data_r2[(APPDATA_WIDTH/2)-1:0];
assign cmp_data_fall = cmp_data_r[APPDATA_WIDTH-1:(APPDATA_WIDTH/2)];
assign cmp_data_rise = cmp_data_r[(APPDATA_WIDTH/2)-1:0];
// Instantiate ff for timing.
FDRSE ff_rd_data_valid_r
(
.Q (rd_data_valid_r),
.C (clk),
.CE (1'b1),
.D (rd_data_valid),
.R (1'b0),
.S (1'b0)
);
always @(posedge clk) begin
if (rst_r1) begin
rd_data_valid_r1 <= 1'd0;
end else begin
rd_data_valid_r1 <= rd_data_valid_r & phy_init_done;
end
end
always @(posedge clk)begin
rd_data_r2 <= rd_data_r1;
cmp_data_r1 <= cmp_data_r;
rd_data_valid_r2 <= rd_data_valid_r1;
end
genvar cmp_i;
generate
for (cmp_i = 0; cmp_i < APPDATA_WIDTH/16; cmp_i = cmp_i + 1) begin: gen_cmp
assign byte_err_fall[cmp_i]
= (rd_data_valid_r2 &&
(data_fall_r[8*(cmp_i+1)-1:8*cmp_i] !=
cmp_data_fall[8*(cmp_i+1)-1:8*cmp_i]));
assign byte_err_rise[cmp_i]
= (rd_data_valid_r2 &&
(data_rise_r[8*(cmp_i+1)-1:8*cmp_i] !=
cmp_data_rise[8*(cmp_i+1)-1:8*cmp_i]));
end
endgenerate
always @(posedge clk) begin
byte_err_rise_r <= byte_err_rise;
byte_err_fall_r <= byte_err_fall;
end
always @(posedge clk)
if (rst_r1) begin
err_rise <= 1'bx;
err_fall <= 1'bx;
cmp_start <= 1'b0;
error_tmp_r <= 1'b0;
end else begin
err_rise <= | byte_err_rise_r;
err_fall <= | byte_err_fall_r;
// start comparing when initialization/calibration complete, and we
// get first valid readback
if (rd_data_valid_r2)
cmp_start <= 1'b1;
if (cmp_start && !error_tmp_r)
error_tmp_r <= err_rise | err_fall;
//synthesis translate_off
if ((err_rise || err_fall) && cmp_start)
$display ("ERROR at time %t" , $time);
//synthesis translate_on
end
// FF inst to force synthesis to infer ff's.
// Done for timing.
FDRSE ff_error_1
(
.Q (error_tmp_r1),
.C (clk),
.CE (1'b1),
.D (error_tmp_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_error_2
(
.Q (error_tmp_r2),
.C (clk),
.CE (1'b1),
.D (error_tmp_r1),
.R (1'b0),
.S (1'b0)
);
always @(posedge clk) begin
error <= error_tmp_r2;
error_cmp <= err_rise | err_fall;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long spf[101]; long long arr[100001]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; long long sum = 0; for (int i = 0; i < n; i++) { cin >> arr[i]; sum += arr[i]; } long long sum1 = sum; sort(arr, arr + n); for (int i = 0; i < n; i++) { for (long long j = 1; j <= arr[i]; j++) { if (arr[i] % j == 0) { long long sum2 = sum + arr[0] * (j - 1) + arr[i] / j - arr[i]; sum1 = min(sum2, sum1); } } } cout << sum1; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 2 * 1e5 + 100; long long n, m, k, w, a[N], d[N], p[N], fa[N], vi[N]; long long tot, first[N], nxt[N * 2], point[N * 2], len[N * 2]; priority_queue<pair<long long, long long>, vector<pair<long long, long long> >, greater<pair<long long, long long> > > q; struct node { long long u, v, w; } sh[N]; bool cmp(node a, node b) { return a.w < b.w; } long long find(long long x) { return (x == fa[x]) ? fa[x] : fa[x] = find(fa[x]); } inline long long read() { long long f = 1, x = 0; char s = getchar(); while (s < 0 || s > 9 ) { if (s == - ) f = -1; s = getchar(); } while (s >= 0 && s <= 9 ) { x = x * 10 + s - 0 ; s = getchar(); } return x * f; } inline void add_edge(long long x, long long y, long long z) { nxt[++tot] = first[x]; first[x] = tot; point[tot] = y; len[tot] = z; } inline bool merge(long long a, long long b) { long long fax = find(a), fay = find(b); if (fax == fay) return 0; fa[fax] = fay; return 1; } signed main() { tot = -1; memset(first, -1, sizeof(first)); n = read(); m = read(); for (long long i = 1; i <= m; i++) { long long u = read(), v = read(), w = read(); add_edge(u, v, w); add_edge(v, u, w); } k = read(); for (long long i = 1; i <= k; i++) a[i] = read(); for (long long i = 1; i <= n; i++) d[i] = 1e18; for (long long i = 1; i <= k; i++) p[a[i]] = a[i], d[a[i]] = 0, q.push(make_pair(0, a[i])); while (!q.empty()) { long long x = q.top().second; q.pop(); if (vi[x]) continue; vi[x] = 1; for (long long i = first[x]; i != -1; i = nxt[i]) { long long u = point[i]; if (d[u] > d[x] + len[i]) { d[u] = d[x] + len[i]; p[u] = p[x]; q.push(make_pair(d[u], u)); } } } for (long long i = 0; i <= tot; i += 2) { long long u = point[i], v = point[i ^ 1]; if (p[u] == p[v]) continue; sh[++w] = (node){p[u], p[v], d[u] + d[v] + len[i]}; } sort(sh + 1, sh + 1 + w, cmp); for (long long i = 1; i <= n; i++) fa[i] = i; long long ans = d[1]; for (long long i = 1; i <= w; i++) if (merge(sh[i].u, sh[i].v)) ans += sh[i].w; printf( %lld n , ans); }
|
/**
\file "inverters-watch.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: inverters-watch.v,v 1.2 2010/04/06 00:08:34 fang Exp $
Thanks to Ilya Ganusov for contributing this test.
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("watch in1 out3");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$to_prsim("TOP.out3", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #45 $finish;
/**
// optional: produce vector file for dump
initial begin
$dumpfile ("test.dump");
$dumpvars(0,TOP);
end
**/
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
module register_file(input clk,input we3,
input [3:0]a1,input [3:0]a2,input [3:0]a3,
input [31:0] wd3,input [31:0] r15,
output [31:0]rd1 ,output[31:0] rd2
);
reg[31:0] mem[0:15];
always@(posedge clk)begin
if(we3) mem[a3]=wd3;
if(r15) mem[15]=r15;
end
assign rd1 = (a1 == 4'b1111) ? r15 : mem[a1];
assign rd2 = (a2 == 4'b1111) ? r15 : mem[a2];
/*always@(*) begin
if(!(&(a1))) rd1=mem[a1]; else rd1 = r15;
if(!(&(a2))) rd2=mem[a2]; else rd2 = r15;
end*/
endmodule
/*
module register_file(input clk,input we3,
input [3:0]a1,input [3:0]a2,input [3:0]a3,
input [31:0] wd3,input [31:0] r15,
output [31:0]rd1 ,output[31:0] rd2
);
reg[31:0] mem[0:14];
always@(posedge clk)
if(we3) mem[a3]<=wd3;
assign rd1 = (a1 == 4'b1111) ? r15 : mem[a1];
assign rd2 = (a2 == 4'b1111) ? r15 : mem[a2];
endmodule*/
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a[100000], p[100000], i, ans = 0, price = INT_MAX; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %d %d , &a[i], &p[i]); for (i = 0; i < n; i++) { price = min(price, p[i]); ans += (a[i] * price); } printf( %d , ans); return 0; }
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
// payloads
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
end
else begin : gen_no_axi3_wid_packing
end
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
end
else begin : gen_no_region_signals
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
end
else begin : gen_no_user_signals
assign s_axi_buser = 'b0;
assign s_axi_ruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign s_axi_bid = 'b0;
assign s_axi_buser = 'b0;
assign s_axi_rlast = 1'b1;
assign s_axi_rid = 'b0;
assign s_axi_ruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// sound_main is the main sound module: it incorporates data storage (512b memory), from which
// it reads data, prepares it through sound_mulacc and sends to sound_dac. It incorporates in itself
// sound_dac, so it has outs to the DAC.
// clock is ordinary 24 MHz clock, mode_8chans is asynchronous input signal controlling mode of operation,
// either 4 or 8 channels.
//
// channels in 4 channel mode (mode_8chans=0,mode_pan4ch=0)
// 1,2 -> left
// 3,4 -> right
// channels in 8 channel mode (mode_8chans=1,mode_pan4ch=0)
// 1,2,5,6 -> left
// 3,4,7,8 -> right
// channels in panning 4 channel mode (mode_8chans=0,mode_pan4ch=1)
// 1,2,3,4 (vols 1,2,5,6) -> left
// 1,2,3,4 (vols 3,4,7,8) -> right
// channels in mem are at addressed 0-7 (corresponding to channels 1-8, respectively).
// mem contains volumes (lower 6 bits, 0-zero volume, 63-max volume) and sound data (signed value with sign inverted:
// -data in mem---+----value--
// $FF | +$7F
// $81 | +$01
// $80 | +$00
// $7F | -$01 (or $FF)
// $01 | -$7F (or $81)
// $00 | -$80 (or $80)
// alternatively, it could be treated as unsigned positive samples with middle point of $7F-$80.
//
// clock ``\__/``\__/``\__/``\__/``\__/``\__/``\__/``\__
// mem_read ______/`````\__________________________________
// mem_wraddr | no | |addr |
// mem_di |write| |data |
// mem_***_we ______|here!|_____/`````\______________________
// ^-- data written here!
module sound_main(
clock, // system clock (24 MHz)
mode_8chans, // =1 - 8 channels, =0 - 4 channels
mode_pan4ch, // =1 - 4 channels with panning
in_wrtoggle, // from ports.v module (async to clock)
in_datnvol, //
in_wraddr, //
in_data, //
dac_clock, // output to DAC
dac_leftright, // output to DAC
dac_data // output to DAC
);
// input-output description
input clock;
input mode_8chans;
input mode_pan4ch;
input in_wrtoggle;
input in_datnvol;
input [2:0] in_wraddr;
input [7:0] in_data;
output dac_clock;
output dac_leftright;
output dac_data;
// internal regs/wires
reg mem_read; // write to mem is forbidden while mem_read=1
reg datnvol;
reg [5:0] vol; // temporary storage for volume
reg mem_we; // write strobe
reg wrtgl1, wrtgl2, wrtgl3; // sync in and edge detect of in_wrtoggle
reg do_write; // indicates that write should be performed
reg [2:0] bf_wraddr;
reg [7:0] bf_data;
reg bf_datnvol;
wire dac_load; // signal from sound_dac module (when it loads new data)
wire [15:0] dac_pardata; // parallel data from sound_mulacc to sound_dac
reg mulacc_load; // load to sound_mulacc
reg mulacc_clrsum; // clr_sum to sound_mulacc
wire mulacc_ready; // ready from sound_mulacc
wire [7:0] mem_do; // data output of DAT or VOL
reg [8:0] mem_rdaddr; // read address for both memory blocks
reg int_mode_8chans; // internal and sync-in mode_8chans signals
reg sync_mode_8chans; //
reg int_mode_pan4ch,sync_mode_pan4ch; // same for pan4ch signal
reg [1:0] chanptr; // pointer to channels (4 channels total: 0,1,4,5 or 2,3,6,7 depending on lrptr state)
reg lrptr; // left-right pointer (selects either left (0) or right (1) channels)
reg [2:0] cur_st,nxt_st;
// for simulation purposes
initial
begin
bf_wraddr <= 0;
bf_datnvol <= 0;
bf_data <= 0;
do_write <= 0;
cur_st <= START;
end
// instantiating modules
sound_dac my_dac( .clock(clock),
.dac_clock(dac_clock),
.dac_leftright(dac_leftright),
.dac_data(dac_data),
.load(dac_load),
.datain(dac_pardata) );
sound_mulacc my_mulacc( .clock(clock),
.vol_in(vol),
.dat_in(mem_do),
.load(mulacc_load),
.clr_sum(mulacc_clrsum),
.ready(mulacc_ready),
.sum_out(dac_pardata) );
// DAT-VOL memory block
mem512b my_mem( .clk(clock),
.rdaddr(mem_rdaddr),
.dataout(mem_do),
.wraddr({5'b0,bf_datnvol,bf_wraddr}),
.datain(bf_data),
.we(mem_we) );
// syncing in asynchronous control signals
always @(posedge clock)
begin
{ int_mode_8chans,sync_mode_8chans } <= { sync_mode_8chans, mode_8chans };
{ int_mode_pan4ch,sync_mode_pan4ch } <= { sync_mode_pan4ch, mode_pan4ch };
end
// load lrptr (left-right pointer) on dac_load pulse
always @(posedge clock)
begin
if( dac_load )
lrptr <= ~dac_leftright;
end
// make memory read address from chanptr and lrptr
always @*
begin
/* mem_rdaddr[8:4] <= 5'd0;
mem_rdaddr[3] <= datnvol;
mem_rdaddr[2] <= int_mode_8chans ? chanptr[1] : 1'b0;
mem_rdaddr[1] <= lrptr;
mem_rdaddr[0] <= chanptr[0];*/
mem_rdaddr[8:4] <= 5'd0;
if( int_mode_8chans )
begin
mem_rdaddr[3] <= datnvol;
mem_rdaddr[2] <= chanptr[1];
mem_rdaddr[1] <= lrptr;
mem_rdaddr[0] <= chanptr[0];
end
else if( int_mode_pan4ch )
begin
mem_rdaddr[3] <= datnvol;
if( datnvol ) // sample data
begin
mem_rdaddr[2] <= 1'b0;
mem_rdaddr[1] <= chanptr[1];
mem_rdaddr[0] <= chanptr[0];
end
else // !datnvol: volumes
begin
mem_rdaddr[2] <= chanptr[1]; // same as in 8 channel
mem_rdaddr[1] <= lrptr;
mem_rdaddr[0] <= chanptr[0];
end
end
else //normal 4 channel mode
begin
mem_rdaddr[3] <= datnvol;
mem_rdaddr[2] <= 1'b0;
mem_rdaddr[1] <= lrptr;
mem_rdaddr[0] <= chanptr[0];
end
end
// handle mulacc_clrsum signal
always @(posedge clock)
begin
if( dac_load )
mulacc_clrsum <= 1'b1; // set on dac_load pulse
else if( mulacc_load )
mulacc_clrsum <= 1'b0; // clear on mulacc_load pulse, so only first mulacc cycle will read clrsum high
end
localparam START = 0;
localparam LOAD_VOL = 1;
localparam LOAD_VOL2 = 2;
localparam LOAD_DAT = 3;
localparam LOAD_DAT2 = 4;
localparam START_MUL = 5;
localparam WAIT_STOP = 6;
localparam LOOP = 7;
// FSM!
always @(posedge clock)
begin
if( dac_load )
cur_st <= START;
else
cur_st <= nxt_st;
end
always @*
begin
case( cur_st )
/////////////////////////////////////////////////////////////////////
START:
nxt_st <= LOAD_VOL;
/////////////////////////////////////////////////////////////////////
LOAD_VOL:
nxt_st <= LOAD_VOL2;
/////////////////////////////////////////////////////////////////////
LOAD_VOL2:
nxt_st <= LOAD_DAT;
/////////////////////////////////////////////////////////////////////
LOAD_DAT:
nxt_st <= LOAD_DAT2;
/////////////////////////////////////////////////////////////////////
LOAD_DAT2:
nxt_st <= START_MUL;
/////////////////////////////////////////////////////////////////////
START_MUL:
nxt_st <= WAIT_STOP;
/////////////////////////////////////////////////////////////////////
WAIT_STOP:
if( (!mulacc_ready) || (chanptr == 2'd3) )
nxt_st <= WAIT_STOP;
else
nxt_st <= LOOP;
/////////////////////////////////////////////////////////////////////
LOOP:
nxt_st <= LOAD_VOL;
/////////////////////////////////////////////////////////////////////
endcase
end
always @(posedge clock)
begin
case( cur_st )
/////////////////////////////////////////////////////////////////////
START:
begin
chanptr <= 2'd0;
mulacc_load <= 1'b0;
mem_read <= 1'b0;
end
/////////////////////////////////////////////////////////////////////
LOAD_VOL:
begin
mem_read <= 1'b1;
datnvol <= 1'b0;
end
/////////////////////////////////////////////////////////////////////
LOAD_VOL2:
begin
mem_read <= 1'b0;
end
/////////////////////////////////////////////////////////////////////
LOAD_DAT:
begin
vol <= mem_do[5:0];
mem_read <= 1'b1;
datnvol <= 1'b1;
end
/////////////////////////////////////////////////////////////////////
LOAD_DAT2:
begin
mem_read <= 1'b0;
mulacc_load <= 1'b1;
end
/////////////////////////////////////////////////////////////////////
START_MUL:
begin
mulacc_load <= 1'b0;
end
/////////////////////////////////////////////////////////////////////
// WAIT_STOP:
/////////////////////////////////////////////////////////////////////
LOOP:
begin
chanptr <= chanptr + 2'd1;
end
/////////////////////////////////////////////////////////////////////
endcase
end
// controlling writes to memory
// toggles
always @(negedge clock)
wrtgl1 <= in_wrtoggle;
always @(posedge clock)
{wrtgl3,wrtgl2} <= {wrtgl2,wrtgl1};
// intermediate buffers and writing
always @(posedge clock)
begin
if( wrtgl3!=wrtgl2 )
begin
bf_wraddr <= in_wraddr;
bf_data <= in_data;
bf_datnvol <= in_datnvol;
do_write <= 1'b1;
end
else if( mem_we )
begin
do_write <= 1'b0;
end
end
always @*
begin
mem_we <= do_write & (~mem_read);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> void chmax(T& a, const T& b) { if (a < b) a = b; } template <typename T> void chmin(T& a, const T& b) { if (a > b) a = b; } int N, M; long long dp[3001][3001]; const long long INF = 1e17; int main() { cin.tie(0); ios::sync_with_stdio(false); cin >> N; vector<int> A(N), B(N); for (int i = (0); i < (N); i++) { cin >> A[i]; A[i] -= i; B[i] = A[i]; } sort((B).begin(), (B).end()); B.erase(unique((B).begin(), (B).end()), B.end()); M = B.size(); fill(dp[0], dp[N + 1], INF); dp[0][0] = 0; for (int i = (0); i < (N); i++) { for (int j = (0); j < (M); j++) { chmin(dp[i + 1][j], dp[i][j] + abs(A[i] - B[j])); chmin(dp[i][j + 1], dp[i][j]); } } long long ans = INF; for (int i = (0); i < (M); i++) { chmin(ans, dp[N][i]); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const bool testing = false; pair<long long, long long> d[100000]; int nf[100000], nb[100000]; pair<long long, long long> getmid(int a, int b) { long long y = d[b].second - d[a].second; long long x = d[b].first - d[a].first; pair<long long, long long> res = make_pair(-y + x * x + 2 * x * d[a].first, 2 * x); return res; } void program() { int n; cin >> n; for (int i = 0; i < n; i++) { long long t1, t2; cin >> t1 >> t2; d[i] = make_pair(t1, t2); } std::sort(d, d + n); int start = 0; while (start + 1 < n && d[start + 1].first == d[start].first) start++; { nb[start] = -1; int prev = start; while (prev < n) { int t = prev + 1; while (t + 1 < n && d[t + 1].first == d[t].first) t++; if (t < n) nb[t] = prev; nf[prev] = t; prev = t; } } { int t1 = start; while (true) { int t2 = nf[t1]; if (t2 == n) break; int t3 = nf[t2]; if (t3 == n) break; pair<long long, long long> A1 = getmid(t1, t2); pair<long long, long long> A2 = getmid(t1, t3); if (A2.first * A1.second <= A1.first * A2.second) { nf[t1] = t3; nb[t3] = t1; if (nb[t1] != -1) t1 = nb[t1]; } else t1 = nf[t1]; } } long long res = 0; { int t = start; while (nf[t] != n) { res++; t = nf[t]; } } cout << res; } int main() { if (!testing) { program(); return 0; } FILE* fin = NULL; fin = fopen( in.txt , w+ ); fprintf(fin, n3 n-1 0 n0 2 n1 0 n ); fclose(fin); freopen( in.txt , r , stdin); printf( test case(1) => expected : n ); printf( 2 ); printf( test case(1) => found : n ); program(); fin = fopen( in.txt , w+ ); fprintf(fin, n5 n1 0 n1 -1 n0 -1 n-1 0 n-1 -1 n ); fclose(fin); freopen( in.txt , r , stdin); printf( test case(2) => expected : n ); printf( 1 ); printf( test case(2) => found : n ); program(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5, M = 5; int cc[N][M], sz[N], k; long long ret[N], sum = 0; vector<int> adj[N]; long long dfs(int x, int p) { int t, v, j, u, i; sz[x] = 1; long long R = 0, temp; for (i = 0; i < adj[x].size(); ++i) { u = adj[x][i]; if (u != p) { temp = dfs(u, x); sum += sz[u] * R; R += temp; sum += temp * sz[x]; for (j = 0; j < k; ++j) for (t = 0; t < k; ++t) { if (j + t + 2 <= k) sum -= (long long)cc[x][j] * cc[u][t]; } for (j = 0; j < k; ++j) cc[x][j] += cc[u][j]; sz[x] += sz[u]; } } u = ++cc[x][k - 1]; for (i = k - 2; i >= 0; --i) cc[x][i + 1] = cc[x][i]; cc[x][0] = u; ret[x] = R + u; return ret[x]; } int main() { int n, i, j, u, v, a, b; cin >> n >> k; for (i = 0; i < n - 1; ++i) { scanf( %d%d , &a, &b); adj[a].push_back(b); adj[b].push_back(a); } dfs(1, 0); cout << sum << endl; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 5; int a[maxn], n, k; long long sum; long long judge1(int m) { long long ans = 0; for (int i = 1; a[i] < m && i <= n; i++) { ans += m - a[i]; } return ans; } long long judge2(int m) { long long ans = 0; for (int i = n; a[i] > m && i >= 1; i--) { ans += a[i] - m; } return ans; } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); sum += a[i]; } sort(a + 1, a + n + 1); int l = a[1], r = a[n], poorest = a[1]; while (l <= r) { int mid = (l + r) >> 1; long long p = judge1(mid); if (p <= k) { poorest = mid; l = mid + 1; } else r = mid - 1; } l = a[1]; r = a[n]; int richest = a[n]; while (l <= r) { int mid = (l + r) >> 1; long long p = judge2(mid); if (p <= k) { richest = mid; r = mid - 1; } else l = mid + 1; } if (poorest < richest) printf( %d n , richest - poorest); else { if (sum % n == 0) printf( 0 n ); else printf( 1 n ); } return 0; }
|
module SimpleMmuTest;
`include "Framework.v"
reg reset;
reg clk;
reg [31:0] addrA;
reg [31:0] addrB;
reg writeEnable = 0;
reg [7:0] dataIn;
reg requestA;
reg requestB;
wire [7:0] outA;
wire [7:0] outB;
wire busyA;
wire busyB;
wire [15:0] displayIn = 0;
wire [31:0] displayAddr;
wire displayWE;
Display dsp(clk, displayIn);
wire [31:0] mmioInB;
wire [31:0] mmioAddrB;
wire mmioWEB;
SimpleMmu mmu(clk, reset, addrA, addrB, writeEnable, dataIn, requestA, requestB, outA, outB, busyA, busyB,
displayIn,displayAddr,displayWE, mmioInB, mmioAddrB, mmioWEB);
always #10 clk = ~clk;
integer i;
integer j;
initial begin
$dumpfile("timing.vcd");
$dumpvars(0,mmu);
reset = 1;
clk = 0;
writeEnable = 0;
#20 reset = 0;
for(i = 0; i < 16; i = i + 1)
begin
addrA = i;
addrB = i;
requestA = 1;
requestB = 1;
@(negedge busyA) $display("Address: 0x%h = 0x%h, 0x%h", i, outA, outB);
requestA = 0;
requestB = 0;
end
j = 0;
for(i = 360; i < 375; i = i + 1)
begin
addrA = i;
dataIn = j;
writeEnable = 1;
requestA = 1;
#100 writeEnable = 0;
requestA = 0;
j = j + 1;
end
for(i = 360; i < 375; i = i + 1)
begin
addrA = i;
requestA = 1;
#100 $display("Address: 0x%h = 0x%h", i, outA);
requestA = 0;
end
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXTP_TB_V
`define SKY130_FD_SC_LS__SEDFXTP_TB_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sedfxtp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 DE = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 DE = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 DE = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 DE = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__sedfxtp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXTP_TB_V
|
#include<bits/stdc++.h> /* #include <ext/pb_ds/assoc_container.hpp> // Common file #include <ext/pb_ds/tree_policy.hpp> // Including */ using namespace std; //using namespace __gnu_pbds; //typedefs typedef long long ll; typedef vector<int> vi; typedef vector<ll> vl; typedef vector<vi> vvi; typedef vector<vl> vvl; typedef pair<int,int> pii; typedef pair<double, double> pdd; typedef pair<ll, ll> pll; typedef vector<pii> vii; typedef vector<pll> vll; typedef vector<int>::iterator vit; typedef set<int>::iterator sit; /* template<typename T> using ordered_set = tree<T, null_type, less<T>, rb_tree_tag, tree_order_statistics_node_update>; template<typename F, typename S> using ordered_map = tree<F, S, less<F>, rb_tree_tag, tree_order_statistics_node_update>; */ //#Defines #define rep(i,a,b) for(i=a;i<=b;i++) #define repR(i,a,b) for(i=a;i>=b;i--) //#define pb push_back #define pb emplace_back #define F first #define S second #define mp make_pair #define all(c) c.begin(),c.end() #define endl n #define pf printf #define sf scanf //#define left __left //#define right __right //#define tree __tree #define MOD 1000000007 //#define harmonic(n) 0.57721566490153286l+log(n) #define RESET(a,b) memset(a,b,sizeof(a)) #define gcd(a,b) __gcd(a,b) #define lcm(a,b) (a*(b/gcd(a,b))) #define sqr(a) ((a) * (a)) #define optimize() ios_base::sync_with_stdio(0);cin.tie(0);cout.tie(0); #define fraction() cout.unsetf(ios::floatfield); cout.precision(10); cout.setf(ios::fixed,ios::floatfield); const double PI = acos(-1); const double eps = 1e-9; const int inf = 2000000000; const ll infLL = 9000000000000000000; //Bit Operations inline bool checkBit(ll n, int i) { return n&(1LL<<i); } inline ll setBit(ll n, int i) { return n|(1LL<<i);; } inline ll resetBit(ll n, int i) { return n&(~(1LL<<i)); } int fx[] = {0, 0, +1, -1}; int fy[] = {+1, -1, 0, 0}; //int dx[] = {+1, 0, -1, 0, +1, +1, -1, -1}; //int dy[] = {0, +1, 0, -1, +1, -1, +1, -1}; //Inline functions inline bool EQ(double a, double b) { return fabs(a-b) < 1e-9; } inline bool isLeapYear(ll year) { return (year%400==0) || (year%4==0 && year%100!=0); } inline void normal(ll &a) { a %= MOD; (a < 0) && (a += MOD); } inline ll modMul(ll a, ll b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a*b)%MOD; } inline ll modAdd(ll a, ll b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a+b)%MOD; } inline ll modSub(ll a, ll b) { a %= MOD, b %= MOD; normal(a), normal(b); a -= b; normal(a); return a; } inline ll modPow(ll b, ll p) { ll r = 1; while(p) { if(p&1) r = modMul(r, b); b = modMul(b, b); p >>= 1; } return r; } inline ll modInverse(ll a) { return modPow(a, MOD-2); } inline ll modDiv(ll a, ll b) { return modMul(a, modInverse(b)); } inline bool isInside(pii p,ll n,ll m) { return (p.first>=0&&p.first<n&&p.second>=0&&p.second<m); } inline bool isInside(pii p,ll n) { return (p.first>=0&&p.first<n&&p.second>=0&&p.second<n); } inline bool isSquare(ll x) { ll s = sqrt(x); return (s*s==x); } inline bool isFib(ll x) { return isSquare(5*x*x+4)|| isSquare(5*x*x-4); } inline bool isPowerOfTwo(ll x) { return ((1LL<<(ll)log2(x))==x); } struct func { //this is a sample overloading function for sorting stl bool operator()(pii const &a, pii const &b) { if(a.F==b.F) return (a.S<b.S); return (a.F<b.F); } }; //Prime Number Generator /* #define M 100000000 int marked[M/64 + 2]; #define on(x) (marked[x/64] & (1<<((x%64)/2))) #define mark(x) marked[x/64] |= (1<<((x%64)/2)) vl prime; bool isPrime(int num) { return num > 1 && (num == 2 || ((num & 1) && !on(num))); } void sieve(ll n) { for (ll i = 3; i * i < n; i += 2) { if (!on(i)) { for (ll j = i * i; j <= n; j += i + i) { mark(j); } } } prime.pb(2); for(ll i = 3; i <= n; i += 2) { if(!on(i)) prime.pb(i); } } */ // //debug #ifdef tajir template < typename F, typename S > ostream& operator << ( ostream& os, const pair< F, S > & p ) { return os << ( << p.first << , << p.second << ) ; } template < typename T > ostream &operator << ( ostream & os, const vector< T > &v ) { os << { ; for(auto it = v.begin(); it != v.end(); ++it) { if( it != v.begin() ) os << , ; os << *it; } return os << } ; } template < typename T > ostream &operator << ( ostream & os, const set< T > &v ) { os << [ ; for(auto it = v.begin(); it != v.end(); ++it) { if( it != v.begin() ) os << , ; os << *it; } return os << ] ; } template < typename T > ostream &operator << ( ostream & os, const multiset< T > &v ) { os << [ ; for(auto it = v.begin(); it != v.end(); ++it) { if( it != v.begin() ) os << , ; os << *it; } return os << ] ; } template < typename F, typename S > ostream &operator << ( ostream & os, const map< F, S > &v ) { os << [ ; for(auto it = v.begin(); it != v.end(); ++it) { if( it != v.begin() ) os << , ; os << it -> first << = << it -> second ; } return os << ] ; } #define dbg(args...) do {cerr << #args << : ; faltu(args); } while(0) clock_t tStart = clock(); #define timeStamp dbg( Execution Time: , (double)(clock() - tStart)/CLOCKS_PER_SEC) void faltu () { cerr << endl; } template <typename T> void faltu( T a[], int n ) { for(int i = 0; i < n; ++i) cerr << a[i] << ; cerr << endl; } template <typename T, typename ... hello> void faltu( T arg, const hello &... rest) { cerr << arg << ; faltu(rest...); } #else #define dbg(args...) #endif // tajir bool valid(string s,int n) { for(int i = 0; i < (n-1); ++i) { if(s[i] == 1 && s[i+1] == 1 ) return false; } return true; } int main() { #ifdef tajir freopen( input.txt , r , stdin); #else // online submission #endif optimize(); int n; string s; cin >> n >> s; if(!valid(s,n)) { cout << No << endl; return 0; } for(int i = 0; i < n; ++i) { if(s[i] == 0 ) { s[i] = 1 ; if(valid(s,n)) { cout << No << endl; return 0; } s[i] = 0 ; } } cout << Yes << endl; return 0; } //?
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_2_V
`define SKY130_FD_SC_MS__O41A_2_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o41a_2 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o41a_2 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_2_V
|
`default_nettype none
`timescale 1ns / 1ps
// The receiver core provides a ITU V.4-compatible bit-serial interface.
// The receiver is broadly broken up into three parts: the Wishbone B4
// slave interface, the transmitter, and the receiver.
//
// This module defines the V.4-compatible receiver.
//
// Note that if both eedd_i and eedc_i are low, the receiver never
// sees any edges to transition with, and therefore can be used to
// disable the receiver.
//
// eedd_i eedc_i Results
// 0 0 Disable receiver.
// 0 1 Receiver clocks on RXC input only. [1]
// 1 0 Receiver clocks on RXD input only. [2]
// 1 1 Receiver clocks on any edge it can find. [1, 2]
//
// Note 1: Only the rising edge of RXC is recognized.
// Note 2: Both rising AND falling edges of RXD are recognized.
module sia_rxq(
input clk_i,
input reset_i,
// These inputs correspond to fields found in the register
// set of the receiver. Register set not included.
input [BW:0] bits_i,
input [BRW:0] baud_i,
input eedd_i,
input eedc_i,
input rxcpol_i,
// Inputs from external hardware
input rxd_i,
input rxc_i,
// FIFO outputs.
input rxq_pop_i,
input rxq_oe_i,
output [SRW:0] rxq_dat_o,
output rxq_full_o,
output rxq_not_empty_o
);
parameter SHIFT_REG_WIDTH = 16;
parameter BAUD_RATE_WIDTH = 32;
parameter BITS_WIDTH = 5;
parameter DATA_BITS = SHIFT_REG_WIDTH;
parameter DEPTH_BITS = 4;
parameter BRW = BAUD_RATE_WIDTH - 1;
parameter SRW = SHIFT_REG_WIDTH - 1;
parameter BW = BITS_WIDTH - 1;
wire rx_rq_idle;
reg rx_rq_idle_dly;
wire [SRW:0] rx_rq_dat;
wire rxq_empty_o;
assign rxq_not_empty_o = ~rxq_empty_o;
always @(posedge clk_i) begin
if(reset_i) begin
rx_rq_idle_dly <= 0;
end
else begin
rx_rq_idle_dly <= rx_rq_idle;
end
end
sia_receiver #(
.SHIFT_REG_WIDTH(SHIFT_REG_WIDTH),
.BAUD_RATE_WIDTH(BAUD_RATE_WIDTH)
) rx (
.clk_i(clk_i),
.reset_i(reset_i),
.bits_i(bits_i),
.baud_i(baud_i),
.eedd_i(eedd_i),
.eedc_i(eedc_i),
.rxd_i(rxd_i),
.rxc_i(rxc_i ^ rxcpol_i),
.dat_o(rx_rq_dat),
.idle_o(rx_rq_idle),
.sample_to()
);
queue #(
.DEPTH_BITS(DEPTH_BITS),
.DATA_BITS(DATA_BITS)
) rq (
.clk_i(clk_i),
.reset_i(reset_i),
.dat_i(rx_rq_dat),
.push_i(rx_rq_idle & ~rx_rq_idle_dly),
.pop_i(rxq_pop_i),
.oe_i(rxq_oe_i),
.dat_o(rxq_dat_o),
.full_o(rxq_full_o),
.empty_o(rxq_empty_o),
.rp_to(),
.wp_to(),
.room_to()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; const int n = s.length() + 5; int arr[n]; memset(arr, 0, sizeof arr); int m, l, r; for (int i = 0; i < s.length(); i++) { if (s[i] == s[i + 1]) { arr[i + 2]++; } arr[i + 1] += arr[i]; } cin >> m; for (int i = 0; i < m; i++) { cin >> l >> r; cout << arr[r] - arr[l] << n ; } }
|
#include <bits/stdc++.h> using namespace std; char str[11][11]; int f[8][20][20]; int dx[] = {0, 1, -1, -1, 1, 1, 0, -1}, dy[] = {-1, -1, -1, 0, 0, 1, 1, 1}; bool check() { memset(f, 0, sizeof f); for (int i = 1; i <= 10; i++) for (int j = 1; j <= 10; j++) { if (str[i][j] != X ) continue; for (int k = 0; k < 4; k++) f[k][i][j] = f[k][i + dy[k]][j + dx[k]] + 1; } for (int i = 10; i >= 1; i--) for (int j = 10; j >= 1; j--) { if (str[i][j] != X ) continue; for (int k = 4; k < 8; k++) f[k][i][j] = f[k][i + dy[k]][j + dx[k]] + 1; } for (int i = 1; i <= 10; i++) for (int j = 1; j <= 10; j++) for (int k = 0; k < 8; k++) if (f[k][i][j] >= 5) return 1; return 0; } int main() { for (int i = 1; i <= 10; i++) scanf( %s , str[i] + 1); for (int i = 1; i <= 10; i++) for (int j = 1; j <= 10; j++) { if (str[i][j] != . ) continue; str[i][j] = X ; if (check()) { puts( YES ); return 0; } str[i][j] = . ; } puts( NO ); return 0; }
|
`include "defines.vh"
/**
* @module max_comparator
* @author sabertazimi
* @email
* @brief find line that has max reference count
* @input cntX reference count of lineX
* @output lru_line line that has max reference count(lru line)
*/
module max_comparator
(
input [`BTB_LINE_SIZE-1:0] cnt0,
input [`BTB_LINE_SIZE-1:0] cnt1,
input [`BTB_LINE_SIZE-1:0] cnt2,
input [`BTB_LINE_SIZE-1:0] cnt3,
input [`BTB_LINE_SIZE-1:0] cnt4,
input [`BTB_LINE_SIZE-1:0] cnt5,
input [`BTB_LINE_SIZE-1:0] cnt6,
input [`BTB_LINE_SIZE-1:0] cnt7,
output reg [`BTB_LINE_SIZE-1:0] lru_line
);
integer i;
reg [`BTB_LINE_SIZE-1:0] max_cnt;
reg [`BTB_LINE_SIZE-1:0] max_line;
initial begin
lru_line <= 0;
end
always @ (cnt0 or cnt1 or cnt2 or cnt3 or cnt4 or cnt5 or cnt6 or cnt7) begin
max_cnt = 0;
max_line = 0;
if (cnt0 >= max_cnt) begin
max_cnt = cnt0;
max_line = 0;
end
if (cnt1 >= max_cnt) begin
max_cnt = cnt1;
max_line = 1;
end
if (cnt2 >= max_cnt) begin
max_cnt = cnt2;
max_line = 2;
end
if (cnt3 >= max_cnt) begin
max_cnt = cnt3;
max_line = 3;
end
if (cnt4 >= max_cnt) begin
max_cnt = cnt4;
max_line = 4;
end
if (cnt5 >= max_cnt) begin
max_cnt = cnt5;
max_line = 5;
end
if (cnt6 >= max_cnt) begin
max_cnt = cnt6;
max_line = 6;
end
if (cnt7 >= max_cnt) begin
max_cnt = cnt7;
max_line = 7;
end
end
always @ (max_line) begin
lru_line <= max_line;
end
endmodule // max_comparator
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BLACKBOX_V
/**
* lpflow_inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso0p (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2005, MOD = 998244353; char ch[MAXN]; long long cnt[MAXN], dp[MAXN][MAXN]; long long KSM(long long a, long long t) { long long ans = 1; while (t) { if (t & 1) ans = ans * a % MOD; t >>= 1; a = a * a % MOD; } return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> (ch + 1); int n = strlen(ch + 1); for (int i = 1; i <= n; i++) cnt[i] = cnt[i - 1] + (ch[i] == ? ); for (int j = 1; j <= n; j++) for (int i = j - 1; i; i--) { if (ch[i] != ) && ch[j] != ( ) dp[i][j] = (dp[i][j] + dp[i + 1][j - 1] + KSM(2, cnt[j - 1] - cnt[i])) % MOD; if (ch[i] != ( ) dp[i][j] = (dp[i][j] + dp[i + 1][j]) % MOD; if (ch[j] != ) ) dp[i][j] = (dp[i][j] + dp[i][j - 1]) % MOD; if (ch[i] != ( && ch[j] != ) ) dp[i][j] = (dp[i][j] - dp[i + 1][j - 1] + MOD) % MOD; } cout << dp[1][n]; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 7805 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4,
w3,
w64,
w61,
w7808,
w7805;
assign w1 = i_data0;
assign w3 = w4 - w1;
assign w4 = w1 << 2;
assign w61 = w64 - w3;
assign w64 = w1 << 6;
assign w7805 = w7808 - w3;
assign w7808 = w61 << 7;
assign o_data0 = w7805;
//multiplier_block area estimate = 5006.23186995147;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; class DSU { public: vector<int> parent; int total_components; DSU(int n) { parent.resize(n + 1); for (int i = 1; i <= n; i++) { parent[i] = i; } total_components = n; } int get(int x) { if (parent[x] == x) { return x; } return parent[x] = get(parent[x]); } bool unite(int x, int y) { int p1 = get(x); int p2 = get(y); if (p1 == p2) { return true; } parent[p1] = p2; total_components--; return false; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; bool cycle = false; DSU g(n); while (m--) { int u, v; cin >> u >> v; if (g.unite(u, v)) { cycle = true; } } if (cycle || g.total_components > 1) { cout << no << endl; } else { cout << yes << endl; } cout.flush(); return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; const int maxn = 1e3 + 10; const int inf = 0x7fffffff; const long long INF = 9E18; const int mod = 1e9 + 7; const long long mod2 = 1e9 + 9; const double eps = 1e-7; const double pi = acos(-1.0); template <typename T> inline bool read(T &x) { T f = 1; char ch = getchar(); if (ch == EOF) return false; for (; ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) f = -1; for (x = 0; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; x *= f; return true; } int dcmp(double x) { return fabs(x) <= eps ? 0 : (x > 0 ? 1 : -1); } int main() { int test; cin >> test; while (test--) { double x; cin >> x; if (dcmp(x) == 0) cout << Y 0 0 << endl; else { if (x * x - 4 * x < 0) cout << N << endl; else { double res = (x + sqrt(x * x - 4 * x)) / 2; double a = x / res; cout << fixed << setprecision(10) << Y << a << << res << endl; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, K, T, to[25]; long double prob[25], dp[2000100], val[25], ans[25]; bool v[2000100]; long double calc(int mask) { if (v[mask]) return dp[mask]; v[mask] = 1; int i; long double tot = 0; for (i = 0; i < N; i++) if (mask & (1 << i)) tot += prob[i]; for (i = 0; i < N; i++) if (mask & (1 << i)) { tot -= prob[i]; dp[mask] = dp[mask] + (prob[i] * calc(mask - (1 << i))) / (1 - tot); tot += prob[i]; } return dp[mask]; } void get_masks(int mask, int cnt, int p) { if (p == N || cnt == K) { if (cnt != K) return; calc(mask); int i; for (i = 0; i < N; i++) if (mask & (1 << i)) val[i] += dp[mask]; return; } get_masks(mask, cnt, p + 1); get_masks(mask + (1 << p), cnt + 1, p + 1); } int main() { cin >> N >> K; int i; for (i = 0; i < N; i++) { cin >> prob[i]; if (prob[i] != 0) { T++; prob[T - 1] = prob[i]; to[T - 1] = i; } } swap(T, N); if (K > N) K = N; dp[0] = 1, v[0] = 1; get_masks(0, 0, 0); for (i = 0; i < N; i++) ans[to[i]] = val[i]; for (i = 0; i < T; i++) cout << fixed << setprecision(9) << ans[i] << ; cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; while (scanf( %d , &n) != EOF) { for (int i = 0; i <= n; i++) { int space = (n - i) * 2; for (int j = 0; j < space; j++) printf( ); if (!i) printf( %d n , 0); else { for (int j = 0; j <= i; j++) printf( %d , j); for (int j = i - 1; j > 0; j--) printf( %d , j); printf( %d n , 0); } } for (int i = n - 1; i >= 0; i--) { int space = (n - i) * 2; for (int j = 0; j < space; j++) printf( ); if (!i) printf( %d n , 0); else { for (int j = 0; j <= i; j++) printf( %d , j); for (int j = i - 1; j > 0; j--) printf( %d , j); printf( %d n , 0); } } } return 0; }
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: fr_cycle_shifter.v
//
// The fr-cycle shifter shifts the input data by X number of full-rate-cycles, where X is specified by the shift_by port.
// datain is a bus that combines data of multiple full rate cycles, in specific time order. For example,
// in a quarter-rate system, the datain bus must be ordered as {T3, T2, T1, T0}, where Ty represents the y'th fr-cycle
// data item, of width DATA_WIDTH. The following illustrates outputs at the dataout port for various values of shift_by.
// "__" means don't-care.
//
// shift_by dataout in current cycle dataout in next clock cycle
// 00 {T3, T2, T1, T0} {__, __, __, __}
// 01 {T2, T1, T0, __} {__, __, __, T3}
// 10 {T1, T0, __, __} {__, __, T3, T2}
// 11 {T0, __, __, __} {__, T3, T2, T1}
//
// In full-rate or half-rate systems, only the least-significant bit of shift-by has an effect
// (i.e. you can only shift by 0 or 1 fr-cycle).
// In quarter-rate systems, all bits of shift_by are used (i.e. you can shift by 0, 1, 2, or 3 fr-cycles).
//
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module ddr3_s4_uniphy_example_if0_p0_fr_cycle_shifter(
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH*RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] shift_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true")
datain_r <= {FULL_DATA_WIDTH{1'b1}};
else
datain_r <= {FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
endmodule
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#include <bits/stdc++.h> using namespace std; void flash() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } void solve() { long long n; cin >> n; vector<long long> v(n); long long sm = 0; long long mx = 0; for (long long i = 0; i < n; i++) { cin >> v[i]; sm += v[i]; mx = max(mx, v[i]); } function<long long(long long)> dfs = [&](long long l) -> long long { if (l <= 0) return 0; return dfs(l - 1); }; long long val1 = mx; long long val2 = sm - mx; if (n == 1) { cout << T << n ; return; } long long ok = dfs(n); if (ok > 5) { cout << T << n ; return; } ok = dfs(n - 1); if (ok > 4) { cout << HL << n ; return; } if (sm - n == 0) { if (n % 2) { cout << T << n ; return; } else { cout << HL << n ; return; } } if (val1 > val2) { cout << T << n ; return; } if (sm % 2 == 0) { cout << HL << n ; return; } else { cout << T << n ; return; } } int32_t main() { flash(); long long t; t = 1; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-7; double L, R, m1, m2, a, b, l; double calc(double alp) { return a * sin(alp) + b * cos(alp) - l * sin(alp) * cos(alp); } int main() { scanf( %lf%lf%lf , &a, &b, &l); if (a > b) swap(a, b); if (l <= b) { printf( %.8lf n , min(l, a)); return 0; } L = 0; R = acos(-1) / 2; while (R - L > eps) { m1 = (2 * L + R) / 3; m2 = (L + 2 * R) / 3; if (calc(m1) > calc(m2)) L = m1; else R = m2; } L = min(calc(L), l); if (L < eps) puts( My poor head =( ); else printf( %.8lf n , L); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> using VV = vector<vector<T>>; template <class T> inline bool SMIN(T &l, const T &r) { return l < r ? l = r, 1 : 0; } template <class T> inline bool SMAX(T &l, const T &r) { return l > r ? l = r, 1 : 0; } const string yes = YES , no = NO ; int X, Y, Z, T1, T2, T3; string solve() { long long s = abs(X - Y) * T1; long long e = abs(Z - X) * T2 + abs(X - Y) * T2 + 3LL * T3; return !(s < e) ? yes : no; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> X >> Y >> Z >> T1 >> T2 >> T3; cout << solve() << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; struct query { int k, pos, ind; } queries[200005]; struct arr { int val, ind; } a[200005]; long long n, q, cnt, res[200005], fw[200005], it[4 * 200005], len, b[200005]; bool cmp(arr a, arr b) { if (a.val != b.val) return a.val > b.val; return a.ind < b.ind; } bool que(query a, query b) { return a.k < b.k; } void update(long long k, long long l, long long r, long long id) { if (l == r) { it[k] = 1; return; } long long mid = (l + r) / 2; if (id <= mid) update(k * 2, l, mid, id); else update(k * 2 + 1, mid + 1, r, id); it[k] = it[k * 2] + it[k * 2 + 1]; } long long get(long long k, long long l, long long r, long long id) { if (id > it[k]) return -1; if (l == r) return l; long long mid = (l + r) / 2; if (id <= it[k * 2]) return get(k * 2, l, mid, id); else return get(k * 2 + 1, mid + 1, r, id - it[k * 2]); } int main() { cin.tie(NULL); ios_base::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i].val; a[i].ind = i; b[i] = a[i].val; } sort(a + 1, a + 1 + n, cmp); cin >> q; for (int i = 1; i <= q; i++) { cin >> queries[i].k >> queries[i].pos; queries[i].ind = i; } sort(queries + 1, queries + 1 + q, que); for (int i = 1; i <= q; i++) { while (len != queries[i].k) { len++; update(1, 1, n, a[len].ind); } res[queries[i].ind] = b[get(1, 1, n, queries[i].pos)]; } for (int i = 1; i <= q; i++) cout << res[i] << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SRSDFSTP_FUNCTIONAL_PP_V
/**
* srsdfstp: Scan flop with sleep mode, inverted set, non-inverted
* clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dff_ps_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_ps_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srsdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire SET ;
wire mux_out ;
wire buf_Q ;
wire pwrgood_pp0_out_Q;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PS_pp$PKG$sN `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, SLEEP_B, , KAPWR, VGND, VPWR);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND );
buf buf0 (Q , pwrgood_pp0_out_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFSTP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { string str; cin >> str; int ans(0); for (int i = 0; i < str.size(); ++i) if (str[i] != str[str.size() - 1 - i]) ++ans; if (ans == 2 || (ans == 0 && str.size() % 2 == 1)) cout << YES << endl; else cout << NO << endl; return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module vgafb_fifo64to16(
input sys_clk,
input vga_rst,
input stb,
input [63:0] di,
output can_burst,
output do_valid,
output reg [15:0] do,
input next /* should only be asserted when do_valid = 1 */
);
/*
* FIFO can hold 8 64-bit words
* that is 32 16-bit words.
*/
reg [63:0] storage[0:7];
reg [2:0] produce; /* in 64-bit words */
reg [4:0] consume; /* in 16-bit words */
/*
* 16-bit words stored in the FIFO, 0-32 (33 possible values)
*/
reg [5:0] level;
wire [63:0] do64;
assign do64 = storage[consume[4:2]];
always @(*) begin
case(consume[1:0])
2'd0: do <= do64[63:48];
2'd1: do <= do64[47:32];
2'd2: do <= do64[31:16];
2'd3: do <= do64[15:0];
endcase
end
always @(posedge sys_clk) begin
if(vga_rst) begin
produce = 3'd0;
consume = 5'd0;
level = 6'd0;
end else begin
if(stb) begin
storage[produce] = di;
produce = produce + 3'd1;
level = level + 6'd4;
end
if(next) begin /* next should only be asserted when do_valid = 1 */
consume = consume + 5'd1;
level = level - 6'd1;
end
end
end
assign do_valid = ~(level == 6'd0);
assign can_burst = level <= 6'd16;
endmodule
|
module avr_interface #(
parameter CLK_RATE = 50000000,
parameter SERIAL_BAUD_RATE = 500000
)(
input clk,
input rst,
// cclk, or configuration clock is used when the FPGA is begin configured.
// The AVR will hold cclk high when it has finished initializing.
// It is important not to drive the lines connecting to the AVR
// until cclk is high for a short period of time to avoid contention.
input cclk,
// signal the rest of the chip we are ready
output ready,
// AVR SPI Signals
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
// AVR Serial Signals
output tx,
input rx,
// Serial Interface
output [7:0] rx_data,
output new_rx_data,
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
// Register interface signals
output [5:0] reg_addr,
output write,
output new_req,
output [7:0] write_value,
input [7:0] read_value
);
wire n_rdy = !ready;
wire spi_done;
wire [7:0] spi_dout;
wire frame_start, frame_end;
wire tx_m;
wire spi_miso_m;
localparam STATE_SIZE = 2;
localparam IDLE = 0,
ADDR = 1,
WRITE = 2,
READ = 3;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [7:0] write_value_d, write_value_q;
reg write_d, write_q;
reg auto_inc_d, auto_inc_q;
reg [5:0] reg_addr_d, reg_addr_q;
reg new_req_d, new_req_q;
reg first_write_d, first_write_q;
assign reg_addr = reg_addr_q;
assign write = write_q;
assign new_req = new_req_q;
assign write_value = write_value_q;
// these signals connect to the AVR and should be Z when the AVR isn't ready
assign spi_miso = ready && !spi_ss ? spi_miso_m : 1'bZ;
assign tx = ready ? tx_m : 1'bZ;
// cclk_detector is used to detect when cclk is high signaling when
// the AVR is ready
cclk_detector #(.CLK_RATE(CLK_RATE)) cclk_detector (
.clk(clk),
.rst(rst),
.cclk(cclk),
.ready(ready)
);
spi_slave spi_slave (
.clk(clk),
.rst(n_rdy),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck(spi_sck),
.done(spi_done),
.din(read_value),
.dout(spi_dout),
.frame_start(frame_start),
.frame_end(frame_end)
);
// CLK_PER_BIT is the number of cycles each 'bit' lasts for
// rtoi converts a 'real' number to an 'integer'
parameter CLK_PER_BIT = $rtoi($ceil(CLK_RATE/SERIAL_BAUD_RATE));
serial_rx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_rx (
.clk(clk),
.rst(n_rdy),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_tx (
.clk(clk),
.rst(n_rdy),
.tx(tx_m),
.block(tx_block),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
always @(*) begin
write_value_d = write_value_q;
write_d = write_q;
auto_inc_d = auto_inc_q;
reg_addr_d = reg_addr_q;
new_req_d = 1'b0;
state_d = state_q;
first_write_d = first_write_q;
case (state_q)
IDLE: begin
if (frame_start)
state_d = ADDR;
end
ADDR: begin
if (spi_done) begin
first_write_d = 1'b1;
{write_d, auto_inc_d, reg_addr_d} = spi_dout;
if (spi_dout[7]) begin
state_d = WRITE;
end else begin
state_d = READ;
new_req_d = 1'b1;
end
end
end
WRITE: begin
if (spi_done) begin
first_write_d = 1'b0;
if (auto_inc_q && !first_write_q)
reg_addr_d = reg_addr_q + 1'b1;
new_req_d = 1'b1;
write_value_d = spi_dout;
end
end
READ: begin
if (spi_done) begin
if (auto_inc_q)
reg_addr_d = reg_addr_q + 1'b1;
new_req_d = 1'b1;
end
end
default: state_d = IDLE;
endcase
if (frame_end)
state_d = IDLE;
end
always @(posedge clk) begin
if (n_rdy) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
write_value_q <= write_value_d;
write_q <= write_d;
auto_inc_q <= auto_inc_d;
reg_addr_q <= reg_addr_d;
new_req_q <= new_req_d;
first_write_q <= first_write_d;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:17 05/31/2016
// Design Name:
// Module Name: prueba_lectura_config_reloj
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module prueba_lectura_config_reloj
(
input wire clk, reset,
input wire ps2data,
input wire ps2clk,
inout [7:0]dato,
output wire AD, CS, WR, RD,
output [7:0] RGB,
output hsync, vsync
);
//Conexiones internas
reg [7:0]in_port;
wire [7:0]out_port;
wire [7:0]port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
wire interrupt;
// conexiones banco de registros a VGA
wire [7:0]out_seg_hora,out_min_hora,out_hora_hora;
wire [7:0]out_dia_fecha,out_mes_fecha,out_jahr_fecha;
wire [7:0]out_seg_timer,out_min_timer,out_hora_timer;
///////////////////////////// hold's
wire hold_seg_hora;
wire hold_min_hora;
wire hold_hora_hora;
wire hold_dia_fecha;
wire hold_mes_fecha;
wire hold_jahr_fecha;
wire hold_dia_semana;
wire hold_seg_timer;
wire hold_min_timer;
wire hold_hora_timer;
// wire hold_banderas_config;
//////////////////////
//Conexiones de controlador RTC
wire fin_lectura_escritura;
wire [7:0] out_dato;
assign interrupt = 1'b0;
microcontrolador instancia_microcontrolador
(
.clk(clk),
.reset(reset),
.interrupt(interrupt),
.in_port(in_port),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.read_strobe(read_strobe),
.interrupt_ack(),
.port_id(port_id),
.out_port(out_port)
);
controlador_VGA instancia_controlador_VGA
(
.clock(clk),
.reset(reset),
.digit0_HH(out_hora_hora[3:0]), .digit1_HH(out_hora_hora[7:4]), .digit0_MM(out_min_hora[3:0]), .digit1_MM(out_min_hora[7:4]), .digit0_SS(out_seg_hora[3:0]), .digit1_SS(out_seg_hora[7:4]),//
.digit0_DAY(out_dia_fecha[3:0]), .digit1_DAY(out_dia_fecha[7:4]), .digit0_MES(out_mes_fecha[3:0]), .digit1_MES(out_mes_fecha[7:4]), .digit0_YEAR(out_jahr_fecha[3:0]), .digit1_YEAR(out_jahr_fecha[7:4]),//
.digit0_HH_T(out_hora_timer[3:0]), .digit1_HH_T(out_hora_timer[7:4]), .digit0_MM_T(out_min_timer[3:0]), .digit1_MM_T(out_min_timer[7:4]), .digit0_SS_T(out_seg_timer[3:0]), .digit1_SS_T(out_seg_timer[7:4]),//Decenas y unidades para los números en pantalla (18 inputs de 3 bits)
.AM_PM(1'b0),
.config_mode(2'b0),
.cursor_location(2'b0),
.formato_hora(1'b1),
.estado_alarma(1'b0),
.hsync(hsync),
.vsync(vsync),
.RGB(RGB)
);
memoria_registros_VGA instancia_memoria_registros_VGA
(
.clk(clk),
.reset(reset),
.cs_seg_hora(1'b0),
.cs_min_hora(1'b0),
.cs_hora_hora(1'b0),
.cs_dia_fecha(1'b0),
.cs_mes_fecha(1'b0),
.cs_jahr_fecha(1'b0),
.cs_seg_timer(1'b0),
.cs_min_timer(1'b0),
.cs_hora_timer(1'b0),
.hold_seg_hora(hold_seg_hora),
.hold_min_hora(hold_min_hora),
.hold_hora_hora(hold_hora_hora),
.hold_dia_fecha(hold_dia_fecha),
.hold_mes_fecha(hold_mes_fecha),
.hold_jahr_fecha(hold_jahr_fecha),
.hold_seg_timer(hold_seg_timer),
.hold_min_timer(hold_min_timer),
.hold_hora_timer(hold_hora_timer),
.hold_banderas_config(1'b1),
.data_PicoBlaze(out_port),
.count_seg_hora(8'b0),
.count_min_hora(8'b0),
.count_hora_hora(8'b0),
.count_dia_fecha(8'b0),
.count_mes_fecha(8'b0),
.count_jahr_fecha(8'b0),
.count_seg_timer(8'b0),
.count_min_timer(8'b0),
.count_hora_timer(8'b0),
.out_seg_hora(out_seg_hora),
.out_min_hora(out_min_hora),
.out_hora_hora(out_hora_hora),
.out_dia_fecha(out_dia_fecha),
.out_mes_fecha(out_mes_fecha),
.out_jahr_fecha(out_jahr_fecha),
.out_seg_timer(out_seg_timer),
.out_min_timer(out_min_timer),
.out_hora_timer(out_hora_timer),
.out_banderas_config()
);
deco_hold_registros instancia_deco_hold_registros (
.write_strobe(write_strobe),
.port_id(port_id),
.hold_seg_hora(hold_seg_hora),
.hold_min_hora(hold_min_hora),
.hold_hora_hora(hold_hora_hora),
.hold_dia_fecha(hold_dia_fecha),
.hold_mes_fecha(hold_mes_fecha),
.hold_jahr_fecha(hold_jahr_fecha),
.hold_seg_timer(hold_seg_timer),
.hold_min_timer(hold_min_timer),
.hold_hora_timer(hold_hora_timer)
);
escritor_lector_rtc_2 instancia_escritor_lector_rtc_2 (
.clk(clk),
.reset(reset),
.in_dato(out_port),
.port_id(port_id),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.read_strobe(read_strobe),
.reg_a_d(AD),
.reg_cs(CS),
.reg_rd(RD),
.reg_wr(WR),
.out_dato(out_dato),
.flag_done(fin_lectura_escritura),
.dato(dato)
);
controlador_teclado_ps2 instancia_controlador_teclado_ps2 (
.clk(clk),
.reset(reset),
.ps2data(ps2data),
.ps2clk(ps2clk),
.port_id(port_id),
.read_strobe(read_strobe),
.ascii_code(ascii_code)
);
//Decodificación del puerto de entrada del microcontrolador
always@(posedge clk)
begin
case (port_id)
8'h0F : in_port <= fin_lectura_escritura;
8'h10 : in_port <= out_dato;
8'h02 : in_port <= ascii_code;
default : in_port <= 8'bXXXXXXXX;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; namespace MCMF { const int N = 1e6; const long long inf = 1e18; struct node { int to, next, v, cap; } edge[N]; int st[2000], cnt, S, T, n; int d[N], from[2000]; int can_flow[2000]; long long dis[2000]; bool bz[N]; void init(int s, int t, int nn) { cnt = 1; n = nn; S = s, T = t; for (int i = 0; i <= n; i++) st[i] = 0; } void add_edge(int x, int y, int v, int cap) { edge[++cnt].to = y; edge[cnt].next = st[x]; edge[cnt].v = v; edge[cnt].cap = cap; st[x] = cnt; edge[++cnt].to = x; edge[cnt].next = st[y]; edge[cnt].v = -v; edge[cnt].cap = 0; st[y] = cnt; } bool spfa() { for (int i = 0; i <= n; i++) dis[i] = -inf; dis[S] = 0; d[1] = S; bz[S] = 1; can_flow[S] = 1e9; int l = 0, r = 1; while (l != r) { int x = d[l = l % n + 1]; for (int i = st[x]; i; i = edge[i].next) if (dis[edge[i].to] < dis[x] + edge[i].v && edge[i].cap) { dis[edge[i].to] = dis[x] + edge[i].v; from[edge[i].to] = i; can_flow[edge[i].to] = min(can_flow[x], edge[i].cap); if (!bz[edge[i].to]) bz[d[r = r % n + 1] = edge[i].to] = 1; } bz[d[l]] = 0; } return dis[T] != -inf; } pair<long long, int> gao() { long long v = 0; int flow = 0; while (spfa()) { int x = T; int tmp = can_flow[T]; flow += tmp; v += 1ll * dis[T] * tmp; while (x != S) { edge[from[x]].cap -= tmp; edge[from[x] ^ 1].cap += tmp; x = edge[from[x] ^ 1].to; } } return make_pair(v, flow); } } // namespace MCMF const int N = 2000; int n, rot1, rot2, s, ss, t, tt; vector<int> g1[N], g2[N]; int v[N], lim1[N], lim2[N]; void dfs1(int x, int fa) { if (lim1[x]) { MCMF::add_edge(ss, x, 0, lim1[x]); MCMF::add_edge(fa, tt, 0, lim1[x]); } else { MCMF::add_edge(fa, x, 0, 1e9); } for (auto u : g1[x]) if (u != fa) dfs1(u, x); } void dfs2(int x, int fa) { if (fa == t) fa -= n; if (lim2[x]) { MCMF::add_edge(ss, fa + n, 0, lim2[x]); MCMF::add_edge(x + n, tt, 0, lim2[x]); } else { MCMF::add_edge(x + n, fa + n, 0, 1e9); } for (auto u : g2[x]) if (u != fa) dfs2(u, x); } int main() { scanf( %d %d %d , &n, &rot1, &rot2); s = n * 2 + 1, t = n * 2 + 2, ss = n * 2 + 3, tt = n * 2 + 4; MCMF::init(ss, tt, tt); for (int i = 1; i <= n; i++) scanf( %d , &v[i]), MCMF::add_edge(i, i + n, v[i], 1); for (int i = 1; i < n; i++) { int x, y; scanf( %d%d , &x, &y); g1[x].push_back(y); g1[y].push_back(x); } for (int i = 1; i < n; i++) { int x, y; scanf( %d%d , &x, &y); g2[x].push_back(y); g2[y].push_back(x); } int q1; scanf( %d , &q1); while (q1--) { int x, k; scanf( %d %d , &x, &k); lim1[x] = k; } int q2; scanf( %d , &q2); while (q2--) { int x, k; scanf( %d %d , &x, &k); lim2[x] = k; } dfs1(rot1, s); dfs2(rot2, t); MCMF::add_edge(t, s, 0, 1e9); long long ans = MCMF::gao().first; for (int i = MCMF::st[ss]; i; i = MCMF::edge[i].next) if (MCMF::edge[i].cap) { printf( -1 ); return 0; } MCMF::S = s; MCMF::T = t; MCMF::st[s] = MCMF::edge[MCMF::st[s]].next; MCMF::st[t] = MCMF::edge[MCMF::st[t]].next; ans += MCMF::gao().first; printf( %lld n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_2_V
`define SKY130_FD_SC_HD__A21BO_2_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_2_V
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// DDC block
module ddc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_cordic_out, q_cordic_out;
wire [31:0] phase;
wire strobe1, strobe2;
reg [3:0] strobe_ctr1,strobe_ctr2;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr2 <= #1 4'd0;
else if(strobe2)
strobe_ctr2 <= #1 4'd0;
else
strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr1 <= #1 4'd0;
else if(strobe1)
strobe_ctr1 <= #1 4'd0;
else if(strobe2)
strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
assign strobe2 = enable & ( strobe_ctr2 == rate2 );
assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
assign strobe = strobe1;
function [2:0] log_ceil;
input [3:0] val;
log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
endfunction
wire [2:0] shift1 = log_ceil(rate1);
wire [2:0] shift2 = log_ceil(rate2);
cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
cordic(.clock(clock), .reset(reset), .enable(enable),
.xi(i_in), .yi(q_in), .zi(phase[31:32-zw]),
.xo(i_cordic_out), .yo(q_cordic_out), .zo() );
cic_decim_2stage #(.bw(bw),.N(4))
decim_i(.clock(clock),.reset(reset),.enable(enable),
.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
.signal_in(i_cordic_out),.signal_out(i_out));
cic_decim_2stage #(.bw(bw),.N(4))
decim_q(.clock(clock),.reset(reset),.enable(enable),
.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
.signal_in(q_cordic_out),.signal_out(q_out));
phase_acc #(.resolution(32))
nco (.clk(clock),.reset(reset),.enable(enable),
.freq(freq),.phase(phase));
endmodule
|
#include <bits/stdc++.h> using namespace std; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } template <typename T> string to_str(T str) { stringstream stream; stream << str; return stream.str(); } template <typename T> int to_int(T num) { int val; stringstream stream; stream << num; stream >> val; return val; } vector<string> split(const string& s, char delim) { vector<string> elems; stringstream ss(s); string item; while (getline(ss, item, delim)) elems.push_back(item); return elems; } const int dr[] = {-1, -1, 0, 1, 1, 1, 0, -1}; const int dc[] = {0, 1, 1, 1, 0, -1, -1, -1}; const int T2 = 105; const int T3 = 1005; const int T4 = 10005; const int T5 = 100005; int a[T3], b[T3]; const int M = 475; bool check(int s, int p) { int i = (s / 50) % M; int loop = 25; while (loop--) { i = (i * 96 + 42) % M; if (26 + i == p) { return true; } } return false; } int main() { ios_base::sync_with_stdio(0); int p, x, y; cin >> p >> x >> y; int s = x; bool f = 0; while (s >= y) { if (check(s, p)) { f = 1; break; } s -= 50; } if (!f) { s = x; while (1) { if (check(s, p)) { f = 1; break; } s += 50; } } int diff = s - x; if (diff < 0) cout << 0 n ; else cout << ceil(diff * 1.0 / 100) << n ; return 0; }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:35:26 02/07/2014
// Design Name:
// Module Name: dp_memory
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dp_memory (
input wire clk, // 28MHz
input wire [20:0] a1,
input wire [20:0] a2,
input wire oe1_n,
input wire oe2_n,
input wire we1_n,
input wire we2_n,
input wire [7:0] din1,
input wire [7:0] din2,
output wire [7:0] dout1,
output wire [7:0] dout2,
output reg [20:0] a,
inout wire [7:0] d,
output reg ce_n,
output reg oe_n,
output reg we_n
);
parameter
ACCESO_M1 = 1,
READ_M1 = 2,
WRITE_M1 = 3,
ACCESO_M2 = 4,
READ_M2 = 5,
WRITE_M2 = 6;
reg [7:0] data_to_write;
reg enable_input_to_sram;
reg [7:0] doutput1;
reg [7:0] doutput2;
reg write_in_dout1;
reg write_in_dout2;
reg [2:0] state = ACCESO_M1;
reg [2:0] next_state;
always @(posedge clk) begin
state <= next_state;
end
always @* begin
a = 0;
oe_n = 0;
we_n = 1;
ce_n = 0;
enable_input_to_sram = 0;
next_state = ACCESO_M1;
data_to_write = 8'h00;
write_in_dout1 = 0;
write_in_dout2 = 0;
case (state)
ACCESO_M1: begin
a = a1;
if (we1_n == 1) begin
next_state = READ_M1;
end
else begin
oe_n = 1;
next_state = WRITE_M1;
end
end
READ_M1: begin
if (we1_n == 1) begin
a = a1;
write_in_dout1 = 1;
end
next_state = ACCESO_M2;
end
WRITE_M1: begin
if (we1_n == 0) begin
a = a1;
enable_input_to_sram = 1;
data_to_write = din1;
oe_n = 1;
we_n = 0;
end
next_state = ACCESO_M2;
end
ACCESO_M2: begin
a = a2;
if (we2_n == 1) begin
next_state = READ_M2;
end
else begin
oe_n = 1;
next_state = WRITE_M2;
end
end
READ_M2: begin
if (we2_n == 1) begin
a = a2;
write_in_dout2 = 1;
end
next_state = ACCESO_M1;
end
WRITE_M2: begin
if (we2_n == 0) begin
a = a2;
enable_input_to_sram = 1;
data_to_write = din2;
oe_n = 1;
we_n = 0;
end
next_state = ACCESO_M1;
end
endcase
end
assign d = (enable_input_to_sram)? data_to_write : 8'hZZ;
assign dout1 = (oe1_n)? 8'hZZ : doutput1;
assign dout2 = (oe2_n)? 8'hZZ : doutput2;
always @(posedge clk) begin
if (write_in_dout1)
doutput1 <= d;
else if (write_in_dout2)
doutput2 <= d;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<long long int, pair<int, bool> > p[200005 << 1]; long long int a[200005], tree[200005 << 2][2]; long long int get(int n, int b, int e, int i, int j, bool c) { if (i > j || j < b || e < i) return 0; if (i <= b && j >= e) return tree[n][c]; int l, r, m; m = (b + e) >> 1; l = (n << 1) + 1; r = l + 1; return max(get(l, b, m, i, j, c), get(r, m + 1, e, i, j, c)); } void update(int n, int b, int e, int i, long long int v, bool c) { if (i < b || i > e) return; if (b == e) { tree[n][c] = v; return; } int l, r, m; m = (b + e) >> 1; l = (n << 1) + 1; r = l + 1; update(l, b, m, i, v, c); update(r, m + 1, e, i, v, c); tree[n][c] = max(tree[l][c], tree[r][c]); } int main() { int n; long long int t; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); p[i] = make_pair(a[i] - i, make_pair(i, 1)); if (i > 0) p[i + n - 1] = make_pair(a[i] - i + 1, make_pair(i - 1, 0)); } int m = 2 * n - 1; sort(p, p + m); for (int i = 0; i < m; i++) { t = get(0, 0, n - 1, 0, p[i].second.first - 1, 1); if (!p[i].second.second) t = max(t, get(0, 0, n - 1, 0, p[i].second.first - 1, 0)); update(0, 0, n - 1, p[i].second.first, t + 1, p[i].second.second); } printf( %lld n , max(0ll, n - 1 - max(tree[0][1], tree[0][0]))); return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; ll n, m; cin >> n >> m; std::vector<int> a(n + 2); n = n + 2; a[0] = 0; a[n - 1] = m; for (int i = 1; i <= n; i++) cin >> a[i]; ll v[n][2]; v[n - 1][0] = 0; v[n - 1][1] = 0; for (int i = n - 2; i >= 0; i--) { v[i][0] = v[i + 1][1]; v[i][1] = (a[i + 1] - a[i]) + v[i + 1][0]; } ll ans = v[0][1]; ll cur = 0; for (int i = 0; i < n - 1; i++) { int f; if (i % 2 == 0) f = 1; else f = 0; if (f == 1) { if (a[i + 1] - a[i] > 1) { ans = max(ans, cur + a[i + 1] - 1 - a[i] + v[i + 1][1]); } cur += a[i + 1] - a[i]; } else { if (a[i + 1] - a[i] > 1) { ans = max(ans, cur + a[i + 1] - (a[i] + 1) + v[i + 1][0]); } } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int dp[50004][8]; int main() { int m, n; cin >> m >> n; for (int i = 1; i <= m; i++) { for (int j = 1; j <= n; j++) cin >> dp[i][j]; } for (int i = 1; i <= m; i++) dp[i][1] += dp[i - 1][1]; for (int i = 1; i <= n; i++) dp[1][i] += dp[1][i - 1]; for (int i = 2; i <= m; i++) { for (int j = 2; j <= n; j++) { if (dp[i - 1][j] >= dp[i][j - 1]) dp[i][j] += dp[i - 1][j]; else dp[i][j] += dp[i][j - 1]; } } for (int i = 1; i <= m; i++) cout << dp[i][n] << ; return 0; }
|
module top;
reg a, q, qb;
reg pass;
always_comb q = a !== 1'bx;
always_comb qb = a === 1'bx;
initial begin
pass = 1'b1;
#0;
// This second delay is needed for vlog95 since it uses #0 to create
// the T0 trigger. vvp also needs it since it puts the event in the
// inactive queue just like a #0 delay.
#0;
if (q !== 1'b0) begin
$display("Expected q = 1'b0 with the default 1'bx input, got %b", q);
pass = 1'b0;
end
if (qb !== 1'b1) begin
$display("Expected qb = 1'b1 with the default 1'bx input, got %b", qb);
pass = 1'b0;
end
#1;
a = 1'b0;
#0;
if (q !== 1'b1) begin
$display("Expected q = 1'b1 with an explicit 1'b0 input, got %b", q);
pass = 1'b0;
end
#1;
a = 1'b1;
#0;
if (q !== 1'b1) begin
$display("Expected q = 1'b1 with an explicit 1'b1 input, got %b", q);
pass = 1'b0;
end
#1;
a = 1'bz;
#0;
if (q !== 1'b1) begin
$display("Expected q = 1'b1 with an explicit 1'bz input, got %b", q);
pass = 1'b0;
end
#1;
a = 1'bx;
#0;
if (q !== 1'b0) begin
$display("Expected q = 1'b0 with an explicit 1'bx input, got %b", q);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > v[100000]; int f[100000]; int d[100000]; void dfs(int x) { int i; for (i = 0; i < v[x].size(); i++) { if (f[v[x][i].first] == 0) { d[v[x][i].first] = d[x] + v[x][i].second; f[v[x][i].first] = 1; dfs(v[x][i].first); } } } int main() { int n, i, j; long long sum = 0; scanf( %d , &n); for (i = 0; i < n - 1; i++) { int x, y, w; scanf( %d %d %d , &x, &y, &w); v[x - 1].push_back(make_pair(y - 1, w)); v[y - 1].push_back(make_pair(x - 1, w)); sum += w * 2; } f[0] = 1; dfs(0); sort(d, d + n); sum -= d[n - 1]; printf( %I64d n , sum); return 0; }
|
#include <bits/stdc++.h> using namespace std; char dirs[100001]; int todo[4]; int main() { int n, fx, fy, tx, ty; string wind; cin >> n >> fx >> fy >> tx >> ty >> wind; memcpy(dirs, wind.c_str(), n); memset(todo, 0, sizeof(todo)); if (fx < tx) todo[0] = tx - fx; if (fy < ty) todo[3] = ty - fy; if (fx > tx) todo[2] = fx - tx; if (fy > ty) todo[1] = fy - ty; for (int i = 0; i < n; i++) { switch (dirs[i]) { case E : if (todo[0]) todo[0]--; break; case S : if (todo[1]) todo[1]--; break; case W : if (todo[2]) todo[2]--; break; case N : if (todo[3]) todo[3]--; break; } if (todo[0] == 0 && todo[1] == 0 && todo[2] == 0 && todo[3] == 0) { cout << i + 1 << endl; return 0; } } cout << -1 << endl; return 0; }
|
`timescale 1ns / 1ps
module MGIA(
input CLK_I_50MHZ,
input RST_I,
output CLK_O_25MHZ,
output HSYNC_O,
output VSYNC_O,
output [2:0] RED_O,
output [2:0] GRN_O,
output [2:1] BLU_O,
output [13:1] MGIA_ADR_O,
input [15:0] MGIA_DAT_I,
output MGIA_CYC_O,
output MGIA_STB_O,
input MGIA_ACK_I
);
wire pen;
wire clk25mhz;
wire vga_refresh;
wire vga_fetch;
wire odd_line;
wire [ 5:0] sh_adr;
wire [15:0] sh_dat;
wire [ 5:0] vfb_ctr;
wire [15:0] vfb_dat;
wire vfb_we;
assign RED_O = {3{pen}};
assign GRN_O = {3{pen}};
assign BLU_O = {2{pen}};
assign CLK_O_25MHZ = clk25mhz;
TIMEBASE tb(
.RST_I(RST_I),
.CLK_I_50MHZ(CLK_I_50MHZ),
.CLK_O_25MHZ(clk25mhz),
.HSYNC_O(HSYNC_O),
.VSYNC_O(VSYNC_O),
.VFEN_O(vga_fetch),
.VREN_O(vga_refresh),
.ODD_O(odd_line)
);
LINE_BUFFERS lb(
.CLK_I(clk25mhz),
.ODD_I(odd_line),
.F_ADR_I(sh_adr),
.F_DAT_O(sh_dat),
.S_ADR_I(vfb_ctr),
.S_DAT_I(vfb_dat),
.S_WE_I(vfb_we)
);
SHIFTER sh(
.CLK_I_25MHZ(clk25mhz),
.VREN_I(vga_refresh & !odd_line),
.F_ADR_O(sh_adr),
.F_DAT_I(sh_dat),
.PEN_O(pen)
);
VIDEO_FETCHER vf(
.RST_I(RST_I),
.CLK_I_25MHZ(clk25mhz),
.VSYNC_I(VSYNC_O),
.VFEN_I(vga_fetch & odd_line),
.RAM_ADR_O(MGIA_ADR_O),
.RAM_CYC_O(MGIA_CYC_O),
.RAM_STB_O(MGIA_STB_O),
.RAM_ACK_I(MGIA_ACK_I),
.RAM_DAT_I(MGIA_DAT_I),
.LB_ADR_O(vfb_ctr),
.LB_DAT_O(vfb_dat),
.LB_WE_O(vfb_we)
);
endmodule
|
/*
Bank of GPRs.
00..0F: R0..R15
10..1F: CS0..CS15
20..2F: F0L..F15L
30..3F: F16L..F31L
/ 40..4F: R0H..R15H
40..47: R0_B..R7_B
48..4F: Reserved
50..5F: CC0..CC15
60..6F: F0H..F15H
70..7F: F16H..F31H
Special Cases (Handled Externally)
58: Opcode D
59: Opcode S
5A: Opcode T
5C: Opcode PC4A2 (Op PC+4 aligned to 2-byte boundary)
5D: Opcode PC4A4 (Op PC+4 aligned to 4-byte boundary)
5E: Opcode Imm
5F: ZZR (Always read as Zero)
Mapping for BJX1:
FR0 =F0H , FR1 =F0L , XF0 =F1H , XF1 =F1L ,
FR2 =F2H , FR3 =F2L , XF2 =F3H , XF3 =F3L ,
FR4 =F4H , FR5 =F4L , XF4 =F5H , XF5 =F5L ,
FR6 =F6H , FR7 =F6L , XF6 =F7H , XF7 =F7L ,
FR8 =F8H , FR9 =F8L , XF8 =F9H , XF9 =F9L ,
FR10=F10H, FR11=F10L, XF10=F11H, XF11=F11L,
FR12=F12H, FR13=F12L, XF12=F13H, XF13=F13L,
FR14=F14H, FR15=F14L, XF14=F15H, XF15=F15L,
...
CS0=MACH
CS1=MACL
CS2=PR
CS3=SGR
CS4=?
CS5=FPUL
CS6=FPSCR
CS7=?
..
CS14=?
CS15=DBR
CC0=SR
CC1=GBR
CC2=VBR
CC3=SSR
CC4=SPC
CC5=?
CC6=?
CC7=PC
*/
parameter[5:0] REGS_R0 = 6'h00;
parameter[5:0] REGS_R15 = 6'h0F;
parameter[5:0] REGS_F0 = 6'h20;
parameter[5:0] REGS_F15 = 6'h2F;
parameter[5:0] REGS_F16 = 6'h30;
parameter[5:0] REGS_F31 = 6'h3F;
// parameter[5:0] REGS_PR = 6'h12;
// parameter[3:0] CREG_SR = 4'h00;
// parameter[3:0] CREG_PC = 4'h0E;
// parameter[4:0] CREG_LR = 5'h01;
parameter[6:0] REG_R0 = 7'h00;
parameter[6:0] REG_R15 = 7'h0F;
parameter[6:0] REG_F0 = 7'h20;
parameter[6:0] REG_F15 = 7'h2F;
parameter[6:0] REG_F16 = 7'h30;
parameter[6:0] REG_F31 = 7'h3F;
parameter[6:0] REG_CS0 = 7'h10;
parameter[6:0] REG_MACH = 7'h10;
parameter[6:0] REG_MACL = 7'h11;
parameter[6:0] REG_PR = 7'h12;
parameter[6:0] REG_SGR = 7'h13;
parameter[6:0] REG_FPUL = 7'h15;
parameter[6:0] REG_FPSCR = 7'h16;
parameter[6:0] REG_DBR = 7'h1F;
parameter[6:0] REG_CC0 = 7'h50;
parameter[6:0] REG_SR = 7'h50;
parameter[6:0] REG_GBR = 7'h51;
parameter[6:0] REG_VBR = 7'h52;
parameter[6:0] REG_SSR = 7'h53;
parameter[6:0] REG_SPC = 7'h54;
parameter[6:0] REG_PC = 7'h57;
parameter[6:0] REG_PC4A2 = 7'h5C;
parameter[6:0] REG_PC4A4 = 7'h5D;
parameter[6:0] REG_IMM = 7'h5E;
parameter[6:0] REG_ZZR = 7'h5F;
module GpReg(
clk,
isWrD,
isQwD,
idRegD,
dataD,
idReg1,
data1,
idReg2,
data2,
idReg3,
data3
);
input clk; //clock
input isWrD; //Is Write
input isQwD; //Is QuadWord
input[6:0] idRegD;
input[63:0] dataD;
input[6:0] idReg1;
input[6:0] idReg2;
input[6:0] idReg3;
output[63:0] data1;
output[63:0] data2;
output[63:0] data3;
reg[31:0] regs_lo[64]; //GPRs and FPRs
reg[31:0] regs_hi[64];
reg[31:0] creg_lo[16]; //Control Registers
reg[31:0] creg_hi[16];
reg[31:0] reg_pc; //PC register, special
reg[31:0] reg_pr; //PR register, special
reg[31:0] reg_sr; //SR register, special
// reg[6:0] tIdRegDLo;
// reg[6:0] tIdRegDHi;
// reg[6:0] tIdReg1Lo;
// reg[6:0] tIdReg1Hi;
// reg[6:0] tIdReg2Lo;
// reg[6:0] tIdReg2Hi;
// reg[6:0] tIdReg3Lo;
// reg[6:0] tIdReg3Hi;
reg[5:0] tIdRegDLo;
reg[5:0] tIdReg1Lo;
reg[5:0] tIdReg2Lo;
reg[5:0] tIdReg3Lo;
// reg rb_curBank;
// reg rb_reqBank;
// reg rb_isSwap;
// reg[3:0] rb_tSwapBank;
// reg[3:0] rb_tNextSwapBank;
always @ (clk) begin
// tIdRegDLo = idRegD;
// tIdRegDHi = idRegD | (7'h40);
// if(rb_isSwap)
// begin
// if(rb_tSwapBank[0])
// end
tIdRegDLo = idRegD[5:0];
tIdReg1Lo = idReg1[5:0];
tIdReg2Lo = idReg2[5:0];
tIdReg3Lo = idReg3[5:0];
// if(idReg1!=REG_ZZR)
if(idReg1[5:4]!=2'b01)
begin
if(idReg1[6])
begin
data1[31: 0] = regs_hi[tIdReg1Lo];
data1[63:32] = 32'h0000_0000 ;
end
else
begin
data1[31: 0] = regs_lo[tIdReg1Lo];
data1[63:32] = regs_hi[tIdReg1Lo];
end
end
else
begin
if(idReg1[6])
begin
data1[31: 0] = creg_lo[tIdReg1Lo[3:0]];
data1[63:32] = creg_hi[tIdReg1Lo[3:0]];
end
else
begin
data1[31: 0] = regs_lo[tIdReg1Lo];
data1[63:32] = regs_hi[tIdReg1Lo];
end
// data1 = 64'h0000_0000_0000_0000;
end
// if(idReg2!=REG_ZZR)
if(idReg2[5:4]!=2'b01)
begin
if(idReg2[6])
begin
data2[31: 0] = regs_hi[tIdReg2Lo];
data2[63:32] = 32'h0000_0000 ;
end
else
begin
data2[31: 0] = regs_lo[tIdReg2Lo];
data2[63:32] = regs_hi[tIdReg2Lo];
end
end
else
begin
if(idReg2[6])
begin
data2[31: 0] = creg_lo[tIdReg2Lo[3:0]];
data2[63:32] = creg_hi[tIdReg2Lo[3:0]];
end
else
begin
data2[31: 0] = regs_lo[tIdReg2Lo];
data2[63:32] = regs_hi[tIdReg2Lo];
end
// data2 = 64'h0000_0000_0000_0000;
end
// if(idReg3!=REG_ZZR)
if(idReg3[5:4]!=2'b01)
begin
if(idReg3[6])
begin
data3[31: 0] = regs_hi[tIdReg3Lo];
data3[63:32] = 32'h0000_0000 ;
end
else
begin
data3[31: 0] = regs_lo[tIdReg3Lo];
data3[63:32] = regs_hi[tIdReg3Lo];
end
end
else
begin
if(idReg3[6])
begin
data3[31: 0] = creg_lo[tIdReg3Lo[3:0]];
data3[63:32] = creg_hi[tIdReg3Lo[3:0]];
end
else
begin
data3[31: 0] = regs_lo[tIdReg3Lo];
data3[63:32] = regs_hi[tIdReg3Lo];
end
// data3 = 64'h0000_0000_0000_0000;
end
end
always @ (posedge clk) begin
if(isWrD==1'b1)
begin
if(idRegD[5:4]!=2'b01)
begin
if(isQwD==1'b1)
begin
$display("R[%X]Q=%X", tIdRegDLo, dataD);
regs_lo[tIdRegDLo] <= dataD[31:0];
regs_hi[tIdRegDLo] <= dataD[63:32];
end
else
begin
$display("R[%X]D=%X", tIdRegDLo, dataD);
if(idRegD[6])
regs_hi[tIdRegDLo] <= dataD[31:0];
else
regs_lo[tIdRegDLo] <= dataD[31:0];
end
end
else
begin
$display("CSR[%X]=%X", tIdRegDLo, dataD);
if(idRegD[6])
begin
creg_lo[tIdRegDLo[3:0]] <= dataD[31:0];
if(isQwD==1'b1)
creg_hi[tIdRegDLo[3:0]] <= dataD[63:32];
end
else
begin
// sreg_lo[tIdRegDLo[3:0]] <= dataD[31:0];
// if(isQwD==1'b1)
// sreg_hi[tIdRegDLo[3:0]] <= dataD[63:32];
regs_lo[tIdRegDLo] <= dataD[31:0];
if(isQwD==1'b1)
regs_hi[tIdRegDLo] <= dataD[63:32];
end
end
end
// if(rb_isSwap)
// begin
// rb_isSwap <= rb_isNextSwap;
// rb_tSwapBank = rb_tNextSwapBank;
// end
// else if(rb_curBank!=rb_reqBank)
// begin
// rb_isSwap <= 1;
// rb_tSwapBank = 15;
// end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[200010]; int a[200010]; int ans[50]; int n, k, x; void init() { cin >> n >> k; for (int i = 1; i <= n; i++) cin >> s[i]; for (int i = 1; i <= n; i++) a[i] = (int)s[i] - a + 1; a[++n] = 30; for (int i = 1; i <= 26; i++) { int l; bool flag = 0; for (int j = 1; j <= n; j++) { if (flag == 0 & a[j] == i) { l = j; flag = 1; } if (flag && a[j] != i) { ans[i] += (j - l) / k; flag = 0; } } } } int main() { init(); for (int i = 1; i <= 26; i++) x = max(ans[i], x); cout << x; cin.get(); cin.get(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; if (n % 2 == 0) { cout << 2; } else cout << 1; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long mod1 = 998244353; const double pie = 3.1415926535; unsigned long long power(unsigned long long x, unsigned long long y) { if (y == 0) return 1; else { if (y % 2 == 0) return power(x * x, y / 2); else return x * power(x * x, (y - 1) / 2); } } long long mod_power(long long x, long long y, long long m) { long long r = 1; x = x % m; if (x == 0) return 0; while (y > 0) { if (y & 1) r = (r * x) % m; y = y / 2; x = (x * x) % m; } return r; } long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } vector<long long> extended_Euclid(long long a, long long b) { vector<long long> v(3); if (b == 0) { v[0] = a; v[1] = 1; v[2] = 0; return v; } else { vector<long long> v1 = extended_Euclid(b, a % b); v[0] = v1[0]; v[1] = v1[2]; v[2] = v1[1] - (a / b) * v1[2]; return v; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int TESTS = 1; cin >> TESTS; while (TESTS--) { unsigned long long a; cin >> a; unsigned long long c = 0; c = __builtin_popcount(a); cout << power(2, c) << endl; } }
|
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