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#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int k; cin >> k; map<char, int> dict; for (int i = 0; i < 27; i++) dict[i + a ] = 0; for (int i = 0; i < s.length(); i++) dict[s[i]]++; map<char, int>::iterator it; vector<pair<int, char> > letras; pair<int, char> aux; int distinto; for (it = dict.begin(); it != dict.end(); ++it) { aux = make_pair((*it).second, (*it).first); if (aux.first != 0) letras.push_back(aux); } sort((letras).begin(), (letras).end()); distinto = letras.size(); int l = 0; int j = 0; while (true) { j += letras[l].first; if (j > k) break; l++; if (j == k) break; if (l == distinto) break; } if (l == distinto) { cout << 0 << endl; cout << endl; return 0; } bool ltras[28]; memset(ltras, 0, sizeof(ltras)); for (int i = l; i < letras.size(); i++) { ltras[letras[i].second - a ] = 1; } string res = ; for (int i = 0; i < s.length(); i++) if (ltras[s[i] - a ]) res += s[i]; cout << distinto - l << endl; cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int N; cin >> N; vector<int> a(N); for (int i = 0; i < N; ++i) { scanf( %d , &a[i]); } sort(a.begin(), a.end()); int res = 0; for (int i = 0; i <= N; ++i) { if (a[i] == a[i + 1]) { ++res; ++i; } } cout << res / 2 << endl; return 0; }
|
#include <bits/stdc++.h> long long mpow(long long a, long long n, long long mod) { long long ret = 1; long long b = a; while (n) { if (n & 1) ret = (ret * b) % mod; b = (b * b) % mod; n >>= 1; } return (long long)ret; } using namespace std; int main() { cin.sync_with_stdio(0); int i, j, n, m, k, s; cin >> n >> m >> k >> s; int a[4][10]; for (j = 0; j < 10; j++) a[0][j] = -1e9, a[2][j] = -1e9; for (j = 0; j < 10; j++) a[1][j] = 1e9, a[3][j] = 1e9; for (i = 0; i < n; i++) for (j = 0; j < m; j++) { long long p; cin >> p; a[0][p] = max(a[0][p], i + j); a[1][p] = min(a[1][p], i + j); a[2][p] = max(a[2][p], i - j); a[3][p] = min(a[3][p], i - j); } int p; cin >> p; int ans = -1; for (j = 1; j < s; j++) { int q; cin >> q; ans = max(ans, a[0][p] - a[1][q]); ans = max(ans, a[0][q] - a[1][p]); ans = max(ans, a[2][p] - a[3][q]); ans = max(ans, a[2][q] - a[3][p]); p = q; } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_4_V
`define SKY130_FD_SC_HS__DLRTP_4_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtp_4 (
RESET_B,
D ,
GATE ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE ;
output Q ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlrtp base (
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtp_4 (
RESET_B,
D ,
GATE ,
Q
);
input RESET_B;
input D ;
input GATE ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlrtp base (
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.Q(Q)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_4_V
|
module autoinst_wildcard;
/*AUTOOUTPUT*/
// Newline between AUTO_TEMPLATE and ( gave a templated line number bug
/* autoinst_wildcard_sub AUTO_TEMPLATE
(
.sd0_clk (sd_clk),
.sd0_dqm\(.*\)_l (c@_sd_dqm_[\1]),
.sd0_ba\([0-9]+\) (c@_sd_ba[\1]),
.sd0_adrs@ (c@_sd_adrs[\1]),
.ics@ (c@_ics[\1]),
); */
/*AUTOOUTPUT*/
autoinst_wildcard_sub sub0
(/*AUTOINST*/
// Inouts
.sd_ras_ (sd_ras_),
.sd0_dqm7_l (c0_sd_dqm_[7]), // Templated 9
.sd0_dqm6_l (c0_sd_dqm_[6]), // Templated 9
.sd0_dqm5_l (c0_sd_dqm_[5]), // Templated 9
.sd0_dqm4_l (c0_sd_dqm_[4]), // Templated 9
.sd0_dqm3_l (c0_sd_dqm_[3]), // Templated 9
.sd0_dqm2_l (c0_sd_dqm_[2]), // Templated 9
.sd0_dqm1_l (c0_sd_dqm_[1]), // Templated 9
.sd0_dqm0_l (c0_sd_dqm_[0]), // Templated 9
.sd0_ba1 (c0_sd_ba[1]), // Templated 10
.sd0_ba0 (c0_sd_ba[0]), // Templated 10
.sd0_adrs11 (c0_sd_adrs[11]), // Templated 11
.sd0_adrs10 (c0_sd_adrs[10]), // Templated 11
.sd0_adrs9 (c0_sd_adrs[9]), // Templated 11
.sd0_adrs8 (c0_sd_adrs[8]), // Templated 11
.sd0_adrs7 (c0_sd_adrs[7]), // Templated 11
.sd0_adrs6 (c0_sd_adrs[6]), // Templated 11
.sd0_adrs5 (c0_sd_adrs[5]), // Templated 11
.sd0_adrs4 (c0_sd_adrs[4]), // Templated 11
.sd0_adrs3 (c0_sd_adrs[3]), // Templated 11
.sd0_adrs2 (c0_sd_adrs[2]), // Templated 11
.sd0_adrs1 (c0_sd_adrs[1]), // Templated 11
.sd0_adrs0 (c0_sd_adrs[0]), // Templated 11
.sd0_clk (sd_clk)); // Templated 8
endmodule
// Local Variables:
// verilog-auto-inst-template-numbers: t
// End:
|
#include <bits/stdc++.h> using namespace std; int minimum(int x, int y) { return (x < y ? x : y); } template <typename type> struct even { bool operator()(const type &x, const type &y) const { return x % 2 == 0; } }; template <typename type> struct odd { bool operator()(const type &x, const type &y) const { return x % 2 != 0; } }; bool flusher(int x) { string s; cout << x << endl; fflush(stdout); cin >> s; return s == yes ; } long long int magic(string s) { long long int sum = 0; for (int i = 0; i < s.size(); i++) { sum += s[i] - 0 ; } return sum; } long long int binaryToInt(string s) { long long int n = s.length(); long long int res = 0; long long int base = 1; for (long long int i = n - 1; i >= 0; i--) { if (s[i] == 1 ) { res += base; } base *= 2; } return res; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); int n, k; cin >> n >> k; int length = n * 2 + 1; int res = 0; int x[length]; for (int i = 0; i < length; i++) { cin >> x[i]; } for (int i = 1; i < length; i += 2) { if (x[i] - 1 > x[i - 1] && x[i] - 1 > x[i + 1]) { x[i]--; res++; } if (res == k) { break; } } for (int i = 0; i < length; i++) { cout << x[i] << ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_1_V
`define SKY130_FD_SC_LS__A21OI_1_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21oi_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_1_V
|
module x;
always @(posedge piclk) begin
if (k_i_reset) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
idat_ICErrData_i3 <= 1'h0;
// End of automatics
end
else begin
idat_ICErrData_i3 <= idat_way0_i2[1*OPCWID-1:0*OPCWID];
end
end
// 2010-04-08
localparam MPND = 5;
always @(posedge usclk)
if (~sso_srst_n) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rd_dat_s4 <= 1'h0;
sel_s3 <= 1'h0;
// End of automatics
end
else begin
sel_s3 <= adr_s2[MIDX];
rd_dat_s4 <= (sel_s3 == 1'h0 ? rd_dat0_s3[MPND:0]
: rd_dat1_s3[MPND:0]);
end
// 2010-04-15
integer i;
always @(posedge usclk)
if (~sso_srst_n) begin
for (int j=0; j<10; j++) blob[j] <= 0;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
zsv <= 1'h0;
zz <= 1'h0;
// End of automatics
end
else begin
for (i=0; i<10; i++) blob[i] <= blob[i+1];
for (i=0; i<10; i++) zz <= 1;
for (int isv=0; isv<10; isv++) zsv <= 1;
end
always @(/*AS*/in) begin
for (i=0; i<10; i++) zz <= in;
for (int isv=0; isv<10; isv++) zsv <= in;
end
endmodule
|
// file: timer_exdes.v
//
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module timer_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output [2:1] COUNT
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 2;
genvar count_gen;
// Create reset for the counters
wire reset_int = COUNTER_RESET;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
timer clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]));
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen]) begin
if (reset_int) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> int i, n, k, a, s, j; int main() { for (std::cin >> n >> k; i < k; i++) std::cin >> a, a % 2 ? a++, j++ : 0, s += a; std::cout << (s > 8 * n || s == 8 * n && k == 4 * n && j < n ? NO : YES ); }
|
`timescale 1 ps / 1 ps
module ram_r(
input clk,
input rst,
output wire[ADD_WIDTH-1:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire[BYTE_ENABLE_WIDTH-1:0] ram_r_byteenable,
output wire ram_r_read,
input wire[DATA_WIDTH-1:0] ram_r_readdata,
output wire[BURST_WIDTH_R-1:0] ram_r_burstcount,
output wire [DATA_WIDTH-1:0] data_fifo_in,
input read_fifo_in,
input start_fifo_in,
input [ADD_WIDTH-1:0] address_fifo_in,
input [DATA_WIDTH-1:0] n_burst_fifo_in,
output wire bussy_fifo_in,
output wire empty_fifo_in,
output wire [FIFO_DEPTH_LOG2:0] usedw_fifo_in
);
parameter DATA_WIDTH = 32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4;
parameter MAX_BURST_COUNT_R = 32;
parameter BURST_WIDTH_R = 6;
parameter FIFO_DEPTH_LOG2 = 8;
parameter FIFO_DEPTH = 256;
wire read_complete;
reg [DATA_WIDTH-1:0] reads_pending;
wire read_burst_end;
reg next_r;
wire too_many_reads_pending;
reg [ADD_WIDTH-1:0] read_address;
reg [DATA_WIDTH-1:0] in_n;
reg [DATA_WIDTH-1:0] in_n_2;
wire fifo_full;
wire fifo_empty;
wire [FIFO_DEPTH_LOG2:0] fifo_used;
scfifo master_to_st_fifo(
.aclr(start_fifo_in),
.clock(clk),
.data(ram_r_readdata),
.wrreq(read_complete),
.q(data_fifo_in),
.rdreq(read_fifo_in),
.full(fifo_full),
.empty(fifo_empty),
.usedw(fifo_used[FIFO_DEPTH_LOG2-1:0])
);
defparam master_to_st_fifo.lpm_width = DATA_WIDTH;
defparam master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam master_to_st_fifo.lpm_showahead = "ON";
defparam master_to_st_fifo.use_eab = "ON";
defparam master_to_st_fifo.add_ram_output_register = "OFF"; // FIFO latency of 2
defparam master_to_st_fifo.underflow_checking = "OFF";
defparam master_to_st_fifo.overflow_checking = "OFF";
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n <= 0;
end else begin
if (start_fifo_in == 1) begin
in_n <= n_burst_fifo_in * MAX_BURST_COUNT_R;
end else begin
if (read_complete == 1) begin
in_n <= in_n - 1;
end
end
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n_2 <= 0;
end else begin
if (start_fifo_in == 1) begin
in_n_2 <= n_burst_fifo_in * MAX_BURST_COUNT_R;
end else begin
if (read_burst_end == 1) begin
in_n_2 <= in_n_2 - MAX_BURST_COUNT_R;
end
end
end
end
always @(posedge clk) begin
if (start_fifo_in == 1) begin
read_address <= address_fifo_in;
end else begin
if (read_burst_end == 1) begin
read_address <= read_address + MAX_BURST_COUNT_R * BYTE_ENABLE_WIDTH;
end
end
end
// tracking FIFO
always @ (posedge clk) begin
if (start_fifo_in == 1) begin
reads_pending <= 0;
end else begin
if(read_burst_end == 1) begin
if(ram_r_readdatavalid == 0) begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R;
end else begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R - 1; // a burst read was posted, but a word returned
end
end else begin
if(ram_r_readdatavalid == 0) begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end else begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
always @ (posedge clk) begin
if (start_fifo_in == 1) begin
next_r <= 0;
end else begin
if(read_burst_end == 1) begin
next_r <= 0;
end else begin
if (ram_r_read == 1) begin
next_r <= 1;
end
end
end
end
assign read_complete = (ram_r_readdatavalid == 1);
assign read_burst_end = (ram_r_waitrequest == 0) & (next_r == 1);// & (header_c > 4);
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFO_DEPTH - MAX_BURST_COUNT_R - 4); // make sure there are fewer reads posted than room in the FIFO
assign ram_r_address = read_address;
assign ram_r_read = (too_many_reads_pending == 0) & (in_n_2 != 0);// & (header_c > 4);
assign ram_r_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};
assign ram_r_burstcount = MAX_BURST_COUNT_R;
assign bussy_fifo_in = in_n != 0;
assign empty_fifo_in = fifo_empty;
assign usedw_fifo_in = fifo_used;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000100; int n, q, s[N / 2], f[N / 2], par[N / 2], timer; vector<int> g[N / 2]; void dfs(int x = 1, int pp = 0) { s[x] = ++timer; par[x] = pp; for (auto &it : g[x]) if (it != par[x]) { dfs(it, x); } f[x] = ++timer; } struct node { int sum; bool set; void merge(node <, node &rt) { sum = lt.sum + rt.sum; } } st[N << 2]; void push(int x, int lx, int rx) { if (st[x].set) { st[x].set = 0; st[x].sum = rx - lx + 1; if (lx == rx) return; st[x << 1].set = st[x << 1 | 1].set = 1; } } void bld(int x = 1, int lx = 1, int rx = n + n) { if (lx == rx) { st[x] = {0, 0}; return; } int mid = lx + rx >> 1; bld(x << 1, lx, mid); bld(x << 1 | 1, mid + 1, rx); st[x].merge(st[x << 1], st[x << 1 | 1]); } void modify(bool z, int &u, int &v, int x = 1, int lx = 1, int rx = n + n) { push(x, lx, rx); if (v < lx or u > rx) return; if (u <= lx and rx <= v) { if (z) { st[x].set = 1; push(x, lx, rx); } else { st[x].sum = 0; } return; } int mid = lx + rx >> 1; modify(z, u, v, x << 1, lx, mid); modify(z, u, v, x << 1 | 1, mid + 1, rx); st[x].merge(st[x << 1], st[x << 1 | 1]); } int qry(int &u, int &v, int x = 1, int lx = 1, int rx = n + n) { push(x, lx, rx); if (v < lx or u > rx) return 0; if (u <= lx and rx <= v) return st[x].sum; int mid = lx + rx >> 1; return qry(u, v, x << 1, lx, mid) + qry(u, v, x << 1 | 1, mid + 1, rx); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int u, v, i = 1; i < n; i++) { cin >> u >> v; g[u].emplace_back(v); g[v].emplace_back(u); } timer = 0; dfs(); bld(); cin >> q; int ty, v; while (q--) { cin >> ty >> v; if (ty == 1) { if (par[v] != 0 and qry(s[v], f[v]) != f[v] - s[v] + 1) { modify(0, s[par[v]], s[par[v]]); } modify(1, s[v], f[v]); } else if (ty == 2) { modify(0, s[v], s[v]); } else { cout << (qry(s[v], f[v]) == f[v] - s[v] + 1) << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int prime[500000]; long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } int main() { long long n; cin >> n; long long x = n; for (long long i = 2; i * i <= n; i++) if (n % i == 0) { x = gcd(x, i); x = gcd(x, n / i); } cout << x << endl; }
|
module gate(
off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9
);
input wire signed [31:0] off;
function automatic integer fib(
input integer k
);
if (k == 0)
fib = 0;
else if (k == 1)
fib = 1;
else
fib = fib(k - 1) + fib(k - 2);
endfunction
function automatic integer fib_wrap(
input integer k,
output integer o
);
o = off + fib(k);
endfunction
output integer fib0;
output integer fib1;
output integer fib2;
output integer fib3;
output integer fib4;
output integer fib5;
output integer fib6;
output integer fib7;
output integer fib8;
output integer fib9;
initial begin : blk
integer unused;
unused = fib_wrap(0, fib0);
unused = fib_wrap(1, fib1);
unused = fib_wrap(2, fib2);
unused = fib_wrap(3, fib3);
unused = fib_wrap(4, fib4);
unused = fib_wrap(5, fib5);
unused = fib_wrap(6, fib6);
unused = fib_wrap(7, fib7);
unused = fib_wrap(8, fib8);
unused = fib_wrap(9, fib9);
end
endmodule
module gold(
off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9
);
input wire signed [31:0] off;
output integer fib0 = off + 0;
output integer fib1 = off + 1;
output integer fib2 = off + 1;
output integer fib3 = off + 2;
output integer fib4 = off + 3;
output integer fib5 = off + 5;
output integer fib6 = off + 8;
output integer fib7 = off + 13;
output integer fib8 = off + 21;
output integer fib9 = off + 34;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFSBP_PP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_PP_SYMBOL_V
|
// megafunction wizard: %ALTERA_MULT_ADD v16.0%
// GENERATION: XML
// mult_add_fix8bx2.v
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module mult_add_fix8bx2 (
output wire [16:0] result, // result.result
input wire [7:0] dataa_0, // dataa_0.dataa_0
input wire [7:0] dataa_1, // dataa_1.dataa_1
input wire [7:0] datab_0, // datab_0.datab_0
input wire [7:0] datab_1, // datab_1.datab_1
input wire clock0 // clock0.clock0
);
mult_add_fix8bx2_0002 mult_add_fix8bx2_inst (
.result (result), // result.result
.dataa_0 (dataa_0), // dataa_0.dataa_0
.dataa_1 (dataa_1), // dataa_1.dataa_1
.datab_0 (datab_0), // datab_0.datab_0
.datab_1 (datab_1), // datab_1.datab_1
.clock0 (clock0) // clock0.clock0
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2017 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_mult_add" version="16.0" >
// Retrieval info: <generic name="number_of_multipliers" value="2" />
// Retrieval info: <generic name="width_a" value="8" />
// Retrieval info: <generic name="width_b" value="8" />
// Retrieval info: <generic name="width_result" value="17" />
// Retrieval info: <generic name="gui_4th_asynchronous_clear" value="false" />
// Retrieval info: <generic name="gui_associated_clock_enable" value="false" />
// Retrieval info: <generic name="gui_output_register" value="true" />
// Retrieval info: <generic name="gui_output_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_output_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_output_register_sclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier1_direction" value="ADD" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register1" value="false" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register1_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_addnsub_multiplier_aclr1" value="NONE" />
// Retrieval info: <generic name="gui_addnsub_multiplier_sclr1" value="NONE" />
// Retrieval info: <generic name="gui_multiplier3_direction" value="ADD" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register3" value="false" />
// Retrieval info: <generic name="gui_addnsub_multiplier_register3_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_addnsub_multiplier_aclr3" value="NONE" />
// Retrieval info: <generic name="gui_addnsub_multiplier_sclr3" value="NONE" />
// Retrieval info: <generic name="gui_use_subnadd" value="false" />
// Retrieval info: <generic name="gui_representation_a" value="SIGNED" />
// Retrieval info: <generic name="gui_register_signa" value="false" />
// Retrieval info: <generic name="gui_register_signa_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_register_signa_aclr" value="NONE" />
// Retrieval info: <generic name="gui_register_signa_sclr" value="NONE" />
// Retrieval info: <generic name="gui_representation_b" value="SIGNED" />
// Retrieval info: <generic name="gui_register_signb" value="false" />
// Retrieval info: <generic name="gui_register_signb_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_register_signb_aclr" value="NONE" />
// Retrieval info: <generic name="gui_register_signb_sclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_a" value="true" />
// Retrieval info: <generic name="gui_input_register_a_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_input_register_a_aclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_a_sclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_b" value="true" />
// Retrieval info: <generic name="gui_input_register_b_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_input_register_b_aclr" value="NONE" />
// Retrieval info: <generic name="gui_input_register_b_sclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier_a_input" value="Multiplier input" />
// Retrieval info: <generic name="gui_scanouta_register" value="false" />
// Retrieval info: <generic name="gui_scanouta_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_scanouta_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_scanouta_register_sclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier_b_input" value="Multiplier input" />
// Retrieval info: <generic name="gui_multiplier_register" value="false" />
// Retrieval info: <generic name="gui_multiplier_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_multiplier_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_multiplier_register_sclr" value="NONE" />
// Retrieval info: <generic name="preadder_mode" value="SIMPLE" />
// Retrieval info: <generic name="gui_preadder_direction" value="ADD" />
// Retrieval info: <generic name="width_c" value="16" />
// Retrieval info: <generic name="gui_datac_input_register" value="false" />
// Retrieval info: <generic name="gui_datac_input_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_datac_input_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_datac_input_register_sclr" value="NONE" />
// Retrieval info: <generic name="width_coef" value="18" />
// Retrieval info: <generic name="gui_coef_register" value="false" />
// Retrieval info: <generic name="gui_coef_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_coef_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_coef_register_sclr" value="NONE" />
// Retrieval info: <generic name="coef0_0" value="0" />
// Retrieval info: <generic name="coef0_1" value="0" />
// Retrieval info: <generic name="coef0_2" value="0" />
// Retrieval info: <generic name="coef0_3" value="0" />
// Retrieval info: <generic name="coef0_4" value="0" />
// Retrieval info: <generic name="coef0_5" value="0" />
// Retrieval info: <generic name="coef0_6" value="0" />
// Retrieval info: <generic name="coef0_7" value="0" />
// Retrieval info: <generic name="coef1_0" value="0" />
// Retrieval info: <generic name="coef1_1" value="0" />
// Retrieval info: <generic name="coef1_2" value="0" />
// Retrieval info: <generic name="coef1_3" value="0" />
// Retrieval info: <generic name="coef1_4" value="0" />
// Retrieval info: <generic name="coef1_5" value="0" />
// Retrieval info: <generic name="coef1_6" value="0" />
// Retrieval info: <generic name="coef1_7" value="0" />
// Retrieval info: <generic name="coef2_0" value="0" />
// Retrieval info: <generic name="coef2_1" value="0" />
// Retrieval info: <generic name="coef2_2" value="0" />
// Retrieval info: <generic name="coef2_3" value="0" />
// Retrieval info: <generic name="coef2_4" value="0" />
// Retrieval info: <generic name="coef2_5" value="0" />
// Retrieval info: <generic name="coef2_6" value="0" />
// Retrieval info: <generic name="coef2_7" value="0" />
// Retrieval info: <generic name="coef3_0" value="0" />
// Retrieval info: <generic name="coef3_1" value="0" />
// Retrieval info: <generic name="coef3_2" value="0" />
// Retrieval info: <generic name="coef3_3" value="0" />
// Retrieval info: <generic name="coef3_4" value="0" />
// Retrieval info: <generic name="coef3_5" value="0" />
// Retrieval info: <generic name="coef3_6" value="0" />
// Retrieval info: <generic name="coef3_7" value="0" />
// Retrieval info: <generic name="accumulator" value="NO" />
// Retrieval info: <generic name="accum_direction" value="ADD" />
// Retrieval info: <generic name="gui_ena_preload_const" value="false" />
// Retrieval info: <generic name="gui_accumulate_port_select" value="0" />
// Retrieval info: <generic name="loadconst_value" value="64" />
// Retrieval info: <generic name="gui_accum_sload_register_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_accum_sload_register_aclr" value="NONE" />
// Retrieval info: <generic name="gui_accum_sload_register_sclr" value="NONE" />
// Retrieval info: <generic name="gui_double_accum" value="false" />
// Retrieval info: <generic name="chainout_adder" value="NO" />
// Retrieval info: <generic name="chainout_adder_direction" value="ADD" />
// Retrieval info: <generic name="port_negate" value="PORT_UNUSED" />
// Retrieval info: <generic name="negate_register" value="UNREGISTERED" />
// Retrieval info: <generic name="negate_aclr" value="NONE" />
// Retrieval info: <generic name="negate_sclr" value="NONE" />
// Retrieval info: <generic name="gui_systolic_delay" value="false" />
// Retrieval info: <generic name="gui_systolic_delay_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_systolic_delay_aclr" value="NONE" />
// Retrieval info: <generic name="gui_systolic_delay_sclr" value="NONE" />
// Retrieval info: <generic name="gui_pipelining" value="0" />
// Retrieval info: <generic name="latency" value="0" />
// Retrieval info: <generic name="gui_input_latency_clock" value="CLOCK0" />
// Retrieval info: <generic name="gui_input_latency_aclr" value="NONE" />
// Retrieval info: <generic name="gui_input_latency_sclr" value="NONE" />
// Retrieval info: <generic name="selected_device_family" value="Stratix V" />
// Retrieval info: <generic name="reg_autovec_sim" value="false" />
// Retrieval info: </instance>
// IPFS_FILES : mult_add_fix8bx2.vo
// RELATED_FILES: mult_add_fix8bx2.v, mult_add_fix8bx2_0002.v
|
#include <bits/stdc++.h> using namespace std; long long n, m, T, x, y, x2, y2, a, b, sol = 1; char c; string s; bool t; vector<int> V; vector<int> V2; int p, p2, mn = INT_MAX; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> x; V.push_back(x); } for (int i = 0; i < m; i++) { cin >> x; V2.push_back(x); } p = n - 1; for (int i = 0; i < m - 1; i++) { x = V2[m - i - 1]; while (p >= 0 && V[p] > x) { p--; } if (p < 0) { cout << 0; return 0; } if (V[p] < x) sol = 0; p2 = p; while (p >= 0 && V[p2] >= x) { p2--; } if (p2 < 0) { cout << 0; return 0; } sol *= p - p2; sol %= 998244353; p = p2; } x = V2[0]; for (int i = 0; i <= p; i++) { mn = min(V[i], mn); } if (mn != x) sol = 0; cout << sol; }
|
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module power_trig_tb();
initial $dumpfile("power_trig_tb.vcd");
initial $dumpvars(0,power_trig_tb);
reg clk = 0;
always #10 clk <= ~clk;
reg rst = 1;
initial #100 rst <= 0;
initial
begin
set_stb <= 0;
#1000;
set_stb <= 1;
end
reg [31:0] sample_in;
reg strobe_in;
wire [31:0] sample_out;
wire strobe_out;
reg set_stb, run;
power_trig #(.BASE(0)) power_trig
(.clk(clk), .reset(rst), .enable(1),
.set_stb(set_stb), .set_addr(0), .set_data(32'h000B_B000),
.run(run),
.ddc_out_sample(sample_in), .ddc_out_strobe(strobe_in),
.bb_sample(sample_out), .bb_strobe(strobe_out));
initial sample_in <= 32'h0100_0300;
always @(posedge clk)
if(~strobe_in)
sample_in <= sample_in + 32'h0001_0001;
initial
#100000 $finish;
initial
begin
run <= 0;
#2000 run <= 1;
#30000 run <= 0;
end
always @(posedge clk)
if(rst | ~run)
strobe_in <= 0;
else
strobe_in <= ~strobe_in;
endmodule // power_trig_tb
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2014 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:46:50 02/18/2016
// Design Name:
// Module Name: AR_RXD
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AR_RXD(
input clk, // clock
input in0, // input for 0 signal
input in1, // input for 1 signal
output [22:0] sr_dat, // received data
output [7:0] sr_adr, // received address
output ce_wr // receive completed correctly
);
parameter Fclk = 50000000; // 50 MHz
parameter V100kb = 100000; // 100 kb/s
parameter V50kb = 50000; // 50 kb/s
parameter V12_5kb = 12500; // 12.5 kb/s
parameter m100kb = Fclk/V100kb; // êîëè÷åñòâî òàêòîâ íà îäèí áèò èíôîðìàöèè
parameter m50kb = Fclk/V50kb;
parameter m12_5kb = Fclk/V12_5kb;
reg [31:0]data = 0; // ïîëó÷åííûå äàííûå
reg [6:0] cb = 0; // ñ÷¸ò÷èê áèò
reg [10:0] cc = 0; // cñ÷¸ò÷èê òàêòîâ
reg [1:0] cur_mode = 0; // òåêóùèé ðåæèì ðàáîòû
reg [1:0] prev_mode = 0; // ðåæèì ðàáîòû ïðåäûäóùåãî áèòà
reg [1:0] new_bit = 0; // ïðèõîä íîâîãî áèòà1
reg [0:0] err = 0;
genvar i;
generate for (i = 23; i >= 1; i = i - 1)
begin
assign sr_dat[i-1] = data[24-i];
end
endgenerate
assign sr_adr = data[31:24];
assign parity =^ data[31:1]; // ÷¸òíîñòü
assign ce_wr = (!parity == data[0]) && (cb == 32); // åñëè ÷¸òíîñòü âåðíà, òî ìû ïðàâèëüíî ïîëó÷èëè ÷èñëî
assign sig = (in1 | in0);
assign glitch = ((!sig) && ((cc != m12_5kb) || (cc != m12_5kb-1)) // ñëó÷àéíûé ñáîé
&& ((cc != m50kb) || (cc != m50kb-1))
&& ((cc != m100kb) || (cc != m100kb-1)));
always @(posedge clk) begin
if (!sig & !glitch) prev_mode = cur_mode;
if (!sig & !glitch) cur_mode = ((cc == m12_5kb) || (cc == m12_5kb-1)) ? 1 :
((cc == m50kb) || (cc == m50kb-1)) ? 2 :
((cc == m100kb) || (cc == m100kb-1)) ? 3 :
0;
if ((!sig) && (cur_mode != prev_mode) && (cb != 32)) err <= 1;
data <= ((!err) && (!sig) && (new_bit == 1)) ? ((data << 1) + 1) :
((!err) && (!sig) && (new_bit == 0)) ? (data << 1):
((!err) && (!sig)) ? data:
(sig) ? data :
0;
if ((!err) && (!sig) && (cb != 32) && ((new_bit == 1) ||(new_bit == 0)))
cb <= cb + 1;
new_bit <= (in1 && !glitch && !err) ? 1 : (in0 && !glitch && !err) ? 0 : 2;
if (new_bit == 2) cc <= 0;
if (sig) cc <= cc + 1;
if (glitch) cc <= 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; static inline void canhazfast() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); } template <typename T> T gcd(T a, T b) { return b == 0 ? a : gcd(b, a % b); } template <typename T> T extgcd(T a, T b, T &x, T &y) { T x0 = 1, y0 = 0, x1 = 0, y1 = 1; while (b) { T q = a / b; a %= b; swap(a, b); x0 -= q * x1; swap(x0, x1); y0 -= q * y1; swap(y0, y1); } x = x0; y = y0; return a; } int main() { canhazfast(); static int a[100016]; static char b[100016]; int n; int l = -1000000000, r = 1000000000; cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; cin >> b; for (int i = 4; i < n; ++i) { if (b[i] != b[i - 1]) { if (b[i] == 0 ) for (int j = 0; j <= 4; ++j) r = min(r, a[i - j] - 1); else for (int j = 0; j <= 4; ++j) l = max(l, a[i - j] + 1); } } cout << l << << r << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; const long long oo = ((long long)1e18) + 7; int N, M, T, K, Q; vector<int> G[MAXN]; int num[MAXN]; int dep[MAXN]; int pa[MAXN][25]; int LOG = 20; int cnt = 0; int child[MAXN]; int DFS(int u, int par, int depth) { num[u] = ++cnt; dep[num[u]] = depth; pa[num[u]][0] = num[par]; for (auto v : G[u]) if (v != par) { child[num[u]] += DFS(v, u, dep[num[u]] + 1); } return child[num[u]]; } int LCA(int u, int v) { if (u == v) return u; if (dep[u] < dep[v]) swap(u, v); for (int i = LOG; i >= 0; i--) if (dep[pa[u][i]] >= dep[v]) u = pa[u][i]; if (u == v) return u; for (int i = LOG; i >= 0; i--) if (pa[u][i] != pa[v][i]) { u = pa[u][i]; v = pa[v][i]; } return pa[u][0]; } int findParent(int u, int k) { if (k == 0) return u; int i = 0; while (k > 0) { if (k & 1) u = pa[u][i]; i++; k >>= 1; } return u; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); if (fopen( 519E .inp , r )) { freopen( 519E .inp , r , stdin); freopen( 519E .out , w , stdout); } cin >> N; for (int i = 1; i < N; i++) { int u, v; cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } for (int i = 1; i <= N; i++) child[i] = 1; dep[0] = -1; DFS(1, 0, 0); for (int k = 1; k <= LOG; k++) for (int i = 1; i <= N; i++) pa[i][k] = pa[pa[i][k - 1]][k - 1]; cin >> Q; while (Q--) { int u, v; cin >> u >> v; u = num[u]; v = num[v]; if (dep[u] < dep[v]) swap(u, v); int p = LCA(u, v); if (u == v) { cout << N << n ; continue; } int diff1 = dep[u] - dep[p]; int diff2 = dep[v] - dep[p]; if ((diff1 + diff2) & 1) { cout << 0 << n ; continue; } int avg = (diff1 + diff2) >> 1; int mid = findParent(u, avg); if (mid == p) { int fakeParent1 = findParent(u, diff1 - 1); int fakeParent2 = findParent(v, diff2 - 1); cout << (child[mid] - child[fakeParent1] - child[fakeParent2]) + N - child[mid] << n ; continue; } diff1 = dep[u] - dep[mid]; int fakeParent1 = findParent(u, diff1 - 1); cout << child[mid] - child[fakeParent1] << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; while (q != 0) { int n; cin >> n; int one = 0; if (n == 1) cout << FastestFinger << endl; else if (n == 2) cout << Ashishgup << endl; else if (n % 2 != 0) cout << Ashishgup << endl; else { int t = n; int count = 0, last = n; set<int> s; while (n != 1) { for (int i = 2; i <= sqrt(n); i++) { if ((n % i) == 0) { if (i % 2 != 0) { s.insert(i); count++; } n = (n / i); } } if (n == last) break; last = n; } if (n % 2 != 0) { s.insert(n); count++; } for (auto a : s) { t = (t / a); } if ((t == 2 && count != 1) || t == 1) cout << Ashishgup << endl; else if (t == 2 && count == 1) cout << FastestFinger << endl; else if (count != 0) cout << Ashishgup << endl; else cout << FastestFinger << endl; } q--; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; long long ans = 0; for (int i = (0); i < (n); ++i) { long long t, T, x, cost; cin >> t >> T >> x >> cost; if (t >= T) { ans += cost + m * x; continue; } long long aux1 = cost; if (m > (T - t)) aux1 += m * x; long long aux2 = (long long)ceil((double)(m - (T - t)) / (T - t)) + 1; aux2 *= cost; ans += min(aux1, aux2); } cout << ans << endl; return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "setup.v"
module vga #(
parameter csr_addr = 4'h0,
parameter fml_depth = 26
) (
input sys_clk,
input clk50,
input sys_rst,
/* Configuration interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Framebuffer FML 4x64 interface */
output [fml_depth-1:0] fml_adr,
output fml_stb,
input fml_ack,
input [63:0] fml_di,
/* Direct Cache Bus */
output dcb_stb,
output [fml_depth-1:0] dcb_adr,
input [63:0] dcb_dat,
input dcb_hit,
/* VGA pads */
output vga_psave_n,
output vga_hsync_n,
output vga_vsync_n,
output [7:0] vga_r,
output [7:0] vga_g,
output [7:0] vga_b,
output vga_clk,
/* DDC */
inout vga_sda,
output vga_sdc
);
reg vga_iclk_25;
wire vga_iclk_50;
wire vga_iclk_65;
wire [1:0] clksel;
reg vga_iclk_sel;
wire vga_iclk;
always @(posedge clk50) vga_iclk_25 <= ~vga_iclk_25;
assign vga_iclk_50 = clk50;
DCM_SP #(
.CLKDV_DIVIDE(2.0), // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
.CLKFX_DIVIDE(16), // 1 to 32
.CLKFX_MULTIPLY(13), // 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(`CLOCK_PERIOD),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("TRUE")
) clkgen_vga (
.CLK0(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(vga_iclk_65),
.CLKFX180(),
.LOCKED(),
.CLKFB(),
.CLKIN(sys_clk),
.RST(sys_rst),
.PSEN(1'b0)
);
always @(*) begin
case(clksel)
2'd0: vga_iclk_sel = vga_iclk_25;
2'd1: vga_iclk_sel = vga_iclk_50;
default: vga_iclk_sel = vga_iclk_65;
endcase
end
BUFG b(
.I(vga_iclk_sel),
.O(vga_iclk)
);
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) clock_forward (
.Q(vga_clk),
.C0(vga_iclk),
.C1(~vga_iclk),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R(1'b0),
.S(1'b0)
);
vgafb #(
.csr_addr(csr_addr),
.fml_depth(fml_depth)
) vgafb (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_ack(fml_ack),
.fml_di(fml_di),
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit),
.vga_clk(vga_iclk),
.vga_psave_n(vga_psave_n),
.vga_hsync_n(vga_hsync_n),
.vga_vsync_n(vga_vsync_n),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b),
.vga_sda(vga_sda),
.vga_sdc(vga_sdc),
.clksel(clksel)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_TB_V
`define SKY130_FD_SC_MS__AND3B_TB_V
/**
* and3b: 3-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and3b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A_N = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A_N = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A_N = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A_N = 1'bx;
end
sky130_fd_sc_ms__and3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_TB_V
|
#include <bits/stdc++.h> using namespace std; int read() { char ch; int sig = 1; for (ch = getchar(); ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) sig = -1; int x = ch - 0 ; for (ch = getchar(); ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; return x * sig; } const int N = 1e6 + 5; const long long Mo = 1e9 + 7; struct P { long long x, y; P(long long _x = 0, long long _y = 0) { x = _x; y = _y; } friend P operator+(P a, P b) { return P(a.x + b.x, a.y + b.y); } friend P operator-(P a, P b) { return P(a.x - b.x, a.y - b.y); } friend long long operator^(P a, P b) { return a.x * b.y - a.y * b.x; } } p[N]; int n; long long S, sq[N], sx[N], sy[N]; int main() { n = read(); for (int i = 1; i <= n; i++) p[i].x = read(), p[i].y = read(); for (int i = 1; i <= n; i++) p[i + n] = p[i]; for (int i = 1; i <= n; i++) S += p[i + 1] ^ p[i]; long long ans = 0, sum = 0; for (int i = 1; i <= n * 2; i++) { (sum += p[i] ^ (p[i - 1])) %= Mo; sq[i] = (sq[i - 1] + sum) % Mo; sx[i] = (sx[i - 1] + p[i].x) % Mo; sy[i] = (sy[i - 1] + p[i].y) % Mo; } long long ns = S % Mo; int pos = 3; sum = 0; for (int i = 2; i <= pos; i++) sum += p[i] ^ p[i - 1]; long long now = 0; for (int i = 1; i <= n; i++) { (now += p[i + 1] ^ p[i]) %= Mo; sum -= p[i + 1] ^ p[i]; if (pos < i + 2) pos++, sum += p[pos] ^ p[pos - 1]; while (pos <= i + n - 2) { long long ar = sum; ar -= p[i] ^ p[i + 1]; ar += p[i] ^ p[pos]; if (ar < S - ar) pos++, sum += p[pos] ^ p[pos - 1]; else break; } int ls = i + 2, rs = pos - 1; long long dx = (sx[rs] - sx[ls - 1]) % Mo, dy = (sy[rs] - sy[ls - 1]) % Mo; if (ls <= rs) { (ans += ns * (rs - ls + 1) % Mo) %= Mo; (ans -= (sq[rs] - sq[ls - 1]) % Mo * 2 % Mo) %= Mo; (ans += now * 2 % Mo * (rs - ls + 1) % Mo) %= Mo; (ans += (p[i] ^ p[i + 1]) % Mo * (rs - ls + 1) % Mo * 2 % Mo) %= Mo; (ans -= (p[i] ^ P(dx, dy)) % Mo * 2 % Mo) %= Mo; } ls = pos, rs = i + n - 2, dx = (sx[rs] - sx[ls - 1]) % Mo, dy = (sy[rs] - sy[ls - 1]) % Mo; if (ls <= rs) { (ans -= ns * (rs - ls + 1) % Mo) %= Mo; (ans += (sq[rs] - sq[ls - 1]) % Mo * 2 % Mo) %= Mo; (ans -= now * 2 % Mo * (rs - ls + 1) % Mo) %= Mo; (ans -= (p[i] ^ p[i + 1]) % Mo * (rs - ls + 1) % Mo * 2 % Mo) %= Mo; (ans += (p[i] ^ P(dx, dy)) % Mo * 2 % Mo) %= Mo; } } ans = ans * (Mo + 1) / 2 % Mo; printf( %lld n , (ans + Mo) % Mo); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; int n; int a[maxn]; int nivel[maxn], in[maxn], out[maxn], tt; vector<int> grafo[maxn]; struct BinaryLifting { int tab[maxn][20]; void dfs(int u, int p) { in[u] = ++tt; for (auto v : grafo[u]) { if (v == p) continue; nivel[v] = nivel[u] + 1, tab[v][0] = u; dfs(v, u); } out[u] = tt; } void build(void) { for (int j = 1; j < 20; j++) for (int i = 1; i <= n; i++) tab[i][j] = tab[tab[i][j - 1]][j - 1]; } int intersect(int u, int v, int w_u, int w_v) { if (nivel[u] < nivel[v]) swap(u, v), swap(w_u, w_v); for (int i = 19; i >= 0; i--) if (nivel[u] - (1 << i) >= nivel[v] && w_u >= (1 << i)) u = tab[u][i], w_u -= (1 << i); if (nivel[u] != nivel[v]) return -1; if (u == v) return u; for (int i = 19; i >= 0; i--) if (tab[u][i] && tab[v][i] && tab[u][i] != tab[v][i] && min(w_u, w_v) >= (1 << i)) u = tab[u][i], v = tab[v][i], w_u -= (1 << i), w_v -= (1 << i); if (tab[u][0] != tab[v][0] || min(w_u, w_v) == 0) return -1; return tab[u][0]; } int dist(int u, int v) { return nivel[u] + nivel[v] - 2 * nivel[intersect(u, v, nivel[u], nivel[v])]; } int get_intersection(int u, int v, int root) { int k = -1; int lca_u = intersect(u, root, nivel[u], nivel[root]); int lca_v = intersect(v, root, nivel[v], nivel[root]); int aux = intersect(u, v, nivel[u] - nivel[lca_u], nivel[v] - nivel[lca_v]); if (k == -1 || (aux != -1 && dist(aux, root) > dist(k, root))) k = aux; aux = intersect(u, root, nivel[u] - nivel[lca_u], nivel[root] - nivel[lca_v]); if (k == -1 || (aux != -1 && dist(aux, root) > dist(k, root))) k = aux; aux = intersect(root, v, nivel[root] - nivel[lca_u], nivel[v] - nivel[lca_v]); if (k == -1 || (aux != -1 && dist(aux, root) > dist(k, root))) k = aux; aux = intersect(root, root, nivel[root] - nivel[lca_u], nivel[root] - nivel[lca_v]); if (k == -1 || (aux != -1 && dist(aux, root) > dist(k, root))) k = aux; return k; } int kth(int u, int k) { for (int i = 19; i >= 0; i--) if (tab[u][i] && k >= (1 << i)) u = tab[u][i], k -= (1 << i); return u; } } LCA; struct SegmentTree { long long tree[3 * maxn], lazy[3 * maxn]; void flush(int node, int l, int r) { if (!lazy[node]) return; if (l != r) { lazy[2 * node] += lazy[node]; lazy[2 * node + 1] += lazy[node]; } tree[node] += 1ll * (r - l + 1) * lazy[node]; lazy[node] = 0; } void upd(int node, int l, int r, int a, int b, int v) { flush(node, l, r); if (l > b || r < a) return; if (l >= a && r <= b) { lazy[node] = 1ll * v; flush(node, l, r); return; } int mid = (l + r) >> 1; upd(2 * node, l, mid, a, b, v); upd(2 * node + 1, mid + 1, r, a, b, v); tree[node] = tree[2 * node] + tree[2 * node + 1]; } long long query(int node, int l, int r, int a, int b) { flush(node, l, r); if (l > b || r < a) return 0; if (l >= a && r <= b) return tree[node]; int mid = (l + r) >> 1; return query(2 * node, l, mid, a, b) + query(2 * node + 1, mid + 1, r, a, b); } } seg; bool is_ancestor(int u, int v) { return (in[v] >= in[u] && out[v] <= out[u]); } int main(void) { int q; scanf( %d %d , &n, &q); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i < n; i++) { int u, v; scanf( %d %d , &u, &v); grafo[u].push_back(v); grafo[v].push_back(u); } LCA.dfs(1, 0); LCA.build(); for (int i = 1; i <= n; i++) seg.upd(1, 1, n, in[i], in[i], a[i]); int root = 1; while (q--) { int op; scanf( %d , &op); if (op == 1) { int v; scanf( %d , &v); root = v; } else if (op == 2) { int u, v, x; scanf( %d %d %d , &u, &v, &x); int k = LCA.get_intersection(u, v, root); if (!is_ancestor(k, root)) seg.upd(1, 1, n, in[k], out[k], x); else { seg.upd(1, 1, n, 1, n, x); if (k != root) { int w = LCA.kth(root, nivel[root] - nivel[k] - 1); seg.upd(1, 1, n, in[w], out[w], -x); } } } else { int u; scanf( %d , &u); if (!is_ancestor(u, root)) printf( %lld n , seg.query(1, 1, n, in[u], out[u])); else { if (u == root) printf( %lld n , seg.query(1, 1, n, 1, n)); else { int w = LCA.kth(root, nivel[root] - nivel[u] - 1); printf( %lld n , seg.query(1, 1, n, 1, n) - seg.query(1, 1, n, in[w], out[w])); } } } } }
|
#include <bits/stdc++.h> using namespace std; int c3[100010], c2[1010]; int graph[110][110]; int main() { ios ::sync_with_stdio(0); cin.tie(0); memset(graph, 0, sizeof graph); for (int i = (3), _b = (100); i <= _b; ++i) { c3[i] = (i * (i - 1) * (i - 2)) / 6; } for (int i = (2), _b = (100); i <= _b; ++i) { c2[i] = (i * (i - 1)) / 2; } int k, esco; cin >> k; for (int i = (100), _b = (3); i >= _b; --i) { if (k >= c3[i]) { k -= c3[i]; esco = i; break; } } for (int i = 0; i < (int)(esco); ++i) { for (int j = 0; j < (int)(esco); ++j) { if (i != j) graph[i][j] = graph[j][i] = 1; } } int fixo = esco; while (k > 0) { int cont = 0; for (int i = (fixo), _b = (2); i >= _b; --i) { cont = i; if (k >= c2[i]) break; } for (int i = 0; i < (int)(cont); ++i) graph[i][esco] = graph[esco][i] = 1; k -= c2[cont]; esco++; } cout << esco << endl; for (int i = 0; i < (int)(esco); ++i) { for (int j = 0; j < (int)(esco); ++j) { cout << graph[i][j] << ; } cout << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD_TB_V
`define SKY130_FD_SC_LP__BUSHOLD_TB_V
/**
* bushold: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates output driver).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bushold.v"
module top();
// Inputs are registered
reg RESET;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
RESET = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 RESET = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 RESET = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 RESET = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 RESET = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 RESET = 1'bx;
end
sky130_fd_sc_lp__bushold dut (.RESET(RESET), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD_TB_V
|
// Copyright (c) 2015 James Bowman
// Distributed under the MIT software license, see the accompanying
// file COPYING or http://www.opensource.org/licenses/mit-license.php.
// Borrowed from https://github.com/jamesbowman/swapforth/blob/master/j1a/icestorm/uart.v
`default_nettype none
module baudgen(
input wire clk,
input wire resetq,
input wire [31:0] baud,
input wire restart,
output wire ser_clk);
parameter CLKFREQ = ;
/* needs to be (CLKFREQ).bit_length() + 1 */
parameter RWIDTH = 25;
wire [RWIDTH-1:0] aclkfreq = CLKFREQ;
reg [RWIDTH-1:0] d;
wire [RWIDTH-1:0] dInc = d[RWIDTH-1] ? ({4'd0, baud}) : (({4'd0, baud}) - aclkfreq);
wire [RWIDTH-1:0] dN = restart ? 0 : (d + dInc);
wire fastclk = ~d[RWIDTH-1];
assign ser_clk = fastclk;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
d <= 0;
end else begin
d <= dN;
end
end
endmodule
/*
-----+ +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+----
| | | | | | | | | | | |
|start| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |stop1|stop2|
| | | | | | | | | | | ? |
+-----+-----+-----+-----+-----+-----+-----+-----+-----+ +
*/
module uart(
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire [31:0] baud,
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
parameter CLKFREQ = ;
reg [3:0] bitcount; // 0 means idle, so this is a 1-based counter
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
wire starting = uart_wr_i & ~uart_busy;
baudgen #(.CLKFREQ(CLKFREQ)) _baudgen(
.clk(clk),
.resetq(resetq),
.baud(baud),
.restart(1'b0),
.ser_clk(ser_clk));
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (starting) begin
shifter <= { uart_dat_i[7:0], 1'b0 };
bitcount <= 1 + 8 + 1; // 1 start, 8 data, 1 stop
end
if (sending & ser_clk) begin
{ shifter, uart_tx } <= { 1'b1, shifter };
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
module rxuart(
input wire clk,
input wire resetq,
input wire [31:0] baud,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data); // data
parameter CLKFREQ = ;
reg [4:0] bitcount;
reg [7:0] shifter;
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen #(.CLKFREQ(CLKFREQ)) _baudgen(
.clk(clk),
.baud({baud[30:0], 1'b0}),
.resetq(resetq),
.restart(startbit),
.ser_clk(ser_clk));
assign valid = (bitcount == 18);
reg [4:0] bitcountN;
always @*
if (startbit)
bitcountN = 0;
else if (!idle & !valid & ser_clk)
bitcountN = bitcount + 5'd1;
else if (valid & rd)
bitcountN = 5'b11111;
else
bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (bitcount > 2) & bitcount[0] & !valid & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
module buart(
input wire clk,
input wire resetq,
input wire [31:0] baud,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
parameter CLKFREQ = ;
rxuart #(.CLKFREQ(CLKFREQ)) _rx (
.clk(clk),
.resetq(resetq),
.baud(baud),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data));
uart #(.CLKFREQ(CLKFREQ)) _tx (
.clk(clk),
.resetq(resetq),
.baud(baud),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_BLACKBOX_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_BLACKBOX_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlygate4sd2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long MAXN = 9223372036854775807, mod = 998244353; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long T = 1; for (long long t = 0; t < T; t++) { long long n, s1, s2, p1, p2; cin >> n >> s1 >> s2 >> p1 >> p2; long long time1 = s1 * n + 2 * p1; long long time2 = s2 * n + 2 * p2; if (time1 < time2) cout << First ; else if (time2 < time1) cout << Second ; else cout << Friendship ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long X[200200]; int Xi[200200], xi; int X2[200200], x2; int Xm[200200], xm; int a[200200], w[200200], x, n, q; inline void update(int u) { for (; u <= n; u += u & -u) { X[u] += x; Xi[u] = (Xi[u] + xi) % 1000000007; X2[u] = (X2[u] + x2) % 1000000007; Xm[u] = (Xm[u] + xm) % 1000000007; } } inline long long calc_x(int u, long long ans = 0) { for (; u; u -= u & -u) ans += X[u]; return ans; } inline void calc(int u) { x = 0, xi = 0, x2 = 0, xm = 0; for (; u; u -= u & -u) { x = (x + X[u]) % 1000000007; xi = (xi + Xi[u]) % 1000000007; x2 = (x2 + X2[u]) % 1000000007; xm = (xm + Xm[u]) % 1000000007; } } int collect(int u, int L, int R) { calc(L - 1); int tx = x, txi = xi, tx2 = x2, txm = xm; calc(u - 1); tx = (x - tx + 1000000007) % 1000000007, txi = (xi - txi + 1000000007) % 1000000007, tx2 = (x2 - tx2 + 1000000007) % 1000000007, txm = (xm - txm + 1000000007) % 1000000007; long long ans = 0; if (L < u) { ans += (long long)a[u] * tx; ans -= txm; ans += txi - (long long)u * tx; } tx = (x + w[u]) % 1000000007, txi = (xi + (long long)u * w[u]) % 1000000007, tx2 = (x2 + (long long)w[u] * w[u]) % 1000000007, txm = (xm + (long long)a[u] * w[u]) % 1000000007; calc(R); tx = (x - tx + 1000000007) % 1000000007, txi = (xi - txi + 1000000007) % 1000000007, tx2 = (x2 - tx2 + 1000000007) % 1000000007, txm = (xm - txm + 1000000007) % 1000000007; if (u < R) { ans += txm; ans -= (long long)a[u] * tx; ans += (long long)u * tx - txi; } ans %= 1000000007; if (ans < 0) ans += 1000000007; return ans; } int main() { scanf( %d %d , &n, &q); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= n; i++) { scanf( %d , w + i); x = w[i]; xi = (long long)i * x % 1000000007; x2 = (long long)x * x % 1000000007; xm = (long long)a[i] * x % 1000000007; update(i); } while (q--) { int L, R; scanf( %d %d , &L, &R); if (L < 0) { L = -L; x = -w[L]; xi = 1000000007 - (long long)L * w[L] % 1000000007; x2 = 1000000007 - (long long)w[L] * w[L] % 1000000007; xm = 1000000007 - (long long)a[L] * w[L] % 1000000007; update(L); w[L] = R; x = w[L]; xi = (long long)L * x % 1000000007; x2 = (long long)x * x % 1000000007; xm = (long long)a[L] * x % 1000000007; update(L); } else if (L == R) puts( 0 ); else { long long L_ = calc_x(L - 1), all = calc_x(R) - L_; int st = L - 1, ed = R; while (st + 1 < ed) { int md = st + ed >> 1; long long sa = calc_x(md) - L_, sb = all - sa; if (sa > sb) ed = md; else st = md; } printf( %d n , collect(ed, L, R)); } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_2_V
`define SKY130_FD_SC_HD__NAND4BB_2_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4bb_2 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4bb_2 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_2_V
|
`timescale 1ns/1ps
`define DEMO_FUNCTION_ADDR 1
module tb_cocotb (
//Virtual Host Interface Signals
input clk,
input sdio_clk,
input rst,
input request_read_wait,
input request_interrupt
);
//Parameters
//Registers/Wires
reg r_rst;
reg r_request_read_wait;
reg r_request_interrupt;
wire sdio_cmd;
wire [3:0] sdio_data;
// Function Interface From CIA
wire fbr1_csa_en;
wire [3:0] fbr1_pwr_mode;
wire [15:0] fbr1_block_size;
wire fbr2_csa_en;
wire [3:0] fbr2_pwr_mode;
wire [15:0] fbr2_block_size;
wire fbr3_csa_en;
wire [3:0] fbr3_pwr_mode;
wire [15:0] fbr3_block_size;
wire fbr4_csa_en;
wire [3:0] fbr4_pwr_mode;
wire [15:0] fbr4_block_size;
wire fbr5_csa_en;
wire [3:0] fbr5_pwr_mode;
wire [15:0] fbr5_block_size;
wire fbr6_csa_en;
wire [3:0] fbr6_pwr_mode;
wire [15:0] fbr6_block_size;
wire fbr7_csa_en;
wire [3:0] fbr7_pwr_mode;
wire [15:0] fbr7_block_size;
wire [7:0] function_enable;
reg [7:0] function_ready;
wire [2:0] function_abort;
wire [7:0] function_int_en;
reg [7:0] function_int_pend;
reg [7:0] function_exec_status;
wire function_activate;
wire function_inc_addr;
wire function_bock_mode;
wire function_finished;
reg [7:0] function_interrupt;
wire [3:0] func_num;
wire func_write_flag;
wire func_rd_after_wr;
wire [7:0] func_write_data;
wire [7:0] func_read_data;
wire func_data_rdy;
wire func_wr_data_stb;
wire func_host_rdy;
wire [17:0] func_addr;
wire [17:0] func_data_count;
wire func_rd_data_stb;
wire func_block_mode;
wire i_func_num;
wire o_read_wait;
wire o_interrupt;
wire demo_func_ready;
wire demo_func_enable;
wire demo_func_abort;
wire demo_func_int_en;
wire demo_func_int_pend;
wire demo_func_busy;
wire demo_func_activate;
wire demo_func_finished;
wire demo_func_inc_addr;
wire demo_func_block_mode;
/* COCOTB Synchronize */
always @ (*) r_rst = rst;
always @ (*) r_request_read_wait = request_read_wait;
always @ (*) r_request_interrupt = request_interrupt;
//Submodules
sdio_device_stack sdio_device (
.sdio_clk (sdio_clk ),
.rst (rst ),
// Function Interface From CIA
.o_fbr1_csa_en (fbr1_csa_en ),
.o_fbr1_pwr_mode (fbr1_pwr_mode ),
.o_fbr1_block_size (fbr1_block_size ),
.o_fbr2_csa_en (fbr2_csa_en ),
.o_fbr2_pwr_mode (fbr2_pwr_mode ),
.o_fbr2_block_size (fbr2_block_size ),
.o_fbr3_csa_en (fbr3_csa_en ),
.o_fbr3_pwr_mode (fbr3_pwr_mode ),
.o_fbr3_block_size (fbr3_block_size ),
.o_fbr4_csa_en (fbr4_csa_en ),
.o_fbr4_pwr_mode (fbr4_pwr_mode ),
.o_fbr4_block_size (fbr4_block_size ),
.o_fbr5_csa_en (fbr5_csa_en ),
.o_fbr5_pwr_mode (fbr5_pwr_mode ),
.o_fbr5_block_size (fbr5_block_size ),
.o_fbr6_csa_en (fbr6_csa_en ),
.o_fbr6_pwr_mode (fbr6_pwr_mode ),
.o_fbr6_block_size (fbr6_block_size ),
.o_fbr7_csa_en (fbr7_csa_en ),
.o_fbr7_pwr_mode (fbr7_pwr_mode ),
.o_fbr7_block_size (fbr7_block_size ),
.o_func_enable (function_enable ),
.i_func_ready (function_ready ),
.o_func_abort (function_abort ),
.o_func_int_en (function_int_en ),
.i_func_int_pending (function_int_pend ),
.i_func_exec_status (function_exec_status),
.o_func_activate (o_func_activate ),
.i_func_finished (i_func_finished ),
.o_func_inc_addr (o_func_inc_addr ),
.o_func_block_mode (o_func_block_mode ),
.o_func_num (func_num ),
.o_func_write_flag (func_write_flag ),
.o_func_rd_after_wr (func_rd_after_wr ),
.o_func_addr (func_addr ),
.o_func_write_data (func_write_data ),
.i_func_read_data (func_read_data ),
.o_func_data_rdy (func_data_rdy ),
.i_func_host_rdy (func_host_rdy ),
.o_func_data_count (func_data_count ),
.i_interrupt (function_interrupt),
.o_ddr_en (o_ddr_en ),
.i_sdio_cmd (sdio_cmd ),
.io_sdio_data (sdio_data )
);
demo_function demo (
.clk (clk ),
.sdio_clk (sdio_clk ),
.rst (r_rst ),
.i_csa_en (fbr1_csa_en ),
.i_block_size (fbr1_block_size ),
.i_enable (demo_func_enable ),
.o_ready (demo_func_ready ),
.i_abort (demo_func_abort ),
.i_interrupt_enable (demo_func_int_en ),
.o_interrupt_pending (demo_func_int_pend ),
.o_busy (demo_func_busy ),
.i_activate (demo_func_activate ),
.o_finished (demo_func_finished ),
.i_inc_addr (demo_func_inc_addr ),
.i_block_mode (demo_func_block_mode),
.i_write_flag (func_write_flag ),
.i_rd_after_wr (func_rd_after_wr ),
.i_addr (func_addr ),
.i_write_data (func_write_data ),
.o_read_data (func_read_data ),
.o_data_rdy (func_data_rdy ),
.i_data_stb (func_wr_data_stb ),
.i_host_rdy (func_host_rdy ),
.i_data_count (func_data_count ),
.o_data_stb (func_rd_data_stb ),
.o_read_wait (demo_func_read_wait ),
.o_interrupt (demo_func_interrupt ),
.i_request_read_wait (r_request_read_wait ),
.i_request_interrupt (r_request_interrupt )
);
//Asynchronous Logic
assign sdio_cmd = 0;
assign sdio_data = 0;
assign demo_func_enable = function_enable[`DEMO_FUNCTION_ADDR];
assign demo_func_abort = (function_abort == `DEMO_FUNCTION_ADDR);
assign demo_func_int_en = function_int_en[`DEMO_FUNCTION_ADDR];
assign demo_func_activate = (func_num == `DEMO_FUNCTION_ADDR) ? function_activate : 1'b0;
assign demo_func_inc_addr = (func_num == `DEMO_FUNCTION_ADDR) ? function_inc_addr : 18'h0;
assign demo_func_block_mode = (func_num == `DEMO_FUNCTION_ADDR) ? func_block_mode : 1'b0;
/* Make a multiplexer that will handle multiple function */
assign function_finished = (func_num == `DEMO_FUNCTION_ADDR) ? demo_func_finished : 1'b0;
assign function_read_wait = (func_num == `DEMO_FUNCTION_ADDR) ? demo_func_read_wait : 1'b0;
//Synchronous Logic
always @ (posedge sdio_clk) begin
if (r_rst) begin
function_ready <= 0;
function_int_pend <= 0;
function_exec_status <= 0;
function_interrupt <= 0;
end
else begin
function_ready[`DEMO_FUNCTION_ADDR] <= demo_func_ready;
function_int_pend[`DEMO_FUNCTION_ADDR] <= demo_func_int_pend;
function_exec_status[`DEMO_FUNCTION_ADDR] <= demo_func_busy;
function_interrupt[`DEMO_FUNCTION_ADDR] <= demo_func_interrupt;
end
end
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O211AI_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o211ai (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 5e5; long long pr(long long a, long long b, long long c) { if (b == 0) return 1LL; long long ans = 1; while (b > 0) { if (b % 2) ans = ((ans % c) * (a % c)) % c; a = ((a % c) * (a % c)) % c; b /= 2; a %= c; ans %= c; } return ans; } void solve() { long long k, m, h, l, r, a, b, c, d, w, mini, maxi = INT_MAX, prev, res; double n; cin >> n; n *= 2.0; double y = (double)3.14159265358979323846 / n; double ans = tan((3.14159265358979323846 / 2.0) - y); cout << fixed << setprecision(10) << ans << endl; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; while (t--) { solve(); } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
module t (
input wire clk,
input wire rst,
output reg [31:0] cyc
);
always @(posedge clk) begin
if (rst) begin
cyc <= 0;
end else begin
cyc <= cyc +1;
end
end
`ifdef CMT
wire net_1 /* verilator forceable */;
wire [7:0] net_8 /* verilator forceable */;
`else
wire net_1;
wire [7:0] net_8;
`endif
assign net_1 = ~cyc[0];
assign net_8 = ~cyc[1 +: 8];
always @ (posedge clk) begin
$display("%d: %x %x", cyc, net_8, net_1);
if (!rst) begin
case (cyc)
3: begin
`checkh (net_1, 0);
`checkh (net_8, ~cyc[1 +: 8]);
end
4: begin
`checkh (net_1, 0);
`checkh (net_8, 8'h5f);
end
5: begin
`checkh (net_1, 1);
`checkh (net_8, 8'h5f);
end
6, 7: begin
`checkh (net_1, 1);
`checkh (net_8, 8'hf5);
end
8: begin
`checkh (net_1, ~cyc[0]);
`checkh (net_8, 8'hf5);
end
10, 11: begin
`checkh (net_1, 1);
`checkh (net_8, 8'h5a);
end
12, 13: begin
`checkh (net_1, 0);
`checkh (net_8, 8'ha5);
end
default: begin
`checkh ({net_8, net_1}, ~cyc[0 +: 9]);
end
endcase
end
if (cyc == 30) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 500010; struct edge { int nxt, t; } e[N * 3]; int head[N], edge_cnt; void add_edge(int x, int y) { e[edge_cnt] = (edge){head[x], y}; head[x] = edge_cnt++; } int dfn[N], low[N], Tar_cnt, stk[N], stk_top, loop_cnt, ID[N], P[N], tot, st[N], ed[N]; void Tarjan(int x, int f) { dfn[x] = low[x] = ++Tar_cnt; stk[++stk_top] = x; int i; for (i = head[x]; ~i; i = e[i].nxt) { int to = e[i].t; if (to == f) { continue; } if (dfn[to] == 0) { Tarjan(to, x); low[x] = min(low[x], low[to]); } else { low[x] = min(low[x], dfn[to]); } } if (low[x] == dfn[x]) { int y; loop_cnt++; st[x] = tot + 1; do { y = stk[stk_top--]; ID[y] = loop_cnt; P[++tot] = y; } while (x != y); ed[x] = tot; } } int D[N], Mx[N][2], dis[N], Fa[N]; bool vis[N]; void cmp(int x, int y) { if (dis[Mx[x][0]] < dis[y]) { Mx[x][1] = Mx[x][0]; Mx[x][0] = y; } else if (dis[Mx[x][1]] < dis[y]) { Mx[x][1] = y; } } void BFS(int n) { int L = 1, R = 1, i; D[1] = 1; vis[1] = 1; while (L <= R) { int x = D[L++]; for (i = head[x]; ~i; i = e[i].nxt) { int to = e[i].t; if (vis[to]) { continue; } vis[to] = 1; Fa[to] = x; D[++R] = to; } } dis[0] = -1; for (i = n; i > 1; i--) { int x = D[i], y = Fa[x]; if (ID[x] != ID[y]) { cmp(y, x); } dis[y] = max(dis[y], dis[x] + 1); } } struct node { int id, w; } Q[N << 1]; int G[N], val[N], Ans[N], dp[N]; void Push(int &L, int &R, node x) { while (L <= R && Q[R].w <= x.w) { R--; } Q[++R] = x; } void Pop1(int &L, int x) { if (Q[L].id < x) { L++; } } void Pop2(int &L, int x) { if (Q[L].id > x) { L++; } } void Solve(int S, int f, int Fr) { int i, j, d = ed[S] - st[S] + 1, k, L, R; dp[S] = Fr; if (d > 1) { for (i = st[S]; i <= ed[S]; i++) { int x = P[i], t = dis[Mx[x][0]] + 1; G[i - st[S] + 1] = x; Ans[x] = t; if (x == S) { val[i - st[S] + 1] = max(Fr, t); } else { val[i - st[S] + 1] = t; } } L = 1, R = 0, k = d / 2; for (i = d - k + 1; i <= d; i++) { Push(L, R, (node){i - d, val[i] - (i - d)}); } for (i = 1; i <= d; i++) { Pop1(L, i - k); dp[G[i]] = max(dp[G[i]], Q[L].w + i); Push(L, R, (node){i, val[i] - i}); } L = 1, R = 0, k = (d - 1) / 2; for (i = k; i >= 1; i--) { Push(L, R, (node){i + d, val[i] + (i + d)}); } for (i = d; i >= 1; i--) { Pop2(L, i + k); dp[G[i]] = max(dp[G[i]], Q[L].w - i); Push(L, R, (node){i, val[i] + i}); } } else { Ans[S] = max(Fr, dis[Mx[S][0]] + 1); } for (i = st[S]; i <= ed[S]; i++) { int x = P[i]; for (j = head[x]; ~j; j = e[j].nxt) { int to = e[j].t; if (ID[x] == ID[to] || to == f) { continue; } if (Mx[x][0] == to) { Solve(to, x, max(dp[x] + 1, dis[Mx[x][1]] + 2)); } else { Solve(to, x, max(dp[x] + 1, dis[Mx[x][0]] + 2)); } } } } int main() { int n, m, i; scanf( %d%d , &n, &m); memset(head + 1, -1, sizeof(int) * 1 * n); for (i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); add_edge(x, y); add_edge(y, x); } memset(dfn + 1, 0, sizeof(int) * 1 * n); Tarjan(1, 0); BFS(n); Solve(1, 0, 0); for (i = 1; i <= n; i++) { printf( %d n , max(Ans[i], dp[i])); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int ar[100001], csum[100001]; int main() { ios::sync_with_stdio(0), cin.tie(NULL), cout.tie(NULL); int n, q; cin >> n; for (int i = 0; i < n; i++) cin >> ar[i]; for (int i = 1; i <= n; i++) { csum[i] = csum[i - 1] + ar[i - 1]; } cin >> q; while (q--) { int l, r; cin >> l >> r; cout << (csum[r] - csum[l - 1]) / 10 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long array1[n]; for (int i = 0; i < n; i++) { cin >> array1[i]; } long long a, b, c, d, e, sum = 0; cin >> a >> b >> c >> d >> e; map<long long, long long> mp; for (int i = 0; i < n; i++) { sum += array1[i]; mp[5] += sum / e; sum %= e; mp[4] += sum / d; sum %= d; mp[3] += sum / c; sum %= c; mp[2] += sum / b; sum %= b; mp[1] += sum / a; sum %= a; } for (int i = 1; i <= 5; i++) { cout << mp[i]; if (i != 5) cout << ; } cout << endl << sum << endl; }
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This tests the behavior of drive strength attached to a buf device.
* The assign of a reg to the bit should override the value and give a
* well defined result.
*/
module main;
wire bit;
PULLDOWN pd(bit);
reg drv;
assign bit = drv;
initial begin
drv = 0;
#100 if (bit !== 1'b0) begin
$display("FAILED -- 0 bit = %b", bit);
$finish;
end
drv = 1;
#100 if (bit !== 1'b1) begin
$display("FAILED -- 1 bit = %b", bit);
$finish;
end
$display("PASSED");
$finish;
end // initial begin
endmodule // main
module PULLDOWN (O);
output O;
wire A;
pulldown (A);
buf (weak0,weak1) #(1,1) (O,A);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD2_BEHAVIORAL_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; const int inf = 0x3f3f3f3f, N = 2e5 + 10; const double pi = acos(-1); using namespace std; char s[N]; int num[N]; int main() { int n, k; while (cin >> n >> k) { scanf( %s , s + 1); memset(num, 0, sizeof(num)); for (int i = 1; s[i]; i++) { if (s[i] == 0 ) num[i] = num[i - 1] + 1; else num[i] = num[i - 1]; } int ans = inf; int last = 0; if (k == 1) { for (int i = 1; i <= n; i++) { if (!last && s[i] == 0 ) last = i; else if (last && s[i] == 0 ) { ans = i - last; break; } } } for (int i = 1; i <= n; i++) { if (s[i] == 1 ) continue; int l = 1, r = n; while (l <= r) { int mid = (l + r) >> 1; int st = max(1, i - mid); int en = min(n, i + mid); if (num[en] - num[st - 1] >= k + 1) r = mid - 1; else l = mid + 1; } ans = min(ans, l); } cout << ans << endl; } return 0; }
|
module top;
function automatic [31:0] operation1;
input [4:0] rounds;
input integer num;
integer i;
begin
begin : shadow
integer rounds;
rounds = 0;
end
for (i = 0; i < rounds; i = i + 1)
num = num * 2;
operation1 = num;
end
endfunction
function automatic [31:0] operation2;
input [4:0] var;
input integer num;
begin
var[0] = var[0] ^ 1;
operation2 = num * var;
end
endfunction
function automatic [31:0] operation3;
input [4:0] rounds;
input integer num;
reg [4:0] rounds;
integer i;
begin
begin : shadow
integer rounds;
rounds = 0;
end
for (i = 0; i < rounds; i = i + 1)
num = num * 2;
operation3 = num;
end
endfunction
wire [31:0] a;
assign a = 2;
parameter A = 3;
wire [31:0] x1;
assign x1 = operation1(A, a);
wire [31:0] x2;
assign x2 = operation2(A, a);
wire [31:0] x3;
assign x3 = operation3(A, a);
// `define VERIFY
`ifdef VERIFY
assert property (a == 2);
assert property (A == 3);
assert property (x1 == 16);
assert property (x2 == 4);
assert property (x3 == 16);
`endif
endmodule
|
// Copyright (C) 1998,2000,2003,2004,2007 Free Software Foundation, Inc.
// This file is part of Gforth.
// Gforth is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation, either version 3
// of the License, or (at your option) any later version.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, see http://www.gnu.org/licenses/.
/* Minimal Instruction Set Computer
\ sources destinations
$0 Constant PC $0 Constant JMP
$1 Constant PC+2 $1 Constant JS
$2 Constant PC+4 $2 Constant JZ
$3 Constant PC+6
$4 Constant JC
$8 Constant ACCU $8 Constant ACCU
$9 Constant SF $9 Constant SUB
$A Constant ZF $A Constant SUBR
$B Constant ADD
$C Constant CF $C Constant XOR
$D Constant OR
$E Constant AND
$F Constant SHR
*/
`define L [0:l-1]
module misc(clock, data, addr, csel, rw);
parameter l=16, d=10;
input clock;
inout `L data;
output `L addr;
output csel;
output rw;
reg `L inst, dtr, accu, pc;
reg [0:1] state;
reg carry, zero;
wire `L regs;
wire alusel, cout, zout, pccond;
wire `L alu1, alu2, aluout;
wire [0:2] aluop;
initial
begin
state = 0;
pc = 'h10;
inst = 0;
dtr = 0;
accu = 0;
carry = 0;
zero = 1;
end
assign
rw=~&state,
csel=~state[1] | |inst[0:l-5],
addr = state[1] ? inst : pc,
data = rw ? {l{1'bz}} : dtr;
assign
alusel= inst[l-4],
pccond = ~|(inst[l-3:l-1] & ~{ carry, zero, accu[0] }),
regs = inst[l-4] ? (|inst[l-3:l-1] ? { {(l-1){1'b0}}, pccond } : accu)
: aluout;
always @(posedge clock)
begin
casez(state)
2'bz0 : begin
inst = data;
pc = aluout;
end
2'b01 : begin
dtr = csel ? data : regs;
// $fwrite(2, "PC: %x : %x -( %x )->", pc-1'b1, inst, dtr);
end
2'b11 :
begin
if(~|inst[0:l-5])
if(alusel) { carry, zero, accu } = { cout, zout, aluout };
else
if (pccond) pc=dtr;
// $fwrite(2, " %x ACCU: %x\n", inst, accu);
end
endcase /* 2 */
state = state + 1;
end
assign
alu1 = &state ? accu : pc,
alu2 = ~state[1] ? {{l{1'b0}}, 1'b1 } :
state[0] ? dtr : { inst[1:l-1], 1'b0 } - 1,
aluop = &state ? inst[l-3:l-1] : 3'b011;
alu #(l,d) alu0(aluop, alu1, alu2, carry, aluout, cout, zout);
endmodule /* misc */
module alu(op, in1, in2, cin, out, cout, zout);
parameter l=16, d=10;
input [0:2] op;
input `L in1, in2;
input cin;
output `L out;
output cout, zout;
reg `L out;
reg cout;
initial
cout = 0;
always @(in1 or in2 or op)
#d case(op)
3'b000 : { cout, out } = { cin, in2 };
3'b001 : { cout, out } = in1 - in2;
3'b010 : { cout, out } = in2 - in1;
3'b011 : { cout, out } = in1 + in2;
3'b100 : { cout, out } = { cin, in1 ^ in2 };
3'b101 : { cout, out } = { cin, in1 | in2 };
3'b110 : { cout, out } = { cin, in1 & in2 };
3'b111 : { cout, out } = { in2[l-1], cin, in2[0:l-2] };
endcase /* 3 */
assign
zout = ~|out;
endmodule /* alu */
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> v; int c; for (int i = 0; i < n; i++) { cin >> c; v.push_back(c); } if (n == 1) { if (v[0] == 1) { cout << YES ; return 0; } } sort(v.begin(), v.end()); if (v[0] == 0 && v[1] == 1) { cout << YES ; } else { cout << NO ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2B_1_V
`define SKY130_FD_SC_HD__NOR2B_1_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2b_1 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2b_1 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2B_1_V
|
//
// Avalon MM Slave for parallel input/output camera registers
//
module avalon_camera (
// Avalon clock interface signals
input clk,
input reset_n,
// Signals for Avalon-MM slave port
input [4:0] avs_s1_address,
input avs_s1_read,
output reg [31:0] avs_s1_readdata,
input avs_s1_write,
input [31:0] avs_s1_writedata,
// Control signals to export to the image_capture
output avs_export_start_capture,
output [15:0] avs_export_capture_width,
output [15:0] avs_export_capture_height,
output [31:0] avs_export_buff0,
output [31:0] avs_export_buff1,
input avs_export_buff0full,
input avs_export_buff1full,
input avs_export_capture_standby,
// Registers to export to the camera_config
output [15:0] avs_export_width,
output [15:0] avs_export_height,
output [15:0] avs_export_start_row,
output [15:0] avs_export_start_column,
output [15:0] avs_export_row_size,
output [15:0] avs_export_column_size,
output [15:0] avs_export_row_mode,
output [15:0] avs_export_column_mode,
output [15:0] avs_export_exposure,
//soft reset
output avs_export_cam_soft_reset_n
);
// Addresses of the registers to control image_capture
`define ADDR_START_CAPTURE 5'h00
`define ADDR_CAPTURE_WIDTH 5'h01
`define ADDR_CAPTURE_HEIGHT 5'h02
`define ADDR_BUFF0 5'h03
`define ADDR_BUFF1 5'h04
`define ADDR_BUFF0FULL 5'h05
`define ADDR_BUFF1FULL 5'h06
`define ADDR_CAPTURE_STANDBY 5'h07
// Addresses of the registers to control camera_config
`define ADDR_WIDTH 5'h09
`define ADDR_HEIGHT 5'h0a
`define ADDR_START_ROW 5'h0b
`define ADDR_START_COLUMN 5'h0c
`define ADDR_ROW_SIZE 5'h0d
`define ADDR_COLUMN_SIZE 5'h0e
`define ADDR_ROW_MODE 5'h0f
`define ADDR_COLUMN_MODE 5'h10
`define ADDR_EXPOSURE 5'h11
// Address of the soft reset
`define SOFT_RESET_N 5'h1F //last address
// Camera config registers default values
parameter WIDTH = 16'd320;
parameter HEIGHT = 16'd240;
parameter START_ROW = 16'h0036;
parameter START_COLUMN = 16'h0010;
parameter ROW_SIZE = 16'h059f;
parameter COLUMN_SIZE = 16'h077f;
parameter ROW_MODE = 16'h0002;
parameter COLUMN_MODE = 16'h0002;
parameter EXPOSURE = 16'h07c0;
// image_capture regs
reg start_capture;
reg [15:0] capture_width;
reg [15:0] capture_height;
reg [31:0] buff0;
reg [31:0] buff1;
reg buff0full;
reg buff1full;
wire standby;
// camera_config regs
reg [15:0] data_width;
reg [15:0] data_height;
reg [15:0] data_start_row;
reg [15:0] data_start_column;
reg [15:0] data_row_size;
reg [15:0] data_column_size;
reg [15:0] data_row_mode;
reg [15:0] data_column_mode;
reg [15:0] data_exposure;
//soft_reset reg
reg cam_soft_reset_n;
// Read/Write registers
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
start_capture <= 1'b0;
capture_width <= 16'd0;
capture_height <= 16'd0;
buff0[31:0] <= 32'd0;
buff1[31:0] <= 32'd0;
data_width[15:0] <= WIDTH[15:0];
data_height[15:0] <= HEIGHT[15:0];
data_start_row[15:0] <= START_ROW[15:0];
data_start_column[15:0] <= START_COLUMN[15:0];
data_row_size[15:0] <= ROW_SIZE[15:0];
data_column_size[15:0] <= COLUMN_SIZE[15:0];
data_row_mode[15:0] <= ROW_MODE[15:0];
data_column_mode[15:0] <= COLUMN_MODE[15:0];
data_exposure[15:0] <= EXPOSURE[15:0];
cam_soft_reset_n <= 1;
end
else begin
if (avs_s1_read) begin
case (avs_s1_address)
//image_capture
`ADDR_START_CAPTURE:
avs_s1_readdata[31:0] <= {31'b0, start_capture};
`ADDR_CAPTURE_WIDTH:
avs_s1_readdata[31:0] <= {16'b0, capture_width};
`ADDR_CAPTURE_HEIGHT:
avs_s1_readdata[31:0] <= {16'b0, capture_height};
`ADDR_BUFF0:
avs_s1_readdata[31:0] <= buff0;
`ADDR_BUFF1:
avs_s1_readdata[31:0] <= buff1;
`ADDR_BUFF0FULL:
avs_s1_readdata[31:0] <= {31'b0, buff0full};
`ADDR_BUFF1FULL:
avs_s1_readdata[31:0] <= {31'b0, buff1full};
`ADDR_CAPTURE_STANDBY:
avs_s1_readdata[31:0] <= {31'b0, standby};
//camera_config
`ADDR_WIDTH:
avs_s1_readdata[15:0] <= data_width[15:0];
`ADDR_HEIGHT:
avs_s1_readdata[15:0] <= data_height[15:0];
`ADDR_START_ROW:
avs_s1_readdata[15:0] <= data_start_row[15:0];
`ADDR_START_COLUMN:
avs_s1_readdata[15:0] <= data_start_column[15:0];
`ADDR_ROW_SIZE:
avs_s1_readdata[15:0] <= data_row_size[15:0];
`ADDR_COLUMN_SIZE:
avs_s1_readdata[15:0] <= data_column_size[15:0];
`ADDR_ROW_MODE:
avs_s1_readdata[15:0] <= data_row_mode[15:0];
`ADDR_COLUMN_MODE:
avs_s1_readdata[15:0] <= data_column_mode[15:0];
`ADDR_EXPOSURE:
avs_s1_readdata[15:0] <= data_exposure[15:0];
//soft reset
`SOFT_RESET_N:
avs_s1_readdata[31:0] <= {31'b0, cam_soft_reset_n};
default:
avs_s1_readdata <= {32'd0};
endcase
end
// if avs_s1_read is FALSE...
else begin
if (avs_s1_write) begin
case (avs_s1_address)
//image_capture
`ADDR_START_CAPTURE:
start_capture <= avs_s1_writedata[0];
`ADDR_CAPTURE_WIDTH:
capture_width <= avs_s1_writedata[16:0];
`ADDR_CAPTURE_HEIGHT:
capture_height <= avs_s1_writedata[16:0];
`ADDR_BUFF0:
buff0 <= avs_s1_writedata[31:0];
`ADDR_BUFF1:
buff1 <= avs_s1_writedata[31:0];
//`ADDR_CAPTURE_STANDBY://not writable
`ADDR_WIDTH:
data_width[15:0] <= avs_s1_writedata[15:0];
`ADDR_HEIGHT:
data_height[15:0] <= avs_s1_writedata[15:0];
`ADDR_START_ROW:
data_start_row[15:0] <= avs_s1_writedata[15:0];
`ADDR_START_COLUMN:
data_start_column[15:0] <= avs_s1_writedata[15:0];
`ADDR_ROW_SIZE:
data_row_size[15:0] <= avs_s1_writedata[15:0];
`ADDR_COLUMN_SIZE:
data_column_size[15:0] <= avs_s1_writedata[15:0];
`ADDR_ROW_MODE:
data_row_mode[15:0] <= avs_s1_writedata[15:0];
`ADDR_COLUMN_MODE:
data_column_mode[15:0] <= avs_s1_writedata[15:0];
`ADDR_EXPOSURE:
data_exposure[15:0] <= avs_s1_writedata[15:0];
`SOFT_RESET_N:
cam_soft_reset_n <= avs_s1_writedata[0];
endcase
end
end
end
end
//buff0full and buff1full registers
//this signals are coming from the capture_image and may be clocked
//by a different clock. Thats why asynchronous set is done here
//to set this signals. The processor uses this signals to know that
//one line has finished and can read the buffer. The processor is
//in charge of erase this signals through the avalon bus.
always @(posedge clk or negedge reset_n or posedge avs_export_buff0full)
begin
if (avs_export_buff0full) buff0full <= 1'b1;
else if (!reset_n) buff0full <= 1'b0;
else begin
if (avs_s1_write == 1) begin
case (avs_s1_address)
`ADDR_BUFF0FULL: buff0full <= avs_s1_writedata[0];
endcase
end
end
end
always @(posedge clk or negedge reset_n or posedge avs_export_buff1full)
begin
if (avs_export_buff1full) buff1full <= 1'b1;
else if (!reset_n) buff1full <= 1'b0;
else begin
if (avs_s1_write == 1) begin
case (avs_s1_address)
`ADDR_BUFF1FULL: buff1full <= avs_s1_writedata[0];
endcase
end
end
end
// Control signals to export to the image capture
assign avs_export_capture_width = capture_width;
assign avs_export_capture_height = capture_height;
assign avs_export_start_capture = start_capture;
assign avs_export_buff0 = buff0;
assign avs_export_buff1 = buff1;
assign standby = avs_export_capture_standby;
// Registers to export to the camera_config
assign avs_export_start_row[15:0] = data_start_row[15:0];
assign avs_export_start_column[15:0] = data_start_column[15:0];
assign avs_export_row_size[15:0] = data_row_size[15:0];
assign avs_export_column_size[15:0] = data_column_size[15:0];
assign avs_export_row_mode[15:0] = data_row_mode[15:0];
assign avs_export_column_mode[15:0] = data_column_mode[15:0];
assign avs_export_exposure[15:0] = data_exposure[15:0];
// Registers to export to the camera_config an
assign avs_export_width[15:0] = data_width[15:0];
assign avs_export_height[15:0] = data_height[15:0];
//soft reset
assign avs_export_cam_soft_reset_n = cam_soft_reset_n;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:23:05 04/19/2017
// Design Name:
// Module Name: decrypt
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decrypt(
message,
DESkey,
decrypted,
done,
clk,
reset,
enable,
ack
);
input [7:0][7:0] message;
input [7:0][7:0] DESkey;
output [7:0][7:0] decrypted;
input clk, reset, enable, ack;
output done;
reg [63:0] msg, key, result;
reg [5:0] state;
reg [55:0] k;
reg [63:0] ip;
integer pc1[55:0] = {57, 49, 41, 33, 25, 17, 9, 1,
58, 50, 42, 34, 26, 18, 10, 2,
59, 51, 43, 35, 27, 19, 11, 3,
60, 52, 44, 36, 63, 55, 47, 39,
31, 23, 15, 7, 62, 54, 46, 38,
30, 22, 14, 6, 61, 53, 45, 37,
29, 21, 13, 5, 28, 20, 12, 4};
integer mp[63:0] = {58, 50, 42, 34, 26, 18, 10, 2,
60, 52, 44, 36, 28, 20, 12, 4,
62, 54, 46, 38, 30, 22, 14, 6,
64, 56, 48, 40, 32, 24, 16, 8,
57, 49, 41, 33, 25, 17, 9, 1,
59, 51, 43, 35, 27, 19, 11, 3,
61, 53, 45, 37, 29, 21, 13, 5,
63, 55, 47, 39, 31, 23, 15, 7};
localparam
INITIAL = 6'b0000001,
FIRSTPERMUTATION_MESSAGE_KEY = 6'b0000010,
LOADSHIFTARRAYS = 6'b0000100,
CREATEALLKEYS = 6'b0001000,
CREATEALLMESSAGEPERMUTATIONS = 6'b0010000,
ENCRYPT = 6'b0100000,
DONE = 7'b1000000;
always @ (posedge clk, posedge reset)
begin
if(reset)
begin
state <= INITIAL;
msg <= 8'hX;
key <= 8'hX;
result <= 8'hX;
end
else
begin
case (state)
INITIAL:
begin
//state
state <= FIRSTPERMUTATION_MESSAGE_KEY;
//rtl
msg <= message;
key <= DESkey;
result <= 0;
end
FIRSTPERMUTATION_MESSAGE_KEY:
begin
integer i;
//state
state <= LOADSHIFTARRAYS;
//rtl
for(i = 0; i < 56; i = i + 1)
begin
integer index;
index = pc1[i];
k[i] <= key[index];
end
/*for(int i = 0; i < 64; i = i + 1)
begin
integer index;
index = mp[i] - 1;
ip[i] <= key[index];
end*/
end
LOADSHIFTARRAYS:
begin
end
CREATEALLKEYS:
begin
end
CREATEALLMESSAGEPERMUTATIONS:
begin
end
ENCRYPT:
begin
end
DONE:
begin
end
endcase
end
end
assign encrypted = result;
assign done = (state == DONE);
endmodule
|
#include <bits/stdc++.h> using namespace std; typedef pair<int, int> pii; template <typename T> inline void read(T &x) { int ch = getchar(); x = 0; bool f = false; double d = 1; for (; ch != - && (ch < 0 || ch > 9 ); ch = getchar()) ; if (ch == - ) { f = true; ch = getchar(); } for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; if (ch == . ) for (ch = getchar(); ch >= 0 && ch <= 9 ; ch = getchar()) x += (ch - 0 ) * (d *= 0.1); if (f) x = -x; } template <typename T> inline bool chkmax(T &a, const T &b) { if (a < b) return a = b, 1; return 0; } template <typename T> inline bool chkmin(T &a, const T &b) { if (a > b) return a = b, 1; return 0; } const int K = 81, N = 170, M = N << 4, INF = 0x3f3f3f3f; int n, k, S, T, a[K], c[K], head[N], to[M], nxt[M], cap[M], w[M], tmp[K]; inline void add(int a, int b, int c, int d) { static int cnt = 1; to[++cnt] = b; nxt[cnt] = head[a]; head[a] = cnt; cap[cnt] = c; w[cnt] = d; to[++cnt] = a; nxt[cnt] = head[b]; head[b] = cnt; cap[cnt] = 0; w[cnt] = -d; } int dis[N], inc[N], q[N], f, r, pre[N], ans; bool inq[N]; inline void AMOD(int &x) { ++x; if (x >= N) x = 0; } inline bool spfa() { memset(inq, 0, sizeof inq); memset(dis, 0x3f, sizeof dis); f = r = 0; q[r++] = S; inc[S] = INF; dis[S] = 0; inq[S] = true; while (f != r) { int u = q[f]; AMOD(f); inq[u] = false; for (register int i = head[u]; i; i = nxt[i]) if (cap[i] && chkmin(dis[to[i]], dis[u] + w[i])) { inc[to[i]] = min(inc[u], cap[i]); pre[to[i]] = i; if (!inq[to[i]]) { inq[to[i]] = true; q[r] = to[i]; AMOD(r); } } } return dis[T] < INF; } int main() { read(n); read(k); for (register int i = 1; i <= n; ++i) read(a[i]); for (register int i = 1; i <= n; ++i) read(c[i]); T = 1 + (S = n << 1 | 1); for (register int i = 1; i <= n; ++i) { add(S, i, 1, c[a[i]]); add(i, i + n, 1, 0); add(i + n, T, 1, 0); if (i < n) add(i, i + 1, k - 1, 0); if (tmp[a[i]]) add(i - 1, tmp[a[i]] + n, 1, -c[a[i]]); tmp[a[i]] = i; } while (spfa()) { ans += inc[T] * dis[T]; for (register int u = T; u; u = to[pre[u] ^ 1]) { cap[pre[u]] -= inc[T]; cap[pre[u] ^ 1] += inc[T]; } } printf( %d , ans); }
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 1G Ethernet MAC with RGMII interface
*/
module eth_mac_1g_rgmii #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-6, 7-series
// Use BUFG for Virtex-5, Spartan-6, Ultrascale
parameter CLOCK_INPUT_STYLE = "BUFG",
// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
input wire gtx_clk,
input wire gtx_clk90,
input wire gtx_rst,
output wire rx_clk,
output wire rx_rst,
output wire tx_clk,
output wire tx_rst,
/*
* AXI input
*/
input wire [7:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* RGMII interface
*/
input wire rgmii_rx_clk,
input wire [3:0] rgmii_rxd,
input wire rgmii_rx_ctl,
output wire rgmii_tx_clk,
output wire [3:0] rgmii_txd,
output wire rgmii_tx_ctl,
/*
* Status
*/
output wire tx_error_underflow,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire [1:0] speed,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
wire [7:0] mac_gmii_rxd;
wire mac_gmii_rx_dv;
wire mac_gmii_rx_er;
wire mac_gmii_tx_clk_en;
wire [7:0] mac_gmii_txd;
wire mac_gmii_tx_en;
wire mac_gmii_tx_er;
reg [1:0] speed_reg = 2'b10;
reg mii_select_reg = 1'b0;
(* srl_style = "register" *)
reg [1:0] tx_mii_select_sync = 2'd0;
always @(posedge tx_clk) begin
tx_mii_select_sync <= {tx_mii_select_sync[0], mii_select_reg};
end
(* srl_style = "register" *)
reg [1:0] rx_mii_select_sync = 2'd0;
always @(posedge rx_clk) begin
rx_mii_select_sync <= {rx_mii_select_sync[0], mii_select_reg};
end
// PHY speed detection
reg [2:0] rx_prescale = 3'd0;
always @(posedge rx_clk) begin
rx_prescale <= rx_prescale + 3'd1;
end
(* srl_style = "register" *)
reg [2:0] rx_prescale_sync = 3'd0;
always @(posedge gtx_clk) begin
rx_prescale_sync <= {rx_prescale_sync[1:0], rx_prescale[2]};
end
reg [6:0] rx_speed_count_1 = 0;
reg [1:0] rx_speed_count_2 = 0;
always @(posedge gtx_clk) begin
if (gtx_rst) begin
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
speed_reg <= 2'b10;
mii_select_reg <= 1'b0;
end else begin
rx_speed_count_1 <= rx_speed_count_1 + 1;
if (rx_prescale_sync[1] ^ rx_prescale_sync[2]) begin
rx_speed_count_2 <= rx_speed_count_2 + 1;
end
if (&rx_speed_count_1) begin
// reference count overflow - 10M
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
speed_reg <= 2'b00;
mii_select_reg <= 1'b1;
end
if (&rx_speed_count_2) begin
// prescaled count overflow - 100M or 1000M
rx_speed_count_1 <= 0;
rx_speed_count_2 <= 0;
if (rx_speed_count_1[6:5]) begin
// large reference count - 100M
speed_reg <= 2'b01;
mii_select_reg <= 1'b1;
end else begin
// small reference count - 1000M
speed_reg <= 2'b10;
mii_select_reg <= 1'b0;
end
end
end
end
assign speed = speed_reg;
rgmii_phy_if #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.USE_CLK90(USE_CLK90)
)
rgmii_phy_if_inst (
.clk(gtx_clk),
.clk90(gtx_clk90),
.rst(gtx_rst),
.mac_gmii_rx_clk(rx_clk),
.mac_gmii_rx_rst(rx_rst),
.mac_gmii_rxd(mac_gmii_rxd),
.mac_gmii_rx_dv(mac_gmii_rx_dv),
.mac_gmii_rx_er(mac_gmii_rx_er),
.mac_gmii_tx_clk(tx_clk),
.mac_gmii_tx_rst(tx_rst),
.mac_gmii_tx_clk_en(mac_gmii_tx_clk_en),
.mac_gmii_txd(mac_gmii_txd),
.mac_gmii_tx_en(mac_gmii_tx_en),
.mac_gmii_tx_er(mac_gmii_tx_er),
.phy_rgmii_rx_clk(rgmii_rx_clk),
.phy_rgmii_rxd(rgmii_rxd),
.phy_rgmii_rx_ctl(rgmii_rx_ctl),
.phy_rgmii_tx_clk(rgmii_tx_clk),
.phy_rgmii_txd(rgmii_txd),
.phy_rgmii_tx_ctl(rgmii_tx_ctl),
.speed(speed)
);
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(mac_gmii_rxd),
.gmii_rx_dv(mac_gmii_rx_dv),
.gmii_rx_er(mac_gmii_rx_er),
.gmii_txd(mac_gmii_txd),
.gmii_tx_en(mac_gmii_tx_en),
.gmii_tx_er(mac_gmii_tx_er),
.rx_clk_enable(1'b1),
.tx_clk_enable(mac_gmii_tx_clk_en),
.rx_mii_select(rx_mii_select_sync[1]),
.tx_mii_select(tx_mii_select_sync[1]),
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; bool ex[100]; int att[100]; int de[100]; int jo[100]; int n, m, n1, n2; int ae() { int ina = 0; int inb = 0; pair<int, bool> mi[200]; for (int i = 0; i < n1; i++) mi[i].first = att[i], mi[i].second = 0; for (int i = n1; i < n1 + m; i++) { mi[i].first = jo[i - n1], mi[i].second = 1; } sort(mi, mi + m + n1); int v = 0; int y = 0; for (int i = 0; i < n1 + m; i++) { if (mi[i].second == 0) v++; else if (v) { v--; y++; } } int v1 = 0; int vt = 0; for (int i = 0; i < y; i++) { vt = jo[m - i - 1] - att[i]; if (vt > 0) v1 += vt; } return v1; } bool di() { int in1 = 0; int in2 = 0; while (true) { if (in2 == n2) return true; if (in1 == m) return false; while (jo[in1++] <= de[in2]) { if (in1 == m) return false; } in1--; ex[in1] = 1; in1++, in2++; } } bool di2() { int in1 = 0; int in2 = 0; while (true) { if (in2 == n1) return true; if (in1 == m) return false; while (ex[in1++] == 1) ; in1--; if (in1 == m) return 0; while (jo[in1++] < att[in2]) { if (in1 == m) return false; } in1--; in1++, in2++; } } int main() { cin >> n >> m; for (int i = 0; i < n; i++) { string s; int t; cin >> s >> t; if (s[0] == A ) { att[n1++] = t; } else { de[n2++] = t; } } for (int i = 0; i < m; i++) cin >> jo[i]; sort(jo, jo + m); sort(de, de + n2); sort(att, att + n1); int m1 = 0; if (di() && di2()) { for (int i = 0; i < m; i++) if (!(ex[i] == 1)) m1 += jo[i]; for (int i = 0; i < n1; i++) m1 -= att[i]; } cout << max(m1, ae()); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; char s[1001001]; int p[1001001] = {1}; int v[10][1001001], deg[1001001]; int Rand() { return rand() * rand(); } int main() { scanf( %s , s); n = strlen(s); for (int i = 1; i <= n; i++) { p[i] = p[i - 1] * 10 % 7; } int rlt = 0; reverse(s, s + n); for (int i = 0; s[i]; i++) { int c = s[i] - 0 ; rlt = (rlt + p[i] * c) % 7; v[c][deg[c]++] = i; } while (rlt) { int x = rand() % 9 + 1; int y = rand() % 9 + 1; if (x == y || !deg[x] || !deg[y]) { continue; } int tx = Rand() % deg[x]; int ty = Rand() % deg[y]; swap(v[x][tx], v[y][ty]); s[v[x][tx]] = x + 0 ; s[v[y][ty]] = y + 0 ; rlt = rlt + (p[v[x][tx]] - p[v[y][ty]]) * (x - y); rlt %= 7; if (rlt < 0) rlt += 7; } reverse(s, s + n); puts(s); return 0; }
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29455 $
// $Date: 2012-08-27 22:02:09 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// A synchronization module for resets. Output resets are held for
// RSTDELAY+1 cycles, RSTDELAY >= 0. Both assertion and deassertions is
// synchronized to the clock.
module PositiveReset (
IN_RST,
CLK,
OUT_RST
);
parameter RSTDELAY = 1 ; // Width of reset shift reg
input CLK ;
input IN_RST ;
output OUT_RST ;
(* ASYNC_REG = "true" *)
reg reset_meta ;
reg [RSTDELAY:1] reset_hold ;
wire [RSTDELAY+1:0] next_reset = {reset_hold, reset_meta, 1'b0} ;
assign OUT_RST = reset_hold[RSTDELAY] ;
always @( posedge CLK ) // reset is read synchronous with clock
begin
if (IN_RST == `BSV_RESET_VALUE)
begin
reset_meta <= 1;
reset_hold <= `BSV_ASSIGNMENT_DELAY -1 ;
end
else
begin
reset_meta <= next_reset[0];
reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:1];
end
end // always @ ( posedge CLK )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
#0 ;
// initialize out of reset forcing the designer to do one
reset_hold = 0 ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // PositiveReset
|
#include <bits/stdc++.h> #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( O8 ) #pragma GCC optimization( unroll-loops ) using namespace std; const long long int N = 60 + 5, mod = 1e9 + 7, inf = 1e12, maxq = 5e5 + 30, maxm = 1e3 + 30; const long double eps = 0.0000001; long long int poww(long long int a, long long int b) { return (!b ? 1 : (b & 1 ? a * poww(a * a % mod, b / 2) % mod : poww(a * a % mod, b / 2) % mod)); } int mat[N][N][N]; int dp[maxm][N][N]; int d[N][N][N][N]; int n, m, r; int main() { ios ::sync_with_stdio(0); cin.tie(0); cout.tie(0); memset(d, 63, sizeof d); cin >> n >> m >> r; for (int i = 1; i < m + 1; i++) for (int j = 1; j < n + 1; j++) for (int k = 1; k < n + 1; k++) cin >> mat[i][j][k]; for (int i = 1; i < n + 1; i++) for (int j = 1; j < n + 1; j++) for (int k = 1; k < m + 1; k++) d[0][i][j][k] = mat[k][i][j]; for (int k = 1; k < n + 1; k++) for (int i = 1; i < n + 1; i++) for (int j = 1; j < n + 1; j++) { if (i != j) { for (int x = 1; x < m + 1; x++) { d[k][i][j][x] = min(d[k - 1][i][j][x], d[k - 1][i][k][x] + d[k - 1][k][j][x]); } } } for (int i = 1; i < n + 1; i++) for (int j = 1; j < n + 1; j++) { if (i != j) { for (int k = 1; k < m + 1; k++) { if (k > 1) { if (dp[0][i][j] > d[n][i][j][k]) dp[0][i][j] = d[n][i][j][k]; } else dp[0][i][j] = d[n][i][j][k]; } } else dp[0][i][j] = 0; } for (int k = 1; k < 1001; k++) { for (int i = 1; i < n + 1; i++) { for (int j = 1; j < n + 1; j++) { dp[k][i][j] = dp[k - 1][i][j]; if (i == j) continue; for (int y = 1; y < n + 1; y++) if (dp[k - 1][i][y] + dp[0][y][j] < dp[k][i][j]) dp[k][i][j] = dp[k - 1][i][y] + dp[0][y][j]; } } } int x, y, z; for (int i = 0; i < r; i++) { cin >> x >> y >> z; cout << dp[z][x][y] << n ; } return 0; }
|
#include <bits/stdc++.h> int main() { long int n; scanf( %ld , &n); long int a[n + 1], i, sum = 0; for (i = 0; i < n; i++) { scanf( %ld , &a[i]); sum = sum + a[i]; } if (sum % n == 0) { printf( %ld n , n); } else { printf( %ld n , n - 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MX = 1e5 + 7; vector<long long> v[MX]; bool vis[MX]; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n; cin >> n; pair<long long, long long> p[n]; for (long long i = 0; i < n; i++) cin >> p[i].first >> p[i].second; long double l = 0, r = 1e10; for (long long i = 0; i < 100; i++) { long long cnt; long double mid = (l + r) / 2, d = -1e20; for (cnt = 0; cnt < n; cnt++) { if (p[cnt].second > 0) d = max(d, p[cnt].first + mid * p[cnt].second); else if (p[cnt].first + mid * p[cnt].second <= d) break; } if (cnt < n) r = mid; else l = mid; } if (r == 1e10) cout << -1; else cout << fixed << setprecision(18) << l; }
|
#include <bits/stdc++.h> using namespace std; int qread() { char c; int s = 0, f = 1; while ((c = getchar()) < 0 || c > 9 ) (c == - ) && (f = -1); do s = s * 10 + c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ); return s * f; } int n, m; const int mod = 1e9 + 7; int a[100011], pos[100011], bin[100011], inv[100011], sum[100011], lp = 0, val[100011], vv[100011], svv[100011]; struct Ques { int l, r, id; bool operator<(const Ques &b) const { return r < b.r; } } q[100011]; int ans[100011]; int WWW(long long v) { return v > 2000000001 ? 2000000001 : v; } int main() { n = qread(); m = qread(); bin[0] = inv[0] = 1; for (int i = 1; i <= n; i++) a[i] = qread(), bin[i] = (bin[i - 1] << 1) % mod, inv[i] = 1ll * inv[i - 1] * ((mod + 1) >> 1) % mod, sum[i] = ((sum[i - 1] + 1ll * a[i] * bin[i]) % mod + mod) % mod; for (int i = 1; i <= m; i++) { q[i].l = qread(); q[q[i].id = i].r = qread(); } sort(q + 1, q + 1 + m); pos[lp = 1] = 1; int j = 1; val[1] = a[1] * 2; vv[1] = svv[1] = ((a[1] * 2) % mod + mod) % mod; while (j <= m && q[j].r == 1) ans[q[j].id] = (a[1] + mod) % mod, j++; for (int i = 2; i <= n; i++) { if (a[i] <= 0) pos[++lp] = i, val[lp] = 2 * a[i], vv[lp] = (a[i] * 2ll % mod + mod) % mod, svv[lp] = (svv[lp - 1] + vv[lp]) % mod; else { int cur = WWW(0ll + val[lp] + bin[pos[lp] - pos[lp - 1] + 1] * 1ll * a[i]); int cvv = (vv[lp] + bin[pos[lp] - pos[lp - 1] + 1] * 1ll * a[i]) % mod; lp--; while (lp && cur > 0) { cur = WWW(0ll + val[lp] + (pos[lp] - pos[lp - 1] > 31 ? 2000000001 : bin[pos[lp] - pos[lp - 1]]) * 1ll * cur); cvv = (vv[lp] + bin[pos[lp] - pos[lp - 1]] * 1ll * cvv) % mod; lp--; } val[++lp] = cur; pos[lp] = i; vv[lp] = cvv; svv[lp] = (svv[lp - 1] + vv[lp]) % mod; } while (j <= m && q[j].r == i) { if (q[j].l == q[j].r) { ans[q[j].id] = (a[i] + mod) % mod; j++; continue; } int l = q[j].l + 1, Ans = (a[q[j].l] + mod) % mod; int L = 1, R = lp; while (L < R) { int mid = (L + R) >> 1; if (pos[mid] >= l) R = mid; else L = mid + 1; } Ans = (Ans + svv[lp] - svv[L]) % mod; Ans = (Ans + mod) % mod; Ans = (Ans + (sum[pos[L]] - sum[l - 1] + mod) * 1ll * inv[l - 1]) % mod; ans[q[j].id] = Ans; j++; } } for (int i = 1; i <= m; i++) printf( %d n , ans[i]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A21OI_BEHAVIORAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_2_V
`define SKY130_FD_SC_MS__FILL_2_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_2_V
|
module test;
reg fail = 1'b0;
reg [3:0] in = 4'b0;
wire [3:0] bus = in;
initial begin
// Check the initial value.
#1 if (bus !== 4'b0) begin
$display("FAILED: initial value, got %b, expected 0000.", bus);
fail = 1'b1;
end
// Check a bit froce and verify a normal bit assign does nothing.
#1 force bus[0] = 1'b1;
#1 in[0] = 1'bz;
#1 if (bus !== 4'b0001) begin
$display("FAILED: force of bus[0], got %b, expected 0001.", bus);
fail = 1'b1;
end
// Check a part force.
#1 force bus[3:2] = 2'b11;
#1 if (bus !== 4'b1101) begin
$display("FAILED: force of bus[3:2], got %b, expected 1101.", bus);
fail = 1'b1;
end
// Check that we can change an unforced bit.
#1 in[1] = 1'bz;
#1 if (bus !== 4'b11z1) begin
$display("FAILED: assignment of bus[1], got %b, expected 11z1.", bus);
fail = 1'b1;
end
#1 in[1] = 1'b0;
// Check a bit release.
#1 release bus[0];
#1 if (bus !== 4'b110z) begin
$display("FAILED: release of bus[0], got %b, expected 110z.", bus);
fail = 1'b1;
end
// Check a part release.
#1 release bus[3:2];
#1 if (bus !== 4'b000z) begin
$display("FAILED: release of bus[3:2], got %b, expected 000z.", bus);
fail = 1'b1;
end
// Check a force from the upper thread bits (>= 8).
#1 force bus[2:1] = 2'bx1;
#1 if (bus !== 4'b0x1z) begin
$display("FAILED: force of bus[2:1], got %b, expected 0x1z.", bus);
fail = 1'b1;
end
if (!fail) $display("PASSED");
end
endmodule
|
/*---------------------------------------------------------------------------------------------------------------------
-- Author: Peter Hasza,
--
-- Create Date: 04/23/2017
-- Module Name: CLK_gen
-- Project Name: AXI_SPI_IF
-- Description:
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2017.apr.2 | hp3265 || Initial version
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-----------------------------------------------------------------------------------------------------------------------*/
module CLK_gen (
input clk_i,
input reset_n_i,
input clk_en,
input [3:0] clk_div_i,
output clk_o
);
reg clk_y;
reg [3:0] clk_cnt_y;
always@(posedge clk_i,negedge reset_n_i)
begin
if (!reset_n_i)
begin
clk_cnt_y <= 0;
clk_y <= 0;
end
else if(clk_en)
begin
if(clk_cnt_y == clk_div_i-1)
begin
clk_y <= ~clk_y;
clk_cnt_y <= 0;
end
else
clk_cnt_y <= clk_cnt_y +1;
end
else
clk_y <= 0;
end
assign clk_o = (clk_div_i==0) ? clk_i : clk_y;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 3e6 + 10, Maxk = 1e6 + 10; int a[Maxn], l[Maxn], r[Maxn], s[Maxn], n, k; vector<int> v[Maxk]; long long ans; int ask(int k, int l, int r) { int x = upper_bound(v[k].begin(), v[k].end(), r) - v[k].begin() - 1, y = lower_bound(v[k].begin(), v[k].end(), l) - v[k].begin() - 1; return x - y; } int main() { ios::sync_with_stdio(0); int i, j; cin >> n >> k; for (i = 1; i <= n; i++) cin >> a[i], s[i] = (s[i - 1] + a[i]) % k; for (i = 0; i <= n; i++) v[s[i]].push_back(i); for (i = 1; i <= n; i++) for (l[i] = i - 1; l[i] >= 1 && a[l[i]] < a[i]; l[i] = l[l[i]]) ; for (i = n; i >= 1; i--) for (r[i] = i + 1; r[i] <= n && a[r[i]] <= a[i]; r[i] = r[r[i]]) ; for (i = 1; i <= n; i++) if (i - l[i] < r[i] - i) { for (j = l[i] + 1; j <= i; j++) ans += ask((a[i] + s[j - 1]) % k, i, r[i] - 1); } else { for (j = i; j <= r[i] - 1; j++) ans += ask(((s[j] - a[i]) % k + k) % k, l[i], i - 1); } cout << ans - n << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22O_2_V
`define SKY130_FD_SC_HDLL__A22O_2_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22o_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22O_2_V
|
#include <bits/stdc++.h> using namespace std; struct point { int x, y; point() {} point(int x, int y) : x(x), y(y) {} } p[1010]; point operator-(const point &a, const point &b) { return point(a.x - b.x, a.y - b.y); } long long operator*(const point &a, const point &b) { return (long long)a.x * b.y - (long long)a.y * b.x; } int main() { int n, i, x, y, low, high; cin >> n; for (i = 0; i < n; i++) { cin >> x >> y; p[i] = point(x, y); } low = p[0].x; high = p[1].x; if (low > high) swap(low, high); p[n] = p[0]; for (i = 0; i < n; i++) { while (low <= high && (p[i + 1] - p[i]) * (point(low, p[0].y) - p[i]) > 0) low++; while (low <= high && (p[i + 1] - p[i]) * (point(high, p[0].y) - p[i]) > 0) high--; } cout << high - low + 1 << endl; }
|
/*
* Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
* Don't remove this header.
* When you use this source, there is a need to inherit this header.
*
* This software is released under the MIT License.
* http://opensource.org/licenses/mit-license.php
*
* For further information please contact.
* URI: http://www.aquaxis.com/
* E-Mail: info(at)aquaxis.com
*/
module aq_axi_lite_slave(
// AXI4 Lite Interface
input ARESETN,
input ACLK,
// Write Address Channel
input [31:0] S_AXI_AWADDR,
input [3:0] S_AXI_AWCACHE,
input [2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
// Write Data Channel
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
// Write Response Channel
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
// Read Address Channel
input [31:0] S_AXI_ARADDR,
input [3:0] S_AXI_ARCACHE,
input [2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
// Read Data Channel
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
// Local Interface
output LOCAL_CS,
output LOCAL_RNW,
input LOCAL_ACK,
output [31:0] LOCAL_ADDR,
output [3:0] LOCAL_BE,
output [31:0] LOCAL_WDATA,
input [31:0] LOCAL_RDATA
);
/*
CACHE[3:0]
WA RA C B
0 0 0 0 Noncacheable and nonbufferable
0 0 0 1 Bufferable only
0 0 1 0 Cacheable, but do not allocate
0 0 1 1 Cacheable and Bufferable, but do not allocate
0 1 1 0 Cacheable write-through, allocate on reads only
0 1 1 1 Cacheable write-back, allocate on reads only
1 0 1 0 Cacheable write-through, allocate on write only
1 0 1 1 Cacheable write-back, allocate on writes only
1 1 1 0 Cacheable write-through, allocate on both reads and writes
1 1 1 1 Cacheable write-back, allocate on both reads and writes
PROR
[2]:0:Data Access
1:Instruction Access
[1]:0:Secure Access
1:NoSecure Access
[0]:0:Privileged Access
1:Normal Access
RESP
00: OK
01: EXOK
10: SLVERR
11: DECERR
*/
localparam S_IDLE = 2'd0;
localparam S_WRITE = 2'd1;
localparam S_WRITE2 = 2'd2;
localparam S_READ = 2'd3;
reg [1:0] state;
reg reg_rnw;
reg [31:0] reg_addr, reg_wdata;
reg [3:0] reg_be;
always @( posedge ACLK or negedge ARESETN ) begin
if( !ARESETN ) begin
state <= S_IDLE;
reg_rnw <= 1'b0;
reg_addr <= 32'd0;
reg_wdata <= 32'd0;
reg_be <= 4'd0;
end else begin
case( state )
S_IDLE: begin
if( S_AXI_AWVALID ) begin
reg_rnw <= 1'b0;
reg_addr <= S_AXI_AWADDR;
state <= S_WRITE;
end else if( S_AXI_ARVALID ) begin
reg_rnw <= 1'b1;
reg_addr <= S_AXI_ARADDR;
state <= S_READ;
end
end
S_WRITE: begin
if( S_AXI_WVALID ) begin
state <= S_WRITE2;
reg_wdata <= S_AXI_WDATA;
reg_be <= S_AXI_WSTRB;
end
end
S_WRITE2: begin
if( LOCAL_ACK & S_AXI_BREADY ) begin
state <= S_IDLE;
end
end
S_READ: begin
if( LOCAL_ACK & S_AXI_RREADY ) begin
state <= S_IDLE;
end
end
default: begin
state <= S_IDLE;
end
endcase
end
end
// Local Interface
assign LOCAL_CS = (( state == S_WRITE2 )?1'b1:1'b0) | (( state == S_READ )?1'b1:1'b0) | 1'b0;
assign LOCAL_RNW = reg_rnw;
assign LOCAL_ADDR = reg_addr;
assign LOCAL_BE = reg_be;
assign LOCAL_WDATA = reg_wdata;
// Write Channel
assign S_AXI_AWREADY = ( state == S_WRITE )?S_AXI_AWVALID:1'b0;
assign S_AXI_WREADY = ( state == S_WRITE )?S_AXI_WVALID:1'b0;
assign S_AXI_BVALID = ( state == S_WRITE2 )?LOCAL_ACK:1'b0;
assign S_AXI_BRESP = 2'b00;
// Read Channel
assign S_AXI_ARREADY = ( state == S_READ )?S_AXI_ARVALID:1'b0;
assign S_AXI_RVALID = ( state == S_READ )?LOCAL_ACK:1'b0;
assign S_AXI_RRESP = 2'b00;
assign S_AXI_RDATA = ( state == S_READ )?LOCAL_RDATA:32'd0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 7; int n; int a[MAXN], r[MAXN], x[MAXN], vt[MAXN]; set<int> tset; int main() { cin >> n; int tmax = 0; for (int i = 0; i < n; i++) { cin >> a[i]; vt[a[i]] = i; if (a[i] > tmax) { r[i] = 1; tmax = a[i]; } } tset.insert(a[0]); x[0] -= r[0]; for (int j = 1; j < n; j++) { tset.insert(a[j]); set<int>::iterator it = tset.end(); it--; it--; set<int>::iterator it2 = tset.end(); it2--; if (*it == a[j]) { x[vt[*it2]]++; } x[j] -= r[j]; } int ans = a[0]; tmax = x[0]; for (int i = 0; i < n; i++) { if (x[i] > tmax) { tmax = x[i]; ans = a[i]; } else if (x[i] == tmax) { ans = min(ans, a[i]); } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; ifstream in( test.in ); ofstream out( test.out ); const int DIM = 2e3 + 1; const int INF = 1e9 + 7; int dp[DIM]; set<int> mst; deque<int> que; vector<int> edg[DIM]; int main() { ios::sync_with_stdio(false); cin.tie(); cout.tie(); int k, n; cin >> k >> n; for (int i = 1; i <= n; i++) { int x; cin >> x; mst.insert(x - k); } for (int x : mst) { for (int i = 0; i < DIM; i++) { if (i + x > -1 && i + x < DIM) edg[i].push_back(i + x); } } fill(dp, dp + DIM, INF); dp[DIM / 2] = 0; que.push_back(DIM / 2); int ans = INF; for (; que.empty() == false; que.pop_front()) { int x = que.front(); for (int y : edg[x]) { if (dp[y] == INF) dp[y] = dp[x] + 1, que.push_back(y); else if (y == DIM / 2) ans = min(ans, dp[x] + 1); } } cout << (ans == INF ? -1 : ans) << endl; return 0; }
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*****************
* Writes a 2-D signal into an In-System Modifiable Memory that can be read out
* over JTAG
*
* After running the design use the accompanying tcl script to generate a .csv
* of the data:
* quartus_stp -t acl_debug_mem.tcl
*****************/
module acl_debug_mem
#(
parameter WIDTH=16,
parameter SIZE=10
)
(
input logic clk,
input logic resetn,
input logic write,
input logic [WIDTH-1:0] data[SIZE]
);
/******************
* LOCAL PARAMETERS
*******************/
localparam ADDRWIDTH=$clog2(SIZE);
/******************
* SIGNALS
*******************/
logic [ADDRWIDTH-1:0] addr;
logic do_write;
/******************
* ARCHITECTURE
*******************/
always@(posedge clk or negedge resetn)
if (!resetn)
addr <= {ADDRWIDTH{1'b0}};
else if (addr != {ADDRWIDTH{1'b0}})
addr <= addr + 2'b01;
else if (write)
addr <= addr + 2'b01;
assign do_write = write | (addr != {ADDRWIDTH{1'b0}});
// Instantiate In-System Modifiable Memory
altsyncram altsyncram_component (
.address_a (addr),
.clock0 (clk),
.data_a (data[addr]),
.wren_a (do_write),
.q_a (),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ACLDEBUGMEM",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = SIZE,
altsyncram_component.widthad_a = ADDRWIDTH,
altsyncram_component.width_a = WIDTH,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.width_byteena_a = 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using P = pair<int, int>; const long long MOD = 1000000007; const long long INF = 1LL << 60; const int INT_INF = 1000000000; int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; void solve() { int n; cin >> n; vector<ll> a(n); for (auto &ai : a) cin >> ai; bool positive; if (a[0] < 0) positive = false; else positive = true; ll sum = 0; ll tmp = a[0]; for (int i = 1; i < n; i++) { if (positive) { if (a[i] > 0) { tmp = max(tmp, a[i]); } else { sum += tmp; tmp = a[i]; positive = false; } } else { if (a[i] > 0) { sum += tmp; tmp = a[i]; positive = true; } else { tmp = max(tmp, a[i]); } } } sum += tmp; cout << sum << endl; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; for (int i = 0; i < t; i++) solve(); return 0; }
|
`timescale 1ns / 1ps
`include "hal/WcaPortDefs.h" //grab register addresses.
// Name: WcaPortNull.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaPortNull(
//Port Controller interface.
inout [31:0] pifData, // 32 bit port interface data bus.
input wire [(NBITS_ADDR+2):0] portCtrl, // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
output wire [1:0] portCmd // Port Command ID
);
parameter ADDR_PORT = 0;
parameter NBITS_ADDR = 2;
wire isAddr = (ADDR_PORT == portCtrl[NBITS_ADDR+2:3]);
assign portCmd = (isAddr ) ? `PIFCMD_IDLE : 2'bz;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e17; struct Node { int to; long long dis; int type; Node(int a = 0, long long b = 0, int c = 0) { to = a; dis = b; type = c; } friend bool operator<(Node a, Node b) { if (a.dis != b.dis) return a.dis > b.dis; return a.type > b.type; } }; int n, m, k; int vis[100005], p[100005]; long long dis[100005]; vector<Node> v[100005]; void djs(int x) { memset(vis, 0, sizeof(vis)); memset(p, 0, sizeof(p)); for (int i = 0; i <= n; i++) dis[i] = INF; priority_queue<Node> q; q.push(Node(x, 0, 0)); dis[x] = 0; Node u, w; while (!q.empty()) { u = q.top(); q.pop(); if (u.dis != dis[u.to] || vis[u.to]) continue; vis[u.to] = 1; for (int i = 0; i < v[u.to].size(); i++) { w = v[u.to][i]; if (!vis[w.to]) { if (u.dis + w.dis < dis[w.to]) { dis[w.to] = u.dis + w.dis; q.push(Node(w.to, dis[w.to], 0)); p[w.to] = w.type; } else if (u.dis + w.dis == dis[w.to] && w.type == 0) { p[w.to] = w.type; } } } } } int main() { while (~scanf( %d%d%d , &n, &m, &k)) { for (int i = 0; i <= n; i++) { while (!v[i].empty()) v[i].clear(); } int a, b; long long c; for (int i = 0; i < m; i++) { scanf( %d%d%lld , &a, &b, &c); v[a].push_back(Node(b, c, 0)); v[b].push_back(Node(a, c, 0)); } for (int i = 0; i < k; i++) { scanf( %d%lld , &b, &c); v[1].push_back(Node(b, c, 1)); v[b].push_back(Node(1, c, 1)); } djs(1); for (int i = 2; i <= n; i++) { k -= p[i]; } printf( %d n , k); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 7; int main() { int n, k; scanf( %d%d , &n, &k); vector<int> ans; int a = (n - k) / 2; while (ans.size() < n) { for (int i = 0; i < a; i++) ans.push_back(0); ans.push_back(1); } for (int i = 0; i < n; i++) printf( %d , ans[i]); puts( ); }
|
`include "../rtl/shift_register.v"
`default_nettype none
`timescale 1ms/1us
module tb_shift_register;
parameter DEPTH = 4;
parameter WIDTH = 4;
reg clk;
reg rst_n;
reg en;
reg [WIDTH-1:0] d;
wire [WIDTH-1:0] q;
shift_register
#(
.DEPTH(DEPTH),
.WIDTH(WIDTH)
) _shift_register
(
.clk ( clk ) ,
.rst_n ( rst_n ) ,
.en ( en ) ,
.d ( d ) ,
.q ( q )
);
parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_shift_register.vcd");
$dumpvars(0, tb_shift_register);
#1 rst_n<=1'bx;clk<=1'bx;en<=1'bx;d<={WIDTH{1'bx}};
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;en<=0;d<=0;
repeat(5) @(posedge clk);
rst_n<=1;
@(posedge clk);
d<=1;
@(posedge clk);
en<=1;
@(posedge clk);
d<=2;
@(posedge clk);
d<=3;
@(posedge clk);
d<=4;
@(posedge clk);
d<=5;
@(posedge clk);
if(q !== 1)
$display("result == ", 1, " expected but ", q);
d<=6;
@(posedge clk);
if(q !== 2)
$display("result == ", 2, " expected but ", q);
d<=7;
@(posedge clk);
if(q !== 3)
$display("result == ", 3, " expected but ", q);
d<=8;
@(posedge clk);
if(q !== 4)
$display("result == ", 4, " expected but ", q);
en<=0;
@(posedge clk);
if(q !== 5)
$display("result == ", 5, " expected but ", q);
repeat(5) @(posedge clk);
$finish(2);
end
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; bool pal(string s) { long long n = s.size(); for (long long i = 0; i < n / 2; i++) if (s[i] != s[n - i - 1]) return false; return true; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long test = 1; while (test--) { long long n, k, x, ab = 1e10, p, c = 0, f; cin >> n >> k >> x; vector<long long> v(n); for (long long i = 0; i < n; i++) { cin >> v[i]; if (abs(v[i]) < abs(ab)) { ab = abs(v[i]); p = i; } if (v[i] < 0) c++; } if (c % 2 == 0) { f = abs(ab) / x + 1; f = min(f, k); k -= f; if (v[p] < 0) v[p] += f * x; else v[p] -= f * x; } set<pair<long long, long long> > s; for (long long i = 0; i < n; i++) s.insert({abs(v[i]), i}); while (k > 0) { k--; p = s.begin()->second; if (v[p] < 0) { v[p] -= x; s.erase(s.begin()); s.insert({abs(v[p]), p}); } else { v[p] += x; s.erase(s.begin()); s.insert({v[p], p}); } } for (long long i = 0; i < n; i++) cout << v[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 22, maxm = (1 << 21) + 5; int n, plc[maxm]; unsigned long long a[maxm], b[maxm], c[maxn]; char s[maxm]; void FMT(unsigned long long *a, int sgn) { for (int i = 0; i < n; i++) for (int j = 0; j < (1 << n); j++) if (!(j & (1 << i))) a[j | (1 << i)] = a[j | (1 << i)] + sgn * a[j]; } int main() { scanf( %d , &n); plc[0] = 0; for (int i = 1; i < (1 << n); i++) plc[i] = plc[i >> 1] + ((i & 1) << 1); scanf( %s , s); for (int i = 0; i < (1 << n); i++) a[i] = ((unsigned long long)(s[i] - 0 ) << plc[i]); scanf( %s , s); for (int i = 0; i < (1 << n); i++) b[i] |= ((unsigned long long)(s[i] - 0 ) << plc[i]); FMT(a, 1); FMT(b, 1); for (int i = 0; i < (1 << n); i++) c[i] = a[i] * b[i]; FMT(c, -1); for (int i = 0; i < (1 << n); i++) printf( %lld , (c[i] >> plc[i]) % 4); puts( ); return 0; }
|
//
// Copyright (c) 2002 Stephen Williams
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Binary ~| (nor) operator.
module main;
reg A, B;
reg result1;
wire result2 = A ~| B;
initial
begin
A = 0;
B = 0;
#1 result1 = A ~| B;
if (result1 !== 1'b1) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b1) begin
$display("FAILED");
$finish;
end
A = 1;
#1 result1 = A ~| B;
if (result1 !== 1'b0) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b0) begin
$display("FAILED");
$finish;
end
B = 1;
#1 result1 = A ~| B;
if (result1 !== 1'b0) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b0) begin
$display("FAILED");
$finish;
end
A = 0;
#1 result1 = A ~| B;
if (result1 !== 1'b0) begin
$display("FAILED");
$finish;
end
if (result2 !== 1'b0) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule // main
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Cache_DataRAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 232 07/05/2012 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Cache_DataRAM (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [10:0] address_a;
input [10:0] address_b;
input clock;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "36864"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]"
// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]"
// Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]"
// Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]"
// Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0
// Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; vector<int> g[100005]; int ans = 0; int csize[100005]; int dfs(int u, int fa) { csize[u] = 1; for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (v == fa) continue; dfs(v, u); csize[u] += csize[v]; if (csize[v] % 2 == 0) ans++; } } int main() { int n; while (cin >> n) { ans = 0; for (int i = 0; i <= n; i++) { g[i].clear(); } for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } if (n % 2) cout << -1 n ; else { dfs(1, 0); cout << ans << n ; } } return 0; }
|
`timescale 1 ns / 1 ps
module sample_generator_v1_0_M_AXIS #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
parameter integer C_M_AXIS_TDATA_WIDTH = 32,
// Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
parameter integer C_M_START_COUNT = 32
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Global ports
input wire M_AXIS_ACLK,
//
input wire M_AXIS_ARESETN,
// Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
output wire M_AXIS_TVALID,
// TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
// TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
// TLAST indicates the boundary of a packet.
output wire M_AXIS_TLAST,
// TREADY indicates that the slave can accept a transfer in the current cycle.
input wire M_AXIS_TREADY
);
//Total number of output data.
// Total number of output data
localparam NUMBER_OF_OUTPUT_WORDS = 8;
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
// WAIT_COUNT_BITS is the width of the wait counter.
localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
// bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
// Define the states of state machine
// The control state machine oversees the writing of input streaming data to the FIFO,
// and outputs the streaming data from the FIFO
parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
INIT_COUNTER = 2'b01, // This state initializes the counter, ones
// the counter reaches C_M_START_COUNT count,
// the state machine changes state to INIT_WRITE
SEND_STREAM = 2'b10; // In this state the
// stream data is output through M_AXIS_TDATA
// State variable
reg [1:0] mst_exec_state;
// Example design FIFO read pointer
reg [bit_num-1:0] read_pointer;
// AXI Stream internal signals
//wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
reg [WAIT_COUNT_BITS-1 : 0] count;
//streaming data valid
wire axis_tvalid;
//streaming data valid delayed by one clock cycle
reg axis_tvalid_delay;
//Last of the streaming data
wire axis_tlast;
//Last of the streaming data delayed by one clock cycle
reg axis_tlast_delay;
//FIFO implementation signals
reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
wire tx_en;
//The master has issued all the streaming data stored in FIFO
reg tx_done;
// I/O Connections assignments
assign M_AXIS_TVALID = axis_tvalid_delay;
assign M_AXIS_TDATA = stream_data_out;
assign M_AXIS_TLAST = axis_tlast_delay;
assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
// Control state machine implementation
always @(posedge M_AXIS_ACLK)
begin
if (!M_AXIS_ARESETN)
// Synchronous reset (active low)
begin
mst_exec_state <= IDLE;
count <= 0;
end
else
case (mst_exec_state)
IDLE:
// The slave starts accepting tdata when
// there tvalid is asserted to mark the
// presence of valid streaming data
//if ( count == 0 )
// begin
mst_exec_state <= INIT_COUNTER;
// end
//else
// begin
// mst_exec_state <= IDLE;
// end
INIT_COUNTER:
// The slave starts accepting tdata when
// there tvalid is asserted to mark the
// presence of valid streaming data
if ( count == C_M_START_COUNT - 1 )
begin
mst_exec_state <= SEND_STREAM;
end
else
begin
count <= count + 1;
mst_exec_state <= INIT_COUNTER;
end
SEND_STREAM:
// The example design streaming master functionality starts
// when the master drives output tdata from the FIFO and the slave
// has finished storing the S_AXIS_TDATA
if (tx_done)
begin
mst_exec_state <= IDLE;
end
else
begin
mst_exec_state <= SEND_STREAM;
end
endcase
end
//tvalid generation
//axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
//number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
// AXI tlast generation
// axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
// (0 to NUMBER_OF_OUTPUT_WORDS-1)
assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
// Delay the axis_tvalid and axis_tlast signal by one clock cycle
// to match the latency of M_AXIS_TDATA
always @(posedge M_AXIS_ACLK)
begin
if (!M_AXIS_ARESETN)
begin
axis_tvalid_delay <= 1'b0;
axis_tlast_delay <= 1'b0;
end
else
begin
axis_tvalid_delay <= axis_tvalid;
axis_tlast_delay <= axis_tlast;
end
end
//read_pointer pointer
always@(posedge M_AXIS_ACLK)
begin
if(!M_AXIS_ARESETN)
begin
read_pointer <= 0;
tx_done <= 1'b0;
end
else
if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
begin
if (tx_en)
// read pointer is incremented after every read from the FIFO
// when FIFO read signal is enabled.
begin
read_pointer <= read_pointer + 1;
tx_done <= 1'b0;
end
end
else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
begin
// tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
// has been out.
tx_done <= 1'b1;
end
end
//FIFO read enable generation
assign tx_en = M_AXIS_TREADY && axis_tvalid;
// Streaming output data is read from FIFO
always @( posedge M_AXIS_ACLK )
begin
if(!M_AXIS_ARESETN)
begin
stream_data_out <= 1;
end
else if (tx_en)// && M_AXIS_TSTRB[byte_index]
begin
stream_data_out <= read_pointer + 32'b1;
end
end
// Add user logic here
// User logic ends
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; int m = 0; while (n > 9) { n -= 9; m += 9 + n % 10; n /= 10; } cout << m + n << endl; return 0; }
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
//
// Copyright (c) 1999 Steve Tell ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Concat in fopen not substituted correctly.
module write_sp_vectors(Clk, a, b, c);
input Clk, a, b, c;
parameter fname = "PhCount.unnamed";
parameter source_id = "(unknown source module RCSID)$";
integer fp;
initial
begin
// fails at runtime: "ERROR: $fopen parameter must be a constant"
fp = $fopen({"work/",fname,".inv"});
// this fails too
// fp = $fopen({"blurfl", ".inv"});
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
$fdisplay(fp, "# captured from: %0s\n", source_id[8*80:8]);
`else
$fdisplay(fp, "# captured from: %0s\n", source_id[$bits(source_id)-1:8]);
`endif
end
endmodule
module main;
parameter fname = "PhCount.unnamed";
reg clk;
reg a,b,c;
write_sp_vectors #("sp2", "foo") v0 (clk,a, b, c);
initial
begin
#10 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } long long min(long long a, long long b) { return a < b ? a : b; } long long max(long long a, long long b) { return a > b ? a : b; } long long max3(long long a, long long b, long long c) { return max(max(a, b), c); } long long max4(long long a, long long b, long long c, long long d) { return max(max(a, b), max(c, d)); } long long min3(long long a, long long b, long long c) { return min(min(a, b), c); } long long min4(long long a, long long b, long long c, long long d) { return min(min(a, b), min(c, d)); } long long po(long long x, long long n, long long mod = 1000000007) { if (n == 0) { return 1; } long long m = po(x, n / 2, mod); m *= m; m %= mod; if (n % 2) { m *= x; m %= mod; } return m; } long long n, k; vector<string> v(2005); vector<string> num{ 1110111 , 0010010 , 1011101 , 1011011 , 0111010 , 1101011 , 1101111 , 1010010 , 1111111 , 1111011 }; long long check(string a, string b) { long long count = 0; for (long long i = 0; i < 7; i++) { if (a[i] == 1 && b[i] == 0 ) { return -1; } else if (a[i] == 0 && b[i] == 1 ) { count++; } } return count; } bool comp(char a, char b) { if (b == - ) { return 1; } else if (a == - ) { return 0; } return a >= b; } vector<long long> ans; long long dp[2005][2005]; bool stored[2005][2005]; long long solve(long long rem, long long index) { if (rem < 0) { return -1; } if (stored[rem][index]) { return dp[rem][index]; } if (index == n - 1) { for (long long j = 9; j >= 0; j--) { if (check(v[index], num[j]) == rem) { stored[rem][index] = 1; ans.push_back(j); return dp[rem][index] = 1; } } stored[rem][index] = 1; return dp[rem][index] = -1; } stored[rem][index] = 1; for (long long j = 9; j >= 0; j--) { if (check(v[index], num[j]) == -1) { continue; } if (solve(rem - check(v[index], num[j]), index + 1) != -1) { ans.push_back(j); return dp[rem][index] = 1; } } return dp[rem][index] = -1; } int32_t main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(false); cin.tie(NULL); clock_t startTime = clock(); cout << fixed << setprecision(12); cin >> n >> k; for (long long i = 0; i < n; i++) cin >> v[i]; if (solve(k, 0) == -1) { cout << -1; } else { reverse((ans).begin(), (ans).end()); for (long long i = 0; i < n; i++) { cout << ans[i]; } } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 100; int arr[MAXN]; int n, x, t; long long ans; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x; if (t <= 1) arr[++t] = x; else { while (t > 1 && arr[t] <= arr[t - 1] && arr[t] <= x) { ans += min(arr[t - 1], x); t--; } arr[++t] = x; } } sort(arr + 1, arr + t + 1, greater<int>()); for (int i = 3; i <= t; i++) ans += arr[i]; return cout << ans << endl, 0; }
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_merge_enc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module ecc_merge_enc
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
mc_wrdata, mc_wrdata_mask,
// Inputs
clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc
);
input clk;
input rst;
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r;
reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r;
always @(posedge clk) wr_data_r <= #TCQ wr_data;
always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask;
always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data;
// Merge new data with memory read data.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data;
genvar h;
genvar i;
generate
for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer
for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner
assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] =
wr_data_mask[h*DATA_WIDTH/8+i]
? rd_merge_data[h*DATA_WIDTH+i*8+:8]
: wr_data[h*PAYLOAD_WIDTH+i*8+:8];
end
if (PAYLOAD_WIDTH > DATA_WIDTH)
assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]=
wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH];
end
endgenerate
// Generate ECC and overlay onto mc_wrdata.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK-1:0] raw_not_ecc;
reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r;
always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc;
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c;
genvar j;
integer k;
generate
for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word
always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin
mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] =
{{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}},
merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]};
for (k=0; k<ECC_WIDTH; k=k+1)
if (~raw_not_ecc_r[j])
mc_wrdata_c[j*DQ_WIDTH+CODE_WIDTH-k-1] =
^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] &
h_rows[k*CODE_WIDTH+:DATA_WIDTH]);
end
end
endgenerate
always @(posedge clk) mc_wrdata <= mc_wrdata_c;
// Set all DRAM masks to zero.
output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}};
endmodule
|
//#############################################################################
//# Purpose: MIO Transmit Datapath #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module mtx # ( parameter PW = 104, // fifo width
parameter AW = 32, // fifo width
parameter IOW = 8, // I./O data width
parameter FIFO_DEPTH = 16, // fifo depth
parameter TARGET = "GENERIC" // fifo target
)
(// reset, clk, cfg
input clk, // main core clock
input io_clk, // clock for tx logic
input nreset, // async active low reset
input tx_en, // transmit enable
input ddr_mode, // configure mio in ddr mode
input lsbfirst, // send bits lsb first
input emode, //emesh mode
input [1:0] iowidth,//input width
// status
output tx_empty, // tx fifo is empty
output tx_full, // tx fifo is full (should never happen!)
output tx_prog_full,// tx is getting full (stop sending!)
// data to transmit
input access_in, // fifo data valid
input [PW-1:0] packet_in, // fifo packet
output wait_out, // wait pushback for fifo
// IO interface (90 deg clock supplied outside this block)
output tx_access, // access signal for IO
output [IOW-1:0] tx_packet, // packet for IO
input tx_wait // pushback from IO
);
//###############
//# LOCAL WIRES
//###############
// End of automatics
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] io_packet; // From mtx_fifo of mtx_fifo.v
wire [7:0] io_valid; // From mtx_fifo of mtx_fifo.v
wire io_wait; // From mtx_io of mtx_io.v
// End of automatics
//########################################
//# Synchronization FIFO
//########################################
mtx_fifo #(.PW(PW),
.AW(AW),
.FIFO_DEPTH(FIFO_DEPTH),
.TARGET(TARGET))
mtx_fifo (/*AUTOINST*/
// Outputs
.wait_out (wait_out),
.io_packet (io_packet[63:0]),
.io_valid (io_valid[7:0]),
// Inputs
.clk (clk),
.io_clk (io_clk),
.nreset (nreset),
.tx_en (tx_en),
.emode (emode),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.io_wait (io_wait));
//########################################
//# IO Logic (DDR, shift register)
//########################################
mtx_io #(.IOW(IOW))
mtx_io (/*AUTOINST*/
// Outputs
.tx_packet (tx_packet[IOW-1:0]),
.tx_access (tx_access),
.io_wait (io_wait),
// Inputs
.nreset (nreset),
.io_clk (io_clk),
.ddr_mode (ddr_mode),
.iowidth (iowidth[1:0]),
.tx_wait (tx_wait),
.io_valid (io_valid[7:0]),
.io_packet (io_packet[IOW-1:0]));
endmodule // mtx
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 100; int a[maxn]; map<pair<int, int>, bool> mp; int main() { ios::sync_with_stdio(false); int N; cin >> N; int M; cin >> M; for (int i = 1; i <= N; i++) cin >> a[i]; for (int i = 1; i <= M; i++) { int x; int y; cin >> x >> y; mp[pair<int, int>(x, y)] = 1; } int pos = N; for (int i = N - 1; i >= 1; i--) { if (mp[pair<int, int>(a[i], a[pos])] == true) { int j; for (j = i; j < pos; j++) { if (mp[pair<int, int>(a[j], a[j + 1])]) swap(a[j], a[j + 1]); else break; } if (j == pos) pos -= 1; } } cout << N - pos; }
|
// ------------------------------------------------------------------------ //
// Texas A&M University //
// CPSC350 Computer Architecture //
// //
// $Id: ALU_behav.v,v 1.3 2002/11/14 16:06:04 miket Exp miket $ //
// //
// ------------------------------------------------------------------------ //
// ------------------------------------------------------------------------ //
// Behavioral Verilog Module for a MIPS-like ALU //
// -- In continuous and procedure assignments Verilog extends the smaller //
// operands by replicating their MSB, if it is equal to x, z; otherwise //
// operends them with 0's. Arithmetic is interpreted as 2's C //
// -- regs are considered as unsigned bit-vectors but the all arithmetic //
// is done in 2's complement. //
// At ALU instatiation time parameter n determines the ALU bit-size //
// ------------------------------------------------------------------------ //
// repetoire of operations for ALU, selected by ALU_ctr (change at will)
`define ADD 4'b0111 // 2's compl add
`define ADDU 4'b0001 // unsigned add
`define SUB 4'b0010 // 2's compl subtract
`define SUBU 4'b0011 // unsigned subtract
`define AND 4'b0100 // bitwise AND
`define OR 4'b0101 // bitwise OR
`define XOR 4'b0110 // bitwise XOR
`define SLT 4'b1010 // set result=1 if less than 2's compl
`define SLTU 4'b1011 // set result=1 if less than unsigned
`define NOP 4'b0000 // do nothing
module ALU_behav( ADin, BDin, ALU_ctr, Result, Overflow, Carry_in, Carry_out, Zero );
parameter n = 32, Ctr_size = 4;
input Carry_in;
input [Ctr_size-1:0] ALU_ctr;
input [n-1:0] ADin, BDin;
output [n-1:0] Result;
reg [n-1:0] Result, tmp;
output Carry_out, Overflow, Zero;
reg Carry_out, Overflow, Zero;
always @(ALU_ctr or ADin or BDin or Carry_in)
begin
case(ALU_ctr)
`ADD: begin
{Carry_out, Result} = ADin + BDin + Carry_in;
Overflow = ADin[n-1] & BDin[n-1] & ~Result[n-1]
| ~ADin[n-1] & ~BDin[n-1] & Result[n-1];
end
`ADDU: {Overflow, Result} = ADin + BDin + Carry_in;
`SUB: begin
{Carry_out, Result} = ADin - BDin;
Overflow = ADin[n-1] & ~BDin[n-1] & Result[n-1]
| ~ADin[n-1] & BDin[n-1] & ~Result[n-1];
end
`SUBU: {Overflow, Result} = ADin - BDin;
`SLT: begin
{Carry_out, tmp} = ADin - BDin;
Overflow = ADin[n-1] & ~BDin[n-1] & ~tmp[n-1]
| ~ADin[n-1] & BDin[n-1] & tmp[n-1];
$display("SLT:- [%d] tmp = %d [%b]; Cout=%b, Ovf=%b; A=%d, B=%d",
$time, tmp, tmp, Carry_out, Overflow, ADin, BDin );
Result = tmp[n-1] ^ Overflow;
$display("SLT:+R=%d [%b]", Result, Result );
end
`SLTU: begin
{Carry_out, tmp} = ADin - BDin;
$display("SLTU:- [%d] tmp = %d [%b]; Cout=%b, Ovf=%b; A=%d, B=%d",
$time, tmp, tmp, Carry_out, Overflow, ADin, BDin );
Result = Carry_out;
$display("SLTU:+R=%d [%b]", Result, Result );
end
`OR : Result = ADin | BDin;
`AND: Result = ADin & BDin;
`XOR: Result = ADin ^ BDin;
`NOP: Result = ADin;
endcase
Zero = ~| Result; // Result = 32'b0
end
/* always @ (Result)
begin
$display("%0d\t ADin = %0d BDin = %0d; Result = %0d; Cout = %b Ovfl = %b Zero = %b OP = %b", $time, ADin, BDin, Result, Carry_out, Overflow, Zero, ALU_ctr );
end
*/
endmodule
// this is a test bench to test the ALU in isolation (without fetching instructions from instruction memory)
// uncomment it only when you are testing
// module TestALU;
// parameter n = 32, Ctr_size = 4;
// reg [n-1:0] A, B, T;
// wire [n-1:0] R, tt;
// reg Carry_in;
// wire Carry_out, Overflow, Zero;
// reg [Ctr_size-1:0] ALU_ctr;
// integer num;
// ALU_behav ALU( A, B, ALU_ctr, R, Overflow, Carry_in, Carry_out, Zero );
// always @( R or Carry_out or Overflow or Zero )
// begin
// $display("%0d\tA = %0d B = %0d; R = %0d; Cout = %b Ovfl = %b Zero = %b OP = %b n = %d", $time, A, B, R, Carry_out, Overflow, Zero, ALU_ctr, num );
// num = num + 1;
// end
// initial begin
// #0 num = 0; Carry_in = 0;
// #1 A = 101; B = 0; ALU_ctr = `NOP;
// #10 A = 10; B = 10; ALU_ctr = `ADD;
// #10 A = 10; B = 20; ALU_ctr = `ADDU;
// #10 A = 10; B = 20; ALU_ctr = `SLT;
// #10 A = 10; B = 20; ALU_ctr = `SLTU;
// #10 A = 32'hffffffff; B = 1; ALU_ctr = `ADDU;
// #10 A = 10; B = 10; ALU_ctr = `ADDU;
// #10 A = 10; B = 10; ALU_ctr = `SUB;
// #10 A = 1; B = 1; ALU_ctr = `SUBU;
// #10 A = 10; B = 10; ALU_ctr = `SUB;
// #10 A = 10; B = 10; ALU_ctr = `SUBU;
// #10 A = -13; B = -12; ALU_ctr = `SLT;
// #100 $finish;
// end
// endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; int cnt, lst, fa[N * 2], len[N * 2], ch[N * 2][26]; long long w[N * 2], ans; int od[N * 2], rk[N * 2], l = 1; char s[N]; void Init() { cnt = lst = 1; } void Insert(int c) { int p = lst, np = lst = ++cnt; len[np] = len[p] + 1; while (p && ch[p][c] == 0) ch[p][c] = np, p = fa[p]; if (!p) fa[np] = 1; else { int q = ch[p][c], nq; if (len[q] == len[p] + 1) fa[np] = q; else { len[nq = ++cnt] = len[p] + 1; fa[nq] = fa[q]; fa[q] = fa[np] = nq; memcpy(ch[nq], ch[q], sizeof(ch[q])); while (ch[p][c] == q) ch[p][c] = nq, p = fa[p]; } } } int n; int main() { Init(); scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , s + l); l += strlen(s + l); s[l++] = # ; } for (int i = 1, j = 0, x, p; i <= n; i++) { lst = 1; for (j += 1; s[j] != # ; j++) { Insert(s[j] - a ); } } for (int i = 1, j = 0, x, p; i <= n; i++) { scanf( %d , &x); for (p = 1, j += 1; s[j] != # ; j++) { p = ch[p][s[j] - a ]; w[p] += x; } } for (int i = 1; i <= cnt; i++) rk[len[i]] += 1; for (int i = 1; i <= cnt; i++) rk[i] += rk[i - 1]; for (int i = 1; i <= cnt; i++) od[rk[len[i]]--] = i; for (int i = cnt; i >= 1; i--) w[fa[od[i]]] += w[od[i]]; for (int i = 2; i <= cnt; i++) ans = max(ans, len[i] * w[i]); printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> char s[1111111]; int f[1111111]; int c[1111111]; int d[1111111]; int main() { int i, j, n, m, l; scanf( %d%d%s , &n, &m, s); if (m == 0) { j = 1; for (i = 0; i < n; i++) j = 26LL * j % 1000000007; printf( %d , j); return 0; } f[0] = -1; for (i = 1; s[i]; i++) { for (j = f[i - 1];; j = f[j]) { if (s[j + 1] == s[i]) break; if (j == -1) break; } if (s[j + 1] == s[i]) f[i] = j + 1; else f[i] = -1; } l = i; for (j = f[l - 1]; j >= 0; j = f[j]) c[l - j - 1] = 1; scanf( %d , &i); d[i - 1] = l; while (--m) { scanf( %d , &j); if (j - i < l && !c[j - i]) { puts( 0 ); return 0; } d[j - 1] = l; i = j; } j = 1; for (i = 0; i < n; i++) { if (i) d[i] = std::max(d[i - 1] - 1, d[i]); if (d[i] == 0) j = 26LL * j % 1000000007; } printf( %d , j); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__XOR2_BEHAVIORAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = 4e+18; const int N = 100010; struct rec { long long a, b, c; }; int cas, n; long long x[N], y[N], z[N]; rec get(long long la, long long ra, long long lb, long long rb, long long lc, long long rc, long long labc, long long rabc, int k) { la -= k, ra -= k, lb -= k, rb -= k, lc -= k, rc -= k; labc -= 3 * k, rabc -= 3 * k; if (la % 2 != 0) la++; if (ra % 2 != 0) ra--; if (lb % 2 != 0) lb++; if (rb % 2 != 0) rb--; if (lc % 2 != 0) lc++; if (rc % 2 != 0) rc--; if (labc % 2 != 0) labc++; if (rabc % 2 != 0) rabc--; if (la > ra || lb > rb || lc > rc || labc > rabc) return (rec){inf, inf, inf}; if (rabc < la + lb + lc) return (rec){inf, inf, inf}; if (labc > ra + rb + rc) return (rec){inf, inf, inf}; if (labc <= la + lb + lc && la + lb + lc <= rabc) return (rec){la + k, lb + k, lc + k}; if (labc <= ra + rb + rc && ra + rb + rc <= rabc) return (rec){ra + k, rb + k, rc + k}; if (labc <= la + lb + rc) return (rec){la + k, lb + k, labc - la - lb + k}; if (labc <= la + rb + rc) return (rec){la + k, labc - la - rc + k, rc + k}; return (rec){labc - rb - rc + k, rb + k, rc + k}; } rec check(long long mid) { long long la, lb, lc, labc, ra, rb, rc, rabc; la = lb = lc = labc = -inf; ra = rb = rc = rabc = inf; for (int i = 1; i <= n; i++) { la = max(la, -x[i] + y[i] + z[i] - mid); ra = min(ra, -x[i] + y[i] + z[i] + mid); lb = max(lb, x[i] - y[i] + z[i] - mid); rb = min(rb, x[i] - y[i] + z[i] + mid); lc = max(lc, x[i] + y[i] - z[i] - mid); rc = min(rc, x[i] + y[i] - z[i] + mid); labc = max(labc, x[i] + y[i] + z[i] - mid); rabc = min(rabc, x[i] + y[i] + z[i] + mid); } if (la > ra || lb > rb || lc > rc || labc > rabc) return (rec){inf, inf, inf}; rec tmp = get(la, ra, lb, rb, lc, rc, labc, rabc, 0); if (tmp.a != inf) return tmp; tmp = get(la, ra, lb, rb, lc, rc, labc, rabc, 1); if (tmp.a != inf) return tmp; return (rec){inf, inf, inf}; } int main() { scanf( %d , &cas); while (cas--) { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld%lld%lld , &x[i], &y[i], &z[i]); long long l = 0, r = inf; while (l < r) { long long mid = (l + r) >> 1; if (check(mid).a != inf) r = mid; else l = mid + 1; } rec ans = check(l); printf( %lld %lld %lld n , (ans.b + ans.c) / 2, (ans.a + ans.c) / 2, (ans.a + ans.b) / 2); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int dx[] = {1, -1, 0, 0}; int dy[] = {0, 0, 1, -1}; int dx2[] = {1, -1, 0, 0, -1, 1, -1, 1}; int dy2[] = {0, 0, 1, -1, 1, -1, -1, 1}; int read() { int x; scanf( %d , &x); return x; } int a[505][505]; int main() { int x, y; x = read(); y = read(); int sx = read(); int sy = read(); string s; cin >> s; a[sx][sy] = 1; cout << 1 << ; for (int i = 0; i < s.size() - 1; i++) { if (s[i] == U ) { int nx = sx - 1 == 0 ? 1 : sx - 1; int ny = sy; if (a[nx][ny]) printf( 0 ); else printf( 1 ); sx = nx; sy = ny; a[nx][ny] = 1; } else if (s[i] == D ) { int nx = sx + 1 == x + 1 ? x : sx + 1; int ny = sy; if (a[nx][ny]) printf( 0 ); else printf( 1 ); sx = nx; sy = ny; a[nx][ny] = 1; } else if (s[i] == R ) { int nx = sx; int ny = sy + 1 == y + 1 ? y : sy + 1; if (a[nx][ny]) printf( 0 ); else printf( 1 ); sx = nx; sy = ny; a[nx][ny] = 1; } else if (s[i] == L ) { int nx = sx; int ny = sy - 1 == 0 ? 1 : sy - 1; if (a[nx][ny]) printf( 0 ); else printf( 1 ); sx = nx; sy = ny; a[nx][ny] = 1; } } int ans = 0; for (int i = 1; i <= x; i++) { for (int j = 1; j <= y; j++) { if (a[i][j] == 0) ans++; } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; long long dmod(long long x, long long MOD) { return x % MOD; } long long m; long long fe(long long x, long long p) { if (p == 0) return 1; long long ret = fe(x, p / 2); ret = dmod(ret * ret, m); if (p & 1) ret = dmod(ret * x, m); return ret; } int n; long long li[N + 5]; set<long long> ada; long long get_count(long long x) { long long ret = 0; for (int i = 1; i <= n; i++) { long long cur = (li[i] + x) % m; if (ada.find(cur) != ada.end()) ret++; } return ret; } bool proc() { if (2 * n < m) return 0; set<long long> tmp; long long cur = 0; for (int i = 1; i <= n; i++) { while (cur != li[i]) tmp.insert(cur++); cur++; } while (cur != m) tmp.insert(cur++); int id = 0; for (auto x : tmp) { id++; li[id] = x; } n = id; return 1; } int main() { scanf( %d%d , &m, &n); for (int i = 1; i <= n; i++) scanf( %lld , &li[i]); if (n == 1) { printf( %lld 0 n , li[1]); return 0; } else if (m == 2 || n == m) { printf( 0 1 n ); return 0; } else if (n == m - 1) { sort(li + 1, li + n + 1); for (int i = 1; i <= n; i++) { if (li[i] != (i - 1)) { printf( %d 1 n , i); return 0; } } printf( 0 1 n ); return 0; } sort(li + 1, li + n + 1); bool tukar = proc(); for (int i = 1; i <= n; i++) ada.insert(li[i]); long long dif = li[2] - li[1]; long long cnt = get_count(dif); long long inv = fe(n - cnt, m - 2); dif = dmod(dif * inv, m); deque<long long> dq; dq.push_front(li[1]); while (1) { long long now = dq.front(); now = dmod(now - dif + m, m); if (ada.find(now) != ada.end()) dq.push_front(now); else break; } while (1) { long long now = dq.back(); now = dmod(now + dif, m); if (ada.find(now) != ada.end()) dq.push_back(now); else break; } if (dq.size() != n) { printf( -1 n ); return 0; } if (tukar) { printf( %lld %lld n , dmod(dq.back() + dif, m), dif); } else { printf( %lld %lld n , dq.front(), dif); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int n, m, sol = 1; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; if (n > m) swap(n, m); if (((n % 10) + 1 <= 2 && n % 10 >= 1 && m % 10 >= 5) || (abs(n - m) > 10)) return cout << 0, 0; else { for (long long int i = n + 1; i <= m; i++) sol = (sol * (i % 10)) % 10; } cout << sol; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; long long ab[11], y[11]; long long val(string abv) { long long res = 0; for (int i = 0; i < (int)abv.size(); i++) res = 10 * res + ((long long)(abv[i] - 0 )); return res; } int main() { cin.sync_with_stdio(false); long long p10 = 10; long long nb = 1989; for (int i = 0; i < (int)10; i++) { ab[i] = nb % p10; y[i] = nb; nb += p10; p10 *= ((long long)10); } cin >> n; while (n--) { char c; string abv; for (int i = 0; i < (int)4; i++) cin >> c; cin >> abv; long long k = val(abv); int l = abv.size() - 1; if (ab[l] <= k) printf( %I64d n , y[l] + k - ab[l]); else printf( %I64d n , y[l + 1] - (ab[l] - k)); } return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_b.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_b
//
// No user `defines in this module
module ent_b
//
// Generated Module inst_b
//
(
port_b_1, // Will create p_mix_sig_1_go port
port_b_3, // Interhierachy link, will create p_mix_sig_3_go
port_b_4, // Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1, // Bus, single bits go to outside, will create p_mix_sig_5_2_2_go
port_b_5_2, // Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO
port_b_6i, // Conflicting definition
port_b_6o, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08 // VHDL intermediate needed (port name)
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
|
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