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#include <bits/stdc++.h> using namespace std; int a[400005]; int q, x; int main() { int aux, cnt = 0, maxim = 0; cin >> q >> x; for (int i = 1; i <= q; i++) { cin >> aux; a[aux % x]++; while (a[cnt] > maxim) { cnt++; if (cnt == x) { cnt = 0; maxim++; } } cout << maxim * x + cnt << n ; } return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data);
always @(posedge clock)
case (addr)
3'd0 : data <= #1 -16'd49;
3'd1 : data <= #1 16'd165;
3'd2 : data <= #1 -16'd412;
3'd3 : data <= #1 16'd873;
3'd4 : data <= #1 -16'd1681;
3'd5 : data <= #1 16'd3135;
3'd6 : data <= #1 -16'd6282;
3'd7 : data <= #1 16'd20628;
endcase // case(addr)
endmodule // coeff_rom
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A221O_BEHAVIORAL_PP_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int q; unsigned long long a, b, c; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> q; while (q--) { cin >> a >> b >> c; unsigned long long sum = a + b + c; cout << sum / 2 << n ; sum = 0; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int k; cin >> k; if (k % 2 == 1) { cout << -1 << endl; return 0; } for (int i = 0; i < k; i++) { if (i > 0) cout << endl; for (int j = 0; j < k; j++) { for (int l = 0; l < k; l++) { int layer = min(j, min(l, min(k - j - 1, k - l - 1))); if (layer % 2 == i % 2) cout << w ; else cout << b ; } cout << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000 * 1000 * 1000; const int MOD = INF + 7; const int XD = 100100; int facts[XD << 1]; void calcFacts(int n) { facts[0] = 1; for (int i = 1; i <= n; ++i) { facts[i] = 1LL * facts[i - 1] * i % MOD; } } int exgcd(int a, int b, int &x, int &y) { if (a == 0) { x = 0; y = 1; return b; } int xx, yy; int d = exgcd(b % a, a, xx, yy); x = yy - b / a * xx; y = xx; return d; } int getInv(int n) { int x, y; exgcd(n, MOD, x, y); x = (x % MOD + MOD) % MOD; return x; } int cnk(int n, int k) { return 1LL * facts[n] * getInv(facts[n - k]) % MOD * getInv(facts[k]) % MOD; } int main() { int zeroes, ones, sm; cin >> zeroes >> ones >> sm; if (zeroes == 0) { if (sm == 1) { cout << ((ones == 1) ? 1 : 0); } else { cout << ((ones == 1) ? 0 : 1); } return 0; } if (ones == 0) { if (sm == 1) { cout << ((zeroes & 1) ? 0 : 1); } else { cout << ((zeroes & 1) ? 1 : 0); } return 0; } calcFacts(zeroes + ones); int res = 0; for (int pos = 0; pos <= zeroes; ++pos) { if (sm == 0 && (pos % 2 == 0 && (pos < zeroes || pos == zeroes && ones > 1) || pos % 2 == 1 && (pos == zeroes && ones == 1))) { res += cnk(zeroes + ones - pos - 1, ones - 1); res %= MOD; } if (sm == 1 && (pos % 2 == 1 && (pos < zeroes || pos == zeroes && ones > 1) || pos % 2 == 0 && (pos == zeroes && ones == 1))) { res += cnk(zeroes + ones - pos - 1, ones - 1); res %= MOD; } } cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; int read() { int x = 0; bool flg = false; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) flg = true; for (; isdigit(ch); ch = getchar()) x = (x << 3) + (x << 1) + (ch ^ 48); return flg ? -x : x; } int n, m; char a[64][64]; void solve() { n = read(), m = read(); for (int i(1), _i(n); i <= _i; i++) scanf( %s , a[i] + 1); int tot = 0; for (int i(1), _i(n); i <= _i; i++) for (int j(1), _j(m); j <= _j; j++) tot += a[i][j] == A ; if (!tot) return puts( MORTAL ), void(); if (tot == n * m) return puts( 0 ), void(); { bool g = 1; for (int i(1), _i(n); i <= _i; i++) g = g && a[i][1] == A ; if (g) return puts( 1 ), void(); g = 1; for (int i(1), _i(n); i <= _i; i++) g = g && a[i][m] == A ; if (g) return puts( 1 ), void(); g = 1; for (int i(1), _i(m); i <= _i; i++) g = g && a[1][i] == A ; if (g) return puts( 1 ), void(); g = 1; for (int i(1), _i(m); i <= _i; i++) g = g && a[n][i] == A ; if (g) return puts( 1 ), void(); } { for (int x : {1, n}) for (int y : {1, m}) if (a[x][y] == A ) return puts( 2 ), void(); for (int i(1), _i(n); i <= _i; i++) { bool g = 1; for (int j(1), _j(m); j <= _j; j++) g = g && a[i][j] == A ; if (g) return puts( 2 ), void(); } for (int j(1), _j(m); j <= _j; j++) { bool g = 1; for (int i(1), _i(n); i <= _i; i++) g = g && a[i][j] == A ; if (g) return puts( 2 ), void(); } } { for (int i(1), _i(n); i <= _i; i++) for (int j(1), _j(m); j <= _j; j++) { if (a[i][j] == A && (i == 1 || i == n || j == 1 || j == m)) return puts( 3 ), void(); } } puts( 4 ); } int main() { for (int T = read(); T--;) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; double s; vector<int> E[100005]; int dist[100005], pa[100005]; int dfs(int u, int p, int d) { dist[u] = d; int ans = u; for (int v : E[u]) { if (v == p) continue; int tmp = dfs(v, u, d + 1); pa[v] = u; if (dist[ans] < dist[tmp]) ans = tmp; } return ans; } int main() { scanf( %d%lf , &n, &s); for (int i = 0; i < n - 1; i++) { int u, v; scanf( %d%d , &u, &v); E[u].push_back(v); E[v].push_back(u); } if (n == 2) { printf( %.10lf n , s); return 0; } int l = 0; for (int i = 1; i <= n; i++) { if (E[i].size() == 1) l++; } printf( %.10lf n , 2.0 * s / l); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__EINVP_PP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRBP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFRBP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRBP_BLACKBOX_V
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
// IP Revision: 8
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dist_mem_gen_0 (
a,
spo
);
input wire [14 : 0] a;
output wire [7 : 0] spo;
dist_mem_gen_v8_0 #(
.C_FAMILY("zynq"),
.C_ADDR_WIDTH(15),
.C_DEFAULT_DATA("0"),
.C_DEPTH(32768),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("dist_mem_gen_0.mif"),
.C_ELABORATION_DIR("./"),
.C_MEM_TYPE(0),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(8),
.C_PARSER_TYPE(1)
) inst (
.a(a),
.d(8'B0),
.dpra(15'B0),
.clk(1'D0),
.we(1'D0),
.i_ce(1'D1),
.qspo_ce(1'D1),
.qdpo_ce(1'D1),
.qdpo_clk(1'D0),
.qspo_rst(1'D0),
.qdpo_rst(1'D0),
.qspo_srst(1'D0),
.qdpo_srst(1'D0),
.spo(spo),
.dpo(),
.qspo(),
.qdpo()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_1_V
`define SKY130_FD_SC_LP__INV_1_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_1_V
|
// MBT 7/25/2014
// async credit counter
//
// In this design, there are two clock domains. The first
// clock domain (w_) receives incoming credits. The second
// clock domain (r_) spends the credits. The first clock domain
// never needs to know how many credits are spent; it just
// accumulates how many have been received. This accumulated
// value is passed as a gray-coded pointer across to the _r clock domain.
// The _r clock domain records how many credits have been spent. It starts
// with a negative value. There will be lag from the w_ domain to
// the r_ domain because of the synchronizers. So imagine, after reset,
// we start sending packets, decrementing the credit counter, but no
// credits are received. The _r pointer will advance until it reaches the w_
// pointer, and then avail will go low, and transmits will stop. Then the
// credits start arriving and the w_ is advanced. After a few cycles delay,
// the _r side will observe this change and start spending credits again.
//
// label all signals in this module accordingly:
//
// w_: signals in "receive credits" clock domain
// r_: signals in "spend credits" clock domain
//
// TOKENS vs. CREDITS. We support a feature here, which is the idea of a token.
// A token is worth multiple credits. We pass tokens through the fifo (so that
// the gray-coded values are still consecutive). The number of credits must
// be a power-of-two multiple of the number of tokens. The log of this value is set
// by lg_credit_to_token_decimation_p. Using tokens can be used to reduce
// the toggle rate of the w_clk_i signal, for example, if it is being run
// over a pin exterior to the chip.
//
// RESET: both resets must be asserted and w_ clock most be posedge (negedge) toggled
// at least once; and the r_ clock posedge toggled at least four times after that.
// This will be a sufficient number of clocks to pass through the synchronizers.
// This will need to be done explicitly for the credit clock.
//
// ASYNC RESET PROCEDURE:
// Step 1: Assert r_ reset.
// Step 2: w_ reset must be posedge/negedge toggled (0->1->0) at least once.
// w_ clock cannot toggle during this step.
// Step 3: r_ clock posedge toggled at least four times after that.
// Step 4: Deassert r_ reset.
//
// MARGIN: when credit counters are used to count outgoing packets, it is sometimes
// helpful to include extra bits of precision in case the latency is longer than
// expected and the downstream module needs more buffer space than originally planned.
// The downstream module can give back tokens right after reset before anything is sent,
// increasing the amount of margin the upstream module thinks it have. Of course, you
// need to have the flexibility of being able to change the downstream's buffer space
// to take advantage of this feature, but this is the case if the downstream module
// is an FPGA. The parameter extra_margin_p is the number of additional bits in the
// credit counter that should be added to accomodate this behaviour. So for example,
// extra_margin_p of 2 increases the credit capacity by 2X.
// The parameter count_negedge_p determines whether we count
// on negedge edge or positive edge of the clock.
`include "bsg_defines.v"
module bsg_async_credit_counter #(parameter `BSG_INV_PARAM(max_tokens_p )
, parameter `BSG_INV_PARAM(lg_credit_to_token_decimation_p )
, parameter count_negedge_p = 0
, parameter extra_margin_p = 0
, parameter check_excess_credits_p = 1
, parameter start_full_p = 1
, parameter use_async_w_reset_p = 0)
(
input w_clk_i
, input w_inc_token_i
, input w_reset_i
, input r_clk_i
, input r_reset_i
, input r_dec_credit_i
, input r_infinite_credits_i // basically suppress this module
, output r_credits_avail_o
);
// $clog2(x) is how many bits are required to represent
// x unique values. we need to represent 0..max_credits_p = max_credits_p+1 values.
localparam r_counter_width_lp = extra_margin_p+$clog2(max_tokens_p+1) + lg_credit_to_token_decimation_p;
localparam w_counter_width_lp = extra_margin_p+$clog2(max_tokens_p+1);
logic [r_counter_width_lp-1:0] r_counter_r;
logic [w_counter_width_lp-1:0] w_counter_gray_r, w_counter_gray_r_rsync, w_counter_binary_r_rsync;
always @(posedge r_clk_i)
if (r_reset_i)
// fixme? not sure this constant will always do as expected
r_counter_r <= { -max_tokens_p * start_full_p, { lg_credit_to_token_decimation_p {1'b0} } };
else
r_counter_r <= r_counter_r + r_dec_credit_i;
// *********** this is basically an async_ptr: begin factor
bsg_async_ptr_gray #(.lg_size_p(w_counter_width_lp)
,.use_negedge_for_launch_p(count_negedge_p)
,.use_async_reset_p(use_async_w_reset_p)) bapg
(.w_clk_i(w_clk_i)
,.w_reset_i(w_reset_i)
,.w_inc_i(w_inc_token_i)
,.r_clk_i(r_clk_i)
,.w_ptr_binary_r_o() // we don't care about the binary version of the ptr on w side
,.w_ptr_gray_r_o(w_counter_gray_r) // synchronized with w clock domain
,.w_ptr_gray_r_rsync_o(w_counter_gray_r_rsync) // synchronized with r clock domain
);
/*
previously, we converted w_counter to binary, appended lg_credit_to_token_decimation 1'b0's and compared them
but instead, we convert the other way now.
assign r_credits_avail_o = r_infinite_credits_i | ~(w_counter_binary_r_rsync_padded == r_counter_r);
*/
wire [w_counter_width_lp-1:0] r_counter_r_hi_bits = r_counter_r[lg_credit_to_token_decimation_p+:w_counter_width_lp];
wire r_counter_r_lo_bits_nonzero;
if (lg_credit_to_token_decimation_p == 0)
assign r_counter_r_lo_bits_nonzero = 1'b0;
else
assign r_counter_r_lo_bits_nonzero = | r_counter_r[0+:lg_credit_to_token_decimation_p];
wire [w_counter_width_lp-1:0] r_counter_r_hi_bits_gray = (r_counter_r_hi_bits >> 1) ^ r_counter_r_hi_bits;
assign r_credits_avail_o = r_infinite_credits_i | r_counter_r_lo_bits_nonzero | (r_counter_r_hi_bits_gray != w_counter_gray_r_rsync);
// ***************************************
// for debug
//
//
// synopsys translate_off
bsg_gray_to_binary #(.width_p(w_counter_width_lp)) bsg_g2b
(.gray_i(w_counter_gray_r_rsync)
,.binary_o(w_counter_binary_r_rsync)
);
wire [r_counter_width_lp-1:0] w_counter_binary_r_rsync_padded = { w_counter_binary_r_rsync, { lg_credit_to_token_decimation_p {1'b0 } }};
wire [r_counter_width_lp-1:0] r_free_credits = w_counter_binary_r_rsync_padded - r_counter_r;
logic [r_counter_width_lp-1:0] r_free_credits_r;
always @(posedge r_clk_i)
r_free_credits_r <= r_free_credits;
if (check_excess_credits_p)
always @(r_free_credits_r)
assert(r_reset_i
| r_infinite_credits_i
| (r_free_credits_r <= (max_tokens_p << lg_credit_to_token_decimation_p)))
else $error("too many credits in credit counter %d (> %3d)"
, r_free_credits_r
, max_tokens_p << lg_credit_to_token_decimation_p
);
always @(negedge r_clk_i)
assert (!(r_dec_credit_i===1 && r_credits_avail_o===0))
else $error("decrementing empty credit counter");
// synopsys translate_on
//
// end debug
//
// ****************************************
endmodule
`BSG_ABSTRACT_MODULE(bsg_async_credit_counter)
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:03:56 02/27/2016
// Design Name: Register
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab5/test_for_reg_with_reset.v
// Project Name: lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_reg_with_reset;
// Inputs
reg clock_in;
reg regWrite;
reg [4:0] readReg1;
reg [4:0] readReg2;
reg [4:0] writeReg;
reg [31:0] writeData;
// Outputs
wire [31:0] readData1;
wire [31:0] readData2;
// Instantiate the Unit Under Test (UUT)
Register uut (
.clock_in(clock_in),
.regWrite(regWrite),
.readReg1(readReg1),
.readReg2(readReg2),
.writeReg(writeReg),
.writeData(writeData),
.readData1(readData1),
.readData2(readData2)
);
initial begin
// Initialize Inputs
clock_in = 0;
regWrite = 0;
readReg1 = 0;
readReg2 = 0;
writeReg = 0;
writeData = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:06:52 06/28/2009
// Design Name:
// Module Name: dcm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_dcm (
input CLKIN,
output CLKFX,
output LOCKED,
input RST,
output[7:0] STATUS
);
// DCM: Digital Clock Manager Circuit
// Spartan-3
// Xilinx HDL Language Template, version 11.1
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
//.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 // 24 MHz
//.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
//.CLKFX_DIVIDE(5), // Can be any integer from 1 to 32 // 21.6 MHz
//.CLKFX_MULTIPLY(18), // Can be any integer from 2 to 32
.CLKFX_DIVIDE(7), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(25), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(41.667), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hFFFF), // FACTORY JF values
// .LOC("DCM_X0Y0"),
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(RST) // DCM asynchronous reset input
);
endmodule
|
// $Id: c_align.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// align a vector inside another one
//==============================================================================
module c_align
(data_in, dest_in, data_out);
// width of input data
parameter in_width = 32;
// width of destination vector
parameter out_width = 32;
// offset at which to place input data within destination vector
// (portions of the input data that end up to the left or right of the
// destination vector will be trimmed)
parameter offset = 0;
// input vector
input [0:in_width-1] data_in;
// destination vector
input [0:out_width-1] dest_in;
// result
output [0:out_width-1] data_out;
wire [0:out_width-1] data_out;
genvar i;
generate
for(i = 0; i < out_width; i = i + 1)
begin:bits
if((i < offset) || (i >= (offset + in_width)))
assign data_out[i] = dest_in[i];
else
assign data_out[i] = data_in[i - offset];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, k, p, x; cin >> n >> k >> p; std::vector<int> even, odd; for (int i = 0; i < n; ++i) { cin >> x; if (x % 2) odd.emplace_back(x); else even.emplace_back(x); } if (odd.size() < k - p || (odd.size() - k - p) % 2 != 0) { cout << NO ; return 0; } if ((even.size() + (odd.size() - (k - p)) / 2) < p) { cout << NO << n ; return 0; } cout << YES << n ; long long cnt = 0; if (k - p) { while (even.size() > 0 && cnt != p) { cout << 1 << << even.back() << n ; even.pop_back(); cnt++; } while (odd.size() > 0 && cnt != p) { cout << 2 << << odd.back() << ; odd.pop_back(); cout << odd.back() << n ; odd.pop_back(); cnt++; } for (int i = 0; i < k - p - 1; i++) { vector<int> ans; while (even.size() > 0) { ans.emplace_back(even.back()); even.pop_back(); } ans.emplace_back(odd.back()); odd.pop_back(); cout << ans.size() << ; for (auto i : ans) { cout << i << ; } cout << n ; } vector<int> ans; while (odd.size() > 0) { ans.emplace_back(odd.back()); odd.pop_back(); } while (even.size() > 0) { ans.emplace_back(even.back()); even.pop_back(); } cout << ans.size() << ; for (auto i : ans) { cout << i << ; } cout << n ; } else { vector<int> ans; for (int i = 0; i < p - 1; i++) { if (even.size() > 0) { cout << 1 << << even.back() << n ; even.pop_back(); } else { cout << 2 << << odd.back() << ; odd.pop_back(); cout << odd.back() << ; odd.pop_back(); } } while (even.size() > 0) { ans.emplace_back(even.back()); even.pop_back(); } while (odd.size()) { ans.emplace_back(odd.back()); odd.pop_back(); } cout << ans.size() << ; for (auto I : ans) { cout << I << ; } } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000004; int a[N], arr[N], nxt[N], big[N], len[N]; int main() { int n; scanf( %d , &n); int i, idx; int mx1 = 0, mx2 = -1; for (i = 0; i < n; i++) { scanf( %d , &a[i]); if (a[i] > mx1) { mx2 = mx1; mx1 = a[i]; idx = i; } else if (a[i] > mx2) mx2 = a[i]; } int id = idx; for (i = 1; i <= n; i++) { arr[i] = a[id]; id = (id + 1) % n; } arr[n + 1] = 1000000007; stack<int> st; st.push(n + 1); for (i = n; i >= 1; i--) { while (!st.empty() && arr[st.top()] < arr[i]) st.pop(); nxt[i] = st.top(); st.push(i); } while (!st.empty()) st.pop(); st.push(n + 1); for (i = n; i >= 1; i--) { while (!st.empty() && arr[st.top()] <= arr[i]) st.pop(); big[i] = st.top(); st.push(i); } len[n + 1] = 1; for (i = n; i >= 1; i--) len[i] = len[nxt[i]] + 1; long long ans = 0; for (i = 1; i <= n; i++) ans = ans + (len[i + 1] - len[big[i]] + 1); for (i = 1; i <= n; i++) { if (arr[i] == mx1 || arr[i] == mx2) ans--; } printf( %I64d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_4_V
`define SKY130_FD_SC_LS__AND2B_4_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and2b_4 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and2b_4 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, a, b, in[100], on[100], i = 0, r, y; cin >> n >> x; int t = n; while (t--) { cin >> a >> b; r = min(a, b); y = max(a, b); in[i] = r; on[i] = y; i++; } sort(in, in + n); sort(on, on + n); if (in[n - 1] < on[0]) { if (x <= in[n - 1]) cout << in[n - 1] - x; else if (x >= on[0]) cout << x - on[0]; else if (x > in[n - 1] && x < on[0]) cout << 0; } else if (in[n - 1] == on[0]) cout << abs(x - on[0]); else cout << -1; }
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: alu_sub.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alu_sub (
dataa,
datab,
result);
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
lpm_add_sub LPM_ADD_SUB_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.add_sub (),
.cin (),
.clken (),
.clock (),
.cout (),
.overflow ()
// synopsys translate_on
);
defparam
LPM_ADD_SUB_component.lpm_direction = "SUB",
LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
LPM_ADD_SUB_component.lpm_representation = "UNSIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
LPM_ADD_SUB_component.lpm_width = 8;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "8"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_sub.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_sub.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_sub.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_sub.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_sub_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_sub_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> const int MAXINT = 2147483640; const long long MAXLL = 9223372036854775800LL; const long long MAXN = 1000000; using namespace std; int l[MAXN], r[MAXN]; int n; int ans[MAXN]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int T; cin >> T; while (T--) { cin >> n; for (int i = 1; i <= n; ++i) ans[i] = 0; for (int i = 1; i <= n; ++i) cin >> l[i] >> r[i]; int t = l[1]; ans[1] = t; for (int i = 2; i <= n; ++i) { if (r[i] <= t) ans[i] = 0; else { ans[i] = max(l[i], t + 1); t = ans[i]; } } for (int i = 1; i <= n; ++i) cout << ans[i] << ; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; int k; bool debug = false; char mp[170][170]; int l[170], r[170]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { scanf( %s , mp[i]); l[i] = m; r[i] = -1; for (int j = 0; j < m; j++) if (mp[i][j] == W ) { l[i] = j; break; } for (int j = m - 1; j >= 0; j--) if (mp[i][j] == W ) { r[i] = j; break; } } int ans = 0, pos = 0, dir = 1; for (int i = 0, j = 1; i < n; i = j) { j = i + 1; while (j < n && r[j] == -1) j++; if (r[i] != -1) { if (dir == 1) { ans += r[i] - pos; pos = r[i]; } else { ans += pos - l[i]; pos = l[i]; } } if (j == n) break; else { dir = (j - i) % 2 == 1 ? 1 - dir : dir; int npos; if (dir == 1) { npos = min(l[j], pos); } else { npos = max(r[j], pos); } ans += abs(npos - pos); pos = npos; ans += (j - i); } } cout << ans << endl; return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_channel_gate.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Provides cross domain synchronization for the CHNL_RX*
// signals between the CHNL_CLK and CLK domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module rx_port_channel_gate #(
parameter C_DATA_WIDTH = 9'd64
)
(
input RST,
input CLK,
input RX, // Channel read signal (CLK)
output RX_RECVD, // Channel read received signal (CLK)
output RX_ACK_RECVD, // Channel read acknowledgment received signal (CLK)
input RX_LAST, // Channel last read (CLK)
input [31:0] RX_LEN, // Channel read length (CLK)
input [30:0] RX_OFF, // Channel read offset (CLK)
output [31:0] RX_CONSUMED, // Channel words consumed (CLK)
input [C_DATA_WIDTH-1:0] RD_DATA, // FIFO read data (CHNL_CLK)
input RD_EMPTY, // FIFO is empty (CHNL_CLK)
output RD_EN, // FIFO read enable (CHNL_CLK)
input CHNL_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal (CHNL_CLK)
input CHNL_RX_ACK, // Channle read received signal (CHNL_CLK)
output CHNL_RX_LAST, // Channel last read (CHNL_CLK)
output [31:0] CHNL_RX_LEN, // Channel read length (CHNL_CLK)
output [30:0] CHNL_RX_OFF, // Channel read offset (CHNL_CLK)
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data (CHNL_CLK)
output CHNL_RX_DATA_VALID, // Channel read data valid (CHNL_CLK)
input CHNL_RX_DATA_REN // Channel read data has been recieved (CHNL_CLK)
);
reg rAckd=0, _rAckd=0;
reg rChnlRxAck=0, _rChnlRxAck=0;
reg [31:0] rConsumed=0, _rConsumed=0;
reg [31:0] rConsumedStable=0, _rConsumedStable=0;
reg [31:0] rConsumedSample=0, _rConsumedSample=0;
reg rCountRead=0, _rCountRead=0;
wire wCountRead;
wire wCountStable;
wire wDataRead = (CHNL_RX_DATA_REN & CHNL_RX_DATA_VALID);
assign RX_CONSUMED = rConsumedSample;
assign RD_EN = CHNL_RX_DATA_REN;
assign CHNL_RX_LAST = RX_LAST;
assign CHNL_RX_LEN = RX_LEN;
assign CHNL_RX_OFF = RX_OFF;
assign CHNL_RX_DATA = RD_DATA;
assign CHNL_RX_DATA_VALID = !RD_EMPTY;
// Buffer the input signals that come from outside the rx_port.
always @ (posedge CHNL_CLK) begin
rChnlRxAck <= #1 (RST ? 1'd0 : _rChnlRxAck);
end
always @ (*) begin
_rChnlRxAck = CHNL_RX_ACK;
end
// Signal receive into the channel domain.
cross_domain_signal rxSig (
.CLK_A(CLK),
.CLK_A_SEND(RX),
.CLK_A_RECV(RX_RECVD),
.CLK_B(CHNL_CLK),
.CLK_B_RECV(CHNL_RX),
.CLK_B_SEND(CHNL_RX)
);
// Signal acknowledgment of receive into the CLK domain.
syncff rxAckSig (.CLK(CLK), .IN_ASYNC(rAckd), .OUT_SYNC(RX_ACK_RECVD));
// Capture CHNL_RX_ACK and reset only after the CHNL_RX drops.
always @ (posedge CHNL_CLK) begin
rAckd <= #1 (RST ? 1'd0 : _rAckd);
end
always @ (*) begin
_rAckd = (CHNL_RX & (rAckd | rChnlRxAck));
end
// Count the words consumed by the channel and pass it into the CLK domain.
always @ (posedge CHNL_CLK) begin
rConsumed <= #1 _rConsumed;
rConsumedStable <= #1 _rConsumedStable;
rCountRead <= #1 (RST ? 1'd0 : _rCountRead);
end
always @ (*) begin
_rConsumed = (!CHNL_RX ? 0 : rConsumed + (wDataRead*(C_DATA_WIDTH/32)));
_rConsumedStable = (wCountRead | rCountRead ? rConsumedStable : rConsumed);
_rCountRead = !wCountRead;
end
always @ (posedge CLK) begin
rConsumedSample <= #1 _rConsumedSample;
end
always @ (*) begin
_rConsumedSample = (wCountStable ? rConsumedStable : rConsumedSample);
end
// Determine when it's safe to update the count in the CLK domain.
cross_domain_signal countSync (
.CLK_A(CHNL_CLK),
.CLK_A_SEND(rCountRead),
.CLK_A_RECV(wCountRead),
.CLK_B(CLK),
.CLK_B_RECV(wCountStable),
.CLK_B_SEND(wCountStable)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2000000; const int mod = 998244353; int used[N][2]; int f[N][2]; bool ok[N]; int solve(int n, int k) { if (used[n][k]) { return f[n][k]; } if (!ok[n]) { return 0; } int last = 0; int m = n; int j = 0; for (int i = 0; i < 40; i++) { if ((1 << i) > m) { last = m; break; } j = i; m -= (1 << i); } if (m == 0) { used[n][k] = 1; f[n][k] = 0; return 0; } int ans = 0; int nxt = (1 << j); int sz = (n - last) / 2; for (int i = max(0, last - sz - 1); i <= min(last, sz + 1); i++) { if ((sz + i) % 2 != k) { continue; } ans += 1ll * (solve(sz + i, 0) + solve(sz + i, 1)) % mod * solve(sz + last - i, 1) % mod; if (ans >= mod) { ans -= mod; } } used[n][k] = 1; f[n][k] = ans; return ans; } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; int x = 1; int v = 0; while (x <= n) { ok[x] = 1; ok[x + 1] = 1; x++; x = x * 2 - v; v = 1 - v; } used[0][0] = 1; f[0][0] = 1; used[0][1] = 1; f[0][1] = 1; used[1][0] = 1; f[1][0] = 1; used[1][1] = 1; f[1][1] = 0; cout << (solve(n, 0) + solve(n, 1)) % mod << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, d; cin >> n >> d; int m; cin >> m; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; if (x + y - d >= 0 && x - y - d <= 0 && x - y + d >= 0 && x + y - 2 * n + d <= 0) { cout << YES n ; } else { cout << NO n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int ans[300005]; int main() { int n, m; scanf( %d%d , &n, &m); set<int> alive; for (int i = 1; i <= n; i++) alive.insert(i); for (int i = 0; i < m; i++) { int l, r, x; scanf( %d%d%d , &l, &r, &x); set<int>::iterator it = alive.lower_bound(l); vector<int> dead; while (it != alive.end()) { int now = *it; if (now > r) break; if (now != x) dead.push_back(now), ans[now] = x; it++; } for (int j = 0; j < (int)((dead).size()); j++) alive.erase(dead[j]); } for (int i = 1; i <= n; i++) printf( %d%c , ans[i], i == n ? n : ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> const long long int inf = 9e18; const long double pi = 2 * acos(0.0); using namespace std; long long int power(long long int a, long long int n) { if (n == 0) { return 1; } long long int p = power(a, n / 2) % 998244353; p = (p * p) % 998244353; if (n % 2 == 1) { p = (p * a) % 998244353; } return p; } long long int gcd(long long int a, long long int b) { if (a == 0) return b; return gcd(b % a, a); } int isprime(long long int n) { for (long long int i = 2; i <= sqrt(n); i++) { if (n % i == 0) { return 0; } } return 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int t; cin >> t; while (t--) { long long int n; cin >> n; if (n >= 15) { n = n % 14; if (n <= 6 && n >= 1) { cout << YES << n ; } else { cout << NO << n ; } } else { cout << NO << n ; } } return 0; }
|
/*
Copyright (C) 2016
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//-------------------------------------------------------------------------
// https://github.com/balanx/laotzu
//
// Description : submodule of stream_asyn_fifo_controller
// write function
//
//-------------------------------------------------------------------------
// History :
// 10/15/2016
// initial draft
//
//-------------------------------------------------------------------------
module stream_asyn_fifo_write #(
parameter ADDRWIDTH = 6,
parameter [ADDRWIDTH:0] FIFODEPTH = 44,
parameter [ADDRWIDTH:0] HEADSIZE = 0,
parameter [ADDRWIDTH:0] MINBIN2 = 0,
parameter [ADDRWIDTH:0] MAXBIN2 = 7
) (
input wire w_clk ,
input wire w_rst_n ,
input wire [2:0] w_ctrl , // see below 'command definition'
input wire [ADDRWIDTH:0] r2w_ptr ,
output reg [ADDRWIDTH-1:0] wbin ,
output [ADDRWIDTH:0] wptr ,
output inc ,
output reg w_full ,
output reg [ADDRWIDTH:0] w_counter,
output reg w_error
);
// command definition
localparam [2:0]
NOP = 3'd0,
WRITE = 3'd1,
EOF_WITH_WRITE = 3'd2,
EOF_WITHOUT_WRITE = 3'd3,
HEAD = 3'd4,
FINAL_HEAD = 3'd5,
DISCARD = 3'd6;
// NO write when full
wire [2:0] w_ctrl_t = ( w_ctrl == DISCARD ) ? DISCARD :
w_full ? NOP : w_ctrl ;
// pointer inc.
assign inc_t = ( w_ctrl_t == WRITE || w_ctrl_t == EOF_WITH_WRITE ) ;
// RAM write enable
assign inc = inc_t || (w_ctrl_t == HEAD) || (w_ctrl_t == FINAL_HEAD) ;
wire withouthead = ( HEADSIZE == { (ADDRWIDTH+1){1'b0} } ) ;
// end-of-frame-with-write
wire eofww = ( w_ctrl_t == EOF_WITH_WRITE ) ;
reg eofww_d ;
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
eofww_d <= 1'b0 ;
else
eofww_d <= eofww ;
// final-data-without-head
wire fdwoh = ( withouthead &&
( eofww_d || w_ctrl_t == EOF_WITHOUT_WRITE )
);
// final-data-with-head
wire fdwhead = ( !withouthead &&
( eofww || w_ctrl_t == EOF_WITHOUT_WRITE )
);
//---------------------------------------------------------------
// "wbin2" is double the amount of "wbin"
// e.g. deepth = 10
// wbin = 0~9
// wbin2 = 6~15, 16~25
// MINBIN2 = 6
//---------------------------------------------------------------
reg [ADDRWIDTH:0] wbin2, wbin2_prev;
wire [ADDRWIDTH:0] wbnext = (wbin2>=MINBIN2 && wbin2<MAXBIN2) ?
(wbin2 + 1'b1) : MINBIN2;
//
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
wbin2 <= bin2add(MINBIN2);
else if ( w_ctrl_t == DISCARD ) // discard
wbin2 <= bin2add(wbin2_prev);
else if ( w_ctrl_t == FINAL_HEAD ) // final-head
wbin2 <= bin2add(wbin2);
else if ( inc_t )
wbin2 <= wbnext;
//
reg [ADDRWIDTH:0] wbin2_prev_t;
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
wbin2_prev_t <= MINBIN2;
else if ( eofww_d || w_ctrl_t == EOF_WITHOUT_WRITE )
wbin2_prev_t <= wbin2;
//
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
wbin2_prev <= MINBIN2;
else if ( w_ctrl_t == FINAL_HEAD ) // final-head
wbin2_prev <= ( eofww_d ? wbin2 : wbin2_prev_t ) ;
else if ( fdwoh ) // final-data
wbin2_prev <= wbin2;
//---------------------------------------------------------------
// memory address
//---------------------------------------------------------------
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
wbin <= HEADSIZE;
else if ( w_ctrl_t == DISCARD ) // discard
wbin <= bin2tobin( bin2add(wbin2_prev) );
else if ( fdwhead ) // head position
wbin <= bin2tobin(wbin2_prev);
else if ( w_ctrl_t == EOF_WITHOUT_WRITE
|| w_ctrl_t == FINAL_HEAD ) // next frame
wbin <= bin2tobin( bin2add(wbin2) );
else if ( inc_t || w_ctrl_t == HEAD ) // +1
wbin <= (wbin >= MAXBIN2[ADDRWIDTH-1:0]) ? {ADDRWIDTH{1'b0}} : (wbin + 1'b1);
//---------------------------------------------------------------
// to other-side
//---------------------------------------------------------------
assign wptr = wbin2_prev;
//---------------------------------------------------------------
// from other-side
//---------------------------------------------------------------
reg [ADDRWIDTH:0] r2w_bin;
always @(r2w_ptr)
begin: GrayToBin
integer i;
for (i=ADDRWIDTH; i>=0; i=i-1)
r2w_bin[i] = ^(r2w_ptr>>i);
end
//---------------------------------------------------------------
// output signals
//---------------------------------------------------------------
wire [ADDRWIDTH:0] distance = ( (wbin2 >= r2w_bin) ?
(wbin2 - r2w_bin) :
(wbin2 - r2w_bin - (MINBIN2<<1) )
) +
( w_ctrl_t == FINAL_HEAD ? HEADSIZE : inc_t );
//
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
w_counter <= {(ADDRWIDTH+1){1'b0}};
else
w_counter <= distance;
//
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
w_full <= 1'b0;
else
w_full <= (distance >= FIFODEPTH);
//
always @(posedge w_clk or negedge w_rst_n)
if (!w_rst_n)
w_error <= 1'b0;
else
w_error <= (w_counter > (FIFODEPTH + HEADSIZE) );
//
function [ADDRWIDTH-1:0] bin2tobin;
input [ADDRWIDTH:0] b2;
begin
bin2tobin = b2[ADDRWIDTH] ? b2[ADDRWIDTH-1:0] :
(b2[ADDRWIDTH-1:0] - MINBIN2[ADDRWIDTH-1:0]);
end
endfunction
//
function [ADDRWIDTH:0] bin2add;
input [ADDRWIDTH:0] b2;
reg [ADDRWIDTH:0] sum;
begin
sum = b2 + HEADSIZE;
if (sum >= b2 && sum <= MAXBIN2)
bin2add = sum;
else
bin2add = sum + MINBIN2 + (~MAXBIN2);
end
endfunction
//
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DECAP_4_V
`define SKY130_FD_SC_MS__DECAP_4_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__decap_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DECAP_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_PP_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, LVPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const double eps = 1e-6; const int mod = 1000000007; int modpow(int x, int y, int md) { if (y == 0) return 1; int ret = modpow(x, y >> 1, md); ret = (long long)ret * ret % md; if (y & 1) ret = (long long)ret * x % md; return ret; } int n; int sum[5555]; vector<int> g[5555]; set<pair<int, int> > ans; void dfs(int x, int par = 0) { sum[x] = 1; for (auto to : g[x]) if (to != par) dfs(to, x); for (auto to : g[x]) if (to != par) sum[x] += sum[to]; vector<bool> ok(5555, false); ok[0] = true; for (auto to : g[x]) if (to != par) { for (int i = 5005; i >= 0; i--) if (ok[i] && i + sum[to] <= 5005) ok[i + sum[to]] = true; } for (int i = 1; i <= 5005; i++) if (ok[i] && n - i - 1 >= 1) ans.insert(make_pair(i, n - i - 1)), ans.insert(make_pair(n - i - 1, i)); } int main() { cin >> n; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } dfs(1); cout << ans.size() << endl; for (auto p : ans) cout << p.first << << p.second << endl; return 0; }
|
`timescale 1 ns / 1 ps
module axis_gpio_reader #
(
parameter integer GPIO_DATA_WIDTH = 8,
parameter integer GPIO_INPUT_WIDTH = 2,
parameter integer GPIO_OUTPUT_WIDTH = 6
)
(
// System signals
input wire aclk,
input wire aresetn,
inout wire [GPIO_DATA_WIDTH-1:0] gpio_data,
input wire soft_trig,
output wire trigger
);
reg [GPIO_DATA_WIDTH-1:0] int_data_reg [1:0];
reg int_trig_reg, int_trig_reg_next;
wire [GPIO_DATA_WIDTH-1:0] int_data_wire;
wire [GPIO_OUTPUT_WIDTH-1:0] int_output;
genvar j;
// input pins
generate
for(j = 0; j < GPIO_INPUT_WIDTH; j = j + 1)
begin : GPIO
IOBUF gpio_iobuf (.O(int_data_wire[j]), .IO(gpio_data[j]), .I({(GPIO_INPUT_WIDTH){1'b0}}), .T(1'b1));
end
endgenerate
// output pins
generate
for(j = GPIO_INPUT_WIDTH; j < GPIO_DATA_WIDTH; j = j + 1)
begin : GPIO_OUT
IOBUF gpio_iobuf (.O(int_data_wire[j]), .IO(gpio_data[j]), .I(int_output[j-GPIO_INPUT_WIDTH]), .T(1'b0));
end
endgenerate
always @(posedge aclk)
begin
int_data_reg[0] <= int_data_wire;
int_data_reg[1] <= int_data_reg[0];
if(~aresetn)
int_trig_reg <= 1'b0;
else
int_trig_reg <= int_trig_reg_next;
end
always @*
begin
int_trig_reg_next = int_trig_reg;
if(soft_trig | int_data_reg[1][0:0])
int_trig_reg_next = 1'b1;
end
assign trigger = int_trig_reg;
assign int_output = {{(GPIO_OUTPUT_WIDTH-2){1'b0}},aclk,trigger};
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n, a[maxn]; struct node { int pre; bool flag; int other; } num[2 * maxn]; int main(int argc, char const *argv[]) { while (cin >> n) { bool flag = true; for (int i = 0; i <= n; i++) { cin >> a[i]; if (a[i] != 1) flag = false; } if (flag == true) { cout << perfect << endl; continue; } bool temp = false; bool ans = false; int cnt = 1; for (int i = 0; i <= n; i++) { if (i > 0 && a[i] > 1 && a[i - 1] > 1 && ans == false) { ans = true; int par = cnt - 1; int k = a[i]; k--; while (k--) { num[cnt].pre = par; num[cnt].other = par - 1; num[cnt].flag = true; cnt++; } num[cnt].pre = num[cnt].other = par; num[cnt].flag = true; cnt++; } else { int par = cnt - 1; int k = a[i]; while (k--) { num[cnt].pre = par; num[cnt].flag = false; cnt++; } } } if (ans == false) { cout << perfect << endl; continue; } cout << ambiguous << endl; for (int i = 1; i < cnt; i++) cout << num[i].pre << ; cout << endl; for (int i = 1; i < cnt; i++) { if (num[i].flag == false) cout << num[i].pre; else cout << num[i].other; cout << ; } cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 150; const double eps = 1e-8; struct point { double x, y; point() {} point(double _x, double _y) : x(_x), y(_y) {} friend bool operator<(const point &a, const point &b) { if (fabs(a.x - b.x) < eps) { return a.y < b.y; } return a.x < b.x; } }; vector<point> vec; map<point, int> vis; point square1; point CircumCenter(point a, point b, point c) { point cp; double a1 = b.x - a.x, b1 = b.y - a.y, c1 = (a1 * a1 + b1 * b1) / 2; double a2 = c.x - a.x, b2 = c.y - a.y, c2 = (a2 * a2 + b2 * b2) / 2; double d = a1 * b2 - a2 * b1; cp.x = a.x + (c1 * b2 - c2 * b1) / d; cp.y = a.y + (a1 * c2 - a2 * c1) / d; return cp; } double getDistance(point a, point b) { return sqrt((a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y)); } double dianji(point veca, point vecb) { return veca.x * vecb.x + veca.y * vecb.y; } bool isLenEqual(point a, point b, point c) { if (fabs(getDistance(a, b) - getDistance(a, c)) < eps) return true; return false; } int fdTriangle(point a, point b, point c) { point vecOne = point(a.x - b.x, a.y - b.y); point vecTwo = point(b.x - c.x, b.y - c.y); point vecThree = point(c.x - a.x, c.y - a.y); double dj1 = dianji(vecOne, vecTwo); double dj2 = dianji(vecTwo, vecThree); double dj3 = dianji(vecThree, vecOne); if (fabs(dj1) < eps || fabs(dj2) < eps || fabs(dj3) < eps) { if (fabs(dj1) < eps && isLenEqual(a, b, c)) { square1 = a; return 2; } else if (fabs(dj2) < eps && isLenEqual(c, a, b)) { square1 = c; return 2; } else if (fabs(dj3) < eps && isLenEqual(b, a, c)) { square1 = b; return 2; } return 0; } if (dj1 < 0 && dj2 < 0 && dj3 < 0) return 1; return 0; } void compute() { double mx = -1.0; point all_ans; int all_flag = 0; for (int i = 0; i < vec.size(); i++) { for (int j = 0; j < vec.size(); j++) { for (int k = 0; k < vec.size(); k++) { if (i == j || j == k || i == k) continue; int flag = 0; point pos_ans; point a = vec[i], b = vec[j], c = vec[k]; if (!(fabs((b.y - a.y) * (c.x - b.x) - (b.x - a.x) * (c.y - b.y)) < eps)) { int type = fdTriangle(a, b, c); if (type == 1) { flag = 1; pos_ans = CircumCenter(a, b, c); } else if (type == 2) { point cc = CircumCenter(a, b, c); double X = 2 * cc.x - square1.x; double Y = 2 * cc.y - square1.y; if (vis[point(X, Y)] == 1) { flag = 1; pos_ans = cc; } } } if (flag == 1) { double r = getDistance(pos_ans, a); for (int z = 0; z < vec.size(); z++) { point each = vec[z]; if (getDistance(pos_ans, each) + eps < r) { flag = 0; break; } } if (flag == 1 && mx < r) { mx = r; all_flag = 1; all_ans = pos_ans; } } } } } if (all_flag == 1) { printf( %.6f n , mx); } else { printf( -1 n ); } } int main() { int n; while (cin >> n) { vis.clear(); vec.clear(); for (int i = 0; i < n; i++) { double x, y; cin >> x >> y; point p = point(x, y); vec.push_back(p); vis[p] = 1; } compute(); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int M = 10 + 10; int minn0[M][M]; int minn[M][M]; int dig[M]; int dignum; int fac(int x) { int ans = 1; for (int i = 1; i <= x; i++) { ans = ans * i; } return ans; } int ex(int a, int x) { int ans = 1; for (int i = 1; i <= x; i++) { ans = ans * a; } return ans; } void mluckyinn0() { for (int n = 1; n <= 9; n++) { for (int m = 0; m <= n; m++) { minn0[0][m] = 1; int nchm = fac(n) / fac(m) / fac(n - m); int lucky = ex(2, m); int unlucky = ex(8, n - m); minn0[n][m] = nchm * lucky * unlucky; } } } void mluckyinn() { minn[1][0] = 7; minn[1][1] = 2; for (int n = 2; n <= 9; n++) { for (int m = 0; m <= n; m++) { int t1 = 0; if (m - 1 >= 0 && n - 1 >= 0) { t1 = minn0[n - 1][m - 1]; } minn[n][m] = 2 * t1 + 7 * minn0[n - 1][m]; } } } void caldig(int x) { int idx = 0; while (x > 0) { dig[dignum - idx] = x % 10; x = x / 10; idx++; } } int lnum[M]; long long int mod = 1000000000 + 7; int main() { int m; cin >> m; mluckyinn0(); mluckyinn(); int tmp = m; while (tmp > 0) { dignum++; tmp /= 10; } caldig(m); for (int d = 1; d < dignum; d++) { for (int j = 0; j <= d; j++) { lnum[j] = lnum[j] + minn[d][j]; } } int pre = 0; int fi = 0; for (int i = 1; i <= dignum; i++) { int st = 0; if (i == 1) { st = 1; } int y47 = 0; int n47 = 0; for (int j = st; j < dig[i]; j++) { if (j == 4 || j == 7) { y47++; } else { n47++; } } int flag = 0; if (y47 > 0) { flag = 1; } int ndg = dignum - i; for (int j = 0; j <= ndg; j++) { lnum[pre + j] = lnum[pre + j] + minn0[ndg][j] * n47; lnum[pre + j + flag] = lnum[pre + j + flag] + minn0[ndg][j] * y47; } if (dig[i] == 4 || dig[i] == 7) { pre++; } } lnum[pre]++; long long int ans = 0; int sta[M]; for (int i1 = 0; i1 <= 9; i1++) { sta[1] = lnum[i1]; lnum[i1]--; for (int i2 = 0; i2 <= 9; i2++) { sta[2] = lnum[i2]; lnum[i2]--; for (int i3 = 0; i3 <= 9; i3++) { sta[3] = lnum[i3]; lnum[i3]--; for (int i4 = 0; i4 <= 9; i4++) { sta[4] = lnum[i4]; lnum[i4]--; for (int i5 = 0; i5 <= 9; i5++) { sta[5] = lnum[i5]; lnum[i5]--; for (int i6 = 0; i6 <= 9; i6++) { sta[6] = lnum[i6]; lnum[i6]--; int st = i1 + i2 + i3 + i4 + i5 + i6; for (int i7 = st + 1; i7 <= 9; i7++) { sta[7] = lnum[i7]; lnum[i7]--; long long int val = 1; for (int j = 1; j <= 7; j++) { if (sta[j] <= 0) { val = 0; break; } else { val = (val * sta[j]) % mod; } } ans = (ans + val) % mod; lnum[i7]++; } lnum[i6]++; } lnum[i5]++; } lnum[i4]++; } lnum[i3]++; } lnum[i2]++; } lnum[i1]++; } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int work() { long long n, q; cin >> n >> q; while (q--) { long long x, y; cin >> x >> y; if ((x + y) % 2 == 0) { long long w = 0; long long a = (x - 1) / 2; w += a * n; if (x % 2 == 1) { w += (y + 1) / 2; } else { w += (n + 1) / 2; w += y / 2; } cout << w << endl; } else { long long w = (n * n + 1) / 2; long long a = (x - 1) / 2; w += a * n; if (x % 2 == 1) { w += y / 2; } else { w += n / 2; w += (y + 1) / 2; } cout << w << endl; } } return 0; } int main() { work(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int t, n, i, l, k; cin >> t; while (t--) { cin >> n >> k >> l; int s = 0, f = 2 * k - 1, dep, flg = 1; for (i = 1; i <= n; i++) { cin >> dep; if (!flg) continue; if (l < dep) { cout << NO << endl; flg = 0; } if (!flg) continue; int s1 = k - 1 - (l - dep), f1 = k - 1 + (l - dep); if (s1 < 0) s1 = 0; if (f1 > 2 * k - 1) f1 = 2 * k - 1; if (s1 == 0 && f1 == 2 * k - 1) { s = 0; f = 2 * k - 1; continue; } if (s == 0 && f == 2 * k - 1) { s = s1; f = f1; continue; } s = max(s + 1, s1); f = f1; if (s > f) { cout << NO << endl; flg = 0; } } if (flg) cout << YES << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; inline long long GCD(long long a, long long b) { while (b != 0) { int t = a; a = b; b = t % b; } return a; } inline long long LCM(long long a, long long b) { if (a == 0 || b == 0) return GCD(a, b); return a * b / GCD(a, b); } inline long long CEIL(long long n, long long d) { return n / d + n % d != 0; } inline long long ROUND(long long n, long long d) { return n / d + (long long)((n % d) * 2 >= d); } inline long long POW(long long a, long long n) { if (n < 0) return 0; long long ret = 1; while (n) { if (n % 2) ret *= a; a = a * a; n /= 2; } return ret; } const int MAXN = 101, INF = 100000; struct node { node *l, *r, *p; int bdp[MAXN], mdp[MAXN]; node(node *p = 0) : l(0), r(0), p(p) { fill(bdp, bdp + MAXN, -INF); fill(mdp, mdp + MAXN, INF); } node *child() { if (!l) return l = new node(this); else return r = new node(this); } } * root, *cur; int p, m, n, op; string str; void input() { cin >> str >> p >> m; } void dfs(node *u) { if (!u->l) { return; } node *l = u->l, *r = u->r; dfs(l), dfs(r); for (int(i) = (0); (i) < (int)(n + 1); ++(i)) { for (int(j) = (0); (j) < (int)(i + 1); ++(j)) { int k = i - j - (op == 1 ? 1 : 0); if (k >= 0) u->bdp[i] = max(u->bdp[i], l->bdp[j] + r->bdp[k]); if (k >= 0) u->mdp[i] = min(u->mdp[i], l->mdp[j] + r->mdp[k]); k = i - j - (op == -1 ? 1 : 0); if (k >= 0) u->bdp[i] = max(u->bdp[i], l->bdp[j] - r->mdp[k]); if (k >= 0) u->mdp[i] = min(u->mdp[i], l->mdp[j] - r->bdp[k]); } } } int solve() { if (p > m) n = m, op = -1; else n = p, op = 1; root = cur = new node(); for (int(i) = (0); (i) < (int)(str.size()); ++(i)) { switch (str[i]) { case ( : case ? : cur = cur->child(); break; case ) : cur = cur->p; break; default: cur->bdp[0] = cur->mdp[0] = str[i] - 0 ; cur = cur->p; } } assert(cur == 0); dfs(root); cout << root->bdp[n] << n ; return 0; } void execute() { input(), solve(); } int main(void) { cin.tie(0); ios_base::sync_with_stdio(false); execute(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 510; const int MOD = 1e9 + 7; long long dp[2][maxn][maxn]; int N, M; char s[maxn][maxn]; void add(long long &x, long long y) { x += y; if (x >= MOD) x -= MOD; } int main() { scanf( %d%d , &N, &M); for (int i = 1; i <= N; i++) scanf( %s , s[i] + 1); dp[0][1][N] = (s[1][1] == s[N][M]); int cur = 0; for (int step = 1; step <= (M + N - 2) / 2; step++) { cur ^= 1; for (int i = 0; i <= N; i++) for (int j = 1; j <= N; j++) dp[cur][i][j] = 0; for (int x1 = 1; x1 <= N && x1 - 1 <= step; x1++) { for (int x2 = N; x2 >= 1 && N - x2 <= step; x2--) { int y1 = 1 + step - (x1 - 1); int y2 = M - (step - (N - x2)); if (s[x1][y1] != s[x2][y2]) continue; add(dp[cur][x1][x2], dp[cur ^ 1][x1][x2]); add(dp[cur][x1][x2], dp[cur ^ 1][x1][x2 + 1]); add(dp[cur][x1][x2], dp[cur ^ 1][x1 - 1][x2]); add(dp[cur][x1][x2], dp[cur ^ 1][x1 - 1][x2 + 1]); } } } long long ans = 0; for (int i = 1; i <= N; i++) { add(ans, dp[cur][i][i]); } if ((N + M) % 2) { for (int i = 1; i < N; i++) add(ans, dp[cur][i][i + 1]); } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 7; string a[N]; int r[N], c[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; for (int i = 0; i <= n; i++) r[i] = 0; for (int j = 0; j <= m; j++) c[j] = 0; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (a[i][j] == . ) r[i]++, c[j]++; int ans = 1e9 + 7; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int cur = r[i] + c[j]; if (a[i][j] == . ) cur--; ans = min(ans, cur); } cout << ans << n ; } }
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module aes_8_bit (rst, clk, key_in, d_in, d_out, d_vld);
input rst, clk;
input [7:0] key_in;
input [7:0] d_in;
output [7:0] d_out;
output reg d_vld;
//key scheduler controller
wire [3:0] round_cnt_w;
reg input_sel, sbox_sel, last_out_sel, bit_out_sel;
reg [7:0] rcon_en;
reg [3:0] cnt;
reg [7:0] round_cnt;
reg [2:0] state;
wire [7:0] rk_delayed_out, rk_last_out;
reg [1:0] c3;
wire pld;
reg [7:0] mc_en_reg;
reg pld_reg;
wire [7:0] mc_en;
reg [7:0] d_out;
wire [7:0] d_out_w;
always @ (posedge clk)
begin
d_out <= d_out_w;
end
assign pld = pld_reg;
assign mc_en = mc_en_reg;
assign round_cnt_w = round_cnt[7:4];
key_expansion key (key_in, rk_delayed_out, round_cnt_w, rk_last_out, clk, input_sel, sbox_sel, last_out_sel, bit_out_sel, rcon_en);
aes_data_path data_path (d_in, d_out_w, pld, c3, clk, mc_en, rk_delayed_out, rk_last_out);
parameter load = 3'h0; //load 16 byte
parameter b1st = 3'h1; //first byte need rcon
parameter b2nd = 3'h2; //2byte go through sbox
parameter b3rd = 3'h3; //last byte go through sbox from redundant register
parameter norm = 3'h4; //normal round calculate two columns
parameter shif = 3'h5; //shift 4 byte
//state machine for key schedule
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
state <= load;
cnt <= 4'h0;
end
else
begin
case (state)
load:
begin
cnt <= cnt + 4'h1;
if (cnt == 4'hf)
begin
state <= b1st;
cnt <= 4'h0;
end
end
b1st:
begin
state <= b2nd;
cnt <= 4'h0;
end
b2nd:
begin
cnt <= cnt + 4'h1;
if (cnt == 4'h1)
begin
state <= b3rd;
cnt <= 4'h0;
end
end
b3rd:
begin
state <= norm;
cnt <= 4'h0;
end
norm:
begin
cnt <= cnt + 4'h1;
if(cnt == 4'h7)
begin
state <= shif;
cnt <= 4'h0;
end
end
shif:
begin
cnt <= cnt + 4'h1;
if(cnt == 4'h3)
begin
state <= b1st;
cnt <= 4'h0;
end
end
endcase
end
end
//mux select and rcon enable for key schedule
always @ (*)
begin
case(state)
load:
begin
input_sel <= 1'b0;
sbox_sel <= 1'b1;
last_out_sel <= 1'b0;
bit_out_sel <= 1'b0;
rcon_en <= 8'h00;
end
b1st:
begin
input_sel <= 1'b1;
sbox_sel <= 1'b1;
last_out_sel <= 1'b0;
bit_out_sel <= 1'b1;
rcon_en <= 8'hFF;
end
b2nd:
begin
input_sel <= 1'b1;
sbox_sel <= 1'b1;
last_out_sel <= 1'b0;
bit_out_sel <= 1'b1;
rcon_en <= 8'h00;
end
b3rd:
begin
input_sel <= 1'b1;
sbox_sel <= 1'b0;
last_out_sel <= 1'b0;
bit_out_sel <= 1'b1;
rcon_en <= 8'h00;
end
norm:
begin
input_sel <= 1'b1;
sbox_sel <= 1'b0;
last_out_sel <= 1'b1;
bit_out_sel <= 1'b1;
rcon_en <= 8'h00;
end
shif:
begin
input_sel <= 1'b1;
sbox_sel <= 1'b0;
last_out_sel <= 1'b1;
bit_out_sel <= 1'b0;
rcon_en <= 8'h00;
end
default:
begin
input_sel <= 1'b0;
sbox_sel <= 1'b1;
last_out_sel <= 1'b0;
bit_out_sel <= 1'b0;
rcon_en <= 8'h00;
end
endcase
end
//round counter
always @ (posedge clk)
begin
if (rst == 1'b1 || cnt == 4'hf || round_cnt_w == 4'ha)
begin
round_cnt <= 6'h00;
end
else
begin
round_cnt <= round_cnt + 6'h01;
end
end
//state machine shift row
always @ (posedge clk)
begin
if (state == load)
begin
c3 <= 2'h3;
end
else
begin
case (round_cnt[3:0])
4'h0: c3 <= 2'h2;
4'h1: c3 <= 2'h1;
4'h2: c3 <= 2'h0;
4'h3: c3 <= 2'h3;
4'h4: c3 <= 2'h2;
4'h5: c3 <= 2'h1;
4'h6: c3 <= 2'h1;
4'h7: c3 <= 2'h3;
4'h8: c3 <= 2'h2;
4'h9: c3 <= 2'h3;
4'hA: c3 <= 2'h2;
4'hB: c3 <= 2'h3;
4'hC: c3 <= 2'h3;
4'hD: c3 <= 2'h3;
4'hE: c3 <= 2'h3;
4'hF: c3 <= 2'h3;
endcase
end
end
//mixcoloumn enable
always @ (posedge clk)
begin
if (round_cnt[1:0] == 2'b11)
begin
mc_en_reg <= 8'h00;
end
else
begin
mc_en_reg <= 8'hFF;
end
end
//parelle load
always @ (posedge clk)
begin
if (state == load)
begin
pld_reg <= 1'b0;
end
else
begin
if (round_cnt[1:0] == 2'b11)
begin
pld_reg <= 1'b1;
end
else
begin
pld_reg <= 1'b0;
end
end
end
always @(posedge clk)
begin
if (rst == 1'b1)
begin
d_vld <= 1'b0;
end
else
begin
if (round_cnt == 8'h90)
begin
d_vld <= 1'b1;
end
end
end
endmodule
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// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: fifo_packer_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Packs 32 bit received data into a 32 bit wide FIFO.
// Assumes the FIFO always has room to accommodate the data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
// Additional Comments:
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module fifo_packer_32 (
input CLK,
input RST,
input [31:0] DATA_IN, // Incoming data
input DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [31:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [31:0] rDataIn=64'd0, _rDataIn=64'd0;
reg rDataInEn=0, _rDataInEn=0;
assign PACKED_DATA = rDataIn;
assign PACKED_WEN = rDataInEn;
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data to ease timing.
always @ (posedge CLK) begin
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 1'd0 : _rDataInEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule
|
/*
File: pulse2toggle.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module pulse2toggle(/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in, reset
);
//clocks
input clk;
input in;
output out;
//reset
input reset;
reg out;
wire toggle;
//if input goes high, toggle output
//note1: input can only be high for one clock cycle
//note2: be careful with clock gating
assign toggle = in ? ~out :
out;
always @ (posedge clk or posedge reset)
if(reset)
out <= 1'b0;
else
out <= toggle;
endmodule // pulse2toggle
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; const double PI = 3.1415926535897932; const int dir[8][2] = {-1, -1, -1, 0, -1, 1, 0, -1, 0, 1, 1, -1, 1, 0, 1, 1}; const int maxn = 2e5 + 5; const int MOD = 998244353; int n, m; long long A[maxn], invA[maxn]; int w[maxn]; bool vis[maxn]; bool del[maxn]; int B[maxn]; int pos[maxn]; int pre[maxn], nex[maxn]; bool judge(int x) { if (x == 0 || x == n + 1) return 0; if (vis[w[x]]) return 0; return 1; } int main() { int T; scanf( %d , &T); while (T--) { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { del[i] = vis[i] = false; pre[i] = i - 1; nex[i] = i + 1; } for (int i = 1; i <= n; i++) scanf( %d , &w[i]), pos[w[i]] = i; for (int i = 1; i <= m; i++) { scanf( %d , &B[i]); vis[B[i]] = true; } long long ans = 1; for (int i = 1; i <= m; i++) { int x = pos[B[i]]; int cnt = 0; cnt += judge(pre[x]); cnt += judge(nex[x]); ans = ans * cnt % MOD; vis[w[x]] = false; nex[pre[x]] = nex[x]; pre[nex[x]] = pre[x]; } printf( %lld n , ans); } return 0; }
|
(** * Rel: Properties of Relations *)
Require Export SfLib.
(** This short, optional chapter develops some basic definitions and a
few theorems about binary relations in Coq. The key definitions
are repeated where they are actually used (in the [Smallstep]
chapter), so readers who are already comfortable with these ideas
can safely skim or skip this chapter. However, relations are also
a good source of exercises for developing facility with Coq's
basic reasoning facilities, so it may be useful to look at it just
after the [Logic] chapter. *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Somewhat confusingly, the Coq standard library hijacks the generic
term "relation" for this specific instance. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, while the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-than-or-equal-to
relation which we usually write like this [n1 <= n2]. *)
Print le.
(* ====> Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m *)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(* ######################################################### *)
(** * Basic Properties of Relations *)
(** As anyone knows who has taken an undergraduate discrete math
course, there is a lot to be said about relations in general --
ways of classifying relations (are they reflexive, transitive,
etc.), theorems that can be proved generically about classes of
relations, constructions that build one relation from another,
etc. For example... *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., if [R x
y1] and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined earlier is a partial
function. *)
Print next_nat.
(* ====> Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n) *)
Check next_nat : relation nat.
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity. Qed.
(** However, the [<=] relation on numbers is not a partial function.
In short: Assume, for a contradiction, that [<=] is a partial
function. But then, since [0 <= 0] and [0 <= 1], it follows that
[0 = 1]. This is nonsense, so our assumption was
contradictory. *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense.
{ (* Proof of assertion *)
apply Hc with (x := 0).
- apply le_n.
- apply le_S. apply le_n. }
inversion Nonsense. Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in earlier is not a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] defined earlier is a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
- (* le_n *) apply Hnm.
- (* le_S *) apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using le_trans. Do this.*)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
apply le_S. apply le_n.
apply H. Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~(S n <= n)]
A formal proof of this is an optional exercise below, but try
the informal proof without doing the formal proof first.
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, here are a few more common ones.
A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
- (* refl *) apply le_reflexive.
- split.
+ (* antisym *) apply le_antisymmetric.
+ (* transitive. *) apply le_trans. Qed.
(* ########################################################### *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y ->
clos_refl_trans R y z ->
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
- (* -> *)
intro H. induction H.
+ (* le_n *) apply rt_refl.
+ (* le_S *)
apply rt_trans with m. apply IHle. apply rt_step. apply nn.
- (* <- *)
intro H. induction H.
+ (* rt_step *) inversion H. apply le_S. apply le_n.
+ (* rt_refl *) apply le_n.
+ (* rt_trans *)
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is
natural -- it says, explicitly, that the reflexive and transitive
closure of [R] is the least relation that includes [R] and that is
closed under rules of reflexivity and transitivity. But it turns
out that this definition is not very convenient for doing
proofs -- the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions.
Here is a more useful definition... *)
Inductive refl_step_closure {X:Type} (R: relation X) : relation X :=
| rsc_refl : forall (x : X), refl_step_closure R x x
| rsc_step : forall (x y z : X),
R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
(** (Note that, aside from the naming of the constructors, this
definition is the same as the [multi] step relation used in many
other chapters.) *)
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [refl_step_closure] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Theorem rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> refl_step_closure R x y.
Proof.
intros X R x y H.
apply rsc_step with y. apply H. apply rsc_refl. Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Theorem rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
refl_step_closure R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> refl_step_closure R x y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date$ *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:35:06 04/15/2014
// Design Name:
// Module Name: diff_d2e
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module diff_d2e(
clk,clrn,
wreg,m2reg,shift,aluimm,wmem,wzero,aluc,rd,qa,qb,eximme,sa,adepend,bdepend,sdepend,
ewreg,em2reg,eshift,ealuimm,ewmem,ewzero,ealuc,erd,eqa,eqb,eeximme,esa,eadepend,ebdepend,esdepend
);
input clk,clrn;
input wreg,m2reg,shift,aluimm,wmem,wzero;
input [3:0] aluc;
input [4:0] rd,sa;
input[31:0] qa,qb,eximme;
input [1:0] adepend,bdepend,sdepend;
output ewreg,em2reg,eshift,ealuimm,ewmem,ewzero;
output[3:0] ealuc;
output[4:0] erd,esa;
output[31:0] eqa,eqb,eeximme;
output [1:0] eadepend,ebdepend,esdepend;
dff1 push_wreg (wreg,clk,clrn,ewreg);
dff1 push_m2reg (m2reg,clk,clrn,em2reg);
dff1 push_shift (shift,clk,clrn,eshift);
dff1 push_aluimm (aluimm,clk,clrn,ealuimm);
dff1 push_wmem (wmem,clk,clrn,ewmem);
dff1 push_wzero (wzero,clk,clrn,ewzero);
dff4 push_aluc (aluc,clk,clrn,ealuc);
dff5 push_rd (rd,clk,clrn,erd);
dff5 push_sa (sa,clk,clrn,esa);
dff32 push_qa (qa,clk,clrn,eqa);
dff32 push_qb (qb,clk,clrn,eqb);
dff32 push_eximme (eximme,clk,clrn,eeximme);
dff2 push_adepend (adepend,clk,clrn,eadepend);
dff2 push_bdepend (bdepend,clk,clrn,ebdepend);
dff2 push_sdepend (sdepend,clk,clrn,esdepend);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 10; string s[105]; int n, last_hh, last_mm, last_tme, cur_tme, cur_mm, cur_hh, ans = 1, cnt = 0; int calch(int i) { return (s[i][1] - 0 ) * 10 + s[i][2] - 0 ; } int calcm(int i) { return (s[i][4] - 0 ) * 10 + s[i][5] - 0 ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; for (int i = 1; i <= n + 1; i++) getline(cin, s[i]); for (int i = 2; i <= n + 1; i++) { last_hh = calch(i - 1); if (last_hh == 12) last_hh = 0; last_mm = calcm(i - 1); cur_hh = calch(i); if (cur_hh == 12) cur_hh = 0; cur_mm = calcm(i); last_tme = last_hh * 60 + last_mm; cur_tme = cur_hh * 60 + cur_mm; if (s[i - 1][7] == p ) last_tme += 12 * 60; if (s[i][7] == p ) cur_tme += 12 * 60; if (last_tme > cur_tme) ans++, cnt = 0; else if (last_tme == cur_tme) { cnt++; if (cnt == 10) ans++, cnt = 0; } else cnt = 0; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 10; int a[N], b[N]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } vector<int> ans; for (int i = 1; i <= n; i++) { b[i] = a[i] - a[i - 1]; } for (int i = 1; i <= n; i++) { int flag = 0; for (int j = 1; i + j <= n; j++) { if (b[j] != b[i + j]) { flag++; break; } } if (!flag) { ans.push_back(i); } } cout << ans.size() << endl; for (auto i : ans) cout << i << ; return 0; }
|
module top
(
// CLOCKS
input CLOCK50, RESET_N,
// SWITCH Y LEDS
input [3:0]SWITCH_ARRAY_IO,
output [7:0]LED_ARRAY_IO,
// QSYS BULLSHIT
output wire hps_io_hps_io_emac1_inst_TX_CLK,
output wire hps_io_hps_io_emac1_inst_TXD0,
output wire hps_io_hps_io_emac1_inst_TXD1,
output wire hps_io_hps_io_emac1_inst_TXD2,
output wire hps_io_hps_io_emac1_inst_TXD3,
input wire hps_io_hps_io_emac1_inst_RXD0,
inout wire hps_io_hps_io_emac1_inst_MDIO,
output wire hps_io_hps_io_emac1_inst_MDC,
input wire hps_io_hps_io_emac1_inst_RX_CTL,
output wire hps_io_hps_io_emac1_inst_TX_CTL,
input wire hps_io_hps_io_emac1_inst_RX_CLK,
input wire hps_io_hps_io_emac1_inst_RXD1,
input wire hps_io_hps_io_emac1_inst_RXD2,
input wire hps_io_hps_io_emac1_inst_RXD3,
output wire [14:0] memory_mem_a,
output wire [2:0] memory_mem_ba,
output wire memory_mem_ck,
output wire memory_mem_ck_n,
output wire memory_mem_cke,
output wire memory_mem_cs_n,
output wire memory_mem_ras_n,
output wire memory_mem_cas_n,
output wire memory_mem_we_n,
output wire memory_mem_reset_n,
inout wire [31:0] memory_mem_dq,
inout wire [3:0] memory_mem_dqs,
inout wire [3:0] memory_mem_dqs_n,
output wire memory_mem_odt,
output wire [3:0] memory_mem_dm,
input wire memory_oct_rzqin
);
wire [7:0] led_array_io_hps;
ledtest inst_ledtest
(
// QSYS BS
.hps_io_hps_io_emac1_inst_TX_CLK (hps_io_hps_io_emac1_inst_TX_CLK),
.hps_io_hps_io_emac1_inst_TXD0 (hps_io_hps_io_emac1_inst_TXD0),
.hps_io_hps_io_emac1_inst_TXD1 (hps_io_hps_io_emac1_inst_TXD1),
.hps_io_hps_io_emac1_inst_TXD2 (hps_io_hps_io_emac1_inst_TXD2),
.hps_io_hps_io_emac1_inst_TXD3 (hps_io_hps_io_emac1_inst_TXD3),
.hps_io_hps_io_emac1_inst_RXD0 (hps_io_hps_io_emac1_inst_RXD0),
.hps_io_hps_io_emac1_inst_MDIO (hps_io_hps_io_emac1_inst_MDIO),
.hps_io_hps_io_emac1_inst_MDC (hps_io_hps_io_emac1_inst_MDC),
.hps_io_hps_io_emac1_inst_RX_CTL (hps_io_hps_io_emac1_inst_RX_CTL),
.hps_io_hps_io_emac1_inst_TX_CTL (hps_io_hps_io_emac1_inst_TX_CTL),
.hps_io_hps_io_emac1_inst_RX_CLK (hps_io_hps_io_emac1_inst_RX_CLK),
.hps_io_hps_io_emac1_inst_RXD1 (hps_io_hps_io_emac1_inst_RXD1),
.hps_io_hps_io_emac1_inst_RXD2 (hps_io_hps_io_emac1_inst_RXD2),
.hps_io_hps_io_emac1_inst_RXD3 (hps_io_hps_io_emac1_inst_RXD3),
.memory_mem_a (memory_mem_a),
.memory_mem_ba (memory_mem_ba),
.memory_mem_ck (memory_mem_ck),
.memory_mem_ck_n (memory_mem_ck_n),
.memory_mem_cke (memory_mem_cke),
.memory_mem_cs_n (memory_mem_cs_n),
.memory_mem_ras_n (memory_mem_ras_n),
.memory_mem_cas_n (memory_mem_cas_n),
.memory_mem_we_n (memory_mem_we_n),
.memory_mem_reset_n (memory_mem_reset_n),
.memory_mem_dq (memory_mem_dq),
.memory_mem_dqs (memory_mem_dqs),
.memory_mem_dqs_n (memory_mem_dqs_n),
.memory_mem_odt (memory_mem_odt),
.memory_mem_dm (memory_mem_dm),
.memory_oct_rzqin (memory_oct_rzqin),
// USEFUL SHIT
.clk_clk (CLOCK50),
.led_array_io_export (led_array_io_hps),
.switch_array_io_export (SWITCH_ARRAY_IO)
);
// ** PLL 200 ** //
wire clock200, locked200, reset;
assign reset = ~RESET_N;
pll_200 inst_pll_200(
.refclk (CLOCK50),
.rst (reset),
.outclk_0 (clock200),
.locked (locked200)
);
// ** LED BEHAVIOR ** //
assign LED_ARRAY_IO[7:2] = led_array_io_hps[7:2];
assign LED_ARRAY_IO[1] = led_array_io_hps[1] || counter_max;
assign LED_ARRAY_IO[0] = led_array_io_hps[0] || locked200;
// ** DUMMY FUNCTIONALITY FOR CLOCK200 ** //
integer counter; initial counter = 0;
parameter PWM_VALUE = 10000;
always @(posedge clock200 or negedge locked200) begin
if(~locked200) counter <= 0;
else begin
if(counter == PWM_VALUE)
counter <= 0;
else
counter <= counter + 1'b1;
end
end
wire counter_max;
assign counter_max = (counter == PWM_VALUE)? 1 : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; struct dsu { int forests = 0, parent[N], groupsize[N]; void add(int x) { parent[x] = x; groupsize[x] = 1; forests++; } int findset(int node) { if (parent[node] == node) return node; return parent[node] = findset(parent[node]); } bool issameset(int x, int y) { return findset(x) == findset(y); } void link(int i, int j) { int x = findset(i), y = findset(j); if (x == y) return; if (groupsize[x] < groupsize[y]) swap(x, y); groupsize[x] += groupsize[y]; parent[y] = x; forests--; } }; map<long long, int> mp; map<int, vector<pair<int, int>>> e; int main() { ios::sync_with_stdio(0), ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; int n, m; cin >> n >> m; dsu mst; for (int i = 1; i <= n; ++i) mst.add(i); for (int i = 1; i <= m; ++i) { int x, y, c; cin >> x >> y >> c; e[c].push_back({x, y}); } long long sum = 0, mx = 0; for (auto u : e) { int add = 0; for (auto uu : u.second) { if (!mst.issameset(uu.first, uu.second)) { add++; } } for (auto uu : u.second) { if (!mst.issameset(uu.first, uu.second)) { add--; mst.link(uu.first, uu.second); } } sum += add; } cout << sum << n ; return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: alt_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.1 Build 150 06/03/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_rom (
address,
clock,
q);
input [11:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "../sw/bootrom.rif"
`else
altsyncram_component.init_file = "./bootrom.mif"
`endif
,
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./bootrom.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./bootrom.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_rom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFXTP_PP_BLACKBOX_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_4_V
`define SKY130_FD_SC_HS__NOR3B_4_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3b_4 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3b_4 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_4_V
|
#include <bits/stdc++.h> using namespace std; namespace fastIO { bool IOerror = 0; inline bool blank(char ch) { return ch == || ch == n || ch == r || ch == t ; } inline long long read() { bool sign = 0; char ch = getchar(); long long x = 0; for (; blank(ch); ch = getchar()) ; if (IOerror) return 0; if (ch == - ) sign = 1, ch = getchar(); for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; if (sign) x = -x; return x; } }; // namespace fastIO using namespace fastIO; struct node { long long l, r, len; node(long long x, long long y) { l = x, r = y, len = y - x + 1; } bool operator<(const node& bb) const { return len != bb.len ? len > bb.len : l < bb.l; } }; set<node> s; long long now = 0; long long l[1000010], r[1000010], len[1000010], num[1000010], ans[2010][2010]; signed main() { long long n = read(), maxx = 0; s.insert(node(1, n + 1)); for (long long i = 1; i <= n; i++) { long long x = read(); now = 0; for (auto i : s) { l[++now] = i.l, r[now] = i.r, len[now] = i.len; num[now] = 0; } for (long long j = 1; j <= now; j++) { num[j] = 1; ans[l[j]][i] = 1; maxx = max(maxx, l[j]); x--; if (!x) break; } if (x) { for (long long j = 1; j <= now; j++) { while (num[j] < len[j] - 1 && x) { ans[l[j] + num[j]][i] = 1; maxx = max(maxx, l[j] + num[j]); num[j]++; x--; } } } if (x) { for (long long j = 1; j <= now; j++) { if (x && num[j] != len[j]) ans[r[j]][i] = 1, x--, num[j]++, maxx = max(maxx, r[j]); } } s.clear(); for (long long j = 1; j <= now; j++) { if (num[j]) s.insert(node(l[j], l[j] + num[j] - 1)); if (num[j] != len[j]) s.insert(node(l[j] + num[j], r[j])); if (len[j] == 1) s.insert(node(l[j], r[j])); } } cout << maxx << n ; for (long long i = 1; i <= maxx; i++) { for (long long j = 1; j <= n; j++) cout << ans[i][j]; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 105, mod = 1e9 + 7; int dp[N][N * N]; bool done[N][N * N]; int fact[N], inv[N]; int arr1[N]; int arr2[N]; int n, k; long long m; inline int add(int a, int b) { int res = a + b; if (res >= mod) res -= mod; return res; } inline int mult(int a, int b) { long long res = a * 1LL * b; return res % mod; } int powmod(int a, long long b) { int res = 1; while (b) { if (b & 1) { res = mult(res, a); } a = mult(a, a); b >>= 1; } return res; } int ncr(int n, int r) { int res = fact[n]; res = mult(res, inv[r]); res = mult(res, inv[n - r]); return res; } int solve(int pos, int cnt) { if (cnt < 0) return 0; if (pos == n + 1) return (cnt == 0); if (done[pos][cnt]) return dp[pos][cnt]; if ((n + 1 - pos) * n < cnt) return 0; long long p = m / n; bool b = (pos <= m % n); if (b) { for (int i = 0; i <= n; i++) { dp[pos][cnt] = add(mult(solve(pos + 1, cnt - i), arr2[i]), dp[pos][cnt]); } } else { for (int i = 0; i <= n; i++) { dp[pos][cnt] = add(mult(solve(pos + 1, cnt - i), arr1[i]), dp[pos][cnt]); } } done[pos][cnt] = true; return dp[pos][cnt]; } int main() { scanf( %d %I64d %d , &n, &m, &k); fact[0] = 1, inv[0] = 1; long long p = m / n; for (int i = 1; i < N; i++) { fact[i] = mult(fact[i - 1], i); inv[i] = powmod(fact[i], mod - 2); } for (int i = 0; i <= n; i++) { arr1[i] = powmod(ncr(n, i), p); arr2[i] = powmod(ncr(n, i), p + 1); } memset(dp, 0, sizeof(dp)); int ans = solve(1, k); printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 11111; pair<int, int> a[maxN]; short dp[maxN][maxN]; int s[maxN]; bool mycmp(pair<int, int> a, pair<int, int> b) { if (a.second != b.second) return (a.second < b.second); return (a.first > b.first); } int main() { ios_base::sync_with_stdio(false); int n, l, r; cin >> n >> l >> r; for (int i = 1; i <= n; ++i) { cin >> a[i].first; } for (int i = 1; i <= n; ++i) { cin >> a[i].second; } sort(a + 1, a + n + 1, mycmp); int sum = 0; for (int i = 1; i <= n; ++i) { sum += a[i].first; } s[0] = 0; for (int i = 1; i <= n; ++i) { s[i] = s[i - 1] + a[i].first; } for (int i = 0; i <= n; ++i) { for (int j = 0; j <= sum; ++j) { dp[i][j] = -1; } } dp[0][0] = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j <= s[i]; ++j) { if (dp[i][j] < 0) continue; int type = a[i + 1].second, w = a[i + 1].first; if (type == 0) { dp[i + 1][j + w] = max(dp[i + 1][j + w], dp[i][j]); dp[i + 1][j] = max(dp[i + 1][j], dp[i][j]); } else { int x = j, y = sum - (s[i] - j); short f1 = (x >= l && x <= r); if (dp[i][j] + f1 > dp[i + 1][j + w]) { dp[i + 1][j + w] = dp[i][j] + f1; } short f2 = (y - a[i + 1].first >= l && y - a[i + 1].first <= r); if (dp[i][j] + f2 > dp[i + 1][j]) { dp[i + 1][j] = dp[i][j] + f2; } } } } short ans = -1; for (int i = 0; i <= sum; ++i) { ans = max(ans, dp[n][i]); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, d; bool b; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { cin >> n >> d; b = false; if (d <= n) { cout << YES n ; continue; } for (long long x = 1; x * x <= d; x++) { long long X = x + 1; long long D = 0; D = d / X; if (d % X != 0) { D++; } long long sol = x + (D); if (sol <= n) { cout << YES n ; b = true; break; } } if (b == false) { cout << NO n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200004 * 4 + 11; long long k[N], add[N]; int a[200004]; int n, m; int x, y; long long z; long long ans; int build(int l, int r, int o) { add[o] = 0; if (l == r) return k[o] = a[l]; int mid = ((l + r) >> 1); return k[o] = build(l, mid, (o << 1)) + build(mid + 1, r, ((o << 1) | 1)); } void pushdown(int l, int r, int o) { add[(o << 1)] += add[o]; add[((o << 1) | 1)] += add[o]; add[o] = 0; } void maintain(int l, int r, int o) { int mid = ((l + r) >> 1); if (r > l) k[o] = k[(o << 1)] + add[(o << 1)] * (mid - l + 1) + k[((o << 1) | 1)] + add[((o << 1) | 1)] * (r - mid); else k[o] = a[l]; } void update(int l, int r, int o) { if (x <= l && r <= y) { add[o] += z; } else { pushdown(l, r, o); int mid = ((l + r) >> 1); if (x <= mid) update(l, mid, (o << 1)); else maintain(l, mid, (o << 1)); if (y > mid) update(mid + 1, r, ((o << 1) | 1)); else maintain(mid + 1, r, ((o << 1) | 1)); } maintain(l, r, o); } void query(int l, int r, int o) { if (x <= l && r <= y) ans += k[o] + add[o] * (r - l + 1); else { pushdown(l, r, o); int mid = ((l + r) >> 1); if (x <= mid) query(l, mid, (o << 1)); if (y > mid) query(mid + 1, r, ((o << 1) | 1)); } maintain(l, r, o); } int main() { long long lst = 0.0; while (~scanf( %d , &n)) { int i, c, e, f; int d; int tot = 1; int tp = 0; build(1, 200004, 1); while (n--) { scanf( %d , &c); if (c == 1) { scanf( %d%d , &e, &d); z = d; x = 1; y = min(e, tot); update(1, 200004, 1); lst += e * d; } else if (c == 2) { scanf( %d , &d); tot++; x = y = tot; z = d; update(1, 200004, 1); lst += d; } else { ans = 0; x = y = tot; query(1, 200004, 1); z = -ans; update(1, 200004, 1); tot--; lst += z; } ans = 0; x = 1; y = 200004; query(1, n, 1); printf( %.9lf n , ans * 1.0 / tot); } } return 0; }
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [7:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output r213f_enable,
output snescmd_enable,
output obc1_enable
);
parameter [2:0]
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_OBC1 = 5
;
wire [23:0] SRAM_SNES_ADDR;
/* currently supported mappers:
Index Mapper
000 HiROM
001 LoROM
010 ExHiROM (48-64Mbit)
*/
/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
Offset 6000-7fff */
assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]));
assign IS_SAVERAM = SAVERAM_MASK[0]
&(((MAPPER == 3'b000
|| MAPPER == 3'b010)
? (!SNES_ADDR[22]
& SNES_ADDR[21]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
)
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd
* Offset 0000-7fff for ROM >= 32 MBit, otherwise 0000-ffff */
:(MAPPER == 3'b001)
? (&SNES_ADDR[22:20]
& (SNES_ADDR[19:16] < 4'b1110)
& (~SNES_ADDR[15] | ~ROM_MASK[21])
)
: 1'b0));
assign IS_WRITABLE = IS_SAVERAM;
assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
:(MAPPER == 3'b001)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[14:0]}
& SAVERAM_MASK)
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK))
:(MAPPER == 3'b010)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
& ROM_MASK))
: 24'b0);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_SEL = 1'b0;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign obc1_enable = featurebits[FEAT_OBC1] & (~SNES_ADDR[22]) & (SNES_ADDR[15:11] == 5'b01111);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_TB_V
`define SKY130_FD_SC_LS__DFXTP_TB_V
/**
* dfxtp: Delay flop, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfxtp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__dfxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 3; int a[MAXN], b[MAXN], p[MAXN]; int read() { int x = 0, w = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) w = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + c - 48; c = getchar(); } return x * w; } int main() { int n = read(), ans = 0; for (int i = 1; i <= n; i++) a[i] = read(), p[a[i]] = 0; for (int i = 1; i <= n; i++) b[i] = read(), p[b[i]] = i; if (p[1]) { int i, j; for (i = 1; p[i] == p[1] + i - 1; i++) ; if (p[i - 1] == n) { for (j = i; j <= n && p[j] <= j - i; j++) ; if (j > n) { printf( %d n , n - i + 1); return 0; } } } for (int i = 1; i <= n; i++) ans = max(ans, p[i] - (i - 1) + n); printf( %d n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__FA_FUNCTIONAL_PP_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fa (
VPWR,
VGND,
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
input VPWR;
input VGND;
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Local signals
wire CIN or0_out ;
wire CIN and0_out ;
wire CIN and1_out ;
wire csi_opt_276, nor0_out ;
wire csi_opt_276, nor1_out ;
wire or1_out_COUT ;
wire u_vpwr_vgnd0_out_COUT;
wire and2_out ;
wire or2_out_SUM ;
wire u_vpwr_vgnd1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , u_vpwr_vgnd0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , u_vpwr_vgnd1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> const int maxn = 200005, K = 37, mod = 1e9 + 7; int add(int a, int b) { return a + b >= mod ? a + b - mod : a + b; } int dec(int a, int b) { return a - b < 0 ? a - b + mod : a - b; } int mul(int a, int b) { return 1ll * a * b % mod; } int ksm(int a, int b = mod - 2) { int ret = 1; for (; b; b >>= 1, a = mul(a, a)) if (b & 1) ret = mul(ret, a); return ret; } int n, a[maxn]; std::tuple<int, int, int> p[maxn]; int f[maxn], c[maxn], mx, ans; void ins(int x, int v) { for (; x <= mx; x += x & -x) c[x] = std::max(c[x], v); } int ask(int x) { int res = 0xcfcfcfcf; for (; x; x -= x & -x) res = std::max(res, c[x]); return res; } int main() { memset(c, 0xcf, sizeof(c)); memset(f, 0xcf, sizeof(f)); scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , a + i), p[i] = std::make_tuple(i - a[i], a[i], i), mx = std::max(mx, a[i]); mx++; std::sort(p + 1, p + 1 + n); ins(1, 0); for (int i = 1; i <= n; i++) { if (std::get<2>(p[i]) >= std::get<1>(p[i])) f[i] = ask(std::get<1>(p[i])) + 1; ins(std::get<1>(p[i]) + 1, f[i]); ans = std::max(ans, f[i]); } printf( %d n , ans); return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: info_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module info_fifo (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input [23:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [23:0] q;
output rdempty;
output wrfull;
wire [23:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [23:0] q = sub_wire0[23:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.aclr (),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone 10 LP",
dcfifo_component.lpm_numwords = 4,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 24,
dcfifo_component.lpm_widthu = 2,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "24"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "24"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "2"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL info_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL info_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL info_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL info_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL info_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL info_fifo_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long n, m, a[100005], tot = 0, tmp; int main() { ios_base::sync_with_stdio(NULL); cin.tie(0); cout.tie(0); cin >> n >> m; for (long long i = 1; i <= m; i++) { cin >> a[i]; if (i + a[i] - 1 > n) { cout << -1 << endl; return 0; } tot += a[i]; } if (tot < n) { cout << -1 << endl; return 0; } cout << 1; tot -= a[1]; n--; for (long long i = 2; i <= m; i++) { if (tot > n) { cout << << i; tot -= a[i]; n--; } else { cout << << i + n - tot; tmp = i + n - tot + a[i]; for (long long j = i + 1; j <= m; j++) { cout << << tmp; tmp += a[j]; } cout << endl; return 0; } } cout << endl; }
|
//=======================================================
// ECE3400 Fall 2017
// Lab 3: Template top-level module
//
// Top-level skeleton from Terasic
// Modified by Claire Chen for ECE3400 Fall 2017
//=======================================================
`define ONE_SEC 25000000
module DE0_NANO(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
GPIO_0_D,
GPIO_0_IN,
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
GPIO_1_D,
GPIO_1_IN,
);
//=======================================================
// PARAMETER declarations
//=======================================================
localparam ONE_SEC = 25000000; // one second in 25MHz clock cycles
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//output [7:0] q; //DAC
/////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [33:0] GPIO_0_D;
input [1:0] GPIO_0_IN;
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO_1_D;
input [1:0] GPIO_1_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg CLOCK_25;
wire reset; // active high reset signal
reg address; // sin table stuff
wire [9:0] PIXEL_COORD_X; // current x-coord from VGA driver
wire [9:0] PIXEL_COORD_Y; // current y-coord from VGA driver
wire [7:0] PIXEL_COLOR; // input 8-bit pixel color for current coords
reg [24:0] led_counter; // timer to keep track of when to toggle LED
reg [24:0] freq_counter;
reg led_state; // 1 is on, 0 is off
reg [2:0] freq_state;
reg [7:0] DAC; //DAC
// Module outputs coordinates of next pixel to be written onto screen
VGA_DRIVER driver(
.RESET(reset),
.CLOCK(CLOCK_25),
.PIXEL_COLOR_IN(PIXEL_COLOR),
.PIXEL_X(PIXEL_COORD_X),
.PIXEL_Y(PIXEL_COORD_Y),
.PIXEL_COLOR_OUT({GPIO_0_D[9],GPIO_0_D[11],GPIO_0_D[13],GPIO_0_D[15],GPIO_0_D[17],GPIO_0_D[19],GPIO_0_D[21],GPIO_0_D[23]}),
.H_SYNC_NEG(GPIO_0_D[12]),
.V_SYNC_NEG(GPIO_0_D[10])
);
sin_rom sin(
.addr(DAC),
.clk(CLOCK_25),
.q({GPIO_1_D[8],GPIO_1_D[10],GPIO_1_D[12],GPIO_1_D[14],GPIO_1_D[16],GPIO_1_D[18],GPIO_1_D[20],GPIO_1_D[22]})
);
assign reset = ~KEY[0]; // reset when KEY0 is pressed
assign PIXEL_COLOR = 8'b000_111_00; // Green
assign LED[0] = led_state;
//=======================================================
// Structural coding
//=======================================================
// Generate 25MHz clock for VGA, FPGA has 50 MHz clock
always @ (posedge CLOCK_50) begin
CLOCK_25 <= ~CLOCK_25;
end // always @ (posedge CLOCK_50)
// Simple state machine to toggle LED0 every one second
always @ (posedge CLOCK_25) begin
if (reset) begin
led_state <= 1'b0;
led_counter <= 25'b0;
end
if (led_counter == ONE_SEC) begin
led_state <= ~led_state;
led_counter <= 25'b0;
end
else begin
led_state <= led_state;
led_counter <= led_counter + 25'b1;
end // always @ (posedge CLOCK_25)
end
always @ (posedge CLOCK_25) begin
if (reset) begin
freq_state <= 2'b00;
freq_counter <= 25'b0;
end
if (freq_counter == ONE_SEC) begin
freq_counter <= 25'b0;
freq_state <= freq_state + 2'b1;
if (freq_state == 2'b11) begin
freq_state <= 2'b00;
end
end
else begin
freq_state <= freq_state;
freq_counter <= freq_counter + 25'b1;
end // always @ (posedge CLOCK_25)
end
// //localparam
// localparam CLKDIVIDER_440 = 25000000 / 440 / 2;
//
// //sound variables
// reg square_440;
// assign GPIO_0_D[1] = square_440;
// reg [15:0] counter;
//
// always @ (posedge CLOCK_25) begin
// if (counter == 0) begin
// counter <= CLKDIVIDER_440 - 1; //reset the clock
// square_440 <= ~square_440; //toggle the square pulse
// end
// else begin
// counter <= counter - 1;
// square_440 <= square_440;
// end
// end
localparam CLKDIVIDER_A_SIN = 25000000 / 400 / 256;
localparam CLKDIVIDER_B_SIN = 25000000 / 800 / 256;
localparam CLKDIVIDER_C_SIN = 25000000 / 600 / 256;
reg [15:0] counter;
always @ (posedge CLOCK_25) begin
if (counter == 0) begin
if (freq_state == 0) begin
counter <= CLKDIVIDER_A_SIN - 1;
end
if (freq_state == 1) begin
counter <= CLKDIVIDER_B_SIN - 1;
end
if (freq_state == 2) begin
counter <= CLKDIVIDER_C_SIN - 1;
end
if (DAC >= 255) begin
DAC <= 0;
end
else begin
DAC <= DAC + 1;
end
end
else begin
counter <= counter - 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool a[55][55], b[55][55], ans[55][55]; int n, m, ans_cnt; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> a[i][j]; for (int i = 1; i <= n - 1; i++) for (int j = 1; j <= m - 1; j++) if (a[i][j] && a[i + 1][j] && a[i][j + 1] && a[i + 1][j + 1]) { ans[i][j] = true; ans_cnt++; b[i][j] = b[i + 1][j] = b[i][j + 1] = b[i + 1][j + 1] = true; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (a[i][j] != b[i][j]) { cout << -1; return 0; } cout << ans_cnt << n ; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (ans[i][j]) cout << i << << j << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct edge { int v, w; edge* next; }; const int N = 100010; int n, p, ordcnt; bool vis[N], cut[N]; int ord[N], sum[N], mex[N], q[N], dep[N], digit[N], rdigit[N], rprod[N], prod[N]; edge* g[N]; void add_edge(int u, int v, int w); void calc_order(int u); void calc_sum(int u); void dfs(int u); long long calc(int u); int rev(int a); void ex_gcd(int a, int b, int& x, int& y); int main() { long long ans = 0; scanf( %d%d , &n, &p); for (int rep = 1; rep < n; ++rep) { int u, v, w; scanf( %d%d%d , &u, &v, &w); add_edge(u, v, w); add_edge(v, u, w); } prod[0] = 1; rprod[0] = 1; rprod[1] = rev(10); for (int i = 1; i <= n; ++i) prod[i] = 10LL * prod[i - 1] % p; for (int i = 2; i <= n; ++i) rprod[i] = (long long)rprod[1] * rprod[i - 1] % p; calc_order(0); memset(cut, 0, sizeof(cut)); for (int i = 0; i < n; ++i) { int u = ord[i]; dep[u] = 0; digit[u] = 0; rdigit[u] = 0; dfs(u); ans += calc(u); cut[u] = true; for (edge* p = g[u]; p; p = p->next) if (!cut[p->v]) ans -= calc(p->v); ans -= 1; ; } printf( %lld n , ans); return 0; } int rev(int a) { int x, y; ex_gcd(a, p, x, y); if (x < 0) x += p; return x; } void ex_gcd(int a, int b, int& x, int& y) { if (b == 0) { x = 1; y = 0; return; } ex_gcd(b, a % b, y, x); y -= a / b * x; } long long calc(int u) { int ql = 0, qr = 1; long long ret = 0; map<int, int> mp; q[0] = u; while (ql < qr) { int v = q[ql++]; vis[v] = true; map<int, int>::iterator it = mp.find(rdigit[v]); if (it != mp.end()) ++it->second; else mp.insert(make_pair(rdigit[v], 1)); for (edge* p = g[v]; p; p = p->next) if (!vis[p->v] && !cut[p->v]) q[qr++] = p->v; } for (int i = 0; i < qr; ++i) vis[q[i]] = false; for (int i = 0; i < qr; ++i) { int key = (long long)-digit[q[i]] * rprod[dep[q[i]]] % p; if (key < 0) key += p; map<int, int>::iterator it = mp.find(key); if (it != mp.end()) { ; ret += it->second; } } return ret; } void dfs(int u) { vis[u] = true; for (edge* p = g[u]; p; p = p->next) if (!vis[p->v] && !cut[p->v]) { dep[p->v] = dep[u] + 1; rdigit[p->v] = ((long long)prod[dep[u]] * p->w + rdigit[u]) % ::p; digit[p->v] = (digit[u] * 10LL + p->w) % ::p; dfs(p->v); } vis[u] = false; } void calc_order(int u) { calc_sum(u); int s = sum[u], ql = 0, qr = 1; q[0] = u; while (ql < qr) { int v = q[ql++]; vis[v] = true; mex[v] = max(mex[v], s - sum[v]); if (mex[v] < mex[u]) u = v; for (edge* p = g[v]; p; p = p->next) if (!vis[p->v] && !cut[p->v]) q[qr++] = p->v; } for (int i = 0; i < qr; ++i) vis[q[i]] = false; ord[ordcnt++] = u; cut[u] = true; for (edge* p = g[u]; p; p = p->next) if (!cut[p->v]) calc_order(p->v); } void calc_sum(int u) { vis[u] = true; mex[u] = 0; sum[u] = 1; for (edge* p = g[u]; p; p = p->next) if (!vis[p->v] && !cut[p->v]) { calc_sum(p->v); sum[u] += sum[p->v]; mex[u] = max(mex[u], sum[p->v]); } vis[u] = false; } void add_edge(int u, int v, int w) { static edge pool[N * 2]; static edge* p = pool; ++p; p->v = v; p->w = w; p->next = g[u]; g[u] = p; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:24:17 03/23/2016
// Design Name: sumcomp4s
// Module Name: C:/XilinxP/Practica2/sumcomp4s_test.v
// Project Name: Practica2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sumcomp4s
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
// Test para Sumador completo de 4 bits con signo, Practica 2
module sumcomp4s_test;
// Inputs
reg x0;
reg x1;
reg x2;
reg x3;
reg x4;
reg y0;
reg y1;
reg y2;
reg y3;
reg y4;
// Outputs
wire z0;
wire z1;
wire z2;
wire z3;
wire z4;
wire Co;
// Instantiate the Unit Under Test (UUT)
sumcomp4s uut (
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.x4(x4),
.y0(y0),
.y1(y1),
.y2(y2),
.y3(y3),
.y4(y4),
.z0(z0),
.z1(z1),
.z2(z2),
.z3(z3),
.z4(z4),
.Co(Co)
);
initial begin
// Initialize Inputs
x0 = 0;
x1 = 0;
x2 = 0;
x3 = 0;
x4 = 0;
y0 = 0;
y1 = 0;
y2 = 0;
y3 = 0;
y4 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
x0 = 1; x1 = 1; x2 = 0; x3 = 1; x4 = 0; y0 = 1; y1 = 0; y2 = 1; y3 = 0; y4 = 0;//11 + 5
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; x4 = 0; y0 = 1; y1 = 0; y2 = 1; y3 = 1; y4 = 0; //10 + 13
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 0; y0 = 0; y1 = 1; y2 = 1; y3 = 1; y4 = 0; //15 + 14
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 0; y0 = 1; y1 = 1; y2 = 1; y3 = 1; y4 = 0; //15 + 15
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 1; x1 = 1; x2 = 0; x3 = 1; x4 = 0; y0 = 1; y1 = 0; y2 = 1; y3 = 0; y4 = 1;//11 + -5
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; x4 = 0; y0 = 1; y1 = 0; y2 = 1; y3 = 1; y4 = 1; //10 + -13
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 0; y0 = 0; y1 = 1; y2 = 1; y3 = 1; y4 = 1; //15 + -14
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 0; y0 = 1; y1 = 1; y2 = 1; y3 = 1; y4 = 1; //15 + -15
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 0; x1 = 0; x2 = 0; x3 = 1; x4 = 1; y0 = 0; y1 = 0; y2 = 1; y3 = 0; y4 = 0; //-8 + 4
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; x4 = 1; y0 = 1; y1 = 0; y2 = 0; y3 = 0; y4 = 0; //-10 + 1
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 1; y0 = 0; y1 = 0; y2 = 0; y3 = 0; y4 = 0; //-15 + 0
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 0; x1 = 1; x2 = 1; x3 = 0; x4 = 1; y0 = 1; y1 = 0; y2 = 0; y3 = 1; y4 = 0; //-6 + 9
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 0; x1 = 0; x2 = 0; x3 = 1; x4 = 1; y0 = 0; y1 = 0; y2 = 1; y3 = 0; y4 = 1; //-8 + -4
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; x4 = 1; y0 = 1; y1 = 0; y2 = 0; y3 = 0; y4 = 1; //-10 + -1
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; x4 = 1; y0 = 0; y1 = 0; y2 = 0; y3 = 0; y4 = 1; //-15 + -0
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
x0 = 0; x1 = 1; x2 = 1; x3 = 0; x4 = 1; y0 = 1; y1 = 0; y2 = 0; y3 = 1; y4 = 1; //-6 + -9
#50;
$display("x = %b%b%b%b%b, y = %b%b%b%b%b, z = %b%b%b%b%b, c = %d", x4, x3, x2, x1, x0, y4, y3, y2, y1, y0, z4, z3, z2, z1, z0, Co);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long n, m, k, l; cin >> n >> m >> k >> l; if (((k + l + m - 1) / m) * m > n) { cout << -1; return 0; } cout << (k + l + m - 1) / m; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m1 = 0, m2 = 0; cin >> n; vector<vector<long long> > m(n, vector<long long>(n)); vector<int> a(n); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) cin >> m[i][j]; for (int i = 1; i < n - 1; i++) a[i] = sqrt(m[i][i + 1] * m[i - 1][i] / m[i - 1][i + 1]); a[0] = m[0][1] / a[1]; a[n - 1] = m[0][n - 1] / a[0]; for (int i = 0; i < n; i++) cout << a[i] << ; return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: log_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.0 Build 153 04/03/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module log_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
almost_full,
q);
input aclr;
input clock;
input [5:0] data;
input rdreq;
input wrreq;
output almost_empty;
output almost_full;
output [5:0] q;
wire sub_wire0;
wire sub_wire1;
wire [5:0] sub_wire2;
wire almost_empty = sub_wire0;
wire almost_full = sub_wire1;
wire [5:0] q = sub_wire2[5:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.almost_empty (sub_wire0),
.almost_full (sub_wire1),
.q (sub_wire2),
.empty (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_empty_value = 2,
scfifo_component.almost_full_value = 254,
scfifo_component.intended_device_family = "Cyclone V",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 6,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "2"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "254"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "6"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "6"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "2"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "254"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL "almost_empty"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 6 0 INPUT NODEFVAL "data[5..0]"
// Retrieval info: USED_PORT: q 0 0 6 0 OUTPUT NODEFVAL "q[5..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 6 0 data 0 0 6 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 6 0 @q 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL log_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL log_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL log_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL log_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL log_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL log_fifo_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1E5 + 5; long long m, n, k, alice[MAXN], bob[MAXN]; bool cmp(int x, int y) { return x > y; } int main() { cin >> n >> m >> k; for (int i = 0; i < n; i++) cin >> alice[i]; for (int i = 0; i < m; i++) cin >> bob[i]; if (n > m) { cout << YES << endl; return 0; } sort(alice, alice + n, cmp); sort(bob, bob + m, cmp); for (int i = 0; i < n; i++) { if (alice[i] > bob[i]) { cout << YES << endl; return 0; } } cout << NO << endl; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1005; int main() { int i, j; int n, pare[maxn], mark[maxn]; while (scanf( %d , &n) != EOF) { memset(pare, 0, sizeof(pare)); memset(mark, 0, sizeof(mark)); for (i = 2; i <= n; i++) { scanf( %d , &pare[i]); mark[pare[i]] = 1; } for (i = n; i >= 2; i--) if (mark[i] == 0) { mark[pare[i]]++; } for (i = 1; i <= n; i++) { if (mark[i] != 0 && mark[i] < 4) break; } if (i == (n + 1)) printf( YES n ); else printf( NO n ); } return 0; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; const int N = 100100; struct point { int id, val, sum; } a[N], b[N]; bool cmp(point x, point y) { return x.val > y.val; } int main() { int n, m; scanf( %d%d , &n, &m); int na = 0; int nb = 1; b[0].val = 0; for (int i = 1; i <= n; ++i) { int op; scanf( %d , &op); if (op == 1) { scanf( %d , &a[na].val); a[na++].id = i; } else { scanf( %d , &b[nb].val); b[nb++].id = i; } } sort(a, a + na, cmp); sort(b + 1, b + nb, cmp); for (int i = 0; i < na; ++i) { if (i == 0) a[i].sum = a[i].val; else a[i].sum = a[i - 1].sum + a[i].val; } int sum = 0; int ia = 0; int ib = 1; int ans = 0; for (int i = 0; i < nb && 2 * i <= m; ++i) { sum += b[i].val; int id = min(m - 2 * i - 1, na - 1); int tmp = sum; if (id >= 0) tmp += a[id].sum; if (tmp > ans) { ans = tmp; ia = id + 1; ib = i + 1; } } printf( %d n , ans); for (int i = 0; i < ia; ++i) printf( %d , a[i].id); for (int i = 1; i < ib; ++i) printf( %d , b[i].id); puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3010; const int M = 11; const int INF = 1 << 30; const double EPS = 1e-8; const int MOD = 1000000007LL; int n, tot[N]; vector<int> edge[N], edge2[N]; int dfs(int u, int fa) { int num = 0, sz; sz = edge[u].size(); for (int i = 0; i < sz; i++) { int v = edge[u][i]; if (v == fa) { continue; } num += dfs(v, u); } sz = edge2[u].size(); for (int i = 0; i < sz; i++) { int v = edge2[u][i]; if (v == fa) { continue; } num += dfs(v, u) + 1; } return num; } void init() { memset(tot, 0, sizeof(tot)); for (int i = 0; i < n; i++) { edge[i].clear(); edge2[i].clear(); } for (int i = 1; i < n; i++) { int u, v; scanf( %d %d , &u, &v); u--, v--; edge[u].push_back(v); edge2[v].push_back(u); } for (int u = 0; u < n; u++) { int sz; sz = edge[u].size(); for (int i = 0; i < sz; i++) { int v = edge[u][i]; int num = dfs(v, u); tot[u] += num; } sz = edge2[u].size(); for (int i = 0; i < sz; i++) { int v = edge2[u][i]; int num = dfs(v, u) + 1; tot[u] += num; } } } int dfs2(int u, int fa) { int sz, ret = tot[u]; sz = edge[u].size(); for (int i = 0; i < sz; i++) { int v = edge[u][i]; if (v == fa) { continue; } ret = min(ret, dfs2(v, u)); } sz = edge2[u].size(); for (int i = 0; i < sz; i++) { int v = edge2[u][i]; if (v == fa) { continue; } ret = min(ret, dfs2(v, u)); } return ret; } void solve() { int ans = INF; for (int i = 0; i < n; i++) { ans = min(ans, tot[i]); } for (int i = 0; i < n; i++) { vector<int> p; int sz; sz = edge[i].size(); for (int j = 0; j < sz; j++) { int v = edge[i][j]; p.push_back(dfs2(v, i)); } sz = edge2[i].size(); for (int j = 0; j < sz; j++) { int v = edge2[i][j]; p.push_back(dfs2(v, i)); } if (p.size() <= 1) { continue; } sort(p.begin(), p.end()); int tmp = p[0] + p[1] - tot[i]; ans = min(ans, tmp); } cout << ans << endl; } int main() { while (cin >> n) { init(); solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int k; vector<int> A; for (int i = 0; i < 4; ++i) { cin >> k; A.push_back(k); } sort(A.begin(), A.end()); if (A[0] + A[1] + A[2] == A[3] or A[0] + A[3] == A[1] + A[2]) { cout << YES ; } else { cout << NO ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, s[3010], c[3010], ans = 1e10; cin >> n; for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < n; i++) cin >> c[i]; for (int i = 0; i < n; i++) { long long min1 = 1e10, min2 = 1e10; for (int j = 0; j < i; j++) { if (s[j] < s[i]) min1 = min(min1, c[j]); } for (int j = i; j < n; j++) { if (s[j] > s[i]) min2 = min(min2, c[j]); } ans = min(ans, min1 + c[i] + min2); } if (ans >= 1e10) puts( -1 ); else cout << ans; return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_engine.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The tx_engine module takes a formatted header, number of alignment
// blanks and a payloa and concatenates all three (in that order) to form a
// packet. These packets must meet max-request, max-payload, and payload
// termination requirements (see Read Completion Boundary). The tx_engine does
// not check these requirements during operation, but may do so during simulation.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_engine
#(parameter C_DATA_WIDTH = 128,
parameter C_DEPTH_PACKETS = 10,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_FORMATTER_DELAY = 1,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: TX HDR
input TX_HDR_VALID,
input [C_MAX_HDR_WIDTH-1:0] TX_HDR,
input [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
input TX_HDR_NOPAYLOAD,
output TX_HDR_READY,
// Interface: TX_DATA
input TX_DATA_VALID,
input [C_DATA_WIDTH-1:0] TX_DATA,
input TX_DATA_START_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_START_OFFSET,
input TX_DATA_END_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_END_OFFSET,
output TX_DATA_READY,
// Interface: TX_PKT
input TX_PKT_READY,
output [C_DATA_WIDTH-1:0] TX_PKT,
output TX_PKT_START_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
output TX_PKT_END_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
output TX_PKT_VALID
);
localparam C_PIPELINE_HDR_FIFO_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_HDR_FIFO_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_PIPELINE_HDR_INPUT = C_PIPELINE_INPUT;
localparam C_ACTUAL_HDR_FIFO_DEPTH = clog2s(C_DEPTH_PACKETS);
localparam C_USE_COMPUTE_REG = 1;
localparam C_USE_READY_REG = 1;
localparam C_USE_FWFT_HDR_FIFO = 1;
localparam C_DATA_FIFO_DEPTH = C_ACTUAL_HDR_FIFO_DEPTH + C_FORMATTER_DELAY +
C_PIPELINE_HDR_FIFO_INPUT + C_PIPELINE_HDR_FIFO_OUTPUT + C_USE_FWFT_HDR_FIFO + // Header Fifo
C_PIPELINE_HDR_INPUT + C_USE_COMPUTE_REG + C_USE_READY_REG + C_PIPELINE_OUTPUT; // Aligner
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNoPayload;
wire wTxDataReady;
wire [C_DATA_WIDTH-1:0] wTxData;
wire [clog2s(C_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
wire wTxDataStartFlag;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordReady;
tx_data_pipeline
#(
.C_MAX_PAYLOAD (C_MAX_PAYLOAD_DWORDS*32),
.C_DEPTH_PACKETS (C_DATA_FIFO_DEPTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
tx_data_pipeline_inst
(
// Outputs
.RD_TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.RD_TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_START_FLAG (wTxDataStartFlag),
.RD_TX_DATA_END_FLAGS (wTxDataEndFlags[(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_READY (TX_DATA_READY),
// Inputs
.RD_TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA (TX_DATA),
.WR_TX_DATA_VALID (TX_DATA_VALID),
.WR_TX_DATA_START_FLAG (TX_DATA_START_FLAG),
.WR_TX_DATA_START_OFFSET (TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_END_FLAG (TX_DATA_END_FLAG),
.WR_TX_DATA_END_OFFSET (TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_hdr_fifo
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_HDR_FIFO_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_HDR_FIFO_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_ACTUAL_HDR_FIFO_DEPTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_VENDOR (C_VENDOR))
txhf_inst
(
// Outputs
.WR_TX_HDR_READY (TX_HDR_READY),
.RD_TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.RD_TX_HDR_VALID (wTxHdrValid),
.RD_TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.RD_TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.RD_TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.RD_TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.WR_TX_HDR (TX_HDR[C_MAX_HDR_WIDTH-1:0]),
.WR_TX_HDR_VALID (TX_HDR_VALID),
.WR_TX_HDR_NOPAYLOAD (TX_HDR_NOPAYLOAD),
.WR_TX_HDR_PAYLOAD_LEN (TX_HDR_PAYLOAD_LEN[`SIG_LEN_W-1:0]),
.WR_TX_HDR_NONPAY_LEN (TX_HDR_NONPAY_LEN[`SIG_NONPAY_W-1:0]),
.WR_TX_HDR_PACKET_LEN (TX_HDR_PACKET_LEN[`SIG_PACKETLEN_W-1:0]),
.RD_TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_alignment_pipeline
#(
// Parameters
.C_PIPELINE_OUTPUT (1),
.C_PIPELINE_DATA_INPUT (1),
.C_PIPELINE_HDR_INPUT (C_PIPELINE_HDR_INPUT),
.C_DATA_WIDTH (C_DATA_WIDTH),
// Parameters
/*AUTOINSTPARAM*/
// Parameters
.C_USE_COMPUTE_REG (C_USE_COMPUTE_REG),
.C_USE_READY_REG (C_USE_READY_REG),
.C_VENDOR (C_VENDOR))
tx_alignment_inst
(
// Outputs
.TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.TX_HDR_READY (wTxHdrReady),
.TX_PKT (TX_PKT[C_DATA_WIDTH-1:0]),
.TX_PKT_VALID (TX_PKT_VALID),
.TX_PKT_START_FLAG (TX_PKT_START_FLAG),
.TX_PKT_START_OFFSET (TX_PKT_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TX_PKT_END_FLAG),
.TX_PKT_END_OFFSET (TX_PKT_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
// Inputs
.TX_DATA_START_FLAG (wTxDataStartFlag),
.TX_DATA_END_FLAGS (wTxDataEndFlags),
.TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_PKT_READY (TX_PKT_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_TB_V
`define SKY130_FD_SC_HVL__SDLXTP_TB_V
/**
* sdlxtp: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdlxtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hvl__sdlxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_p4.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
//
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cpx_buf_p4(/*AUTOARG*/
// Outputs
scache3_cpx_req_bufp4_cq, scache3_cpx_atom_bufp4_cq,
io_cpx_req_bufp4_cq, cpx_scache3_grant_bufp4_ca,
cpx_spc7_data_rdy_bufp4_cx,
// Inputs
scache3_cpx_req_bufpt_cq_l, scache3_cpx_atom_bufpt_cq_l,
io_cpx_req_bufpt_cq_l, cpx_scache3_grant_bufp3_ca_l,
cpx_spc7_data_rdy_bufp3_cx
);
output [7:0] scache3_cpx_req_bufp4_cq;
output scache3_cpx_atom_bufp4_cq;
output [7:0] io_cpx_req_bufp4_cq;
output [7:0] cpx_scache3_grant_bufp4_ca;
output cpx_spc7_data_rdy_bufp4_cx;
input [7:0] scache3_cpx_req_bufpt_cq_l;
input scache3_cpx_atom_bufpt_cq_l;
input [7:0] io_cpx_req_bufpt_cq_l;
input [7:0] cpx_scache3_grant_bufp3_ca_l;
input cpx_spc7_data_rdy_bufp3_cx;
assign scache3_cpx_req_bufp4_cq[7:0] = ~scache3_cpx_req_bufpt_cq_l[7:0];
assign scache3_cpx_atom_bufp4_cq = ~scache3_cpx_atom_bufpt_cq_l;
assign io_cpx_req_bufp4_cq[7:0] = ~io_cpx_req_bufpt_cq_l[7:0];
assign cpx_scache3_grant_bufp4_ca = ~cpx_scache3_grant_bufp3_ca_l;
assign cpx_spc7_data_rdy_bufp4_cx = cpx_spc7_data_rdy_bufp3_cx;
endmodule
|
// -----------------------------------------------------------------------
//
// Copyright 2004,2007 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
//
// Main module
/*
4000_0000 - 400F_FFFF Extern SRAM (1 MiB)
BFC0_0000 - BFC0_3FFF Boot ROM (16 KiB) (Preloaded I$ cache)
FF00_0000 - FF00_1FFF Peripherals
Read Write
0 rs232out busy rs232out data
1 rs232in data
2 rs232in count
3 TSC
*/
`timescale 1ns/10ps
`include "../../soclib/pipeconnect.h"
module main(
input wire clk,
//
// serial interface
//
output wire ser_txd,
input wire ser_rxd,
input wire ser_ncts,
output wire ser_nrts,
//
// watchdog
//
output wire wd,
//
// two ram banks
//
output wire [17:0] rama_a,
inout wire [15:0] rama_d,
output wire rama_ncs,
output wire rama_noe,
output wire rama_nlb,
output wire rama_nub,
output wire rama_nwe,
output wire [17:0] ramb_a,
inout wire [15:0] ramb_d,
output wire ramb_ncs,
output wire ramb_noe,
output wire ramb_nlb,
output wire ramb_nub,
output wire ramb_nwe);
wire clock;
pll pll(.inclk0(clk), // 20 MHz on Cycore
.c0(clock)); // xx MHz output
assign wd = rst_counter[22];
reg [26:0] rst_counter = 0;
always @(posedge clock)
// if (~USER_PB[0])
// rst_counter <= 'd48_000_000;
// else if (~rst_counter[26])
if (~rst_counter[26])
rst_counter <= rst_counter - 1;
wire rst = ~rst_counter[26];
assign ramb_a = rama_a;
assign ramb_ncs = rama_ncs;
assign ramb_noe = rama_noe;
assign ramb_nwe = rama_nwe;
parameter FREQ = 80_000_000; // match clock frequency
parameter BPS = 115_200; // Serial speed
wire [ 7:0] rs232out_d;
wire rs232out_w;
wire rs232out_busy;
wire [ 7:0] rs232in_data;
wire rs232in_attention;
wire mem_waitrequest;
wire [1:0] mem_id;
wire [29:0] mem_address;
wire mem_read;
wire mem_write;
wire [31:0] mem_writedata;
wire [3:0] mem_writedatamask;
wire [31:0] mem_readdata;
wire [1:0] mem_readdataid;
wire `REQ rs232_req;
wire `RES rs232_res;
yari yari_inst(
.clock(clock)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.peripherals_req(rs232_req)
,.peripherals_res(rs232_res)
);
sram_ctrl sram_ctrl
(.clock(clock)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.sram_a(rama_a)
,.sram_d({rama_d,ramb_d})
,.sram_cs_n(rama_ncs)
,.sram_be_n({rama_nub,rama_nlb,ramb_nub,ramb_nlb})
,.sram_oe_n(rama_noe)
,.sram_we_n(rama_nwe)
);
defparam sram_ctrl.need_wait = 1;
rs232out rs232out_inst
(.clock(clock),
.serial_out(ser_txd),
.transmit_data(rs232out_d),
.we(rs232out_w),
.busy(rs232out_busy));
defparam rs232out_inst.frequency = FREQ,
rs232out_inst.bps = BPS;
rs232in rs232in_inst
(.clock(clock),
.serial_in(ser_rxd),
.received_data(rs232in_data),
.attention(rs232in_attention));
defparam rs232in_inst.frequency = FREQ,
rs232in_inst.bps = BPS;
rs232 rs232_inst(.clk(clock),
.rst(rst),
.rs232_req(rs232_req),
.rs232_res(rs232_res),
.rs232in_attention(rs232in_attention),
.rs232in_data(rs232in_data),
.rs232out_busy(rs232out_busy),
.rs232out_w(rs232out_w),
.rs232out_d(rs232out_d));
endmodule
|
//
// fixed for 9.1 jan 21 2010 cruben
//
//`include "timescale.v"
`include "i2c_master_defines.v"
module i2c_opencores
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
scl_pad_io, sda_pad_io
);
// Common bus signals
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
// Slave signals
input [2:0] wb_adr_i; // WISHBONE address input
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
input wb_we_i; // WISHBONE write enable input
input wb_stb_i; // WISHBONE strobe input
//input wb_cyc_i; // WISHBONE cycle input
output wb_ack_o; // WISHBONE acknowledge output
output wb_inta_o; // WISHBONE interrupt output
// I2C signals
inout scl_pad_io; // I2C clock io
inout sda_pad_io; // I2C data io
wire wb_cyc_i; // WISHBONE cycle input
// Wire tri-state scl/sda
wire scl_pad_i;
wire scl_pad_o;
wire scl_pad_io;
wire scl_padoen_o;
assign wb_cyc_i = wb_stb_i;
assign scl_pad_i = scl_pad_io;
assign scl_pad_io = scl_padoen_o ? 1'bZ : scl_pad_o;
wire sda_pad_i;
wire sda_pad_o;
wire sda_pad_io;
wire sda_padoen_o;
assign sda_pad_i = sda_pad_io;
assign sda_pad_io = sda_padoen_o ? 1'bZ : sda_pad_o;
// Avalon doesn't have an asynchronous reset
// set it to be inactive and just use synchronous reset
// reset level is a parameter, 0 is the default (active-low reset)
wire arst_i;
assign arst_i = 1'b1;
// Connect the top level I2C core
i2c_master_top i2c_master_top_inst
(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; char grid[55][55]; char vis[55][55]; int di[] = {0, 1, -1, 0}; int dj[] = {1, 0, 0, -1}; bool dfs(int pi, int pj, char c, int li = -1, int lj = -1) { if (vis[pi][pj]) return true; vis[pi][pj] = true; for (int d = 0; d < 4; d++) { int ni = pi + di[d]; int nj = pj + dj[d]; if (ni == li && nj == lj) continue; if (ni < 0 || ni >= n || nj < 0 || nj >= m) continue; if (grid[ni][nj] != c) continue; if (dfs(ni, nj, c, pi, pj)) return true; } return false; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> grid[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (vis[i][j] == false) { if (dfs(i, j, grid[i][j])) { cout << Yes << endl; return 0; } } } } cout << No << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD1_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD1_FUNCTIONAL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD1_FUNCTIONAL_V
|
/*
File: eio_tx.v
This file is part of the Parallella Project .
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module eio_tx (/*AUTOARG*/
// Outputs
TX_LCLK_P, TX_LCLK_N, TX_FRAME_P, TX_FRAME_N, TX_DATA_P, TX_DATA_N,
tx_wr_wait, tx_rd_wait,
// Inputs
reset, ioreset, TX_WR_WAIT_P, TX_WR_WAIT_N, TX_RD_WAIT_P,
TX_RD_WAIT_N, txlclk_p, txlclk_s, txlclk_out, txframe_p, txdata_p,
ecfg_tx_enable, ecfg_tx_gpio_mode, ecfg_tx_clkdiv, ecfg_dataout
);
parameter IOSTD_ELINK = "LVDS_25";
//###########
//# eLink pins
//###########
output TX_LCLK_P, TX_LCLK_N; // Differential clock from PLL to eLink
input reset;
input ioreset;
output TX_FRAME_P, TX_FRAME_N; // Outputs to eLink
output [7:0] TX_DATA_P, TX_DATA_N;
input TX_WR_WAIT_P, TX_WR_WAIT_N;
input TX_RD_WAIT_P, TX_RD_WAIT_N;
//#############
//# Fabric interface, 1/8 bit rate of eLink
//#############
input txlclk_p; // Parallel clock in (bit rate / 8)
input txlclk_s; // Serial clock in (bit rate / 2)
input txlclk_out; // "LCLK" source in, 90deg from lclk_s
input [7:0] txframe_p;
input [63:0] txdata_p;
output tx_wr_wait;
output tx_rd_wait;
//#############
//# Configuration bits
//#############
input ecfg_tx_enable; //enable signal for rx
input ecfg_tx_gpio_mode; //forces rx wait pins to constants
input [3:0] ecfg_tx_clkdiv; // TODO: Implement this
input [10:0] ecfg_dataout; // frame & data for GPIO mode
//############
//# REGS
//############
//############
//# WIRES
//############
wire [7:0] tx_data; // High-speed serial data outputs
wire [7:0] tx_data_t; // Tristate signal to OBUF's
wire tx_frame; // serial frame signal
wire tx_lclk;
//#############################
//# Serializer instantiations
//#############################
reg [63:0] pdata;
reg [7:0] pframe;
reg [1:0] txenb_sync;
wire txenb = txenb_sync[0];
reg [1:0] txgpio_sync;
wire txgpio = txgpio_sync[0];
integer n;
// Sync these control bits into our domain
always @ (posedge txlclk_p) begin
txenb_sync <= {ecfg_tx_enable, txenb_sync[1]};
txgpio_sync <= {ecfg_tx_gpio_mode, txgpio_sync[1]};
if(txgpio) begin
pframe <= {8{ecfg_dataout[8]}};
for(n=0; n<8; n=n+1)
pdata[n*8+7 -: 8] <= ecfg_dataout[7:0];
end else if(txenb) begin
pframe <= txframe_p;
pdata <= txdata_p;
end else begin
pframe <= 8'd0;
pdata <= 64'd0;
end // else: !if(txgpio)
end // always @ (posedge txlclk_p)
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_serdes
OSERDESE2
#(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("BUF"), // DDR, BUF, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b1), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b1), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
) OSERDESE2_txdata
(
.OFB(), // 1-bit output: Feedback path for data
.OQ(tx_data[i]), // 1-bit output: Data path output
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(tx_data_t[i]), // 1-bit output: 3-state control
.CLK(txlclk_s), // 1-bit input: High speed clock
.CLKDIV(txlclk_p), // 1-bit input: Divided clock
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(pdata[i+56]), // First data out
.D2(pdata[i+48]),
.D3(pdata[i+40]),
.D4(pdata[i+32]),
.D5(pdata[i+24]),
.D6(pdata[i+16]),
.D7(pdata[i+8]),
.D8(pdata[i]), // Last data out
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(ioreset), // 1-bit input: Reset
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(~ecfg_tx_enable),
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b1) // 1-bit input: 3-state clock enable
);
end // block: gen_serdes
endgenerate
OSERDESE2
#(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("SDR"), // DDR, BUF, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(1) // 3-state converter width (1,4)
) OSERDESE2_tframe
(
.OFB(), // 1-bit output: Feedback path for data
.OQ(tx_frame), // 1-bit output: Data path output
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
.SHIFTOUT1(),
.SHIFTOUT2(),
.TBYTEOUT(), // 1-bit output: Byte group tristate
.TFB(), // 1-bit output: 3-state control
.TQ(), // 1-bit output: 3-state control
.CLK(txlclk_s), // 1-bit input: High speed clock
.CLKDIV(txlclk_p), // 1-bit input: Divided clock
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(pframe[7]), // first data out
.D2(pframe[6]),
.D3(pframe[5]),
.D4(pframe[4]),
.D5(pframe[3]),
.D6(pframe[2]),
.D7(pframe[1]),
.D8(pframe[0]), // last data out
.OCE(1'b1), // 1-bit input: Output data clock enable
.RST(ioreset), // 1-bit input: Reset
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(1'b0),
.T2(1'b0),
.T3(1'b0),
.T4(1'b0),
.TBYTEIN(1'b0), // 1-bit input: Byte group tristate
.TCE(1'b0) // 1-bit input: 3-state clock enable
);
//################################
//# LClock Creation
//################################
reg [1:0] txenb_out_sync;
wire txenb_out = txenb_out_sync[0];
// sync the enable signal to the phase-shifted output clock
always @ (posedge txlclk_out)
txenb_out_sync <= {ecfg_tx_enable, txenb_out_sync[1]};
ODDR
#(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_lclk_inst
(
.Q (tx_lclk),
.C (txlclk_out),
.CE (1'b1),
.D1 (txenb_out),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
//################################
//# Output Buffers
//################################
OBUFTDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFTDS_txdata [7:0]
(
.O (TX_DATA_P),
.OB (TX_DATA_N),
.I (tx_data),
.T (tx_data_t)
);
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFDS_txframe
(
.O (TX_FRAME_P),
.OB (TX_FRAME_N),
.I (tx_frame)
);
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("FAST")
) OBUFDS_lclk
(
.O (TX_LCLK_P),
.OB (TX_LCLK_N),
.I (tx_lclk)
);
//################################
//# Wait Input Buffers
//################################
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_txwrwait
(.I (TX_WR_WAIT_P),
.IB (TX_WR_WAIT_N),
.O (tx_wr_wait));
// On Parallella this signal comes in single-ended
assign tx_rd_wait = TX_RD_WAIT_P;
endmodule // eio_rx
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__EINVP_PP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long double PI = acosl(-1.0); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m; cin >> n >> m; int a[n][m], ans[n][m]; for (long long i = 0; i < n; i++) for (long long j = 0; j < m; j++) cin >> a[i][j]; vector<map<int, int> > vc1, vc2; map<int, int> mymap; vector<int> v1, v11, v22; for (int i = 0; i < n; i++) { mymap.clear(); v1.clear(); for (int j = 0; j < m; j++) v1.push_back(a[i][j]); sort(v1.begin(), v1.end()); int k = 1; for (int j = 0; j < m; j++) { if (mymap.find(v1[j]) == mymap.end()) mymap[v1[j]] = k++; } v11.push_back(k - 1); vc1.push_back(mymap); } for (int i = 0; i < m; i++) { mymap.clear(); v1.clear(); for (int j = 0; j < n; j++) v1.push_back(a[j][i]); sort(v1.begin(), v1.end()); int k = 1; for (int j = 0; j < n; j++) { if (mymap.find(v1[j]) == mymap.end()) mymap[v1[j]] = k++; } v22.push_back(k - 1); vc2.push_back(mymap); } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int x = vc1[i][a[i][j]]; int y = vc2[j][a[i][j]]; if (x < y) ans[i][j] = max(v11[i] + y - x, v22[j]); else if (y < x) ans[i][j] = max(v11[i], v22[j] + x - y); else ans[i][j] = max(v11[i], v22[j]); } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << ans[i][j] << ; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1e9 + 7; long long int inf = 1e9 + 7; void solve() { long long int n, m; cin >> n >> m; vector<vector<long long int> > v(n, vector<long long int>(m)); long long int i, j; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cin >> v[i][j]; } } vector<long long int> ans(n, -1); for (i = 0; i < n; i++) { ans[i] = i; } for (i = 0; i < m; i++) { long long int mx = 0; for (j = 1; j < n; j++) { if (v[j][i] >= v[j - 1][i]) { ans[j] = min(ans[j], mx); } else { mx = j; ans[j] = min(ans[j], mx); } } } long long int q; cin >> q; while (q--) { long long int l, r; cin >> l >> r; l--; r--; if (l >= ans[r]) { cout << Yes << endl; } else { cout << No << endl; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t = 1; while (t--) { solve(); } }
|
/*
module for a simple PWM generator stage
*/
module pwm_output_stage (clk, reset, sel, adr, data, pwm_out);
parameter REG_WIDTH = 32; //width of internal registers and counter, determines min frequency
parameter ADR_FREQ = 2'b00; //the different register adresses
parameter ADR_ON = 2'b01;
parameter ADR_COUNTER = 2'b10;
input clk;
input reset;
input sel;
input [1:0] adr;
input [REG_WIDTH-1:0] data;
output pwm_out;
reg [REG_WIDTH-1:0] cycle;
reg [REG_WIDTH-1:0] on_time;
reg [REG_WIDTH-1:0] counter;
assign pwm_out = (counter < on_time);
always @(posedge clk) begin
if (reset) begin
cycle <= {(REG_WIDTH){1'b0}}; //initialize period with 0
on_time <= {(REG_WIDTH){1'b0}}; //initialize on_time with 0 -> output disabled
counter <= {(REG_WIDTH){1'b0}}; //reset counter to 0
end else begin
if (sel) begin
case (adr) //store data to register addressed with "adr" line
ADR_FREQ: cycle <= data;
ADR_ON: on_time <= data;
ADR_COUNTER: counter <= data;
endcase
end
if (!(sel && adr[1])) begin //no write action to counter register
if (counter == cycle)
counter <= {(REG_WIDTH){1'b0}}; //reset counter if max value reached
else
counter <= counter + 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> const long long N = 5e5 + 5; const int MOD = 1e9 + 7; using namespace std; int n; int a[N]; long long b[N], c[N]; multiset<long long> s; void xuly() { cin >> n; for (int i = (1); i <= (n); ++i) cin >> a[i]; sort(a + 1, a + 1 + n); cout << (n - 1) / 2 << n ; int top2 = n, top1 = 1; for (int i = (1); i <= (n); ++i) { if (i & 1) cout << a[top2--] << ; else cout << a[top1++] << ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); xuly(); }
|
#include <bits/stdc++.h> using namespace std; int a[100010], dp[100010], rec[100010]; int n; int main() { while (~scanf( %d , &n)) { int maxn = 0; for (int i = 1; i <= n; i++) { dp[i] = 1; scanf( %d , &a[i]); } for (int i = 1; i <= n; i++) { rec[a[i]] = 1; if (rec[a[i] - 1] > 0) { dp[a[i]] = dp[a[i] - 1] + 1; } maxn = max(maxn, dp[a[i]]); } printf( %d n , n - maxn); } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:08:40 11/19/2015
// Design Name:
// Module Name: EX_MEM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module EX_MEM(
input clock,
input reset,
input[4:0] writeRegister,
input[31:0] writeData,
input[31:0] aluOut,
input regWrite,
input memToReg,
input [3:0]memWrite,
input [1:0] memReadWidth,
output reg[4:0] writeRegisterOut,
output reg[31:0] writeDataOut,
output reg[31:0] aluOutOut,
output reg regWriteOut,
output reg memToRegOut,
output reg [3:0]memWriteOut,
output reg [1:0] memReadWidthOut
);
always @(negedge clock,posedge reset)begin
if(reset)begin
writeRegisterOut<=0;
writeDataOut<=0;
aluOutOut<=0;
regWriteOut<=0;
memToRegOut<=0;
memWriteOut<=0;
memReadWidthOut<=0;
end
else begin
writeRegisterOut<=writeRegister;
writeDataOut<=writeData;
aluOutOut<=aluOut;
regWriteOut<=regWrite;
memToRegOut<=memToReg;
memWriteOut<=memWrite;
memReadWidthOut<=memReadWidth;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[211111]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } long long l = 0; long long r = 0; long long suml = 0; long long sumr = 0; for (int i = 0; i < n; i++) { if (a[i] == 1) { r++; } if (a[i] == 0) { suml += r; } } for (int i = n - 1; i >= 0; i--) { if (a[i] == 0) { l++; } if (a[i] == 1) { sumr += l; } } cout << min(sumr, suml); return 0; }
|
module Timer(clk_i, signal_i, second_o);
input clk_i;
input [2:0] signal_i;
output [31:0] second_o;
reg [31:0] counter;
reg [1:0] state;
reg [31:0] second;
assign second_o = second;
`define SSTOP 2'b00
`define SSTART 2'b01
`define SPAUSE 2'b10
initial begin
state = `SSTOP;
counter = 0;
second = 0;
end
`define K0 3'b100
`define K1 3'b101
`define K2 3'b110
`define K3 3'b111
// `define CLKRATE 32'd500000
`define CLKRATE 32'd25000
always@(negedge clk_i) begin
case (state)
`SSTOP: begin
case (signal_i)
`K3: begin
state <= `SSTART;
end
endcase
end
`SSTART: begin
if (counter == `CLKRATE) begin
counter <= 1;
second <= second + 1;
end else begin
counter <= counter + 1;
end
case (signal_i)
`K1: begin
state <= `SSTOP;
counter <= 0;
second <= 0;
end
`K3: begin
state <= `SPAUSE;
end
endcase
end
`SPAUSE: begin
case (signal_i)
`K1: begin
state <= `SSTOP;
counter <= 0;
second <= 0;
end
`K3: begin
state <= `SSTART;
end
endcase
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_SYMBOL_V
`define SKY130_FD_SC_MS__A311O_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a311o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j, k, l, m, t; vector<int> a[10001]; cin >> n; for (i = 1; i < n; i++) { cin >> m >> t; a[m].push_back(t); a[t].push_back(m); } l = 0; m = 0; int b[30001], c[30001]; for (t = 1; t <= n; t++) { j = 0; for (i = 0; i < a[t].size(); i++) { j++; b[j] = a[t][i]; } l = 0; for (i = 1; i <= a[t].size(); i++) { for (j = 0; j < a[b[i]].size(); j++) { l++; c[l] = a[b[i]][j]; } } for (i = 1; i <= l; i++) if (c[i] > t) m++; } cout << m << endl; }
|
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