text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; vector<int> mat[100010]; int vis[100010], val[100010]; int dfs(int p, int pa) { if (vis[p]) return 1; int ret = 0; vis[p] = 1; if (p != pa) val[p] += val[pa]; for (auto x : mat[p]) ret = max(ret, dfs(x, p)); return ret; } int in[100010], out[100010], n, dp[302][100002][2]; int rec(int p, int r, int t) { if (p == n + 1) return (r == 0); if (r < 0) return 0; int &temp = dp[p][r][t]; if (temp != -1) return temp; temp = 0; if (!out[p] || t) temp += rec(p + 1, r, 0); if (temp > 1000000007) temp -= 1000000007; temp += rec(p, r - val[p], 1); if (temp > 1000000007) temp -= 1000000007; return temp; } int main() { ios::sync_with_stdio(0); int q, t, u, v; cin >> n >> q >> t; for (int i = 1; i <= n; i++) cin >> val[i]; for (int i = 0; i <= q - 1; i++) { cin >> u >> v; mat[u].push_back(v); in[v]++; out[u]++; } int chao = 0; for (int i = 1; i <= n; i++) if (!vis[i] && !in[i]) chao = max(chao, dfs(i, i)); for (int i = 1; i <= n; i++) if (!vis[i]) chao = 1; memset(dp, -1, sizeof(dp)); if (chao) cout << 0 << endl; else cout << rec(1, t, 0) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[610000], i, j, k, l, n, m, p[610000], t, last, o, r, mid; char c[610000]; bool check(int mid) { int tmp = 1e9, res = 0; p[0] = mid; m = last; for (i = 1; i <= n; ++i) { p[i] = p[i - 1] + a[i]; if (p[i] == 0 && p[i - 1] == -1) m = max(m, i); } if (m == 0) return 1; for (i = 1; i <= m; ++i) { if (p[i - 1] == 0 && p[i] == -1) { o = i; tmp = min(tmp, res + (m - i) * 2); } if (p[i - 1] == -1 && p[i] == 0) { if (i == m) tmp = min(tmp, res + m - o); res += (i - o) * 2; } res++; } tmp = min(tmp, res - 1); return tmp + 1 <= t; } int main() { scanf( %d%d%s , &n, &t, c + 1); for (i = 1; i <= n; ++i) a[i] = c[i] == H ? -1 : c[i] == S ? 1 : 0; for (i = 1; i <= n; ++i) { if (a[i] == -1) r++, last = i; if (a[i] == 1) l--; } l += r; if (l < 0) l = 0; if (last > t) { printf( -1 n ); exit(0); } while (l <= r) { mid = (l + r) / 2; if (check(mid)) r = mid - 1; else l = mid + 1; } printf( %d n , r + 1); }
|
#include <bits/stdc++.h> using namespace std; bool func(vector<pair<int, int> > vd, vector<pair<int, int> > vu) { for (int i = 0; i < vd.size(); i++) { if ((vd[i].first < vu[i].first && vd[i].second < vu[i].second) || (vd[i].first > vu[i].first && vd[i].second > vu[i].second)) { return true; } } return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t, i, j, k, n, m, a = 1, b = 1, c, p, prev, q, r, width, o, rc, height, mx = -999999999, mn = 99999999, ct = 0, ans = 0, flag = 1, sum = 0, pos1, pos2; cin >> n >> m >> k; std::vector<pair<long long int, long long int> > row(n), col(m); for (i = 1; i <= k; i++) { cin >> o >> rc >> a; if (o == 1) { row[rc - 1] = {a, i}; } else { col[rc - 1] = {a, i}; } } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (col[j].second > row[i].second) cout << col[j].first << ; else cout << row[i].first << ; } cout << n ; } return 0; }
|
//-----------------------------------------------------------------------------
// Jonathan Westhues, March 2006
// iZsh <izsh at fail0verflow.com>, June 2014
// Piwi, Feb 2019
// Anon, 2019
//-----------------------------------------------------------------------------
// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
// Note: the definitions here are without shifts
// Commands:
`define FPGA_CMD_SET_CONFREG 1
`define FPGA_CMD_SET_DIVISOR 2
`define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD 3
// Major modes:
`define FPGA_MAJOR_MODE_LF_READER 0
`define FPGA_MAJOR_MODE_LF_EDGE_DETECT 1
`define FPGA_MAJOR_MODE_LF_PASSTHRU 2
`define FPGA_MAJOR_MODE_LF_ADC 3
// Options for LF_READER
`define FPGA_LF_ADC_READER_FIELD 1
// Options for LF_EDGE_DETECT
`define FPGA_LF_EDGE_DETECT_READER_FIELD 1
`define FPGA_LF_EDGE_DETECT_TOGGLE_MODE 2
`include "lo_read.v"
`include "lo_passthru.v"
`include "lo_edge_detect.v"
`include "lo_adc.v"
`include "util.v"
`include "clk_divider.v"
module fpga_lf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
/*
Attempt to write up how its hooked up. Iceman 2020.
Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
Send 16 bit command / data pair to FPGA
The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
where
C is 4bit command
D is 12bit data
shift_reg receive this 16bit frame
LF command
----------
shift_reg[15:12] == 4bit command
LF has three commands (FPGA_CMD_SET_CONFREG, FPGA_CMD_SET_DIVISOR, FPGA_CMD_SET_EDGE_DETECT_THRESHOLD)
Current commands uses only 2bits. We have room for up to 4bits of commands total (7).
LF data
-------
shift_reg[11:0] == 12bit data
lf data is divided into MAJOR MODES and configuration values.
The major modes uses 3bits (0,1,2,3,7 | 000, 001, 010, 011, 111)
000 FPGA_MAJOR_MODE_LF_READER = Act as LF reader (modulate)
001 FPGA_MAJOR_MODE_LF_EDGE_DETECT = Simulate LF
010 FPGA_MAJOR_MODE_LF_PASSTHRU = Passthrough mode, CROSS_LO line connected to SSP_DIN. SSP_DOUT logic level controls if we modulate / listening
011 FPGA_MAJOR_MODE_LF_ADC = refactor hitag2, clear ADC sampling
111 FPGA_MAJOR_MODE_OFF = turn off sampling.
Each one of this major modes can have options. Currently these two major modes uses options.
- FPGA_MAJOR_MODE_LF_READER
- FPGA_MAJOR_MODE_LF_EDGE_DETECT
FPGA_MAJOR_MODE_LF_READER
-------------------------------------
lf_field = 1bit (FPGA_LF_ADC_READER_FIELD)
You can send FPGA_CMD_SET_DIVISOR to set with FREQUENCY the fpga should sample at
divisor = 8bits shift_reg[7:0]
FPGA_MAJOR_MODE_LF_EDGE_DETECT
------------------------------------------
lf_ed_toggle_mode = 1bits
lf_ed_threshold = 8bits threshold defaults to 127
You can send FPGA_CMD_SET_EDGE_DETECT_THRESHOLD to set a custom threshold
lf_ed_threshold = 8bits threshold value.
conf_word 12bits
conf_word[8:6] = 3bit major mode.
conf_word[0] = 1bit lf_field
conf_word[1] = 1bit lf_ed_toggle_mode
conf_word[7:0] = 8bit divisor
conf_word[7:0] = 8bit threshold
-----+--------- frame layout --------------------
bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-----+-------------------------------------------
cmd | x x x x
major| x x x
opt | x x
divi | x x x x x x x x
thres| x x x x x x x x
-----+-------------------------------------------
*/
reg [15:0] shift_reg;
reg [7:0] divisor;
reg [7:0] lf_ed_threshold;
reg [11:0] conf_word;
wire [2:0] major_mode = conf_word[8:6];
wire lf_field = conf_word[0];
wire lf_ed_toggle_mode = conf_word[1];
// Handles cmd / data frame from ARM
always @(posedge ncs)
begin
// 4 bit command
case (shift_reg[15:12])
`FPGA_CMD_SET_CONFREG:
begin
// 12 bit data
conf_word <= shift_reg[11:0];
if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT)
begin
lf_ed_threshold <= 127; // default threshold
end
end
`FPGA_CMD_SET_DIVISOR:
divisor <= shift_reg[7:0]; // 8bits
`FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
lf_ed_threshold <= shift_reg[7:0]; // 8 bits
endcase
end
// Receive 16bits of data from ARM here.
always @(posedge spck)
begin
if (~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
wire [7:0] pck_cnt;
wire pck_divclk;
clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
lo_read lr(
pck0, pck_cnt, pck_divclk,
lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
adc_d, lr_adc_clk,
lr_ssp_frame, lr_ssp_din, lr_ssp_clk,
lr_dbg, lf_field
);
lo_passthru lp(
pck_divclk,
lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
lp_adc_clk,
lp_ssp_din, ssp_dout,
cross_lo,
lp_dbg
);
lo_edge_detect le(
pck0, pck_divclk,
le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
adc_d, le_adc_clk,
le_ssp_frame, ssp_dout, le_ssp_clk,
cross_lo,
le_dbg,
lf_field,
lf_ed_toggle_mode, lf_ed_threshold
);
lo_adc la(
pck0,
la_pwr_lo, la_pwr_hi, la_pwr_oe1, la_pwr_oe2, la_pwr_oe3, la_pwr_oe4,
adc_d, la_adc_clk,
la_ssp_frame, la_ssp_din, ssp_dout, la_ssp_clk,
la_dbg, divisor,
lf_field
);
// Major modes:
// 000 -- LF reader (generic)
// 001 -- LF edge detect (generic)
// 010 -- LF passthrough
// 011 -- LF ADC (read/write)
// 100 -- unused
// 101 -- unused
// 110 -- unused
// 111 -- FPGA_MAJOR_MODE_OFF
// 000 001 010 011 100 101 110 111
mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, la_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, la_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, la_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, la_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, la_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, la_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, la_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, la_pwr_lo, 1'b0, 1'b0, 1'b1, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, la_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, la_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, la_dbg, 1'b0, 1'b0, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module counts which bits for serial audio transfers. The module *
* assume that the data format is I2S, as it is described in the audio *
* chip's datasheet. *
* *
******************************************************************************/
module altera_up_audio_bit_counter (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
// Bidirectionals
// Outputs
counting
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BIT_COUNTER_INIT = 5'h0F;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
// Bidirectionals
// Outputs
output reg counting;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire reset_bit_counter;
// Internal Registers
reg [ 4: 0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
bit_counter <= 5'h00;
else if (reset_bit_counter == 1'b1)
bit_counter <= BIT_COUNTER_INIT;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter != 5'h00))
bit_counter <= bit_counter - 5'h01;
end
always @(posedge clk)
begin
if (reset == 1'b1)
counting <= 1'b0;
else if (reset_bit_counter == 1'b1)
counting <= 1'b1;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter == 5'h00))
counting <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign reset_bit_counter = left_right_clk_rising_edge |
left_right_clk_falling_edge;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0P_BEHAVIORAL_V
`define SKY130_FD_SC_LP__ISO0P_BEHAVIORAL_V
/**
* iso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__iso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0P_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long x, long long y) { if (y == 0) return x; else return gcd(y, x % y); } long long expo(long long n, long long m) { long long r = 1; while (m > 0) { if (m % 2) r = (r * n) % 1000000009; n = (n * n) % 1000000009; m = m / 2; } return r % 1000000009; } long long lx = 0, ly = 0; bool check(long long x, long long y) {} int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long a, b; cin >> a >> b; string s; cin >> s; long long p = 0, q = 0; if (a == 0 && b == 0) { cout << Yes ; return 0; } for (long long i = 0; i < s.size(); i++) { if (s[i] == U ) { ly++; } else if (s[i] == D ) ly--; else if (s[i] == L ) lx--; else lx++; if (lx == a && ly == b) { cout << Yes ; return 0; } } if (lx == 0 && ly == 0) { cout << No ; return 0; } for (long long i = 0; i < s.size(); i++) { if (s[i] == U ) { q++; } else if (s[i] == D ) q--; else if (s[i] == L ) p--; else p++; long long x = a - p, y = b - q, X = lx, Y = ly; if (lx == 0) { if (ly > 0 && y > 0 && x == 0 && y % ly == 0) { cout << Yes ; return 0; } else if (ly < 0 && y < 0 && x == 0) { ly = -1 * ly, y = -1 * y; if (y % ly == 0) { cout << Yes ; return 0; } } } else if (ly == 0) { if (lx > 0 && x > 0 && y == 0 && x % lx == 0) { cout << Yes ; return 0; } else if (lx < 0 && x < 0 && y == 0) { lx = -1 * lx, x = -1 * x; if (x % lx == 0) { cout << Yes ; return 0; } } } else { if (lx > 0 && x > 0) { if (ly > 0 && y > 0) { if (x / lx == y / ly && x % lx == 0 && y % ly == 0) { cout << Yes ; return 0; } } else if (ly < 0 && y < 0) { ly = -1 * ly, y = -1 * y; if (x / lx == y / ly && x % lx == 0 && y % ly == 0) { cout << Yes ; return 0; } } } else if (lx < 0 && x < 0) { lx = -1 * lx, x = -1 * x; if (ly > 0 && y > 0) { if (x / lx == y / ly && x % lx == 0 && y % ly == 0) { cout << Yes ; return 0; } } else if (ly < 0 && y < 0) { ly = -1 * ly, y = -1 * y; if (x / lx == y / ly && x % lx == 0 && y % ly == 0) { cout << Yes ; return 0; } } } } lx = X, ly = Y; } cout << No ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SRSDFXTP_PP_BLACKBOX_V
/**
* srsdfxtp: Scan flop with sleep mode, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFXTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long n, k; bool check(long long mid) { long long sum = (mid + k - 1) * (k - mid) / 2; return (sum >= n - 1); } int main() { scanf( %I64d%I64d , &n, &k); if (n == 1) { printf( 0 ); return 0; } long long l = 1, r = k - 1, mid; while (l < r) { mid = (l + r + 1) >> 1; if (check(mid)) l = mid; else r = mid - 1; } if ((l + k - 1) * (k - l) / 2 >= n - 1) printf( %I64d , k - l); else printf( -1 ); }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module contains a character map for 128 different characters. *
* *
******************************************************************************/
module altera_up_video_128_character_rom (
// Inputs
clk,
clk_en,
character,
x_coordinate,
y_coordinate,
// Bidirectionals
// Outputs
character_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input clk_en;
input [ 6: 0] character;
input [ 2: 0] x_coordinate;
input [ 2: 0] y_coordinate;
// Bidirectionals
// Outputs
output character_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [12: 0] character_address;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign character_address = {character, y_coordinate, x_coordinate};
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altsyncram character_data_rom (
// Inputs
.clock0 (clk),
.clocken0 (clk_en),
.address_a (character_address),
// Bidirectionals
// Outputs
.q_a (character_data),
// Unused
.aclr0 (1'b0),
.aclr1 (1'b0),
.q_b (),
.clocken1 (1'b1),
.data_b (1'b1),
.wren_a (1'b0),
.data_a (1'b1),
.rden_b (1'b1),
.address_b (1'b1),
.wren_b (1'b0),
.byteena_b (1'b1),
.addressstall_a (1'b0),
.byteena_a (1'b1),
.addressstall_b (1'b0),
.clock1 (1'b1)
);
defparam
character_data_rom.clock_enable_input_a = "NORMAL",
character_data_rom.clock_enable_output_a = "NORMAL",
character_data_rom.init_file = "altera_up_video_char_mode_rom_128.mif",
character_data_rom.intended_device_family = "Cyclone II",
character_data_rom.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
character_data_rom.lpm_type = "altsyncram",
character_data_rom.numwords_a = 8192,
character_data_rom.operation_mode = "ROM",
character_data_rom.outdata_aclr_a = "NONE",
character_data_rom.outdata_reg_a = "CLOCK0",
character_data_rom.power_up_uninitialized = "FALSE",
character_data_rom.read_during_write_mode_mixed_ports = "DONT_CARE",
character_data_rom.widthad_a = 13,
character_data_rom.width_a = 1,
character_data_rom.width_byteena_a = 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long n, m, val, i, j = 0, sum = 0, k = 0; vector<long> toys; vector<long> selected; cin >> n >> m; for (i = 0; i < n; i++) { cin >> val; toys.push_back(val); } sort(toys.begin(), toys.end()); for (i = 0; i < 1000000000; i++) { if (j < (long)toys.size()) { if (toys[j] == (i + 1)) { j++; } else { if (sum + i + 1 <= m) { selected.push_back(i + 1); sum += i + 1; k++; } else { break; } } } else if (sum + i + 1 <= m) { selected.push_back(i + 1); sum += i + 1; k++; } else { break; } } cout << k << endl; for (auto t : selected) { cout << t << ; } cout << endl; return 0; }
|
/**
* $Id: red_pitaya_hk.v -01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya house keeping.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* House keeping module takes care of system identification.
*
*
* This module takes care of system identification via DNA readout at startup and
* ID register which user can define at compile time.
*
* Beside that it is currently also used to test expansion connector and for
* driving LEDs.
*
*/
module red_pitaya_hk
(
input clk_i , //!< clock
input rstn_i , //!< reset - active low
// LED
output [ 8-1: 0] led_o , //!< LED output
// Expansion connector
input [ 8-1: 0] exp_p_dat_i , //!< exp. con. input data
output reg [ 8-1: 0] exp_p_dat_o , //!< exp. con. output data
output reg [ 8-1: 0] exp_p_dir_o , //!< exp. con. 1-output enable
input [ 8-1: 0] exp_n_dat_i , //!<
output reg [ 8-1: 0] exp_n_dat_o , //!<
output reg [ 8-1: 0] exp_n_dir_o , //!<
// System bus
input sys_clk_i , //!< bus clock
input sys_rstn_i , //!< bus reset - active low
input [ 32-1: 0] sys_addr_i , //!< bus address
input [ 32-1: 0] sys_wdata_i , //!< bus write data
input [ 4-1: 0] sys_sel_i , //!< bus write byte select
input sys_wen_i , //!< bus write enable
input sys_ren_i , //!< bus read enable
output reg [ 32-1: 0] sys_rdata_o , //!< bus read data
output reg sys_err_o , //!< bus error indicator
output reg sys_ack_o //!< bus acknowledge signal
);
//---------------------------------------------------------------------------------
//
// Simple LED logic
reg [32-1: 0] shift_led_cnt ;
reg [ 8-1: 0] shift_led_reg ;
reg shift_led_dir ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
shift_led_cnt <= 32'h0 ;
shift_led_reg <= 8'h1 ;
shift_led_dir <= 1'b1 ; // 1-left, 0-right
end
else begin
if (shift_led_cnt == 32'd40000000)
shift_led_cnt <= 32'h1;
else
shift_led_cnt <= shift_led_cnt + 32'h1;
if (shift_led_cnt == 32'h1) begin
if (shift_led_dir)
shift_led_reg <= {shift_led_reg[6:0], 1'b0} ; //shift left
else
shift_led_reg <= {1'b0, shift_led_reg[7:1]} ; //shift right
// change direction
if (shift_led_dir && (shift_led_reg==8'h40))
shift_led_dir <= !shift_led_dir ;
else if (!shift_led_dir && (shift_led_reg==8'h2))
shift_led_dir <= !shift_led_dir ;
end
end
end
//---------------------------------------------------------------------------------
//
// Testing logic
// LED blinking
reg [ 8-1: 0] led_reg ;
reg [ 32-1: 0] led_cnt ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
led_reg[0] <= 1'b0 ;
led_cnt <= 32'h0 ;
end
else begin
led_reg[0] <= led_cnt[26] ;
led_cnt <= led_cnt + 32'h1 ;
end
end
assign led_o = led_reg ; //shift_led_reg;
//---------------------------------------------------------------------------------
//
// Read device DNA
wire dna_dout ;
reg dna_clk ;
reg dna_read ;
reg dna_shift ;
reg [ 9-1: 0] dna_cnt ;
reg [57-1: 0] dna_value ;
reg dna_done ;
always @(posedge sys_clk_i) begin
if (sys_rstn_i == 1'b0) begin
dna_clk <= 1'b0 ;
dna_read <= 1'b0 ;
dna_shift <= 1'b0 ;
dna_cnt <= 9'd0 ;
dna_value <= 57'd0 ;
dna_done <= 1'b0 ;
end
else begin
if (!dna_done)
dna_cnt <= dna_cnt + 1'd1 ;
dna_clk <= dna_cnt[2] ;
dna_read <= (dna_cnt < 9'd10);
dna_shift <= (dna_cnt > 9'd18);
if ((dna_cnt[2:0]==3'h0) && !dna_done)
dna_value <= {dna_value[57-2:0], dna_dout};
if (dna_cnt > 9'd465)
dna_done <= 1'b1;
end
end
DNA_PORT #( .SIM_DNA_VALUE(57'h0823456789ABCDE) ) // Specifies a sample 57-bit DNA value for simulation
i_DNA
(
.DOUT ( dna_dout ), // 1-bit output: DNA output data.
.CLK ( dna_clk ), // 1-bit input: Clock input.
.DIN ( 1'b0 ), // 1-bit input: User data input pin.
.READ ( dna_read ), // 1-bit input: Active high load DNA, active low read input.
.SHIFT ( dna_shift ) // 1-bit input: Active high shift enable input.
);
//---------------------------------------------------------------------------------
//
// Desing identification
wire [32-1: 0] id_value ;
assign id_value[31: 4] = 28'h0 ; // reserved
assign id_value[ 3: 0] = 4'h1 ; // board type 1-release1
//---------------------------------------------------------------------------------
//
// System bus connection
always @(posedge sys_clk_i) begin
if (sys_rstn_i == 1'b0) begin
led_reg[7:1] <= 7'h0 ;
exp_p_dat_o <= 8'h0 ;
exp_p_dir_o <= 8'h0 ;
exp_n_dat_o <= 8'h0 ;
exp_n_dir_o <= 8'h0 ;
end
else begin
if (sys_wen_i) begin
if (sys_addr_i[19:0]==20'h10) exp_p_dir_o <= sys_wdata_i[8-1:0] ;
if (sys_addr_i[19:0]==20'h14) exp_n_dir_o <= sys_wdata_i[8-1:0] ;
if (sys_addr_i[19:0]==20'h18) exp_p_dat_o <= sys_wdata_i[8-1:0] ;
if (sys_addr_i[19:0]==20'h1C) exp_n_dat_o <= sys_wdata_i[8-1:0] ;
if (sys_addr_i[19:0]==20'h30) led_reg[7:1] <= sys_wdata_i[8-1:1] ;
end
end
end
always @(*) begin
sys_err_o <= 1'b0 ;
casez (sys_addr_i[19:0])
20'h00000 : begin sys_ack_o <= 1'b1; sys_rdata_o <= { id_value } ; end
20'h00004 : begin sys_ack_o <= 1'b1; sys_rdata_o <= { dna_value[31: 0] } ; end
20'h00008 : begin sys_ack_o <= 1'b1; sys_rdata_o <= {{32-25{1'b0}}, dna_value[56:32] } ; end
20'h00010 : begin sys_ack_o <= 1'b1; sys_rdata_o <= {{32- 8{1'b0}}, exp_p_dir_o } ; end
20'h00014 : begin sys_ack_o <= 1'b1; sys_rdata_o <= {{32- 8{1'b0}}, exp_n_dir_o } ; end
20'h00018 : begin sys_ack_o <= 1'b1; sys_rdata_o <= {{32- 8{1'b0}}, exp_p_dat_o } ; end
20'h0001C : begin sys_ack_o <= 1'b1; sys_rdata_o <= {{32- 8{1'b0}}, exp_n_dat_o } ; end
20'h00020 : begin sys_ack_o <= 1'b1; sys_rdata_o <= {{32- 8{1'b0}}, exp_p_dat_i } ; end
20'h00024 : begin sys_ack_o <= 1'b1; sys_rdata_o <= {{32- 8{1'b0}}, exp_n_dat_i } ; end
20'h00030 : begin sys_ack_o <= 1'b1; sys_rdata_o <= {{32- 8{1'b0}}, led_reg[7:1], 1'b0 } ; end
default : begin sys_ack_o <= 1'b1; sys_rdata_o <= 32'h0 ; end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4_TB_V
`define SKY130_FD_SC_HDLL__AND4_TB_V
/**
* and4: 4-input AND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hdll__and4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4_TB_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; const double eps = 1e-6; int x[8], y[8]; bool check(int a, int b) { return a >= min({x[0], x[1], x[2], x[3]}) && a <= max({x[0], x[1], x[2], x[3]}) && b >= min({y[0], y[1], y[2], y[3]}) && b <= max({y[0], y[1], y[2], y[3]}); } int main() { for (int i = 0; i < 8; i++) scanf( %d%d , x + i, y + i); int tx = (x[4] + x[6]) / 2; int ty = (y[4] + y[6]) / 2; int d = abs(x[4] - tx) + abs(y[4] - ty); for (int xx = -100; xx <= 100; xx++) for (int yy = -100; yy <= 100; yy++) if (abs(xx - tx) + abs(yy - ty) <= d) if (check(xx, yy)) return cout << YES , 0; cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, x, b, k, v[100005], v2[100005], m; bool OK(int x) { int lst = -1e9, nr = 0; for (int i = 1; i <= n; i++) { if (v[i] - lst >= x) { nr++; lst = v[i]; } } return nr <= k; } int main() { ios::sync_with_stdio(false); cin >> n >> m >> k; for (int i = 1; i <= n; i++) { cin >> v[i]; } sort(v + 1, v + n + 1); if (k >= n) { cout << n << n ; return 0; } for (int i = 2; i <= n; i++) { v2[i - 1] = v[i] - v[i - 1]; } sort(v2 + 1, v2 + n); k--; int ans = v[n] - v[1] + 1; for (int i = n - 1; i >= 1 && k > 0; i--, k--) { ans -= (v2[i] - 1); } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> int ar[100000]; int main() { int i, j, m, n, total = 0, a, b, c; scanf( %d %d , &n, &m); if (m == 0 || n == 1) printf( 0 ); else { for (j = 1; j <= m; j++) { scanf( %d %d %d , &a, &b, &c); ar[a] += c; ar[b] -= c; } for (i = 1; i <= n; i++) { if (ar[i] < 0) total += ar[i]; } total = -1 * total; printf( %d , total); } return 0; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ns / 1 ns
// synopsys translate_on
module altera_jtag_sld_node (
ir_out,
tdo,
ir_in,
tck,
tdi,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir
);
parameter TCK_FREQ_MHZ = 20;
localparam TCK_HALF_PERIOD_US = (1000/TCK_FREQ_MHZ)/2;
localparam IRWIDTH = 3;
input [IRWIDTH - 1:0] ir_out;
input tdo;
output reg [IRWIDTH - 1:0] ir_in;
output tck;
output reg tdi = 1'b0;
output virtual_state_cdr;
output virtual_state_cir;
output virtual_state_e1dr;
output virtual_state_e2dr;
output virtual_state_pdr;
output virtual_state_sdr;
output virtual_state_udr;
output virtual_state_uir;
// PHY Simulation signals
`ifndef ALTERA_RESERVED_QIS
reg simulation_clock;
reg sdrs;
reg cdr;
reg sdr;
reg e1dr;
reg udr;
reg [7:0] bit_index;
`endif
// PHY Instantiation
`ifdef ALTERA_RESERVED_QIS
wire tdi_port;
wire [IRWIDTH - 1:0] ir_in_port;
always @(tdi_port)
tdi = tdi_port;
always @(ir_in_port)
ir_in = ir_in_port;
sld_virtual_jtag_basic sld_virtual_jtag_component (
.ir_out (ir_out),
.tdo (tdo),
.tdi (tdi_port),
.tck (tck),
.ir_in (ir_in_port),
.virtual_state_cir (virtual_state_cir),
.virtual_state_pdr (virtual_state_pdr),
.virtual_state_uir (virtual_state_uir),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_e1dr (virtual_state_e1dr),
.virtual_state_e2dr (virtual_state_e2dr)
// synopsys translate_off
,
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_e1ir (),
.jtag_state_e2dr (),
.jtag_state_e2ir (),
.jtag_state_pdr (),
.jtag_state_pir (),
.jtag_state_rti (),
.jtag_state_sdr (),
.jtag_state_sdrs (),
.jtag_state_sir (),
.jtag_state_sirs (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.tms ()
// synopsys translate_on
);
defparam
sld_virtual_jtag_component.sld_mfg_id = 110,
sld_virtual_jtag_component.sld_type_id = 132,
sld_virtual_jtag_component.sld_version = 1,
sld_virtual_jtag_component.sld_auto_instance_index = "YES",
sld_virtual_jtag_component.sld_instance_index = 0,
sld_virtual_jtag_component.sld_ir_width = IRWIDTH,
sld_virtual_jtag_component.sld_sim_action = "",
sld_virtual_jtag_component.sld_sim_n_scan = 0,
sld_virtual_jtag_component.sld_sim_total_length = 0;
`endif
// PHY Simulation
`ifndef ALTERA_RESERVED_QIS
localparam DATA = 0;
localparam LOOPBACK = 1;
localparam DEBUG = 2;
localparam INFO = 3;
localparam CONTROL = 4;
localparam MGMT = 5;
always
//#TCK_HALF_PERIOD_US simulation_clock = $random;
#TCK_HALF_PERIOD_US simulation_clock = ~simulation_clock;
assign tck = simulation_clock;
assign virtual_state_cdr = cdr;
assign virtual_state_sdr = sdr;
assign virtual_state_e1dr = e1dr;
assign virtual_state_udr = udr;
task reset_jtag_state;
begin
simulation_clock = 0;
enter_data_mode;
clear_states_async;
end
endtask
task enter_data_mode;
begin
ir_in = DATA;
clear_states;
end
endtask
task enter_loopback_mode;
begin
ir_in = LOOPBACK;
clear_states;
end
endtask
task enter_debug_mode;
begin
ir_in = DEBUG;
clear_states;
end
endtask
task enter_info_mode;
begin
ir_in = INFO;
clear_states;
end
endtask
task enter_control_mode;
begin
ir_in = CONTROL;
clear_states;
end
endtask
task enter_mgmt_mode;
begin
ir_in = MGMT;
clear_states;
end
endtask
task enter_sdrs_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b10000;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_cdr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b01000;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_e1dr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b00010;
tdi = 1'b0;
@(posedge tck);
end
endtask
task enter_udr_state;
begin
{sdrs, cdr, sdr, e1dr, udr} = 5'b00001;
tdi = 1'b0;
@(posedge tck);
end
endtask
task clear_states;
begin
clear_states_async;
@(posedge tck);
end
endtask
task clear_states_async;
begin
{cdr, sdr, e1dr, udr} = 4'b0000;
end
endtask
task shift_one_bit;
input bit_to_send;
output reg bit_received;
begin
{cdr, sdr, e1dr, udr} = 4'b0100;
tdi = bit_to_send;
@(posedge tck);
bit_received = tdo;
end
endtask
task shift_one_byte;
input [7:0] byte_to_send;
output reg [7:0] byte_received;
integer i;
reg bit_received;
begin
for (i=0; i<8; i=i+1)
begin
bit_index = i;
shift_one_bit(byte_to_send[i], bit_received);
byte_received[i] = bit_received;
end
end
endtask
`endif
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:27:15 11/09/2016
// Design Name: Sprite_Controller
// Module Name: C:/Users/yoe/Desktop/Experimento4/Monitor/testSprite.v
// Project Name: Monitor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Sprite_Controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testSprite;
// Inputs
reg [9:0] iColumnCount;
reg [9:0] iRowCount;
reg imask;
reg iEnable;
reg [9:0] iPosX;
reg [9:0] iPosY;
reg [2:0] iColorSprite;
reg [2:0] iColorBack;
// Outputs
wire [2:0] oRGB;
// Instantiate the Unit Under Test (UUT)
Sprite_Controller spriteTest (
.iColumnCount(iColumnCount),
.iRowCount(iRowCount),
.imask(imask),
.iEnable(iEnable),
.iPosX(iPosX),
.iPosY(iPosY),
.iColorSprite(iColorSprite),
.iColorBack(iColorBack),
.oRGB(oRGB)
);
initial begin
// Initialize Inputs
iColumnCount = 0;
iRowCount = 0;
imask = 0;
iEnable = 0;
iPosX = 5;
iPosY = 5;
iColorSprite = 2;
iColorBack = 5;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always
begin
#10
iColumnCount = iColumnCount + 1;
iRowCount = iRowCount + 1;
{iEnable,imask} = {iEnable,imask} +1;
end
endmodule
|
module user_design(clk, rst, exception, input_rs232_rx, input_gps_rx, input_gps_count, input_rs232_rx_stb, input_gps_rx_stb, input_gps_count_stb, input_rs232_rx_ack, input_gps_rx_ack, input_gps_count_ack, output_tx_ctl, output_rs232_tx, output_leds, output_gps_tx, output_tx_freq, output_tx_am, output_tx_ctl_stb, output_rs232_tx_stb, output_leds_stb, output_gps_tx_stb, output_tx_freq_stb, output_tx_am_stb, output_tx_ctl_ack, output_rs232_tx_ack, output_leds_ack, output_gps_tx_ack, output_tx_freq_ack, output_tx_am_ack);
input clk;
input rst;
output exception;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_gps_rx;
input input_gps_rx_stb;
output input_gps_rx_ack;
input [31:0] input_gps_count;
input input_gps_count_stb;
output input_gps_count_ack;
output [31:0] output_tx_ctl;
output output_tx_ctl_stb;
input output_tx_ctl_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_gps_tx;
output output_gps_tx_stb;
input output_gps_tx_ack;
output [31:0] output_tx_freq;
output output_tx_freq_stb;
input output_tx_freq_ack;
output [31:0] output_tx_am;
output output_tx_am_stb;
input output_tx_am_ack;
wire exception_140581388082136;
main_0 main_0_140581388082136(
.clk(clk),
.rst(rst),
.exception(exception_140581388082136),
.input_gps_count(input_gps_count),
.input_gps_count_stb(input_gps_count_stb),
.input_gps_count_ack(input_gps_count_ack),
.input_gps_rx(input_gps_rx),
.input_gps_rx_stb(input_gps_rx_stb),
.input_gps_rx_ack(input_gps_rx_ack),
.input_rs232_rx(input_rs232_rx),
.input_rs232_rx_stb(input_rs232_rx_stb),
.input_rs232_rx_ack(input_rs232_rx_ack),
.output_rs232_tx(output_rs232_tx),
.output_rs232_tx_stb(output_rs232_tx_stb),
.output_rs232_tx_ack(output_rs232_tx_ack),
.output_leds(output_leds),
.output_leds_stb(output_leds_stb),
.output_leds_ack(output_leds_ack),
.output_freq_out(output_tx_freq),
.output_freq_out_stb(output_tx_freq_stb),
.output_freq_out_ack(output_tx_freq_ack),
.output_gps_tx(output_gps_tx),
.output_gps_tx_stb(output_gps_tx_stb),
.output_gps_tx_ack(output_gps_tx_ack),
.output_ctl_out(output_tx_ctl),
.output_ctl_out_stb(output_tx_ctl_stb),
.output_ctl_out_ack(output_tx_ctl_ack),
.output_am_out(output_tx_am),
.output_am_out_stb(output_tx_am_stb),
.output_am_out_ack(output_tx_am_ack));
assign exception = exception_140581388082136;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 500010, INF = MAXN + 1; struct Query { int pos, l, r; }; struct AddEvent { int pos, value, start_valid; }; int n, m; int as[MAXN]; int close[MAXN]; Query queries[MAXN]; AddEvent add_events[MAXN]; int results[MAXN]; int st[4 * MAXN]; void update(int v, int l, int r, int ind, int val) { if (l == r) { assert(st[v] == INF); st[v] = val; } else { int m = (l + r) >> 1; if (ind <= m) update(v + v, l, m, ind, val); else update(v + v + 1, m + 1, r, ind, val); st[v] = min(st[v + v], st[v + v + 1]); } } int get(int v, int l, int r, int tl, int tr) { assert(l <= tl && tr <= r && tl <= tr); if (l == tl && r == tr) return st[v]; int res = INF, m = (l + r) >> 1; if (tl <= m) res = get(v + v, l, m, tl, min(tr, m)); if (tr > m) res = min(res, get(v + v + 1, m + 1, r, max(m + 1, tl), tr)); return res; } int main() { for (int i = 0; i < int(4 * MAXN); ++i) st[i] = INF; scanf( %d%d , &n, &m); for (int i = 0; i < int(n); ++i) scanf( %d , &as[i]); for (int i = 0; i < int(m); ++i) { scanf( %d%d , &queries[i].l, &queries[i].r); --queries[i].l, --queries[i].r; queries[i].pos = i; } sort(queries, queries + m, [](Query a, Query b) { return a.r < b.r; }); map<int, int> last; for (int i = n - 1; i >= 0; i--) { auto it = last.find(as[i]); if (it == last.end()) { close[i] = INF; } else { close[i] = it->second - i; } last[as[i]] = i; } for (int i = 0; i < int(n); ++i) { add_events[i] = {i, close[i], i + close[i]}; } sort(add_events, add_events + n, [](AddEvent a, AddEvent b) { return a.start_valid < b.start_valid; }); int qp = 0, ap = 0; for (int i = 0; i < n; i++) { while (ap < n && add_events[ap].start_valid == i) { update(1, 0, n - 1, add_events[ap].pos, add_events[ap].value); ++ap; } while (qp < m && queries[qp].r == i) { results[queries[qp].pos] = get(1, 0, n - 1, queries[qp].l, queries[qp].r); ++qp; } } for (int i = 0; i < int(m); ++i) { if (results[i] == INF) results[i] = -1; printf( %d n , results[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; int n; signed main() { ios_base ::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> s; vector<pair<int, int>> a; vector<int> p(n, 0), nxt(n, 0); stack<pair<int, int>> S; S.push({0, -1}); for (int i = 0; i < n; ++i) { if (s[i] == ( ) { p[i] = S.top().second; a.push_back({S.top().first + 1, i}); S.push({a.back().first, i}); } else { nxt[S.top().second] = i; S.pop(); } } sort(a.rbegin(), a.rend()); string k(n, x ); for (int i = 0; i < int(a.size()); ++i) { int y = a[i].second; if (k[y] != x ) { k[nxt[y]] = k[y]; continue; } int c = -1, cnt = 0; for (y = a[i].second; y != -1 && k[y] == x ; y = p[y]) cnt ^= 1; if (y != -1) c = k[y] - 0 ; int t = 1; if (c != -1) t = c ^ cnt; for (y = a[i].second; y != -1 && k[y] == x ; t ^= 1, y = p[y]) k[y] = t + 0 ; k[nxt[a[i].second]] = k[a[i].second]; } cout << k << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4BB_FUNCTIONAL_PP_V
|
/*
* comperator_2 module:
* this module is combinatorical. it comperes 2 given inputs and returns
* the one with greater or smaller value (c_data and corresponding index) accorging
* to great_n_small signal.
* comperation region is scalable and can be chosen using lo and hi parameters.
*
* PARAMETERS:
* data_wd: width of input data
* idx_wd: width of index
* lo: bit select. starting mark of significant bits to be taken
into accound in comperation
* hi: bit select. end of mark region
*
* OUTPUT:
* c_dat: choosen element
* c_idx: choosen element index
* c_dv: output data valid indication
* INPUT:
* d0,d1: input data to be compared
* d0_idx,
* d1_idx: input data indexes
* d0_dv,
* d1_dv: input data valid indication
* great_n_samll:
* operation to be performed. '1' - greater index will be returned
* '0' - smaller index will be returned
*
* Author: Kimi
*/
`ifndef _comperator_2
`define _comperator_2
`timescale 1ns /1ps
//`include "../common_defines.v"
module comperator_2 #(parameter data_wd = 16,idx_wd = 4,hi = 15,lo = 0)
(
output reg [data_wd-1:0] c_dat,
output reg [idx_wd-1 :0] c_idx,
output reg c_dv,
input wire [data_wd-1:0] d0, d1,
input wire [idx_wd-1 :0] d0_idx, d1_idx,
input wire d0_dv, d1_dv,
input wire great_n_small
);
always @(*) begin
if (d0_dv && d1_dv && great_n_small) begin
c_dat = (d0[hi:lo] > d1[hi:lo]) ? d0 : d1;
c_idx = (d0[hi:lo] > d1[hi:lo]) ? d0_idx : d1_idx;
c_dv = 1'b1;
end
else if (d0_dv && d1_dv && !great_n_small) begin
c_dat = (d0[hi:lo] < d1[hi:lo]) ? d0 : d1;
c_idx = (d0[hi:lo] < d1[hi:lo]) ? d0_idx : d1_idx;
c_dv = 1'b1;
end
else if (d0_dv && !d1_dv) begin
c_dat = d0;
c_idx = d0_idx;
c_dv = 1'b1;
end
else if (!d0_dv && d1_dv) begin
c_dat = d1;
c_idx = d1_idx;
c_dv = 1'b1;
end
else begin /* (!d0_dv && !d1_dv) */
c_dat = {data_wd{1'b0}};
c_idx = {idx_wd {1'b0}};
c_dv = 1'b0;
end
end
endmodule
`endif
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : ;
endmodule
|
#include <bits/stdc++.h> using namespace std; class CElections { public: struct person { long long p, c; }; int n, m; person arr[3100]; vector<long long> parties[3100]; long long sol(int votes) { int total_votes_needed = votes - (int)parties[0].size(); vector<long long> rem; long long ans = 0; for (__typeof(m) i = (0) - ((0) > (m)); i != (m) - ((0) > (m)); i += 1 - 2 * ((0) > (m))) { if (!i) continue; int num = (int)parties[i].size() - votes + 1; if (num > 0) { total_votes_needed -= num; for (__typeof(num) j = (0) - ((0) > (num)); j != (num) - ((0) > (num)); j += 1 - 2 * ((0) > (num))) ans += parties[i][j]; } for (int j = max(num, 0); j < parties[i].size(); j++) rem.push_back(parties[i][j]); } if (total_votes_needed > 0) { nth_element(rem.begin(), rem.begin() + total_votes_needed, rem.end()); for (__typeof(total_votes_needed) i = (0) - ((0) > (total_votes_needed)); i != (total_votes_needed) - ((0) > (total_votes_needed)); i += 1 - 2 * ((0) > (total_votes_needed))) ans += rem[i]; } return ans; } void solve(std::istream &in, std::ostream &out) { in >> n >> m; for (__typeof(n) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) in >> arr[i].p >> arr[i].c, arr[i].p--, parties[arr[i].p].push_back(arr[i].c); sort(arr, arr + n, [](person a, person b) { return a.c < b.c; }); for (__typeof(m) i = (0) - ((0) > (m)); i != (m) - ((0) > (m)); i += 1 - 2 * ((0) > (m))) sort(parties[i].begin(), parties[i].end()); int low = max(1, (int)parties[0].size()), high = n; while (low < high) { int mid = (low + high) / 2; if (sol(mid) < sol(mid + 1)) { high = mid; } else { low = mid + 1; } } long long ans = sol(low); out << ans << n ; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); CElections solver; std::istream &in(std::cin); std::ostream &out(std::cout); solver.solve(in, out); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int max(long long int a, long long int b) { if (a > b) { return a; } return b; } long long int gcd(long long int a, long long int b) { if (a == 0) { return b; } return gcd(b % a, a); } long long int min(long long int a, long long int b) { if (a < b) { return a; } return b; } long long int power(long long int x, long long int n) { long long int res = 1; while (n > 0) { if (n % 2 == 1) { res = (res * x); } x = (x * x); n = n / 2; } return res; } long long int factorialNumInverse[1000001]; long long int naturalNumInverse[1000001]; long long int fact[1000001]; void InverseofNumber(long long int n, long long int p) { naturalNumInverse[0] = naturalNumInverse[1] = 1; for (long long int i = 2; i <= n; i++) naturalNumInverse[i] = naturalNumInverse[p % i] * (p - p / i) % p; } void InverseofFactorial(long long int n, long long int p) { factorialNumInverse[0] = factorialNumInverse[1] = 1; for (long long int i = 2; i <= n; i++) factorialNumInverse[i] = (naturalNumInverse[i] * factorialNumInverse[i - 1]) % p; } void factorial(long long int n, long long int p) { fact[0] = 1; for (long long int i = 1; i <= n; i++) { fact[i] = (fact[i - 1] * i) % p; } } long long int nCrModp(long long int n, long long int r, long long int p) { long long int ans = ((fact[n] * factorialNumInverse[r]) % p * factorialNumInverse[n - r]) % p; return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int tc; cin >> tc; factorial(200005, 1000000007); InverseofNumber(200005, 1000000007); InverseofFactorial(200005, 1000000007); while (tc--) { long long int n; cin >> n; string s; cin >> s; long long int ans = 0; long long int i = 1; long long int len = 1; while (i < n) { if (s[i] == s[0]) { len++; } i++; } if (len == n) { cout << ceil((long double)n / (long double)3) << n ; continue; } len = 0; i = 0; int j = s.length() - 1; while (j >= 0 && s[j] == s[0]) { len++; j--; } while (i <= j && s[i] == s[0]) { len++; i++; } ans += (len) / 3; len = 1; i++; while (i <= j) { if (s[i] == s[i - 1]) { len++; } else { ans += (len) / 3; len = 1; } i++; } ans += (len) / 3; cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2000005; char str[MAXN]; struct Palindromic_Tree { vector<pair<int, int>> next[MAXN]; int fail[MAXN]; int cnt[MAXN]; int num[MAXN]; int len[MAXN]; int S[MAXN]; int last; int n; int p; int newnode(int l) { next[p].clear(); cnt[p] = 0; num[p] = 0; len[p] = l; return p++; } void init() { p = 0; next[0].clear(); next[1].clear(); newnode(0); newnode(-1); last = 0; n = 0; S[n] = -1; fail[0] = 1; } int get_fail(int x) { while (S[n - len[x] - 1] != S[n]) x = fail[x]; return x; } int find(int cur, int c) { for (int i = 0; i < next[cur].size(); i++) { if (next[cur][i].first == c) return next[cur][i].second; } return 0; } int add(int c) { c -= a ; S[++n] = c; int cur = get_fail(last); int k = find(cur, c); if (k == 0) { int now = newnode(len[cur] + 2); fail[now] = find(get_fail(fail[cur]), c); next[cur].push_back(make_pair(c, now)); num[now] = num[fail[now]] + 1; } last = find(cur, c); cnt[last]++; return num[last]; } void count() { for (int i = p - 1; i >= 0; --i) cnt[fail[i]] += cnt[i]; } } tree; long long head[MAXN], tail[MAXN]; int main() { int n; while (~scanf( %d , &n)) { memset(head, 0, sizeof(head)); memset(tail, 0, sizeof(tail)); scanf( %s , str + 1); tree.init(); for (int i = 1; i <= n; i++) { tail[i] = tree.add(str[i]); } tree.init(); for (int i = n; i >= 1; i--) { head[i] = ((head[i + 1] + tree.add(str[i])) % 51123987) % 51123987; } long long ans = head[1] * (head[1] - 1) / 2 % 51123987; for (int i = 2; i <= n; i++) ans = (ans - tail[i - 1] * head[i] % 51123987) % 51123987; ans = (ans + 51123987) % 51123987; printf( %lld n , ans); } return 0; }
|
`timescale 1ns / 100ps
`define EIC_DIRECT_CHANNELS 20
`define EIC_SENSE_CHANNELS 20
`include "mfp_eic_core.vh"
module test_eicAhb;
`include "ahb_lite.vh"
reg [ `EIC_CHANNELS -1 : 0 ] signal;
wire [ 17 : 1 ] EIC_Offset;
wire [ 3 : 0 ] EIC_ShadowSet;
wire [ 7 : 0 ] EIC_Interrupt;
wire [ 5 : 0 ] EIC_Vector;
wire EIC_Present;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
reg [ 31 : 0 ] write_data;
reg write_enable;
task delay;
begin
@(posedge HCLK);
@(posedge HCLK);
@(posedge HCLK);
end
endtask
mfp_ahb_lite_eic eic
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HADDR ( HADDR ),
.HBURST ( HBURST ),
.HSEL ( HSEL ),
.HSIZE ( HSIZE ),
.HTRANS ( HTRANS ),
.HWDATA ( HWDATA ),
.HWRITE ( HWRITE ),
.HRDATA ( HRDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
.signal ( signal ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present )
);
/*
module mfp_ahb_lite_eic
(
//ABB-Lite side
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK, // ignored
input [ 3 : 0 ] HPROT, // ignored
input HSEL,
input [ 2 : 0 ] HSIZE,
input [ 1 : 0 ] HTRANS,
input [ 31 : 0 ] HWDATA,
input HWRITE,
output reg [ 31 : 0 ] HRDATA,
output HREADY,
output HRESP,
input SI_Endian, // ignored
//Interrupt side
input [ `EIC_CHANNELS-1 : 0 ] signal,
//CPU side
output [ 17 : 1 ] EIC_Offset,
output [ 3 : 0 ] EIC_ShadowSet,
output [ 7 : 0 ] EIC_Interrupt,
output [ 5 : 0 ] EIC_Vector,
output EIC_Present
);
*/
parameter Tclk = 20;
always #(Tclk/2) HCLK = ~HCLK;
initial begin
begin
signal = 16'b0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
@(posedge HCLK);
ahbPhaseFst(`EIC_REG_EICR << 2, WRITE, HSIZE_X32, St_x); //enable eic
ahbPhase (`EIC_REG_EISMSK_0 << 2, WRITE, HSIZE_X32, 32'h01); //any logical change for irq 1, 2 (pins 0, 1)
ahbPhase (`EIC_REG_EIMSK_0 << 2, WRITE, HSIZE_X32, 32'h05); //enable irq 1, 2 (pins 0, 1)
ahbPhase (`EIC_REG_EIMSK_1 << 2, WRITE, HSIZE_X32, 32'h03); //enable irq 33 (pin 32)
ahbPhase (`EIC_REG_EICR << 2, READ, HSIZE_X32, 32'h01); //enable irq 33 (pin 32)
ahbPhase (`EIC_REG_EISMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_0 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIMSK_1 << 2, READ, HSIZE_X32, St_x);
@(posedge HCLK); signal[0] = 1'b1;
@(posedge HCLK); signal[1] = 1'b1;
delay();
@(posedge HCLK); signal[32] = 1'b1;
@(posedge HCLK); signal[32] = 1'b0;
delay();
ahbPhase (`EIC_REG_EIFR_1 << 2, READ, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFRC_1 << 2, WRITE, HSIZE_X32, St_x); //clear irq 33 (pin 32)
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01);
delay();
ahbPhase (`EIC_REG_EIFR_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h01); //set EIFR word0
delay();
ahbPhase (`EIC_REG_EIFRS_0 << 2, WRITE, HSIZE_X32, St_x);
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, 32'h04); //set EIFR bit3
ahbPhase (`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
ahbPhaseLst(`EIC_REG_EIFR_0 << 2, READ, HSIZE_X32, St_x);
delay();
end
$stop;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; string rev(string s) { string p; for (auto i : s) p.insert(0, 1, i); return p; } int main() { cin >> s; int n = s.size(); for (int i = 0; i <= s.size(); i++) for (int j = 0; j < 26; j++) { string p = s; p.insert(i, 1, j + a ); if (p == rev(p)) return cout << p, 0; } cout << NA ; }
|
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 7; bool pri(int a) { if (a == 1) return 0; for (int i = 2; i * i <= a; i++) { if (a % i == 0) { return 0; } } return 1; } long long n, m, t, a[200000]; string s; int main() { cin >> t; while (t--) { long long x, y; cin >> x >> y; if (x > y) { cout << x + y << n ; continue; } if (x == y) { cout << x << n ; continue; } if (2 * x >= y) { cout << (x + y) / 2 << n ; continue; } x = x * int(y / x); cout << (x + y) / 2 << n ; } return 0; }
|
#include <bits/stdc++.h> const int maxn = 2e5 + 50; using namespace std; int n; long long a[maxn], dp[maxn], he[maxn]; vector<int> maps[maxn]; void dfs(int u, int fa) { he[u] = 0; for (int i = 0, len = maps[u].size(); i < len; i++) { int v = maps[u][i]; if (v != fa) { dfs(v, u); dp[u] += dp[v] + he[v]; he[u] += he[v]; } } he[u] += a[u]; } long long ans; void dfs1(int u, int fa) { for (int i = 0, len = maps[u].size(); i < len; i++) { int v = maps[u][i]; if (v != fa) { dp[v] = dp[u] - he[v] + he[1] - he[v]; ans = max(ans, dp[v]); dfs1(v, u); } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1, a, b; i < n; i++) { scanf( %d%d , &a, &b); maps[a].push_back(b); maps[b].push_back(a); } dfs(1, 1); ans = dp[1]; dfs1(1, 1); printf( %lld n , ans); return 0; }
|
module DM9000A_IF( // HOST Side
iDATA,
oDATA,
iCMD,
iRD_N,
iWR_N,
iCS_N,
iRST_N,
iCLK,
iOSC_50,
oINT,
// DM9000A Side
ENET_DATA,
ENET_CMD,
ENET_RD_N,
ENET_WR_N,
ENET_CS_N,
ENET_RST_N,
ENET_INT,
ENET_CLK );
// HOST Side
input [15:0] iDATA;
input iCMD;
input iRD_N;
input iWR_N;
input iCS_N;
input iRST_N;
input iCLK;
input iOSC_50;
output [15:0] oDATA;
output oINT;
// DM9000A Side
inout [15:0] ENET_DATA;
output ENET_CMD;
output ENET_RD_N;
output ENET_WR_N;
output ENET_CS_N;
output ENET_RST_N;
output ENET_CLK;
input ENET_INT;
reg [15:0] TMP_DATA;
reg ENET_CMD;
reg ENET_RD_N;
reg ENET_WR_N;
reg ENET_CS_N;
reg ENET_CLK;
reg [15:0] oDATA;
reg oINT;
assign ENET_DATA = ENET_WR_N ? 16'hzzzz : TMP_DATA;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
TMP_DATA <= 0;
ENET_CMD <= 0;
ENET_RD_N <= 1;
ENET_WR_N <= 1;
ENET_CS_N <= 1;
oDATA <= 0;
oINT <= 0;
end
else
begin
oDATA <= ENET_DATA;
oINT <= ENET_INT;
TMP_DATA <= iDATA;
ENET_CMD <= iCMD;
ENET_CS_N <= iCS_N;
ENET_RD_N <= iRD_N;
ENET_WR_N <= iWR_N;
end
end
always@(posedge iOSC_50)
ENET_CLK <= ~ENET_CLK;
assign ENET_RST_N = iRST_N;
endmodule
|
`include "assert.vh"
`include "SuperStack.vh"
module SuperStack_tb();
parameter WIDTH = 8;
parameter DEPTH = 1; // frames (exponential)
localparam MAX_STACK = (1 << DEPTH+1) - 1;
reg clk = 0;
reg reset;
reg [ 2:0] op;
reg [WIDTH-1:0] data;
reg [DEPTH :0] offset;
reg [DEPTH :0] underflow_limit=0;
reg [DEPTH :0] upper_limit=0;
wire [DEPTH :0] index;
wire [WIDTH-1:0] out;
wire [WIDTH-1:0] out1;
wire [WIDTH-1:0] out2;
wire [WIDTH-1:0] getter;
wire [ 1:0] status;
wire [ 1:0] error;
SuperStack #(
.WIDTH(WIDTH),
.DEPTH(DEPTH),
.ZEROED_SLICES(1)
)
dut(
.clk(clk),
.reset(reset),
.op(op),
.data(data),
.offset(offset),
.underflow_limit(underflow_limit),
.upper_limit(upper_limit),
.lower_limit(2'b0),
.dropTos(1'b0),
.index(index),
.out(out),
.out1(out1),
.out2(out2),
.getter(getter),
.status(status),
.error(error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("SuperStack_tb.vcd");
$dumpvars(0, SuperStack_tb);
// `status` is `empty` by default
`assert(status, `EMPTY);
// Underflow
op <= `POP;
data <= 0;
#2
`assert(error, `UNDERFLOW);
// Push
op <= `PUSH;
data <= 0;
#2
`assert(status, `NONE);
`assert(out , 8'h00);
op <= `PUSH;
data <= 1;
#2
`assert(status, `NONE);
`assert(out , 8'h01);
`assert(out1 , 8'h00);
op <= `PUSH;
data <= 2;
#2
`assert(status, `FULL);
`assert(out , 8'h02);
`assert(out1 , 8'h01);
`assert(out2 , 8'h00);
// Top of Stack
op <= `NONE;
#2
`assert(status, `FULL);
`assert(out , 8'h02);
`assert(out1 , 8'h01);
`assert(out2 , 8'h00);
// Overflow
op <= `PUSH;
data <= 3;
#2
`assert(error, `OVERFLOW);
`assert(out , 8'h02);
`assert(out1 , 8'h01);
`assert(out2 , 8'h00);
// Pop
op <= `POP;
data <= 0;
#2
`assert(status, `NONE);
`assert(out , 8'h01);
`assert(out1 , 8'h00);
op <= `POP;
data <= 0;
#2
`assert(status, `NONE);
`assert(out , 8'h00);
op <= `POP;
data <= 0;
#2
`assert(status, `EMPTY);
// Replace
op <= `REPLACE;
data <= 4;
#2
`assert(error, `UNDERFLOW);
op <= `PUSH;
data <= 5;
#2
`assert(status, `NONE);
`assert(out , 8'h05);
op <= `REPLACE;
data <= 6;
#2
`assert(status, `NONE);
`assert(out , 8'h06);
op <= `NONE;
#2
`assert(status, `NONE);
`assert(out , 8'h06);
// Reset
reset <= 1;
#2
reset <= 0;
`assert(status, `EMPTY);
`assert(index , 0);
//
// Underflow limit
//
// Underflow after change limit
op <= `NONE;
underflow_limit <= 1;
#2
`assert(status, `UNDERFLOW);
// `assert(out , 8'h06);
`assert(index , 0);
// Push data while we are under the underflow limit...
// and get an empty stack! Magic! :-P
op <= `PUSH;
data <= 8;
#2
`assert(status, `EMPTY);
`assert(out , 8'h08);
`assert(index , 1);
// Reset with underflow limit set
op <= `PUSH;
data <= 9;
#2
`assert(status, `NONE);
`assert(out , 8'h09);
`assert(out1 , 8'h08);
`assert(index , 2);
op <= `INDEX_RESET;
offset <= 1;
#2
`assert(status, `EMPTY);
`assert(out , 8'h08);
`assert(index , 1);
// Get underflow error when underflow limit is not zero (data is protected)
op <= `POP;
data <= 0;
#2
op <= `NONE;
`assert(error, `UNDERFLOW);
`assert(out , 8'h08);
`assert(index, 1);
// Reset underflow limit, and now we can access the data
underflow_limit <= 0;
#2
`assert(status, `NONE);
`assert(out , 8'h08);
`assert(index , 1);
// Get empty when index get zero
op <= `POP;
data <= 0;
#2
`assert(status, `EMPTY);
`assert(index , 0);
// Underflow reset push
op <= `INDEX_RESET_AND_PUSH;
data <= 10;
underflow_limit <= 2;
offset <= 0;
#2
`assert(status, `UNDERFLOW);
`assert(out , 8'h0a);
`assert(index , 1);
op <= `INDEX_RESET_AND_PUSH;
data <= 11;
underflow_limit <= 0;
#2
`assert(status, `NONE);
`assert(out , 8'h0b);
`assert(index , 1);
// Underfow set
op <= `UNDERFLOW_SET;
data <= 12;
underflow_limit <= 1;
offset <= 0;
#2
`assert(error, `BAD_OFFSET);
`assert(out , 8'h0b);
`assert(index, 1);
upper_limit <= 1;
#2
`assert(status, `EMPTY);
`assert(out , 8'h0c);
`assert(index , 1);
op <= `NONE;
#2
`assert(status, `EMPTY);
`assert(index , 1);
op <= `PUSH;
data <= 13;
#2
`assert(status, `NONE);
`assert(out , 8'h0d);
`assert(index , 2);
// Underfow get
offset <= 0;
op <= `UNDERFLOW_GET;
#2
`assert(status, `NONE);
`assert(getter, 8'h0c);
`assert(index , 2);
offset <= 1;
op <= `UNDERFLOW_GET;
#2
`assert(error, `BAD_OFFSET);
`assert(index, 2);
// Reset index over current one and fill with zeroes
op <= `INDEX_RESET;
offset <= 3;
#2
`assert(status, `FULL);
`assert(out , 8'h00);
`assert(out1 , 8'h0d);
`assert(out2 , 8'h0c);
`assert(index , 3);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> ostream &operator<<(ostream &out, const pair<T, U> &p) { out << ( << p.first << , << p.second << ) ; return out; } template <template <typename, typename...> class ContainerType, typename ValueType, typename... Args> void print(const ContainerType<ValueType, Args...> &c) { for (const auto &v : c) cout << v << ; cout << n ; } void print() { cout << n ; } template <typename T, typename... Args> void print(T a, Args... args) { cout << a << ; print(args...); } long long llipower(long long x, long long y, long long p = LLONG_MAX) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int main() { int t; cin >> t; while (t--) { int x, y, z; cin >> x >> y >> z; if (x == y && x >= z) { cout << YES << n ; print(x, 1, z); } else if (y == z && y >= x) { cout << YES << n ; print(1, x, y); } else if (z == x && x >= y) { cout << YES << n ; print(1, x, y); } else { cout << NO << n ; } } }
|
// oversampling.v
module oversampling
(
input [7:0]sclk,
input sdata,
output [7:0]samples,
output reg [7:0]trans
);
reg [7:0]s1; // fixed position in FPGA
always @(posedge sclk[0]) s1[0] <= sdata;
always @(posedge sclk[1]) s1[1] <= sdata;
always @(posedge sclk[2]) s1[2] <= sdata;
always @(posedge sclk[3]) s1[3] <= sdata;
always @(posedge sclk[4]) s1[4] <= sdata;
always @(posedge sclk[5]) s1[5] <= sdata;
always @(posedge sclk[6]) s1[6] <= sdata;
always @(posedge sclk[7]) s1[7] <= sdata;
reg [7:0]s2; // fixed position in FPGA
always @(posedge sclk[0]) s2[0] <= s1[0];
always @(posedge sclk[0]) s2[1] <= s1[1];
always @(posedge sclk[0]) s2[2] <= s1[2];
always @(posedge sclk[0]) s2[3] <= s1[3];
always @(posedge sclk[0]) s2[4] <= s1[4];
always @(posedge sclk[1]) s2[5] <= s1[5];
always @(posedge sclk[2]) s2[6] <= s1[6];
always @(posedge sclk[3]) s2[7] <= s1[7];
reg [7:0]s3;
reg [7:0]s4;
always @(posedge sclk[0])
begin
s3 <= s2;
s4 <= s3;
end
assign samples = s4;
// xor transition detector
wire [7:0]t;
assign t[0] = s3[0] ^ s3[1];
assign t[1] = s3[1] ^ s3[2];
assign t[2] = s3[2] ^ s3[3];
assign t[3] = s3[3] ^ s3[4];
assign t[4] = s3[4] ^ s3[5];
assign t[5] = s3[5] ^ s3[6];
assign t[6] = s3[6] ^ s3[7];
assign t[7] = s3[7] ^ s2[0];
always @(posedge sclk[0]) trans <= t;
endmodule
|
// nios_system_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 189
`timescale 1 ps / 1 ps
module nios_system_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, i = 0; cin >> n; for (i = n + 1; i <= (2 * n); i++) cout << i << ; return (0); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; vector<string> v(n); for (auto& i : v) cin >> i; bool state = true; for (int i = n - 2; i >= 0; i--) { for (int j = n - 2; j >= 0; --j) { if (v[i][j] == 1 && v[i + 1][j] == 0 && v[i][j + 1] == 0 ) state = false; } } if (state) cout << Yes << n ; else cout << No << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int cnt[4]; int main() { int n; scanf( %d , &n); getchar(); for (int i = 0; i < n; ++i) { char ch = getchar(); if (ch == A ) { ++cnt[0]; } else if (ch == C ) { ++cnt[1]; } else if (ch == G ) { ++cnt[2]; } else if (ch == T ) { ++cnt[3]; } } int mx = *max_element(cnt, cnt + 4); int nMax = count(cnt, cnt + 4, mx); long long ans = 1; for (int i = 0; i < n; ++i) { ans = (ans * nMax) % mod; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int a, b, c, d, e, y = 0, x = 0, l = 0, z = 0, k = 0, m = 0; cin >> a >> b >> c >> d >> e; if (d > e) { while (a > 1 && b > 0) { y++; a = a - 2; b = b - 1; } while (a > 1 && c > 0) { x++; a = a - 2; c = c - 1; } l = (d * y) + (x * e); cout << l << endl; } else { while (a > 1 && c > 0) { z++; a = a - 2; c = c - 1; } while (a > 1 && b > 0) { k++; a = a - 2; b = b - 1; } m = (e * z) + (k * d); cout << m << endl; } y = 0, x = 0, l = 0, z = 0, k = 0, m = 0; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Mauricio Carvajal Delgado
//
// Create Date: 03.17.2013 10:36:22
// Design Name:
// Module Name: Uart
// Project Name:
// Target Devices:
// Tool versions:
// Description: Interfaz UART
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_UART #(parameter W = 32, parameter EW = 8, parameter SW = 23, parameter SWR=26, parameter EWR = 5)(//-- Single Precision*/
/*#(parameter W = 64, parameter EW = 11, parameter SW = 52, parameter SWR = 55, parameter EWR = 6) //-- Double Precision */
input wire clk,
input wire rst,
output wire TX
);
//local parameters
//localparam shift_region = 2'b00;
localparam N = 2; //2 para 32 bits, 3 para 64 bits
//localparam op = 1'b1;
localparam d = 0;
//signal declaration
wire ready_op;
wire max_tick_address;
wire max_tick_ch;
wire TX_DONE;
wire beg_op;
wire ack_op;
wire load_address;
wire enab_address;
wire enab_ch;
wire load_ch;
wire TX_START;
wire [W-1:0] data_cordic;
wire [W-1:0] data_cordic_out;
wire [7:0] TX_DATA;
wire [9:0] cont_address_sig;
wire [N-1:0] cont_ch;
wire OR;
assign OR = rst | ack_op;
FSM_test fsm_test_uart(
.clk(clk),
.rst(rst),
.ready_op(ready_op),
.max_tick_address(max_tick_address),
.max_tick_ch(max_tick_ch),
.TX_DONE(TX_DONE),
.beg_op(beg_op),
.ack_op(ack_op),
.load_address(load_address),
.enab_address(enab_address),
.enab_ch(enab_ch),
.load_ch(load_ch),
.TX_START(TX_START)
);
LINEALIZADOR_NORMALIZADOR L_N(
.CLK(clk), //SYSTEM CLOCK
.I(data_cordic), //VALOR DEL ARGUMENTO DEL LOGARITMO QUE SE DESEA CALCULAR I
//.V(data_cordic), //VALOR DEL ARGUMENTO DE V PARA CONVERSION FLOTANTE A FIJO
.RST_LN_FF(OR), //SYSTEM RESET
.Begin_FSM_I(beg_op), //INICIA FSM I
//.Begin_FSM_V(beg_op), //INICIA FSM V
.ACK_I(ready_op), //INDICA QUE EL CALCULO FUE REALIZADO I
//.ACK_V(ready_op), //INDICA QUE EL CALCULO FUE REALIZADO V
.RESULT_I(data_cordic_out) //RESULTADO FINAL I
//.RESULT_V(data_cordic_out) //RESULTADO FINAL V
);
Uart uart_mod(
.RST(rst),
.CLK(clk),
.TX_START(TX_START),
.TX_DATA(TX_DATA),
.TX(TX),
.TX_DONE(TX_DONE)
);
ROM_test #(.W(W)) rom_test_uart(
.address(cont_address_sig),
.data(data_cordic)
);
cont_test #(.W(10)) cont_address(
.clk(clk),
.rst(rst),
.load(load_address),
.enable(enab_address),
.d(d),
.max_tick(max_tick_address),
.q(cont_address_sig)
);
cont_test #(.W(N)) con_mux_data(
.clk(clk),
.rst(rst),
.load(load_ch),
.enable(enab_ch),
.d(d),
.max_tick(max_tick_ch),
.q(cont_ch)
);
generate
case(W)
32:
begin
Mux_4x1 mux_32_uart
(
.select(cont_ch),
.ch_0(data_cordic_out[7:0]),
.ch_1(data_cordic_out[15:8]),
.ch_2(data_cordic_out[23:16]),
.ch_3(data_cordic_out[31:24]),
.data_out(TX_DATA)
);
end
64:
begin
Mux_8x1 mux_64_uart
(
.select(cont_ch),
.ch_0(data_cordic_out[7:0]),
.ch_1(data_cordic_out[15:8]),
.ch_2(data_cordic_out[23:16]),
.ch_3(data_cordic_out[31:24]),
.ch_4(data_cordic_out[39:32]),
.ch_5(data_cordic_out[47:40]),
.ch_6(data_cordic_out[55:48]),
.ch_7(data_cordic_out[63:56]),
.data_out(TX_DATA)
);
end
default:
begin
Mux_4x1 mux_32_uart
(
.select(cont_ch),
.ch_0(data_cordic_out[7:0]),
.ch_1(data_cordic_out[15:8]),
.ch_2(data_cordic_out[23:16]),
.ch_3(data_cordic_out[31:24]),
.data_out(TX_DATA)
);
end
endcase
endgenerate
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_phy_dm_iob.v
// /___/ /\ Date Last Modified: $Date: 2008/12/23 14:26:00 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module places the data mask signals into the IOBs.
//Reference:
//Revision History:
// Rev 1.1 - To fix timing issues with Synplicity 9.6.1, syn_preserve
// attribute added for the instance u_dm_ce. PK. 11/11/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_dm_iob
(
input clk90,
input dm_ce,
input mask_data_rise,
input mask_data_fall,
output ddr_dm
);
wire dm_out;
wire dm_ce_r;
FDRSE_1 u_dm_ce
(
.Q (dm_ce_r),
.C (clk90),
.CE (1'b1),
.D (dm_ce),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve=1 */;
ODDR #
(
.SRTYPE("SYNC"),
.DDR_CLK_EDGE("SAME_EDGE")
)
u_oddr_dm
(
.Q (dm_out),
.C (clk90),
.CE (dm_ce_r),
.D1 (mask_data_rise),
.D2 (mask_data_fall),
.R (1'b0),
.S (1'b0)
);
OBUF u_obuf_dm
(
.I (dm_out),
.O (ddr_dm)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int N = 1e6 + 100; int n, m, q; struct Qu { int op, x; } qu[N]; struct Edge { int u, v, w; bool operator<(const Edge& t) const { return w < t.w; } } edge[N]; struct Max { int val, pos; Max() {} Max(int val, int pos) : val(val), pos(pos) {} static Max inf() { return Max(-0x3f3f3f3f, 0); } bool operator<(const Max& t) const { return val < t.val; } }; struct Node { int l, r; Max mmax; } tree[N << 2]; int a[N], f[N], val[N], dp[N][25], L[N], R[N], id[N], tot; vector<int> node[N]; void pushup(int k) { tree[k].mmax = max(tree[k << 1].mmax, tree[k << 1 | 1].mmax); } void build(int k, int l, int r) { tree[k].l = l; tree[k].r = r; if (l == r) { tree[k].mmax.val = a[id[l]]; tree[k].mmax.pos = l; return; } int mid = l + r >> 1; build(k << 1, l, mid); build(k << 1 | 1, mid + 1, r); pushup(k); } void update(int k, int pos) { if (tree[k].l == tree[k].r) { tree[k].mmax.val = 0; return; } int mid = tree[k].l + tree[k].r >> 1; if (pos <= mid) update(k << 1, pos); else update(k << 1 | 1, pos); pushup(k); } Max query(int k, int l, int r) { if (tree[k].l > r || tree[k].r < l) return Max::inf(); if (tree[k].l >= l && tree[k].r <= r) return tree[k].mmax; return max(query(k << 1, l, r), query(k << 1 | 1, l, r)); } void dfs(int u, int fa) { dp[u][0] = fa; for (int i = 1; i <= 20; i++) dp[u][i] = dp[dp[u][i - 1]][i - 1]; L[u] = ++tot; id[tot] = u; for (auto v : node[u]) dfs(v, u); R[u] = tot; } int get_pos(int u, int up) { for (int i = 20; i >= 0; i--) if (dp[u][i] != 0 && val[dp[u][i]] <= up) u = dp[u][i]; return u; } int find(int x) { return f[x] == x ? x : f[x] = find(f[x]); } int Ex_Kruskal() { for (int i = 1; i <= n << 1; i++) f[i] = i; int index = n; sort(edge + 1, edge + 1 + m); for (int i = 1; i <= m; i++) { int xx = find(edge[i].u), yy = find(edge[i].v); if (xx != yy) { f[xx] = f[yy] = ++index; val[index] = edge[i].w; node[index].push_back(xx); node[index].push_back(yy); } } int last = 1; for (int i = 1; i <= n; i++) { int xx = find(last), yy = find(i); if (xx != yy) { f[xx] = f[yy] = ++index; val[index] = inf; node[index].push_back(xx); node[index].push_back(yy); last = index; } } return index; } int main() { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= m; i++) { scanf( %d%d , &edge[i].u, &edge[i].v); edge[i].w = 0; } int val = inf; for (int i = 1; i <= q; i++) { scanf( %d%d , &qu[i].op, &qu[i].x); if (qu[i].op == 2) edge[qu[i].x].w = --val; } int root = Ex_Kruskal(); dfs(root, 0); build(1, 1, root); val = inf - 1; for (int i = 1; i <= q; i++) { if (qu[i].op == 1) { int x = get_pos(qu[i].x, val); Max ans = query(1, L[x], R[x]); printf( %d n , ans.val); update(1, ans.pos); } else val--; } return 0; }
|
// $Id: vcr_routing_logic.v 2039 2010-05-19 06:51:53Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// routing logic for VC router
module vcr_routing_logic
(clk, reset, router_address, sel_rc, route_info, route_op, inc_rc);
`include "c_functions.v"
`include "c_constants.v"
// nuber of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// number of dimensions in network
parameter num_dimensions = 2;
// width required to select individual router in network
localparam router_addr_width = num_dimensions * dim_addr_width;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 1;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// select routing function type
parameter routing_type = `ROUTING_TYPE_DOR;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// total number of bits required for storing routing information
localparam route_info_width
= num_resource_classes * router_addr_width + node_addr_width;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// current router's address
input [0:router_addr_width-1] router_address;
// select current resource class
input [0:num_resource_classes-1] sel_rc;
// routing data
input [0:route_info_width-1] route_info;
// output port to forward to
output [0:num_ports-1] route_op;
wire [0:num_ports-1] route_op;
// if we have reached our destination for the current resource class,
// increment the resource class (unless it's already the highest)
output inc_rc;
wire inc_rc;
// all router addresses (intermediate + final)
wire [0:num_resource_classes*router_addr_width-1] route_info_addresses;
assign route_info_addresses
= route_info[0:num_resource_classes*router_addr_width-1];
// address of destination router for current resource class
wire [0:router_addr_width-1] dest_router_address;
c_select_1ofn
#(.width(router_addr_width),
.num_ports(num_resource_classes))
dest_router_address_sel
(.select(sel_rc),
.data_in(route_info_addresses),
.data_out(dest_router_address));
wire reached_dest;
assign reached_dest = (router_address == dest_router_address);
wire final_rc;
assign final_rc = sel_rc[num_resource_classes-1];
assign inc_rc = reached_dest & ~final_rc;
wire [0:num_dimensions-1] dim_addr_match;
generate
case(routing_type)
`ROUTING_TYPE_DOR:
begin
genvar dim;
for(dim = 0; dim < num_dimensions; dim = dim + 1)
begin:dims
wire [0:dim_addr_width-1] dest_dim_addr;
assign dest_dim_addr
= dest_router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
wire [0:dim_addr_width-1] local_dim_addr;
assign local_dim_addr
= router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
assign dim_addr_match[dim]
= (dest_dim_addr == local_dim_addr);
wire dim_sel;
case(dim_order)
`DIM_ORDER_ASCENDING:
begin
if(dim == 0)
assign dim_sel = ~dim_addr_match[dim];
else
assign dim_sel = &dim_addr_match[0:dim-1] &
~dim_addr_match[dim];
end
`DIM_ORDER_DESCENDING:
begin
if(dim == (num_dimensions - 1))
assign dim_sel = ~dim_addr_match[dim];
else
assign dim_sel = ~dim_addr_match[dim] &
dim_addr_match[(dim+1):
(num_dimensions-1)];
end
endcase
wire [0:num_neighbors_per_dim-1] port_dec;
case(connectivity)
`CONNECTIVITY_LINE:
begin
assign port_dec
= {dest_dim_addr < local_dim_addr,
dest_dim_addr > local_dim_addr};
end
`CONNECTIVITY_RING:
begin
// FIXME: add implementation here!
// synopsys translate_off
initial
begin
$display({"ERROR: The routing logic module %m ",
"does not yet support ring ",
"connectivity within each dimension."});
$stop;
end
// synopsys translate_on
end
`CONNECTIVITY_FULL:
begin
wire [0:num_routers_per_dim-1] dest_dim_addr_dec;
c_decoder
#(.num_ports(num_routers_per_dim))
dest_dim_addr_dec_dec
(.data_in(dest_dim_addr),
.data_out(dest_dim_addr_dec));
wire [0:(2*num_routers_per_dim-1)-1]
dest_dim_addr_dec_repl;
assign dest_dim_addr_dec_repl
= {dest_dim_addr_dec,
dest_dim_addr_dec[0:(num_routers_per_dim-1)-1]};
assign port_dec
= dest_dim_addr_dec_repl[(local_dim_addr+1) +:
num_neighbors_per_dim];
end
endcase
assign route_op[dim*num_neighbors_per_dim:
(dim+1)*num_neighbors_per_dim-1]
= port_dec & {num_neighbors_per_dim{dim_sel}};
end
end
endcase
if(num_nodes_per_router > 1)
begin
wire [0:node_addr_width-1] dest_node_address;
assign dest_node_address
= route_info[route_info_width-node_addr_width:route_info_width-1];
wire [0:num_nodes_per_router-1] node_sel;
c_decoder
#(.num_ports(num_nodes_per_router))
node_sel_dec
(.data_in(dest_node_address),
.data_out(node_sel));
assign route_op[num_ports-num_nodes_per_router:num_ports-1]
= node_sel &
{num_nodes_per_router{&dim_addr_match & final_rc}};
end
else
assign route_op[num_ports-1] = &dim_addr_match & final_rc;
endgenerate
endmodule
|
`timescale 1ns / 1ps
/*
* File : Hazard_Detection.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers ()
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 23-Jul-2011 GEA Initial design.
* 2.0 26-May-2012 GEA Release version with CP0.
* 2.01 1-Nov-2012 GEA Fixed issue with Jal.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* Hazard Detection and Forward Control. This is the glue that allows a
* pipelined processor to operate efficiently and correctly in the presence
* of data, structural, and control hazards. For each pipeline stage, it
* detects whether that stage requires data that is still in the pipeline,
* and whether that data may be forwarded or if the pipeline must be stalled.
*
* This module is heavily commented. Read below for more information.
*/
module Hazard_Detection(
input [7:0] DP_Hazards,
input [4:0] ID_Rs,
input [4:0] ID_Rt,
input [4:0] EX_Rs,
input [4:0] EX_Rt,
input [4:0] EX_RtRd,
input [4:0] MEM_RtRd,
input [4:0] WB_RtRd,
input EX_Link,
input EX_RegWrite,
input MEM_RegWrite,
input WB_RegWrite,
input MEM_MemRead,
input MEM_MemWrite, // Needed for Store Conditional which writes to a register
input InstMem_Read,
input InstMem_Ready,
input Mfc0, // Using fwd mux; not part of haz/fwd.
input IF_Exception_Stall,
input ID_Exception_Stall,
input EX_Exception_Stall,
input EX_ALU_Stall,
input M_Stall_Controller, // Determined by data memory controller
output IF_Stall,
output ID_Stall,
output EX_Stall,
output M_Stall,
output WB_Stall,
output [1:0] ID_RsFwdSel,
output [1:0] ID_RtFwdSel,
output [1:0] EX_RsFwdSel,
output [1:0] EX_RtFwdSel,
output M_WriteDataFwdSel
);
/* Hazard and Forward Detection
*
* Most instructions read from one or more registers. Normally this occurs in
* the ID stage. However, frequently the register file in the ID stage is stale
* when one or more forward stages in the pipeline (EX, MEM, or WB) contains
* an instruction which will eventually update it but has not yet done so.
*
* A hazard condition is created when a forward pipeline stage is set to write
* the same register that a current pipeline stage (e.g. in ID) needs to read.
* The solution is to stall the current stage (and effectively all stages behind
* it) or bypass (forward) the data from forward stages. Fortunately forwarding
* works for most combinations of instructions.
*
* Hazard and Forward conditions are handled based on two simple rules:
* "Wants" and "Needs." If an instruction "wants" data in a certain pipeline
* stage, and that data is available further along in the pipeline, it will
* be forwarded. If it "needs" data and the data is not yet available for forwarding,
* the pipeline stage stalls. If it does not want or need data in a certain
* stage, forwarding is disabled and a stall will not occur. This is important
* for instructions which insert custom data, such as jal or movz.
*
* Currently, "Want" and "Need" conditions are defined for both Rs data and Rt
* data (the two read registers in MIPS), and these conditions exist in the
* ID and EX pipeline stages. This is a total of eight condition bits.
*
* A unique exception exists with Store instructions, which don't need the
* "Rt" data until the MEM stage. Because data doesn't change in WB, and WB
* is the only stage following MEM, forwarding is *always* possible from
* WB to Mem. This unit handles this situation, and a condition bit is not
* needed.
*
* When data is needed from the MEM stage by a previous stage (ID or EX), the
* decision to forward or stall is based on whether MEM is accessing memory
* (stall) or not (forward). Normally store instructions don't write to registers
* and thus are never needed for a data dependence, so the signal 'MEM_MemRead'
* is sufficient to determine. Because of the Store Conditional instruction,
* however, 'MEM_MemWrite' must also be considered because it writes to a register.
*
*/
wire WantRsByID, NeedRsByID, WantRtByID, NeedRtByID, WantRsByEX, NeedRsByEX, WantRtByEX, NeedRtByEX;
assign WantRsByID = DP_Hazards[7];
assign NeedRsByID = DP_Hazards[6];
assign WantRtByID = DP_Hazards[5];
assign NeedRtByID = DP_Hazards[4];
assign WantRsByEX = DP_Hazards[3];
assign NeedRsByEX = DP_Hazards[2];
assign WantRtByEX = DP_Hazards[1];
assign NeedRtByEX = DP_Hazards[0];
// Trick allowed by RegDst = 0 which gives Rt. MEM_Rt is only used on
// Data Memory write operations (stores), and RegWrite is always 0 in this case.
wire [4:0] MEM_Rt = MEM_RtRd;
// Forwarding should not happen when the src/dst register is $zero
wire EX_RtRd_NZ = (EX_RtRd != 5'b00000);
wire MEM_RtRd_NZ = (MEM_RtRd != 5'b00000);
wire WB_RtRd_NZ = (WB_RtRd != 5'b00000);
// ID Dependencies
wire Rs_IDEX_Match = (ID_Rs == EX_RtRd) & EX_RtRd_NZ & (WantRsByID | NeedRsByID) & EX_RegWrite;
wire Rt_IDEX_Match = (ID_Rt == EX_RtRd) & EX_RtRd_NZ & (WantRtByID | NeedRtByID) & EX_RegWrite;
wire Rs_IDMEM_Match = (ID_Rs == MEM_RtRd) & MEM_RtRd_NZ & (WantRsByID | NeedRsByID) & MEM_RegWrite;
wire Rt_IDMEM_Match = (ID_Rt == MEM_RtRd) & MEM_RtRd_NZ & (WantRtByID | NeedRtByID) & MEM_RegWrite;
wire Rs_IDWB_Match = (ID_Rs == WB_RtRd) & WB_RtRd_NZ & (WantRsByID | NeedRsByID) & WB_RegWrite;
wire Rt_IDWB_Match = (ID_Rt == WB_RtRd) & WB_RtRd_NZ & (WantRtByID | NeedRtByID) & WB_RegWrite;
// EX Dependencies
wire Rs_EXMEM_Match = (EX_Rs == MEM_RtRd) & MEM_RtRd_NZ & (WantRsByEX | NeedRsByEX) & MEM_RegWrite;
wire Rt_EXMEM_Match = (EX_Rt == MEM_RtRd) & MEM_RtRd_NZ & (WantRtByEX | NeedRtByEX) & MEM_RegWrite;
wire Rs_EXWB_Match = (EX_Rs == WB_RtRd) & WB_RtRd_NZ & (WantRsByEX | NeedRsByEX) & WB_RegWrite;
wire Rt_EXWB_Match = (EX_Rt == WB_RtRd) & WB_RtRd_NZ & (WantRtByEX | NeedRtByEX) & WB_RegWrite;
// MEM Dependencies
wire Rt_MEMWB_Match = (MEM_Rt == WB_RtRd) & WB_RtRd_NZ & WB_RegWrite;
// ID needs data from EX : Stall
wire ID_Stall_1 = (Rs_IDEX_Match & NeedRsByID);
wire ID_Stall_2 = (Rt_IDEX_Match & NeedRtByID);
// ID needs data from MEM : Stall if mem access
wire ID_Stall_3 = (Rs_IDMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRsByID);
wire ID_Stall_4 = (Rt_IDMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRtByID);
// ID wants data from MEM : Forward if not mem access
wire ID_Fwd_1 = (Rs_IDMEM_Match & ~(MEM_MemRead | MEM_MemWrite));
wire ID_Fwd_2 = (Rt_IDMEM_Match & ~(MEM_MemRead | MEM_MemWrite));
// ID wants/needs data from WB : Forward
wire ID_Fwd_3 = (Rs_IDWB_Match);
wire ID_Fwd_4 = (Rt_IDWB_Match);
// EX needs data from MEM : Stall if mem access
wire EX_Stall_1 = (Rs_EXMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRsByEX);
wire EX_Stall_2 = (Rt_EXMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRtByEX);
// EX wants data from MEM : Forward if not mem access
wire EX_Fwd_1 = (Rs_EXMEM_Match & ~(MEM_MemRead | MEM_MemWrite));
wire EX_Fwd_2 = (Rt_EXMEM_Match & ~(MEM_MemRead | MEM_MemWrite));
// EX wants/needs data from WB : Forward
wire EX_Fwd_3 = (Rs_EXWB_Match);
wire EX_Fwd_4 = (Rt_EXWB_Match);
// MEM needs data from WB : Forward
wire MEM_Fwd_1 = (Rt_MEMWB_Match);
// Stalls and Control Flow Final Assignments
assign WB_Stall = M_Stall;
assign M_Stall = IF_Stall | M_Stall_Controller;
assign EX_Stall = (EX_Stall_1 | EX_Stall_2 | EX_Exception_Stall) | EX_ALU_Stall | M_Stall;
assign ID_Stall = (ID_Stall_1 | ID_Stall_2 | ID_Stall_3 | ID_Stall_4 | ID_Exception_Stall) | EX_Stall;
assign IF_Stall = /*InstMem_Read |*/ ~InstMem_Ready | IF_Exception_Stall;
// Forwarding Control Final Assignments
assign ID_RsFwdSel = (ID_Fwd_1) ? 2'b01 : ((ID_Fwd_3) ? 2'b10 : 2'b00);
assign ID_RtFwdSel = (Mfc0) ? 2'b11 : ((ID_Fwd_2) ? 2'b01 : ((ID_Fwd_4) ? 2'b10 : 2'b00));
assign EX_RsFwdSel = (EX_Link) ? 2'b11 : ((EX_Fwd_1) ? 2'b01 : ((EX_Fwd_3) ? 2'b10 : 2'b00));
assign EX_RtFwdSel = (EX_Link) ? 2'b11 : ((EX_Fwd_2) ? 2'b01 : ((EX_Fwd_4) ? 2'b10 : 2'b00));
assign M_WriteDataFwdSel = MEM_Fwd_1;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> thing[20005 * 4], query[20005 * 4]; struct Thing { int cost, happy; } d[20005]; int cost[20005], f[4005], tree[20005 * 4], tmp[16][4005], ans[20005]; int x, i, n, m, p, y; void build1(int k, int l, int r) { if (x <= l && r <= y) { thing[k].push_back(i); return; } int mid = (l + r) >> 1; if (x <= mid) build1(k << 1, l, mid); if (y > mid) build1(k << 1 | 1, mid + 1, r); } void build2(int k, int l, int r) { tree[k] = 1; int mid = (l + r) >> 1; if (l == r) { query[k].push_back(i); return; } if (x <= mid) build2(k << 1, l, mid); else build2(k << 1 | 1, mid + 1, r); } void work(int k, int l, int r, int dep) { if (thing[k].size()) { memcpy(tmp[dep], f, sizeof(f)); for (int i = 0; i < thing[k].size(); i++) { int lose = d[thing[k][i]].cost, win = d[thing[k][i]].happy; for (int j = 4000; j >= lose; j--) f[j] = max(f[j], f[j - lose] + win); } } if (l == r) { for (int i = 0; i < query[k].size(); i++) ans[query[k][i]] = f[cost[query[k][i]]]; if (thing[k].size()) memcpy(f, tmp[dep], sizeof(tmp[dep])); return; } int mid = (l + r) >> 1; work(k << 1, l, mid, dep + 1); work(k << 1 | 1, mid + 1, r, dep + 1); if (thing[k].size()) memcpy(f, tmp[dep], sizeof(tmp[dep])); } int main() { scanf( %d %d , &n, &p); for (i = 1; i <= n; i++) { scanf( %d%d%d , &d[i].cost, &d[i].happy, &x); y = x + p - 1; build1(1, 1, 20000); } scanf( %d , &m); for (i = 1; i <= m; i++) { scanf( %d%d , &x, &cost[i]); build2(1, 1, 20000); } work(1, 1, 20000, 0); for (i = 1; i <= m; i++) printf( %d n , ans[i]); }
|
module random_gen(
input reset,
input clock,
input init,
input [3:0] retry_count,
output reg trigger
);
reg [9:0] random_sequence;
reg [9:0] random;
reg [9:0] random_counter;
reg [7:0] slot_time_counter; //256*2=512bit=1 slot time
always @ (posedge clock or posedge reset)
if (reset)
random_sequence <= 0;
else
random_sequence <= {random_sequence[8:0],~(random_sequence[2]^random_sequence[9])};
always @ (retry_count or random_sequence)
case (retry_count)
4'h0 : random = {9'b0, random_sequence[0]};
4'h1 : random = {8'b0, random_sequence[1:0]};
4'h2 : random = {7'b0, random_sequence[2:0]};
4'h3 : random = {6'b0, random_sequence[3:0]};
4'h4 : random = {5'b0, random_sequence[4:0]};
4'h5 : random = {4'b0, random_sequence[5:0]};
4'h6 : random = {3'b0, random_sequence[6:0]};
4'h7 : random = {2'b0, random_sequence[7:0]};
4'h8 : random = {1'b0, random_sequence[8:0]};
4'h9 : random = { random_sequence[9:0]};
default : random = { random_sequence[9:0]};
endcase
always @ (posedge clock or posedge reset)
if (reset)
slot_time_counter <= 0;
else if(init)
slot_time_counter <= 0;
else if(!trigger)
slot_time_counter <= slot_time_counter + 1;
always @ (posedge clock or posedge reset)
if (reset)
random_counter <= 0;
else if (init)
random_counter <= random;
else if (random_counter != 0 && slot_time_counter == 255)
random_counter <= random_counter - 1;
always @ (posedge clock or posedge reset)
if (reset)
trigger <= 1;
else if (init)
trigger <= 0;
else if (random_counter == 0)
trigger <= 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); long long n; long long m; long long k; cin >> n >> m >> k; vector<long long> p(m); for (long long i = 0; i < m; ++i) { cin >> p[i]; } long long i = 0; long long r = ((p[0] + k - 1) / k) * k; long long cur = 0; long long cnt = 0; long long ans = 0; while (i < m) { if (p[i] - cur > r && i < m) { r = ((p[i] - cur + k - 1) / k) * k; } else { cnt = 0; while (i < m && p[i] - cur <= r) { ++cnt; ++i; } ++ans; cur += cnt; } } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_1_V
`define SKY130_FD_SC_HD__O32AI_1_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32ai_1 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_1_V
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// A qa_wrapper with only the message_stream_combiner.
// The input stream and an empty stream go to the combiner.
module qa_wrapper
#(
parameter WDTH = 32
)
(
input wire clk,
input wire reset,
input wire [WDTH-1:0] in_data,
input wire in_nd,
output wire [WDTH-1:0] out_data,
output wire out_nd
);
reg empty_nd;
reg [WDTH-1:0] empty_data;
wire combiner_error;
initial
begin
empty_nd <= 1'b0;
empty_data <= 12;
end
assign rst_n = ~reset;
message_stream_combiner #(2, 1, WDTH, `COMBINER_BUFFER_LENGTH, `LOG_COMBINER_BUFFER_LENGTH, `MAX_PACKET_LENGTH, `MSG_LENGTH_WIDTH) message_stream_combiner_0
(.clk(clk),
.rst_n(rst_n),
.in_data({in_data, empty_data}),
.in_nd({in_nd, empty_nd}),
.out_data(out_data),
.out_nd(out_nd),
.error(combiner_error)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<string> ans; map<string, int> lo; string s[100], V[55]; long long int n, m, k, done[100], fyes = -1; void give() { string T = abcdef ; do { ans.push_back(T); } while (next_permutation(T.begin(), T.end())); for (int i = 0; i < ans.size(); i++) lo[ans[i]] = i; } int main() { give(); cin >> n >> k; for (int i = 0; i < (n - k + 1); i++) { cin >> s[i]; if (s[i] == YES && fyes == -1) fyes = i; } if (fyes != -1) { for (int i = fyes, j = 0; j < k; i++, j++) V[i] = ans[j]; for (int i = fyes + 1; i < n - k + 1; i++) { if (s[i] == YES ) { V[i + k - 1] = ans[lo[V[i]] + k - 1]; } else { V[i + k - 1] = V[i]; } } for (int i = 0; i < fyes; i++) V[i] = V[fyes]; } else { for (int i = 0; i < n; i++) V[i] = fuchka ; } for (int i = 0; i < n; i++) { V[i][0] = V[i][0] + A - a ; cout << V[i] << ; } }
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[300007]; bool vis[300007]; int Time[300007], timeMin[300007], cnt = 0, res = 0; int dfs(int u, int p) { vis[u] = true; Time[u] = timeMin[u] = cnt++; int ret = 0; vector<int> childList; for (auto child : adj[u]) { if (child == p) { continue; } if (vis[child]) { timeMin[u] = min(timeMin[u], Time[child]); } else { int temp = dfs(child, u); timeMin[u] = min(timeMin[u], timeMin[child]); if (timeMin[child] > Time[u]) { temp++; } ret = max(ret, temp); childList.push_back(temp); } } sort(childList.rbegin(), childList.rend()); if (childList.size() == 1) { res = max(res, childList[0]); } else if (childList.size() > 1) { res = max(res, childList[0] + childList[1]); } return ret; } int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { int u, v; scanf( %d %d , &u, &v); u--; v--; adj[u].emplace_back(v); adj[v].emplace_back(u); } dfs(0, -1); printf( %d n , res); }
|
#include <bits/stdc++.h> using namespace std; char a[2000][1000]; int main() { int n, s; cin >> n; int nowx = 0, nowy = 1000; int miny = 1000, maxy = 1000; for (int i = 0; i < n; i++) { cin >> s; for (int j = nowx; j < nowx + s; j++) if (i % 2 == 0) a[nowy][j] = / , maxy = max(maxy, nowy++); else a[--nowy][j] = , miny = min(miny, nowy); nowx += s; } for (int i = maxy; i >= miny; i--, cout << endl) for (int j = 0; j < nowx; j++) if (a[i][j]) cout << a[i][j]; else cout << ; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC TAGs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of instruction cache tag rams ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_ic_tag.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_ic_tag(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, tag_v, tag
);
parameter dw = `OR1200_ICTAG_W;
parameter aw = `OR1200_ICTAG;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Internal i/f
//
input [aw-1:0] addr;
input en;
input we;
input [dw-1:0] datain;
output tag_v;
output [dw-2:0] tag;
`ifdef OR1200_NO_IC
//
// Insn cache not implemented
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of TAG RAM block
//
or1200_spram #
(
.aw(`OR1200_ICTAG),
.dw(`OR1200_ICTAG_W)
)
ic_tag0
(
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.ce(en),
.we(we),
//.oe(1'b1),
.addr(addr),
.di(datain),
.doq({tag, tag_v})
);
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_2_V
`define SKY130_FD_SC_LS__O41AI_2_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_2 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_2_V
|
#include <vector> #include <array> #include <stack> #include <queue> #include <list> #include <bitset> #include <set> #include <map> #include <unordered_set> #include <unordered_map> #include <algorithm> #include <numeric> #include <iostream> #include <iomanip> #include <string> #include <chrono> #include <random> #include <cmath> #include <cassert> #include <climits> #include <cstring> #include <cstdlib> #include <functional> #include <sstream> using namespace std; const long long MOD = 998244353; vector<vector<int>> matXmat(const vector<vector<int>>& A, const vector<vector<int>>& B, long long M = MOD) { int n = A.size(); assert(n != 0); assert(A[0].size() == B.size()); int l = B.size(); assert(l != 0); int m = B[0].size(); assert(m != 0); vector<vector<int>> res(n, vector<int>(m, 0)); long long MOD2 = M * 1LL * M; for (int i = 0; i < n; ++i) { for (int j = 0; j < l; ++j) { for (int k = 0; k < m; ++k) { res[i][k] += A[i][j] * 1LL * B[j][k] % M; if (res[i][k] >= M) { res[i][k] -= M; } if (res[i][k] < 0) { res[i][k] += M; } } } } return res; } vector<long long> __tmpA(500, 0); vector<vector<int>> matXmat2(const vector<vector<int>>& A, const vector<vector<int>>& B, long long M = MOD) { int n = A.size(); assert(n != 0); assert(A[0].size() == B.size()); int l = B.size(); assert(l != 0); int m = B[0].size(); assert(m != 0); vector<vector<int>> res(n, vector<int>(m, 0)); long long MOD2 = M * 1LL * M; for (int i = 0; i < n; ++i) { for (int k = 0; k < m; ++k) { __tmpA[k] = 0; } for (int j = 0; j < l; ++j) { for (int k = 0; k < m; ++k) { __tmpA[k] += A[i][j] * 1LL * B[j][k]; if (__tmpA[k] >= MOD2) { __tmpA[k] -= MOD2; } } } for (int k = 0; k < m; ++k) { if (__tmpA[k] >= MOD) { res[i][k] = __tmpA[k] % MOD; } else { res[i][k] = __tmpA[k]; } } } return res; } vector<int> matXvec(const vector<vector<int>>& A, const vector<int>& B, long long M = MOD) { int n = A.size(); assert(n != 0); int m = A[0].size(); assert(m == B.size()); vector<int> res(n, 0); long long MOD2 = M * 1LL * M; for (int i = 0; i < n; ++i) { long long ans = 0; for (int j = 0; j < m; ++j) { ans += A[i][j] * 1LL * B[j]; if (ans >= MOD2) { ans -= MOD2; } if (ans < 0) { ans += MOD2; } } ans %= M; if (ans < 0) { ans += M; } res[i] = ans; } return res; } vector<vector<int>> matPow(vector<vector<int>> A, long long n, long long M = MOD) { int m = A.size(); assert(m != 0 && A[0].size() == m); vector<vector<int>> res(m, vector<int>(m, 0)); for (int i = 0; i < m; ++i) { res[i][i] = 1; } while (n > 0) { if (n & 1) { res = matXmat2(res, A, M); } A = matXmat2(A, A, M); n >>= 1; } return res; } class Trie{ public: Trie(int n = 110000) : N(n), nodes(n), rt(-1), idx(-1) { rt = newNode(); } void reset() { for (int i = 0; i <= idx; ++i) { nodes[i].reset(); } idx = -1; rt = newNode(); } int root() { return rt; } int index(char ch) { return ch - a ; } void insert(string& s) { int cur = rt; for (auto c : s) { c = index(c); if (nodes[cur].nexts[c] == -1) { nodes[cur].nexts[c] = newNode(); } cur = nodes[cur].nexts[c]; nodes[cur].cnt += 1; } nodes[cur].isEnd = true; } bool query(string& s) { int cur = rt; for (auto c : s) { c = index(c); if (nodes[cur].nexts[c] == -1) { return false; } cur = nodes[cur].nexts[c]; } return nodes[cur].isEnd; } int next(int r, char ch) { ch = index(ch); return nodes[r].nexts[ch]; } bool isEnd(int u) { return nodes[u].isEnd; } private: const static int A = 26; struct Node { Node() : cnt(0), isEnd(false) { fill(begin(nexts), end(nexts), -1); } void reset() { cnt = 0; isEnd = false; fill(begin(nexts), end(nexts), -1); } int nexts[A]; int cnt; bool isEnd; }; int N; int rt; int idx; vector<Node> nodes; int newNode() { return ++idx; } }; class Solution { public: long long solve(vector<string>& S, int m) { int n = S.size(); Trie tr(2000); for (auto s : S) { tr.insert(s); } const int N = 100; vector<vector<vector<pair<int,int>>>> nexts(N, vector<vector<pair<int,int>>>(N)); int rt = tr.root(); vector<pair<int,int>> que; que.emplace_back(rt, rt); vector<vector<bool>> ok(N, vector<bool>(N, false)); ok[rt][rt] = true; vector<vector<bool>> visited(N, vector<bool>(N, false)); visited[rt][rt] = true; for (int i = 0; i < que.size(); ++i) { int u = que[i].first, v = que[i].second; for (int j = a ; j <= z ; ++j) { int nu = tr.next(u, j); int nv = tr.next(v, j); if (nu < 0 || nv < 0) { continue; } if (tr.isEnd(nu) && tr.isEnd(nv)) { nexts[u][v].emplace_back(rt, rt); } if (tr.isEnd(nu)) { nexts[u][v].emplace_back(rt, nv); if (!visited[rt][nv]) { visited[rt][nv] = true; que.emplace_back(rt, nv); } } if (tr.isEnd(nv)) { nexts[u][v].emplace_back(nu, rt); if (!visited[nu][rt]) { visited[nu][rt] = true; que.emplace_back(nu, rt); } } { nexts[u][v].emplace_back(nu, nv); if (!visited[nu][nv]) { visited[nu][nv] = true; que.emplace_back(nu, nv); } } } } while (true) { int chg = 0; for (auto& p : que) { int u = p.first, v = p.second; if (ok[u][v]) { continue; } for (auto& p2 : nexts[u][v]) { int nu = p2.first, nv = p2.second; if (ok[nu][nv]) { ok[u][v] = true; ++chg; break; } } } if (chg == 0) { break; } } map<pair<int,int>,int> indices; for (auto& p : que) { int u = p.first, v = p.second; if (ok[u][v]) { int idx = indices.size(); indices[p] = idx; } } int sz = indices.size(); // cout << sz << sz << endl; vector<vector<int>> mat(sz, vector<int>(sz, 0)); for (auto& p : que) { int u = p.first, v = p.second; if (ok[u][v]) { for (auto& p2 : nexts[u][v]) { int nu = p2.first, nv = p2.second; if (ok[nu][nv]) { // cout << indices[p] << << indices[p2] << << u << << v << endl; mat[indices[p2]][indices[p]] += 1; } } } } auto M = matPow(mat, m); return M[0][0]; } }; int main(int argc, char** argv) { ios::sync_with_stdio(false); cin.tie(0); Solution sol; int n, m; cin >> n >> m; vector<string> S(n); for (int i = 0; i < n; ++i) { cin >> S[i]; } cout << sol.solve(S, m) << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:11:30 08/20/2015
// Design Name:
// Module Name: Sixth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Comparators
//Module Parameter
//W_Exp = 9 ; Single Precision Format
//W_Exp = 11; Double Precision Format
# (parameter W_Exp = 9)
/* # (parameter W_Exp = 12)*/
(
input wire [W_Exp-1:0] exp, //exponent of the fifth phase
output wire overflow, //overflow flag
output wire underflow //underflow flag
);
wire [W_Exp-1:0] U_limit; //Max Normal value of the standar ieee 754
wire [W_Exp-1:0] L_limit; //Min Normal value of the standar ieee 754
//Compares the exponent with the Max Normal Value, if the exponent is
//larger than U_limit then exist overflow
Greater_Comparator #(.W(W_Exp)) GTComparator (
.Data_A(exp),
.Data_B(U_limit),
.gthan(overflow)
);
//Compares the exponent with the Min Normal Value, if the exponent is
//smaller than L_limit then exist underflow
Comparator_Less #(.W(W_Exp)) LTComparator (
.Data_A(exp),
.Data_B(L_limit),
.less(underflow)
);
//This generate sentence creates the limit values based on the
//precision format
generate
if(W_Exp == 9) begin
assign U_limit = 9'hfe;
assign L_limit = 9'h01;
end
else begin
assign U_limit = 12'b111111111110;
assign L_limit = 12'b000000000001;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111O_2_V
`define SKY130_FD_SC_MS__A2111O_2_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2111o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2111o_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111O_2_V
|
module top
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
wire TDO1;
reg [47:0] header;
reg [15:0] len;
reg have_header = 0;
assign MOSI = TDI ;
wire SEL1;
wire SHIFT;
wire RESET;
reg CS_GO = 0;
reg CS_GO_PREP = 0;
reg CS_STOP = 0;
reg CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg RAM_WE = 0;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1'b0),
.DIB(RAM_DI),
.ENA(1'b1),
.ENB(1'b1),
.SSRA(1'b0),
.SSRB(1'b0),
.WEA(1'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN6 BSCAN_SPARTAN6_inst
(
.CAPTURE(CAPTURE),
.DRCK(DRCK1),
.RESET(RESET),
.RUNTEST(),
.SEL(SEL1),
.SHIFT(SHIFT),
.TCK(),
.TDI(TDI),
.TMS(),
.UPDATE(UPDATE),
.TDO(TDO1)
);
`include "bscan_common.vh"
endmodule
|
/*
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
`include "config.vh"
module oddr_wrap (input c, input [1:0] i, output o);
`ifdef X7SERIES
ODDR #(.DDR_CLK_EDGE("SAME_EDGE"), .INIT(1'b1), .SRTYPE("ASYNC"))
ODDR_inst
(
.Q(o),
.C(c),
.CE(1'b1), // 1-bit clock enable input
.D1(i[0]), // positive edge
.D2(i[1]), // negative edge
.R(1'b0), .S(1'b0));
`else
ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(1'b1), .SRTYPE("ASYNC")) ODDR2_i
(.Q(o),
.C0(c), .C1(~c),
.CE(1'b1),
.D0(i[0]), .D1(i[1]),
.R(1'b0), .S(1'b0));
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BLACKBOX_V
/**
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
* keep-alive power rail.
*
* X = (!A | SLEEP)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; vector<int> adjl[4009]; set<pair<int, int> > st; int main() { int n, m, a, b; cin >> n >> m; for (int i = 1; i <= m; i++) { cin >> a >> b; adjl[a].push_back(b); adjl[b].push_back(a); st.insert(pair<int, int>(a, b)); st.insert(pair<int, int>(b, a)); } int ans = 9999999; for (int i = 1; i <= n; i++) { if (adjl[i].size() >= 2) { for (int j = 0; j < adjl[i].size(); j++) { for (int k = j + 1; k < adjl[i].size(); k++) { if (st.find(pair<int, int>(adjl[i][j], adjl[i][k])) != st.end()) { if (ans > adjl[i].size() + adjl[adjl[i][j]].size() + adjl[adjl[i][k]].size() - 6) ans = adjl[i].size() + adjl[adjl[i][j]].size() + adjl[adjl[i][k]].size() - 6; } } } } } if (ans == 9999999) cout << -1 << endl; else cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const long double eps = 1e-6; const long double pi = acos(-1.0); long double sign(long double x) { return (x > 0) - (x < 0); } long long sign(long long x) { return (x > 0) - (x < 0); } int sign(int x) { return (x > 0) - (x < 0); } struct pt { long double x, y; pt() {} pt(long double _x, long double _y) : x(_x), y(_y) {} bool operator<(pt p) { return tie(x, y) < tie(p.x, p.y); } bool operator==(pt p) { return tie(x, y) == tie(p.x, p.y); } pt operator+(pt p) { return {x + p.x, y + p.y}; } pt operator-(pt p) { return {x - p.x, y - p.y}; } pt operator*(long double d) { return {x * d, y * d}; } pt operator/(long double d) { return {x / d, y / d}; } long double dot(pt p) { return x * p.x + y * p.y; } long double det(pt p) { return x * p.y - y * p.x; } long double cross(pt p, pt q) { return (p - *this).det(q - *this); } long double dist() { return sqrtl(x * x + y * y); } pt rot90() { return pt(-y, x); } pt unit() { return *this / dist(); } long double angle() { return atan2(y, x); } pt rot(long double an) { return {x * cos(an) - y * sin(an), x * sin(an) + y * cos(an)}; } void read() { cin >> x >> y; } void write() { cout << ( << x << , << y << ) << endl; } }; struct seg { pt fi, sc; seg() {} seg(pt _fi, pt _sc) : fi(_fi), sc(_sc) {} long double dist(pt C) { if (fi == sc) return (C - fi).dist(); long double d = pow((sc - fi).dist(), 2); long double t = min(d, max((long double)0.0, (C - fi).dot(sc - fi))); return ((C - fi) * d - (sc - fi) * t).dist() / d; } long double len() { return (fi - sc).dist(); } bool on_seg(pt C) { return abs(C.cross(fi, sc)) < eps && (fi - C).dot(sc - C) <= eps; } vector<pt> intersect(seg rhs) { long double oa = rhs.fi.cross(rhs.sc, fi); long double ob = rhs.fi.cross(rhs.sc, sc); long double oc = fi.cross(sc, rhs.fi); long double od = fi.cross(sc, rhs.sc); if (sign(oa) * sign(ob) < 0 && sign(oc) * sign(od) < 0) return {(fi * ob - sc * oa) / (ob - oa)}; vector<pt> ans; if (rhs.on_seg(fi)) ans.push_back(fi); if (rhs.on_seg(sc)) ans.push_back(sc); if (on_seg(rhs.fi)) ans.push_back(rhs.fi); if (on_seg(rhs.sc)) ans.push_back(rhs.sc); return ans; } }; struct line { long double a, b, c; line(pt p1, pt p2) { assert(!(p1 == p2)); a = p2.y - p1.y; b = p1.x - p2.x; c = a * p1.x + b * p1.y; } line() {} line(long double _a, long double _b, long double _c) : a(_a), b(_b), c(_c) {} long double dist(pt p) { return fabs(a * p.x + b * p.y - c) / sqrtl(a * a + b * b); } pair<int, pt> intersect(line rhs) { long double dett = a * rhs.b - b * rhs.a; if (fabs(dett) <= eps) { long double det2 = c * rhs.a - a * rhs.c; if (fabs(det2) <= eps) return {-1, pt()}; return {0, pt()}; } return {1, pt((c * rhs.b - rhs.c * b) / dett, (a * rhs.c - c * rhs.a) / dett)}; } }; pt reflect(pt A, line L) { line perpendicular(-L.b, L.a, -L.b * A.x + L.a * A.y); pt insect = perpendicular.intersect(L).second; return insect * (long double)2.0 - A; } struct mint { int val; mint() { val = 0; } mint(const long long& v) { val = (-mod <= v && v < mod) ? v : v % mod; if (val < 0) val += mod; } friend ostream& operator<<(ostream& os, const mint& a) { return os << a.val; } friend bool operator==(const mint& a, const mint& b) { return a.val == b.val; } friend bool operator!=(const mint& a, const mint& b) { return a.val != b.val; } friend bool operator<(const mint& a, const mint& b) { return a.val < b.val; } friend bool operator>(const mint& a, const mint& b) { return a.val > b.val; } friend bool operator<=(const mint& a, const mint& b) { return a.val <= b.val; } friend bool operator>=(const mint& a, const mint& b) { return a.val >= b.val; } mint operator-() { return mint(-val); } mint& operator+=(const mint& m) { if ((val += m.val) >= mod) val -= mod; return *this; } mint& operator-=(const mint& m) { if ((val -= m.val) < 0) val += mod; return *this; } mint& operator*=(const mint& m) { val = (val * 1ll * m.val) % mod; return *this; } friend mint pow(mint a, long long p) { mint ans = 1; for (; p; p /= 2, a *= a) if (p % 2 == 1) ans *= a; return ans; } friend mint inv(const mint& a) { return pow(a, mod - 2); } mint& operator/=(const mint& m) { return (*this) *= inv(m); } mint& operator^=(const mint& m) { if ((val ^= m.val) >= mod) val -= mod; return *this; } friend mint operator+(mint a, const mint& b) { return a += b; } friend mint operator-(mint a, const mint& b) { return a -= b; } friend mint operator*(mint a, const mint& b) { return a *= b; } friend mint operator/(mint a, const mint& b) { return a /= b; } friend mint operator^(mint a, const mint& b) { return a ^= b; } }; int solve(); void precomp(); int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int t = 1; if (0) cin >> t; if (0) cout << fixed << setprecision(10); precomp(); for (int tc = 1; tc <= t; tc++) { if (0 && 0) cout << Case # << tc << : ; solve(); } } void precomp() { return; } int n, k; mint ans = 0, sum = 0, dp[2000005], pw[2000005]; int solve() { cin >> n >> k; for (int i = 1; i <= k; i++) pw[i] = pow(mint(i), n); for (int i = 1; i <= k; i++) { dp[i] += pw[i]; dp[i] -= pw[i - 1]; sum += dp[i]; ans += sum ^ i; for (int j = i * 2; j <= k; j += i) dp[j] -= dp[i]; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n, k; cin >> n >> k; string s; cin >> s; string res = ; for (int i = 0; i < n; i++) { if ((s[i] - a ) >= ( z - s[i])) { if ((s[i] - a ) <= k) { k -= (s[i] - a ); res += a ; } else { res += (char)(s[i] - k); k = 0; } } else { if (( z - s[i]) <= k) { k -= ( z - s[i]); res += z ; } else { res += (char)(s[i] + k); k = 0; } } } if (k != 0) { cout << -1; } else { cout << res; } }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Input must be RGB or CrYCb in that order, output is CrY/CbY
`timescale 1ns/100ps
module ad_ss_444to422 #(
parameter CR_CB_N = 0,
parameter DELAY_DATA_WIDTH = 16) (
// 444 inputs
input clk,
input s444_de,
input [DW:0] s444_sync,
input [23:0] s444_data,
// 422 outputs
output reg [DW:0] s422_sync,
output reg [15:0] s422_data);
localparam DW = DELAY_DATA_WIDTH - 1;
// internal registers
reg s444_de_d = 'd0;
reg [DW:0] s444_sync_d = 'd0;
reg [23:0] s444_data_d = 'd0;
reg s444_de_2d = 'd0;
reg [DW:0] s444_sync_2d = 'd0;
reg [23:0] s444_data_2d = 'd0;
reg s444_de_3d = 'd0;
reg [DW:0] s444_sync_3d = 'd0;
reg [23:0] s444_data_3d = 'd0;
reg [ 7:0] cr = 'd0;
reg [ 7:0] cb = 'd0;
reg cr_cb_sel = 'd0;
// internal wires
wire [ 9:0] cr_s;
wire [ 9:0] cb_s;
// fill the data pipe lines, hold the last data on edges
always @(posedge clk) begin
s444_de_d <= s444_de;
s444_sync_d <= s444_sync;
if (s444_de == 1'b1) begin
s444_data_d <= s444_data;
end
s444_de_2d <= s444_de_d;
s444_sync_2d <= s444_sync_d;
if (s444_de_d == 1'b1) begin
s444_data_2d <= s444_data_d;
end
s444_de_3d <= s444_de_2d;
s444_sync_3d <= s444_sync_2d;
if (s444_de_2d == 1'b1) begin
s444_data_3d <= s444_data_2d;
end
end
// get the average 0.25*s(n-1) + 0.5*s(n) + 0.25*s(n+1)
assign cr_s = {2'd0, s444_data_d[23:16]} +
{2'd0, s444_data_3d[23:16]} +
{1'd0, s444_data_2d[23:16], 1'd0};
assign cb_s = {2'd0, s444_data_d[7:0]} +
{2'd0, s444_data_3d[7:0]} +
{1'd0, s444_data_2d[7:0], 1'd0};
always @(posedge clk) begin
cr <= cr_s[9:2];
cb <= cb_s[9:2];
if (s444_de_3d == 1'b1) begin
cr_cb_sel <= ~cr_cb_sel;
end else begin
cr_cb_sel <= CR_CB_N;
end
end
// 422 outputs
always @(posedge clk) begin
s422_sync <= s444_sync_3d;
if (s444_de_3d == 1'b0) begin
s422_data <= 'd0;
end else if (cr_cb_sel == 1'b1) begin
s422_data <= {cr, s444_data_3d[15:8]};
end else begin
s422_data <= {cb, s444_data_3d[15:8]};
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module qpsk_mod (
clk,
data_input,
data_valid,
data_qpsk_i,
data_qpsk_q
);
input clk;
input [ 1:0] data_input;
input data_valid;
output [15:0] data_qpsk_i;
output [15:0] data_qpsk_q;
wire [15:0] modulated_data_i;
wire [15:0] modulated_data_q;
wire [15:0] filtered_data_i;
wire [15:0] filtered_data_q;
// output logic
assign data_qpsk_i = filtered_data_i;
assign data_qpsk_q = filtered_data_q;
// instantiations
QPSK_Modulator_Baseband i_qpsk_mod (
.in0({6'b0, data_input}),
.out0_re(modulated_data_i),
.out0_im(modulated_data_q)
);
Raised_Cosine_Transmit_Filter i_tx_filter (
.clk(clk),
.reset(),
.enb_1_1_1(data_valid),
.In1_re(modulated_data_i),
.In1_im(modulated_data_q),
.Out1_re(filtered_data_i),
.Out1_im(filtered_data_q)
);
endmodule
|
`timescale 1ns/10ps
`include "pipeconnect.h"
module dmem(input wire clk,
input wire rst,
input wire `REQ dmem_req,
output wire `RES dmem_res,
output wire `REQ dc_ctrl_req,
input wire `RES dc_ctrl_res,
output wire `REQ bus_ctrl_d_req,
input wire `RES bus_ctrl_d_res);
parameter debug = 0;
demux2 demux2(clk,
(dmem_req`A & 'hFFFF_E000) == 'h1000_0000, // XXX Get rid of this!
dmem_req, dmem_res,
dc_ctrl_req, dc_ctrl_res,
bus_ctrl_d_req, bus_ctrl_d_res);
`ifdef SIMULATE_MAIN
pipechecker check1("dmem", clk, dmem_req, dmem_res);
pipechecker check2("dmem dc_ctrl_d", clk, dc_ctrl_req, dc_ctrl_res);
pipechecker check3("dmem bus_ctrl_d", clk, bus_ctrl_d_req, bus_ctrl_d_res);
`endif
reg r_ = 0;
always @(posedge clk) if (debug) begin
r_ <= dmem_req`R;
if (dmem_res`HOLD)
$display("%5d DMEM: Stall in data memory: %d %d %d", $time,
dmem_res`HOLD, dc_ctrl_res`HOLD, bus_ctrl_d_res`HOLD);
else begin
if (dmem_req`R)
$display("%5d DMEM: load [%x]", $time, dmem_req`A);
if (r_)
$display("%5d DMEM: load -> %x", $time, dmem_res`RD);
if (dmem_req`W)
$display("%5d DMEM: store %x->[%x] (bytena %x)",
$time, dmem_req`WD, dmem_req`A, dmem_req`WBE);
end
end
endmodule // dmem
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T checkmin(T &a, T b) { return (a < b) ? a : a = b; } template <class T> inline T checkmax(T &a, T b) { return (a > b) ? a : a = b; } template <class T> T GCD(T a, T b) { if (a < 0) return GCD(-a, b); if (b < 0) return GCD(a, -b); return (a == 0) ? b : GCD(b % a, a); } template <class T> T LCM(T a, T b) { if (a < 0) return LCM(-a, b); if (b < 0) return LCM(a, -b); return (a == 0 || b == 0) ? 0 : a / GCD(a, b) * b; } template <class T> inline T sqr(T X) { return X * X; } namespace Poor { const int MaxiN = 2005; const int MaxiM = 2005; const int MaxiS = 2005; int N, M; int Id[MaxiM]; pair<int, int> Opt[MaxiS][MaxiS]; string Base[MaxiN]; string St; vector<int> List[MaxiN][26]; void Run() { cin >> N; for (int i = 0; i < N; ++i) cin >> Base[i]; cin >> M; for (int i = 0; i < M; ++i) { cin >> Id[i]; --Id[i]; } cin >> St; for (int i = 0; i < N; ++i) for (int j = 0; j < (int)Base[i].size(); ++j) List[i][Base[i][j] - a ].push_back(j); int Len = St.size(); for (int i = 0; i < Len + 1; ++i) for (int j = 0; j < Len + 1; ++j) Opt[i][j] = make_pair(M, 0); Opt[0][0] = make_pair(0, 0); for (int i = 1; i <= Len; ++i) { int t = St[i - 1] - a ; Opt[i][0] = make_pair(0, 0); for (int j = 1; j <= i; ++j) { Opt[i][j] = Opt[i - 1][j]; pair<int, int> Tmp = Opt[i - 1][j - 1]; while (Tmp < Opt[i][j]) { vector<int>::iterator it = lower_bound(List[Id[Tmp.first]][t].begin(), List[Id[Tmp.first]][t].end(), Tmp.second); if (it != List[Id[Tmp.first]][t].end()) { Tmp.second = *it + 1; break; } ++Tmp.first; Tmp.second = 0; } checkmin(Opt[i][j], Tmp); } } for (int j = Len; j >= 0; --j) if (Opt[Len][j] < make_pair(M, 0)) { cout << j << endl; break; } } } // namespace Poor int main() { ios::sync_with_stdio(false); Poor::Run(); return 0; }
|
`define ADDER_WIDTH 009
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000005; const int mod = 998244353; long long f[5009]; long long c[5009][5009]; long long ch(int a, int b) { long long sum = 0; for (int i = 0; i <= a && i <= b; i++) { sum += ((c[a][i] * c[b][i] % mod) * f[i] % mod); } return sum % mod; } int main() { f[0] = f[1] = 1; for (int i = 2; i <= 5000; i++) { f[i] = f[i - 1] * i % mod; } for (int i = 1; i <= 5000; i++) { c[i][0] = c[i][i] = 1; for (int j = 1; j < i; j++) { c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % mod; } } int a, b, c; while (~scanf( %d%d%d , &a, &b, &c)) { long long ans = 1; ans = ans * ch(a, b); ans %= mod; ans = ans * ch(a, c); ans %= mod; ans = ans * ch(b, c); ans %= mod; printf( %I64d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double inf = 1e14; const double pi = acos(-1); const double eps = 1e-10; const int maxn = 25010; int n, x[maxn], y[maxn], dx[maxn], dy[maxn], s[maxn]; double ans = inf, ddx[maxn], ddy[maxn], K[maxn], B[maxn]; inline double solve(int a, int b) { double b1, k1, b2, k2; k1 = K[a]; b1 = B[a]; k2 = K[b]; b2 = B[b]; if (k1 == k2) { double kk = sqrt((x[a] - x[b]) * (x[a] - x[b]) + (y[a] - y[b]) * (y[a] - y[b])); double X, Y, XX, YY, t; t = kk / double(s[a] + s[b]); X = (double)x[a] + (double)ddx[a] * t * s[a]; Y = (double)y[a] + (double)ddy[a] * t * s[a]; XX = (double)x[b] + (double)ddx[b] * t * s[b]; YY = (double)y[b] + (double)ddy[b] * t * s[b]; if (abs(X - XX) <= eps && abs(Y - YY) <= eps) return t; if (s[a] == s[b]) return inf; t = kk / double(s[a]); X = (double)x[a] + (double)ddx[a] * t * s[a]; Y = (double)y[a] + (double)ddy[a] * t * s[a]; if (abs(X - x[b]) <= eps && abs(Y - y[b]) <= eps) return t; t = kk / double(s[b]); X = (double)x[b] + (double)ddx[b] * t * s[b]; Y = (double)y[b] + (double)ddy[b] * t * s[b]; if (abs(X - x[a]) <= eps && abs(Y - y[a]) <= eps) return t; return inf; } double X = (b2 - b1) / (k1 - k2), Y; Y = k1 * X + b1; if ((Y - y[a]) * dy[a] < 0) return inf; if ((Y - y[b]) * dy[b] < 0) return inf; if ((X - x[a]) * dx[a] < 0) return inf; if ((X - x[b]) * dx[b] < 0) return inf; double now1 = sqrt((X - x[a]) * (X - x[a]) + (Y - y[a]) * (Y - y[a])) / s[a]; double now2 = sqrt((X - x[b]) * (X - x[b]) + (Y - y[b]) * (Y - y[b])) / s[b]; return max(now1, now2); } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d%d%d%d%d , &x[i], &y[i], &dx[i], &dy[i], &s[i]); double v = sqrt(dx[i] * dx[i] + dy[i] * dy[i]); ddx[i] = dx[i] / v; ddy[i] = dy[i] / v; K[i] = (double)dy[i] / dx[i]; B[i] = y[i] - (double)dy[i] / dx[i] * x[i]; } for (int i = 1; i <= n; ++i) for (int j = i + 1; j <= n; ++j) { ans = min(ans, solve(i, j)); } if (ans > 1e12) printf( No show :( n ); else printf( %.15f n , ans); return 0; }
|
`timescale 1ns / 1ps
/*
Group Members: Kevin Ingram and Warren Seto
Lab Name: Traffic Light Controller (Lab 3)
Project Name: eng312_proj3
Design Name: Traffic_Test_F_eng312_proj3.v
Design Description: Verilog Test Bench to Implement Test F (2 PM)
*/
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire[4:0] count1;
wire[3:0] count2;
wire[1:0] count3;
// Counter Modules
nsCounter clock1(clk, count1); // Count a total of 32 seconds
ewCounter clock2(clk, count2); // Counts a total of 16 seconds
yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @ (clk) begin
if ($time % 15 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 2 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/05/2016 08:56:02 PM
// Design Name:
// Module Name: hapara_axis_64timer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module hapara_axis_64timer # (
parameter DATA_WIDTH = 32
)(
bram_clk,
bram_rst,
bram_en,
bram_we,
bram_addr,
bram_din,
bram_dout,
valid,
ready,
data,
rstn,
clk
);
output bram_clk;
output bram_rst;
output bram_en;
output [3 : 0] bram_we;
output [DATA_WIDTH - 1 : 0] bram_addr;
output [DATA_WIDTH - 1 : 0] bram_din;
input [DATA_WIDTH - 1 : 0] bram_dout;
output valid;
input ready;
output [DATA_WIDTH - 1 : 0] data;
input rstn;
input clk;
assign bram_clk = clk;
assign bram_rst = ~rstn;
reg [DATA_WIDTH - 1 : 0] bram_din;
reg [2 * DATA_WIDTH - 1 : 0] counter;
reg [2 * DATA_WIDTH - 1 : 0] temp;
reg [DATA_WIDTH - 1 : 0] raddr;
reg [1 : 0] curr_state;
reg [1 : 0] next_state;
localparam idle = 2'b00;
localparam s0 = 2'b01;
localparam s1 = 2'b10;
localparam wait0 = 2'b11;
// Logic for raadr;
always @(posedge clk) begin
if (~rstn) begin
raddr <= {DATA_WIDTH{1'b0}};
end else if (curr_state == s0 || curr_state == s1) begin
raddr <= raddr + 4;
end else begin
raddr <= raddr;
end
end
assign bram_addr = raddr;
// Logic for curr_state
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
curr_state <= idle;
end else begin
curr_state <= next_state;
end
end
// Logic for next_state
always @(*) begin
case (curr_state)
idle:
if (ready) next_state = s0;
else next_state = idle;
s0:
next_state = s1;
s1:
next_state = wait0;
wait0:
if (~ready) next_state = idle;
else next_state = wait0;
default:
next_state = 2'bxx;
endcase
end
// Logic for counter
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
counter <= {2 * DATA_WIDTH{1'b0}};
end else begin
counter <= counter + 1;
end
end
// Logic for temp
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
temp <= {2 * DATA_WIDTH{1'b0}};
end else if ((curr_state == idle) && ready) begin
temp <= counter;
end else begin
temp <= temp;
end
end
// Logic for bram_din
always @(*) begin
case (curr_state)
idle:
bram_din = {DATA_WIDTH{1'b0}};
s0:
bram_din = temp[DATA_WIDTH - 1 : 0];
s1:
bram_din = temp[2 * DATA_WIDTH - 1 : DATA_WIDTH];
wait0:
bram_din = {DATA_WIDTH{1'b0}};
default:
bram_din = {DATA_WIDTH{1'bx}};
endcase
end
// Logic for bram_en and bram_we
assign bram_en = (curr_state == s0 || curr_state == s1)?1'b1:1'b0;
assign bram_we = (curr_state == s0 || curr_state == s1)?4'b1111:4'b0000;
// Logic for valid
assign valid = (curr_state == wait0 && ready)?1'b1:1'b0;
assign data = (curr_state == wait0 && ready)?1:0;
endmodule
|
`timescale 1 ns / 1 ps
module lookup_table_behavioural #
(
// signal width definitions
parameter integer TDATA_WIDTH = 32,
parameter integer ADDRESS_WIDTH = 8
)
(
// input data AXI bus
input wire data_in_aclk,
input wire data_in_aresetn,
output wire data_in_tready,
input wire [ADDRESS_WIDTH-1:0] data_in_tdata,
input wire data_in_tlast,
input wire data_in_tvalid,
// output data AXI bus
output wire data_out_aclk,
output wire data_out_aresetn,
input wire data_out_tready,
output reg [TDATA_WIDTH-1:0] data_out_tdata,
output reg data_out_tlast,
output reg data_out_tvalid,
// load new data into lookup table AXI bus
input wire data_load_aclk,
input wire data_load_aresetn,
output wire data_load_tready,
input wire [TDATA_WIDTH-1:0] data_load_tdata,
input wire data_load_tlast,
input wire data_load_tvalid
);
reg [TDATA_WIDTH-1:0] register_space[2**ADDRESS_WIDTH-1:0];
// load the data into the register space structure
integer i;
always @(posedge data_load_aclk) begin
if(!data_load_aresetn) begin
for (i = 0; i < ADDRESS_WIDTH; i=i+1) begin
register_space[i] <= 0;
end
end
else begin
if (data_load_tvalid & data_load_tready) begin
register_space[data_load_address] <= data_load_tdata;
end
end
end
// index out the data
always @(posedge data_out_aclk) begin
if(!data_out_aresetn) begin
data_out_tdata <= 0;
end
else begin
data_out_tdata <= register_space[data_in_tdata];
end
end
// pass the ready signal directly through
assign data_in_tready = data_out_tready;
// the signals are delayed by a single cycle
always @(posedge data_in_aclk) begin
if(!data_in_aresetn) begin
data_out_tvalid <= 0;
data_out_tlast <= 0;
end
else begin
data_out_tvalid <= data_in_tvalid;
data_out_tlast <= data_in_tlast;
end
end
// if the AXI bus is ready and has valid data we're loading data
assign data_load = data_load_tvalid & data_load_tready;
// generate incrementing address for loading data
reg [ADDRESS_WIDTH-1:0] data_load_address;
assign data_load_tready = 1;
always @(posedge data_load_aclk) begin
if(!data_load_aresetn) begin
data_load_address <= 0;
end
else begin
if (data_load_tlast) begin
data_load_address <= 0;
end
else if (data_load) begin
data_load_address <= data_load_address + 1;
end
end
end
// used to create the GTKwave dump file
`ifdef COCOTB_SIM
initial begin
$dumpfile ("waveform.vcd");
$dumpvars (0, lookup_table_behavioural);
#1;
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; long long N, P; long long L[100001]; long long R[100001]; long long getAc(long long l, long long r, long long p) { if ((l + p - 1) / p * p > r) return 0; return (r - (l + p - 1) / p * p) / p + 1; } int main() { scanf( %lld%lld , &N, &P); for (int i = 0; i < N; i++) scanf( %lld%lld , &L[i], &R[i]); double ans = 0; for (int i = 0; i < N; i++) { long long a = getAc(L[i], R[i], P); long long b = getAc(L[(i + 1) % N], R[(i + 1) % N], P); long long cur = (R[i] - L[i] + 1) * b; cur += (R[(i + 1) % N] - L[(i + 1) % N] + 1) * a; cur -= a * b; ans += (double)cur * 2000 / (R[i] - L[i] + 1) / (R[(i + 1) % N] - L[(i + 1) % N] + 1); } printf( %.8f , (double)ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long ctos, modd = 1000000007, dos = 2; long long P[4005], B[4005][4005], res; long long bi(int n, int k) { if (n == k) return 1; if (k == 0) return 1; if (k > n) return 0; if (k == 1) return n; if (B[n][k] > 0) return B[n][k]; B[n][k] = (bi(n - 1, k - 1) + bi(n - 1, k)) % modd; return B[n][k]; } int main() { cin >> ctos; P[0] = 1; for (int i = 1; i <= ctos; i++) { for (int e = 0; e < i; e++) { P[i] += 1LL * P[i - e - 1] * bi(i - 1, e) % modd; P[i] %= modd; } } for (int i = 1; i <= ctos; i++) { res += P[ctos - i] * bi(ctos, i) % modd; res %= modd; } cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int flow, n, m, S, T, tot, x, y; int g[3000], dis[3000], pre[3000]; int Next[50000], adj[50000], f[50000], c[50000]; bool used[3000]; queue<int> q; int ans = 0; int calc[110][30]; string t, s; void add(int x, int y, int flow, int cost) { adj[tot] = y; c[tot] = cost; f[tot] = flow; Next[tot] = g[x]; g[x] = tot++; adj[tot] = x; c[tot] = -cost; f[tot] = 0; Next[tot] = g[y]; g[y] = tot++; } bool spfa() { for (int i = 1; i <= T; i++) dis[i] = 1 << 23; dis[S] = 0; memset(used, 0, sizeof(used)); while (!q.empty()) q.pop(); q.push(S); used[S] = true; int p; while (!q.empty()) { x = q.front(); used[x] = false; p = g[x]; while (p != -1) { y = adj[p]; if (f[p] && dis[x] + c[p] < dis[y]) { dis[y] = dis[x] + c[p]; pre[y] = p; if (!used[y]) { used[y] = true; q.push(y); } } p = Next[p]; } q.pop(); } return dis[T] != 1 << 23; } int path() { int del = 1 << 23; int p = T; while (p != S) { if (f[pre[p]] < del) del = f[pre[p]]; p = adj[pre[p] ^ 1]; } p = T; while (p != S) { f[pre[p]] -= del; f[pre[p] ^ 1] += del; p = adj[pre[p] ^ 1]; } flow += del; return del * dis[T]; } void solve() { memset(pre, 0, sizeof(pre)); while (spfa()) ans += path(); if (flow != t.size()) cout << -1 << endl; else cout << ans << endl; } int main() { cin >> t; cin >> n; memset(g, -1, sizeof(g)); tot = 0; S = 26 * (n + 1) + n + 1; T = S + 1; for (int i = 1; i <= n; i++) { cin >> s >> x; for (int j = 0; j < s.size(); j++) calc[i][s[j] - a ]++; add(S, 26 * (n + 1) + i, x, 0); } for (int i = 0; i < t.size(); i++) calc[n + 1][t[i] - a ]++; for (int i = 0; i < 26; i++) add(26 * n + i + 1, T, calc[n + 1][i], 0); for (int i = 1; i <= n; i++) for (int j = 0; j < 26; j++) { add(26 * (n + 1) + i, (i - 1) * 26 + j + 1, 1 << 23, 0); add((i - 1) * 26 + j + 1, 26 * n + j + 1, calc[i][j], i); } solve(); return 0; }
|
//
module ddr3_s4_amphy_ex_lfsr8 (
clk, reset_n, enable, pause, load, data, ldata);
parameter seed = 32;
input clk;
input reset_n;
input enable;
input pause;
input load;
output[8 - 1:0] data;
wire[8 - 1:0] data;
input[8 - 1:0] ldata;
reg[8 - 1:0] lfsr_data;
assign data = lfsr_data ;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
// Reset - asynchronously reset to seed value
lfsr_data <= seed[7:0] ;
end
else
begin
if (!enable)
begin
lfsr_data <= seed[7:0];
end
else
begin
if (load)
begin
lfsr_data <= ldata ;
end
else
begin
// Registered mode - synchronous propagation of signals
if (!pause)
begin
lfsr_data[0] <= lfsr_data[7] ;
lfsr_data[1] <= lfsr_data[0] ;
lfsr_data[2] <= lfsr_data[1] ^ lfsr_data[7] ;
lfsr_data[3] <= lfsr_data[2] ^ lfsr_data[7] ;
lfsr_data[4] <= lfsr_data[3] ^ lfsr_data[7] ;
lfsr_data[5] <= lfsr_data[4] ;
lfsr_data[6] <= lfsr_data[5] ;
lfsr_data[7] <= lfsr_data[6] ;
end
end
end
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_channel_gate_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Captures transaction open/close events as well as data
// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
// CHNL_TX drops, the channel closes (until the next transaction -- signaled by
// CHNL_TX going up again).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTGATE32_IDLE 2'b00
`define S_TXPORTGATE32_OPENING 2'b01
`define S_TXPORTGATE32_OPEN 2'b10
`define S_TXPORTGATE32_CLOSED 2'b11
`timescale 1ns/1ns
module tx_port_channel_gate_32 #(
parameter C_DATA_WIDTH = 9'd32,
// Local parameters
parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1
)
(
input RST,
input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE32_IDLE, _rState=`S_TXPORTGATE32_IDLE;
reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE32_OPEN
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// FIFO for temporarily storing data from the channel.
(* RAM_STYLE="DISTRIBUTED" *)
async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (
.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY)
);
// Pass the transaction open event, transaction data, and the transaction
// close event through to the RD_CLK domain via the async_fifo.
always @ (posedge CHNL_CLK) begin
rState <= #1 (RST ? `S_TXPORTGATE32_IDLE : _rState);
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
case (rState)
`S_TXPORTGATE32_IDLE: begin // Write the len
_rPause = 0;
_rClosed = 0;
if (!wFifoFull) begin
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, rChnlLen};
if (rChnlTx)
_rState = `S_TXPORTGATE32_OPENING;
end
end
`S_TXPORTGATE32_OPENING: begin // Write the off, last
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoData = {1'd1, rChnlOff, rChnlLast};
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE32_CLOSED;
else
_rState = `S_TXPORTGATE32_OPEN;
end
end
`S_TXPORTGATE32_OPEN: begin // Copy channel data into the FIFO
_rAck = 0;
if (!wFifoFull) begin
_rFifoWen = CHNL_TX_DATA_VALID; // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
_rFifoData = {1'd0, CHNL_TX_DATA}; // but the VALID+REN model seem to make this difficult.
end
if (!rChnlTx)
_rState = `S_TXPORTGATE32_CLOSED;
end
`S_TXPORTGATE32_CLOSED: begin // Write the end marker (twice)
_rAck = 0;
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE32_IDLE;
end
end
endcase
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CHNL_CLK),
.CONTROL(wControl0),
.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
.DATA({313'd0,
rChnlOff, // 31
rChnlLen, // 32
rChnlLast, // 1
rChnlTx, // 1
CHNL_TX_OFF, // 31
CHNL_TX_LEN, // 32
CHNL_TX_LAST, // 1
CHNL_TX, // 1
wFifoFull, // 1
rFifoData, // 65
rFifoWen, // 1
rState}) // 2
);
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = (1 << 22) + 20; bool vis[2][N]; int a[N], n, m, ex[N]; int get_not(int x) { return (1 << n) - 1 - x; } void dfs(int type, int msk) { vis[type][msk] = true; if (type == 1) { if (!vis[0][get_not(msk)]) dfs(0, get_not(msk)); for (int i = 0; i < n; i++) if ((!(msk & (1 << i))) && (!vis[1][msk ^ (1 << i)])) dfs(1, msk ^ (1 << i)); } else if (!vis[1][msk] && ex[msk]) dfs(1, msk); } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> m; for (int i = 0; i < m; i++) cin >> a[i], ex[a[i]] = 1; int ans = 0; for (int i = 0; i < m; i++) { if (!vis[0][a[i]]) dfs(0, a[i]), ans++; } cout << ans; return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : sys_clk_gen_ds.v
// Version : 1.11
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module sys_clk_gen_ds (sys_clk_p, sys_clk_n);
output sys_clk_p;
output sys_clk_n;
parameter offset = 0;
parameter halfcycle = 500;
sys_clk_gen #(
.offset( offset ),
.halfcycle( halfcycle )
)
clk_gen (
.sys_clk(sys_clk_p)
);
assign sys_clk_n = !sys_clk_p;
endmodule // sys_clk_gen_ds
|
//b12015 Rohit Patiyal
`include "ALU/Arith/Signed/SSubtractor/mux32to16.v" //`
`include "ALU/Arith/Signed/SSubtractor/mux48to16.v" //`
`include "ALU/Arith/Signed/SAdder/SAdder.v"
`include "ALU/Arith/Signed/SSubtractor/SSubtractor.v"
`include "ALU/Arith/Signed/SDivider/SDivider.v"
`include "ALU/Arith/Signed/SMultiplier/SMultiplier.v"
//`include "ALU/mux4to1.v"//`
module Signed(output [31:0] Answer, input [31:0] A,input [31:0] B,input [1:0] OpCode);
output [31:0] Sum;
output [31:0] Difference;
output [63:0] Product;
output [31:0] Quotient;
output [31:0] Remainder;
wire carry_out;
wire overflow;
// SDivider myDiv(Quotient, Remainder, A, B);
// SAdder myAdder(Sum, carry_out, overflow, A, B ,0);
// SDivider myDiv3(Difference, Remainder, A, B);
SAdder myAdd(Sum, Remainder, A, B);
SSubtractor mySub(Difference, Remainder, A, B);
SMultiplier myProduct(Product, A, B);
SDivider myDiv(Quotient, Remainder, A, B);
genvar i;
generate for(i=0;i<32;i=i+1) begin: muxingthebits
mux4to1 m(Answer[i], Sum[i], Difference[i], Product[i], Quotient[i], OpCode);
end endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const double pi = acos(-1.0); const int inf = 2147483647; int n, w; int a[1005]; bool first; int MIN; void output(int x) { if (first) first = false; else printf( ); if (x == MIN) x = 0; else if (x == 0) x = MIN; printf( %d , x + 1); } int main() { scanf( %d%d , &n, &w); int total = 0; MIN = 0; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); total += a[i]; if (a[MIN] > a[i]) MIN = i; } first = true; if (w >= a[MIN] && w <= total) { printf( Yes n ); swap(a[0], a[MIN]); output(0); total = total - w; for (int i = 1; i < n && total; i++) { while (total && a[i]) { total--; a[i]--; output(i); output(i); } } output(0); a[0]--; for (int i = 0; i < n; i++) { while (a[i]) { a[i]--; output(i); output(i); } } printf( n ); } else if (w > total || n == 1) { printf( No n ); } else if (w <= 1) { printf( No n ); } else { printf( Yes n ); swap(a[0], a[MIN]); output(0); total = total - w; for (int i = 1; i < n && total; i++) { int limit = (i == 1 ? 1 : 0); while (total && a[i] > limit) { total--; a[i]--; output(i); output(i); } } output(0); a[0]--; output(1); while (a[0] >= w - 1) { output(0); output(0); a[0]--; } output(1); while (a[0]) { output(0); output(0); a[0]--; } printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int lowbit(int x) { return x & -x; } int read() { int kkk = 0, x = 1; char c = getchar(); while ((c < 0 || c > 9 ) && c != - ) c = getchar(); if (c == - ) c = getchar(), x = -1; while (c >= 0 && c <= 9 ) kkk = kkk * 10 + (c - 0 ), c = getchar(); return kkk * x; } int n, K, p, minn[101], dp[500001], tree[110], DP[10001][101], a[500001]; inline int MOD(int x) { return x + ((x >> 31) & p); } void sbsolve() { memset(DP, 0x3f, sizeof(DP)); DP[0][0] = 0; for (int j = 1; j <= K; ++j) { memset(minn, 0x3f, sizeof(minn)); for (int i = j - 1; i <= n; ++i) { for (int k = 0; k < p; ++k) DP[i][j] = min(DP[i][j], minn[k] + MOD(a[i] - k)); minn[a[i]] = min(minn[a[i]], DP[i][j - 1]); } } printf( %d n , DP[n][K]); } void xg(int zone, int v) { while (zone <= p) { tree[zone] = max(tree[zone], v); zone += lowbit(zone); } } int cx(int zone) { int bck = 0; while (zone) { bck = max(tree[zone], bck); zone -= lowbit(zone); } return bck; } int main() { n = read(), K = read(), p = read(); for (int i = 1; i <= n; ++i) a[i] = MOD(a[i - 1] + read() % p - p); if (n < K * p) { sbsolve(); return 0; } int ans = a[n]; for (int i = 1; i <= n; ++i) a[i] += 1; dp[1] = 1; xg(a[1], dp[1]); for (int i = 2; i <= n; ++i) { dp[i] = cx(a[i]) + 1; xg(a[i], dp[i]); } if (dp[n] >= K) printf( %d n , ans); else printf( %d n , ans + p); return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_axi_basic_rx.v
// Version : 1.10
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_core_axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_core_axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
pcie_core_axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file blk_mem_gen_v6_2.v when simulating
// the core, blk_mem_gen_v6_2. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module blk_mem_gen_v6_2(
clka,
addra,
douta
);
input clka;
input [11 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(1),
.C_DISABLE_WARN_BHV_RANGE(1),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("blk_mem_gen_v6_2.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, p[10]; map<long long, string> m; set<long long> s[10]; template <class T> string toString(T x) { ostringstream os; os << x; return os.str(); } int getlen(long long x) { int ans = 0; while (x) { ans++; x /= 10; } return max(ans, 1); } string get(long long x) { if (m.count(x)) return m[x]; return toString(x); } void relaxPower(long long x, string str) { if (x > n || str.length() >= getlen(x)) return; if (m.count(x) && m[x].length() <= str.length()) return; s[m[x].length()].erase(x); m[x] = str; s[str.length()].insert(x); } void getPowers() { for (long long x = 2; x * x <= n; x++) { long long rs = x * x; int p = 2; while (rs <= n) { string tmp = toString(x) + ^ + toString(p); relaxPower(rs, tmp); rs *= x; p++; } } } void getPowerAndPower(int len) { for (int i = 1; i <= len; i++) for (int j = i; i + j + 1 <= len; j++) for (auto x : s[i]) for (auto y : s[j]) relaxPower(x * y, get(x) + * + get(y)); } void getSimpleAndPower(int len) { for (int i = 1; i + 2 <= len; i++) { for (long long x = 1; x < p[len - i - 1]; x++) for (long long y : s[i]) relaxPower(x * y, toString(x) + * + get(y)); } } void precalc() { getPowers(); getPowerAndPower(7); getSimpleAndPower(7); } string ans; void relaxAnswer(string str) { if (str.length() < ans.length()) ans = str; } void checkAnswer() { for (int i = 1; i * 2 + 1 < ans.length(); i++) { for (long long x = 1; x <= p[i]; x++) { relaxAnswer(get(n - x) + + + get(x)); if (n % x == 0) relaxAnswer(get(n / x) + * + get(x)); } for (auto x : s[i]) { relaxAnswer(get(n - x) + + + get(x)); if (n % x == 0) relaxAnswer(get(n / x) + * + get(x)); } } } int main() { p[0] = 1; for (int i = 1; i < 10; i++) p[i] = p[i - 1] * 10; cin >> n; precalc(); ans = get(n); checkAnswer(); cout << ans << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlygate4sd2 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int n, m, k, i, j, a; int c[11]; int main() { cin >> n >> m >> k; for (i = 1; i <= n; ++i) { for (j = 1; j <= m; ++j) { char x; cin >> x; c[j] += (x == Y ); } } for (i = 1; i <= m; ++i) a += (c[i] >= k); cout << a; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int x1, y1, x2, y2; while (scanf( %*d %*d %d %d %d %d , &x1, &y1, &x2, &y2) == 4) { int a = abs(x1 - x2), b = abs(y1 - y2); if (min(a, b) <= 2 && max(a, b) < 5) puts( First ); else if (max(a, b) < 4) puts( First ); else puts( Second ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, b, mod; cin >> n >> m >> b >> mod; int dp[502][502]; int bugs[n + 2]; for (int i = 0; i < n; i++) cin >> bugs[i]; memset(dp, 0, sizeof dp); dp[0][0] = 1; for (int k = 0; k < n; k++) { for (int j = 0; j <= b - bugs[k]; j++) { for (int i = 0; i < m; i++) { dp[i + 1][j + bugs[k]] += dp[i][j]; dp[i + 1][j + bugs[k]] %= mod; } } } int ans = 0; for (int i = 0; i <= b; i++) { ans += dp[m][i]; ans %= mod; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, d; cin >> n >> d; long long arr[n]; for (long long i = 0; i < n; i++) cin >> arr[i]; set<long long> s1; for (long long i = 0; i < n; i++) { long long pd = arr[i] - d; if (i == 0) s1.insert(pd); else if (i != 0) { long long a1 = abs(arr[i - 1] - pd); if (a1 >= d) s1.insert(pd); } long long nd = arr[i] + d; if (i == n - 1) s1.insert(nd); else if (i != n - 1) { long long a1 = abs(arr[i + 1] - nd); if (a1 >= d) s1.insert(nd); } } cout << s1.size() << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; priority_queue<pair<int, int> > a; priority_queue<pair<int, int> > b; vector<pair<int, int> > A; vector<pair<int, int> > B; int main() { int n, x; scanf( %d%d , &n, &x); int x0 = x; for (int i = 0; i < n; i++) { int t; int h, m; scanf( %d%d%d , &t, &h, &m); if (t == 0) A.push_back(pair<int, int>(h, m)); else B.push_back(pair<int, int>(h, m)); } int pa = 0, push_back = 0; sort(A.begin(), A.end()); sort(B.begin(), B.end()); int ans = 0; while (pa < A.size() && A[pa].first <= x) a.push(pair<int, int>(A[pa].second, A[pa].first)), pa++; while (push_back < B.size() && B[push_back].first <= x) b.push(pair<int, int>(B[push_back].second, B[push_back].first)), push_back++; int nn = 0; int cur = 0; while (nn < 2) { pair<int, int> k; if (cur == 0) { if (a.size() == 0) { nn++; continue; } k = a.top(); a.pop(); } if (cur == 1) { if (b.size() == 0) { nn++; continue; } k = b.top(); b.pop(); } x += k.first; ans++; while (pa < A.size() && A[pa].first <= x) a.push(pair<int, int>(A[pa].second, A[pa].first)), pa++; while (push_back < B.size() && B[push_back].first <= x) b.push(pair<int, int>(B[push_back].second, B[push_back].first)), push_back++; cur ^= 1; nn = 0; } int ans2 = 0; cur = 1; nn = 0; while (a.size()) a.pop(); while (b.size()) b.pop(); pa = push_back = 0; x = x0; while (pa < A.size() && A[pa].first <= x) a.push(pair<int, int>(A[pa].second, A[pa].first)), pa++; while (push_back < B.size() && B[push_back].first <= x) b.push(pair<int, int>(B[push_back].second, B[push_back].first)), push_back++; while (nn < 2) { pair<int, int> k; if (cur == 0) { if (a.size() == 0) { nn++; continue; } k = a.top(); a.pop(); } if (cur == 1) { if (b.size() == 0) { nn++; continue; } k = b.top(); b.pop(); } x += k.first; ans2++; while (pa < A.size() && A[pa].first <= x) a.push(pair<int, int>(A[pa].second, A[pa].first)), pa++; while (push_back < B.size() && B[push_back].first <= x) b.push(pair<int, int>(B[push_back].second, B[push_back].first)), push_back++; cur ^= 1; nn = 0; } printf( %d n , max(ans, ans2)); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// Very simple test for interface pathclearing
interface ifc;
integer hidden_from_isub;
integer value;
modport out_modport (output value);
endinterface
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc itop();
sub c1 (.isub(itop),
.i_value(4));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==20) begin
if (itop.value != 4) $stop;
itop.hidden_from_isub = 20;
if (itop.hidden_from_isub != 20) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub
`ifdef NANSI // bug868
(
isub, i_value
);
ifc.out_modport isub; // Note parenthesis are not legal here
input integer i_value;
`else
(
ifc.out_modport isub,
input integer i_value
);
`endif
always @* begin
isub.value = i_value;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int INF = 2e9 + 5; const int MAXN = 100010; int n; long long a, r, m, h[MAXN]; int main() { cin.sync_with_stdio(0); cin.tie(0); cin >> n >> a >> r >> m; for (int i = 0; i < n; i++) { cin >> h[i]; } m = min(m, a + r); sort(h, h + n, greater<long long>()); long long sum = 0; for (int i = 0; i < n; i++) { sum += h[i]; } long long lbound = (sum + n - 1) / n; long long cur = (n * h[0] - sum) * a; long long ans = 1e18; long long run = 0; for (int i = 0; i < n; i++) { if (h[i] < lbound) break; long long lo = lbound; if (i + 1 < n) { lo = max(lo, h[i + 1]); } ans = min(ans, cur + run); long long delta = (i + 1) * m - n * a; run += delta * (h[i] - lo); } ans = min(ans, cur + run); reverse(h, h + n); long long ubound = sum / n; cur = (sum - n * h[0]) * r; run = 0; for (int i = 0; i < n; i++) { if (h[i] > ubound) break; long long hi = ubound; if (i + 1 < n) { hi = min(hi, h[i + 1]); } ans = min(ans, cur + run); long long delta = (i + 1) * m - n * r; run += delta * (hi - h[i]); ; } ans = min(ans, cur + run); cout << ans; }
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 5
*/
// Testbench for behavioral model for the circular FIFO
// Import the modules that will be tested for in this testbench
`include "fifo.v"
// IMPORTANT: To run this, try: ncverilog -f fifo.f +gui
module tb_fifo();
/**
* Depth = number of rows for the register file
*
* The construct base**exponent is not synthesizable for our
* tool and technology library set up. It should be with the latest
* version of Verilog, Verilog 2005
*/
parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
// Width of the register file
parameter WIDTH = 8;
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the FIFO queue
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_out & emp & full_cb output signals
wire [7:0] d_out;
wire empty_cb,full_cb;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// push, pop, reset, & clk
reg push_cb,pop_cb,rst,clock;
// data_in
reg [WIDTH-1:0] d_in;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of SIPO() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
FIFO fifo_cb (
// instance_name(signal name),
// Signal name can be the same as the instance name
d_out,empty_cb,full_cb,d_in,push_cb,pop_cb,rst,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
rst=1'd1; // Reset
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd45;
// Push...
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd231;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd37;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd174;
// Pop
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd45;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd145;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd24; // Empty
// Pop more
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
// Push
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd235;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd39;
// Push and Pop
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd1;
d_in=8'd201;
// Continue pushing
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd72;
// DO NOT PUSH NOR POP
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd82;
// Continue pushing
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd58;
#10 // FULL
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd238;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd125;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
//b12015 ROHIT PATIYAL
`include "ALU/Arith/UnSigned/UDivider/BasicCell.v"
`include "ALU/Arith/UnSigned/UDivider/stepof32.v"
`include "ALU/Arith/UnSigned/UDivider/laststepof32.v"
//`include "ALU/mux2to1.v" //`
module UDivider(Quotient, Remainder, Dividend, Divisor);
output [31:0] Quotient;
output [31:0] Remainder;
input [31:0] Divisor;
input [31:0] Dividend;
wire [31:0] TR[0:32];
wire cin;
wire cout;
wire garbage;
stepof32 myStep1(TR[0], garbage, 0, Dividend[31], Divisor, 1);
stepof32 myStep2(TR[1], Quotient[31], TR[0], Dividend[30], Divisor, garbage);
stepof32 myStep3(TR[2], Quotient[30], TR[1], Dividend[29], Divisor, Quotient[31]);
stepof32 myStep4(TR[3], Quotient[29], TR[2], Dividend[28], Divisor, Quotient[30]);
stepof32 myStep5(TR[4], Quotient[28], TR[3], Dividend[27], Divisor, Quotient[29]);
stepof32 myStep6(TR[5], Quotient[27], TR[4], Dividend[26], Divisor, Quotient[28]);
stepof32 myStep7(TR[6], Quotient[26], TR[5], Dividend[25], Divisor, Quotient[27]);
stepof32 myStep8(TR[7], Quotient[25], TR[6], Dividend[24], Divisor, Quotient[26]);
stepof32 myStep9(TR[8], Quotient[24], TR[7], Dividend[23], Divisor, Quotient[25]);
stepof32 myStep10(TR[9], Quotient[23], TR[8], Dividend[22], Divisor, Quotient[24]);
stepof32 myStep11(TR[10], Quotient[22], TR[9], Dividend[21], Divisor, Quotient[23]);
stepof32 myStep12(TR[11], Quotient[21], TR[10], Dividend[20], Divisor, Quotient[22]);
stepof32 myStep13(TR[12], Quotient[20], TR[11], Dividend[19], Divisor, Quotient[21]);
stepof32 myStep14(TR[13], Quotient[19], TR[12], Dividend[18], Divisor, Quotient[20]);
stepof32 myStep15(TR[14], Quotient[18], TR[13], Dividend[17], Divisor, Quotient[19]);
stepof32 myStep16(TR[15], Quotient[17], TR[14], Dividend[16], Divisor, Quotient[18]);
stepof32 myStep17(TR[16], Quotient[16], TR[15], Dividend[15], Divisor, Quotient[17]);
stepof32 myStep18(TR[17], Quotient[15], TR[16], Dividend[14], Divisor, Quotient[16]);
stepof32 myStep19(TR[18], Quotient[14], TR[17], Dividend[13], Divisor, Quotient[15]);
stepof32 myStep20(TR[19], Quotient[13], TR[18], Dividend[12], Divisor, Quotient[14]);
stepof32 myStep21(TR[20], Quotient[12], TR[19], Dividend[11], Divisor, Quotient[13]);
stepof32 myStep22(TR[21], Quotient[11], TR[20], Dividend[10], Divisor, Quotient[12]);
stepof32 myStep23(TR[22], Quotient[10], TR[21], Dividend[9], Divisor, Quotient[11]);
stepof32 myStep24(TR[23], Quotient[9], TR[22], Dividend[8], Divisor, Quotient[10]);
stepof32 myStep25(TR[24], Quotient[8], TR[23], Dividend[7], Divisor, Quotient[9]);
stepof32 myStep26(TR[25], Quotient[7], TR[24], Dividend[6], Divisor, Quotient[8]);
stepof32 myStep27(TR[26], Quotient[6], TR[25], Dividend[5], Divisor, Quotient[7]);
stepof32 myStep28(TR[27], Quotient[5], TR[26], Dividend[4], Divisor, Quotient[6]);
stepof32 myStep29(TR[28], Quotient[4], TR[27], Dividend[3], Divisor, Quotient[5]);
stepof32 myStep30(TR[29], Quotient[3], TR[28], Dividend[2], Divisor, Quotient[4]);
stepof32 myStep31(TR[30], Quotient[2], TR[29], Dividend[1], Divisor, Quotient[3]);
stepof32 myStep32(TR[31], Quotient[1], TR[30], Dividend[0], Divisor, Quotient[2]);
laststepof32 myStep33(Remainder,Quotient[0],TR[31],Divisor,Quotient[1]); //Includes a step similar to stepof32
//$display ("HEllo");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O32AI_PP_BLACKBOX_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32AI_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:50:49 09/24/2013
// Design Name: Contador
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab3/laboratorio3/test_contador.v
// Project Name: laboratorio3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Contador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_contador;
// Inputs
reg enable_cuenta;
reg reset;
// Outputs
wire [3:0] mem_address;
// Instantiate the Unit Under Test (UUT)
Contador uut (
.enable_cuenta(enable_cuenta),
.reset(reset),
.mem_address(mem_address)
);
initial begin
// Initialize Inputs
enable_cuenta = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
enable_cuenta = 1;
#10;
enable_cuenta = 0;
#10;
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_BNC_P_read_AW30h for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_BNC_P_read_AW30h
// Module Name: NPCG_Toggle_BNC_P_read_AW30h
// File Name: NPCG_Toggle_BNC_P_read_AW30h.v
//
// Version: v1.0.0
//
// Description: Page read trigger FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_BNC_P_read_AW30h
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
iWaySelect ,
iColAddress ,
iRowAddress ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CASelect ,
oPM_CAData
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
input [NumberOfWays - 1:0] iWaySelect ;
input [15:0] iColAddress ;
input [23:0] iRowAddress ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
reg [NumberOfWays - 1:0] rTargetWay ;
reg [15:0] rColAddress ;
reg [23:0] rRowAddress ;
wire wModuleTriggered;
wire wTMStart ;
reg [7:0] rPMTrigger ;
reg [2:0] rPCommandOption ;
reg [15:0] rNumOfData ;
reg [7:0] rCAData ;
reg rPMCommandOrAddress ;
localparam State_Idle = 4'b0000 ;
localparam State_NCALIssue = 4'b0001 ;
localparam State_NCmdWrite0 = 4'b0011 ;
localparam State_NAddrWrite0 = 4'b0010 ;
localparam State_NAddrWrite1 = 4'b0110 ;
localparam State_NAddrWrite2 = 4'b0111 ;
localparam State_NAddrWrite3 = 4'b0101 ;
localparam State_NAddrWrite4 = 4'b0100 ;
localparam State_NCmdWrite1 = 4'b1100 ;
localparam State_NTMIssue = 4'b1101 ;
localparam State_WaitDone = 4'b1111 ;
reg [3:0] rCurState ;
reg [3:0] rNextState ;
always @ (posedge iSystemClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (wModuleTriggered)?State_NCALIssue:State_Idle;
State_NCALIssue:
rNextState <= (iPM_Ready)?State_NCmdWrite0:State_NCALIssue;
State_NCmdWrite0:
rNextState <= State_NAddrWrite0;
State_NAddrWrite0:
rNextState <= State_NAddrWrite1;
State_NAddrWrite1:
rNextState <= State_NAddrWrite2;
State_NAddrWrite2:
rNextState <= State_NAddrWrite3;
State_NAddrWrite3:
rNextState <= State_NAddrWrite4;
State_NAddrWrite4:
rNextState <= State_NCmdWrite1;
State_NCmdWrite1:
rNextState <= State_NTMIssue;
State_NTMIssue:
rNextState <= (wTMStart)?State_WaitDone:State_NTMIssue;
State_WaitDone:
rNextState <= (oLastStep)?State_Idle:State_WaitDone;
default:
rNextState <= State_Idle;
endcase
assign wModuleTriggered = (iCMDValid && iTargetID == 5'b00101 && iOpcode == 6'b000000);
assign wTMStart = (rCurState == State_NTMIssue) & iPM_LastStep[3];
assign oCMDReady = (rCurState == State_Idle);
always @ (posedge iSystemClock)
if (iReset)
begin
rTargetWay <= {(NumberOfWays){1'b0}};
rColAddress <= 16'b0;
rRowAddress <= 24'b0;
end
else
if (wModuleTriggered && (rCurState == State_Idle))
begin
rTargetWay <= iWaySelect ;
rColAddress <= iColAddress ;
rRowAddress <= iRowAddress ;
end
always @ (*)
case (rCurState)
State_NCALIssue:
rPMTrigger <= 8'b00001000;
State_NTMIssue:
rPMTrigger <= 8'b00000001;
default:
rPMTrigger <= 0;
endcase
always @ (*)
case (rCurState)
State_NTMIssue:
rPCommandOption[2:0] <= 3'b110;
default:
rPCommandOption[2:0] <= 0;
endcase
always @ (*)
case (rCurState)
State_NCALIssue:
rNumOfData[15:0] <= 16'd6; // 1 cmd + 5 addr + 1 cmd = 7 (=> 6)
State_NTMIssue:
rNumOfData[15:0] <= 16'd3; // 40 ns
default:
rNumOfData[15:0] <= 0;
endcase
always @ (*)
case (rCurState)
State_NCmdWrite0:
rPMCommandOrAddress <= 1'b0;
State_NCmdWrite1:
rPMCommandOrAddress <= 1'b0;
State_NAddrWrite0:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite1:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite2:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite3:
rPMCommandOrAddress <= 1'b1;
State_NAddrWrite4:
rPMCommandOrAddress <= 1'b1;
default:
rPMCommandOrAddress <= 1'b0;
endcase
always @ (posedge iSystemClock)
if (iReset)
rCAData <= 0;
else
case (rNextState)
State_NCmdWrite0:
rCAData <= 8'h00;
State_NAddrWrite0:
rCAData <= rColAddress[7:0];
State_NAddrWrite1:
rCAData <= rColAddress[15:8];
State_NAddrWrite2:
rCAData <= rRowAddress[7:0];
State_NAddrWrite3:
rCAData <= rRowAddress[15:8];
State_NAddrWrite4:
rCAData <= rRowAddress[23:16];
State_NCmdWrite1:
rCAData <= 8'h30;
default:
rCAData <= 0;
endcase
assign oStart = wModuleTriggered;
assign oLastStep = (rCurState == State_WaitDone) & iPM_LastStep[0];
assign oPM_PCommand = rPMTrigger;
assign oPM_PCommandOption = rPCommandOption;//1'b0;
assign oPM_TargetWay = rTargetWay;
assign oPM_NumOfData = rNumOfData; //16'd6;
assign oPM_CASelect = rPMCommandOrAddress;
assign oPM_CAData = rCAData;
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.