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//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module: ram_dp8 - dual port block RAM
//-----------------------------------------------------------------
module ram_dp8
(
aclk_i,
aadr_i,
adat_i,
awr_i,
adat_o,
bclk_i,
badr_i,
bdat_i,
bwr_i,
bdat_o
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] WIDTH = 8;
parameter [31:0] SIZE = 14;
parameter FILENAME = "mem.hex";
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input aclk_i /*verilator public*/;
output [(WIDTH - 1):0] adat_o /*verilator public*/;
input [(WIDTH - 1):0] adat_i /*verilator public*/;
input [(SIZE - 1):0] aadr_i /*verilator public*/;
input awr_i /*verilator public*/;
input bclk_i /*verilator public*/;
output [(WIDTH - 1):0] bdat_o /*verilator public*/;
input [(WIDTH - 1):0] bdat_i /*verilator public*/;
input [(SIZE - 1):0] badr_i /*verilator public*/;
input bwr_i /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */
reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [(SIZE - 1):0] rd_addr_a;
reg [(SIZE - 1):0] rd_addr_b;
wire [(WIDTH - 1):0] adat_o;
wire [(WIDTH - 1):0] bdat_o;
//-----------------------------------------------------------------
// Processes
//-----------------------------------------------------------------
always @ (posedge aclk_i)
begin
if (awr_i == 1'b1)
ram[aadr_i] <= adat_i;
rd_addr_a <= aadr_i;
end
always @ (posedge bclk_i)
begin
if (bwr_i == 1'b1)
ram[badr_i] <= bdat_i;
rd_addr_b <= badr_i;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign adat_o = ram[rd_addr_a];
assign bdat_o = ram[rd_addr_b];
//-----------------------------------------------------------------
// Load memory image
//-----------------------------------------------------------------
integer i;
initial
begin
for (i=0;i<((2<< (SIZE-1)) - 1);i=i+1)
begin
ram[i] = 0;
end
$readmemh(FILENAME, ram);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> v(6); for (int i = 0; i < 6; ++i) cin >> v[i]; int n; cin >> n; vector<pair<int, int>> a; int num; for (int i = 0; i < n; ++i) { cin >> num; for (int j = 0; j < 6; ++j) { a.push_back({num - v[j], i}); } } sort(a.begin(), a.end()); int ans = 1e9 + 7; map<int, int> mp; int t = 0; int l = 0; for (int i = 0; i < a.size(); ++i) { int k = a[i].second; if (mp[k] == 0) { t++; } mp[k]++; while (mp[a[l].second] > 1) { mp[a[l].second]--; l++; } if (t == n) { ans = min(ans, a[i].first - a[l].first); } } cout << ans; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_TB_V
`define SKY130_FD_SC_LS__CLKBUF_TB_V
/**
* clkbuf: Clock tree buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkbuf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_SYMBOL_V
`define SKY130_FD_SC_MS__O311A_SYMBOL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o311a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; double n, r; signed main() { scanf( %lf%lf , &n, &r); printf( %.10f n , 2.0 * n * 0.5 * r * r * sin(acos(-1.0) / (2.0 * n)) / sin(acos(-1.0) - (acos(-1.0) / (2.0 * n)) * 3) * sin(2 * acos(-1.0) / (2.0 * n))); return 0; }
|
/**
*@file tai_ecc.v
*@brief Automatically detect error of TAI counter
*@author LUAN Yuezhen
*@date Origin 2016.11.17
*@tab Tab size = 4 spaces
*/
module tai_ecc(
input clk,
input rst_n,
input pps,
input [63 : 0] tai_sec_1,
input [63 : 0] tai_sec_2,
input [63 : 0] tai_sec_3,
output [63 : 0] tai_sec_correct,
output [ 7 : 0] tai_cnt_err_1,
output [ 7 : 0] tai_cnt_err_2,
output [ 7 : 0] tai_cnt_err_3,
output reg fault_interrupt
);
localparam IDLE = 5'b0;
localparam WAIT_PPS_RISE = 5'b1;
localparam GET_DATA = 5'b10;
localparam CMP_DATA = 5'b100;
localparam ERROR_CNT = 5'b1000;
localparam WAIT_PPS_FALL = 5'b10000;
reg [ 4 : 0] corr_state;
reg [ 4 : 0] corr_next_state;
reg [63 : 0] tai_sec_1_hold;
reg [63 : 0] tai_sec_2_hold;
reg [63 : 0] tai_sec_3_hold;
reg [63 : 0] tai_most_probably_fine;
reg [63 : 0] last_sec;
reg [ 7 : 0] t1_err;
reg [ 7 : 0] t2_err;
reg [ 7 : 0] t3_err;
reg t1_equal_t2;
reg t1_equal_t3;
reg t2_equal_t3;
assign tai_sec_correct = tai_most_probably_fine;
assign tai_cnt_err_1 = t1_err;
assign tai_cnt_err_2 = t2_err;
assign tai_cnt_err_3 = t3_err;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
tai_most_probably_fine <= 64'b0;
end
else begin
tai_most_probably_fine <= ((tai_sec_1 & tai_sec_2 & tai_sec_3) |
(( ~tai_sec_1) & tai_sec_2 & tai_sec_3) |
( tai_sec_1 & (~tai_sec_2) & tai_sec_3) |
( tai_sec_1 & tai_sec_2 & (~tai_sec_3)));
end
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
corr_state <= 0;
end
else begin
corr_state <= corr_next_state;
end
end
always @ (*)
begin
case (corr_state)
IDLE : begin
corr_next_state = WAIT_PPS_RISE;
end
WAIT_PPS_RISE : begin
if (pps) begin
corr_next_state = GET_DATA;
end
else begin
corr_next_state = WAIT_PPS_RISE;
end
end
GET_DATA : begin
corr_next_state = CMP_DATA;
end
CMP_DATA : begin
corr_next_state = ERROR_CNT;
end
ERROR_CNT : begin
corr_next_state = WAIT_PPS_FALL;
end
WAIT_PPS_FALL : begin
if (!pps) begin
corr_next_state = WAIT_PPS_RISE;
end
else begin
corr_next_state = WAIT_PPS_FALL;
end
end
default : begin
corr_next_state = IDLE;
end
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
tai_sec_1_hold <= 64'b0;
tai_sec_2_hold <= 64'b0;
tai_sec_3_hold <= 64'b0;
t1_equal_t2 <= 1'b0;
t1_equal_t3 <= 1'b0;
t2_equal_t3 <= 1'b0;
fault_interrupt <= 1'b0;
t1_err <= 8'b0;
t2_err <= 8'b0;
t3_err <= 8'b0;
end
else begin
case (corr_state)
IDLE : begin
end
WAIT_PPS_RISE : begin
end
GET_DATA : begin
tai_sec_1_hold <= tai_sec_1;
tai_sec_2_hold <= tai_sec_2;
tai_sec_3_hold <= tai_sec_3;
end
CMP_DATA : begin
t1_equal_t2 <= (tai_sec_1_hold == tai_sec_2_hold) ? 1'b1 : 1'b0;
t1_equal_t3 <= (tai_sec_1_hold == tai_sec_3_hold) ? 1'b1 : 1'b0;
t2_equal_t3 <= (tai_sec_2_hold == tai_sec_3_hold) ? 1'b1 : 1'b0;
end
ERROR_CNT : begin
casez ({t1_equal_t2, t1_equal_t3, t2_equal_t3})
3'b11? : begin
fault_interrupt <= 1'b0;
end
3'b10? : begin
t3_err <= t3_err + 1'b1;
fault_interrupt <= 1'b1;
end
3'b01? : begin
t2_err <= t2_err + 1'b1;
fault_interrupt <= 1'b1;
end
3'b001 : begin
t1_err <= t1_err + 1'b1;
fault_interrupt <= 1'b1;
end
3'b000 : begin
fault_interrupt <= 1'b1;
end
endcase
end
WAIT_PPS_FALL : begin
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_4_V
`define SKY130_FD_SC_HDLL__SDFRTP_4_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_4_V
|
#include <bits/stdc++.h> using namespace std; bool si[1000007]; int x0 = 1000007; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int x2; cin >> x2; si[0] = si[1] = false; for (int i = 2; i < 1000007; i++) { si[i] = true; } for (int i = 2; i < 1000007; i++) { if (si[i]) { for (int j = i * 2; j < 1000007; j += i) { si[j] = false; } } } int lp = 0; for (int i = 2; i <= sqrt(x2); i++) { if (x2 % i == 0) { if (si[i]) lp = max(lp, i); if (si[x2 / i]) lp = max(lp, x2 / i); } } for (int x1 = (x2 / lp - 1) * lp + 1; x1 <= x2; x1++) { for (int i = 2; i <= sqrt(x1); i++) { if (x1 % i == 0) { if (si[i]) { if (((x1 / i - 1) * i + 1) >= 3) x0 = min(x0, (x1 / i - 1) * i + 1); } if (si[x1 / i]) { if (((i - 1) * (x1 / i) + 1) >= 3) x0 = min(x0, (i - 1) * (x1 / i) + 1); } } } } cout << x0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; const long long N = 2e5 + 10; ; long long n, p[N], t[N], a[N], b[N], Ma[N], Mi[N], T; long long check(double m) { double M = 0.0; for (long long i = 1, j = 1; i <= n; i++) { while (j <= n && p[b[j]] < p[b[i]]) M = max(M, (1.0 - m * Mi[b[j]] / T) * p[b[j]]), j++; if ((1.0 - m * Ma[b[i]] / T) * p[b[i]] < M) return 0; } return 1; } signed main() { scanf( %lld n , &n); for (long long i = 1; i <= n; i++) scanf( %lld , &p[i]), a[i] = i; for (long long i = 1; i <= n; i++) scanf( %lld , &t[i]), b[i] = i; sort(a + 1, a + n + 1, [&](long long i, long long j) { return p[i] * t[j] > p[j] * t[i]; }); sort(b + 1, b + n + 1, [&](long long i, long long j) { return p[i] < p[j]; }); for (long long i = 1, j, s; i <= n; i = j) { for (j = i + 1, s = 0; j <= n; j++) if (p[a[i]] * t[a[j]] != p[a[j]] * t[a[i]]) break; for (long long k = i; k < j; k++) s += t[a[k]]; for (long long k = i; k < j; k++) Mi[a[k]] = T + t[a[k]], Ma[a[k]] = T + s; T += s; } double l = 0, r = 1; while (r - l > eps) { double mid = (l + r) / 2.0; if (!check(mid)) r = mid; else l = mid; } printf( %.10f n , l); return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: diploma_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module diploma_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites-new/diploma_new.mif",
altsyncram_component.intended_device_family = "Cyclone IV GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites-new/diploma_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites-new/diploma_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL diploma_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int N = 5000 + 10; const int BASE = 1e9 + 7; int n; int memo[N][N], _memo[N][N]; string s; int _solve(int pos_1, int pos_2) { if (pos_1 > n || pos_2 > n) return 0; if (_memo[pos_1][pos_2] != -1) return _memo[pos_1][pos_2]; int cur = 0; if (s[pos_1] == s[pos_2]) cur += _solve(pos_1 + 1, pos_2 + 1) + 1; return _memo[pos_1][pos_2] = cur; } int solve(int pos, int len) { if (s[pos] == 0 ) return 0; if (pos + len - 1 > n) return 0; if (pos + len - 1 == n) return 1; if (memo[pos][len] != -1) return memo[pos][len]; int cur = 0; cur = (cur + solve(pos, len + 1)) % BASE; if (pos + 2 * len - 1 <= n) { int tmp = _solve(pos, pos + len); if (tmp < len && s[pos + tmp] < s[pos + len + tmp]) { cur = (cur + solve(pos + len, len)) % BASE; } else cur = (cur + solve(pos + len, len + 1)) % BASE; } return memo[pos][len] = cur; } int main() { ios ::sync_with_stdio(0); cin.tie(0); cin >> n >> s; s = @ + s; memset(memo, -1, sizeof(memo)); memset(_memo, -1, sizeof(_memo)); cout << solve(1, 1); }
|
`timescale 1 ns / 1 ps
`include "Speck_Block_Cipher_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module Speck_Block_Cipher_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHR_4 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
input RST_N;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
always @(posedge CLK) begin
if (RST_N == 0) begin
r <= RESET_VAL;
end else begin
r <= wire_4;
end
end
endmodule
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 5
*/
// Testbench for behavioral model for the circular FIFO
// Import the modules that will be tested for in this testbench
// IMPORTANT: To run this, try: ncverilog -f fifo.f +gui
module tb_fifo();
reg a;
reg b;
reg c;
reg d;
reg e;
reg [1:0] opA;
reg opB;
reg opC;
reg [0:7] alicia;
reg [0:7] lowery;
reg [0:7] patrice;
initial
begin
opA=1;
opB=0;
opC=1;
//if(opA==opB) ? (b==1):((opC==opB)?(d==1):(e==0)
// opA = (opB==opC) ? 2'd0 : (opA==opB) ? 2'd1:2'd2;
$display("opA",opA);
//2
#10
opA=3;
opB=2;
opC=0;
opA = (opB>opC) ? 2'd0 : (opA==opB) ? 2'd1 : 2'd2;
$display("opA",opA);
//0
#10
opA=2;
opB=2;
opC=3;
opA = (opB<opC) ? 2'd0 : (opA==opB) ? 2'd1 : 2'd2;
$display("opA",opA);
//1
#20
alicia=8'b10110101;
lowery=8'b00000100;
patrice={lowery[0:2],{alicia}};
#20
alicia=8'b10110101;
lowery=8'b00000100;
patrice={{alicia},lowery[0:2]};
#20
alicia=8'b11010100;
$display("a[0]",alicia[0],"a[6]",alicia[6]);
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> #define int long long #define INF (1e15 + 7) #define pii pair<int, int> using namespace std; struct Node { int x, y; Node(int _x = 0, int _y = 0) : x(_x), y(_y) {} bool operator<(const Node &u)const { if (x < u.x) return true; if (x > u.x) return false; return y > u.y; } }; const int MAX_N = 2e5 + 7; Node in[MAX_N], de[MAX_N]; vector<pii> ab, ba; int a[MAX_N], b[MAX_N]; int n, mx, dis, top; inline int low_bound(vector<pii> &s, int x) { while (top && s[top - 1].first > x) { --top; } if (!top) return -1; return s[top - 1].second; } signed main() { // freopen( in.txt , r , stdin); scanf( %lld , &n); for (int i = 1; i <= n; ++i) scanf( %lld , a + i); for (int i = 1; i <= n; ++i) scanf( %lld , b + i); int n1 = 0, n2 = 0; for (int i = 1; i <= n; ++i) { if (a[i] < b[i]) in[++n1] = Node(a[i], b[i]); else if (a[i] > b[i]) de[++n2] = Node(b[i], a[i]); dis += abs(a[i] - b[i]); } sort(in + 1, in + 1 + n1); sort(de + 1, de + 1 + n2); int len1 = 0, len2 = 0; for (int i = 1; i <= n1; ++i) { if (!len1 || in[i].y > ab[len1 - 1].second) { ab.push_back(pii(in[i].x, in[i].y)); ++len1; } } for (int i = 1; i <= n2; ++i) { if (!len2 || de[i].y > ba[len2 -1].second) { ba.push_back(pii(de[i].x, de[i].y)); ++len2; } } top = len2; for (int i = len1 - 1; i >= 0; --i) { int y = low_bound(ba, ab[i].first); if (~y) mx = max(mx, min(y, ab[i].second) - ab[i].first); } top = len1; for (int i = len2 - 1; i >= 0; --i) { int y = low_bound(ab, ba[i].first); if (~y) mx = max(mx, min(y, ba[i].second) - ba[i].first); } printf( %lld n , dis - mx * 2); return 0; }
|
module LCD_TEST ( // Host Side
iCLK,iRST_N,
d0,d1,d2,d3,d4,d5,
// LCD Side
LCD_DATA,LCD_RW,LCD_EN,LCD_RS );
// Host Side
input iCLK,iRST_N;
// Data test
input [15:0] d0,d1,d2,d3,d4,d5;
// LCD Side
output [7:0] LCD_DATA;
output LCD_RW,LCD_EN,LCD_RS;
// Internal Wires/Registers
reg [5:0] LUT_INDEX;
reg [8:0] LUT_DATA;
reg [5:0] mLCD_ST;
reg [17:0] mDLY;
reg mLCD_Start;
reg [7:0] mLCD_DATA;
reg mLCD_RS;
wire mLCD_Done;
parameter LCD_INTIAL = 0;
parameter LCD_RESTART = 4;
parameter LCD_LINE1 = 5;
parameter LCD_CH_LINE = LCD_LINE1+16;
parameter LCD_LINE2 = LCD_LINE1+16+1;
parameter LUT_SIZE = LCD_LINE2+16-1;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mLCD_ST <= 0;
mDLY <= 0;
mLCD_Start <= 0;
mLCD_DATA <= 0;
mLCD_RS <= 0;
end
else
begin
begin
case(mLCD_ST)
0: begin
mLCD_DATA <= LUT_DATA[7:0];
mLCD_RS <= LUT_DATA[8];
mLCD_Start <= 1;
mLCD_ST <= 1;
end
1: begin
if(mLCD_Done)
begin
mLCD_Start <= 0;
mLCD_ST <= 2;
end
end
2: begin
if(mDLY<18'h3FFFE)
mDLY <= mDLY+1;
else
begin
mDLY <= 0;
mLCD_ST <= 3;
end
end
3: begin
if(LUT_INDEX<LUT_SIZE)
LUT_INDEX <= LUT_INDEX+1;
else
LUT_INDEX <= LCD_RESTART;
mLCD_ST <= 0;
end
endcase
end
end
end
function [8:0] hex2char;
input [3:0] h;
hex2char = (h>9 ? 9'h137 : 9'h130) + h;
endfunction
always
begin
case(LUT_INDEX)
// Initial
LCD_INTIAL+0: LUT_DATA <= 9'h038;
LCD_INTIAL+1: LUT_DATA <= 9'h00C;
LCD_INTIAL+2: LUT_DATA <= 9'h001;
LCD_INTIAL+3: LUT_DATA <= 9'h006;
LCD_INTIAL+4: LUT_DATA <= 9'h080;
// Line 1
LCD_LINE1+0: LUT_DATA <= 9'h120;
LCD_LINE1+1: LUT_DATA <= hex2char(d0[15:12]);
LCD_LINE1+2: LUT_DATA <= hex2char(d0[11: 8]);
LCD_LINE1+3: LUT_DATA <= hex2char(d0[ 7: 4]);
LCD_LINE1+4: LUT_DATA <= hex2char(d0[ 3: 0]);
LCD_LINE1+5: LUT_DATA <= 9'h120;
LCD_LINE1+6: LUT_DATA <= hex2char(d1[15:12]);
LCD_LINE1+7: LUT_DATA <= hex2char(d1[11: 8]);
LCD_LINE1+8: LUT_DATA <= hex2char(d1[ 7: 4]);
LCD_LINE1+9: LUT_DATA <= hex2char(d1[ 3: 0]);
LCD_LINE1+10: LUT_DATA <= 9'h120;
LCD_LINE1+11: LUT_DATA <= hex2char(d2[15:12]);
LCD_LINE1+12: LUT_DATA <= hex2char(d2[11: 8]);
LCD_LINE1+13: LUT_DATA <= hex2char(d2[ 7: 4]);
LCD_LINE1+14: LUT_DATA <= hex2char(d2[ 3: 0]);
LCD_LINE1+15: LUT_DATA <= 9'h120;
// Change Line
LCD_CH_LINE: LUT_DATA <= 9'h0C0;
// Line 2
LCD_LINE2+0: LUT_DATA <= 9'h120;
LCD_LINE2+1: LUT_DATA <= hex2char(d3[15:12]);
LCD_LINE2+2: LUT_DATA <= hex2char(d3[11: 8]);
LCD_LINE2+3: LUT_DATA <= hex2char(d3[ 7: 4]);
LCD_LINE2+4: LUT_DATA <= hex2char(d3[ 3: 0]);
LCD_LINE2+5: LUT_DATA <= 9'h120;
LCD_LINE2+6: LUT_DATA <= hex2char(d4[15:12]);
LCD_LINE2+7: LUT_DATA <= hex2char(d4[11: 8]);
LCD_LINE2+8: LUT_DATA <= hex2char(d4[ 7: 4]);
LCD_LINE2+9: LUT_DATA <= hex2char(d4[ 3: 0]);
LCD_LINE2+10: LUT_DATA <= 9'h120;
LCD_LINE2+11: LUT_DATA <= hex2char(d5[15:12]);
LCD_LINE2+12: LUT_DATA <= hex2char(d5[11: 8]);
LCD_LINE2+13: LUT_DATA <= hex2char(d5[ 7: 4]);
LCD_LINE2+14: LUT_DATA <= hex2char(d5[ 3: 0]);
LCD_LINE2+15: LUT_DATA <= 9'h120;
default: LUT_DATA <= 9'h120;
endcase
end
LCD_Controller u0 ( // Host Side
.iDATA(mLCD_DATA),
.iRS(mLCD_RS),
.iStart(mLCD_Start),
.oDone(mLCD_Done),
.iCLK(iCLK),
.iRST_N(iRST_N),
// LCD Interface
.LCD_DATA(LCD_DATA),
.LCD_RW(LCD_RW),
.LCD_EN(LCD_EN),
.LCD_RS(LCD_RS) );
endmodule
|
module FramesyncFSM(clk,rst,DataIn,DataOut,DataOutEn,State,inter,S);
input wire clk,rst,DataIn;
output reg DataOut,DataOutEn;
output reg [1:0]State;
output wire S;
output reg inter;
reg [1:0]MissCount;
reg [1:0]RecCount;
reg [7:0]count;
reg CountEn;
Probe u0(DataIn,S,clk);
//Count256 u1(clk,CountEn,inter);
initial
begin
State<=2'd0;
MissCount<=2'd0; count<=8'd0; RecCount<=2'd0;
end
always@(posedge clk)
begin
if(count==8'b1111_1111) begin inter<=1;count<=0;end
else
begin
inter<=0;
if(CountEn==1) count<=count+1;
else count<=8'b0000_0000;
end
if(rst==0)count<=8'd0;
end
always@(negedge clk)
begin
if(rst==0) begin State<=2'd0; MissCount<=2'd0; RecCount<=2'd0; end
case(State)
2'b00:
begin
if(S==1) begin State<=2'b01;CountEn<=1; end
DataOutEn<=0;
end
2'b01:
begin
if(inter==1&&S==1)
begin
if(RecCount==2'd1) begin State<=2'b10; RecCount<=2'd0; end
else RecCount<=RecCount+1;
end
else if(inter==1&&S==0)begin State<=2'b00;DataOutEn<=1;RecCount<=0; CountEn<=0;end
DataOutEn<=0;
end
2'b10:
begin
if(inter==1&&S==0) State<=2'b11;
if(count<8'd247)
begin
DataOutEn<=1;
DataOut<=DataIn;
end
else DataOutEn<=0;
end
2'b11:
begin
if(inter==1&&S==1) State<=2'b10;
else if(inter==1&&S==0)
begin
if(MissCount==2'd2) begin State<=2'b00; MissCount<=2'd0;CountEn<=0;end
else MissCount<=MissCount+1;
end
DataOutEn<=0;
end
endcase
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_pm_even.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cpx_buf_pm_even(/*AUTOARG*/
// Outputs
arbcp0_cpxdp_grant_ca, arbcp0_cpxdp_q0_hold_ca_l,
arbcp0_cpxdp_qsel0_ca, arbcp0_cpxdp_qsel1_ca_l,
arbcp0_cpxdp_shift_cx, arbcp2_cpxdp_grant_ca,
arbcp2_cpxdp_q0_hold_ca_l, arbcp2_cpxdp_qsel0_ca,
arbcp2_cpxdp_qsel1_ca_l, arbcp2_cpxdp_shift_cx,
arbcp4_cpxdp_grant_ca, arbcp4_cpxdp_q0_hold_ca_l,
arbcp4_cpxdp_qsel0_ca, arbcp4_cpxdp_qsel1_ca_l,
arbcp4_cpxdp_shift_cx, arbcp6_cpxdp_grant_ca,
arbcp6_cpxdp_q0_hold_ca_l, arbcp6_cpxdp_qsel0_ca,
arbcp6_cpxdp_qsel1_ca_l, arbcp6_cpxdp_shift_cx,
// Inputs
arbcp0_cpxdp_grant_arbbf_ca_l, arbcp0_cpxdp_q0_hold_arbbf_ca,
arbcp0_cpxdp_qsel0_arbbf_ca_l, arbcp0_cpxdp_qsel1_arbbf_ca,
arbcp0_cpxdp_shift_arbbf_cx_l, arbcp2_cpxdp_grant_arbbf_ca_l,
arbcp2_cpxdp_q0_hold_arbbf_ca, arbcp2_cpxdp_qsel0_arbbf_ca_l,
arbcp2_cpxdp_qsel1_arbbf_ca, arbcp2_cpxdp_shift_arbbf_cx_l,
arbcp4_cpxdp_grant_arbbf_ca_l, arbcp4_cpxdp_q0_hold_arbbf_ca,
arbcp4_cpxdp_qsel0_arbbf_ca_l, arbcp4_cpxdp_qsel1_arbbf_ca,
arbcp4_cpxdp_shift_arbbf_cx_l, arbcp6_cpxdp_grant_arbbf_ca_l,
arbcp6_cpxdp_q0_hold_arbbf_ca, arbcp6_cpxdp_qsel0_arbbf_ca_l,
arbcp6_cpxdp_qsel1_arbbf_ca, arbcp6_cpxdp_shift_arbbf_cx_l
);
output arbcp0_cpxdp_grant_ca ;
output arbcp0_cpxdp_q0_hold_ca_l ;
output arbcp0_cpxdp_qsel0_ca ;
output arbcp0_cpxdp_qsel1_ca_l ;
output arbcp0_cpxdp_shift_cx ;
output arbcp2_cpxdp_grant_ca ;
output arbcp2_cpxdp_q0_hold_ca_l ;
output arbcp2_cpxdp_qsel0_ca ;
output arbcp2_cpxdp_qsel1_ca_l ;
output arbcp2_cpxdp_shift_cx ;
output arbcp4_cpxdp_grant_ca ;
output arbcp4_cpxdp_q0_hold_ca_l ;
output arbcp4_cpxdp_qsel0_ca ;
output arbcp4_cpxdp_qsel1_ca_l ;
output arbcp4_cpxdp_shift_cx ;
output arbcp6_cpxdp_grant_ca ;
output arbcp6_cpxdp_q0_hold_ca_l ;
output arbcp6_cpxdp_qsel0_ca ;
output arbcp6_cpxdp_qsel1_ca_l ;
output arbcp6_cpxdp_shift_cx ;
input arbcp0_cpxdp_grant_arbbf_ca_l;
input arbcp0_cpxdp_q0_hold_arbbf_ca;
input arbcp0_cpxdp_qsel0_arbbf_ca_l;
input arbcp0_cpxdp_qsel1_arbbf_ca;
input arbcp0_cpxdp_shift_arbbf_cx_l;
input arbcp2_cpxdp_grant_arbbf_ca_l;
input arbcp2_cpxdp_q0_hold_arbbf_ca;
input arbcp2_cpxdp_qsel0_arbbf_ca_l;
input arbcp2_cpxdp_qsel1_arbbf_ca;
input arbcp2_cpxdp_shift_arbbf_cx_l;
input arbcp4_cpxdp_grant_arbbf_ca_l;
input arbcp4_cpxdp_q0_hold_arbbf_ca;
input arbcp4_cpxdp_qsel0_arbbf_ca_l;
input arbcp4_cpxdp_qsel1_arbbf_ca;
input arbcp4_cpxdp_shift_arbbf_cx_l;
input arbcp6_cpxdp_grant_arbbf_ca_l;
input arbcp6_cpxdp_q0_hold_arbbf_ca;
input arbcp6_cpxdp_qsel0_arbbf_ca_l;
input arbcp6_cpxdp_qsel1_arbbf_ca;
input arbcp6_cpxdp_shift_arbbf_cx_l;
assign arbcp0_cpxdp_grant_ca = ~arbcp0_cpxdp_grant_arbbf_ca_l;
assign arbcp0_cpxdp_q0_hold_ca_l = ~arbcp0_cpxdp_q0_hold_arbbf_ca;
assign arbcp0_cpxdp_qsel0_ca = ~arbcp0_cpxdp_qsel0_arbbf_ca_l;
assign arbcp0_cpxdp_qsel1_ca_l = ~arbcp0_cpxdp_qsel1_arbbf_ca;
assign arbcp0_cpxdp_shift_cx = ~arbcp0_cpxdp_shift_arbbf_cx_l;
assign arbcp2_cpxdp_grant_ca = ~arbcp2_cpxdp_grant_arbbf_ca_l;
assign arbcp2_cpxdp_q0_hold_ca_l = ~arbcp2_cpxdp_q0_hold_arbbf_ca;
assign arbcp2_cpxdp_qsel0_ca = ~arbcp2_cpxdp_qsel0_arbbf_ca_l;
assign arbcp2_cpxdp_qsel1_ca_l = ~arbcp2_cpxdp_qsel1_arbbf_ca;
assign arbcp2_cpxdp_shift_cx = ~arbcp2_cpxdp_shift_arbbf_cx_l;
assign arbcp4_cpxdp_grant_ca = ~arbcp4_cpxdp_grant_arbbf_ca_l;
assign arbcp4_cpxdp_q0_hold_ca_l = ~arbcp4_cpxdp_q0_hold_arbbf_ca;
assign arbcp4_cpxdp_qsel0_ca = ~arbcp4_cpxdp_qsel0_arbbf_ca_l;
assign arbcp4_cpxdp_qsel1_ca_l = ~arbcp4_cpxdp_qsel1_arbbf_ca;
assign arbcp4_cpxdp_shift_cx = ~arbcp4_cpxdp_shift_arbbf_cx_l;
assign arbcp6_cpxdp_grant_ca = ~arbcp6_cpxdp_grant_arbbf_ca_l;
assign arbcp6_cpxdp_q0_hold_ca_l = ~arbcp6_cpxdp_q0_hold_arbbf_ca;
assign arbcp6_cpxdp_qsel0_ca = ~arbcp6_cpxdp_qsel0_arbbf_ca_l;
assign arbcp6_cpxdp_qsel1_ca_l = ~arbcp6_cpxdp_qsel1_arbbf_ca;
assign arbcp6_cpxdp_shift_cx = ~arbcp6_cpxdp_shift_arbbf_cx_l;
endmodule
|
#include <bits/stdc++.h> using namespace std; int readint() { char c; while (c = getchar(), (c < 0 || c > 9 ) && c != - ) ; bool flag = (c == - ); if (flag) c = getchar(); int x = 0; while (c >= 0 && c <= 9 ) { x = x * 10 + c - 48; c = getchar(); } return flag ? -x : x; } char readchar() { char c; while (c = getchar(), c != A && c != C && c != < && c != > && c != ^ ) ; return c; } const int maxn = 100005; const int maxm = 15; const int block = 300; int n, m, q, x, y; pair<int, int> pos; char t[maxn][maxm]; pair<int, int> nxt[maxn][maxm], go[maxn][maxm]; inline bool on(pair<int, int> pos) { return pos.first >= 1 && pos.first <= n && pos.second >= 1 && pos.second <= m; } void calc(int x, int y) { if (!on(make_pair(x, y))) { nxt[x][y] = make_pair(x, y); return; } if (nxt[x][y].first != -2) return; if (t[x][y] == < ) { if (t[x][y - 1] == > ) nxt[x][y] = make_pair(-1, -1); else calc(x, y - 1), nxt[x][y] = nxt[x][y - 1]; } else if (t[x][y] == > ) { if (t[x][y + 1] == < ) nxt[x][y] = make_pair(-1, -1); else calc(x, y + 1), nxt[x][y] = nxt[x][y + 1]; } else nxt[x][y] = make_pair(x - 1, y); } void jump(int start, int finish) { for (int i = start; i <= finish && i <= n; i++) { if (i % block == 1) { for (int j = 1; j <= m; j++) go[i][j] = nxt[i][j]; } else { for (int j = 1; j <= m; j++) { if (!on(nxt[i][j])) go[i][j] = nxt[i][j]; else go[i][j] = go[nxt[i][j].first][nxt[i][j].second]; } } } } int main() { n = readint(); m = readint(); q = readint(); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) t[i][j] = readchar(), nxt[i][j] = make_pair(-2, -2); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) calc(i, j); jump(1, n); while (q--) { char type = readchar(); if (type == A ) { pos.first = readint(); pos.second = readint(); while (on(pos)) { pos = go[pos.first][pos.second]; } printf( %d %d n , pos.first, pos.second); } else { x = readint(); y = readint(); char op = readchar(); t[x][y] = op; for (int j = 1; j <= m; j++) nxt[x][j] = make_pair(-2, -2); for (int j = 1; j <= m; j++) calc(x, j); jump(x, x); jump(x + 1, (x / block + (x % block == 0 ? 0 : 1)) * block); } } return 0; }
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#include <iostream> #include <vector> #include <algorithm> #include <map> using namespace std; const int64_t INF = 1e15; struct Dinic { struct Edge { int v; int64_t f, c; Edge(int _v = 0, int64_t _f = 0, int64_t _c = 0): v(_v), f(_f), c(_c) {}; }; int n; vector<int> idx, dep, qu; vector<vector<int>> adj; vector<Edge> edges; Dinic(int _n): n(_n), idx(_n), dep(_n), adj(_n), edges(0) {} void addEdge(int u, int v, int64_t c) { adj[u].push_back((int) edges.size()); edges.emplace_back(v, 0, c); adj[v].push_back((int) edges.size()); edges.emplace_back(u, 0, 0); } bool levelGraph(int s, int t) { qu.clear(); fill(dep.begin(), dep.end(), n + 1); fill(idx.begin(), idx.end(), 0); qu.push_back(s); dep[s] = 0; for (int qi = 0; qi < (int) qu.size() && qu.back() != t; ++qi) { int u = qu[qi]; for (int i : adj[u]) { auto &e = edges[i]; if (e.f < e.c && dep[u] + 1 < dep[e.v]) { dep[e.v] = dep[u] + 1; qu.push_back(e.v); } } } return dep[t] <= n; } int64_t sendFlow(int u, int t, int64_t f) { if (u == t) return f; for (int &i = idx[u]; i < (int) adj[u].size(); ++i) { auto &e = edges[adj[u][i]]; if (e.f < e.c && dep[u] + 1 == dep[e.v]) { int64_t g = sendFlow(e.v, t, min(f, e.c - e.f)); if (g > 0) { edges[adj[u][i]].f += g; edges[adj[u][i] ^ 1].f -= g; return g; } } } return 0; } int64_t maxFlow(int s, int t) { while (levelGraph(s, t)) { while (sendFlow(s, t, INF)); } int64_t flow = 0; for (int i : adj[s]) { flow += edges[i].f; } return flow; } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; map<pair<int, int>, int> a; auto get = [&](int x, int y) { auto it = a.find(make_pair(x, y)); return (it == a.end() ? -1 : it->second); }; cin >> n; Dinic dinic(n * 2 + 2); int s = n * 2, t = n * 2 + 1; int64_t total = 0; for (int i = 0; i < n; ++i) { int x, y, w; cin >> x >> y >> w; dinic.addEdge(2 * i, 2 * i + 1, w); total += w; a[make_pair(x, y)] = i; } for (auto rit = a.begin(); rit != a.end(); ++rit) { int x = rit->first.first, y = rit->first.second, i = rit->second, j; if (x % 2 == 0 && y % 2 == 0) { for (int y0 = y - 1; y0 <= y + 1; y0 += 2) { if (~(j = get(x, y0))) dinic.addEdge(2 * i + 1, 2 * j, INF); } for (int x0 = x - 1; x0 <= x + 1; x0 += 2) { if (~(j = get(x0, y))) dinic.addEdge(2 * j + 1, 2 * i, INF); } } else if (x % 2 == 0) { for (int x0 = x - 1; x0 <= x + 1; x0 += 2) { if (~(j = get(x0, y))) dinic.addEdge(2 * i + 1, 2 * j, INF); } } else if (y % 2 == 0) { dinic.addEdge(s, 2 * i, INF); } else { dinic.addEdge(2 * i + 1, t, INF); } } cout << total - dinic.maxFlow(s, t) << endl; }
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#include <bits/stdc++.h> using namespace std; int main() { int t, n, cnt[2000000]; scanf( %d , &n); for (int i = 0; i < 2000000; ++i) cnt[i] = 0; for (int i = 0; i < n; ++i) { scanf( %d , &t); cnt[t]++; } long long ans = 0; for (int i = 0; i < 2000000 - 1; ++i) { cnt[i + 1] += cnt[i] / 2; if (cnt[i] % 2) ++ans; } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; vector<int> AdjList[maxn]; bool vis[maxn]; int child[maxn]; char ans[maxn]; int n; void dfs(int s, int p = -1) { child[s] = 1; for (int u : AdjList[s]) { if (vis[u]) continue; if (u == p) continue; dfs(u, s); child[s] += child[u]; } } int find_cen(int s, int p, int sz) { for (int u : AdjList[s]) { if (vis[u]) continue; if (u == p) continue; if (child[u] * 2 > sz) return find_cen(u, s, sz); } return s; } void centroid(int u, char c) { dfs(u, u); int cen = find_cen(u, u, child[u]); ans[cen] = c; vis[cen] = 1; for (int v : AdjList[cen]) { if (vis[v]) continue; centroid(v, c + 1); } } signed main() { cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; AdjList[u].push_back(v); AdjList[v].push_back(u); } centroid(1, A ); for (int i = 1; i <= n; i++) { cout << ans[i] << ; } }
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`timescale 1 ns / 1 ps
`include "d_axi_pdm_v1_2_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S_AXI_MAX_BURST_LENGTH 1
`define S_AXI_DATA_BUS_WIDTH 32
`define S_AXI_ADDRESS_BUS_WIDTH 32
`define S_AXI_MAX_DATA_SIZE (`S_AXI_DATA_BUS_WIDTH*`S_AXI_MAX_BURST_LENGTH)/8
module d_axi_pdm_v1_2_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S_AXI AXI4 Lite Local Reg
reg [`S_AXI_DATA_BUS_WIDTH-1:0] S_AXI_rd_data_lite;
reg [`S_AXI_DATA_BUS_WIDTH-1:0] S_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S_AXI_lite_response;
reg [`S_AXI_ADDRESS_BUS_WIDTH-1:0] S_AXI_mtestAddress;
reg [3-1:0] S_AXI_mtestProtection_lite;
integer S_AXI_mtestvectorlite; // Master side testvector
integer S_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S_AXI_mtestvectorlite = 0;
S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS;
S_AXI_mtestProtection_lite = 0;
S_AXI_mtestdatasizelite = `S_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S_AXI_mtestvectorlite = 0; S_AXI_mtestvectorlite <= 3; S_AXI_mtestvectorlite = S_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S_AXI_mtestAddress,
S_AXI_mtestProtection_lite,
S_AXI_test_data_lite[S_AXI_mtestvectorlite],
S_AXI_mtestdatasizelite,
S_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S_AXI_mtestvectorlite,S_AXI_test_data_lite[S_AXI_mtestvectorlite],S_AXI_lite_response);
CHECK_RESPONSE_OKAY(S_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S_AXI_mtestAddress,
S_AXI_mtestProtection_lite,
S_AXI_rd_data_lite,
S_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S_AXI_mtestvectorlite,S_AXI_rd_data_lite,S_AXI_lite_response);
CHECK_RESPONSE_OKAY(S_AXI_lite_response);
COMPARE_LITE_DATA(S_AXI_test_data_lite[S_AXI_mtestvectorlite],S_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S_AXI_mtestvectorlite,S_AXI_mtestvectorlite);
S_AXI_mtestAddress = S_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S_AXI_test_data_lite[0] = 32'h0101FFFF;
S_AXI_test_data_lite[1] = 32'habcd0001;
S_AXI_test_data_lite[2] = 32'hdead0011;
S_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S_AXI_TEST();
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISOLATCH_BEHAVIORAL_V
`define SKY130_FD_SC_LP__INPUTISOLATCH_BEHAVIORAL_V
/**
* inputisolatch: Latching input isolator with inverted enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__inputisolatch (
Q ,
D ,
SLEEP_B
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SLEEP_B_delayed;
wire D_delayed ;
reg notifier ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISOLATCH_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a[5], sum = 0; for (int i = 0; i < 5; i++) { cin >> a[i]; sum += a[i]; } n = sum / 5; if (sum == 0) cout << -1; else if (n * 5 == sum) cout << n; else cout << -1; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, n1, m1; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m; n1 = n, m1 = m; if ((n1 == m1 + 1 and !(n1 + m1 % 2)) or n1 > m1 + 1 or m1 / 2 + (m1 % 2) > n1 + 1 or (m1 / 2 + (m1 % 2)) == n1 + 1 and !(m1 / 2 + (m1 % 2) + n1 % 2)) { cout << -1; exit(0); } int p = 0; for (int i = 0; i < n + m; i++) { if (n1 > m1 or p == 2) cout << 0, p = 0, n1--; else cout << 1, p++, m1--; } return 0; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninja_life.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ninja_life (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/ninja_life.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/ninja_life.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// -----------------------------------------------------------------------
//
// Copyright 2004,2007,2008 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
//
// Main module
/*
4000_0000 - 400F_FFFF Extern SRAM (1 MiB)
BFC0_0000 - BFC0_3FFF Boot ROM (16 KiB) (Preloaded I$ cache)
FF00_0000 - FF00_1FFF Peripherals
Read Write
0 rs232out busy rs232out data
1 rs232in data
2 rs232in count
3 TSC
*/
`timescale 1ns/10ps
`include "../../soclib/pipeconnect.h"
`ifdef SIMULATE_MAIN
`define BLOCKRAM 1
`endif
module main(// Clock and reset
input wire clkin // K5 PLL input clock (50 MHz)
,output wire pld_clkout // L8 Clock to zero-skew buffer Lancelot board
,input wire pld_clkfb // L14 Feedback from pld_clkout to PLL2
,input wire reset_n // C4 CPU Reset button
// Lancelot VGA interface
,output wire [7:0] vga_r // VGA red
,output wire [7:0] vga_g // VGA green
,output wire [7:0] vga_b // VGA blue
,output wire vga_hs // VGA horz sync
,output wire vga_vs // VGA vert sync
,output wire vga_blank_n // VGA DAC force blank
,output wire vga_sync_n // VGA sync enable
,output wire vga_sync_t // VGA sync on R/G/B
,output wire vga_m1 // VGA color space config
,output wire vga_m2 // VGA color space config
`ifdef PS2_ENABLED
// PS/2 keyboard/mouse
,output ps2_sel // PS/2 port input/output select
,inout ps2_kclk // PS/2 keyboard clock
,inout ps2_kdata // PS/2 keyboard data
,inout ps2_mclk // PS/2 mouse clock
,inout ps2_mdata // PS/2 mouse data
`endif
// Push buttons LEDs 7-segments
,input wire [3:0] sw // Pushbutton switches
,output [7:0] led // Debugging LEDs
,output wire [7:0] s7_0 // Debugging 7-segment LEDs
,output wire [7:0] s7_1 // --
`ifndef SIMULATE_MAIN
// Flash-SRAM-Ethernet bus
,output wire [22:0] fse_a // Mainboard common bus address
,inout wire [31:0] fse_d // Mainboard common bus data
,output wire flash_cs_n // Flash ROM CS#
,output wire enet_aen // Ethernet Access Enable
,output wire sram_cs_n // SRAM CS#
,output wire [3:0] sram_be_n // SRAM byte enables
,output wire sram_oe_n // SRAM OE#
,output wire sram_we_n // SRAM WE#
`endif
`ifdef SERIAL_ENABLED
// Serial IO
,output ttya_dcd // Console DCD#
,output ttya_txd // Console TxD
,input ttya_rxd // Console RxD
,input ttya_dtr // Console DTR#
,output ttya_dsr // Console DSR#
,input ttya_rts // Console RTS#
,output ttya_cts // Console CTS#
,output ttya_ri // Console RI#
`endif
,output ttyb_txd // Debug TxD
,input ttyb_rxd // Debug RxD
`ifdef CF_ENABLED
// CompactFlash slot
,output [10:0] cf_a // CompactFlash address bus
,inout [15:0] cf_d // CompactFlash data bus
,input cf_rdy // CompactFlash RDY
,input cf_wait_n // CompactFlash WAIT#
,output cf_ce1_n // CompactFlash CE1#
,output cf_ce2_n // CompactFlash CE2#
,output cf_oe_n // CompactFlash OE#
,output cf_we_n // CompactFlash WE#
,output cf_reg_n // CompactFlash REG#
,input cf_cd1_n // CompactFlash card detect
`endif
// SDRAM
// Audio
// Ethernet
// Flash memory
);
// ------------------------------------------------------------------------
// Reset
// (there is option for extending the reset internally here, if necessary)
// ------------------------------------------------------------------------
// wire rst = ~reset_n;
// ------------------------------------------------------------------------
// PLLs and clock distribution
// ------------------------------------------------------------------------
// XXX Note 45 MHz appears to be the limit for the sram with just 1
// wait state (I happen to know the memory is good for much more
// with a trick I can't explain why works.)
parameter FREQ = 45_454_545; // match clock frequency
parameter BPS = 115_200; // Serial speed
wire [ 7:0] rs232out_d;
wire rs232out_w;
wire rs232out_busy;
wire [ 7:0] rs232in_data;
wire rs232in_attention;
wire mem_waitrequest;
wire [1:0] mem_id;
wire [29:0] mem_address;
wire mem_read;
wire mem_write;
wire [31:0] mem_writedata;
wire [3:0] mem_writedatamask;
wire [31:0] mem_readdata;
wire [1:0] mem_readdataid;
wire `REQ rs232_req;
wire `RES rs232_res;
`ifdef SIMULATE_MAIN
// Flash-SRAM-Ethernet bus
wire [22:0] fse_a; // Mainboard common bus address
wire [31:0] fse_d; // Mainboard common bus data
wire flash_cs_n; // Flash ROM CS#
wire enet_aen; // Ethernet Access Enable
wire sram_cs_n; // SRAM CS#
wire [3:0] sram_be_n; // SRAM byte enables
wire sram_oe_n; // SRAM OE#
wire sram_we_n; // SRAM WE#
`ifndef BLOCKRAM
idt71v416s10 u35(fse_d[15: 0], fse_a[19:2], sram_we_n, sram_oe_n, sram_cs_n,
sram_be_n[0], sram_be_n[1]); // Yep, strange order...
idt71v416s10 u36(fse_d[31:16], fse_a[19:2], sram_we_n, sram_oe_n, sram_cs_n,
sram_be_n[2], sram_be_n[3]);
`endif
`endif
assign flash_cs_n = 1; // Disable flash ROM
assign enet_aen = 1; // Disable Ethernet
`ifdef SIMULATE_MAIN
reg clk = 0;
`else
wire clk;
wire pll_locked;
pll pll(
.inclk0(clkin), // 50 MHz input clock
.c0(clk),
.locked(pll_locked)
);
assign led = {rled[0],rled[1],rled[2],rled[3],rled[4],rled[5],rled[6],rled[7]};
reg [7:0] rled = 0;
`endif // SIMULATE_MAIN
reg [ 3:0] reset_count_up = 0;
`ifdef SIMULATE_MAIN
wire rst = 0;
`else
wire rst = ~reset_n /*reset_count_up != 15*/;
`endif
always @(posedge clk)
if (~reset_n)
reset_count_up <= 0;
else if (rst) begin
if (reset_count_up == 14)
$display("Reset count %d", reset_count_up);
reset_count_up <= reset_count_up + 1'd1;
end
yari yari_inst(
.clock(clk)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.peripherals_req(rs232_req)
,.peripherals_res(rs232_res)
);
`ifdef SIMULATE_MAIN
blockram blockram_inst
(.clock(clk)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
);
defparam blockram_inst.INIT_FILE="`SRAM_INIT";
`else
sram_ctrl sram_ctrl_inst
(.clock(clk)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.sram_a(fse_a[19:2])
,.sram_d(fse_d)
,.sram_cs_n(sram_cs_n)
,.sram_be_n(sram_be_n)
,.sram_oe_n(sram_oe_n)
,.sram_we_n(sram_we_n)
);
defparam sram_ctrl_inst.need_wait = 1;
`endif
rs232out rs232out_inst
(.clock(clk),
.serial_out(ttyb_txd),
.transmit_data(rs232out_d),
.we(rs232out_w),
.busy(rs232out_busy));
defparam rs232out_inst.frequency = FREQ,
rs232out_inst.bps = BPS;
rs232in rs232in_inst
(.clock(clk),
.serial_in(ttyb_rxd),
.received_data(rs232in_data),
.attention(rs232in_attention));
defparam rs232in_inst.frequency = FREQ,
rs232in_inst.bps = BPS;
rs232 rs232_inst(.clk(clk),
.rst(rst),
.rs232_req(rs232_req),
.rs232_res(rs232_res),
.rs232in_attention(rs232in_attention),
.rs232in_data(rs232in_data),
.rs232out_busy(rs232out_busy),
.rs232out_w(rs232out_w),
.rs232out_d(rs232out_d));
`ifdef SIMULATE_MAIN
always #50 clk = ~clk;
initial #50 clk = 0;
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const long long MOD = 1e9 + 7; const int inf = 1e9; const int N = 3e5 + 5; bool flag; template <typename T> istream& operator>>(istream& is, vector<T>& v) { for (auto& i : v) is >> i; return is; } template <typename T> void mul(T& a, T b) { a += b; if (b < (T)0) a += MOD; if (a >= (T)MOD) a -= MOD; } void solve() { int n, a, b; cin >> n >> a >> b; if (abs(a - b) > 1 or a + b + 2 > n) { cout << -1; return; } if (a == 0 and b == 0) { for (int i = 1; i <= n; i++) cout << i << ; return; } vector<int> ans; int l = 1, r = n; if (a > b) { ans.push_back(l++); for (int i = 1; i <= a + b; i++) { if (i % 2) ans.push_back(r--); else ans.push_back(l++); } for (int i = a + b + 1; i < n; i++) ans.push_back(r--); } else { ans.push_back(r--); for (int i = 1; i <= a + b; i++) { if (i % 2 == 0) ans.push_back(r--); else ans.push_back(l++); } for (int i = a + b + 1; i < n; i++) ans.push_back(a == b ? r-- : l++); } for (auto now : ans) cout << now << ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed << setprecision(12); int tt = 1; cin >> tt; while (tt--) { flag = 0; solve(); cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int arr[n], brr[m], check[n], indexer = 0; for (int i = 0; i < n; i++) cin >> arr[i], check[i] = -2; for (int i = 0; i < m; i++) { cin >> brr[i]; for (int j = 0; j < n; j++) if (brr[i] == arr[j]) { check[indexer] = j; indexer++; } } sort(check, check + indexer); for (int j = 0; j < indexer; j++) { cout << arr[check[j]] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, M, i, X, A[100005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> N >> M; for (i = 0; i < 2 * M; i++) { cin >> X; A[X]++; } if (N == M) { for (i = 1; 1; i++) { if (A[i] != 2) { break; } if (i == N) { cout << ring topology n ; return 0; } } } if (N - 1 == M) { for (i = 1; i <= N; i++) { if (A[i] == N - 1) { cout << star topology n ; return 0; } } for (i = 1; 1; i++) { if (A[i] > 2 || A[i] == 0) { break; } if (i == N) { cout << bus topology n ; return 0; } } } cout << unknown topology n ; }
|
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Synchronous Fifo
//
// Revision Information:
// Date Description
//
//
// SVN Revision Information:
// SVN $Revision: 21608 $
// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// Sept 5th. Fix for reading empty fifo.
//
// *********************************************************************/
module spi_fifo( pclk,
presetn,
fiforst,
//fifosize,
data_in,
flag_in,
data_out,
flag_out,
read_in,
write_in,
full_out,
empty_out,
full_next_out,
empty_next_out,
overflow_out,
fifo_count
);
parameter CFG_FRAME_SIZE = 4; // 4-32
parameter FIFO_DEPTH = 4; // 2,4,8,16,32
input pclk;
input presetn;
input fiforst;
//input [1:0] fifosize;
input [CFG_FRAME_SIZE-1:0] data_in;
input read_in;
input write_in;
input flag_in;
output [CFG_FRAME_SIZE-1:0] data_out;
output empty_out;
output full_out;
output empty_next_out;
output full_next_out;
output overflow_out;
output flag_out;
output [5:0] fifo_count;
reg [4:0] rd_pointer_d;
reg [4:0] rd_pointer_q; //read pointer address
reg [4:0] wr_pointer_d;
reg [4:0] wr_pointer_q; //write pointer address
reg [5:0] counter_d;
reg [5:0] counter_q; //counter 5 bits
reg [CFG_FRAME_SIZE:0] fifo_mem_d[0:FIFO_DEPTH-1]; //FIFO has extra flag bit (CFG_FRAME_SIZE + 1)
reg [CFG_FRAME_SIZE:0] fifo_mem_q[0:FIFO_DEPTH-1];
reg [CFG_FRAME_SIZE:0] data_out_dx;
reg [CFG_FRAME_SIZE:0] data_out_d;
reg full_out;
reg empty_out;
reg full_next_out;
reg empty_next_out;
// -----------------------------
// AS: replaced with fixed width
// -----------------------------
//localparam [1:0] FS4 = 2'b00;
//localparam [1:0] FS8 = 2'b01;
//localparam [1:0] FS16 = 2'b10;
//localparam [1:0] FS32 = 2'b11;
//
//
//// AS: replaced with parameter
////reg [5:0] FIFO_DEPTH;
//
//always @(posedge pclk or negedge presetn) // Register as this feeds into lots of logic
//begin
// if (~presetn)
// FIFO_DEPTH <= 4;
// else
// begin
// case (fifosize)
// FS8 : FIFO_DEPTH <= 8;
// FS16 : FIFO_DEPTH <= 16;
// FS32 : FIFO_DEPTH <= 32;
// default : FIFO_DEPTH <= 4;
// endcase
// end
//end
wire [CFG_FRAME_SIZE-1:0] data_out = data_out_d[CFG_FRAME_SIZE-1:0];
wire flag_out = data_out_d[CFG_FRAME_SIZE];
assign overflow_out = (write_in && (counter_q == FIFO_DEPTH)); /* write and fifo full */
integer i;
//------------------------------------------------------------------------------------------------------------
//infer the FIFO - no reset required
always @(posedge pclk)
begin
for (i=0; i<FIFO_DEPTH; i=i+1)
begin
fifo_mem_q[i] <= fifo_mem_d[i];
end
end
//infer the registers and register the flags
always @(posedge pclk or negedge presetn)
begin
if (~presetn)
begin
rd_pointer_q <= 0;
wr_pointer_q <= 0;
counter_q <= 0;
full_out <= 0;
empty_out <= 1;
full_next_out <= 0;
empty_next_out <= 0;
end
else
begin
rd_pointer_q <= rd_pointer_d;
wr_pointer_q <= wr_pointer_d;
counter_q <= counter_d;
full_out <= (counter_d == FIFO_DEPTH); //is next pointer equal to fifo length
empty_out <= (counter_d == 0);
full_next_out <= (counter_q == FIFO_DEPTH-1);
empty_next_out <= (counter_q == 1);
end
end
integer j;
always @(*)
begin
for (j=0; j<FIFO_DEPTH; j=j+1) // Hold old values
begin
fifo_mem_d[j] = fifo_mem_q[j];
end
if (write_in)
begin
if (counter_q != FIFO_DEPTH)
begin
// -----------------------------------------
// AS: replaced with fixed size (CFG_FRAME_SIZE)
// -----------------------------------------
fifo_mem_d[wr_pointer_q[4:0]][CFG_FRAME_SIZE-1:0] = data_in[CFG_FRAME_SIZE-1:0];
fifo_mem_d[wr_pointer_q[4:0]][CFG_FRAME_SIZE] = flag_in;
end
end
//Read - data out always available
data_out_dx = fifo_mem_q[rd_pointer_q[4:0]];
end
// Perform extra read mux on Byte/Half wide reads
always @(*)
begin
// AS: removed Byte/Half wide read option
// flag bits are zero if count zero
data_out_d = data_out_dx[CFG_FRAME_SIZE:0];
if (counter_q == 0) data_out_d[CFG_FRAME_SIZE] = 1'b0;
end
// Pointers and Flags
always @(*)
begin
if (fiforst==1'b1)
begin
wr_pointer_d = 5'b00000;
rd_pointer_d = 5'b00000;
counter_d = 6'b000000;
end
else
begin
//defaults
counter_d = counter_q;
rd_pointer_d = rd_pointer_q;
wr_pointer_d = wr_pointer_q;
if (read_in)
begin
if (counter_q != 0) // ignore read when empty
begin
if (~write_in) //if not writing decrement count of the number of objects in fifo else count stays the same
begin
counter_d = counter_q - 1'b1;
end
// AS: Added limits for wrap-around
if (rd_pointer_q == FIFO_DEPTH - 1)
rd_pointer_d = 5'b00000;
else
rd_pointer_d = rd_pointer_q + 1'b1;
end
end //~read_n
if (write_in)
begin
if (counter_q != FIFO_DEPTH) // ignore write when full
begin
if (~read_in)
begin
counter_d = counter_q + 1'b1;
end
// AS: Added limits for wrap-around
if (wr_pointer_q == FIFO_DEPTH-1)
wr_pointer_d = 5'b00000;
else
wr_pointer_d = wr_pointer_q + 1'b1;
end //~write_n
end
end
end
wire [5:0] fifo_count = counter_q;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_clgen.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
`include "timescale.v"
module spi_flash_clgen (clk_in, rst, go, enable, last_clk, clk_out, pos_edge, neg_edge);
parameter divider_len = 2;
parameter divider = 1;
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
//input [spi_divider_len-1:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg pos_edge;
reg neg_edge;
reg [divider_len-1:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {divider_len{1'b0}};
assign cnt_one = cnt == {{divider_len-1{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
cnt <= #Tp {divider_len{1'b1}};
else
begin
if(!enable || cnt_zero)
cnt <= #Tp divider;
else
cnt <= #Tp cnt - {{divider_len-1{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
clk_out <= #Tp 1'b0;
else
clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst)
begin
if(rst)
begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end
else
begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAP_3_V
`define SKY130_FD_SC_LP__DECAP_3_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 3 units (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decap_3 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decap_3 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAP_3_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; int t; long long n; vector<int> v; long long cnt[30]; long long pos[30]; long long fact[21]; void init() { for (int i = 0; i < int(30); i++) cnt[i] = pos[i] = 0; v.clear(); } int main() { cin.tie(0); ios_base::sync_with_stdio(false); fact[0] = 1; for (int i = 1; i <= 20; i++) fact[i] = fact[i - 1] * i; cin >> t; while (t--) { init(); long long n; cin >> n; int cur = 2; while (n) { v.push_back(n % cur); n /= cur; cur++; } sort(v.begin(), v.end()); for (int i = 0; i < int(v.size()); i++) cnt[v[i]]++; pos[1] = cnt[0]; for (int i = 2; i <= v.size() + 1; i++) pos[i] = pos[i - 1] + cnt[i - 1]; long long A = 1; for (int i = 2; i <= v.size() + 1; i++) A *= (pos[i] - (i - 2)); long long B = 1; if (cnt[0] == 0) B = 0; else { B = cnt[0]; for (int i = 2; i <= v.size(); i++) B *= (pos[i] - (i - 1)); } long long ans = A - B; for (int i = 0; i < int(21); i++) ans /= fact[cnt[i]]; cout << ans - 1 << n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_SYMBOL_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PS_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PG_N_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31A_TB_V
`define SKY130_FD_SC_LS__O31A_TB_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o31a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ls__o31a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31A_TB_V
|
#include <bits/stdc++.h> using namespace std; int mymax(int x) { int max = 0; while (x) { int s = x % 10; if (s > max) max = s; x /= 10; } return max; } int zh(int x, int n) { int s = 0, p = 1; while (x) { s += x % 10 * p; x /= 10; p *= n; } return s; } int main() { int a, b; cin >> a >> b; int n = max(mymax(a), mymax(b)) + 1; int num = zh(a, n) + zh(b, n); int j = 0; while (num) { int s = num % n; num /= n; j++; } cout << j << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<pair<long long, long long>>> adj; vector<long long> d; long long n; vector<bool> mark; vector<long long> trains; void dijktras(long long s) { d[s] = 0; priority_queue<pair<long long, long long>, vector<pair<long long, long long>>, greater<pair<long long, long long>>> pq; pq.push({0, s}); for (long long i = 2; i <= n; i++) { if (trains[i] != INT_MAX) pq.push({trains[i], i}); } while (!pq.empty()) { long long v = pq.top().second; long long d_v = pq.top().first; pq.pop(); if (d_v != d[v]) continue; for (auto edge : adj[v]) { long long to = edge.first; long long len = edge.second; if (d[to] > d[v] + len) { d[to] = d[v] + len; pq.push({d[to], to}); } else if (d[to] == d[v] + len) { if (d[to] == trains[to]) mark[to] = true; } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long m, k; cin >> n >> m >> k; adj.resize(n + 1); d.assign(n + 1, INT_MAX); mark.assign(n + 1, false); while (m--) { long long u, v, w; cin >> u >> v >> w; adj[u].push_back({v, w}); adj[v].push_back({u, w}); } long long ans = 0; trains.assign(n + 1, INT_MAX); while (k--) { long long s, y; cin >> s >> y; if (d[s] == INT_MAX) { d[s] = y; trains[s] = y; } else { ans++; trains[s] = min(trains[s], y); d[s] = min(d[s], y); } } dijktras(1); for (int i = 2; i <= n; i++) if (d[i] < trains[i] && trains[i] != INT_MAX) { mark[i] = true; } for (int i = 2; i <= n; i++) if (mark[i]) ans++; cout << ans << n ; cout << n ; return 0; }
|
`timescale 1 ns / 1 ps
module hapara_bram_dma_switch_v1_0 #
(
// Users to add parameters here
parameter integer BRAM_ADDR_WIDTH = 14,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
input [BRAM_ADDR_WIDTH - 1 : 0] addr_ctrl,
input [C_S00_AXI_DATA_WIDTH - 1 : 0] data_in_ctrl,
output [C_S00_AXI_DATA_WIDTH - 1 : 0] data_out_ctrl,
input [C_S00_AXI_DATA_WIDTH / 8 - 1 : 0] we_ctrl,
input clk_ctrl,
input rst_ctrl,
input en_ctrl,
output [BRAM_ADDR_WIDTH - 1 : 0] addr_inst,
output [C_S00_AXI_DATA_WIDTH - 1 : 0] data_in_inst,
input [C_S00_AXI_DATA_WIDTH - 1 : 0] data_out_inst,
output [C_S00_AXI_DATA_WIDTH / 8 - 1 : 0] we_inst,
output clk_inst,
output rst_inst,
output en_inst,
output [BRAM_ADDR_WIDTH - 1 : 0] addr_data,
output [C_S00_AXI_DATA_WIDTH - 1 : 0] data_in_data,
input [C_S00_AXI_DATA_WIDTH - 1 : 0] data_out_data,
output [C_S00_AXI_DATA_WIDTH / 8 - 1 : 0] we_data,
output clk_data,
output rst_data,
output en_data,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
wire [C_S00_AXI_DATA_WIDTH - 1 : 0] base_full;
wire [C_S00_AXI_DATA_WIDTH - 1 : 0] length_full;
hapara_bram_dma_switch_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) hapara_bram_dma_switch_v1_0_S00_AXI_inst (
.base(base_full),
.length(length_full),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
wire [BRAM_ADDR_WIDTH - 1 : 0] base_addr;
wire [BRAM_ADDR_WIDTH - 1 : 0] length_addr;
assign base_addr = base_full[BRAM_ADDR_WIDTH - 1 : 0];
assign length_addr = length_full[BRAM_ADDR_WIDTH - 1 : 0];
localparam BYTE_WIDTH = C_S00_AXI_DATA_WIDTH / 8;
assign clk_inst = clk_ctrl;
assign clk_data = clk_ctrl;
assign rst_inst = rst_ctrl;
assign rst_data = rst_ctrl;
assign we_inst = ((addr_ctrl >= base_addr) && (addr_ctrl < (base_addr + length_addr)))?
we_ctrl :
{BYTE_WIDTH{1'b0}};
assign we_data = we_ctrl;
assign addr_inst = addr_ctrl;
assign addr_data = addr_ctrl;
assign data_in_inst = data_in_ctrl;
assign data_in_data = data_in_ctrl;
assign en_inst = en_ctrl;
assign en_data = en_ctrl;
assign data_out_ctrl = data_out_data;
// User logic ends
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $
//
// $Date: 2004/02/18 11:40:46 $
// $Revision: 1.7 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_byte_ctrl.v,v $
// Revision 1.7 2004/02/18 11:40:46 rherveille
// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
//
// Revision 1.6 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.5 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.4 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.3 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
// synopsys translate_off
`timescale 1ns / 10ps
// synopsys translate_on
// bitcontroller states
`define I2C_CMD_NOP 4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP 4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ 4'b1000
module i2c_master_byte_ctrl (
clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
//
// inputs & outputs
//
input clk; // master clock
input rst; // synchronous active high reset
input nReset; // asynchronous active low reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
//
// Variable declarations
//
// statemachine
parameter ST_IDLE = 5'b0_0000;
parameter ST_START = 5'b0_0001;
parameter ST_READ = 5'b0_0010;
parameter ST_WRITE = 5'b0_0100;
parameter ST_ACK = 5'b0_1000;
parameter ST_STOP = 5'b1_0000;
// signals for bit_controller
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.rst ( rst ),
.nReset ( nReset ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk or negedge nReset)
if (!nReset)
sr <= #1 8'h0;
else if (rst)
sr <= #1 8'h0;
else if (ld)
sr <= #1 din;
else if (shift)
sr <= #1 {sr[6:0], core_rxd};
// generate counter
always @(posedge clk or negedge nReset)
if (!nReset)
dcnt <= #1 3'h0;
else if (rst)
dcnt <= #1 3'h0;
else if (ld)
dcnt <= #1 3'h7;
else if (shift)
dcnt <= #1 dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [4:0] c_state; // synopsis enum_state
always @(posedge clk or negedge nReset)
if (!nReset)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else if (rst | i2c_al)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
ld <= #1 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
ld <= #1 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= #1 core_rxd;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
endcase
end
endmodule
|
//--------------------------------------------------------------------------------
//
// Copyright (C) 2013 Iztok Jeras
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
`timescale 1ns/1ps
module shifter #(
parameter integer DW = 32
)(
// system signals
input wire clk,
input wire rst,
// control signals
input wire ctl_clr,
input wire ctl_ena,
// configuration signals
input wire [DW-1:0] cfg_mask,
// input stream
input wire sti_valid,
output wire sti_ready,
input wire [DW-1:0] sti_data,
// output stream
output wire sto_valid,
input wire sto_ready,
output wire [DW-1:0] sto_data
);
// number of data procesing layers
localparam DL = $clog2(DW);
// input data path signals
wire sti_transfer;
assign sti_transfer = sti_valid & sti_ready;
// delay data path signals
reg [DL-1:0] [DW-1:0] pipe_data;
reg [DL-1:0] pipe_valid = {DL{1'b0}};
wire [DL-1:0] pipe_ready;
// shifter dynamic control signal
reg [DW-1:0] [DL-1:0] shift;
// rotate right
//function [DW-1:0] rtr (
// input [DW-1:0] data,
// input integer len
//);
// rtr = {data [DW-len-1:0], data [DW-1:DW-len]};
//endfunction
// control path
always @ (posedge clk, posedge rst)
if (rst) begin
pipe_valid <= {DL{1'b0}};
end else if (ctl_ena) begin
pipe_valid <= {pipe_valid [DL-2:0], sti_valid};
end
// data path
genvar l, b;
generate
for (l=0; l<DL; l=l+1) begin: layer
for (b=0; b<DW; b=b+1) begin: dbit
always @ (posedge clk)
if (ctl_ena) pipe_data[l][b] <= shift[b][l] ? pipe_data[l-1][(b+l)%DW] : pipe_data[l-1][b];
end
end
endgenerate
// combinatorial bypass
assign sto_valid = !ctl_ena ? sti_valid : pipe_valid[DL-1];
assign sto_data = !ctl_ena ? sti_data : pipe_data [DL-1];
assign sti_ready = !ctl_ena ? sto_ready : pipe_ready[0] | ~pipe_valid[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 4e5 + 5; int n, I; int a[MAXN], num[MAXN]; int read() { int s = 1, x = 0; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) s = -1; ch = getchar(); } while (isdigit(ch)) { x = 10 * x + ch - 0 ; ch = getchar(); } return x * s; } int main() { n = read(), I = read(); int maxk = 8 * I / n, maxK = pow(2, maxk); if (maxk >= 20) { cout << 0 n ; return 0; } for (int i = 1; i <= n; ++i) a[i] = read(); sort(a + 1, a + n + 1); int cnt = 1; num[cnt] = 1; for (int i = 2; i <= n; ++i) { if (a[i] == a[i - 1]) num[cnt]++; else num[++cnt] = num[cnt - 1] + 1; } if (cnt <= maxK) { cout << 0 n ; return 0; } int max_con = -1; for (int i = maxK; i <= cnt; ++i) { int tmp = num[i] - num[i - maxK]; max_con = max(max_con, tmp); } cout << n - max_con << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_BLACKBOX_V
`define SKY130_FD_SC_HS__A311O_BLACKBOX_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_BLACKBOX_V
|
// bsg_nonsynth_dpi_to_fifo: A FIFO Interface for transmitting FIFO
// data from C/C++ into simulation via DPI
//
// Parameters:
//
// width_p: is the bit-width of the FIFO interface. Must be a power
// of 2 and divisible by 8, i.e. a ctype.
//
// debug_p: is the intial value to set on debug_o and to control
// debug messages. The bsg_dpi_debug() DPI function can be used to
// control messages at runtime, but this allows it to be set in
// the initial block, before any runtime functions can be called.
//
// Functions:
//
// init(): Initialize this FIFO DPI Interface. Init must be called
// before any other function
//
// bsg_dpi_debug(input bit): Enable or disable BSG DBGINFO messages
// from this module and set the debug_o output bit.
//
// width(): Return the bit-width of data_i
//
// fini(): De-Initialize this FIFO DPI Interface. This must be
// called before $finish is called in the testbench.
//
// bsg_dpi_fifo_tx(input bit [width_p-1:0] data_i): Write data_i to the FIFO
// interface and set v_o. If the consumer is ready (ready_i === 1)
// this function will return 1 to indicate that the consumer
// accepted the data. Ifthe consumer is not ready (ready_i === 0)
// this function will return 0 to indicate that the consumer did
// not accept the data.
//
// If the data is not accepted by the consumer FIFO, the host
// C/C++ program MUST call this method again on the next cycle.
//
// If the data is not accepted by the consumer FIFO, the host
// C/C++ program MUST call this this method with the same
// arguments (i.e. data_i should remain constant across calls).
//
// bsg_dpi_fifo_tx() CAN ONLY be called after the positive edge of clk_i is
// evaluated.
//
// bsg_dpi_fifo_tx() CAN ONLY be called only once per clk_i cycle.
//
// Violating any of these constraints this will cause $fatal to be
// called to indicate a protocol violation.
//
// For safe operation of this interface use the bsg_nonsynth_fifo_to_dpi
// class provided in bsg_nonsynth_fifo.hpp header.
`include "bsg_defines.v"
module bsg_nonsynth_dpi_to_fifo
#(
parameter `BSG_INV_PARAM(width_p )
,parameter bit debug_p = 0
)
(
input clk_i
, input reset_i
, output logic v_o
, output logic [width_p-1:0] data_o
, input ready_i
, output bit debug_o);
// This bit tracks whether initialize has been called. If data is
// sent and recieved before init() is called, then this module will
// call $fatal
bit init_r = 0;
// This bit checks whether bsg_dpi_fifo_tx() has been called multiple times in a
// cycle.
bit tx_r = 0;
// Check if width_p is a ctype width. call $fatal, if not.
if (!(width_p == 32'd8 || width_p == 32'd16 || width_p == 32'd32 || width_p == 32'd64 || width_p == 32'd128)) begin
$fatal(1, "BSG ERROR (%M): width_p of %d is not supported. Must be a power of 2 and divisible by 8", width_p);
end
// Print module parameters to the console and set the intial debug
// value
initial begin
debug_o = debug_p;
$display("BSG INFO: bsg_nonsynth_dpi_to_fifo (initial begin)");
$display("BSG INFO: Instantiation: %M");
$display("BSG INFO: width_p = %d", width_p);
$display("BSG INFO: debug_p = %d", debug_p);
end
// This checks that fini was called before $finish
final begin
if (init_r === 1)
$fatal(1, "BSG ERROR (%M): fini() was not called before $finish");
end
export "DPI-C" function bsg_dpi_init;
export "DPI-C" function bsg_dpi_fini;
export "DPI-C" function bsg_dpi_debug;
export "DPI-C" function bsg_dpi_width;
export "DPI-C" function bsg_dpi_fifo_tx;
export "DPI-C" function bsg_dpi_fifo_is_window;
// Set or unset the debug_o output bit. If a state change occurs
// (0->1 or 1->0) then module will print DEBUG ENABLED / DEBUG
// DISABLED. No messages are printed if a state change does not
// occur.
function void bsg_dpi_debug(input bit switch_i);
if(!debug_o & switch_i)
$display("BSG DBGINFO (%M@%t): DEBUG ENABLED", $time);
else if (debug_o & !switch_i)
$display("BSG DBGINFO (%M@%t): DEBUG DISABLED", $time);
debug_o = switch_i;
endfunction
// Silly, but useful.
function int bsg_dpi_width();
return width_p;
endfunction
// Initialize this FIFO DPI Interface
function void bsg_dpi_init();
if(debug_o)
$display("BSG DBGINFO (%M@%t): bsg_dpi_init() called", $time);
if(init_r)
$fatal(1, "BSG ERROR (%M): bsg_dpi_init() already called");
init_r = 1;
endfunction
// Terminate this FIFO DPI Interface
function void bsg_dpi_fini();
if(debug_o)
$display("BSG DBGINFO (%M@%t): bsg_dpi_fini() called", $time);
if(~init_r)
$fatal(1, "BSG ERROR (%M): bsg_dpi_fini() already called");
init_r = 0;
endfunction
// bsg_dpi_fifo_tx(input logic [width_p-1:0] data_i) -- Provide data_i
// to the FIFO interface on data_o and set v_o. When the consumer
// is ready (ready_i == 1) this function will return 1 to indicate
// that the consumer accepted the data. When the consumer is not
// ready this function will return 0 to indicate that the consumer
// did not accept the data.
//
// If the data is not consumed, the host C/C++ program MUST call
// this method again on the next cycle with the same arguments
// (i.e. data_i should remain constant across calls). Not doing
// this will cause $fatal to be called to indicate a protocol
// violation because v_o will return to 0 in the next cycle.
//
// bsg_dpi_fifo_tx() MUST be called after the positive edge of clk_i is
// evaluated. It MUST be called only once per cycle. Failure will
// cause an error and a call to $fatal.
// We set v_o_n so that we can signal a read to the producer on the
// NEXT positive edge. v_o_n flows to v_o on the negative edge of
// clk_i
logic v_o_n;
// Same as above, but with data_o.
logic [width_p-1:0] data_o_n;
// We track the "last" data_o and last ready_i values to detect
// protocol violations. These are captured on the positive edge of
// the clock
reg [width_p-1:0] data_o_r;
reg ready_i_r;
// We track the polarity of the current edge so that we can call
// $fatal when $rx is called during the wrong phase of clk_i.
reg edgepol;
always @(posedge clk_i or negedge clk_i) begin
edgepol <= clk_i;
end
function bit bsg_dpi_fifo_tx(input bit [width_p-1:0] data_bi);
if(init_r === 0) begin
$fatal(1, "BSG ERROR (%M): bsg_dpi_fifo_tx() called before init()");
end
if(reset_i === 1) begin
$fatal(1, "BSG ERROR (%M): bsg_dpi_fifo_tx() called while reset_i === 1");
end
if(tx_r !== 0) begin
$fatal(1, "BSG ERROR (%M): bsg_dpi_fifo_tx() called multiple times in a clk_i cycle");
end
if(clk_i === 0) begin
$fatal(1, "BSG ERROR (%M): bsg_dpi_fifo_tx() must be called when clk_i == 1");
end
if(edgepol === 0) begin
$fatal(1, "BSG ERROR (%M): bsg_dpi_fifo_tx() must be called after the positive edge of clk_i has been evaluated");
end
if((ready_i_r === 0 & v_o === 1) & !(data_bi === data_o_r)) begin
$fatal(1, "BSG ERROR (%M): bsg_dpi_fifo_tx() argument data_bi must be constant across calls/cycles when the consumer is not ready");
end
// These will flow to their respective outputs on the next
// negative clock edge.
v_o_n = '1;
data_o_n = data_bi;
tx_r = 1;
if(debug_o)
$display("BSG DBGINFO (%M@%t): bsg_dpi_fifo_tx() called -- ready_i: %b, data_o_n: 0x%x",
$time, ready_i, data_bi);
return (ready_i === 1);
endfunction
// The function bsg_dpi_fifo_is_window returns true if the interface is
// in a valid time-window to call bsg_dpi_fifo_tx()
function bit bsg_dpi_fifo_is_window();
return (~tx_r & clk_i & edgepol & ~reset_i);
endfunction
// We set v_o and data_o on a negative clock edge so that it is
// seen on the next positive edge. v_o_n and data_o_n hold the "next"
// values for v_o and data_o.
//
// We proactively clear v_o by setting v_o_n to 0 in case ready_i ==
// 1 on the positive edge. If ready_i == 1, and we don't set v_o_n
// here, then the user will have to call tx again to clear v_o even
// though they aren't sending data. If ready_i === 0 then the user
// MUST call tx again and v_o will be set to 1 again, otherwise
// $fatal will be called because dropping v_o without ready_i === 1
// is a protocol violation.
//
// If the user wants to send NEW data after ready_i === 1, they
// will call bsg_dpi_fifo_tx() and v_o will be set to 1 again.
always @(negedge clk_i) begin
// If the user fails to call bsg_dpi_fifo_tx() AGAIN (v_o_n === 0) after a
// data beat was not accepted (v_o == 1 && ready_i == 0) that is
// a protocol error.
if(v_o_n === 0 & (v_o === 1 & ready_i_r === 0)) begin
$fatal(1, "BSG ERROR: bsg_dpi_fifo_tx() was not called again on the cycle after the consumer was not ready");
end
data_o <= data_o_n;
v_o <= v_o_n;
v_o_n = 0;
end
// Save the last ready_i and data_o values for protocol checking
// and reset tx_r to 0 to.
always @(posedge clk_i) begin
ready_i_r <= ready_i;
data_o_r <= data_o;
// reset v_o to 0 so that negedge clk assertions aren't triggered.
v_o <= v_o_n;
tx_r = 0;
if(debug_o)
$display("BSG DBGINFO (%M@%t): posedge clk_i -- reset_i: %b v_o: %b ready_i: %b data_i: 0x%x",
$time, reset_i, v_o, ready_i, data_o);
end
endmodule // bsg_nonsynth_dpi_to_fifo
`BSG_ABSTRACT_MODULE(bsg_nonsynth_dpi_to_fifo)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
// see bug 591
package pkg1;
parameter PARAM2 = 16;
parameter PARAM3 = 16;
endpackage : pkg1
package pkg10;
import pkg1::*;
import pkg1::*; // Ignore if already
`ifdef T_PACKAGE_EXPORT
export *::*; // Not supported on all simulators
`endif
parameter PARAM1 = 8;
endpackage
package pkg11;
import pkg10::*;
endpackage
package pkg20;
import pkg1::*;
`ifdef T_PACKAGE_EXPORT
export pkg1::*;
`endif
parameter PARAM1 = 8;
endpackage
package pkg21;
import pkg20::*;
endpackage
package pkg30;
import pkg1::*;
`ifdef T_PACKAGE_EXPORT
export pkg1::PARAM2;
export pkg1::PARAM3;
`endif
`ifdef T_PACKAGE_EXPORT_BAD
export pkg1::BAD_DOES_NOT_EXIST;
`endif
parameter PARAM1 = 8;
endpackage
package pkg31;
import pkg30::*;
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [pkg11::PARAM1 : 0] bus11;
reg [pkg11::PARAM2 : 0] bus12;
reg [pkg11::PARAM3 : 0] bus13;
reg [pkg21::PARAM1 : 0] bus21;
reg [pkg21::PARAM2 : 0] bus22;
reg [pkg21::PARAM3 : 0] bus23;
reg [pkg31::PARAM1 : 0] bus31;
reg [pkg31::PARAM2 : 0] bus32;
reg [pkg31::PARAM3 : 0] bus33;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// Author: Zhangfeifei ////
//// ////
//// Advance Test Technology Laboratory, ////
//// Institute of Computing Technology, ////
//// Chinese Academy of Sciences ////
//// ////
//// If you encountered any problem, please contact : ////
//// Email: or ////
//// Tel: +86-10-6256 5533 ext. 5673 ////
//// ////
//// Downloaded from: ////
//// http://www.opencores.org/pdownloads.cgi/list/ucore ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2005-2006 Zhangfeifei ////
//// ////
//// ////
//// ////
//// This source file may be used and distributed freely without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and any derivative work contains the ////
//// original copyright notice and the associated disclaimer. ////
//// ////
//// Please let the author know if it is used ////
//// for commercial purpose. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Date of Creation: 2005.12.3 ////
//// ////
//// Version: 0.0.1 ////
//// ////
//// Description: branch prediction module of ucore processor ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Change log: ////
//// ////
/////////////////////////////////////////////////////////////////////
`include "ucore_defines.v"
//`define DEBUG
module predict
(
input clk_i,
input rst_i,
// Datas from PF pipeline stage
input [31:0] EI_adr, // PC of the current instruction extracted
// Datas from DI pipeline stage
input DI_bra, // Branch detected
input DI_jmp,
input [31:0] DI_jmp_target,
input [31:0] DI_adr, // Address of the branch
// Datas from EX pipeline stage
input EX_bra_confirm, // Confirm if the branch test is ok
input EX_jr,
input [31:0] EX_adr, // Address of the branch
input [31:0] EX_adresse, // Result of the branch
input EX_cleared, // Define if the EX stage is cleared
// Outputs to PF pipeline stage
output reg PR_bra_cmd, // Defined a branch
output reg PR_bra_bad, // Defined a branch to restore from a bad prediction
output reg [31:0] PR_bra_adr, // New PC
// Clear the pipeline stage : EI
output reg PR_clear_EI,
// Clear the pipeline stage : DI
output reg PR_clear_DI
);
parameter nb_record = 2 ;
parameter nb_record_width = 1;//nb_record = 2^nb_record_width
`define BRA_ADDR [31:0]
`define CODE_ADDR [63:32]
`define LAST_BRA [64]
`define VALID [65]
//Record contained in the table of prediction
//the arrangement of the table are as follow
// [31:0] : bra_addr,the target of the branch
// [63:32] : code_addr, the address of the branch in the code
// [64] last_bra: if it branch last time
// [65] valid : if the record if valid
// Table of predictions
/*reg [65:0] pred_tab[nb_record-1:0];
reg [65:0] record_add;
reg [nb_record_width-1:0] next_out; // Next record to be erased in the table
reg flag_add;
reg [65:0] record_modify;
reg [nb_record_width-1:0] next_modify;
reg flag_modify;
// Update the table of prediction
always @(posedge clk_i or posedge rst_i)
begin:CLK_SECTION
integer i;
if(rst_i == 1)
begin
next_out <= 0; // At the beginning the first record must be chosen to be filled
for(i=0;i<nb_record;i=i+1)
pred_tab[i] <= 66'b0;
end
else begin
if (flag_add == 1)
begin
pred_tab[next_out] <= record_add;
next_out <= next_out+1; // Next record to be erased
end
if(flag_modify ==1 && next_modify != next_out)
begin
pred_tab[next_modify] <= record_modify;
end
end
end
*/
// Do the predictions
always @(/*EI_adr, DI_bra, DI_adr, EX_adr, */EX_adresse, EX_bra_confirm)
begin:PREDICT_SECTION1
//integer i;
//integer index_EI, index_DI , index_EX;
// Default signal affectations
//index_EI = nb_record;
//index_DI = nb_record;
//index_EX = nb_record;
PR_bra_cmd = 0;
PR_bra_bad = 0;
PR_bra_adr = 0;
PR_clear_DI = 0;
PR_clear_EI = 0;
/*flag_add = 0;
//record_add = 66'b0;
//flag_modify = 0;
//record_modify = 0;
//next_modify = 66'b0;
// Check a match in the table
for (i=0;i<nb_record;i=i+1)
if (pred_tab[i]`VALID == 1)
begin
if (EI_adr == pred_tab[i]`CODE_ADDR) index_EI = i;
if (DI_adr == pred_tab[i]`CODE_ADDR) index_DI = i;
if (EX_adr == pred_tab[i]`CODE_ADDR) index_EX = i;
end
// Branch prediciton
if (index_EI != nb_record)
begin
if(pred_tab[index_EI]`LAST_BRA)
begin
`ifdef DEBUG
$display($time, , ,"\n\npredict a bra,addr=%h,bra_addr=%h,bra=%b,index=%0d .\n",
EI_adr,pred_tab[index_EI]`BRA_ADDR,pred_tab[index_EI]`LAST_BRA,index_EI);
`endif
PR_bra_cmd = 1;
PR_bra_adr = pred_tab[index_EI]`BRA_ADDR;
end
end
*/
// Check if the last prediction is ok
//if (EX_cleared==0 && /*index_EX!=nb_record && pred_tab[index_EX]`LAST_BRA!=*/(EX_bra_confirm||
//EX_jr == 1))
//begin
if( EX_bra_confirm)
begin
//set the modify flag and modify record
/*next_modify = index_EX;
//record_modify = pred_tab[index_EX];
flag_modify = 1;
record_modify`VALID = 1;
record_modify`LAST_BRA = EX_bra_confirm;
record_modify`CODE_ADDR = EX_adr;
record_modify`BRA_ADDR = EX_adresse;
end*/
// Clear the pipeline and branch to the new instruction
PR_bra_bad = 1;
PR_bra_adr = EX_adresse;
PR_clear_EI = 1;
PR_clear_DI = 1;
//if (EX_bra_confirm == 1)
//begin
//record_modify`BRA_ADDR = EX_adresse;
//PR_bra_adr = EX_adresse;
//end
//else begin
//record_modify`BRA_ADDR = 32'bx;
//PR_bra_adr = EX_adr+4+4;
//end
/*`ifdef DEBUG
$display($time, , ,"\n\npredict bad,addr=%h,bra_addr=%h,bra=%b,index=%0d .",
EX_adr,pred_tab[index_EX]`BRA_ADDR,pred_tab[index_EX]`LAST_BRA,index_EX);
$display("correct,bra_addr=%h,bra=%b .\n", PR_bra_adr,record_modify`LAST_BRA);
`endif*/
end
//check if there is a jmp instruction
if(DI_jmp)
begin
PR_bra_bad = 1;
PR_bra_adr = DI_jmp_target;
PR_clear_EI = 1;
end
/*else if (DI_bra == 1 && index_DI == nb_record )
begin // check if it's need to add a record in the table
`ifdef DEBUG
$display($time, , ,"\n\ndetect a bra,addr=%h,next_out=%0d .\n", DI_adr,next_out);
`endif
flag_add = 1;
record_add`VALID = 1; // The record is affected
record_add`LAST_BRA = 0; // Can't predict the branch the first time
record_add`CODE_ADDR = DI_adr; // Save the branch address
record_add`BRA_ADDR = 32'bx; // Branch result
end*/
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD2_PP_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD2_PP_SYMBOL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd2 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MX = (int)2e5 + 10; const int mod = (int)1e9 + 7; bool check(string& t) { bool ok = true; int n = t.size(); for (int j = 0; j < n / 2; ++j) { ok &= t[j] == t[n - j - 1]; } return ok; } int main(int argc, char* argv[]) { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); string s; cin >> s; int n = s.size(); int it = 0; while (it < n && s[it] == s[0]) it++; if (it == n) { cout << Impossible << endl; return 0; } for (int i = 1; i < n; ++i) { string s1 = s.substr(0, i); string s2 = s.substr(i); string t = s2 + s1; if (t != s && check(t)) { cout << 1 << endl; return 0; } } if (n % 2 == 0) { string sx = s.substr(0, n / 2); if (!check(sx)) { cout << 1 << endl; return 0; } } for (int i = 0; i < n / 2; ++i) { string sx = s.substr(0, i + 1); if (!check(sx)) { cout << 2 << endl; return 0; } } cout << Impossible << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off GENCLK
reg [7:0] cyc; initial cyc=0;
reg [7:0] padd;
reg dsp_ph1, dsp_ph2, dsp_reset;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] out; // From dspchip of t_dspchip.v
// End of automatics
t_dspchip dspchip (/*AUTOINST*/
// Outputs
.out (out[7:0]),
// Inputs
.dsp_ph1 (dsp_ph1),
.dsp_ph2 (dsp_ph2),
.dsp_reset (dsp_reset),
.padd (padd[7:0]));
always @ (posedge clk) begin
$write("cyc %d\n",cyc);
if (cyc == 8'd0) begin
cyc <= 8'd1;
dsp_reset <= 0; // Need a posedge
padd <= 0;
end
else if (cyc == 8'd20) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
cyc <= cyc + 8'd1;
dsp_ph1 <= ((cyc&8'd3) == 8'd0);
dsp_ph2 <= ((cyc&8'd3) == 8'd2);
dsp_reset <= (cyc == 8'd1);
padd <= cyc;
//$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out);
case (cyc)
default: $stop;
8'd01: ;
8'd02: ;
8'd03: ;
8'd04: ;
8'd05: ;
8'd06: ;
8'd07: ;
8'd08: ;
8'd09: if (out!==8'h04) $stop;
8'd10: if (out!==8'h04) $stop;
8'd11: if (out!==8'h08) $stop;
8'd12: if (out!==8'h08) $stop;
8'd13: if (out!==8'h00) $stop;
8'd14: if (out!==8'h00) $stop;
8'd15: if (out!==8'h00) $stop;
8'd16: if (out!==8'h00) $stop;
8'd17: if (out!==8'h0c) $stop;
8'd18: if (out!==8'h0c) $stop;
8'd19: if (out!==8'h10) $stop;
endcase
end
end
endmodule
module t_dspchip (/*AUTOARG*/
// Outputs
out,
// Inputs
dsp_ph1, dsp_ph2, dsp_reset, padd
);
input dsp_ph1, dsp_ph2, dsp_reset;
input [7:0] padd;
output [7:0] out;
wire dsp_ph1, dsp_ph2;
wire [7:0] out;
wire pla_ph1, pla_ph2;
wire out1_r;
wire [7:0] out2_r, padd;
wire clk_en;
t_dspcore t_dspcore (/*AUTOINST*/
// Outputs
.out1_r (out1_r),
.pla_ph1 (pla_ph1),
.pla_ph2 (pla_ph2),
// Inputs
.dsp_ph1 (dsp_ph1),
.dsp_ph2 (dsp_ph2),
.dsp_reset (dsp_reset),
.clk_en (clk_en));
t_dsppla t_dsppla (/*AUTOINST*/
// Outputs
.out2_r (out2_r[7:0]),
// Inputs
.pla_ph1 (pla_ph1),
.pla_ph2 (pla_ph2),
.dsp_reset (dsp_reset),
.padd (padd[7:0]));
assign out = out1_r ? 8'h00 : out2_r;
assign clk_en = 1'b1;
endmodule
module t_dspcore (/*AUTOARG*/
// Outputs
out1_r, pla_ph1, pla_ph2,
// Inputs
dsp_ph1, dsp_ph2, dsp_reset, clk_en
);
input dsp_ph1, dsp_ph2, dsp_reset;
input clk_en;
output out1_r, pla_ph1, pla_ph2;
wire dsp_ph1, dsp_ph2, dsp_reset;
wire pla_ph1, pla_ph2;
reg out1_r;
always @(posedge dsp_ph1 or posedge dsp_reset) begin
if (dsp_reset)
out1_r <= 1'h0;
else
out1_r <= ~out1_r;
end
assign pla_ph1 = dsp_ph1;
assign pla_ph2 = dsp_ph2 & clk_en;
endmodule
module t_dsppla (/*AUTOARG*/
// Outputs
out2_r,
// Inputs
pla_ph1, pla_ph2, dsp_reset, padd
);
input pla_ph1, pla_ph2, dsp_reset;
input [7:0] padd;
output [7:0] out2_r;
wire pla_ph1, pla_ph2, dsp_reset;
wire [7:0] padd;
reg [7:0] out2_r;
reg [7:0] latched_r;
always @(posedge pla_ph1 or posedge dsp_reset) begin
if (dsp_reset)
latched_r <= 8'h00;
else
latched_r <= padd;
end
always @(posedge pla_ph2 or posedge dsp_reset) begin
if (dsp_reset)
out2_r <= 8'h00;
else
out2_r <= latched_r;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, A[100001], BIT[100001], res[100001]; vector<int> v; map<int, int> m; int main() { scanf( %d , &N); for (int i = 1; i <= N; ++i) scanf( %d , &A[i]), v.push_back(A[i]); sort(v.begin(), v.end()); v.resize(unique(v.begin(), v.end()) - v.begin()); int n = v.size(); for (int i = 0; i < n; ++i) m[v[i]] = i + 1; for (int i = N; i >= 1; --i) { int mx = 0; for (int x = m[A[i]] - 1; x > 0; x -= x & -x) if (mx < BIT[x]) mx = BIT[x]; res[i] = ((mx - i - 1 >= 0) ? (mx - i - 1) : -1); for (int x = m[A[i]]; x <= n; x += x & -x) if (!BIT[x]) BIT[x] = i; } for (int i = 1; i <= N; ++i) printf( %d , res[i]); return 0; }
|
#include <bits/stdc++.h> inline char gc() { static const int L = 23333; static char sxd[L], *sss = sxd, *ttt = sxd; if (sss == ttt) { ttt = (sss = sxd) + fread(sxd, 1, L, stdin); if (sss == ttt) { return EOF; } } return *sss++; } template <class T> inline bool read(T& x) { x = 0; char c = gc(); bool flg = false; for (; !isdigit(c); c = gc()) { if (c == - ) { flg = true; } else if (c == EOF) { return false; } } for (; isdigit(c); c = gc()) { x = (x * 10) + (c ^ 48); } if (flg) { x = -x; } return true; } template <class T> inline void write(T x) { if (x < 0) { x = -x; putchar( - ); } if (x > 9) { write(x / 10); x %= 10; } putchar(x | 48); } template <class T> inline void writeln(T x) { write(x); puts( ); } template <class T> inline void writesp(T x) { write(x); putchar( ); } using namespace std; const int maxn = 100005; int gcd(int a, int b) { while (b) { int t = a % b; a = b; b = t; } return a; } int n; struct Edge { int to, nxt; } e[maxn << 1]; int first[maxn]; int du[maxn]; int dubk[maxn]; int cnt; void add_edge(int u, int v) { du[u]++, du[v]++; e[++cnt].nxt = first[u]; first[u] = cnt; e[cnt].to = v; e[++cnt].nxt = first[v]; first[v] = cnt; e[cnt].to = u; } int final_ans[maxn]; void init() { cnt = 0; for (int i = 1; i <= n; ++i) { first[i] = du[i] = final_ans[i] = 0; } } bool np[maxn]; int factor[maxn]; int prime[maxn]; void oula(const int n = 100000) { np[1] = true; int cnt = 0; for (int i = 2; i <= n; ++i) { if (!np[i]) { prime[++cnt] = i; factor[i] = i; } for (int j = 1; j <= cnt && (long long)i * prime[j] <= n; ++j) { np[i * prime[j]] = true; factor[i * prime[j]] = prime[j]; if (!(i % prime[j])) { break; } } } } bool vis[maxn]; int nn[maxn]; int bfs(int xx) { for (int i = 1; i <= n; ++i) { vis[i] = false; nn[i] = du[i] = dubk[i]; } queue<int> q; while (!q.empty()) { q.pop(); } for (int i = 1; i <= n; ++i) { if (du[i] <= 1) { q.push(i); vis[i] = true; } } int ans = n - 1; while (!q.empty()) { int now = q.front(); q.pop(); bool flg = false; if (du[now]) { int tmpans = gcd(ans, nn[now]); if (tmpans % xx) { nn[now]--; ans = gcd(ans, nn[now]); } else { ans = tmpans; flg = true; } } else { ans = gcd(ans, nn[now]); } if (ans % xx) { return 1; } for (int i = first[now]; i; i = e[i].nxt) { int to = e[i].to; if (!vis[to]) { du[to]--; if (flg) { nn[to]--; } if (du[to] <= 1) { q.push(to); vis[to] = true; } } } } return ans; } const int mod = 998244353; int ksm(int a, int b) { int ans = 1; for (; b; b >>= 1, a = (long long)a * a % mod) { if (b & 1) { ans = (long long)ans * a % mod; } } return ans; } void solve() { read(n); init(); for (int i = 1; i < n; ++i) { int u, v; read(u), read(v); add_edge(u, v); } for (int i = 1; i <= n; ++i) { dubk[i] = du[i]; } int tt = n - 1; int tmpans = 0; while (tt > 1) { int pme = factor[tt]; while (!(tt % pme)) { tt /= pme; } int nowans = bfs(pme); if (nowans > 1 && !final_ans[nowans]) { final_ans[nowans] = 1; tmpans++; } } final_ans[1] = ksm(2, n - 1) - tmpans; if (final_ans[1] < 0) { final_ans[1] += mod; } for (int i = 1; i <= n; ++i) { writesp(final_ans[i]); } puts( ); } int main() { oula(); int T; read(T); while (T--) { solve(); } return 0; }
|
#include <bits/stdc++.h> const int MAXN = 1000 + 5; char str[MAXN]; int n; inline std::vector<int> query(std::vector<int> d) { std::vector<int> ans; printf( ? ); for (auto x : d) printf( %d , x); puts( ); std::fflush(stdout); scanf( %s , str + 1); for (int i = 1; i <= n; ++i) ans.push_back(str[i] - 0 ); return ans; } std::vector<int> G[MAXN]; std::vector<int> node[MAXN * 50]; int tot = 1; struct Node { int l, r, id; Node(int l = 0, int r = 0, int id = 0) : l(l), r(r), id(id) {} inline bool operator<(const Node &t) const { return l < t.l; } }; int fa[MAXN]; inline void work(std::vector<int> id, int bit) { std::vector<int> d; d.resize(n); for (auto x : id) { for (auto y : G[x - 1]) if ((y >> bit) & 1) d[y - 1] = 1; } std::vector<int> a; a = query(d); for (auto x : id) { for (auto y : G[x]) fa[y] |= (a[y - 1] << bit); } } bool tag[MAXN]; int main() { scanf( %d , &n); std::vector<Node> now; G[0].push_back(1); now.push_back(Node(0, n, 1)); for (int i = 2; i <= n; ++i) node[tot].push_back(i); while (!now.empty()) { std::vector<Node> v1, v2; std::sort(now.begin(), now.end()); for (int i = 0; i < now.size(); i += 2) { v1.push_back(now[i]); if (i + 1 < now.size()) v2.push_back(now[i + 1]); } std::vector<int> d, a1, a2; d.resize(n); now.clear(); memset(tag, 0, sizeof(tag)); for (auto x : v1) { int mid = (x.l + x.r) >> 1; assert(x.l < x.r - 1); for (auto y : G[x.l]) d[y - 1] = mid - x.l - 1, tag[y - 1] = 1; } a1 = query(d); for (int i = 0; i <= n - 1; ++i) if (tag[i]) d[i]++; a2 = query(d); for (auto x : v1) { int mid = (x.l + x.r) >> 1; Node ls = Node(x.l, mid, ++tot), rs = Node(mid, x.r, ++tot); for (auto y : node[x.id]) { if (!a1[y - 1] && a2[y - 1]) G[mid].push_back(y); else if (a1[y - 1]) node[ls.id].push_back(y); else node[rs.id].push_back(y); } if (ls.l + 1 < ls.r) now.push_back(ls); if (rs.l + 1 < rs.r) now.push_back(rs); } d.clear(); d.resize(n); memset(tag, 0, sizeof(tag)); for (auto x : v2) { int mid = (x.l + x.r) >> 1; assert(x.l < x.r - 1); for (auto y : G[x.l]) d[y - 1] = mid - x.l - 1, tag[y - 1] = 1; } a1 = query(d); for (int i = 0; i <= n - 1; ++i) if (tag[i]) d[i]++; a2 = query(d); for (auto x : v2) { int mid = (x.l + x.r) >> 1; Node ls = Node(x.l, mid, ++tot), rs = Node(mid, x.r, ++tot); for (auto y : node[x.id]) { if (!a1[y - 1] && a2[y - 1]) G[mid].push_back(y); else if (a1[y - 1]) node[ls.id].push_back(y); else node[rs.id].push_back(y); } if (ls.l + 1 < ls.r) now.push_back(ls); if (rs.l + 1 < rs.r) now.push_back(rs); } } for (int i = 0; i <= 9; ++i) { std::vector<int> v1, v2, v3; for (int i = 1; i < n; i += 3) { v1.push_back(i); if (i + 1 < n) v2.push_back(i + 1); if (i + 2 < n) v3.push_back(i + 2); } work(v1, i); work(v2, i); work(v3, i); } puts( ! ); for (int i = 2; i <= n; ++i) printf( %d %d n , fa[i], i); std::fflush(stdout); return 0; }
|
// -----------------------------------------------------------------------
//
// Copyright 2004 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
/*
* Simulate a specific subset of the Altera Shift register
* (lpm_clshift).
*
* Not very ambitious, just the bare minimum.
*/
module arithshiftbidir(distance,
data,
direction,
result);
parameter lpm_type = "LPM_CLSHIFT";
parameter lpm_shifttype = "ARITHMETIC";
parameter lpm_width = 32;
parameter lpm_widthdist = 5;
input wire [lpm_widthdist-1:0] distance;
input wire [lpm_width-1 :0] data;
input wire direction;
output wire [lpm_width-1 :0] result;
assign result = direction ? data >>> distance : data << distance;
endmodule
module test_arithshiftbidir();
reg [31:0] data;
reg [ 4:0] dist;
reg dir;
wire [31:0] resulta, resultl;
arithshiftbidir a(dist, data, dir, resulta);
defparam a.lpm_shifttype = "ARITHMETIC";
initial begin
#0 data = 48; dir = 0; dist = 0;
$monitor("dir %d dist %2d A %8x", dir, dist, resulta);
repeat (2) begin
repeat (32)
#1 dist = dist + 1;
dir = ~dir;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUSDRIVER_FUNCTIONAL_V
/**
* busdriver: Bus driver (pmoshvt devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdriver (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21O_1_V
`define SKY130_FD_SC_HS__A21O_1_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21o_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21o_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21O_1_V
|
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file Ins_Mem.v when simulating
// the core, Ins_Mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module Ins_Mem(
a,
spo);
input [9 : 0] a;
output [31 : 0] spo;
// synthesis translate_off
DIST_MEM_GEN_V5_1 #(
.C_ADDR_WIDTH(10),
.C_DEFAULT_DATA("0"),
.C_DEPTH(1024),
.C_FAMILY("spartan3"),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("Ins_Mem.mif"),
.C_MEM_TYPE(0),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(32))
inst (
.A(a),
.SPO(spo),
.D(),
.DPRA(),
.SPRA(),
.CLK(),
.WE(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.DPO(),
.QSPO(),
.QDPO());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of Ins_Mem is "black_box"
endmodule
|
#include <bits/stdc++.h> using namespace std; int cnt[10]; int main() { int n; while (scanf( %d , &n) != EOF) { int sum = 0; memset(cnt, 0, sizeof(cnt)); for (int i = 0; i < n; i++) { int j; scanf( %d , &j); cnt[j]++; sum += j; } int ans = -1; for (int i = 0; i <= n; i++) if (4 * i <= sum && (sum - 4 * i) % 3 == 0 && (sum - 4 * i) / 3 <= n - i) { int j = (sum - 4 * i) / 3; int cost = min(max(cnt[4] - i, 0), j); int p = cnt[1] + cnt[2] + cnt[3] + cnt[4]; for (int k = 1; k <= 4 && p > i + j; k++) { cost += min(p - i - j, cnt[k]) * k; p -= min(p - i - j, cnt[k]); } if (cost < ans || ans == -1) ans = cost; } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<string> ans; string f = 1 ; bool sort2(string &a, string &b) { if (a.size() == b.size()) { return a < b; } return a.size() < b.size(); } void calc(string s) { if (s.size() >= 11) { return; } ans.push_back(s); s += 1 ; calc(s); s.pop_back(); s += 0 ; calc(s); s.pop_back(); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; string l = to_string(n); calc(f); int ans2 = 0; sort(ans.begin(), ans.end(), sort2); for (int i = 0; i < ans.size(); i++) { if (ans[i].size() > l.size()) { break; } else if (ans[i].size() == l.size()) { if (l >= ans[i]) { ans2++; } else { break; } } else { ans2++; } } cout << ans2 << n ; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:39:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_overlay_0_0 -prefix
// system_vga_overlay_0_0_ system_vga_overlay_0_0_stub.v
// Design : system_vga_overlay_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_overlay,Vivado 2016.4" *)
module system_vga_overlay_0_0(clk, rgb_0, rgb_1, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb_0[23:0],rgb_1[23:0],rgb[23:0]" */;
input clk;
input [23:0]rgb_0;
input [23:0]rgb_1;
output [23:0]rgb;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_4_V
`define SKY130_FD_SC_HS__A31O_4_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a31o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a31o_4 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_4_V
|
// hps_design_SMP_HPS.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_SMP_HPS #(
parameter F2S_Width = 0,
parameter S2F_Width = 0
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
hps_design_SMP_HPS_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY) // .rready
);
hps_design_SMP_HPS_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; vector<int> g; while (cin >> n) { int xi, xf; xi = -1; xf = -1; bool init = false; g = vector<int>(n); for (int i = 0; i < n; i++) { cin >> g[i]; if (init == false && g[i] == 1) { xi = i; xf = i; init = true; } else if (init == true && g[i] == 1) xf = max(xf, i); } if (xi == -1 || xf == -1) cout << 0 << endl; else { int ceros = 0; for (int i = xi; i < xf;) { if (g[i] == 0 && g[i + 1] == 0) { i += 2; ceros += 2; int b = i; for (int q = b; q <= xf; q++) if (g[q] == 0) { ceros++; b = max(b, q); } else break; i = b + 1; } else i++; } cout << (xf - xi + 1) - ceros << endl; } } return 0; }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module combines two video streams by overlaying one onto the *
* other using alpha blending. The foreground image must include alpha *
* bits to be used in the blending formula: Cn = (1 - a)Cb + (a)Cf *
* Cn - new color *
* a - alpha *
* Cb - background colour *
* Cf - foreground colour *
* *
******************************************************************************/
module altera_up_video_alpha_blender_normal (
// Inputs
background_data,
foreground_data,
// Bidirectionals
// Outputs
new_red,
new_green,
new_blue
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [29: 0] background_data;
input [39: 0] foreground_data;
// Bidirectionals
// Outputs
output [ 9: 0] new_red;
output [ 9: 0] new_green;
output [ 9: 0] new_blue;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] one_minus_a;
wire [17: 0] r_x_alpha;
wire [17: 0] g_x_alpha;
wire [17: 0] b_x_alpha;
wire [17: 0] r_x_one_minus_alpha;
wire [17: 0] g_x_one_minus_alpha;
wire [17: 0] b_x_one_minus_alpha;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign new_red = {1'b0, r_x_alpha[17:9]} +
{1'b0, r_x_one_minus_alpha[17:9]};
assign new_green = {1'b0, g_x_alpha[17:9]} +
{1'b0, g_x_one_minus_alpha[17:9]};
assign new_blue = {1'b0, b_x_alpha[17:9]} +
{1'b0, b_x_one_minus_alpha[17:9]};
// Internal Assignments
assign one_minus_a = 10'h3FF - foreground_data[39:30];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
lpm_mult r_times_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (foreground_data[29:21]),
.datab (foreground_data[39:31]),
// Outputs
.result (r_x_alpha)
);
defparam
r_times_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
r_times_alpha.lpm_representation = "UNSIGNED",
r_times_alpha.lpm_type = "LPM_MULT",
r_times_alpha.lpm_widtha = 9,
r_times_alpha.lpm_widthb = 9,
r_times_alpha.lpm_widthp = 18;
lpm_mult g_times_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (foreground_data[19:11]),
.datab (foreground_data[39:31]),
// Outputs
.result (g_x_alpha)
);
defparam
g_times_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
g_times_alpha.lpm_representation = "UNSIGNED",
g_times_alpha.lpm_type = "LPM_MULT",
g_times_alpha.lpm_widtha = 9,
g_times_alpha.lpm_widthb = 9,
g_times_alpha.lpm_widthp = 18;
lpm_mult b_times_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (foreground_data[ 9: 1]),
.datab (foreground_data[39:31]),
// Outputs
.result (b_x_alpha)
);
defparam
b_times_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
b_times_alpha.lpm_representation = "UNSIGNED",
b_times_alpha.lpm_type = "LPM_MULT",
b_times_alpha.lpm_widtha = 9,
b_times_alpha.lpm_widthb = 9,
b_times_alpha.lpm_widthp = 18;
lpm_mult r_times_one_minus_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (background_data[29:21]),
.datab (one_minus_a[ 9: 1]),
// Outputs
.result (r_x_one_minus_alpha)
);
defparam
r_times_one_minus_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
r_times_one_minus_alpha.lpm_representation = "UNSIGNED",
r_times_one_minus_alpha.lpm_type = "LPM_MULT",
r_times_one_minus_alpha.lpm_widtha = 9,
r_times_one_minus_alpha.lpm_widthb = 9,
r_times_one_minus_alpha.lpm_widthp = 18;
lpm_mult g_times_one_minus_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (background_data[19:11]),
.datab (one_minus_a[ 9: 1]),
// Outputs
.result (g_x_one_minus_alpha)
);
defparam
g_times_one_minus_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
g_times_one_minus_alpha.lpm_representation = "UNSIGNED",
g_times_one_minus_alpha.lpm_type = "LPM_MULT",
g_times_one_minus_alpha.lpm_widtha = 9,
g_times_one_minus_alpha.lpm_widthb = 9,
g_times_one_minus_alpha.lpm_widthp = 18;
lpm_mult b_times_one_minus_alpha (
// Inputs
.clock (1'b0),
.clken (1'b1),
.aclr (1'b0),
.sum (1'b0),
.dataa (background_data[ 9: 1]),
.datab (one_minus_a[ 9: 1]),
// Outputs
.result (b_x_one_minus_alpha)
);
defparam
b_times_one_minus_alpha.lpm_hint = "MAXIMIZE_SPEED=5",
b_times_one_minus_alpha.lpm_representation = "UNSIGNED",
b_times_one_minus_alpha.lpm_type = "LPM_MULT",
b_times_one_minus_alpha.lpm_widtha = 9,
b_times_one_minus_alpha.lpm_widthb = 9,
b_times_one_minus_alpha.lpm_widthp = 18;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 205; const long long modulo = 1000000007; struct point { long long x, y; }; point operator-(point A, point B) { point C; C.x = A.x - B.x; C.y = A.y - B.y; return C; } bool operator==(point A, point B) { return (A.x == B.x && A.y == B.y); } long long cross(point A, point B) { return (A.x * B.y - A.y * B.x); } long long dot(point A, point B) { return (A.x * B.x + A.y * B.y); } struct Line { long long A, B, C; Line(point P, point R) { A = R.y - P.y; B = P.x - R.x; C = (P.y * R.x) - (P.x * R.y); } }; long long sgn(long long x) { if (x > 0) return 1; if (x < 0) return -1; if (x == 0) return 0; } long long f(Line L, point P) { return sgn(L.A * P.x + L.B * P.y + L.C); } bool OnSegment(point A, point B, point X) { if (f(Line(A, B), X) != 0) return false; if (dot(A - X, B - X) < 0) return true; else return false; } bool intersect(point A, point B, point C, point D) { if (A == C || A == D || B == C || B == D) return false; if (f(Line(A, B), C) * f(Line(A, B), D) >= 0) return false; if (f(Line(C, D), A) * f(Line(C, D), B) >= 0) return false; return true; } point a[MAXN]; long long dp[MAXN][MAXN]; int main() { int N; cin >> N; for (int i = 1; i <= N; i++) { cin >> a[i].x >> a[i].y; } a[N + 1] = a[1]; long long Area = 0; for (int i = 1; i <= N; i++) { Area += cross(a[i], a[i + 1]); } Area = abs(Area); for (int d = 1; d < N - 1; d++) { for (int l = 1; l + d <= N; l++) { int r = l + d; if (d == 1) { dp[l][r] = 1; continue; } else dp[l][r] = 0; bool bad = false; for (int i = 1; i <= N; i++) { if (i != l && i != r && OnSegment(a[l], a[r], a[i])) bad = true; } if (bad) continue; for (int i = 1; i <= N; i++) { int next = i + 1; if (next == N + 1) next = 1; if (intersect(a[l], a[r], a[i], a[next])) bad = true; } if (bad) continue; long long AreaX = 0, AreaY = 0; for (int i = l; i <= r; i++) { int next = i + 1; if (next == r + 1) next = l; AreaX += cross(a[i], a[next]); } int j = 1; while (j <= N) { int next; if (j == l) next = r; else next = j + 1; if (next == N + 1) next = 1; AreaY += cross(a[j], a[next]); j = next; if (j == 1) j = N + 1; } if (Area != abs(AreaX) + abs(AreaY)) continue; for (int i = l + 1; i < r; i++) { dp[l][r] += (dp[l][i] * dp[i][r]) % modulo; dp[l][r] = dp[l][r] % modulo; } } } dp[1][N] = 0; for (int i = 2; i < N; i++) { dp[1][N] += (dp[1][i] * dp[i][N]) % modulo; dp[1][N] = dp[1][N] % modulo; } cout << dp[1][N] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void task(); int main() { srand(time(0)); task(); return 0; } const int INF = 0x3f3f3f3f; const int N = 1e5 + 10; const int M = 1e5 + 10; int n, x; int l[N]; int r[N]; long long int dp[2 * N + 10]; vector<int> v; void task() { scanf( %d %d , &n, &x); v.push_back(x); for (int i = 0; i < n; ++i) { scanf( %d %d , &l[i], &r[i]); v.push_back(l[i]); v.push_back(r[i]); } sort((v.begin()), (v.end())); int m = ((int)((v).size())); memset(dp, 0x3f, sizeof(dp)); for (int i = 0; i < m; ++i) if (v[i] == x) dp[i] = 0; for (int i = 0; i < n; ++i) { for (int j = 1; j < m; ++j) dp[j] = min(dp[j], dp[j - 1] + v[j] - v[j - 1]); for (int j = m - 2; j >= 0; --j) dp[j] = min(dp[j], dp[j + 1] + v[j + 1] - v[j]); for (int j = 0; j < m; ++j) if (v[j] < l[i]) dp[j] += l[i] - v[j]; else if (v[j] > r[i]) dp[j] += v[j] - r[i]; } cout << *min_element(dp, dp + m); }
|
#include <bits/stdc++.h> using namespace std; int n, m; int c[1010100], cc[1010100]; int lowbit(int x) { return x & (-x); } void upd(int v, int idx, int a[]) { while (idx <= n) { a[idx] += v; idx += lowbit(idx); } } int qu(int idx, int a[]) { int sum = 0; if (idx == 0) return 0; while (idx > 0) { sum += a[idx]; idx -= lowbit(idx); } return sum; } struct Node { int v, id; } arr[1010100]; int cmp(Node a, Node b) { return a.v < b.v; } int find() { int ll = 1, rr = n + 1, mid, ans = n; while (ll < rr) { mid = (ll + rr) / 2; if (qu(mid, cc) < mid) ans = rr = mid; else ll = mid + 1; } return ans; } int vis[1010100]; int main() { int i, j; while (scanf( %d %d , &n, &m) != EOF) { memset(vis, 0, sizeof(vis)); for (i = 1; i <= n; i++) scanf( %d , &arr[i].v), arr[i].id = i; for (i = 1; i <= m; i++) scanf( %d , &j), vis[j] = 1; sort(arr + 1, arr + 1 + n, cmp); memset(c, 0, sizeof(c)); memset(cc, 0, sizeof(cc)); long long sum = 0; for (i = 1; i <= n; i++) { if (vis[arr[i].v]) { upd(1, arr[i].id, c); } else { int ll = 0, rr = arr[i].id, mid; int v = qu(rr, c), x = rr; while (ll < rr) { mid = (ll + rr) / 2; if (qu(mid, c) == v) x = rr = mid; else ll = mid + 1; } if (qu(n, c) == 0) x = 0; ll = arr[i].id, rr = n + 1; v = qu(ll, c); int y = ll; while (ll < rr) { mid = (ll + rr) / 2; if (qu(mid, c) == v) y = mid, ll = mid + 1; else rr = mid; } y = y - qu(y, cc); x = max(find() - 1, x); x = x - qu(x, cc); sum = sum + (y - x); upd(1, arr[i].id, cc); } } printf( %I64d n , sum); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_1_V
`define SKY130_FD_SC_HVL__O21A_1_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o21a_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o21a_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_1_V
|
module ram_1p (
clk_i,
rst_ni,
req_i,
we_i,
be_i,
addr_i,
wdata_i,
rvalid_o,
rdata_o
);
parameter signed [31:0] Depth = 128;
input clk_i;
input rst_ni;
input req_i;
input we_i;
input [3:0] be_i;
input [31:0] addr_i;
input [31:0] wdata_i;
output reg rvalid_o;
output reg [31:0] rdata_o;
parameter signed [31:0] Aw = $clog2(Depth);
reg [31:0] mem [0:(Depth - 1)];
wire [(Aw - 1):0] addr_idx;
assign addr_idx = addr_i[((Aw - 1) + 2):2];
wire [(31 - Aw):0] unused_addr_parts;
assign unused_addr_parts = {addr_i[31:(Aw + 2)], addr_i[1:0]};
always @(posedge clk_i)
if (req_i) begin
if (we_i) begin : sv2v_autoblock_1
reg signed [31:0] i;
for (i = 0; (i < 4); i = (i + 1))
if ((be_i[i] == 1'b1))
mem[addr_idx][(i * 8)+:8] <= wdata_i[(i * 8)+:8];
end
rdata_o <= mem[addr_idx];
end
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
rvalid_o <= 1'sb0;
else
rvalid_o <= req_i;
localparam MEM_FILE = "led.vmem";
initial begin
$display("Initializing SRAM from %s", MEM_FILE);
$readmemh("led.vmem", mem);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int powr(long long a, long long b) { if (b == 0) { return 1; } if (b % 2 == 0) { return powr(((a % 1000000007) * (a % 1000000007)) % 1000000007, b / 2); } else { if (b == 1) { return a; } else { return (a * powr(((a % 1000000007) * (a % 1000000007) % 1000000007), (b - 1) / 2)) % 1000000007; } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long s, b; cin >> s >> b; long long a[s]; long long u[b]; for (long long i = 0; i < s; i++) { cin >> a[i]; } vector<pair<long long, long long> > p; long long c, d; for (long long i = 0; i < b; i++) { cin >> c >> d; p.push_back({c, d}); u[i] = c; } sort(p.begin(), p.end()); sort(u, u + b); long long y = 0; long long sum[b]; for (long long i = 0; i < b; i++) { y += p[i].second; sum[i] = y; } for (long long i = 0; i < s; i++) { pair<long long, long long> cur = {a[i], INT_MAX}; auto idx = lower_bound(p.begin(), p.end(), cur); if (idx == p.begin()) { cout << 0 << ; continue; } idx--; long long j = idx - p.begin(); cout << sum[j] << ; } cerr << Time : << 1000 * ((double)clock()) / (double)CLOCKS_PER_SEC << ms n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBN_1_V
`define SKY130_FD_SC_HD__DLXBN_1_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlxbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBN_1_V
|
//======================================================================
//
// sha256_k_constants.v
// --------------------
// The table K with constants in the SHA-256 hash function.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module sha256_k_constants(
input wire [5 : 0] round,
output wire [31 : 0] K
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_K;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign K = tmp_K;
//----------------------------------------------------------------
// round_mux
//----------------------------------------------------------------
always @*
begin : round_mux
case(round)
00: tmp_K = 32'h428a2f98;
01: tmp_K = 32'h71374491;
02: tmp_K = 32'hb5c0fbcf;
03: tmp_K = 32'he9b5dba5;
04: tmp_K = 32'h3956c25b;
05: tmp_K = 32'h59f111f1;
06: tmp_K = 32'h923f82a4;
07: tmp_K = 32'hab1c5ed5;
08: tmp_K = 32'hd807aa98;
09: tmp_K = 32'h12835b01;
10: tmp_K = 32'h243185be;
11: tmp_K = 32'h550c7dc3;
12: tmp_K = 32'h72be5d74;
13: tmp_K = 32'h80deb1fe;
14: tmp_K = 32'h9bdc06a7;
15: tmp_K = 32'hc19bf174;
16: tmp_K = 32'he49b69c1;
17: tmp_K = 32'hefbe4786;
18: tmp_K = 32'h0fc19dc6;
19: tmp_K = 32'h240ca1cc;
20: tmp_K = 32'h2de92c6f;
21: tmp_K = 32'h4a7484aa;
22: tmp_K = 32'h5cb0a9dc;
23: tmp_K = 32'h76f988da;
24: tmp_K = 32'h983e5152;
25: tmp_K = 32'ha831c66d;
26: tmp_K = 32'hb00327c8;
27: tmp_K = 32'hbf597fc7;
28: tmp_K = 32'hc6e00bf3;
29: tmp_K = 32'hd5a79147;
30: tmp_K = 32'h06ca6351;
31: tmp_K = 32'h14292967;
32: tmp_K = 32'h27b70a85;
33: tmp_K = 32'h2e1b2138;
34: tmp_K = 32'h4d2c6dfc;
35: tmp_K = 32'h53380d13;
36: tmp_K = 32'h650a7354;
37: tmp_K = 32'h766a0abb;
38: tmp_K = 32'h81c2c92e;
39: tmp_K = 32'h92722c85;
40: tmp_K = 32'ha2bfe8a1;
41: tmp_K = 32'ha81a664b;
42: tmp_K = 32'hc24b8b70;
43: tmp_K = 32'hc76c51a3;
44: tmp_K = 32'hd192e819;
45: tmp_K = 32'hd6990624;
46: tmp_K = 32'hf40e3585;
47: tmp_K = 32'h106aa070;
48: tmp_K = 32'h19a4c116;
49: tmp_K = 32'h1e376c08;
50: tmp_K = 32'h2748774c;
51: tmp_K = 32'h34b0bcb5;
52: tmp_K = 32'h391c0cb3;
53: tmp_K = 32'h4ed8aa4a;
54: tmp_K = 32'h5b9cca4f;
55: tmp_K = 32'h682e6ff3;
56: tmp_K = 32'h748f82ee;
57: tmp_K = 32'h78a5636f;
58: tmp_K = 32'h84c87814;
59: tmp_K = 32'h8cc70208;
60: tmp_K = 32'h90befffa;
61: tmp_K = 32'ha4506ceb;
62: tmp_K = 32'hbef9a3f7;
63: tmp_K = 32'hc67178f2;
endcase // case (round)
end // block: round_mux
endmodule // sha256_k_constants
//======================================================================
// sha256_k_constants.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1005; bool vis[maxn]; int n, m, k, p[maxn], a[maxn]; char s[maxn][maxn]; void func(int x, int y) { --m; if (x <= y) { s[m][x] = s[m][y] = / ; } else { s[m][x] = s[m][y] = ; } } int main() { scanf( %d , &n); m = n + 1, k = 0; for (int i = 1; i <= n; i++) { scanf( %d , &p[i]); for (int j = 1; j <= n; j++) { s[i][j] = . ; } } for (int i = 1; i <= n; i++) { if (!vis[i]) { int c = 0, v = i; while (!vis[v]) { a[++c] = v; vis[v] = 1; v = p[v]; } if (c <= 1) continue; reverse(a + 1, a + c + 1); if (k == 0) { func(a[1], a[1]); k = a[c]; for (int i = 2; i <= c; i++) { func(a[i], a[i - 1]); } continue; } for (int i = 1; i <= c; i++) { if (k <= a[i] && a[i] <= a[i == c ? 1 : i + 1]) { func(a[i == c ? 1 : i + 1], a[i]); s[m][k] = ; for (int j = i + 2; j <= c; j++) { func(a[j], a[j - 1]); } for (int j = (i == c) + 1; j < i; j++) { func(a[j], a[j == 1 ? c : j - 1]); } func(k, a[i == 1 ? c : i - 1]); break; } else if (k >= a[i] && a[i] >= a[i == c ? 1 : i + 1]) { func(a[i == c ? 1 : i + 1], a[i]); s[m][k] = / ; for (int j = i + 2; j <= c; j++) { func(a[j], a[j - 1]); } for (int j = 1; j < i; j++) { func(a[j], a[j == 1 ? c : j - 1]); } func(k, a[i == 1 ? c : i - 1]); break; } } } } printf( %d n , k == 0 ? n : n - 1); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { putchar(s[i][j]); } putchar( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int N; vector<int> Q[100010]; long long F[100010][2]; bool vis[100010]; void dfs(int u) { if (vis[u]) return; vis[u] = true, F[u][1] = 1LL, F[u][0] = 0LL; if (!Q[u].size()) return; long long d0, d1; for (int i = 0; i < Q[u].size(); i++) { int v = Q[u][i]; dfs(v); d0 = (F[u][1] * F[v][1] + F[u][0] * F[v][0]) % 1000000007; d1 = (F[u][1] * F[v][0] + F[u][0] * F[v][1]) % 1000000007; F[u][0] = (F[u][0] + d0) % 1000000007; F[u][1] = (F[u][1] + d1) % 1000000007; } long long p0 = 1LL, p1 = 1LL, p2 = 0LL; for (int i = 0; i < Q[u].size(); i++) { int v = Q[u][i]; p0 = (p0 + p0 * F[v][0]) % 1000000007; long long tmp = p1; p1 = (p1 + p2 * F[v][1]) % 1000000007; p2 = (p2 + tmp * F[v][1]) % 1000000007; } F[u][0] = (F[u][0] * 2 - p2 + 1000000007) % 1000000007; F[u][1] = (F[u][1] * 2 - p0 + 1000000007) % 1000000007; return; } int main() { scanf( %d , &N); for (int i = 2; i <= N; i++) { int x; scanf( %d , &x); Q[x].push_back(i); } memset(vis, false, sizeof(vis)); memset(F, 0, sizeof(F)); dfs(1); cout << (F[1][0] + F[1][1]) % 1000000007 << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; long long n, p; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long te; cin >> te; while (te--) { cin >> n >> p; vector<pair<long long, long long> > ans; for (long long i = 1; i <= n; i++) { for (long long j = i + 1; j <= n; j++) { ans.push_back({i, j}); } } for (long long i = 0; i < 2 * n + p; i++) cout << ans[i].first << << ans[i].second << n ; } return 0; }
|
module registerfile(
Q1,Q2.DI,clk,reset written,AD,A1,A2
);
output [31:0] Q1,Q2;
input [31:0] DI;
input clk,reset,written;
input [4:0] AD,A1,A2;
wire [31:0] decoderout,regen;
wire [31:0] q[31:0];
decoder dec_0(decoderout,AD);
assign regen[0] = decoderout[0]& written;
assign regen[1] = decoderout[1]& written;
//省略
assign regen[31] = decoderout[31]& written;
regesiter reg_0(q[0],DI,clk,reset,regen[0]);
regesiter reg_1(q[1],DI,clk,reset,regen[1]);
//省略
regesiter reg_31(q[31],DI,clk,reset,regen[31]);
mux_32 mux_1(Q1,q,A1);
mux_32 mux_2(Q2,q,A2);
endmodule
module dff(q,data,clk,reset,en)
output q;
input data,clk,reset,en;
reg q;
always@(posedge clk)
begin
if(reset) q<=0;
else if(en) q<=data;
else q<=q;
end
endmodule
module register(
q,data,clk,reset,en
);
output [31:0] q;
input [31:0]data;
input clk,reset,en;
dff u_0(q[0],data[0],clk,reset,en);
dff u_1(q[1],data[1],clk,reset,en);
// 省略
dff u_31(q[31],data[31],clk,reset,en);
endmodule
module mux_32(
output reg [31:0]q;
input [31:0]q[31:0];
input [4:0]raddr;
);
always@(raddr or q[31:0])
case(raddr)
5’d0: q<=q[0];
5’d1: q<=q[1];
// 省略
5’d31: q<=q[31];
default: q<= X;
endcase
endmodule
module decoder(
decoderout,waddr
);
output[31:0]decoderout;
input[4:0] waddr;
reg [31:0]decoderout;
always@(wadder)
case(wadder)
5’d0: decoderout<=32’b0000_00000_0000_0000_0000_0000_0000_0001;
5’d1: decoderout<=32’b0000_00000_0000_0000_0000_0000_0000_0010;
// 省略
5’d31: decoderout<=32’b1000_00000_0000_0000_0000_0000_0000_0000;
default: decoderout<= 32’bxxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx;
endcase
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:268435456 ) using namespace std; template <typename T> inline T abs(T a) { return ((a < 0) ? -a : a); } template <typename T> inline T sqr(T a) { return a * a; } template <class T> T gcd(T a, T b) { return a ? gcd(b % a, a) : b; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } template <class T> T sign(T a) { return a > 0 ? 1 : (a < 0 ? -1 : 0); } const int dx[] = {-1, 0, 1, 0}; const int dy[] = {0, 1, 0, -1}; const int dxK[] = {-1, -1, 0, 1, 1, 1, 0, -1}; const int dyK[] = {0, 1, 1, 1, 0, -1, -1, -1}; const int dxKn[] = {-2, -1, 1, 2, 2, 1, -1, -2}; const int dyKn[] = {1, 2, 2, 1, -1, -2, -2, -1}; const int N = int(1e6) + 9; const int M = int(2e2) + 9; const int LOGN = 22; const int SQN = 350; const int MOD = int(1e9) + 7; const int INF = 1e9 + 100; const long long INF64 = 2e18; const long double PI = 3.1415926535897932384626433832795; const long double EPS = 1e-9; long long d, v, n; pair<long long, long long> p[N]; void solve() { scanf( %I64d %I64d %I64d , &d, &v, &n); for (int i = 0; i < (int)(n); ++i) scanf( %I64d %I64d , &p[i].first, &p[i].second); p[n++] = make_pair(0, 0); p[n++] = make_pair(d, 0); sort(p, p + n); p[n] = make_pair(d, 0); multiset<pair<long long, long long> > s; long long res = 0; long long remd = v; for (int i = 0; i < (int)(n); ++i) { long long dist = p[i + 1].first - p[i].first; if (dist > v) { cout << -1; return; } long long cost = p[i].second; while (!s.empty() && s.rbegin()->first > cost) { pair<long long, long long> cur = *s.rbegin(); s.erase(--s.end()); res -= cur.first * 1LL * cur.second; remd += cur.second; } if (remd) { res += cost * remd; s.insert(make_pair(cost, remd)); remd = 0; } while (dist > 0) { pair<long long, long long> cur = *s.begin(); s.erase(s.begin()); long long curdist = min(dist, cur.second); dist -= curdist; cur.second -= curdist; remd += curdist; if (cur.second > 0) s.insert(cur); } } cout << res; } int main() { srand(time(NULL)); srand(time(NULL)); cout << setprecision(10) << fixed; cerr << setprecision(10) << fixed; solve(); return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - always force reg_lvalue = constant ;
// D: No dependancy
module main ;
wire [3:0] value1 ;
initial
begin
#15;
if(value1 != 4'h5)
$display("FAILED - 3.1.3F always force net_lvalue = constant;\n");
else
begin
$display("PASSED\n");
$finish;
end
end
always force value1 = 4'h5;
endmodule
|
#include <bits/stdc++.h> using namespace std; int cf[45], nc[45]; vector<int> ppf[45]; bool canadd(int i, int m) { for (int p : ppf[m]) { if (nc[p] && cf[p] != i % p) return false; } return true; } void add(int i, int m) { for (int p : ppf[m]) { if (nc[p] == 0) cf[p] = i % p; nc[p]++; } } void rem(int m) { for (int p : ppf[m]) { nc[p]--; } } vector<pair<int, int> > loc[100005]; int k[100005]; int n, m; int main() { for (int i = (2); i < (45); i++) { int x = i; for (int j = (2); j < (45); j++) { int fct = 1; while (x % j == 0) { fct *= j; ppf[i].push_back(fct); x /= j; } } } scanf( %d %d , &n, &m); for (int i = (0); i < (n); i++) { scanf( %d , k + i); for (int j = (0); j < (k[i]); j++) { int x; scanf( %d , &x); loc[x].push_back(make_pair(i, j)); } } for (int x = (1); x < (m + 1); x++) { queue<pair<int, int> > cq; int prv = -1, ans = 0; for (auto l : loc[x]) { int i, j; tie(i, j) = l; if (i != prv + 1) { while (int(cq.size())) { int fi, fj; tie(fi, fj) = cq.front(); cq.pop(); rem(k[fi]); } } while (!canadd(j, k[i])) { int fi, fj; tie(fi, fj) = cq.front(); cq.pop(); rem(k[fi]); } add(j, k[i]); cq.emplace(i, j); prv = i; ans = max(ans, int(cq.size())); } while (int(cq.size())) { int fi, fj; tie(fi, fj) = cq.front(); cq.pop(); rem(k[fi]); } printf( %d n , ans); } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); string s; cin >> s; int br = 0; for (int i = 0; i < s.size() / 2; i++) { if (s[i] == s[s.size() - i - 1]) continue; br++; } if (br >= 2 || br == 0) { if (s.size() % 2 == 1 && br == 0) { cout << YES ; return 0; } cout << NO << endl; } else { cout << YES << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = LLONG_MAX / 2; int extractMin(set<int> &mySet) { set<int>::iterator it = mySet.begin(); int ans = *(it); mySet.erase(it); return ans; } int search(set<int> &mySet, int index) { set<int>::iterator it = mySet.lower_bound(index); if (it == mySet.end()) { return -1; } int ans = *(it); return ans; } void eliminate(set<int> &mySet, int index) { set<int>::iterator it = mySet.lower_bound(index); if (it == mySet.end()) { assert(false); } mySet.erase(it); } void notFound() { cout << -1 << n ; } void impr(vector<vector<int> > ans) { printf( %d n , ((int)(ans).size())); for (int i = 0; i < ((int)(ans).size()); i++) { printf( %d , ((int)(ans[i]).size())); for (int j = 0; j < ((int)(ans[i]).size()); j++) { printf( %d , ans[i][j] + 1); } puts( ); } } void solve(string str) { int n = ((int)(str).size()); set<int> zeroes, ones; for (int i = 0; i < n; i++) { if (str[i] == 0 ) { zeroes.insert(i); } else { ones.insert(i); } } vector<vector<int> > ans; while (true) { if (zeroes.empty() && ones.empty()) { break; } if (zeroes.empty()) { notFound(); return; } int curZero = extractMin(zeroes); vector<int> seq(1, curZero); while (true) { int curOne = search(ones, curZero + 1); curZero = search(zeroes, curOne + 1); if (curOne == -1 || curZero == -1) { break; } seq.push_back(curOne); seq.push_back(curZero); eliminate(ones, curOne); eliminate(zeroes, curZero); } ans.push_back(seq); } impr(ans); } int main() { string str; while (cin >> str) { solve(str); } }
|
// $Id: c_fifo_tracker.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// module for tracking state of a FIFO
//==============================================================================
module c_fifo_tracker
(clk, reset, active, push, pop, almost_empty, empty, almost_full, full,
two_free, errors);
`include "c_functions.v"
`include "c_constants.v"
// total number of credits available
parameter depth = 8;
// generate the almost_empty output early in the clock cycle
parameter fast_almost_empty = 0;
// generate the two_free output early in the clock cycle
parameter fast_two_free = 0;
// allow bypassing through empty FIFO (i.e., empty & push & pop)
parameter enable_bypass = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
// width required to represent full range of credit count (0..depth)
localparam free_width = clogb(depth+1);
input clk;
input reset;
input active;
// add an entry
input push;
// remove an entry
input pop;
// all but one entries free
output almost_empty;
wire almost_empty;
// all entries free
output empty;
wire empty;
// all but one entries occupied
output almost_full;
wire almost_full;
// all entries occupied
output full;
wire full;
// two entries are free
output two_free;
wire two_free;
// internal error condition encountered
output [0:1] errors;
wire [0:1] errors;
wire error_underflow;
generate
if(enable_bypass)
assign error_underflow = empty & ~push & pop;
else
assign error_underflow = empty & pop;
endgenerate
wire error_overflow;
assign error_overflow = full & push;
generate
if(depth == 1)
begin
wire empty_s, empty_q;
assign empty_s = pop ? 1'b1 :
push ? 1'b0 :
empty_q;
c_dff
#(.width(1),
.reset_value(1'b1),
.reset_type(reset_type))
emptyq
(.clk(clk),
.reset(reset),
.active(active),
.d(empty_s),
.q(empty_q));
assign empty = empty_q;
assign almost_empty = ~empty;
assign almost_full = empty;
assign full = ~empty;
assign two_free = 1'b0;
end
else if(depth > 1)
begin
wire [0:free_width-1] free;
wire [0:free_width-1] free_minus1;
c_decr
#(.width(free_width))
free_minus1_decr
(.data_in(free),
.data_out(free_minus1));
wire [0:free_width-1] free_plus1;
c_incr
#(.width(free_width))
free_plus1_incr
(.data_in(free),
.data_out(free_plus1));
wire [0:free_width-1] free_s, free_q;
assign free_s = (push & ~pop) ? free_minus1 :
(~push & pop) ? free_plus1 :
free_q;
c_dff
#(.width(free_width),
.reset_value(depth),
.reset_type(reset_type))
freeq
(.clk(clk),
.reset(reset),
.active(active),
.d(free_s),
.q(free_q));
assign free = free_q;
wire free_max_minus1;
assign free_max_minus1 = (free == (depth - 1));
if(fast_almost_empty)
begin
wire free_max;
assign free_max = (free == depth);
wire free_max_minus2;
assign free_max_minus2 = (free == (depth - 2));
wire almost_empty_s, almost_empty_q;
if(enable_bypass)
assign almost_empty_s = (push & ~pop) ? free_max :
(~push & pop) ? free_max_minus2 :
almost_empty_q;
else
assign almost_empty_s = push ? free_max :
pop ? free_max_minus2 :
almost_empty_q;
c_dff
#(.width(1),
.reset_type(reset_type))
almost_emptyq
(.clk(clk),
.reset(reset),
.active(active),
.d(almost_empty_s),
.q(almost_empty_q));
assign almost_empty = almost_empty_q;
end
else
assign almost_empty = free_max_minus1;
wire empty_s, empty_q;
if(enable_bypass)
assign empty_s = (push & ~pop) ? 1'b0 :
(pop & ~push) ? free_max_minus1 :
empty_q;
else
assign empty_s = push ? 1'b0 :
pop ? free_max_minus1 :
empty_q;
c_dff
#(.width(1),
.reset_value(1'b1),
.reset_type(reset_type))
emptyq
(.clk(clk),
.reset(reset),
.active(active),
.d(empty_s),
.q(empty_q));
assign empty = empty_q;
wire free_one;
assign free_one = (free == 1);
if(depth == 2)
begin
assign almost_full = almost_empty;
assign two_free = empty;
end
else if(depth > 2)
begin
wire free_two;
assign free_two = (free == 2);
wire free_zero;
assign free_zero = (free == 0);
wire almost_full_s, almost_full_q;
assign almost_full_s = (push & ~pop) ? free_two :
(~push & pop) ? free_zero :
almost_full_q;
c_dff
#(.width(1),
.reset_type(reset_type))
almost_fullq
(.clk(clk),
.reset(reset),
.active(active),
.d(almost_full_s),
.q(almost_full_q));
assign almost_full = almost_full_q;
wire free_three;
assign free_three = (free == 3);
if(fast_two_free)
begin
wire two_free_s, two_free_q;
assign two_free_s = (push & ~pop) ? free_three :
(~push & pop) ? free_one :
two_free_q;
c_dff
#(.width(1),
.reset_type(reset_type))
two_freeq
(.clk(clk),
.reset(reset),
.active(active),
.d(two_free_s),
.q(two_free_q));
assign two_free = two_free_q;
end
else
assign two_free = free_two;
end
wire full_s, full_q;
assign full_s = pop ? 1'b0 :
push ? free_one :
full_q;
c_dff
#(.width(1),
.reset_type(reset_type))
fullq
(.clk(clk),
.reset(reset),
.active(active),
.d(full_s),
.q(full_q));
assign full = full_q;
end
// synopsys translate_off
else
begin
initial
begin
$display({"ERROR: FIFO tracker module %m requires a depth of at ",
"least one entry."});
$stop;
end
end
// synopsys translate_on
endgenerate
// synopsys translate_off
always @(posedge clk)
begin
if(error_underflow)
$display("ERROR: FIFO tracker underflow in module %m.");
if(error_overflow)
$display("ERROR: FIFO tracker overflow in module %m.");
end
// synopsys translate_on
assign errors = {error_underflow, error_overflow};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3_SYMBOL_V
`define SKY130_FD_SC_MS__NOR3_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111A_TB_V
`define SKY130_FD_SC_HS__O2111A_TB_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2111a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 C1 = 1'b1;
#240 D1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 C1 = 1'b0;
#380 D1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 D1 = 1'b1;
#500 C1 = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 D1 = 1'bx;
#640 C1 = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__o2111a dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111A_TB_V
|
#include <bits/stdc++.h> using namespace std; char types[11]; bool possible[1005][12][11]; int m; int pre[1005][12][11][3]; int main() { scanf( %s , types); scanf( %d , &m); for (int i = 0; i < 11; ++i) for (int d = 0; d <= 10; ++d) possible[0][i][d] = 0; possible[0][0][0] = 1; int best = 0; int bestVal[3]; for (int j = 1; j <= m; ++j) { for (int d = 0; d <= 10; ++d) possible[j][0][d] = 0; for (int i = 1; i < 11; ++i) for (int d = 0; d <= 10; ++d) { possible[j][i][d] = 0; if (types[i - 1] == 0 || !d || d > i) { continue; } for (int k = 0; k < 11; ++k) { if (!possible[j - 1][k][i - d] || k == i) continue; possible[j][i][d] = 1; pre[j][i][d][0] = j - 1; pre[j][i][d][1] = k; pre[j][i][d][2] = i - d; best = j; bestVal[0] = j; bestVal[1] = i; bestVal[2] = d; } } } if (best == m) { printf( YES n ); int j = bestVal[0], i = bestVal[1], d = bestVal[2]; int ansList[1005]; ansList[j - 1] = i; while (j > 1) { int jp = pre[j][i][d][0], ip = pre[j][i][d][1], kp = pre[j][i][d][2]; j = jp; i = ip; d = kp; ansList[j - 1] = i; } for (int a = 0; a < m; ++a) printf( %d , ansList[a]); } else printf( NO n ); return 0; }
|
/*
* Author : Tom Stanway-Mayers
* Description : Pre-Fetch Unit
* Version: :
* License : Apache License Version 2.0, January 2004
* License URL : http://www.apache.org/licenses/
*/
`include "riscv_defs.v"
module merlin_pfu32ic
#(
parameter C_FIFO_PASSTHROUGH = 0,
parameter C_FIFO_DEPTH_X = 2, // depth >= read latency + 2
parameter C_WORD_RESET_VECTOR = 30'b0
)
(
// global
input wire clk_i,
input wire reset_i,
// instruction cache interface
input wire ireqready_i,
output wire ireqvalid_o,
output wire [1:0] ireqhpl_o,
output wire [31:0] ireqaddr_o, // TODO - consider bypassing the pc on a jump
output wire irspready_o,
input wire irspvalid_i,
input wire irsprerr_i,
input wire [31:0] irspdata_i,
// decoder interface
output wire ids_dav_o, // new fetch available
input wire ids_ack_i, // ack this fetch
input wire [1:0] ids_ack_size_i, // size of this ack
output reg [`RV_SOFID_RANGE] ids_sofid_o, // first fetch since vectoring
output reg [31:0] ids_ins_o, // instruction fetched
output wire ids_ferr_o, // this instruction fetch resulted in error
output wire [31:0] ids_pc_o, // address of this instruction
// ex stage vectoring interface
input wire exs_pc_wr_i,
input wire [31:0] exs_pc_din_i,
// pfu stage interface
input wire [1:0] exs_hpl_i
);
//--------------------------------------------------------------
// interface assignments
// request gate register
reg request_gate;
// ibus debt
reg ibus_debt;
wire request;
wire response;
// fifo level counter
reg [C_FIFO_DEPTH_X:0] fifo_level_q;
reg fifo_accepting;
// program counter
reg [31:0] pc_q;
reg [31:0] request_addr_q;
// vectoring flag register
reg vectoring_q;
// sofid register
reg sofid_q;
// line fifo
parameter C_FIFO_LINE_WIDTH = 1 + 30;
//
parameter C_FERR_LSB = 30;
parameter C_FIFO_PC_LSB = 0;
//
wire fifo_line_rd;
wire [C_FIFO_LINE_WIDTH-1:0] fifo_line_din;
wire [C_FIFO_LINE_WIDTH-1:0] fifo_line_dout;
// atom fifo
genvar genvar_i;
wire [1:0] fifo_atom_empty;
wire [1:0] fifo_atom_wr_mask;
wire [1:0] fifo_atom_rd_mask;
wire [1:0] fifo_atom_din_sof;
wire [16:0] fifo_atom_dout[1:0];
wire [15:0] fifo_atom_dout_ins[1:0];
wire [1:0] fifo_atom_dout_sof;
// base pointer
reg atom_base_q;
reg atom_base;
//--------------------------------------------------------------
//--------------------------------------------------------------
// interface assignments
//--------------------------------------------------------------
assign ireqhpl_o = exs_hpl_i;
assign ireqvalid_o = fifo_accepting & ~exs_pc_wr_i & (~ibus_debt | response) & request_gate;
assign ireqaddr_o = { pc_q[31:2], 2'b0 };
assign irspready_o = 1'b1; //irspvalid_i; // always ready
//
assign ids_dav_o = ~(|fifo_atom_empty);
//--------------------------------------------------------------
// request gate register
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
request_gate <= 1'b0;
end else begin
request_gate <= 1'b1;
end
end
//--------------------------------------------------------------
// ibus debt
//--------------------------------------------------------------
assign request = ireqvalid_o & ireqready_i;
assign response = irspvalid_i & irspready_o;
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
ibus_debt <= 1'b0;
end else begin
if (request & ~response) begin
ibus_debt <= 1'b1;
end else if (~request & response) begin
ibus_debt <= 1'b0;
end
end
end
//--------------------------------------------------------------
// fifo level counter
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
fifo_level_q <= { 1'b1, { C_FIFO_DEPTH_X {1'b0} } };
end else begin
if (exs_pc_wr_i) begin
fifo_level_q <= { 1'b1, { C_FIFO_DEPTH_X {1'b0} } };
end else if (request & ~fifo_line_rd) begin
fifo_level_q <= fifo_level_q - { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end else if (~request & fifo_line_rd) begin
fifo_level_q <= fifo_level_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end
end
end
always @ (*) begin
if (|fifo_level_q) begin
fifo_accepting = 1'b1;
end else begin
fifo_accepting = 1'b0;
end
end
//--------------------------------------------------------------
// program counter
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
pc_q <= { C_WORD_RESET_VECTOR, 2'b0 };
end else begin
if (exs_pc_wr_i) begin
pc_q <= exs_pc_din_i;
end else if (request) begin
pc_q <= pc_q + 32'd4;
end
end
end
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
if (request) begin
request_addr_q <= pc_q;
end
end
//--------------------------------------------------------------
// vectoring flag register
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
vectoring_q <= 1'b0;
end else begin
if (exs_pc_wr_i) begin
vectoring_q <= 1'b1;
end else if (request) begin
vectoring_q <= 1'b0;
end
end
end
//--------------------------------------------------------------
// sofid register
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
sofid_q <= 1'b0;
end else begin
if (vectoring_q & request) begin
sofid_q <= 1'b1;
end else if (response) begin
sofid_q <= 1'b0;
end
end
end
//--------------------------------------------------------------
// line fifo
//--------------------------------------------------------------
assign fifo_line_rd = ids_ack_i & (atom_base | ids_ack_size_i[1]);
assign fifo_line_din[ C_FERR_LSB +: 1] = irsprerr_i;
assign fifo_line_din[C_FIFO_PC_LSB +: 30] = request_addr_q[31:2];
//
assign ids_ferr_o = fifo_line_dout[C_FERR_LSB +: 1];
assign ids_pc_o = { fifo_line_dout[C_FIFO_PC_LSB +: 30], atom_base, 1'b0 };
//
merlin_fifo
#(
.C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
.C_FIFO_WIDTH (C_FIFO_LINE_WIDTH),
.C_FIFO_DEPTH_X (C_FIFO_DEPTH_X)
) i_line_merlin_fifo (
// global
.clk_i (clk_i),
.reset_i (reset_i),
// control and status
.flush_i (exs_pc_wr_i | vectoring_q),
.empty_o (),
.full_o (),
// write port
.wr_i (response),
.din_i (fifo_line_din),
// read port
.rd_i (fifo_line_rd),
.dout_o (fifo_line_dout)
);
//--------------------------------------------------------------
// atom fifo
//--------------------------------------------------------------
assign fifo_atom_wr_mask = { 1'b1, ~sofid_q | (sofid_q & ~request_addr_q[1]) };
assign fifo_atom_rd_mask = { atom_base | ids_ack_size_i[1], ~atom_base | ids_ack_size_i[1] };
assign fifo_atom_din_sof = { (sofid_q & request_addr_q[1]), (sofid_q & ~request_addr_q[1]) };
//
generate
for (genvar_i = 0; genvar_i < 2; genvar_i = genvar_i + 1) begin : atom_fifo
assign fifo_atom_dout_ins[genvar_i] = fifo_atom_dout[genvar_i][15:0];
assign fifo_atom_dout_sof[genvar_i] = fifo_atom_dout[genvar_i][16];
//
merlin_fifo
#(
.C_FIFO_PASSTHROUGH (C_FIFO_PASSTHROUGH),
.C_FIFO_WIDTH (17), // <last> <first> <instruction atom>
.C_FIFO_DEPTH_X (C_FIFO_DEPTH_X)
) i_atom_merlin_fifo (
// global
.clk_i (clk_i),
.reset_i (reset_i),
// control and status
.flush_i (exs_pc_wr_i | vectoring_q),
.empty_o (fifo_atom_empty[genvar_i]),
.full_o (),
// write port
.wr_i (response & fifo_atom_wr_mask[genvar_i]),
.din_i ({ fifo_atom_din_sof[genvar_i], irspdata_i[16*genvar_i +: 16] }),
// read port
.rd_i (ids_ack_i & fifo_atom_rd_mask[genvar_i]),
.dout_o (fifo_atom_dout[genvar_i])
);
end
endgenerate
//--------------------------------------------------------------
// base pointer
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
atom_base_q <= 1'b0; // NOTE: don't care
end else if (ids_ack_i) begin
if (|fifo_atom_dout_sof) begin
if (~ids_ack_size_i[1]) begin // ack 16
atom_base_q <= ~fifo_atom_dout_sof[1];
end else begin // ack 32
atom_base_q <= fifo_atom_dout_sof[1];
end
end else begin
if (~ids_ack_size_i[1]) begin // ack 16
atom_base_q <= ~atom_base_q;
end
end
end
end
//
always @ (*) begin
if (|fifo_atom_dout_sof) begin
atom_base = fifo_atom_dout_sof[1];
end else begin
atom_base = atom_base_q;
end
end
//--------------------------------------------------------------
// instruction output mux
//--------------------------------------------------------------
always @ (*) begin
if (atom_base == 1'b0) begin
ids_ins_o = { fifo_atom_dout_ins[1], fifo_atom_dout_ins[0] };
end else begin
ids_ins_o = { fifo_atom_dout_ins[0], fifo_atom_dout_ins[1] };
end
if (|fifo_atom_dout_sof) begin
ids_sofid_o = `RV_SOFID_JUMP;
end else begin
ids_sofid_o = `RV_SOFID_RUN;
end
end
endmodule
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module VOICE_ROM_INIT (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [5 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [15 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [5 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [15 : 0] doutb;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("VOICE_ROM_INIT.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_READ_WIDTH_A(16),
.C_WRITE_DEPTH_A(64),
.C_READ_DEPTH_A(64),
.C_ADDRA_WIDTH(6),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(16),
.C_READ_WIDTH_B(16),
.C_WRITE_DEPTH_B(64),
.C_READ_DEPTH_B(64),
.C_ADDRB_WIDTH(6),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("0"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.01735 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(addrb),
.dinb(16'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(16'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2017 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`timescale 1ps / 1ps
module pixel_reader (
input clk,
input rst,
//FIFO interface
input i_read_rdy,
output reg o_read_act,
input [23:0] i_read_size,
input [24:0] i_read_data,
output reg o_read_stb,
//Output Pixels
output reg [7:0] o_red,
output reg [7:0] o_green,
output reg [7:0] o_blue,
output reg o_pixel_rdy,
input i_pixel_stb,
//Test Generator
input i_tp_red,
input i_tp_blue,
input i_tp_green,
output reg o_last
);
//local parameters
//registes/wires
reg [7:0] r_next_red;
reg [7:0] r_next_green;
reg [7:0] r_next_blue;
reg [31:0] r_read_count;
reg r_tp_green;
reg r_tp_blue;
//submodules
//asynchronous logic
//synchronous logic
always @ (posedge clk) begin
o_read_stb <= 0;
o_pixel_rdy <= 0;
if (rst) begin
o_read_act <= 0;
o_red <= 0;
o_green <= 0;
o_blue <= 0;
r_next_red <= 0;
r_next_green <= 0;
r_next_blue <= 0;
o_last <= 0;
end
else begin
//If a FIFO is available activate it
if (i_read_rdy && !o_read_act) begin
r_read_count <= 0;
o_read_act <= 1;
end
if (o_pixel_rdy) begin
if (i_pixel_stb) begin
o_pixel_rdy <= 0;
o_red <= i_read_data[23:16];
o_green <= i_read_data[15:8];
o_blue <= i_read_data[7:0];
o_last <= i_read_data[24];
end
end
if (o_read_act) begin
o_pixel_rdy <= 1;
if (r_read_count < i_read_size) begin
if (i_pixel_stb) begin
r_read_count <= r_read_count + 1;
o_read_stb <= 1;
end
end
else begin
o_read_act <= 0;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; cin >> n >> m; long long mod = 1; int k = 0; while (k < n) { if (mod > m) { break; } mod *= 2; k++; } cout << m % mod << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4_4_V
`define SKY130_FD_SC_MS__NOR4_4_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4_4_V
|
#include <bits/stdc++.h> using namespace std; std::vector<long long> v[100009]; long long vis[100009], c = 0; void dfs(long long x) { c++; vis[x] = 1; for (auto i : v[x]) if (!vis[i]) dfs(i); } signed main() { ios_base::sync_with_stdio(false), cin.tie(NULL); long long i, n, m, s = 0; cin >> n >> m; for (i = 1; i <= m; i++) { long long a, b; cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } for (i = 1; i <= n; i++) { if (!vis[i]) { c = 0; dfs(i); s += (c - 1); } } cout << m - s; }
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module seven_seg_pio (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 15: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 15: 0] data_out;
wire [ 15: 0] out_port;
wire [ 15: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {16 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[15 : 0];
end
assign readdata = {{{32- 16}{1'b0}},read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, q, a[200010]; struct node { int l, r, color; node(int ll = 0, int rr = 0, int cc = 0) : l(ll), r(rr), color(cc) {} }; node p[200010]; vector<int> vec[200010]; bool cmp(node a, node b) { if (a.l != b.l) return a.l < b.l; return a.r > b.r; } int main() { cin >> n >> q; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); vec[a[i]].push_back(i); } int cnt = 0; for (int i = 1; i <= 200000; ++i) { if (!vec[i].size()) continue; int l = vec[i][0], r = vec[i][vec[i].size() - 1]; p[++cnt] = node(l, r, i); } sort(p + 1, p + 1 + cnt, cmp); p[cnt + 1].l = 1e9 + 10; int ans = 0, l = 1e9 + 10, r = 0, tmp = 0; for (int i = 1; i <= cnt + 1; ++i) { if (i == 1 || p[i].l < r) { l = min(l, p[i].l); r = max(r, p[i].r); tmp = max(tmp, (int)vec[p[i].color].size()); } else { ans += r - l + 1 - tmp; l = p[i].l; r = p[i].r; tmp = vec[p[i].color].size(); } } printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5; char s[maxn]; int a[maxn]; int n, l, r, i, x; int main() { scanf( %s , s + 1); n = strlen(s + 1); for (i = 1; i <= n; i++) a[i] = s[i] - 0 ; l = 1; r = n; if (a[l] != a[r]) { a[l]--; a[l + 1] += 10; if (!a[l]) l++; else if (a[l] != a[r]) { printf( 0 ); return 0; } } while (l <= r) { if (a[l] >= a[r] + 10 && a[r] < 10) a[r - 1]--, a[r] += 10; if (a[l] == a[r] + 1) a[l + 1] += 10, a[l]--; if (a[l] != a[r]) break; if (l != r) { a[l] = a[l] - a[l] / 2; a[r] -= a[l]; } else if ((a[l] & 1) == 0) a[l] >>= 1; else break; if (a[l] < 0 || a[l] > 9 || a[r] < 0 || a[r] > 9) break; l++; r--; } if (l <= r) { printf( 0 ); } else { l = 1; if (!a[l]) l++; while (l <= n) { printf( %d , a[l]); l++; } } return 0; }
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_eth_fcs_insert_64
*/
module test_axis_eth_fcs_insert_64;
// Parameters
parameter ENABLE_PADDING = 0;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] s_axis_tdata = 0;
reg [7:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [63:0] m_axis_tdata;
wire [7:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser,
busy
);
// dump file
$dumpfile("test_axis_eth_fcs_insert_64.lxt");
$dumpvars(0, test_axis_eth_fcs_insert_64);
end
axis_eth_fcs_insert_64 #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.busy(busy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200009; int a[N], pos[N]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) { int x; cin >> x; pos[x] = i; } for (int i = 1; i <= n; i++) a[i] = pos[a[i]]; int ans = 0; for (int i = 2; i <= n; i++) { if (a[i] < a[i - 1]) { i--; cout << n - i << endl; return 0; } } cout << 0 << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O2BB2A_PP_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_TB_V
`define SKY130_FD_SC_HS__SDFSTP_TB_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfstp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SCD = 1'b1;
#180 SCE = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SCD = 1'b0;
#300 SCE = 1'b0;
#320 SET_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SET_B = 1'b1;
#440 SCE = 1'b1;
#460 SCD = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SET_B = 1'bx;
#560 SCE = 1'bx;
#580 SCD = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_1_V
`define SKY130_FD_SC_LS__O2BB2A_1_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2bb2a_1 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2bb2a_1 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BO_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A21BO_PP_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BO_PP_BLACKBOX_V
|
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