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#include <bits/stdc++.h> using namespace std; int m, n, rowStart[1010], rowEnd[1010], colStart[1010], colEnd[1010], sum[1010][1010]; int startX = -1, startY; string a[1010]; void quit() { cout << -1 << endl; exit(0); } int getSum(int x, int y, int row, int col) { return sum[x][y] + sum[x - row][y - col] - sum[x - row][y] - sum[x][y - col]; } int ok(int row, int col) { int x = startX + row - 1, y = startY + col - 1, covered = col * row; while (1) { if (x < m && getSum(x + 1, y, row, col) == row * col) { x++; covered += col; } else if (y < n && getSum(x, y + 1, row, col) == row * col) { y++; covered += row; } else break; } return covered == sum[m][n]; } void solve() { int sideRow = colEnd[startY] - colStart[startY] + 1; int sideCol = rowEnd[startX] - rowStart[startX] + 1; int ans = m * n + 1; for (int col = 1; col <= sideCol; col++) if (ok(sideRow, col)) { ans = min(ans, sideRow * col); break; } for (int row = 1; row <= sideRow; row++) if (ok(row, sideCol)) { ans = min(ans, sideCol * row); break; } if (ans > m * n) ans = -1; cout << ans << endl; } int main() { ios::sync_with_stdio(0); cin >> m >> n; for (int i = 1; i <= m; i++) { cin >> a[i]; rowStart[i] = rowEnd[i] = -1; int cntX = 0; for (int j = 1; j <= n; j++) { sum[i][j] = sum[i - 1][j] + sum[i][j - 1] - sum[i - 1][j - 1]; if (a[i][j - 1] == X ) { if (startX < 0) { startX = i; startY = j; } if (rowStart[i] < 0) rowStart[i] = j; rowEnd[i] = j; cntX++; sum[i][j]++; } } if (rowStart[i] > 0 && cntX != rowEnd[i] - rowStart[i] + 1) quit(); } for (int j = 1; j <= n; j++) { colStart[j] = colEnd[j] = -1; int cntX = 0; for (int i = 1; i <= m; i++) if (a[i][j - 1] == X ) { if (colStart[j] < 0) colStart[j] = i; colEnd[j] = i; cntX++; } if (colStart[j] > 0 && cntX != colEnd[j] - colStart[j] + 1) quit(); } solve(); }
|
(****************************************************************************)
(* Copyright 2021 The Project Oak Authors *)
(* *)
(* Licensed under the Apache License, Version 2.0 (the "License") *)
(* you may not use this file except in compliance with the License. *)
(* You may obtain a copy of the License at *)
(* *)
(* http://www.apache.org/licenses/LICENSE-2.0 *)
(* *)
(* Unless required by applicable law or agreed to in writing, software *)
(* distributed under the License is distributed on an "AS IS" BASIS, *)
(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *)
(* See the License for the specific language governing permissions and *)
(* limitations under the License. *)
(****************************************************************************)
Require Import Coq.Lists.List.
Require Import Coq.Vectors.Vector.
Require Import ExtLib.Structures.Monads.
Import ListNotations VectorNotations MonadNotation.
Open Scope monad_scope.
Require Import Cava.Core.Core.
Require Import Cava.Lib.CavaPrelude.
Require Import Cava.Lib.Combinators.
Require Import Cava.Util.Vector.
(**** IMPORTANT: if you make changes to the API of these definitions, or add new
ones, make sure you update the reference at docs/reference.md! ****)
Section WithCava.
Context `{semantics:Cava}.
(* Build a half adder *)
Definition halfAdder '(x, y) :=
partial_sum <- xor2 (x, y) ;;
carry <- and2 (x, y) ;;
ret (partial_sum, carry).
(* A full adder *)
Definition fullAdder '(cin, (x, y))
: cava (signal Bit * signal Bit) :=
'(xyl, xyh) <- halfAdder (x, y) ;;
'(xycl, xych) <- halfAdder (xyl, cin) ;;
cout <- or2 (xyh, xych) ;;
ret (xycl, cout).
(* Unsigned adder for n-bit vectors with carry bits both in and out *)
Definition addC {n : nat}
(inputs : signal (Vec Bit n) * signal (Vec Bit n) * signal Bit) :
cava (signal (Vec Bit n) * signal Bit) :=
let '(x, y, cin) := inputs in
x <- unpackV x ;;
y <- unpackV y ;;
col fullAdder cin (vcombine x y).
(* Unsigned adder for n-bit vectors with bit-growth and no carry bits in or out *)
Definition addN {n : nat}
(xy: signal (Vec Bit n) * signal (Vec Bit n)) :
cava (signal (Vec Bit n)) :=
'(sum, _) <- addC (xy, zero) ;;
ret sum.
(* Increment an n-bit vector, representing result as an n-bit vector and a
carry bit *)
Definition incrC {n : nat} : signal (Vec Bit n) -> cava (signal (Vec Bit n) * signal Bit) :=
match n with
| 0 => fun input => ret (input, one) (* incrementing a 0-length vector always overflows *)
| S m =>
fun input : signal (Vec Bit (S m)) =>
(* use synthesizable adder to add 1 *)
onev <- packV [one] ;;
sum <- unsignedAdd (input, onev) ;;
(* resize (1 + Nat.max (S m) 1) to S (S m) *)
sum <- Vec.resize_default (S (S m)) sum ;;
(* separate highest bit from rest of sum *)
sum_low <- Vec.shiftout sum ;;
sum_high <- Vec.last sum ;;
ret (sum_low, sum_high)
end.
(* Increment an n-bit vector with no bit-growth *)
Definition incrN {n : nat} (input : signal (Vec Bit n)) : cava (signal (Vec Bit n)) :=
'(out, _) <- incrC input ;;
ret out.
Section XilinxAdders.
(* Build a full-adder with explicit use of Xilinx FPGA fast carry logic *)
Definition xilinxFullAdder '(cin, (x, y))
: cava (signal Bit * signal Bit) :=
part_sum <- xor2 (x, y) ;;
sum <- xorcy (part_sum, cin) ;;
cout <- muxcy part_sum cin x ;;
ret (sum, cout).
(* An unsigned adder built using the fast carry full-adder.*)
Definition xilinxAdderWithCarry {n: nat}
(xyc : signal (Vec Bit n) * signal (Vec Bit n) * signal Bit)
: cava (signal (Vec Bit n) * signal Bit)
:= let '(x, y, cin) := xyc in
x <- unpackV x ;;
y <- unpackV y ;;
col xilinxFullAdder cin (vcombine x y).
(* An unsigned adder with no bit-growth and no carry in or out *)
Definition xilinxAdder {n: nat}
(x y : signal (Vec Bit n))
: cava (signal (Vec Bit n)) :=
'(sum, carry) <- xilinxAdderWithCarry (x, y, zero) ;;
ret sum.
End XilinxAdders.
End WithCava.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A222OI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long mod1 = 19260817; const long long mod2 = 19660813; int n; int m; char s[200005]; char opt[5]; struct { int tree[200005]; int lowbit(int x) { return x & -x; } void ins(int pos, int val) { for (; pos <= n; pos += lowbit(pos)) tree[pos] += val; } int query(int pos) { int sum = 0; for (; pos; pos -= lowbit(pos)) sum += tree[pos]; return sum; } } t[125]; int find(int x) { int ret = 0; for (int i = 20; i >= 0; --i) { if (ret + (1 << i) > n) continue; int sum = 0; for (int j = 48; j < 125; ++j) sum += t[j].tree[ret + (1 << i)]; if (x >= sum) { x -= sum; ret += (1 << i); } } return ret; } set<int> book[125]; set<int>::iterator it; vector<int> memo; bool check(int pos) { if (pos == 1) { if (t[s[pos]].query(pos)) return true; } else { if (t[s[pos]].query(pos) - t[s[pos]].query(pos - 1)) return true; } return false; } int main() { scanf( %d %d , &n, &m); scanf( %s , s + 1); for (int i = 1; i <= n; ++i) { t[s[i]].ins(i, 1); book[s[i]].insert(i); } while (m--) { int l; int r; scanf( %d %d %s , &l, &r, opt + 1); int lcur = find(l - 1) + 1; int rcur = find(r - 1) + 1; it = book[opt[1]].lower_bound(lcur); memo.clear(); while (it != book[opt[1]].end()) { int pos = *it; if (pos > rcur) break; memo.push_back(pos); ++it; } for (auto p : memo) book[opt[1]].erase(p); for (auto p : memo) t[opt[1]].ins(p, -1); } for (int i = 1; i <= n; ++i) { if (check(i)) printf( %c , s[i]); } printf( n ); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : 64 by 32 two port RAM
// File : ram_64x32_2p.v
// Author : Jim Macleod
// Created : 06-April-2005
// RCS File : $Source: /u/Maxwell/hdl/vga/RCS/ram_64x32_2p.v,v $
// Status : $Id: ram_64x32_2p.v,v 1.1 2005/10/11 21:14:15 fbruno Exp fbruno $
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
/////////////////////////////////////////////////////////////////////////////////
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log: ram_64x32_2p.v,v $
// Revision 1.1 2005/10/11 21:14:15 fbruno
// Initial revision
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module ram_64x32_2p
(
input clock,
input wren,
input [4:0] wraddress,
input [4:0] rdaddress,
input [63:0] data,
output reg [63:0] q
);
reg [63:0] mem_a [0:31];
always @(posedge clock) if(wren) mem_a[wraddress] <= data;
always @(posedge clock) q <= mem_a[rdaddress];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:43:21 09/16/2016
// Design Name:
// Module Name: Display
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Display(input clk,
input rst,
input Start,
input Text,
input flash,
input [31:0]Hexs,
input [7:0]point,
input [7:0]LES,
output segclk,
output segsout,
output SEGEN,
output segclrn
);
wire [63:0]a,b,o;
assign o = Text ? a : b;
HexTo8SEG SM1(.Hexs(Hexs),
.points(point),
.LES(LES),
.flash(flash),
.SEG_TXT(a)
);
SSeg_map SM3(.Disp_num({Hexs,Hexs}),
.Seg_map(b)
);
P2S #(.DATA_BITS(64),.DATA_COUNT_BITS(6),.DIR(1))
P7SEG (.clk(clk),
.rst(rst),
.Start(Start),
.PData(o),
.sclk(segclk),
.sclrn(segclrn),
.sout(segsout),
.EN(SEGEN)
);
endmodule
|
//****************************************************
// 6502 soft core project
// 8 bit ALU module
// Created March 14, 2005
// Author: Jim Patchell
//
// This code can be used for any purpose, except as
// a being used to turn in as a homework problem for
// school courses...note to teachers...your student
// did not do this work...
//
//****************************************************
module alu(CLK,RESET,A,B,Y,OP,C,N,V,Z);
//****************************************************
// 8 bit arithmetic logic unit
//
// parameter:
// CLK.......system clock
// RESET.....System Reset
// A.........A input
// B.........B input
// OP........operation to perform
// Y.........8 bit result output
// C.........carry status
// V.........overflow status
// N.........sign status
// Z.........zero status
//
//****************************************************
input CLK,RESET;
input [7:0] A;
input [7:0] B;
input [15:0] OP;
output [7:0] Y;
output C;
output V;
output N;
output Z;
//------------------------------------------------------
// internal nodes
//------------------------------------------------------
reg [7:0] Y,LogicUnit,AluNoShift;
wire [7:0] ArithUnit;
reg shiftout;
wire C,V,N,Z;
wire carryout;
wire ovf;
reg Neg; //negative status from ALU
reg Zero; //Zero Status from ALU
//-----------------------------------------------------------
// Arithmetic unit
//
// gona use myAddSub for this part...it seems to work right...
// rather than trying to infer the thing.
//
// operation of the adder subtractor is as follows
//
// OP[0] OP[1] carry | operation
// 0 0 0 | Y = A - 1;
// 0 0 1 | Y = A;
// 0 1 0 | Y = A - B - 1;
// 0 1 1 | Y = A - B;
// 1 0 0 | Y = A;
// 1 0 1 | Y = A + 1;
// 1 1 0 | Y = A + B;
// 1 1 1 | Y = A + B + 1;
//
//------------------------------------------------------------
myAddSub Add1(.A(A),.B(B),.CI(C),.ADD(OP[0]),.BOP(OP[1]),.Y(ArithUnit),.CO(carryout),.OVF(ovf));
//---------------------------------------------
// Logic Unit
// OP[1] OP[0] | operation
// 0 0 | Y = A and B
// 0 1 | Y = A or B
// 1 0 | Y = A xor B
// 1 1 | Y = Not A
//---------------------------------------------
always @ (A or B or OP[1:0])
begin
case (OP[1:0])
2'b00:LogicUnit = A & B;
2'b01:LogicUnit = A | B;
2'b10:LogicUnit = A ^ B;
2'b11:LogicUnit = !A;
default:LogicUnit = 8'bx;
endcase
end
//----------------------------------------------
// Select between logic and arithmatic
// OP[2] | operation
// 0 | Arithmetic operation
// 1 | Logical Operation
//----------------------------------------------
always @ (OP[2] or LogicUnit or ArithUnit)
begin
if(OP[2])
AluNoShift = LogicUnit;
else
AluNoShift = ArithUnit[7:0];
end
//-----------------------------------------------
// Shift operations
//
// OP[3] OP[4] OP[5] | operation
// 0 0 0 | NOP
// 1 0 0 | Shift Left (ASL)
// 0 1 0 | Arithmentic Shift Right (ASR..new)
// 1 1 0 | Logical Shift Right (LSR)
// 0 0 1 | Rotate Left (ROL)
// 1 0 1 | Rotate Right (ROR)
// 0 1 1 | NOP
// 1 1 1 | NOP
//-----------------------------------------------
always @ (OP[5:3] or AluNoShift or C)
begin
case(OP[5:3])
3'b000: begin
Y = AluNoShift; //do not shift output
shiftout = 0;
end
3'b001: begin
Y = {AluNoShift[6:0],1'b0}; //ASL
shiftout = AluNoShift[7];
end
3'b010: begin
Y = {AluNoShift[7],AluNoShift[7:1]}; //ASR
shiftout = AluNoShift[0];
end
3'b011: begin
Y = {1'b0,AluNoShift[7:1]}; //LSR
shiftout = AluNoShift[0];
end
3'b100: begin
Y = {AluNoShift[6:0],C};
shiftout = AluNoShift[7];
end
3'b101: begin
Y = {C,AluNoShift[7:1]}; //LSR
shiftout = AluNoShift[0];
end
3'b110: begin
Y = AluNoShift; //do not shift output
shiftout = 0;
end
3'b111: begin
Y = AluNoShift; //do not shift output
shiftout = 0;
end
default: begin
Y = 8'bx;
shiftout = 0;
end
endcase
end
//-----------------------------------------------------------
// Generate the status bits for the status registers
//
//-----------------------------------------------------------
always @(Y)
begin
if(!Y[0] & !Y[1] & !Y[2] & !Y[3] & !Y[4] & !Y[5] & !Y[6] & !Y[7])
Zero = 1;
else
Zero = 0;
end
always @ (Y[7])
Neg = Y[7];
//-----------------------------------------------------------
// Carry Status Register
// OP[6] OP[7] OP[8] | operation
// 0 0 0 | NOP
// 0 0 1 | Carry <- Adder/Sub Carry/Borrow
// 1 0 1 | Carry <- Shifter Out
// 0 1 1 | Carry <- 0
// 1 1 1 | Carry <- 1
//-----------------------------------------------------------
status CARRY1(.clk(CLK),.reset(RESET),.load(OP[8]),.a(carryout),.b(shiftout),.c(1'b0),.d(1'b1),.sel(OP[7:6]),.s(C));
//-----------------------------------------------------------
// Overflow status register
// OP[9] OP[10] OP[11] | operation
// 0 0 0 | NOP
// 0 0 1 | Overflow <- Adder/Sub Overflow
// 1 0 1 | Overflow <- External
// 0 1 1 | Overflow <- 0
// 1 1 1 | Overflow <- 1
//-----------------------------------------------------------
status OVF1(.clk(CLK),.reset(RESET),.load(OP[11]),.a(ovf),.b(Y[6]),.c(1'b0),.d(1'b1),.sel(OP[10:9]),.s(V));
//-----------------------------------------------------------
// Zero Status Register
// OP[12] OP[13] | operation
// 0 0 | NOP
// 1 0 | Zero <- Zero Input1
// 0 1 | Zero <- Zero Input2
// 1 1 | Zero <- 0
//-----------------------------------------------------------
status ZERO1(.clk(CLK),.reset(RESET),.load(1'b1),.a(Z),.b(Zero),.c(1'b1),.d(1'b0),.sel(OP[13:12]),.s(Z));
//-----------------------------------------------------------
// Negative Status Register
// OP[14] OP[15] | operation
// 0 0 | NOP
// 1 0 | Neg <- Neg Input1
// 0 1 | Neg <- Neg Input2
// 1 1 | Neg <- 0
//-----------------------------------------------------------
status NEG1(.clk(CLK),.reset(RESET),.load(1'b1),.a(N),.b(Neg),.c(1'b1),.d(1'b0),.sel(OP[15:14]),.s(N));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_LP_V
`define SKY130_FD_SC_LP__OR2_LP_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_lp (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_lp (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_LP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m, rb, cb, rd, cd; int count = 0; cin >> n >> m >> rb >> cb >> rd >> cd; if (rb <= rd && cb <= cd) cout << min(rd - rb, cd - cb) << endl; else if (rb <= rd && cb > cd) cout << min(rd - rb, 2 * m - cb - cd) << endl; else if (cb <= cd && rb > rd) cout << min(cd - cb, 2 * n - rb - rd) << endl; else cout << min(2 * n - rb - rd, 2 * m - cb - cd) << endl; } return 0; }
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : ram_2p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Dual Port Ram Model
//
// $Id$
//-------------------------------------------------------------------
module ram_lcu_row_32x64 (
clka ,
cena_i ,
oena_i ,
wena_i ,
addra_i ,
dataa_o ,
dataa_i ,
clkb ,
cenb_i ,
oenb_i ,
wenb_i ,
addrb_i ,
datab_o ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width=32;
parameter Addr_Width=6;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka; // clock input
input cena_i; // chip enable, low active
input oena_i; // data output enable, low active
input wena_i; // write enable, low active
input [Addr_Width-1:0] addra_i; // address input
input [Word_Width-1:0] dataa_i; // data input
output [Word_Width-1:0] dataa_o; // data output
// B Port
input clkb; // clock input
input cenb_i; // chip enable, low active
input oenb_i; // data output enable, low active
input wenb_i; // write enable, low active
input [Addr_Width-1:0] addrb_i; // address input
input [Word_Width-1:0] datab_i; // data input
output [Word_Width-1:0] datab_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] dataa_r;
reg [Word_Width-1:0] datab_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
always @(posedge clka) begin
if(!cena_i && !wena_i)
mem_array[addra_i] <= dataa_i;
end
always @(posedge clka) begin
if (!cena_i && wena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = oena_i ? 'bz : dataa_r;
// -- B Port --//
always @(posedge clkb) begin
if(!cenb_i && !wenb_i)
mem_array[addrb_i] <= datab_i;
end
always @(posedge clkb) begin
if (!cenb_i && wenb_i)
datab_r <= mem_array[addrb_i];
else
datab_r <= 'bx;
end
assign datab_o = oenb_i ? 'bz : datab_r;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int mas[105] = {0}; int n; scanf( %d , &n); int res = -1; int resl = -1; for (int i = 0; i < n; i++) scanf( %d , &mas[i]); for (int i = 0; i < n; i++) { int len = 0; int mest = 0; for (int j = i; j < n; j++) { len++; mest ^= mas[j]; if (mest > res) { res = mest; resl = len; } } } cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> graf[300007]; struct zap { long long zmiana; long long gle; }; vector<zap> z[300007]; int ojc[300007]; long long liczba[300007]; map<long long, long long> zmiany; void licz(int poz, int pop, long long zmiana, long long gl) { for (int i = 0; i < z[poz].size(); i++) { zmiana += z[poz][i].zmiana; zmiany[gl + z[poz][i].gle] += z[poz][i].zmiana; } liczba[poz] = zmiana; zmiana -= zmiany[gl]; for (int i = 0; i < graf[poz].size(); i++) { if (graf[poz][i] != pop) { licz(graf[poz][i], poz, zmiana, gl + 1); } } for (int i = 0; i < z[poz].size(); i++) { zmiany[gl + z[poz][i].gle] -= z[poz][i].zmiana; } } int main() { ios_base::sync_with_stdio(0); int n, m; cin >> n; int a, b; for (int i = 1; i < n; i++) { cin >> a >> b; graf[a].push_back(b); graf[b].push_back(a); } cin >> m; for (int i = 0; i < m; i++) { cin >> a; long long dl, ile; cin >> dl >> ile; zap x; x.zmiana = ile; x.gle = dl; z[a].push_back(x); } licz(1, -1, 0, 0); for (int i = 1; i <= n; i++) cout << liczba[i] << ; }
|
`timescale 1ns / 1ps
/*
* Spartan3AN_PicoBlaze_LCD.v
*
* ___ _ _ _ _ ___ _ _ ___
* | __._ _ _| |_ ___ _| |_| |___ _| | . | \ |_ _|
* | _>| ' ' | . / ._/ . / . / ._/ . | | || |
* |___|_|_|_|___\___\___\___\___\___|_|_|_\_||_|
*
*
* Created on : 20/07/2015
* Author : Ernesto Andres Rincon Cruz
* Web : www.embeddedant.org
* Device : XC3S700AN - 4FGG484
* Board : Spartan-3AN Starter Kit.
*
* Revision History:
* Rev 1.0.0 - (ErnestoARC) First release 19/06/2015.
*/
//////////////////////////////////////////////////////////////////////////////////
module Spartan3AN_PicoBlaze_LCD(
//////////// CLOCK //////////
CLK_50M,
//////////// LCD //////////
LCD_DB,
LCD_E,
LCD_RS,
LCD_RW
);
//=======================================================
// PARAMETER declarations
//=======================================================
parameter LCD_PORT_ID = 8'h00;
//=======================================================
// PORT declarations
//=======================================================
input wire CLK_50M;
output wire [7:0] LCD_DB;
output wire LCD_E;
output wire LCD_RS;
output wire LCD_RW;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire [7:0] Lcd_Port;
//=======================================================
// Structural coding
//=======================================================
//******************************************************************//
// Instantiate PicoBlaze and the Program ROM. //
//******************************************************************//
wire [9:0] address;
wire [17:0] instruction;
wire [7:0] port_id;
wire [7:0] out_port;
wire [7:0] in_port;
wire write_strobe;
wire read_strobe;
wire interrupt;
wire reset;
kcpsm3 kcpsm3_inst (
.address(address),
.instruction(instruction),
.port_id(port_id),
.write_strobe(write_strobe),
.out_port(out_port),
.read_strobe(read_strobe),
.in_port(in_port),
.interrupt(interrupt),
.interrupt_ack(),
.reset(reset),
.clk(CLK_50M));
picocode picocode_inst (
.address(address),
.instruction(instruction),
.clk(CLK_50M));
PicoBlaze_OutReg #(.LOCAL_PORT_ID(LCD_PORT_ID)) Lcd_Port_inst(
.clk(CLK_50M),
.reset(reset),
.port_id(port_id),
.write_strobe(write_strobe),
.out_port(out_port),
.new_out_port(Lcd_Port));
//=======================================================
// Connections & assigns
//=======================================================
//******************************************************************//
// Input PicoBlaze Interface. //
//******************************************************************//
assign in_port = 8'h00;
assign interrupt = 1'b0;
assign reset = 1'b0;
//******************************************************************//
// Output PicoBlaze Interface. //
//******************************************************************//
assign LCD_E=Lcd_Port[0];
assign LCD_RW=Lcd_Port[1];
assign LCD_RS=Lcd_Port[2];
assign LCD_DB={Lcd_Port[7:4],4'bzzzz};
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100000]; int b[100000]; bool judge(long long x, int n, long long k) { for (int i = 0; i < n; ++i) { k -= max(0LL, a[i] * x - b[i]); if (k < 0) { return false; } } return true; } int main(void) { int n, k; assert(scanf( %d%d , &n, &k) == 2); for (int i = 0; i < n; ++i) { assert(scanf( %d , &a[i]) == 1); } for (int i = 0; i < n; ++i) { assert(scanf( %d , &b[i]) == 1); } long long l = 0, r = 2000000001; while (r - l > 1) { long long m = (l + r) / 2; if (judge(m, n, k)) { l = m; } else { r = m; } } printf( %I64d n , l); return 0; }
|
#include <bits/stdc++.h> using namespace std; int N; long long shu[200010]; int main() { while (scanf( %d , &N) != EOF) { for (int i = 1; i <= N * 2; i++) { scanf( %I64d , &shu[i]); } sort(shu + 1, shu + 1 + 2 * N); long long ans = (shu[N] - shu[1]) * (shu[2 * N] - shu[N + 1]); for (int i = 2; i <= N; i++) { ans = min(ans, (shu[i + N - 1] - shu[i]) * (shu[2 * N] - shu[1])); } printf( %I64d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; map<int, vector<int> > m; int main() { int n, k, query; scanf( %d %d , &n, &k); for (int i = 0; i < (int)(k); i++) { scanf( %d , &query); m[query - 1].push_back(i); } int ans = 0; std::vector<int>::iterator low; for (int i = 0; i < (int)(n); i++) { if (m[i].size() == 0) { ans += 3; if (i == 0 || i == n - 1) ans--; } else { if (i - 1 >= 0) { low = lower_bound(m[i - 1].begin(), m[i - 1].end(), m[i][0]); if (low == m[i - 1].end() || m[i - 1].size() == 0) { ans++; } } if (i + 1 < n) { low = lower_bound(m[i + 1].begin(), m[i + 1].end(), m[i][0]); if (low == m[i + 1].end() || m[i + 1].size() == 0) ans++; } } } printf( %d n , ans); return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 16:06:27 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_internoc_ni_axi_master_0_0/DemoInterconnect_internoc_ni_axi_master_0_0_stub.v
// Design : DemoInterconnect_internoc_ni_axi_master_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "internoc_ni_axi_master_v1_0,Vivado 2017.3" *)
module DemoInterconnect_internoc_ni_axi_master_0_0(if00_data_in, if00_load_in, if00_data_out,
if00_load_out, if00_send_done, if00_send_busy, m00_axi_awaddr, m00_axi_awprot,
m00_axi_awvalid, m00_axi_awready, m00_axi_wdata, m00_axi_wstrb, m00_axi_wvalid,
m00_axi_wready, m00_axi_bresp, m00_axi_bvalid, m00_axi_bready, m00_axi_araddr,
m00_axi_arprot, m00_axi_arvalid, m00_axi_arready, m00_axi_rdata, m00_axi_rresp,
m00_axi_rvalid, m00_axi_rready, m00_axi_aclk, m00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="if00_data_in[7:0],if00_load_in,if00_data_out[7:0],if00_load_out,if00_send_done,if00_send_busy,m00_axi_awaddr[31:0],m00_axi_awprot[2:0],m00_axi_awvalid,m00_axi_awready,m00_axi_wdata[31:0],m00_axi_wstrb[3:0],m00_axi_wvalid,m00_axi_wready,m00_axi_bresp[1:0],m00_axi_bvalid,m00_axi_bready,m00_axi_araddr[31:0],m00_axi_arprot[2:0],m00_axi_arvalid,m00_axi_arready,m00_axi_rdata[31:0],m00_axi_rresp[1:0],m00_axi_rvalid,m00_axi_rready,m00_axi_aclk,m00_axi_aresetn" */;
input [7:0]if00_data_in;
input if00_load_in;
output [7:0]if00_data_out;
output if00_load_out;
input if00_send_done;
input if00_send_busy;
output [31:0]m00_axi_awaddr;
output [2:0]m00_axi_awprot;
output m00_axi_awvalid;
input m00_axi_awready;
output [31:0]m00_axi_wdata;
output [3:0]m00_axi_wstrb;
output m00_axi_wvalid;
input m00_axi_wready;
input [1:0]m00_axi_bresp;
input m00_axi_bvalid;
output m00_axi_bready;
output [31:0]m00_axi_araddr;
output [2:0]m00_axi_arprot;
output m00_axi_arvalid;
input m00_axi_arready;
input [31:0]m00_axi_rdata;
input [1:0]m00_axi_rresp;
input m00_axi_rvalid;
output m00_axi_rready;
input m00_axi_aclk;
input m00_axi_aresetn;
endmodule
|
#include <bits/stdc++.h> long long gcd(long long a, long long b) { while (a && b) { if (a > b) a %= b; else b %= a; } return a + b; } long long lcm(long long a, long long b) { return (((a) / gcd(a, b))) * b; } int phi(int n) { int result = n; for (int i = 2; i * i <= n; i++) { if (n % i == 0) { while (n % i == 0) n /= i; result -= result / i; } } if (n > 1) result -= result / n; return result; } long long power(long long a, long long b, long long c) { long long r = 1; while (b) { if (b & 1) r *= a; a *= a; a %= c; r %= c; b /= 2; } return r; } void nxi(int& n) { bool min = 0; char c; n = 0; while ((c = getc(stdin)) && c <= 32) ; if (c == - ) min = 1; else n = c - 48; while ((c = getc(stdin)) && c > 32) n = (n << 3) + (n << 1) + c - 48; if (min) n = -n; } void prl(int n) { if (n == 0) { puts( 0 ); return; } static int s[10]; int top = 0; while (n > 0) s[top++] = n % 10, n /= 10; while (top--) putchar(s[top] + 48); } using namespace std; int n, m; pair<int, int> mem[101010]; map<long long, vector<long long> > sv; map<long long, long long> t; void inc(int pos, long long val) { for (long long i = pos; i < 1000000007; i = (i | (i + 1))) { t[i] += val, t[i] %= 1000000007; } } long long get(int r) { long long s = 0; for (long long i = r; i >= 0; i = (i & (i + 1)) - 1) { if (t.count(i)) { s += t[i]; s %= 1000000007; } } return s; } long long get(int l, int r) { long long x = (long long)get(r) - (l > 0 ? 1ll * get(l - 1) : 0); x = (x + 1000000007) % 1000000007; x = (x + 1000000007) % 1000000007; return x; } int main() { ios::sync_with_stdio(0); cin >> n >> m; for (int i = 0; i < m; i++) { cin >> mem[i].first >> mem[i].second; int x = mem[i].second; sv[x].push_back(mem[i].first); } inc(0, 1); for (map<long long, vector<long long> >::iterator it = sv.begin(); it != sv.end(); it++) { long long s = 0; int x = it->first; for (int i = 0; i < it->second.size(); i++) { s += get(it->second[i], x - 1); s %= 1000000007; s = (s + 1000000007) % 1000000007; s = (s + 1000000007) % 1000000007; } inc(x, s); } cout << get(n, n) << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSBP_TB_V
`define SKY130_FD_SC_HD__DFSBP_TB_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfsbp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__dfsbp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A31OI_PP_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31OI_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
`define clkperiodby2 10
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/09/2015 12:23:19 PM
// Design Name:
// Module Name: tb_MMUI
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "params.vh"
module tb_MMUI #(
parameter N = `MAT_SIZE,
parameter WIDTH = `DATA_WIDTH,
parameter M_WIDTH = 2*WIDTH+N-1,
parameter ADDR = `CLOG2(N)
);
//inputs
reg clk;
reg start;
reg A_USR_wr;
reg B_USR_wr;
reg C_USR_rd;
reg [ADDR-1:0] A_USR_addr;
reg [ADDR-1:0] B_USR_addr;
reg [ADDR-1:0] C_USR_addr;
reg [N*WIDTH-1:0] A_USR_din;
reg [N*WIDTH-1:0] B_USR_din;
wire [N-1:0] valid;
wire [N*M_WIDTH-1:0] C_USR_dout;
wire [N*WIDTH-1:0] A;
wire [WIDTH-1:0] B;
wire [N*M_WIDTH-1:0] C;
wire A_MAT_rd;
wire B_MAT_rd;
wire C_MAT_wr;
wire [ADDR-1:0] A_MAT_addr;
wire [ADDR-1:0] B_MAT_addr;
wire [ADDR-1:0] C_MAT_addr;
wire [N*WIDTH-1:0] A_MAT_dout;
wire [N*WIDTH-1:0] B_MAT_dout;;
wire [N*M_WIDTH-1:0] C_MAT_din;
//////////////////////////////////////////////////////////////////////////
multi_MAC_Base MAC_Base (
.clk (clk),
.sof (sof),
.A (A),
.B (B),
.C (C),
.valid (valid)
);
defparam MAC_Base.N = N;
defparam MAC_Base.WIDTH = WIDTH;
defparam MAC_Base.M_WIDTH = M_WIDTH;
DMA_Controller DMAC (
.clk (clk),
.start (start),
// MATRIX MEMORY A
.A_rd (),
.A_addr (A_MAT_addr),
.A_dout (A_MAT_dout),
// MATRIX MEMORY B
.B_rd (),
.B_addr (B_MAT_addr),
.B_dout (B_MAT_dout),
// MATRIX MEMORY C
.C_wr (C_MAT_wr),
.C_addr (C_MAT_addr),
.C_din (C_MAT_din),
// MAC BASE INTERFACE
.sof (sof),
.A (A),
.B (B),
.C (C),
.valid (valid)
);
defparam DMAC.N = N;
defparam DMAC.WIDTH = WIDTH;
defparam DMAC.ADDR = ADDR;
defparam DMAC.M_WIDTH = M_WIDTH;
BRAM_Matrix Memory(
.clk_USR (clk),
.clk_MAT (clk),
// USER MEMORY A
.A_USR_wr (A_USR_wr),
.A_USR_addr (A_USR_addr),
.A_USR_din (A_USR_din),
// USER MEMORY B
.B_USR_wr (B_USR_wr),
.B_USR_addr (B_USR_addr),
.B_USR_din (B_USR_din),
// USER MEMORY C
.C_USR_rd (C_USR_rd),
.C_USR_addr (C_USR_addr),
.C_USR_dout (C_USR_dout),
// MATRIX MEMORY A
.A_MAT_rd (),
.A_MAT_addr (A_MAT_addr),
.A_MAT_dout (A_MAT_dout),
// MATRIX MEMORY B
.B_MAT_rd (),
.B_MAT_addr (B_MAT_addr),
.B_MAT_dout (B_MAT_dout),
// MATRIX MEMORY C
.C_MAT_wr (C_MAT_wr),
.C_MAT_addr (C_MAT_addr),
.C_MAT_din (C_MAT_din)
);
defparam Memory.N = N;
defparam Memory.WIDTH = WIDTH;
defparam Memory.M_WIDTH = M_WIDTH;
defparam Memory.ADDR = ADDR;
//////////////////////////////////////////////////////////////////////////
initial begin
// Initialize Inputs
clk = 0;
start = 0;
#310
writemem(1);
#10000
$stop;
end
//////////////////////////////////////////////////////////////////////////
task writemem;
input strt;
reg [8:0] i;
begin
if(strt) begin
@ (posedge clk);
for(i = 0; i < N; i = i+1) begin
@ (posedge clk);
A_USR_wr = 1'b1;
A_USR_addr = i;
A_USR_din = 96'h000600050004000300020001;//(3*(i+1) << (i+5)*16) || (2*(i+1) << (i+4)*16) || (4*(i+1) << (i+3)*16) || (3*(i+1) << (i+2)*16) || (2*(i+1) << (i+1)*16) || ((i+1) << i*16);
B_USR_wr = 1'b1;
B_USR_addr = i;
B_USR_din = 96'h000600050004000300020001;//(3*(i+1) << (i+5)*16) || (2*(i+1) << (i+4)*16) || (4*(i+1) << (i+3)*16) || (3*(i+1) << (i+2)*16) || (2*(i+1) << (i+1)*16) || ((i+1) << i*16) ;
// @ (posedge clk);
end
end
start = 1'b1;
@ (posedge clk);
@ (posedge clk);
@ (posedge clk);
start = 1'b0;
end
endtask
always
#`clkperiodby2 clk <= ~clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR4BB_PP_BLACKBOX_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e4 + 10; const int maxk = 2e4 + 10; const int inf = 0x3f3f3f3f; int n, m, k; bool g[maxn][maxn]; struct Block { int l, r, b, t; }; Block b[maxk]; int bnum; bool vis[maxk]; int d[maxk]; int res; int start, stop; void bfs() { memset(d, 0, sizeof d); res = inf; queue<int> q; q.push(start); while (q.size()) { int u = q.front(); q.pop(); vis[u] = true; if (u == stop) { res = min(d[u], res); continue; } else if (b[u].b >= n - 1 || b[u].r >= m - 1) { res = min(d[u] + 1, res); continue; } for (int i = 0; i < bnum; i++) { if (vis[i]) continue; if (b[u].t > b[i].b + 2 && (b[u].l > b[i].r + 2 || b[u].r < b[i].l - 2)) continue; if (b[u].b < b[i].t - 2 && (b[u].l > b[i].r + 2 || b[u].r < b[i].l - 2)) continue; vis[i] = true; d[i] = d[u] + 1; q.push(i); } } } bool dvis[maxn][maxn]; void dfs(int r, int c, int bnum) { if (dvis[r][c]) return; if (r == 1 && c == 1) start = bnum; if (r == n && c == m) stop = bnum; dvis[r][c] = 1; b[bnum].l = min(b[bnum].l, c); b[bnum].r = max(b[bnum].r, c); b[bnum].b = max(b[bnum].b, r); b[bnum].t = min(b[bnum].t, r); if (r > 1 && g[r - 1][c]) dfs(r - 1, c, bnum); if (r < n && g[r + 1][c]) dfs(r + 1, c, bnum); if (c > 1 && g[r][c - 1]) dfs(r, c - 1, bnum); if (c < m && g[r][c + 1]) dfs(r, c + 1, bnum); } int main() { memset(g, 0, sizeof g); scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < k; i++) { int r, c; scanf( %d%d , &r, &c); g[r][c] = 1; } bnum = 0; start = stop = -1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (g[i][j] && !dvis[i][j]) { b[bnum].r = b[bnum].l = j; b[bnum].b = b[bnum].t = i; dfs(i, j, bnum); bnum++; } } } bfs(); if (res < inf) printf( %d n , res); else printf( -1 n ); }
|
#include <bits/stdc++.h> using namespace std; const int N=2e5+7; int n; int x=-1,y=-1,z=-1; int a[N], t[N*4]; vector<int> suff(N), pref(N); void build(int v=1, int tl=1, int tr=n){ if(tl==tr) t[v]=a[tl]; else { int tm = (tl+tr)/ 2; build(v*2, tl, tm); build(v*2+1,tm+1,tr); t[v]=min(t[v*2], t[v*2+1]); } } int get(int v, int tl, int tr, int l, int r){ if(l<=tl and tr<=r) return t[v]; if(r < tl || tr< l) return INT_MAX; int tm=(tl + tr)>>1; return min(get(v*2, tl, tm, l, r), get(v*2+1, tm+1,tr,l,r)); } void calc(){ pref[1]=a[1]; for(int i=2;i<=n;i++) pref[i]=max(pref[i-1], a[i]); suff[n]=a[n]; for(int i=n-1;i>=1;i--) suff[i]=max(suff[i+1], a[i]); } int main(){ ios_base::sync_with_stdio(false); cin.tie(0); int tt; cin>>tt; while(tt--){ cin>>n; for(int i = 1; i <= n; i++) cin>>a[i]; build(); calc(); bool flag=false; int x, y, z; for(int i=n;i>=3;i--){ int value = suff[i]; auto j1 = lower_bound(pref.begin(), pref.begin()+i-1, value); int start = j1 - pref.begin(); auto j2 = upper_bound(pref.begin(), pref.begin()+i-1, value); int end = j2 - pref.begin(); //cout<<start<< <<end<< ; if(start >= end) continue; int low= start, high=end; while(high - low > 1) { int mid = (low + high) / 2; if (get(1,1,n,mid, i-1)<value) { low=mid; } else { high=mid; } } //cout<< << high << n ; if (high < i and get(1,1,n,high,i-1) == value and pref[high-1] == value) { x = high-1; y = i-high; z = n-i+1; flag=true; } } if(!flag) cout<< NO n ; else cout<< YES n <<x<< << y << << z << n ; } }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $
//
// $Date: 2004/02/18 11:40:46 $
// $Revision: 1.7 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_byte_ctrl.v,v $
// Revision 1.7 2004/02/18 11:40:46 rherveille
// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
//
// Revision 1.6 2003/08/09 07:01:33 rherveille
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
// Fixed a potential bug in the byte controller's host-acknowledge generation.
//
// Revision 1.5 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.4 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.3 2001/11/05 11:59:25 rherveille
// Fixed wb_ack_o generation bug.
// Fixed bug in the byte_controller statemachine.
// Added headers.
//
// synopsys translate_off
//rsf `include "timescale.v"
// synopsys translate_on
//rsf `include "i2c_master_defines.v"
// I2C registers wishbone addresses
// bitcontroller states
`define I2C_CMD_NOP 4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP 4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ 4'b1000
module i2c_master_byte_ctrl (
clk, rst, ena, clk_cnt, start, stop, read, write, ack_in, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
//
// inputs & outputs
//
input clk; // master clock
input rst; // synchronous active high reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
//
// Variable declarations
//
// statemachine
parameter [4:0] ST_IDLE = 5'b0_0000;
parameter [4:0] ST_START = 5'b0_0001;
parameter [4:0] ST_READ = 5'b0_0010;
parameter [4:0] ST_WRITE = 5'b0_0100;
parameter [4:0] ST_ACK = 5'b0_1000;
parameter [4:0] ST_STOP = 5'b1_0000;
// signals for bit_controller
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.rst ( rst ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk)
if (rst)
sr <= #1 8'h0;
else if (ld)
sr <= #1 din;
else if (shift)
sr <= #1 {sr[6:0], core_rxd};
// generate counter
always @(posedge clk)
if (rst)
dcnt <= #1 3'h0;
else if (ld)
dcnt <= #1 3'h7;
else if (shift)
dcnt <= #1 dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [4:0] c_state; // synopsis enum_state
always @(posedge clk)
if (rst | i2c_al)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
ld <= #1 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
ld <= #1 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= #1 core_rxd;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 333; const long long linf = 1e18 + inf; const int LEN = 6e5 + 5; int n, m, q, len; char str[LEN], s[LEN]; int a[LEN], st[LEN], nd[LEN], suf[LEN], ord[LEN], lcp[LEN], w[LEN], root[LEN], L[LEN], R[LEN]; pair<pair<int, int>, int> C[LEN]; long long cnt[LEN]; void add(int x, char str[]) { int m = strlen(str); s[++len] = # ; st[x] = len + 1; for (int i = 0; i < m; i++) s[++len] = str[i]; nd[x] = len; } int f(int x) { if (x == root[x]) return x; return root[x] = f(root[x]); } void merge(int x, int y) { x = f(x); y = f(y); if (x == y) return; root[y] = x; cnt[x] += cnt[y]; L[x] = min(L[x], L[y]); R[x] = max(R[x], R[y]); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , str); add(i, str); } for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= len; i++) suf[i] = s[i]; for (int it = 1; it < len; it *= 2) { for (int j = 1; j <= len; j++) { C[j] = make_pair(pair<int, int>(suf[j], suf[min(j + it, len + 1)]), j); } sort(C + 1, C + len + 1); for (int j = 1; j <= len; j++) { suf[C[j].second] = suf[C[j - 1].second] + (C[j].first != C[j - 1].first); } } for (int i = 1; i <= len; i++) ord[suf[i]] = i; for (int i = 1; i <= len; i++) { } int j = 0; for (int i = 1; i <= len; i++) { if (suf[i] == 1) continue; while (i + j <= len and ord[suf[i] - 1] + j <= len and s[i + j] == s[ord[suf[i] - 1] + j] and s[i + j] != # ) j++; lcp[suf[i]] = j; if (j) j--; } for (int i = 1; i <= len; i++) { assert(s[ord[i] + lcp[i]] != s[ord[i - 1] + lcp[i]] or s[ord[i] + lcp[i]] == # ); } for (int i = 1; i <= len; i++) { } memset(w, -1, sizeof(w)); for (int i = 1; i <= n; i++) { for (int j = st[i]; j <= nd[i]; j++) { w[suf[j]] = i; } } for (int i = 1; i <= len; i++) { if (w[i] != -1) cnt[i] = a[w[i]]; L[i] = R[i] = root[i] = i; } vector<pair<int, int> > vs; for (int i = 1; i <= len; i++) { vs.push_back(pair<int, int>(lcp[i], i)); } sort(vs.begin(), vs.end()); long long ans = 0; for (int i = 1; i <= n; i++) { int x = suf[st[i]]; if (nd[i] - st[i] + 1 > lcp[x] and nd[i] - st[i] + 1 > lcp[x + 1]) { ans = max(ans, (long long)a[i] * (nd[i] - st[i] + 1)); } } for (int it = len - 1; it >= 0; it--) { int l = vs[it].first, x = vs[it].second; merge(x, x - 1); x = f(x); if (lcp[L[x]] < l and lcp[R[x] + 1] < l) ans = max(ans, cnt[f(x)] * l); } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int ucln(int a, int b) { int r; while (b > 0) { r = a % b; a = b; b = r; } return a; } int main() { int x, y, a, b, bc; cin >> x >> y >> a >> b; bc = x * y / ucln(x, y); int l = a, r = b; while (l % bc != 0) l++; while (r % bc != 0) r--; cout << (r - l) / bc + 1; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 1e5 + 50; const int inf = 1e8 + 10; int l[maxn], e[maxn]; int bs(int a[], int x, int n) { int l = 0, r = n; int m; while (l < r) { m = (l + r) / 2; if (a[m] >= x) r = m; else l = m + 1; } return l; } int get_dis(int x1, int x2, int t) { return abs(x1 - t) + abs(x2 - t); } int main() { int n, m; int cl, ce; int v; cin >> n >> m >> cl >> ce >> v; l[0] = e[0] = -inf; for (int i = 1; i <= cl; ++i) scanf( %d , &l[i]); for (int i = 1; i <= ce; ++i) scanf( %d , &e[i]); l[cl + 1] = e[ce + 1] = inf * 2; int q; scanf( %d , &q); while (q--) { int x1, x2, y1, y2; scanf( %d %d %d %d , &y1, &x1, &y2, &x2); int dy = abs(y1 - y2); if (!dy) { printf( %d n , abs(x1 - x2)); continue; } int ans = inf * 4; int a = bs(l, x1, cl + 2); ans = min(ans, dy + min(get_dis(x1, x2, l[a]), get_dis(x1, x2, l[a - 1]))); a = bs(l, x2, cl + 2); ans = min(ans, dy + min(get_dis(x1, x2, l[a]), get_dis(x1, x2, l[a - 1]))); int b = bs(e, x1, ce + 2); ans = min(ans, (dy + v - 1) / v + min(get_dis(x1, x2, e[b]), get_dis(x1, x2, e[b - 1]))); b = bs(e, x2, ce + 2); ans = min(ans, (dy + v - 1) / v + min(get_dis(x1, x2, e[b]), get_dis(x1, x2, e[b - 1]))); printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int tt = 120; int test[6] = {0, 1, 3, 5, 2, 4}; int n = 5; int p[2001], s[2001]; int p_l[2001], s_l[2001]; int ans = 0; vector<pair<int, int> > v_ans; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &p[i]); p_l[p[i]] = i; } for (int i = 1; i <= n; i++) s[i] = i; for (int i = 1; i <= n; i++) { scanf( %d , &s[i]); s_l[s[i]] = i; } for (int i = 1; i <= n; i++) { if (p[i] != s[i]) { int r = p_l[s[i]]; for (int j = i; j <= r; j++) { int pos_j = s_l[p[j]]; int pos_r = s_l[p[r]]; if ((pos_j >= r && pos_r <= j && pos_j != pos_r)) { ans += abs(j - r); v_ans.push_back(make_pair(j, r)); swap(p[j], p[r]); swap(p_l[p[j]], p_l[p[r]]); r = j; j = i - 1; } } } } printf( %d n%d n , ans, v_ans.size()); for (int i = 0; i < v_ans.size(); i++) printf( %d %d n , v_ans[i].first, v_ans[i].second); return 0; }
|
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: counter_bus_mux.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module counter_bus_mux (
data0x,
data1x,
sel,
result);
input [3:0] data0x;
input [3:0] data1x;
input sel;
output [3:0] result;
wire [3:0] sub_wire5;
wire [3:0] sub_wire2 = data1x[3:0];
wire [3:0] sub_wire0 = data0x[3:0];
wire [7:0] sub_wire1 = {sub_wire2, sub_wire0};
wire sub_wire3 = sel;
wire sub_wire4 = sub_wire3;
wire [3:0] result = sub_wire5[3:0];
lpm_mux LPM_MUX_component (
.data (sub_wire1),
.sel (sub_wire4),
.result (sub_wire5)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_size = 2,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 4,
LPM_MUX_component.lpm_widths = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
// Retrieval info: USED_PORT: data0x 0 0 4 0 INPUT NODEFVAL "data0x[3..0]"
// Retrieval info: USED_PORT: data1x 0 0 4 0 INPUT NODEFVAL "data1x[3..0]"
// Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]"
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
// Retrieval info: CONNECT: @data 0 0 4 0 data0x 0 0 4 0
// Retrieval info: CONNECT: @data 0 0 4 4 data1x 0 0 4 0
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
// Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
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#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } bool isPrime(long long n) { long long c; if (n <= 1) return false; c = sqrt(n); for (int i = 2; i <= c; i++) if (n % i == 0) return false; return true; } int D(long long n) { int count = 0; while (n != 0) { n = n / 10; ++count; } return count; } const long long N = 2e5 + 7; long long l, k, d, tr, n, m, sum, mini, maxi, a, b, c, x, y; long long t[5007]; set<int> vis; vector<int> v; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); for (cin >> tr; tr--;) { cin >> n; mini = 0; cin >> t[0]; for (int i = 1; i < n; i++) { cin >> t[i]; if (t[i] != t[i - 1]) { a = i; c = t[i]; b = i - 1; mini++; } } if (mini) { cout << YES << endl; for (int i = 0; i < n; i++) { if (i != a) { if (t[i] != c) { cout << i + 1 << << a + 1 << endl; } else { cout << i + 1 << << b + 1 << endl; } } } } else { cout << NO << endl; } } }
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#include <bits/stdc++.h> using namespace std; int sum[705][705], a[500100]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int q, t, x, y; memset(sum, 0, sizeof(sum)); cin >> q; while (q--) { cin >> t >> x >> y; if (t == 1) { a[x] += y; for (int i = 1; i < 705; ++i) { sum[i][x % i] += y; } } else { if (x < 705) { cout << sum[x][y] << endl; } else { int ans = 0; for (int i = y; i < 500100; i += x) ans += a[i]; cout << ans << endl; } } } return 0; }
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#include <bits/stdc++.h> using namespace std; bool check(long n, long k) { long dem = 0; while (n > 0) { long x = n % 10; n /= 10; (x == 4 || x == 7) ? dem++ : dem = dem; } if (dem <= k) return 1; return 0; } int main() { long n, k, dem = 0; cin >> n >> k; long a[n]; for (long i = 0; i < n; i++) { cin >> a[i]; if (check(a[i], k) == 1) dem++; } cout << dem; }
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#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const int maxn = 5555; int s[maxn]; int main(int argc, char const *argv[]) { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = 1; i <= n; ++i) { int t; cin >> t; s[i] = s[i - 1] + t; } int res = 0; for (int i = 1; i <= n; ++i) { for (int j = i; j <= n; ++j) { int sum = s[j] - s[i - 1]; int t = j - i + 1; if (sum > t * 100 && t > res) res = t; } } cout << res << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { bool check = false; int left, right; cin >> left >> right; for (int i = left; i <= right; i++) { int num = i; bool ch[10] = {false}; while (num > 0) { if (ch[num % 10]) break; ch[num % 10] = true; num /= 10; } if (num == 0) { cout << i; check = true; break; } } if (!check) cout << -1 ; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 100; const long long M = 21; const long long mod = 1e9 + 7; const long long MOD = 998244353; const long long P = 1336; const long double eps = 0.000000001; const long long inf = 1e16 + 7; mt19937 gen(chrono::high_resolution_clock::now().time_since_epoch().count()); vector<pair<long long, long long> > g[N], ng[N]; long long sz[N], pr[N], tin[N], tout[N]; long long tim = 0; pair<long long, long long> w[N][M]; long long r[N]; long long get(long long v) { if (pr[v] == v) return v; return pr[v] = get(pr[v]); } void unite(long long a, long long b) { a = get(a); b = get(b); if (a == b) return; if (sz[a] < sz[b]) swap(a, b); sz[a] += sz[b]; pr[b] = a; } void DFS(long long v, long long pr, long long zn) { w[v][0].first = pr; w[v][0].second = zn; for (long long i = 1; i < M; i++) { w[v][i].first = w[w[v][i - 1].first][i - 1].first; w[v][i].second = max(w[v][i - 1].second, w[w[v][i - 1].first][i - 1].second); } tim++; tin[v] = tim; for (auto to : ng[v]) { if (to.first == pr) continue; DFS(to.first, v, to.second); } tim++; tout[v] = tim; } bool upper(long long a, long long b) { return ((tin[a] <= tin[b]) && (tout[a] >= tout[b])); } long long LCA(long long a, long long b) { if (upper(b, a)) swap(a, b); long long mx = 0; for (long long i = M - 1; i >= 0; i--) { if (!upper(w[b][i].first, a)) { mx = max(mx, w[b][i].second); b = w[b][i].first; } } mx = max(mx, w[b][0].second); b = w[b][0].first; for (long long i = M - 1; i >= 0; i--) { if (!upper(w[a][i].first, b)) { mx = max(mx, w[a][i].second); a = w[a][i].first; } } if (a != b) mx = max(mx, w[a][0].second); return mx; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); srand(time(0)); long long n, m, k, T; cin >> n >> m >> k >> T; for (long long i = 0; i < m; i++) { long long x, y, z; cin >> x >> y >> z; x--; y--; g[x].push_back({y, z}); g[y].push_back({x, z}); } for (long long i = 0; i < n; i++) { r[i] = inf; } priority_queue<pair<long long, long long> > q; for (long long i = 0; i < k; i++) { q.push({0, i}); } while (!q.empty()) { long long v = q.top().second; long long ra = q.top().first; ra = -ra; q.pop(); if (ra > r[v]) continue; r[v] = ra; for (auto to : g[v]) { if (r[to.first] > r[v] + to.second) { r[to.first] = r[v] + to.second; q.push({-r[to.first], to.first}); } } } vector<pair<long long, pair<long long, long long> > > e; for (long long i = 0; i < n; i++) { for (auto to : g[i]) { e.push_back({r[i] + r[to.first] + to.second, {i, to.first}}); } } for (long long i = 0; i < n; i++) { pr[i] = i; sz[i] = 1; } sort(e.begin(), e.end()); for (auto to : e) { if (get(to.second.first) != get(to.second.second)) { unite(to.second.first, to.second.second); ng[to.second.first].push_back({to.second.second, to.first}); ng[to.second.second].push_back({to.second.first, to.first}); } } DFS(0, 0, 0); while (T--) { long long a, b; cin >> a >> b; a--; b--; cout << LCA(a, b) << n ; } }
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#include <bits/stdc++.h> using namespace std; template <class A, class B> ostream &operator<<(ostream &out, const pair<A, B> &a) { return out << ( << a.first << , << a.second << ) ; } template <class A> ostream &operator<<(ostream &out, const vector<A> &a) { for (const A &it : a) out << it << ; return out; } template <class A, class B> istream &operator>>(istream &in, pair<A, B> &a) { return in >> a.first >> a.second; } template <class A> istream &operator>>(istream &in, vector<A> &a) { for (A &i : a) in >> i; return in; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, x, y; cin >> n >> x >> y; string s; cin >> s; reverse((s).begin(), (s).end()); long long cnt = 0; for (long long i = 0; i < x; i++) { if ((i == x || i == y)) { cnt += s[i] == 0 ; } else cnt += s[i] == 1 ; } cout << cnt; }
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#include <bits/stdc++.h> using namespace std; int i, n, mx, mn, p1, p2, poz, poz1, poz2, k, mx1, mx2, m, mij, u, x, y, z, q; struct para { int x, y, z, ind; } a[100007]; int cmp(para k1, para k2) { if (k1.x > k2.x) return 0; else if (k1.x == k2.x) { if (k1.y > k2.y) return 0; else if (k1.y == k2.y) { if (k1.z > k2.z) return 0; else if (k1.z == k2.z) { return 0; } return 1; } return 1; } return 1; } int main() { scanf( %d , &n); mx = -1; for (i = 1; i <= n; i++) { scanf( %d%d%d , &a[i].x, &a[i].y, &a[i].z); a[i].ind = i; mn = a[i].x; if (mn > a[i].y) mn = a[i].y; if (mn > a[i].z) mn = a[i].z; if (mx < mn) { mx = mn; k = 1; poz = a[i].ind; } m = max(max(a[i].x, a[i].y), a[i].z); mij = a[i].x + a[i].y + a[i].z - m - mn; a[i].x = mn; a[i].y = mij; a[i].z = m; } sort(a + 1, a + n + 1, cmp); for (i = 1; i <= n; i++) { mx1 = -1; mx2 = -1; u = 0; while (a[i].x == a[i + 1].x && a[i].y == a[i + 1].y) { u = 1; if (mx1 < a[i].z) { mx2 = mx1; poz2 = poz1; mx1 = a[i].z; poz1 = a[i].ind; } else if (mx2 < a[i].z) { mx2 = a[i].z; poz2 = a[i].ind; } i++; } if (u == 1) { if (mx1 < a[i].z) { mx2 = mx1; poz2 = poz1; mx1 = a[i].z; poz1 = a[i].ind; } else if (mx2 < a[i].z) { mx2 = a[i].z; poz2 = a[i].ind; } } q = min(min(a[i].x, a[i].y), mx1 + mx2); if (mx < q) { mx = q; k = 2; p1 = poz1; p2 = poz2; } } for (i = 1; i <= n; i++) { x = a[i].x; y = a[i].y; z = a[i].z; a[i].x = y; a[i].y = z; a[i].z = x; } sort(a + 1, a + n + 1, cmp); for (i = 1; i <= n; i++) { mx1 = -1; mx2 = -1; u = 0; while (a[i].x == a[i + 1].x && a[i].y == a[i + 1].y) { u = 1; if (mx1 < a[i].z) { mx2 = mx1; poz2 = poz1; mx1 = a[i].z; poz1 = a[i].ind; } else if (mx2 < a[i].z) { mx2 = a[i].z; poz2 = a[i].ind; } i++; } if (u == 1) { if (mx1 < a[i].z) { mx2 = mx1; poz2 = poz1; mx1 = a[i].z; poz1 = a[i].ind; } else if (mx2 < a[i].z) { mx2 = a[i].z; poz2 = a[i].ind; } } q = min(min(a[i].x, a[i].y), mx1 + mx2); if (mx < q) { mx = q; k = 2; p1 = poz1; p2 = poz2; } } for (i = 1; i <= n; i++) { x = a[i].x; y = a[i].y; z = a[i].z; a[i].x = y; a[i].y = z; a[i].z = x; } sort(a + 1, a + n + 1, cmp); for (i = 1; i <= n; i++) { mx1 = -1; mx2 = -1; u = 0; while (a[i].x == a[i + 1].x && a[i].y == a[i + 1].y) { u = 1; if (mx1 < a[i].z) { mx2 = mx1; poz2 = poz1; mx1 = a[i].z; poz1 = a[i].ind; } else if (mx2 < a[i].z) { mx2 = a[i].z; poz2 = a[i].ind; } i++; } if (u == 1) { if (mx1 < a[i].z) { mx2 = mx1; poz2 = poz1; mx1 = a[i].z; poz1 = a[i].ind; } else if (mx2 < a[i].z) { mx2 = a[i].z; poz2 = a[i].ind; } } q = min(min(a[i].x, a[i].y), mx1 + mx2); if (mx < q) { mx = q; k = 2; p1 = poz1; p2 = poz2; } } printf( %d n , k); if (k == 1) printf( %d n , poz); else { printf( %d %d n , p1, p2); } return 0; }
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/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
David Fritz
memory map module
*/
/* the memory map is as follows:
0x00000000 512 bootloader ROM
0x10000000 16777216 SRAM
0xf0000000 16 UART
0xf0100000 4 switches
0xf0200000 4 leds
0xf0300000 12 gpio
0xf0400000 8 VGA
0xf0500000 8 PLPID
0xf0600000 4 timer
0xf0700000 8 interrupt controller
0xf0800000 ? pmc hardware
0xf0a00000 4 sseg
*/
module mm(addr, mod, eff_addr);
input [31:0] addr; /* word aligned base address */
output [7:0] mod; /* the module */
output [31:0] eff_addr; /* effective address */
assign mod = (addr[31:20] == 12'h000) ? 0 : /* mod_rom */
(addr[31:24] == 8'h10) ? 1 : /* mod_ram */
(addr[31:20] == 12'hf00) ? 2 : /* mod_uart */
(addr[31:20] == 12'hf01) ? 3 : /* mod_switches */
(addr[31:20] == 12'hf02) ? 4 : /* mod_leds */
(addr[31:20] == 12'hf03) ? 5 : /* mod_gpio */
(addr[31:20] == 12'hf04) ? 6 : /* mod_vga */
(addr[31:20] == 12'hf05) ? 7 : /* mod_plpid */
(addr[31:20] == 12'hf06) ? 8 : /* mod_timer */
(addr[31:20] == 12'hf07) ? 10 : /* mod_interrupt */
(addr[31:20] == 12'hf08) ? 11 : /* mod_pmc */
(addr[31:20] == 12'hf0a) ? 9 : /* mod_sseg */
0;
assign eff_addr = (mod == 8'h01) ? {8'h00,addr[23:0]} : {12'h000,addr[19:0]};
endmodule
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#include <bits/stdc++.h> using namespace std; void solve() { int t; cin >> t; while (t--) { int n; cin >> n; int r, p, s; cin >> r >> p >> s; string q; cin >> q; int lastn = ceil(n / 2.0); int R = 0, P = 0, S = 0; for (long long i = 0; i < q.size(); i++) { if (q[i] == R ) { R++; } else if (q[i] == S ) { S++; } else { P++; } } int total = min(R, p) + min(P, s) + min(S, r); if (total < lastn) { cout << NO << endl; ; continue; } else { char ans[q.size()]; memset(ans, 0 , sizeof(ans)); for (int i = 0; i < q.size(); i++) { if (q[i] == S ) { if (r > 0) { ans[i] = R ; r--; } } else if (q[i] == R ) { if (p > 0) { ans[i] = P ; p--; } } else { if (s > 0) { ans[i] = S ; s--; } } } for (int i = 0; i < q.size(); i++) { if (ans[i] == 0 ) { if (r > 0) { ans[i] = R ; r--; } else if (p > 0) { ans[i] = P ; p--; } else if (s > 0) { ans[i] = S ; s--; } } } cout << YES << endl; ; for (int i = 0; i < q.size(); i++) { cout << ans[i]; } cout << endl; } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); }
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// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, i; cin >> n; long long int arr1[n]; for (i = 0; i < n; i++) cin >> arr1[i]; cin >> m; long long int arr2[m]; for (i = 0; i < m; i++) cin >> arr2[i]; sort(arr1, arr1 + n); sort(arr2, arr2 + m); cout << arr1[n - 1] << << arr2[m - 1]; }
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#include <bits/stdc++.h> using namespace std; void MAIN() { long long N; cin >> N; string S = to_string(N); reverse(S.begin(), S.end()); int sz = (int)S.size(); long long ans = -2; for (int i = 0; i < (1 << sz); i++) { int i_c = i; if ((i_c >> (sz - 1) & 1) || (i_c >> (sz - 2) & 1)) { continue; } string T = S; long long now = 1; for (int j = 0; j < sz; j++) { if (i_c >> j & 1) { int X = 10 + (int)(T[j] - 0 ); now *= 19 - X; if (T[j + 2] == 0 ) { if (i_c >> (j + 2) & 1) { T[j + 2] = 9 ; i_c ^= (1 << (j + 2)); } else { now = 0; break; } } else { T[j + 2]--; } } else { now *= (int)(T[j] - 0 ) + 1; if (T[j] == 9 && j >= 2 && (i >> (j - 2) & 1)) { T[j + 2]--; } } } ans += now; } cout << ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int T; cin >> T; while (T--) { MAIN(); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int mx = 2e5 + 5; int dp[mx][3], arr[mx], n, h[mx]; void solve() { cin >> n; for (int i = 1; i <= n; i++) { cin >> arr[i]; h[arr[i]]++; } sort(arr, arr + n + 1); memset(dp, 0, sizeof dp); dp[1][0] = dp[1][1] = dp[1][2] = 1; for (int i = 2; i <= n; i++) { if (arr[i] - arr[i - 1] > 2) { dp[i][1] = dp[i][2] = dp[i][0] = min(dp[i - 1][0], min(dp[i - 1][1], dp[i - 1][2])) + 1; } else if (arr[i] - arr[i - 1] == 2) { dp[i][0] = min(dp[i - 1][0] + 1, min(dp[i - 1][1] + 1, dp[i - 1][2])); dp[i][1] = dp[i][2] = min(dp[i - 1][0], min(dp[i - 1][1], dp[i - 1][2])) + 1; } else if (arr[i] - arr[i - 1] == 1) { dp[i][0] = min(dp[i - 1][0] + 1, min(dp[i - 1][1], dp[i - 1][2] + 1)); dp[i][1] = min(dp[i - 1][0] + 1, min(dp[i - 1][1] + 1, dp[i - 1][2])); dp[i][2] = min(dp[i - 1][0] + 1, min(dp[i - 1][1] + 1, dp[i - 1][2] + 1)); } else { dp[i][0] = min(dp[i - 1][0], min(dp[i - 1][1] + 1, dp[i - 1][2] + 1)); dp[i][1] = min(dp[i - 1][0] + 1, min(dp[i - 1][1], dp[i - 1][2] + 1)); dp[i][2] = min(dp[i - 1][0] + 1, min(dp[i - 1][1] + 1, dp[i - 1][2])); } } cout << min(dp[n][0], min(dp[n][1], dp[n][2])) << ; set<int> s; for (int i = 0; i < mx; i++) { if (h[i] > 0) { int t = min(3, h[i]); int x = i - 1; if (s.find(x) == s.end()) { s.insert(x); h[i]--; } x++; if (h[i] > 0) { if (s.find(x) == s.end()) { s.insert(x); h[i]--; } } x++; if (h[i] > 0) { if (s.find(x) == s.end()) { s.insert(x); h[i]--; } } } } cout << s.size(); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); ; int t = 1; while (t--) { solve(); } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkinvlp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINVLP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long n; cin >> n; vector<pair<long long, long long> > v(n); for (long long i = 0; i < n; i++) { cin >> v[i].first >> v[i].second; } sort(v.begin(), v.end()); long long a, b; a = v[n - 1].first; for (long long i = 0; i < n; i++) swap(v[i].first, v[i].second); sort(v.begin(), v.end()); b = v[0].first; if (a - b <= 0) cout << 0 << endl; else cout << a - b << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int num[200000 + 5]; int main() { int i, j, k, n, m; cin >> n; long long sum = 0; for (i = 0; i < n; i++) { cin >> num[i]; sum += num[i]; } long long ans = 0; sum++; sum /= 2; for (i = 0; i < n; i++) { ans += num[i]; if (ans >= sum) { cout << i + 1 << endl; return 0; } } }
|
#include <bits/stdc++.h> using namespace std; int res = INT_MAX; int i, j; int n, d; int a[2018]; int main() { cin >> n >> d; for (int x = 0; x < n; x++) cin >> a[x]; sort(a, a + n); for (i = 0; i < n; i++) for (j = n - 1; j >= i; j--) { if (a[j] - a[i] <= d) { res = min(res, n - j + i - 1); break; } } return !printf( %d , res); }
|
#include <bits/stdc++.h> using namespace std; map<long long, long long> m; long long n, p; int main() { cin >> n; while (cin >> n) m[n]++; for (n = 1; n < 11; n++) p += m[n] * m[n * -1]; cout << p + m[0] * (m[0] - 1) / 2; }
|
//======================================================================
//
// rosc.v
// ------
// Digital ring oscillator used as entropy source. Based on the
// idea of using carry chain in adders as inverter by Bernd Paysan.
//
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module rosc #(parameter WIDTH = 2)
(
input wire clk,
input wire reset_n,
input wire we,
input wire [(WIDTH - 1) : 0] opa,
input wire [(WIDTH - 1) : 0] opb,
output wire dout
);
//----------------------------------------------------------------
// Registers.
//----------------------------------------------------------------
reg dout_reg;
reg dout_new;
//----------------------------------------------------------------
// Concurrent assignment.
//----------------------------------------------------------------
assign dout = dout_reg;
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
dout_reg <= 1'b0;
end
else
begin
if (we)
begin
dout_reg <= dout_new;
end
end
end
//----------------------------------------------------------------
// adder_osc
//
// Adder logic that generates the oscillator.
//
// NOTE: This logic contains a combinational loop and does
// not play well with an event driven simulator.
//----------------------------------------------------------------
always @*
begin: adder_osc
reg [WIDTH : 0] sum;
reg cin;
cin = ~sum[WIDTH];
sum = opa + opb + cin;
dout_new = sum[WIDTH];
end
endmodule // rosc
//======================================================================
// EOF rosc.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; int a[100005], b[100005]; int main(void) { int n; stack<int> s; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = n; i >= 1; i--) { if (s.empty()) { s.push(a[i]); b[i] = 0; continue; } if (a[i] < s.top()) { s.push(a[i]); b[a[i]] = 0; } else if (a[i] > s.top()) { int temp = max(1, b[s.top()]); s.pop(); while (!s.empty() && a[i] > s.top()) { temp = max(temp + 1, b[s.top()]); s.pop(); } b[a[i]] = temp; s.push(a[i]); } } int k = 0; for (int i = 1; i <= n; i++) k = max(k, b[i]); printf( %d n , k); }
|
#include <bits/stdc++.h> using namespace std; long long numbit(long long x) { return (1LL << x) - 1LL; } long long getbit(long long x, long long i) { return (x >> i) & 1LL; } long long onbit(long long x, long long i) { return x | (1LL << i); } long long offbit(long long x, long long i) { return x & (~(1LL << i)); } const int oo = 1000111000; const int Nmax = 1e5 + 10; const long long mod = 1e9 + 7; const long double PI = 3.14159265358979323846; int p[Nmax * 2], c[Nmax * 2]; int ch[Nmax * 2]; bool ok[Nmax * 2]; int main() { ios::sync_with_stdio(0); cin.tie(NULL); int test; cin >> test; for (long long e = (1); e <= (test); e++) { int n; cin >> n; for (long long i = (1); i <= (n); i++) cin >> p[i]; for (long long i = (1); i <= (n); i++) cin >> c[i]; memset(ok, false, sizeof(ok)); memset(ch, 0, sizeof(ch)); int cnt = 0; vector<int> circle[n + 1]; for (long long i = (1); i <= (n); i++) if (!ok[i]) { cnt++; int j = i; while (!ok[j]) { circle[cnt].push_back(j); ok[j] = true; j = p[j]; } } int res = n + 1; for (long long i = (1); i <= (cnt); i++) { int it = 0; for (long long m = (1); m <= (circle[i].size()); m++) if (circle[i].size() % m == 0) { if (m >= res) break; int j = 0; it++; bool ok = false; while (j < circle[i].size()) { if (ch[circle[i][j]] == it) { j++; continue; } ok = true; int h = j; while (ok) { if (ch[circle[i][h]] == it || c[circle[i][j]] != c[circle[i][h]]) { ok = false; break; } ch[circle[i][h]] = it; h = (h + m) % circle[i].size(); if (h == j) break; } if (ok) break; j++; } if (ok) { res = min(res, int(m)); break; } } } cout << res << endl; } }
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; signed main() { long long int t; cin >> t; vector<long long int> nums = {6, 10, 14, 15}; long long int minS = nums[0] + nums[1] + nums[2]; long long int maxS = nums[0] + nums[1] + nums[3]; while (t--) { long long int n; cin >> n; if (n <= minS) cout << NO n ; else { long long int d = n - minS; if (d == nums[0] || d == nums[1] || d == nums[2]) { if (n <= maxS) cout << NO n ; else cout << YES n << 6 << << 10 << << 15 << << n - maxS << n ; } else cout << YES n << 6 << << 10 << << 14 << << d << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; double a, b, c, d; int main() { char st = e ; cin >> a >> b >> c >> d; if (a / b == b / c && b / c == c / d) st = g ; if (a - b == b - c && b - c == c - d) st = a ; if (st == e ) cout << 42 << endl; else if (st == g ) { int d1 = d, b1 = b, a1 = a; if (d * b / a == d1 * b1 / a1) cout << d * b / a << endl; else cout << 42 << endl; } else cout << d + b - a << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int width; int height; cin >> height; cin >> width; char art[height][width]; for (int i = 0; i < height; i++) { for (int k = 0; k < width; k++) { cin >> art[i][k]; } } bool found_content = false; int max_width = width - 1; int min_width = 0; int max_height = height - 1; int min_height = 0; int collumn = 0; while (!found_content) { for (int i = 0; i < height && !found_content; i++) { if (art[i][collumn] == * ) { min_width = collumn; found_content = true; } } collumn++; } found_content = false; collumn = width - 1; while (!found_content) { for (int i = 0; i < height && !found_content; i++) { if (art[i][collumn] == * ) { max_width = collumn; found_content = true; } } collumn--; } found_content = false; int row = 0; while (!found_content) { for (int i = 0; i < width && !found_content; i++) { if (art[row][i] == * ) { min_height = row; found_content = true; } } row++; } found_content = false; row = height - 1; while (!found_content) { for (int i = 0; i < width && !found_content; i++) { if (art[row][i] == * ) { max_height = row; found_content = true; } } row--; } for (int r = min_height; r <= max_height; r++) { for (int c = min_width; c <= max_width; c++) { cout << art[r][c]; } cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; char c; int n, m, cnt, f[3600][3]; bool a[60][60], flag, heng[51][51][51], shu[51][51][51]; bool go(int x1, int y1, int x2, int y2) { if (heng[x1][min(y1, y2)][max(y1, y2)] && shu[y2][min(x1, x2)][max(x1, x2)]) return true; if (heng[x2][min(y1, y2)][max(y1, y2)] && shu[y1][min(x1, x2)][max(x1, x2)]) return true; return false; } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> c; if (c == B ) a[i][j] = 1, f[++cnt][1] = i, f[cnt][2] = j; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (a[i][j]) { heng[i][j][j] = true; for (int k = j + 1; k <= m; k++) { if (a[i][k]) heng[i][j][k] = true; else break; } } for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) if (a[j][i]) { shu[i][j][j] = true; for (int k = j + 1; k <= n; k++) { if (a[k][i]) shu[i][j][k] = true; else break; } } flag = true; for (int i = 1; i < cnt; i++) for (int j = i + 1; j <= cnt; j++) if (!go(f[i][1], f[i][2], f[j][1], f[j][2])) { flag = false; break; } if (flag) cout << YES << endl; else cout << NO << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 2e5 + 10; int beg[N]; int nxt[N]; int to[N]; int tot; int a[N]; void add(int x, int y) { ++tot; nxt[tot] = beg[x]; to[tot] = y; beg[x] = tot; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, m, k; cin >> n >> m >> k; for (int i = 1; i <= n; ++i) { int x; cin >> x; add(x, i); } int ans = 0; for (int i = 1; i <= m; ++i) { int siz = 0; for (int j = beg[i]; j; j = nxt[j]) a[++siz] = to[j]; if (siz == 0) continue; reverse(a + 1, a + 1 + siz); for (int r = 1, l = 1; r <= siz; ++r) { for (; l < r && a[r] - a[l] + 1 > k + r - l + 1; ++l) ; ans = max(ans, r - l + 1); } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; int solve(); void precomp(); int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int t = 1; if (0) cin >> t; precomp(); for (int tc = 1; tc <= t; tc++) { if (0 && 0) cout << Case # << tc << : ; solve(); } } void precomp() { return; } int cnt[26][26], ans[26], tmp[26]; string s; int solve() { cin >> s; for (int i = 1; i <= s.size(); i++) { memset(cnt, 0, sizeof(cnt)); memset(tmp, 0, sizeof(tmp)); for (int j = 0; j < s.size(); j++) cnt[s[j] - a ][s[(j + i) % s.size()] - a ]++; for (int j = 0; j < s.size(); j++) if (cnt[s[j] - a ][s[(i + j) % s.size()] - a ] == 1) tmp[s[j] - a ]++; for (int j = 0; j < 26; j++) ans[j] = max(ans[j], tmp[j]); } int tot = 0; for (int i = 0; i < 26; i++) tot += ans[i]; long double ans = (long double)tot / (long double)s.size(); cout << fixed << setprecision(10); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng_32(chrono::steady_clock::now().time_since_epoch().count()); const int maxn = 2e5 + 10; const double pi = acos(-1); int main() { int cas; cin >> cas; double n; while (cas--) { cin >> n; printf( %.10lf n , cos(pi / 4.0 / n) / sin(pi / 2.0 / n)); } return 0; }
|
#include <bits/stdc++.h> int main() { int tux; scanf( %d , &tux); int foo = 0, bar = 0, baz = 0, quz = 1; for (int i = 0; i < tux; i++) { int pur; scanf( %d , &pur); foo += pur; bar++; if (foo * quz >= bar * baz) { baz = foo; quz = bar; } } printf( %.6lf n , (double)baz / quz); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long pw(long long a, long long b) { if (b == 0) return 1; if (b % 2 == 1) return (a * pw(a * a, b / 2)); else return (1 * pw(a * a, b / 2)); } void solve() { long long n, k; cin >> n >> k; long long a[n], b[k]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int n1 = 0; for (int i = 0; i < k; i++) { cin >> b[i]; if (b[i] == 1) n1++; } sort(b, b + k); long long ans = 0; for (int i = 0; i < n1; i++) ans += (a[n - 1 - i] * 2); long long st = 0, en = n - 1 - n1; for (long long i = k - 1; i >= n1; i--) { if (b[i] == 1) { ans += (a[en] * 2); en--; } else { ans += a[en]; b[i]--; en--; ans += a[st]; st += b[i]; } } cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; cin >> t; while (t--) { solve(); } return 0; }
|
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// ============================================================
// File Name: CLK_LOCK.v
// Megafunction Name(s):
// altclkctrl
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altclkctrl clock_type="Global Clock" DEVICE_FAMILY="CYCLONE II" clkselect ena inclk outclk
//VERSION_BEGIN 5.0 cbx_altclkbuf 2004:11:30:11:29:52:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
//synthesis_resources = clkctrl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module CLK_LOCK_altclkctrl_tb8
(
clkselect,
ena,
inclk,
outclk) /* synthesis synthesis_clearbox=1 */;
input [1:0] clkselect;
input ena;
input [3:0] inclk;
output outclk;
wire wire_clkctrl1_outclk;
cycloneii_clkctrl clkctrl1
(
.clkselect(clkselect),
.ena(ena),
.inclk(inclk),
.outclk(wire_clkctrl1_outclk));
defparam
clkctrl1.clock_type = "Global Clock",
clkctrl1.ena_register_mode = "none",
clkctrl1.lpm_type = "cycloneii_clkctrl";
assign
outclk = wire_clkctrl1_outclk;
endmodule //CLK_LOCK_altclkctrl_tb8
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module CLK_LOCK (
inclk,
outclk)/* synthesis synthesis_clearbox = 1 */;
input inclk;
output outclk;
wire sub_wire0;
wire sub_wire1 = 1'h1;
wire [2:0] sub_wire4 = 3'h0;
wire [1:0] sub_wire5 = 2'h0;
wire outclk = sub_wire0;
wire sub_wire2 = inclk;
wire [3:0] sub_wire3 = {sub_wire4, sub_wire2};
CLK_LOCK_altclkctrl_tb8 CLK_LOCK_altclkctrl_tb8_component (
.ena (sub_wire1),
.inclk (sub_wire3),
.clkselect (sub_wire5),
.outclk (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: clock_type STRING "Global Clock"
// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
// Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0
// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CLK_LOCK_bb.v FALSE FALSE
|
#include <bits/stdc++.h> using namespace std; const int maxn = 105000; int a[maxn], ans[maxn]; int n, p, res1, res2; bool judge1(int k) { int sum = 0; for (int i = 1; i <= n; i++) { if (a[i] <= k) sum++; else { int tmp = a[i] - k; sum -= tmp; if (sum < 0) return 0; k += tmp; sum++; } } return 1; } bool judge2(int k) { int sum = 0; for (int i = 1; i <= n; i++) { if (a[i] <= k) { sum++; if (sum >= p) return 0; } else { int tmp = a[i] - k; sum -= tmp; k += tmp; sum++; } } return 1; } void solve() { scanf( %d %d , &n, &p); int max_v = 0; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); max_v = max(max_v, a[i]); } sort(a + 1, a + n + 1); int l = 1, r = max_v; while (l <= r) { int mid = l + r >> 1; if (judge1(mid)) r = mid - 1; else l = mid + 1; } res1 = l; r = max_v; while (l <= r) { int mid = l + r >> 1; if (judge2(mid)) l = mid + 1; else r = mid - 1; } res2 = r; printf( %d n , res2 - res1 + 1); for (int i = res1; i <= res2; i++) printf( %d , i); printf( n ); } int main() { solve(); return 0; }
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#include <bits/stdc++.h> #define debug(x) cerr << #x << = << x << endl using namespace std; typedef long long LL; const int N = 400005; int a[N], b[N], n; vector<int> vec; int main() { int T; scanf( %d , &T); while(T--) { vec.clear(); scanf( %d , &n); for(int i = 1; i <= n; i++) scanf( %d , &a[i]); //1 for(int i = 1; i <= n; i++) b[i] = a[i]; int pos = -1; for(int i = 2; i <= n; i++) { b[i] = b[i] - b[i - 1]; b[i - 1] -= b[i - 1]; if(b[i] < 0) { pos = i; break; } } if(b[n]) { if(pos == -1) pos = n; } if(pos == -1) { puts( YES ); continue; } if(pos > 0) { vec.push_back(pos); for(int id = 1; id <= 10; id++) { vec.push_back(pos - id); vec.push_back(pos + id); } } //2 pos = -1; for(int i = 1; i <= n; i++) b[i] = a[i]; for(int i = n - 1; i >= 1; i--) { b[i] = b[i] - b[i + 1]; b[i + 1] -= b[i + 1]; if(b[i] < 0) { pos = i; break; } } if(b[1]) { if(pos == -1) pos = 1; } if(pos > 0) { vec.push_back(pos); for(int id = 1; id <= 10; id++) { vec.push_back(pos - id); vec.push_back(pos + id); } } //3 for(int i = 1; i <= n; i++) b[i] = a[i]; pos = -1; bool ok = false; for(int i = 2; i <= n; i++) { b[i] = b[i] - b[i - 1]; if(b[i] < 0) { if(!ok) pos = i, ok = true; } } b[1] = 0; if(b[n]) { if(pos == -1) pos = n; } int tmp = b[n]; // if(tmp % 2) { // puts( NO ); // continue; // } for(int i = n; i > 0; i -= 2) { if(i <= pos) { if(a[i] - a[i + 1] == tmp / 2 || a[i] - a[i - 1] == tmp / 2) { vec.push_back(i); break; } } } int sz = vec.size(); bool flag = true; for(int i = 0; i < sz; i++) { int now = vec[i]; if(now < 1 || now > n) continue; if(now > 1) { for(int j = 1; j <= n; j++) b[j] = a[j]; flag = true; swap(b[now], b[now - 1]); for(int j = 2; j <= n; j++) { b[j] = b[j] - b[j - 1]; b[j - 1] -= b[j - 1]; if(b[j] < 0) { flag = false; break; } } if(b[n]) flag = false; if(flag) break; } if(now < n) { for(int j = 1; j <= n; j++) b[j] = a[j]; flag = true; swap(b[now], b[now + 1]); for(int j = 2; j <= n; j++) { b[j] = b[j] - b[j - 1]; b[j - 1] -= b[j - 1]; if(b[j] < 0) { flag = false; break; } } if(b[n]) flag = false; if(flag) break; } } if(!sz) flag = false; if(flag) puts( YES ); else puts( NO ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a; cin >> n; long long arr[n], sum[n], ans[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; sum[i] = arr[i]; if (i > 0) sum[i] += sum[i - 1]; } sort(arr, arr + n); for (int i = 0; i < n; i++) { ans[i] = arr[i]; if (i > 0) ans[i] += ans[i - 1]; } int m; cin >> m; for (int i = 0; i < m; i++) { int a, b, c; cin >> a >> b >> c; b--; c--; if (a == 1) { if (b != 0) { cout << (sum[c] - sum[b - 1]) << endl; } else cout << sum[c] << endl; } else { if (b != 0) { cout << (ans[c] - ans[b - 1]) << endl; } else cout << ans[c] << endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; long long n, m, p; long long A[5001]; long long a[5001]; long long l[1000005]; long long dp[2][5001]; long long s[5001][5001]; void work(long long *prev, long long *nxt) { long long total = 0, prev_total = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= min(l[i], m); j++) { nxt[j] = (s[l[i]][j] * A[j] % p) * prev_total % p; if (j <= l[i - 1]) nxt[j] = (nxt[j] - ((prev[j] * a[j] % p) * s[l[i]][j]) % p + p) % p; total = (total + nxt[j]) % p; } swap(nxt, prev); memset(nxt, 0, sizeof(long long) * 5000); prev_total = total; total = 0; } printf( %I64d n , prev_total); } int main() { scanf( %I64d %I64d %I64d , &n, &m, &p); for (int i = 1; i <= n; i++) { scanf( %I64d , &l[i]); } a[0] = 1; A[0] = 1; for (int i = 1; i <= 5000; i++) { A[i] = A[i - 1] * (m - i + 1) % p; a[i] = a[i - 1] * i % p; } s[0][0] = 1; for (int i = 1; i <= 5000; i++) for (int j = 1; j <= i; j++) { s[i][j] = (s[i - 1][j - 1] + s[i - 1][j] * (j - 1) % p) % p; } work(dp[0], dp[1]); }
|
//////////////////////////////////////////////////////////////////////////////////////////////
// File: delta_frame.v
// Author: B. Brown, T. Dotsikas
// About: Produces the delta frame using grayscale pixels from two different frames.
//////////////////////////////////////////////////////////////////////////////////////////////
module delta_frame #(
parameter COLOR_WIDTH = 10,
parameter FILTER_LENGTH = 20,
parameter CLOG2_FILTER_LENGTH = 5
)(
// Control
input wire clk,
input wire aresetn,
// Moving Average Filter
input wire is_filter,
input wire is_not_blank,
// Saturation Filter
input wire [(COLOR_WIDTH-1):0] threshold,
// Input Data
input wire [(COLOR_WIDTH-1):0] base_frame,
input wire [(COLOR_WIDTH-1):0] curr_frame,
// Output Data
output wire [(COLOR_WIDTH-1):0] delta_frame
);
// Not totally sure if this is the right way, think its safe though
localparam SUM_LENGTH = CLOG2_FILTER_LENGTH + COLOR_WIDTH;
// Internal signals and variables
genvar c;
integer i;
reg [2:0] counter;
reg [(COLOR_WIDTH-1):0] old [FILTER_LENGTH];
reg [(SUM_LENGTH-1):0] sum;
wire [(COLOR_WIDTH-1):0] avg;
reg [(COLOR_WIDTH-1):0] int_delta_frame;
wire [(COLOR_WIDTH-1):0] comp_value;
// Saturation Filter
assign comp_value = is_filter ? avg : int_delta_frame;
assign delta_frame = (comp_value > threshold) ? {COLOR_WIDTH{1'b1}} : {COLOR_WIDTH{1'b0}};
// Delta Frame
always @(posedge clk or negedge aresetn) begin
if (~aresetn) int_delta_frame <= 'd0;
else if (~is_not_blank) int_delta_frame <= 'd0;
else
begin
// Poor man's absolute value
if (curr_frame > base_frame) int_delta_frame <= curr_frame - base_frame;
else int_delta_frame <= base_frame - curr_frame;
end
end
// Moving Average Filter
always @(posedge clk or negedge aresetn) begin
if (~aresetn) counter <= 'd0;
else if (~is_not_blank) counter <= counter;
else if (counter == FILTER_LENGTH) counter <= 'd0;
else counter <= counter + 1;
end
generate
for (c = 0; c < FILTER_LENGTH; c = c + 1) begin: moving_avg_filter
always @(posedge clk or negedge aresetn) begin
if (~aresetn) old[c] <= 'd0;
else if (~is_not_blank) old[c] <= 'd0;
else if (counter == c) old[c] <= int_delta_frame;
else old[c] <= old[c];
end
end
endgenerate
always @* begin
sum = 'd0;
for (i = 0; i < FILTER_LENGTH; i = i + 1)
sum = sum + old[i];
end
assign avg = sum / FILTER_LENGTH;
endmodule
|
`timescale 1ns / 1ps
// Xilinx Single Port Write First RAM
// This code implements a parameterizable single-port write-first memory where when data
// is written to the memory, the output reflects the same data being written to the memory.
// If the output data is not needed during writes or the last read value is desired to be
// it is suggested to use a No Change as it is more power efficient.
// If a reset or enable is not necessary, it may be tied off or removed from the code.
// Modify the parameters for the desired RAM characteristics.
module xilinx_single_port_ram_write_first #(
parameter RAM_WIDTH = 32, // Specify RAM data width
parameter RAM_DEPTH = 1024, // Specify RAM depth (number of entries)
parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not)
) (
input [clogb2(RAM_DEPTH-1)-1:0] addra, // Address bus, width determined from RAM_DEPTH
input [RAM_WIDTH-1:0] dina, // RAM input data
input clka, // Clock
input wea, // Write enable
input ena, // RAM Enable, for additional power savings, disable port when not in use
output [RAM_WIDTH-1:0] douta // RAM output data
);
reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
reg [RAM_WIDTH-1:0] ram_data = {RAM_WIDTH{1'b0}};
// The following code either initializes the memory values to a specified file or to all zeros to match hardware
generate
if (INIT_FILE != "") begin: use_init_file
initial
$readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
end else begin: init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b0}};
end
endgenerate
always @(posedge clka)
if (!ena)
if (!wea) begin
BRAM[addra] <= dina;
ram_data <= dina;
end else
ram_data <= BRAM[addra];
assign douta = ram_data;
// The following function calculates the address width based on specified RAM depth
function integer clogb2;
input integer depth;
for (clogb2=0; depth>0; clogb2=clogb2+1)
depth = depth >> 1;
endfunction
endmodule
module SP32B1024 (
output [31:0] Q,
input CLK,
input CEN,
input WEN,
input [9:0] A,
input [31:0] D
);
xilinx_single_port_ram_write_first #(
.RAM_WIDTH(32), // Specify RAM data width
.RAM_DEPTH(1024), // Specify RAM depth (number of entries)
.INIT_FILE("") // Specify name/location of RAM initialization file if using one (leave blank if not)
) your_instance_name (
.addra(A), // Address bus, width determined from RAM_DEPTH
.dina(D), // RAM input data, width determined from RAM_WIDTH
.clka(CLK), // Clock
.wea(WEN), // Write enable
.ena(CEN), // RAM Enable, for additional power savings, disable port when not in use
.douta(Q) // RAM output data, width determined from RAM_WIDTH
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100000 + 10; int mod; int n, m; vector<int> E[MAX_N]; bool v[MAX_N]; int cnt; void dfs(int u) { if (v[u]) return; v[u] = true; ++cnt; for (vector<int>::iterator e = E[u].begin(); e != E[u].end(); ++e) { dfs(*e); } } int main() { cin >> n >> m >> mod; for (int i = 0; i < m; ++i) { int a, b; scanf( %d%d , &a, &b); --a, --b; E[a].push_back(b), E[b].push_back(a); } memset(v, 0, sizeof v); vector<int> comp; for (int i = 0; i < n; ++i) { if (!v[i]) { cnt = 0; dfs(i); comp.push_back(cnt); } } if (comp.size() == 1) { cout << 1 % mod << endl; return 0; } long long ans = 1, sum = 0; for (vector<int>::iterator e = comp.begin(); e != comp.end(); ++e) { ans = ans * (*e) % mod; sum += *e; sum %= mod; } for (int i = 0; i < comp.size() - 2; ++i) { ans = ans * sum % mod; } cout << ans << endl; return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: net2pci_dma_512x32.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module net2pci_dma_512x32 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [31:0] data;
input rdreq;
input wrreq;
output almost_empty;
output almost_full;
output empty;
output full;
output [31:0] q;
output [8:0] usedw;
wire [8:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [31:0] sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire [8:0] usedw = sub_wire0[8:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [31:0] q = sub_wire3[31:0];
wire almost_empty = sub_wire4;
wire almost_full = sub_wire5;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (sub_wire4),
.almost_full (sub_wire5),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 4,
scfifo_component.almost_full_value = 480,
scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = 512,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 32,
scfifo_component.lpm_widthu = 9,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "4"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "480"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "4"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "480"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL "almost_empty"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 9 0 OUTPUT NODEFVAL "usedw[8..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: usedw 0 0 9 0 @usedw 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL net2pci_dma_512x32_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// (c) NedoPC 2010
//
// wait generator for Z80
`include "../include/tune.v"
module zwait(
input wire rst_n,
input wire wait_start_gluclock,
input wire wait_start_comport,
input wire wait_end,
output reg [6:0] waits,
output wire wait_n,
output wire spiint_n
);
`ifdef SIMULATE
initial
begin
// force waits = 7'd0;
waits <= 7'd0;
end
`endif
wire wait_off_n;
assign wait_off_n = (~wait_end) & rst_n;
// RS-flipflops
//
always @(posedge wait_start_gluclock, negedge wait_off_n)
if( !wait_off_n )
waits[0] <= 1'b0;
else if( wait_start_gluclock )
waits[0] <= 1'b1;
//
always @(posedge wait_start_comport, negedge wait_off_n)
if( !wait_off_n )
waits[1] <= 1'b0;
else if( wait_start_comport )
waits[1] <= 1'b1;
always @(posedge wait_end) // just dummy for future extensions
begin
waits[6:2] <= 5'd0;
end
assign spiint_n = ~|waits;
`ifndef SIMULATE
assign wait_n = spiint_n ? 1'bZ : 1'b0;
`else
assign wait_n = 1'bZ;
`endif
endmodule
|
//Jun.29.2004 w0,w1,w2,w3 bug fix
//Jun.30.2004 endian bug fix
//Jul.1.2004 endian bug fix
//Apr.2.2005 Change Port Address
`include "define.h"
`define COMB_MOUT
`define COMB_MOUT_IR
`define NO_SIGNED_MOUT
module ram_module_altera(clock,sync_reset,IR,MOUT,Paddr,Daddr,wren,datain,access_mode,M_signed,
uread_port,write_busy);
input clock,sync_reset;
input wren;
input [31:0] datain;
input M_signed;
input [7:0] uread_port;
input write_busy;//Apr.2.2005
`ifdef RAM32K
input [14:0] Paddr,Daddr;//4KB address
reg [14:0] DaddrD;
`endif
`ifdef RAM16K
input [13:0] Paddr,Daddr;//4KB address
reg [13:0] DaddrD;
`endif
`ifdef RAM4K
input [11:0] Paddr,Daddr;//4KB address
reg [11:0] DaddrD;
`endif
output [31:0] IR;//Instrcuntion Register
output [31:0] MOUT;//data out
input [1:0] access_mode;
reg [31:0] IR;
reg [31:0] MOUT;
reg [1:0] access_modeD;
wire [7:0] a0,a1,a2,a3;
wire [7:0] b0,b1,b2,b3;
wire [7:0] dport0,dport1,dport2,dport3;
wire w0,w1,w2,w3;
wire uread_port_access=`UART_PORT_ADDRESS==Daddr;
reg uread_access_reg;
assign dport0=datain[7:0] ;
assign dport1=access_mode !=`BYTE_ACCESS ? datain[15:8] : datain[7:0];
assign dport2=access_mode==`LONG_ACCESS ? datain[23:16] : datain[7:0];
assign dport3=access_mode==`LONG_ACCESS ? datain[31:24] :
access_mode==`WORD_ACCESS ? datain[15:8] : datain[7:0];
`ifdef RAM32K
ram8192x8_3 ram0(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
.data_b(dport0),.address_b(Daddr[14:2]),.wren_b(w0),.clock(clock),
.q_a(a0),.q_b(b0));
ram8192x8_2 ram1(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
.data_b(dport1),.address_b(Daddr[14:2]),.wren_b(w1),.clock(clock),
.q_a(a1),.q_b(b1));
ram8192x8_1 ram2(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
.data_b(dport2),.address_b(Daddr[14:2]),.wren_b(w2),.clock(clock),
.q_a(a2),.q_b(b2));
ram8192x8_0 ram3(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[14:2]),
.data_b(dport3),.address_b(Daddr[14:2]),.wren_b(w3),.clock(clock),
.q_a(a3),.q_b(b3));
`endif
`ifdef RAM16K
ram1k3 ram0(.addra(Paddr[13:2]),
.dinb(dport0),.addrb(Daddr[13:2]),.web(w0),.clka(clock),.clkb(clock),
.douta(a0),.doutb(b0));
ram1k2 ram1(.addra(Paddr[13:2]),
.dinb(dport1),.addrb(Daddr[13:2]),.web(w1),.clka(clock),.clkb(clock),
.douta(a1),.doutb(b1));
ram1k1 ram2(.addra(Paddr[13:2]),
.dinb(dport2),.addrb(Daddr[13:2]),.web(w2),.clka(clock),.clkb(clock),
.douta(a2),.doutb(b2));
ram1k0 ram3(.addra(Paddr[13:2]),
.dinb(dport3),.addrb(Daddr[13:2]),.web(w3),.clka(clock),.clkb(clock),
.douta(a3),.doutb(b3));
`endif
`ifdef RAM4K
ram_1k_3 ram0(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
.data_b(dport0),.address_b(Daddr[11:2]),.wren_b(w0),.clock(clock),
.q_a(a0),.q_b(b0));
ram_1k_2 ram1(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
.data_b(dport1),.address_b(Daddr[11:2]),.wren_b(w1),.clock(clock),
.q_a(a1),.q_b(b1));
ram_1k_1 ram2(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
.data_b(dport2),.address_b(Daddr[11:2]),.wren_b(w2),.clock(clock),
.q_a(a2),.q_b(b2));
ram_1k_0 ram3(.data_a(8'h00),.wren_a(1'b0),.address_a(Paddr[11:2]),
.data_b(dport3),.address_b(Daddr[11:2]),.wren_b(w3),.clock(clock),
.q_a(a3),.q_b(b3));
`endif
wire temp=( access_mode==`BYTE_ACCESS && Daddr[1:0]==2'b00);
assign w3= wren &&
( access_mode==`LONG_ACCESS ||
( access_mode==`WORD_ACCESS && !Daddr[1] ) ||
( access_mode==`BYTE_ACCESS && Daddr[1:0]==2'b00));
assign w2= wren &&
( access_mode==`LONG_ACCESS ||
( access_mode==`WORD_ACCESS && !Daddr[1]) ||
( Daddr[1:0]==2'b01));
assign w1= wren &&
( access_mode==`LONG_ACCESS ||
( access_mode==`WORD_ACCESS && Daddr[1]) ||
( Daddr[1:0]==2'b10));
assign w0= wren &&
( access_mode==`LONG_ACCESS ||
( access_mode==`WORD_ACCESS && Daddr[1]) ||
( Daddr[1:0]==2'b11));
//IR
`ifdef COMB_MOUT_IR
always @(*) IR={a3,a2,a1,a0};
`else
always @(posedge clock) begin
if (sync_reset) IR <=0;
else IR <={a3,a2,a1,a0};
end
`endif
always @(posedge clock) begin
if (access_modeD==`LONG_ACCESS) begin
if(uread_access_reg) begin
MOUT <={23'h00_0000,write_busy,uread_port};
end else
MOUT <={b3,b2,b1,b0};
end else if (access_modeD==`WORD_ACCESS) begin
case (DaddrD[1])
1'b0: if(M_signed) MOUT <={{16{b3[7]}},b3,b2};//Jul.1.2004
else MOUT <={16'h0000,b3,b2};
1'b1: if(M_signed) MOUT <={{16{b1[7]}},b1,b0};//Jul.1.2004
else MOUT <={16'h0000,b1,b0};
endcase
end else begin//BYTE ACCESSS
case (DaddrD[1:0])
2'b00:if(M_signed) MOUT <={{24{b3[7]}},b3};
else MOUT <={16'h0000,8'h00,b3};
2'b01:if(M_signed) MOUT <={{24{b2[7]}},b2};
else MOUT <={16'h0000,8'h00,b2};
2'b10:if(M_signed) MOUT <={{24{b1[7]}},b1};
else MOUT <={16'h0000,8'h00,b1};
2'b11:if(M_signed) MOUT <={{24{b0[7]}},b0};
else MOUT <={16'h0000,8'h00,b0};
endcase
end
end
always @(posedge clock) begin
access_modeD<=access_mode;
DaddrD<=Daddr;
uread_access_reg<=uread_port_access;//Jul.7.2004
end
endmodule
|
#include <bits/stdc++.h> int main() { int n, i, sum1, sum2, sum3; scanf( %d , &n); sum1 = 0; for (i = 0; i < n; i++) { int a; scanf( %d , &a); sum1 ^= a; } sum2 = 0; for (i = 0; i < n - 1; i++) { int b; scanf( %d , &b); sum2 ^= b; } sum3 = 0; for (i = 0; i < n - 2; i++) { int c; scanf( %d , &c); sum3 ^= c; } printf( %d n%d n , sum1 ^ sum2, sum2 ^ sum3); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> T abs(T x) { return x > 0 ? x : -x; } template <typename T> T sqr(T x) { return x * x; } template <typename T> ostream &operator<<(ostream &s, const vector<T> &x) { s << [ ; for (auto it : x) { s << it << , ; } s << ] ; return s; } template <typename T> ostream &operator<<(ostream &s, const set<T> &x) { s << { ; for (auto it : x) { s << it << , ; } s << } ; return s; } vector<pair<long long, long long> > a[5]; int main() { int n, k, b, c; cin >> n >> k >> b >> c; if (b > c * 5) b = c * 5; for (int i = 1; i <= n; i++) { int x; cin >> x; for (int i = 0; i < 5; i++) a[((x + i) % 5 + 5) % 5].push_back(make_pair(x + i, i * c)); } long long ans = 1e18; for (int i = 0; i < 5; i++) { sort(a[i].begin(), a[i].end()); auto v = a[i]; bool flag = false; long long firstpos = -1; multiset<long long> setic; long long allsum = 0; for (auto f : v) { long long pos = f.first, w = f.second; if (!flag) { flag = true; firstpos = pos; } w -= (pos - firstpos) / 5 * b; allsum += w; setic.insert(w); if ((int)setic.size() > k) { auto it = setic.end(); it--; allsum -= *it; setic.erase(it); } if ((int)setic.size() == k) { ans = min(ans, allsum + (long long)k * (pos - firstpos) / 5 * b); } } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> g[5000]; vector<int> r[5000]; vector<int8_t> vis(5000); int n, m, s; void dfs(int src) { vis[src] = true; for (auto v : g[src]) { if (!vis[v]) { dfs(v); } } } int root(int src, vector<bool> &df) { df[src] = true; int c = 0; for (int v : g[src]) { if (!df[v] && !vis[v]) { c += root(v, df) + 1; } } return c; } int main() { ios_base::sync_with_stdio(0); cin >> n >> m >> s; --s; for (int x, y, i = 0; i < m; ++i) { cin >> x >> y; g[--x].push_back(--y); r[y].push_back(x); } dfs(s); int ans = 0; vector<pair<int, int>> sl; for (int i = 0; i < n; ++i) { if (!vis[i]) { vector<bool> df(n); int a = root(i, df); sl.push_back({-a, i}); } } sort(sl.begin(), sl.end()); for (auto c : sl) { if (!vis[c.second]) { g[s].push_back(c.second); dfs(s); ++ans; } } printf( %d n , ans); return false & true; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; #ifdef LOCAL #define debug(...) { std::cout << [ << __FUNCTION__ << : << __LINE__ << ] << #__VA_ARGS__ << << __VA_ARGS__ << std::endl; } #else #define debug(...) #endif const long long mod = 1000000007; #define MOD(x) ((x)%mod) struct UnionFind { vector<int> par; vector<int> siz; vector<int> val; UnionFind(int N) { par.resize(N); siz.resize(N); val.resize(N); for (int i = 0; i < N; i++) { par[i] = i; siz[i] = 1; val[i] = 0; } } int& operator[](const int &x) { return val[getParent(x)]; } int getParent(int x) { int t = x; while (par[x] != x) { x = par[x]; } par[t] = x; return x; } int getSize(const int &x) { return siz[getParent(x)]; } bool merge(int x, int y) { x = getParent(x); y = getParent(y); if (x == y) { return false; } if (val[x] and val[y]) { return false; } if (siz[x] > siz[y]) { swap(x, y); // siz[x] is smaller } par[x] = y; siz[y] += siz[x]; val[y] = val[x] or val[y]; return true; } bool connected(const int &x, const int &y) { return getParent(x) == getParent(y); } }; long long power(long long x, long long n) { int i = 0; long long d = x; long long ats = 1; while (n > 0) { if (n & (1ll << i)) { n ^= (1ll << i); ats *= d; ats %= mod; } i++; d = (d * d) % mod; } return ats; } /*input 3 2 1 1 1 2 2 2 1 */ /*input 2 3 2 1 3 2 1 2 */ /*input 3 5 2 1 2 1 3 1 4 */ int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long n, m; cin >> n >> m; UnionFind par(m); set<int> imt; for (int i = 0; i < n; ++i) { int k; cin >> k; if (k == 1) { int a; cin >> a; a--; if (!par[a]) { par[a] = true; imt.insert(i); } } else if (k == 2) { int a, b; cin >> a >> b; a--, b--; if (par.merge(a, b)) { imt.insert(i); } } } long long vis = 0; for (int i = 0; i < m; ++i) { if (par.getParent(i) == i) { if (par.val[i]) { vis += par.siz[i]; } else { vis += par.siz[i] - 1; } } } cout << power(2, vis) << << imt.size() << n ; for (auto &&i : imt) { cout << i + 1 << ; } }
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic dual-port RAM
*/
module ram_dp #
(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10
)
(
// port A
input wire a_clk,
input wire a_we,
input wire [ADDR_WIDTH-1:0] a_addr,
input wire [DATA_WIDTH-1:0] a_din,
output wire [DATA_WIDTH-1:0] a_dout,
// port B
input wire b_clk,
input wire b_we,
input wire [ADDR_WIDTH-1:0] b_addr,
input wire [DATA_WIDTH-1:0] b_din,
output wire [DATA_WIDTH-1:0] b_dout
);
reg [DATA_WIDTH-1:0] a_dout_reg = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] b_dout_reg = {DATA_WIDTH{1'b0}};
// (* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
assign a_dout = a_dout_reg;
assign b_dout = b_dout_reg;
integer i, j;
initial begin
// two nested loops for smaller number of iterations per loop
// workaround for synthesizer complaints about large loop counts
for (i = 0; i < 2**ADDR_WIDTH; i = i + 2**(ADDR_WIDTH/2)) begin
for (j = i; j < i + 2**(ADDR_WIDTH/2); j = j + 1) begin
mem[j] = 0;
end
end
end
// port A
always @(posedge a_clk) begin
a_dout_reg <= mem[a_addr];
if (a_we) begin
mem[a_addr] <= a_din;
a_dout_reg <= a_din;
end
end
// port B
always @(posedge b_clk) begin
b_dout_reg <= mem[b_addr];
if (b_we) begin
mem[b_addr] <= b_din;
b_dout_reg <= b_din;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int a[maxn], x[maxn], y[maxn], sk[maxn], top, cnt; int main() { int n, P, ly = -1, fl = 0; scanf( %d , &n), P = n; for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = n; i >= 1; i--) { if (a[i] == 1) { sk[++top] = x[++cnt] = P--; y[cnt] = i; if (!fl) ly = i; } else if (a[i] == 2) { if (top <= 0) return puts( -1 ), 0; x[++cnt] = sk[top--]; y[cnt] = i; if (!fl) ly = i; P = min(P, x[cnt] - 1); } else if (a[i] == 3) { if (ly == -1) return puts( -1 ), 0; x[++cnt] = P; y[cnt] = ly; x[++cnt] = P; y[cnt] = ly = i; if (!fl) top--; fl = 1; P--; } } printf( %d n , cnt); for (int i = 1; i <= cnt; i++) printf( %d %d n , x[i], y[i]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; int m, v, m1, m2, v1, v2; cin >> a >> b >> c >> d; m1 = 3 * a / 10; m2 = a - (a / 250) * c; if (m1 > m2) m = m1; else m = m2; v1 = 3 * b / 10; v2 = b - (b / 250) * d; if (v1 > v2) v = v1; else v = v2; if (m > v) cout << Misha ; else if (m < v) cout << Vasya ; else cout << Tie ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 10; vector<pair<string, int> > ch[MAXN]; int nxt[MAXN][27], n, gp, ans; string t; void adds(string &tmp) { for (int i = 0; i < tmp.size(); i++) { gp = nxt[gp][tmp[i] - a ]; if (gp == t.size()) ans++; } } void dfs(int v, int p) { for (int i = 0; i < ch[v].size(); i++) { gp = p; adds(ch[v][i].first); dfs(ch[v][i].second, gp); } } int main() { cin >> n; for (int i = 2; i <= n; i++) { string tmp; int r; cin >> r >> tmp; ch[r].push_back({tmp, i}); } cin >> t; nxt[0][t[0] - a ] = 1; int cp = 0; for (int i = 1; i <= t.size(); i++) { for (char c = a ; c <= z ; c++) { if (t[cp] == c) nxt[i][c - a ] = cp + 1; else nxt[i][c - a ] = nxt[cp][c - a ]; } if (i < t.size()) { nxt[i][t[i] - a ] = i + 1; if (t[cp] == t[i]) cp++; else cp = nxt[cp][t[i] - a ]; } } dfs(1, 0); cout << ans; }
|
//############################################################################
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// (C) Copyright
// All Right Reserved
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 2015 DLAB Course
// Lab02 : Matrix
// Author : Hsiao-Kai, Liao
// File name : TESTBED.v
//###########################################################################
`timescale 1ns/10ps
`include "PATTERN.v"
`ifdef RTL
`include "Circle.vp"
`endif
`ifdef RTL2
`include "Circle2.vp"
`endif
`ifdef RTL3
`include "Circle3.vp"
`endif
`ifdef RTL4
`include "Circle4.vp"
`endif
`ifdef RTL5
`include "Circle5.vp"
`endif
`ifdef RTL6
`include "Circle6.vp"
`endif
`ifdef RTL7
`include "Circle7.vp"
`endif
`ifdef RTL8
`include "Circle8.vp"
`endif
module TESTBED();
wire clk;
wire [2:0] circle1;
wire [2:0] circle2;
wire rst_n;
wire in_valid;
wire [4:0] in;
wire out_valid;
wire [5:0] out;
/*initial begin
`ifdef RTL
$fsdbDumpfile("Circle.fsdb");
$fsdbDumpvars;
`endif
end*/
//---------------------------------
// module connection
//---------------------------------
PATTERN I_PATTERN(
.out(out),
.out_valid(out_valid),
.in(in),
.in_valid(in_valid),
.clk(clk),
.rst_n(rst_n),
.circle1(circle1),
.circle2(circle2)
);
Circle I_Circle(
.out(out),
.out_valid(out_valid),
.in(in),
.in_valid(in_valid),
.clk(clk),
.rst_n(rst_n),
.circle1(circle1),
.circle2(circle2)
);
initial begin
`ifdef RTL
$fsdbDumpfile("Circle.fsdb");
$fsdbDumpvars;
`endif
`ifdef RTL2
$fsdbDumpfile("Circle2.fsdb");
$fsdbDumpvars;
`endif
`ifdef RTL3
$fsdbDumpfile("Circle3.fsdb");
$fsdbDumpvars;
`endif
`ifdef RTL4
$fsdbDumpfile("Circle4.fsdb");
$fsdbDumpvars;
`endif
`ifdef RTL5
$fsdbDumpfile("Circle5.fsdb");
$fsdbDumpvars;
`endif
`ifdef RTL6
$fsdbDumpfile("Circle6.fsdb");
$fsdbDumpvars;
`endif
`ifdef RTL7
$fsdbDumpfile("Circle7.fsdb");
$fsdbDumpvars;
`endif
`ifdef RTL8
$fsdbDumpfile("Circle8.fsdb");
$fsdbDumpvars;
`endif
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_PP_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int K = 30; const int MOD = 1e9 + 7; long long n, power[K + 1]; int k; __inline void add(int &a, int b) { if ((a += b) >= MOD) { a -= MOD; } } struct Matrix { int trans[K][K]; int go[K]; Matrix() { memset(trans, 0, sizeof(trans)); memset(go, 0, sizeof(go)); } int all() { int result = 0; for (int i = 0; i < k; i++) { add(result, go[i]); for (int j = 0; j < k; j++) { add(result, trans[i][j]); } } return result; } }; map<long long, Matrix> mp; Matrix search(long long n) { if (mp.count(n)) { return mp[n]; } Matrix ret; if (k >= n) { for (int i = 0; i < n; i++) { ret.go[i] = 0; ret.trans[i][i] = 1; for (int j = i + 1; j < n; j++) { ret.trans[i][j] = power[j - i - 1]; } } return ret; } long long unit = 1; int length = 1; while (unit <= n / k && unit * k < n) { unit *= k; length++; } Matrix base = search(unit); ret = base; long long remaind = n % unit; Matrix extra = search(remaind); static int reach[K][K], _reach[K][K]; for (int i = 0; i < k; i++) { ret.go[i] = base.go[i]; for (int j = 0; j < k; j++) { reach[i][j] = base.trans[i][j]; } } for (int i = 1; i <= n / unit; i++) { if (i == n / unit && remaind == 0) { break; } Matrix &nxt = (i < n / unit) ? base : extra; int lead = i; for (int j = 0; j < k; j++) { for (int l = 0; l < k; l++) { _reach[j][l] = reach[j][l]; add(ret.go[j], reach[j][l]); reach[j][l] = 0; } } int t = ((k - 1) * (length - 2) + i - 1) % k; for (int start = 0; start < k; start++) { int sum = 0; for (int prev = k - 1; prev >= 0; prev--) { int pv = (prev + t) % k; add(sum, _reach[start][pv]); int succ = prev; int sv = (succ + t) % k, temp = ((sv - i) % k + k) % k; add(ret.go[start], 1LL * sum * nxt.go[temp] % MOD); for (int end = 0; end < k; end++) { add(reach[start][end], 1LL * sum * nxt.trans[temp][((end - i) % k + k) % k] % MOD); } } } for (int i = 0; i < k; i++) { for (int j = 0; j < k; j++) { ret.trans[i][j] = reach[i][j]; } } } return mp[n] = ret; } int main() { power[0] = 1; for (int i = 1; i <= K; i++) { power[i] = power[i - 1] * 2; } cin >> n >> k; Matrix answer = search(n); cout << (answer.all() + 1) % MOD << endl; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic 32x32 multiplier ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// Generic 32x32 multiplier with pipeline stages. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_gmultp2_32x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// No update
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
// 32x32 multiplier, no input/output registers
// Registers inside Wallace trees every 8 full adder levels,
// with first pipeline after level 4
`ifdef OR1200_GENERIC_MULTP2_32X32
`define OR1200_W 32
`define OR1200_WW 64
module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P );
input [`OR1200_W-1:0] X;
input [`OR1200_W-1:0] Y;
input CLK;
input RST;
output [`OR1200_WW-1:0] P;
reg [`OR1200_WW-1:0] p0;
reg [`OR1200_WW-1:0] p1;
integer xi;
integer yi;
//
// Conversion unsigned to signed
//
always @(X)
xi = X;
//
// Conversion unsigned to signed
//
always @(Y)
yi = Y;
//
// First multiply stage
//
always @(posedge CLK or `OR1200_RST_EVENT RST)
if (RST == `OR1200_RST_VALUE)
p0 <= `OR1200_WW'b0;
else
p0 <= xi * yi;
//
// Second multiply stage
//
always @(posedge CLK or `OR1200_RST_EVENT RST)
if (RST == `OR1200_RST_VALUE)
p1 <= `OR1200_WW'b0;
else
p1 <= p0;
assign P = p1;
endmodule
`endif
|
// File gh_fifo_async16_sr.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
//-------------------------------------------------------------------
// Filename: gh_fifo_async16_sr.vhd
//
//
// Description:
// an Asynchronous FIFO
//
// Copyright (c) 2006 by George Huber
// an OpenCores.org Project
// free to use, but see documentation for conditions
//
// Revision History:
// Revision Date Author Comment
// -------- ---------- --------- -----------
// 1.0 12/17/06 h lefevre Initial revision
//
//------------------------------------------------------
// no timescale needed
module gh_fifo_async16_sr(
clk_WR,
clk_RD,
rst,
srst,
WR,
RD,
D,
Q,
empty,
full
);
parameter [31:0] data_width=8;
// size of data bus
input clk_WR;
// write clock
input clk_RD;
// read clock
input rst;
// resets counters
input srst;
// resets counters (sync with clk_WR)
input WR;
// write control
input RD;
// read control
input [data_width - 1:0] D;
output [data_width - 1:0] Q;
output empty;
output full;
wire clk_WR;
wire clk_RD;
wire rst;
wire srst;
wire WR;
wire RD;
wire [data_width - 1:0] D;
wire [data_width - 1:0] Q;
wire empty;
wire full;
reg [data_width - 1:0] ram_mem[15:0];
wire iempty;
wire ifull;
wire add_WR_CE;
reg [4:0] add_WR; // 4 bits are used to address MEM
reg [4:0] add_WR_GC; // 5 bits are used to compare
wire [4:0] n_add_WR; // for empty, full flags
reg [4:0] add_WR_RS; // synced to read clk
wire add_RD_CE;
reg [4:0] add_RD;
reg [4:0] add_RD_GC;
reg [4:0] add_RD_GCwc;
wire [4:0] n_add_RD;
reg [4:0] add_RD_WS; // synced to write clk
reg srst_w;
reg isrst_w;
reg srst_r;
reg isrst_r;
//------------------------------------------
//----- memory -----------------------------
//------------------------------------------
always @(posedge clk_WR) begin
if(((WR == 1'b 1) && (ifull == 1'b 0))) begin
ram_mem[(add_WR[3:0])] <= D;
end
end
assign Q = ram_mem[(add_RD[3:0])];
//---------------------------------------
//--- Write address counter -------------
//---------------------------------------
assign add_WR_CE = (ifull == 1'b 1) ? 1'b 0 : (WR == 1'b 0) ? 1'b 0 : 1'b 1;
assign n_add_WR = add_WR + 4'h 1;
always @(posedge clk_WR or posedge rst) begin
if((rst == 1'b 1)) begin
add_WR <= {5{1'b0}};
add_RD_WS <= 5'b 11000;
add_WR_GC <= {5{1'b0}};
end else begin
add_RD_WS <= add_RD_GCwc;
if((srst_w == 1'b 1)) begin
add_WR <= {5{1'b0}};
add_WR_GC <= {5{1'b0}};
end
else if((add_WR_CE == 1'b 1)) begin
add_WR <= n_add_WR;
add_WR_GC[0] <= n_add_WR[0] ^ n_add_WR[1];
add_WR_GC[1] <= n_add_WR[1] ^ n_add_WR[2];
add_WR_GC[2] <= n_add_WR[2] ^ n_add_WR[3];
add_WR_GC[3] <= n_add_WR[3] ^ n_add_WR[4];
add_WR_GC[4] <= n_add_WR[4];
end
else begin
add_WR <= add_WR;
add_WR_GC <= add_WR_GC;
end
end
end
assign full = ifull;
assign ifull = (iempty == 1'b 1) ? 1'b 0 : (add_RD_WS != add_WR_GC) ? 1'b 0 : 1'b 1;
//---------------------------------------
//--- Read address counter --------------
//---------------------------------------
assign add_RD_CE = (iempty == 1'b 1) ? 1'b 0 : (RD == 1'b 0) ? 1'b 0 : 1'b 1;
assign n_add_RD = add_RD + 4'h 1;
always @(posedge clk_RD or posedge rst) begin
if((rst == 1'b 1)) begin
add_RD <= {5{1'b0}};
add_WR_RS <= {5{1'b0}};
add_RD_GC <= {5{1'b0}};
add_RD_GCwc <= 5'b 11000;
end else begin
add_WR_RS <= add_WR_GC;
if((srst_r == 1'b 1)) begin
add_RD <= {5{1'b0}};
add_RD_GC <= {5{1'b0}};
add_RD_GCwc <= 5'b 11000;
end
else if((add_RD_CE == 1'b 1)) begin
add_RD <= n_add_RD;
add_RD_GC[0] <= n_add_RD[0] ^ n_add_RD[1];
add_RD_GC[1] <= n_add_RD[1] ^ n_add_RD[2];
add_RD_GC[2] <= n_add_RD[2] ^ n_add_RD[3];
add_RD_GC[3] <= n_add_RD[3] ^ n_add_RD[4];
add_RD_GC[4] <= n_add_RD[4];
add_RD_GCwc[0] <= n_add_RD[0] ^ n_add_RD[1];
add_RD_GCwc[1] <= n_add_RD[1] ^ n_add_RD[2];
add_RD_GCwc[2] <= n_add_RD[2] ^ n_add_RD[3];
add_RD_GCwc[3] <= n_add_RD[3] ^ (( ~n_add_RD[4]));
add_RD_GCwc[4] <= ( ~n_add_RD[4]);
end
else begin
add_RD <= add_RD;
add_RD_GC <= add_RD_GC;
add_RD_GCwc <= add_RD_GCwc;
end
end
end
assign empty = iempty;
assign iempty = (add_WR_RS == add_RD_GC) ? 1'b 1 : 1'b 0;
//--------------------------------
//- sync rest stuff --------------
//- srst is sync with clk_WR -----
//- srst_r is sync with clk_RD ---
//--------------------------------
always @(posedge clk_WR or posedge rst) begin
if((rst == 1'b 1)) begin
srst_w <= 1'b 0;
isrst_r <= 1'b 0;
end else begin
isrst_r <= srst_r;
if((srst == 1'b 1)) begin
srst_w <= 1'b 1;
end
else if((isrst_r == 1'b 1)) begin
srst_w <= 1'b 0;
end
end
end
always @(posedge clk_RD or posedge rst) begin
if((rst == 1'b 1)) begin
srst_r <= 1'b 0;
isrst_w <= 1'b 0;
end else begin
isrst_w <= srst_w;
if((isrst_w == 1'b 1)) begin
srst_r <= 1'b 1;
end
else begin
srst_r <= 1'b 0;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O221A_BEHAVIORAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221A_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_TB_V
`define SKY130_FD_SC_LP__OR4_TB_V
/**
* or4: 4-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_lp__or4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_TB_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_dec_fix.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ecc_dec_fix
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_data, ecc_single, ecc_multiple,
// Inputs
clk, rst, h_rows, phy_rddata, correct_en, ecc_status_valid
);
input clk;
input rst;
// Compute syndromes.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
wire [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_ns;
genvar k;
genvar m;
generate
for (k=0; k<2*nCK_PER_CLK; k=k+1) begin : ecc_word
for (m=0; m<ECC_WIDTH; m=m+1) begin : ecc_bit
assign syndrome_ns[k*ECC_WIDTH+m] =
^(phy_rddata[k*DQ_WIDTH+:CODE_WIDTH] & h_rows[m*CODE_WIDTH+:CODE_WIDTH]);
end
end
endgenerate
reg [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_r;
always @(posedge clk) syndrome_r <= #TCQ syndrome_ns;
// Extract payload bits from raw DRAM bits and register.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_ns;
genvar i;
generate
for (i=0; i<2*nCK_PER_CLK; i=i+1) begin : extract_payload
assign ecc_rddata_ns[i*PAYLOAD_WIDTH+:PAYLOAD_WIDTH] =
phy_rddata[i*DQ_WIDTH+:PAYLOAD_WIDTH];
end
endgenerate
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_r;
always @(posedge clk) ecc_rddata_r <= #TCQ ecc_rddata_ns;
// Regenerate h_matrix from h_rows leaving out the identity part
// since we're not going to correct the ECC bits themselves.
genvar n;
genvar p;
wire [ECC_WIDTH-1:0] h_matrix [DATA_WIDTH-1:0];
generate
for (n=0; n<DATA_WIDTH; n=n+1) begin : h_col
for (p=0; p<ECC_WIDTH; p=p+1) begin : h_bit
assign h_matrix [n][p] = h_rows [p*CODE_WIDTH+n];
end
end
endgenerate
// Compute flip bits.
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] flip_bits;
genvar q;
genvar r;
generate
for (q=0; q<2*nCK_PER_CLK; q=q+1) begin : flip_word
for (r=0; r<DATA_WIDTH; r=r+1) begin : flip_bit
assign flip_bits[q*DATA_WIDTH+r] =
h_matrix[r] == syndrome_r[q*ECC_WIDTH+:ECC_WIDTH];
end
end
endgenerate
// Correct data.
output reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
input correct_en;
integer s;
always @(/*AS*/correct_en or ecc_rddata_r or flip_bits)
for (s=0; s<2*nCK_PER_CLK; s=s+1)
if (correct_en)
rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH] ^
flip_bits[s*DATA_WIDTH+:DATA_WIDTH];
else rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH];
// Copy raw payload bits if ECC_TEST is ON.
localparam RAW_BIT_WIDTH = PAYLOAD_WIDTH - DATA_WIDTH;
genvar t;
generate
if (RAW_BIT_WIDTH > 0)
for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits
always @(/*AS*/ecc_rddata_r)
rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] =
ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH];
end
endgenerate
// Generate status information.
input ecc_status_valid;
output wire [2*nCK_PER_CLK-1:0] ecc_single;
output wire [2*nCK_PER_CLK-1:0] ecc_multiple;
genvar v;
generate
for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status
wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
assign ecc_single[v] = ecc_status_valid && ~zero && odd;
assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:54:33 12/16/2015
// Design Name:
// Module Name: uart_unload.v
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_unload #(parameter BYTE_WIDTH = 8, WORD_WIDTH = 13) (
input rst,
input clk,
input byte_rdy,
`ifdef TWO_BYTE_DECODE
input [BYTE_WIDTH-1:0] din,
output reg signed [WORD_WIDTH-1:0] dout,
`endif
output reg unload_uart
);
reg byte_rdy_b = 1'b0;
`ifdef TWO_BYTE_DECODE
reg [WORD_WIDTH-2:0] data_tmp = {BYTE_WIDTH-1{1'b0}};
`endif
always @(posedge clk) begin
if (rst) begin
unload_uart <= 1'b0;
byte_rdy_b <= 1'b0;
`ifdef TWO_BYTE_DECODE
data_tmp <= {BYTE_WIDTH-1{1'b0}};
dout <= {WORD_WIDTH{1'b0}};
`endif
end else begin
byte_rdy_b <= byte_rdy;
unload_uart <= (byte_rdy & ~byte_rdy_b) ? 1'b1 : 1'b0;
`ifdef TWO_BYTE_DECODE
if (din[BYTE_WIDTH-1]) data_out <= {din[BYTE_WIDTH-3:0], data_tmp};
else data_tmp <= din[BYTE_WIDTH-2:0];
`endif
end
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: wb_rom_32x8192.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module wb_rom_32x8192 (
address,
clock,
q);
input [12:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "rom_image.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "rom_image.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_rom_32x8192.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_rom_32x8192.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_rom_32x8192.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_rom_32x8192.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_rom_32x8192_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_rom_32x8192_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BEHAVIORAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/01/2016 11:47:41 AM
// Design Name:
// Module Name: FullAdder_WithErrorDetection
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FullAdder_WithErrorDetection(
input [3:0] A,
input [3:0] B,
input Operation,
output [3:0] S,
output Error
);
// Operation detects if subtraction or addition is being done
//assign B = B ^ {Operation, Operation, Operation, Operation};
wire carry_out1, carry_out2, carry_out3;
AdderSlice Bit0 (
.A(A[0]),
.B(B[0] ^ Operation), // or try B[0] ^ Operation
.S(S[0]),
.Cout(carry_out1),
.Cin(Operation)
);
AdderSlice Bit1 (
.A(A[1]),
.B(B[1] ^ Operation),
.S(S[1]),
.Cout(carry_out2), //no overflow -> .Cout(S[2:0]),
.Cin(carry_out1)
);
AdderSlice Bit2 (
.A(A[2]),
.B(B[2] ^ Operation),
.S(S[2]),
.Cout(carry_out3), //no overflow -> .Cout(S[2:0]),
.Cin(carry_out2)
);
AdderSlice Bit3 (
.A(A[3]),
.B(B[3] ^ Operation),
.S(S[3]),
.Cout(Cout), //no overflow -> .Cout(S[2:0]),
.Cin(carry_out3)
);
ErrorDetection Part (
.A_MSB(A[3]),
.B_MSB(B[3]),
.Operation(Operation),
.S_MSB(S[3]),
.Error(Error)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long t = 1; template <class myType> void print_arr(myType &arr, long long L, string sep) { for (long long(i) = (0); (i) < (L); ++(i)) { cout << arr[i]; if (i < L - 1) { cout << sep; } } cout << n ; return; } long long merge(long long arr[], long long temp_arr[], long long left, long long mid, long long right) { long long i, j, k; i = left; j = mid + 1; k = left; long long inv_count = 0; while (i <= mid && j <= right) { if (arr[i] <= arr[j]) { temp_arr[k] = arr[i]; k += 1; i += 1; } else { temp_arr[k] = arr[j]; inv_count += (mid - i + 1); k += 1; j += 1; } } while (i <= mid) { temp_arr[k] = arr[i]; k += 1; i += 1; } while (j <= right) { temp_arr[k] = arr[j]; k += 1; j += 1; } for (long long loop_var = left; loop_var <= right; loop_var++) { arr[loop_var] = temp_arr[loop_var]; } return inv_count; } long long _mergeSort(long long arr[], long long temp_arr[], long long left, long long right) { long long inv_count = 0; if (left < right) { long long mid; mid = (left + right) / 2; inv_count += _mergeSort(arr, temp_arr, left, mid); inv_count += _mergeSort(arr, temp_arr, mid + 1, right); inv_count += merge(arr, temp_arr, left, mid, right); } return inv_count; } long long mergeSort(long long arr[], long long n) { long long temp_arr[n]; for (long long(i) = (0); (i) < (n); ++(i)) temp_arr[i] = 0; return _mergeSort(arr, temp_arr, 0, n - 1); } void solve() { long long n; cin >> n; long long a[n]; for (long long(i) = (0); (i) < (n); ++(i)) cin >> a[i]; long long invs, invs2; long long b[n]; for (long long(i) = (0); (i) < (n); ++(i)) b[i] = a[i]; invs = mergeSort(b, n); long long ans = 0; long long p; for (long long(i) = (0); (i) < (30); ++(i)) { p = (1 << i); for (long long(j) = (0); (j) < (n); ++(j)) b[j] = a[j] ^ p; invs2 = mergeSort(b, n); if (invs2 < invs) { ans += p; } } for (long long(j) = (0); (j) < (n); ++(j)) b[j] = a[j] ^ ans; cout << mergeSort(b, n) << << ans << n ; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, T, fa[500005], top, st[500005 << 2], d[500005], a[500005]; struct E { int x, y, l, r; } e[500005]; int Getfa(int x) { while (fa[x] != x) x = fa[x]; return x; } int col(int x) { int now = 0; while (fa[x] != x) now ^= a[x], x = fa[x]; return now; } void link(int x, int y, int D) { if (d[x] > d[y]) swap(x, y); if (d[x] == d[y]) d[y]++, st[++top] = -y; fa[x] = y; a[x] = D; st[++top] = x; } void RE(int t) { for (; top > t; top--) if (st[top] < 0) d[-st[top]]--; else fa[st[top]] = st[top], a[st[top]] = 0; } void work(int l, int r, int k) { int mid = (l + r) >> 1, now = top; for (int i = 1; i <= k; i++) if (e[i].l <= l && r <= e[i].r) { int u = Getfa(e[i].x), v = Getfa(e[i].y); if (u != v) link(u, v, col(e[i].x) == col(e[i].y)); else if (col(e[i].x) == col(e[i].y)) { for (int i = l; i <= r; i++) puts( NO ); RE(now); return; } swap(e[k--], e[i--]); } if (l == r) puts( YES ); else { int i, j; for (i = 1, j = 0; i <= k; i++) if (e[i].l <= mid) swap(e[i], e[++j]); work(l, mid, j); for (i = 1, j = 0; i <= k; i++) if (e[i].r > mid) swap(e[i], e[++j]); work(mid + 1, r, j); } RE(now); } map<int, int> M[500005]; int main() { scanf( %d%d , &n, &T); for (int i = 1; i <= T; i++) { int x, y; scanf( %d%d , &x, &y); if (x > y) swap(x, y); if (M[x][y]) e[M[x][y]].r = i - 1, M[x][y] = 0; else { M[x][y] = ++m; e[m].x = x; e[m].y = y; e[m].l = i - 1; e[m].r = T; } } for (int i = 1; i <= m; i++) { if (++e[i].l > e[i].r) { i--, m--; assert(false); } } for (int i = 1; i <= n; i++) fa[i] = i, d[i] = 1; work(1, T, m); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [63:0] rf;
reg [63:0] rf2;
reg [63:0] biu;
reg b;
always @* begin
rf[63:32] = biu[63:32] & {32{b}};
rf[31:0] = {32{b}};
rf2 = rf;
rf2[31:0] = ~{32{b}};
end
reg [31:0] src1, src0, sr, mask;
wire [31:0] dualasr
= ((| src1[31:4])
? {{16{src0[31]}}, {16{src0[15]}}}
: ( ( sr & {2{mask[31:16]}})
| ( {{16{src0[31]}}, {16{src0[15]}}}
& {2{~mask[31:16]}})));
wire [31:0] sl_mask
= (32'hffffffff << src1[4:0]);
wire [31:0] sr_mask
= {sl_mask[0], sl_mask[1],
sl_mask[2], sl_mask[3], sl_mask[4],
sl_mask[5], sl_mask[6], sl_mask[7],
sl_mask[8], sl_mask[9],
sl_mask[10], sl_mask[11],
sl_mask[12], sl_mask[13], sl_mask[14],
sl_mask[15], sl_mask[16],
sl_mask[17], sl_mask[18], sl_mask[19],
sl_mask[20], sl_mask[21],
sl_mask[22], sl_mask[23], sl_mask[24],
sl_mask[25], sl_mask[26],
sl_mask[27], sl_mask[28], sl_mask[29],
sl_mask[30], sl_mask[31]};
wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}};
wire [1:0] w = {2{b}};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("cyc=%0d d=%x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask);
`endif
if (cyc==1) begin
biu <= 64'h12451282_abadee00;
b <= 1'b0;
src1 <= 32'h00000001;
src0 <= 32'h9a4f1235;
sr <= 32'h0f19f567;
mask <= 32'h7af07ab4;
end
if (cyc==2) begin
biu <= 64'h12453382_abad8801;
b <= 1'b1;
if (rf != 64'h0) $stop;
if (rf2 != 64'h00000000ffffffff) $stop;
src1 <= 32'h0010000f;
src0 <= 32'h028aa336;
sr <= 32'h42ad0377;
mask <= 32'h1ab3b906;
if (dualasr != 32'h8f1f7060) $stop;
if (sl_mask != 32'hfffffffe) $stop;
if (sr_mask != 32'h7fffffff) $stop;
if (widerep != '0) $stop;
end
if (cyc==3) begin
biu <= 64'h12422382_77ad8802;
b <= 1'b1;
if (rf != 64'h12453382ffffffff) $stop;
if (rf2 != 64'h1245338200000000) $stop;
src1 <= 32'h0000000f;
src0 <= 32'h5c158f71;
sr <= 32'h7076c40a;
mask <= 32'h33eb3d44;
if (dualasr != 32'h0000ffff) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
if (widerep != '1) $stop;
end
if (cyc==4) begin
if (rf != 64'h12422382ffffffff) $stop;
if (rf2 != 64'h1242238200000000) $stop;
if (dualasr != 32'h3062cc1e) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
$write("*-* All Finished *-*\n");
if (widerep != '1) $stop;
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, l, r, ar[110], ubah; int main() { cin >> n >> m; for (int i = 1; i <= m; i++) { cin >> l >> r; ar[l]++; ar[r + 1]--; } for (int i = 1; i <= n; i++) { ubah += ar[i]; if (ubah != 1) { cout << i << << ubah << n ; return 0; } } cout << OK n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_2_V
`define SKY130_FD_SC_HVL__DIODE_2_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__diode_2 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__diode_2 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_2_V
`define SKY130_FD_SC_HS__OR3B_2_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3b_2 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3b_2 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_2_V
|
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