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module linked_fifo(rst, clk, push, push_fifo, pop, pop_fifo, d, q, empty, full, count, almost_full);
parameter WIDTH = 8;
parameter DEPTH = 32;
parameter FIFOS = 8;
parameter LOG2_FIFOS = log2(FIFOS-1);
parameter LOG2_DEPTH = log2(DEPTH-1);
parameter FIFO_COUNT = FIFOS;
input rst;
input clk;
input push;
input [LOG2_FIFOS-1:0] push_fifo;
input pop;
input [LOG2_FIFOS-1:0] pop_fifo;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
//output [2**FIFOS-1:0] empty;
output empty;
output full;
output [(LOG2_DEPTH+1)*(2**FIFOS)-1:0] count;
output reg almost_full;
//stores actual data not links
reg [WIDTH-1:0] ram [DEPTH - 1:0];
//ram to store links
reg [LOG2_DEPTH:0] linked_ram [DEPTH - 1:0];
reg ram_we;
reg [LOG2_DEPTH-1:0] ram_addr_a, ram_addr_b;
reg [WIDTH-1:0] ram_d, ram_q;
reg [LOG2_DEPTH:0] linked_ram_d, linked_ram_q;
reg [WIDTH-1:0] r_q;
reg [LOG2_DEPTH-1:0] r_beg [FIFOS-1:0];
reg [LOG2_DEPTH-1:0] r_end [FIFOS-1:0];
reg [LOG2_DEPTH-1:0] beg_next, beg_curr, end_next, end_curr;
reg [LOG2_DEPTH-1:0] empty_check;
reg c_empty;
reg [LOG2_FIFOS-1:0] beg_ptr, end_ptr;
reg [LOG2_DEPTH:0] free, next_free;
reg [LOG2_DEPTH:0] free_count;
reg beg_we, end_we;
//TODO: clarify
//reg [DEPTH:0] r_free_end, c_free_end;
//reg [DEPTH:0] r_free_beg, c_free_beg;
integer i, j, k;
reg [LOG2_DEPTH:0] rst_counter, next_rst_counter;
reg [1:0] state, next_state;
`define RST1 0
`define RST2 1
`define STEADY 2
always @(posedge clk) begin
if(state != `STEADY) begin
free_count <= DEPTH-FIFOS;
end else if(pop & push) begin
end else if(pop) begin
free_count <= free_count + 1;
end else if(push) begin
free_count <= free_count - 1;
end
end
always @*
if(free_count < 2)
almost_full = 1;
else
almost_full = 0;
always @(posedge clk) begin
if(ram_we) begin
ram[ram_addr_a] <= ram_d;
end
ram_q <= ram[ram_addr_b];
end
assign q = ram_q;
always @*
ram_d = d;
always @(posedge clk) begin
if(ram_we) begin
linked_ram[ram_addr_a] <= linked_ram_d;
end
end
always @*
linked_ram_q = linked_ram[ram_addr_b];
//TODO: add write enable
always @(posedge clk) begin
if(beg_we)
r_beg[beg_ptr] <= beg_next;
if(end_we)
r_end[end_ptr] <= end_next;
end
always @* begin
beg_curr = r_beg[beg_ptr];
end_curr = r_end[end_ptr];
empty_check = r_end[beg_ptr];
end
always @* begin
if(empty_check == beg_curr)
c_empty = 1;
else
c_empty = 0;
end
assign empty = c_empty;
always @* begin
if(rst) begin
next_rst_counter = 0;
end else if(rst_counter[LOG2_DEPTH] != 1) begin
next_rst_counter = rst_counter + 1;
end else
next_rst_counter = DEPTH;
end
always @(posedge clk)
rst_counter <= next_rst_counter;
/* always @(posedge clk) begin
r_free_end <= c_free_end;
r_free_beg <= c_free_beg;
end
*/
always @* begin
if(rst)
next_state = `RST1;
else if((state == `RST1) && (next_rst_counter == FIFOS))
next_state = `RST2;
else if(rst_counter[LOG2_DEPTH] == 1)
next_state = `STEADY;
else
next_state = state;
end
always @(posedge clk) begin
state <= next_state;
free <= next_free;
end
always @* begin
//Defaults:
ram_we = 0;
beg_next = 0;
beg_we = 0;
end_we = 0;
end_next = 0;
beg_ptr = pop_fifo;
end_ptr = push_fifo;
next_free = free;
ram_addr_a = end_curr;
ram_addr_b = beg_curr;
linked_ram_d = 0;
if(state == `RST1)begin
ram_we = 0;
beg_we = 1;
end_we = 1;
beg_next = rst_counter;
end_next = rst_counter;
beg_ptr = rst_counter;
end_ptr = rst_counter;
next_free = FIFOS;
ram_addr_a = end_curr;
ram_addr_b = beg_curr;
end else if(state == `RST2) begin
ram_we = 1;
linked_ram_d = next_rst_counter;
ram_addr_a = rst_counter;
end else if(state == `STEADY) begin
if(push && pop) begin
ram_we = 1;
beg_we = 1;
end_we = 1;
ram_addr_a = end_curr;
linked_ram_d = beg_curr;
end_ptr = push_fifo;
beg_ptr = pop_fifo;
end_next = beg_curr;
beg_next = linked_ram_q;
ram_addr_b = beg_curr;
end else if(push) begin
ram_we = 1;
end_we = 1;
ram_addr_a = end_curr;
linked_ram_d = free;
end_ptr = push_fifo;
end_next = free;
ram_addr_b = free;
next_free = linked_ram_q;
end else if(pop) begin
beg_we = 1;
beg_next = linked_ram_q;
ram_addr_b = beg_curr;
ram_addr_a = beg_curr;
next_free = beg_curr;
ram_we = 1;
linked_ram_d = free;
end
end
end
assign full = free[LOG2_DEPTH];
//debug
//synthesis off
/*
//TODO: print last 8 clock cycles.
integer prev_buffer_ptr;
initial prev_buffer_ptr = 0;
reg [WIDTH-1:0]prev_linked_ram[0:7][0:DEPTH-1];
reg [LOG2_DEPTH:0] prev_r_beg[0:7][0:FIFOS-1];
reg [LOG2_DEPTH:0] prev_r_end[0:7][0:FIFOS-1];
reg [0:7] prev_pop;
reg [0:7] prev_push;
reg [LOG2_DEPTH:0] prev_free[0:7];
always @(posedge clk) begin
for(i = 0; i < DEPTH; i = i + 1)
prev_linked_ram[prev_buffer_ptr][i] <= linked_ram[i];
for(i = 0; i < FIFOS; i = i + 1) begin
prev_r_beg[prev_buffer_ptr][i] <= r_beg[i];
prev_r_end[prev_buffer_ptr][i] <= r_end[i];
end
prev_pop[prev_buffer_ptr] <= pop;
prev_push[prev_buffer_ptr] <= push;
prev_free[prev_buffer_ptr] <= free;
prev_buffer_ptr <= (prev_buffer_ptr + 1) % 8;
end
task print_linked_info;
begin
for(j = 0; j < 8; j = j + 1) begin
k = (prev_buffer_ptr + j) % 8;
$display("%d clock cycles ago:", 8-j);
$display("push: %b, pop: %b", prev_push[k], prev_pop[k]);
$display("linked_ram:");
for(i = 0; i < DEPTH; i = i + 1)
$display("%d : %d", i, prev_linked_ram[k][i]);
$display("r_beg:");
for(i = 0; i < FIFOS; i = i + 1)
$display("%d : %d", i, prev_r_beg[k][i]);
$display("r_end:");
for(i = 0; i < FIFOS; i = i + 1)
$display("%d : %d", i, prev_r_end[k][i]);
$display("free: %d", prev_free[k]);
end
$display("linked_ram:");
for(i = 0; i < DEPTH; i = i + 1)
$display("%d : %d", i, linked_ram[i]);
$display("r_beg:");
for(i = 0; i < FIFOS; i = i + 1)
$display("%d : %d", i, r_beg[i]);
$display("r_end:");
for(i = 0; i < FIFOS; i = i + 1)
$display("%d : %d", i, r_end[i]);
end
endtask
reg [1:0] prev_state;
integer debug_free_count, free_trace, timeout;
integer trace, count, total_count;
integer error = 0;
always @(posedge clk) begin
if(full && push) begin
$display("%m ERROR: OVERFLOW");
$finish;
end
prev_state <= state;
if(prev_state != state) begin
if(state == `RST2) begin
$display("In RST2 state");
end else if(state == `STEADY) begin
$display("In steady state");
end
end
total_count = 0;
debug_free_count = 0;
free_trace = free;
timeout = DEPTH;
if(state == `STEADY) begin
while(timeout != 0 && !free_trace[LOG2_DEPTH]) begin
timeout = timeout - 1;
debug_free_count = debug_free_count + 1;
free_trace = linked_ram[free_trace];
end
if(debug_free_count != free_count) begin
$display("free count mismatch %m");
$display("debug: %d", debug_free_count);
$display("free: %d", free_count);
$finish;
end
total_count = debug_free_count + total_count;
//$display("@linked_fifo: free count: %d", debug_free_count);
for(i = 0; i < FIFOS; i = i + 1) begin
count = 0;
trace = r_beg[i];
timeout = DEPTH;
while(timeout != 0 && trace != r_end[i]) begin
trace = linked_ram[trace];
count = count + 1;
timeout = timeout - 1;
end
total_count = total_count + count;
//$display("@linked_fifo: count: %d", count);
end
if(total_count != DEPTH-FIFOS) begin
$display("%d: @linked_fifo: %m ERROR: total_count: %d", $time, total_count);
//print_linked_info();
$finish;
error = 1;
end
end
end
*/
//sythesis on
`include "log2.vh"
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [43:0] mi;
reg [5:0] index;
integer indexi;
reg read;
initial begin
// Static
mi = 44'b01010101010101010101010101010101010101010101;
if (mi[0] !== 1'b1) $stop;
if (mi[1 -: 2] !== 2'b01) $stop;
`ifdef VERILATOR
// verilator lint_off SELRANGE
if (mi[-1] !== 1'bx && mi[-1] !== 1'b0) $stop;
if (mi[0 -: 2] !== 2'b1x && 1'b0) $stop;
if (mi[-1 -: 2] !== 2'bxx && 1'b0) $stop;
// verilator lint_on SELRANGE
`else
if (mi[-1] !== 1'bx) $stop;
if (mi[0 -: 2] !== 2'b1x) $stop;
if (mi[-1 -: 2] !== 2'bxx) $stop;
`endif
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
mi = 44'h123;
end
if (cyc==2) begin
index = 6'd43;
indexi = 43;
end
if (cyc==3) begin
read = mi[index];
if (read!==1'b0) $stop;
read = mi[indexi];
if (read!==1'b0) $stop;
end
if (cyc==4) begin
index = 6'd44;
indexi = 44;
end
if (cyc==5) begin
read = mi[index];
$display("-Illegal read value: %x",read);
//if (read!==1'b1 && read!==1'bx) $stop;
read = mi[indexi];
$display("-Illegal read value: %x",read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==6) begin
indexi = -1;
end
if (cyc==7) begin
read = mi[indexi];
$display("-Illegal read value: %x",read);
//if (read!==1'b1 && read!==1'bx) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module top (
input clk,
input [15:0] wdata,
output [15:0] rdata,
input [7:0] addr
);
SB_RAM40_4K #(
.WRITE_MODE(0),
.READ_MODE(0)
) ram (
.RDATA(rdata),
.RADDR(addr),
.RCLK(clk),
.RCLKE(1'b1),
.RE(1'b1),
.WADDR(addr),
.WCLK(clk),
.WCLKE(1'b1),
.WDATA(wdata),
.WE(1'b1),
.MASK(16'b0)
);
defparam ram.INIT_0 = 256'h123456789abcdef00000dddd0000eeee00000012483569ac0111044400000001;
defparam ram.INIT_1 = 256'h56789abcdef123400000dddd0000eeee00000012483569ac0111044401000002;
defparam ram.INIT_2 = 256'habcdef12345678900000dddd0000eeee00000012483569ac0111044402000004;
defparam ram.INIT_3 = 256'h00000000000000000000dddd0000eeee00000012483569ac0111044403000008;
defparam ram.INIT_4 = 256'hffff000022220000444400006666000088880012483569ac0111044404000010;
defparam ram.INIT_5 = 256'hffff000022220000444400006666000088880012483569ac0111044405000020;
defparam ram.INIT_6 = 256'hffff000022220000444400006666000088880012483569ac0111044406000040;
defparam ram.INIT_7 = 256'hffff000022220000444400006666000088880012483569ac0111044407000080;
defparam ram.INIT_8 = 256'h0000111100003333000055550000777700000012483569ac0111044408000100;
defparam ram.INIT_9 = 256'h0000111100003333000055550000777700000012483569ac0111044409000200;
defparam ram.INIT_A = 256'h0000111100003333000055550000777700000012483569ac011104440a000400;
defparam ram.INIT_B = 256'h0000111100003333000055550000777700000012483569ac011104440b000800;
defparam ram.INIT_C = 256'h0123000099990000aaaa0000bbbb0000cccc0012483569ac011104440c001000;
defparam ram.INIT_D = 256'h4567000099990000aaaa0000bbbb0000cccc0012483569ac011104440d002000;
defparam ram.INIT_E = 256'h89ab000099990000aaaa0000bbbb0000cccc0012483569ac011104440e004000;
defparam ram.INIT_F = 256'hcdef000099990000aaaa0000bbbb0000cccc0012483569ac011104440f008000;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int D[8][2] = {{1, 0}, {0, 1}, {-1, 0}, {0, -1}, {1, -1}, {-1, 1}, {-1, -1}, {1, 1}}; int N, M, K, f[600005], F[3005][6005], b[600005], tot; int find(int x) { return x == f[x] ? x : f[x] = find(f[x]); } bool can(int& x, int& y) { if (!y) y = 2 * M; if (y > 2 * M) y = 1; return 1 <= x && x <= N && F[x][y]; } bool check(int x, int y) { tot++; int xx, yy; for (int i = 0; i < 8; i++) if (can(xx = x + D[i][0], yy = y + D[i][1])) b[find(F[xx][yy])] = tot; for (int i = 0; i < 8; i++) if (can(xx = x + D[i][0], yy = y + M + D[i][1]) && b[find(F[xx][yy])] == tot) return 0; return 1; } void add(int x, int y, int z) { F[x][y] = z; for (int i = 0; i < 8; i++) { int xx = x + D[i][0], yy = y + D[i][1]; if (can(xx, yy)) f[find(F[xx][yy])] = find(z); } } void doit() { int ans = 0; scanf( %d%d%d , &N, &M, &K); if (M == 1) { puts( 0 ); return; } for (int i = 1; i <= 2 * K; i++) f[i] = i; for (int i = 1, x, y; i <= K; i++) { scanf( %d%d , &x, &y); if (check(x, y)) add(x, y, i), add(x, y + M, i + K), ans++; } printf( %d n , ans); } int main() { doit(); return 0; }
|
module qsys_serial_host(
// Qsys serial interface
output reg sdo,
input sdi,
input clk,
input sle,
output reg srdy,
input reset,
// Qsys bus interface
output rso_MRST_reset,
output cso_MCLK_clk,
output reg[31:0]avm_M1_writedata,
input [31:0] avm_M1_readdata,
output reg[7:0] avm_M1_address,
output [3:0] avm_M1_byteenable,
output reg avm_M1_write,
output reg avm_M1_read,
output avm_M1_begintransfer,
input avm_M1_readdatavalid,
input avm_M1_waitrequest
);
assign cso_MCLK_clk = clk;
assign rso_MRST_reset = reset;
reg [64:0] data_buffer;
assign avm_M1_byteenable = 4'b1111;
parameter initial_state = 8'd0;
parameter bus_ready = initial_state+8'd1;
parameter bus_transmit_start = bus_ready+8'd1;
parameter bus_transmit_ready = bus_transmit_start+8'd1;
parameter bus_address_ready = bus_transmit_ready + 8'd1;
parameter bus_data_wait = bus_address_ready + 8'd1;
parameter bus_data_ready = bus_data_wait + 8'd1;
parameter bus_transmit_back = bus_data_ready + 8'd1;
parameter bus_transmit_finish = bus_transmit_back + 8'd32;
reg [7:0] state;
reg [7:0] nextstate;
always@(posedge clk or posedge reset)
begin
if (reset)
state <= initial_state;
else
state <= nextstate;
end
always@(state or sle or avm_M1_waitrequest)
begin
case(state)
initial_state: nextstate <= bus_ready;
bus_ready: begin
if(sle == 1'b1) nextstate <= bus_transmit_start;
else nextstate <= bus_ready;
end
bus_transmit_start: begin
if(sle == 1'b0) nextstate <= bus_transmit_ready;
else nextstate <= bus_transmit_start;
end
bus_transmit_ready: nextstate <= bus_address_ready;
bus_address_ready: nextstate <= bus_data_wait;
bus_data_wait: begin
if(avm_M1_waitrequest == 1'b0) nextstate <= bus_data_ready;
else nextstate <= bus_data_wait;
end
bus_data_ready: nextstate <= bus_transmit_back;
bus_transmit_back:nextstate <= state + 1;
bus_transmit_finish:nextstate <= bus_ready;
default:
nextstate <= state + 1;
endcase
end
always@(posedge clk)
begin
if (state >= bus_transmit_back && state < bus_transmit_finish)
begin
integer i;
for(i=0;i<64;i=i+1)
data_buffer[i+1] <= data_buffer[i];
sdo <= data_buffer[31];
end
else begin
case(state)
bus_transmit_start:
begin
integer i;
for(i=0;i<64;i=i+1)
data_buffer[i+1] <= data_buffer[i];
data_buffer[0]<= sdi;
end
bus_transmit_ready:
avm_M1_address <= data_buffer[63:32];
bus_address_ready:
begin
if (data_buffer[64] == 1'b0) begin
avm_M1_read <= 1'b1;
avm_M1_write <= 1'b0;
end
else begin
avm_M1_writedata <= data_buffer[31:0];
avm_M1_read <= 1'd0;
avm_M1_write <= 1'b1;
end
end
bus_data_ready: begin
data_buffer[31:0] <= avm_M1_readdata;
avm_M1_read <= 1'd0;
avm_M1_write <= 1'b0;
end
endcase
end
end
always@(posedge clk)
begin
if (state >= bus_data_ready && state < bus_transmit_finish-1)
srdy <= 1;
else
srdy <= 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct S { int dist, u, v; S(int dd, int uu, int vv) { dist = dd; u = uu; v = vv; } bool operator<(const S& a) const { if (dist != a.dist) return dist < a.dist; return u < a.u; } bool operator>(const S& a) const { if (dist != a.dist) return dist > a.dist; return u > a.u; } }; vector<pair<int, int> > pA; vector<pair<int, int> > pB; vector<int> A; vector<int> B; pair<int, int> res[100007]; int main() { int N, M; scanf( %d %d , &N, &M); ; for (int i = (0); i < (M); i++) { int a, b; scanf( %d %d , &a, &b); ; if (b) A.push_back(a); else B.push_back(a); if (b) pA.push_back(make_pair(a, i)); else pB.push_back(make_pair(a, i)); } sort(A.begin(), A.end()); sort(B.begin(), B.end()); sort(pA.begin(), pA.end()); sort(pB.begin(), pB.end()); priority_queue<S, vector<S>, greater<S> > pq; for (int i = (0); i < ((int)A.size() - 1); i++) pq.push(S(A[i + 1], i, i + 1)); for (int m = (0); m < (B.size()); m++) { S s = pq.top(); pq.pop(); if (B[m] < s.dist) { cout << -1 << endl; return 0; } res[pB[m].second] = make_pair(s.u, s.v); s.v++; if (s.v < A.size()) { s.dist -= A[s.v - 1]; s.dist += A[s.v]; pq.push(s); } } for (int i = (0); i < (A.size()); i++) res[pA[i].second] = make_pair(i, N - 1); for (int i = (0); i < (M); i++) cout << res[i].first + 1 << << res[i].second + 1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<pair<int, int>> v(n); for (auto &x : v) cin >> x.first >> x.second; if (is_sorted(v.rbegin(), v.rend())) { bool ok = true; for (auto x : v) if (x.first != x.second) ok = false; if (ok) { cout << maybe n ; return 0; } } for (auto x : v) if (x.first != x.second) { cout << rated n ; return 0; } cout << unrated n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[307][307]; inline bool check(const int& i, const int& j) { return i >= 0 && i < n && j >= 0 && j < m; } int cnt_neighbors(const int& i, const int& j) { int res = 0; if (check(i - 1, j)) res++; if (check(i, j + 1)) res++; if (check(i + 1, j)) res++; if (check(i, j - 1)) res++; return res; } int main() { int tc; scanf( %d , &tc); while (tc--) { scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &a[i][j]); bool flag = 1; for (int i = 0; i < n && flag; i++) for (int j = 0; j < m && flag; j++) { int tmp = cnt_neighbors(i, j); if (a[i][j] > tmp) flag = 0; else a[i][j] = tmp; } if (flag) { puts( YES ); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) printf( %d , a[i][j]); puts( ); } } else puts( NO ); } return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module add2_and_round_reg
#(parameter WIDTH=16)
(input clk,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
output reg [WIDTH-1:0] sum);
wire [WIDTH-1:0] sum_int;
add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int));
always @(posedge clk)
sum <= sum_int;
endmodule // add2_and_round_reg
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFRBP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 105; const int mod = 1e9 + 7; long long n, m, x; long long dp[2][320][320][2]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); if (fopen( A.inp , r )) { freopen( test.inp , r , stdin); freopen( test.out , w , stdout); } cin >> n >> m >> x; if (n > m) return cout << 0, 0; dp[0][0][0][0] = 1; for (int i = 1; i <= m; i++) { for (int j = 0; j <= min(1ll * i, n); j++) { for (int k = 0; k <= j; k++) { if (i == x) { if (j > 0) dp[i & 1][j][k][1] = (dp[i & 1][j][k][1] + dp[(i + 1) & 1][j - 1][k][0]) % mod; if (j > 0 && k > 0) dp[i & 1][j][k][1] = (dp[i & 1][j][k][1] + dp[(i + 1) & 1][j - 1][k - 1][0]) % mod; } else { if (j > 0) dp[i & 1][j][k][i > x] = (dp[i & 1][j][k][i > x] + dp[(i + 1) & 1][j - 1][k][i > x]) % mod; if (j > 0 && k > 0) dp[i & 1][j][k][i > x] = (dp[i & 1][j][k][i > x] + dp[(i + 1) & 1][j - 1][k - 1][i > x]) % mod; dp[i & 1][j][k][i > x] = (dp[i & 1][j][k][i > x] + dp[(i + 1) & 1][j][k][i > x]) % mod; if (k > 0) dp[i & 1][j][k][i > x] = (dp[i & 1][j][k][i > x] + dp[(i + 1) & 1][j][k - 1][i > x]) % mod; } } } for (int j = 0; j <= min(1ll * i, n); j++) { for (int k = 0; k <= j; k++) { dp[(i + 1) & 1][j][k][0] = 0; dp[(i + 1) & 1][j][k][1] = 0; } } } long long res = dp[m & 1][n][n][1]; for (int i = 1; i <= n; i++) { res = res * i % mod; } cout << res; }
|
module sw_reset
#(
parameter WIDTH=32,
parameter LOG2_RESET_CYCLES=8
)
(
input clk,
input resetn,
// Slave port
input slave_address, // Word address
input [WIDTH-1:0] slave_writedata,
input slave_read,
input slave_write,
input [WIDTH/8-1:0] slave_byteenable,
output slave_readdata,
output slave_waitrequest,
output reg sw_reset_n_out
);
reg sw_reset_n_out_r;
reg sw_reset_n_out_r2;
reg [LOG2_RESET_CYCLES:0] reset_count;
initial // Power up condition
reset_count <= {LOG2_RESET_CYCLES+1{1'b0}};
always@(posedge clk or negedge resetn)
if (!resetn)
reset_count <= {LOG2_RESET_CYCLES+1{1'b0}};
else if (slave_write)
reset_count <= {LOG2_RESET_CYCLES+1{1'b0}};
else if (!reset_count[LOG2_RESET_CYCLES])
reset_count <= reset_count + 2'b01;
always@(posedge clk)
sw_reset_n_out = sw_reset_n_out_r;
// Allow additional stages to get to global clock buffers.
always@(posedge clk) sw_reset_n_out_r2 = reset_count[LOG2_RESET_CYCLES];
always@(posedge clk) sw_reset_n_out_r = sw_reset_n_out_r2;
assign slave_waitrequest = !reset_count[LOG2_RESET_CYCLES];
assign slave_readdata = sw_reset_n_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 205; char str[20][N]; int n, m, des; int dp[20][2]; int call(int flr, int side) { if (flr == des) { if (side == 0) { int p = 0; for (int i = 1; i <= m; i++) if (str[flr][i] == 1 ) p = i; return p; } else { int p = m + 1; for (int i = m; i >= 1; i--) if (str[flr][i] == 1 ) p = i; return m + 1 - p; } } if (dp[flr][side] != -1) return dp[flr][side]; int ret = 1e9; if (side == 0) { ret = min(ret, m + 2 + call(flr - 1, 1)); int p = 0; for (int i = 1; i <= m; i++) if (str[flr][i] == 1 ) p = i; ret = min(ret, 2 * p + 1 + call(flr - 1, 0)); } else { ret = min(ret, m + 2 + call(flr - 1, 0)); int p = m + 1; for (int i = m; i >= 1; i--) if (str[flr][i] == 1 ) p = i; ret = min(ret, (m + 1 - p) * 2 + 1 + call(flr - 1, 1)); } return dp[flr][side] = ret; } int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); memset(dp, -1, sizeof(dp)); cin >> n >> m; for (int i = 0; i < n; i++) cin >> str[i]; des = n - 1; for (int i = n - 1; i >= 0; i--) { for (int j = 1; j <= m; j++) if (str[i][j] == 1 ) des = i; } cout << call(n - 1, 0) << n ; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 17249 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w16,
w17,
w17408,
w17409,
w128,
w17281,
w32,
w17249;
assign w1 = i_data0;
assign w128 = w1 << 7;
assign w16 = w1 << 4;
assign w17 = w1 + w16;
assign w17249 = w17281 - w32;
assign w17281 = w17409 - w128;
assign w17408 = w17 << 10;
assign w17409 = w1 + w17408;
assign w32 = w1 << 5;
assign o_data0 = w17249;
//multiplier_block area estimate = 6612.88314944412;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Note -- clocks must be synchronous (derived from the same source)
// Assumes alt_clk is running at a multiple of wb_clk
module wb_readback_mux
(input wb_clk_i,
input wb_rst_i,
input wb_stb_i,
input [15:0] wb_adr_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o,
input [31:0] word00,
input [31:0] word01,
input [31:0] word02,
input [31:0] word03,
input [31:0] word04,
input [31:0] word05,
input [31:0] word06,
input [31:0] word07,
input [31:0] word08,
input [31:0] word09,
input [31:0] word10,
input [31:0] word11,
input [31:0] word12,
input [31:0] word13,
input [31:0] word14,
input [31:0] word15
);
always @(posedge wb_clk_i)
if(wb_rst_i)
wb_ack_o <= 0;
else
wb_ack_o <= wb_stb_i & ~wb_ack_o;
always @(posedge wb_clk_i)
case(wb_adr_i[5:2])
0 : wb_dat_o <= word00;
1 : wb_dat_o <= word01;
2 : wb_dat_o <= word02;
3 : wb_dat_o <= word03;
4 : wb_dat_o <= word04;
5 : wb_dat_o <= word05;
6 : wb_dat_o <= word06;
7 : wb_dat_o <= word07;
8 : wb_dat_o <= word08;
9 : wb_dat_o <= word09;
10: wb_dat_o <= word10;
11: wb_dat_o <= word11;
12: wb_dat_o <= word12;
13: wb_dat_o <= word13;
14: wb_dat_o <= word14;
15: wb_dat_o <= word15;
endcase // case(addr_reg[3:0])
endmodule // wb_readback_mux
|
#include <bits/stdc++.h> using namespace std; char name[110][3000], text[110][3000]; int name_len[110], text_len[110]; bool found[110][110], dp[110][110]; int pre[110][110]; int chosen[110]; void variable_init() { memset(found, 0, sizeof found); memset(dp, 0, sizeof dp); } int main() { int tcase, n, m; scanf( %d , &tcase); while (tcase--) { variable_init(); scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , name[i]); name_len[i] = strlen(name[i]); } scanf( %d , &m); gets(text[0]); for (int i = 1; i <= m; i++) { gets(text[i]); text_len[i] = strlen(text[i]); if (text[i][0] != ? ) { for (int k = 1; k <= n; k++) { bool ok = true; if (text_len[i] < name_len[k]) ok = false; for (int l = 0; l < name_len[k] && ok; l++) { if (text[i][l] != name[k][l]) ok = false; } ok &= (name_len[k] == text_len[i] || (!isalpha(text[i][name_len[k]]) && !isdigit(text[i][name_len[k]]))); if (ok) { bool found_others = false; int pre_choose; if (i == 1) { found_others = true; pre_choose = -1; } for (int j = 1; j <= n; j++) if (j != k && dp[i - 1][j]) { found_others = true; pre_choose = j; break; } dp[i][k] = found_others; pre[i][k] = pre_choose; break; } } continue; } for (int j = 0; j < text_len[i]; j++) { if (!isalpha(text[i][j]) && !isdigit(text[i][j])) { for (int k = 1; k <= n; k++) { bool ok = true; if (text_len[i] - 1 - j < name_len[k]) ok = false; for (int l = j + 1; l <= j + name_len[k] && ok; l++) { if (text[i][l] != name[k][l - (j + 1)]) ok = false; } ok &= (j + name_len[k] + 1 == text_len[i] || (!isalpha(text[i][j + name_len[k] + 1]) && !isdigit(text[i][j + name_len[k] + 1]))); if (ok) found[i][k] = true; } } } for (int j = 1; j <= n; j++) { for (int k = 1; k <= n; k++) { if (i == 1) { if (!found[i][k]) { dp[i][k] = true; pre[i][k] = -1; } } else { if (j != k && dp[i - 1][j] && !found[i][k]) { dp[i][k] = true; pre[i][k] = j; } } } } } bool least_one = false; int last; for (int i = 1; i <= n; i++) { if (dp[m][i]) { least_one = true; last = i; } } if (!least_one) puts( Impossible ); else { for (int i = m; i >= 1; i--) { chosen[i] = last; last = pre[i][last]; } for (int i = 1; i <= m; i++) { if (text[i][0] == ? ) { printf( %s , name[chosen[i]]); int pos; for (int j = 1; j < text_len[i]; j++) if (text[i][j] == : ) { pos = j; break; } puts(text[i] + pos); } else { puts(text[i]); } } } } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 05/09/2017 07:54:56 PM
// Design Name:
// Module Name: DECODING_STAGE
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DECODING_STAGE #(
parameter ADDRESS_WIDTH = 32 ,
parameter DATA_WIDTH = 32 ,
parameter REG_ADD_WIDTH = 5 ,
parameter ALU_INS_WIDTH = 5 ,
parameter D_CACHE_LW_WIDTH = 3 ,
parameter D_CACHE_SW_WIDTH = 2 ,
parameter IMM_FORMAT_SELECT = 3 ,
parameter HIGH = 1'b1 ,
parameter LOW = 1'b0
) (
input CLK ,
input STALL_DECODING_STAGE ,
input CLEAR_DECODING_STAGE ,
input [REG_ADD_WIDTH - 1 : 0] RD_ADDRESS_IN ,
input [DATA_WIDTH - 1 : 0] RD_DATA_IN ,
input RD_WRITE_ENABLE_IN ,
input [DATA_WIDTH - 1 : 0] INSTRUCTION ,
input [ADDRESS_WIDTH - 1 : 0] PC_IN ,
input PC_VALID ,
output [ADDRESS_WIDTH - 1 : 0] PC_OUT ,
output [REG_ADD_WIDTH - 1 : 0] RS1_ADDRESS ,
output [REG_ADD_WIDTH - 1 : 0] RS2_ADDRESS ,
output [REG_ADD_WIDTH - 1 : 0] RD_ADDRESS_OUT ,
output [DATA_WIDTH - 1 : 0] RS1_DATA ,
output [DATA_WIDTH - 1 : 0] RS2_DATA ,
output [DATA_WIDTH - 1 : 0] IMM_OUTPUT ,
output [ALU_INS_WIDTH - 1 : 0] ALU_INSTRUCTION ,
output ALU_INPUT_1_SELECT ,
output ALU_INPUT_2_SELECT ,
output [D_CACHE_LW_WIDTH - 1 : 0] DATA_CACHE_LOAD ,
output [D_CACHE_SW_WIDTH - 1 : 0] DATA_CACHE_STORE ,
output WRITE_BACK_MUX_SELECT ,
output RD_WRITE_ENABLE_OUT
);
reg [ADDRESS_WIDTH - 1 : 0] pc_reg ;
reg [REG_ADD_WIDTH - 1 : 0] rs1_address_reg ;
reg [REG_ADD_WIDTH - 1 : 0] rs2_address_reg ;
reg [REG_ADD_WIDTH - 1 : 0] rd_address_reg ;
reg [DATA_WIDTH - 1 : 0] rs1_data_reg ;
reg [DATA_WIDTH - 1 : 0] rs2_data_reg ;
reg [DATA_WIDTH - 1 : 0] imm_output_reg ;
reg [ALU_INS_WIDTH - 1 : 0] alu_instruction_reg ;
reg alu_input_1_select_reg ;
reg alu_input_2_select_reg ;
reg [D_CACHE_LW_WIDTH - 1 : 0] data_cache_load_reg ;
reg [D_CACHE_SW_WIDTH - 1 : 0] data_cache_store_reg ;
reg write_back_mux_select_reg ;
reg rd_write_enable_reg ;
wire [REG_ADD_WIDTH - 1 : 0] rs1_address ;
wire [REG_ADD_WIDTH - 1 : 0] rs2_address ;
wire [REG_ADD_WIDTH - 1 : 0] rd_address_out ;
wire [DATA_WIDTH - 1 : 0] rs1_data ;
wire [DATA_WIDTH - 1 : 0] rs2_data ;
wire [IMM_FORMAT_SELECT - 1 : 0] imm_format ;
wire [DATA_WIDTH - 1 : 0] imm_output ;
wire [ALU_INS_WIDTH - 1 : 0] alu_instruction ;
wire alu_input_1_select ;
wire alu_input_2_select ;
wire [D_CACHE_LW_WIDTH - 1 : 0] data_cache_load ;
wire [D_CACHE_SW_WIDTH - 1 : 0] data_cache_store ;
wire write_back_mux_select ;
wire rd_write_enable_out ;
INSTRUCTION_DECODER instruction_decoder(
.INSTRUCTION(INSTRUCTION),
.IMM_FORMAT(imm_format),
.RS1_ADDRESS(rs1_address),
.RS2_ADDRESS(rs2_address),
.RD_ADDRESS(rd_address_out),
.ALU_INSTRUCTION(alu_instruction),
.ALU_INPUT_1_SELECT(alu_input_1_select),
.ALU_INPUT_2_SELECT(alu_input_2_select),
.DATA_CACHE_LOAD(data_cache_load),
.DATA_CACHE_STORE(data_cache_store),
.WRITE_BACK_MUX_SELECT(write_back_mux_select),
.RD_WRITE_ENABLE(rd_write_enable_out)
);
REGISTER_FILE register_file(
.CLK(CLK),
.RS1_ADDRESS(rs1_address),
.RS2_ADDRESS(rs2_address),
.RS1_DATA(rs1_data),
.RS2_DATA(rs2_data),
.RD_ADDRESS(RD_ADDRESS_IN),
.RD_DATA(RD_DATA_IN),
.RD_WRITE_EN(RD_WRITE_ENABLE_IN)
);
IMM_EXTENDER imm_extender(
.IMM_INPUT(INSTRUCTION[31:7]),
.IMM_FORMAT(imm_format),
.IMM_OUTPUT(imm_output)
);
always@(posedge CLK)
begin
if(CLEAR_DECODING_STAGE == LOW)
begin
if(STALL_DECODING_STAGE == LOW)
begin
if(PC_VALID == HIGH)
begin
pc_reg <= PC_IN ;
rs1_address_reg <= rs1_address ;
rs2_address_reg <= rs2_address ;
rd_address_reg <= rd_address_out ;
rs1_data_reg <= rs1_data ;
rs2_data_reg <= rs2_data ;
imm_output_reg <= imm_output ;
alu_instruction_reg <= alu_instruction ;
alu_input_1_select_reg <= alu_input_1_select ;
alu_input_2_select_reg <= alu_input_2_select ;
data_cache_load_reg <= data_cache_load ;
data_cache_store_reg <= data_cache_store ;
write_back_mux_select_reg <= write_back_mux_select ;
rd_write_enable_reg <= rd_write_enable_out ;
end
else
begin
pc_reg <= 32'b0 ;
rs1_address_reg <= 5'b0 ;
rs2_address_reg <= 5'b0 ;
rd_address_reg <= 5'b0 ;
rs1_data_reg <= 32'b0 ;
rs2_data_reg <= 32'b0 ;
imm_output_reg <= 32'b0 ;
alu_instruction_reg <= 5'b0 ;
alu_input_1_select_reg <= LOW ;
alu_input_2_select_reg <= LOW ;
data_cache_load_reg <= 3'b0 ;
data_cache_store_reg <= 2'b0 ;
write_back_mux_select_reg <= LOW ;
rd_write_enable_reg <= LOW ;
end
end
end
else
begin
pc_reg <= 32'b0 ;
rs1_address_reg <= 5'b0 ;
rs2_address_reg <= 5'b0 ;
rd_address_reg <= 5'b0 ;
rs1_data_reg <= 32'b0 ;
rs2_data_reg <= 32'b0 ;
imm_output_reg <= 32'b0 ;
alu_instruction_reg <= 5'b0 ;
alu_input_1_select_reg <= LOW ;
alu_input_2_select_reg <= LOW ;
data_cache_load_reg <= 3'b0 ;
data_cache_store_reg <= 2'b0 ;
write_back_mux_select_reg <= LOW ;
rd_write_enable_reg <= LOW ;
end
end
assign PC_OUT = pc_reg ;
assign RS1_ADDRESS = rs1_address_reg ;
assign RS2_ADDRESS = rs2_address_reg ;
assign RD_ADDRESS_OUT = rd_address_reg ;
assign RS1_DATA = rs1_data_reg ;
assign RS2_DATA = rs2_data_reg ;
assign IMM_OUTPUT = imm_output_reg ;
assign ALU_INSTRUCTION = alu_instruction_reg ;
assign ALU_INPUT_1_SELECT = alu_input_1_select_reg ;
assign ALU_INPUT_2_SELECT = alu_input_2_select_reg ;
assign DATA_CACHE_LOAD = data_cache_load_reg ;
assign DATA_CACHE_STORE = data_cache_store_reg ;
assign WRITE_BACK_MUX_SELECT = write_back_mux_select_reg ;
assign RD_WRITE_ENABLE_OUT = rd_write_enable_reg ;
endmodule
|
//-----------------------------------------------------------------------------
// setbit.v
//-----------------------------------------------------------------------------
//- (C) D. Cuartielles for Arduino, December 2015
//- GPLv3 License
//- based on previous work by Obijuan for BQ
//-----------------------------------------------------------------------------
//-- Componente "hola mundo" que simplemente pone a '1' su salida
//-- Es el ejemplo mas sencillo que se puede sintetizar en
//-- la fpga. Su principal utilidad es comprobar que toda la cadena de
//-- compilacion/sintesis/simulacion funciona correctamente
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//-- Modulo setbit
//--
//-- Definimos nuestro componente como un modulo que tiene solo una salida, que
//-- denominamos LED1. Este pin esta cableado a '1'
//-- para evitar que las otras salidas queden a nivel de voltaje incierto, hay
//-- que declararlas y asignarles una salida a nivel '0'
//-----------------------------------------------------------------------------
module setbit(
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output LED6,
output LED7,
output LED8
);
wire LED1;
wire LED2;
wire LED3;
wire LED4;
wire LED5;
wire LED6;
wire LED7;
wire LED8;
//-- Implementacion: el pin deseado esta cableado a '1'
// los demas estan cableados a '0'
assign LED1 = 1;
assign LED2 = 0;
assign LED3 = 0;
assign LED4 = 0;
assign LED5 = 0;
assign LED6 = 0;
assign LED7 = 0;
assign LED8 = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long b, r, g, w, i, j = 0, p = 0, n, m, s1, s2; cin >> n >> m >> s1 >> s2; if (s2 == 2) { cout << s1 << << s2 << endl; cout << 1 << << s2 << endl; for (i = 1; i <= n; i++) { if (i % 2 == 1) { for (j = 1; j <= m; j++) { if ((i == 1 && j == 2) || (i == s1 && j == 2)) { continue; } else cout << i << << j << endl; } } else { for (j = m; j >= 1; j--) { if ((i == 1 && j == 2) || (i == s1 && j == 2)) { continue; } else cout << i << << j << endl; } } } } else { cout << s1 << << s2 << endl; cout << s1 << << 2 << endl; cout << 1 << << 2 << endl; for (i = 1; i <= n; i++) { if (i % 2 == 1) { for (j = 1; j <= m; j++) { if ((i == 1 && j == 2) || (i == s1 && j == s2) || (i == s1 && j == 2)) { continue; } else cout << i << << j << endl; } } else { for (j = m; j >= 1; j--) { if ((i == 1 && j == 2) || (i == s1 && j == s2) || (i == s1 && j == 2)) { continue; } else cout << i << << j << endl; } } } } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_maccontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.5 2002/11/21 00:14:39 mohor
// TxDone and TxAbort changed so they're not propagated to the wishbone
// module when control frame is transmitted.
//
// Revision 1.4 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
`include "timescale.v"
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input MRxClk; // Receive clock (from PHY)
input TxReset; // Transmit reset
input RxReset; // Receive reset
input TPauseRq; // Transmit control frame (from host)
input [7:0] TxDataIn; // Transmit packet data byte (from host)
input TxStartFrmIn; // Transmit packet start frame input (from host)
input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
input TxEndFrmIn; // Transmit packet end frame input (from host)
input TxDoneIn; // Transmit packet done (from TxEthMAC)
input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
input PadIn; // Padding (input from registers)
input CrcEnIn; // Crc append (input from registers)
input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
input RxValid; // Received a valid packet
input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
input ReceivedPacketGood; // Received packet is good
input ReceivedLengthOK; // Length of the received packet is OK
input TxFlow; // Tx flow control (from registers)
input RxFlow; // Rx flow control (from registers)
input DlyCrcEn; // Delayed CRC enabled (from registers)
input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
input [47:0] MAC; // MAC address (from registers)
input RxStatusWriteLatched_sync2;
input r_PassAll;
output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
output TxDoneOut; // Transmit packet done (to host)
output TxAbortOut; // Transmit packet aborted (to host)
output TxUsedDataOut; // Transmit packet used data (to host)
output PadOut; // Padding (output to TxEthMAC)
output CrcEnOut; // Crc append (output to TxEthMAC)
output WillSendControlFrame;
output TxCtrlEndFrm;
output ReceivedPauseFrm;
output ControlFrmAddressOK;
output SetPauseTimer;
reg TxUsedDataOutDetected;
reg TxAbortInLatched;
reg TxDoneInLatched;
reg MuxedDone;
reg MuxedAbort;
wire Pause;
wire TxCtrlStartFrm;
wire [7:0] ControlData;
wire CtrlMux;
wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
wire BlockTxDone;
// Signal TxUsedDataOut was detected (a transfer is already in progress)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataOutDetected <= 1'b0;
else
if(TxDoneIn | TxAbortIn)
TxUsedDataOutDetected <= 1'b0;
else
if(TxUsedDataOut)
TxUsedDataOutDetected <= 1'b1;
end
// Latching variables
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
TxAbortInLatched <= 1'b0;
TxDoneInLatched <= 1'b0;
end
else
begin
TxAbortInLatched <= TxAbortIn;
TxDoneInLatched <= TxDoneIn;
end
end
// Generating muxed abort signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedAbort <= 1'b0;
else
if(TxStartFrmIn)
MuxedAbort <= 1'b0;
else
if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
MuxedAbort <= 1'b1;
end
// Generating muxed done signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedDone <= 1'b0;
else
if(TxStartFrmIn)
MuxedDone <= 1'b0;
else
if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
MuxedDone <= 1'b1;
end
// TxDoneOut
assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
// TxAbortOut
assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
// TxUsedDataOut
assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
// TxStartFrmOut
assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
// TxEndFrmOut
assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
// TxDataOut[7:0]
assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
// PadOut
assign PadOut = PadIn | SendingCtrlFrm;
// CrcEnOut
assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
// Connecting receivecontrol module
eth_receivecontrol receivecontrol1
(
.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
.r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
);
eth_transmitcontrol transmitcontrol1
(
.MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
.TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
.TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
.MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
.CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
);
endmodule
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// ###########################################################################
// # MEMORY TRANSACTION TRANSLATOR
// #
// # This block uses the upper 12 bits [31:20] of a memory address as an index
// # to read an entry from a table.
// #
// # Writes are done from the register config interface
// #
// # The table can be configured as 12 bits wide or 44 bits wide.
// #
// # 32bit address output = {table_data[11:0],dstaddr[19:0]}
// # 64bit address output = {table_data[43:0],dstaddr[19:0]}
// #
// ############################################################################
module emmu (/*AUTOARG*/
// Outputs
reg_rdata, emesh_access_out, emesh_packet_out,
// Inputs
wr_clk, rd_clk, nreset, mmu_en, reg_access, reg_packet,
emesh_access_in, emesh_packet_in, emesh_wait_in
);
//#####################################################################
//# INTERFACE
//#####################################################################
// parameters
parameter AW = 32; // address width
parameter MW = 48; // width of table
parameter MAW = 12; // memory addres width (entries = 1<<MAW)
localparam PW = 2*AW+40; // packet width
//reset
input nreset; // async active low reset
//config
input mmu_en; // enables mmu (by config register)
//write port
input wr_clk; // single clock
input reg_access; // valid packet
input [PW-1:0] reg_packet; // packet
output [31:0] reg_rdata; // readback data
//read port
input rd_clk; // single clock
input emesh_access_in; // valid packet
input [PW-1:0] emesh_packet_in; // input packet
input emesh_wait_in; // pushback
//translated packet
output emesh_access_out;// valid packet
output [PW-1:0] emesh_packet_out;// output packet
//#####################################################################
//# BODY
//#####################################################################
//wires + regs
reg emesh_access_out;
reg [PW-1:0] emesh_packet_reg;
wire [63:0] emesh_dstaddr_out;
wire [MW-1:0] emmu_lookup_data;
wire [MW-1:0] mem_wem;
wire [MW-1:0] mem_data;
wire [AW-1:0] emesh_dstaddr_in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] reg_ctrlmode; // From pe2 of packet2emesh.v
wire [AW-1:0] reg_data; // From pe2 of packet2emesh.v
wire [1:0] reg_datamode; // From pe2 of packet2emesh.v
wire [AW-1:0] reg_dstaddr; // From pe2 of packet2emesh.v
wire [AW-1:0] reg_srcaddr; // From pe2 of packet2emesh.v
wire reg_write; // From pe2 of packet2emesh.v
// End of automatics
//###########################
//# WRITE LOGIC
//###########################
/*packet2emesh AUTO_TEMPLATE ( .\(.*\)_in (reg_\1[]));*/
packet2emesh #(.AW(AW))
pe2 (/*AUTOINST*/
// Outputs
.write_in (reg_write), // Templated
.datamode_in (reg_datamode[1:0]), // Templated
.ctrlmode_in (reg_ctrlmode[4:0]), // Templated
.dstaddr_in (reg_dstaddr[AW-1:0]), // Templated
.srcaddr_in (reg_srcaddr[AW-1:0]), // Templated
.data_in (reg_data[AW-1:0]), // Templated
// Inputs
.packet_in (reg_packet[PW-1:0])); // Templated
//write controls
assign mem_wem[MW-1:0] = ~reg_dstaddr[2] ? {{(MW-32){1'b0}},32'hFFFFFFFF} :
{{(MW-32){1'b1}},32'h00000000};
assign mem_write = reg_access &
reg_write;
assign mem_data[MW-1:0] = {reg_data[31:0], reg_data[31:0]};
//###########################
//# EMESh PACKET DECODE
//###########################
packet2emesh #(.AW(32))
p2e (// Outputs
.write_in (),
.datamode_in (),
.ctrlmode_in (),
.dstaddr_in (emesh_dstaddr_in[AW-1:0]),
.srcaddr_in (),
.data_in (),
// Inputs
.packet_in (emesh_packet_in[PW-1:0]));
//###########################
//# LOOKUP TABLE
//###########################
oh_memory_dp #(.DW(MW),
.DEPTH(4096))
memory_dp (//read port
.rd_dout (emmu_lookup_data[MW-1:0]),
.rd_en (emesh_access_in),
.rd_addr (emesh_dstaddr_in[31:20]),
.rd_clk (rd_clk),
//write port
.wr_en (mem_write),
.wr_wem (mem_wem[MW-1:0]),
.wr_addr (reg_dstaddr[14:3]),
.wr_din (mem_data[MW-1:0]),
.wr_clk (wr_clk)
);
//###########################
//# OUTPUT PACKET
//###########################
//pipeline (compensates for 1 cycle memory access)
always @ (posedge rd_clk)
if (!nreset)
emesh_access_out <= 1'b0;
else if(~emesh_wait_in)
emesh_access_out <= emesh_access_in;
always @ (posedge rd_clk)
if(~emesh_wait_in)
emesh_packet_reg[PW-1:0] <= emesh_packet_in[PW-1:0];
//like base register for trampolining to 64 bit space
assign emesh_dstaddr_out[63:0] = mmu_en ? {emmu_lookup_data[43:0],
emesh_packet_reg[27:8]} :
{32'b0,emesh_packet_reg[39:8]};
//concatenating output packet
assign emesh_packet_out[PW-1:0] = {emesh_packet_reg[PW-1:40],
emesh_dstaddr_out[31:0],
emesh_packet_reg[7:0]
};
//assign emesh_packet_hi_out[31:0] = emesh_dstaddr_out[63:32];
endmodule // emmu
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../memory/hdl" "../../emesh/hdl")
// End:
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#include <bits/stdc++.h> using namespace std; int main() { long int a, b, c; cin >> a >> b >> c; a = abs(a) + abs(b); if (a > c) cout << NO << endl; else { if ((c - a) % 2 == 0) cout << YES << endl; else cout << NO << endl; } }
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#include <bits/stdc++.h> using namespace std; const long long inf = 1e15; const long double pi = 3.141592; const long long mod1 = 1e9 + 7; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int main() { int n; cin >> n; vector<int> d(n + 1); set<int> set; int x = 1, y = 1; int m = 1; for (int i = 1; i <= n; i++) { cin >> d[i]; m = max(m, d[i]); } for (int i = 1; i <= n; i++) { if (m % d[i] == 0 && set.find(d[i]) == set.end()) { set.insert(d[i]); d[i] = -1; } } for (int i = 1; i <= n; i++) { y = max(y, d[i]); } cout << m << << y; return 0; }
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module autolisp_top (/*AUTOARG*/);
/* autolisp_inst AUTO_TEMPLATE (
.\(.*\)A (\1_@"(eval tense)"_A),
.\(.*\)B (\1_@"(eval tense)"_B),
);
*/
/* AUTO_LISP(setq tense "is") */
autolisp_inst AUTOLISP_INST_I0
(/*AUTOINST*/
// Outputs
.result (result),
// Inputs
.portA (port_is_A), // Templated
.busA (bus_is_A), // Templated
.portB (port_is_B), // Templated
.busB (bus_is_B)); // Templated
/* AUTO_LISP(setq tense "was") */
autolisp_inst AUTOLISP_INST_I1
(/*AUTOINST*/
// Outputs
.result (result),
// Inputs
.portA (port_was_A), // Templated
.busA (bus_was_A), // Templated
.portB (port_was_B), // Templated
.busB (bus_was_B)); // Templated
endmodule
module autolisp_inst (/*AUTOARG*/
// Outputs
result,
// Inputs
portA, busA, portB, busB
);
input portA;
input [3:0] busA;
input portB;
input [1:0] busB;
output result;
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const long long INF = 1e18 + 5; const int MAXN = 1e6; const int base = 317; const long long bs = 1e5 + 1; const long long mod = 998244353; struct node { node *left, *right; int val; node(node* l = NULL, node* r = NULL, int v = 0) { left = l; right = r; val = v; } }; node* version[N]; int n, m, d[N], up[21][N]; int tin[N], tout[N], timer; vector<int> g[N]; void build(node* v, int L, int R) { if (L == R) return; int md = (L + R) >> 1; v->left = new node(); v->right = new node(); build(v->left, L, md); build(v->right, md + 1, R); } node* upd(node* v, int L, int R, int pos, int val) { if (L == R) { return new node(NULL, NULL, val); } node* nw = new node(); int md = (L + R) >> 1; if (md >= pos) { nw->right = v->right; nw->left = upd(v->left, L, md, pos, val); } else { nw->left = v->left; nw->right = upd(v->right, md + 1, R, pos, val); } nw->val = nw->left->val + nw->right->val; return nw; } void dfs(int v, int p = 0) { d[v] = d[p] + 1; up[0][v] = p; tin[v] = ++timer; for (int i = 1; i <= 20; i++) { up[i][v] = up[i - 1][up[i - 1][v]]; } for (int to : g[v]) { if (to != p) { dfs(to, v); } } tout[v] = ++timer; } int lca(int a, int b) { if (d[a] > d[b]) { swap(a, b); } for (int i = 20; i >= 0; i--) { if (d[a] <= d[up[i][b]]) { b = up[i][b]; } } if (a == b) return a; for (int i = 20; i >= 0; i--) { if (up[i][a] != up[i][b]) { a = up[i][a]; b = up[i][b]; } } return up[0][a]; } int get(node* v, int L, int R, int l, int r) { if (L > r || l > R) return 0; if (l <= L && R <= r) return v->val; int md = (L + R) >> 1; return get(v->left, L, md, l, r) + get(v->right, md + 1, R, l, r); } int calc(int u, int v, int y1, int y2) { int r = tin[u], l = tin[v]; return d[u] - d[v] + 1 - (get(version[y2], 1, 2 * n, l, r) - get(version[y1], 1, 2 * n, l, r)); } int getk(int a, int k, int y1, int y2) { for (int i = 20; i >= 0; i--) { int count = calc(a, up[i][a], y1, y2) - calc(a, a, y1, y2); if (count < k) { k -= count; a = up[i][a]; } } return up[0][a]; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) { int p; cin >> p; g[i].push_back(p); g[p].push_back(i); } dfs(g[0][0], g[0][0]); version[0] = new node(); build(version[0], 0, n * 2); cin >> m; for (int i = 1; i <= m; i++) { int t; cin >> t; if (t == 1) { int id; cin >> id; version[i] = upd(version[i - 1], 1, 2 * n, tin[id], 1); version[i] = upd(version[i], 1, 2 * n, tout[id], -1); } else { int a, b, k, y; cin >> a >> b >> k >> y; version[i] = version[i - 1]; int lc = lca(a, b); int len1 = calc(a, lc, y, i) - calc(a, a, y, i), len2 = calc(b, lc, y, i) - calc(b, b, y, i); int count = len1 + len2 - calc(lc, lc, y, i); if (count < k) { cout << -1 << n ; continue; } if (len1 >= k) { cout << getk(a, k, y, i) << n ; } else { cout << getk(b, count - k + 1, y, i) << n ; } } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int M = 10005; vector<int> g[M]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n - 1; i++) { int a, b; scanf( %d %d , &a, &b); g[a].push_back(b); g[b].push_back(a); } int ans = 0; for (int i = 1; i <= n; i++) { for (int j = 0; j < g[i].size(); j++) { int v = g[i][j]; ans += ((int)g[v].size()) - 1; } } cout << ans / 2; return 0; }
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#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; vector<vector<long long>> adj(n + 1, vector<long long>(n + 1, 0)); for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= n; j++) { cin >> adj[i][j]; } } vector<long long> del(n + 1), v, ans; for (long long i = 1; i <= n; i++) cin >> del[i]; for (long long k = n; k >= 1; k--) { v.push_back(del[k]); for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= n; j++) { adj[i][j] = min(adj[i][j], adj[i][del[k]] + adj[del[k]][j]); } } long long sum = 0; for (long long i = 0; i < v.size(); i++) { for (long long j = 0; j < v.size(); j++) { sum += adj[v[i]][v[j]]; } } ans.push_back(sum); } for (long long i = ans.size() - 1; i >= 0; i--) { cout << ans[i] << ; } cout << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long qu = 1; for (long long cas = 1; cas <= qu; cas++) { solve(); } }
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#include <bits/stdc++.h> using namespace std; void solve(long long int input) { long long int n; cin >> n; double a[n], b[n]; for (long long int i = 0; i < n; i++) cin >> a[i]; for (long long int i = 0; i < n; i++) cin >> b[i]; map<long double, long long int> mp; long long int ans = 0; long long int j = 0; for (long long int i = 0; i < n; i++) { if (a[i] == 0 && b[i] == 0) { j++; continue; } if (a[i] == 0) continue; mp[(b[i] / (a[i]))]++; ans = max(ans, mp[(b[i] / (a[i]))]); } cout << ans + j << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int x = 1; for (long long int i = 1; i <= x; i++) solve(i); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long INF = (long long)4e18 + 7; inline void minimize(long long &x, const long long &y) { if (x > y) x = y; } struct help { int x, s, r; help() { x = s = r = 0; } void input(void) { x = s = r = 0; int k; scanf( %d%d%d , &x, &r, &k); for (int zz = 0; zz < (k); zz = zz + 1) { int v; scanf( %d , &v); v--; s |= (1 << (v)); } } bool operator<(const help &a) const { return (r < a.r); } }; long long f[(1 << (20)) + 7]; help a[111]; int n, m, b; void init(void) { scanf( %d%d%d , &n, &m, &b); for (int i = (1); i <= (n); i = i + 1) a[i].input(); sort(a + 1, a + n + 1); } void process(void) { for (int i = 0; i < ((1 << (m))); i = i + 1) f[i] = INF; f[0] = 0; long long res = INF; for (int i = (1); i <= (n); i = i + 1) { long long cost = 1LL * b * a[i].r; for (int j = 0; j < ((1 << (m))); j = j + 1) if (f[j] < INF) minimize(f[j | a[i].s], f[j] + a[i].x); minimize(res, f[(1 << (m)) - 1] + cost); } if (res < INF) cout << res; else cout << -1; } int main(void) { init(); process(); return 0; }
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#include <bits/stdc++.h> using namespace std; double t, k, d, start = 0, sum = 0; int main() { scanf( %lf%lf%lf , &k, &d, &t); if ((long long)k % (long long)d == 0) printf( %.1f n , t); else if (k >= t) printf( %.1f n , t); else { if (k > d) { long long a = k / d; d *= a + 1; } long long x = (long long)t / (k + (d - k) / 2); start = (double)x * d; sum = (double)x * (k + (d - k) / 2); sum = t - sum; if (sum > k) start += k + (sum - k) * 2; else start += sum; printf( %.9f n , start); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s = to_string(n); int m = s.size(); vector<int> v; for (int i = 9 * m; i >= 0; i--) { int j = n - i; int sum = 0; for (sum = 0; j > 0; j /= 10) sum += j % 10; if (sum == i) v.push_back(n - i); } cout << v.size() << endl; for (auto i : v) cout << i << endl; }
|
/*
* This module is made for use in bsg_cams, managing the valids and tags for each entry.
* We separate v_rs and tags so that we can support reset with minimal hardware.
* This module does not protect against setting multiple entries to the same value -- this must be
* prevented at a higher protocol level, if desired
*/
`include "bsg_defines.v"
module bsg_cam_1r1w_tag_array
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter multiple_entries_p = 0
, parameter safe_els_lp = `BSG_MAX(els_p,1)
)
(input clk_i
, input reset_i
// zero or one-hot
, input [safe_els_lp-1:0] w_v_i
// Mutually exclusive set or clear
, input w_set_not_clear_i
// Tag to set or clear
, input [width_p-1:0] w_tag_i
// Vector of empty CAM entries
, output logic [safe_els_lp-1:0] w_empty_o
// Async read
, input r_v_i
// Tag to match on read
, input [width_p-1:0] r_tag_i
// one or zero-hot
, output logic [safe_els_lp-1:0] r_match_o
);
logic [safe_els_lp-1:0][width_p-1:0] tag_r;
logic [safe_els_lp-1:0] v_r;
if (els_p == 0)
begin : zero
assign w_empty_o = '0;
assign r_match_o = '0;
end
else
begin : nz
for (genvar i = 0; i < els_p; i++)
begin : tag_array
bsg_dff_reset_en
#(.width_p(1))
v_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(w_v_i[i])
,.data_i(w_set_not_clear_i)
,.data_o(v_r[i])
);
bsg_dff_en
#(.width_p(width_p))
tag_r_reg
(.clk_i(clk_i)
,.en_i(w_v_i[i] & w_set_not_clear_i)
,.data_i(w_tag_i)
,.data_o(tag_r[i])
);
assign r_match_o[i] = r_v_i & v_r[i] & (tag_r[i] == r_tag_i);
assign w_empty_o[i] = ~v_r[i];
end
end
//synopsys translate_off
always_ff @(negedge clk_i) begin
assert(multiple_entries_p || reset_i || $countones(r_match_o) <= 1)
else $error("Multiple similar entries are found in match_array\
%x while multiple_entries_p parameter is %d\n", r_match_o,
multiple_entries_p);
assert(reset_i || $countones(w_v_i & {safe_els_lp{w_set_not_clear_i}}) <= 1)
else $error("Inv_r one-hot write address %b\n", w_v_i);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_cam_1r1w_tag_array)
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, num; cin >> n >> k; num = (n) * (n - 1) / 2; if (num <= k) cout << no solution << endl; else for (int i = 1; i <= n; i++) cout << 1 << << i << endl; }
|
/**
# XcvrSpi #
Simple SPI transceiver with FIFOs. 8 bit interface, but continously clocks out
data. CS stays asserted until TX FIFO is empty.
*/
///////////////////////////////////////////////////////////////////////////
// MODULE DECLARATION
///////////////////////////////////////////////////////////////////////////
module XcvrSpiSlave #(
parameter LOG2_DEPTH = 4
)
(
// INPUTS
input clk, ///< System Clock
input rst, ///< Reset, synchronous and active high
// Data Interface Inputs
input [7:0] dataIn, ///< Data to send
input write, ///< Strobe to write to TX FIFO
input read, ///< Strove to read from RX FIFO
input cpol, ///< SPI data polarity
input cpha, ///< SPI clock phase
// SPI Signals
input nCs, ///< ~Chip select
input sck, ///< SPI clock
input miso, ///< Master in, slave out
output mosi, ///< Master out, slave in
// FIFO Status
output txDataPresent, ///< When high, interface has data to send back
output txHalfFull, ///< TX FIFO is getting full
output txFull, ///< TX FIFO is full
output rxDataPresent, ///< RX FIFO has data available
output rxHalfFull, ///< RX FIFO is getting full
output rxFull, ///< RX FIFO is full
// Data Interface Outputs
output [7:0] dataOut ///< Data received
);
///////////////////////////////////////////////////////////////////////////
// SIGNAL DECLARATIONS
///////////////////////////////////////////////////////////////////////////
wire [7:0] txData;
wire [7:0] rxData;
reg [7:0] dataInReg;
reg [7:0] dataOutReg;
reg [7:0] shiftReg;
reg [2:0] spiCount;
reg busy;
reg dataOutReady;
reg mosiCapture;
reg sckD1;
reg txRead;
reg rxWrite;
///////////////////////////////////////////////////////////////////////////
// MAIN CODE
///////////////////////////////////////////////////////////////////////////
// TX FIFO
if (LOG2_DEPTH > 0) begin
Fifo #(
.WIDTH(8), ///< Width of data word
.LOG2_DEPTH(LOG2_DEPTH) ///< log2(depth of FIFO). Must be an integer
)
txFifo (
.clk(clk), ///< System clock
.rst(rst), ///< Reset FIFO pointer
.write(write), ///< Write strobe (1 clk)
.read(txRead), ///< Read strobe (1 clk)
.dataIn(dataIn), ///< [7:0] Data to write
// Outputs
.dataOut(txData), ///< [7:0] Data from FIFO
.dataPresent(txDataPresent), ///< Data is present in FIFO
.halfFull(txHalfFull), ///< FIFO is half full
.full(txFull) ///< FIFO is full
);
end
else begin
// Create a simple busy bit and register the data to be sent
assign txData = dataInReg;
assign txDataPresent = busy;
assign txHalfFull = busy;
assign txFull = busy;
always @(posedge clk) begin
if (write) begin
dataInReg <= dataIn;
end
busy <= busy ? (~txRead & busy) : write;
end
end
// RX FIFO
if (LOG2_DEPTH > 0) begin
Fifo #(
.WIDTH(8), ///< Width of data word
.LOG2_DEPTH(LOG2_DEPTH) ///< log2(depth of FIFO). Must be an integer
)
rxFifo (
.clk(clk), ///< System clock
.rst(rst), ///< Reset FIFO pointer
.write(rxWrite), ///< Write strobe (1 clk)
.read(read), ///< Read strobe (1 clk)
.dataIn(rxData), ///< [7:0] Data to write
// Outputs
.dataOut(dataOut), ///< [7:0] Data from FIFO
.dataPresent(rxDataPresent), ///< Data is present in FIFO
.halfFull(rxHalfFull), ///< FIFO is half full
.full(rxFull) ///< FIFO is full
);
end
else begin
// Create a simple rxReady bit and register received data
assign dataOut = dataOutReg;
assign rxDataPresent = dataOutReady;
assign rxHalfFull = dataOutReady;
assign rxFull = dataOutReady;
always @(posedge clk) begin
if (rxWrite) begin
dataOutReg <= rxData;
end
dataOutReady <= dataOutReady ? (dataOutReady & ~read) : rxWrite;
end
end
initial begin
dataOutReg = 'b0;
dataInReg = 'b0;
shiftReg = 'd0;
spiCount = 'd7;
busy = 1'b0;
dataOutReady = 1'b0;
mosiCapture = 1'b0;
sckD1 = 1'b0;
txRead = 1'b0;
rxWrite = 1'b0;
end
assign miso = shiftReg[7]; // Slave out is MSB of shift register
assign rxData = {shiftReg[6:0], mosiCapture};
always @(posedge clk) begin
sckD1 <= sck;
if (nCs) begin
spiCount <= 'd7;
shiftReg <= txData;
txRead <= 1'b0;
rxWrite <= 1'b0;
end
else if ((sck ^sckD1) && !(sck ^ cpol ^ cpha)) begin
spiCount <= spiCount - 'd1;
if (spiCount == 'd0) begin
shiftReg <= txData;
txRead <= 1'b1;
end
else begin
shiftReg <= {shiftReg[6:0], mosiCapture};
txRead <= 1'b0;
end
end
else begin
spiCount <= spiCount;
shiftReg <= shiftReg;
txRead <= 1'b0;
end
// MISO data capture
if ((sck ^ sckD1) && (sck ^ cpol ^ cpha)) begin
mosiCapture <= mosi;
if (spiCount == 'd0) begin
rxWrite <= 1'b1;
end
else begin
rxWrite <= 1'b0;
end
end
else begin
mosiCapture <= mosiCapture;
rxWrite <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long int a[100]; for (int i = 0; i < n; i++) { cin >> a[i]; } int m = a[0]; for (int i = 1; i < n; i++) { if (a[i] > m) { m = a[i]; } } int o = 0; for (int i = 0; i < n; i++) { o = o + (m - a[i]); } cout << o; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int mod = 998244353; long long int expo(long long int base, long long int exponent, long long int mod) { long long int ans = 1; while (exponent != 0) { if (exponent & 1) ans = (1LL * ans * base) % mod; base = (1LL * base * base) % mod; exponent >>= 1; } return ans % mod; } vector<long long int> g[100005]; long long int val[100005], dist[100005]; void dfs(long long int node, long long int par, long long int d) { dist[node] = d; if (g[node].size() == 1) val[par]++; for (auto x : g[node]) { if (x != par) dfs(x, node, d + 1); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tests = 1; while (tests--) { long long int i, j, u, v, n; cin >> n; for (long long int i = 1; i <= n - 1; i++) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } long long int root = -1; for (long long int i = 1; i <= n; i++) { if (g[i].size() > 1) { root = i; break; } } dfs(root, 0, 0); long long int mx = n - 1, mn; long long int odd = 0, even = 0; for (long long int i = 1; i <= n; i++) { if (g[i].size() > 1) continue; if (dist[i] % 2) odd++; else even++; } if (odd == 0 || even == 0) mn = 1; else mn = 3; for (long long int i = 1; i <= n; i++) { mx -= max(0LL, val[i] - 1); } cout << mn << << mx; } cerr << nTime elapsed: << 1000 * clock() / CLOCKS_PER_SEC << ms n ; return 0; }
|
#include <bits/stdc++.h> int min(int a, int b) { return (a < b ? a : b); } int max(int a, int b) { return (a > b ? a : b); } int main() { char a[10], b[10]; int x, y; scanf( %s n%s , a, b); if (strcmp(a, sunday ) == 0) x = 0; else if (strcmp(a, monday ) == 0) x = 1; else if (strcmp(a, tuesday ) == 0) x = 2; else if (strcmp(a, wednesday ) == 0) x = 3; else if (strcmp(a, thursday ) == 0) x = 4; else if (strcmp(a, friday ) == 0) x = 5; else if (strcmp(a, saturday ) == 0) x = 6; if (strcmp(b, sunday ) == 0) y = 0; else if (strcmp(b, monday ) == 0) y = 1; else if (strcmp(b, tuesday ) == 0) y = 2; else if (strcmp(b, wednesday ) == 0) y = 3; else if (strcmp(b, thursday ) == 0) y = 4; else if (strcmp(b, friday ) == 0) y = 5; else if (strcmp(b, saturday ) == 0) y = 6; if (x == y) printf( YES ); else if (y == (x + 2) % 7) printf( YES ); else if (y == (x + 3) % 7) printf( YES ); else printf( NO ); return 0; }
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2016-2020 NUDT, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//Vendor: NUDT
//Version: 0.1
//Filename: parser.v
//Target Device: Altera
//Dscription:
// 1)receive & parse 9 tuple from pkt
// 2)retransmit pkt to next module after parsed all key field
// 3)only support ipv4
//
// pkt type:
// pkt_site 2bit : 2'b01 pkt head / 2'b11 pkt body / 2'b10 pkt tail
// invalid 4bit : the invalid byte sum of every payload cycle
// payload 128bit : pkt payload
//
//
// 9tuple struct: {
// SMAC 48bit : source mac address
// DMAC 48bit : destination mac address
// ETH_TYPE 16bit : ethernet head's next layer type field
// SIP 32bit : source ip address
// DIP 32bit : destination ip address
// IP_PROTO 8bit : ipv4 head's next layer protocol field
// SPORT 16bit : source port(tcp or udp can be judged by IP_PROTO)
// DPORT 16bit : destination port(tcp or udp can be judged by IP_PROTO)
// INPORT 8bit : inport number
// RSV 64bit : reserve field,must set all bit to 1
// }
//
//Author :
//Revision List:
// rn1:
// date: 2016/10/09
// modifier: lxj
// description: rearrange 9tuple's struct for adapt software difine
// rn2:
// date: 2016/10/11
// modifier: lxj
// description: inport in metadata is orgnize by slotid+inportnumber, old code just use inportnumber
// rn3: date: modifier: description:
//
module parser(
input clk,
input rst_n,
//input pkt from port
input port2parser_data_wr,
input [133:0] port2parser_data,
input port2parser_valid_wr,
input port2parser_valid,
output parser2port_alf,
//parse key which transmit to lookup
output reg parser2lookup_key_wr,
output [287:0] parser2lookup_key,
//transport to next module
output parser2next_data_wr,
output [133:0] parser2next_data,
input next2parser_alf
);
//***************************************************
// Intermediate variable Declaration
//***************************************************
//all wire/reg/parameter variable
//should be declare below here
reg [7:0] pkt_step_count,pkt_step_count_inc;
reg [7:0] INPORT;
reg [47:0] DMAC;
reg [47:0] SMAC;
reg [15:0] ETH_TYPE;
reg [7:0] IP_PROTO;
reg [31:0] SIP;
reg [31:0] DIP;
reg [15:0] SPORT;
reg [15:0] DPORT;
wire is_ipv4;
wire is_tcp;
wire is_udp;
//***************************************************
// Retransmit Pkt
//***************************************************
assign parser2next_data_wr = port2parser_data_wr;
assign parser2next_data = port2parser_data;
assign parser2port_alf = next2parser_alf;
//***************************************************
// Pkt Step Count
//***************************************************
//count the pkt cycle step for locate parse procotol field
//compare with pkt_step_count, pkt_step count_inc always change advance 1 cycle
always @* begin
if(port2parser_data_wr == 1'b1) begin//a pkt is receiving
if(port2parser_data[133:132] == 2'b01) begin//pkt head
pkt_step_count_inc = 8'b0;
end
else begin
pkt_step_count_inc = pkt_step_count + 8'd1;
end
end
else begin
pkt_step_count_inc = pkt_step_count;
end
end
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
pkt_step_count <= 8'b0;
end
else begin
pkt_step_count <= pkt_step_count_inc;
end
end
//***************************************************
// Key Field Parse
//***************************************************
//------INPORT/DMAC/SMAC/ETH_TYPE Field Parse----------
always @(posedge clk) begin
if((port2parser_data_wr == 1'b1) && (pkt_step_count_inc == 8'd0)) begin
INPORT <= {5'b0,port2parser_data[110],port2parser_data[59:58]};//slot id + inport number
end
else begin
INPORT <= INPORT;
end
end
//------DMAC/SMAC/ETH_TYPE Field Parse----------
always @(posedge clk) begin
if((port2parser_data_wr == 1'b1) && (pkt_step_count_inc == 8'd2)) begin//eth head
DMAC <= port2parser_data[127:80];
SMAC <= port2parser_data[79:32];
ETH_TYPE <= port2parser_data[31:16];
end
else begin
DMAC <= DMAC;
SMAC <= SMAC;
ETH_TYPE <= ETH_TYPE;
end
end
assign is_ipv4 = (ETH_TYPE == 16'h0800);
//------IP_PROTO/SIP/DIP Field Parse----------
always @(posedge clk) begin
if((port2parser_data_wr == 1'b1) && (pkt_step_count_inc == 8'd3)) begin
//second pkt line, ip head
IP_PROTO <= port2parser_data[71:64];
SIP <= port2parser_data[47:16];
DIP[31:16] <= port2parser_data[15:0];
end
else if((port2parser_data_wr == 1'b1) && (pkt_step_count_inc == 8'd4)) begin
//third pkt line, destination ip last 4 byte
DIP[15:0] <= port2parser_data[127:112];//parse DIP's last 4 byte
end
else begin
IP_PROTO <= IP_PROTO;
SIP <= SIP;
DIP <= DIP;
end
end
assign is_tcp = (is_ipv4) && (IP_PROTO == 16'h6);
assign is_udp = (is_ipv4) && (IP_PROTO == 16'h11);
//------SPORT/DPORT Field Parse----------
always @(posedge clk) begin
if((port2parser_data_wr == 1'b1) && (pkt_step_count_inc == 8'd4)) begin
SPORT <= port2parser_data[111:96];
DPORT <= port2parser_data[95:80];
end
else begin
SPORT <= SPORT;
DPORT <= DPORT;
end
end
//***************************************************
// Key Field Wrapper
//***************************************************
assign parser2lookup_key[287:240] = SMAC;
assign parser2lookup_key[239:192] = DMAC;
assign parser2lookup_key[191:176] = ETH_TYPE;
assign parser2lookup_key[175:144] = (is_ipv4) ? SIP : 32'hffff_ffff;
assign parser2lookup_key[143:112] = (is_ipv4) ? DIP : 32'hffff_ffff;
assign parser2lookup_key[111:104] = (is_ipv4) ? IP_PROTO : 8'hff;
assign parser2lookup_key[103:88] = (is_tcp || is_udp) ? SPORT : 16'hffff;
assign parser2lookup_key[87:72] = (is_tcp || is_udp) ? DPORT : 16'hffff;
assign parser2lookup_key[71:64] = INPORT;
assign parser2lookup_key[63:0] = 64'hffff_ffff_ffff_ffff;
always @(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
parser2lookup_key_wr <= 1'b0;
end
else begin
if(port2parser_valid_wr == 1'b1) begin
//send key at last cycle of pkt
parser2lookup_key_wr <= 1'b1;
end
else begin
parser2lookup_key_wr <= 1'b0;
end
end
end
endmodule
/**********************************
Initial Inst
parser parser(
.clk(),
.rst_n(),
//input pkt from port
.port2parser_data_wr(),
.port2parser_data(),
.port2parser_valid_wr(),
.port2parser_valid(),
.parser2port_alf(),
//parse key which transmit to lookup
.parser2lookup_key_wr(),
.parser2lookup_key(),
//transport to next module
.parser2next_data_wr(),
.parser2next_data(),
.next2parser_alf()
);
**********************************/
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_BEHAVIORAL_V
`define SKY130_FD_SC_LP__FAH_BEHAVIORAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__fah (
COUT,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int binSearch(int *a, int n, int x) { int l = 0; int r = n - 1; while (l < r) { int mid = (l + r) / 2; if (a[mid] == x) return mid; else if (a[mid] < x) l = mid + 1; else r = mid - 1; } return -1; } int main() { map<long long, long long> mp; int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; mp[a[i]] = i + 1; } int q; cin >> q; long long cntFirst = 0, cntSecond = 0; for (int i = 0; i < q; i++) { int x; cin >> x; long long res = mp[x]; cntFirst += res; cntSecond += (n - res + 1); } cout << cntFirst << << cntSecond; return 0; }
|
// DESCRIPTION: Verilator: Interface parameter getter
//
// A test of the import parameter used with modport
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader
// SPDX-License-Identifier: CC0-1.0
interface test_if #(parameter integer FOO = 1);
// Interface variable
logic data;
localparam integer BAR = FOO + 1;
// Modport
modport mp(
import getFoo,
output data
);
function integer getFoo ();
return FOO;
endfunction
endinterface // test_if
function integer identity (input integer x);
return x;
endfunction
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
test_if #( .FOO (identity(5)) ) the_interface ();
test_if #( .FOO (identity(7)) ) array_interface [1:0] ();
testmod testmod_i (.clk (clk),
.intf (the_interface),
.intf_no_mp (the_interface),
.intf_array (array_interface)
);
localparam THE_TOP_FOO = the_interface.FOO;
localparam THE_TOP_FOO_BITS = $bits({the_interface.FOO, the_interface.FOO});
localparam THE_ARRAY_FOO = array_interface[0].FOO;
initial begin
if (THE_TOP_FOO != 5) begin
$display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO);
$stop;
end
if (THE_TOP_FOO_BITS != 64) begin
$display("%%Error: THE_TOP_FOO_BITS = %0d", THE_TOP_FOO_BITS);
$stop;
end
if (THE_ARRAY_FOO != 7) begin
$display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO);
$stop;
end
end
endmodule
module testmod
(
input clk,
test_if.mp intf,
test_if intf_no_mp,
test_if.mp intf_array [1:0]
);
localparam THE_FOO = intf.FOO;
localparam THE_OTHER_FOO = intf_no_mp.FOO;
localparam THE_ARRAY_FOO = intf_array[0].FOO;
localparam THE_BAR = intf.BAR;
localparam THE_OTHER_BAR = intf_no_mp.BAR;
localparam THE_ARRAY_BAR = intf_array[0].BAR;
always @(posedge clk) begin
if (THE_FOO != 5) begin
$display("%%Error: THE_FOO = %0d", THE_FOO);
$stop;
end
if (THE_OTHER_FOO != 5) begin
$display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO);
$stop;
end
if (THE_ARRAY_FOO != 7) begin
$display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO);
$stop;
end
if (intf.FOO != 5) begin
$display("%%Error: intf.FOO = %0d", intf.FOO);
$stop;
end
if (intf_no_mp.FOO != 5) begin
$display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO);
$stop;
end
if (intf_array[0].FOO != 7) begin
$display("%%Error: intf_array[0].FOO = %0d", intf_array[0].FOO);
$stop;
end
// if (i.getFoo() != 5) begin
// $display("%%Error: i.getFoo() = %0d", i.getFoo());
// $stop;
// end
if (THE_BAR != 6) begin
$display("%%Error: THE_BAR = %0d", THE_BAR);
$stop;
end
if (THE_OTHER_BAR != 6) begin
$display("%%Error: THE_OTHER_BAR = %0d", THE_OTHER_BAR);
$stop;
end
if (THE_ARRAY_BAR != 8) begin
$display("%%Error: THE_ARRAY_BAR = %0d", THE_ARRAY_BAR);
$stop;
end
if (intf.BAR != 6) begin
$display("%%Error: intf.BAR = %0d", intf.BAR);
$stop;
end
if (intf_no_mp.BAR != 6) begin
$display("%%Error: intf_no_mp.BAR = %0d", intf_no_mp.BAR);
$stop;
end
if (intf_array[0].BAR != 8) begin
$display("%%Error: intf_array[0].BAR = %0d", intf_array[0].BAR);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> const int INF_INT = 0x3f3f3f3f; const long long INF_LL = 0x7f7f7f7f; const int MOD = 1e9 + 7; const double eps = 1e-10; const double pi = acos(-1); using namespace std; int n; int a[30]; int vis[30]; bool dfs(int root, int cnt, int son) { if (root == n + 1) return true; if (cnt + 1 == a[root]) { if (son != 1 && dfs(root + 1, 0, 0)) return true; return false; } int same = 0; for (int i = 1; i <= n; i++) { if (!vis[i] && cnt + a[i] < a[root] && a[i] != same) { same = a[i]; vis[i] = 1; if (dfs(root, cnt + a[i], son + 1)) return true; vis[i] = 0; } } return false; } int main(int argc, char const *argv[]) { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + 1 + n); memset(vis, 0, sizeof(vis)); if (a[n] != n) puts( NO ); else { if (dfs(1, 0, 0)) puts( YES ); else puts( NO ); } return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file asfifo9_4.v when simulating
// the core, asfifo9_4. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module asfifo9_4(
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full);
input [8 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [8 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_4 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(9),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(9),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex2p"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(13),
.C_PROG_FULL_THRESH_NEGATE_VAL(12),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_RESPONSE_LATENCY(1))
inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> int n, m; int f[2000010], mx, mn = (int)1e7; short check(int x) { int i; for (i = x; i <= mx; i += x) if (f[i + x - 1] >= i && f[i + x - 1] - i > m) return 0; return 1; } int main() { int i, x; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) { scanf( %d , &x); f[x] = x; mx = mx > x ? mx : x; mn = mn < x ? mn : x; } mx <<= 1; for (i = 1; i <= mx; i++) f[i] = f[i] > f[i - 1] ? f[i] : f[i - 1]; mx >>= 1; for (i = mn; i > 1; i--) if (check(i)) break; printf( %d , i); return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:47:50 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_led_0/system_axi_gpio_led_0_stub.v
// Design : system_axi_gpio_led_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2016.4" *)
module system_axi_gpio_led_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t,
gpio2_io_i, gpio2_io_o, gpio2_io_t)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0],gpio2_io_i[11:0],gpio2_io_o[11:0],gpio2_io_t[11:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [3:0]gpio_io_i;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
input [11:0]gpio2_io_i;
output [11:0]gpio2_io_o;
output [11:0]gpio2_io_t;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFINV_16_V
`define SKY130_FD_SC_LS__BUFINV_16_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__bufinv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__bufinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFINV_16_V
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module ram_2k (clk, rst, cs, we, addr, rdata, wdata);
// IO Ports
input clk;
input rst;
input cs;
input we;
input [10:0] addr;
output [7:0] rdata;
input [7:0] wdata;
// Net declarations
wire dp;
// Module instantiations
RAMB16_S9 ram (.DO(rdata),
.DOP (dp),
.ADDR (addr),
.CLK (clk),
.DI (wdata),
.DIP (dp),
.EN (cs),
.SSR (rst),
.WE (we));
defparam ram.INIT_00 = 256'h554456_2043504F53_20302E3176_20726F737365636F7270_2074655A;
/*
defparam ram.INIT_00 = 256'h31303938373635343332313039383736_35343332313039383736353433323130;
defparam ram.INIT_01 = 256'h33323130393837363534333231303938_37363534333231303938373635343332;
defparam ram.INIT_02 = 256'h3139383736353433323130393837363534;
defparam ram.INIT_03 = 256'h43000000;
defparam ram.INIT_05 = 256'h32;
defparam ram.INIT_07 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_0A = 256'h34;
defparam ram.INIT_0C = 256'h3500000000000000000000000000000000;
defparam ram.INIT_0F = 256'h36;
defparam ram.INIT_11 = 256'h3700000000000000000000000000000000;
defparam ram.INIT_14 = 256'h38;
defparam ram.INIT_16 = 256'h3900000000000000000000000000000000;
defparam ram.INIT_19 = 256'h30;
defparam ram.INIT_1B = 256'h3100000000000000000000000000000000;
defparam ram.INIT_1E = 256'h32;
defparam ram.INIT_20 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_23 = 256'h34;
defparam ram.INIT_25 = 256'h3500000000000000000000000000000000;
defparam ram.INIT_28 = 256'h36;
defparam ram.INIT_2A = 256'h3700000000000000000000000000000000;
defparam ram.INIT_2D = 256'h38;
defparam ram.INIT_2F = 256'h3900000000000000000000000000000000;
defparam ram.INIT_32 = 256'h30;
defparam ram.INIT_34 = 256'h3100000000000000000000000000000000;
defparam ram.INIT_37 = 256'h32;
defparam ram.INIT_39 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_3C = 256'h31303938373635343332313039383736_35343332313039383736353433323134;
defparam ram.INIT_3D = 256'h33323130393837363534333231303938_37363534333231303938373635343332;
defparam ram.INIT_3E = 256'h35343332313039383736353433323130_39383736353433323130393837363534;
defparam ram.INIT_3F = 256'h37363534333231303938373635343332_31303938373635343332313039383736;
*/
endmodule
|
#include <bits/stdc++.h> const long long N = 200005; long long hi, ls, n, X[N], t, A[N], bk[N]; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> t; for (int i = 0; i < n; ++i) { cin >> A[i]; } for (int i = 0; i < n; ++i) { cin >> X[i], --X[i]; } for (int i = 0; i < n; ++i) { if ((X[i] < i || (i < n - 1 && X[i] > X[i + 1])) || (X[i] != i && (X[X[i]] != X[i] || (X[i] + 1 < n && A[X[i] + 1] - 1 == A[X[i]])))) { cout << No , std::exit(0); } } for (int i = 0; i < n; ++i) { if (X[i] > i) { for (int j = max(hi, 1ll + i); j < X[i] + 1; ++j) { bk[j] = 1; } hi = max(hi, X[i]); } } cout << Yes n ; for (int i = 0; i < n; ++i) (i < n - 1 && bk[i + 1] ? hi = A[i + 1] + t : hi = A[i] + t), (i > 0 && hi == ls ? cout << hi + 1 << : cout << hi << ), ls = hi; return 0; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_value (clock, reset, enable, test_expr, vals, disallow, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter num_values = 1;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input disallow;
input [width-1 : 0] test_expr;
input [(num_values*width)-1 : 0] vals;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_VALUE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_value_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_value
|
#include <bits/stdc++.h> using namespace std; long long m; long long p(long long x) { long long kmx = 0; while ((kmx * kmx * kmx) <= x) kmx++; kmx--; long long ret = 0; for (long long i = 2; i <= kmx; i++) ret += x / (i * i * i); return ret; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> m; long long ans = 0; long long lo = 1, hi = 1e16; while (lo <= hi) { long long mi = (lo + hi) / 2; if (p(mi) >= m) { ans = mi; hi = mi - 1; } else lo = mi + 1; } if (p(ans) != m) ans = -1; cout << ans << n ; return 0; }
|
module Project(
input clock,
input reset
);
wire [15:0] IF_Output;
wire [7:0] PC_Out;
wire [15:0] ID_Input;
wire [15:0] ID_Alusrc1;
wire [15:0] ID_Alusrc2;
wire [15:0] ID_Memwritedata;
wire [3:0] ID_Alucmd;
wire [2:0] ID_Rfwritebackdest;
wire IDJump;
wire IDBranch;
wire IDMemwriteenable;
wire IDWritebackenable;
wire IDWritebackresultmux;
wire [57:0] EX_Input;
wire [37:0] MEM_Input;
wire [15:0] EX_Lowresult;
wire [36:0] WB_Input;
wire [15:0] MEM_Memoryout;
wire WBWriteenable;
wire [2:0] WBWritedest;
wire [15:0] WBWritedata;
wire stall;
wire [2:0] IDop1;
wire [2:0] IDop2;
wire zero;
IF_STAGE Inst_Fetch(
.clk(clock),
.rst(reset),
.instr_fetch_enable(stall),
.imm_branch_offset(ID_Input[5:0]),
.branch_enable(IDBranch),
.jump(IDJump),
.pc(PC_Out),
.instr(IF_Output)
);
IF_ID IF_ID_Register(
.clock(clock),
.reset(reset),
.In(IF_Output),
.InEnable(stall),
.Out(ID_Input)
);
ID_STAGE Inst_Decode(
.clk(clock),
.rst(reset),
.ID_Zero(zero),
.ID_RegWriteEn(WBWriteenable),
.ID_RegWriteDest(WBWritedest),
.ID_RegWriteData(WBWritedata),
.ID_In(ID_Input),
.ID_Controller(IF_Output),
.ID_AluSrc1(ID_Alusrc1),
.ID_AluSrc2(ID_Alusrc2),
.ID_MemWriteData(ID_Memwritedata),
.ID_RFWriteBackDest(ID_Rfwritebackdest),
.ID_MemWriteEn(IDMemwriteenable),
.ID_WriteBackResultMux(IDWritebackresultmux),
.ID_RFWriteBackEn(IDWritebackenable),
.ID_ALUCmd(ID_Alucmd),
.ID_jump(IDJump),
.ID_branch(IDBranch),
.ID_op1(IDop1),
.ID_op2(IDop2)
);
ID_EX ID_EX_Register(
.clock(clock),
.reset(reset),
.ex_alu_cmd(ID_Alucmd),
.ex_alu_src1(ID_Alusrc1),
.ex_alu_src2(ID_Alusrc2),
.mem_write_en(IDMemwriteenable),
.mem_write_data(ID_Memwritedata),
.write_back_en(IDWritebackenable),
.write_back_dest(ID_Rfwritebackdest),
.write_back_result_mux(IDWritebackresultmux),
.stall(stall),
.RegIDToExOut(EX_Input)
);
EX_STAGE Inst_Execute(
.EX_AluCmd(EX_Input[57:54]),
.EX_AluSrc1(EX_Input[53:38]),
.EX_AluSrc2(EX_Input[37:22]),
.zeroFlag(zero),
.EX_LowResult(EX_Lowresult)
);
EX_MEM EX_MEM_Register(
.clock(clock),
.reset(reset),
.ex_alu_result(EX_Lowresult),
.mem_write_en(EX_Input[21:21]),
.mem_write_data(EX_Input[20:5]),
.write_back_en(EX_Input[4:4]),
.write_back_dest(EX_Input[3:1]),
.write_back_result_mux(EX_Input[0:0]),
.RegExToMemOut(MEM_Input)
);
MEM_STAGE Inst_Memory(
.rst(reset),
.DataMemoryAddress(MEM_Input[37:22]),
.DataMemoryWriteData(MEM_Input[20:5]),
.DataMemoryWriteEnable(MEM_Input[21:21]),
.DataMemoryOut(MEM_Memoryout)
);
MEM_WB MEM_WB_Register(
.clock(clock),
.reset(reset),
.ex_alu_result(MEM_Input[37:22]),
.mem_read_data(MEM_Memoryout),
.write_back_en(MEM_Input[4:4]),
.write_back_dest(MEM_Input[3:1]),
.write_back_result_mux(MEM_Input[0:0]),
.RegMemToWBOut(WB_Input)
);
WB_STAGE Inst_WriteBack(
.pipeline_reg_in(WB_Input),
.Reg_write_en(WBWriteenable),
.Reg_write_dest(WBWritedest),
.Reg_write_data(WBWritedata)
);
HAZARD myHazard(
.clk(clock),
.rst(reset),
.decoding_op_src1(IDop1),
.decoding_op_src2(IDop2),
.decoding_op_dest(ID_Input[11:9]),
.ex_op_dest(EX_Input[3:1]),
.mem_op_dest(MEM_Input[3:1]),
.wb_op_dest(WBWritedest),
.pipeline_stall_n(stall)
);
endmodule
|
module Top_Show(clk, change, Reset, String, RS, RW, EN, StringDisplay, MsbOD);
input clk;
input change, Reset;
input [76:0] String;
output [6:0] StringDisplay;
output RS, RW, EN;
output MsbOD;
wire [76:0] w_Regin;
wire [6:0] w_D;
wire [2:0] w_scrinit;
wire w_Init,w_Shift, w_enhe, w_Z, w_creaenhe, w_Start, w_outcont, w_rst, w_Beg, w_Ready, w_Cycend;
Timer Timer1(.rst(w_rst), .clk(clk), .Beg(w_Beg), .Ready(w_Ready), .Cycend(w_Cycend), .scrinit(w_scrinit));
StringInput StringInput1(.String(String), .Init(w_Init), .clk(clk), .Shift(w_Shift), .rst(w_rst), .Regin(w_Regin));
Accumulator Accumulator1(.MsbR(w_Regin[76]), .Shift(w_Shift), .clk(clk), .D(w_D), .rst(w_rst));
Enhecomp Enhecomp1(.D(w_D), .enhe(w_enhe));
Zerocomp Zerocomp1(.Regin(w_Regin), .Z(w_Z));
Create Create1(.Init(w_Init), .creaenhe(w_creaenhe), .D(w_D), .rst(w_rst), .MsbOD(MsbOD), .RS(RS), .RW(RW), .Out_display(StringDisplay), .clk(clk), .scrinit(w_scrinit));
SevenCont SevenCont1(.Start(w_Start), .rst(w_rst), .clk(clk), .outcont(w_outcont));
ShowControl ShowControl1(.clk(clk), .enhe(w_enhe), .outcont(w_outcont), .Reset(Reset), .change(change), .Z(w_Z), .Start(w_Start), .EN(EN), .creaenhe(w_creaenhe), .Init(w_Init), .Shift(w_Shift), .Ready(w_Ready), .rst(w_rst), .Beg(w_Beg), .scrinit(w_scrinit), .Cycend(w_Cycend));
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 1995/2006 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.51)
// \ \ Description :
// / /
// /__/ /\ Filename : ICAPE2.v
// \ \ / \
// \__\/\__ \
//
// Revision:
// 04/30/10 - Initial version.
// 09/03/10 - Change to bus timing.
// 02/18/11 - Change DEVICE_ID default (CR593951)
// 02/10/14 - Fixed GSR deassertion (CR 772626).
// End Revision
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module ICAPE2 (
O,
CLK,
CSIB,
I,
RDWRB
);
parameter [31:0] DEVICE_ID = 32'h03651093;
parameter ICAP_WIDTH = "X32";
parameter SIM_CFG_FILE_NAME = "NONE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
output [31:0] O;
input CLK;
input CSIB;
input RDWRB;
input [31:0] I;
wire cso_b;
reg prog_b;
reg init_b;
reg [3:0] bw = 4'b0000;
wire busy_out;
reg cs_bi = 0, rdwr_bi = 0;
wire cs_b_t;
wire clk_in;
wire rdwr_b_t;
wire [31:0] dix;
reg [31:0] di;
reg [31:0] data_rbt;
reg [7:0] tmp_byte0;
reg [7:0] tmp_byte1;
reg [7:0] tmp_byte2;
reg [7:0] tmp_byte3;
reg icap_idone = 0;
reg clk_osc = 0;
reg sim_file_flag;
integer icap_fd;
reg notifier;
wire delay_CLK;
wire delay_CSIB;
wire delay_RDWRB;
wire [31:0] delay_I;
tri1 p_up;
tri init_tri = (icap_idone == 0) ? init_b : p_up;
tri (weak1, strong0) done_o = p_up;
tri (pull1, supply0) [31:0] di_t = (icap_idone == 1 && delay_RDWRB == 1)? 32'bz : dix;
`ifndef XIL_TIMING
assign delay_I = I;
assign delay_RDWRB = RDWRB;
assign delay_CLK = CLK;
assign delay_CSIB = CSIB;
`endif
assign dix = (icap_idone == 1) ? delay_I : di;
assign cs_b_t = (icap_idone == 1) ? delay_CSIB : cs_bi;
assign clk_in = (icap_idone == 1) ? delay_CLK : clk_osc;
assign rdwr_b_t = (icap_idone == 1) ? delay_RDWRB : rdwr_bi;
assign O = (icap_idone == 1 && delay_RDWRB == 1) ? di_t : 32'b0;
always
// if (icap_idone == 0)
#1000 clk_osc <= ~clk_osc;
always @(delay_CSIB or delay_RDWRB)
if ($time > 1 && icap_idone == 0) begin
$display (" Warning : ICAPE2 on instance %m at time %t has not finished initialization. A message will be printed after the initialization. User need start read/write operation after that.", $time);
end
SIM_CONFIGE2 #(
.DEVICE_ID(DEVICE_ID),
.ICAP_SUPPORT("TRUE"),
.ICAP_WIDTH(ICAP_WIDTH)
)
SIM_CONFIGE2_INST (
.CSOB(cso_b),
.DONE(done_o),
.CCLK(clk_in),
.CSB(cs_b_t),
.D(di_t),
.INITB(init_tri),
.M(3'b110),
.PROGB(prog_b),
.RDWRB(rdwr_b_t)
);
initial begin
case (ICAP_WIDTH)
"X8" : bw = 4'b0000;
"X16" : bw = 4'b0010;
"X32" : bw = 4'b0011;
default : begin
$display("Attribute Syntax Error : The Attribute ICAP_WIDTH on ICAPE2 instance %m is set to %s. Legal values for this attribute are X8, X16 or X32.", ICAP_WIDTH);
end
endcase
icap_idone = 0;
sim_file_flag = 0;
if (SIM_CFG_FILE_NAME == "NONE") begin
sim_file_flag = 1;
end
else begin
icap_fd = $fopen(SIM_CFG_FILE_NAME, "r");
if (icap_fd == 0)
begin
$display(" Error: The configure rbt data file %s for ICAPE2 instance %m was not found. Use the SIM_CFG_FILE_NAME parameter to pass the file name.\n", SIM_CFG_FILE_NAME);
sim_file_flag = 1;
end
end
init_b = 1;
prog_b = 1;
rdwr_bi = 0;
cs_bi = 1;
#600000;
@(posedge clk_in)
prog_b = 0;
@(negedge clk_in)
init_b = 0;
#600000;
@(posedge clk_in)
prog_b = 1;
@(negedge clk_in) begin
init_b = 1;
cs_bi = 0;
end
if (sim_file_flag == 0) begin
while ($fscanf(icap_fd, "%b", data_rbt) != -1) begin
if (done_o == 0) begin
tmp_byte3 = bit_revers8(data_rbt[31:24]);
tmp_byte2 = bit_revers8(data_rbt[23:16]);
tmp_byte1 = bit_revers8(data_rbt[15:8]);
tmp_byte0 = bit_revers8(data_rbt[7:0]);
if (bw == 4'b0000) begin
@(negedge clk_in)
di = {24'b0, tmp_byte3};
@(negedge clk_in)
di = {24'b0, tmp_byte2};
@(negedge clk_in)
di = {24'b0, tmp_byte1};
@(negedge clk_in)
di = {24'b0, tmp_byte0};
end
else if (bw == 4'b0010) begin
@(negedge clk_in)
di = {16'b0, tmp_byte3, tmp_byte2};
@(negedge clk_in)
di = {16'b0, tmp_byte1, tmp_byte0};
end
else if (bw == 4'b0011) begin
@(negedge clk_in)
di = {tmp_byte3, tmp_byte2, tmp_byte1, tmp_byte0};
end
end
else begin
@(negedge clk_in);
di = 32'hFFFFFFFF;
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
if (icap_idone == 0) begin
$display (" Message: ICAPE2 on instance %m at time %t has finished initialization. User can start read/write operation.", $time);
icap_idone = 1;
end
end
end
$fclose(icap_fd);
#1000;
end
else begin
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'hFFFFFFFF;
@(negedge clk_in)
di = 32'h000000DD;
@(negedge clk_in) begin
if (bw == 4'b0000)
di = 32'h00000088;
else if (bw == 4'b0010)
di = 32'h00000044;
else if (bw == 4'b0011)
di = 32'h00000022;
end
rbt_data_wr(32'hFFFFFFFF);
rbt_data_wr(32'hFFFFFFFF);
rbt_data_wr(32'hAA995566);
rbt_data_wr(32'h30008001);
rbt_data_wr(32'h00000005);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
@(negedge clk_in);
if (icap_idone == 0) begin
$display (" Message: ICAPE2 on instance %m at time %t has finished initialization. User can start read/write operation.", $time);
icap_idone = 1;
end
#1000;
end
end
task rbt_data_wr;
input [31:0] dat_rbt;
reg [7:0] tp_byte3;
reg [7:0] tp_byte2;
reg [7:0] tp_byte1;
reg [7:0] tp_byte0;
begin
tp_byte3 = bit_revers8(dat_rbt[31:24]);
tp_byte2 = bit_revers8(dat_rbt[23:16]);
tp_byte1 = bit_revers8(dat_rbt[15:8]);
tp_byte0 = bit_revers8(dat_rbt[7:0]);
if (bw == 4'b0000) begin
@(negedge clk_in)
di = {24'b0, tp_byte3};
@(negedge clk_in)
di = {24'b0, tp_byte2};
@(negedge clk_in)
di = {24'b0, tp_byte1};
@(negedge clk_in)
di = {24'b0, tp_byte0};
end
else if (bw == 4'b0010) begin
@(negedge clk_in)
di = {16'b0, tp_byte3, tp_byte2};
@(negedge clk_in)
di = {16'b0, tp_byte1, tp_byte0};
end
else if (bw == 4'b0011) begin
@(negedge clk_in)
di = {tp_byte3, tp_byte2, tp_byte1, tp_byte0};
end
end
endtask
function [7:0] bit_revers8;
input [7:0] din8;
begin
bit_revers8[0] = din8[7];
bit_revers8[1] = din8[6];
bit_revers8[2] = din8[5];
bit_revers8[3] = din8[4];
bit_revers8[4] = din8[3];
bit_revers8[5] = din8[2];
bit_revers8[6] = din8[1];
bit_revers8[7] = din8[0];
end
endfunction
specify
( CLK => O) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CLK, 0:0:0, notifier);
$setuphold (posedge CLK, negedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB);
$setuphold (posedge CLK, posedge CSIB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_CSIB);
$setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I);
$setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_I);
$setuphold (posedge CLK, negedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB);
$setuphold (posedge CLK, posedge RDWRB, 0:0:0, 0:0:0, notifier,,, delay_CLK, delay_RDWRB);
`endif //
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { int i, n, k, j; cin >> n >> k; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) if (i == j) cout << k << ; else cout << 0 << ; cout << n ; } }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module axi_ad9467_if (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_data,
adc_or,
// processor interface
adc_ddr_edgesel,
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked);
// buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [15:0] adc_data;
output adc_or;
// processor interface
input adc_ddr_edgesel;
// delay control signals
input up_clk;
input [ 8:0] up_dld;
input [44:0] up_dwdata;
output [44:0] up_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg [ 7:0] adc_data_p = 'd0;
reg [ 7:0] adc_data_n = 'd0;
reg [ 7:0] adc_data_p_d = 'd0;
reg [ 7:0] adc_dmux_a = 'd0;
reg [ 7:0] adc_dmux_b = 'd0;
reg [15:0] adc_data = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg adc_or = 'd0;
// internal signals
wire [ 7:0] adc_data_p_s;
wire [ 7:0] adc_data_n_s;
wire adc_or_p_s;
wire adc_or_n_s;
genvar l_inst;
// sample select (p/n) swap
always @(posedge adc_clk) begin
adc_data_p <= adc_data_p_s;
adc_data_n <= adc_data_n_s;
adc_data_p_d <= adc_data_p;
adc_dmux_a <= (adc_ddr_edgesel == 1'b1) ? adc_data_n : adc_data_p;
adc_dmux_b <= (adc_ddr_edgesel == 1'b1) ? adc_data_p_d : adc_data_n;
adc_data[15] <= adc_dmux_b[7];
adc_data[14] <= adc_dmux_a[7];
adc_data[13] <= adc_dmux_b[6];
adc_data[12] <= adc_dmux_a[6];
adc_data[11] <= adc_dmux_b[5];
adc_data[10] <= adc_dmux_a[5];
adc_data[ 9] <= adc_dmux_b[4];
adc_data[ 8] <= adc_dmux_a[4];
adc_data[ 7] <= adc_dmux_b[3];
adc_data[ 6] <= adc_dmux_a[3];
adc_data[ 5] <= adc_dmux_b[2];
adc_data[ 4] <= adc_dmux_a[2];
adc_data[ 3] <= adc_dmux_b[1];
adc_data[ 2] <= adc_dmux_a[1];
adc_data[ 1] <= adc_dmux_b[0];
adc_data[ 0] <= adc_dmux_a[0];
adc_or_p <= adc_or_p_s;
adc_or_n <= adc_or_n_s;
if ((adc_or_p == 1'b1) || (adc_or_n == 1'b1)) begin
adc_or <= 1'b1;
end else begin
adc_or <= 1'b0;
end
end
// data interface
generate
for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.up_clk (up_clk),
.up_dld (up_dld[8]),
.up_dwdata (up_dwdata[44:40]),
.up_drdata (up_drdata[44:40]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int n, m, hd, el; char s[1000]; struct E { char tag; int p[26]; } e[1000000]; void ins() { int i, j, k, l; for (i = 0, l = hd; s[i]; i++) { if (!e[l].p[s[i] - a ]) e[l].p[s[i] - a ] = el++; l = e[l].p[s[i] - a ]; } } void dfs(int ei) { int i, j, c[5] = {0, 0, 0, 0, 0}; for (i = j = 0; i < 26; i++) { if (e[ei].p[i]) { j = 1; dfs(e[ei].p[i]); c[e[e[ei].p[i]].tag]++; } } if (!j) e[ei].tag = 1; else if (c[4] || (c[1] && c[2])) e[ei].tag = 3; else if (c[1]) e[ei].tag = 2; else if (c[2]) e[ei].tag = 1; else e[ei].tag = 4; } void init() { int i, j, k, l; hd = el = 0; el++; scanf( %d%d , &n, &m); for (i = 0; i < n; i++) { scanf( %s , s); ins(); } dfs(hd); } void solve() { if (e[hd].tag == 1 || e[hd].tag == 4) puts( Second ); else if (e[hd].tag == 3) puts( First ); else if (m & 1) puts( First ); else puts( Second ); } int main() { init(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, i, x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; cout << (x2 - x1) * (y2 - y1) + 1 << n ; } int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long tt; cin >> tt; while (tt--) { solve(); } cerr << Execution : << (1.0 * clock()) / CLOCKS_PER_SEC << s n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; int nums[n]; for (int i = 0; i < n; i++) { cin >> nums[i]; } int ans = 0; int maxi = 0; int mini = 1e9; for (int i = 0; i < n; i++) { maxi = max(maxi, nums[i]); mini = min(mini, nums[i]); } int f = -1, l = -1; for (int i = 0; i < n; i++) { if (nums[i] == maxi) { f = i; break; } } for (int i = n - 1; i >= 0; i--) { if (nums[i] == mini) { l = i; break; } } ans += f + n - 1 - l; if (l < f) ans--; cout << ans; return 0; }
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`timescale 1ns / 1ns
module gentest;
reg [7:0] a=0, b=0;
wire co;
wire [7:0] result;
adder work(a, b, 1'b0, result, co);
integer cc;
initial begin
for (cc=0; cc<10; cc=cc+1) begin
a=a+1;
#10;
$display("%d %d %d", a, b, result);
b=result;
end
if (b==55) $display("PASSED");
else $display("FAIL");
end
endmodule
module adder(a, b, ci, out, co);
parameter SIZE=8;
input [SIZE-1:0] a;
input [SIZE-1:0] b;
input ci;
output [SIZE-1:0] out;
output co;
wire [SIZE:0] c;
assign c[0] = ci;
assign co = c[SIZE];
`ifdef NOGENERATE
add1 bit0(a[0], b[0], c[0], out[0], c[0+1]);
add1 bit1(a[1], b[1], c[1], out[1], c[1+1]);
add1 bit2(a[2], b[2], c[2], out[2], c[2+1]);
add1 bit3(a[3], b[3], c[3], out[3], c[3+1]);
add1 bit4(a[4], b[4], c[4], out[4], c[4+1]);
add1 bit5(a[5], b[5], c[5], out[5], c[5+1]);
add1 bit6(a[6], b[6], c[6], out[6], c[6+1]);
add1 bit7(a[7], b[7], c[7], out[7], c[7+1]);
`else
genvar i;
generate for(i=0; i<SIZE; i=i+1) begin:addbit
add1 bit(a[i], b[i], c[i], out[i], c[i+1]);
end endgenerate
`endif
endmodule
module add1(a, b, ci, sum, co);
input a, b, ci;
output sum, co;
assign {co,sum} = a + b + ci;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int test; cin >> test; while (test--) { int n, m; cin >> n >> m; string S; cin >> S; vector<int> P(m); vector<int> cnt(n); for (int i = 0; i < m; i++) { cin >> P[i]; cnt[0]++; cnt[P[i]]--; } vector<int> res(26); for (int i = 0; i < n; i++) res[S[i] - a ]++; res[S[0] - a ] += cnt[0]; for (int i = 1; i < n; i++) { cnt[i] += cnt[i - 1]; res[S[i] - a ] += cnt[i]; } for (int i = 0; i < 26; i++) cout << res[i] << << flush; cout << endl; } return 0; }
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// PentEvo project (c) NedoPC 2008-2009
//
// state: | RD1 | RD2 | RD3 | RD4 | WR1 | WR2 | WR3 | WR4 | RFSH1 | RFSH2 | RFSH3 | RFSH4 |
// clk: ___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\__
// | READ CYCLE | WRITE CYCLE | REFRESH CYCLE |
// ras: ```````````````````\_______________/```````````````\_______________/```````````````````````\_______________/
// cas: ```````````````````````````\_______________/```````````````\_______________/```````\_______________/````````
// ra: | row | column| | row | column|
// rd: XXXXXXXXXXXXXXXXXXXXXXXXX<read data read| write data write data write |
// rwe: `````````````````````````````````````````\_______________________________/````````````````````````````````
// req: __/```````\_______________________/```````\________________________________________________________________
// rnw: XX/```````\XXXXXXXXXXXXXXXXXXXXXXX\_______/XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// cbeg: __________/```````\_______________________/```````\_______________________/```````\_______________________/
// rrdy: __________________________________/```````\________________________________________________________________
// addr: XX< addr >XXXXXXXXXXXXXXXXXXXXXXX< addr >XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
//wrdata:XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX< write >XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
//rddata:XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX< read >XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
//
// comments:
// rucas_n, rlcas_n, rras0_n, rras1_n, rwe_n could be made 'fast output register'
// ra[] couldn't be such in acex1k, because output registers could be all driven only by
// single clock polarity (and here they are driven by negative edge, while CAS/RAS by positive)
//
// rst_n is resynced before use and acts as req inhibit. so while in reset, dram regenerates and isn't corrupted
module dram(
input clk,
input rst_n, // shut down accesses, remain refresh
output reg [9:0] ra, // to the DRAM pins
inout [15:0] rd, // . .
// . .
output reg rwe_n, // . .
output reg rucas_n, // . .
output reg rlcas_n, // . .
output reg rras0_n, // . .
output reg rras1_n, // to the DRAM pins
input [20:0] addr, // access address of 16bit word: addr[0] selects between rras0_n and rras1_n,
// addr[10:1] goes to row address, addr[20:11] goes to column address
input req, // request for read/write cycle
input rnw, // READ/nWRITE (=1: read, =0: write)
output reg cbeg, // cycle begin (any including refresh), can be used for synchronizing
output reg rrdy, // Read data ReaDY
output reg [15:0] rddata, // data just read
input [15:0] wrdata, // data to be written
input [1:0] bsel // positive byte select for write: bsel[0] is for wrdata[7:0], bsel[1] is for wrdata[15:8]
);
reg [1:0] rst_sync;
wire reset;
wire int_req;
reg [20:0] int_addr;
reg [15:0] int_wrdata;
reg [1:0] int_bsel;
reg [3:0] state;
reg [3:0] next_state;
localparam RD1 = 0;
localparam RD2 = 1;
localparam RD3 = 2;
localparam RD4 = 3;
localparam WR1 = 4;
localparam WR2 = 5;
localparam WR3 = 6;
localparam WR4 = 7;
localparam RFSH1 = 8;
localparam RFSH2 = 9;
localparam RFSH3 = 10;
localparam RFSH4 = 11;
always @(posedge clk)
begin
state <= next_state;
end
always @*
case( state )
RD1:
next_state = RD2;
RD2:
next_state = RD3;
RD3:
next_state = RD4;
RD4:
if( !int_req )
next_state = RFSH1;
else
next_state = rnw?RD1:WR1;
WR1:
next_state = WR2;
WR2:
next_state = WR3;
WR3:
next_state = WR4;
WR4:
if( !int_req )
next_state = RFSH1;
else
next_state = rnw?RD1:WR1;
RFSH1:
next_state = RFSH2;
RFSH2:
next_state = RFSH3;
RFSH3:
next_state = RFSH4;
RFSH4:
if( !int_req )
next_state = RFSH1;
else
next_state = rnw?RD1:WR1;
endcase
// incoming data latching
always @(posedge clk)
begin
if( (state==RD4) || (state==WR4) || (state==RFSH4) )
begin
int_addr <= addr;
int_wrdata <= wrdata;
int_bsel <= bsel;
end
end
// WE control
always @(posedge clk)
begin
if( (next_state==WR1) || (next_state==WR2) || (next_state==WR3) || (next_state==WR4) )
rwe_n <= 1'b0;
else
rwe_n <= 1'b1;
end
// RAS/CAS sequencing
always @(posedge clk)
begin
case( state )
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RD1:
begin
rras0_n <= int_addr[0];
rras1_n <= ~int_addr[0];
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RD2:
begin
rucas_n <= 1'b0;
rlcas_n <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RD3:
begin
rras0_n <= 1'b1;
rras1_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RD4:
begin
rras0_n <= 1'b1;
rras1_n <= 1'b1;
rucas_n <= 1'b1;
rlcas_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
WR1:
begin
rras0_n <= int_addr[0];
rras1_n <= ~int_addr[0];
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
WR2:
begin
rucas_n <= ~int_bsel[1];
rlcas_n <= ~int_bsel[0];
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
WR3:
begin
rras0_n <= 1'b1;
rras1_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
WR4:
begin
rras0_n <= 1'b1;
rras1_n <= 1'b1;
rucas_n <= 1'b1;
rlcas_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RFSH1:
begin
rucas_n <= 1'b0;
rlcas_n <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RFSH2:
begin
rras0_n <= 1'b0;
rras1_n <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RFSH3:
begin
rucas_n <= 1'b1;
rlcas_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
RFSH4:
begin
rras0_n <= 1'b1;
rras1_n <= 1'b1;
rucas_n <= 1'b1;
rlcas_n <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
endcase
end
// row/column address multiplexing
always @(negedge clk)
begin
if( (state==RD1) || (state==WR1) )
ra <= int_addr[10:1];
else
ra <= int_addr[20:11];
end
// DRAM data bus control
assign rd = rwe_n ? 16'hZZZZ : int_wrdata;
// read data from DRAM
always @(posedge clk)
begin
if( state==RD3 )
rddata <= rd;
end
// cbeg and rrdy control
always @(posedge clk)
begin
if( (state==RD4) || (state==WR4) || (state==RFSH4) )
cbeg <= 1'b1;
else
cbeg <= 1'b0;
if( state==RD3 )
rrdy <= 1'b1;
else
rrdy <= 1'b0;
end
// reset must be synchronous here in order to preserve
// DRAM state while other modules reset, but we have only
// asynchronous one globally. so we must re-synchronize it
// and use it as 'DRAM operation enable'. when in reset,
// controller ignores req signal and generates only refresh cycles
always @(posedge clk)
rst_sync[1:0] <= { rst_sync[0], ~rst_n };
assign reset = rst_sync[1];
assign int_req = req & (~reset);
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: D5M CCD_Capture
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
`include "VGA_Param.h"
module CCD_Capture( oDATA,
oDVAL,
oX_Cont,
oY_Cont,
oFrame_Cont,
iDATA,
iFVAL,
iLVAL,
iSTART,
iEND,
iCLK,
iRST
);
input [11:0] iDATA;
input iFVAL;
input iLVAL;
input iSTART;
input iEND;
input iCLK;
input iRST;
output [11:0] oDATA;
output [15:0] oX_Cont;
output [15:0] oY_Cont;
output [31:0] oFrame_Cont;
output oDVAL;
reg Pre_FVAL;
reg mCCD_FVAL;
reg mCCD_LVAL;
reg [11:0] mCCD_DATA;
reg [15:0] X_Cont;
reg [15:0] Y_Cont;
reg [31:0] Frame_Cont;
reg mSTART;
`ifdef VGA_640x480p60
parameter COLUMN_WIDTH = 1280;
`else
parameter COLUMN_WIDTH = 800;
`endif
assign oX_Cont = X_Cont;
assign oY_Cont = Y_Cont;
assign oFrame_Cont = Frame_Cont;
assign oDATA = mCCD_DATA;
assign oDVAL = mCCD_FVAL&mCCD_LVAL;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
mSTART <= 0;
else
begin
if(iSTART)
mSTART <= 1;
if(iEND)
mSTART <= 0;
end
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
Pre_FVAL <= 0;
mCCD_FVAL <= 0;
mCCD_LVAL <= 0;
X_Cont <= 0;
Y_Cont <= 0;
end
else
begin
Pre_FVAL <= iFVAL;
if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
mCCD_FVAL <= 1;
else if({Pre_FVAL,iFVAL}==2'b10)
mCCD_FVAL <= 0;
mCCD_LVAL <= iLVAL;
if(mCCD_FVAL)
begin
if(mCCD_LVAL)
begin
if(X_Cont<(COLUMN_WIDTH-1))
X_Cont <= X_Cont+1;
else
begin
X_Cont <= 0;
Y_Cont <= Y_Cont+1;
end
end
end
else
begin
X_Cont <= 0;
Y_Cont <= 0;
end
end
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
Frame_Cont <= 0;
else
begin
if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
Frame_Cont <= Frame_Cont+1;
end
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
mCCD_DATA <= 0;
else if (iLVAL)
mCCD_DATA <= iDATA;
else
mCCD_DATA <= 0;
end
reg ifval_dealy;
wire ifval_fedge;
reg [15:0] y_cnt_d;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
y_cnt_d <= 0;
else
y_cnt_d <= Y_Cont;
end
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
ifval_dealy <= 0;
else
ifval_dealy <= iFVAL;
end
assign ifval_fedge = ({ifval_dealy,iFVAL}==2'b10)?1:0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int modInverse(int a, int m); int gcd(int a, int b); int power(int x, unsigned int y, unsigned int m); void pairsort(int a[], int b[], int n); int logint(int x, int y); int gcd(int a, int b) { if (a == 0) return b; return gcd(b % a, a); } int power(int x, unsigned int y, unsigned int m) { if (y == 0) return 1; int p = power(x, y / 2, m) % m; p = (p * p) % m; return (y % 2 == 0) ? p : (x * p) % m; } int modInverse(int a, int m) { int m0 = m; int y = 0, x = 1; if (m == 1) return 0; while (a > 1) { int q = a / m; int t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } void pairsort(int a[], int b[], int n) { pair<int, int> pairt[n]; for (int i = 0; i < n; i++) { pairt[i].first = a[i]; pairt[i].second = b[i]; } sort(pairt, pairt + n); for (int i = 0; i < n; i++) { a[i] = pairt[i].first; b[i] = pairt[i].second; } } int logint(int x, int y) { int ans = 0; int a = 1; for (int i = 0; i < x; i++) { if (x <= a) { return ans; } ans++; a *= y; } return -1; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; int mink; int k = 0; int a[n]; for (int i = 0; i < n; i++) { int t; cin >> t; a[i] = t; if (i == 0) mink = t; else mink = min(mink, t); } for (int i = 0; i < n; i++) { int t = a[i]; if (t == mink) k++; } if (k > (n / 2)) { cout << Bob ; } else { cout << Alice ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void getre() { int x = 0; printf( %d n , 1 / x); } void gettle() { int res = 1; while (1) res <<= 1; printf( %d n , res); } template <typename T, typename S> inline bool upmin(T &a, const S &b) { return a > b ? a = b, 1 : 0; } template <typename T, typename S> inline bool upmax(T &a, const S &b) { return a < b ? a = b, 1 : 0; } template <typename N, typename PN> inline N flo(N a, PN b) { return a >= 0 ? a / b : -((-a - 1) / b) - 1; } template <typename N, typename PN> inline N cei(N a, PN b) { return a > 0 ? (a - 1) / b + 1 : -(-a / b); } template <typename N> N gcd(N a, N b) { return b ? gcd(b, a % b) : a; } template <typename N> inline int sgn(N a) { return a > 0 ? 1 : (a < 0 ? -1 : 0); } inline void gn(long long &x) { int sg = 1; char c; while (((c = getchar()) < 0 || c > 9 ) && c != - ) ; c == - ? (sg = -1, x = 0) : (x = c - 0 ); while ((c = getchar()) >= 0 && c <= 9 ) x = x * 10 + c - 0 ; x *= sg; } inline void gn(int &x) { long long t; gn(t); x = t; } inline void gn(unsigned long long &x) { long long t; gn(t); x = t; } inline void gn(double &x) { double t; scanf( %lf , &t); x = t; } inline void gn(long double &x) { double t; scanf( %lf , &t); x = t; } inline void gs(char *s) { scanf( %s , s); } inline void gc(char &c) { while ((c = getchar()) > 126 || c < 33) ; } inline void pc(char c) { putchar(c); } inline long long sqr(long long a) { return a * a; } inline double sqrf(double a) { return a * a; } const int inf = 0x3f3f3f3f; const double pi = 3.14159265358979323846264338327950288L; const double eps = 1e-6; const int mo = 1; int qp(int a, long long b) { int n = 1; do { if (b & 1) n = 1ll * n * a % mo; a = 1ll * a * a % mo; } while (b >>= 1); return n; } int n; int a[222]; int nok[33333]; int ok[33333]; int bo[222][222]; const int dinic_inf = 0x3f3f3f3f; const int DINIC_MAXV = 555 + 5; const int DINIC_MAXE = 55555 + 5; int s, t, vtot; struct edge { int v, next; int f; } e[DINIC_MAXE * 2]; int g[DINIC_MAXV], etot, eid; int ae(int u, int v, int f) { upmax(vtot, u); upmax(vtot, v); e[etot].v = v; e[etot].f = f; e[etot].next = g[u]; g[u] = etot++; e[etot].v = u; e[etot].f = 0; e[etot].next = g[v]; g[v] = etot++; return eid++; } int d[DINIC_MAXV]; bool lb() { for (int i = 0; i <= vtot; i++) d[i] = 0; static int qu[DINIC_MAXV]; int p = 0, q = 0; qu[q++] = s, d[s] = 1; while (p != q) { int u = qu[p++]; for (int i = g[u]; ~i; i = e[i].next) if (e[i].f && !d[e[i].v]) { d[e[i].v] = d[u] + 1; if (e[i].v == t) return 1; qu[q++] = e[i].v; } } return 0; } int aug(int u, int mi) { if (u == t) return mi; int su = 0, del; for (int i = g[u]; ~i; i = e[i].next) if (e[i].f && d[e[i].v] == d[u] + 1) { del = aug(e[i].v, min(mi, e[i].f)); e[i].f -= del; e[i ^ 1].f += del; mi -= del; su += del; if (!mi) break; } if (!su) d[u] = -1; return su; } int dinic() { int su = 0; while (lb()) su += aug(s, dinic_inf); return su; } void dinic_init() { static bool ini = 0; if (!ini) { ini = 1; memset(g, -1, sizeof(g)); } else { for (int i = 0; i <= vtot; i++) g[i] = -1; } etot = eid = 0; vtot = 2, s = 1, t = 2; } inline int capaof(int ei) { return e[ei << 1].f + e[ei << 1 ^ 1].f; } inline int flowof(int ei) { return e[ei << 1 ^ 1].f; } inline int resiof(int ei) { return e[ei << 1].f; } inline int uof(int ei) { return e[ei << 1 ^ 1].v; } inline int vof(int ei) { return e[ei << 1].v; } vector<int> nei[222]; int vis[222]; int cur = 0; vector<int> ans[222]; void dfs(int u) { if (vis[u]) return; ans[cur].push_back(u); vis[u] = 1; dfs(nei[u][0]); dfs(nei[u][1]); } int main() { nok[1] = 1; for (int i = 2; i <= 30000; i++) if (!nok[i]) for (int j = i + i; j <= 30000; j += i) nok[j] = 1; for (int i = 2; i <= 30000; i++) ok[i] = !nok[i]; gn(n); for (int i = (1), _ed = (n + 1); i < _ed; i++) gn(a[i]); for (int i = (1), _ed = (n + 1); i < _ed; i++) for (int j = (1), _ed = (n + 1); j < _ed; j++) if (i != j && ok[a[i] + a[j]]) bo[i][j] = 1; int nu0 = 0, nu1 = 0; for (int i = (1), _ed = (n + 1); i < _ed; i++) if (a[i] & 1) nu1++; else nu0++; if (nu0 != nu1) { printf( Impossible n ); return 0; } dinic_init(); for (int i = (1), _ed = (n + 1); i < _ed; i++) if (a[i] & 1) for (int j = (1), _ed = (n + 1); j < _ed; j++) if (bo[i][j]) ae(i, j, 1); s = n + 1, t = n + 2; for (int i = (1), _ed = (n + 1); i < _ed; i++) if (a[i] & 1) ae(s, i, 2); else ae(i, t, 2); int su = dinic(); if (su != n) { printf( Impossible n ); return 0; } for (int i = (0), _ed = (eid); i < _ed; i++) if (uof(i) != s && vof(i) != t && flowof(i) == 1) { nei[uof(i)].push_back(vof(i)); nei[vof(i)].push_back(uof(i)); } for (int i = (1), _ed = (n + 1); i < _ed; i++) if (!vis[i]) { ++cur; dfs(i); } printf( %d , cur); for (int i = (1), _ed = (cur + 1); i < _ed; i++) { printf( n%d , ans[i].size()); for (int j = (0), _ed = (((int)(ans[i]).size())); j < _ed; j++) printf( %d , ans[i][j]); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTP_4_V
`define SKY130_FD_SC_HDLL__DLRTP_4_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTP_4_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c h, c n) { return {h, n}; } template <class c> auto dud(c* r) -> decltype(cerr << *r); template <class c> char dud(...); struct muu { template <class c> muu& operator<<(const c&) { return *this; } muu& operator()() { return *this; } }; const int N = 1e5 + 7; long long tab[N]; int n; long long inf = 1e18; void fail() { printf( No n ); exit(0); } int main() { scanf( %d , &n); for (int i = 2; i <= n; i += 2) scanf( %lld , tab + i); long long sum = 0; for (int i = 2; i <= n; i += 2) { long long nsum = inf; for (int d = 1; d * d <= tab[i]; ++d) { if (tab[i] % d == 0) { long long a = (tab[i] / d) - d; long long b = (tab[i] / d) + d; if (a % 2 == 0 && b % 2 == 0) { if (a * a > 4 * sum) { nsum = min(nsum, (b * b) / 4); } } } } (muu() << __FUNCTION__ << # << 67 << : ) << i << << nsum; if (nsum == inf) fail(); tab[i - 1] = nsum - sum - tab[i]; sum = nsum; } printf( Yes n ); for (int i = 1; i <= n; ++i) printf( %lld , tab[i]); printf( n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_BLACKBOX_V
`define SKY130_FD_SC_HS__OR4B_BLACKBOX_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4b (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_BLACKBOX_V
|
// Copyright (c) 2015 The Connectal Project
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module LinkInverter(CLK,
RST,
put,
EN_put,
RDY_put,
get,
EN_get,
RDY_get,
modReady,
inverseReady
);
parameter DATA_WIDTH = 1;
input CLK;
input RST;
output [DATA_WIDTH-1 : 0] get;
input [DATA_WIDTH-1 : 0] put;
input EN_get;
input EN_put;
output RDY_get;
output RDY_put;
output modReady;
output inverseReady;
// will this work?
assign get = put;
assign RDY_get = 1;
assign RDY_put = 1;
assign modReady = EN_get;
assign inverseReady = EN_put;
endmodule // LinkInverter
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:27:54 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_0_0/system_util_vector_logic_0_0_stub.v
// Design : system_util_vector_logic_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "util_vector_logic,Vivado 2016.4" *)
module system_util_vector_logic_0_0(Op1, Op2, Res)
/* synthesis syn_black_box black_box_pad_pin="Op1[0:0],Op2[0:0],Res[0:0]" */;
input [0:0]Op1;
input [0:0]Op2;
output [0:0]Res;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> all; void backtrack(long long x, int cnt4, int cnt7) { if (x > 1e10) return; if (cnt4 == cnt7) all.push_back(x); long long nxt = x * 10 + 4; backtrack(nxt, cnt4 + 1, cnt7); nxt = x * 10 + 7; backtrack(nxt, cnt4, cnt7 + 1); } int main() { std::ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; backtrack(0, 0, 0); sort(all.begin(), all.end()); cout << *lower_bound(all.begin(), all.end(), n); return 0; }
|
// DESCRIPTION: Verilator: Check initialisation of cloned clock variables
//
// This tests issue 1327 (Strange initialisation behaviour with
// "VinpClk" cloned clock variables)
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Rupert Swarbrick (Argon Design).
// bug1327
// This models some device under test with an asynchronous reset pin
// which counts to 15.
module dut (input wire clk,
input wire rst_n,
output wire done);
reg [3:0] counter;
always @(posedge clk or negedge rst_n) begin
if (rst_n & ! clk) begin
$display("[%0t] %%Error: Oh dear! 'always @(posedge clk or negedge rst_n)' block triggered with clk=%0d, rst_n=%0d.",
$time, clk, rst_n);
$stop;
end
if (! rst_n) begin
counter <= 4'd0;
end else begin
counter <= counter < 4'd15 ? counter + 4'd1 : counter;
end
end
assign done = rst_n & (counter == 4'd15);
endmodule
module t(input wire clk,
input wire rst_n);
wire dut_done;
// A small FSM for driving the test
//
// This is just designed to be enough to force Verilator to make a
// "VinpClk" variant of dut_rst_n.
// Possible states:
//
// 0: Device in reset
// 1: Device running
// 2: Device finished
reg [1:0] state;
always @(posedge clk or negedge rst_n) begin
if (! rst_n) begin
state <= 0;
end else begin
if (state == 2'd0) begin
// One clock after resetting the device, we switch to running
// it.
state <= 2'd1;
end
else if (state == 2'd1) begin
// If the device is running, we switch to finished when its
// done signal goes high.
state <= dut_done ? 2'd2 : 2'd1;
end
else begin
// If the dut has finished, the test is done.
$write("*-* All Finished *-*\n");
$finish;
end
end
end
wire dut_rst_n = rst_n & (state != 0);
wire done;
dut dut_i (.clk (clk),
.rst_n (dut_rst_n),
.done (dut_done));
endmodule
|
/*
In this test a single IOBUF is controlled by switches. There is also one
input (connected to a LED) and one oputput (controlled by a switch) that.
can be used for verification of 3-state I/O.
This test requires a physical jumper to be installed on the Basys3 board.
Depending on which pins are connected we have different truth tables of
LED output w.r.t. switch input.
Truth table. When JC.1 is connected to JC.2:
SW2 SW1 SW0 | LED1 LED0
0 0 0 | 0 0
0 0 1 | 1 1
0 1 0 | x x
0 1 1 | x x
1 0 0 | 0 0
1 0 1 | 1 1
1 1 0 | x x
1 1 1 | x x
Truth table. When JC.3 is connected to JC.2:
SW2 SW1 SW0 | LED1 LED0
0 0 0 | x 0
0 0 1 | x 1
0 1 0 | x 0
0 1 1 | x 0
1 0 0 | x 0
1 0 1 | x 1
1 1 0 | x 1
1 1 1 | x 1
*/
`default_nettype none
// ============================================================================
module top
(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led,
input wire jc1,
inout wire jc2,
output wire jc3,
input wire jc4 // unused
);
// ============================================================================
// IOBUF
wire io_i;
wire io_o;
wire io_t;
IOBUF # (
.IOSTANDARD("LVCMOS33"),
.DRIVE(12),
.SLEW("SLOW")
)
iobuf
(
.I (io_i),
.T (io_t),
.O (io_o),
.IO (jc2) // Directly to the module ledput
);
// ============================================================================
// SW0 controls IOBUF.I
assign io_i = sw[0];
// SW1 controls IOBUF.T
assign io_t = sw[1];
// SW2 controls OBUF.I (JC.3)
assign jc3 = sw[2];
// LED0 swdicates IOBUF.O
assign led[0] = io_o;
// LED1 is connected to JC.1
assign led[1] = jc1;
// Unused IOs - SW->LED passthrough.
assign led[15:2] = {sw[15:3], 1'd0};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22O_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A22O_PP_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a22o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22O_PP_SYMBOL_V
|
// 74181 4-bit ALU
module alu181(
input [3:0] a, b,
input m,
input c_,
input [3:0] s,
output [3:0] f,
output g, p,
output co_,
output eq
);
wire [3:0] s0 = {4{s[0]}};
wire [3:0] s1 = {4{s[1]}};
wire [3:0] s2 = {4{s[2]}};
wire [3:0] s3 = {4{s[3]}};
wire [3:0] u = ~((a) | (b & s0) | (~b & s1)); // 3 ands
wire [3:0] v = ~((~b & s2 & a) | (b & s3 & a)); // 2 ands
wire [3:0] w = u ^ v;
wire [3:0] z;
assign z[0] = ~(~m & c_);
assign z[1] = ~(~m & ((u[0]) | (v[0] & c_)));
assign z[2] = ~(~m & ((u[1]) | (u[0] & v[1]) | (v[1] & v[0] & c_)));
assign z[3] = ~(~m & ((u[2]) | (v[2] & u[1]) | (v[2] & u[0] & v[1]) | (v[2] & v[1] & v[0] & c_)));
assign g = ~((u[0] & v[1] & v[2] & v[3]) | (u[1] & v[2] & v[3]) | (u[2] & v[3]) | (u[3]));
assign p = ~(&v);
wire g2 = ~(&v & c_);
assign co_ = ~g2 | ~g;
assign f = w ^ z;
assign eq = &f;
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
#include <bits/stdc++.h> int main() { char g[100]; scanf( %s , g); for (int w = 0; g[w] != 0 ; w++) { if (g[w] >= 65 && g[w] <= 90) g[w] = g[w] + 32; } for (int w = 0; g[w] != 0 ; w++) { if (!(g[w] == a || g[w] == e || g[w] == i || g[w] == o || g[w] == u || g[w] == y )) printf( .%c , g[w]); } }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { string s; cin >> s; if (s.size() % 2) cout << NO n ; else { string word1 = , word2 = ; for (int i = 0; i < s.size() / 2; i++) word1 += s[i]; for (int i = s.size() / 2; i < s.size(); i++) word2 += s[i]; if (word1 == word2) cout << YES n ; else cout << NO n ; } } }
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#include <bits/stdc++.h> using namespace std; ifstream in( input.txt ); ofstream out( output.txt ); int main() { vector<int> a; int n, x; cin >> n >> x; a.resize(100001); vector<int> b; for (int i = 0; i < n; i++) { int t; cin >> t; a[t]++; b.push_back(t); } unsigned long long ans = 0; for (int i = 0; i < n; i++) { if ((b[i] ^ x) == b[i]) { ans += (a[b[i]] - 1); } else if ((b[i] ^ x) < 100001) { ans += a[b[i] ^ x]; } a[b[i]]--; } cout << ans; }
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#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const int prime = 9241; const long double pi = acos(-1.); int in[100005]; int masks[1000005]; bool used[1 << 22]; int main() { int n, m, d; scanf( %d%d%d , &n, &m, &d); for (int i = 0; i < m; i++) { int s; scanf( %d , &s); for (int j = 0; j < s; j++) { int a; scanf( %d , &a); a--; in[a] = i; } } int cur[25] = {}; for (int i = 0; i < m; i++) cur[i] = 0; for (int i = 0; i < d; i++) cur[in[i]]++; int mcnt = 0; masks[0] = 0; for (int i = 0; i < m; i++) if (cur[i] > 0) masks[0] |= 1 << i; mcnt++; for (int i = d; i < n; i++) { cur[in[i - d]]--; cur[in[i]]++; masks[mcnt] = 0; for (int j = 0; j < m; j++) if (cur[j] > 0) masks[mcnt] |= 1 << j; mcnt++; } queue<int> q; for (int i = 0; i < (1 << m); i++) used[i] = 0; for (int i = 0; i < mcnt; i++) { q.push(masks[i]); used[masks[i]] = 1; } while (!q.empty()) { int cur = q.front(); q.pop(); for (int i = 0; i < m; i++) { if (cur & (1 << i)) continue; int nw = cur | (1 << i); if (!used[nw]) { used[nw] = 1; q.push(nw); } } } int ans = 1000; for (int i = 0; i < (1 << m); i++) if (!used[i]) ans = min(ans, m - __builtin_popcount(i)); cout << ans << endl; return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx ) #pragma GCC optimize( unroll-loops ) using namespace std; template <typename T1, typename T2> inline void chkmin(T1 &first, T2 second) { if (first > second) first = second; } template <typename T1, typename T2> inline void chkmax(T1 &first, T2 second) { if (first < second) first = second; } template <typename T, typename U> inline ostream &operator<<(ostream &_out, const pair<T, U> &_p) { _out << _p.first << << _p.second; return _out; } template <typename T, typename U> inline istream &operator>>(istream &_in, pair<T, U> &_p) { _in >> _p.first >> _p.second; return _in; } template <typename T> inline ostream &operator<<(ostream &_out, const vector<T> &_v) { if (_v.empty()) { return _out; } _out << _v.front(); for (auto _it = ++_v.begin(); _it != _v.end(); ++_it) { _out << << *_it; } return _out; } template <typename T> inline istream &operator>>(istream &_in, vector<T> &_v) { for (auto &_i : _v) { _in >> _i; } return _in; } template <typename T> inline ostream &operator<<(ostream &_out, const set<T> &_s) { if (_s.empty()) { return _out; } _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) { _out << << *_it; } return _out; } template <typename T> inline ostream &operator<<(ostream &_out, const multiset<T> &_s) { if (_s.empty()) { return _out; } _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) { _out << << *_it; } return _out; } template <typename T> inline ostream &operator<<(ostream &_out, const unordered_set<T> &_s) { if (_s.empty()) { return _out; } _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) { _out << << *_it; } return _out; } template <typename T> inline ostream &operator<<(ostream &_out, const unordered_multiset<T> &_s) { if (_s.empty()) { return _out; } _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) { _out << << *_it; } return _out; } template <typename T, typename U> inline ostream &operator<<(ostream &_out, const map<T, U> &_m) { if (_m.empty()) { return _out; } _out << ( << _m.begin()->first << : << _m.begin()->second << ) ; for (auto _it = ++_m.begin(); _it != _m.end(); ++_it) { _out << , ( << _it->first << : << _it->second << ) ; } return _out; } template <typename T, typename U> inline ostream &operator<<(ostream &_out, const unordered_map<T, U> &_m) { if (_m.empty()) { return _out; } _out << ( << _m.begin()->first << : << _m.begin()->second << ) ; for (auto _it = ++_m.begin(); _it != _m.end(); ++_it) { _out << , ( << _it->first << : << _it->second << ) ; } return _out; } const int N = 1e5 + 5; int n, m; int dsu[N]; vector<pair<int, int>> edge[N]; vector<pair<int, pair<int, int>>> edges, v; set<pair<int, int>> used; int get(int i) { return i == dsu[i] ? i : dsu[i] = get(dsu[i]); } bool merge(int i, int j) { i = get(i); j = get(j); if (i == j) return false; dsu[i] = j; return true; } const int LOG = 18; int t; int tin[N], tout[N]; pair<int, int> up[LOG][N]; void dfs(int i, int p = -1) { tin[i] = t++; for (auto j : edge[i]) { if (j.first == p) continue; up[0][j.first] = {i, j.second}; dfs(j.first, i); } tout[i] = t++; } bool is_parent(int a, int b) { return tin[a] <= tin[b] && tout[b] <= tout[a]; } int lca(int a, int b) { int ans = 0; for (int t = 0; t < 2; ++t) { if (tin[a] > tin[b]) swap(a, b); if (!is_parent(b, a)) { for (int t = LOG; t--;) { int c = up[t][b].first; if (!is_parent(c, a)) { chkmax(ans, up[t][b].second); b = c; } } chkmax(ans, up[0][b].second); b = up[0][b].first; } assert(is_parent(b, a)); } return ans; } int main() { ios::sync_with_stdio(0); srand(time(0)); cin >> n >> m; edges.resize(m); for (int i = 0; i < m; ++i) { cin >> edges[i].second.first >> edges[i].second.second >> edges[i].first; } v = edges; sort(edges.begin(), edges.end()); bool was = false; for (int i = 0; i <= n; ++i) dsu[i] = i; for (auto i : edges) { if (merge(i.second.first, i.second.second)) { used.insert(i.second); edge[i.second.first].push_back({i.second.second, i.first}); edge[i.second.second].push_back({i.second.first, i.first}); } } up[0][1] = {1, 0}; dfs(1); for (int t = 0; t + 1 < LOG; ++t) { for (int i = 1; i <= n; ++i) { up[t + 1][i] = {up[t][up[t][i].first].first, max(up[t][i].second, up[t][up[t][i].first].second)}; } } for (auto i : v) { if (used.count(i.second)) { continue; } cout << lca(i.second.first, i.second.second) << n ; } }
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#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d, case1, case2, case3, case4; cin >> a >> b >> c >> d; case1 = abs(pow(a, 2) + pow(b, 2) - pow(c, 2)) - 2 * a * b; case2 = abs(pow(a, 2) + pow(b, 2) - pow(d, 2)) - 2 * b * a; case3 = abs(pow(a, 2) + pow(c, 2) - pow(d, 2)) - 2 * a * c; case4 = abs(pow(b, 2) + pow(c, 2) - pow(d, 2)) - 2 * b * c; if ((case1 < 0) || (case2 < 0) || (case3 < 0) || (case4 < 0)) { cout << TRIANGLE ; } else if ((case1 == 0) || (case2 == 0) || (case3 == 0) || (case4 == 0)) { cout << SEGMENT ; } else cout << IMPOSSIBLE ; return 0; }
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#include <bits/stdc++.h> using namespace std; int vis[100005], tick = 0; vector<int> G[100005]; int a[200001], b[200005]; int main() { int n, m, h, t; scanf( %d%d%d%d , &n, &m, &h, &t); for (int i = 1; i <= m; ++i) { int u, v; scanf( %d%d , &u, &v); G[u].push_back(v); G[v].push_back(u); a[i * 2 - 1] = u; b[i * 2 - 1] = v; a[i * 2] = v; b[i * 2] = u; } for (int i = 1; i <= n; ++i) sort(G[i].begin(), G[i].end()); bool flag = 0; for (int i = 1; i <= 2 * m; ++i) { int u = a[i], v = b[i]; if (G[u].size() - 1 < h || G[v].size() - 1 < t) continue; bool done = 0; if (G[u].size() > G[v].size()) { swap(u, v); done = 1; } int acnt = 0, bcnt = 0, bothcnt = 0; for (int j = 0; j < G[u].size(); ++j) { if (G[u][j] == v) continue; if (binary_search(G[v].begin(), G[v].end(), G[u][j])) { bothcnt++; } else { acnt++; } } bcnt = G[v].size() - 1 - bothcnt; if (done) { swap(acnt, bcnt); swap(u, v); } if (max(0, h - acnt) + max(0, t - bcnt) > bothcnt) continue; tick++; for (int j = 0; j < G[u].size(); ++j) if (G[u][j] != v) { vis[G[u][j]] = tick; } vector<int> A, B, BOTH; tick++; for (int j = 0; j < G[v].size(); ++j) if (G[v][j] != u) { if (vis[G[v][j]] == tick - 1) { BOTH.push_back(G[v][j]); } else { B.push_back(G[v][j]); } vis[G[v][j]] = tick; } for (int j = 0; j < G[u].size(); ++j) if (G[u][j] != v) { if (vis[G[u][j]] != tick) { A.push_back(G[u][j]); } } if (max(0, h - (int)A.size()) + max(0, t - (int)B.size()) <= (int)BOTH.size()) { flag = 1; puts( YES ); printf( %d %d n , u, v); int k = 0; while (A.size() < h) A.push_back(BOTH[k++]); while (B.size() < t) B.push_back(BOTH[k++]); for (int i = 0; i < h; ++i) printf( %d%c , A[i], n [i == h - 1]); for (int i = 0; i < t; ++i) printf( %d%c , B[i], n [i == t - 1]); break; } } if (!flag) puts( NO ); }
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0(clk, ce, a, b, p);
input clk;
input ce;
input[16 - 1 : 0] a; // synthesis attribute keep a "true"
input[8 - 1 : 0] b; // synthesis attribute keep b "true"
output[24 - 1 : 0] p;
reg[24 - 1 : 0] p;
wire [24 - 1 : 0] tmp_product;
assign tmp_product = a * b;
always @ (posedge clk) begin
if (ce) begin
p <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0 nfa_accept_samples_generic_hw_mul_16ns_8ns_24_2_MAC2S_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
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/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_eth_fcs_insert
*/
module test_axis_eth_fcs_insert_pad;
// Parameters
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tvalid,
s_axis_tlast,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser,
busy
);
// dump file
$dumpfile("test_axis_eth_fcs_insert_pad.lxt");
$dumpvars(0, test_axis_eth_fcs_insert_pad);
end
axis_eth_fcs_insert #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.busy(busy)
);
endmodule
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module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [255:0] din, output [255:0] dout);
clb_NCY0_MX # (.LOC("SLICE_X20Y100"), .BEL("A6LUT"), .N(0))
am (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y101"), .BEL("A6LUT"), .N(0))
a5 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[8 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y102"), .BEL("B6LUT"), .N(1))
bm (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[16 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y103"), .BEL("B6LUT"), .N(1))
b5 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[24 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y104"), .BEL("C6LUT"), .N(2))
cm (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[32 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y105"), .BEL("C6LUT"), .N(2))
c5 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[40 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y106"), .BEL("D6LUT"), .N(3))
dm (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[48 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y107"), .BEL("D6LUT"), .N(3))
d5 (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[56 +: 8]));
endmodule
module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X16Y129_FIXME";
parameter BEL="A6LUT_FIXME";
parameter N=-1;
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
always @(*) begin
s = din[7:4];
s[N] = o6;
end
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
endmodule
module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X16Y129_FIXME";
parameter BEL="A6LUT_FIXME";
parameter N=-1;
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
reg [3:0] di;
always @(*) begin
s = din[7:4];
s[N] = o6;
di = {din[3:0]};
di[N] = o5;
end
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 00:02:33 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_FlagReg_1_0/RAT_FlagReg_1_0_stub.v
// Design : RAT_FlagReg_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "FlagReg,Vivado 2016.4" *)
module RAT_FlagReg_1_0(IN_FLAG, LD, SET, CLR, CLK, OUT_FLAG)
/* synthesis syn_black_box black_box_pad_pin="IN_FLAG,LD,SET,CLR,CLK,OUT_FLAG" */;
input IN_FLAG;
input LD;
input SET;
input CLR;
input CLK;
output OUT_FLAG;
endmodule
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#include <bits/stdc++.h> using namespace std; template <typename T> void read(T& x) { x = 0; int fl = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) fl = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } x *= fl; } template <typename T, typename... Args> inline void read(T& t, Args&... args) { read(t); read(args...); } const int N = 3005; int T, n, a[N], b[N]; int main() { for (read(T); T; T--) { read(n); for (int i = 1; i <= n; i++) read(a[i]), b[i] = a[i]; sort(b + 1, b + n + 1); int len = unique(b + 1, b + n + 1) - (b + 1); for (int i = 1; i <= n; i++) a[i] = lower_bound(b + 1, b + n + 1, a[i]) - b; int now = 1, mx = 0; while (now <= n) { int len = 0; for (int i = 1; i <= n; i++) if (a[i] == now) len++, now++; mx = max(mx, len); } printf( %d n , n - mx); } return 0; }
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#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( -ffloat-store ) #pragma GCC optimize( -fno-defer-pop ) long long int power(long long int a, long long int b, long long int m) { if (b == 0) return 1; if (b == 1) return a % m; long long int t = power(a, b / 2, m) % m; t = (t * t) % m; if (b & 1) t = ((t % m) * (a % m)) % m; return t; } long long int modInverse(long long int a, long long int m) { return power(a, m - 2, m); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int i, j, k, l, n; cin >> n; long long int ar[n + 1]; for (i = 1; i <= n; i++) { cin >> ar[i]; } long long int L[n + 2], R[n + 2]; memset(L, 0, sizeof(L)); memset(R, 0, sizeof(R)); L[1] = 1; for (i = 2; i <= n; i++) { L[i] = min(ar[i], L[i - 1] + 1); } R[n] = 1; for (i = n - 1; i > 0; i--) { R[i] = min(ar[i], 1 + R[i + 1]); } long long int an = -1e18; for (i = 1; i <= n; i++) { an = max(an, min(L[i], R[i])); } cout << an; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); string s; cin >> s; for (int i = 0; i < (int)s.size(); i++) { if (s[i] == . ) cout << 0 ; else { if (s[i + 1] == . ) cout << 1 ; else cout << 2 ; i++; } } cout << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1000 + 10, M = 2000 + 10; int n, m, s, t; int h[N], ecnt, nxt[M], v[M]; bool mp[N][N]; int dis[2][N], ans; void _add(int x, int y) { nxt[++ecnt] = h[x]; v[ecnt] = y; h[x] = ecnt; mp[x][y] = 1; } queue<int> que; void dijkstra(int s, int *dis) { for (int i = 1; i <= n; ++i) dis[i] = -1; que.push(s); dis[s] = 0; while (!que.empty()) { int u = que.front(); que.pop(); for (int i = h[u]; i; i = nxt[i]) if (dis[v[i]] == -1) { dis[v[i]] = dis[u] + 1; que.push(v[i]); } } } int main() { ios::sync_with_stdio(false); cin >> n >> m >> s >> t; ecnt = 1; for (int i = 1; i <= m; ++i) { int x, y; cin >> x >> y; _add(x, y); _add(y, x); } dijkstra(s, dis[0]); dijkstra(t, dis[1]); for (int i = 1; i <= n; ++i) for (int j = i + 1; j <= n; ++j) if (!mp[i][j]) { ans += min(dis[0][i] + dis[1][j] + 1, dis[1][i] + dis[0][j] + 1) >= dis[0][t]; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int dx[] = {1, -1, 0, 0}; int dy[] = {0, 0, 1, -1}; int dx2[] = {1, -1, 0, 0, -1, 1, -1, 1}; int dy2[] = {0, 0, 1, -1, 1, -1, -1, 1}; int read() { int x; scanf( %d , &x); return x; } int ans[100005]; int a[100005]; int used[1000001]; int main() { int n = read(); int m = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = n; i >= 1; i--) { if (used[a[i]]) ans[i] = ans[i + 1]; else ans[i] = ans[i + 1] + 1, used[a[i]] = 1; } while (m--) { printf( %d n , ans[read()]); } return 0; }
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#include <bits/stdc++.h> using namespace std; int mod = (int)1e9 + 7; struct matrix { int A[2][2] = {0}; matrix operator*(matrix B) { matrix C; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) for (int k = 0; k < 2; k++) C[i][j] = (C[i][j] + 1ll * A[i][k] * B[k][j]) % mod; return C; } matrix operator+(matrix B) { matrix C; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) C[i][j] = (A[i][j] + B[i][j]) % mod; return C; } matrix pow(int n) { matrix B, C = *this; for (int i = 0; i < 2; i++) B[i][i] = 1; while (n) { if (n & 1) B = B * C; C = C * C; n >>= 1; } return B; } int *operator[](int i) { return A[i]; } }; matrix fib; struct segment_tree { struct node { node *node_l, *node_r; int l, r; matrix sum, mul; } * root; node *build(vector<int> &a, int l, int r) { node *res = new node; res->l = l; res->r = r; res->mul[0][0] = res->mul[1][1] = 1; if (l == r) { res->sum = fib.pow(a[l]); res->node_l = res->node_r = nullptr; } else { int m = (l + r) >> 1; res->node_l = build(a, l, m); res->node_r = build(a, m + 1, r); res->sum = res->node_l->sum + res->node_r->sum; } return res; } void build(vector<int> &a) { root = build(a, 0, a.size() - 1); } void push(node *root) { if (root->mul[1][0] + root->mul[0][0] + root->mul[0][1] + root->mul[1][1] == 2) return; if (root->node_l) { root->node_l->mul = root->node_l->mul * root->mul; root->node_l->sum = root->node_l->sum * root->mul; } if (root->node_r) { root->node_r->mul = root->node_r->mul * root->mul; root->node_r->sum = root->node_r->sum * root->mul; } root->mul[0][0] = root->mul[1][1] = 1; root->mul[1][0] = root->mul[0][1] = 0; } void update(node *root, int l, int r) { if (root->l > r || root->r < l) return; if (root->l >= l && root->r <= r) { root->sum = root->sum * fib; root->mul = root->mul * fib; } else { push(root); update(root->node_l, l, r); update(root->node_r, l, r); root->sum = root->node_l->sum + root->node_r->sum; } } void update(int l, int r) { update(root, l, r); } matrix query(node *root, int l, int r) { push(root); if (root->l > r || root->r < l) return matrix(); if (root->l >= l && root->r <= r) return root->sum; return query(root->node_l, l, r) + query(root->node_r, l, r); } matrix query(int l, int r) { return query(root, l, r); } }; int main() { fib[0][1] = fib[1][0] = fib[0][0] = 1; int n, m; scanf( %d %d , &n, &m); vector<int> v(n); for (int &p : v) scanf( %d , &p); segment_tree sg; sg.build(v); for (int i = 0; i < m; i++) { int t, l, r; scanf( %d %d %d , &t, &l, &r); l--, r--; if (t == 1) { int x; scanf( %d , &x); matrix tmp = fib; fib = fib.pow(x); sg.update(l, r); fib = tmp; } else { printf( %d n , sg.query(l, r)[0][1]); } } }
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// Problem: A. Dungeon // Contest: Codeforces - Educational Codeforces Round 100 (Rated for Div. 2) // URL: https://codeforces.com/problemset/problem/1463/A // Memory Limit: 256 MB // Time Limit: 2000 ms // // Powered by CP Editor (https://cpeditor.org) #include<bits/stdc++.h> using namespace std; #pragma GCC optimize( O2 ) #define M 1000000007 #define ll long long int #define pb push_back #define pf push_front #define all(x) x.begin(), x.end() #define pob pop_back #define pof pop_front #define debug1(x) cout<<#x<< <<x<<endl; #define debug2(x,y) cout<<#x<< <<x<< <<#y<< <<y<<endl; #define debug3(x,y,z) cout<<#x<< <<x<< <<#y<< <<y<< <<#z<< <<z<<endl; #define present(c,x) ((c).find(x) != (c).end()) #define null NULL #define mp make_pair #define sz(x) (ll)x.size() #define fi first #define se second #define boost ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL); #define inf 1e18 //#define endl n //unsigned seed = std::chrono::system_clock::now().time_since_epoch().count(); //shuffle (foo.begin(), foo.end(), std::default_random_engine(seed)); #define ordered_set tree<ll, null_type,less<ll>,rb_tree_tag,tree_order_statistics_node_update> typedef pair<int, int> pii; #define pi (3.14159265358979323846264338327950288) template<typename T> void printv(const T& t) { std::copy(t.cbegin(), t.cend(), std::ostream_iterator<typename T::value_type>(std::cout, , )); cout<<endl; } ll modpower(ll a,ll b,ll c) { ll res=1; while(b) { if(b&1LL) res=(res*a)%c; a=(a*a)%c; b>>=1; } return res; } //-------------------------------Template--Above----------------------------------------------- void solve(){ vector<ll>v(3); for(ll i=0;i<3;i++) cin>>v[i]; sort(all(v)); ll sum=v[0]+v[1]+v[2]; if(sum%9!=0){ cout<< NO <<endl; return; } if(v[0]<sum/9){ cout<< NO <<endl; return; } cout<< YES <<endl; return; } int main() { boost ll t; // t=1; cin>>t; while(t--){ solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__MUX2I_PP_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void solve(); int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int times = 1; cin >> times; for (int i = 0; i < times; i++) { solve(); cout << n ; } return 0; } long long a, b, c, d, e, f, g, h; long long arr[500000 + 50]; void solve() { cin >> a >> b >> c; for (int i = 1; i <= a; i++) cin >> arr[i]; sort(arr + 1, arr + a + 1); long long dp[a + 50][2]; for (int i = 1; i <= a; i++) dp[i][0] = dp[i][1] = 21474836477777; dp[0][0] = dp[0][1] = 0; for (int i = 1; i <= a; i++) { if (i > 0) { dp[i][0] = min(dp[i][0], dp[i - 1][0] + arr[i]); dp[i][0] = min(dp[i][0], dp[i - 1][1] + arr[i]); } if (i >= c) { dp[i][1] = min(dp[i][1], dp[i - c][0] + arr[i]); dp[i][1] = min(dp[i][1], dp[i - c][1] + arr[i]); } } int ans = 0; for (int i = 1; i <= a; i++) { if (dp[i][0] <= b || dp[i][1] <= b) ans = i; } cout << ans; }
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#include <bits/stdc++.h> using namespace std; int n, m; char matr[1010][1010]; int dx[] = {-1, 0, 1, 0}; int dy[] = {0, -1, 0, 1}; bool Field(int x, int y) { if (x < 1 || x > n) return false; if (y < 1 || y > m) return false; return true; } int color[1010][1010]; int ans[1010][1010]; int f[10]; int H; void Solve() { int i, j, o; int x2, y2; for (j = 1; j <= m; j++) { for (i = 1; i <= n; i++) { if (color[j][i]) continue; if (matr[j][i] == . ) { for (o = 0; o <= 3; o++) { x2 = i + dx[o]; y2 = j + dy[o]; if (!Field(x2, y2)) continue; if (color[y2][x2]) continue; if (matr[y2][x2] != . ) continue; color[j][i] = 1; color[y2][x2] = 1; memset(f, 0, sizeof(f)); ; ans[j][i] = H; ans[y2][x2] = H; H++; color[j][i] = 1; color[y2][x2] = 1; break; } } } } } int C; int dfs(int x, int y) { int o; int x2, y2; int res; res = 1; color[y][x] = C; for (o = 0; o <= 3; o++) { x2 = x + dx[o]; y2 = y + dy[o]; if (!Field(x2, y2)) continue; if (color[y2][x2] == C) continue; if (ans[y2][x2] != ans[y][x]) continue; if (matr[y2][x2] != . ) continue; res += dfs(x2, y2); } return res; } void Solve2() { int i, j, o; int x2, y2; memset(color, 0, sizeof(color)); ; int flag; for (j = 1; j <= m; j++) { for (i = 1; i <= n; i++) { if (matr[j][i] == . && ans[j][i] == -1) { flag = 0; for (o = 0; o <= 3; o++) { x2 = i + dx[o]; y2 = j + dy[o]; if (!Field(x2, y2)) continue; if (ans[y2][x2] == -1) continue; C++; if (dfs(x2, y2) < 5) { ans[j][i] = ans[y2][x2]; flag = 1; break; } } if (!flag) { printf( -1 n ); exit(0); } } } } } vector<pair<int, int> > t; void dfs2(int x, int y) { int o; int x2, y2; color[y][x] = C; t.push_back(make_pair(x, y)); for (o = 0; o <= 3; o++) { x2 = x + dx[o]; y2 = y + dy[o]; if (!Field(x2, y2)) continue; if (color[y2][x2] == C) continue; if (matr[y2][x2] != . ) continue; if (ans[y2][x2] >= 0 && ans[y2][x2] <= 9) { f[ans[y2][x2]] = 1; } if (ans[y2][x2] != ans[y][x]) continue; dfs2(x2, y2); } } void Solve3() { int i, j, o; int k; for (j = 1; j <= m; j++) { for (i = 1; i <= n; i++) { if (ans[j][i] >= 10) { memset(f, 0, sizeof(f)); ; C++; t.clear(); dfs2(i, j); k = 0; for (o = 0; o <= 9; o++) { if (!f[o]) { k = o; break; } } for (o = 0; o <= (int)t.size() - 1; o++) { ans[t[o].second][t[o].first] = k; } } } } } int main() { int i, j; scanf( %d %d , &m, &n); for (j = 1; j <= m; j++) { scanf( %s , matr[j] + 1); } memset(ans, -1, sizeof(ans)); Solve(); Solve2(); Solve3(); for (j = 1; j <= m; j++) { for (i = 1; i <= n; i++) { if (matr[j][i] == . ) { printf( %d , ans[j][i]); } else { printf( %c , matr[j][i]); } } printf( n ); } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; using pii = pair<int, int>; using pll = pair<long long, long long>; using vb = vector<bool>; using vi = vector<int>; using vl = vector<long long>; using vvb = vector<vector<bool>>; using vvi = vector<vector<int>>; using vvl = vector<vector<long long>>; using vpii = vector<pair<int, int>>; using mii = map<int, int>; template <typename... ArgTypes> void print(ArgTypes... args); template <typename... ArgTypes> void input(ArgTypes &...args); template <> void print() {} template <> void input() {} template <typename T, typename... ArgTypes> void print(T t, ArgTypes... args) { cout << t; print(args...); } template <typename T, typename... ArgTypes> void input(T &t, ArgTypes &...args) { cin >> t; input(args...); } void traverse(int n, int mul) { if (n == 0) return; int a = n - n / 2, b = n - n / 3; int x = 2, y = 3; if (a >= b) { swap(a, b); swap(x, y); } for (int i = 1; i <= a; i++) cout << mul << ; int remaining = n / x; traverse(remaining, mul * x); } int main() { ios_base::sync_with_stdio(0); int n; cin >> n; traverse(n, 1); }
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/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's reg2mem aligner ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Aligns register data to memory alignment. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_reg2mem.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.2 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_reg2mem(addr, lsu_op, regdata, memdata);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input [1:0] addr;
input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] regdata;
output [width-1:0] memdata;
//
// Internal regs and wires
//
reg [7:0] memdata_hh;
reg [7:0] memdata_hl;
reg [7:0] memdata_lh;
reg [7:0] memdata_ll;
assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};
//
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
default : memdata_hh = regdata[31:24];
endcase
end
//
// Mux to memdata[23:16]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
default : memdata_hl = regdata[7:0];
endcase
end
//
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
default : memdata_lh = regdata[15:8];
endcase
end
//
// Mux to memdata[7:0]
//
always @(regdata)
memdata_ll = regdata[7:0];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) & cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) & cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) & cond0 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1005; char ch[MAX]; int ans[MAX]; int main() { int n; scanf( %d%s , &n, ch); ans[0] = 1; for (int i = 1; i < n; i++) { if (ch[i - 1] == = ) ans[i] = ans[i - 1]; else if (ch[i - 1] == L ) { ans[i] = 1; for (int j = i - 1; j >= 0; j--) { if (ch[j] == L && ans[j] <= ans[j + 1]) ans[j] = ans[j + 1] + 1; else if (ch[j] == = && ans[j] != ans[j + 1]) ans[j] = ans[j + 1]; else break; } } else ans[i] = ans[i - 1] + 1; } for (int i = 0; i < n; i++) { if (i == 0) printf( %d , ans[i]); else printf( %d , ans[i]); } printf( n ); }
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#include <bits/stdc++.h> using namespace std; const int iinf = 1e9 + 7; const int oo = 0x3f3f3f3f; const long long linf = 1ll << 60; const double dinf = 1e60; template <typename T> inline void scf(T &x) { bool f = 0; x = 0; char c = getchar(); while ((c < 0 || c > 9 ) && c != - ) c = getchar(); if (c == - ) { f = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } if (f) x = -x; return; } template <typename T1, typename T2> void scf(T1 &x, T2 &y) { scf(x); return scf(y); } template <typename T1, typename T2, typename T3> void scf(T1 &x, T2 &y, T3 &z) { scf(x); scf(y); return scf(z); } template <typename T1, typename T2, typename T3, typename T4> void scf(T1 &x, T2 &y, T3 &z, T4 &w) { scf(x); scf(y); scf(z); return scf(w); } inline char mygetchar() { char c = getchar(); while (c == || c == n ) c = getchar(); return c; } template <typename T> inline bool chkmax(T &x, const T &y) { return y > x ? x = y, 1 : 0; } template <typename T> inline bool chkmin(T &x, const T &y) { return y < x ? x = y, 1 : 0; } const int maxn = 1e6 + 10; struct node { node *go[26], *par; int len, siz, tag; node() { memset(go, 0, sizeof go); par = 0; len = siz = tag = 0; } inline void cpy(node *u) { memcpy(go, u->go, sizeof go); par = u->par; return; } } * root, *last; vector<node *> lvl[maxn]; char s[maxn]; inline void expand(int id) { node *p = last, *np = new node; np->len = p->len + 1; np->siz = 1; while (p && !p->go[id]) p->go[id] = np, p = p->par; if (!p) np->par = root; else { node *q = p->go[id]; if (q->len == p->len + 1) np->par = q; else { node *nq = new node; nq->cpy(q); q->par = np->par = nq; nq->len = p->len + 1; while (p && p->go[id] == q) p->go[id] = nq, p = p->par; } } last = np; return; } inline void dfs(node *u) { if (!~u->tag) return; u->tag = -1; lvl[u->len].push_back(u); for (int i = 0, _end_ = (26); i < _end_; ++i) if (u->go[i]) dfs(u->go[i]); return; } int main() { root = new node; last = root; char c = getchar(); while (c < a || c > z ) c = getchar(); while (c >= a && c <= z ) expand(c - a ), c = getchar(); dfs(root); for (int i = last->len; i; --i) for (int j = 0, _end_ = ((int)lvl[i].size()); j < _end_; ++j) if (lvl[i][j]->par) lvl[i][j]->par->siz += lvl[i][j]->siz; int q; scf(q); while (q--) { scanf( %s , s); int n = strlen(s), matched = 0, ans = 0; node *u = root; for (int i = 0, _end_ = (n << 1); i < _end_; ++i) { int id = s[i % n] - a ; while (u && !u->go[id]) u = u->par, matched = u ? u->len : 0; if (!u) u = root; else { u = u->go[id]; ++matched; while (u->par && u->par->len >= n) u = u->par, matched = u->len; if (matched >= n && u->tag != q) u->tag = q, ans += u->siz; } } printf( %d n , ans); } return 0; }
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