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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A2111OI_PP_BLACKBOX_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111OI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_1_V
`define SKY130_FD_SC_LS__DLRTP_1_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_1_V
|
#include <bits/stdc++.h> int main() { int n, i, j, r; char lvl[110]; scanf( %d , &n); scanf( %s , lvl); for (r = 1; r < n; r++) { for (i = 0; i < n; i++) { for (j = 0; j <= 4; j++) { if (i + j * r >= n || lvl[i + j * r] != * ) break; } if (j >= 5) { printf( yes n ); return 0; } } } printf( no n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const long long N = 2e5 + 7; const int mod = 1e9 + 7; bool cmp(const pair<long long, long long>& a, const pair<long long, long long>& b) { return a.first < b.first; } long long median(long long a, long long b, long long c, long long d) { vector<long long> v(4); v[0] = a; v[1] = b; v[2] = c; v[3] = d; sort(v.begin(), v.end()); return ((v[1] + v[2]) / 2); } void solve() { long long n, m; cin >> n >> m; long long a[n][m]; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { cin >> a[i][j]; } } long long ans = 0; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { long long k = median(a[i][j], a[i][m - 1 - j], a[n - 1 - i][j], a[n - 1 - i][m - 1 - j]); ans += abs(k - a[i][j]); } } cout << ans << n ; return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { solve(); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCIN_SYMBOL_V
`define SKY130_FD_SC_HS__FAHCIN_SYMBOL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCIN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n; map<int, int> a; void reset() { a.clear(); } void input() { cin >> n; int c; for (int(i) = (0); (i) < (n); ++i) { cin >> c; a[c]++; } } bool check(int s) { for (auto it = a.begin(); it != a.end(); ++it) { double b = (double)(it->second); if ((int)ceil(b / s) != (int)floor(b / (s - 1))) { return false; } } return true; } void process() { double d = (double)n; int mn = n + 1; for (auto it = a.begin(); it != a.end(); ++it) mn = min(mn, it->second); int m = n + 1; for (int(s) = (2); (s) < (mn + 2); ++s) { bool ok = true; int tmp = 0; for (auto it = a.begin(); it != a.end(); ++it) { int f = it->second; int q = (int)ceil(1.0 * f / s); if (f < q * (s - 1)) { ok = false; break; } tmp += q; } if (ok) m = min(m, tmp); } cout << m << n ; } void solve() { reset(); input(); process(); } int main() { ios::sync_with_stdio(false); cin.tie(0); int T; cin >> T; while (T--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, d; cin >> n >> d; int t[n], sum = 0, rest = (n - 1) * 10; for (int i = 0; i < n; i++) { cin >> t[i]; sum = sum + t[i]; } if ((rest + sum) > d) { cout << -1 ; return 0; } else { int bal = d - sum, max; max = bal / 5; cout << max; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long a[300010], po[300010], ans; int n, p = 1e9 + 7; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %I64d , &a[i]); sort(a + 1, a + n + 1); po[0] = 1; for (int i = 1; i <= n; i++) po[i] = po[i - 1] * 2 % p; for (int i = 1; i <= n; i++) (ans += a[i] * (p + po[i - 1] - po[n - i]) % p) %= p; printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, deg[N], fa[N]; int root = 0; vector<pair<pair<int, int>, int> > ans; struct edge { int to, val; edge() {} edge(int to, int val) : to(to), val(val) {} }; vector<edge> G[N]; vector<int> leaf[N]; void add_edge(int x, int y, int z) { G[x].push_back(edge(y, z)); } void init() { scanf( %d , &n); int x, y, z; if (n == 2) { scanf( %d%d%d , &x, &y, &z); printf( YES n1 n1 2 %d n , z); exit(0); } for (int i = 1; i < n; ++i) { scanf( %d%d%d , &x, &y, &z); add_edge(x, y, z); add_edge(y, x, z); ++deg[x], ++deg[y]; } } void pre(int x, int f) { fa[x] = f; for (int i = 0; i < (int)G[x].size(); ++i) { int to = G[x][i].to, w = G[x][i].val; if (to == f) continue; pre(to, x); leaf[x].push_back(leaf[to][0]); } if (G[x].size() == 1) { leaf[x].push_back(x); } } void add_to_root(int x, int val) { if (leaf[x].size() >= 2) { int f1 = leaf[x][0], f2 = leaf[x][1]; ans.push_back(make_pair(make_pair(root, f1), val / 2)); ans.push_back(make_pair(make_pair(root, f2), val / 2)); ans.push_back(make_pair(make_pair(f1, f2), -val / 2)); } else { ans.push_back(make_pair(make_pair(root, x), val)); } } void dfs(int x, int f) { for (int i = 0; i < (int)G[x].size(); ++i) { int to = G[x][i].to, w = G[x][i].val; if (to == f) continue; dfs(to, x); add_to_root(to, w); if (x != root) add_to_root(x, -w); } } void solve() { int flag = 1; for (int i = 1; i <= n; ++i) { if (deg[i] == 2) { puts( NO ); return; } } puts( YES ); for (int i = 1; i <= n; ++i) { if (G[i].size() == 1) { root = i; break; } } pre(root, 0); dfs(root, 0); printf( %d n , ans.size()); for (int i = 0; i < (int)ans.size(); ++i) { printf( %d %d %d n , ans[i].first.first, ans[i].first.second, ans[i].second); } } int main() { init(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[200000 + 1]; int n; int b[200000 + 1]; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; b[a[i]] = 0; } int max = -1; int k = 0; int numb; for (int i = n; i > 0; i--) { k = 0; if (b[a[i]] == 0) { b[a[i]] = 1; k = n - i; } if (k > max) { max = k; numb = a[i]; } } cout << numb; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:14:28 05/18/2015
// Design Name: median5x5
// Module Name: /home/vka/Programming/VHDL/workspace/sysrek/skin_color_segm/tb_median5x5.v
// Project Name: vision
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: median5x5
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_median5x5(
);
wire rx_pclk;
wire rx_de;
wire rx_hsync;
wire rx_vsync;
wire [7:0] rx_red;
wire [7:0] rx_green;
wire [7:0] rx_blue;
wire tx_de;
wire tx_hsync;
wire tx_vsync;
wire [7:0] tx_red;
wire [7:0] tx_green;
wire [7:0] tx_blue;
// --------------------------------------
// HDMI input
// --------------------------------------
hdmi_in file_input (
.hdmi_clk(rx_pclk),
.hdmi_de(rx_de),
.hdmi_hs(rx_hsync),
.hdmi_vs(rx_vsync),
.hdmi_r(rx_red),
.hdmi_g(rx_green),
.hdmi_b(rx_blue)
);
// proccessing
reg [7:0] median_r;
reg [7:0] median_g;
reg [7:0] median_b;
wire median;
wire median_de;
wire median_vsync;
wire median_hsync;
median5x5 #
(
.H_SIZE(10'd83)
)
med5
(
.clk(rx_pclk),
.ce(1'b1),
.rst(1'b0),
.mask((rx_red == 8'hFF) ? 1'b1 : 1'b0),
.in_de(rx_de),
.in_vsync(rx_vsync),
.in_hsync(rx_hsync),
.median(median),
.out_de(median_de),
.out_vsync(median_vsync),
.out_hsync(median_hsync)
);
always @(posedge rx_pclk) begin
median_r = (median) ? 8'hFF : 8'h00;
median_g = (median) ? 8'hFF : 8'h00;
median_b = (median) ? 8'hFF : 8'h00;
end
// --------------------------------------
// Output assigment
// --------------------------------------
assign tx_de = median_de;
assign tx_hsync = median_hsync;
assign tx_vsync = median_vsync;
assign tx_red = median_r;
assign tx_green = median_g;
assign tx_blue = median_b;
// --------------------------------------
// HDMI output
// --------------------------------------
hdmi_out file_output (
.hdmi_clk(rx_pclk),
.hdmi_vs(tx_vsync),
.hdmi_de(tx_de),
.hdmi_data({8'b0,tx_red,tx_green,tx_blue})
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { long long int n, m; cin >> n >> m; long long int a[n], b[m]; long long int aux[n]; for (long long int i = 0; i < n; ++i) { cin >> a[i]; if (i == 0) aux[i] = a[i]; else aux[i] = aux[i - 1] + a[i]; } for (long long int i = 0; i < m; ++i) cin >> b[i]; long long int j = 0; for (long long int i = 0; i < m; ++i) { while (j < n && aux[j] < b[i]) ++j; if (j == 0) cout << j + 1 << << b[i] << endl; else cout << j + 1 << << b[i] - aux[j - 1] << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { string s, t; cin >> s >> t; int n = s.length(); int x = t.length(); vector<int> lft(x); vector<int> rgt(x); int l = 0; for (int i = 0; i < n && l < x; ++i) { if (s[i] == t[l]) { lft[l++] = i; } } l = x - 1; for (int i = n - 1; i >= 0 && l >= 0; --i) { if (s[i] == t[l]) { rgt[l--] = i; } } int mx = 0; mx = max(mx, lft[0]); mx = max(mx, rgt[0]); mx = max(mx, n - 1 - lft[x - 1]); mx = max(mx, n - 1 - rgt[x - 1]); for (int i = 1; i < x; ++i) mx = max(mx, rgt[i] - lft[i - 1] - 1); cout << mx; }
|
// --------------------------------------------------------------------
// Virtual JTAG DSKY console
// --------------------------------------------------------------------
module vji_dsky(
input clk, // main clock
input [7:0] data_in, // data input
output reg [3:0] sel_out, // select output register
output reg [4:0] key_pad, // KeyPad output
output key_rdy, // Keyboard valid signal.
output reg test_out // Test output line
);
// --------------------------------------------------------------------
// Instantiate Virtual JTAG
// --------------------------------------------------------------------
wire tdo; // vjtag output data signals
wire tck; // vjtag Clock signals
wire tdi; // vjtag input data signals
wire capture_dr; // Captutre data register signal
wire shift_dr; // data Shift state
wire update_dr; // data Update state
wire update_ir; // instruction register update state
virt_jtag virt_jtag_inst(
.tck ( tck ), // vjtag clock
.tdi ( tdi ), // vjtag data in
.tdo ( tdo ), // vjtag data out
.ir_in ( Control_reg ), // Instruction register input
.ir_out ( 3'b000 ), // Instruction register output
.virtual_state_cdr ( capture_dr ), // Capture DR state
.virtual_state_sdr ( shift_dr ), // Shift DR state
.virtual_state_udr ( update_dr ), // Update DR state
.virtual_state_uir ( update_ir ) // Update IR state
);
// --------------------------------------------------------------------
// VJI control constants
// --------------------------------------------------------------------
parameter SEL = 3'b001; // single write transaction
parameter POP = 3'b010; // single read transaction
parameter KEY = 3'b011; // select output
parameter NOP = 3'b111; // not used
// --------------------------------------------------------------------
// VJI register bank
// --------------------------------------------------------------------
reg [7:0] push_in; // Push in register
reg [7:0] push_out; // Push out register
wire [2:0] Control_reg; // Instruction register
// --------------------------------------------------------------------
// Control register state sense
// --------------------------------------------------------------------
wire crPOP = (Control_reg == POP); // We are poping
wire crSEL = (Control_reg == SEL); // We are selecting
wire crKEY = (Control_reg == KEY); // We are sending a key
// --------------------------------------------------------------------
// Write buffer pulse : tck @ 5-7 MHz; wrclk @ 50 MHz.
// will clock up wrclk to 100 MHz if necessary to perform edge detect
// --------------------------------------------------------------------
always @(posedge tck) begin
if((crSEL | crKEY) && shift_dr) push_in <= {tdi, push_in[7:1]};
end
always @(posedge clk) begin
if(crKEY && update_dr) begin
key_pad <= push_in[4:0];
end
else if(crSEL) begin
sel_out <= push_in[3:0];
test_out <= push_in[7];
end
end
assign key_rdy = (crKEY && update_dr);
// --------------------------------------------------------------------
// Read buffer on capture DR
// --------------------------------------------------------------------
always @(posedge tck) begin
if(crPOP && capture_dr) begin
push_out <= data_in;
end
else if(crPOP && shift_dr) begin
push_out <= {push_out[0], push_out[7:1]};
end
end
assign tdo = push_out[0];
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
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#include <bits/stdc++.h> using namespace std; struct node { int sum; int adj[6]; node() { sum = 0; memset(adj, -1, sizeof adj); } }; int n, m; vector<node> T; map<string, int> S; void add(string x) { int cur = 0; for (int i = 0; i < x.size(); i++) { int c = x[i] - a ; if (T[cur].adj[c] == -1) { T.push_back(node()); T[cur].adj[c] = T.size() - 1; cur = T.size() - 1; } else { cur = T[cur].adj[c]; } if (i == x.size() - 1) T[cur].sum++; } } int ask(string x) { string y = ; for (int i = 0; i < x.size(); i++) { if (x[i] == ? ) continue; y += x[i]; } bool take = true; if (S.find(y) != S.end()) { take = false; } else { S[y] = 1; } int cur = 0; int ans = 0; int i = 0; for (i = 0; i < x.size(); i++) { if (x[i] == ? ) { string y = x; for (char a = a ; a <= e ; a++) { y[i] = a; ans += ask(y); } if (i == x.size() - 1 && take) { ans += T[cur].sum; } continue; } int c = x[i] - a ; if (T[cur].adj[c] != -1) { cur = T[cur].adj[c]; } else { break; } if (i == x.size() - 1 && take) { ans += T[cur].sum; } } return ans; } int main() { cin >> n >> m; T.push_back(node()); for (int i = 0; i < n; i++) { string x; cin >> x; add(x); } int ans = 0; for (int i = 0; i < m; i++) { S.clear(); ans = 0; string x; cin >> x; ans += ask(x); cout << ans << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; struct proc { string name; string var[10]; }; struct vari { string name; string x; }; string s, t, name, varr[10]; proc a[1005]; vari b[1005]; int res, n, m, k, para[1005], p; bool check; int main() { if (0) { freopen( a.inp , r , stdin); }; scanf( %d n , &n); size_t found; for (int i = 0; i < n; i++) { getline(cin, s); found = s.find( void ); s.erase(0, int(found) + 4); while (s[0] == ) s.erase(0, 1); for (int j = 0; j < s.length(); j++) { if (s[j] == || s[j] == ( ) break; a[i].name += s[j]; } t = ; found = s.find( ( ); for (int j = int(found) + 1; s[j] != ) ; j++) { if (s[j] == , || s[j] == ) continue; while (s[j] != , && s[j] != && s[j] != ) ) t += s[j], j++; para[i]++; a[i].var[para[i]] = t; t = ; if (s[j] == ) ) break; } } scanf( %d n , &m); for (int i = 0; i < m; i++) { getline(cin, s); int j = 0; t = ; while (s[j] == ) j++; while (s[j] != ) t += s[j], j++; b[i].x = t; t = ; while (s[j] == ) j++; while (j < s.length() && s[j] != ) t += s[j], j++; b[i].name = t; } scanf( %d n , &k); for (int i = 0; i < k; i++) { getline(cin, s); int j = 0; while (s[j] == ) j++; t = ; while (s[j] != && s[j] != ( ) t += s[j], j++; name = t; while (s[j] != ( ) j++; j++; t = ; p = 0; for (; s[j] != ) ; j++) { if (s[j] == || s[j] == , ) continue; while (s[j] != && s[j] != , && s[j] != ) ) t += s[j], j++; check = false; for (int x = 0; x < m; x++) if (b[x].name == t) { t = b[x].x; check = true; break; } if (!check) break; p++; varr[p] = t; t = ; if (s[j] == ) ) break; } if (!check) { printf( 0 n ); continue; } res = 0; for (int x = 0; x < n; x++) { if (para[x] != p || a[x].name != name) continue; check = true; for (int y = 1; y <= p; y++) { if (a[x].var[y][0] == T ) continue; if (a[x].var[y][0] != varr[y][0]) { check = false; break; } } if (check) res++; } printf( %d n , res); } }
|
module operator(
clk,
reset_n,
synth_ctrl,
synth_data,
data_out,
wreq);
input wire clk, reset_n;
input wire [7:0] synth_data, synth_ctrl;
output wire wreq;
output wire [15:0] data_out;
wire [15:0] sine_out;
wire [20:0] phase;
reg [20:0] phase_1;
reg [31:0] accum_1;
reg [23:0] add_1;
reg [7:0] p_synth_ctrl;
reg wreq_r, wr_now;
initial add_1 <= 19224; //default frequency
assign data_out = accum_1[15:0];
assign phase = phase_1;
assign wreq = wreq_r;
always @(posedge clk, negedge reset_n)
begin
if(!reset_n)
begin
phase_1 <= 0;
accum_1 <= 0;
add_1 <= 0;
wreq_r <= 0;
wr_now <= 0;
end
else
begin
p_synth_ctrl <= synth_ctrl;
case(synth_ctrl)
8'b00000001 : phase_1 <= add_1; //step phase
8'b10000001 : wreq_r <= 1; //write req to fifo(one shot)
8'b01000001 : begin //write synth_data to lower add_1
add_1[7:0] <= synth_data;
wr_now <= 1; //wr_now is unused yet
end
8'b00010001 : add_1[15:8] <= synth_data; //write synth_data to middle of add_1
8'b01010001 : begin //write synth_data to upper of add_1
add_1[23:16] <= synth_data;
wr_now <= 0;
end
8'b00100000 : begin //reset command
phase_1 <= 0;
accum_1 <= 0;
add_1 <= 0;
wreq_r <= 0;
wr_now <= 0;
end
default : phase_1 <= phase_1;
endcase
case(p_synth_ctrl)
8'b00000001 : accum_1 <= sine_out; //store output data to accum_1
8'b10000001 : wreq_r <= 0;
endcase
end
end
sine sine(
.phase(phase),
.sine_out(sine_out));
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the advanced register file
// Import the modules that will be tested for in this testbench
`include "regfileww.v"
// IMPORTANT: To run this, try: ncverilog -f regfileww.f +gui
module regfilewwtb();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the advanced register file
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// rd1data or rd2data output signals
wire [127:0] rd1_d,rd2_d;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, wren,rd1en,rd2en;
reg clock,wr_en,r1_en,r2_en;
// wrdata
reg [127:0] wr_d;
// wraddr, rd1addr, rd2addr
reg [4:0] w_addr,r1_addr,r2_addr;
// wrbyteen
reg [15:0] wrbytn;
// 32 Words of 128-bits
reg r[0:31];
reg [127:0] r_row;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#2.5 clock = 0;
#2.5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
regfileww rg (
// instance_name(signal name),
// Signal name can be the same as the instance name
rd1_d,rd2_d,wr_d,r1_addr,r2_addr,w_addr,r1_en,r2_en,
wr_en,wrbytn,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/*
for(count=0;count<=size_of_input;count=count+1)
begin
#10
//$display("Next");
r_row=r[count];
$display("Next",r_row);
end
*/
// Write to 8 data locations
#20
wr_d=128'h787897ea12fec60cae787897eac22354;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd0;
wrbytn=16'hff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h72348973465465465464645664654666;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd1;
wrbytn=16'h7f;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h48545618548486131875531264684565;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd2;
wrbytn=16'h3f;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h48646517897894613514684987984614;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd3;
wrbytn=16'h1f;
r1_en=0;
r2_en=0;
wr_en=1;
// ===================================
#20
wr_d=128'hcaacecce09c4ae54864c6ae464ca3544;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd4;
wrbytn=16'hfff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'hceac45564c1ae151c53ae15c153ae1c4;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd5;
wrbytn=16'h7ff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'hdc46da456c1ad561c65ad1c6ad61c455;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd6;
wrbytn=16'h3ff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
//wr_d=128'h18342cad864c65da4654cad646c5d4a564cd56ca552;
wr_d=128'hc65da4654cad646c5d4a564cd56ca552;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd7;
wrbytn=16'h1ff;
r1_en=0;
r2_en=0;
wr_en=1;
// Read the data from the aforementioned locations
#20
wr_d=128'd12345;
r1_addr=5'd0;
r2_addr=5'd7;
w_addr=5'd20;
wrbytn=16'hffff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd1;
r2_addr=5'd6;
w_addr=5'd20;
wrbytn=16'h7fff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd2;
r2_addr=5'd5;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd3;
r2_addr=5'd4;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
// ====================================================
#20
wr_d=128'd12345;
r1_addr=5'd4;
r2_addr=5'd3;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd5;
r2_addr=5'd2;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd6;
r2_addr=5'd1;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd7;
r2_addr=5'd0;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:42:42 05/12/2015
// Design Name:
// Module Name: inverse_perm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module inverse_perm(
left,
right,
cipher
);
input [32:1] left;
input [32:1] right;
output reg [64:1] cipher;
wire [64:1] left_ryt ;
assign left_ryt = {right,left}; //teta5d mn 16
always @(left_ryt)
begin
cipher[1] <= left_ryt[40];
cipher[2] <= left_ryt[8];
cipher[3] <= left_ryt[48];
cipher[4] <= left_ryt[16];
cipher[5] <= left_ryt[56];
cipher[6] <= left_ryt[24];
cipher[7] <= left_ryt[64];
cipher[8] <= left_ryt[32];
cipher[9] <= left_ryt[39];
cipher[10] <= left_ryt[7];
cipher[11] <= left_ryt[47];
cipher[12] <= left_ryt[15];
cipher[13] <= left_ryt[55];
cipher[14] <= left_ryt[23];
cipher[15] <= left_ryt[63];
cipher[16] <= left_ryt[31];
cipher[17] <= left_ryt[38];
cipher[18] <= left_ryt[6];
cipher[19] <= left_ryt[46];
cipher[20] <= left_ryt[14];
cipher[21] <= left_ryt[54];
cipher[22] <= left_ryt[22];
cipher[23] <= left_ryt[62];
cipher[24] <= left_ryt[30];
cipher[25] <= left_ryt[37];
cipher[26] <= left_ryt[5];
cipher[27] <= left_ryt[45];
cipher[28] <= left_ryt[13];
cipher[29] <= left_ryt[53];
cipher[30] <= left_ryt[21];
cipher[31] <= left_ryt[61];
cipher[32] <= left_ryt[29];
cipher[33] <= left_ryt[36];
cipher[34] <= left_ryt[4];
cipher[35] <= left_ryt[44];
cipher[36] <= left_ryt[12];
cipher[37] <= left_ryt[52];
cipher[38] <= left_ryt[20];
cipher[39] <= left_ryt[60];
cipher[40] <= left_ryt[28];
cipher[41] <= left_ryt[35];
cipher[42] <= left_ryt[3];
cipher[43] <= left_ryt[43];
cipher[44] <= left_ryt[11];
cipher[45] <= left_ryt[51];
cipher[46] <= left_ryt[19];
cipher[47] <= left_ryt[59];
cipher[48] <= left_ryt[27];
cipher[49] <= left_ryt[34];
cipher[50] <= left_ryt[2];
cipher[51] <= left_ryt[42];
cipher[52] <= left_ryt[10];
cipher[53] <= left_ryt[50];
cipher[54] <= left_ryt[18];
cipher[55] <= left_ryt[58];
cipher[56] <= left_ryt[26];
cipher[57] <= left_ryt[33];
cipher[58] <= left_ryt[1];
cipher[59] <= left_ryt[41];
cipher[60] <= left_ryt[9];
cipher[61] <= left_ryt[49];
cipher[62] <= left_ryt[17];
cipher[63] <= left_ryt[57];
cipher[64] <= left_ryt[25];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e7 + 2; const int M = (int)5e5 + 2; const int mod = (int)1e9 + 7; int mu[N], cnt[N]; int n, mx, x, p[M]; long long res; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); if (fopen( test .inp , r )) { freopen( test .inp , r , stdin); freopen( test .out , w , stdout); } cin >> n; p[0] = 1; for (int i = 1; i <= n; ++i) { cin >> x; mx = max(mx, x); ++cnt[x]; p[i] = 2ll * p[i - 1] % mod; } mu[1] = 1; fill(mu + 2, mu + mx + 1, -1); int s; for (int i = 2; i <= mx; ++i) { s = cnt[i]; for (int j = 2 * i; j <= mx; j += i) mu[j] -= mu[i], s += cnt[j]; if (mu[i] != 0) res = (res + 1ll * (p[s] - 1) * (-mu[i]) * (n - s) % mod) % mod; } res += mod; cout << res % mod; }
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Bit select of a net (a wire) using the index of a for loop.
*/
module main;
// Make a vector of bits, an array of functors in practice, and
// create a net that hooks to that array backwards.
reg [4:0] vect = 5'b10100;
wire [4:0] tmp = { vect[0], vect[1], vect[2], vect[3], vect[4] };
reg [2:0] idx;
initial begin
#1 $display("vect=%b, tmp=%b", vect, tmp);
for (idx = 0 ; idx < 5 ; idx = idx + 1) begin
$display("idx=%d: vect=%b, tmp=%b", idx, vect[idx], tmp[idx]);
if (tmp[idx] !== vect[4-idx]) begin
$display("FAILED");
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; void DBG() { cerr << ] n ; } template <typename T, typename... Args> void DBG(T first, Args... args) { cerr << first; if (sizeof...(args)) cerr << , ; DBG(args...); } void solve() { long long int x0, y0, ax, ay, bx, by, sx, sy, t; cin >> x0 >> y0 >> ax >> ay >> bx >> by >> sx >> sy >> t; vector<long long int> px, py; px.push_back(x0); py.push_back(y0); while (true) { long long bound = 0; if (px.back() > sx) { bound += px.back() - sx; } if (py.back() > sy) { bound += py.back() - sy; } if (bound > t) { px.pop_back(); py.pop_back(); break; } px.push_back(px.back() * ax + bx); py.push_back(py.back() * ay + by); } long long int n = px.size(); long long int g = 0; for (long long int i = 0; i < n; i++) { for (long long int j = i; j < n; j++) { long long int from_i = abs(sx - px[i]) + abs(sy - py[i]); long long int from_j = abs(sx - px[j]) + abs(sy - py[j]); long long int cnt = min(from_i, from_j) + abs(px[i] - px[j]) + abs(py[i] - py[j]); if (cnt <= t) { g = max(g, j - i + 1); } } } cout << g << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); long long int t = 1; for (long long int tt = 1; tt <= t; tt++) { solve(); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O21BAI_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_BLACKBOX_V
|
#include <bits/stdc++.h> typedef struct Segment { int start; int last; int Xor; } segment; using namespace std; vector<segment> V; int score(segment s) { if (s.last == s.start) return s.Xor; else { int value = 0; for (int i = s.start + 1; i < s.last;) { if (V[i].start == -1) i++; else { value += score(V[i]); i = V[i].last + 1; } } return max(value, s.Xor); } } int cities_final[5010]; int cities_first[5010]; int cities[5010]; int main() { int n; scanf( %d , &n); int people[n]; int cumulativeXOR[n + 1]; cumulativeXOR[0] = 0; for (int i = 0; i < n; i++) { scanf( %d , &people[i]); if (!cities[people[i]]) cumulativeXOR[i + 1] = cumulativeXOR[i] ^ people[i]; else cumulativeXOR[i + 1] = cumulativeXOR[i]; if (!cities[people[i]]) cities_first[people[i]] = i; cities[people[i]] = 1; cities_final[people[i]] = i; } int start; int last; int Xor; for (int i = 0; i < n; i++) { start = i; last = i; int flag = 0; if (cities[people[i]]) { for (int j = i; j <= last; j++) { if (cities_first[people[j]] < start) { flag = 1; } if (cities_final[people[j]] > last) last = cities_final[people[j]]; } Xor = cumulativeXOR[last + 1] ^ cumulativeXOR[start]; segment s; s.start = start; s.last = last; s.Xor = Xor; if (flag) s.start = -1; cities[people[i]] = 0; V.push_back(s); } else { segment s; s.start = -1; V.push_back(s); } } int ans = 0; for (int i = 0; i < n;) { ans += score(V[i]); i = V[i].last + 1; } printf( %d , ans); }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_onchip_sram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_system_onchip_sram.hex";
output [ 31: 0] readdata;
input [ 16: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 90112,
the_altsyncram.numwords_a = 90112,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 17;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; long long p[222222]; long long sum[222222]; long long max1[222222]; long long max2[222222]; long long get(long long l, long long r) { long long t = sum[r]; if (l >= 1) { t -= sum[l - 1]; } return t; } int main() { long long n, k; cin >> n >> k; for (long long i = 0; i < n; i++) { cin >> p[i]; if (i) { sum[i] = sum[i - 1] + p[i]; } else { sum[i] = p[i]; } } for (long long i = 0; i < n; i++) { if (i < k - 1) { max1[i] = 0; } else { max1[i] = max(max1[i - 1], get(i + 1 - k, i)); } } long long b = -1; for (long long i = 0; i < n; i++) { if (i < 2 * k - 1) { max2[i] = 0; } else { max2[i] = max(max2[i - 1], get(i + 1 - k, i) + max1[i - k]); ; } } long long i = n - 1; while (i >= 0) { if (max2[i - 1] >= get(i + 1 - k, i) + max1[i - k]) { i--; } else { b = i + 1 - k; break; } } long long se = max2[n - 1] - get(b, b + k - 1); for (long long i = 0; i < n; i++) { if (get(i, i + k - 1) == se) { cout << i + 1 << ; cout << b + 1 << n ; return 0; } } return 0; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench to test some Verilog concepts
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
// ============================================================
module tb_communication_channel();
// Read inputs from the text file
// reg [256:0] r;
/*
reg [1:0] r [13:0];
reg count;
*/
integer count;
reg clk;
reg r[0:13];
always begin
#8 clk = 0;
#8 clk = 1; // Invert clock signal every 10 ns
// Clock signal has a period of 20 ns or 50 MHz
end
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("./ytest.txt",r);
// $readmemb("testfile.bit",rf);
//size_of_input=256
for(count=0; count<5; count = count + 1)
//while(clk<97)
begin
#5
$display("Next");
end
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x; } const int maxn = 100005; int n; long long zero = 0, one = 0, z1 = 0, o1 = 0; char s[maxn], t[maxn]; int main() { n = read(); scanf( %s%s , s, t); for (int i = 0; i < n; ++i) { if (s[i] == 0 ) { zero++; if (t[i] == 0 ) z1++; } else { one++; if (t[i] == 0 ) o1++; } } printf( %lld n , z1 * one + o1 * zero - z1 * o1); return 0; }
|
// A small processor I once created, intended to be used as a debug
// processor in ASICs and FPGAs.
//
// Very limited instruction set, but I never intended to write
// many programs for it.
//
// In an FPGA it would probably be better to use for example
// PicoBlaze...
//
module serial_wb_top(
input wire clk_i,rst_i,rx_i,
output wire tx_o,
input wire [31:0] parport_i,
output wire [31:0] parport_o,
output wire parport_readstrobe_o,
output wire parport_writestrobe_o,
// Wishbone master interface wbm_*:
input wire [31:0] wbm_dat_i,
output wire [31:0] wbm_dat_o,
input wire wbm_ack_i,
output wire [31:0] wbm_adr_o,
output wire wbm_cyc_o,
input wire wbm_err_i,
output wire wbm_lock_o,
input wire wbm_rty_i,
output wire [3:0] wbm_sel_o,
output wire wbm_stb_o,
output wire wbm_we_o
);
wire [9:0] pm_addr;
wire [15:0] pm_insn;
wire [7:0] port0;
wire [7:0] port1;
wire [7:0] port2;
wire strobe1;
wire strobe2;
serial_wb_mcu controller(.clk_i(clk_i),
.rst_i(rst_i),
.pm_addr_o(pm_addr),
.pm_insn_i(pm_insn),
.port0_o(port0),
.port1_o(port1),
.port2_i(port2),
.strobe1_o(strobe1),
.strobe2_o(strobe2));
serial_wb_program program_memory(.clk_i(clk_i),
.pm_addr_i(pm_addr),
.pm_insn_o(pm_insn));
serial_wb_io io(
.clk_i (clk_i),
.rst_i (rst_i),
// Serial port
.tx_o (tx_o),
.rx_i (rx_i),
// Parallell port I/O
.parport_o (parport_o),
.parport_i (parport_i),
.parport_readstrobe_o (parport_readstrobe_o),
.parport_writestrobe_o (parport_writestrobe_o),
// Wishbone interface
.wbm_dat_o(wbm_dat_o),
.wbm_adr_o(wbm_adr_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_lock_o(wbm_lock_o),
.wbm_sel_o(wbm_sel_o),
.wbm_stb_o(wbm_stb_o),
.wbm_we_o(wbm_we_o),
.wbm_dat_i(wbm_dat_i),
.wbm_ack_i(wbm_ack_i),
.wbm_err_i(wbm_err_i),
.wbm_rty_i(wbm_rty_i),
// Processor bus
.data_o (port2),
.address_i (port0),
.data_i (port1),
.read_strobe_i (strobe2),
.write_strobe_i (strobe1));
endmodule // serial_wb_top
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.1 (lin64) Build Fri Apr 8 15:45:23 MDT 2016
// Date : Mon Jun 6 23:00:46 2016
// Host : edinburgh running 64-bit Ubuntu 15.04
// Command : write_verilog -force -mode funcsim
// /home/greg/opl3_fpga_vivado_project/opl3_fpga_vivado_project.srcs/sources_1/ip/clk_gen/clk_gen_sim_netlist.v
// Design : clk_gen
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module clk_gen
(clk125,
clk,
clk_locked);
input clk125;
output clk;
output clk_locked;
wire clk;
(* IBUF_LOW_PWR *) wire clk125;
wire clk_locked;
clk_gen_clk_gen_clk_wiz inst
(.clk(clk),
.clk125(clk125),
.clk_locked(clk_locked));
endmodule
(* ORIG_REF_NAME = "clk_gen_clk_wiz" *)
module clk_gen_clk_gen_clk_wiz
(clk125,
clk,
clk_locked);
input clk125;
output clk;
output clk_locked;
wire clk;
wire clk125;
wire clk125_clk_gen;
wire clk_clk_gen;
wire clk_locked;
wire clkfbout_clk_gen;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk125),
.O(clk125_clk_gen));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_clk_gen),
.O(clk));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("HIGH"),
.CLKFBOUT_MULT_F(53.375000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(8.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(87.375000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(6),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_clk_gen),
.CLKFBOUT(clkfbout_clk_gen),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk125_clk_gen),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_clk_gen),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(clk_locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`begin_keywords "1364-2005"
/*
* This tests the synthesis of a case statement that has an empty case.
*/
module main;
reg clk, bit, foo;
// Synchronous device that toggles whenever enabled by a high bit.
always @(posedge clk)
case (bit)
1'b0: ;
1'b1: foo <= ~foo;
endcase // case(bit)
(* ivl_synthesis_off *)
always begin
#5 clk = 1;
#5 clk = 0;
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
bit = 0;
foo = 0;
# 6 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 0 || foo !== 0) begin
$display("FAILED");
$finish;
end
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 0 || foo !== 0) begin
$display("FAILED");
$finish;
end
bit <= 1;
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 1 || foo !== 1) begin
$display("FAILED");
$finish;
end
#10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
if (bit !== 1 || foo !== 0) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
`end_keywords
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int kq = 0; vector<pair<int, int> > res; int n, k; cin >> n >> k; vector<bool> used(2 * n + 1, false); for (int i = 1; i <= k; i++) { int u, v; cin >> u >> v; res.push_back({min(u, v), max(u, v)}); used[u] = true; used[v] = true; } vector<int> conlai; for (int i = 1; i <= 2 * n; i++) { if (!used[i]) conlai.push_back(i); } int len = n - k; for (int i = 0; i < len; i++) { res.push_back({conlai[i], conlai[i + len]}); } for (int i = 0; i < res.size(); i++) { for (int j = i + 1; j < res.size(); j++) { int a = (res[j].first - res[i].first) * (res[j].second - res[i].first); int b = (res[j].first - res[i].second) * (res[j].second - res[i].second); if (a * b < 0) { kq++; } } } cout << kq << endl; } }
|
#include <bits/stdc++.h> using namespace std; void solve(int test_number); int main() { cout.setf(ios::fixed); cout.precision(9); cerr.setf(ios::fixed); cerr.precision(3); int n = 1; for (int i = 0; i < n; i++) { solve(i + 1); } return 0; } const int MAXN = 200100; const int BUBEN = 800; int n; int a[MAXN]; int d[MAXN]; int nd; bool used[BUBEN][MAXN]; int sum[BUBEN]; vector<int> q[MAXN]; int st[MAXN]; inline int gcd(int a, int b) { if (b == 0) return a; else return gcd(b, a % b); } void solve(int test_number) { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 1; i * i <= n; i++) { if (n % i == 0) { d[nd++] = i; int j = n / i; if (i != j && j != n) d[nd++] = j; } } sort(d, d + nd); for (int j = 0; j < nd; j++) { int step = d[j]; for (int from = 0; from < step; from++) { int mx = a[from]; for (int i = from; i < n; i += step) { mx = max(mx, a[i]); } for (int i = from; i < n; i += step) { if (mx == a[i]) { used[j][i] = true; } } } int last = -1; int pref = 0; for (int i = 0; i < n; i++) if (used[j][i]) { if (last == -1) last = i; } else if (last != -1) { if (last == 0) { pref = i - last; } else { q[j].push_back(i - last); sum[j] += i - last; } last = -1; } if (last != -1) { pref += n - last; } q[j].push_back(pref); sum[j] += pref; sort(q[j].begin(), q[j].end()); } long long res = 0; for (int len = 1; len < n; len++) { int step = gcd(len, n); long long j = lower_bound(d, d + nd, step) - d; while ((int)q[j].size() != st[j] && q[j][st[j]] < len) { sum[j] -= q[j][st[j]]; st[j]++; } if (sum[j] == n) { res += (long long)n; } else { res += (long long)sum[j] - (long long)(len - 1) * (long long)(q[j].size() - st[j]); } } cout << res << endl; }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts video in stream between color spaces on the DE *
* boards. *
* *
******************************************************************************/
module Raster_Laser_Projector_Video_In_video_csc (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IW = 23;
parameter OW = 23;
parameter EIW = 1;
parameter EOW = 1;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EIW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [OW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EOW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [OW: 0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [EOW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IW: 0] data;
reg startofpacket;
reg endofpacket;
reg [EIW:0] empty;
reg valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 2'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'b0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data = ~stream_out_valid |
(stream_out_ready & stream_out_valid);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_YCrCb_to_RGB_converter YCrCb_to_RGB (
// Inputs
.clk (clk),
.clk_en (transfer_data),
.reset (reset),
.Y (data[ 7: 0]),
.Cr (data[23:16]),
.Cb (data[15: 8]),
.stream_in_startofpacket (startofpacket),
.stream_in_endofpacket (endofpacket),
.stream_in_empty (empty),
.stream_in_valid (valid),
// Bidirectionals
// Outputs
.R (converted_data[23:16]),
.G (converted_data[15: 8]),
.B (converted_data[ 7: 0]),
.stream_out_startofpacket (converted_startofpacket),
.stream_out_endofpacket (converted_endofpacket),
.stream_out_empty (converted_empty),
.stream_out_valid (converted_valid)
);
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// FIFO intended to be interchangeable with shortfifo, but
// based on block ram instead of SRL16's
// only one clock domain
// Port A is write port, Port B is read port
module fifo_long
#(parameter WIDTH=32, SIZE=9)
(input clk, input reset, input clear,
input [WIDTH-1:0] datain,
input src_rdy_i,
output dst_rdy_o,
output [WIDTH-1:0] dataout,
output src_rdy_o,
input dst_rdy_i,
output reg [15:0] space,
output reg [15:0] occupied);
wire write = src_rdy_i & dst_rdy_o;
wire read = dst_rdy_i & src_rdy_o;
wire full, empty;
assign dst_rdy_o = ~full;
assign src_rdy_o = ~empty;
// Read side states
localparam EMPTY = 0;
localparam PRE_READ = 1;
localparam READING = 2;
reg [SIZE-1:0] wr_addr, rd_addr;
reg [1:0] read_state;
reg empty_reg, full_reg;
always @(posedge clk)
if(reset)
wr_addr <= 0;
else if(clear)
wr_addr <= 0;
else if(write)
wr_addr <= wr_addr + 1;
ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
ram (.clka(clk),
.ena(1'b1),
.wea(write),
.addra(wr_addr),
.dia(datain),
.doa(),
.clkb(clk),
.enb((read_state==PRE_READ)|read),
.web(0),
.addrb(rd_addr),
.dib({WIDTH{1'b1}}),
.dob(dataout));
always @(posedge clk)
if(reset)
begin
read_state <= EMPTY;
rd_addr <= 0;
empty_reg <= 1;
end
else
if(clear)
begin
read_state <= EMPTY;
rd_addr <= 0;
empty_reg <= 1;
end
else
case(read_state)
EMPTY :
if(write)
begin
//rd_addr <= wr_addr;
read_state <= PRE_READ;
end
PRE_READ :
begin
read_state <= READING;
empty_reg <= 0;
rd_addr <= rd_addr + 1;
end
READING :
if(read)
if(rd_addr == wr_addr)
begin
empty_reg <= 1;
if(write)
read_state <= PRE_READ;
else
read_state <= EMPTY;
end
else
rd_addr <= rd_addr + 1;
endcase // case(read_state)
wire [SIZE-1:0] dont_write_past_me = rd_addr - 3;
wire becoming_full = wr_addr == dont_write_past_me;
always @(posedge clk)
if(reset)
full_reg <= 0;
else if(clear)
full_reg <= 0;
else if(read & ~write)
full_reg <= 0;
//else if(write & ~read & (wr_addr == (rd_addr-3)))
else if(write & ~read & becoming_full)
full_reg <= 1;
//assign empty = (read_state != READING);
assign empty = empty_reg;
// assign full = ((rd_addr - 1) == wr_addr);
assign full = full_reg;
//////////////////////////////////////////////
// space and occupied are for diagnostics only
// not guaranteed exact
localparam NUMLINES = (1<<SIZE)-2;
always @(posedge clk)
if(reset)
space <= NUMLINES;
else if(clear)
space <= NUMLINES;
else if(read & ~write)
space <= space + 1;
else if(write & ~read)
space <= space - 1;
always @(posedge clk)
if(reset)
occupied <= 0;
else if(clear)
occupied <= 0;
else if(read & ~write)
occupied <= occupied - 1;
else if(write & ~read)
occupied <= occupied + 1;
endmodule // fifo_long
|
module chanOffsetMUX (
input clk,
input signed [12:0] chanOffset,
input [3:0] chanOffsetSel,
output reg signed [12:0] chan1_offset = 13'sd0, // program static offsets here!
output reg signed [12:0] chan2_offset = 13'sd0,
output reg signed [12:0] chan3_offset = 13'sd0,
output reg signed [12:0] chan4_offset = 13'sd0,
output reg signed [12:0] chan5_offset = 13'sd0,
output reg signed [12:0] chan6_offset = 13'sd0,
output reg signed [12:0] chan7_offset = 13'sd0,
output reg signed [12:0] chan8_offset = 13'sd0,
output reg signed [12:0] chan9_offset = 13'sd0
);
(* async_reg = "TRUE" *) reg signed [12:0] chanOffset_a = 13'sd0, chanOffset_b = 13'sd0;
(* async_reg = "TRUE" *) reg [3:0] chanOffsetSel_a = 4'h0, chanOffsetSel_b = 4'h0;
always @(posedge clk) begin
chanOffset_a <= chanOffset;
chanOffset_b <= chanOffset_a;
chanOffsetSel_a <= chanOffsetSel;
chanOffsetSel_b <= chanOffsetSel_a;
/*chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;*/
(* full_case, parallel_case *)
case (chanOffsetSel_b)
4'h1: begin
chan1_offset <= chanOffset_b;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h2: begin
chan1_offset <= chan1_offset;
chan2_offset <= chanOffset_b;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h3: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chanOffset_b;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h4: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chanOffset_b;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h5: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chanOffset_b;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h6: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chanOffset_b;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h7: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chanOffset_b;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h8: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chanOffset_b;
chan9_offset <= chan9_offset;
end
4'h9: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chanOffset_b;
end
default: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
endcase
end
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY frame sync
*/
module eth_phy_10g_rx_frame_sync #
(
parameter HDR_WIDTH = 2,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8
)
(
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire rx_block_lock
);
parameter BITSLIP_MAX_CYCLES = BITSLIP_HIGH_CYCLES > BITSLIP_LOW_CYCLES ? BITSLIP_HIGH_CYCLES : BITSLIP_LOW_CYCLES;
parameter BITSLIP_COUNT_WIDTH = $clog2(BITSLIP_MAX_CYCLES);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
reg [5:0] sh_count_reg = 6'd0, sh_count_next;
reg [3:0] sh_invalid_count_reg = 4'd0, sh_invalid_count_next;
reg [BITSLIP_COUNT_WIDTH-1:0] bitslip_count_reg = 0, bitslip_count_next;
reg serdes_rx_bitslip_reg = 1'b0, serdes_rx_bitslip_next;
reg rx_block_lock_reg = 1'b0, rx_block_lock_next;
assign serdes_rx_bitslip = serdes_rx_bitslip_reg;
assign rx_block_lock = rx_block_lock_reg;
always @* begin
sh_count_next = sh_count_reg;
sh_invalid_count_next = sh_invalid_count_reg;
bitslip_count_next = bitslip_count_reg;
serdes_rx_bitslip_next = serdes_rx_bitslip_reg;
rx_block_lock_next = rx_block_lock_reg;
if (bitslip_count_reg) begin
bitslip_count_next = bitslip_count_reg-1;
end else if (serdes_rx_bitslip_reg) begin
serdes_rx_bitslip_next = 1'b0;
bitslip_count_next = BITSLIP_LOW_CYCLES > 0 ? BITSLIP_LOW_CYCLES-1 : 0;
end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
sh_count_next = sh_count_reg + 1;
if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = 0;
sh_invalid_count_next = 0;
if (!sh_invalid_count_reg) begin
rx_block_lock_next = 1'b1;
end
end
end else begin
// invalid header
sh_count_next = sh_count_reg + 1;
sh_invalid_count_next = sh_invalid_count_reg + 1;
if (!rx_block_lock_reg || &sh_invalid_count_reg) begin
// invalid count overflow, lost block lock
sh_count_next = 0;
sh_invalid_count_next = 0;
rx_block_lock_next = 1'b0;
// slip one bit
serdes_rx_bitslip_next = 1'b1;
bitslip_count_next = BITSLIP_HIGH_CYCLES > 0 ? BITSLIP_HIGH_CYCLES-1 : 0;
end else if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = 0;
sh_invalid_count_next = 0;
end
end
end
always @(posedge clk) begin
sh_count_reg <= sh_count_next;
sh_invalid_count_reg <= sh_invalid_count_next;
bitslip_count_reg <= bitslip_count_next;
serdes_rx_bitslip_reg <= serdes_rx_bitslip_next;
rx_block_lock_reg <= rx_block_lock_next;
if (rst) begin
sh_count_reg <= 6'd0;
sh_invalid_count_reg <= 4'd0;
bitslip_count_reg <= 0;
serdes_rx_bitslip_reg <= 1'b0;
rx_block_lock_reg <= 1'b0;
end
end
endmodule
`resetall
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/13.0sp1/ip/merlin/altera_customins_master_translator/altera_customins_master_translator.v#1 $
// $Revision: #1 $
// $Date: 2013/03/07 $
// $Author: swbranch $
// ------------------------------------------
// Custom instruction master translator
// ------------------------------------------
`timescale 1 ns / 1 ns
module altera_customins_master_translator
#(
parameter SHARED_COMB_AND_MULTI = 0
)
(
// ------------------------------------------
// Hybrid slave
// ------------------------------------------
input wire [31:0] ci_slave_dataa, // ci_slave.dataa
input wire [31:0] ci_slave_datab, // .datab
output wire [31:0] ci_slave_result, // .result
input wire [7:0] ci_slave_n, // .n
input wire ci_slave_readra, // .readra
input wire ci_slave_readrb, // .readrb
input wire ci_slave_writerc, // .writerc
input wire [4:0] ci_slave_a, // .a
input wire [4:0] ci_slave_b, // .b
input wire [4:0] ci_slave_c, // .c
input wire [31:0] ci_slave_ipending, // .ipending
input wire ci_slave_estatus, // .estatus
input wire ci_slave_multi_clk, // .clk
input wire ci_slave_multi_reset, // .reset
input wire ci_slave_multi_clken, // .clk_en
input wire ci_slave_multi_start, // .start
output wire ci_slave_multi_done, // .done
input wire [31:0] ci_slave_multi_dataa, // .multi_dataa
input wire [31:0] ci_slave_multi_datab, // .multi_datab
output wire [31:0] ci_slave_multi_result, // .multi_result
input wire [7:0] ci_slave_multi_n, // .multi_n
input wire ci_slave_multi_readra, // .multi_readra
input wire ci_slave_multi_readrb, // .multi_readrb
input wire ci_slave_multi_writerc, // .multi_writerc
input wire [4:0] ci_slave_multi_a, // .multi_a
input wire [4:0] ci_slave_multi_b, // .multi_b
input wire [4:0] ci_slave_multi_c, // .multi_c
// ------------------------------------------
// Comb master
// ------------------------------------------
output wire [31:0] comb_ci_master_dataa, // comb_ci_master.dataa
output wire [31:0] comb_ci_master_datab, // .datab
input wire [31:0] comb_ci_master_result, // .result
output wire [7:0] comb_ci_master_n, // .n
output wire comb_ci_master_readra, // .readra
output wire comb_ci_master_readrb, // .readrb
output wire comb_ci_master_writerc, // .writerc
output wire [4:0] comb_ci_master_a, // .a
output wire [4:0] comb_ci_master_b, // .b
output wire [4:0] comb_ci_master_c, // .c
output wire [31:0] comb_ci_master_ipending, // .ipending
output wire comb_ci_master_estatus, // .estatus
// ------------------------------------------
// Multi master
// ------------------------------------------
output wire multi_ci_master_clk, // multi_ci_master.clk
output wire multi_ci_master_reset, // .reset
output wire multi_ci_master_clken, // .clk_en
output wire multi_ci_master_start, // .start
input wire multi_ci_master_done, // .done
output wire [31:0] multi_ci_master_dataa, // .dataa
output wire [31:0] multi_ci_master_datab, // .datab
input wire [31:0] multi_ci_master_result, // .result
output wire [7:0] multi_ci_master_n, // .n
output wire multi_ci_master_readra, // .readra
output wire multi_ci_master_readrb, // .readrb
output wire multi_ci_master_writerc, // .writerc
output wire [4:0] multi_ci_master_a, // .a
output wire [4:0] multi_ci_master_b, // .b
output wire [4:0] multi_ci_master_c // .c
);
assign comb_ci_master_dataa = ci_slave_dataa;
assign comb_ci_master_datab = ci_slave_datab;
assign comb_ci_master_n = ci_slave_n;
assign comb_ci_master_a = ci_slave_a;
assign comb_ci_master_b = ci_slave_b;
assign comb_ci_master_c = ci_slave_c;
assign comb_ci_master_readra = ci_slave_readra;
assign comb_ci_master_readrb = ci_slave_readrb;
assign comb_ci_master_writerc = ci_slave_writerc;
assign comb_ci_master_ipending = ci_slave_ipending;
assign comb_ci_master_estatus = ci_slave_estatus;
assign multi_ci_master_clk = ci_slave_multi_clk;
assign multi_ci_master_reset = ci_slave_multi_reset;
assign multi_ci_master_clken = ci_slave_multi_clken;
assign multi_ci_master_start = ci_slave_multi_start;
assign ci_slave_multi_done = multi_ci_master_done;
generate if (SHARED_COMB_AND_MULTI == 0) begin
assign multi_ci_master_dataa = ci_slave_multi_dataa;
assign multi_ci_master_datab = ci_slave_multi_datab;
assign multi_ci_master_n = ci_slave_multi_n;
assign multi_ci_master_a = ci_slave_multi_a;
assign multi_ci_master_b = ci_slave_multi_b;
assign multi_ci_master_c = ci_slave_multi_c;
assign multi_ci_master_readra = ci_slave_multi_readra;
assign multi_ci_master_readrb = ci_slave_multi_readrb;
assign multi_ci_master_writerc = ci_slave_multi_writerc;
assign ci_slave_result = comb_ci_master_result;
assign ci_slave_multi_result = multi_ci_master_result;
end else begin
assign multi_ci_master_dataa = ci_slave_dataa;
assign multi_ci_master_datab = ci_slave_datab;
assign multi_ci_master_n = ci_slave_n;
assign multi_ci_master_a = ci_slave_a;
assign multi_ci_master_b = ci_slave_b;
assign multi_ci_master_c = ci_slave_c;
assign multi_ci_master_readra = ci_slave_readra;
assign multi_ci_master_readrb = ci_slave_readrb;
assign multi_ci_master_writerc = ci_slave_writerc;
assign ci_slave_result = ci_slave_multi_done ? multi_ci_master_result :
comb_ci_master_result;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:55:21 05/03/2016
// Design Name:
// Module Name: data_deal
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_deal(
clk,
rst_n,
data_in,
data_in_sign,
data_out,
data_out_sign,
data_valid,
data_ok
);
input clk;
input rst_n;
input [6:0] data_in;
input data_in_sign;
output [6:0] data_out;
output data_out_sign;
input data_valid;
output data_ok;
reg [6:0] data_reg;
reg data_ok;
reg [6:0] data_out;
reg data_out_sign;
reg data_in_sign_reg;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_reg <= 7'h0;
data_ok <= 1'h0;
data_in_sign_reg <= 1'b0;
end
else begin
data_in_sign_reg <= data_in_sign;
data_reg <= data_in_sign ? data_reg + 1'b1 : data_reg;
data_ok <= data_in_sign_reg ? &(data_reg ~^ data_in) : data_ok;
end
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_out_sign <= 1'b0;
data_out <= 'h0;
end
else begin
if(~data_out_sign & data_valid) data_out_sign <= 1'b1;
else data_out_sign <= 1'b0;
data_out <= ~data_out_sign & data_valid ? data_out + 1'b1 : data_out;
end
end
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Physical-Channel Buffers
* =======================
*
* Instantiates 'N' FIFOs in parallel, if 'push' is asserted
* data_in is sent to FIFO[pl_id].
*
* The output is determined by an external 'select' input.
*
* if 'pop' is asserted by the end of the clock cycle, the
* FIFO that was read (indicated by 'select') recieves a
* pop command.
*
* - flags[] provides access to all FIFO status flags.
* - output_port[] provides access to 'output_port' field of flits at head of FIFOs
*/
module LAG_pl_buffers (push, pop, data_in,
data_out, flags,
clk, rst_n);
// length of PL FIFOs
parameter size = 3;
// number of physical channels
parameter n = 4;
input [n-1:0] push;
input [n-1:0] pop;
input fifo_elements_t data_in [n-1:0];
output fifo_elements_t data_out [n-1:0];
output fifov_flags_t flags [n-1:0];
input clk, rst_n;
genvar i;
generate
for (i=0; i<n; i++) begin:plbufs
// **********************************
// SINGLE FIFO holds complete flit
// **********************************
LAG_fifo_v #(.size(size)
) pl_fifo
(.push(push[i]),
.pop(pop[i]),
.data_in(data_in[i]),
.data_out(data_out[i]),
.flags(flags[i]),
.clk, .rst_n);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int Search[1001][1001], Target1[1001], Target2[1001], Attack = 0; int main() { int Data1, Data2; cin >> Data1 >> Data2; for (int i = 0; i < Data1; i++) { for (int i2 = 0; i2 < Data2; i2++) { char Test; cin >> Test; if (Test == * ) { Search[i][i2] = 1, Attack++; } Target1[i] += Search[i][i2]; Target2[i2] += Search[i][i2]; } } for (int i = 0; i < Data1; i++) { for (int i2 = 0; i2 < Data2; i2++) { if (Search[i][i2] == 0 && Target1[i] + Target2[i2] == Attack) return cout << YES << endl << i + 1 << << i2 + 1, 0; if (Search[i][i2] == 1 && Target1[i] + Target2[i2] == Attack + 1) return cout << YES << endl << i + 1 << << i2 + 1, 0; } } cout << NO ; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:47:17 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_iic_0_0/system_axi_iic_0_0_stub.v
// Design : system_axi_iic_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_iic,Vivado 2016.4" *)
module system_axi_iic_0_0(s_axi_aclk, s_axi_aresetn, iic2intc_irpt,
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, sda_i, sda_o, sda_t, scl_i,
scl_o, scl_t, gpo)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,iic2intc_irpt,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,sda_i,sda_o,sda_t,scl_i,scl_o,scl_t,gpo[0:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
output iic2intc_irpt;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input sda_i;
output sda_o;
output sda_t;
input scl_i;
output scl_o;
output scl_t;
output [0:0]gpo;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a, b, c; int getlength(int x, int y, int z) { return (x - y + 1) / (z); } int main() { int n, a, b, right, left; cin >> n >> a >> b; set<int> M; int sh = (n + 1) / (b + 1); n++; b++; M.insert(0); M.insert(n); int m, x; cin >> m; for (int i = 1; i <= m; i++) { cin >> x; auto ptr = M.upper_bound(x); right = *ptr; left = *--ptr; sh -= (right - left) / b; sh += (right - x) / b; sh += (x - left) / b; M.insert(x); if (sh < a) { cout << i << endl; return 0; } } cout << -1 << endl; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 09:37:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_sync_0_0 -prefix
// system_vga_sync_0_0_ system_vga_sync_0_0_stub.v
// Design : system_vga_sync_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync,Vivado 2016.4" *)
module system_vga_sync_0_0(clk_25, rst, active, hsync, vsync, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk_25,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]" */;
input clk_25;
input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rain.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rain (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites/rain.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/rain.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/rain.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rain.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rain.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rain.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rain.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rain_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rain_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { string x; getline(cin, x); sort(x.begin(), x.end()); int res = unique(x.begin(), x.end()) - x.begin(); if (res % 2 == 0) { cout << CHAT WITH HER! ; } else { cout << IGNORE HIM! ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_PP_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BEHAVIORAL_PP_V
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_reconf_registers (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "amm_master_qsys_with_pcie_reconf_registers.hex";
output [ 31: 0] readdata;
input [ 6: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
reg [ 31: 0] readdata;
wire [ 31: 0] readdata_ram;
wire wren;
always @(posedge clk)
begin
if (clken)
readdata <= readdata_ram;
end
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata_ram),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=RCNF",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 128,
the_altsyncram.numwords_a = 128,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 7;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int already = 0; int n, k; cin >> n >> k; int ans = 0; for (int i = 0; i < k; ++i) { int cnt; cin >> cnt; int first; cin >> first; if (first == 1) { int good = 1; already = 1; --ans; while (good < cnt) { cin >> first; if (first == good + 1) { ++good; already = good; --ans; } else { ++good; break; } } ans += cnt; while (good < cnt) { cin >> first; ++good; } } else { ans += (cnt - 1); for (int j = 1; j < cnt; ++j) cin >> first; } } ans += (n - already); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long power(long long base, long long pow, long long mo) { long long res = 1; while (pow) { if (pow % 2 != 0) res = (res * base) % mo; base = (base * base) % mo; pow /= 2; } return res; } long long inv(long long i) { return power(i, 1000000007 - 2, 1000000007); } std::string str = All Good Till Here ; void solve() { long long i, j, x, n; cin >> n; long long a[n], p[n]; for (long long c1 = 0; c1 < n; c1++) cin >> a[c1]; ; for (long long i = 0; i < n; i++) { p[a[i] - 1] = i; } long long ans = 0, max2 = 1; for (long long i = 1; i < n; i++) { if (p[i] > p[i - 1]) { max2++; } else { ans = max(max2, ans); max2 = 1; } } ans = max(max2, ans); cout << n - ans << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long tt; tt = 1; while (tt--) { solve(); } return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for arp_eth_tx
*/
module test_arp_eth_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_frame_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [15:0] s_arp_htype = 0;
reg [15:0] s_arp_ptype = 0;
reg [15:0] s_arp_oper = 0;
reg [47:0] s_arp_sha = 0;
reg [31:0] s_arp_spa = 0;
reg [47:0] s_arp_tha = 0;
reg [31:0] s_arp_tpa = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
// Outputs
wire s_frame_ready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_frame_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_arp_htype,
s_arp_ptype,
s_arp_oper,
s_arp_sha,
s_arp_spa,
s_arp_tha,
s_arp_tpa,
m_eth_hdr_ready,
m_eth_payload_axis_tready
);
$to_myhdl(
s_frame_ready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tkeep,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tuser,
busy
);
// dump file
$dumpfile("test_arp_eth_tx_64.lxt");
$dumpvars(0, test_arp_eth_tx_64);
end
arp_eth_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// ARP frame input
.s_frame_valid(s_frame_valid),
.s_frame_ready(s_frame_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_arp_htype(s_arp_htype),
.s_arp_ptype(s_arp_ptype),
.s_arp_oper(s_arp_oper),
.s_arp_sha(s_arp_sha),
.s_arp_spa(s_arp_spa),
.s_arp_tha(s_arp_tha),
.s_arp_tpa(s_arp_tpa),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Status signals
.busy(busy)
);
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : buf_ram_dp_128x512.v
// Author : Yibo FAN
// Created : 2014-04-07
// Description : buf ram for coefficient
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module buf_ram_dp_128x512 (
clk ,
a_ce ,
a_we ,
a_addr ,
a_data_i ,
a_data_o ,
b_ce ,
b_we ,
b_addr ,
b_data_i ,
b_data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ********************************************
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk ;
// PORT A
input a_ce ;
input [1:0] a_we ;
input [8:0] a_addr ;
input [`COEFF_WIDTH*8-1:0] a_data_i ;
output [`COEFF_WIDTH*8-1:0] a_data_o ;
// PORT B
input b_ce ;
input [1:0] b_we ;
input [8:0] b_addr ;
input [`COEFF_WIDTH*8-1:0] b_data_i ;
output [`COEFF_WIDTH*8-1:0] b_data_o ;
// ********************************************
//
// Signals DECLARATION
//
// ********************************************
reg [`COEFF_WIDTH*8-1:0] a_dataw ;
reg [15:0] a_wen ;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
always @(*) begin
case (a_we)
2'b00: begin a_wen=16'hffff ; a_dataw=a_data_i; end
2'b01: begin a_wen={8'hff, 8'h0}; a_dataw={a_data_i[`COEFF_WIDTH*4-1:`COEFF_WIDTH*0],
a_data_i[`COEFF_WIDTH*8-1:`COEFF_WIDTH*4]}; end
2'b10: begin a_wen={8'h0, 8'hff}; a_dataw=a_data_i; end
2'b11: begin a_wen=16'h0 ; a_dataw=a_data_i; end
endcase
end
`ifndef FPGA_MODEL
ram_dp_be #(.Addr_Width(9), .Word_Width(`COEFF_WIDTH*8))
u_ram_dp_128x512 (
.clka ( clk ),
.cena_i ( ~a_ce ),
.oena_i ( 1'b0 ),
.wena_i ( a_wen ),
.addra_i ( a_addr ),
.dataa_o ( a_data_o ),
.dataa_i ( a_dataw ),
.clkb ( clk ),
.cenb_i ( ~b_ce ),
.oenb_i ( 1'b0 ),
.wenb_i ( {16{1'b1}} ),
.addrb_i ( b_addr ),
.datab_o ( b_data_o ),
.datab_i ( b_data_i )
);
`endif
`ifdef FPGA_MODEL
wire wren_a;
wire wren_b;
assign wren_a = &a_wen;
ram_dp_512x128 u_ram_dp_512x128(
.address_a ( a_addr ),
.address_b ( b_addr ),
.byteena_a ( ~a_wen ),
.clock ( clk ),
.data_a ( a_dataw ),
.data_b ( b_data_i ),
.rden_a ( a_ce&&wren_a ),
.rden_b ( b_ce ),
.wren_a ( ~wren_a ),
.wren_b ( 1'b0 ),
.q_a ( a_data_o ),
.q_b ( b_data_o )
);
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
|
#include <bits/stdc++.h> template <typename T> extern inline void SWAP(T &a, T &b) { T t = a; a = b, b = t; } const int MAXN = 500005; const int MAXBIT = 20; const int MEMBIT = MAXBIT + 5; int bas[MEMBIT], pos[MEMBIT], n, rt, a[MAXN], q; struct quest { int lt, rt, id; bool operator<(const quest &tmp) const { return rt < tmp.rt; } } Q[MAXN]; void insert(int x, int id) { for (register int i = (MAXBIT); i >= (0); --i) { if (x & (1 << i)) { if (!bas[i]) { bas[i] = x, pos[i] = id; return; } if (pos[i] < id) SWAP(pos[i], id), SWAP(x, bas[i]); x ^= bas[i]; } } } int work(int lt) { int ans = 0; for (register int i = (MAXBIT); i >= (0); --i) if (pos[i] >= lt && ans < (ans ^ bas[i])) ans ^= bas[i]; return ans; } int ans[MAXN]; int main() { scanf( %d , &n); for (register int i = (1); i <= (n); ++i) scanf( %d , &a[i]); scanf( %d , &q); for (register int i = (1); i <= (q); ++i) scanf( %d%d , &Q[i].lt, &Q[i].rt), Q[i].id = i; std::sort(Q + 1, Q + 1 + q); for (register int i = (1); i <= (q); ++i) { while (rt < Q[i].rt) { ++rt; insert(a[rt], rt); } ans[Q[i].id] = work(Q[i].lt); } for (register int i = (1); i <= (q); ++i) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[20]; long long b[20]; int getbit(long long x) { int ret = 0; while (x) { x /= 10; ++ret; } return ret; } int main() { a[1] = 9; b[1] = 9; for (int i = 2; i <= 18; ++i) b[i] = b[i - 1] * 10 + 9; for (int i = 2; i <= 18; ++i) a[i] = a[i - 1] * 10; long long w, m, k; while (cin >> w >> m >> k) { long long num = getbit(m); long long cnt = b[num] - m + 1; long long ans = 0; if (w <= num * k * cnt || (num * k * cnt) <= 0) { ans = w / (num * k); } else { ans = cnt; w -= cnt * num * k; for (int i = num + 1; w > 0; ++i) { if (w <= a[i] * i * k || a[i] * i * k <= 0) { ans += w / (i * k); break; } else { ans += a[i]; w -= a[i] * k * i; } } } cout << ans << endl; } return 0; }
|
module hardcaml_lib_add #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output [b-1:0] o
);
assign o = i0 + i1;
endmodule
module hardcaml_lib_sub #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output [b-1:0] o
);
assign o = i0 - i1;
endmodule
module hardcaml_lib_mulu
#(
parameter w0=1,
parameter w1=1
)
(
input [w0-1:0] i0,
input [w1-1:0] i1,
output [w0+w1-1:0] o
);
assign o = i0 * i1;
endmodule
module hardcaml_lib_muls
#(
parameter w0=1,
parameter w1=1
)
(
input [w0-1:0] i0,
input [w1-1:0] i1,
output [w0+w1-1:0] o
);
assign o = $signed(i0) * $signed(i1);
endmodule
module hardcaml_lib_and #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output [b-1:0] o
);
assign o = i0 & i1;
endmodule
module hardcaml_lib_or #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output [b-1:0] o
);
assign o = i0 | i1;
endmodule
module hardcaml_lib_xor #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output [b-1:0] o
);
assign o = i0 ^ i1;
endmodule
module hardcaml_lib_not #(parameter b=1)
(
input [b-1:0] i,
output [b-1:0] o
);
assign o = ~ i;
endmodule
module hardcaml_lib_eq #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output o
);
assign o = i0 == i1;
endmodule
module hardcaml_lib_lt #(parameter b=1)
(
input [b-1:0] i0,
input [b-1:0] i1,
output o
);
assign o = i0 < i1;
endmodule
module hardcaml_lib_gnd
(
output o
);
assign o = 1'b0;
endmodule
module hardcaml_lib_vdd
(
output o
);
assign o = 1'b1;
endmodule
module hardcaml_lib_z
(
output o
);
assign o = 1'bz;
endmodule
module hardcaml_lib_concat2
#(
parameter w0=1,
parameter w1=1
)
(
input [w0-1:0] i0,
input [w1-1:0] i1,
output [w0+w1-1:0] o
);
assign o = {i0,i1};
endmodule
module hardcaml_lib_mux2 #(parameter b=1)
(
input sel,
input [b-1:0] d0,
input [b-1:0] d1,
output [b-1:0] o
);
assign o = sel ? d1 : d0;
endmodule
module hardcaml_lib_select
#(
parameter b=1,
parameter h=0,
parameter l=0
)
(
input [b-1:0] i,
output [h-l:0] o
);
assign o=i[h:l];
endmodule
module hardcaml_tristate_buffer
#(
parameter b=1
)
(
input en,
input [b-1:0] i,
output [b-1:0] o,
inout [b-1:0] io
);
assign io = en ? i : {b{1'bz}};
assign o = io;
endmodule
|
#include <bits/stdc++.h> using namespace std; int en[100004]; long long int dp[100004][3]; string x[100004]; int n; long long int sol(int i, int ck) { if (i > n) return 0; if (dp[i][ck] != -1) return dp[i][ck]; string org = x[i]; long long int ans = 0; long long int ans1 = 0; if (!ck) { string p = x[i - 1]; if (org >= p) { ans = sol(i + 1, 0); } else { ans = 10000000000000000; } reverse(org.begin(), org.end()); if (org >= p) { ans1 = min(ans, sol(i + 1, 1)) + en[i]; } else { ans1 = 10000000000000000; } return dp[i][ck] = min(ans1, ans); } else { string p = x[i - 1]; reverse(p.begin(), p.end()); if (org >= p) { ans = sol(i + 1, 0); } else { ans = 10000000000000000; } reverse(org.begin(), org.end()); if (org >= p) { ans1 = min(ans, sol(i + 1, 1) + en[i]); } else { ans1 = 10000000000000000; } return dp[i][ck] = min(ans, ans1); } } int main() { cin >> n; for (int i = 1; i <= n; i++) scanf( %d , &en[i]); for (int i = 1; i <= n; i++) cin >> x[i]; memset(dp, -1, sizeof dp); long long int ans = sol(2, 0); ans = min(ans, en[1] + sol(2, 1)); if (ans == 10000000000000000) ans = -1; cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; string s; cin >> s; queue<string> q; set<string> st; int ans = 0; q.push(s); st.insert(s); while (!q.empty() && int(st.size()) < k) { string v = q.front(); q.pop(); for (int i = 0; i < v.length(); i++) { string nv = v; nv.erase(i, 1); if (st.count(nv) == 0 && int(st.size()) + 1 <= k) { q.push(nv); st.insert(nv); ans += n - nv.size(); } } } if (int(st.size()) < k) cout << -1 << endl; else cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a, b, c, d, e, k[30]; string s; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> a >> s; for (b = 1; b < a; b++) { if (s[b] < s[b - 1]) { cout << YES << endl; cout << b << << b + 1; return 0; } } cout << NO ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:06:50 12/01/2014
// Design Name:
// Module Name: Registrodesplazamiento
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Registrodesplazamiento #(parameter Width = 10)
(CLK,reset,Enable,Indato,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9);
input CLK,reset,Enable;
input signed [Width-1:0] Indato;
output signed [Width-1:0] Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9;
reg [(Width*10)-1:0] Aux = 0;
//reg [Width-1:0] Aux2=0;
always @(posedge CLK) begin
if (reset) begin
Aux <= 0;
//Aux2 <= 0;
end else if (Enable) begin
//Aux2 <= Indato;
Aux <= {Indato, Aux[(Width*10)-1:Width]};
end
end
assign Y0 = Aux[(Width)-1:0];
assign Y1 = Aux[(Width*2)-1:Width];
assign Y2 = Aux[(Width*3)-1:Width*2];
assign Y3 = Aux[(Width*4)-1:Width*3];
assign Y4 = Aux[(Width*5)-1:Width*4];
assign Y5 = Aux[(Width*6)-1:Width*5];
assign Y6 = Aux[(Width*7)-1:Width*6];
assign Y7 = Aux[(Width*8)-1:Width*7];
assign Y8 = Aux[(Width*9)-1:Width*8];
assign Y9 = Aux[(Width*10)-1:Width*9];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k; int log2(long long x) { int ret = 0; while (x > 0) { x /= 2; ret++; } return ret; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); clock_t ck; ck = clock(); cin >> n >> k; if (k == 1) { cout << n << n ; return 0; } int exp = log2(n); cout << (1ll << exp) - 1 << n ; ck = clock() - ck; cerr << It took << 1.0 * ck / CLOCKS_PER_SEC << sec n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long T = 0; int f = 0; char c = getchar(); for (; c < 0 || c > 9 ; c = getchar()) f |= c == - ; for (; c >= 0 && c <= 9 ; c = getchar()) T = T * 10 + c - 0 ; return f ? -T : T; } const double eps = 1e-7; const int maxn = 1e5 + 233; const double pi = acos(-1.0); struct Vector { double x, y, r; } A[maxn]; int n, a; double ans; struct WZP_AK_SZB { double l, r; bool operator<(const WZP_AK_SZB &n) const { if (l == n.l) return r > n.r; return l < n.l; } } B[maxn]; int numB; set<double> S; set<double>::iterator it; bool check(double x) { numB = 0; for (register int i = (1); i <= (n); ++i) { double dis = sqrt(((A[i].x - a) * (A[i].x - a)) + ((A[i].y) * (A[i].y))); if (dis > A[i].r + x || A[i].r > dis + x || x > dis + A[i].r) continue; double u = atan2(A[i].y, A[i].x - a); double t = acos((((dis) * (dis)) + ((x) * (x)) - ((A[i].r) * (A[i].r))) / 2.0 / dis / x); double l = u - t, r = u + t; if (l < -pi) l += 2 * pi; if (l > pi) l -= 2 * pi; if (r < -pi) r += 2 * pi; if (r > pi) r -= 2 * pi; if (l > r) swap(l, r); B[++numB].l = l; B[numB].r = r; } sort(B + 1, B + 1 + numB); S.clear(); for (register int i = (1); i <= (numB); ++i) { it = S.upper_bound(B[i].l); if (it != S.end() && *it < B[i].r) return true; S.insert(B[i].r); } return false; } int main() { n = read(), a = read(); for (register int i = (1); i <= (n); ++i) { A[i].x = read(), A[i].y = read(); A[i].r = sqrt(((A[i].x + a) * (A[i].x + a)) + ((A[i].y) * (A[i].y))); } double l = 0.0; double r = 2.0 * a; while (r - l > 1e-7) { double mid = (l + r) / 2; if (check(mid)) { r = mid; } else { l = mid; } } printf( %.10lf n , l); }
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char* argv[]) { ios_base::sync_with_stdio(false); long long int N, M; cin >> N >> M; long long int max_n1; for (max_n1 = 1; (max_n1 * (max_n1 - 1)) / 2 + 1 <= N; max_n1 += 2) ; max_n1 -= 2; long long int max_n2; for (max_n2 = 0; (max_n2 * (max_n2 - 1)) / 2 + max_n2 / 2 <= N; max_n2 += 2) ; max_n2 -= 2; long long int max_n = max(max_n1, max_n2); vector<long long int> qs(M, 0); vector<long long int> ws(M, 0); for (int m = 0; m < M; ++m) cin >> qs[m] >> ws[m]; sort(ws.begin(), ws.end(), greater<long long int>()); max_n = min(max_n, (long long int)ws.size()); long long int res = 0; for (int i = 0; i < max_n; ++i) res += ws[i]; cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 mt_rand(time(0)); const int N = 105; int t, n; char a[N], b[N], c[N]; int main() { scanf( %d , &t); while (t--) { scanf( %s%s%s , a, b, c); n = 0; while (a[n]) n++; bool ok = 1; for (int i = 0; i < n; i++) { if (c[i] == a[i] || c[i] == b[i]) ; else ok = 0; } if (!ok) printf( NO n ); else printf( YES n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long q, n, c[30], r, a[100001]; string s; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> s; for (int i = 0; i < n; i++) { if (s[i] == ) ) { c[1]--; if (c[1] < 0) c[2] += 2; } else c[1]++; } if (c[1] != 0) cout << -1; else cout << c[2]; }
|
#include <bits/stdc++.h> int main() { int n, b; scanf( %d%d , &n, &b); int a[100], s = b; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); s += a[i]; } for (int i = 0; i < n; i++) if (s < a[i] * n) { puts( -1 ); return 0; } for (int i = 0; i < n; i++) printf( %.8lf n , 1. * s / n - a[i]); return 0; }
|
module pipeline1(
clk_in, // clock_in
RST, // reset
pc_chg, // indica mudanca do PC fora do pipeline 1
pc_in, // entrada - contador de programa
instr, // instrucao
pc_out // saida - contador de programa
);
// faz o include dos parameters das instrucoes
`include "params_proc.v"
// declaracao de entrada
input clk_in, RST, pc_chg;
input [PC_WIDTH-1:0] pc_in;
// declaracao de saida
output [INSTR_WIDTH-1:0] instr;
output [PC_WIDTH-1:0] pc_out;
// variaveis auxiliares
reg [PC_WIDTH-1:0] new_pc;
wire we, clk_neg;
wire [INSTR_WIDTH-1:0] data;
// instancia de Memoria ROM de programa
mem_program rom0(.clk(clk_neg), .we(we), .addr(new_pc), .data_in(data), .data_out(instr));
assign we = 0;
assign data = 0;
assign clk_neg = ~clk_in;
assign pc_out = new_pc + 1;
// defina o PC de leitura de memoria
always @(posedge clk_in) begin
if (!RST) begin
new_pc <= PC_INITIAL;
end else if (pc_chg) begin
new_pc <= pc_in;
end else begin
new_pc <= new_pc + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void fre() { freopen( c://test//input.in , r , stdin); freopen( c://test//output.out , w , stdout); } template <class T1, class T2> inline void gmax(T1 &a, T2 b) { if (b > a) a = b; } template <class T1, class T2> inline void gmin(T1 &a, T2 b) { if (b < a) a = b; } const int N = (1 << 20) + 10, M = 0, Z = 1e9 + 7, inf = 0x3f3f3f3f; template <class T1, class T2> inline void gadd(T1 &a, T2 b) { a = (a + b) % Z; } int n, m, top; int a[N], b[N]; long long num[21]; long long sum[21]; int v[N]; void add(int x, int val) { for (; x <= top; x += x & -x) v[x] += val; } int cnt(int x) { int ret = 0; for (; x; x -= x & -x) ret += v[x]; return ret; } void init() { for (int i = 1; i <= n; ++i) { int l = 1 << i; int d = m / l; sum[i] = 0; num[i] = 0; int st = 0; while (d--) { for (int j = l / 2 + 1; j <= l; ++j) add(a[st + j], 1); for (int j = 1; j <= l / 2; ++j) { int tmp1 = cnt(a[st + j] - 1); int tmp2 = cnt(a[st + j]); num[i] += tmp1; sum[i] += l / 2 - (tmp2 - tmp1); } for (int j = l / 2 + 1; j <= l; ++j) add(a[st + j], -1); st += l; } } } int main() { while (~scanf( %d , &n)) { m = 1 << n; for (int i = 1; i <= m; ++i) scanf( %d , &a[i]), b[i] = a[i]; sort(b + 1, b + m + 1); top = unique(b + 1, b + m + 1) - b - 1; for (int i = 1; i <= m; ++i) a[i] = lower_bound(b + 1, b + top + 1, a[i]) - b; init(); int q; scanf( %d , &q); while (q--) { int x; scanf( %d , &x); for (int i = x; i >= 1; --i) num[i] = sum[i] - num[i]; long long ans = 0; for (int i = 1; i <= n; ++i) ans += num[i]; printf( %lld n , ans); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long int LINF = 0x3f3f3f3f3f3f3f3fll; const long double pi = acos(-1); const int MOD = 1e9 + 7; int main() { int n, i; double ans = 0.0; scanf( %d , &n); for (i = 1; i <= n; i++) { ans += 1 / (float)i; } printf( %.6lf n , ans); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Dedicated Dual Data Rate (DDR) Input Register
// /___/ /\ Filename : IDDRE1.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IDDRE1 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
parameter [0:0] IS_C_INVERTED = 1'b0
)(
output Q1,
output Q2,
input C,
input CB,
input D,
input R
);
// define constants
localparam MODULE_NAME = "IDDRE1";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam DDR_CLK_EDGE_OPPOSITE_EDGE = 0;
localparam DDR_CLK_EDGE_SAME_EDGE = 1;
localparam DDR_CLK_EDGE_SAME_EDGE_PIPELINED = 2;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "IDDRE1_dr.v"
`else
localparam [152:1] DDR_CLK_EDGE_REG = DDR_CLK_EDGE;
localparam [0:0] IS_C_INVERTED_REG = IS_C_INVERTED;
`endif
wire [1:0] DDR_CLK_EDGE_BIN;
wire IS_C_INVERTED_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
reg Q1_out;
reg Q2_out;
wire Q1_delay;
wire Q2_delay;
wire CB_in;
wire C_in;
wire D_in;
wire R_in;
wire CB_delay;
wire C_delay;
wire D_delay;
wire R_delay;
reg q1_out_int,q1_out_pipelined,q2_out_same_edge_int,q2_out_int;
assign #(out_delay) Q1 = Q1_delay;
assign #(out_delay) Q2 = Q2_delay;
// inputs with no timing checks
assign #(inclk_delay) CB_delay = CB;
assign #(inclk_delay) C_delay = C;
assign #(in_delay) D_delay = D;
assign #(in_delay) R_delay = R;
assign Q1_delay = Q1_out;
assign Q2_delay = Q2_out;
assign CB_in = CB_delay;
assign C_in = C_delay ^ IS_C_INVERTED_BIN;
assign D_in = D_delay;
assign R_in = R_delay;
assign DDR_CLK_EDGE_BIN =
(DDR_CLK_EDGE_REG == "OPPOSITE_EDGE") ? DDR_CLK_EDGE_OPPOSITE_EDGE :
(DDR_CLK_EDGE_REG == "SAME_EDGE") ? DDR_CLK_EDGE_SAME_EDGE :
(DDR_CLK_EDGE_REG == "SAME_EDGE_PIPELINED") ? DDR_CLK_EDGE_SAME_EDGE_PIPELINED :
DDR_CLK_EDGE_OPPOSITE_EDGE;
assign IS_C_INVERTED_BIN = IS_C_INVERTED_REG;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((DDR_CLK_EDGE_REG != "OPPOSITE_EDGE") &&
(DDR_CLK_EDGE_REG != "SAME_EDGE") &&
(DDR_CLK_EDGE_REG != "SAME_EDGE_PIPELINED"))) begin
$display("Error: [Unisim %s-101] DDR_CLK_EDGE attribute is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED. Instance: %m", MODULE_NAME, DDR_CLK_EDGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_C_INVERTED_REG !== 1'b0) && (IS_C_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-103] IS_C_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_C_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
always @(glblGSR or R_in) begin
if (glblGSR == 1'b1) begin
assign q1_out_int = 0;
assign q1_out_pipelined = 0;
assign q2_out_same_edge_int = 0;
assign q2_out_int = 0;
end
else if (glblGSR == 1'b0) begin
if (R_in == 1'b1) begin
assign q1_out_int = 0;
assign q1_out_pipelined = 0;
assign q2_out_same_edge_int = 0;
assign q2_out_int = 0;
end
else if (R_in == 1'b0) begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end
end
end
always @(posedge C_in) begin
if (R_in == 1'b1) begin
q1_out_int <= 1'b0;
q1_out_pipelined <= 1'b0;
q2_out_same_edge_int <= 1'b0;
end
else if (R_in == 1'b0) begin
q1_out_int <= D_in;
q1_out_pipelined <= q1_out_int;
q2_out_same_edge_int <= q2_out_int;
end
end
always @(posedge CB_in) begin
if (R_in == 1'b1)
q2_out_int <= 1'b0;
else if (R_in == 1'b0)
q2_out_int <= D_in;
end
always @(C_in or q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined) begin
case (DDR_CLK_EDGE_REG)
"OPPOSITE_EDGE" : begin
Q1_out <= q1_out_int;
Q2_out <= q2_out_int;
end
"SAME_EDGE" : begin
Q1_out <= q1_out_int;
Q2_out <= q2_out_same_edge_int;
end
"SAME_EDGE_PIPELINED" : begin
Q1_out <= q1_out_pipelined;
Q2_out <= q2_out_same_edge_int;
end
default : begin
$display("Error: [Unisim %s-104] Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDRE1 instance is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.Instance: %m", MODULE_NAME,DDR_CLK_EDGE);
$finish;
end
endcase // case(DDR_CLK_EDGE_REG)
end // always @ (C_in or q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined)
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; map<string, int> m1, m2; void go(string s, map<string, int>& mp) { if (mp.find(s) != mp.end()) { return; } mp[s] = 1; if (s[0] == X ) { string s1 = s; string s2 = s; swap(s1[0], s1[1]); swap(s2[0], s2[2]); go(s1, mp); go(s2, mp); } else if (s[1] == X ) { string s1 = s; string s2 = s; swap(s1[1], s1[0]); swap(s2[1], s2[3]); go(s1, mp); go(s2, mp); } else if (s[3] == X ) { string s1 = s; string s2 = s; swap(s1[3], s1[1]); swap(s2[3], s2[2]); go(s1, mp); go(s2, mp); } else { string s1 = s; string s2 = s; swap(s1[2], s1[0]); swap(s2[2], s2[3]); go(s1, mp); go(s2, mp); } } int main() { string tmp; string a; cin >> a; cin >> tmp; a += tmp; string b; cin >> b; cin >> tmp; b += tmp; go(a, m1); go(b, m2); int done = 0; for (auto it : m1) { if (m2[it.first]) { done = 1; cout << YES << endl; break; } } if (!done) { cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int64_t mod = 1000000007; int main() { int n; cin >> n; int64_t ways = 1; for (int i = 0; i < 3 * n; ++i) { ways *= 3; ways %= mod; } int64_t bad = 1; for (int i = 0; i < n; ++i) { bad *= 7; bad %= mod; } cout << (mod + (ways - bad) % mod) % mod << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n, m, k, u, v, c[200005] = {}, d[200005] = {}, z = 0; vector<int> g[200005] = {}; cin >> n >> m >> k; for (int i = 1; i <= n; i++) cin >> c[i]; for (int i = 0; i < m; i++) cin >> u >> v, g[u].push_back(v), g[v].push_back(u); for (int i = 1; i <= n; i++) { if (d[i]) continue; d[i] = 1; queue<int> q; vector<int> w = {i}; q.push(i); while (!q.empty()) { int x = q.front(); q.pop(); for (int j = 0; j < g[x].size(); j++) { if (!d[g[x][j]]) d[g[x][j]] = 1, q.push(g[x][j]), w.push_back(g[x][j]); } } unordered_map<int, int> p; int o = 0; for (int j = 0; j < w.size(); j++) p[c[w[j]]]++, o = max(o, p[c[w[j]]]); z += w.size() - o; } cout << z; }
|
#include<bits/stdc++.h> using namespace std; #define sfd(x) scanf( %d ,&x) #define sfd2(x,y) scanf( %d%d ,&x,&y) #define sfd3(x,y,z) scanf( %d%d%d ,&x,&y,&z) #define sfs(x) scanf( %s ,x) #define sfll(x) scanf( %lld ,&x) #define sfll2(x,y) scanf( %lld%lld ,&x,&y) #define pfd(x) printf( %d ,x) #define pfs(x) printf( %s ,x) #define pfll(x) printf( %lld ,x) #define nl printf( n ) #define sp printf( ) #define pfyes printf( YES ) #define pfno printf( NO ) #define pf0 printf( 0 ) #define FOR(i,a,b,in) for(int i=a;i<=b;i+=in) #define RFOR(i,a,b,de) for(int i=a;i>=b;i-=de) #define rep(i,n) for(int i=0;i<n;i++) #define pb push_back #define mkp make_pair #define mod 998244353 typedef long long int ll; typedef vector<int> vi; typedef pair<int,int> pii; // ------------------------// ll power(long long x, int y, int p) { ll res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res*x) % p; y = y>>1; x = (x*x) % p; } return res; } int main() { int t; sfd(t); while(t--) { int n; sfd(n); char s[n+1]; sfs(s); int c0 = 0; int c1 = 0; int cx = 0; rep(i,n) { if(s[i]== 1 ) { cx+=1; } else { c1+=(cx/2); cx=0; c0+=1; } } c1+=(cx/2); ll v1=1,v2=1,v3=1; for(int i=1;i<=c0;i++) { v1=(v1*i)%mod; } for(int i=1;i<=c1;i++) { v2=(v2*i)%mod; } for(int i=1;i<=c0+c1;i++) { v3=(v3*i)%mod; } v1=(v1*v2)%mod; ll ans = (v3*power(v1,mod-2,mod))%mod; pfll(ans); nl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mul(long long a, long long b) { return (a * b) % 1000000007; } long long add(long long a, long long b) { a += b; if (a >= 1000000007) a -= 1000000007; return a; } long long binary_expo(long long base, long long expo) { long long res = 1; while (expo) { if (expo % 2) { res = mul(res, base); } expo /= 2; base = mul(base, base); } return res; } long long A[202]; void solve() { long long n; cin >> n; for (long long i = 1; i <= 2 * n; i++) { cin >> A[i]; } long long ans = 0; for (long long i = 1; i <= 2 * n; i += 2) { long long index = -1; for (long long j = i + 1; j <= 2 * n; j++) { if (A[i] == A[j]) { index = j; break; } } for (long long j = index - 1; j >= i + 1; j--) { swap(A[j], A[j + 1]); ans++; } } cout << ans << n ; } signed main() { long long t; t = 1; while (t--) { solve(); } }
|
#include<iostream> #include<algorithm> #include<vector> #include<bitset> #include<time.h> using namespace std; #define R register int bitset<200000>S[60]; bool c[60]; int main(){ srand(time(0)); int n,m,p,q; cin>>n>>m>>p; q=n-1>>1; string s; for(R i=0;i!=n;i++){ cin>>s; for(R j=0;j!=m;j++){ if(s[j]== 1 ){ S[j][i]=1; } } } vector<int>A,E; for(int i=0;i!=m;i++){ c[i]=false; if(S[i].count()>q){ A.push_back(i); } } if(A.empty()==true){ for(R i=0;i!=m;i++){ cout<<0; } return 0; } p=0; while(clock()<2950){ bitset<200000>B=S[A[p]]; vector<int>C,D; D.push_back(A[p]); for(R i=A.size()-1;i!=-1;i--){ if(i!=p){ C.push_back(A[i]); } } random_shuffle(C.begin(),C.end()); for(vector<int>::iterator T=C.begin();T!=C.end();T++){ if((B&S[*T]).count()>q){ B&=S[*T]; D.push_back(*T); } } if(D.size()>E.size()){ E=D; } p++; if(p==A.size()){ p=0; } } for(vector<int>::iterator T=E.begin();T!=E.end();T++){ c[*T]=true; } for(R i=0;i!=m;i++){ if(c[i]==true){ cout<<1; }else{ cout<<0; } } return 0; }
|
`timescale 1ns / 1ps
// @module
// top module
// @input
// clk_src: bind to E3(100Hz)
// power: electric power
// enable: enable switch(pause switch)
// reset: reset switch
// add_time/sub_time: add/sub time manually
// timing_clock_switch: switch for enabling to change timing clock
// timing_clock_disable: shutdown timing clock manually
// @output
// alarm: round time alarm
// timing_clock_alarm: timing clock arrive
// anodes/cnodes: displaye time
module clock
#(parameter WIDTH = 32, CLK_CH = 25, SEC_RANGE = 60, MIN_RANGE = 60, HOUR_RANGE = 24, LEN = 30, NUM = 5)
(
input clk_src,
input power,
input enable,
input reset,
input [2:0] add_time,
input [2:0] sub_time,
input timing_clock_switch,
input timing_clock_disable,
output alarm,
output [(NUM-1):0] timing_clock_alarm,
output [7:0] anodes,
output [7:0] cnodes
);
// record current time
wire [(WIDTH-1):0] sec, min, hour;
// record whole point signal
wire sig_sec, sig_min, sig_hour;
// divided clock source
wire clk_dst;
wire [(WIDTH-1):0] clk_group;
// segment light when power on
wire [7:0] inner_anodes, inner_cnodes;
// segment light of timing clock
wire [7:0] timing_anodes, timing_cnodes;
range_divider DRANGE_DIVIDER (
.clk_src(clk_src),
.clk_dst(clk_dst)
);
// for debug only
// assign clk_dst = clk_group[0];
tick_divider TICK_DIVIDER (
.clk_src(clk_src),
.clk_group(clk_group)
);
timer #(.WIDTH(WIDTH), .RANGE(SEC_RANGE)) SEC_TIMER (
.clk_normal(clk_dst),
// && !timing_clock_switch : when changing timing clock, lock manual changing of real clock
.clk_change_time(clk_group[CLK_CH] && !timing_clock_switch),
.power(power),
.enable(enable),
.reset(reset),
.add_time(add_time[0]),
.sub_time(sub_time[0]),
.count(sec),
.sig_end(sig_sec)
);
timer #(.WIDTH(WIDTH), .RANGE(MIN_RANGE)) MIN_TIMER (
.clk_normal(sig_sec),
.clk_change_time(clk_group[CLK_CH] && !timing_clock_switch),
.power(power),
.enable(enable),
.reset(reset),
.add_time(add_time[1]),
.sub_time(sub_time[1]),
.count(min),
.sig_end(sig_min)
);
timer #(.WIDTH(WIDTH), .RANGE(HOUR_RANGE)) HOUR_TIMER (
.clk_normal(sig_min),
.clk_change_time(clk_group[CLK_CH] && !timing_clock_switch),
.power(power),
.enable(enable),
.reset(reset),
.add_time(add_time[2]),
.sub_time(sub_time[2]),
.count(hour),
.sig_end(sig_hour)
);
time_displayer SEG_SEVEN (
.clk_src(clk_group[15]),
.sec_data(sec),
.min_data(min),
.hour_data(hour),
// when power off, light off
.anodes(inner_anodes),
.cnodes(inner_cnodes)
);
ring RING (
.power(power),
.sig_ring(sec == (SEC_RANGE-1) && min == (MIN_RANGE-1) && enable),
.sig_step(clk_dst),
.alarm(alarm)
);
timing_clock #(WIDTH, CLK_CH, SEC_RANGE, MIN_RANGE, HOUR_RANGE, LEN, NUM) TIMING_CLOCK (
.clk_dst(clk_dst),
.clk_group(clk_group),
.timing_clock_switch(timing_clock_switch),
.timing_clock_disable(timing_clock_disable),
.power(power),
.enable(enable),
.reset(reset),
.add_time(add_time),
.sub_time(sub_time),
.sec(sec),
.min(min),
.hour(hour),
.timing_anodes(timing_anodes),
.timing_cnodes(timing_cnodes),
.timing_clock_alarm(timing_clock_alarm)
);
assign anodes = !power ? 8'b11111111
: timing_clock_switch ? timing_anodes
: inner_anodes;
assign cnodes = !power ? 8'b11111111
: timing_clock_switch ? timing_cnodes
: inner_cnodes;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
`define SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int Day12[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int prime100[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103}; template <typename T> inline bool isLeap(T y) { return (y % 400 == 0) || (y % 100 ? y % 4 == 0 : false); } template <typename T> inline T BIGMOD(T A, T B, T M = 1000000007) { T ret = 1; while (B) { if (B & 1) ret = (ret * A) % M; A = (A * A) % M; B = B >> 1; } return ret; } template <typename T> inline T BigMod(T A, T B, T M) { T ret = 1; while (B) { if (B & 1) ret = (ret * A) % M; A = (A * A) % M; B = B >> 1; } return ret; } long long int MySqrt(long long int n) { long long int p = sqrt(n); if ((p + 1) * (p + 1) <= n) return p + 1; else if (p * p <= n) return p; else return p - 1; } long long int MyPow(long long int x, long long int n) { if (n == 0) return 1; else if (n % 2 == 0) return MyPow(x * x, n / 2); else return x * MyPow(x * x, ((n - 1) / 2)); } long long int modInverse(long long int n) { return BIGMOD(n, (long long int)1000000007 - 2) % 1000000007; } int a[105][105]; int main() { int n, d; scanf( %d%d , &(n), &(d)); for (int i = 1; i <= d; i++) { for (int j = 1; j <= n; j++) { char ch; cin >> ch; a[i][j] = ch - 0 ; } } int mx = INT_MIN; int cnt = 0; for (int i = 1; i <= d; i++) { int present = 1; for (int j = 1; j <= n; j++) { present = present & a[i][j]; } if (!present) { cnt++; } else cnt = 0; mx = max(mx, cnt); } cout << mx << n ; }
|
`include "DEF.v"
module dcache(clock, address, data, read, write, rs_ex_ok, out_address, out_data, out_read, out_write, in_databus, out_databus, write_databus);
input [31:0] address;
inout [31:0] data, out_data;
input read, write;
input [63:0] in_databus;
input clock;
output [31:0] out_address;
output out_read, out_write;
output [63:0] out_databus;
output write_databus;
output rs_ex_ok;
reg [31:0] dcache [14'h3FFF:0];
reg [31:0] tag [14'h3FFF:0];
reg dirty [14'h3FFF:0];
reg [31:0] r_out_address;
reg [31:0] r_out_data;
reg r_out_read, r_out_write;
reg [31:0] r_data;
reg [63:0] r_out_databus;
reg r_write_databus;
reg signed [31:0] r_status;
reg [31:0] r_address;
reg r_lw_or_sw;
reg r_rs_ex_ok;
integer i;
assign data = r_data;
assign out_read = r_out_read;
assign out_write = r_out_write;
assign out_address = r_out_address;
assign out_data = r_out_data;
assign out_databus = r_out_databus;
assign write_databus = r_write_databus;
assign rs_ex_ok = r_rs_ex_ok;
always @(negedge clock)
begin
if(r_status === `DELAY_MEMORY)
begin
r_write_databus <= 1;
end
#0.001
r_status = r_status - 1;
//#0.001 $display("r_status: %d\n", r_status);
#0.001
if(r_status <= 0)
begin
r_write_databus <= 0;
/*
if(r_status === 0)
begin
if(r_lw_or_sw === 0)
r_out_databus <= {16'b000000_00000_00001, 16'b000000_00000_00000, r_address};
else
r_out_databus <= {16'b000000_00000_00010, 16'b000000_00000_00000, r_address};
end
else
*/
if(r_status === 0)
begin
if(in_databus[31:0] === 0)
r_out_databus <= 64'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
else
r_out_databus <= in_databus - 1;
end
#0.001
r_write_databus <= 1;
end
end
always @(posedge read)
begin
r_out_read <= 0;
r_out_write <= 0;
r_write_databus <= 0;
/*
$display("READ!!!!! %d [%d %d %d]\n", address, tag[address % 15'h4000], dcache[address % 15'h4000], dirty[address % 15'h4000]);
$stop;
*/
if(tag[address % 15'h4000] === address)
begin
r_data <= dcache[address % 15'h4000];
r_out_databus <= in_databus;
r_status <= 0;
r_address <= address;
r_lw_or_sw <= 0;
r_rs_ex_ok <= 1;
end
else
begin
r_rs_ex_ok <= 0;
//$display("miss \n");
//$stop;
if(dirty[address % 15'h4000] === 1)
begin
r_out_address <= tag[address % 15'h4000];
r_out_data <= dcache[address % 15'h4000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address;
r_out_write <= 0;
r_out_data <= 32'hz;
r_out_read <= 1;
#0.001
/*
if(address === 14999)
begin
$display("INFO READ!!!! %d %d %d\n", r_out_address, r_out_write, r_out_data);
$stop;
end
*/
dcache[address % 15'h4000] <= out_data;
tag[address % 15'h4000] <= address;
dirty[address % 15'h4000] <= 0;
r_data <= out_data;
/*
$display("READ!!!!!!! %d %d\n", address, out_data);
$stop;
*/
for(i=0; i<64; i=i+1)
begin
#0.001
r_out_read <= 0;
#0.001
if(dirty[address / 64 * 64 + i] === 1)
begin
r_out_address <= tag[(address / 64 * 64 + i) % 15'h4000];
r_out_data <= dcache[(address / 64 * 64 + i) % 15'h4000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address / 64 * 64 + i;
r_out_write <= 0;
r_out_data <= 32'hz;
r_out_read <= 1;
#0.001
dcache[out_address % 15'h4000] <= out_data;
tag[out_address % 15'h4000] <= out_address;
dirty[out_address % 15'h4000] <= 0;
end
if(in_databus[63:48] === 16'b100000_00000_00000)
r_out_databus <= in_databus + 1;
else
r_out_databus <= 64'b100000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
//r_out_databus <= 64'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= `DELAY_MEMORY;
r_address <= address;
r_lw_or_sw <= 0;
end
end
always @(negedge read)
begin
r_data <= 32'hz;
end
always @(posedge write)
begin
/*
$display("WRITE!!!!! %d %d %d %d\n", address, address*4, data, tag[address % 15'h4000]);
$stop;
*/
r_write_databus <= 0;
if(tag[address % 15'h4000] === address)
begin
dcache[address % 15'h4000] <= data;
dirty[address % 15'h4000] <= 1;
r_out_databus <= in_databus;
r_status <= 1;
r_address <= address;
r_lw_or_sw <= 1;
r_rs_ex_ok <= 1;
end
else
begin
r_rs_ex_ok <= 0;
if(dirty[address % 15'h4000] === 1)
begin
r_out_address <= tag[address % 15'h4000];
r_out_data <= dcache[address % 15'h4000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_write <= 0;
dcache[address % 15'h4000] <= data;
tag[address % 15'h4000] <= address;
dirty[address % 15'h4000] <= 0;
for(i=0; i<64; i=i+1)
begin
if(address / 64 * 64 + i !== address)
begin
#0.001
if(dirty[address / 64 * 64 + i] === 1)
begin
r_out_address <= tag[(address / 64 * 64 + i) % 15'h4000];
r_out_data <= dcache[(address / 64 * 64 + i) % 15'h4000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address / 64 * 64 + i;
r_out_write <= 0;
r_out_data <= 32'hz;
r_out_read <= 1;
#0.001
dcache[out_address % 15'h4000] <= out_data;
tag[out_address % 15'h4000] <= out_address;
dirty[address % 15'h4000] <= 0;
end
end
if(in_databus[63:48] === 16'b100000_00000_00000)
r_out_databus <= in_databus + 1;
else
r_out_databus <= 64'b100000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
//r_out_databus <= 64'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= `DELAY_MEMORY;
r_address <= address;
r_lw_or_sw <= 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int LIM = 1e+5 + 100; int n, m, k; int get_rd(int i, int j) { if (i == j) { return n; } else if (i < j) { return n + (j - i); } else { return n - (i - j); } } int get_ld(int i, int j) { if (i + j == n) { return n; } else if (i + j < n) { return i + j; } else { return i + j; } } struct detector { int i, j, id; detector(int i, int j, int id) : i(i), j(j), id(id) {} int get_rd() { return ::get_rd(i, j); } int get_ld() { return ::get_ld(i, j); } }; vector<bool> used(LIM, false); vector<long long> ans(LIM, -1); vector<vector<detector>> ld(2 * LIM); vector<vector<detector>> rd(2 * LIM); int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> m >> k; for (int i = 0; i < k; ++i) { int pi, pj; cin >> pi >> pj; detector newbie(pi, pj, i); rd[newbie.get_rd()].push_back(newbie); ld[newbie.get_ld()].push_back(newbie); } int i = 0, j = 0; int di = 1, dj = 1; long long time = 0; while (true) { int d = -1; if (di == dj) { d = get_rd(i, j); for (const detector& det : rd[d]) { int id = det.id; if (!used[id]) { ans[id] = time + abs(i - det.i); used[id] = true; } } } else { d = get_ld(i, j); for (const detector& det : ld[d]) { int id = det.id; if (!used[id]) { ans[id] = time + abs(i - det.i); used[id] = true; } } } if (di == 1 && dj == 1) { int delta = min(n - i, m - j); time += delta; i += delta; j += delta; if (i == n && j == m) { break; } if (i == n) di = -1; else dj = -1; } else if (di == -1 && dj == -1) { int delta = min(i, j); time += delta; i -= delta; j -= delta; if (i == 0 && j == 0) break; if (i == 0) di = 1; else dj = 1; } else if (di == 1 && dj == -1) { int delta = min(n - i, j); time += delta; i += delta; j -= delta; if (i == n && j == 0) break; if (i == n) di = -1; else dj = 1; } else { int delta = min(i, m - j); time += delta; i -= delta; j += delta; if (i == 0 && j == m) break; if (i == 0) di = 1; else dj = -1; } } for (int i = 0; i < k; ++i) cout << ans[i] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long K = 10001; signed main() { long long n, l, r, ans = 0; cin >> n >> l >> r; vector<long long> a(n), b(n); for (long long i = 0; i < n; i++) cin >> a[i]; for (long long i = 0; i < n; i++) cin >> b[i]; vector<long long> bad, good; for (long long i = 0; i < n; i++) { if (b[i] == 0) bad.push_back(a[i]); else good.push_back(a[i]); } if (good.size() == 0) { cout << 0 << endl; return 0; } sort(good.begin(), good.end()); long long S = 0; for (long long i = 0; i < good.size(); i++) S += good[i]; bool knapbad[K], knapgood[K]; for (long long i = 0; i < K; i++) knapbad[i] = false; for (long long i = 0; i < K; i++) knapgood[i] = false; knapbad[0] = true; knapgood[0] = true; for (long long i = 0; i < bad.size(); i++) { for (long long j = K - 1; j >= bad[i]; j--) knapbad[j] |= knapbad[j - bad[i]]; } long long pref[K + 1]; pref[0] = 0; for (long long i = 1; i <= K; i++) pref[i] = pref[i - 1] + knapbad[i - 1]; vector<vector<long long> > close(good.size()); long long INF = 1e9; close[good.size() - 1].push_back(0); for (long long i = good.size() - 1; i >= 0; i--) { for (long long j = K - 1; j >= good[i]; j--) { if (!knapgood[j] && knapgood[j - good[i]]) { if (i != 0) close[i - 1].push_back(j); knapgood[j] = true; } } } for (long long i = l; i <= r; i++) if (knapgood[i] && i != S) ans = max(ans, (long long)1); long long Kn[K]; for (long long i = 0; i < K; i++) Kn[i] = -INF; Kn[0] = 0; for (long long i = 0; i < good.size(); i++) { for (long long j = K - 1; j >= good[i]; j--) { Kn[j] = max(Kn[j], Kn[j - good[i]] + 1); } for (long long j = 0; j < close[i].size(); j++) { long long N = close[i][j]; for (long long p = 0; p < K; p++) { if (Kn[p] < 0) continue; long long L = max((long long)0, l - N), R = r - N - p; if (L > R) continue; if (pref[R + 1] - pref[L] == 0) continue; if (N + p == S) ans = max(ans, Kn[p]); else ans = max(ans, Kn[p] + 1); } } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int n, m; int R[101]; double dp[100100], sum[100100]; int main() { scanf( %d%d , &n, &m); if (m == 1) { puts( 1 ); return 0; } int score = 0; dp[0] = 1; double f = 1. / (m - 1); for (int i = 0; i < n; ++i) { scanf( %d , R + i); score += R[i]; } for (int i = 0; i < n; ++i) { int r = R[i]; sum[0] = dp[0]; for (int j = 1; j <= min(score - 1, (i + 1) * m); ++j) { sum[j] = sum[j - 1] + dp[j]; } for (int j = min(score - 1, (i + 1) * m); j > 0; --j) { dp[j] = sum[j - 1]; if (j - m - 1 >= 0) dp[j] -= sum[j - m - 1]; if (j - r >= 0) dp[j] -= dp[j - r]; dp[j] *= f; } dp[0] = 0; } double res = 1; for (int i = 0; i < score; ++i) { res += dp[i] * (m - 1); } printf( %.15lf n , res); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 16-Bit Shift Register Look-Up-Table with Carry and Clock Enable
// /___/ /\ Filename : SRLC16E.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:04 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module SRLC16E #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [15:0] INIT = 16'h0000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output Q,
output Q15,
input A0,
input A1,
input A2,
input A3,
input CE,
input CLK,
input D
);
reg [15:0] data;
wire [3:0] addr;
wire CLK_dly, D_dly, CE_dly;
wire CLK_in, D_in, CE_in;
wire clk_is_inverted;
reg notifier;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
while ((CLK_in !== 1'b0) && (first_time == 1'b1)) #1000;
deassign data;
end
assign addr[3:0] = {A3, A2, A1, A0};
always @(posedge CLK_in)
if (CE_in == 1'b1)
{data[15:0]} <= #100 {data[14:0], D_in};
assign Q = data[addr];
assign Q15 = data[15];
always @(notifier)
data[0] <= 1'bx;
`ifndef XIL_TIMING
assign D_dly = D;
assign CLK_dly = CLK;
assign CE_dly = CE;
`endif
assign clk_is_inverted = IS_CLK_INVERTED;
assign CLK_in = clk_is_inverted ^ CLK_dly;
assign D_in = D_dly;
assign CE_in = CE_dly;
specify
(A0 => Q) = (0:0:0, 0:0:0);
(A1 => Q) = (0:0:0, 0:0:0);
(A2 => Q) = (0:0:0, 0:0:0);
(A3 => Q) = (0:0:0, 0:0:0);
(CLK => Q) = (0:0:0, 0:0:0);
(CLK => Q15) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (negedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,CE_dly);
$setuphold (posedge CLK, posedge D &&& CE, 0:0:0, 0:0:0, notifier,,,CLK_dly,D_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; double lo = 0.0, hi = 10000000.0; for (int i = 1; i <= n; i++) { int sta; cin >> sta; lo = max(lo, (double)10.0 * sta / i); hi = min(hi, (double)10.0 * (sta + 1) / i); } int nextlo = floor(lo * (n + 1) / 10.0); int nexthi = ceil(hi * (n + 1) / 10.0); if (nextlo + 1 >= nexthi) { cout << unique << endl << nextlo << endl; } else { cout << not unique << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; string s2; cin >> s >> s2; transform(s.begin(), s.end(), s.begin(), ::tolower); transform(s2.begin(), s2.end(), s2.begin(), ::tolower); if (s == s2) { printf( 0 n ); } else if (s < s2) { printf( -1 n ); } else if (s > s2) { printf( 1 n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, cnt[10], sta[10], g[10][10], f[10][10], pru[10], deg[10], tag[10]; char s[10]; int cal(int x) { int res = 0; while (x) { res++; x /= 10; } return res; } int read() { scanf( %s , s); int res = 0; for (int i = 0; s[i]; i++) res++; return res; } bool hall() { for (int i = 1; i <= m; i++) for (int j = i; j <= m; j++) f[i][j] = g[i][j]; for (int i = 1; i <= m; i++) deg[i] = 1; for (int i = 1; i <= m - 2; i++) deg[pru[i]]++; for (int i = 1; i <= m - 2; i++) { bool ok = 0; for (int j = 1; j <= m; j++) { if (deg[j] == 1) { ok = 1; deg[pru[i]]--; deg[j]--; if (f[min(pru[i], j)][max(pru[i], j)] == 0) return 0; f[min(pru[i], j)][max(pru[i], j)]--; break; } } if (!ok) return 0; } int x, y; for (int i = 1; i <= m; i++) { if (deg[i] == 1) { x = i; break; } } for (int i = 1; i <= m; i++) { if (deg[i] == 1) y = i; } if (f[x][y] == 0) return 0; f[x][y]--; int tmp; for (int i = 1; i < 1 << m; i++) { tmp = 0; for (int j = 0; j < m; j++) if (i & (1 << j)) tmp += cnt[j + 1] - 1; for (int j = 0; j < m; j++) for (int k = j; k < m; k++) if (((1 << j) & i) || (i & (1 << k))) tmp -= f[j + 1][k + 1]; if (tmp > 0) return 0; } return 1; } bool hall_() { int tmp; for (int i = 1; i < 1 << m; i++) { tmp = 0; for (int j = 0; j < m; j++) if (i & (1 << j)) tmp += cnt[j + 1]; for (int j = 0; j < m; j++) for (int k = j; k < m; k++) if (((1 << j) & i) || (i & (1 << k))) tmp -= g[j + 1][k + 1]; if (tmp > 0) return 0; } return 1; } void print() { for (int i = 1; i <= m; i++) deg[i] = 1; for (int i = 1; i <= m - 2; i++) deg[pru[i]]++; for (int i = 1; i <= m - 2; i++) { for (int j = 1; j <= m; j++) { if (deg[j] == 1) { deg[pru[i]]--; deg[j]--; g[min(pru[i], j)][max(pru[i], j)]--; printf( %d %d n , sta[pru[i]], sta[j]); break; } } } int x, y; for (int i = 1; i <= m; i++) { if (deg[i] == 1) { x = i; break; } } for (int i = 1; i <= m; i++) { if (deg[i] == 1) y = i; } g[x][y]--; printf( %d %d n , sta[x], sta[y]); n -= m; for (int i = 1; i <= m; i++) tag[i] = sta[i], sta[i]--, cnt[i]--; for (int i = 1; i <= m; i++) { while (cnt[i] != 0) { for (int j = 1; j <= m; j++) { if (g[min(i, j)][max(i, j)]) { g[min(i, j)][max(i, j)]--; cnt[i]--; if (hall_()) { printf( %d %d n , sta[i], tag[j]); sta[i]--; break; } cnt[i]++; g[min(i, j)][max(i, j)]++; } } } } } void dfs(int x) { if (x == m - 2 + 1) { if (hall()) { print(); exit(0); } return; } for (int i = 1; i <= m; i++) { pru[x] = i; dfs(x + 1); } } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int x = read(), y = read(); if (x > y) swap(x, y); g[x][y]++; } for (int i = 1; i <= n; i++) { m = cal(i); cnt[m]++; sta[m] = i; } if (m == 1) { for (int i = 1; i < n; i++) printf( %d %d n , i, n); return 0; } dfs(1); puts( -1 ); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/);
logic [3:0] array_simp [1:0] [3:0]; // big endian array
initial begin
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'h3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//array_simp[0] = '{ 1:4'd3, default:13 };
//if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_1234) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3210_3210) $stop;
array_simp = '{2{ '{4{ 4'd3 }} }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 32'h3333_3333) $stop;
// Not legal in other simulators - replication doesn't match
// However IEEE suggests this is legal.
//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Zet processor core
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet_core (
input clk,
input rst,
// interrupts
input intr,
output inta,
input nmi,
output nmia,
// interface to wishbone
output [19:0] cpu_adr_o,
input [15:0] iid_dat_i,
input [15:0] cpu_dat_i,
output [15:0] cpu_dat_o,
output cpu_byte_o,
input cpu_block,
output cpu_mem_op,
output cpu_m_io,
output cpu_we_o,
output [19:0] pc // for debugging purposes
);
// Net declarations
wire [`IR_SIZE-1:0] ir;
wire [15:0] off;
wire [15:0] imm;
wire wr_ip0;
wire [15:0] cs;
wire [15:0] ip;
wire of;
wire zf;
wire ifl;
wire iflm;
wire tfl;
wire tflm;
wire iflss;
wire wr_ss;
wire cx_zero;
wire div_exc;
wire [19:0] addr_exec;
wire byte_fetch;
wire byte_exec;
// wire decode - microcode
wire [`MICRO_ADDR_WIDTH-1:0] seq_addr;
wire [3:0] src;
wire [3:0] dst;
wire [3:0] base;
wire [3:0] index;
wire [1:0] seg;
wire end_seq;
wire [2:0] fdec;
wire div;
// wires fetch - decode
wire [7:0] opcode;
wire [7:0] modrm;
wire rep;
wire exec_st;
wire ld_base;
wire [2:0] sop_l;
wire need_modrm;
wire need_off;
wire need_imm;
wire off_size;
wire imm_size;
wire ext_int;
// wires fetch - microcode
wire [15:0] off_l;
wire [15:0] imm_l;
wire [15:0] imm_d;
wire [`IR_SIZE-1:0] rom_ir;
wire [5:0] ftype;
// wires fetch - exec
wire [15:0] imm_f;
// wires and regs for hlt
wire block_or_hlt;
wire hlt_op;
wire hlt_in;
wire hlt_out;
reg hlt_op_old;
reg hlt;
// regs for nmi
reg nmir;
reg nmi_old;
reg nmia_old;
wire use_eintp;
// Module instantiations
zet_fetch fetch (
.clk (clk),
.rst (rst),
// to decode
.opcode (opcode),
.modrm (modrm),
.rep (rep),
.exec_st (exec_st),
.ld_base (ld_base),
.sop_l (sop_l),
// from decode
.need_modrm (need_modrm),
.need_off (need_off),
.need_imm (need_imm),
.off_size (off_size),
.imm_size (imm_size),
.ext_int (ext_int),
.end_seq (end_seq),
// to microcode
.off_l (off_l),
.imm_l (imm_l),
// from microcode
.ftype (ftype),
// to exec
.imm_f (imm_f),
.wr_ip0 (wr_ip0),
// from exec
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.iflm (iflm),
.tflm (tflm),
.iflss (iflss),
.cx_zero (cx_zero),
.div_exc (div_exc),
// to wb
.data (cpu_dat_i),
.pc (pc),
.bytefetch (byte_fetch),
.block (block_or_hlt),
.intr (intr),
.nmir (nmir),
.use_eintp (use_eintp)
);
zet_decode decode (
.clk (clk),
.rst (rst),
.opcode (opcode),
.modrm (modrm),
.rep (rep),
.block (block_or_hlt),
.exec_st (exec_st),
.div_exc (div_exc),
.ld_base (ld_base),
.div (div),
.tfl (tfl),
.tflm (tflm),
.need_modrm (need_modrm),
.need_off (need_off),
.need_imm (need_imm),
.off_size (off_size),
.imm_size (imm_size),
.sop_l (sop_l),
.intr (intr),
.ifl (ifl),
.iflm (iflm),
.inta (inta),
.ext_int (ext_int),
.nmir (nmir),
.nmia (nmia),
.wr_ss (wr_ss),
.iflss (iflss),
.seq_addr (seq_addr),
.src (src),
.dst (dst),
.base (base),
.index (index),
.seg (seg),
.f (fdec),
.end_seq (end_seq),
.use_eintp (use_eintp)
);
zet_micro_data micro_data (
// from decode
.n_micro (seq_addr),
.off_i (off_l),
.imm_i (imm_l),
.src (src),
.dst (dst),
.base (base),
.index (index),
.seg (seg),
.fdec (fdec),
.div (div),
.end_seq (end_seq),
// to exec
.ir (rom_ir),
.off_o (off),
.imm_o (imm_d)
);
zet_exec exec (
.clk (clk),
.rst (rst),
// from fetch
.ir (ir),
.off (off),
.imm (imm),
.wrip0 (wr_ip0),
// to fetch
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.ifl (ifl),
.tfl (tfl),
.cx_zero (cx_zero),
.div_exc (div_exc),
.wr_ss (wr_ss),
// from wb
.memout (iid_dat_i),
.wr_data (cpu_dat_o),
.addr (addr_exec),
.we (cpu_we_o),
.m_io (cpu_m_io),
.byteop (byte_exec),
.block (block_or_hlt)
);
// Assignments
assign cpu_adr_o = exec_st ? addr_exec : pc;
assign cpu_byte_o = exec_st ? byte_exec : byte_fetch;
assign cpu_mem_op = ir[`MEM_OP];
assign ir = exec_st ? rom_ir : `ADD_IP;
assign imm = exec_st ? imm_d : imm_f;
assign ftype = rom_ir[28:23];
assign hlt_op = ((opcode == `OP_HLT) && exec_st);
assign hlt_in = (hlt_op && !hlt_op_old && !hlt_out);
assign hlt_out = (intr & ifl) | nmir;
assign block_or_hlt = cpu_block | hlt | hlt_in;
// Behaviour
always @(posedge clk)
if (rst)
hlt_op_old <= 1'b0;
else
if (hlt_op)
hlt_op_old <= 1'b1;
else
hlt_op_old <= 1'b0;
always @(posedge clk)
if (rst)
hlt <= 1'b0;
else
if (hlt_in)
hlt <= 1'b1;
else if (hlt_out)
hlt <= 1'b0;
always @(posedge clk)
if (rst)
begin
nmir <= 1'b0;
nmi_old <= 1'b0;
nmia_old <= 1'b0;
end
else
begin
nmi_old <= nmi;
nmia_old <= nmia;
if (nmi & ~nmi_old)
nmir <= 1'b1;
else if (nmia_old)
nmir <= 1'b0;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:10:17 05/08/2017
// Design Name: axi_spi_if
// Module Name: D:/Projects/Rendszerarch/axi_spi_master_if/axi_spi/axi_spi_test.v
// Project Name: axi_spi
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: axi_spi_if
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module axi_spi_test;
// Inputs
reg clk_i;
reg reset_n_i;
reg awvalid_i;
reg [27:0] awaddr_i;
reg awprot_i;
reg wvalid_i;
reg [31:0] wdata_i;
reg [3:0] wstrb_i;
reg bready_i;
reg arvalid_i;
reg [27:0] araddr_i;
reg [2:0] arprot_i;
reg rready_i;
reg spi_miso_i;
// Outputs
wire awready_o;
wire wready_o;
wire bvalid_o;
wire [1:0] bresp_o;
wire arready_o;
wire rvalid_o;
wire [31:0] rdata_o;
wire [1:0] rresp_o;
wire [3:0] spi_ssel_o;
wire spi_sck_o;
wire spi_mosi_o;
// Instantiate the Unit Under Test (UUT)
axi_spi_if uut (
.clk_i(clk_i),
.reset_n_i(reset_n_i),
.awvalid_i(awvalid_i),
.awready_o(awready_o),
.awaddr_i(awaddr_i),
.awprot_i(awprot_i),
.wvalid_i(wvalid_i),
.wready_o(wready_o),
.wdata_i(wdata_i),
.wstrb_i(wstrb_i),
.bvalid_o(bvalid_o),
.bready_i(bready_i),
.bresp_o(bresp_o),
.arvalid_i(arvalid_i),
.arready_o(arready_o),
.araddr_i(araddr_i),
.arprot_i(arprot_i),
.rvalid_o(rvalid_o),
.rready_i(rready_i),
.rdata_o(rdata_o),
.rresp_o(rresp_o),
.spi_ssel_o(spi_ssel_o),
.spi_sck_o(spi_sck_o),
.spi_mosi_o(spi_mosi_o),
.spi_miso_i(spi_miso_i)
);
initial begin
// Initialize Inputs
clk_i = 0;
reset_n_i = 0;
awvalid_i = 0;
awaddr_i = 0;
awprot_i = 0;
wvalid_i = 0;
wdata_i = 0;
wstrb_i = 0;
bready_i = 0;
arvalid_i = 0;
araddr_i = 0;
arprot_i = 0;
rready_i = 0;
spi_miso_i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset_n_i = 1;
spi_miso_i = 1;
bready_i = 1;
rready_i = 1;
/*
reg_control_i = 32'h0000_0602;
reg_trans_ctrl_i = 32'h0000_0002;
*/
wdata_i = 32'h0000_0602;
awaddr_i = 0;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#1000;
wdata_i = 32'h0000_0002;
awaddr_i = 1;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
wdata_i = 32'h0000_0073;
awaddr_i = 3;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
wdata_i = 32'h0000_0073;
awaddr_i = 4;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
end
always #5 clk_i = ~clk_i;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__BUF_FUNCTIONAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; vector<int> s[10]; int n1, n2; int ok(int a, int b) { int sum = a + b * 2; int len = 0; for (int i = 0; i < n1 - a; i++) len += s[1][i]; for (int i = 0; i < n2 - b; i++) len += s[2][i]; return len <= sum; } int main() { int a, b, n, m, i, j, ans = 99999999; ; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d%d , &a, &b); s[a].push_back(b); } sort(s[1].begin(), s[1].end()); sort(s[2].begin(), s[2].end()); n1 = s[1].size(); n2 = s[2].size(); for (i = 0; i <= n1; i++) for (j = 0; j <= n2; j++) { if (ok(i, j)) { if (i + j * 2 < ans) ans = i + j * 2; } } printf( %d n , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_SYMBOL_V
`define SKY130_FD_SC_LS__DLYGATE4SD2_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD2_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_LP_V
`define SKY130_FD_SC_LP__ISO0N_LP_V
/**
* iso0n: ????.
*
* Verilog wrapper for iso0n with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__iso0n.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso0n_lp (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__iso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.KAGND(KAGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso0n_lp (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__iso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_LP_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: ip_checksum_ttl.v
// Project: NF2.1 reference router
// Description: Check the IP checksum over the IP header, and
// generate a new one assuming that the TTL gets decremented.
// Check if the TTL is valid, and generate the new TTL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ip_checksum_ttl
#(parameter DATA_WIDTH = 64)
(
//--- datapath interface
input [DATA_WIDTH-1:0] in_data,
input in_wr,
//--- interface to preprocess
input word_ETH_IP_VER,
input word_IP_LEN_ID,
input word_IP_FRAG_TTL_PROTO,
input word_IP_CHECKSUM_SRC_HI,
input word_IP_SRC_DST,
input word_IP_DST_LO,
// --- interface to process
output ip_checksum_vld,
output ip_checksum_is_good,
output ip_hdr_has_options,
output ip_ttl_is_good,
output [7:0] ip_new_ttl,
output [15:0] ip_new_checksum, // new checksum assuming decremented TTL
input rd_checksum,
// misc
input reset,
input clk
);
//---------------------- Wires and regs---------------------------
reg [19:0] checksum_word_0, checksum_word_1;
reg [19:0] in_word_0_0, in_word_0_1, in_word_0_2;
reg [19:0] in_word_1_0, in_word_1_1, in_word_1_2;
wire [19:0] next_sum_0, next_sum_1;
reg [16:0] adjusted_checksum;
reg checksum_done;
wire empty;
reg [7:0] ttl_new;
reg ttl_good;
reg hdr_has_options;
reg add_carry_1, add_carry_2;
//------------------------- Modules-------------------------------
fallthrough_small_fifo #(.WIDTH(27), .MAX_DEPTH_BITS(2))
arp_fifo
(.din ({&checksum_word_0[15:0], adjusted_checksum[15:0], ttl_good, ttl_new, hdr_has_options}), // {IP good, new checksum}
.wr_en (checksum_done), // Write enable
.rd_en (rd_checksum), // Read the next word
.dout ({ip_checksum_is_good, ip_new_checksum, ip_ttl_is_good, ip_new_ttl, ip_hdr_has_options}),
.full (),
.nearly_full (),
.prog_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------- Logic -------------------------------
assign ip_checksum_vld = !empty;
/* MUX the additions to save adder logic */
assign next_sum_0 = in_word_0_0 + in_word_0_1 + in_word_0_2;
assign next_sum_1 = in_word_1_0 + in_word_1_1 + in_word_1_2;
always @(*) begin
in_word_0_0 = {4'h0, in_data[31:16]};
in_word_0_1 = {4'h0, in_data[15:0]};
in_word_0_2 = checksum_word_0;
in_word_1_0 = {4'h0, in_data[DATA_WIDTH-1:DATA_WIDTH-16]};
in_word_1_1 = {4'h0, in_data[DATA_WIDTH-17:DATA_WIDTH-32]};
in_word_1_2 = checksum_word_1;
if(word_ETH_IP_VER) begin
in_word_0_0 = 20'h0;
in_word_0_2 = 20'h0;
end
if(word_IP_DST_LO) begin
in_word_0_0 = {4'h0, in_data[DATA_WIDTH-1:DATA_WIDTH-16]};
in_word_0_1 = checksum_word_1;
end
if(add_carry_1 | add_carry_2) begin
in_word_0_0 = 20'h0;
in_word_0_1 = {16'h0, checksum_word_0[19:16]};
in_word_0_2 = {4'h0, checksum_word_0[15:0]};
end
if(word_IP_LEN_ID) begin
in_word_1_2 = 20'h0;
end
end // always @ (*)
// checksum logic. 16bit 1's complement over the IP header.
// --- see RFC1936 for guidance.
// 1's compl add: do a 2's compl add and then add the carry out
// as if it were a carry in.
// Final checksum (computed over the whole header incl checksum)
// is in checksum_a and valid when IP_checksum_valid is 1
// If checksum is good then it should be 0xffff
always @(posedge clk) begin
if(reset) begin
checksum_word_0 <= 20'h0; // does the addition for the low 32 bits
checksum_word_1 <= 20'h0; // does the addition for the high 32 bits
adjusted_checksum <= 17'h0; // calculates the new chksum
checksum_done <= 0;
add_carry_1 <= 0;
add_carry_2 <= 0;
ttl_new <= 0;
ttl_good <= 0;
hdr_has_options <= 0;
end
else begin
/* make sure the version is correct and there are no options */
if(word_ETH_IP_VER) begin
hdr_has_options <= (in_data[15:8]!=8'h45);
end
if(word_IP_FRAG_TTL_PROTO) begin
ttl_new <= (in_data[15:8]==8'h0) ? 8'h0 : in_data[15:8] - 1'b1;
ttl_good <= (in_data[15:8] > 8'h1);
end
if(word_ETH_IP_VER | word_IP_FRAG_TTL_PROTO | word_IP_SRC_DST |
word_IP_DST_LO | add_carry_1 | add_carry_2) begin
checksum_word_0 <= next_sum_0;
end
if(word_IP_LEN_ID | word_IP_CHECKSUM_SRC_HI) begin
checksum_word_1 <= next_sum_1;
end
// see RFC 1141
if(word_IP_CHECKSUM_SRC_HI) begin
adjusted_checksum <= {1'h0, in_data[DATA_WIDTH-1:DATA_WIDTH-16]} + 17'h0100; // adjust for the decrement in TTL
end
if(word_IP_DST_LO) begin
adjusted_checksum <= {1'h0, adjusted_checksum[15:0]} + adjusted_checksum[16];
add_carry_1 <= 1;
end
else begin
add_carry_1 <= 0;
end
if(add_carry_1) begin
add_carry_2 <= 1;
end
else begin
add_carry_2 <= 0;
end
if(add_carry_2) begin
checksum_done <= 1;
end
else begin
checksum_done <= 0;
end
// synthesis translate_off
// If we have any carry left in top 4 bits then algorithm is wrong
if (checksum_done && checksum_word_0[19:16] != 4'h0) begin
$display("%t %m ERROR: top 4 bits of checksum_word_0 not zero - algo wrong???",
$time);
#100 $stop;
end
// synthesis translate_on
end // else: !if(reset)
end // always @ (posedge clk)
endmodule // IP_checksum
|
#include <bits/stdc++.h> using namespace std; const int N = 500001; const int oo = 1e9; const int LOGN = 20; const int MOD = 1000000007; const double PI = acos(-1); int n, a[N]; int main() { cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i]; } int mn = oo, idx = -1; for (int t = 1; t <= 101; ++t) { int cur = 0; for (int j = 0; j < n; ++j) { int cst = max(0, abs(a[j] - t) - 1); cur += cst; } if (cur < mn) { mn = cur; idx = t; } } cout << idx << << mn << endl; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 11:55:09 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub C:/ZyboIP/general_ip/svd_2x2/svd_2x2.runs/sqrt_synth_1/sqrt_stub.v
// Design : sqrt
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "cordic_v6_0_11,Vivado 2016.4" *)
module sqrt(aclk, s_axis_cartesian_tvalid,
s_axis_cartesian_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]" */;
input aclk;
input s_axis_cartesian_tvalid;
input [15:0]s_axis_cartesian_tdata;
output m_axis_dout_tvalid;
output [15:0]m_axis_dout_tdata;
endmodule
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1'b1)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTP_BLACKBOX_V
`define SKY130_FD_SC_LP__SRSDFRTP_BLACKBOX_V
/**
* srsdfrtp: Scan flop with sleep mode, inverted reset, non-inverted
* clock, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
SLEEP_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; char s[1000010]; int n, p[1000010]; int main() { scanf( %s , s), n = strlen(s); for (int i = 0; i < n; i++) if (s[i] == 1 ) p[n - 1 - i] = 1; for (int i = 0, j; i < n + 2;) if (!p[i]) i++; else { j = i; while (p[j]) j++; if (j - i >= 2) { p[i] = -1; for (int k = i + 1; k < j; k++) p[k] = 0; p[j] = 1; } i = j; } int S = 0; for (int i = 0; i < n + 2; i++) if (p[i] != 0) S++; printf( %d n , S); for (int i = 0; i < n + 2; i++) if (p[i] != 0) if (p[i] > 0) printf( +2^%d n , i); else printf( -2^%d n , i); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, s, e; long long x[5001]; long long a[5001]; long long b[5001]; long long c[5001]; long long d[5001]; long long pd[5001][5001]; long long func(int at, int comp, int left, int right) { if (comp <= 0 && at != 0) return 0x3f3f3f3f3f3f3f3fll; if (at == n) return ((comp == 1) ? 0 : 0x3f3f3f3f3f3f3f3fll); if (pd[at][comp] != -1) return pd[at][comp]; long long ans = 0x3f3f3f3f3f3f3f3fll; int onlycomp = (comp - left - right); if (at != s && at != e) { ans = func(at + 1, comp + 1, left, right) - 2 * x[at] + d[at] + b[at]; if (left) { ans = min(ans, func(at + 1, comp, left, right) + a[at] + d[at]); if (onlycomp) ans = min(ans, func(at + 1, comp - 1, left, right) + a[at] + c[at] + 2 * x[at]); } if (right) { ans = min(ans, func(at + 1, comp, left, right) + c[at] + b[at]); if (onlycomp) ans = min(ans, func(at + 1, comp - 1, left, right) + c[at] + a[at] + 2 * x[at]); } if (onlycomp) { ans = min( ans, func(at + 1, comp - 1, left, right) + c[at] + a[at] + 2 * x[at]); ans = min(ans, func(at + 1, comp, left, right) + b[at] + c[at]); ans = min(ans, func(at + 1, comp, left, right) + a[at] + d[at]); } if (at == n - 1 && comp == 2) ans = min( ans, func(at + 1, comp - 1, left, right) + c[at] + a[at] + 2 * x[at]); } else if (at == s) { ans = func(at + 1, comp + 1, 1, right) - x[at] + d[at]; if (onlycomp) ans = min(ans, func(at + 1, comp, 1, right) + x[at] + c[at]); if (at == n - 1 && comp == 1) ans = min(ans, func(at + 1, comp, 1, right) + c[at] + x[at]); } else { ans = func(at + 1, comp + 1, left, 1) - x[at] + b[at]; if (onlycomp) ans = min(ans, func(at + 1, comp, left, 1) + x[at] + a[at]); if (at == n - 1 && comp == 1) ans = min(ans, func(at + 1, comp, left, 1) + a[at] + x[at]); } return pd[at][comp] = ans; } int main() { scanf( %d %d %d , &n, &s, &e); s--; e--; for (int i = 0; i < n; i++) scanf( %lld , &x[i]); for (int i = 0; i < n; i++) scanf( %lld , &a[i]); for (int i = 0; i < n; i++) scanf( %lld , &b[i]); for (int i = 0; i < n; i++) scanf( %lld , &c[i]); for (int i = 0; i < n; i++) scanf( %lld , &d[i]); memset(pd, -1, sizeof pd); printf( %lld n , func(0, 0, 0, 0)); return 0; }
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