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// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// frame INT generation
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module zint
(
input wire fclk,
input wire zpos,
input wire zneg,
input wire int_start,
input wire iorq_n,
input wire m1_n,
input wire wait_n,
output reg int_n
);
wire intend;
reg [9:0] intctr;
reg [1:0] wr;
`ifdef SIMULATE
initial
begin
intctr = 10'b1100000000;
end
`endif
always @(posedge fclk)
wr[1:0] <= { wr[0], wait_n };
always @(posedge fclk)
begin
if( int_start )
intctr <= 10'd0;
else if( !intctr[9:8] && wr[1] )
intctr <= intctr + 10'd1;
end
assign intend = intctr[9:8] || ( (!iorq_n) && (!m1_n) && zneg );
always @(posedge fclk)
begin
if( int_start )
int_n <= 1'b0;
else if( intend )
int_n <= 1'bZ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, k; int a[100]; int ans; int main() { cin >> n >> m >> k; for (int i = 0; i < k; i++) { cin >> a[i]; a[i]--; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int x; cin >> x; x--; int pos = 0; while (a[pos] != x) { pos++; } ans += pos + 1; for (int i = pos; i > 0; i--) { a[i] = a[i - 1]; } a[0] = x; } } cout << ans; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22O_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A22O_BEHAVIORAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100000 + 5; int g[10][10]; int a[5]; int ans; int cal() { int sum = 0; for (int i = 0; i < 5; ++i) { for (int j = i; j < 4; j += 2) sum += g[a[j]][a[j + 1]] + g[a[j + 1]][a[j]]; } return sum; } int main() { for (int i = 0; i < 5; ++i) for (int j = 0; j < 5; ++j) cin >> g[i][j]; for (int i = 0; i < 5; ++i) a[i] = i; ans = -1; do { ans = max(ans, cal()); } while (next_permutation(a, a + 5)); cout << ans << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SDFSBP_FUNCTIONAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_s_pg/sky130_fd_sc_hs__u_df_p_s_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfsbp (
VPWR ,
VGND ,
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_s_pg `UNIT_DELAY u_df_p_s_pg0 (buf_Q , mux_out, CLK, SET, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSBP_FUNCTIONAL_V
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ulight_fifo_auto_start (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int x, y; int p[1000003]; int r[1000003]; map<int, int> a; int ans[200003]; int s; int parent(int x) { if (p[x] < 0) return x; return p[x] = parent(p[x]); } void join(int x, int y) { p[y] = parent(x); } int main() { fill_n(p, 1000003, -1); scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d%d , &x, &y); if (y) join(x, y); a.insert(pair<int, int>(x, y)); } int i = 2; int j = 0; while (a[j] != 0) { ans[i] = a[j]; j = a[j]; i += 2; } i = 1; j = 0; while (p[j] < 0 || parent(j) == 0) j++; j = parent(j); ans[i] = j; i += 2; while (a[j] != 0) { ans[i] = a[j]; j = a[j]; i += 2; } for (i = 1; i <= n; ++i) printf( %d , ans[i]); return 0; }
|
//
// .. hwt-autodoc::
//
module FullAdder (
input wire a,
input wire b,
input wire ci,
output reg co,
output reg s
);
always @(a, b, ci) begin: assig_process_co
co = a & b | (a & ci) | (b & ci);
end
always @(a, b, ci) begin: assig_process_s
s = a ^ b ^ ci;
end
endmodule
//
// .. hwt-autodoc::
//
module RippleAdder2 #(
parameter p_wordlength = 4
) (
input wire[3:0] a,
input wire[3:0] b,
input wire ci,
output reg co,
output reg[3:0] s
);
reg[4:0] c;
reg sig_fa_0_a;
reg sig_fa_0_b;
reg sig_fa_0_ci;
wire sig_fa_0_co;
wire sig_fa_0_s;
reg sig_fa_1_a;
reg sig_fa_1_b;
reg sig_fa_1_ci;
wire sig_fa_1_co;
wire sig_fa_1_s;
reg sig_fa_2_a;
reg sig_fa_2_b;
reg sig_fa_2_ci;
wire sig_fa_2_co;
wire sig_fa_2_s;
reg sig_fa_3_a;
reg sig_fa_3_b;
reg sig_fa_3_ci;
wire sig_fa_3_co;
wire sig_fa_3_s;
FullAdder fa_0_inst (
.a(sig_fa_0_a),
.b(sig_fa_0_b),
.ci(sig_fa_0_ci),
.co(sig_fa_0_co),
.s(sig_fa_0_s)
);
FullAdder fa_1_inst (
.a(sig_fa_1_a),
.b(sig_fa_1_b),
.ci(sig_fa_1_ci),
.co(sig_fa_1_co),
.s(sig_fa_1_s)
);
FullAdder fa_2_inst (
.a(sig_fa_2_a),
.b(sig_fa_2_b),
.ci(sig_fa_2_ci),
.co(sig_fa_2_co),
.s(sig_fa_2_s)
);
FullAdder fa_3_inst (
.a(sig_fa_3_a),
.b(sig_fa_3_b),
.ci(sig_fa_3_ci),
.co(sig_fa_3_co),
.s(sig_fa_3_s)
);
always @(ci, sig_fa_0_co, sig_fa_1_co, sig_fa_2_co, sig_fa_3_co) begin: assig_process_c
c = {{{{sig_fa_3_co, sig_fa_2_co}, sig_fa_1_co}, sig_fa_0_co}, ci};
end
always @(c) begin: assig_process_co
co = c[4];
end
always @(sig_fa_0_s, sig_fa_1_s, sig_fa_2_s, sig_fa_3_s) begin: assig_process_s
s = {{{sig_fa_3_s, sig_fa_2_s}, sig_fa_1_s}, sig_fa_0_s};
end
always @(a) begin: assig_process_sig_fa_0_a
sig_fa_0_a = a[0];
end
always @(b) begin: assig_process_sig_fa_0_b
sig_fa_0_b = b[0];
end
always @(c) begin: assig_process_sig_fa_0_ci
sig_fa_0_ci = c[0];
end
always @(a) begin: assig_process_sig_fa_1_a
sig_fa_1_a = a[1];
end
always @(b) begin: assig_process_sig_fa_1_b
sig_fa_1_b = b[1];
end
always @(c) begin: assig_process_sig_fa_1_ci
sig_fa_1_ci = c[1];
end
always @(a) begin: assig_process_sig_fa_2_a
sig_fa_2_a = a[2];
end
always @(b) begin: assig_process_sig_fa_2_b
sig_fa_2_b = b[2];
end
always @(c) begin: assig_process_sig_fa_2_ci
sig_fa_2_ci = c[2];
end
always @(a) begin: assig_process_sig_fa_3_a
sig_fa_3_a = a[3];
end
always @(b) begin: assig_process_sig_fa_3_b
sig_fa_3_b = b[3];
end
always @(c) begin: assig_process_sig_fa_3_ci
sig_fa_3_ci = c[3];
end
generate if (p_wordlength != 4)
$error("%m Generated only for this param value");
endgenerate
endmodule
|
`timescale 1ns/10ps
module pll_vga_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("25.0 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.rst (rst),
.refclk (refclk)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v2_3_phy_ocd_cntlr.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Steps through the major sections of the output clock
// delay algorithm. Enabling various subblocks at the right time.
//
// Steps through each byte of the interface.
//
// Implements both the simple and complex data pattern.
//
// for each byte in interface
// begin
// Limit
// Scan - which includes DQS centering
// Precharge
// end
// set _wrlvl and _done equal to one
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ocd_cntlr #
(parameter TCQ = 100,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8)
(/*AUTOARG*/
// Outputs
wrlvl_final, complex_wrlvl_final, oclk_init_delay_done,
ocd_prech_req, lim_start, complex_oclkdelay_calib_done,
oclkdelay_calib_done, phy_rddata_en_1, phy_rddata_en_2,
phy_rddata_en_3, ocd_cntlr2stg2_dec, oclkdelay_calib_cnt,
reset_scan,
// Inputs
clk, rst, prech_done, oclkdelay_calib_start,
complex_oclkdelay_calib_start, lim_done, phy_rddata_en,
po_counter_read_val, po_rdy, scan_done
);
localparam ONE = 1;
input clk;
input rst;
output wrlvl_final, complex_wrlvl_final;
reg wrlvl_final_ns, wrlvl_final_r, complex_wrlvl_final_ns, complex_wrlvl_final_r;
always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final_ns;
always @(posedge clk) complex_wrlvl_final_r <= #TCQ complex_wrlvl_final_ns;
assign wrlvl_final = wrlvl_final_r;
assign complex_wrlvl_final = complex_wrlvl_final_r;
// Completed initial delay increment
output oclk_init_delay_done; // may not need this... maybe for fast cal mode.
assign oclk_init_delay_done = 1'b1;
// Precharge done status from ddr_phy_init
input prech_done;
reg ocd_prech_req_ns, ocd_prech_req_r;
always @(posedge clk) ocd_prech_req_r <= #TCQ ocd_prech_req_ns;
output ocd_prech_req;
assign ocd_prech_req = ocd_prech_req_r;
input oclkdelay_calib_start, complex_oclkdelay_calib_start;
input lim_done;
reg lim_start_ns, lim_start_r;
always @(posedge clk) lim_start_r <= #TCQ lim_start_ns;
output lim_start;
assign lim_start = lim_start_r;
reg complex_oclkdelay_calib_done_ns, complex_oclkdelay_calib_done_r;
always @(posedge clk) complex_oclkdelay_calib_done_r <= #TCQ complex_oclkdelay_calib_done_ns;
output complex_oclkdelay_calib_done;
assign complex_oclkdelay_calib_done = complex_oclkdelay_calib_done_r;
reg oclkdelay_calib_done_ns, oclkdelay_calib_done_r;
always @(posedge clk) oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done_ns;
output oclkdelay_calib_done;
assign oclkdelay_calib_done = oclkdelay_calib_done_r;
input phy_rddata_en;
reg prde_r1, prde_r2;
always @(posedge clk) prde_r1 <= #TCQ phy_rddata_en;
always @(posedge clk) prde_r2 <= #TCQ prde_r1;
wire prde = complex_oclkdelay_calib_start ? prde_r2 : phy_rddata_en;
reg phy_rddata_en_r1, phy_rddata_en_r2, phy_rddata_en_r3;
always @(posedge clk) phy_rddata_en_r1 <= #TCQ prde;
always @(posedge clk) phy_rddata_en_r2 <= #TCQ phy_rddata_en_r1;
always @(posedge clk) phy_rddata_en_r3 <= #TCQ phy_rddata_en_r2;
output phy_rddata_en_1, phy_rddata_en_2, phy_rddata_en_3;
assign phy_rddata_en_1 = phy_rddata_en_r1;
assign phy_rddata_en_2 = phy_rddata_en_r2;
assign phy_rddata_en_3 = phy_rddata_en_r3;
input [8:0] po_counter_read_val;
reg ocd_cntlr2stg2_dec_r;
output ocd_cntlr2stg2_dec;
assign ocd_cntlr2stg2_dec = ocd_cntlr2stg2_dec_r;
input po_rdy;
reg [3:0] po_rd_wait_ns, po_rd_wait_r;
always @(posedge clk) po_rd_wait_r <= #TCQ po_rd_wait_ns;
reg [DQS_CNT_WIDTH-1:0] byte_ns, byte_r;
always @(posedge clk) byte_r <= #TCQ byte_ns;
output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
assign oclkdelay_calib_cnt = {1'b0, byte_r};
reg reset_scan_ns, reset_scan_r;
always @(posedge clk) reset_scan_r <= #TCQ reset_scan_ns;
output reset_scan;
assign reset_scan = reset_scan_r;
input scan_done;
reg [2:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
// Primary state machine.
always @(*) begin
// Default next state assignments.
byte_ns = byte_r;
complex_wrlvl_final_ns = complex_wrlvl_final_r;
lim_start_ns = lim_start_r;
oclkdelay_calib_done_ns = oclkdelay_calib_done_r;
complex_oclkdelay_calib_done_ns = complex_oclkdelay_calib_done_r;
ocd_cntlr2stg2_dec_r = 1'b0;
po_rd_wait_ns = po_rd_wait_r;
if (|po_rd_wait_r) po_rd_wait_ns = po_rd_wait_r - 4'b1;
reset_scan_ns = reset_scan_r;
wrlvl_final_ns = wrlvl_final_r;
sm_ns = sm_r;
ocd_prech_req_ns= 1'b0;
if (rst == 1'b1) begin
// RESET next states
complex_oclkdelay_calib_done_ns = 1'b0;
complex_wrlvl_final_ns = 1'b0;
sm_ns = /*AK("READY")*/3'd0;
lim_start_ns = 1'b0;
oclkdelay_calib_done_ns = 1'b0;
reset_scan_ns = 1'b1;
wrlvl_final_ns = 1'b0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/3'd0: begin
byte_ns = {DQS_CNT_WIDTH{1'b0}};
if (oclkdelay_calib_start && ~oclkdelay_calib_done_r ||
complex_oclkdelay_calib_start && ~complex_oclkdelay_calib_done_r)
begin
sm_ns = /*AK("LIMIT_START")*/3'd1;
lim_start_ns = 1'b1;
end
end
/*AL("LIMIT_START")*/3'd1:
sm_ns = /*AK("LIMIT_WAIT")*/3'd2;
/*AL("LIMIT_WAIT")*/3'd2:begin
if (lim_done) begin
lim_start_ns = 1'b0;
sm_ns = /*AK("SCAN")*/3'd3;
reset_scan_ns = 1'b0;
end
end
/*AL("SCAN")*/3'd3:begin
if (scan_done) begin
reset_scan_ns = 1'b1;
sm_ns = /*AK("COMPUTE")*/3'd4;
end
end
/*AL("COMPUTE")*/3'd4:begin
sm_ns = /*AK("PRECHARGE")*/3'd5;
ocd_prech_req_ns = 1'b1;
end
/*AL("PRECHARGE")*/3'd5:begin
if (prech_done) sm_ns = /*AK("DONE")*/3'd6;
end
/*AL("DONE")*/3'd6:begin
byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
byte_ns = {DQS_CNT_WIDTH{1'b0}};
po_rd_wait_ns = 4'd8;
sm_ns = /*AK("STG2_2_ZERO")*/3'd7;
end else begin
sm_ns = /*AK("LIMIT_START")*/3'd1;
lim_start_ns = 1'b1;
end
end
/*AL("STG2_2_ZERO")*/3'd7:
if (~|po_rd_wait_r && po_rdy)
if (|po_counter_read_val[5:0]) ocd_cntlr2stg2_dec_r = 1'b1;
else begin
if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
sm_ns = /*AK("READY")*/3'd0;
oclkdelay_calib_done_ns= 1'b1;
wrlvl_final_ns = 1'b1;
if (complex_oclkdelay_calib_start) begin
complex_oclkdelay_calib_done_ns = 1'b1;
complex_wrlvl_final_ns = 1'b1;
end
end else begin
byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
po_rd_wait_ns = 4'd8;
end
end // else: !if(|po_counter_read_val[5:0])
endcase // case (sm_r)
end // always @ begin
endmodule // mig_7series_v2_3_ddr_phy_ocd_cntlr
// Local Variables:
// verilog-autolabel-prefix: "3'd"
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBN_SYMBOL_V
`define SKY130_FD_SC_HD__DLRBN_SYMBOL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> bool uin(T &a, T b) { if (a > b) { a = b; return true; } return false; } template <class T> bool uax(T &a, T b) { if (a < b) { a = b; return true; } return false; } const int MAXN = 1100000; vector<int> lft[MAXN], rgt[MAXN]; int leftf[MAXN], anyf[MAXN]; int lc[MAXN], rc[MAXN]; char s[10]; struct TNode { int left, right; int L, R; int maxk; TNode(int L = -1, int R = -1) : left(-1), right(-1), L(L), R(R), maxk(-1e9) {} }; const int MAXT = 2100000; TNode t[MAXT]; int tc = 0; int buildTree(int L, int R) { int node = tc++; t[node] = TNode(L, R); if (R - L == 1) return node; int M = (L + R) / 2; t[node].left = buildTree(L, M); t[node].right = buildTree(M, R); return node; } int getMax(int node, int L, int R) { if (max(L, t[node].L) >= min(R, t[node].R)) return -1e9; if (L <= t[node].L && t[node].R <= R) return t[node].maxk; return max(getMax(t[node].left, L, R), getMax(t[node].right, L, R)); } void setMax(int node, int i, int x) { if (i >= t[node].R || i < t[node].L) return; if (i == t[node].L && i + 1 == t[node].R) { t[node].maxk = x; return; } setMax(t[node].left, i, x); setMax(t[node].right, i, x); t[node].maxk = max(t[t[node].left].maxk, t[t[node].right].maxk); } bool buildAns(int l, int r) { if (anyf[l] > r) return false; for (int x : rgt[l]) { if (x <= leftf[l]) return false; } if (leftf[l] == l) { lc[l] = -1; if (r == l) return true; rc[l] = l + 1; return buildAns(l + 1, r); } lc[l] = l + 1; if (!buildAns(lc[l], leftf[l])) return false; if (leftf[l] == r) return true; rc[l] = leftf[l] + 1; return buildAns(rc[l], r); } void print(int v) { if (v == -1) return; print(lc[v]); printf( %d , v + 1); print(rc[v]); } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.precision(10); cout << fixed; int N, C; scanf( %d%d , &N, &C); bool ok = true; int root = buildTree(0, N); for (int i = 0; i < (int)(C); ++i) { int x, y; scanf( %d%d%s , &x, &y, s); --x; --y; ok &= x < y; if (s[0] == L ) lft[x].push_back(y); else rgt[x].push_back(y); } if (!ok) { cout << IMPOSSIBLE n ; return 0; } for (int i = (int)(N)-1; i >= 0; --i) { leftf[i] = anyf[i] = i; for (int x : lft[i]) { uax(leftf[i], getMax(root, i, x + 1)); } for (int x : rgt[i]) { uax(anyf[i], getMax(root, i, x + 1)); } uax(anyf[i], leftf[i]); setMax(root, i, anyf[i]); } for (int i = 0; i < (int)(N); ++i) lc[i] = rc[i] = -1; if (!buildAns(0, N - 1)) { cout << IMPOSSIBLE n ; return 0; } print(0); printf( n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S4S_SYMBOL_V
`define SKY130_FD_SC_HD__DLYMETAL6S4S_SYMBOL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlymetal6s4s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S4S_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long n = 1009; int LG2(int N) { int ans = 0; while (N) { N >>= 1; ans++; } return ans - 1; } int main() { cin.tie(0); cin.sync_with_stdio(0); int n; cin >> n; map<string, int> M; int o = 1; vector<long long> v(n); vector<string> vv(n); int ans = 0; for (int i = 0; i < (n); i++) { string s; cin >> s; ans += s.length(); vv[i] = s; if (M[s]) { v[i] = M[s]; } else { M[s] = o; v[i] = o; o++; } } ans += n - 1; int L = ans; for (int f = 0; f < n; f++) { int len = 0; vector<long long> p; for (int l = f; l < n; l++) { len += vv[l].length(); if (l > f) len++; p.push_back(v[l]); int pL = l - f + 1; int cntP = 0; for (int i = l + 1; i < n; i++) { int o = i + pL - 1; if (o > n) continue; int c = 0; bool b = 1; for (int j = i; j <= o; j++) { if (v[j] == p[c]) { } else { b = 0; break; } c++; } if (b) { cntP++; i = o; } } if (!cntP) continue; int rB = (len - pL) * (cntP + 1); ans = min(ans, L - rB); } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; const int INF = 0x3f3f3f3f; const int mo = 1e9 + 7; inline int ksm(int a, int b) { int ret = 1; for (; b; b >>= 1, a = 1ll * a * a % mo) if (b & 1) ret = 1ll * ret * a % mo; return ret; } inline int read() { char ch = getchar(); int x = 0, f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 3) + (x << 1) + ch - 0 ; ch = getchar(); } return x * f; } int n = 4, m, f[N][21], dep[N]; struct node { int u, v, mx; bool operator<(const node &A) const { return mx < A.mx; } } a; int LCA(int x, int y) { if (dep[x] < dep[y]) swap(x, y); for (int i = 20; i >= 0; i--) if (dep[f[x][i]] >= dep[y]) x = f[x][i]; if (x == y) return x; for (int i = 20; i >= 0; i--) if (f[x][i] != f[y][i]) x = f[x][i], y = f[y][i]; return f[x][0]; } int dist(int x, int y) { int lca = LCA(x, y); return dep[x] + dep[y] - 2 * dep[lca]; } void add(int u) { int x = n + 1, y = n + 2; n += 2; dep[x] = dep[y] = dep[u] + 1; f[x][0] = f[y][0] = u; for (int i = 1; i <= 20; i++) f[x][i] = f[y][i] = f[f[x][i - 1]][i - 1]; int xx = a.u, yy = a.v; node b = (node){xx, x, dist(xx, x)}, c = (node){xx, y, dist(xx, y)}; node d = (node){yy, x, dist(yy, x)}, e = (node){yy, y, dist(yy, y)}; node f = (node){xx, yy, dist(xx, yy)}; if (a < b) a = b; if (a < c) a = c; if (a < d) a = d; if (a < e) a = e; if (a < f) a = f; } signed main() { dep[1] = 1; a.u = 2, a.v = 4, a.mx = 2; dep[2] = dep[3] = dep[4] = 2; f[1][0] = f[2][0] = f[3][0] = f[4][0] = 1; m = read(); for (; m; m--) { int u = read(); add(u); printf( %d n , a.mx); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; map<string, int> m; int groot = 0; string p = ; vector<string> vec; for (int i = 1; i < s.size(); i++) { p.push_back(s[i - 1]); p.push_back(s[i]); m[p]++; groot = max(groot, m[p]); vec.push_back(p); p = ; } for (int i = 0; i < vec.size(); i++) { if (m[vec[i]] == groot) { cout << vec[i] << endl; break; } } return 0; }
|
// (c) NedoPC 2010
//
// doubles video line by replicating it in 3x512b RAM buffer
module vga_double(
input wire clk,
input wire hsync_start,
input wire scanin_start,
input wire [ 5:0] pix_in,
input wire scanout_start,
output reg [ 5:0] pix_out
);
/*
addressing of non-overlapping pages:
pg0 pg1
0xx 1xx
2xx 3xx
4xx 5xx
*/
reg [9:0] ptr_in; // count up to 720
reg [9:0] ptr_out; //
reg pages; // swapping of pages
reg wr_stb;
wire [ 7:0] data_out;
always @(posedge clk) if( hsync_start )
pages <= ~pages;
// write ptr and strobe
always @(posedge clk)
begin
if( scanin_start )
begin
ptr_in[9:8] <= 2'b00;
ptr_in[5:4] <= 2'b11;
end
else
begin
if( ptr_in[9:8]!=2'b11 ) // 768-720=48
begin
wr_stb <= ~wr_stb;
if( wr_stb )
begin
ptr_in <= ptr_in + 10'd1;
end
end
end
end
// read ptr
always @(posedge clk)
begin
if( scanout_start )
begin
ptr_out[9:8] <= 2'b00;
ptr_out[5:4] <= 2'b11;
end
else
begin
if( ptr_out[9:8]!=2'b11 )
begin
ptr_out <= ptr_out + 10'd1;
end
end
end
//read data
always @(posedge clk)
begin
if( ptr_out[9:8]!=2'b11 )
pix_out <= data_out[5:0];
else
pix_out <= 6'd0;
end
mem1536 line_buf( .clk(clk),
.wraddr({ptr_in[9:8], pages, ptr_in[7:0]}),
.wrdata({2'b00,pix_in}),
.wr_stb(wr_stb),
.rdaddr({ptr_out[9:8], (~pages), ptr_out[7:0]}),
.rddata(data_out)
);
endmodule
// 3x512b memory
module mem1536(
input wire clk,
input wire [10:0] wraddr,
input wire [ 7:0] wrdata,
input wire wr_stb,
input wire [10:0] rdaddr,
output reg [ 7:0] rddata
);
reg [7:0] mem [0:1535];
always @(posedge clk)
begin
if( wr_stb )
begin
mem[wraddr] <= wrdata;
end
rddata <= mem[rdaddr];
end
endmodule
|
/*****************************************************************************
-------------------------------------------------------------------------------
-- Entity: mig_interface_model
-- File: mig_interface_model.v
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
--
-- This is a interface model for Xilinx Virtex-7 MIG used on eval board
-- VC707 and KC705.
--
-------------------------------------------------------------------------------
*****************************************************************************/
`timescale 1ps/1ps
module mig_interface_model
(
// user interface signals
input [27:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [511:0] app_wdf_data,
input app_wdf_end,
input [63:0] app_wdf_mask,
input app_wdf_wren,
output wire [511:0] app_rd_data,
output wire app_rd_data_end,
output wire app_rd_data_valid,
output wire app_rdy,
output wire app_wdf_rdy,
output reg ui_clk,
output reg ui_clk_sync_rst,
output reg init_calib_complete,
input sys_rst
);
parameter AddressSize = 28 - 8;
//parameter AddressSize = 10;
//parameter AddressSize = 7;
parameter WordSize = 512;
parameter MEM_SIZE = (1<<AddressSize);
reg app_rd_data_end_r;
reg app_rd_data_valid_r;
reg app_rdy_r;
reg app_wdf_rdy_r;
reg app_en_r;
reg app_wdf_wren_r;
reg app_wdf_end_r;
reg [27:0] app_addr_r;
reg [27:0] app_addr_r1;
reg [27:0] app_addr_r2;
reg [27:0] app_addr_r3;
reg [27:0] app_addr_r4;
reg [511:0] mask;
reg [WordSize-1:0] Mem [0:MEM_SIZE];
integer k;
assign #100 app_rd_data_end = app_rd_data_end_r;
assign #100 app_rdy = app_rdy_r;
assign #100 app_wdf_rdy = app_wdf_rdy_r;
assign app_rd_data_valid = app_rd_data_valid_r;
assign #100 app_rd_data = Mem[app_addr_r >> 3];
// Clear memory
initial
begin
for (k = 0; k < MEM_SIZE ; k = k + 1)
begin
Mem[k] = 512'd0;
end
end
initial
begin
app_rd_data_valid_r = 1'b0;
app_rd_data_end_r = 1'b0;
app_rdy_r = 1'b1;
app_wdf_rdy_r = 1'b1;
init_calib_complete = 1'b0;
ui_clk_sync_rst = 1'b0;
ui_clk = 1'b0;
end
// Generate clocks
always
begin
forever begin
#5000;
ui_clk = ~ui_clk;
end
end
// Release reset and calibration
initial
begin
#10000;
$display("Reset release of simulation time is %d",$time);
@(posedge ui_clk) ui_clk_sync_rst = 1'b1;
#1000;
$display("Calibration release of simulation time is %d",$time);
@(posedge ui_clk) init_calib_complete = 1'b1;
end
// Write Process
always@(posedge app_wdf_wren)
begin
#100;
for (k = 0; k < 512 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
#10000;
if (app_wdf_wren) begin
#100;
for (k = 0; k < 512 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
end
#10000;
if (app_wdf_wren) begin
#100;
for (k = 0; k < 512 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
end
#10000;
if (app_wdf_wren) begin
#100;
for (k = 0; k < 512 ; k = k + 1)
begin
mask[k] = ~ app_wdf_mask[k >> 3];
end
Mem[app_addr >> 3] = (app_wdf_data & mask) | (Mem[app_addr >> 3] & (~ mask) );
end
end
// Read Process
always@(posedge app_en)
begin
#100;
if (MEM_SIZE < app_addr) begin
$display("Warning read/write access outside memory at %d",$time);
end
if (app_cmd == 3'd1) begin
app_addr_r1 = app_addr;
#10000;
app_addr_r2 = app_addr;
#10000;
app_addr_r3 = app_addr;
#10000;
app_addr_r4 = app_addr;
#40000;
app_addr_r = app_addr_r1;
#100;
app_rd_data_valid_r = 1'b1;
#10000;
app_addr_r = app_addr_r2;
#10000;
app_addr_r = app_addr_r3;
#10000;
app_addr_r = app_addr_r4;
#10000;
app_rd_data_valid_r = 1'b0;
#10000;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000003; char in[2010]; int catlen[2010]; long long fac[4010], inv[4010], rf[4010]; int t[2010], tc; int first[2010], stc; long long dp[2010][2010]; inline int solve() { int n = strlen(in); tc = 0; bool isn = 0, ist; for (int i = (0); i < (int)(n); ++i) { ist = 0; if (in[i] <= 9 && in[i] >= 0 ) isn = 1; else { if (isn) { t[tc++] = 0; isn = 0; } if (i == 0 || !(in[i - 1] <= 9 && in[i - 1] >= 0 )) { if (in[i] == * || in[i] == / ) return 0; t[tc++] = 1; } else ist = 1; } } if (isn) t[tc++] = 0; if (t[tc - 1] == 1 || ist) return 0; stc = 0; for (int i = (0); i < (int)(tc); ++i) if (t[i] == 0) first[stc]++; else stc++; if (stc == 0) return catlen[tc]; dp[stc + 1][0] = 1; int ms = 0; for (int i = (int)(stc + 1) - 1; i >= 0; --i) { int r = first[i]; if (i) { ms += r; for (int j = (1); j < (int)(ms + 1); ++j) { for (int k = max(r - j, 0); k <= ms - j; k++) { dp[i][k + 1] += (dp[i + 1][k + j - r] * catlen[j]) % mod; if (dp[i][k + 1] >= mod) dp[i][k + 1] -= mod; } } } else { for (int j = (0); j < (int)(ms + 1); ++j) dp[i][j + r] = dp[i + 1][j]; ms += r; } } int ret = 0; for (int i = (1); i < (int)(tc + 1); ++i) ret = (ret + dp[0][i] * catlen[i]) % mod; return ret; } int main() { inv[1] = 1; for (int i = 2; i <= 4000; i++) inv[i] = (inv[mod % i] * (mod - mod / i)) % mod; fac[0] = rf[0] = 1; for (int i = 1; i <= 4000; i++) { fac[i] = (fac[i - 1] * i) % mod; rf[i] = (rf[i - 1] * inv[i]) % mod; } catlen[1] = 1; for (int i = 1; i <= 2000; i++) catlen[i + 1] = (inv[i + 1] * (((fac[2 * i] * rf[i]) % mod * rf[i]) % mod)) % mod; scanf( %s , in); printf( %d n , solve()); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SDFXTP_FUNCTIONAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e6 + 7; int n; string s; vector<int> p; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> s; n = (int)s.size(); for (int i = 0; i < n; i++) { if (s[i] != s[(i + 1) % n]) { p.push_back(i); } } int ant = -1; int yes = 0; int no = 0; for (int i = 1; i < (int)p.size(); i++) { if (ant == -1 || p[i] != ant + 1) { ant = p[i]; yes++; } } if (p.back() == n - 1 && p[0] == 0) { p.pop_back(); } ant = -1; for (int i = 0; i < (int)p.size(); i++) { if (ant == -1 || p[i] != ant + 1) { ant = p[i]; no++; } } cout << max(yes, no) << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_4_V
`define SKY130_FD_SC_HD__INV_4_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__inv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFXBP_PP_BLACKBOX_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_PP_BLACKBOX_V
|
// Check that the signedness of methods on the built-in enum type is handled
// correctly when calling the method without parenthesis.
module test;
bit failed = 1'b0;
`define check(x) \
if (!(x)) begin \
$display("FAILED(%0d): ", `__LINE__, `"x`"); \
failed = 1'b1; \
end
int unsigned x = 10;
int y = 10;
int z;
enum shortint {
A = -1,
B = -2,
C = -3
} es;
enum bit [15:0] {
X = 65535,
Y = 65534,
Z = 65533
} eu;
initial begin
es = B;
eu = Y;
// These all evaluate as signed
`check($signed(eu.first) < 0)
`check(es.first < 0)
`check($signed(eu.last) < 0)
`check(es.last < 0)
`check($signed(eu.prev) < 0)
`check(es.prev < 0)
`check($signed(eu.next) < 0)
`check(es.next < 0)
// These all evaluate as unsigned
`check(eu.first > 0)
`check({es.first} > 0)
`check($unsigned(es.first) > 0)
`check(es.first > 16'h0)
`check(eu.last > 0)
`check({es.last} > 0)
`check($unsigned(es.last) > 0)
`check(es.last > 16'h0)
`check(eu.prev > 0)
`check({es.prev} > 0)
`check($unsigned(es.prev) > 0)
`check(es.prev > 16'h0)
`check(eu.next > 0)
`check({es.next} > 0)
`check($unsigned(es.next) > 0)
`check(es.next > 16'h0)
// In arithmetic expressions if one operand is unsigned all operands are
// considered unsigned
z = eu.first + x;
`check(z === 65545)
z = eu.first + y;
`check(z === 65545)
z = eu.last + x;
`check(z === 65543)
z = eu.last + y;
`check(z === 65543)
z = eu.prev + x;
`check(z === 65545)
z = eu.prev + y;
`check(z === 65545)
z = eu.next + x;
`check(z === 65543)
z = eu.next + y;
`check(z === 65543)
z = es.first + x;
`check(z === 65545)
z = es.first + y;
`check(z === 9)
z = es.last + x;
`check(z === 65543)
z = es.last + y;
`check(z === 7)
z = es.prev + x;
`check(z === 65545)
z = es.prev + y;
`check(z === 9)
z = es.next + x;
`check(z === 65543)
z = es.next + y;
`check(z === 7)
// For ternary operators if one operand is unsigned the result is unsigend
z = x ? eu.first : x;
`check(z === 65535)
z = x ? eu.first : y;
`check(z === 65535)
z = x ? eu.last : x;
`check(z === 65533)
z = x ? eu.last : y;
`check(z === 65533)
z = x ? eu.prev : x;
`check(z === 65535)
z = x ? eu.prev : y;
`check(z === 65535)
z = x ? eu.next : x;
`check(z === 65533)
z = x ? eu.next : y;
`check(z === 65533)
z = x ? es.first : x;
`check(z === 65535)
z = x ? es.first : y;
`check(z === -1)
z = x ? es.last : x;
`check(z === 65533)
z = x ? es.last : y;
`check(z === -3)
z = x ? es.prev : x;
`check(z === 65535)
z = x ? es.prev : y;
`check(z === -1)
z = x ? es.next : x;
`check(z === 65533)
z = x ? es.next : y;
`check(z === -3)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
module spi_engine_offload (
input ctrl_clk,
input ctrl_cmd_wr_en,
input [15:0] ctrl_cmd_wr_data,
input ctrl_sdo_wr_en,
input [7:0] ctrl_sdo_wr_data,
input ctrl_enable,
output ctrl_enabled,
input ctrl_mem_reset,
input spi_clk,
input spi_resetn,
input trigger,
output cmd_valid,
input cmd_ready,
output [15:0] cmd,
output sdo_data_valid,
input sdo_data_ready,
output [7:0] sdo_data,
input sdi_data_valid,
output sdi_data_ready,
input [7:0] sdi_data,
input sync_valid,
output sync_ready,
input [7:0] sync_data,
output offload_sdi_valid,
input offload_sdi_ready,
output [7:0] offload_sdi_data
);
parameter SPI_CLK_ASYNC = 0;
parameter CMD_MEM_ADDR_WIDTH = 4;
parameter SDO_MEM_ADDR_WIDTH = 4;
reg spi_active = 1'b0;
reg [CMD_MEM_ADDR_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00;
reg [CMD_MEM_ADDR_WIDTH-1:0] spi_cmd_rd_addr = 'h00;
reg [SDO_MEM_ADDR_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00;
reg [SDO_MEM_ADDR_WIDTH-1:0] spi_sdo_rd_addr = 'h00;
reg [15:0] cmd_mem[0:2**CMD_MEM_ADDR_WIDTH-1];
reg [7:0] sdo_mem[0:2**SDO_MEM_ADDR_WIDTH-1];
wire [CMD_MEM_ADDR_WIDTH-1:0] spi_cmd_rd_addr_next;
wire spi_enable;
assign cmd_valid = spi_active;
assign sdo_data_valid = spi_active;
assign sync_ready = 1'b1;
assign offload_sdi_valid = sdi_data_valid;
assign sdi_data_ready = offload_sdi_ready;
assign offload_sdi_data = sdi_data;
assign cmd = cmd_mem[spi_cmd_rd_addr];
assign sdo_data = sdo_mem[spi_sdo_rd_addr];
generate if (SPI_CLK_ASYNC) begin
/*
* The synchronization circuit takes care that there are no glitches on the
* ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is
* asserted, but only deasserted once the signal has been synchronized back from
* the SPI domain. This makes sure that we can't end up in a state where the
* enable signal in the SPI domain is asserted, but neither enable nor enabled
* is asserted in the control domain.
*/
reg ctrl_do_enable = 1'b0;
wire ctrl_is_enabled;
reg spi_enabled = 1'b0;
always @(posedge ctrl_clk) begin
if (ctrl_enable == 1'b1) begin
ctrl_do_enable <= 1'b1;
end else if (ctrl_is_enabled == 1'b1) begin
ctrl_do_enable <= 1'b0;
end
end
assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
always @(posedge spi_clk) begin
spi_enabled <= spi_enable | spi_active;
end
sync_bits # (
.NUM_BITS(1),
.CLK_ASYNC(1)
) i_sync_enable (
.in(ctrl_do_enable),
.out_clk(spi_clk),
.out_resetn(1'b1),
.out(spi_enable)
);
sync_bits # (
.NUM_BITS(1),
.CLK_ASYNC(1)
) i_sync_enabled (
.in(spi_enabled),
.out_clk(ctrl_clk),
.out_resetn(1'b1),
.out(ctrl_is_enabled)
);
end else begin
assign spi_enable = ctrl_enable;
assign ctrl_enabled = spi_enable | spi_active;
end endgenerate
assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
always @(posedge spi_clk) begin
if (spi_resetn == 1'b0) begin
spi_active <= 1'b0;
end else begin
if (spi_active == 1'b0) begin
if (trigger == 1'b1 && spi_enable == 1'b1)
spi_active <= 1'b1;
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
spi_active <= 1'b0;
end
end
end
always @(posedge spi_clk) begin
if (cmd_valid == 1'b0) begin
spi_cmd_rd_addr <= 'h00;
end else if (cmd_ready == 1'b1) begin
spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
end
end
always @(posedge spi_clk) begin
if (spi_active == 1'b0) begin
spi_sdo_rd_addr <= 'h00;
end else if (sdo_data_ready == 1'b1) begin
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
end
end
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1)
ctrl_cmd_wr_addr <= 'h00;
else if (ctrl_cmd_wr_en == 1'b1)
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
end
always @(posedge ctrl_clk) begin
if (ctrl_cmd_wr_en == 1'b1)
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
end
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1)
ctrl_sdo_wr_addr <= 'h00;
else if (ctrl_sdo_wr_en == 1'b1)
ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
end
always @(posedge ctrl_clk) begin
if (ctrl_sdo_wr_en == 1'b1)
sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sat May 27 20:55:50 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_g8_to_rgb888_0_0/system_g8_to_rgb888_0_0_sim_netlist.v
// Design : system_g8_to_rgb888_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_g8_to_rgb888_0_0,g8_to_rgb888,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "g8_to_rgb888,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_g8_to_rgb888_0_0
(g8,
rgb888);
input [7:0]g8;
output [23:0]rgb888;
wire [7:0]g8;
assign rgb888[23:16] = g8;
assign rgb888[15:8] = g8;
assign rgb888[7:0] = g8;
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module tb_sram (
// main clock
input CLOCk_50,
// Switches & keys
input [17:0] SW,
input [3:0] KEY,
output [17:0] LEDR,
// Hex displays (seven segment displays)
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
// SRAM
inout [15:0] SRAM_DQ,
output [19:0] SRAM_ADDR,
output SRAM_CE_N, SRAM_OE_N, SRAM_WE_N, SRAM_UB_N, SRAM_LB_N
);
parameter S_RESET = 4'd0;
parameter S_IDLE = 4'd1;
parameter S_WE_PUSHED = 4'd2;
parameter S_WE_RELEASED = 4'd3;
parameter S_RE_PUSHED = 4'd4;
parameter S_RE_RELEASED = 4'd5;
wire clk, rst_n;
wire user_re, user_we;
reg user_re_reg, user_we_reg;
wire data_r_rdy, busy, overflow, empty;
wire [4:0] ssd_0_data;
wire [4:0] ssd_1_data;
wire [4:0] ssd_2_data;
wire [4:0] ssd_3_data;
wire [4:0] ssd_4_data;
wire [4:0] ssd_5_data;
wire [4:0] ssd_6_data;
wire [4:0] ssd_7_data;
wire [31:0] fifo_data_in;
wire [31:0] fifo_data_out;
reg [31:0] fifo_data_out_r;
wire [3:0] writeAddr;
wire [3:0] readAddr;
wire [3:0] state;
wire [3:0] available;
reg [3:0] current_push_state, next_push_state;
// fifo Data out
assign {ssd_1_data[3:0], ssd_0_data[3:0]} = fifo_data_out[7:0];
assign {ssd_1_data[4], ssd_0_data[4]} = 2'b0;
// fifo Data in
assign fifo_data_in = {24'b0, SW[7:0]};
assign {ssd_7_data[3:0], ssd_6_data[3:0]} = fifo_data_in[7:0];
assign {ssd_7_data[4], ssd_6_data[4]} = 2'b0;
// common
assign clk = CLOCk_50;
assign user_re = !KEY[2];
assign user_we = !KEY[1];
assign rst_n = KEY[0];
assign LEDR[17:4] = 14'b0;
assign LEDR[0] = !rst_n;
assign LEDR[1] = busy;
assign LEDR[2] = overflow;
assign LEDR[3] = empty;
// ssd inactive lines
assign ssd_2_data = {1'b0, writeAddr};
assign ssd_3_data = {1'b0, readAddr};
assign ssd_4_data = {1'b0, state};
assign ssd_5_data = {1'b0, available};
SSD ssd_i_0 (ssd_0_data, HEX0);
SSD ssd_i_1 (ssd_1_data, HEX1);
SSD ssd_i_2 (ssd_2_data, HEX2);
SSD ssd_i_3 (ssd_3_data, HEX3);
SSD ssd_i_4 (ssd_4_data, HEX4);
SSD ssd_i_5 (ssd_5_data, HEX5);
SSD ssd_i_6 (ssd_6_data, HEX6);
SSD ssd_i_7 (ssd_7_data, HEX7);
fifo_SRAM fifo_SRAM_i_0 (
.clk (clk),
.rst_n (rst_n),
// SRAM pins
.Addr (SRAM_ADDR),
.IO (SRAM_DQ),
.CE_n (SRAM_CE_N), // Chip
.OE_n (SRAM_OE_N), // Outpu
.WE_n (SRAM_WE_N), // Write
.LB_n (SRAM_LB_N), // Lower
.UB_n (SRAM_UB_N), // Upper
// user interface
.dataIn (fifo_data_in),
.dataOut (fifo_data_out),
.user_we (user_we_reg),
.user_re (user_re_reg),
.data_r_rdy (data_r_rdy),
.busy (busy),
.overflow (overflow),
.empty (empty),
.debug0 (writeAddr),
.debug1 (readAddr),
.debug2 (state),
.debug3 (available)
);
// Data out register update
always @ (posedge clk) begin
if (!rst_n) begin
fifo_data_out_r = 32'b0;
end
else begin
if (data_r_rdy)
fifo_data_out_r = fifo_data_out;
else
fifo_data_out_r = fifo_data_out_r;
end
end
////////////////////////////////////////////////////////////////
// FSM //
////////////////////////////////////////////////////////////////
// State register
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
current_push_state = S_RESET;
end
else begin
current_push_state = next_push_state;
end
end
// WE reg
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
user_we_reg = 1'b0;
end
else begin
if (current_push_state == S_WE_PUSHED)
user_we_reg = 1'b1;
else
user_we_reg = 1'b0;
end
end
// RE reg
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
user_re_reg = 1'b0;
end
else begin
if (current_push_state == S_RE_PUSHED)
user_re_reg = 1'b1;
else
user_re_reg = 1'b0;
end
end
// FSM Combinationnal in/out
always @ (*) begin
next_push_state = current_push_state;
case(current_push_state)
////////////////////////////////////////////////////////
S_RESET: begin
next_push_state = S_IDLE;
end
////////////////////////////////////////////////////////
S_IDLE: begin
if (user_we)
next_push_state = S_WE_PUSHED;
if (user_re)
next_push_state = S_RE_PUSHED;
end
////////////////////////////////////////////////////////
S_WE_PUSHED: begin
next_push_state = S_WE_RELEASED;
end
////////////////////////////////////////////////////////
S_WE_RELEASED: begin
if (!user_we)
next_push_state = S_IDLE;
end
////////////////////////////////////////////////////////
S_RE_PUSHED: begin
next_push_state = S_RE_RELEASED;
end
////////////////////////////////////////////////////////
S_RE_RELEASED: begin
if (!user_re)
next_push_state = S_IDLE;
end
////////////////////////////////////////////////////////
default: begin
next_push_state = S_IDLE;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long arr[100005]; long long ans = 0; long long temp[100005]; bool is(int m, string s) { set<char> ss; map<char, int> mp; for (int i = 0; i < m; i++) { ss.insert(s[i]); mp[s[i]]++; } if (ss.size() == ans) return true; for (int i = 0; i <= s.length() - m - 1; i++) { mp[s[i]]--; if (mp[s[i]] == 0) ss.erase(s[i]); ss.insert(s[i + m]); mp[s[i + m]]++; if (ss.size() == ans) { return true; } } return false; } int main() { int n; string s; cin >> n >> s; set<char> se; for (char c : s) se.insert(c); ans = se.size(); int l = 0; int r = n + 1; while (r - l > 1) { int m = l + (r - l) / 2; if (!is(m, s)) l = m; else r = m; } cout << r << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_SYMBOL_V
`define SKY130_FD_SC_MS__NAND4B_SYMBOL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
input D ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_SYMBOL_V
|
module single_cycle(input clk,input enable,output LED1,output reg LED2,LED3);
reg [32:0] cnt = 0;
reg number=0;
reg start=0;
reg stop=0;
reg reset=0;
wire debug1,debug2;
single_cycle_top sc(number,reset,debug1,debug2);
always @(negedge enable,posedge stop)begin
if(stop)
start=0;
else begin
if(!enable)
start=1;
else
start=0;
end
end
always @(posedge clk)begin
cnt <= cnt + 1'b1;
end
always @(posedge cnt[4]) begin // normal is 21
if(!start) begin
number=0;
stop=0;
reset=1;
end else begin
reset=0;
number = ~number;
if(debug1&&debug2)
stop=1;
end
end
always @(debug1, debug2,start) begin
if(start) begin
LED2=~debug1;
LED3=~debug2;
end
end
assign LED1 = !number;
endmodule
module single_cycle_tp(input clk,reset,output y,z);
reg [3:0]cnt;
assign y=cnt[2];
assign z=cnt[3];
always@(negedge clk,posedge reset) begin
if(reset)
cnt<=0;
else
cnt<=cnt+1'b1;
end
endmodule
module single_cycle_top(clk,reset,debug1,debug2);
input clk;
input reset;
output reg debug1,debug2;
wire [31:0] instruction,PC;
wire [31:0] DataAdr,WriteData,ReadData;
wire Write_Enable;
memory im(PC,instruction);
datamem dm(DataAdr,WriteData,Write_Enable,ReadData,clk);
ARM proc(clk,reset,instruction,ReadData,DataAdr,WriteData,Write_Enable,PC);
always@(negedge clk,posedge reset) begin
if(reset) begin
debug1=0;
debug2=0;
end else begin
if((WriteData==8'h00000007)&(DataAdr==8'h00000014))
debug1=1;
if((WriteData==8'h00000007)&(DataAdr==8'h0000001A))
debug2=1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int mini(int a, int b) { return a < b ? a : b; } inline int maxi(int a, int b) { return a > b ? a : b; } int main() { int n; scanf( %d , &n); int *a = new int[n]; int najm = 1000000010; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); najm = mini(najm, a[i]); } vector<int> vec; for (int i = 0; i < n; i++) { if (a[i] == najm) { vec.push_back(i); } } int najv = 0; for (int i = 0; i < vec.size() - 1; i++) { najv = maxi(najv, vec[i + 1] - vec[i] - 1); } najv = maxi(najv, n - 1 - vec[vec.size() - 1] + vec[0]); long long res = ((long long)najm) * (long long)n + (long long)najv; cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; using i64 = long long int; using ii = pair<int, int>; using ii64 = pair<i64, i64>; i64 ipow(i64 x, i64 n) { if (n == 0) return 1ll; i64 half = ipow(x, n / 2); half = (half * half) % 1000000007; if (n % 2 == 0) return half; else return (half * x) % 1000000007; } int main() { i64 n, m; scanf( %lld %lld , &n, &m); vector<i64> s1(n); vector<i64> s2(n); for (int i = 0; i < n; i++) scanf( %lld , &s1[i]); for (int i = 0; i < n; i++) scanf( %lld , &s2[i]); vector<i64> ps(n + 1); vector<i64> qs(n + 1); ps[n] = 0; qs[n] = 1; for (int i = n - 1; i >= 0; i--) { qs[i] = qs[i + 1]; if (s1[i] == 0) qs[i] = (qs[i] * m) % 1000000007; if (s2[i] == 0) qs[i] = (qs[i] * m) % 1000000007; } for (int i = n - 1; i >= 0; i--) { if (s1[i] != 0 && s2[i] != 0) { if (s1[i] == s2[i]) ps[i] = ps[i + 1]; else if (s1[i] > s2[i]) ps[i] = qs[i + 1]; else ps[i] = 0; } else if (s1[i] == 0 && s2[i] != 0) { ps[i] = ps[i + 1]; ps[i] += (qs[i + 1] * (m - s2[i])) % 1000000007; ps[i] %= 1000000007; } else if (s1[i] != 0 && s2[i] == 0) { ps[i] = ps[i + 1]; ps[i] += (qs[i + 1] * (s1[i] - 1)) % 1000000007; ps[i] %= 1000000007; } else if (s1[i] == 0 && s2[i] == 0) { ps[i] = (m * ps[i + 1]) % 1000000007; i64 arg = (m * (m - 1) / 2) % 1000000007; ps[i] += (qs[i + 1] * arg) % 1000000007; ps[i] %= 1000000007; } } printf( %lld n , (ps[0] * ipow(qs[0], 1000000007 - 2)) % 1000000007); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VERILATOR
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function integer mon_check();
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
input clk;
reg onebit /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */;
reg [31:0] count /*verilator public_flat_rd */;
reg [31:0] half_count /*verilator public_flat_rd */;
reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */;
reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */;
reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */;
reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */;
reg [511:0] text /*verilator public_flat_rw @(posedge clk) */;
integer status;
sub sub();
// Test loop
initial begin
onebit = 1'b0;
text_byte = "B";
text_half = "Hf";
text_word = "Word";
text_long = "Long64b";
text = "Verilog Test module";
`ifdef VERILATOR
status = $c32("mon_check()");
`else
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
if (onebit != 1'b1) $stop;
if (quads[2] != 62'h12819213_abd31a1c) $stop;
if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
if (text_byte != "A") $stop;
if (text_half != "T2") $stop;
if (text_word != "Tree") $stop;
if (text_long != "44Four44") $stop;
if (text != "lorem ipsum") $stop;
end
always @(posedge clk) begin
count <= count + 2;
if (count[1])
half_count <= half_count + 2;
if (count == 1000) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
genvar i;
generate
for (i=1;i<=128;i++) begin : arr
arr #(.LENGTH(i)) arr();
end endgenerate
endmodule
module sub;
reg subsig1 /*verilator public_flat_rd*/;
reg subsig2 /*verilator public_flat_rd*/;
endmodule
module arr;
parameter LENGTH = 1;
reg [LENGTH-1:0] sig /*verilator public_flat_rw*/;
reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/;
reg check /*verilator public_flat_rw*/;
reg verbose /*verilator public_flat_rw*/;
always @(posedge check) begin
if (verbose) $display("%m : %x %x", sig, rfr);
if (check && sig != rfr) $stop;
check <= 0;
end
endmodule : arr
|
// Put your file header here
//
`ifndef TESTSIZE
`define TESTSIZE 78
`endif
module stimulus;
reg [9:0] test_vector [`TESTSIZE-1:0];
parameter period = 20;
parameter delay = 2;
// declare the signals here
reg clk, rst_n, push, pop;
reg [15:0] datain;
wire empty, almost_empty, full, almost_full, error;
wire [15:0] dataout;
integer i;
fifo fifo1 (
clk,
rst_n,
push,
pop,
datain,
empty,
almost_empty,
full,
almost_full,
error,
dataout
);
always #(period/2) clk = ~clk;
initial begin
`ifdef NETLIST
$sdf_annotate("fifo_my_64x16_syn.sdf", fifo1);
$fsdbDumpfile("fifo_my_64x16_syn.fsdb");
`else
$fsdbDumpfile("fifo_my_64x16.fsdb");
`endif
$fsdbDumpvars;
end
initial begin
$readmemb("pattern1.dat", test_vector);
clk = 1;
rst_n = 1;
idle;
#(period);
#(delay) rst_n = 0;
#(period*4) rst_n = 1;
// #(period/2*5+delay) rst_n = 1;
// #(period/2-delay);
#(period*2);
for (i = 0; i < `TESTSIZE; i = i + 1) begin
case ({test_vector[i][9],test_vector[i][8]})
2'b00: begin
#(period) pushing({test_vector[i][7:0]});
end
2'b01: begin
#(period) popping;
end
2'b10: begin
#(period) idle;
end
2'b11: begin
#(period) invalid;
end
endcase
end
#(period) idle;
#(period*4);
$finish;
end
// tasks
task idle;
begin
push = 0;
pop = 0;
datain = 16'b0;
end
endtask
task pushing;
input [15:0] data;
begin
push = 1;
pop = 0;
datain = data;
end
endtask
task popping;
begin
push = 0;
pop = 1;
end
endtask
task invalid;
begin
push = 1;
pop = 1;
end
endtask
endmodule
|
#include <bits/stdc++.h> inline long long read() { long long x = 0; char ch = getchar(), w = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * w; } void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } inline void writeln(long long x) { write(x); puts( ); } using namespace std; const int N = 3e5 + 666; long long a[N], n; const long long mo = 998244353; long long ksm(long long x, long long y) { long long res = 1; for (; y; y >>= 1, x = x * x % mo) if (y & 1) res = res * x % mo; return res; } int main() { n = read(); long long inv = ksm(100, mo - 2); for (int i = 1; i <= n; ++i) a[i] = read() * inv % mo; long long e1 = 0, s = 1; for (int i = 1; i <= n; ++i) { e1 += s; s *= a[i] % mo; s %= mo; e1 %= mo; } e1 = e1 * ksm(s, mo - 2) % mo; long long ans = 0; for (int i = n; i >= 1; --i) { ans = ans * a[i] % mo + (1 - a[i] + mo) * e1 % mo; ans += 1; ans %= mo; } writeln(ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int r, c, n, k, x, y; int flag[101][101]; int main() { cin >> r >> c >> n >> k; for (int i = 0; i < n; i++) { cin >> x >> y; flag[x][y] = 1; } int cnt = 0; for (int i = 1; i <= r; i++) { for (int i1 = 1; i1 <= c; i1++) { for (int i2 = 1; i2 <= r; i2++) { for (int i3 = 1; i3 <= c; i3++) { int sum = 0; for (int i5 = i; i5 <= i2; i5++) { for (int i6 = i1; i6 <= i3; i6++) { if (flag[i5][i6] == 1) sum++; } } if (sum >= k) cnt++; } } } } cout << cnt; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<set<int> > > setgrid; vector<string> grid; int k; int ro[4] = {1, -1, 0, 0}; int co[4] = {0, 0, -1, 1}; struct s { s() : r(-1), c(-1), set(-1), path( ), let( A ), d(0) {} s(int nr, int nc, unsigned int nset, string npath, char nlet, int nd) : r(nr), c(nc), set(nset), path(npath), let(nlet), d(nd) {} int r, c, d; unsigned int set; string path; char let; }; bool operator<(const s &lhs, const s &rhs) { if (lhs.d == rhs.d) if (lhs.path == rhs.path) return lhs.let >= rhs.let; else return lhs.path >= rhs.path; else return lhs.d >= rhs.d; } bool visited(int r, int c, unsigned int set) { unsigned int subset = set; do { subset = (subset - 1) & set; if (setgrid[r][c].find(subset) != setgrid[r][c].end()) { return true; } } while (subset != set); return false; } int main(void) { s qf; int rs, cs, nr, nc; unsigned int nset, one = 0x00000001; priority_queue<s> q; vector<s> pv, tv; cin >> rs >> cs >> k; grid.resize(rs); for (int i = 0; i < rs; i++) cin >> grid[i]; setgrid.resize(rs); for (int i = 0; i < rs; i++) setgrid[i].resize(cs); int sr, sc; for (int i = 0; i < rs; i++) for (int j = 0; j < cs; j++) if (grid[i][j] == S ) { sr = i; sc = j; break; } q.push(s(sr, sc, 0, , a , 0)); setgrid[sr][sc].insert(0); while (!q.empty()) { pv.clear(); qf = q.top(); for (int i = 0; i < 4; i++) { nr = qf.r + ro[i]; nc = qf.c + co[i]; if (nr < 0 || nr >= rs || nc < 0 || nc >= cs) continue; if (grid[nr][nc] == T ) goto success; nset = qf.set | (one << int(grid[nr][nc] - a )); if ((__builtin_popcount(nset) > k) || visited(nr, nc, nset)) continue; pv.push_back( s(nr, nc, nset, qf.path + grid[nr][nc], grid[nr][nc], qf.d + 1)); setgrid[nr][nc].insert(nset); } sort(pv.begin(), pv.end()); for (int i = 0; i < pv.size(); i++) q.push(pv[i]); q.pop(); } cout << -1 << n ; return 0; success: if (qf.path != ) cout << qf.path << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; std::vector<long long> x0, x1, y0, y1; long long a[n][4]; for (long long int i = 0; i < n; i++) { cin >> a[i][0] >> a[i][1] >> a[i][2] >> a[i][3]; x0.push_back(a[i][0]); x1.push_back(a[i][2] + 1); y0.push_back(a[i][1]); y1.push_back(a[i][3] + 1); } sort((x0).begin(), (x0).end()); sort((x1).begin(), (x1).end()); sort((y0).begin(), (y0).end()); sort((y1).begin(), (y1).end()); long long lx = x0[n - 1]; long long ly = y0[n - 1]; long long ux = x1[0]; long long uy = y1[0]; for (long long int i = 0; i < n; i++) { long long xi = a[i][0]; long long xf = a[i][2] + 1; long long yi = a[i][1]; long long yf = a[i][3] + 1; long long x00 = lx; long long x11 = ux; long long y00 = ly; long long y11 = uy; if (xi == lx) { x00 = x0[n - 2]; } if (xf == ux) { x11 = x1[1]; } if (yi == ly) { y00 = y0[n - 2]; } if (yf == uy) { y11 = y1[1]; } if (x00 < x11 && y00 < y11) { cout << x00 << << y00; return 0; } } }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e+18; int main() { cin.tie(0); ios::sync_with_stdio(0); int n, c = 0; cin >> n; while (n != 0) { string str = to_string(n); int maxi = 0; for (int i = 0; i < str.size(); i++) { if ((str[i] - 0 ) > maxi) { maxi = str[i] - 0 ; } } n -= maxi; c++; } cout << c << n ; }
|
`timescale 1ns/10ps
`include "demux2to4.v"
module spdutb;
reg in0, in1, in2, in3, d0, d1;
wire out;
demux demux1 (in0, in1, in2, in3, d0, d1, out);
initial
begin
in0=1'b0; in1=1'b1; in2=1'b1; in3=1'b1;
d0=1'b0; d1=1'b0;
#10;
d0=1'b1; d1=1'b0;
#10;
d0=1'b0; d1=1'b1;
#10;
d0=1'b1; d1=1'b1;
#10;
in0=1'b1; in1=1'b0; in2=1'b1; in3=1'b1;
d0=1'b0; d1=1'b0;
#10;
d0=1'b1; d1=1'b0;
#10;
d0=1'b0; d1=1'b1;
#10;
d0=1'b1; d1=1'b1;
#10;
in0=1'b1; in1=1'b1; in2=1'b0; in3=1'b1;
d0=1'b0; d1=1'b0;
#10;
d0=1'b1; d1=1'b0;
#10;
d0=1'b0; d1=1'b1;
#10;
d0=1'b1; d1=1'b1;
#10;
in0=1'b1; in1=1'b1; in2=1'b1; in3=1'b0;
d0=1'b0; d1=1'b0;
#10;
d0=1'b1; d1=1'b0;
#10;
d0=1'b0; d1=1'b1;
#10;
d0=1'b1; d1=1'b1;
#10;
end
initial
begin
$shm_open("demux2to4.shm");
$shm_probe("AC");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int x, y, z; } a[10]; int flag; long long v[5]; long long dist(int i, int j) { long long x = a[i].x - a[j].x; long long y = a[i].y - a[j].y; long long z = a[i].z - a[j].z; return x * x + y * y + z * z; } int ok() { int cnt = 0; for (int i = 1; i < 8; i++) for (int j = 0; j < i; j++) { long long w = dist(i, j); if (!cnt) v[++cnt] = w; else { int k = 1; while (k <= cnt && v[k] != w) k++; if (k > cnt && cnt == 3) return 0; if (k > cnt) v[++cnt] = w; } } if (cnt == 3) return 1; return 0; } void dfs(int p) { if (flag) return; if (p == 8) { if (ok()) flag = 1; return; } node tmp = a[p]; dfs(p + 1); if (!flag) { a[p].y = tmp.z; a[p].z = tmp.y; dfs(p + 1); } if (!flag) { a[p].x = tmp.y; a[p].y = tmp.x; a[p].z = tmp.z; dfs(p + 1); } if (!flag) { a[p].x = tmp.y; a[p].y = tmp.z; a[p].z = tmp.x; dfs(p + 1); } if (!flag) { a[p].x = tmp.z; a[p].y = tmp.x; a[p].z = tmp.y; dfs(p + 1); } if (!flag) { a[p].x = tmp.z; a[p].y = tmp.y; a[p].z = tmp.x; dfs(p + 1); } } int main() { for (int i = 0; i < 8; i++) cin >> a[i].x >> a[i].y >> a[i].z; dfs(0); if (!flag) puts( NO ); else { puts( YES ); for (int i = 0; i < 8; i++) printf( %d %d %d n , a[i].x, a[i].y, a[i].z); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, q; cin >> n >> m >> q; vector<vector<int> > arr(n); for (int i = 0; i < n; i++) { arr[i].resize(m); } vector<pair<int, int> > did; for (int i = 0; i < q; i++) { int t; cin >> t; if (t == 1) { int x, c; cin >> x; x--; c = arr[x][0]; for (int j = 0; j < m - 1; j++) { arr[x][j] = arr[x][j + 1]; } arr[x][m - 1] = c; did.push_back({1, x}); } if (t == 2) { int x, c; cin >> x; x--; c = arr[0][x]; for (int j = 0; j < n - 1; j++) { arr[j][x] = arr[j + 1][x]; } arr[n - 1][x] = c; did.push_back({2, x}); } if (t == 3) { int x, y, c; cin >> x >> y >> c; arr[x - 1][y - 1] = c; } } for (int i = did.size() - 1; i >= 0; i--) { int x = did[i].second; if (did[i].first == 1) { int c = arr[x][m - 1]; for (int j = m - 1; j > 0; j--) { arr[x][j] = arr[x][j - 1]; } arr[x][0] = c; } else { int c = arr[n - 1][x]; for (int j = n - 1; j > 0; j--) { arr[j][x] = arr[j - 1][x]; } arr[0][x] = c; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << arr[i][j] << ; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[1234567], ans[1234567]; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; int in = 0; for (int i = 0; i < n; i++) if (!a[i]) { in = i; break; } for (int i = 0; i <= in; i++) ans[i] = in - i; for (int i = in + 1; i < n; i++) { if (!a[i]) in = i; ans[i] = abs(i - in); } for (int i = n - 1; i >= 0; i--) if (!a[i]) { in = i; break; } for (int i = n - 1; i >= 0; i--) { if (!a[i]) in = i; ans[i] = min(ans[i], abs(i - in)); } for (int i = 0; i < n; i++) cout << ans[i] << ; }
|
/**
* @module controller
* @author sabertazimi
* @email
* @brief control signals generator
* @input op op code
* @input funct functy code
* @output aluop,
* @output alusrc 1 => imm16, 0 => rt
* @output alusham 1 => sham, 0=> rt
* @output regdst 1 => rd, 0 => rt
* @output regwe 1 => enable, 0 => disable
* @output extop 1 => signed, 0 => unsigned
* @output ramtoreg 1 => ram to regfile, 0 => alu to regfile
* @output ramwe 1 => enable, 0 => disable
* @output beq 1 => current instruction is beq
* @output bne 1 => current instruction is bne
* @output bgtz 1 => current instruction is bgtz
* @output j 1 => current instruction is j
* @output jal 1 => current instruction is jal
* @output jr 1 => current instruction is jr
* @output syscall 1 => current instruction is syscall
* @output writetolo 1 => lo register write enable, 0 => lo register write disable
* @output lotoreg 1 => lo register to regfile, 0 => ram/alu to regfile
* @output rambyte 1 => load byte from ram, 0 => load word from ram
*/
module controller
(
input [5:0] op,
input [5:0] funct,
output [3:0] aluop,
output alusrc,
output alusham,
output regdst,
output regwe,
output extop,
output ramtoreg,
output ramwe,
output beq,
output bne,
output bgtz,
output j,
output jal,
output jr,
output syscall,
output writetolo,
output lotoreg,
output rambyte
);
wire add, addi, addiu, addu;
wire s_and, andi, sll, sra, srl;
wire sub, s_or, ori, s_nor;
wire lw, sw;
wire slt, slti, sltu;
wire divu, mflo;
wire lb;
instruction_typer instruction_typer (
.op(op),
.funct(funct),
.add(add),
.addi(addi),
.addiu(addiu),
.addu(addu),
.s_and(s_and),
.andi(andi),
.sll(sll),
.sra(sra),
.srl(srl),
.sub(sub),
.s_or(s_or),
.ori(ori),
.s_nor(s_nor),
.lw(lw),
.sw(sw),
.beq(beq),
.bne(bne),
.slt(slt),
.slti(slti),
.sltu(sltu),
.j(j),
.jal(jal),
.jr(jr),
.syscall(syscall),
.divu(divu),
.mflo(mflo),
.lb(lb),
.bgtz(bgtz)
);
assign aluop[0] = add || addi || addiu || addu || s_and || andi
|| sra || lw || sw || slt || slti || jal || lb || bgtz;
assign aluop[1] = s_and || andi || srl || sub || s_nor || slt || slti || bgtz;
assign aluop[2] = add || addi || addiu || addu || s_and || andi
|| sub || lw || sw || sltu || jal || divu || lb;
assign aluop[3] = s_or || ori || s_nor || slt || slti || sltu || bgtz;
assign alusrc = addi || addiu || andi || ori || lw || sw || slti || lb;
assign alusham = sll || sra || srl;
assign regdst = add || addu || s_and || sll || sra || srl
|| sub || s_or || s_nor || slt || sltu || mflo;
assign regwe = add || addi || addiu || addu || s_and || andi
|| sll || sra || srl || sub || s_or || ori || s_nor || lw
|| slt || slti || sltu || jal || mflo || lb;
assign extop = addi || addiu || lw || sw || slti || lb;
assign ramtoreg = lw || lb;
assign ramwe = sw;
assign writetolo = divu;
assign lotoreg = mflo;
assign rambyte = lb;
endmodule // controller
|
#include <bits/stdc++.h> int main(void) { int a, b, x, y; scanf( %d %d , &a, &b); x = (a > b) ? a : b; y = (a < b) ? a : b; printf( %d %d n , y, ((x - y) / 2)); return 0; }
|
// This tests SystemVerilog casting support
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
// Extended by Maciej Suminski
// Copied and modified by Martin Whitaker
module test();
typedef logic signed [7:0] reg08;
typedef logic signed [15:0] reg16;
typedef logic signed [31:0] reg32;
typedef logic signed [63:0] reg64;
// variables used in casting
reg08 var_08;
reg16 var_16;
reg32 var_32;
reg64 var_64;
real var_real;
// error counter
bit err = 0;
initial begin
var_08 = reg08'(4'sh5); if (var_08 !== 8'sh05) begin $display("FAILED -- var_08 = 'h%0h != 8'h05", var_08); err=1; end
var_16 = reg16'(var_08); if (var_16 !== 16'sh05) begin $display("FAILED -- var_16 = 'h%0h != 16'h05", var_16); err=1; end
var_32 = reg32'(var_16); if (var_32 !== 32'sh05) begin $display("FAILED -- var_32 = 'h%0h != 32'h05", var_32); err=1; end
var_64 = reg64'(var_32); if (var_64 !== 64'sh05) begin $display("FAILED -- var_64 = 'h%0h != 64'h05", var_64); err=1; end
var_real = 13.4; var_08 = reg08'(var_real); if (var_08 !== 13) begin $display("FAILED -- var_08 = %d != 13", var_08); err=1; end
var_real = 14.5; var_16 = reg16'(var_real); if (var_16 !== 15) begin $display("FAILED -- var_16 = %d != 15", var_16); err=1; end
var_real = 15.6; var_32 = reg32'(var_real); if (var_32 !== 16) begin $display("FAILED -- var_32 = %d != 16", var_32); err=1; end
var_real = -15.6; var_64 = reg64'(var_real); if (var_64 !== -16) begin $display("FAILED -- var_64 = %d != -16", var_64); err=1; end
var_08 = reg08'(4'hf); if (var_08 !== 8'sh0f) begin $display("FAILED -- var_08 = 'h%0h != 8'h0f", var_08); err=1; end
var_08 = reg08'(4'shf); if (var_08 !== 8'shff) begin $display("FAILED -- var_08 = 'h%0h != 8'hff", var_08); err=1; end
var_16 = reg08'(16'h0f0f); if (var_16 !== 16'sh0f) begin $display("FAILED -- var_16 = 'h%0h != 16'h0f", var_16); err=1; end
var_16 = reg08'(4'shf) + 'd0; if (var_16 !== 16'shff) begin $display("FAILED -- var_16 = 'h%0h != 16'hff", var_16); err=1; end
if (!err) $display("PASSED");
end
endmodule // test
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4_BLACKBOX_V
`define SKY130_FD_SC_LS__OR4_BLACKBOX_V
/**
* or4: 4-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int mark[1 << 22]; int is[1 << 22]; int a[1 << 22]; int n, m; int tot; void dfs(int x) { if (mark[x]) return; mark[x] = 1; if (is[x]) dfs(tot ^ x); for (int j = 0; j < n; j++) { if (x >> j & 1) { dfs(x ^ (1 << j)); } } } signed main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d , &a[i]); is[a[i]] = 1; } tot = (1 << n) - 1; int ans = 0; for (int i = 1; i <= m; i++) { if (mark[a[i]]) continue; mark[a[i]] = 1; ans++; dfs(tot ^ a[i]); } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 50; int n, cnt; pair<int, int> poi[maxn], A[maxn]; void solve(int l, int r) { if (l > r) return; int mid = (l + r) >> 1; for (int i = l; i <= r; i++) poi[++cnt] = (pair<int, int>){A[mid].first, A[i].second}; solve(l, mid - 1); solve(mid + 1, r); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d%d , &A[i].first, &A[i].second); sort(A + 1, A + 1 + n); solve(1, n); sort(poi + 1, poi + 1 + cnt); cnt = unique(poi + 1, poi + 1 + cnt) - poi - 1; printf( %d n , cnt); for (int i = 1; i <= cnt; i++) printf( %d %d n , poi[i].first, poi[i].second); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 103; using pi = pair<int, int>; inline int rd() { int x = 0, f = 1, c; while (!isdigit(c = getchar())) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; return f * x; } int n, m, k; char p[N][N]; inline void solve() { n = rd(), m = rd(), k = rd(); int cntr = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> p[i][j], cntr += p[i][j] == R ; vector<int> sz; for (int i = 1; i <= cntr - cntr / k * k; i++) sz.push_back(cntr / k + 1); while (sz.size() < k) sz.push_back(cntr / k); vector<char> ch; for (int i = 0; i < 26; i++) ch.push_back( A + i), ch.push_back( a + i); for (char i = 0 ; i <= 9 ; i++) ch.push_back(i); for (int r = 1, cr = 0; r <= n; r++) { if (r & 1) for (int c = 1; c <= m; c++) { if (p[r][c] == R ) cr++; p[r][c] = ch.back(); if (cr == sz.back()) { sz.pop_back(); cr = 0; if (sz.size()) ch.pop_back(); } } else for (int c = m; c; c--) { if (p[r][c] == R ) cr++; p[r][c] = ch.back(); if (cr == sz.back()) { sz.pop_back(); cr = 0; if (sz.size()) ch.pop_back(); } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) cout << p[i][j]; cout << endl; } } int main() { for (int T = rd(); T--; solve()) ; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int N = 2e5 + 10; char s[3][N]; int main() { int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= 2; i++) for (int j = 1; j <= n; j++) { cin >> s[i][j]; if (s[i][j] == 1 || s[i][j] == 2 ) s[i][j] = 1 ; else s[i][j] = 2 ; } int flag = 0, x = 1, y = 1; for (int i = 1; i <= n; i++) { if (s[y][i] == 1 ) { x++; } else if (s[y][i] == 2 ) { if (y == 1 && s[y + 1][i] == 2 ) { y++; x++; } else if (y == 2 && s[y - 1][i] == 2 ) { y--; x++; } else { flag = 1; break; } } } if (flag) cout << NO << endl; else if (x == n + 1 && y == 2) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; double ax, ay, bx, by, tx, ty, x, y; char s[100100]; double len(double x1, double y1, double x2, double y2) { return sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)); } int main() { ios_base::sync_with_stdio(false); cin >> ax >> ay >> bx >> by >> tx >> ty; cin >> n; vector<pair<double, int> > v1, v2; double total = 0; for (int i = 0; i < n; i++) { cin >> x >> y; v1.push_back(make_pair(len(ax, ay, x, y) - len(tx, ty, x, y), i)); v2.push_back(make_pair(len(bx, by, x, y) - len(tx, ty, x, y), i)); total += 2 * len(tx, ty, x, y); } sort(v1.begin(), v1.end()); sort(v2.begin(), v2.end()); double res = total; double case1 = total + v1[0].first; double case2 = total + v2[0].first; res = min(case1, case2); if (v1[0].second != v2[0].second) { double case3 = total + v1[0].first + v2[0].first; res = min(res, case3); } else if (n > 1) { double case4 = total + v1[0].first + v2[1].first; res = min(res, case4); double case5 = total + v1[1].first + v2[0].first; res = min(res, case5); } printf( %.10lf , res); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKMUX2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__CLKMUX2_BEHAVIORAL_V
/**
* clkmux2: Clock mux.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hdll__clkmux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKMUX2_BEHAVIORAL_V
|
//Verilint 182 off // WARNING: Illegal statement for synthesis: $realtobits (in1)
//Verilint 311 off // WARNING: Converting real to unsigned: $realtobits (in1)
//Verilint 20 off // WARNING: Assign statement may not be synthesizable: assign out7[i] = ...;
//Verilint 599 off // WARNING: This construct is not supported by Synopsys
//Verilint 433 off // WARNING: More than one top level module
//Verilint 71 off // WARNING: Case statement without default clause
module testmodule (/*AUTOARG*/
// Outputs
out1, out2, out3, out4, out5, out7, out8, outb2, outb3, outb4, outb6, outb7, outb8, outb9,
outb10, outw1, outw2, outw3,
// Inputs
in1, in2, in3, in4, in5
);
function [2:0] ffs;
input [2:0] in;
ffs = in & 3'b010;
endfunction
task show;
input [2:0] in;
begin
$display ("Hi %x", in);
end
endtask
input [2:0] in1,in2,in3,in4,in5;
output [2:0] out1, out2,out3,out4,out5,out7,out8;
output outb2,outb3,outb4,outb6,outb7,outb8,outb9,outb10;
output [7:0] outw1,outw2,outw3;
reg [2:0] memarry [0:2];
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [2:0] out1;
reg [2:0] out2;
reg [2:0] out3;
reg [2:0] out4;
reg [2:0] out5;
reg [2:0] out8;
reg outb2;
reg outb3;
reg outb4;
reg outb6;
reg outb7;
reg [7:0] outw1;
reg [7:0] outw2;
reg [7:0] outw3;
// End of automatics
wire outb8=1'b1, outb9=|{in1[0],in2[0]}, outb10=1'b0;
always @(/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
:ignore_label
out1 = $realtobits(in1);
out2 = ffs(in1 | (in2) );
out3 = ffs /*check*/ (in2);
$display ("chk ", in1);
show (in4);
if (|in3) out4=1; else out4=0;
end
always @ (/*AUTOSENSE*/in1 or in2 or in3 or in5) begin
casex ({in5[1:0], (3'b010==in2)})
3'bx_1_0: out5=3'b000;
3'bx_1_1: out5=3'b010;
3'bx_0_x: out5=3'b100;
endcase
casex ({in3[in1]})
1'bx: out5=3'b000;
endcase
end
/*AUTO_CONSTANT (`temp) */
`define temp 3'b010
always @(/*AUTOSENSE*/in3) begin
outb6 = (in3 == `temp);
end
integer i;
reg [2:0] out7;
always @ (/*AUTOSENSE*/in1) begin
for (i=0; i<3; i=i+1) begin
assign out7[i] = ~in1[i];
end
end
always @ (/*AUTOSENSE*/in1 or in2 or in3) begin
{outw1 [ffs(in1)], outw2 [ffs(in2)]} = 2'b10;
{outw3[(|in1)?in2:in3], outb2} = 2'b10;
end
initial memarry[0] = in2;
always @ (/*AUTOSENSE*/ /*memory or*/ in1) begin
$display (memarry[in1]);
end
always @(/*AUTOSENSE*/in1 or in2)
casex(in1[1:0]) // synopsys full_case parallel_case
2'b01 : out8 = 3'b001;
2'b10 : out8 = 3'b010;
default
out8 = in2;
endcase
parameter READ = 3'b111,
//WRITE = 3'b111,
CFG = 3'b010;
//supply1 one;
always @(/*AUTOSENSE*/in1 or in2) begin
outb7 = (in1==READ) || (in2==CFG);
end
always @(/*AUTOSENSE*/in1) begin
if (|in1) $display("We're at %t\n",$time);
end // case: default
`define shift_instr 5'b01011
always @(/*AUTOSENSE*/in1 or in2 or in3 or in4 or in5 or outw1)
/*AUTO_CONSTANT(`shift_instr)*/
begin: label_no_sense
casex (outw1) // synopsys full_case parallel_case
{`shift_instr,3'bxxx}:
outb3 = in3[0];
8'b00001x10: outb3 = in4[0];
8'b00110011:
if (in5[0])
outb3 = in1[0];
else
outb3 = in2[1];
default
outb3 = in4[0];
endcase
end
parameter WIDLE = 0; // No Manual Write Burst
always @ (/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
case(1'b1)
in2[WIDLE]:
outb4 = in1[0];
in3[in4]:
outb4 = in1[0];
default:
outb4 = 1'bx;
endcase
end
endmodule
module darren_jones_2 (/*AUTOARG*/
// Outputs
next_WSTATE,
// Inputs
WSTATE
);
input [1:0] WSTATE;
output [1:0] next_WSTATE;
reg [1:0] next_WSTATE;
parameter
WIDLE = 0, // No Manual Write Burst
WCB0 = 1; // 1st of the 4 Manual Write Burst
always @ (/*AUTOSENSE*/WSTATE) begin
next_WSTATE = 2'b0;
case (1'b1)
WSTATE[WIDLE]:
next_WSTATE[1'b0] = 1'b1;
WSTATE[WCB0]:
next_WSTATE[WCB0] = 1'b1;
endcase
end
endmodule
module darren_jones_3 (/*AUTOARG*/
// Outputs
var1,
// Inputs
state
);
input [2:1] state;
output var1;
reg var1;
parameter
IDLE = 1,
CAS1 = 2;
always @(/*AUTOSENSE*/state) begin
case (1'b1)
state[IDLE] : begin
var1 = 1'b1;
end
state[CAS1] : begin
var1 = 1'b1;
end
default : begin
var1 = 1'b1;
end
endcase
end
always @(/*AUTOSENSE*/add or lo or mc_32pff or mc_losel or slo or var1) begin
case(mc_losel)
6'b000001: lo_mux = mc_32pff ? {add[39:0],lo[31:8]} :
{add[7:0],lo[63:8]};
6'b010000: lo_mux = lo;
6'b100000: lo_mux = var1 ? IDLE : slo;
endcase
end // always @ (...
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 17:58:33 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode synth_stub
// /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul16_16/mul16_16_stub.v
// Design : mul16_16
// Purpose : Stub declaration of top-level module interface
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
module mul16_16(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[15:0],B[15:0],P[15:0]" */;
input CLK;
input [15:0]A;
input [15:0]B;
output [15:0]P;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int LIM = 3e5 + 7; int T[LIM][10], n, m, ans1, ans2; bool spr(int x) { vector<int> V[1 << m]; for (int i = 0; i < (n); ++i) { int l = 0; for (int j = 0; j < (m); ++j) { if (T[i][j] >= x) l += 1 << j; } V[l].push_back(i); } for (int i = 0; i < (1 << m); ++i) { if (!V[i].size()) continue; for (int j = 0; j < (1 << m); ++j) { if (!V[j].size()) continue; if ((i | j) == (1 << m) - 1) { ans1 = V[i][0]; ans2 = V[j][0]; return true; } } } return false; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 0; i < (n); ++i) for (int j = 0; j < (m); ++j) cin >> T[i][j]; int p = 0, k = 1000000000; while (p < k) { int sr = (p + k) / 2; if (spr(sr)) p = sr + 1; else k = sr - 1; } spr(p); cout << ans1 + 1 << << ans2 + 1 << n ; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the tx_engine and buffers the input
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_128 #(
parameter C_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
input TXN_DONE_ACK, // Write transaction actual transfer length read
input [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather data
input SG_DATA_EMPTY, // Scatter gather buffer empty
output SG_DATA_REN, // Scatter gather data read enable
output SG_RST, // Scatter gather reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire wGateRen;
wire wGateEmpty;
wire [C_DATA_WIDTH:0] wGateData;
wire wBufWen;
wire [C_FIFO_DEPTH_WIDTH-1:0] wBufCount;
wire [C_DATA_WIDTH-1:0] wBufData;
wire wTxn;
wire wTxnAck;
wire wTxnLast;
wire [31:0] wTxnLen;
wire [30:0] wTxnOff;
wire [31:0] wTxnWordsRecvd;
wire wTxnDone;
wire wTxnErr;
wire wSgElemRen;
wire wSgElemRdy;
wire wSgElemEmpty;
wire [31:0] wSgElemLen;
wire [63:0] wSgElemAddr;
wire wTxLast;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Capture channel transaction open/close events as well as channel data.
tx_port_channel_gate_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.RD_CLK(CLK),
.RD_DATA(wGateData),
.RD_EMPTY(wGateEmpty),
.RD_EN(wGateRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
// Filter transaction events from channel data. Use the events to put only
// the requested amount of data into the port buffer.
tx_port_monitor_128 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
.RST(rRst),
.CLK(CLK),
.EVT_DATA(wGateData),
.EVT_DATA_EMPTY(wGateEmpty),
.EVT_DATA_RD_EN(wGateRen),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount),
.TXN(wTxn),
.ACK(wTxnAck),
.LAST(wTxnLast),
.LEN(wTxnLen),
.OFF(wTxnOff),
.WORDS_RECVD(wTxnWordsRecvd),
.DONE(wTxnDone),
.TX_ERR(SG_ERR)
);
// Buffer the incoming channel data. Also make sure to discard only as
// much data as is needed for a transfer (which may involve non-integral
// packets (i.e. reading only 1, 2, or 3 words out of the packet).
tx_port_buffer_128 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
.CLK(CLK),
.RST(rRst | (TXN_DONE & wTxnErr)),
.RD_DATA(TX_DATA),
.RD_EN(TX_DATA_REN),
.LEN_VALID(TX_REQ_ACK),
.LEN_LSB(TX_LEN[1:0]),
.LEN_LAST(wTxLast),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | SG_RST),
.BUF_DATA(SG_DATA),
.BUF_DATA_EMPTY(SG_DATA_EMPTY),
.BUF_DATA_REN(SG_DATA_REN),
.VALID(wSgElemRdy),
.EMPTY(wSgElemEmpty),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Controls the flow of request to the tx engine for transfers in a transaction.
tx_port_writer writer (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN),
.TXN_ACK(TXN_ACK),
.TXN_LEN(TXN_LEN),
.TXN_OFF_LAST(TXN_OFF_LAST),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.NEW_TXN(wTxn),
.NEW_TXN_ACK(wTxnAck),
.NEW_TXN_LAST(wTxnLast),
.NEW_TXN_LEN(wTxnLen),
.NEW_TXN_OFF(wTxnOff),
.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
.NEW_TXN_DONE(wTxnDone),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_EMPTY(wSgElemEmpty),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(SG_RST),
.SG_ERR(SG_ERR),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_LAST(wTxLast),
.TX_SENT(TX_SENT)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int i, j, n, m, k; int main() { scanf( %d , &n); if (n <= 2) { printf( %d n , -1); } else { printf( %d n , 35); printf( %d n , 77); for (i = 1; i <= n - 2; i++) printf( %d n , i * 55); } return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_ba.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No user `defines in this module
module ent_ba
//
// Generated Module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int main(void) { int n; char str[102][102]; scanf( %d , &n); bool row, col; row = col = false; for (int i = 0; i < n; i++) { scanf( %s , str[i]); bool bolong = false; for (int j = 0; j < n; j++) { if (str[i][j] == . ) { bolong = true; } } if (!bolong) { row = true; } } if (!row) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (str[i][j] == . ) { printf( %d %d n , i + 1, j + 1); break; } } } return 0; } for (int i = 0; i < n; i++) { bool bolong = false; for (int j = 0; j < n; j++) { if (str[j][i] == . ) bolong = true; } if (!bolong) col = true; } if (!col) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (str[j][i] == . ) { printf( %d %d n , j + 1, i + 1); break; } } } } else printf( -1 ); return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// NOTE: Will not work with single-line frames
module ethrx_realign
(input clk, input reset, input clear,
input [35:0] datain, input src_rdy_i, output dst_rdy_o,
output [35:0] dataout, output src_rdy_o, input dst_rdy_i);
reg [1:0] state;
reg [15:0] held;
reg [1:0] held_occ;
wire xfer_in = src_rdy_i & dst_rdy_o;
wire xfer_out = src_rdy_o & dst_rdy_i;
wire sof_in = datain[32];
wire eof_in = datain[33];
wire [1:0] occ_in = datain[35:34];
wire sof_out, eof_out;
wire [1:0] occ_out;
always @(posedge clk)
if(reset | clear)
begin
held <= 0;
held_occ <= 0;
end
else if(xfer_in)
begin
held <= datain[15:0];
held_occ <= datain[35:34];
end
localparam RE_IDLE = 0;
localparam RE_HELD = 1;
localparam RE_DONE = 2;
always @(posedge clk)
if(reset | clear)
state <= RE_IDLE;
else
case(state)
RE_IDLE :
if(src_rdy_i & dst_rdy_i)
if(eof_in)
state <= RE_DONE;
else
state <= RE_HELD;
RE_HELD :
if(src_rdy_i & dst_rdy_i & eof_in)
if((occ_in==0)|(occ_in==3))
state <= RE_DONE;
else
state <= RE_IDLE;
RE_DONE :
if(dst_rdy_i)
state <= RE_IDLE;
endcase // case (state)
assign sof_out = (state == RE_IDLE);
assign eof_out = (state == RE_DONE) | (occ_in == 1) | (occ_in == 2);
assign occ_out = (state == RE_DONE) ? ((held_occ == 3) ? 1 : 2) :
(occ_in == 1) ? 3 : 0;
assign dataout = {occ_out,eof_out,sof_out,held,datain[31:16]};
assign src_rdy_o = (state == RE_DONE) | src_rdy_i;
assign dst_rdy_o = dst_rdy_i & ((state == RE_IDLE)|(state == RE_HELD));
endmodule // ethrx_realign
|
/**
\file "celem-test.v"
Drive a single C-element with phase-shifted clocks
Expect to see missing keeper diagnostics.
$Id: inverters.v,v 1.3 2010/04/06 00:08:35 fang Exp $
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in0, in1;
reg out;
clk_gen #(.HALF_PERIOD(1)) clk0(in0);
clk_gen #(.HALF_PERIOD(1), .PHASE_SHIFT(0.5)) clk1(in1);
// prsim stuff
initial
begin
// @haco@ celem.haco-c
$prsim_options("-f fast-weak-keepers");
$prsim("celem.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("weak-rules on");
$prsim_cmd("keeper-check-fail warn");
$to_prsim("TOP.in0", "in0");
$to_prsim("TOP.in1", "in1");
$from_prsim("out","TOP.out");
end
initial #15 $finish;
always @(in0)
begin
$display("at time %7.3f, observed in0 %b", $realtime,in0);
end
always @(in1)
begin
$display("at time %7.3f, observed in1 %b", $realtime,in1);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_1_V
`define SKY130_FD_SC_LS__TAPVGND2_1_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog wrapper for tapvgnd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapvgnd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapvgnd2_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__tapvgnd2 base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_1_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const int MAXN = 1000005; int dp[MAXN]; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; int x; int maxn = 0; for (int i = 0; i < n; i++) { cin >> x; dp[x]++; maxn = max(maxn, dp[x]); for (int j = x * 2; j < MAXN; j += x) { dp[j] = max(dp[j], dp[x]); } } cout << maxn << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int x1[200010]; int x2[200010]; int yz1[200010]; int yz2[200010]; int n; pair<pair<int, int>, pair<int, int> > pp[200010]; pair<pair<int, int>, pair<int, int> > qq[200010]; bool isValid(int x1, int y1, int x2, int y2) { if (x1 <= x2 && y1 <= y2) { return true; } return false; } pair<pair<int, int>, pair<int, int> > fn(int x1, int y1, int x2, int y2, int x3, int y3, int x4, int y4) { return make_pair(make_pair(max(x1, x3), max(y1, y3)), make_pair(min(x2, x4), min(y2, y4))); } int main() { int INF = INT_MAX; cin >> n; for (int i = 0; i < n; i++) { cin >> x1[i] >> yz1[i] >> x2[i] >> yz2[i]; } pp[0].first.first = x1[0]; pp[0].first.second = yz1[0]; pp[0].second.first = x2[0]; pp[0].second.second = yz2[0]; for (int i = 1; i < n; i++) { pair<pair<int, int>, pair<int, int> > uu; uu = fn(pp[i - 1].first.first, pp[i - 1].first.second, pp[i - 1].second.first, pp[i - 1].second.second, x1[i], yz1[i], x2[i], yz2[i]); if (isValid(uu.first.first, uu.first.second, uu.second.first, uu.second.second)) { pp[i] = uu; } else { pp[i] = make_pair(make_pair(INF, INF), make_pair(-INF, -INF)); } } qq[n - 1].first.first = x1[n - 1]; qq[n - 1].first.second = yz1[n - 1]; qq[n - 1].second.first = x2[n - 1]; qq[n - 1].second.second = yz2[n - 1]; for (int i = n - 2; i >= 0; i--) { pair<pair<int, int>, pair<int, int> > uu; uu = fn(qq[i + 1].first.first, qq[i + 1].first.second, qq[i + 1].second.first, qq[i + 1].second.second, x1[i], yz1[i], x2[i], yz2[i]); if (isValid(uu.first.first, uu.first.second, uu.second.first, uu.second.second)) { qq[i] = uu; } else { qq[i] = make_pair(make_pair(INF, INF), make_pair(-INF, -INF)); } } for (int i = 0; i < n; i++) { if (i == 0) { if (isValid(qq[1].first.first, qq[1].first.second, qq[1].second.first, qq[1].second.second)) { cout << qq[1].first.first << << qq[1].first.second; return 0; } } else if (i == n - 1) { if (isValid(pp[n - 2].first.first, pp[n - 2].first.second, pp[n - 2].second.first, pp[n - 2].second.second)) { cout << pp[n - 2].first.first << << pp[n - 2].first.second; return 0; } } else { pair<pair<int, int>, pair<int, int> > uu; uu = fn(qq[i + 1].first.first, qq[i + 1].first.second, qq[i + 1].second.first, qq[i + 1].second.second, pp[i - 1].first.first, pp[i - 1].first.second, pp[i - 1].second.first, pp[i - 1].second.second); if (isValid(uu.first.first, uu.first.second, uu.second.first, uu.second.second)) { cout << uu.first.first << << uu.first.second; return 0; } } } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; multiset<long long> s; long long now = 0; for (int i = 1; i <= n; i++) { long long a; cin >> a; a -= i; s.insert(a); s.insert(a); now -= a; long long x = (*s.rbegin()); s.erase(s.find(x)); now += x; } cout << now << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFSBP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311O_BLACKBOX_V
`define SKY130_FD_SC_LS__A311O_BLACKBOX_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311O_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_FUNCTIONAL_V
`define SKY130_FD_SC_LP__OR3B_FUNCTIONAL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or3b (
X ,
A ,
B ,
C_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, gn1 = 0, gj1 = 0, gn2 = 0, gj2 = 0; cin >> n >> m; for (int i = 0; i < n; i++) { int x; cin >> x; if (x % 2 == 0) gn1++; else gj1++; } for (int i = 0; i < m; i++) { int x; cin >> x; if (x % 2 == 0) gn2++; else gj2++; } cout << min(gj1, gn2) + min(gj2, gn1) << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i; cin >> n; cout << (n / 2) + 1 << endl; for (i = 1; i <= (n / 2) + 1; i++) cout << i << 1 << endl; ; if (n % 2 != 0) for (i = 2; i <= (n / 2) + 1; i++) cout << (n / 2) + 1 << << i << endl; else for (i = 2; i < (n / 2) + 1; i++) cout << (n / 2) + 1 << << i << endl; }
|
#include <bits/stdc++.h> using namespace std; int T; int h, c, t; int main() { scanf( %d , &T); while (T--) { scanf( %d%d%d , &h, &c, &t); if (t * 2 <= (h + c)) printf( %d n , 2); else { long long lef = (h - t) / (2 * t - (h + c)); double a1 = (1.0 * h * (lef + 1) + c * lef) / (2 * lef + 1); lef++; double a2 = (1.0 * h * (lef + 1) + c * lef) / (2 * lef + 1); if (abs(a1 - t) <= abs(a2 - t)) printf( %lld n , 2 * (lef - 1) + 1); else printf( %lld n , 2 * lef + 1); } } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 10; struct pos { double x, y; } p[maxn]; int n; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lf%lf , &p[i].x, &p[i].y); double ans = 0x3f3f3f3f; for (int i = 0; i < n; i++) { pos a = p[i]; pos b = p[(i + 1) % n]; pos c = p[(i + 2) % n]; double dis = (double)(c.x - a.x) * (b.y - c.y) - (c.y - a.y) * (b.x - c.x); if (dis < 0) dis = -dis; dis = dis / (sqrt((c.x - a.x) * (c.x - a.x) + (c.y - a.y) * (c.y - a.y))); dis = dis / 2; ans = min(ans, dis); } printf( %f , ans); }
|
// lattice ice5lp4k spi_slave + R G B blinky for RPi
// 10-05-16 E. Brombaugh
module rpi_tst(
// SPI slave port
input SPI_CSL,
input SPI_MOSI,
output SPI_MISO,
input SPI_SCLK,
// RGB output
output wire o_red,
output wire o_green,
output wire o_blue
);
// This should be unique so firmware knows who it's talking to
parameter DESIGN_ID = 32'h1CE50100;
//------------------------------
// Instantiate HF Osc with div 1
//------------------------------
wire clk;
SB_HFOSC #(.CLKHF_DIV("0b00")) OSCInst0 (
.CLKHFEN(1'b1),
.CLKHFPU(1'b1),
.CLKHF(clk)
) /* synthesis ROUTE_THROUGH_FABRIC= 0 */;
//------------------------------
// reset generator
//------------------------------
reg [3:0] reset_pipe = 4'hf;
reg reset = 1'b1;
always @(posedge clk)
begin
reset <= |reset_pipe;
reset_pipe <= {reset_pipe[2:0],1'b0};
end
//------------------------------
// Internal SPI slave port
//------------------------------
wire [31:0] wdat;
reg [31:0] rdat;
wire [6:0] addr;
wire re, we, spi_slave_miso;
spi_slave
uspi(.clk(clk), .reset(reset),
.spiclk(SPI_SCLK), .spimosi(SPI_MOSI),
.spimiso(SPI_MISO), .spicsl(SPI_CSL),
.we(we), .re(re), .wdat(wdat), .addr(addr), .rdat(rdat));
//------------------------------
// Writeable registers
//------------------------------
reg [13:0] cnt_limit_reg;
reg [31:0] freq;
reg gate;
always @(posedge clk)
if(reset)
begin
cnt_limit_reg <= 14'd2499; // 1/4 sec blink rate
end
else if(we)
case(addr)
7'h01: cnt_limit_reg <= wdat;
endcase
//------------------------------
// readback
//------------------------------
always @(*)
case(addr)
7'h00: rdat = DESIGN_ID;
7'h01: rdat = cnt_limit_reg;
default: rdat = 32'd0;
endcase
//------------------------------
// Instantiate LF Osc
//------------------------------
wire CLKLF;
SB_LFOSC OSCInst1 (
.CLKLFEN(1'b1),
.CLKLFPU(1'b1),
.CLKLF(CLKLF)
) /* synthesis ROUTE_THROUGH_FABRIC= 0 */;
//------------------------------
// Divide the clock
//------------------------------
reg [13:0] clkdiv;
reg onepps;
always @(posedge CLKLF)
begin
if(clkdiv == 14'd0)
begin
onepps <= 1'b1;
clkdiv <= cnt_limit_reg;
end
else
begin
onepps <= 1'b0;
clkdiv <= clkdiv - 14'd1;
end
end
//------------------------------
// LED signals
//------------------------------
reg [2:0] state;
always @(posedge CLKLF)
begin
if(onepps)
state <= state + 3'd1;
end
//------------------------------
// Instantiate RGB DRV
//------------------------------
wire red_pwm_i = state[0];
wire grn_pwm_i = state[1];
wire blu_pwm_i = state[2];
SB_RGB_DRV RGB_DRIVER (
.RGBLEDEN (1'b1), // Enable current for all 3 RGB LED pins
.RGB0PWM (red_pwm_i), // Input to drive RGB0 - from LEDD HardIP
.RGB1PWM (grn_pwm_i), // Input to drive RGB1 - from LEDD HardIP
.RGB2PWM (blu_pwm_i), // Input to drive RGB2 - from LEDD HardIP
.RGBPU (led_power_up_i), //Connects to LED_DRV_CUR primitive
.RGB0 (o_red),
.RGB1 (o_green),
.RGB2 (o_blue)
);
defparam RGB_DRIVER.RGB0_CURRENT = "0b000111";
defparam RGB_DRIVER.RGB1_CURRENT = "0b000111";
defparam RGB_DRIVER.RGB2_CURRENT = "0b000111";
//------------------------------
// Instantiate LED CUR DRV
//------------------------------
SB_LED_DRV_CUR LED_CUR_inst (
.EN (1'b1), //Enable to supply reference current to the LED drivers
.LEDPU (led_power_up_i) //Connects to SB_RGB_DRV primitive
);
endmodule
|
module LCDhex (
//////////////////// Clock Input ////////////////////
CLOCK_27, // 27 MHz
CLOCK_50, // 50 MHz
//////////////////// Push Button ////////////////////
KEY, // Button[3:0]
//////////////////// DPDT Switch ////////////////////
SW, // DPDT Switch[17:0]
//////////////////// 7-SEG Dispaly ////////////////////
HEX0, // Seven Segment Digital 0
HEX1, // Seven Segment Digital 1
HEX2, // Seven Segment Digital 2
HEX3, // Seven Segment Digital 3
HEX4, // Seven Segment Digital 4
HEX5, // Seven Segment Digital 5
HEX6, // Seven Segment Digital 6
HEX7, // Seven Segment Digital 7
//////////////////////// LED ////////////////////////
LEDG, // LED Green[8:0]
LEDR, // LED Red[17:0]
//////////////////////// UART ////////////////////////
UART_TXD, // UART Transmitter
UART_RXD, // UART Rceiver
//////////////////////// IRDA ////////////////////////
//////////////////// LCD Module 16X2 ////////////////
LCD_ON, // LCD Power ON/OFF
LCD_BLON, // LCD Back Light ON/OFF
LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN, // LCD Enable
LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA, // LCD Data bus 8 bits
GPIO_0, // GPIO
GPIO_1
);
//////////////////////// Clock Input ////////////////////////
input CLOCK_27; // 27 MHz
input CLOCK_50; // 50 MHz
//////////////////////// Push Button ////////////////////////
input [3:0] KEY; // Button[3:0]
//////////////////////// DPDT Switch ////////////////////////
input [17:0] SW; // DPDT Switch[17:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
output [6:0] HEX0; // Seven Segment Digital 0
output [6:0] HEX1; // Seven Segment Digital 1
output [6:0] HEX2; // Seven Segment Digital 2
output [6:0] HEX3; // Seven Segment Digital 3
output [6:0] HEX4; // Seven Segment Digital 4
output [6:0] HEX5; // Seven Segment Digital 5
output [6:0] HEX6; // Seven Segment Digital 6
output [6:0] HEX7; // Seven Segment Digital 7
//////////////////////////// LED ////////////////////////////
output [8:0] LEDG; // LED Green[8:0]
output [17:0] LEDR; // LED Red[17:0]
//////////////////////////// UART ////////////////////////////
output UART_TXD; // UART Transmitter
input UART_RXD; // UART Rceiver
//////////////////// LCD Module 16X2 ////////////////////////////
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
////////////////////////////////////////////////////////////////////
// All inout port turn to tri-state
assign GPIO_1 = 36'hzzzzzzzzz;
assign GPIO_0 = 36'hzzzzzzzzz;
////////////////////////////////////////////////////////////////////
reg [15:0] d0,d1,d2,d3,d4;
always @(posedge KEY[2])
case(SW[17:16])
0: d0 <= SW[15:0];
1: d1 <= SW[15:0];
2: d2 <= SW[15:0];
default: d3 <= SW[15:0];
endcase
always @(posedge CLOCK_27)
if(!KEY[0]) begin
d4 <= 0;
end
else begin
d4 <= d4+d0;
end
// LCD
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
LCD_TEST u5 (
// Host Side
.iCLK ( CLOCK_50 ),
.iRST_N ( KEY[0] ),
// Data to display
.d0 (d0),
.d1 (d1),
.d2 (d2),
.d3 (d3),
.d4 (d4),
.d5 (SW[15:0]),
// LCD Side
.LCD_DATA( LCD_DATA ),
.LCD_RW ( LCD_RW ),
.LCD_EN ( LCD_EN ),
.LCD_RS ( LCD_RS )
);
/*assign HEX3=7'b0101011;
assign HEX2=7'b0001000;
assign HEX1=7'b0000111;
assign HEX0=7'b0100011;
assign HEX4=7'b1111111;
assign HEX5=7'b1111111;
assign HEX6=7'b1111111;
assign HEX7=7'b1111111;*/
endmodule
|
/****************************************************************************
Shifter unit
Opcode Table:
sign_ext dir
0 0 | ShiftLeft
0 1 | ShiftRightLogic
1 1 | ShiftRightArith
****************************************************************************/
module shifter(
clk, resetn,
opB, sa,
op,
result);
parameter WIDTH=32;
input clk;
input resetn;
input [WIDTH-1:0] opB;
input [4:0] sa; // Shift Amount
input [2-1:0] op;
output [WIDTH-1:0] result;
wire sign_ext;
wire shift_direction;
assign sign_ext=op[1];
assign shift_direction=op[0];
wire dum,dum_,dum2;
wire [WIDTH-1:0] partial_result_,partial_result;
lpm_clshift shifter_inst1(
.data({sign_ext&opB[WIDTH-1],opB}),
.distance({sa[4:3],3'b0}),
.direction(shift_direction),
.result({dum,partial_result}));
defparam
shifter_inst1.lpm_width = WIDTH+1,
shifter_inst1.lpm_widthdist = 5,
shifter_inst1.lpm_shifttype="ARITHMETIC";
register partial_reg({dum,partial_result},clk,resetn,1'b1,{dum_,partial_result_});
defparam partial_reg.WIDTH=33;
wire [2:0] sa_2;
wire shift_direction_2;
register secondstage({shift_direction,sa[2:0]},clk,resetn,1'b1,{shift_direction_2, sa_2});
defparam secondstage.WIDTH=4;
lpm_clshift shifter_inst2(
.data({dum_,partial_result_}),
.distance(sa_2[2:0]),
.direction(shift_direction_2),
.result({dum2,result}));
defparam
shifter_inst2.lpm_width = WIDTH+1,
shifter_inst2.lpm_widthdist = 3,
shifter_inst2.lpm_shifttype="ARITHMETIC";
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:34:44 03/13/2015
// Design Name:
// Module Name: PreProcessxy
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PreProcessxy(
input [107:0] InstructionPacket, // Unprocessed square root is given an opcode that is not defined in fetch.
input clock,
output [107:0] InstructionPacketOut,
output InputReady
);
wire [3:0] Opcode;
wire [31:0] x_processor;
wire [31:0] y_processor;
wire [31:0] z_processor;
wire [7:0] InsTagIn;
wire [31:0] x_new, y_new, z_newX, z_newY;
wire [3:0] OpcodeX, OpcodeY;
wire DoneX, DoneY;
wire [7:0] InsX,InsY;
assign InsTagIn = InstructionPacket[107:100];
assign Opcode = InstructionPacket[99:96];
assign x_processor = InstructionPacket[31:0];
assign y_processor = InstructionPacket[63:32];
assign z_processor = InstructionPacket[95:64];
assign InstructionPacketOut[31:0] = x_new;
assign InstructionPacketOut[63:32] = y_new;
assign InputReady = DoneX && DoneY;
assign InstructionPacketOut[95:64] = z_newX;
assign InstructionPacketOut[99:96] = OpcodeX;
assign InstructionPacketOut[107:100] = InsX;
PreProcessX X (
.z_preprocess(z_processor),
.Opcode(Opcode),
.b_adder(x_processor),
.InsTagIn(InsTagIn),
.clock(clock),
.FinalSum(x_new),
.Done(DoneX),
.z_postprocess(z_newX),
.Opcode_out(OpcodeX),
.InsTagOut(InsX)
);
PreProcessY Y (
.z_preprocess(z_processor),
.Opcode(Opcode),
.b_adder(y_processor),
.InsTagIn(InsTagIn),
.clock(clock),
.FinalSum(y_new),
.Done(DoneY),
.z_postprocess(z_newY),
.Opcode_out(OpcodeY),
.InsTagOut(InsY)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; ++i) cin >> a[i]; int m; cin >> m; int b[m]; for (int i = 0; i < m; ++i) cin >> b[i]; sort(a + 0, a + n); sort(b + 0, b + m); int ans = 0; for (int i = 0, j = 0; i < n; i++) { while (j < m) { if (abs(a[i] - b[j]) <= 1) { ans++; j++; break; } else if (a[i] - b[j] < 0) { break; } else { j++; } } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int x, k = 0; cin >> x; while (x) { k += x % 2; x /= 2; } cout << k; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long>> g[111111]; long long d[111111]; set<long long> t[111111]; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { d[i] = 1e13; } for (int i = 1; i <= m; i++) { long long a, b, cost; cin >> a >> b >> cost; g[a].push_back({b, cost}); g[b].push_back({a, cost}); } for (int i = 1; i <= n; i++) { long long a; cin >> a; for (int j = 1; j <= a; j++) { long long b; cin >> b; t[i].insert(b); } } d[1] = 0; set<pair<long long, long long>> q; q.insert({0, 1}); while (!q.empty()) { long long h = 0; int v = q.begin()->second; q.erase(q.begin()); while (t[v].find(d[v]) != t[v].end()) { h++; d[v]++; } for (int i = 0; i < g[v].size(); i++) { long long to = g[v][i].first, cost = g[v][i].second; if (d[to] > d[v] + cost) { q.erase({d[to], to}); d[to] = d[v] + cost; q.insert({d[to], to}); } } d[v] = d[v] - h; } if (d[n] == 1e13) { cout << -1; return 0; } cout << d[n]; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const int inf = 0x3f3f3f3f; const long long inff = 0x3f3f3f3f3f3f3f3f; int n; int a[200010]; int dp[200010]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; a[i] += a[i - 1]; } dp[n] = a[n]; int mx = dp[n]; for (int i = n - 1; i >= 2; i--) { dp[i] = max(a[i] - mx, mx); mx = max(a[i] - mx, mx); } cout << mx << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 155; const int INF = 123456789; struct edge { int to, lim, pri, rev; edge() : to(0), lim(0), pri(0), rev(0){}; edge(int to, int lim, int pri, int rev) : to(to), lim(lim), pri(pri), rev(rev){}; }; vector<edge> nei[N]; char ss[105]; int hv[26]; int n, sl, s, t, cst, flw; int d[N], f[N], p[N], v[N]; queue<int> q; void add_edge(int x, int y, int l, int p) { nei[x].push_back(edge(y, l, p, int(nei[y].size()))); nei[y].push_back(edge(x, 0, -p, int(nei[x].size()) - 1)); } int spfa() { for (int i = s; i <= t; i++) { v[i] = 0; d[i] = f[i] = INF; } d[s] = 0, v[s] = 1; while (!q.empty()) q.pop(); q.push(s); while (!q.empty()) { int x = q.front(); q.pop(); v[x] = 0; for (int i = 0; i < nei[x].size(); i++) { int to = nei[x][i].to; int lim = nei[x][i].lim; int pri = nei[x][i].pri; int rev = nei[x][i].rev; if (lim == 0) continue; if (d[to] > d[x] + pri) { p[to] = rev; d[to] = d[x] + pri; f[to] = min(f[x], lim); if (!v[to]) { v[to] = 1; q.push(to); } } } } return d[t] != INF; } void mcmf() { while (spfa()) { flw += f[t]; cst += d[t] * f[t]; int x = t; while (x != s) { int r = p[x]; int to = nei[x][r].to; int rev = nei[x][r].rev; nei[x][r].lim += f[t]; nei[to][rev].lim -= f[t]; x = to; } } } int main() { scanf( %s , &ss); sl = strlen(ss); int Sl = sl; for (int i = 0; i < sl; i++) hv[ss[i] - a ]++; scanf( %d , &n); s = 1; t = n + 28; for (int i = 0; i < 26; i++) if (hv[i]) { add_edge(n + 2 + i, t, hv[i], 0); hv[i] = 0; } for (int i = 1; i <= n; i++) { int x; scanf( %s%d , ss, &x); sl = strlen(ss); for (int j = 0; j < sl; j++) hv[ss[j] - a ]++; add_edge(s, i + 1, x, 0); for (int j = 0; j < 26; j++) if (hv[j]) { add_edge(i + 1, n + 2 + j, hv[j], i); hv[j] = 0; } } mcmf(); if (Sl == flw) printf( %d n , cst); else puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 110; vector<int> G[N]; int vis[N]; void DFS(int cur) { vis[cur]++; int sz = G[cur].size(); int v; for (int i = 0; i < sz; i++) { v = G[cur][i]; if (!vis[v]) DFS(v); } } int main() { int n, m, u, v; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } DFS(1); for (int i = 1; i <= n; i++) if (!vis[i]) { cout << NO ; return 0; } if (n == m) cout << FHTAGN! ; else cout << NO ; return 0; }
|
//--------------------------------------------------------------------------------
// meta.v
//
// Copyright (C) 2011 Ian Davis
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details:
// http://www.dangerousprototypes.com/ols
// http://www.gadgetfactory.net/gf/project/butterflylogic
// http://www.mygizmos.org/ols
//
// Inserts META data into spi_transmitter datapath upon command...
//
`timescale 1ns/100ps
module meta_handler(
clock, extReset,
query_metadata, xmit_idle,
// outputs...
writeMeta, meta_data);
input clock;
input extReset;
input query_metadata;
input xmit_idle;
output writeMeta;
output [7:0] meta_data;
reg [5:0] metasel, next_metasel;
reg writeMeta;
`define ADDBYTE(cmd) meta_rom[i]=cmd; i=i+1
`define ADDSHORT(cmd,b0) meta_rom[i]=cmd; meta_rom[i+1]=b0; i=i+2
`define ADDLONG(cmd,b0,b1,b2,b3) meta_rom[i]=cmd; meta_rom[i+1]=b0; meta_rom[i+2]=b1; meta_rom[i+3]=b2; meta_rom[i+4]=b3; i=i+5
// Create meta data ROM...
reg [5:0] METADATA_LEN;
reg [7:0] meta_rom[63:0];
wire [7:0] meta_data = meta_rom[metasel];
initial
begin : meta
integer i;
i=0;
`ADDLONG(8'h01, "O", "p", "e", "n"); // Device name string...
`ADDLONG(" ", "L", "o", "g", "i");
`ADDLONG("c", " ", "S", "n", "i");
`ADDLONG("f", "f", "e", "r", " ");
`ADDLONG("v", "1", ".", "0", "1");
`ADDBYTE(0);
`ADDLONG(8'h02, "3", ".", "0", "7"); // FPGA firmware version string
`ADDBYTE(0);
//`ADDLONG(8'h21,8'h00,8'h60,8'h00,8'h00); // Amount of sample memory (24K)
//`ADDLONG(8'h23,8'h00,8'hC2,8'hEB,8'h0B); // Max sample rate (200Mhz)
`ADDLONG(8'h21,8'h00,8'h00,8'h60,8'h00); // Amount of sample memory (24K)
`ADDLONG(8'h23,8'h0B,8'hEB,8'hC2,8'h00); // Max sample rate (200Mhz)
`ADDSHORT(8'h40,8'h20); // Max # of probes
`ADDSHORT(8'h41,8'h02); // Protocol version
`ADDBYTE(0); // End of data flag
METADATA_LEN = i;
for (i=i; i<64; i=i+1) meta_rom[i]=0; // Padding
end
//
// Control FSM for sending meta data...
//
parameter [1:0] IDLE = 0, METASEND = 1, METAPOLL = 2;
reg [1:0] state, next_state;
initial state = IDLE;
always @(posedge clock or posedge extReset)
begin
if (extReset)
begin
state = IDLE;
metasel = 3'h0;
end
else
begin
state = next_state;
metasel = next_metasel;
end
end
always @*
begin
#1;
next_state = state;
next_metasel = metasel;
writeMeta = 1'b0;
case (state)
IDLE :
begin
next_metasel = 0;
next_state = (query_metadata && xmit_idle) ? METASEND : IDLE;
end
METASEND : // output contents of META data rom - IED
begin
writeMeta = 1'b1;
next_metasel = metasel+1'b1;
next_state = METAPOLL;
end
METAPOLL :
begin
if (xmit_idle)
next_state = (metasel==METADATA_LEN) ? IDLE : METASEND;
end
default : next_state = IDLE;
endcase
end
endmodule
|
module forward_mem_stage(mem_wb_op,mem_wb_regA,mem_wb_regC,ex_mem_op,ex_mem_regA,F3,mem_wb_CCR_write,ex_mem_CCR_write);
parameter ADD = 6'b000000;
parameter NDU = 6'b001000;
parameter ADC = 6'b000010;
parameter ADZ = 6'b000001;
parameter ADI = 4'b0001;
parameter NDC = 6'b001010;
parameter NDZ = 6'b001001;
parameter LHI = 4'b0011;
parameter LW = 4'b0100;
parameter SW = 4'b0101;
parameter LM = 4'b0110;
parameter SM = 4'b0111;
parameter BEQ = 4'b1100;
parameter JAL = 4'b1000;
parameter JLR = 4'b1001;
input [2:0] mem_wb_regA,mem_wb_regC,ex_mem_regA;
input [5:0]mem_wb_op,ex_mem_op;
input mem_wb_CCR_write,ex_mem_CCR_write;
output reg [1:0]F3;
always @(*)
begin
if(ex_mem_op[5:2]==SW)
begin
if((ex_mem_regA == mem_wb_regC)&&(mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC||mem_wb_op==ADZ
||mem_wb_op==NDC||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
F3 = 2'd2;//b
else if((ex_mem_regA==mem_wb_regA)&&(mem_wb_op[5:2]==LW))
F3 = 2'd3;//c
else
F3 = 2'b0;
end
else
F3 = 2'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = (119 << 23) + 1; int add(int a, int b) { return (a += b) < M ? a : a - M; } int sub(int a, int b) { return (a -= b) < 0 ? a + M : a; } int mul(int a, int b) { return 1LL * a * b % M; } int mod_pow(int a, int b) { int res = 1; while (b) { if (b % 2) { res = mul(res, a); } a = mul(a, a); b /= 2; } return res; } int mod_inv(int a) { return mod_pow(a, M - 2); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<int> a(n); for (auto& i : a) { cin >> i; } sort(a.rbegin(), a.rend()); for (int i = 1; i < n; ++i) { a[i] = add(a[i], a[i - 1]); } for (int k = 1; k <= n; ++k) { int ans = 0; for (int i = 0; i < n; i += k) { int sum = a[min(i + k - 1, n - 1)]; sum = sub(sum, i ? a[i - 1] : 0); ans = add(ans, mul(i / k, sum)); } ans = mul(ans, mod_inv(n)); cout << ans << ; } cout << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__NAND2_BEHAVIORAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int n, u, v, N; vector<char> ans(1e5 + 5); vector<int> sub(1e5 + 5); vector<set<int> > adj(1e5 + 5); void dfs(int u, int par) { sub[u] = 1; for (int v : adj[u]) { if (v != par) { dfs(v, u); sub[u] += sub[v]; } } } int centroid(int u, int par) { for (int v : adj[u]) { if (v != par && sub[v] > n / 2) { return centroid(v, u); } } return u; } void build(int u, int prev, int level) { dfs(u, -1); n = sub[u]; int cur = centroid(u, -1); ans[cur] = char(level + 65); for (int v : adj[cur]) { adj[v].erase(cur); build(v, cur, level + 1); } } int main(void) { ios ::sync_with_stdio(0); cin.tie(0); cin >> n; N = n; for (int i = 1; i <= n - 1; ++i) { cin >> u >> v; adj[u].insert(v); adj[v].insert(u); } build(1, -1, 0); for (int i = 1; i <= N; ++i) { cout << ans[i] << ; } cout << n ; return 0; }
|
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
Generic small FIFO using distributed memory
Caution: There is no protection against overflow or underflow,
driving logic should avoid wen on full or ren on empty.
########################################################################
*/
module syncfifo
#(
// Address width (must be 5 => 32-deep FIFO)
parameter AW = 5,
// Data width
parameter DW = 16
)
(
input clk,
input reset,
input [DW-1:0] wdata,
input wen,
input ren,
output wire [DW-1:0] rdata,
output reg empty,
output reg full
);
reg [AW-1:0] waddr;
reg [AW-1:0] raddr;
reg [AW-1:0] count;
always @ ( posedge clk ) begin
if( reset ) begin
waddr <= 'd0;
raddr <= 'd0;
count <= 'd0;
empty <= 1'b1;
full <= 1'b0;
end else begin
if( wen & ren ) begin
waddr <= waddr + 'd1;
raddr <= raddr + 'd1;
end else if( wen ) begin
waddr <= waddr + 'd1;
count <= count + 'd1;
empty <= 1'b0;
if( & count )
full <= 1'b1;
end else if( ren ) begin
raddr <= raddr + 'd1;
count <= count - 'd1;
full <= 1'b0;
if( count == 'd1 )
empty <= 1'b1;
end
end // else: !if( reset )
end // always @ ( posedge clk )
genvar dn;
generate for(dn=0; dn<DW; dn=dn+1)
begin : genbits
RAM32X1D RAM32X1D_inst
(
.DPO(rdata[dn] ), // Read-only 1-bit data output
.SPO(), // Rw/ 1-bit data output
.A0(waddr[0]), // Rw/ address[0] input bit
.A1(waddr[1]), // Rw/ address[1] input bit
.A2(waddr[2]), // Rw/ address[2] input bit
.A3(waddr[3]), // Rw/ address[3] input bit
.A4(waddr[4]), // Rw/ address[4] input bit
.D(wdata[dn]), // Write 1-bit data input
.DPRA0(raddr[0]), // Read-only address[0] input bit
.DPRA1(raddr[1]), // Read-only address[1] input bit
.DPRA2(raddr[2]), // Read-only address[2] input bit
.DPRA3(raddr[3]), // Read-only address[3] input bit
.DPRA4(raddr[4]), // Read-only address[4] input bit
.WCLK(clk), // Write clock input
.WE(wen) // Write enable input
);
end
endgenerate
endmodule // syncfifo
|
module edge_detect
(/*autoport*/
input clk,
input rst_n,
input signal_in,
output reg signal_out
);
//*******************************************************
//Internal
//*******************************************************
//Local Parameters
//Wires
//Registers
reg ff1,ff2;
//*******************************************************
//General Purpose Signals
//*******************************************************
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
ff1 <= 1'b0;
ff2 <= 1'b0;
end
else begin
ff1 <= signal_in;
ff2 <= ff1;
end
end
//*******************************************************
//Outputs
//*******************************************************
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
signal_out <= 1'b0;
end
else begin
if (!ff2 && ff1)
signal_out <= 1'b1;
else begin
signal_out <= 1'b0;
end
end
end
//*******************************************************
//Instantiations
//*******************************************************
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; unsigned long long k, res = 0; cin >> n >> k; unsigned long long *arr = new unsigned long long[n + 1]; arr[0] = 1; for (int i = 1; i <= n; i++) arr[i] = arr[i - 1] * 2; bool left = true; while (n > 1) { if (k > arr[n - 1]) { if (left) { res += arr[n]; } else { res++; left = true; } k -= arr[n - 1]; } else { if (left) { res++; } else { res += arr[n]; } left = false; } n--; } if (k == 1 && left) res += 2; else if (k == 2 && left) res += 3; else if (k == 1) res += 3; else res += 2; cout << res - 1; return 0; }
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 160;
localparam integer DOUT_N = 160;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [159:0] din, output [159:0] dout);
DRAM32X1S
#(
.LOC("SLICE_X1Y240")
)
inst_0 (
.clk(clk),
.din(din[ 0 +: 10]),
.dout(dout[ 0 +: 1])
);
DRAM64X1S
#(
.LOC("SLICE_X1Y241")
)
inst_1 (
.clk(clk),
.din(din[ 10 +: 10]),
.dout(dout[ 1 +: 1])
);
endmodule
// ---------------------------------------------------------------------
module DRAM32X1S(input clk, input [5:0] din, output dout);
parameter LOC = "";
(* LOC=LOC *)
RAM32X1S #(
.INIT(32'h00000000), // Initial contents of RAM
.IS_WCLK_INVERTED(1'b0) // Specifies active high/low WCLK
) RAM32X1S_inst (
.O(dout), // RAM output
.A0(din[0]), // RAM address[0] input
.A1(din[1]), // RAM address[1] input
.A2(din[2]), // RAM address[2] input
.A3(din[3]), // RAM address[3] input
.A4(din[4]), // RAM address[4] input
.D(din[5]), // RAM data input
.WCLK(clk), // Write clock input
.WE(1'b1) // Write enable input
);
endmodule
module DRAM64X1S(input clk, input [6:0] din, output dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X1S #(
.INIT(64'h00000000), // Initial contents of RAM
.IS_WCLK_INVERTED(1'b0) // Specifies active high/low WCLK
) RAM64X1S_inst (
.O(dout), // RAM output
.A0(din[0]), // RAM address[0] input
.A1(din[1]), // RAM address[1] input
.A2(din[2]), // RAM address[2] input
.A3(din[3]), // RAM address[3] input
.A4(din[4]), // RAM address[4] input
.A5(din[5]), // RAM address[5] input
.D(din[6]), // RAM data input
.WCLK(clk), // Write clock input
.WE(1'b1) // Write enable input
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; if (k <= (n + 1) / 2) { cout << k * 2 - 1 << n ; } else cout << (k - (n + 1) / 2) * 2 << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T, typename U> ostream& operator<<(ostream& os, const pair<T, U>& _p) { return os << ( << _p.first << , << _p.second << ) ; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& _V) { bool f = true; os << [ ; for (auto v : _V) { os << (f ? : , ) << v; f = false; } return os << ] ; } template <typename T> ostream& operator<<(ostream& os, const set<T>& _S) { bool f = true; os << ( ; for (auto s : _S) { os << (f ? : , ) << s; f = false; } return os << ) ; } template <typename T, typename U> ostream& operator<<(ostream& os, const map<T, U>& _M) { return os << set<pair<T, U>>(_M.begin(), _M.end()); } const signed long long INF = 1000000100; const long double EPS = 1e-9; namespace MCMF { const int MAXN = 10005; const int MAXM = 500500; int nodes, nedge, src, dest; int point[MAXM], nex[MAXM], flow[MAXM], capa[MAXM], cost[MAXM]; int head[MAXN], dist[MAXN], expand[MAXN], pre[MAXN], edge[MAXN]; bool changed[MAXN]; void init(int n, int s, int t) { nodes = n; src = s; dest = t; nedge = 0; for (int(i) = (0); (i) < (nodes); (i)++) head[i] = -1; } int add_edge(int u, int v, int c, int w) { point[nedge] = v, capa[nedge] = c, cost[nedge] = w, flow[nedge] = 0, nex[nedge] = head[u], head[u] = (nedge++); point[nedge] = u, capa[nedge] = 0, cost[nedge] = -w, flow[nedge] = 0, nex[nedge] = head[v], head[v] = (nedge++); return nedge - 2; } pair<int, int> run() { int mflow = 0, mcost = 0; while (true) { for (int(i) = (0); (i) < (nodes); (i)++) dist[i] = INF, pre[i] = -1, changed[i] = 0; dist[src] = 0; changed[src] = 1; expand[src] = INF; while (true) { bool ok = 1; for (int(i) = (0); (i) < (nodes); (i)++) if (changed[i]) { changed[i] = 0; for (int k = head[i]; k >= 0; k = nex[k]) { if (flow[k] < capa[k] && dist[i] + cost[k] < dist[point[k]]) { dist[point[k]] = dist[i] + cost[k]; changed[point[k]] = 1; pre[point[k]] = i; edge[point[k]] = k; expand[point[k]] = min(expand[i], capa[k] - flow[k]); ok = 0; } } } if (ok) break; } if (pre[dest] < 0) break; int d = expand[dest]; mflow += d; mcost += d * dist[dest]; for (int k = dest; k != src; k = pre[k]) { flow[edge[k]] += d; flow[edge[k] ^ 1] -= d; } } return make_pair(mflow, mcost); } }; // namespace MCMF int M, N; const int MAXN = 88; int A[MAXN][MAXN]; void read_data() { scanf( %d %d , &M, &N); for (int(i) = (1); (i) <= (M); (i)++) for (int(j) = (1); (j) <= (N); (j)++) scanf( %d , &A[i][j]); } int encode(int x, int y) { return x + M * (y - 1); } bool ok(int x, int y) { return 1 <= x and x <= M and 1 <= y and y <= N; } int dx[] = {-1, 1, 0, 0}; int dy[] = {0, 0, -1, 1}; void solve() { int S = M * N + 1; int T = M * N + 2; MCMF::init(T + 1, S, T); for (int(x) = (1); (x) <= (M); (x)++) for (int(y) = (1); (y) <= (N); (y)++) { if ((x + y) % 2 == 1) { MCMF::add_edge(S, encode(x, y), 1, 0); for (int(d) = (0); (d) <= (3); (d)++) { int nx = x + dx[d]; int ny = y + dy[d]; if (!ok(nx, ny)) continue; int w = (A[x][y] != A[nx][ny]); MCMF::add_edge(encode(x, y), encode(nx, ny), 1, w); } } else { MCMF::add_edge(encode(x, y), T, 1, 0); } } cout << MCMF::run().second << endl; } int main() { read_data(); solve(); }
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#include <bits/stdc++.h> using namespace std; int N, M; vector<int> edge[100001]; int val[100001]; vector<int> ans[2]; void dfs(int i, int fi) { if (val[i] != 0 && fi != val[i]) { cout << -1 n ; exit(0); } if (val[i] != 0 && fi == val[i]) { return; } val[i] = fi; ans[(fi + 1) / 2].push_back(i); for (int j = 0; j < edge[i].size(); j++) { dfs(edge[i][j], -fi); } } int main() { ios_base::sync_with_stdio(false); if (fopen( cf688c.in , r )) { freopen( cf688c.in , r , stdin); freopen( cf688c.out , w , stdout); } cin >> N >> M; for (int i = 0; i < M; i++) { int a, b; cin >> a >> b; a--; b--; edge[a].push_back(b); edge[b].push_back(a); } for (int i = 0; i < N; i++) { if (val[i] == 0) { if (ans[0].size() == 0) { dfs(i, -1); } else { dfs(i, 1); } } } if (ans[0].size() == 0 || ans[1].size() == 0) { cout << -1 n ; return 0; } cout << ans[0].size() << n ; for (int i = 0; i < ans[0].size(); i++) { cout << ans[0][i] + 1 << ; } cout << n ; cout << ans[1].size() << n ; for (int i = 0; i < ans[1].size(); i++) { cout << ans[1][i] + 1 << ; } cout << n ; return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
ign, ign2, ign3,
// Inputs
clk
);
input clk;
output [31:0] ign;
output [3:0] ign2;
output [11:0] ign3;
parameter [95:0] P6 = 6;
localparam P64 = (1 << P6);
// verilator lint_off WIDTH
localparam [4:0] PBIG23 = 1'b1 << ~73'b0;
localparam [3:0] PBIG29 = 4'b1 << 33'h100000000;
// verilator lint_on WIDTH
reg [31:0] right;
reg [31:0] left;
reg [P64-1:0] qright;
reg [P64-1:0] qleft;
reg [31:0] amt;
assign ign = {31'h0, clk} >>> 4'bx; // bug760
assign ign2 = {amt[1:0] >> {22{amt[5:2]}}, amt[1:0] << (0 <<< amt[5:2])}; // bug1174
assign ign3 = {amt[1:0] >> {22{amt[5:2]}},
amt[1:0] >> {11{amt[5:2]}},
$signed(amt[1:0]) >>> {22{amt[5:2]}},
$signed(amt[1:0]) >>> {11{amt[5:2]}},
amt[1:0] << {22{amt[5:2]}},
amt[1:0] << {11{amt[5:2]}}};
always @* begin
right = 32'h819b018a >> amt;
left = 32'h819b018a << amt;
qright = 64'hf784bf8f_12734089 >> amt;
qleft = 64'hf784bf8f_12734089 >> amt;
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x\n", cyc, left, right, qleft, qright);
`endif
if (cyc==1) begin
amt <= 32'd0;
if (P64 != 64) $stop;
if (5'b10110>>2 != 5'b00101) $stop;
if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness
if (5'b10110<<2 != 5'b11000) $stop;
if (5'b10110<<<2 != 5'b11000) $stop;
if (5'sb10110>>2 != 5'sb00101) $stop;
if (5'sb10110>>>2 != 5'sb11101) $stop;
if (5'sb10110<<2 != 5'sb11000) $stop;
if (5'sb10110<<<2 != 5'sb11000) $stop;
// Allow >64 bit shifts if the shift amount is a constant
if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop;
end
if (cyc==2) begin
amt <= 32'd28;
if (left != 32'h819b018a) $stop;
if (right != 32'h819b018a) $stop;
if (qleft != 64'hf784bf8f_12734089) $stop;
if (qright != 64'hf784bf8f_12734089) $stop;
end
if (cyc==3) begin
amt <= 32'd31;
if (left != 32'ha0000000) $stop;
if (right != 32'h8) $stop;
if (qleft != 64'h0000000f784bf8f1) $stop;
if (qright != 64'h0000000f784bf8f1) $stop;
end
if (cyc==4) begin
amt <= 32'd32;
if (left != 32'h0) $stop;
if (right != 32'h1) $stop;
if (qleft != 64'h00000001ef097f1e) $stop;
if (qright != 64'h00000001ef097f1e) $stop;
end
if (cyc==5) begin
amt <= 32'd33;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h00000000f784bf8f) $stop;
if (qright != 64'h00000000f784bf8f) $stop;
end
if (cyc==6) begin
amt <= 32'd64;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h000000007bc25fc7) $stop;
if (qright != 64'h000000007bc25fc7) $stop;
end
if (cyc==7) begin
amt <= 32'd128;
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==8) begin
if (left != 32'h0) $stop;
if (right != 32'h0) $stop;
if (qleft != 64'h0) $stop;
if (qright != 64'h0) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; bool fun(int n) { if (n == 1) return false; if (n == 2) return true; if (n % 2 == 0) return false; for (int i = 2; i * i <= n; i++) { if (n % i == 0) return false; } return true; } int main() { int n; scanf( %d , &n); if (fun(n)) printf( 1 n ); else if (n & 1) { if (fun(n - 2)) { printf( 2 n ); } else printf( 3 n ); } else printf( 2 n ); }
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// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////////////////////////
//
// This module facilitates a transition between two clock domains. We assume that the input
// is provided in the clock domain in parallel (1 data set) and is to be serialized into two
// subsequent transactions in the clock2x domain.
//
// Note that this operation consumes 4 clock2x cycles. Thus a mirror operation will have to do the
// same, or the data will become desynchronized.
//
///////////////////////////////////////////////////////////////////////////////////////////////////
module acl_vector_to_stream_converter_single(
clock, clock2x, resetn, start,
a1, a2, dataa,
valid_in, valid_out, stall_in, stall_out);
parameter WIDTH = 32;
input clock, clock2x, resetn, valid_in, stall_in, start;
input [WIDTH-1:0] a1;
input [WIDTH-1:0] a2;
output [WIDTH-1:0] dataa;
output valid_out;
output stall_out;
// Put a staging register on inputs
reg [WIDTH-1:0] a1_sr /* synthesis preserve */;
reg [WIDTH-1:0] a2_sr /* synthesis preserve */;
reg sr_in_valid /* synthesis preserve */;
wire stall_sr;
assign stall_out = sr_in_valid;
reg start_reg /* synthesis preserve */;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
sr_in_valid <= 1'b0;
start_reg <= 1'b0;
a1_sr <= {WIDTH{1'bx}};
a2_sr <= {WIDTH{1'bx}};
end
else
begin
start_reg <= start;
if (~stall_sr | start)
sr_in_valid <= 1'b0;
else if (~sr_in_valid)
sr_in_valid <= valid_in;
if (~sr_in_valid)
begin
a1_sr <= a1;
a2_sr <= a2;
end
end
end
// Prevent sharing of these registers across different instances
// (and even kernels!). The sharing may cause very long paths
// across the chip, which limits fmax of clock2x.
reg sel2x, sel_ref /* synthesis preserve */;
initial
begin
sel2x = 1'b0;
sel_ref = 1'b0;
end
always@(posedge clock2x)
begin
sel2x <= ~sel2x;
end
// Register the data in the 'clock' domain.
reg [WIDTH-1:0] a1_reg /* synthesis preserve */;
reg [WIDTH-1:0] a2_reg /* synthesis preserve */;
reg valid_reg /* synthesis preserve */;
wire stall_reg;
assign stall_sr = valid_reg & stall_reg;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
sel_ref <= 1'b0;
valid_reg <= 1'b0;
a1_reg <= {WIDTH{1'bx}};
a2_reg <= {WIDTH{1'bx}};
end
else
begin
sel_ref <= sel2x;
if (start)
valid_reg <= 1'b0;
else if (~valid_reg | ~stall_reg)
valid_reg <= valid_in | sr_in_valid;
if (~valid_reg | ~stall_reg)
begin
a1_reg <= sr_in_valid ? a1_sr : a1;
a2_reg <= sr_in_valid ? a2_sr : a2;
end
end
end
// Clock 2X domain
reg [WIDTH-1:0] shift_reg_a1 /* synthesis preserve */;
reg [WIDTH-1:0] shift_reg_a2 /* synthesis preserve */;
reg read_data /* synthesis preserve */;
reg valid_a1, valid_a2 /* synthesis preserve */;
reg start_reg_2x /* synthesis preserve */;
wire stall_shift;
assign stall_reg = ~read_data;
wire w;
assign w = (sel_ref == sel2x);
always@(posedge clock2x or negedge resetn)
begin
if (~resetn)
begin
start_reg_2x <= 1'b0;
valid_a1 <= 1'b0;
valid_a2 <= 1'b0;
read_data <= 1'b0;
shift_reg_a1 <= {WIDTH{1'bx}};
shift_reg_a2 <= {WIDTH{1'bx}};
end
else
begin
start_reg_2x <= start_reg;
// There are two cases: when we have a clock cycle right after the positive
// edge of clock and right after negative edge of clock. Treat them separately.
if (~w)
begin
// This is right after positive edge of 'clock'.
if (~valid_a1)
begin
// Load only in the cycle after the data is provided to the input registers
valid_a1 <= valid_reg & ~start_reg_2x;
valid_a2 <= valid_reg & ~start_reg_2x;
shift_reg_a1 <= a1_reg;
shift_reg_a2 <= a2_reg;
// Now signal the 1X clock domain that you read its data.
read_data <= valid_reg;
end
else if (~stall_shift)
begin
// If data was already present in the shift register, then shift it over.
// However, if we are about to shift out the last element, the we may as well load data from
// 1X clock domain.
if (~valid_a2)
begin
// The shift-register is about to become empty. So we can just shift
// in new data if it is available.
valid_a1 <= valid_reg & ~start_reg_2x;
valid_a2 <= valid_reg & ~start_reg_2x;
shift_reg_a1 <= a1_reg;
shift_reg_a2 <= a2_reg;
read_data <= valid_reg;
end
else
begin
// Otherwise, just shift the data over.
valid_a1 <= valid_a2 & ~start_reg_2x;
valid_a2 <= 1'b0;
shift_reg_a1 <= shift_reg_a2;
shift_reg_a2 <= {WIDTH{1'b0}};
read_data <= 1'b0;
end
end
else
read_data <= 1'b0;
end
else
begin
// This is right after negative edge of the clock.
// Now if at all possible, shift the data over by one position.
if (~stall_shift)
begin
// Otherwise, just shift the data over.
valid_a1 <= valid_a2 & ~start_reg_2x;
valid_a2 <= 1'b0;
shift_reg_a1 <= shift_reg_a2;
shift_reg_a2 <= {WIDTH{1'b0}};
end
else
begin
valid_a1 <= valid_a1 & ~start_reg_2x;
valid_a2 <= valid_a2 & ~start_reg_2x;
end
end
end
end
// Adding a staging register at the output.
//reg [WIDTH-1:0] dataa_sr /* synthesis preserve */;
//reg sr_valid /* synthesis preserve */;
//always@(posedge clock2x or negedge resetn)
//begin
// if (~resetn)
// begin
// sr_valid <= 1'b0;
// dataa_sr <= {WIDTH{1'bx}};
// end
// else
// begin
// if (~stall_in | start_reg_2x)
// sr_valid <= 1'b0;
// else if (~sr_valid)
// sr_valid <= valid_a1;
//
// if (~sr_valid)
// dataa_sr <= shift_reg_a1;
// end
//end
//assign stall_shift = sr_valid;
//assign valid_out = sr_valid | valid_a1;
//assign dataa = sr_valid ? dataa_sr : shift_reg_a1;
assign dataa = shift_reg_a1;
assign stall_shift = stall_in;
assign valid_out = valid_a1;
endmodule
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