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#include <bits/stdc++.h> using namespace std; const int N = 600005; int n, m, l, r, ma, a[N], f[N][22]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d%d , &l, &r); a[l] = max(a[l], r); ma = max(ma, r); } for (int i = 1; i <= ma; i++) a[i] = max(a[i], a[i - 1]); for (int i = 0; i <= ma; i++) f[i][0] = a[i]; for (int i = 1; i <= 20; i++) for (int j = 0; j <= ma; j++) f[j][i] = f[f[j][i - 1]][i - 1]; while (m--) { cin >> l >> r; int ans = 0; for (int i = 20; i >= 0; i--) if (f[l][i] < r) { ans += 1 << i; l = f[l][i]; } if (a[l] >= r) printf( %d n , ans + 1); else cout << -1 << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 2020; vector<tuple<int, int, int> > edges; vector<int> g[N]; vector<int> back_edge[N]; bool global; int num[N], low[N], low2[N], cnt, pai[N], pw[N], aux[N], prev_pai[N], prev_pw[N], sobe[N], prev_sobe[N]; int edg_used, edg_u, edg_v, edg_w; void dfs(int u) { num[u] = low[u] = ++cnt; bool flag = false; for (auto w : g[u]) { int x, v, p; tie(x, v, p) = edges[w]; if (v == u) swap(v, x); if (edg_used == w) continue; if (!num[v]) { pai[v] = u; pw[v] = p; sobe[v] = w; dfs(v); low[u] = min(low[u], low[v]); } else if (flag or pai[u] != v) { low[u] = min(low[u], num[v]); if (!global and num[u] > num[v]) back_edge[u].push_back(w); } else if (pai[u] == v) flag = true; } } int main(void) { int n, m; scanf( %d %d , &n, &m); int s, t; scanf( %d %d , &s, &t); for (int i = 0; i < m; i++) { int u, v, w; scanf( %d %d %d , &u, &v, &w); g[u].push_back(i); g[v].push_back(i); edges.emplace_back(u, v, w); } edg_used = -1; dfs(s); global = true; int S = s; if (!low[t]) { printf( 0 n0 n ); return 0; } int ans = 0x3f3f3f3f; int edg; int v = t; while (v != s) { int u = pai[v]; if (low[v] > num[u]) { if (pw[v] < ans) edg = sobe[v]; ans = min(ans, pw[v]); } v = u; } int dupla = INT_MAX; int x, y; for (int i = 1; i <= n; i++) { if (back_edge[i].empty()) continue; int k = 0, ans = 0x3f3f3f3f; for (int j = 0; j < back_edge[i].size(); j++) { int e = back_edge[i][j]; int x, v, p; tie(x, v, p) = edges[e]; if (v == i) swap(v, x); if (num[v] < ans) k = j; } vector<int> c[5]; cnt = 0; for (int j = 1; j <= n; j++) { c[0].push_back(num[j]); c[1].push_back(low[j]); c[2].push_back(pai[j]); c[3].push_back(pw[j]); c[4].push_back(sobe[j]); num[j] = low[j] = 0; } tie(edg_u, edg_v, edg_w) = edges[back_edge[i][k]]; edg_used = back_edge[i][k]; dfs(s); ans = 0x3f3f3f3f; int v = t, edg; while (v != s) { int u = pai[v]; if (low[v] > num[u]) { if (pw[v] < ans) edg = sobe[v]; ans = min(ans, pw[v]); } v = u; } if (ans != 0x3f3f3f3f and ans + edg_w < dupla) { dupla = ans + edg_w; x = back_edge[i][k]; y = edg; } for (int j = 1; j <= n; j++) { num[j] = c[0][j - 1]; low[j] = c[1][j - 1]; pai[j] = c[2][j - 1]; pw[j] = c[3][j - 1]; sobe[j] = c[4][j - 1]; } } for (int i = 1; i <= n; i++) { prev_pai[i] = pai[i]; prev_pw[i] = pw[i]; prev_sobe[i] = sobe[i]; } for (int i = 1; i <= n; i++) { if (i == s) continue; cnt = 0; for (int j = 1; j <= n; j++) num[j] = low[j] = 0; tie(edg_u, edg_v, edg_w) = edges[prev_sobe[i]]; edg_used = prev_sobe[i]; dfs(s); if (!low[t]) continue; int ans = 0x3f3f3f3f, v = t, edg; while (v != s) { int u = pai[v]; if (low[v] > num[u]) { if (pw[v] < ans) edg = sobe[v]; ans = min(ans, pw[v]); } v = u; } if (ans != 0x3f3f3f3f and ans + edg_w < dupla) { dupla = ans + edg_w; x = prev_sobe[i]; y = edg; } } if (ans == 0x3f3f3f3f and dupla == INT_MAX) { printf( -1 n ); } else if (ans < dupla and ans != 0x3f3f3f3f) printf( %d n1 n%d n , ans, edg + 1); else printf( %d n2 n%d %d n , dupla, x + 1, y + 1); return 0; }
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`timescale 1ns / 1ps
module DataMemory(
output reg [31:0] ReadData,
output reg [31:0] DATO1,
output reg [31:0] DATO2,
output reg [31:0] RESULTADO,
input [31:0] Address,
input [31:0] WriteData,
input [31:0] MouseData,
input MouseEnable,
input WriteEnable,
input CLK
);
reg [31:0] block [0:9];
always @ (*) begin
DATO1 = block[4];
DATO2 = block[5];
RESULTADO = block[7];
if (CLK) begin
case (Address)
32'h00000000: ReadData = block[0];
32'h00000004: ReadData = block[1];
32'h00000008: ReadData = block[2];
32'h0000000c: ReadData = block[3];
32'h00000010: ReadData = block[4];
32'h00000014: ReadData = block[5];
32'h00000018: ReadData = block[6];
32'h0000001c: ReadData = block[7];
32'h00000020: ReadData = block[8];
32'h00000024: ReadData = block[9];
default: ReadData = 32'b0;
endcase
end
else begin
if (MouseEnable) begin
block[1] = MouseData;
end
if (WriteEnable)
case (Address)
32'h00000000: block[0] = WriteData;
32'h00000004: block[1] = WriteData;
32'h00000008: block[2] = WriteData;
32'h0000000c: block[3] = WriteData;
32'h00000010: block[4] = WriteData;
32'h00000014: block[5] = WriteData;
32'h00000018: block[6] = WriteData;
32'h0000001c: block[7] = WriteData;
32'h00000020: block[8] = WriteData;
32'h00000024: block[9] = WriteData;
endcase
end
end
integer i = 0;
initial begin
for (i=0;i<10;i=i+1)
block[i] = 32'b0;
block[1] = 2;
block[4] = 2;
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 15; long long Get_Num(int num[], int b, int n) { long long number = 0; long long in = 1; for (int i = n - 1; i >= 0; i--) { number += num[i] * in; in = in * b; } return number; } int main() { int x[N], y[N]; int b; int n; long long X, Y; cin >> n >> b; for (int i = 0; i < n; i++) { cin >> x[i]; } X = Get_Num(x, b, n); cin >> n >> b; for (int i = 0; i < n; i++) { cin >> y[i]; } Y = Get_Num(y, b, n); if (X == Y) { printf( = n ); } else if (X > Y) { printf( > n ); } else { printf( < n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_M_V
`define SKY130_FD_SC_LP__INVLP_M_V
/**
* invlp: Low Power Inverter.
*
* Verilog wrapper for invlp with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__invlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invlp_m (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__invlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invlp_m (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__invlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_M_V
|
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module B100
(input CLK_FPGA_P, input CLK_FPGA_N, // Diff
output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
// GPIF
inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output GPIF_SLOE,
output [1:0] GPIF_ADR, output GPIF_SLWR, output GPIF_SLRD, output GPIF_PKTEND,
input IFCLK,
inout SDA_FPGA, inout SCL_FPGA, // I2C
output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, // DB TX SPI
output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, // DB TX SPI
output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC, // AD9862 main SPI
input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
inout [15:0] io_tx, inout [15:0] io_rx,
output [13:0] dac, output TXSYNC, output TXBLANK,
input [11:0] adc, input RXSYNC,
input PPS_IN,
input reset_n, output reset_codec,
input ext_reset
);
assign reset_codec = 1; // Believed to be active low
// /////////////////////////////////////////////////////////////////////////
// Clocking
wire clk_fpga, clk_fpga_in, reset;
wire gpif_clk = IFCLK;
wire gpif_rst;
IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga));
reset_sync reset_sync(.clk(clk_fpga), .reset_in((~reset_n) | (~ext_reset)), .reset_out(reset));
reset_sync reset_sync_gpif(.clk(gpif_clk), .reset_in((~reset_n) | (~ext_reset)), .reset_out(gpif_rst));
// /////////////////////////////////////////////////////////////////////////
// SPI
wire mosi, sclk, miso;
assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0;
assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0;
assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0;
assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) |
(~SEN_CODEC & MISO_CODEC);
// /////////////////////////////////////////////////////////////////////////
// TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
assign TXBLANK = 0;
wire [13:0] tx_i, tx_q;
genvar i;
generate
for(i=0;i<14;i=i+1)
begin : gen_dacout
ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
ODDR2_inst (.Q(dac[i]), // 1-bit DDR output data
.C0(clk_fpga), // 1-bit clock input
.C1(~clk_fpga), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(tx_i[i]), // 1-bit data input (associated with C0)
.D1(tx_q[i]), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0)); // 1-bit set input
end // block: gen_dacout
endgenerate
ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data
.C0(clk_fpga), // 1-bit clock input
.C1(~clk_fpga), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b0), // 1-bit data input (associated with C0)
.D1(1'b1), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0)); // 1-bit set input
// /////////////////////////////////////////////////////////////////////////
// RX ADC -- handles deinterleaving
wire rxsync_0, rxsync_1;
reg [11:0] rx_i, rx_q;
wire [11:0] rx_a, rx_b;
genvar j;
generate
for(j=0;j<12;j=j+1)
begin : gen_adcin
IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1
.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
IDDR2_inst (.Q0(rx_a[j]), // 1-bit output captured with C0 clock
.Q1(rx_b[j]), // 1-bit output captured with C1 clock
.C0(clk_fpga), // 1-bit clock input
.C1(~clk_fpga), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(adc[j]), // 1-bit DDR data input
.R(1'b0), // 1-bit reset input
.S(1'b0)); // 1-bit set input
end // block: gen_adcin
endgenerate
IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1
.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
IDDR2_sync (.Q0(rxsync_0), // 1-bit output captured with C0 clock
.Q1(rxsync_1), // 1-bit output captured with C1 clock
.C0(clk_fpga), // 1-bit clock input
.C1(~clk_fpga), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D(RXSYNC), // 1-bit DDR data input
.R(1'b0), // 1-bit reset input
.S(1'b0)); // 1-bit set input
always @(posedge clk_fpga)
if(rxsync_0)
begin
rx_i <= ~rx_b;
rx_q <= ~rx_a;
end
else
begin
rx_i <= ~rx_a;
rx_q <= ~rx_b;
end
// /////////////////////////////////////////////////////////////////////////
// Main Core
wire [35:0] rx_data, tx_data, ctrl_data, resp_data;
wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy;
wire dsp_rx_run, dsp_tx_run;
wire [7:0] sen8;
assign {SEN_CODEC,SEN_TX_DB,SEN_RX_DB} = sen8[2:0];
wire [31:0] core_debug;
assign debug_led = {dsp_tx_run, dsp_rx_run, cgen_st_ld};
wire cgen_sync;
assign { cgen_sync_b, cgen_ref_sel } = {~cgen_sync, 1'b1};
u1plus_core #(
`ifdef NUM_RX_DSP
.NUM_RX_DSPS(`NUM_RX_DSP),
`else
.NUM_RX_DSPS(1),
`endif
.DSP_RX_XTRA_FIFOSIZE(11),
.DSP_TX_XTRA_FIFOSIZE(12),
.USE_PACKET_PADDER(1)
) core(
.clk(clk_fpga), .reset(reset),
.debug(core_debug), .debug_clk(debug_clk),
.rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
.tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
.ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
.resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
.dsp_rx_run(dsp_rx_run), .dsp_tx_run(dsp_tx_run),
.clock_sync(cgen_sync),
.db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
.sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso),
.io_tx(io_tx), .io_rx(io_rx),
.tx_i(tx_i), .tx_q(tx_q),
.rx_i(rx_i), .rx_q(rx_q),
.pps_in(PPS_IN) );
// /////////////////////////////////////////////////////////////////////////
// Interface from host to/from GPIF
wire [31:0] gpif_debug;
slave_fifo slave_fifo (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(GPIF_D),
.gpif_ctl(GPIF_CTL), .sloe(GPIF_SLOE), .slwr(GPIF_SLWR), .slrd(GPIF_SLRD),
.pktend(GPIF_PKTEND), .fifoadr(GPIF_ADR),
.fifo_clk(clk_fpga), .fifo_rst(reset),
.rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
.tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
.ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
.resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
.debug(gpif_debug));
//assign debug = gpif_debug;
assign debug = core_debug;
endmodule // B100
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 18 23:19:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_stub.v
// Design : system_vga_color_test_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_color_test,Vivado 2016.4" *)
module system_vga_color_test_0_0(clk_25, xaddr, yaddr, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_25,xaddr[9:0],yaddr[9:0],rgb[23:0]" */;
input clk_25;
input [9:0]xaddr;
input [9:0]yaddr;
output [23:0]rgb;
endmodule
|
#include <bits/stdc++.h> using namespace std; int myrand(int m) { return (rand() * (1 << 15) + rand()) % m; } int main() { srand(time(0)); int n, ind, x; cin >> n >> ind >> x; --ind; vector<int> left(n); vector<bool> vis(n, 0); for (int i = 0; i < n; ++i) left[i] = i; vis[ind] = 1; random_shuffle(left.begin(), left.end()); int best = -1; for (int i = 0; i < min(1000, n); ++i) { int v, ii = left[i]; cout << ? << ii + 1 << n ; fflush(stdout); cin >> v >> ii; if (v < x && v > best) { ind = left[i]; best = max(best, v); } } if (ind < 0) { cout << ! -1 n ; fflush(stdout); return 0; } int itt, LIM = 999; for (itt = 0; itt < LIM; ++itt) { cout << ? << ind + 1 << n ; fflush(stdout); int v; cin >> v >> ind; --ind; if (v >= x) { best = v; break; } if (ind < 0) break; } if (itt == LIM) { int j = 1; while (1) { j = j + 1; } } cout << ! << ((best < x) ? -1 : best) << n ; fflush(stdout); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2B_SYMBOL_V
`define SKY130_FD_SC_MS__AND2B_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2B_SYMBOL_V
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#include <bits/stdc++.h> using namespace std; using i64 = long long; constexpr int MAX = 400010; constexpr int MOD = 1000000007; i64 fac[MAX], inv[MAX]; int l[MAX], r[MAX], x[MAX], cnt[MAX]; i64 ModPow(i64 a, i64 b, i64 p = MOD) { i64 ret = 1; for (a %= p; b; b >>= 1) { if (b & 1) ret = ret * a % p; a = a * a % p; } return ret; } inline i64 Inv(i64 x, i64 p = MOD) { return ModPow(x, p - 2, p); } void Init() { fac[0] = 1; inv[0] = 1; for (int i = 1; i < MAX; ++i) { fac[i] = fac[i - 1] * i % MOD; inv[i] = Inv(fac[i]); } } inline i64 C(int n, int m) { return n < m ? 0 : fac[n] * inv[m] % MOD * inv[n - m] % MOD; } i64 Solve(int n, int k) { int m = 0; for (int i = 0; i < n; ++i) { l[i] <<= 1; r[i] = ((r[i] << 1) | 1); x[m++] = l[i]; x[m++] = r[i]; } sort(x, x + m); int a = x[0], b = x[m - 1]; x[m++] = a - 1; x[m++] = b + 1; sort(x, x + m); m = unique(x, x + m) - x; memset(cnt, 0, sizeof(cnt)); for (int i = 0; i < n; ++i) { int u = lower_bound(x, x + m, l[i]) - x; int v = lower_bound(x, x + m, r[i]) - x; ++cnt[u]; --cnt[v]; } i64 ret = 0; for (int i = 1; i < m - 1; ++i) { cnt[i] += cnt[i - 1]; if (cnt[i] >= k) { int u = ((x[i + 1] + 1) >> 1), v = ((x[i] + 1) >> 1); int d = u - v; i64 cur = C(cnt[i], k) * d % MOD; ret = (ret + cur) % MOD; } } return ret; } int main() { Init(); int n, k; while (~scanf( %d%d , &n, &k)) { for (int i = 0; i < n; ++i) { scanf( %d%d , &l[i], &r[i]); } printf( %d n , (int)Solve(n, k)); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const double pi = acos(-1.0); struct Complex { double x, y; Complex(double x = 0.0, double y = 0.0) { this->x = x; this->y = y; } Complex operator-(const Complex &b) const { return Complex(x - b.x, y - b.y); } Complex operator+(const Complex &b) const { return Complex(x + b.x, y + b.y); } Complex operator*(const Complex &b) const { return Complex(x * b.x - y * b.y, x * b.y + y * b.x); } }; void change(Complex y[], int len) { for (int i = 1, j = len / 2; i < len - 1; i++) { if (i < j) swap(y[i], y[j]); int k = len / 2; while (j >= k) { j -= k; k /= 2; } if (j < k) j += k; } } void fft(Complex y[], int len, int on) { change(y, len); for (int h = 2; h <= len; h <<= 1) { Complex wn(cos(-on * 2 * pi / h), sin(-on * 2 * pi / h)); for (int j = 0; j < len; j += h) { Complex w(1, 0); for (int k = j; k < j + h / 2; k++) { Complex u = y[k]; Complex t = w * y[k + h / 2]; y[k] = u + t; y[k + h / 2] = u - t; w = w * wn; } } } if (on == -1) for (int i = 0; i < len; i++) y[i].x /= len; } int n, m, k, i, j, p[30]; Complex A[N], B[N], C[N]; int a[N], b[N]; char sa[N], sb[N]; int main() { for (i = 1; i <= 26; i++) scanf( %d , &p[i]); scanf( %s %s , sa, sb); m = strlen(sa), n = strlen(sb); for (i = 0, j = m - 1; i < j; i++, j--) swap(sa[i], sa[j]); for (i = 0; i < m; i++) a[i] = sa[i] - a + 1; for (i = 0; i < n; i++) b[i] = sb[i] - a + 1; for (k = 1; k < n; k <<= 1) ; for (i = 0; i < k; i++) A[i] = Complex(2 * a[i] * p[a[i]] * (a[i] + p[a[i]]), 0), B[i] = Complex(b[i], 0); for (fft(A, k, 1), fft(B, k, 1), i = 0; i < k; i++) C[i] = C[i] - A[i] * B[i]; for (i = 0; i < k; i++) A[i] = Complex(a[i] * a[i] + p[a[i]] * p[a[i]] + 4 * a[i] * p[a[i]], 0), B[i] = Complex(b[i] * b[i], 0); for (fft(A, k, 1), fft(B, k, 1), i = 0; i < k; i++) C[i] = C[i] + A[i] * B[i]; for (i = 0; i < k; i++) A[i] = Complex(2 * (a[i] + p[a[i]]), 0), B[i] = Complex(b[i] * b[i] * b[i], 0); for (fft(A, k, 1), fft(B, k, 1), i = 0; i < k; i++) C[i] = C[i] - A[i] * B[i]; for (i = 0; i < k; i++) { if (i < m) A[i] = Complex(1, 0); else A[i] = Complex(0, 0); B[i] = Complex(b[i] * b[i] * b[i] * b[i], 0); } for (fft(A, k, 1), fft(B, k, 1), i = 0; i < k; i++) C[i] = C[i] + A[i] * B[i]; for (i = 0; i < k; i++) { A[i] = Complex(a[i] * a[i] * p[a[i]] * p[a[i]], 0); if (i < n) B[i] = Complex(1, 0); else B[i] = Complex(0, 0); } for (fft(A, k, 1), fft(B, k, 1), i = 0; i < k; i++) C[i] = C[i] + A[i] * B[i]; fft(C, k, -1); for (int i = 0; i < n - m + 1; i++) printf( %d , ((long long)(C[i + m - 1].x + 0.5) == 0)); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long mxn = 1e5 + 7; int main() { int n, a[mxn], q, l[mxn], r[mxn], x; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= n; i++) { if (i == 1) { l[i] = 1; r[i] = a[i]; } else { l[i] = r[i - 1] + 1; r[i] = a[i] + r[i - 1]; } } cin >> q; for (int i = 1; i <= q; i++) { int l1 = 0, r1 = n, x; cin >> x; while (r1 - l1 > 1) { int m = (l1 + r1) >> 1; if (r[m] >= x) r1 = m; else l1 = m; } cout << r1 << endl; } }
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//======================================================================
//
// sha3.v
// --------
// Top level wrapper for the SHA-3 hash function core providing
// a simple memory like interface with 32 bit data access.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module sha3(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam STATUS_ERROR_BIT = 2;
localparam ADDR_BLOCK00 = 8'h10;
localparam ADDR_BLOCK31 = 8'h2f;
localparam ADDR_DIGEST00 = 8'h40;
localparam ADDR_DIGEST15 = 8'h4f;
localparam CORE_NAME0 = 32'h7368612d; // "sha-"
localparam CORE_NAME1 = 32'h33202020; // "3 "
localparam CORE_VERSION = 32'h302e3130; // "0.10"
localparam MODE_SHA3_224 = 2'h0;
localparam MODE_SHA3_256 = 2'h1;
localparam MODE_SHA3_384 = 2'h2;
localparam MODE_SHA3_512 = 2'h3;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg [1 : 0] mode_reg;
reg [1 : 0] mode_new;
reg mode_we;
reg ready_reg;
reg [31 : 0] block_reg [0 : 31];
reg [4 : 0] block_addr;
reg block_we;
reg [511 : 0] digest_reg;
reg [7 : 0] digest_addr;
reg digest_valid_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire core_init;
wire core_next;
wire [1 : 0] core_mode;
wire core_work_factor;
wire [31 : 0] core_work_factor_num;
wire core_ready;
wire [1023 : 0] core_block;
wire [511 : 0] core_digest;
wire core_digest_valid;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_init = init_reg;
assign core_next = next_reg;
assign core_mode = mode_reg;
assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
block_reg[04], block_reg[04], block_reg[05], block_reg[07],
block_reg[08], block_reg[09], block_reg[10], block_reg[11],
block_reg[12], block_reg[13], block_reg[14], block_reg[15],
block_reg[16], block_reg[17], block_reg[18], block_reg[19],
block_reg[20], block_reg[21], block_reg[22], block_reg[23],
block_reg[24], block_reg[24], block_reg[25], block_reg[27],
block_reg[28], block_reg[29], block_reg[30], block_reg[31]};
assign read_data = tmp_read_data;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
sha3_core core(
.clk(clk),
.reset_n(reset_n),
.init(core_init),
.next(core_next),
.mode(core_mode),
.block(core_block),
.ready(core_ready),
.digest(core_digest),
.digest_valid(core_digest_valid)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
init_reg <= 0;
next_reg <= 0;
mode_reg <= MODE_SHA3_256;
ready_reg <= 0;
digest_reg <= 512'h0;
digest_valid_reg <= 0;
for (i = 0 ; i < 32 ; i = i + 1)
block_reg[i] = 32'h0;
end
else
begin
ready_reg <= core_ready;
digest_valid_reg <= core_digest_valid;
init_reg <= init_new;
next_reg <= next_new;
if (mode_we)
mode_reg <= write_data[3 : 2];
if (core_digest_valid)
digest_reg <= core_digest;
if (block_we)
block_reg[block_addr] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// api_logic
//
// Implementation of the api logic. If cs is enabled will either
// try to write to or read from the internal registers.
//----------------------------------------------------------------
always @*
begin : api_logic
init_new = 0;
next_new = 0;
mode_we = 0;
block_we = 0;
tmp_read_data = 32'h0;
block_addr = address - ADDR_BLOCK00;
digest_addr = 8'h10 - (address - ADDR_DIGEST00);
if (cs)
begin
if (we)
begin
if ((address >= ADDR_BLOCK00) && (address <= ADDR_BLOCK31))
block_we = 1;
case (address)
// Write operations.
ADDR_CTRL:
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
mode_we = 1;
end
default:
begin
end
endcase // case (address)
end // if (we)
else
begin
if ((address >= ADDR_BLOCK00) && (address <= ADDR_BLOCK31))
tmp_read_data = block_reg[block_addr];
// TODO: Fix mux construction for digest.
if ((address >= ADDR_DIGEST00) && (address <= ADDR_DIGEST15))
tmp_read_data = digest_reg[32 * digest_addr -: 32];
case (address)
// Read operations.
ADDR_NAME0:
tmp_read_data = CORE_NAME0;
ADDR_NAME1:
tmp_read_data = CORE_NAME1;
ADDR_VERSION:
tmp_read_data = CORE_VERSION;
ADDR_CTRL:
tmp_read_data = {28'h0, mode_reg, next_reg, init_reg};
ADDR_STATUS:
tmp_read_data = {30'h0, digest_valid_reg, ready_reg};
default:
begin
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // sha3
//======================================================================
// EOF sha3.v
//======================================================================
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#include <bits/stdc++.h> using namespace std; struct Solve { bool mark[(int)(3e5 + 10)]; vector<pair<int, int>> ed[(int)(3e5 + 10)]; vector<int> mtch; int n, m, T; void go() { T = 0; input(); find_mx_match(); if (T >= 2 * n) prnt_match(); else prnt_ind(); } void input() { cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--, v--; ed[u].push_back({v, i + 1}); ed[v].push_back({u, i + 1}); } } void find_mx_match() { for (int i = 0; i < 3 * n; i++) { if (mark[i]) continue; for (auto x : ed[i]) { if (mark[x.first]) continue; mark[x.first] = mark[i] = true; mtch.push_back(x.second); T += 2; break; } } } void prnt_match() { cout << Matching n ; int I = 0; for (auto x : mtch) { if (I == n) break; cout << x << ; I++; } cout << endl; } void prnt_ind() { cout << IndSet n ; for (int I = 0, J = 0; I < 3 * n && J < n; I++) { if (!mark[I]) { cout << I + 1 << ; J++; } } cout << endl; } void clear() { T = 0; for (int i = 0; i < 3 * n; i++) mark[i] = false; for (int i = 0; i < 3 * n; i++) ed[i].clear(); n = -1, m = -1; mtch.clear(); } } S; int main() { ios::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); int T; cin >> T; while (T--) { S.go(); S.clear(); } return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; template <class t, class u> void chmax(t& first, u second) { if (first < second) first = second; } template <class t, class u> void chmin(t& first, u second) { if (second < first) first = second; } template <class t> using vc = vector<t>; template <class t> using vvc = vc<vc<t>>; using pi = pair<int, int>; using vi = vc<int>; template <class t, class u> ostream& operator<<(ostream& os, const pair<t, u>& p) { return os << { << p.first << , << p.second << } ; } template <class t> ostream& operator<<(ostream& os, const vc<t>& v) { os << { ; for (auto e : v) os << e << , ; return os << } ; } using uint = unsigned; using ull = unsigned long long; template <int i, class T> void print_tuple(ostream&, const T&) {} template <int i, class T, class H, class... Args> void print_tuple(ostream& os, const T& t) { if (i) os << , ; os << get<i>(t); print_tuple<i + 1, T, Args...>(os, t); } template <class... Args> ostream& operator<<(ostream& os, const tuple<Args...>& t) { os << { ; print_tuple<0, tuple<Args...>, Args...>(os, t); return os << } ; } void print(ll x, int suc = 1) { cout << x; if (suc == 1) cout << n ; if (suc == 2) cout << ; } ll read() { ll i; cin >> i; return i; } vi readvi(int n, int off = 0) { vi v(n); for (int i = int(0); i < int(n); i++) v[i] = read() + off; return v; } template <class T> void print(const vector<T>& v, int suc = 1) { for (int i = int(0); i < int(v.size()); i++) print(v[i], i == int(v.size()) - 1 ? suc : 2); } string readString() { string s; cin >> s; return s; } template <class T> T sq(const T& t) { return t * t; } void yes(bool ex = true) { cout << Yes << endl; if (ex) exit(0); } void no(bool ex = true) { cout << No << endl; if (ex) exit(0); } constexpr ll ten(int n) { return n == 0 ? 1 : ten(n - 1) * 10; } const ll infLL = LLONG_MAX / 3; const int inf = INT_MAX / 2 - 100; int topbit(signed t) { return t == 0 ? -1 : 31 - __builtin_clz(t); } int topbit(ll t) { return t == 0 ? -1 : 63 - __builtin_clzll(t); } int botbit(signed first) { return first == 0 ? 32 : __builtin_ctz(first); } int botbit(ll first) { return first == 0 ? 64 : __builtin_ctzll(first); } int popcount(signed t) { return __builtin_popcount(t); } int popcount(ll t) { return __builtin_popcountll(t); } bool ispow2(int i) { return i && (i & -i) == i; } int mask(int i) { return (int(1) << i) - 1; } bool inc(int first, int second, int c) { return first <= second && second <= c; } template <class t> void mkuni(vc<t>& v) { sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); } ll rand_int(ll l, ll r) { static random_device rd; static mt19937_64 gen(rd()); return uniform_int_distribution<ll>(l, r)(gen); } template <class t> int lwb(const vc<t>& v, const t& first) { return lower_bound(v.begin(), v.end(), first) - v.begin(); } using uint = unsigned; using ull = unsigned long long; const uint mod = 998244353; struct mint { uint v; mint(ll vv = 0) { s(vv % mod + mod); } mint& s(uint vv) { v = vv < mod ? vv : vv - mod; return *this; } mint operator-() const { return mint() - *this; } mint& operator+=(const mint& rhs) { return s(v + rhs.v); } mint& operator-=(const mint& rhs) { return s(v + mod - rhs.v); } mint& operator*=(const mint& rhs) { v = ull(v) * rhs.v % mod; return *this; } mint& operator/=(const mint& rhs) { return *this *= rhs.inv(); } mint operator+(const mint& rhs) const { return mint(*this) += rhs; } mint operator-(const mint& rhs) const { return mint(*this) -= rhs; } mint operator*(const mint& rhs) const { return mint(*this) *= rhs; } mint operator/(const mint& rhs) const { return mint(*this) /= rhs; } mint pow(int n) const { mint res(1), x(*this); while (n) { if (n & 1) res *= x; x *= x; n >>= 1; } return res; } mint inv() const { return pow(mod - 2); } friend ostream& operator<<(ostream& os, const mint& m) { return os << m.v; } bool operator<(const mint& r) const { return v < r.v; } bool operator==(const mint& r) const { return v == r.v; } }; const int vmax = (1 << 21) + 10; mint fact[vmax], finv[vmax], invs[vmax]; void initfact() { fact[0] = 1; for (int i = int(1); i < int(vmax); i++) { fact[i] = fact[i - 1] * i; } finv[vmax - 1] = fact[vmax - 1].inv(); for (int i = vmax - 2; i >= 0; i--) { finv[i] = finv[i + 1] * (i + 1); } for (int i = vmax - 1; i >= 1; i--) { invs[i] = finv[i] * fact[i - 1]; } } mint choose(int n, int k) { return fact[n] * finv[n - k] * finv[k]; } mint binom(int first, int second) { return fact[first + second] * finv[first] * finv[second]; } mint catalan(int n) { return binom(n, n) - (n - 1 >= 0 ? binom(n - 1, n + 1) : 0); } const int nmax = 4010; const int K = 40; vi t[nmax]; mint dp[nmax][K]; vc<mint> buf; mint work[K][K]; void dfs(int v, int p) { for (auto c : t[v]) if (c != p) dfs(c, v); memset(work, 0, sizeof(work)); work[0][0] = 1; for (int us = int(0); us < int(K - 1); us++) { for (auto c : t[v]) if (c != p) { for (int i = int(0); i < int(K); i++) { for (int j = int(0); j < int(K - i - 1); j++) { work[us + 1][i + j + 1] += work[us][i] * dp[c][j]; } } } } buf[0] += 1; for (int us = int(0); us < int(K); us++) for (int i = int(0); i < int(K); i++) dp[v][i] += work[us][i]; for (int us = int(1); us < int(K); us++) { for (int i = int(1); i < int(K); i++) if (work[us][i].v) { for (int j = int(2); j < int(min((K - 1) / us, (K - 1) / i) + 1); j++) { work[us * j][i * j] -= work[us][i]; } for (int j = int(1); j < int(min((K - 1) / us, (K - 1) / i) + 1); j++) { buf[i * j] += work[us][i] * i * 2 * invs[us]; } } } } signed main() { cin.tie(0); ios::sync_with_stdio(0); cout << fixed << setprecision(20); initfact(); int n[2]; for (int i = int(0); i < int(2); i++) cin >> n[i]; int k; cin >> k; if (k % 2) { cout << 0 << endl; return 0; } k /= 2; vc<mint> x[2]; for (int w = int(0); w < int(2); w++) { for (int i = int(0); i < int(n[w]); i++) t[i].clear(); memset(dp, 0, sizeof(dp)); buf.assign(K, 0); for (int _ = int(0); _ < int(n[w] - 1); _++) { int first, second; cin >> first >> second; first--; second--; t[first].push_back(second); t[second].push_back(first); } dfs(0, -1); x[w] = buf; } void(0); void(0); mint ans = 0; for (int i = int(0); i < int(k + 1); i++) { ans += x[0][i] * x[1][k - i] * choose(k * 2, i * 2); } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; [[maybe_unused]] const int MAX = INT32_MAX, MIN = -INT32_MAX, maxInd = 1E6 + 1E5 + 1; [[maybe_unused]] bool directed = true, end_now = false; bool possible = false; int n, k; struct node_data_structure { int pre = 0, post = 0; bool visited = false, processed = false; } nodes[maxInd]; vector<int> graph[maxInd]; void insert_graph(int pre, int post) { graph[pre].push_back(post); nodes[pre].post++; nodes[post].pre++; if (!directed) { graph[post].push_back(pre); nodes[post].post++; nodes[pre].pre++; } } [[maybe_unused]] void undoVisit() { for (auto &i : nodes) { i.visited = false; i.processed = false; } end_now = false; } void dfs(int u, int ac = 1) { if (end_now) return; if (u > 1E6) { if (u - 1E6 < ac) return; if (u - 1E6 + k > n || u - 1E6 == n) { end_now = true; possible = true; return; } } else { if (u < ac) return; if (u + k > n || u == n) { end_now = true; possible = true; return; } } nodes[u].visited = true; for (int v : graph[u]) { if (!nodes[v].visited) { dfs(v, ac + 1); } } nodes[u].processed = true; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); string s1, s2; cin >> n >> k >> s1 >> s2; for (int i = 1; i < n; i++) { if (i + k <= n) { if (s1[i - 1] == - && s2[i - 1 + k] == - ) { insert_graph(i, 1E6 + i + k); } if (s2[i - 1] == - && s1[i - 1 + k] == - ) { insert_graph(1E6 + i, i + k); } } if (s1[i] == - && s1[i - 1] == - ) { insert_graph(i, i + 1); insert_graph(i + 1, i); } if (s2[i] == - && s2[i - 1] == - ) { insert_graph(1E6 + i, 1E6 + i + 1); insert_graph(1E6 + i + 1, 1E6 + i); } } dfs(1); possible ? cout << YES << endl : cout << NO << endl; return 0; }
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///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//////////////////////////////////////////////////////////////////
// Float to fixed converts floating point numbers to 16.16 sign
//
//
module flt_fx_rnd
(
input [31:0] fp_in, // Floating point in IEEE fmt
output reg [31:0] int_out // Fixed point integer out
);
//
// 24.8, Z.
// 16.16
// 12.8 U,V
//
wire [7:0] bias_exp; /* Real exponent -127 - 128 */
wire [7:0] bias_exp2; /* Real exponent 2's comp */
wire [39:0] fixed_out2; /* 2's complement of fixed out */
wire [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [38:0] int_fixed_out;
reg [31:0] fixed_out;
assign bias_mant = {25'h0001, fp_in[22:0]};
assign bias_exp = fp_in[30:23] - 'd127;
assign bias_exp2 = ~bias_exp + 1;
// infinity or NaN - Don't do anything special, will overflow
always @* begin
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant << bias_exp;
fixed_out = int_fixed_out[38:7] + int_fixed_out[6];
int_out = (fp_in[31]) ? ~fixed_out + 1 : fixed_out;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int Int() { int x; scanf( %d , &x); return x; } long long Long() { long long x; scanf( %lld , &x); return x; } void err(istream_iterator<string> it) { cout << endl; } template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << ; err(++it, args...); } const int N = (int)2e5 + 5; const int maxN = (int)1e6 + 6; const long long Mod = (long long)1e9 + 7; const int inf = (int)2e9; const long long Inf = (long long)1e18; long long dp[20][5][5][11][11]; int n, k; long long call(int pos, int prior, int last, int hump, int uhump) { if (pos == n) { return hump == k and uhump == k - 1; } long long &ret = dp[pos][prior][last][hump][uhump]; if (~ret) return ret; ret = 0; for (int i = 1; i <= 4; ++i) { if (i == last) continue; int f = hump; int first = uhump; if (prior and last) { f += (prior < last and last > i); first += (prior > last and last < i); } ret += call(pos + 1, last, i, f, first); } return ret; } int main() { int test = 1, tc = 0; while (test--) { n = Int(), k = Int(); memset(dp, -1, sizeof dp); long long res = 0; for (int i = 1; i <= 4; ++i) { res += call(1, 0, i, 0, 0); } cout << res << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NAND2_PP_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f, mod = 1000000007; const long long INF = 0x3f3f3f3f3f3f3f3fLL; const double pi = acosl(-1.), eps = 1e-9; inline int power(int a, int b, int m = mod, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } int que(vector<int> a, vector<int> b) { printf( %d %d , a.size(), b.size()); for (auto r : a) cout << r << ; for (auto r : b) cout << r << ; fflush(stdout); int ans; cin >> ans; return ans; } int main() { int T; cin >> T; while (T--) { int n; scanf( %d , &n); vector<int> a, b; a.push_back(1); for (int i = 2; i <= n; i++) b.push_back(i); int t = que(a, b); int st = 1, ed = n; while (st + 1 < ed) { int md = st + ed >> 1; b.clear(); for (int i = 2; i <= md; i++) b.push_back(i); if (que(a, b) == t) ed = md; else st = md; } a.clear(); b.clear(); a.push_back(ed); for (int i = 1; i <= n; i++) if (ed != i) b.push_back(i); t = que(a, b); printf( -1 %d n , t); fflush(stdout); } return 0; }
|
`include "../RF/reg_file.v"
module test;
reg [4:0] readReg1, readReg2, writeReg;
reg [31:0] writeData;
reg regWrite, clk;
wire [31:0] readData1, readData2;
reg_file rf(.readReg1(readReg1),
.readReg2(readReg2),
.writeReg(writeReg),
.writeData(writeData),
.regWrite(regWrite),
.clk(clk),
.readData1(readData1),
.readData2(readData2));
initial begin
$dumpfile("reg_file_wave.vcd");
$dumpvars(0, test);
//$monitor($time, ": readReg1=%5d, readReg2=%5d, writeReg=%5d, writeData=%5d, regWrite=%b, readData1=%5d, readData2=%5d",
// readReg1, readReg2, writeReg, writeData, regWrite, readData1, readData2);
clk = 0;
#5 writeReg = 0; writeData = 10; regWrite = 1;
#5 writeReg = 1;
#5 writeReg = 2;
#5 writeReg = 3;
#5 writeReg = 4;
#5 writeReg = 5;
#5 writeReg = 6;
#5 writeReg = 7;
#5 writeReg = 8;
#5 writeReg = 9;
#5 writeReg = 10;
#5 writeReg = 11;
#5 writeReg = 12;
#5 writeReg = 13;
#5 writeReg = 14;
#5 writeReg = 15;
#5 writeReg = 16;
#5 writeReg = 17;
#5 writeReg = 18;
#5 writeReg = 19;
#5 writeReg = 20;
#5 writeReg = 21;
#5 writeReg = 22;
#5 writeReg = 23;
#5 writeReg = 24;
#5 writeReg = 25;
#5 writeReg = 26;
#5 writeReg = 27;
#5 writeReg = 28;
#5 writeReg = 29;
#5 writeReg = 30;
#5 writeReg = 31;
#5 readReg1 = 0; readReg2 = 2;
#5;
$display(": readReg1=%5d, readReg2=%5d, writeReg=%5d, writeData=%5d, regWrite=%b, readData1=%5d, readData2=%5d",
readReg1, readReg2, writeReg, writeData, regWrite, readData1, readData2);
$finish;
end
always #1 clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; pair<long long, int> arr[N]; long long t[4 * N] = {}; inline void update(int v, int vl, int vr, int pos, long long val) { if (vl == vr) { t[v] = val; return; } int vm = vl + (vr - vl) / 2; if (pos <= vm) update(2 * v + 1, vl, vm, pos, val); else update(2 * v + 2, vm + 1, vr, pos, val); t[v] = max(t[2 * v + 1], t[2 * v + 2]); } inline long long get(int v, int vl, int vr, int l, int r) { if (r < vl || vr < l) return 0; if (l <= vl && vr <= r) return t[v]; int vm = vl + (vr - vl) / 2; long long ql = get(2 * v + 1, vl, vm, l, r); long long qr = get(2 * v + 2, vm + 1, vr, l, r); return max(ql, qr); } inline bool c(pair<long long, int> x, pair<long long, int> y) { if (x.first != y.first) return x.first < y.first; else return x.second > y.second; } int main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) { long long r, h; cin >> r >> h; arr[i] = {1ll * r * r * h, i}; } sort(arr, arr + n, c); for (int i = 0; i < n; i++) { long long res = get(0, 0, n - 1, 0, max(0, arr[i].second - 1)); update(0, 0, n - 1, arr[i].second, res + arr[i].first); } cout << fixed << setprecision(6) << 3.14159265 * get(0, 0, n - 1, 0, n - 1) << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long int mod = 998244353; vector<long long int> roots; long long int powermod(long long int a, long long int n, long long int p) { long long int ans = 1; while (n > 0) { if (n & 1) ans = (ans * a) % p; n >>= 1; a = a * a % p; } return ans; } long long int primitive_root(long long int p) { vector<long long int> fact; int phi = p - 1, n = phi; for (int i = 2; i * i <= n; ++i) { if (n % i == 0) { fact.push_back(i); while (n % i == 0) n /= i; } } if (n > 1) fact.push_back(n); for (int res = 2; res <= p; ++res) { bool ok = true; for (int i = 0; i < fact.size() && ok; ++i) ok &= powermod(res, phi / fact[i], p) != 1; if (ok) return res; } return -1; } long long int mod_inverse(long long int a, long long int p) { vector<long long int> A = {p, 1, 0}; vector<long long int> B = {a, 0, 1}; while (B[0] != 1) { long long int ratio = A[0] / B[0]; A[0] -= ratio * B[0]; A[1] -= ratio * B[1]; A[2] -= ratio * B[2]; swap(A, B); } return (p + (B[2] % p)) % p; } void find_root() { long long int val = mod - 1; int start = 1 << 20; while (start > 0) { if (val % start == 0) { long long int c = val / start; roots.push_back(powermod(primitive_root(mod), c, mod)); } start >>= 1; } reverse(roots.begin(), roots.end()); } void initFFT(vector<long long int>& W, vector<long long int>& rbit, bool inverse, long long int root) { int n = W.size(); for (int i = 0; i < n; ++i) { int k = i, power = n >> 1, ans = 0; while (k > 0) { if (k & 1) ans += power; power >>= 1; k >>= 1; } rbit[ans] = i; } W[0] = 1; for (int i = 1; i < n; ++i) W[i] = (W[i - 1] * root) % mod; if (inverse) { for (int i = 1; i < n / 2; ++i) swap(W[i], W[n - i]); } } vector<long long int> FFT(vector<long long int> P, bool inverse, long long int root) { int n = P.size(); vector<long long int> W(n), rbit(n); initFFT(W, rbit, inverse, root); vector<long long int> Q(n); for (int i = 0; i < n; ++i) Q[i] = P[rbit[i]]; for (int l = 1; l < n; l <<= 1) { int step = n / (l << 1); for (int i = 0; i < n; i += l << 1) { int j = 0; for (int k = 0; k < l; ++k) { long long int u = Q[i + k], v = (W[j] * Q[i + k + l]) % mod; Q[i + k] = (u + v) % mod; Q[i + k + l] = (mod + (u - v) % mod) % mod; j += step; } } } if (inverse) { long long int inv = mod_inverse(n, mod); for (int i = 0; i < n; ++i) { Q[i] = (Q[i] * inv) % mod; } } return Q; } vector<long long int> multiply(vector<long long int>& A, vector<long long int>& B) { long long int n = 1, root = 0; while (n < A.size() + B.size()) { ++root; n <<= 1; } root = roots[root]; A.resize(n, 0); B.resize(n, 0); vector<long long int> DFTA = FFT(A, false, root); vector<long long int> DFTB = FFT(B, false, root); for (int i = 0; i < n; ++i) DFTA[i] = DFTA[i] * DFTB[i] % mod; DFTA = FFT(DFTA, true, root); return DFTA; } vector<long long int> A; void query(int k, int q, int l, int r, int d, int type) { int n = A.size(); vector<vector<long long int> > B(n); for (int i = 0; i < n; ++i) { if (i < l or i > r) B[i] = {1, q - A[i]}; else if (type == 2) B[i] = {1, q - d - A[i]}; else B[i] = {1, q - d}; } while (B.size() > 1) { vector<vector<long long int> > C; for (int i = 0; i < B.size(); i += 2) { if (i == B.size() - 1) C.push_back(B.back()); else C.push_back(multiply(B[i], B[i + 1])); } B = C; } cout << (B[0][k] % mod + mod) % mod << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); find_root(); int n, k; cin >> n >> k; A = vector<long long int>(n); for (int i = 0; i < n; ++i) cin >> A[i]; int Q; cin >> Q; for (int i = 0; i < Q; ++i) { int type; cin >> type; if (type == 1) { int q, l, d; cin >> q >> l >> d; query(k, q, l - 1, l - 1, d, type); } else { int q, l, r, d; cin >> q >> l >> r >> d; query(k, q, l - 1, r - 1, d, type); } } }
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#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > marks(200002); vector<pair<int, int> > marksbyy(200002); vector<vector<int> > partials(2005, vector<int>(2005)); vector<vector<int> > inpart(2005, vector<int>(2005)); int n; void fillpart() { sort(marks.begin() + 1, marks.begin() + n + 1); sort(marksbyy.begin() + 1, marksbyy.begin() + n + 1); for (int i = 1; i <= n; i++) { int j = marks[i].second; inpart[(i - 1) / 100][(j - 1) / 100]++; } partials[0][0] = inpart[0][0]; for (int i = 1; i <= 2000; i++) { partials[0][i] = partials[0][i - 1] + inpart[0][i]; } for (int i = 1; i <= 2000; i++) { partials[i][0] = partials[i - 1][0] + inpart[i][0]; } for (int i = 1; i <= 2000; i++) { for (int j = 1; j <= 2000; j++) { partials[i][j] = partials[i - 1][j] + partials[i][j - 1] - partials[i - 1][j - 1] + inpart[i][j]; } } } int query(int x, int y) { int ans = 0; int biggestpartx = x / 100 - 1; int biggestparty = y / 100 - 1; if (biggestpartx >= 0 && biggestparty >= 0) { ans += partials[biggestpartx][biggestparty]; for (int i = (biggestpartx + 1) * 100 + 1; i <= x; i++) { if (marks[i].second <= (biggestparty + 1) * 100) { ans++; } } for (int i = (biggestparty + 1) * 100 + 1; i <= y; i++) { if (marksbyy[i].second <= x) { ans++; } } } else { for (int i = 1; i <= x; i++) { if (marks[i].second <= y) { ans++; } } } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); int q; cin >> n >> q; vector<int> arr(n); for (int i = 1; i <= n; i++) { int x; cin >> x; x = n + 1 - x; marks[i] = make_pair(x, i); marksbyy[i] = make_pair(i, x); } fillpart(); for (int i = 0; i < q; i++) { int l, d, r, u; cin >> l >> d >> r >> u; u = n + 1 - u; d = n + 1 - d; long long int topleft = query(u - 1, l - 1); long long int top = query(u - 1, r) - topleft; long long int left = query(d, l - 1) - topleft; long long int inside = query(d, r) - topleft - top - left; long long int topright = query(u - 1, n) - top - topleft; long long int bottomleft = query(n, l - 1) - left - topleft; long long int bottom = query(n, r) - inside - bottomleft - topleft - top - left; long long int right = query(d, n) - inside - topright - topleft - top - left; long long int bottomright = query(n, n) - inside - topright - topleft - top - left - bottom - bottomleft - right; long long int ans = 0; ans += topleft * (bottom + right + bottomright + inside); ans += topright * (bottom + left + bottomleft + inside); ans += bottomleft * (top + right + topright + inside); ans += bottomright * (top + left + topleft + inside); ans += inside * (topright + topleft + bottomleft + bottomright + top + right + bottom + left + inside - 1); ans += top * (bottom + left + right + bottomleft + bottomright + inside); ans += right * (top + left + bottom + topleft + bottomleft + inside); ans += bottom * (top + left + right + topleft + topright + inside); ans += left * (top + bottom + right + topright + bottomright + inside); ans /= 2; cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int frd[2110][2110], rev[2110][2110]; vector<int> v; int main() { int a, b, c, d, e, i, j, p, q, mx, mx1, len; string x, y; cin >> x >> y; a = x.length(); b = y.length(); x = % + x; y = * + y; for (i = b; i >= 1; i--) { for (j = a; j >= 1; j--) { if (y[i] == x[j]) { frd[i][j] = frd[i + 1][j + 1] + 1; } } for (j = 1; j <= a; j++) { if (y[i] == x[j]) { rev[i][j] = rev[i + 1][j - 1] + 1; } } } for (i = 1; i <= b;) { p = -1; q = -1; mx = -1; mx1 = -1; for (j = 1; j <= a; j++) { if (frd[i][j] > mx) { mx = frd[i][j]; p = j; } } for (j = 1; j <= a; j++) { if (rev[i][j] > mx1) { mx1 = rev[i][j]; q = j; } } len = max(mx, mx1); if (len == 0) { cout << -1 << endl; return 0; } if (len == mx) { v.push_back(p); v.push_back(p + len - 1); } else { v.push_back(q); v.push_back(q - len + 1); } i = i + len; } cout << v.size() / 2 << endl; e = v.size(); for (i = 0; i < e; i = i + 2) { cout << v[i] << << v[i + 1] << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, k; int arr[600][600] = {}; int visited[600][600] = {}; void dfs(int, int); int main() { cin >> n >> m >> k; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { char t; cin >> t; if (t == . ) { arr[i][j] = 1; } if (t == # ) arr[i][j] = 2; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (arr[i][j] == 1) { dfs(i, j); break; } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (arr[i][j] == 1) cout << . ; if (arr[i][j] == 2) cout << # ; if (arr[i][j] == 3) cout << X ; } cout << endl; } } void dfs(int i, int j) { visited[i][j] = 1; if (arr[i][j + 1] == 1 && !visited[i][j + 1]) { dfs(i, j + 1); } if (arr[i + 1][j] == 1 && !visited[i + 1][j]) { dfs(i + 1, j); } if (arr[i][j - 1] == 1 && !visited[i][j - 1]) { dfs(i, j - 1); } if (arr[i - 1][j] == 1 && !visited[i - 1][j]) { dfs(i - 1, j); } if (k) { arr[i][j] = 3; k--; } }
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//#############################################################################
//# Purpose: SPI Master Transmit Fifo #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
`include "spi_regmap.vh"
module spi_master_fifo #(parameter DEPTH = 16, // fifo entries
parameter AW = 32, // address width
parameter PW = 104, // input packet width
parameter SW = 8 // io packet width
)
(
//clk,reset, cfg
input clk, // clk
input nreset, // async active low reset
input spi_en, // spi enable
output fifo_prog_full, // fifo full indicator for status
// Incoming interface
input access_in, // access by core
input [PW-1:0] packet_in, // packet from core
output wait_out, // pushback to core
// IO interface
input fifo_read, // pull a byte to IO
output fifo_empty, // fifo is empty
output [SW-1:0] fifo_dout // byte for IO
);
localparam FAW = $clog2(DEPTH); // fifo address width
localparam SRW = $clog2(PW/SW); // serialization factor
//###############
//# LOCAL WIRES
//###############
wire [7:0] datasize;
wire [PW-1:0] tx_data;
wire [SW-1:0] fifo_din;
wire tx_write;
wire fifo_wait;
wire fifo_wr;
wire fifo_full;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
//##################################
//# DECODE
//###################################
packet2emesh #(.AW(AW),
.PW(PW))
p2e (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
assign datasize[7:0] = (1<<datamode_in[1:0]);
assign tx_write = spi_en &
write_in &
access_in &
~fifo_wait &
(dstaddr_in[5:0]==`SPI_TX);
assign wait_out = fifo_wait; // & tx_write;
//epiphany mode works in msb or lsb mode
//data mode up to 64 bits works in lsb mode
//for msb transfer, use byte writes only
assign tx_data[PW-1:0] = {{(40){1'b0}},
srcaddr_in[AW-1:0],
data_in[AW-1:0]};
//##################################
//# FIFO PACKET WRITE
//##################################
oh_par2ser #(.PW(PW),
.SW(SW))
oh_par2ser (// Outputs
.dout (fifo_din[SW-1:0]),
.access_out (fifo_wr),
.wait_out (fifo_wait),
// Inputs
.clk (clk),
.nreset (nreset),
.din (tx_data[PW-1:0]),
.shift (1'b1),
.datasize (datasize[7:0]),
.load (tx_write),
.lsbfirst (1'b1),
.fill (1'b0),
.wait_in (fifo_prog_full)
);
//##################################
//# FIFO
//###################################
oh_fifo_sync #(.DEPTH(DEPTH),
.DW(SW))
fifo(// Outputs
.dout (fifo_dout[7:0]),
.full (fifo_full),
.prog_full (fifo_prog_full),
.empty (fifo_empty),
.rd_count (),
// Inputs
.clk (clk),
.nreset (nreset),
.din (fifo_din[7:0]),
.wr_en (fifo_wr),
.rd_en (fifo_read));
endmodule // spi_master_fifo
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../emesh/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[105][105]; int main() { scanf( %d %d , &n, &m); if (n + m == 3 or n + m == 4) printf( -1 n ); else { int num = 2; if (n >= m) { for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (num > m * n) num = 1; a[i][j] = num; num += 2; } } else for (int j = 1; j <= m; j++) for (int i = 1; i <= n; i++) { if (num > m * n) num = 1; a[i][j] = num; num += 2; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { printf( %d , a[i][j]); if (j == m) printf( n ); else printf( ); } } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_hstl_drv.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// HSTL Driver
*/
////////////////////////////////////////////////////////////////////////
`include "sys.h"
module bw_io_hstl_drv(
// Outputs
pad,
// Inputs
sel_data_n, pad_up, pad_dn_l, por,
bsr_up, bsr_dn_l, cbu, cbd, vddo );
output pad;
input [8:1] cbu;
input [8:1] cbd;
input sel_data_n;
input pad_up;
input pad_dn_l;
input por;
input bsr_up;
input bsr_dn_l;
inout vddo;
reg /*4value*/ out;
always @(/*AUTOSENSE*/bsr_dn_l or bsr_up or pad_dn_l or pad_up or por
or sel_data_n) begin
// 5/6/2005: Fixed for Bug 7184
if (por == 1'b1) out = 1'bz;
else if (por == 1'b0) begin
if (sel_data_n == 1'b0) begin
case ({pad_up, pad_dn_l})
2'b00: out = 1'b0;
2'b01: out = 1'bz;
2'b11: out = 1'b1;
default: out = 1'bx;
endcase // case({pad_up, pad_dn_l})
end
else if (sel_data_n == 1'b1) begin
case ({bsr_up, bsr_dn_l})
2'b00: out = 1'b0;
2'b01: out = 1'bz;
2'b11: out = 1'b1;
default: out = 1'bx;
endcase // case({bsr_up, bsr_dn_l})
end
else out = 1'bx;
end // if (por == 1'b0)
else out = 1'bx;
// ORIGINAL CODE
// casex ({por, sel_data_n, pad_up, pad_dn_l, bsr_up, bsr_dn_l})
// 6'b1xxxxx: out= 1'bz; // normal path (pad) reset
// 6'b0000xx: out= 1'b0; // normal path (pad) write 0
// 6'b0001xx: out= 1'bz; // normal path (pad) hi-Z
// 6'b0011xx: out= 1'b1; // normal path (pad) write 1
// 6'b01xx00: out= 1'b0; // boundary scan (bsr) write 0
// 6'b01xx01: out= 1'bz; // boundary scan (bsr) hi-Z
// 6'b01xx11: out= 1'b1; // boundary scan (bsr) write 1
// default: out= 1'bx; // all other cases illegal and not defined
// endcase
end // always @ (...
assign (pull1, strong0) #1 pad = out;
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/17/2017 10:33:49 AM
// Design Name:
// Module Name: Small Program Top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Small_Program_Top(
input clk,
input rst,
input left,
input right,
input up,
input down,
output hsync,
output vsync,
output [11:0]color_out,
output [7:0]seg_out,
output [3:0]sel
);
wire[7:0] direction;
wire[7:0] appleX;
wire[7:0] appleY;
wire[15:0] point;
wire[1:0] game_status;
wire[7:0] snake;
wire[9:0] pos_x;
wire[9:0] pos_y;
wire clk0;
wire clk1;
clk_div clk_div0(
.clkin(clk),
.clkout(clk0));
clk_div clk_div1(
.clkin(clk0),
.clkout(clk1));
Key key0(
.clk(clk0),
.rst(rst),
.left(left),
.right(right),
.up(up),
.down(down),
.direction(direction));
Apple apple0(
.clk(clk0),
.rst(rst),
.signal(signal),
.apple_x(appleX),
.apple_y(appleY));
openmips_min_sopc openmips_min_sopc0(
.clk(clk0),
.rst(rst),
.direction(direction),
.signal(signal),
.point(point),
.AppleX(appleX),
.AppleY(appleY),
.snake(snake),
.gamestatus(game_status)
);
Seg_Display seg_display0
(
.clk(clk0),
.rst(rst),
.add_cube(signal),
.game_status(game_status),
.point(point),
.seg_out(seg_out),
.sel(sel)
);
VGA_Control vga1(
.clk(clk1),
.rst(rst),
.snake(snake),
.apple_x(appleX),
.apple_y(appleY),
.x_pos(pos_x),
.y_pos(pos_y),
.hsync(hsync),
.vsync(vsync),
.color_out(color_out));
endmodule
|
#include <bits/stdc++.h> using namespace std; using ull = unsigned long long; const int kMod = 1e9 + 7; mt19937_64 rng(time(0)); struct SegTree { struct Node { ull dp = 0; int l = 0, r = 0; ull hash = 0; }; int n; vector<Node> T; vector<ull> rnd; SegTree(int n) : n(n), T(1), rnd(n) { for (int i = 0; i < n; ++i) rnd[i] = rng(); } pair<int, int> add(int node, int b, int e, int pos) { if (e <= pos) return {node, 0}; if (b == pos && T[node].dp + 1 == 0) return {0, 1}; T.emplace_back(); int ret = T.size() - 1; if (e - b == 64) { T[ret].dp = T[node].dp; T[ret].dp += (1ULL << (pos - b)); int state = 1 + (T[ret].dp > T[node].dp); for (int i = b; i < e; ++i) if (T[ret].dp & (1ULL << (i - b))) T[ret].hash += rnd[i]; return {ret, state}; } int state; int l = T[node].l, r = T[node].r; int m = (b + e) / 2; tie(l, state) = add(l, b, m, pos); if (state == 0) tie(r, state) = add(r, m, e, pos); else if (state == 1) tie(r, state) = add(r, m, e, m); T[ret].l = l; T[ret].r = r; T[ret].hash = T[l].hash + T[r].hash; T[ret].dp = min(T[l].dp, T[r].dp); return {ret, state}; } int Add(int node, int val) { auto [ret, state] = add(node, 0, n, val); assert(state == 2); return ret; } int compare(int x, int y, int b, int e) { if (T[x].hash == T[y].hash) return 0; if (e - b == 64) return T[x].dp < T[y].dp ? -1 : 1; int m = (b + e) / 2; int ret = compare(T[x].r, T[y].r, m, e); if (ret) return ret; return compare(T[x].l, T[y].l, b, m); } int Compare(int a, int b) { return compare(a, b, 0, n); } void get(int node, int b, int e, int& ans) { if (e - b == 64) { for (int i = b; i < e; ++i) ans = (ans + ans) % kMod; ans = (ans + T[node].dp % kMod) % kMod; } else { int m = (b + e) / 2; get(T[node].r, m, e, ans); get(T[node].l, b, m, ans); } } int Get(int node) { int ans = 0; get(node, 0, n, ans); return ans; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; vector<vector<pair<int, int>>> graph(n); for (int i = 0; i < m; ++i) { int a, b, c; cin >> a >> b >> c; --a; --b; graph[a].emplace_back(c, b); graph[b].emplace_back(c, a); } SegTree st(1 << 17); int s, t; cin >> s >> t; --s; --t; auto cmp = [&](pair<int, int> a, pair<int, int> b) { return st.Compare(a.first, b.first) == 1; }; priority_queue<pair<int, int>, vector<pair<int, int>>, decltype(cmp)> pq(cmp); vector<int> dist(n, -1), parent(n, -1), vis(n, false); dist[s] = 0; pq.emplace(0, s); while (pq.size()) { auto [d, node] = pq.top(); pq.pop(); if (d != dist[node]) continue; if (node == t) break; vis[node] = true; for (auto [cost, vec] : graph[node]) { if (vis[vec]) continue; int nd = st.Add(d, cost); if (dist[vec] == -1 || st.Compare(nd, dist[vec]) == -1) { dist[vec] = nd; parent[vec] = node; pq.emplace(nd, vec); } } } if (dist[t] == -1) { cout << -1 << n ; } else { vector<int> trace; for (int node = t; node != -1; node = parent[node]) trace.push_back(node); reverse(trace.begin(), trace.end()); cout << st.Get(dist[t]) << endl; cout << trace.size() << endl; for (auto x : trace) cout << x + 1 << ; cout << endl; } return 0; }
|
`timescale 100 ps / 100 ps
module tb_magnitude();
reg clk;
initial clk = 0;
always #10000 clk = ~clk;
wire [11:0] mag1, mag2;
reg [11:0] Y0, Y1, Y2, Y3;
magnitude magnitude_inst(.Y0(Y0), .Y1(Y1), .Y2(Y2), .Y3(Y3), .mag1(mag1), .mag2(mag2));
initial begin
@(posedge clk);
Y0 <= 12'b111111111101;
Y1 <= 12'b111111111110;
Y2 <= 12'b111111111111;
Y3 <= 12'b111111111110;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
Y0 <= 12'b000000010110;
Y1 <= 12'b000001000100;
Y2 <= 12'b000001001110;
Y3 <= 12'b000011110011;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
Y0 <= $random;
Y1 <= $random;
Y2 <= $random;
Y3 <= $random;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
Y0 <= $random;
Y1 <= $random;
Y2 <= $random;
Y3 <= $random;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
Y0 <= $random;
Y1 <= $random;
Y2 <= $random;
Y3 <= $random;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
Y0 <= $random;
Y1 <= $random;
Y2 <= $random;
Y3 <= $random;
#10;
$display("Y0 = %d, Y1 = %d, Y2 = %d, Y3 = %d.", Y0, Y1, Y2, Y3);
@(posedge clk);
$display("mag1 = %d, mag2 = %d", mag1, mag2);
#1000 $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_1_V
`define SKY130_FD_SC_LP__NOR4_1_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__XOR2_BEHAVIORAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xor2 (
X ,
A ,
B ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
// Local signals
wire xor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const long long inf = (1ll << 60); int n, m, k, cnt, a, b, v[N], p[N], ta[N], tb[N], td[N], ca[N << 2], cb[N << 2], cd[N << 2], flag[N], pa, pb, pc, pd; long long A[N], B[N], C[N], D[N], co[N], sum, ans = inf; int read() { int x = 0, f = 1; char s; while ((s = getchar()) > 9 || s < 0 ) if (s == - ) f = -1; while (s <= 9 && s >= 0 ) x = (x << 1) + (x << 3) + (s ^ 48), s = getchar(); return x * f; } bool cmp(const int a, const int b) { return v[a] < v[b]; } void build(const int o, const int l, const int r) { if (l == r) { ca[o] = ta[l], cb[o] = tb[l], cd[o] = td[l]; return; } int mid = l + r >> 1; build(o << 1, l, mid); build(o << 1 | 1, mid + 1, r); ca[o] = ca[o << 1 | 1]; cb[o] = cb[o << 1 | 1]; cd[o] = cd[o << 1 | 1]; } long long query(const int o, const int l, const int r, const int need) { if (l == r) return A[max(need, ca[o])] + B[max(need, cb[o])] + D[cd[o]] - co[l] * (max(need, ca[o]) + max(need, cb[o]) + cd[o] + k - need - m); int mid = l + r >> 1; long long t = max(need, ca[o << 1]) + max(need, cb[o << 1]) + cd[o << 1] + k - need; if (t >= m) return query(o << 1, l, mid, need); else return query(o << 1 | 1, mid + 1, r, need); } int main() { n = read(), m = read(), k = read(); for (int i = 1; i <= n; ++i) v[i] = read(), p[i] = i; sort(p + 1, p + n + 1, cmp); for (int i = 1; i <= n; ++i) { if (i == 1 || co[cnt] < v[p[i]]) co[++cnt] = v[p[i]]; v[p[i]] = cnt; } a = read(); for (int i = 1; i <= a; ++i) b = read(), flag[b] |= 1; a = read(); for (int i = 1; i <= a; ++i) b = read(), flag[b] |= 2; for (int i = 1; i <= n; ++i) { if (flag[i] == 0) D[++pd] = co[v[i]], ++td[v[i]]; if (flag[i] == 1) A[++pa] = co[v[i]], ++ta[v[i]]; if (flag[i] == 2) B[++pb] = co[v[i]], ++tb[v[i]]; if (flag[i] == 3) C[++pc] = co[v[i]]; } sort(A + 1, A + pa + 1); sort(B + 1, B + pb + 1); sort(C + 1, C + pc + 1); sort(D + 1, D + pd + 1); for (int i = 1; i <= cnt; ++i) ta[i] += ta[i - 1], tb[i] += tb[i - 1], td[i] += td[i - 1]; for (int i = 1; i <= pa; ++i) A[i] += A[i - 1]; for (int i = 1; i <= pb; ++i) B[i] += B[i - 1]; for (int i = 1; i <= pd; ++i) D[i] += D[i - 1]; build(1, 0, cnt); for (int i = 0; i <= min(m, pc); ++i) { sum += C[i]; if (min(pa, pb) >= k - i && 2 * k - 2 * i <= m - i && i + pa + pb + pd >= m) ans = min(ans, sum + query(1, 0, cnt, k - i)); } printf( %lld n , ans == inf ? -1 : ans); return 0; }
|
module ram ( input [15:0] din, output [15:0] dout, input[10:0] address, input rnw, input clk, input cs_b);
// parameter MEM_INIT_FILE = "opc5monitor.init";
//
// reg [15:0] ram [0:2047];
// reg [15:0] dout;
//
// initial begin
// if (MEM_INIT_FILE != "") begin
// $readmemh(MEM_INIT_FILE, ram);
// end
// end
//
// always @(posedge clk)
// if (!cs_b) begin
// if (!rnw)
// ram[address] <= data;
// dout <= ram[address];
// end
wire en = !cs_b;
wire we = !rnw;
RAMB16_S9 ram0
(
.WE(we),
.EN(en),
.SSR(),
.CLK(clk),
.ADDR(address),
.DI(din[7:0]),
.DIP(1'b0),
.DO(dout[7:0]),
.DOP()
);
RAMB16_S9 ram1
(
.WE(we),
.EN(en),
.SSR(),
.CLK(clk),
.ADDR(address),
.DI(din[15:8]),
.DIP(1'b0),
.DO(dout[15:8]),
.DOP()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int y[N], pos[N]; int main() { int n, m, t = 0, ans = 0, cnt = 0; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &y[i]); for (int i = 1; i <= m; i++) { int y1, y2, x; scanf( %d %d %d , &y1, &y2, &x); if (y1 == 1) { pos[++t] = y2; } if (y2 == 1e9) { ans++; } } sort(y + 1, y + 1 + n); sort(pos + 1, pos + 1 + t); int i = 1, j = 1; cnt = t, ans += n; while (i <= n) { while (j <= t) { if (pos[j] < y[i]) { j++, cnt--; } else break; } ans = min(ans, cnt + i - 1); i++; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; struct pony { long long s, m, r, t; } ponys[100005]; bool cmp(pony &x, pony &y) { return x.t < y.t; } struct node { long long l, r, latest; long long *sm, *sr, *t; } nodes[100005 << 4]; void build(long long ord, long long l, long long r) { nodes[ord].latest = 0; nodes[ord].l = l, nodes[ord].r = r; if (l == r) { nodes[ord].sm = &ponys[l].m; nodes[ord].sr = &ponys[l].r; nodes[ord].t = &ponys[l].t; return; } int m = (l + r) >> 1; build(ord << 1, l, m); build(ord << 1 | 1, m + 1, r); pony *tmp = new pony[r - l + 1]; for (int i = 0; i < r - l + 1; i++) tmp[i] = ponys[l + i]; sort(tmp, tmp + r - l + 1, cmp); nodes[ord].sm = new long long[r - l + 2]; nodes[ord].sr = new long long[r - l + 2]; nodes[ord].t = new long long[r - l + 2]; nodes[ord].sm[0] = nodes[ord].sr[0] = nodes[ord].t[0] = 0; for (int i = 1; i < r - l + 2; i++) { nodes[ord].sm[i] = tmp[i - 1].m + nodes[ord].sm[i - 1]; nodes[ord].sr[i] = tmp[i - 1].r + nodes[ord].sr[i - 1]; nodes[ord].t[i] = tmp[i - 1].t; } delete[] tmp; } long long mana_obserbed(long long ord, long long t, long long l, long long r) { long long res = 0; if (nodes[ord].latest > 0) nodes[ord << 1].latest = nodes[ord << 1 | 1].latest = nodes[ord].latest; if (nodes[ord].l == l && nodes[ord].r == r) { if (nodes[ord].latest > 0) { if (l == r) res = min(ponys[l].m, ponys[l].r * (t - nodes[ord].latest)); else { int len = nodes[ord].r - nodes[ord].l + 2; int tmp = upper_bound(nodes[ord].t + 1, nodes[ord].t + len, t - nodes[ord].latest) - nodes[ord].t; res = nodes[ord].sm[tmp - 1] + (nodes[ord].sr[len - 1] - nodes[ord].sr[tmp - 1]) * (t - nodes[ord].latest); } nodes[ord].latest = t; return res; } else if (nodes[ord].latest == 0 && l == r) { res = min(ponys[l].m, ponys[l].s + ponys[l].r * t); nodes[ord].latest = t; return res; } } int m = (nodes[ord].l + nodes[ord].r) >> 1; if (r <= m) res += mana_obserbed(ord << 1, t, l, r); else if (m < l) res += mana_obserbed(ord << 1 | 1, t, l, r); else res += mana_obserbed(ord << 1, t, l, m) + mana_obserbed(ord << 1 | 1, t, m + 1, r); nodes[ord].latest = nodes[ord << 1].latest == nodes[ord << 1 | 1].latest ? nodes[ord << 1].latest : -1; return res; } int main() { long long n, m, t, l, r; cin >> n; for (long long i = 1; i <= n; i++) { cin >> ponys[i].s >> ponys[i].m >> ponys[i].r; if (ponys[i].r) ponys[i].t = (ponys[i].m + ponys[i].r - 1) / ponys[i].r; else ponys[i].t = 0x7fffffffffffffff; } build(1, 1, n); cin >> m; for (long long i = 1; i <= m; i++) { cin >> t >> l >> r; cout << mana_obserbed(1, t, l, r) << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int a[26]; char s[100001]; int gcd(int a, int b) { if (a % b == 0) { return b; } else { return gcd(b, a % b); } } int main() { int n, ans, sum = 0, c = 0, i, j, k, l; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &a[i]); sum += a[i]; if (a[i] % 2 == 1) c++; } if (c >= 2) { ans = 0; for (i = 0, j = 0; i < n; i++) { while (a[i] > 0) { s[j++] = a + i; a[i]--; } } } else { ans = a[0]; for (i = 1; i < n; i++) ans = gcd(ans, a[i]); if (c == 1) { int p; for (i = 0; i < n; i++) { if (a[i] % 2 == 1) { p = i; a[i] -= ans; } } for (i = 0, l = 0; i < ans * 2; i++) { if (i % 2 == 0) { for (j = 0; j < n; j++) { for (k = 0; k < a[j] / ans / 2; k++) s[l++] = a + j; } s[l++] = a + p; } else { for (j = n - 1; j >= 0; j--) { for (k = 0; k < a[j] / ans / 2; k++) s[l++] = a + j; } } } } else { for (i = 0, l = 0; i < ans; i++) { if (i % 2 == 0) { for (j = 0; j < n; j++) { for (k = 0; k < a[j] / ans; k++) s[l++] = a + j; } } else { for (j = n - 1; j >= 0; j--) { for (k = 0; k < a[j] / ans; k++) s[l++] = a + j; } } } } } printf( %d n , ans); printf( %s n , s); return 0; }
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#include <bits/stdc++.h> using namespace std; struct MinCostFlow { struct Edge { int t; int f; int c; Edge *next, *rev; Edge(int _t, int _f, int _c, Edge* _next) : t(_t), f(_f), c(_c), next(_next) {} }; vector<Edge*> E; int addV() { E.push_back((Edge*)0); return E.size() - 1; } Edge* makeEdge(int s, int t, int f, int c) { return E[s] = new Edge(t, f, c, E[s]); } void addEdge(int s, int t, int f, int c) { Edge *e1 = makeEdge(s, t, f, c), *e2 = makeEdge(t, s, 0, -c); e1->rev = e2, e2->rev = e1; } pair<int, int> minCostFlow(int vs, int vt, bool maxFlow) { int n = E.size(); int flow = 0; int cost = 0; const int MAX_COST = ~0U >> 1; const int MAX_FLOW = ~0U >> 1; for (;;) { vector<int> dist(n, MAX_COST); vector<int> am(n, 0); vector<Edge*> prev(n); vector<bool> inQ(n, false); queue<int> que; dist[vs] = 0; am[vs] = MAX_FLOW; que.push(vs); inQ[vs] = true; while (!que.empty()) { int u = que.front(); int c = dist[u]; que.pop(); inQ[u] = false; for (Edge* e = E[u]; e; e = e->next) if (e->f > 0) { int nc = c + e->c; if (nc < dist[e->t]) { dist[e->t] = nc; prev[e->t] = e; am[e->t] = min(am[u], e->f); if (!inQ[e->t]) { que.push(e->t); inQ[e->t] = true; } } } } if (maxFlow) { if (dist[vt] == MAX_COST) break; } else { if (dist[vt] >= 0) break; } int by = am[vt]; int u = vt; flow += by; cost += by * dist[vt]; while (u != vs) { Edge* e = prev[u]; e->f -= by; e->rev->f += by; u = e->rev->t; } } return make_pair(flow, cost); } }; const int MAX_N = 100 + 10; int n, m; string how[MAX_N]; int A[MAX_N], B[MAX_N]; int ia[MAX_N], ib[MAX_N]; int notKillAll() { MinCostFlow net; int vs = net.addV(), vt = net.addV(); for (int i = 0; i < n; ++i) { ia[i] = net.addV(); net.addEdge(vs, ia[i], 1, 0); } for (int i = 0; i < m; ++i) { ib[i] = net.addV(); net.addEdge(ib[i], vt, 1, 0); } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (B[j] > A[i] && how[i] == ATK ) { net.addEdge(ia[i], ib[j], 1, -(B[j] - A[i])); } } } return -net.minCostFlow(vs, vt, false).second; } int killAll() { MinCostFlow net; int vs = net.addV(), vt = net.addV(); for (int i = 0; i < m; ++i) { ia[i] = net.addV(); net.addEdge(vs, ia[i], 1, 0); } for (int i = 0; i < m; ++i) { ib[i] = net.addV(); net.addEdge(ib[i], vt, 1, 0); } for (int i = 0; i < m; ++i) { for (int j = 0; j < m; ++j) { if (i < n) { if (how[i] == ATK ) { if (B[j] >= A[i]) net.addEdge(ia[i], ib[j], 1, -(B[j] - A[i])); } else { if (B[j] > A[i]) net.addEdge(ia[i], ib[j], 1, 0); } } else { net.addEdge(ia[i], ib[j], 1, -B[j]); } } } pair<int, int> ret = net.minCostFlow(vs, vt, true); if (ret.first == m) return -ret.second; return 0; } int main() { cin >> n >> m; for (int i = 0; i < n; ++i) { cin >> how[i] >> A[i]; } for (int i = 0; i < m; ++i) { cin >> B[i]; } int ans = notKillAll(); if (m > n) ans = max(ans, killAll()); cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long q = 0; vector<long long> a; a.push_back(0); for (long long i = 0; i < 4; i++) { long long te; cin >> te; a.push_back(te); } string s; cin >> s; for (long long i = 0; i < s.size(); i++) { q += a[s[i] - 0 ]; } cout << q; return 0; ; }
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/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: rx_lane_logic
*
*/
`default_nettype none
module rx_lane_logic #(
parameter DWIDTH = 512,
parameter NUM_LANES = 8,
parameter LANE_DWIDTH = (DWIDTH/NUM_LANES),
parameter CTRL_LANE_POLARITY = 1,
parameter BITSLIP_SHIFT_RIGHT= 1
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----CONNECT
//----------------------------------
input wire [LANE_DWIDTH-1:0] scrambled_data_in,
input wire bit_slip, //bit slip per lane
input wire lane_polarity,
input wire can_lock,
output wire [LANE_DWIDTH-1:0] descrambled_data_out,
output wire descrambler_locked,
input wire descrambler_disable
);
wire [LANE_DWIDTH-1:0] descrambled_data_out_tmp;
wire [LANE_DWIDTH-1:0] data_2_descrambler;
wire descrambler_locked_tmp;
assign descrambler_locked = descrambler_disable ? can_lock : descrambler_locked_tmp;
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------ACTUAL LOGIC STARTS HERE--------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
generate
if(CTRL_LANE_POLARITY==1) begin
reg [LANE_DWIDTH-1:0] scrambled_data_in_reg;
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
`ifdef RESET_ALL
if(!res_n) begin
scrambled_data_in_reg <= {LANE_DWIDTH{1'b0}};
end else
`endif
begin
scrambled_data_in_reg <= scrambled_data_in^{LANE_DWIDTH{lane_polarity}};
end
end
assign data_2_descrambler = scrambled_data_in_reg;
assign descrambled_data_out = descrambler_disable ? scrambled_data_in_reg : descrambled_data_out_tmp;
end else begin
assign data_2_descrambler = scrambled_data_in;
assign descrambled_data_out = descrambler_disable ? scrambled_data_in : descrambled_data_out_tmp;
end
endgenerate
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//Descrambler Init
rx_descrambler #(
.DWIDTH(LANE_DWIDTH),
.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT)
) descrambler_I (
.clk(clk),
.res_n(res_n),
.can_lock(can_lock),
.bit_slip(bit_slip),
.locked(descrambler_locked_tmp),
.data_in(data_2_descrambler),
.data_out(descrambled_data_out_tmp)
);
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; array<int, N> a; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, k; cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; long long ans = 0; long long power = 1; while (abs(power) < 1e15) { map<long long, int> m; m[0] = 1; long long sum = 0ll; for (int i = 0; i < n; i++) { sum += a[i]; ans += m[sum - power]; m[sum]++; } power *= k; if (power == 1) break; } cout << ans << endl; return 0; }
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Thu Mar 20 00:59:05 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/lab_2/part_4/ip/dds/dds_stub.v
// Design : dds
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module dds(aclk, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,m_axis_data_tvalid,m_axis_data_tdata[7:0]" */;
input aclk;
output m_axis_data_tvalid;
output [7:0]m_axis_data_tdata;
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the Viterbi decoder
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
`include "viterbidec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_viterbi_decoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the Viterbi decoder
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire data; // Output signal d
// Declare "reg" signals: inputs to the DUT
reg [1:0] encoded_input; // Input signal - cx
reg clock; // Input signal - clk
reg reset_sig; // Input signal - reset
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
data,encoded_input,clock,reset_sig);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=10,
#10
reset_sig = 1'd1;
encoded_input = 2'd0;
// @t=20,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=30,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=40,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=50,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=60,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=70,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=80,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=90,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=100,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=110,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=120,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=130,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=140,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=150,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=160,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=170,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=180,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=190,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=200,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=210,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=220,
#10
reset_sig = 0;
encoded_input = $random;
// @t=230,
#10
reset_sig = 0;
encoded_input = $random;
// @t=240,
#10
reset_sig = 0;
encoded_input = $random;
// @t=250,s
#10
reset_sig = 0;
encoded_input = $random;
// @t=260,
#10
reset_sig = 0;
encoded_input = $random;
// @t=270,
#10
reset_sig = 0;
encoded_input = $random;
// @t=280,
#10
reset_sig = 0;
encoded_input = $random;
// @t=290,
#10
reset_sig = 0;
encoded_input = $random;
// @t=300,
#10
reset_sig = 0;
encoded_input = $random;
// @t=310,
#10
reset_sig = 0;
encoded_input = $random;
// @t=320,
#10
reset_sig = 0;
encoded_input = $random;
// @t=330,
#10
reset_sig = 0;
encoded_input = $random;
// @t=340,
#10
reset_sig = 0;
encoded_input = $random;
// @t=350,
#10
reset_sig = 0;
encoded_input = $random;
// @t=360,
#10
reset_sig = 0;
encoded_input = $random;
// @t=370,
#10
reset_sig = 0;
encoded_input = $random;
// @t=380,
#10
reset_sig = 0;
encoded_input = $random;
// @t=390,
#10
reset_sig = 0;
encoded_input = $random;
// @t=400,
#10
reset_sig = 1;
encoded_input = $random;
// @t=410,
#10
reset_sig = 0;
encoded_input = $random;
// @t=420,
#10
reset_sig = 0;
encoded_input = $random;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DECAP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DECAP_BLACKBOX_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DECAP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; typedef int64_t g; g n,p[269420],v=1e9+7,T,r,i,k,s; map<g,g> l; int main(){ cin>>T; while(T--){ cin>>n; l.clear(); for(i=0,s=0,p[0]=1,l[0]=1;++i<=n;){ cin>>k; p[i]=(p[i-1]*2+v-p[l[s]-1])%v; l[s]=i; s+=k; }cout<<p[n]<<endl; } }
|
#include <bits/stdc++.h> using namespace std; const int M = 2e5 + 10; const int inf = 0x3f3f3f3f; const long long mod = 1e9 + 7; const int bit = 32; const double pi = acos(-1.0); int a[M]; int dfs(int k, int l, int r) { if (l > r) return 0; if (k < 0) return 1; int mid = r; int t = 1 << k; for (int i = l; i <= r; i++) { if (t & a[i]) { mid = i - 1; break; } } int x = dfs(k - 1, l, mid), y = dfs(k - 1, mid + 1, r); return max(x + min(r - mid, 1), y + min(mid - l + 1, 1)); } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + 1 + n); printf( %d n , n - dfs(30, 1, n)); return 0; }
|
#include <bits/stdc++.h> using namespace std; int arr[2505][2505], sum[2505][2505], n, m; int get_sum(int x1, int y1, int x2, int y2) { x2 = min(x2, n); y2 = min(y2, m); assert(x1 <= x2); assert(y1 <= y2); return sum[x2][y2] - sum[x2][y1 - 1] - sum[x1 - 1][y2] + sum[x1 - 1][y1 - 1]; } int main() { ios::sync_with_stdio(false); ; cin.tie(0); ; int i, j, k, ans = 100000000, ones, zeroes; string s; cin >> n >> m; for (i = 1; i <= n; i++) { cin >> s; s = + s; for (j = 1; j <= m; j++) arr[i][j] = s[j] - 0 ; } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) sum[i][j] = sum[i - 1][j] + sum[i][j - 1] - sum[i - 1][j - 1] + arr[i][j]; } for (k = 2; k <= max(n, m); k++) { int got = 0; for (i = 1; i <= n; i = i + k) { for (j = 1; j <= m; j = j + k) { ones = get_sum(i, j, i + k - 1, j + k - 1); zeroes = k * k - ones; got += min(ones, zeroes); } } ans = min(ans, got); } cout << ans; return 0; }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_increment (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter value = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_INCREMENT";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_increment_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_increment_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_increment_psl_logic.v"
`else
`endmodule // ovl_increment
`endif
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "jpdt.v"
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_alu();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
alu a_l_u (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ww,a_op,res);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwmuleu AND w8
/*
r_A=31'h0402050f;
r_B=31'h0301020c;
e_r=31'h000c0006;
c_ww=`w8;
a_op=`aluwmuleu;
*/
r_A=128'h0402030405060708f00a0b0cff0eff00;
r_B=128'h03010202030303031004f505ff09fe10;
e_r=128'h000c0006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w16
r_A=128'h000100020000ffff000f10bff103ffff;
r_B=128'h000200040006ffff000c100000120014;
e_r=128'h0000000200000000000000b40010f236;
c_ww=`w16;
a_op=`aluwmuleu;
// ======================================
#10
// aluwmulou AND w8
r_A=128'h0102030405060708090aff0c0dff0fff;
r_B=128'h01010202030303031004040508000fff;
e_r=128'h00020008001200180028003c0000fe01;
c_ww=`w8;
a_op=`aluwmulou;
#10
// aluwmulou AND w16
r_A=128'h0001000200000008000f10bff103ffff;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000000080000004000010bf00013ffec;
c_ww=`w16;
a_op=`aluwmulou;
// ======================================
#10
// aluwmulos AND w8
/*
r_A=128'h010330405060708090aff0c0dff0ff02;
r_B=128'h01fa0202030303031004040508000f08;
*/
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmulos;
#10
// aluwmulos AND w16
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmulos;
// ======================================
#10
// aluwmules AND w8
/*
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
*/
r_A=128'h80010501f9015301040100013c010001;
r_B=128'h7f010901fa010001fd01f101b8010001;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmules;
#10
// aluwmules AND w16
/*
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
*/
r_A=128'h000211118000111120541111fff91111;
r_B=128'h0004ffff7fffffff0000fffffffdffff;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmules;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: GDA_St_N16_M4_P4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GDA_St_N16_M4_P4(
input [15:0] in1,
input [15:0] in2,
output [16:0] res
);
wire [4:0] temp1, temp2, temp3, temp4;
//C4
wire g0,g1,g2,g3,p0,p1,p2,p3;
wire p3g2,p3p2,p3p2g1,p3p2p1,p3p2p1g0;
wire res_or_1, res_or_2;
wire c4;
and and_3(g3,in1[3],in2[3]);
and and_2(g2,in1[2],in2[2]);
and and_1(g1,in1[1],in2[1]);
and and_0(g0,in1[0],in2[0]);
xor xor_3(p3,in1[3],in2[3]);
xor xor_2(p2,in1[2],in2[2]);
xor xor_1(p1,in1[1],in2[1]);
xor xor_0(p0,in1[0],in2[0]);
and and_4(p3g2,p3,g2);
and and_5(p3p2,p3,p2);
and and_6(p3p2g1,p3p2,g1);
and and_7(p3p2p1,p3p2,p1);
and and_8(p3p2p1g0,p3p2p1,g0);
or or_3(res_or_1,g3,p3g2);
or or_2(res_or_2,p3p2g1,p3p2p1g0);
or or_1(c4,res_or_1,res_or_2);
//C8
wire g4,g5,g6,g7,p4,p5,p6,p7;
wire p7g6,p7p6,p7p6g5,p7p6p5,p7p6p5g4;
wire res_or_3, res_or_4;
wire c8;
and and_9 (g7,in1[7],in2[7]);
and and_10(g6,in1[6],in2[6]);
and and_11(g5,in1[5],in2[5]);
and and_12(g4,in1[4],in2[4]);
xor xor_7(p7,in1[7],in2[7]);
xor xor_6(p6,in1[6],in2[6]);
xor xor_5(p5,in1[5],in2[5]);
xor xor_4(p4,in1[4],in2[4]);
and and_13(p7g6,p7,g6);
and and_14(p7p6,p7,p6);
and and_15(p7p6g5,p7p6,g5);
and and_16(p7p6p5,p7p6,p5);
and and_17(p7p6p5g4,p7p6p5,g4);
or or_6(res_or_3,g7,p7g6);
or or_5(res_or_4,p7p6g5,p7p6p5g4);
or or_4(c8,res_or_3,res_or_4);
//C12
wire g8,g9,g10,g11,p8,p9,p10,p11;
wire p11g10,p11p10,p11p10g9,p11p10p9;
wire res_or_5, res_or_6;
wire c12;
and and_18(g11,in1[11],in2[11]);
and and_19(g10,in1[10],in2[10]);
and and_20(g9,in1[9],in2[9]);
and and_21(g8,in1[8],in2[8]);
xor xor_11(p11,in1[11],in2[11]);
xor xor_10(p10,in1[10],in2[10]);
xor xor_9(p9,in1[9],in2[9]);
xor xor_8(p8,in1[8],in2[8]);
and and_22(p11g10,p11,g10);
and and_23(p11p10,p11,p10);
and and_24(p11p10g9,p11p10,g9);
and and_25(p11p10p9,p11p10,p9);
and and_26(p11p10p9g8,p11p10p9,g8);
or or_9(res_or_5,g11,p11g10);
or or_8(res_or_6,p11p10g9,p11p10p9g8);
or or_7(c12,res_or_5,res_or_6);
// Results
assign temp1[4:0] = in1[ 3: 0] + in2[ 3: 0];
assign temp2[4:0] = in1[ 7: 4] + in2[ 7: 4] + c4;
assign temp3[4:0] = in1[11: 8] + in2[11: 8] + c8;
assign temp4[4:0] = in1[15:12] + in2[15:12] + c12;
assign res[16:0] = {temp4[4:0],temp3[3:0],temp2[3:0],temp1[3:0]};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A22OI_BEHAVIORAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a22oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
// Local signals
wire B2 nand0_out ;
wire B2 nand1_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int ile(long long int a) { int ans = 0; while (a) { if (a % 2 == 1) ans++; a /= 2; } return ans; } int main() { int n; cin >> n; long long int* a; a = new long long int[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } int* b; b = new int[n]; for (int i = 0; i < n; i++) { b[i] = ile(a[i]); } int* pre; pre = new int[n]; pre[0] = b[0] % 2; for (int i = 1; i < n; i++) { pre[i] = (pre[i - 1] + b[i]) % 2; } int ile0 = 0; int ile1 = 0; for (int i = 0; i < n; i++) { if (pre[i] == 0) ile0++; else ile1++; } long long int ans = 0; ans += ile0; for (int i = 1; i < n; i++) { if (pre[i - 1] == 0) ile0--; else ile1--; if (pre[i - 1] == 0) ans += ile0; else ans += ile1; } for (int i = 0; i < n; i++) { int j = i; int naj = 0; int sum = 0; while (j < n && sum <= 128) { naj = max(naj, b[j]); sum += b[j]; if (naj > (sum - naj)) { if (i == 0) { if (pre[j] == 0) ans--; } else { if (pre[j] - pre[i - 1] == 0) ans--; } } j++; } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class A, class B> A cvt(B x) { stringstream ss; ss << x; A y; ss >> y; return y; } int n, a, b, t; string s; int solve() { int tb = 0; vector<int> tm; for (int k = n; k >= 1; k--) { tb += a; if (s[k - 1] != h ) tb += b; tb += 1; tm.push_back(tb); } int best = 0; int t1 = 0; for (int k = 1; k <= n; k++) { if (k != 1) t1 += a; if (s[k - 1] != h ) t1 += b; t1 += 1; if (t1 > t) break; int t2 = t - t1 - (k - 1) * a; int l = lower_bound(tm.begin(), tm.end(), t2 + 1) - tm.begin(); best = max(best, min(k + l, n)); } return best; } int main() { cin >> n >> a >> b >> t >> s; int s1 = solve(); reverse(s.begin() + 1, s.end()); int s2 = solve(); cout << max(s1, s2) << endl; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:59 08/23/2015
// Design Name: binary_to_BCD_ten_bit
// Module Name: D:/Digilent/Data/Xilinx/Projects/ISE_12_4/Binary_to_BCD_Ten_Bit/binary_to_BCD_ten_bit_tb.v
// Project Name: Binary_to_BCD_Ten_Bit
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: binary_to_BCD_ten_bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module binary_to_BCD_ten_bit_tb;
// Inputs
reg [9:0] in;
// Outputs
wire [3:0] ones;
wire [3:0] tens;
wire [3:0] hundreds;
wire thousands;
// Instantiate the Unit Under Test (UUT)
binary_to_BCD_ten_bit uut (
.in(in),
.ones(ones),
.tens(tens),
.hundreds(hundreds),
.thousands(thousands)
);
initial begin
// Initialize Inputs
in = 0;
for (in =0; in < 1024; in = in +1) begin
#1
$display(" in = %d thousand = %d hundreds = %d tens = %d ones = %d",in, thousands, hundreds, tens, ones);
end
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_BLACKBOX_V
`define SKY130_FD_SC_LP__OR2_BLACKBOX_V
/**
* or2: 2-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; char str[1000005]; int ar[1000005]; void solve() { int n = (int)strlen(str + 1), i, j, ans = 0; memset(ar, 0, sizeof(ar)); str[0] = 0 ; for (i = n; i >= 0; i--) { if (str[i] == 1 ) { j = i; while (str[j] == 1 ) --j; if (i - j > 1) ar[i] = -1, ar[j] = 1, str[j] = 1 ; else { int k; for (k = -~j; k <= i; k++) ar[k] = 1; } i = -~j; } } for (i = 0; i <= n; i++) if (ar[i]) ans++; printf( %d n , ans); for (i = 0; i <= n && ans; i++) { if (ar[i]) { putchar(~ar[i] ? + : - ), printf( 2^%d n , n - i); --ans; } } } int main(void) { while (~scanf( %s , str + 1)) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct mat { double a[3][3]; mat() { for (int i = (int)(0); i <= (int)(2); ++i) for (int j = (int)(0); j <= (int)(2); ++j) a[i][j] = 0; } mat operator*(const mat &b) const { mat c; for (int i = (int)(0); i <= (int)(2); ++i) for (int j = (int)(0); j <= (int)(2); ++j) for (int k = (int)(0); k <= (int)(2); ++k) c.a[i][j] += a[i][k] * b.a[k][j]; return c; } }; struct node { int id; long long las; mat pre; }; vector<node> S; mat bas[100005], f[40], org; pair<double, double> p[100005]; int n; long long m; double b; int main() { scanf( %d%lld , &n, &m); for (int i = (int)(1); i <= (int)(n); ++i) { double x, y, v; scanf( %lf%lf%lf , &x, &y, &v); b = max(b, y * v); p[i] = pair<double, double>(x * v, v); } sort(p + 1, p + n + 1, greater<pair<double, double> >()); org.a[2][0] = 1; for (int i = (int)(1); i <= (int)(n); ++i) { bas[i].a[1][1] = 1; bas[i].a[2][2] = 1; bas[i].a[0][0] = 1 - p[i].second; bas[i].a[0][1] = p[i].second; bas[i].a[0][2] = p[i].first; bas[i].a[1][2] = b; } S.push_back((node){1, m, org}); for (int i = (int)(2); i <= (int)(n); ++i) { for (;;) if ((bas[i] * S.back().pre).a[0][0] > (bas[S.back().id] * S.back().pre).a[0][0]) S.pop_back(); else break; if (!S.back().las) continue; node tmp = S.back(); f[0] = bas[tmp.id]; for (int j = (int)(1); j <= (int)(35); ++j) f[j] = f[j - 1] * f[j - 1]; for (int j = (int)(35); j >= (int)(0); --j) if (tmp.las - (1ll << j) >= 1) if ((bas[i] * f[j] * tmp.pre).a[0][0] <= (bas[tmp.id] * f[j] * tmp.pre).a[0][0]) { tmp.pre = f[j] * tmp.pre; tmp.las -= (1ll << j); } tmp.pre = f[0] * tmp.pre; --tmp.las; if (tmp.las) tmp.id = i; S.push_back(tmp); } int id = S.back().id; long long las = S.back().las; mat ans = S.back().pre, x = bas[id]; for (; las; las /= 2, x = x * x) if (las & 1) ans = x * ans; printf( %.15lf n , ans.a[0][0]); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, x, p, m = 0; stack<int> s; cin >> n; p = n % 2; for (int i = 0; i < n; i++) { cin >> x; m = max(x, m); if (!s.empty() && s.top() < x) cout << NO , exit(0); if (s.empty() || (s.top() != x)) s.push(x); else s.pop(); } if (p) { if (s.size() == 0) { cout << YES ; } else if (s.size() == 1 && s.top() == m) { cout << YES ; } else { cout << NO ; } } else { if (s.size()) cout << NO ; else cout << YES ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void start() { ios_base::sync_with_stdio(false); cin.tie(NULL); } long long ans = INT_MAX; void solve(long long a, long long b, long long k, long long steps) { if (a == 1 && b == 1) { ans = min(ans, steps); return; } if (a - b > 0) solve(a - b, b, k, steps + 1); if (b - a > 0) solve(a, b - a, k, steps + 1); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); start(); long long n; cin >> n; for (long long i = 1; i < n; i++) { solve(i, n - i, n, 1); } if (ans == INT_MAX) cout << 0 << n ; else cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; queue<pair<int, int> > q; int n, s[3][7005], f[3][7005], k[3], dd[3][7005]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= 2; i++) { cin >> k[i]; for (int j = 1; j <= k[i]; j++) cin >> s[i][j]; } memset(f, 0, sizeof f); q.push(pair<int, int>(1, 0)); q.push(pair<int, int>(2, 0)); f[1][0] = 1; f[2][0] = 1; while (!q.empty()) { int t = q.front().first; int u = q.front().second; q.pop(); if (f[t][u] == 1) { for (int i = 1; i <= k[3 - t]; i++) { int v = (u + n - s[3 - t][i]) % n; if (f[3 - t][v] > 0) continue; f[3 - t][v] = 2; q.push(pair<int, int>(3 - t, v)); } } else { for (int i = 1; i <= k[3 - t]; i++) { int v = (u + n - s[3 - t][i]) % n; if (f[3 - t][v] > 0) continue; ++dd[3 - t][v]; if (dd[3 - t][v] == k[3 - t]) { f[3 - t][v] = 1; q.push(pair<int, int>(3 - t, v)); } } } } for (int i = 1; i <= 2; i++) { for (int j = 1; j <= n - 1; j++) { if (f[i][j] < 1) cout << Loop ; if (f[i][j] == 1) cout << Lose ; if (f[i][j] > 1) cout << Win ; } cout << n ; } return 0; }
|
`include "Definition.v"
module ReadWrite#
(
parameter[ 3 : 0 ]ReadState = 0, // read raw data operation
parameter[ 3 : 0 ]ProcessState = 1, // color correction
parameter[ 3 : 0 ]WriteState = 2
)
(
input Clock,
input Reset,
input[ `size_char - 1 : 0 ]R,
input[ `size_char - 1 : 0 ]G,
input[ `size_char - 1 : 0 ]B,
output reg[ `size_char - 1 : 0 ]R_out,
output reg[ `size_char - 1 : 0 ]G_out,
output reg[ `size_char - 1 : 0 ]B_out
);
reg[ `size_int - 1 : 0 ]ScaleR[ 0 : `SumPixel - 1 ];
reg[ `size_int - 1 : 0 ]ScaleG[ 0 : `SumPixel - 1 ];
reg[ `size_int - 1 : 0 ]ScaleB[ 0 : `SumPixel - 1 ];
reg[ 3 : 0 ]StateNow;
reg[ 3 : 0 ]StateNext;
integer ReadIndex;
integer WriteIndex;
always@( posedge Clock )
begin
if( Reset == 1'b1 )
begin
ReadIndex = 0;
WriteIndex = 0;
StateNext = ReadState;
end
end
always@( StateNext )
StateNow = StateNext;
always@( posedge Clock )
begin
if( StateNow == ReadState )
begin
////////////////
// read raw data
ScaleR[ ReadIndex ] = R << `ScaleBit;
ScaleG[ ReadIndex ] = G << `ScaleBit;
ScaleB[ ReadIndex ] = B << `ScaleBit;
ReadIndex = ReadIndex + 1;
if( ReadIndex == `SumPixel )
StateNext = ProcessState;
end
else if( StateNow == WriteState )
begin
if( WriteIndex < `SumPixel )
begin
R_out = ScaleR[ WriteIndex ] >> `ScaleBit;
G_out = ScaleG[ WriteIndex ] >> `ScaleBit;
B_out = ScaleB[ WriteIndex ] >> `ScaleBit;
WriteIndex = WriteIndex + 1;
end
end
end
always@( StateNow )
begin
case( StateNow )
ProcessState:
begin
//
// work here
//
StateNext = WriteState;
end
endcase
end
endmodule
module ReadWrite_testbench;
// Signal declaration
reg Clock;
reg Reset;
reg[ `size_char - 1 : 0 ]R;
reg[ `size_char - 1 : 0 ]G;
reg[ `size_char - 1 : 0 ]B;
wire[ `size_char - 1 : 0 ]R_out;
wire[ `size_char - 1 : 0 ]G_out;
wire[ `size_char - 1 : 0 ]B_out;
reg[ `size_char - 1 : 0 ]RBlock[ 0 : `SumPixel - 1 ];
reg[ `size_char - 1 : 0 ]GBlock[ 0 : `SumPixel - 1 ];
reg[ `size_char - 1 : 0 ]BBlock[ 0 : `SumPixel - 1 ];
integer i;
integer RFile;
integer GFile;
integer BFile;
ReadWrite ReadWrite_test
(
Clock,
Reset,
R,
G,
B,
R_out,
G_out,
B_out
);
initial
begin
#2
begin
// open test data file
$readmemh( "data/IM000565_RAW_20x15R.dat", RBlock );
$readmemh( "data/IM000565_RAW_20x15G.dat", GBlock );
$readmemh( "data/IM000565_RAW_20x15B.dat", BBlock );
end
#2 Reset = 1'b1;
// Apply Stimulus
for( i = 0; i < `SumPixel; i = i + 1 )
begin
#2
begin
// initialization, start to read data into buffer
Reset = 1'b0;
R = RBlock[ i ];
G = GBlock[ i ];
B = BBlock[ i ];
end
end
#2
begin
RFile = $fopen( "data/R.dat" );
GFile = $fopen( "data/G.dat" );
BFile = $fopen( "data/B.dat" );
end
for( i = 0; i < `SumPixel; i = i + 1 )
begin
#2
begin
// display information on the screen
//$display( "R = %d, G = %d, B = %d\t\tR = %d, G = %d, B = %d",
// RBlock[ i ], GBlock[ i ], BBlock[ i ], R_out, G_out, B_out );
if( i % 16 == 0 )
begin
$fwrite( RFile, "\n" );
$fwrite( GFile, "\n" );
$fwrite( BFile, "\n" );
end
$fwrite( RFile, "%X ", R_out );
$fwrite( GFile, "%X ", G_out );
$fwrite( BFile, "%X ", B_out );
end
end
$fclose( RFile );
$fclose( GFile );
$fclose( BFile );
#100000 $stop;
#100000 $finish;
end
initial Clock = 0;
always #1 Clock = ~Clock; //Toggle Clock
endmodule
|
module data_gen_submodule (
//input
input clk ,
input reset_n ,
//output
output [11:0] Data_A ,
output [11:0] Data_B ,
output [11:0] Data_C ,
output [11:0] Data_D ,
output [11:0] Data_E ,
output [11:0] Data_F ,
output [11:0] Data_G ,
output [11:0] Data_H
);
//wire
//reg
reg [11:0] data_buf ;
always@(posedge clk or negedge reset_n )
begin
if (!reset_n)
begin
data_buf <= 0 ;
end
else if (data_buf < 511)
data_buf <= data_buf + 1'b1 ;
else
data_buf <= 0 ;
end
assign Data_A = data_buf ;
assign Data_B = Data_A+1 ;
assign Data_C = Data_B+1 ;
assign Data_D = Data_C+1 ;
assign Data_E = data_buf ;
assign Data_F = Data_E+1 ;
assign Data_G = Data_F+1 ;
assign Data_H = Data_G+1 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; set<pair<int, int> > s, e; long long dp[N]; int l[N], r[N]; struct Point { int x, h, k; bool f; } p[2 * N]; struct temp { int h, k; } q[N]; int m; bool cmp1(const temp &a, const temp &b) { return a.h > b.h; } bool cmp(const Point &a, const Point &b) { if (a.x != b.x) return a.x < b.x; if (a.f != b.f) return a.f; return a.k < b.k; } vector<int> tran[N]; int main() { set<pair<int, int> >::iterator it; int n, t; scanf( %d%d , &n, &t); for (int i = 0; i < n; i++) { int h; scanf( %d%d%d , &h, &l[i + 1], &r[i + 1]); p[m].x = l[i + 1], p[m].h = h, p[m].k = i + 1, p[m++].f = false; p[m].x = r[i + 1], p[m].h = h, p[m].k = i + 1, p[m++].f = true; q[i].h = h, q[i].k = i + 1; } l[0] = -(1 << 30), r[0] = (1 << 30); l[n + 1] = -(1 << 30), r[n + 1] = (1 << 30); q[n].h = t, q[n].k = 0; q[n + 1].h = 0, q[n + 1].k = n + 1; sort(p, p + m, cmp); sort(q, q + n + 2, cmp1); s.insert(make_pair(t, 0)); s.insert(make_pair(0, n + 1)); for (int i = 0; i < m; i++) { if (p[i].f) { it = s.find(make_pair(p[i].h, p[i].k)); if (it != s.end()) s.erase(it); } else { int a, b; it = s.lower_bound(make_pair(p[i].h, 0)); a = it->second; --it; b = it->second; it = e.find(make_pair(a, b)); if (it != e.end()) e.erase(it); e.insert(make_pair(a, p[i].k)); e.insert(make_pair(p[i].k, b)); s.insert(make_pair(p[i].h, p[i].k)); } } for (it = e.begin(); it != e.end(); it++) tran[it->first].push_back(it->second); dp[0] = (1ll << 50); for (int i = 0; i < n + 2; i++) { int now = q[i].k; for (int j = 0; j < tran[now].size(); j++) { int tag = tran[now][j]; dp[tag] = max( dp[tag], min(dp[now], min((long long)r[now], (long long)r[tag]) - max((long long)l[now], (long long)l[tag]))); } } printf( %I64d n , dp[n + 1]); return 0; }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
/* TODO: Describe the following mode */
module fa
(input a_c,
input b_c,
input cin_c,
output cout_t,
output sum_x);
wire a_c;
wire b_c;
wire cout_t;
wire cin_c;
wire sum_x;
wire VCC;
assign VCC = 1'b1;
cycloneiv_lcell_comb gen_sum_0 (.combout(sum_x),
.dataa(a_c),
.datab(b_c),
.datac(cin_c),
.datad(VCC));
defparam syn__05_.lut_mask = 16'b1001011010010110;
defparam syn__05_.sum_lutc_input = "datac";
cycloneiv_lcell_comb gen_cout_0 (.combout(cout_t),
.dataa(cin_c),
.datab(b_c),
.datac(a_c),
.datad(VCC));
defparam syn__06_.lut_mask = 16'b1110000011100000;
defparam syn__06_.sum_lutc_input = "datac";
endmodule // fa
module f_stage();
endmodule // f_stage
module f_end();
endmodule // f_end
module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH < 5;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
fa f0 (.a_c(AA[0]),
.b_c(BB[0]),
.cin_c(C[0]),
.cout_t(C0[1]),
.sum_x(Y[0]));
genvar i;
generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
end endgenerate
assign X = AA ^ BB;
endmodule
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// 'PFD' design based on ZEK code
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
module fapch_zek
(
input wire fclk,
input wire rdat_n,
output reg vg_rclk,
output reg vg_rawr
);
reg [3:0] rdat_sr;
reg rawr_sync;
reg rdat_n_r;
always @ (posedge fclk)
begin
rdat_n_r <= rdat_n;
rdat_sr <= { rdat_sr[2:0], rdat_n_r };
if (rdat_sr == 4'hF || rdat_sr == 4'h0)
rawr_sync <= rdat_sr[3];
end
// rawr
reg [4:0] rawr_sr;
always @ (posedge fclk)
begin
rawr_sr <= { rawr_sr[3:0], rawr_sync };
vg_rawr <= !(rawr_sr[4] && !rawr_sr[0] ); // rawr 140ns
end
// rclk
reg [5:0] counter = 0;
wire[5:0] delta = 27 - counter;
wire[5:0] shift = { delta[5], delta[5], delta[4:1] }; // sign div
wire[5:0] inc = rawr_sr[1:0] == 2'b10 ? shift : 1;
always @ (posedge fclk)
begin
if (counter < 55)
counter <= counter + inc;
else
begin
counter <= 0;
vg_rclk = ~vg_rclk;
end
end
initial
vg_rclk = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, c0, d0; cin >> n >> m >> c0 >> d0; long long a[m + 4], b[m + 5], c[m + 5], d[m + 5]; for (int i = 1; i <= m; i++) { cin >> a[i] >> b[i] >> c[i] >> d[i]; a[i] /= b[i]; } c[0] = c0; a[0] = 1005; long long dp[n + 4][m + 4]; memset(dp, 0, sizeof(dp)); for (long long i = 1; i <= n; i++) { for (long long j = 0; j <= m; j++) { for (long long k = 0; k <= a[j]; k++) { if (i - c[j] * k < 0) break; if (j == 0) { dp[i][j] = k * d0; } else { dp[i][j] = max(dp[i - c[j] * k][j - 1] + k * d[j], dp[i][j]); } } } } cout << dp[n][m] << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long t, n, i, j, k; double p, q, m; cin >> n >> m; p = pow(1.000000011, m); q = n * p; printf( %.12lf , q); return 0; }
|
#include <bits/stdc++.h> using namespace std; int t = 1; void solve() { long long n, i, k, s = 0, b; cin >> n >> k; long long a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); b = a[0]; for (i = 1; i < n; i++) { long long c = (k - a[i]) / b; if (c > 0) s += c; } cout << s << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> t; while (t--) { solve(); } }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( no-stack-protector ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( fast-math ) #pragma GCC target( sse,sse2,sse3,ssse3,popcnt,abm,mmx,tune=native ) using namespace std; template <typename T> void uin(T &a, T b) { if (b < a) { a = b; } } template <typename T> void uax(T &a, T b) { if (b > a) { a = b; } } const long long N = 100 * 1000 + 228; vector<long long> g[N]; long long deg[N]; long long h[N], p[N]; void dfs(long long v, long long par = -1) { h[v] = (par == -1 ? 0 : h[par] + 1); p[v] = par; for (long long to : g[v]) { if (to != par) dfs(to, v); } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; for (long long i = 0; i < n - 1; ++i) { long long u, v; cin >> u >> v; ++deg[u]; ++deg[v]; g[u].emplace_back(v); g[v].emplace_back(u); } long long root = 1; for (long long i = 1; i <= n; ++i) { if (deg[i] > 1) { root = i; break; } } dfs(root); bool even = 0, odd = 0; for (long long i = 1; i <= n; ++i) { if (deg[i] == 1) { if (h[i] & 1) odd = 1; else even = 1; } } long long min_colors = 0; if (even && odd) { min_colors = 3; } else { min_colors = 1; } vector<long long> pars; long long leafs = 0; for (long long i = 1; i <= n; ++i) { if (deg[i] == 1) { pars.emplace_back(p[i]); ++leafs; } } sort(pars.begin(), pars.end()); pars.erase(unique(pars.begin(), pars.end()), pars.end()); long long max_colors = (long long)pars.size(); max_colors += (n - 1 - leafs); cout << min_colors << << max_colors << n ; return 0; }
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// -----------------------------------------------------------
// PLI byte transport HDL interface
//
// @author jyeap, gkwan
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_pli_streaming (
clk,
reset_n,
// source out
source_valid,
source_data,
source_ready,
// sink in
sink_valid,
sink_data,
sink_ready,
// resetrequest
resetrequest
);
parameter PLI_PORT = 50000;
parameter PURPOSE = 0;
input clk;
input reset_n;
output reg source_valid;
output reg [7 : 0] source_data;
input source_ready;
input sink_valid;
input [7 : 0] sink_data;
output reg sink_ready;
output reg resetrequest;
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(.PURPOSE(PURPOSE)) jtag_dc_streaming (
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)
);
always @* begin
source_valid = jtag_source_valid;
source_data = jtag_source_data;
sink_ready = jtag_sink_ready;
resetrequest = jtag_resetrequest;
//synthesis translate_off
source_valid = pli_out_valid;
source_data = pli_out_data;
sink_ready = pli_in_ready;
resetrequest = 0;
//synthesis translate_on
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxk = 51; struct matrix { bool e[maxk][maxk]; int sz; void print() { for (int i = 0, _n = (sz); i < _n; i++) { for (int j = 0, _n = (sz); j < _n; j++) { printf( %d , e[i][j]); } printf( n ); } printf( n ); } }; matrix operator*(const matrix &A, const matrix &B) { matrix ret; memset(&ret, 0, sizeof(ret)); ret.sz = A.sz; for (int i = 0, _n = (A.sz); i < _n; i++) for (int k = 0, _n = (A.sz); k < _n; k++) if (A.e[i][k]) for (int j = 0, _n = (A.sz); j < _n; j++) ret.e[i][j] ^= B.e[k][j]; return ret; } matrix one; matrix pow2(matrix M, long long deg) { matrix ret; memset(&ret, 0, sizeof(ret)); for (int i = 0, _n = (M.sz); i < _n; i++) ret.e[i][i] = 1; ret.sz = M.sz; while (deg) { if (deg & 1) ret = ret * M; M = M * M; deg >>= 1; } return ret; } long long my_rand() { long long ret = 0; for (int i = 0, _n = (4); i < _n; i++) ret = (ret << 15) + rand() % (1 << 15); return ret; } vector<long long> prime_div; int check_one(const matrix &tmp) { bool zero = 1; for (int i = 0, _n = (tmp.sz); i < _n; i++) for (int j = 0, _n = (tmp.sz); j < _n; j++) if (tmp.e[i][j]) zero = 0; if (zero) return 0; for (int i = 0, _n = (tmp.sz); i < _n; i++) for (int j = 0, _n = (tmp.sz); j < _n; j++) if (tmp.e[i][j] != (i == j)) return -1; return 1; } bool check(long long c, int k) { matrix cM; memset(&cM, 0, sizeof(cM)); cM.sz = k; for (int i = 0, _n = (k - 1); i < _n; i++) cM.e[i][i + 1] = 1; for (int i = 0, _n = (k); i < _n; i++) cM.e[k - 1][k - i - 1] = ((c & (1ll << i)) > 0); matrix tmp = pow2(cM, (1ll << k) - 1); long long m = (1ll << k) - 1; if (check_one(tmp) == 1) { for (int i = 0, _n = (prime_div.size()); i < _n; i++) { tmp = pow2(cM, m / prime_div[i]); if (check_one(tmp) != -1) return 0; } return 1; } return 0; } long long find_ans(int k) { prime_div.clear(); long long m = (1ll << k) - 1; for (long long q = 2; q * q <= m; q++) { if (m % q == 0) { while (m % q == 0) m /= q; prime_div.push_back(q); } } if (m > 1) prime_div.push_back(m); one.sz = k; long long c = 0; for (c = (1ll << (k - 1)); !check(c, k); c++) ; return c; } void generate_ans() { memset(&one, 0, sizeof(one)); for (int k = 0, _n = (50); k < _n; k++) one.e[k][k] = 1; for (int k = 2, _b = (50); k <= _b; k++) { long long c = find_ans(k); cout << c << ll, << endl; fprintf(stderr, %d n , k); } } long long const_ans[51] = { 0ll, 0ll, 3ll, 5ll, 9ll, 18ll, 33ll, 65ll, 142ll, 264ll, 516ll, 1026ll, 2089ll, 4109ll, 8213ll, 16385ll, 32790ll, 65540ll, 131091ll, 262163ll, 524292ll, 1048578ll, 2097153ll, 4194320ll, 8388621ll, 16777220ll, 33554467ll, 67108883ll, 134217732ll, 268435458ll, 536870953ll, 1073741828ll, 2147483735ll, 4294967337ll, 8589934707ll, 17179869186ll, 34359738427ll, 68719476767ll, 137438953521ll, 274877906952ll, 549755813916ll, 1099511627780ll, 2199023255583ll, 4398046511148ll, 8796093022258ll, 17592186044429ll, 35184372088983ll, 70368744177680ll, 140737488355419ll, 281474976710712ll, 562949953421326ll, }; int k; int main() { scanf( %d , &k); const_ans[k] = find_ans(k); for (int i = 0, _n = (k); i < _n; i++) { if (i) printf( ); printf( %d , (const_ans[k] & (1ll << i)) > 0); } printf( n ); for (int i = 0, _n = (k - 1); i < _n; i++) printf( 0 ); printf( 1 n ); return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:200000000 ) using namespace std; template <typename T> inline T Abs(T x) { return (x >= 0) ? x : -x; } template <typename T> inline T sqr(T x) { return x * x; } template <typename T> string toStr(T x) { stringstream st; st << x; string s; st >> s; return s; } inline int nextInt() { int x; if (scanf( %d , &x) != 1) throw; return x; } inline long long nextInt64() { long long x; if (scanf( %I64d , &x) != 1) throw; return x; } inline double nextDouble() { double x; if (scanf( %lf , &x) != 1) throw; return x; } const int INF = (int)1E9; const long long INF64 = (long long)1E18; const long double EPS = 1E-9; const long double PI = 3.1415926535897932384626433832795; const int MAXN = 3000100; int n, a[MAXN], l[MAXN], r[MAXN]; int tree[MAXN]; int get(int x) { int ans = 0; if (x < 0) return ans; for (; x >= 0; x = (x & (x + 1)) - 1) ans += tree[x]; return ans; } int get(int l, int r) { int ans = get(r); if (l > 0) ans -= get(l - 1); return ans; } void update(int x, int value) { for (; x < 3 * n; x = (x | (x + 1))) tree[x] += value; } int main() { n = nextInt(); for (int i = 0; i < (int)(n); i++) a[i + n] = a[i + 2 * n] = a[i] = nextInt(); int n1 = n / 2, n2 = n - n1; vector<pair<int, int> > st; for (int i = 0; i < (int)(3 * n); i++) { while (!st.empty() && st.back().first <= a[i]) st.pop_back(); if (st.empty()) l[i] = i - n1 + 1; else l[i] = st.back().second; st.push_back(make_pair(a[i], i)); } st.clear(); for (int i = (int)(3 * n) - 1; i >= 0; i--) { while (!st.empty() && st.back().first <= a[i]) st.pop_back(); if (st.empty()) r[i] = i + n2; else r[i] = st.back().second; st.push_back(make_pair(a[i], i)); } st.clear(); for (int i = 0; i < (int)(n); i++) { update(i, +1); update(i + n, +1); update(i + 2 * n, +1); st.push_back(make_pair(a[i], i)); } long long ans = 0; sort((st).begin(), (st).end()); for (int i = 0; i < (int)(n); i++) { int x = st[i].second; int ll = l[x + n], rr = r[x + n]; if ((ll % n) == (rr % n)) ll++; update(x, -1); update(x + n, -1); update(x + 2 * n, -1); ans += get(ll, rr); } cout << ans << endl; return 0; }
|
module fan_motor_driver(
// Qsys bus interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input [2:0] avs_ctrl_address,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input rsi_PWMRST_reset,
input csi_PWMCLK_clk,
//brush_moter_interface
output fan
);
//Qsys controller
reg on_off;
reg [31:0] PWM_width;
reg [31:0] PWM_frequent;
reg [31:0] read_data;
assign avs_ctrl_readdata = read_data;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else if(avs_ctrl_write)
begin
case(avs_ctrl_address)
1: begin
if(avs_ctrl_byteenable[3]) PWM_frequent[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_frequent[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_frequent[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_frequent[7:0] <= avs_ctrl_writedata[7:0];
end
2: begin
if(avs_ctrl_byteenable[3]) PWM_width[31:24] <= avs_ctrl_writedata[31:24];
if(avs_ctrl_byteenable[2]) PWM_width[23:16] <= avs_ctrl_writedata[23:16];
if(avs_ctrl_byteenable[1]) PWM_width[15:8] <= avs_ctrl_writedata[15:8];
if(avs_ctrl_byteenable[0]) PWM_width[7:0] <= avs_ctrl_writedata[7:0];
end
3: on_off <= avs_ctrl_writedata[0];
default:;
endcase
end
else begin
case(avs_ctrl_address)
0: read_data <= 32'hEA680003;
1: read_data <= PWM_frequent;
2: read_data <= PWM_width;
3: read_data <= {31'b0,on_off};
default: read_data <= 32'b0;
endcase
end
end
//PWM controller
reg [31:0] PWM;
reg PWM_out;
always @ (posedge csi_PWMCLK_clk or posedge rsi_PWMRST_reset)
begin
if(rsi_PWMRST_reset)
PWM <= 32'b0;
else
begin
PWM <= PWM + PWM_frequent;
PWM_out <=(PWM > PWM_width) ? 0:1;
end
end
//Output
assign fan = on_off?PWM_out:0;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct __timestamper {}; struct change { int s, t, u; }; vector<long long> solve(vector<int> a, vector<change> b) { long long sum = 0; for (auto x : a) sum += x; vector<long long> ans; int n = a.size(); vector<int> cntr(n); auto change_counter = [&](int i, int delta) { sum -= max(0, a[i] - cntr[i]); cntr[i] += delta; sum += max(0, a[i] - cntr[i]); }; map<pair<int, int>, int> mp; for (auto c : b) { auto it = mp.find({c.s, c.t}); if (it != mp.end()) { change_counter(it->second, -1); mp.erase(it); } if (c.u != -1) { mp[{c.s, c.t}] = c.u; change_counter(c.u, +1); } ans.push_back(sum); } return ans; } int main() { int n; while (scanf( %d , &n) == 1) { vector<int> a(n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } int q; scanf( %d , &q); vector<change> b(q); for (int i = 0; i < q; i++) { scanf( %d%d%d , &b[i].s, &b[i].t, &b[i].u); b[i].s--; b[i].u--; } auto ans = solve(a, b); for (auto x : ans) printf( %lld n , x); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int d, n, x, ans; int main() { cin >> d; cin >> n; for (int i = 0; i < n - 1; i++) { cin >> x; ans += d - x; } cin >> x; cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; unsigned long long tcc, n, m; int main() { scanf( %lld , &tcc); while (tcc--) { scanf( %lld %lld , &n, &m); unsigned long long sum = 0, m2 = m, t = 10; while (t-- && m2 <= n) { sum += m2 % 10; m2 += m; } m2 = m * 10; t = n / m2; sum *= t; n -= m2 * t; m2 = m; while (m2 <= n) { sum += m2 % 10; m2 += m; } printf( %lld n , sum); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int b[1100000], a[1100000], pre[1100000]; int main() { int n, m, k, i, j, s, cnt, len = 0, max = 0; long long ans = 0; scanf( %d%d%d , &n, &m, &k); for (i = 1; i <= m; ++i) { scanf( %d , &s); b[s] = 1; } b[n] = 1; for (i = 1; i < n; ++i) if (b[i]) pre[i] = pre[i - 1]; else pre[i] = i; for (i = 1; i < n; ++i) { if (b[i]) ++len; else len = 0; if (len > max) max = len; } for (i = 1; i <= k; ++i) scanf( %d , &a[i]); if (max == 0) max = 1; else ++max; for (i = max; i <= k; ++i) { cnt = 0; j = 0; if (b[j]) continue; while (j < n) { ++cnt; if (!b[j]) j = j + i; else j = pre[j] + i; } if (ans == 0) ans = (long long)cnt * a[i]; else if ((long long)cnt * a[i] < ans) ans = (long long)cnt * a[i]; } if (ans > 0) printf( %I64d , ans); else printf( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t; cin >> t; while (t != 0) { t--; int n, k, l = -1, r = -1; cin >> n >> k; int c = k + 1, z, res = 0; string x; cin >> x; for (int i = 0; i < n; i++) { if (x[i] == 1 ) { r = i; if (l == -1) z = r - l - 1 - k; else z = r - l - 1 - (2 * k); if (z > 0) { c = k + 1; for (int j = 0; j < z; j++) { if (c > k) { res++; c = 0; } c++; } } l = i; z = 0; } } r = n; if (l == -1) z = r - l - 1; else z = r - l - 1 - k; if (z > 0) { c = k + 1; for (int j = 0; j < z; j++) { if (c > k) { res++; c = 0; } c++; } } cout << res << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(false); long long n; cin >> n; set<long long> s = {-2, -1}; vector<long long> arr(n, 0); while (n--) { long long x; cin >> x; --x; if ((*prev(s.end())) > x && (*prev(prev(s.end()))) < x) ++arr[(*prev(s.end()))]; if ((*prev(s.end())) < x) --arr[x]; s.insert(x); } cout << (max_element(arr.begin(), arr.end()) - arr.begin() + 1) << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const long long Mod = 1000000007LL, INF = 1e9, LINF = 1e18; const long double Pi = 3.141592653589793116, EPS = 1e-9, Gold = ((1 + sqrt(5)) / 2); long long keymod[] = {1000000007LL, 1000000009LL, 1000000021LL, 1000000033LL}; long long keyCount = sizeof(keymod) / sizeof(long long); mt19937 rng32(chrono::steady_clock::now().time_since_epoch().count()); mt19937_64 rng64(chrono::steady_clock::now().time_since_epoch().count()); template <class T> int getbit(T s, int i) { return (s >> i) & 1; } template <class T> T onbit(T s, int i) { return s | (T(1) << i); } template <class T> T offbit(T s, int i) { return s & (~(T(1) << i)); } template <class T> int cntbit(T s) { return __builtin_popcountll(s); } auto TimeStart = chrono::steady_clock::now(); auto TimeEnd = chrono::steady_clock::now(); void ControlIO(int argc, char* argv[]); void TimerStart(); void TimerStop(); void Exit(); string cppstr_infile = FILE.IN ; string cppstr_outfile = FILE.OUT ; int n; vector<int> c; vector<long long> dp; vector<vector<int>> adj; vector<vector<int>> DependencyList; set<int> FinalList; void DFS_GetList(int z, int last, vector<int>& MaxLeaf, vector<int>& MaxID, vector<int>& MaxCnt) { dp[z] = 0; bool isLeaf = true; for (auto t : adj[z]) { if (t == last) continue; isLeaf = false; DFS_GetList(t, z, MaxLeaf, MaxID, MaxCnt); dp[z] += dp[t]; if (MaxLeaf[t] >= MaxLeaf[z]) MaxID[z] = MaxID[t]; if (MaxLeaf[t] > MaxLeaf[z]) MaxCnt[z] = MaxCnt[t]; else if (MaxLeaf[t] == MaxLeaf[z]) MaxCnt[z] += MaxCnt[t]; MaxLeaf[z] = max(MaxLeaf[z], MaxLeaf[t]); } if (isLeaf) { MaxLeaf[z] = dp[z] = c[z]; MaxID[z] = z; MaxCnt[z] = 1; DependencyList[z].push_back(z); return; } int MaxRemovable = -MaxLeaf[z]; if (MaxRemovable + c[z] > 0) return; if (MaxRemovable + c[z] < 0 && MaxCnt[z] == 1) { DependencyList[MaxID[z]].clear(); } if (MaxCnt[z] == 1) DependencyList[MaxID[z]].push_back(z); else { DependencyList[z].push_back(z); MaxID[z] = z; } dp[z] += (MaxRemovable + c[z]); MaxLeaf[z] = c[z]; MaxCnt[z] = 1; } void Input() { cin >> n; c.resize(n); dp.resize(n); adj.resize(n); DependencyList.resize(n); for (auto& z : c) cin >> z; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; a--; b--; adj[a].push_back(b); adj[b].push_back(a); } } void Solve() { vector<int> MaxLeaf(n, -1), MaxID(n, -1), MaxCnt(n, 0); DFS_GetList(0, -1, MaxLeaf, MaxID, MaxCnt); for (int id = 0; id < n; id++) { for (auto z : DependencyList[id]) FinalList.insert(z + 1); } cout << dp[0] << << FinalList.size() << n ; for (auto it = FinalList.begin(); it != FinalList.end(); it++) cout << (*it) << ; cout << n ; } int main(int argc, char* argv[]) { ControlIO(argc, argv); ios_base::sync_with_stdio(0); cin.tie(NULL); Input(); TimerStart(); Solve(); TimerStop(); return 0; } void ControlIO(int argc, char* argv[]) { char* infile = new char[cppstr_infile.size() + 1]; char* outfile = new char[cppstr_outfile.size() + 1]; strcpy(infile, cppstr_infile.c_str()); strcpy(outfile, cppstr_outfile.c_str()); } void TimerStart() {} void TimerStop() {} void Exit() { TimerStop(); exit(0); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; int s[n]; int m[n]; string st; cin >> st; for (int i = 0; i < n; i++) s[i] = st[i] - 0 ; cin >> st; for (int i = 0; i < n; i++) m[i] = st[i] - 0 ; sort(s, s + n); sort(m, m + n); int sher = 0; int mor = 0; int pos = 0; for (int i = 0; i < n; i++) { if (s[pos] < m[i]) { sher++; pos++; } } pos = 0; mor = n; for (int i = 0; i < n; i++) { if (m[i] >= s[pos]) mor--, pos++; } cout << mor << n << sher; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_TB_V
`define SKY130_FD_SC_LS__A32OI_TB_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a32oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a32oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_TB_V
|
module neopixels(
input CLOCK_50,
input [1:0] KEY,
output data
);
reg r_data;
reg [3:0] state_reg;
reg [3:0] state_set = 4'b0;
reg [7:0] timer_0 = 7'b0;
reg [7:0] timer_0_compare = 7'd40; // 0.8us
reg timer_0_run = 1'b0;
reg timer_0_match = 1'b0;
reg [32:0] counter = 32'b0;
reg lighting = 1'b0;
reg [7:0] press_count = 8'b0;
reg [1:0] key_edge_detect = 2'b00;
reg on = 1'b1;
assign data = r_data;
always @(posedge CLOCK_50) begin
// Send 24 "1" for each release of KEY[1] which should turn on the next pixel as white.
if (key_edge_detect == 2'b10) begin // falling edge of KEY[1]
lighting <= 1'b1;
counter <= 1'b0;
press_count <= press_count + 1'b1;
// 16 pixels
if (press_count == 16) begin
press_count <= 1'b0;
on <= !on;
end
end
if (lighting) begin
if (counter == (32'd24 * press_count)) begin
lighting <= 1'b0;
end else begin
if (state_reg == 4'b0 && state_set == 4'b0) begin
counter <= counter + 1'b1;
if (on) begin
// Send a high
state_set <= 4'b0001;
end else begin
// Send a low
state_set <= 4'b0100;
end
end else begin
// Wait
state_set <= 4'b0;
end
end
end else begin
state_set <= 4'b0;
end
end
always @(posedge CLOCK_50) begin
key_edge_detect <= {key_edge_detect[0], KEY[1]};
end
always @(posedge CLOCK_50) begin
if (timer_0_run) begin
if (timer_0 == timer_0_compare) begin
timer_0 <= 1'b0;
timer_0_match <= 1'b1;
end else begin
timer_0 <= timer_0 + 1'b1;
timer_0_match <= 1'b0;
end
end else begin
timer_0 <= 1'b0;
timer_0_match <= 1'b0;
end
end
always @(posedge CLOCK_50) begin
case (state_reg)
4'b0000: // Idle
begin
if (state_set != 4'b0) begin
state_reg <= state_set;
end
r_data <= 1'b0;
end
4'b0001: // Send first part of high
begin
if (timer_0_match) begin
timer_0_run <= 1'b0;
state_reg <= 4'b0010;
end else begin
r_data <= 1'b1;
// Start the counter
timer_0_compare <= 7'd40; // 0.8us (800ns)
timer_0_run <= 1'b1;
end
end
4'b0010: // Send second part of high
begin
if (timer_0_match) begin
timer_0_run <= 1'b0;
state_reg <= 4'b0;
end else begin
r_data <= 1'b0;
// Start the counter
timer_0_compare <= 7'd20; // 0.4us (400ns)
timer_0_run <= 1'b1;
end
end
4'b0100: // Send first part of low
begin
if (timer_0_match) begin
timer_0_run <= 1'b0;
state_reg <= 4'b1000;
end else begin
r_data <= 1'b1;
// Start the counter
timer_0_compare <= 7'd20; // 0.4us (400ns)
timer_0_run <= 1'b1;
end
end
4'b1000: // Send second part of low
begin
if (timer_0_match) begin
timer_0_run <= 1'b0;
state_reg <= 4'b0;
end else begin
r_data <= 1'b0;
// Start the counter
timer_0_compare <= 7'd40; // 0.8us (800ns)
timer_0_run <= 1'b1;
end
end
default: // Idle
begin
state_reg <= 4'b0;
end
endcase
end
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 20843 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4096,
w4095,
w128,
w4223,
w16892,
w21115,
w16,
w21099,
w256,
w20843;
assign w1 = i_data0;
assign w128 = w1 << 7;
assign w16 = w1 << 4;
assign w16892 = w4223 << 2;
assign w20843 = w21099 - w256;
assign w21099 = w21115 - w16;
assign w21115 = w4223 + w16892;
assign w256 = w1 << 8;
assign w4095 = w4096 - w1;
assign w4096 = w1 << 12;
assign w4223 = w4095 + w128;
assign o_data0 = w20843;
//multiplier_block area estimate = 8858.20315051765;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : gtx_drp_chanalign_fix_3752_v6.v
// Version : 2.4
//--
//-- Description: Virtex6 Workaround for deadlock due lane-lane skew Bug
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ps
module GTX_DRP_CHANALIGN_FIX_3752_V6
#(
parameter TCQ = 1,
parameter C_SIMULATION = 0 // Set to 1 for simulation
)
(
output reg dwe,
output reg [15:0] din, //THIS IS THE INPUT TO THE DRP
output reg den,
output reg [7:0] daddr,
output reg [3:0] drpstate,
input write_ts1,
input write_fts,
input [15:0] dout, //THIS IS THE OUTPUT OF THE DRP
input drdy,
input Reset_n,
input drp_clk
);
reg [7:0] next_daddr;
reg [3:0] next_drpstate;
reg write_ts1_gated;
reg write_fts_gated;
localparam DRP_IDLE_FTS = 1;
localparam DRP_IDLE_TS1 = 2;
localparam DRP_RESET = 3;
localparam DRP_WRITE_FTS = 6;
localparam DRP_WRITE_DONE_FTS = 7;
localparam DRP_WRITE_TS1 = 8;
localparam DRP_WRITE_DONE_TS1 = 9;
localparam DRP_COM = 10'b0110111100;
localparam DRP_FTS = 10'b0100111100;
localparam DRP_TS1 = 10'b0001001010;
always @(posedge drp_clk) begin
if ( ~Reset_n ) begin
daddr <= #(TCQ) 8'h8;
drpstate <= #(TCQ) DRP_RESET;
write_ts1_gated <= #(TCQ) 0;
write_fts_gated <= #(TCQ) 0;
end else begin
daddr <= #(TCQ) next_daddr;
drpstate <= #(TCQ) next_drpstate;
write_ts1_gated <= #(TCQ) write_ts1;
write_fts_gated <= #(TCQ) write_fts;
end
end
always @(*) begin
// DEFAULT CONDITIONS
next_drpstate=drpstate;
next_daddr=daddr;
den=0;
din=0;
dwe=0;
case(drpstate)
// RESET CONDITION, WE NEED TO READ THE TOP 6 BITS OF THE DRP REGISTER WHEN WE GET THE WRITE FTS TRIGGER
DRP_RESET : begin
next_drpstate= DRP_WRITE_TS1;
next_daddr=8'h8;
end
// WRITE FTS SEQUENCE
DRP_WRITE_FTS : begin
den=1;
dwe=1;
case (daddr)
8'h8 : din = 16'hFD3C;
8'h9 : din = 16'hC53C;
8'hA : din = 16'hFDBC;
8'hB : din = 16'h853C;
endcase
next_drpstate=DRP_WRITE_DONE_FTS;
end
// WAIT FOR FTS SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO FTS IDLE
DRP_WRITE_DONE_FTS : begin
if(drdy) begin
if(daddr==8'hB) begin
next_drpstate=DRP_IDLE_FTS;
next_daddr=8'h8;
end else begin
next_drpstate=DRP_WRITE_FTS;
next_daddr=daddr+1'b1;
end
end
end
// FTS IDLE: WAIT HERE UNTIL WE NEED TO WRITE TS1
DRP_IDLE_FTS : begin
if(write_ts1_gated) begin
next_drpstate=DRP_WRITE_TS1;
next_daddr=8'h8;
end
end
// WRITE TS1 SEQUENCE
DRP_WRITE_TS1 : begin
den=1;
dwe=1;
case (daddr)
8'h8 : din = 16'hFC4A;
8'h9 : din = 16'hDC4A;
8'hA : din = 16'hC04A;
8'hB : din = 16'h85BC;
endcase
next_drpstate=DRP_WRITE_DONE_TS1;
end
// WAIT FOR TS1 SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO TS1 IDLE
DRP_WRITE_DONE_TS1 : begin
if(drdy) begin
if(daddr==8'hB) begin
next_drpstate=DRP_IDLE_TS1;
next_daddr=8'h8;
end else begin
next_drpstate=DRP_WRITE_TS1;
next_daddr=daddr+1'b1;
end
end
end
// TS1 IDLE: WAIT HERE UNTIL WE NEED TO WRITE FTS
DRP_IDLE_TS1 : begin
if(write_fts_gated) begin
next_drpstate=DRP_WRITE_FTS;
next_daddr=8'h8;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; ll mod = 1e9 + 7; ll bpow(ll a, ll b, ll m) { a %= m; ll res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } bool cmp(vector<ll> v1, vector<ll> v2) { return v1[1] < v2[1]; } ll power(ll x, ll y) { ll result = 1; while (y > 0) { if (y % 2 == 0) { x = x * x; y = y / 2; } else { result = result * x; y = y - 1; } } return result; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { ll n; cin >> n; ll a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); ll count = 0; ll tar = n / 2; for (int i = 1; i < n; i++) { cout << a[i] << << a[0] << endl; count++; if (count == tar) break; } } }
|
#include <bits/stdc++.h> using namespace std; const int N = 666; const double eps = 1e-10; int n, m, K, cnt, sz; int id[N], nod[N], cur[N]; double deg[N], g[N][N]; bool trap[N]; double v[N][N]; struct node { double vec[N]; } vv[N]; struct mat { double v[166][166]; mat() { memset(v, 0, sizeof(v)); } } ans; node operator*(node a, double w) { for (int i = 0; i <= n; i++) a.vec[i] *= w; return a; } node operator/(node a, double w) { for (int i = 0; i <= n; i++) a.vec[i] /= w; return a; } node operator+(node a, node b) { for (int i = 0; i <= n; i++) a.vec[i] += b.vec[i]; return a; } node operator-(node a, node b) { for (int i = 0; i <= n; i++) a.vec[i] -= b.vec[i]; return a; } mat operator*(mat a, mat b) { mat t; memset(t.v, 0, sizeof(t.v)); for (int i = 0; i <= sz; i++) { for (int j = 0; j <= sz; j++) { for (int k = 0; k <= sz; k++) { t.v[i][j] += a.v[i][k] * b.v[k][j]; } } } return t; } int main() { cin >> n >> m >> K; for (int i = 1; i <= n; i++) scanf( %d , &trap[i]); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); ++deg[x], ++deg[y], ++g[x][y], ++g[y][x]; } for (int i = 1; i <= n; i++) { if (trap[i]) { nod[++cnt] = i, id[i] = cnt; } } sz = cnt; for (int i = 1; i <= n; i++) { v[i][i] = -1; for (int j = 1; j <= n; j++) { if (trap[j]) { v[i][id[j] + n] += 1.0 * g[i][j] / deg[i]; } else { v[i][j] += 1.0 * g[i][j] / deg[i]; } } } for (int i = 1; i <= sz; i++) { vv[i + n].vec[i] = 1; v[i + n][i + n] = 1; } for (int i = 1; i <= n + sz; i++) { int me = -1; double mx = 0; for (int j = 1; j <= n + sz; j++) { if (abs(v[i][j]) > mx) { mx = abs(v[i][j]); me = j; } } if (me == -1 || abs(mx) < eps) continue; cur[i] = me; double val = v[i][me]; for (int j = 1; j <= n + sz; j++) v[i][j] /= val; vv[i] = vv[i] / val; for (int j = 1; j <= n + sz; j++) { if (j != i && abs(v[j][me]) > eps) { double val = v[j][me]; for (int k = 1; k <= n + sz; k++) v[j][k] -= v[i][k] * val; vv[j] = vv[j] - vv[i] * val; } } } for (int i = 1; i <= n + sz; i++) { if ((cur[i] <= n && trap[cur[i]]) || cur[i] == 1) { if (cur[i] == 1) { for (int j = 1; j <= sz; j++) ans.v[0][j] = vv[i].vec[j]; } else { for (int j = 1; j <= sz; j++) ans.v[id[cur[i]]][j] = vv[i].vec[j]; } } } mat res; memset(res.v, 0, sizeof(res.v)); for (int i = 0; i <= sz; i++) res.v[i][i] = 1; int nn = K - 1; for (; nn; nn >>= 1) { if (nn & 1) res = res * ans; ans = ans * ans; } printf( %.10lf n , res.v[0][id[n]]); return 0; }
|
module multistage_interconnect_network(clk, push, d_in, valid, d_out, control);
parameter WIDTH = 64;
parameter IN_PORTS = 16;
parameter PIPELINE_STAGES = 5;
parameter OUT_PORTS = IN_PORTS;
parameter ADDR_WIDTH_PORTS = log2(OUT_PORTS-1); //TODO: max
input clk;
input [0:IN_PORTS-1] push;
input [IN_PORTS*WIDTH-1:0] d_in;
output [0:OUT_PORTS-1] valid;
output [OUT_PORTS*WIDTH-1:0] d_out;
input [ADDR_WIDTH_PORTS-1:0] control;
`include "log2.vh"
integer i, j;
genvar g, g2;
reg [WIDTH:0] input_stage[0:IN_PORTS-1];
wire [WIDTH:0] stage [0:ADDR_WIDTH_PORTS-1][0:IN_PORTS-1];
always @*
for(i = 0; i < IN_PORTS; i = i + 1) begin
input_stage[i][0] = push[i];
input_stage[i][WIDTH -:WIDTH] = d_in[(WIDTH)*(IN_PORTS-i)-1 -: WIDTH];
end
generate for(g = 0; g < IN_PORTS/2; g = g + 1) begin: generate_start
basic_switch #(WIDTH+1) sw(input_stage[g*2], input_stage[g*2+1], stage[0][g*2], stage[0][g*2+1], control[ADDR_WIDTH_PORTS-1]);
//basic_switch #(WIDTH+1) sw(input_stage[g*2], input_stage[g*2+1], stage[0][g*2], stage[0][g*2+1], control[ADDR_WIDTH_PORTS-1]);
end
for(g = 1; g < ADDR_WIDTH_PORTS; g = g + 1) begin: generate_stage
for(g2 = 0; g2 < IN_PORTS/2; g2 = g2 + 1) begin: generate_switch
basic_switch #(WIDTH+1) sw(stage[g-1][g2*2], stage[g-1][(g2^(1<<(ADDR_WIDTH_PORTS-2)))*2+1], stage[g][g2*2], stage[g][g2*2+1], control[ADDR_WIDTH_PORTS-g-1]);
end
end
endgenerate
reg [WIDTH:0] output_pipeline [0:PIPELINE_STAGES-1][0:OUT_PORTS-1];
always @(posedge clk)begin
for(i = 0; i < OUT_PORTS; i = i + 1)
output_pipeline[0][i] <= stage[ADDR_WIDTH_PORTS-1][i];
for(i = 1; i < PIPELINE_STAGES; i = i + 1) begin
for(j = 0; j < OUT_PORTS; j = j + 1) begin
output_pipeline[i][j] <= output_pipeline[i-1][j];
end
end
end
generate for(g=0; g < OUT_PORTS; g = g + 1) begin: generate_output
assign valid[g] = output_pipeline[PIPELINE_STAGES-1][g][0];
assign d_out[WIDTH*(OUT_PORTS-g)-1 -:WIDTH] = output_pipeline[PIPELINE_STAGES-1][g][WIDTH -: WIDTH];
end
endgenerate
//DEBUG
always @(posedge clk) begin
if(push)
for(i = 0; i < ADDR_WIDTH_PORTS; i = i + 1)
for(j = 0; j < OUT_PORTS; j = j + 1)
$display("stages: %d, %d, %b", i, j, stage[i][j]);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCON_SYMBOL_V
`define SKY130_FD_SC_HD__FAHCON_SYMBOL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCON_SYMBOL_V
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module is a simple clock crosser for control signals. It will take
// the asynchronous control signal and synchronize it to the clk domain
// attached to the clk input. It does so by passing the control signal
// through a pair of registers and then sensing the level transition from
// either hi-to-lo or lo-to-hi. *ATTENTION* This module makes the assumption
// that the control signal will always transition every time is asserted.
// i.e.:
// ____ ___________________
// -> ___| |___ and ___| |_____
//
// on the control signal will be seen as only one assertion of the control
// signal. In short, if your control could be asserted back-to-back, then
// don't use this module. You'll be losing data.
`timescale 1 ns / 1 ns
module altera_jtag_control_signal_crosser (
clk,
reset_n,
async_control_signal,
sense_pos_edge,
sync_control_signal
);
input clk;
input reset_n;
input async_control_signal;
input sense_pos_edge;
output sync_control_signal;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
reg sync_control_signal;
wire synchronized_raw_signal;
reg edge_detector_register;
altera_std_synchronizer #(.depth(SYNC_DEPTH)) synchronizer (
.clk(clk),
.reset_n(reset_n),
.din(async_control_signal),
.dout(synchronized_raw_signal)
);
always @ (posedge clk or negedge reset_n)
if (~reset_n)
edge_detector_register <= 1'b0;
else
edge_detector_register <= synchronized_raw_signal;
always @* begin
if (sense_pos_edge)
sync_control_signal <= ~edge_detector_register & synchronized_raw_signal;
else
sync_control_signal <= edge_detector_register & ~synchronized_raw_signal;
end
endmodule
// This module crosses the clock domain for a given source
module altera_jtag_src_crosser (
sink_clk,
sink_reset_n,
sink_valid,
sink_data,
src_clk,
src_reset_n,
src_valid,
src_data
);
parameter WIDTH = 8;
parameter SYNC_DEPTH = 3; // number of synchronizer stages for clock crossing
input sink_clk;
input sink_reset_n;
input sink_valid;
input [WIDTH-1:0] sink_data;
input src_clk;
input src_reset_n;
output src_valid;
output [WIDTH-1:0] src_data;
reg sink_valid_buffer;
reg [WIDTH-1:0] sink_data_buffer;
reg src_valid;
reg [WIDTH-1:0] src_data /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101 ; {-from \"*\"} CUT=ON " */;
wire synchronized_valid;
altera_jtag_control_signal_crosser #(
.SYNC_DEPTH(SYNC_DEPTH)
) crosser (
.clk(src_clk),
.reset_n(src_reset_n),
.async_control_signal(sink_valid_buffer),
.sense_pos_edge(1'b1),
.sync_control_signal(synchronized_valid)
);
always @ (posedge sink_clk or negedge sink_reset_n) begin
if (~sink_reset_n) begin
sink_valid_buffer <= 1'b0;
sink_data_buffer <= 'b0;
end else begin
sink_valid_buffer <= sink_valid;
if (sink_valid) begin
sink_data_buffer <= sink_data;
end
end //end if
end //always sink_clk
always @ (posedge src_clk or negedge src_reset_n) begin
if (~src_reset_n) begin
src_valid <= 1'b0;
src_data <= {WIDTH{1'b0}};
end else begin
src_valid <= synchronized_valid;
src_data <= synchronized_valid ? sink_data_buffer : src_data;
end
end
endmodule
module altera_jtag_dc_streaming #(
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = 0
) (
// Signals in the JTAG clock domain
input wire tck,
input wire tdi,
output wire tdo,
input wire [2:0] ir_in,
input wire virtual_state_cdr,
input wire virtual_state_sdr,
input wire virtual_state_udr,
input wire clk,
input wire reset_n,
output wire [7:0] source_data,
output wire source_valid,
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
output wire resetrequest,
output wire debug_reset,
output wire mgmt_valid,
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output wire mgmt_data
);
// the tck to sysclk sync depth is fixed at 8
// 8 is the worst case scenario from our metastability analysis, and since
// using TCK serially is so slow we should have plenty of clock cycles.
localparam TCK_TO_SYSCLK_SYNC_DEPTH = 8;
// The clk to tck path is fixed at 3 deep for Synchronizer depth.
// Since the tck clock is so slow, no parameter is exposed.
localparam SYSCLK_TO_TCK_SYNC_DEPTH = 3;
wire jtag_clock_reset_n; // system reset is synchronized with tck
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire [7:0] jtag_sink_data;
wire jtag_sink_valid;
wire jtag_sink_ready;
/* Reset Synchronizer module.
*
* The SLD Node does not provide a reset for the TCK clock domain.
* Due to the handshaking nature of the Avalon-ST Clock Crosser,
* internal states need to be reset to 0 in order to guarantee proper
* functionality throughout resets.
*
* This reset block will asynchronously assert reset, and synchronously
* deassert reset for the tck clock domain.
*/
altera_std_synchronizer #(
.depth(SYSCLK_TO_TCK_SYNC_DEPTH)
) synchronizer (
.clk(tck),
.reset_n(reset_n),
.din(1'b1),
.dout(jtag_clock_reset_n)
);
altera_jtag_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.reset_n(jtag_clock_reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(jtag_sink_data),
.sink_valid(jtag_sink_valid),
.sink_ready(jtag_sink_ready),
.clock_to_sample(clk),
.reset_to_sample(reset_n),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
// synchronization in both clock domain crossings takes place in the "clk" system clock domain!
altera_avalon_st_clock_crosser #(
.SYMBOLS_PER_BEAT(1),
.BITS_PER_SYMBOL(8),
.FORWARD_SYNC_DEPTH(SYSCLK_TO_TCK_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) sink_crosser (
.in_clk(clk),
.in_reset(~reset_n),
.in_data(sink_data),
.in_ready(sink_ready),
.in_valid(sink_valid),
.out_clk(tck),
.out_reset(~jtag_clock_reset_n),
.out_data(jtag_sink_data),
.out_ready(jtag_sink_ready),
.out_valid(jtag_sink_valid)
);
altera_jtag_src_crosser #(
.SYNC_DEPTH(TCK_TO_SYSCLK_SYNC_DEPTH)
) source_crosser (
.sink_clk(tck),
.sink_reset_n(jtag_clock_reset_n),
.sink_valid(jtag_source_valid),
.sink_data(jtag_source_data),
.src_clk(clk),
.src_reset_n(reset_n),
.src_valid(source_valid),
.src_data(source_data)
);
endmodule
|
module aaa (/*AUTOARG*/
// Outputs
y1, y0, u1, u0,
// Inputs
y3, y2
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output u0; // From bbb of bbb.v
output u1; // From bbb of bbb.v
output y0; // From bbb of bbb.v
output y1; // From bbb of bbb.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input y2; // To bbb of bbb.v
input y3; // To bbb of bbb.v
// End of automatics
/*AUTOWIRE*/
wire u0, u1, z0, z1;
/*
bbb AUTO_TEMPLATE (
.xo0 ({(u0), y0}),
.xo1 ({y1, (u1)}),
.xi0 ({(z0), y2}),
.xi1 ({y3, (z1)}),
);
*/
bbb bbb (/*AUTOINST*/
// Outputs
.xo0 ({(u0), y0}), // Templated
.xo1 ({y1, (u1)}), // Templated
// Inputs
.xi0 ({(z0), y2}), // Templated
.xi1 ({y3, (z1)})); // Templated
endmodule // aaa
module bbb (/*AUTOARG*/
// Outputs
xo0, xo1,
// Inputs
xi0, xi1
);
output [1:0] xo0, xo1;
input [1:0] xi0, xi1;
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire [1:0] xo0 = 2'h0;
wire [1:0] xo1 = 2'h0;
// End of automatics
endmodule // bbb
|
#include <bits/stdc++.h> using namespace std; mt19937 rang(chrono::high_resolution_clock::now().time_since_epoch().count()); const long double PI = 3.141592653589793; const long long INF = 9223372036854775807ll; const long long mod = 1e9 + 7; const int N = 1e5 + 5; long long tree[4 * N + 10]; long long lazy[4 * N + 10]; long long b[N]; void build(int node, int start, int end) { if (start == end) { tree[node] = b[start]; return; } int mid = (start + end) / 2; build(2 * node, start, mid); build(2 * node + 1, mid + 1, end); tree[node] = tree[2 * node] + tree[2 * node + 1]; } long long query(int node, int start, int end, int l, int r) { if (lazy[node] != -INF / 10000) { tree[node] = lazy[node] * (end - start + 1); if (start != end) { lazy[2 * node] = lazy[node]; lazy[2 * node + 1] = lazy[node]; } lazy[node] = -INF / 10000; } if (l > end || r < start) return 0; if (l <= start && r >= end) { return tree[node]; } int mid = (start + end) / 2; return query(2 * node, start, mid, l, r) + query(2 * node + 1, mid + 1, end, l, r); } void update(int node, int start, int end, int l, int r, long long val) { if (lazy[node] != (-INF / 10000)) { tree[node] = lazy[node] * (end - start + 1ll); if (start != end) { lazy[2 * node] = lazy[node]; lazy[2 * node + 1] = lazy[node]; } lazy[node] = (-INF / 10000); } if (l > end || r < start) return; if (l <= start && r >= end) { tree[node] = (end - start + 1) * val; if (start != end) { lazy[2 * node] = val; lazy[2 * node + 1] = val; } return; } int mid = (start + end) / 2; update(2 * node, start, mid, l, r, val); update(2 * node + 1, mid + 1, end, l, r, val); tree[node] = tree[2 * node] + tree[2 * node + 1]; } void solve() { fill(tree, tree + 4 * N + 4, 0ll); fill(lazy, lazy + 4 * N + 4, -INF / 10000); fill(b, b + N, 0); long long n; cin >> n; long long a[n]; long long t[n + 1]; t[0] = 0; for (int i = 0; i < n; ++i) { cin >> a[i]; } for (int i = 1; i < n; ++i) { long long k; cin >> k; t[i] = t[i - 1] + k; } for (int i = 0; i < n; ++i) { b[i] = a[i] - t[i]; } for (int i = 1; i < n; ++i) { t[i] += t[i - 1]; } b[n] = INF / 10000; build(1, 0, n); int q; cin >> q; while (q--) { char now; cin >> now; if (now == s ) { int l; int r; cin >> l >> r; l--; r--; long long pr = query(1, 0, n, l, r); if (l - 1 < 0) l++; cout << (pr + t[r] - t[l - 1]) << n ; } else { int i; long long x; cin >> i >> x; i--; long long val = query(1, 0, n, i, i) + x; int lo = i; int hi = n; while (hi - lo > 1) { int mid = (hi + lo) / 2; if (query(1, 0, n, mid, mid) <= val) { lo = mid; } else { hi = mid; } } update(1, 0, n, i, lo, val); } } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); srand(chrono::high_resolution_clock::now().time_since_epoch().count()); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; void PrintVector(vector<int> v2, string s) { cout << s; for (int i = 0; i < v2.size(); i++) cout << v2[i] << ; cout << endl; } void PrintVector(vector<int> v2) { for (int i = 0; i < v2.size(); i++) cout << v2[i] << ; cout << endl; } int isOdd(int x) { return (x % 2); } int toInt(string str) { int num; istringstream iss(str); iss >> num; return num; } template <class T> string toStr(T par) { ostringstream oss; oss << par; return oss.str(); } void readVector(vector<int> &vec, int len) { for (int i = 0; i < len; i++) { cin >> vec[i]; } } long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } bool sortPairsCmp(const pair<int, int> &a, const pair<int, int> &b) { return a.second > b.second; } multiset<int> arr; int main() { long long n, x, y; long long hours = 0; cin >> n >> x; for (int i = 0; i < n; i++) { cin >> y; arr.insert(y); } for (auto t : arr) { hours += (x * t); if (x > 1) x--; } cout << hours << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace fastIO { bool IOerror = 0; inline char nc() { static char buf[100000], *p1 = buf + 100000, *pend = buf + 100000; if (p1 == pend) { p1 = buf; pend = buf + fread(buf, 1, 100000, stdin); if (pend == p1) { IOerror = 1; return -1; } } return *p1++; } inline bool blank(char ch) { return ch == || ch == n || ch == r || ch == t ; } inline long long read() { bool sign = 0; char ch = nc(); long long x = 0; for (; blank(ch); ch = nc()) ; if (IOerror) return 0; if (ch == - ) sign = 1, ch = nc(); for (; ch >= 0 && ch <= 9 ; ch = nc()) x = x * 10 + ch - 0 ; if (sign) x = -x; return x; } }; // namespace fastIO using namespace fastIO; long long qpow(long long n, long long k) { long long ans = 1; while (k) { if (k & 1) ans *= n, ans %= 998244353; n *= n, n %= 998244353; k >>= 1; } return ans; } char s[3000010]; long long fac[3000010], ifac[3000010], l[3000010], r[3000010], x[3000010], y[3000010]; long long c(long long x, long long y) { return fac[x] * ifac[x - y] % 998244353 * ifac[y] % 998244353; } signed main() { cin >> s + 1; long long n = strlen(s + 1); fac[0] = 1; for (long long i = 1; i <= n; i++) { fac[i] = fac[i - 1] * i % 998244353; } ifac[n] = qpow(fac[n], 998244353 - 2); for (long long i = n - 1; i >= 0; i--) ifac[i] = ifac[i + 1] * (i + 1) % 998244353; for (long long i = 1; i <= n; i++) { l[i] = l[i - 1] + (s[i] == ( ); x[i] = x[i - 1] + (s[i] == ? ); } for (long long i = n; i >= 1; i--) { r[i] = r[i + 1] + (s[i] == ) ); y[i] = y[i + 1] + (s[i] == ? ); } long long ans = 0; for (long long i = 1; i <= n - 1; i++) { ans += l[i] * c(x[i] + y[i + 1], y[i + 1] - l[i] + r[i + 1]) + x[i] * c(x[i] + y[i + 1] - 1, y[i + 1] - l[i] + r[i + 1] - 1), ans %= 998244353; } cout << ans; return 0; }
|
#include <bits/stdc++.h> inline long long read() { long long x = 0, f = 1; char c = getchar(); for (; c > 9 || c < 0 ; c = getchar()) { if (c == - ) f = -1; } for (; c >= 0 && c <= 9 ; c = getchar()) { x = x * 10 + c - 0 ; } return x * f; } int dp[18][(1 << 18)][2][2]; bool fan[200005]; inline void work() { int n = read(), k = read(); for (int i = 1; i <= k; i++) { int x = read(); fan[x] = 1; } memset(dp, -0x3f, sizeof dp); for (int i = 1; i <= n; i++) { for (int j = 1; j <= (1 << n); j += (1 << i)) { if (i == 1) { dp[i][j][fan[j]][fan[j + 1]] = (fan[j] | fan[j + 1]); dp[i][j][fan[j + 1]][fan[j]] = (fan[j] | fan[j + 1]); } else { for (int x1 = 0; x1 < 2; x1++) { for (int x2 = 0; x2 < 2; x2++) { for (int y1 = 0; y1 < 2; y1++) { for (int y2 = 0; y2 < 2; y2++) { int tmp = dp[i - 1][j][x1][y1] + dp[i - 1][j + (1 << i - 1)][x2][y2]; if (x1 | x2) tmp++; if (y1 | y2) tmp++; dp[i][j][x1][x2] = std::max(dp[i][j][x1][x2], tmp + (x2 | y1)); dp[i][j][x1][x2] = std::max(dp[i][j][x1][x2], tmp + (x2 | y2)); dp[i][j][x1][y1] = std::max(dp[i][j][x1][y1], tmp + (y1 | x2)); dp[i][j][x1][y2] = std::max(dp[i][j][x1][y2], tmp + (y2 | x2)); dp[i][j][x2][x1] = std::max(dp[i][j][x2][x1], tmp + (x1 | y1)); dp[i][j][x2][x1] = std::max(dp[i][j][x2][x1], tmp + (x1 | y2)); dp[i][j][x2][y1] = std::max(dp[i][j][x2][y1], tmp + (y1 | x1)); dp[i][j][x2][y2] = std::max(dp[i][j][x2][y2], tmp + (y2 | x1)); } } } } } } } int ans = -0x3f3f3f3f; ans = std::max(ans, dp[n][1][1][1] + 1); ans = std::max(ans, dp[n][1][0][1] + 1); ans = std::max(ans, dp[n][1][1][0] + 1); ans = std::max(ans, dp[n][1][0][0]); printf( %d n , ans); } int main() { work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> T in() { char ch; T n = 0; bool ng = false; while (1) { ch = getchar(); if (ch == - ) { ng = true; ch = getchar(); break; } if (ch >= 0 && ch <= 9 ) break; } while (1) { n = n * 10 + (ch - 0 ); ch = getchar(); if (ch < 0 || ch > 9 ) break; } return (ng ? -n : n); } template <typename T> inline T POW(T B, T P) { if (P == 0) return 1; if (P & 1) return B * POW(B, P - 1); else return (POW(B, P / 2) * POW(B, P / 2)); } template <typename T> inline T Gcd(T a, T b) { if (a < 0) return Gcd(-a, b); if (b < 0) return Gcd(a, -b); return (b == 0) ? a : Gcd(b, a % b); } template <typename T> inline T Lcm(T a, T b) { if (a < 0) return Lcm(-a, b); if (b < 0) return Lcm(a, -b); return a * (b / Gcd(a, b)); } long long Bigmod(long long base, long long power, long long MOD) { long long ret = 1; while (power) { if (power & 1) ret = (ret * base) % MOD; base = (base * base) % MOD; power >>= 1; } return ret; } bool isVowel(char ch) { ch = toupper(ch); if (ch == A || ch == U || ch == I || ch == O || ch == E ) return true; return false; } long long ModInverse(long long number, long long MOD) { return Bigmod(number, MOD - 2, MOD); } bool isConst(char ch) { if (isalpha(ch) && !isVowel(ch)) return true; return false; } int toInt(string s) { int sm; stringstream second(s); second >> sm; return sm; } vector<int> A[500007]; int a[500007]; long long int Dp[500007]; vector<pair<long long int, int> > dp[500007]; void Dfs1(int u, int p, long long int vl) { long long int mx1 = -1, mx2 = -1; dp[u].push_back(make_pair(vl, p)); for (int i = 0; i < A[u].size(); i++) { int v = A[u][i]; if (v == p) continue; int Ln = dp[u].size() - 1; int lft = max(0, Ln - 5); long long int now = vl; for (int j = Ln; j >= lft; j--) { int tp = dp[u][j].second; if (tp == v) continue; now = max(now, dp[u][j].first); } Dfs1(v, u, now + a[u]); } sort(dp[u].begin(), dp[u].end()); } long long int Dfs(int u, int p) { long long int mx1 = -1, mx2 = -1; for (int i = 0; i < A[u].size(); i++) { int v = A[u][i]; if (v == p) continue; long long int tp = Dfs(v, u); dp[u].push_back(make_pair(tp, v)); if (tp > mx1) { mx2 = mx1; mx1 = tp; } else if (tp > mx2) { mx2 = tp; } } Dp[u] = max(0LL, mx1) + max(0LL, mx2) + a[u]; sort(dp[u].begin(), dp[u].end()); return ((0LL > mx1) ? 0LL : mx1) + a[u]; } void Wow(int u, int p) { for (int i = 0; i < A[u].size(); i++) { int v = A[u][i]; if (v == p) continue; Wow(v, u); Dp[u] = max(Dp[u], Dp[v]); } } long long int Ans; void Dekhi(int u, int p) { for (int i = 0; i < A[u].size(); i++) { int v = A[u][i]; if (v == p) continue; Dekhi(v, u); } if (p) { int Ln = dp[p].size() - 1; int lft = max(0, Ln - 5); long long int now = Dp[u] + a[p]; for (int i = Ln; i >= lft; i--) { if (dp[p][i].second == u) continue; for (int j = i - 1; j >= lft; j--) { if (dp[p][j].second == u) continue; long long int tp = dp[p][i].first + dp[p][j].first; if (Ans < now + tp) { Ans = now + tp; } } long long int tp = dp[p][i].first; if (Ans < now + tp) { Ans = now + tp; } } Ans = max(Ans, now); } return; } int main() { int n; n = in<int>(); for (int i = 1; i <= n; i++) a[i] = in<int>(); for (int i = 1; i < n; i++) { int u, v; u = in<int>(), v = in<int>(); A[u].push_back(v); A[v].push_back(u); } vector<int> root; for (int i = 1; i <= n; i++) { if (A[i].size() == 1) { root.push_back(i); } } for (int i = 0; i < root.size(); i++) { for (int j = 1; j <= n; j++) { dp[j].clear(); } long long int tp = Dfs(root[i], 0); Dfs1(root[i], 0, 0); Wow(root[i], 0); Dekhi(root[i], 0); if (i == 10) break; } printf( %lld n , Ans); return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PIO_TO_CTRL.v
// Version : 1.11
//--
//-- Description: Turn-off Control Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module PIO_TO_CTRL #(
parameter TCQ = 1
) (
input clk,
input rst_n,
input req_compl,
input compl_done,
input cfg_to_turnoff,
output reg cfg_turnoff_ok
);
reg trn_pending;
// Check if completion is pending
always @ ( posedge clk ) begin
if (!rst_n )
begin
trn_pending <= #TCQ 0;
end
else
begin
if (!trn_pending && req_compl)
trn_pending <= #TCQ 1'b1;
else if (compl_done)
trn_pending <= #TCQ 1'b0;
end
end
// Turn-off OK if requested and no transaction is pending
always @ ( posedge clk ) begin
if (!rst_n )
begin
cfg_turnoff_ok <= #TCQ 1'b0;
end
else
begin
if ( cfg_to_turnoff && !trn_pending)
cfg_turnoff_ok <= #TCQ 1'b1;
else
cfg_turnoff_ok <= #TCQ 1'b0;
end
end
endmodule // PIO_TO_CTRL
|
#include <bits/stdc++.h> using namespace std; const int maxn = 305; int n, m; class Point { public: long long x, y; Point() : x(0), y(0) {} Point(long long _x, long long _y) : x(_x), y(_y) {} void read() { scanf( %lld%lld , &x, &y); } Point operator+(const Point &o) const { return Point(x + o.x, y + o.y); } Point operator-(const Point &o) const { return Point(x - o.x, y - o.y); } long long operator*(const Point &o) const { return x * o.y - y * o.x; } bool operator<(const Point &o) const { int c = (y == 0 && x > 0) || (y > 0); int oc = (o.y == 0 && o.x > 0) || (o.y > 0); if (c != oc) return c > oc; return (*this) * o > 0; } } p[maxn]; class Edge { public: Point w; int u, v; Edge() {} Edge(Point _w, int _u, int _v) : w(_w), u(_u), v(_v) {} bool operator<(const Edge &o) const { return w < o.w; } } e[maxn * maxn]; long long dp[maxn][maxn][6]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) p[i].read(); for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) { e[m++] = Edge(p[j] - p[i], i, j); e[m++] = Edge(p[i] - p[j], j, i); } sort(e, e + m); for (int i = 0; i < n; i++) dp[i][i][0] = 1; for (int i = 0; i < m; i++) for (int j = 0; j < n; j++) for (int k = 0; k < 5; k++) dp[j][e[i].v][k + 1] += dp[j][e[i].u][k]; long long ans = 0; for (int i = 0; i < n; i++) ans += dp[i][i][5]; printf( %lld n , ans); return 0; }
|
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