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#include <bits/stdc++.h> using namespace std; struct in { int x, y; } a[300000]; int get(int prex, int prey, int x, int y, int k) { int num, ans = 100000000; if (prex <= k) { num = (prex + x + k - 1) / k - 1; if (y == num) ans = prex + x - num * k; else if (y > num && y <= (long long)x * k) ans = 1; } if (prey <= k) { num = (x + k - 1) / k - 1; if (y == num) ans = min(ans, x - num * k); else if (y > num && y - k + prey <= (long long)(x - 1) * k) ans = 1; } return ans; } int main() { int N, K, pre0 = 0, pre1 = 0, next0, next1; scanf( %d%d , &N, &K); for (int i = 1; i <= N; i++) scanf( %d , &a[i].x); for (int i = 1; i <= N; i++) scanf( %d , &a[i].y); for (int i = 1; i <= N; i++) { next0 = get(pre0, pre1, a[i].x, a[i].y, K); next1 = get(pre1, pre0, a[i].y, a[i].x, K); pre0 = next0; pre1 = next1; } if (pre0 <= K || pre1 <= K) puts( YES ); else puts( NO ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1000005; const int inf = 1e9 + 7; long long fac[N], M, inv[N]; inline long long po(long long x, long long y, long long z) { long long res = 1; while (y) { if (y & 1) res = res * x % z; x = x * x % z; y >>= 1; } return res; } long long ans[N], M2; inline long long C(int x, int y) { return fac[x] * inv[y] % M2 * inv[x - y] % M2; } int main() { int n, m, a; scanf( %d%d%d%lld , &n, &m, &a, &M); long long res = 1; for (int i = (1); i <= (2000000); i++) { res = res * (long long)a % M; if (res == 1) { M2 = i; break; } } fac[0] = fac[1] = inv[0] = inv[1] = 1; for (int i = (2); i <= (M2); i++) { fac[i] = fac[i - 1] * (long long)i % M2; inv[i] = po(fac[i], M2 - 2, M2); } ans[0] = 1; for (int i = (1); i <= (N - 1); i++) { ans[i] = ans[i - 1]; ans[i] += C(m, i); } for (int i = (n - 1); i >= (0); i--) printf( %lld , po(a, ans[i], M)); puts( ); return 0; }
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#include <bits/stdc++.h> #define pb push_back #define pf push_front #define fi first #define se second using namespace std; typedef long long ll; int main() { ios::sync_with_stdio(0); cin.tie(0); ll t, n, k; cin >> t; while(t--) { cin >> n >> k; for(ll i=1; i<2*k-n; i++) { cout << i << ; } for(ll i=k; i>=2*k-n; i--) { cout << i << ; } cout << n ; } }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_zero_one_hot_assert #(
.width(width))
assert_zero_one_hot_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_zero_one_hot_assume #(
.width(width))
assert_zero_one_hot_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
wire [width-1:0] test_expr_1 = test_expr - {{width-1{1'b0}},1'b1};
reg [width-1:0] one_hots_checked;
always @(posedge clk)
if (`OVL_RESET_SIGNAL != 1'b1)
one_hots_checked <= {width{1'b0}};
else //check for known driven and zero one hot test_expr and update one_hots_checked
one_hots_checked <= ((test_expr ^ test_expr)=={width{1'b0}}) && ((test_expr & test_expr_1) == {width{1'b0}}) ?
one_hots_checked | test_expr : one_hots_checked;
wire all_one_hots_checked;
assign all_one_hots_checked = (one_hots_checked == {width{1'b1}});
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_zero_one_hot_cover #(
.width(width),
.OVL_COVER_SANITY_ON(OVL_COVER_SANITY_ON),
.OVL_COVER_CORNER_ON(OVL_COVER_CORNER_ON))
assert_zero_one_hot_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.all_one_hots_checked(all_one_hots_checked));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_zero_one_hot.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_zero_one_hot_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n, xzcheck_enable;
input [width-1:0] test_expr;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_zero_one_hot_assume (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n, xzcheck_enable;
input [width-1:0] test_expr;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_zero_one_hot_cover (clk, reset_n, test_expr, all_one_hots_checked);
parameter width = 1;
parameter OVL_COVER_SANITY_ON = 1;
parameter OVL_COVER_CORNER_ON = 1;
input clk, reset_n, all_one_hots_checked;
input [width-1:0] test_expr;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; long long int x; x = n % 4; if (n == 0) cout << 1 ; else if (x == 0) cout << 6 ; else if (x == 1) cout << 8 ; else if (x == 2) cout << 4 ; else if (x == 3) cout << 2 ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S6S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLYMETAL6S6S_FUNCTIONAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlymetal6s6s (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S6S_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; bool Notlucky(int x) { for (int i = x; i != 0; i /= 10) { if (i % 10 == 8 || i % 10 == -8) return false; } return true; } int main() { int a, b; cin >> a; b = a + 1; while (Notlucky(b)) { b++; } cout << b - a; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int32_t INFint = 1e9; const long long INFll = 1e18; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) { long long n; cin >> n; long long arr[n]; for (long long i = 0; i < n; i++) cin >> arr[i]; ; sort(arr, arr + n); long long ans = arr[0] * arr[n - 1]; long long fact[100000]; long long index = 0; for (long long i = 2; i <= sqrt(ans); i++) { if (ans % i == 0) { fact[index] = i; index++; if (i != ans / i) { fact[index] = ans / i; index++; } } } sort(fact, fact + index); if (index != n) { cout << -1 << n ; } else { long long flag = 0; for (long long i = 0; i < n; i++) { if (fact[i] != arr[i]) { flag = 1; break; } } ans = flag ? -1 : ans; cout << ans << n ; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SREGRBP_PP_BLACKBOX_V
/**
* sregrbp: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sregrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGRBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, a, b, x, y, x1, y1; cin >> n >> a >> b; if (max(n - a, n - b) < max(a - 1, b - 1)) cout << black n ; else cout << white n ; return 0; }
|
module register #(parameter SIZE = 16, parameter DEF = {SIZE{1'bx}}) (input clk, input [SIZE-1:0] i, output reg [SIZE-1:0] o, input [1:0] rw);
initial o <= DEF;
always @(clk) begin
case (rw)
2'b01 : begin
o[SIZE/2-1 : 0] <= i[SIZE/2-1 : 0];
end
2'b10 : begin
o[SIZE-1 : SIZE/2] <= i[SIZE-1 : SIZE/2];
end
2'b11 : begin
o <= i;
end
endcase
end
endmodule
module bus_register #(parameter SIZE = 16) (input clk, input [SIZE-1:0] i, output reg [SIZE-1:0] o);
always @(clk) begin
o <= i;
end
endmodule
module program_counter #(parameter SIZE = 16) (input clk, input [SIZE-1:0] i, output reg [SIZE-1:0] o, input rw, input [1:0] inc);
initial o <= 0;
always @(clk) begin
case (inc)
2'b00 : begin
if (rw)
o <= i;
end
2'b01 : o <= o + 2;
2'b10 : o <= o + 4;
2'b11 : o <= o + 6;
endcase
end
endmodule
module simple_register #(parameter SIZE = 16) (input clk, input [SIZE-1:0] i, output reg [SIZE-1:0] o, input rw);
always @(clk) begin
if (rw) begin
o <= i;
end
end
endmodule
module register_test;
reg clk;
reg [1:0] rw;
wire [15:0] oline;
reg [15:0] iline;
register register(clk, iline, oline, rw);
initial begin
$monitor("%t: rw = %b, o = %x, i = %x", $time, rw, oline, iline);
clk <= 0;
#10
rw <= 2'b11;
iline <= 16'h1234;
#10
rw <= 2'b00;
iline <= 16'hz;
#10
rw <= 2'b11;
iline <= 16'h4567;
#10
rw <= 2'b00;
iline <= 16'hz;
#10
rw <= 2'b01;
iline <= 16'h89AB;
#10
rw <= 2'b00;
iline <= 16'hz;
#10
rw <= 2'b10;
iline <= 16'hCDEF;
#10
rw <= 2'b00;
iline <= 16'hz;
#10 $finish;
end
always #10 begin
clk <= ~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void runTest() { long long int n, a, b, k; cin >> n >> a >> b >> k; long long int ans = 0; vector<long long int> v; for (long long int i = 0; i < n; i++) { long long int val; cin >> val; long long int temp = ((val % (a + b) == 0) ? (val / (a + b)) - 1 : val / (a + b)); temp *= (a + b); temp = val - temp; temp = ((temp - 1) / a) + 1; temp--; if (temp <= 0) ans++; else v.push_back(temp); } sort(v.begin(), v.end()); for (auto i : v) { if (k >= i) { ans++; k -= i; } } cout << ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) runTest(); return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve(int cnum) { int di[] = {-1, 0, 0, 1}; int dj[] = {0, -1, 1, 0}; int n, m; cin >> n >> m; vector<vector<int>> arr(n, vector<int>(m)); vector<vector<int>> ans(n, vector<int>(m)); for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) cin >> arr[i][j]; auto isvalid = [&](int i, int j) { if (i < 0 || j < 0) return false; if (i >= n || j >= m) return false; return true; }; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { int neicnt = 0; for (int k = 0; k < 4; ++k) { if (isvalid(i + di[k], j + dj[k])) neicnt++; } if (neicnt < arr[i][j]) { cout << NO n ; return; } ans[i][j] = neicnt; } } cout << YES n ; for (auto a : ans) { for (auto b : a) cout << b << ; cout << n ; } } int main() { int t; int count = 1; for (cin >> t; t--; solve(count), count++) ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S4S_1_V
`define SKY130_FD_SC_LP__DLYMETAL6S4S_1_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s4s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlymetal6s4s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlymetal6s4s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlymetal6s4s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlymetal6s4s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlymetal6s4s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S4S_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BA_2_V
`define SKY130_FD_SC_HDLL__O21BA_2_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BA_2_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; struct M { int v[2][2]; } A, V, c[1 << 20]; struct Vec { int v[2]; } a[1 << 20], Vec0; bool E(const M& a) { return a.v[0][0] == 1 && a.v[1][1] == 1 && a.v[0][1] == 0 && a.v[1][0] == 0; } M operator*(const M& a, const M& b) { M ret; for (int i = 0; i < 2; ++i) for (int j = 0; j < 2; ++j) ret.v[i][j] = (1ll * a.v[i][0] * b.v[0][j] + 1ll * a.v[i][1] * b.v[1][j]) % mod; return ret; }; Vec operator+(const Vec& a, const Vec& b) { Vec ret; ret.v[0] = (a.v[0] + b.v[0]) % mod; ret.v[1] = (a.v[1] + b.v[1]) % mod; return ret; } Vec operator*(const M& m, const Vec& vec) { Vec ret; ret.v[0] = (1ll * vec.v[0] * m.v[0][0] + 1ll * vec.v[1] * m.v[0][1]) % mod; ret.v[1] = (1ll * vec.v[0] * m.v[1][0] + 1ll * vec.v[1] * m.v[1][1]) % mod; return ret; } M pow(M a, int b) { M t; t.v[0][0] = t.v[1][1] = 1; t.v[0][1] = t.v[1][0] = 0; while (b) { if (b & 1) t = t * a; b = b >> 1; a = a * a; } return t; } void init(int u, int l, int r) { if (l == r) { int b; scanf( %d , &b); M t = pow(A, b - 1); a[u].v[0] = t.v[0][0]; a[u].v[1] = t.v[0][1]; return; } c[u].v[0][0] = c[u].v[1][1] = 1; c[u].v[0][1] = c[u].v[1][0] = 0; int mid = (l + r) >> 1; init(u << 1, l, mid); init(u << 1 | 1, mid + 1, r); a[u] = a[u << 1] + a[u << 1 | 1]; } int L, R; void change(int u, int l, int r) { if (R < l || r < L) return; if (L <= l && r <= R) { c[u] = V * c[u]; a[u] = V * a[u]; return; } if (!E(c[u])) { c[u << 1] = c[u] * c[u << 1]; a[u << 1] = c[u] * a[u << 1]; c[u << 1 | 1] = c[u] * c[u << 1 | 1]; a[u << 1 | 1] = c[u] * a[u << 1 | 1]; c[u].v[0][0] = c[u].v[1][1] = 1; c[u].v[0][1] = c[u].v[1][0] = 0; } int mid = (l + r) >> 1; change(u << 1, l, mid); change(u << 1 | 1, mid + 1, r); a[u] = a[u << 1] + a[u << 1 | 1]; } Vec query(int u, int l, int r) { if (R < l || r < L) return Vec0; if (L <= l && r <= R) return a[u]; int mid = (l + r) >> 1; return c[u] * (query(u << 1, l, mid) + query(u << 1 | 1, mid + 1, r)); } int main() { A.v[0][0] = A.v[0][1] = A.v[1][0] = 1; int n, m; scanf( %d%d , &n, &m); init(1, 1, n); for (int i = 0; i < m; ++i) { int op, x; scanf( %d , &op); if (op == 1) { scanf( %d%d%d , &L, &R, &x); V = pow(A, x); change(1, 1, n); } else { scanf( %d%d , &L, &R); Vec vec = query(1, 1, n); printf( %d n , vec.v[0]); } } return 0; }
|
// DESCRIPTION: Verilator: Test symbol table scope map and general public
// signal reflection
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader.
module t
(
input wire CLK
);
foo #(.WIDTH (1)) foo1 (.*);
foo #(.WIDTH (7)) foo7 (.*);
foo #(.WIDTH (8)) foo8 (.*);
foo #(.WIDTH (32)) foo32 (.*);
foo #(.WIDTH (33)) foo33 (.*);
foo #(.WIDTH (40)) foo40 (.*);
foo #(.WIDTH (41)) foo41 (.*);
foo #(.WIDTH (64)) foo64 (.*);
foo #(.WIDTH (65)) foo65 (.*);
foo #(.WIDTH (96)) foo96 (.*);
foo #(.WIDTH (97)) foo97 (.*);
foo #(.WIDTH (128)) foo128 (.*);
foo #(.WIDTH (256)) foo256 (.*);
foo #(.WIDTH (1024)) foo1024 (.*);
bar #(.WIDTH (1024)) bar1024 (.*);
endmodule
module foo
#(
parameter WIDTH = 32
)
(
input CLK
);
logic [ ( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0 ] initial_value;
logic [ WIDTH - 1 : 0 ] value_q /* verilator public */;
integer i;
initial begin
initial_value = '1;
for (i = 0; i < WIDTH / 8; i++)
initial_value[ i * 8 +: 8 ] = i[ 7 : 0 ];
value_q = initial_value[ WIDTH - 1 : 0 ];
end
always @(posedge CLK)
value_q <= ~value_q;
endmodule
module bar
#(
parameter WIDTH = 32
)
(
input CLK
);
foo #(.WIDTH (WIDTH)) foo (.*);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int v[200100], cnt[200020]; int n, s; int main(void) { ios::sync_with_stdio(false); cin >> n >> s; --s; int er = 0; int ans = 0; for (int(i) = (0); (i) < (n); ++(i)) { cin >> v[i]; cnt[v[i]]++; } if (v[s] != 0) { ans++; cnt[v[s]]--; cnt[0]++; } int e = n - 1; while (cnt[e] == 0) e--; er = cnt[0] - 1; ans += er; for (int i = 1; i < e; i++) { if (!cnt[i]) { if (er) er--; else { cnt[e]--; cnt[i]++; ans++; while (cnt[e] == 0) e--; } } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; ; clock_t start; mt19937_64 rng(chrono::system_clock::now().time_since_epoch().count()); const long long N = 501, lmx = 11; long long mx[N][N][lmx][lmx], n, m, q, col[4][N][N], logg[N]; long long sum(long long k, long long r1, long long c1, long long r2, long long c2) { return col[k][r2][c2] - col[k][r2][c1] - col[k][r1][c2] + col[k][r1][c1]; } void sparse() { for (long long i = 2; i < N; i++) logg[i] = logg[i / 2] + 1; for (long long lgi = 1; lgi < lmx; lgi++) { for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { if (i + (1 << (lgi - 1)) <= n) mx[i][j][lgi][0] = max(mx[i][j][lgi - 1][0], mx[i + (1 << (lgi - 1))][j][lgi - 1][0]); } } } for (long long lgi = 0; lgi < lmx; lgi++) { for (long long lgj = 1; lgj < lmx; lgj++) { for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { long long k = lgj - 1; if (j + (1 << k) <= m) mx[i][j][lgi][lgj] = max(mx[i][j][lgi][k], mx[i][j + (1 << k)][lgi][k]); } } } } } long long query(long long r1, long long c1, long long r2, long long c2) { if (r1 > r2 || c1 > c2) return 0; long long k1 = logg[r2 - r1 + 1], k2 = logg[c2 - c1 + 1]; long long m1 = max(mx[r1][c1][k1][k2], mx[r2 - (1 << k1) + 1][c1][k1][k2]); long long m2 = max(mx[r1][c2 - (1 << k2) + 1][k1][k2], mx[r2 - (1 << k1) + 1][c2 - (1 << k2) + 1][k1][k2]); return max(m1, m2); } void solve() { string s, ss = RGYB ; cin >> n >> m >> q; for (long long i = 0; i < n; i++) { cin >> s; for (long long j = 0; j < m; j++) { for (long long k = 0; k < 4; k++) if (ss[k] == s[j]) col[k][i + 1][j + 1] = 1; } } for (long long k = 0; k < 4; k++) { for (long long i = 1; i <= n; i++) for (long long j = 1; j <= m; j++) col[k][i][j] += col[k][i - 1][j] + col[k][i][j - 1] - col[k][i - 1][j - 1]; } for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= m; j++) { long long lim = min(min(i, j), min(n - i, m - j)); for (long long len = 1; len <= lim; len++) { if (sum(0, i - len, j - len, i, j) != len * len) break; if (sum(1, i - len, j, i, j + len) != len * len) break; if (sum(2, i, j - len, i + len, j) != len * len) break; if (sum(3, i, j, i + len, j + len) != len * len) break; mx[i][j][0][0] = len * len; } } } sparse(); while (q--) { long long r1, c1, r2, c2, ans = 0; cin >> r1 >> c1 >> r2 >> c2; long long s = 1, e = min(r2 - r1 + 1, c2 - c1 + 1); while (s <= e) { long long mid = (s + e) / 2; if (query(r1 + mid - 1, c1 + mid - 1, r2 - mid, c2 - mid) >= mid * mid) { s = mid + 1, ans = mid; } else e = mid - 1; } cout << 4 * ans * ans << n ; } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; start = clock(); cout << fixed << setprecision(15); while (t--) { solve(); } double time_taken = double(clock() - start) / double(CLOCKS_PER_SEC); cerr << time_taken; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 3e5 + 10; const long long M = 1e9 + 7; int n, x, y, z; int last[N], to[2 * N], w[2 * N], num, nxt[2 * N]; long long a[N]; long long ans; void Add(int u, int v, int c) { nxt[++num] = last[u]; to[num] = v; w[num] = c; last[u] = num; } long long dp[N]; long long dfs(int u, int f) { long long max1, max2; max1 = max2 = 0; for (int i = last[u]; i; i = nxt[i]) { int v = to[i]; if (v == f) continue; dfs(v, u); long long now = dp[v] - w[i]; if (now >= max1) { max2 = max1; max1 = now; } else if (now > max2) max2 = now; } long long tot = max1 + max2 + a[u]; ans = max(ans, tot); return dp[u] = max(max1, max2) + a[u]; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %lld , a + i); for (int i = 1; i <= n - 1; ++i) { scanf( %d%d%d , &x, &y, &z); Add(x, y, z); Add(y, x, z); } dfs(1, 0); printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100000 + 10; struct node { int t; int x; int y; } tt[maxn]; int main() { int n, m, s, f; while (~scanf( %d%d%d%d , &n, &m, &s, &f)) { memset(tt, 0, sizeof tt); for (int i = 0; i < m; i++) { scanf( %d%d%d , &tt[i].t, &tt[i].x, &tt[i].y); } int cnt = 0; int time = 1; int peo = s; int jj; if (f > s) jj = 1; else jj = -1; while (peo != f) { if (tt[cnt].t != time) { peo += jj; if (jj == 1) { printf( R ); } else printf( L ); } else if ((peo < tt[cnt].x || peo > tt[cnt].y) && ((peo + jj) < tt[cnt].x || (peo + jj) > tt[cnt].y)) { peo += jj; if (jj == 1) { printf( R ); } else printf( L ); cnt++; } else { printf( X ); cnt++; } time++; } printf( n ); } return 0; }
|
/*
`BF.v'
Balsa Verilog netlist file
Created: Thu Apr 22 18:40:25 BST 2010
By: dell@dell-laptop (Linux)
With net-verilog (balsa-netlist) version: 3.5.1
Using technology: example/four_b_rb
Command line : (balsa-netlist -v BF.breeze)
*/
module AND3 (
out,
in0,
in1,
in2
);
output out;
input in0;
input in1;
input in2;
endmodule
module BALSA_FA (
nStart,
A,
B,
nCVi,
Ci,
nCVo,
Co,
sum
);
input nStart;
input A;
input B;
input nCVi;
input Ci;
output nCVo;
output Co;
output sum;
endmodule
module BUFF (
Z,
A
);
output Z;
input A;
endmodule
module INV (
out,
in
);
output out;
input in;
endmodule
module NOR2 (
out,
in0,
in1
);
output out;
input in0;
input in1;
endmodule
module NOR3 (
out,
in0,
in1,
in2
);
output out;
input in0;
input in1;
input in2;
endmodule
module BrzBinaryFunc__Data_8_8_8_s3_Add_s5_False__m7m (
go_0r, go_0a,
out_0r, out_0a, out_0d,
inpA_0r, inpA_0a, inpA_0d,
inpB_0r, inpB_0a, inpB_0d
);
input go_0r;
output go_0a;
input out_0r;
output out_0a;
output [7:0] out_0d;
output inpA_0r;
input inpA_0a;
input [7:0] inpA_0d;
output inpB_0r;
input inpB_0a;
input [7:0] inpB_0d;
wire [2:0] internal_0n;
wire start_0n;
wire nStart_0n;
wire [8:0] nCv_0n;
wire [8:0] c_0n;
wire [7:0] eq_0n;
wire [7:0] addOut_0n;
wire [7:0] w_0n;
wire [7:0] n_0n;
wire v_0n;
wire z_0n;
wire nz_0n;
wire nxv_0n;
wire done_0n;
supply0 gnd;
NOR3 I0 (internal_0n[0], nCv_0n[1], nCv_0n[2], nCv_0n[3]);
NOR3 I1 (internal_0n[1], nCv_0n[4], nCv_0n[5], nCv_0n[6]);
NOR2 I2 (internal_0n[2], nCv_0n[7], nCv_0n[8]);
AND3 I3 (done_0n, internal_0n[0], internal_0n[1], internal_0n[2]);
BUFF I4 (out_0d[0], addOut_0n[0]);
BUFF I5 (out_0d[1], addOut_0n[1]);
BUFF I6 (out_0d[2], addOut_0n[2]);
BUFF I7 (out_0d[3], addOut_0n[3]);
BUFF I8 (out_0d[4], addOut_0n[4]);
BUFF I9 (out_0d[5], addOut_0n[5]);
BUFF I10 (out_0d[6], addOut_0n[6]);
BUFF I11 (out_0d[7], addOut_0n[7]);
BALSA_FA I12 (nStart_0n, n_0n[0], w_0n[0], nCv_0n[0], c_0n[0], nCv_0n[1], c_0n[1], addOut_0n[0]);
BALSA_FA I13 (nStart_0n, n_0n[1], w_0n[1], nCv_0n[1], c_0n[1], nCv_0n[2], c_0n[2], addOut_0n[1]);
BALSA_FA I14 (nStart_0n, n_0n[2], w_0n[2], nCv_0n[2], c_0n[2], nCv_0n[3], c_0n[3], addOut_0n[2]);
BALSA_FA I15 (nStart_0n, n_0n[3], w_0n[3], nCv_0n[3], c_0n[3], nCv_0n[4], c_0n[4], addOut_0n[3]);
BALSA_FA I16 (nStart_0n, n_0n[4], w_0n[4], nCv_0n[4], c_0n[4], nCv_0n[5], c_0n[5], addOut_0n[4]);
BALSA_FA I17 (nStart_0n, n_0n[5], w_0n[5], nCv_0n[5], c_0n[5], nCv_0n[6], c_0n[6], addOut_0n[5]);
BALSA_FA I18 (nStart_0n, n_0n[6], w_0n[6], nCv_0n[6], c_0n[6], nCv_0n[7], c_0n[7], addOut_0n[6]);
BALSA_FA I19 (nStart_0n, n_0n[7], w_0n[7], nCv_0n[7], c_0n[7], nCv_0n[8], c_0n[8], addOut_0n[7]);
BUFF I20 (nCv_0n[0], nStart_0n);
BUFF I21 (c_0n[0], gnd);
INV I22 (nStart_0n, start_0n);
BUFF I23 (n_0n[0], inpB_0d[0]);
BUFF I24 (n_0n[1], inpB_0d[1]);
BUFF I25 (n_0n[2], inpB_0d[2]);
BUFF I26 (n_0n[3], inpB_0d[3]);
BUFF I27 (n_0n[4], inpB_0d[4]);
BUFF I28 (n_0n[5], inpB_0d[5]);
BUFF I29 (n_0n[6], inpB_0d[6]);
BUFF I30 (n_0n[7], inpB_0d[7]);
BUFF I31 (w_0n[0], inpA_0d[0]);
BUFF I32 (w_0n[1], inpA_0d[1]);
BUFF I33 (w_0n[2], inpA_0d[2]);
BUFF I34 (w_0n[3], inpA_0d[3]);
BUFF I35 (w_0n[4], inpA_0d[4]);
BUFF I36 (w_0n[5], inpA_0d[5]);
BUFF I37 (w_0n[6], inpA_0d[6]);
BUFF I38 (w_0n[7], inpA_0d[7]);
BUFF I39 (inpB_0r, inpB_0a);
BUFF I40 (inpA_0r, inpA_0a);
BUFF I41 (out_0a, out_0r);
BUFF I42 (go_0a, done_0n);
BUFF I43 (start_0n, go_0r);
endmodule
module Balsa_BF (
go_0r, go_0a,
i1_0r, i1_0a, i1_0d,
i2_0r, i2_0a, i2_0d,
o_0r, o_0a, o_0d
);
input go_0r;
output go_0a;
output i1_0r;
input i1_0a;
input [7:0] i1_0d;
output i2_0r;
input i2_0a;
input [7:0] i2_0d;
input o_0r;
output o_0a;
output [7:0] o_0d;
BrzBinaryFunc__Data_8_8_8_s3_Add_s5_False__m7m I0 (go_0r, go_0a, o_0r, o_0a, o_0d[7:0], i1_0r, i1_0a, i1_0d[7:0], i2_0r, i2_0a, i2_0d[7:0]);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_PR_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_DLATCH_PR_BLACKBOX_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dlatch$PR (
Q ,
D ,
GATE ,
RESET
);
output Q ;
input D ;
input GATE ;
input RESET;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_PR_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int read() { int nm = 0, fh = 1; char cw = getchar(); for (; !isdigit(cw); cw = getchar()) if (cw == - ) fh = -fh; for (; isdigit(cw); cw = getchar()) nm = nm * 10 + (cw - 0 ); return nm * fh; } struct node { int x, y, w; } p[1000010]; int fa[1000010], cnt[1000010], vis[1000010], n, m, k; bool cmp(node x1, node x2) { return x1.w < x2.w; } int fd(int x) { return x == fa[x] ? x : fa[x] = fd(fa[x]); } bool merge(int x, int y) { int t1 = fd(x), t2 = fd(y); if (t1 == t2) return false; fa[t1] = t2; cnt[t2] += cnt[t1]; if (cnt[t2] == k) return true; return false; } int main() { n = read(), m = read(), k = read(); for (int i = 1; i <= k; i++) vis[read()] = 1; for (int i = 1; i <= n; i++) { fa[i] = i; if (vis[i]) cnt[i] = 1; } for (int i = 1; i <= m; i++) p[i].x = read(), p[i].y = read(), p[i].w = read(); sort(p + 1, p + m + 1, cmp); for (int i = 1; i <= m; i++) { if (merge(p[i].x, p[i].y)) { for (int j = 1; j <= k; j++) printf( %d , p[i].w); return 0; } } return 0; }
|
//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// Version and Release Control Information:
//
// File Revision : $Revision: $
// File Date : $Date: $
//
// Release Information : Cortex-M0 DesignStart-r1p0-00rel0
//------------------------------------------------------------------------------
// Verilog-2001 (IEEE Std 1364-2001)
//------------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
// Abstract : Simple AHB RAM behavioral model
//-----------------------------------------------------------------------------
module cmsdk_ahb_ram_beh #(
parameter AW = 16,// Address width
parameter filename = "",
parameter WS_N = 0, // First access wait state
parameter WS_S = 0) // Subsequent access wait state
(
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire HSEL, // Device select
input wire [AW-1:0] HADDR, // Address
input wire [1:0] HTRANS, // Transfer control
input wire [2:0] HSIZE, // Transfer size
input wire HWRITE, // Write control
input wire [31:0] HWDATA, // Write data
input wire HREADY, // Transfer phase done
output wire HREADYOUT, // Device ready
output wire [31:0] HRDATA, // Read data output
output wire HRESP); // Device response (always OKAY)
// Internal signals
reg [7:0] ram_data[0:((1<<AW)-1)]; // 64k byte of RAM data
wire read_valid; // Address phase read valid
wire write_valid; // Address phase write valid
reg read_enable; // Data phase read enable
reg write_enable; // Data phase write enable
reg [3:0] reg_byte_lane; // Data phase byte lane
reg [3:0] next_byte_lane; // Next state of reg_byte_lane
reg [7:0] rdata_out_0; // Read Data Output byte#0
reg [7:0] rdata_out_1; // Read Data Output byte#1
reg [7:0] rdata_out_2; // Read Data Output byte#2
reg [7:0] rdata_out_3; // Read Data Output byte#3
reg [AW-1:0] word_addr; // Word aligned address
wire [AW-1:0] nxt_word_addr; // Word aligned address
integer i; // Loop counter
// Wait state control
wire [31:0] nxt_waitstate_cnt;
reg [31:0] reg_waitstate_cnt;
wire sequential_access;
// Start of main code
// Initialize ROM
initial
begin
for (i=0;i<(1<<AW);i=i+1)
begin
ram_data[i] = 8'h00; //Initialize all data to 0
end
if (filename != "")
begin
$readmemh(filename, ram_data); // Then read in program code
end
end
// Generate read control (address phase)
assign read_valid = HSEL & HREADY & HTRANS[1] & (~HWRITE);
// Generate write control (address phase)
assign write_valid = HSEL & HREADY & HTRANS[1] & HWRITE;
// Read enable for each byte (address phase)
always @(read_valid or write_valid or HADDR or HSIZE)
begin
if (read_valid | write_valid)
begin
case (HSIZE)
0 : // Byte
begin
case (HADDR[1:0])
0: next_byte_lane = 4'b0001; // Byte 0
1: next_byte_lane = 4'b0010; // Byte 1
2: next_byte_lane = 4'b0100; // Byte 2
3: next_byte_lane = 4'b1000; // Byte 3
default:next_byte_lane = 4'b0000; // Address not valid
endcase
end
1 : // Halfword
begin
if (HADDR[1])
next_byte_lane = 4'b1100; // Upper halfword
else
next_byte_lane = 4'b0011; // Lower halfword
end
default : // Word
next_byte_lane = 4'b1111; // Whole word
endcase
end
else
next_byte_lane = 4'b0000; // Not reading
end
// Registering control signals to data phase
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
begin
reg_byte_lane <= 4'b0000;
read_enable <= 1'b0;
write_enable <= 1'b0;
word_addr <= {AW{1'b0}};
end
else if (HREADY)
begin
reg_byte_lane <= next_byte_lane;
read_enable <= read_valid;
write_enable <= write_valid;
word_addr <= nxt_word_addr;
end
end
assign nxt_word_addr = {HADDR[AW-1:2], 2'b00};
// Read operation
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[0]))
rdata_out_0 = ram_data[word_addr ];
else
rdata_out_0 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[1]))
rdata_out_1 = ram_data[word_addr+1];
else
rdata_out_1 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[2]))
rdata_out_2 = ram_data[word_addr+2];
else
rdata_out_2 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[3]))
rdata_out_3 = ram_data[word_addr+3];
else
rdata_out_3 = 8'h00;
// Registered write
always @(posedge HCLK)
begin
if (write_enable & reg_byte_lane[0])
begin
ram_data[word_addr ] = HWDATA[ 7: 0];
end
if (write_enable & reg_byte_lane[1])
begin
ram_data[word_addr+1] = HWDATA[15: 8];
end
if (write_enable & reg_byte_lane[2])
begin
ram_data[word_addr+2] = HWDATA[23:16];
end
if (write_enable & reg_byte_lane[3])
begin
ram_data[word_addr+3] = HWDATA[31:24];
end
end
// Wait state control
// Wait state generate treat access as sequential if
// HTRANS = 2'b11, or access address is in the same word,
// or if the access is in the next word
assign sequential_access = (HTRANS==2'b11) |
(HADDR[AW-1:2] == word_addr[AW-1:2]) |
(HADDR[AW-1:2] == (word_addr[AW-1:2]+1));
assign nxt_waitstate_cnt = (read_valid|write_valid) ?
((sequential_access) ? WS_S : WS_N) :
((reg_waitstate_cnt!=0) ? (reg_waitstate_cnt - 1) : 0);
// Register wait state counter
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
reg_waitstate_cnt <= 0;
else
reg_waitstate_cnt <= nxt_waitstate_cnt;
end
// Connect to top level
assign HREADYOUT = (reg_waitstate_cnt==0) ? 1'b1 : 1'b0;
assign HRESP = 1'b0; // Always response with OKAY
// Read data output
assign HRDATA = {rdata_out_3, rdata_out_2, rdata_out_1,rdata_out_0};
endmodule
|
#include <bits/stdc++.h> using namespace std; int l[100100]; int d[100100]; map<int, vector<int> > p; int cntd[202] = {0}; int main(int argc, char** argv) { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) cin >> l[i]; for (int i = 0; i < n; i++) cin >> d[i]; for (int i = 0; i < n; i++) { cntd[d[i]]++; p[l[i]].push_back(d[i]); } int sumcnt = 0; int sumval = 0; int ans = 1e9; int m = n; for (map<int, vector<int> >::reverse_iterator it = p.rbegin(); it != p.rend(); it++) { int j = 0; for (int i = 0; i < it->second.size(); i++) { cntd[it->second[i]]--; } j = 0; int need = m - (2 * (it->second.size())) + 1; int deleted = 0; while (j <= 201 && need > 0) { if (cntd[j] != 0) { deleted += ((min(need, cntd[j])) * j); need -= min(need, cntd[j]); } j++; } ans = min(ans, sumval + deleted); m -= it->second.size(); for (int i = 0; i < it->second.size(); i++) { sumval += (it->second[i]); } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t; cin >> t; while (t--) { long long p, f, s, w, cntS, cntW; cin >> p >> f >> cntS >> cntW >> s >> w; if (s > w) { swap(cntS, cntW); swap(s, w); } long long ans = 0; for (long long i = 0; i <= cntS; i++) { if (i * s > p) break; long long sf = i; long long ss = min(f / s, cntS - i); long long leftf = p - sf * s; long long lefts = f - ss * s; long long wf = min(cntW, leftf / w); long long ws = min(cntW - wf, lefts / w); ans = max(ans, ss + sf + wf + ws); } cout << ans << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_4_V
`define SKY130_FD_SC_HD__CLKBUF_4_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkbuf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkbuf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_4_V
|
#include <bits/stdc++.h> using namespace std; const long long int MOD = (long long int)1e9 + 7; long long int powmod(long long int a, long long int b) { long long int res = 1; while (b > 0) { if (b & 1) res = (res * a) % MOD; a = (a * a) % MOD; b = b >> 1; } return res % MOD; } vector<vector<long long int> > G; void solve(long long int testnum) { long long int n, m; cin >> n >> m; G.resize(n + 1); vector<long long int> tt(n + 1, 0); for (long long int i = 0; i < m; i++) { long long int a, b; cin >> a >> b; G[a].push_back(b); G[b].push_back(a); } vector<pair<long long int, long long int> > bc; for (long long int i = 1; i <= n; i++) { long long int temp; cin >> temp; bc.push_back(make_pair(temp, i)); } sort(bc.begin(), bc.end()); long long int check = 0; for (long long int i = 0; i < bc.size(); i++) { tt[bc[i].second] = bc[i].first; vector<long long int> naap; for (long long int j = 0; j < G[bc[i].second].size(); j++) { naap.push_back(tt[G[bc[i].second][j]]); } if (naap.size() == 0) { if (bc[i].first != 1) { check = 1; } continue; } sort(naap.begin(), naap.end()); for (long long int k = 0; k < naap.size(); k++) { long long int temp = naap[k]; if (k > 0) { temp -= naap[k - 1]; } if (temp > 1) { check = 1; } } if (naap[naap.size() - 1] != bc[i].first - 1) { check = 1; } } if (check == 1) { cout << -1 n ; return; } for (long long int i = 0; i < n; i++) { cout << bc[i].second << ; } cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t = 1; for (long long int i = 1; i <= t; i++) { solve(i); } }
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Generic source synchronous DDR output
*/
module ssio_ddr_out_diff #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Use 90 degree clock for transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire clk90,
input wire [WIDTH-1:0] input_d1,
input wire [WIDTH-1:0] input_d2,
output wire output_clk_p,
output wire output_clk_n,
output wire [WIDTH-1:0] output_q_p,
output wire [WIDTH-1:0] output_q_n
);
wire output_clk;
wire [WIDTH-1:0] output_q;
ssio_ddr_out #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.USE_CLK90(USE_CLK90),
.WIDTH(WIDTH)
)
ssio_ddr_out_inst(
.clk(clk),
.clk90(clk90),
.input_d1(input_d1),
.input_d2(input_d2),
.output_clk(output_clk),
.output_q(output_q)
);
genvar n;
generate
if (TARGET == "XILINX") begin
OBUFDS
clk_obufds_inst (
.I(output_clk),
.O(output_clk_p),
.OB(output_clk_n)
);
for (n = 0; n < WIDTH; n = n + 1) begin
OBUFDS
data_obufds_inst (
.I(output_q[n]),
.O(output_q_p[n]),
.OB(output_q_n[n])
);
end
end else if (TARGET == "ALTERA") begin
ALT_OUTBUF_DIFF
clk_outbuf_diff_inst (
.i(output_clk),
.o(output_clk_p),
.obar(output_clk_n)
);
for (n = 0; n < WIDTH; n = n + 1) begin
ALT_OUTBUF_DIFF
data_outbuf_diff_inst (
.i(output_q[n]),
.o(output_q_p[n]),
.obar(output_q_n[n])
);
end
end else begin
assign output_clk_p = output_clk;
assign output_clk_n = ~output_clk;
assign output_q_p = output_q;
assign output_q_n = ~output_q;
end
endgenerate
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; int d[1000001] = {0}; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0, a, b; i < m; ++i) scanf( %d%d , &a, &b), d[a]++, d[b]++; long long ans = 0; for (int i = 1; i <= n; ++i) { long long de = d[i], ade = n - 1 - de; ans += de * (de - 1) + ade * (ade - 1) - de * ade; } cout << ans / 6 << endl; return 0; }
|
//#############################################################################
//# Purpose: SPI master Registers #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
`include "spi_regmap.vh"
module spi_master_regs # (parameter CLKDIV = 1, // default clkdiv
parameter AW = 32, // addresss width
parameter PW = 104 // packet width
)
(
//clk,reset, cfg
input clk, // core clock
input nreset, // async active low reset
input hw_en, // block enable
//io interface
input [63:0] rx_data, // rx data
input rx_access, // rx access pulse
//control
output cpol, // clk polarity (default is 0)
output cpha, // clk phase shift (default is 0)
output lsbfirst, // send lsbfirst
output spi_en, // enable transmitter
output manual_mode,// sets manual ss control
output send_data, // controls ss in manual ss mode
output reg [7:0] clkdiv_reg, // baud rate setting
input [2:0] spi_state, // transmit state
input fifo_prog_full, // fifo reached half/full
input fifo_wait, // tx transfer wait
//packet to transmit
input access_in, // access from core
input [PW-1:0] packet_in, // data to core
output wait_out, // pushback from spi master
//return packet
output reg access_out, // writeback from spi
output [PW-1:0] packet_out, // writeback data from spi
input wait_in // pushback by core
);
//###############
//# LOCAL WIRES
//###############
reg [7:0] config_reg;
reg [7:0] status_reg;
reg [63:0] rx_reg;
reg [AW-1:0] reg_rdata;
reg autotran;
reg [AW-1:0] dstaddr_out;
reg [4:0] ctrlmode_out;
reg [1:0] datamode_out;
wire [31:0] reg_wdata;
wire reg_write;
wire reg_read;
wire config_write;
wire status_write;
wire clkdiv_write;
wire cmd_write;
wire tx_write;
wire irq_en;
wire wait_pulse;
integer i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From pe2 of packet2emesh.v
wire [AW-1:0] data_in; // From pe2 of packet2emesh.v
wire [1:0] datamode_in; // From pe2 of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From pe2 of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From pe2 of packet2emesh.v
wire write_in; // From pe2 of packet2emesh.v
// End of automatics
//####################################
//# DECODE
//####################################
packet2emesh #(.AW(AW),
.PW(PW))
pe2 (/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]),
// Inputs
.packet_in (packet_in[PW-1:0]));
assign reg_write = access_in & write_in;
assign reg_read = access_in & ~write_in;
assign reg_wdata[31:0] = data_in[AW-1:0];
assign config_write = reg_write & (dstaddr_in[5:0]==`SPI_CONFIG);
assign status_write = reg_write & (dstaddr_in[5:0]==`SPI_STATUS);
assign clkdiv_write = reg_write & (dstaddr_in[5:0]==`SPI_CLKDIV);
assign cmd_write = reg_write & (dstaddr_in[5:0]==`SPI_CMD);
assign tx_write = reg_write & (dstaddr_in[5:0]==`SPI_TX);
//####################################
//# CONFIG
//####################################
always @ (posedge clk or negedge nreset)
if (~nreset)
config_reg[7:0] <= 'b0;
else if(config_write)
config_reg[7:0] <= data_in[7:0];
assign spi_en = hw_en & ~config_reg[0]; // disable spi (on by default)
assign irq_en = config_reg[1]; // enable interrupt
assign cpol = config_reg[2]; // cpol
assign cpha = config_reg[3]; // cpha
assign lsbfirst = config_reg[4]; // send lsb first
assign manual_mode = config_reg[5]; // manual control of ss bit
assign send_data = config_reg[6]; // ss bit
//####################################
//# STATUS
//####################################
always @ (posedge clk or negedge nreset)
if (~nreset)
status_reg[7:0] <= 'b0;
else if(status_write)
status_reg[7:0] <= reg_wdata[7:0];
else
status_reg[7:0] <= {5'b0, //7:4
fifo_prog_full, //3
1'b0, //reserved
(rx_access | (~tx_write & status_reg[0]))};//0
//####################################
//# CLKDIV
//####################################
always @ (posedge clk or negedge nreset)
if (~nreset)
clkdiv_reg[7:0] <= CLKDIV;
else if(clkdiv_write)
clkdiv_reg[7:0] <= reg_wdata[7:0];
//####################################
//# RX REG
//####################################
always @ (posedge clk)
if(rx_access)
rx_reg[63:0] <= rx_data[63:0];
//####################################
//# READBACK
//####################################
//read back registers
always @ (posedge clk)
if(reg_read)
case(dstaddr_in[4:0])
`SPI_CONFIG : reg_rdata[31:0] <= {24'b0,config_reg[7:0]};
`SPI_STATUS : reg_rdata[31:0] <= {24'b0,status_reg[7:0]};
`SPI_CLKDIV : reg_rdata[31:0] <= {24'b0,clkdiv_reg[7:0]};
`SPI_RX0 : reg_rdata[31:0] <= rx_reg[31:0];
`SPI_RX1 : reg_rdata[31:0] <= rx_reg[63:32];
default : reg_rdata[31:0] <= 32'hDEADBEEF;
endcase // case (dstaddr_in[5:0])
always @ (posedge clk or negedge nreset)
if(!nreset)
access_out <= 1'b0;
else
access_out <= reg_read;
always @ (posedge clk)
begin
dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
ctrlmode_out[4:0] <= ctrlmode_in[4:0];
datamode_out[1:0] <= datamode_in[1:0];
end
//create a single cycle pulse on register read
oh_edge2pulse e2pulse (.out (wait_pulse),
.nreset (nreset),
.clk (clk),
.in (reg_read));
//TODO: fix!
assign wait_out = fifo_wait;
emesh2packet #(.AW(AW),
.PW(PW))
e2p (.write_out (1'b1),
.srcaddr_out ({(AW){1'b0}}),
.data_out (reg_rdata[AW-1:0]),
/*AUTOINST*/
// Outputs
.packet_out (packet_out[PW-1:0]),
// Inputs
.datamode_out (datamode_out[1:0]),
.ctrlmode_out (ctrlmode_out[4:0]),
.dstaddr_out (dstaddr_out[AW-1:0]));
endmodule // spi_master_regs
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; void solve() { map<string, pair<string, long long>> best; long long n; cin >> n; for (long long i = 0; i < n; i++) { string name; long long score; cin >> name >> score; best[name].second = max(best[name].second, score); } for (auto itr = best.begin(); itr != best.end(); itr++) { long long count = 0; for (auto i = best.begin(); i != best.end(); i++) { if (itr->second.second >= i->second.second) count++; } double percent = ((double)count / best.size() * 1.0) * 100.0; if (percent < 50.0) itr->second.first = noob ; else if (percent >= 50.0 && percent < 80.0) itr->second.first = random ; else if (percent >= 80.0 && percent < 90.0) itr->second.first = average ; else if (percent >= 90.0 && percent < 99.0) itr->second.first = hardcore ; else itr->second.first = pro ; } cout << best.size() << endl; for (auto x : best) { cout << x.first << << x.second.first << endl; } } int32_t main() { long long testcases = 1; while (testcases--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; int mod(int x, int m) { if (x < 0) x += m; return x % m; } int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; vector<int> v(n); int mx = -1; for (int i = 0; i < n; ++i) { cin >> v[i]; mx = max(v[i], mx); } int ans = -1; for (int i = 0; i < n; ++i) { if (v[i] == mx) { if (i != 0 && v[i - 1] < v[i]) { ans = i; break; } else if (i != (n - 1) && v[i] > v[i + 1]) { ans = i; break; } } } cout << ans + (ans != -1) << n ; } return 0; }
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: small_fifo_test_72.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module small_fifo_test_72 (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [71:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [71:0] q;
output [7:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "72"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "72"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_72.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_72.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_72.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_72.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_72_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_72_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module rs232 (
input clk,
input resetn,
input [ 3:0] ctrl_wr,
input ctrl_rd,
input [15:0] ctrl_addr,
input [31:0] ctrl_wdat,
output reg [31:0] ctrl_rdat,
output reg ctrl_done,
input rxd,
output reg txd
);
parameter integer BAUD_RATE = 115200;
parameter integer CLOCK_FREQ_HZ = 50000000;
localparam integer HALF_PERIOD = CLOCK_FREQ_HZ / (2 * BAUD_RATE);
reg [7:0] send_din;
wire [7:0] send_dout;
reg send_shift_in;
reg send_shift_out;
wire [7:0] send_used_slots;
wire [7:0] send_free_slots;
reg [7:0] recv_din;
wire [7:0] recv_dout;
reg recv_shift_in;
reg recv_shift_out;
wire [7:0] recv_used_slots;
wire [7:0] recv_free_slots;
reg [$clog2(3*HALF_PERIOD):0] rx_cnt;
reg [3:0] rx_state;
reg rxd_q;
always @(posedge clk) begin
rxd_q <= rxd;
recv_shift_in <= 0;
if (!resetn) begin
rx_state <= 0;
rx_cnt <= 0;
end else
if (rx_cnt) begin
rx_cnt <= rx_cnt - |1;
end else
if (rx_state == 0) begin
if (rxd_q && !rxd) begin
rx_state <= rx_state + |1;
rx_cnt <= 3*HALF_PERIOD;
end
end else begin
recv_din <= {rxd, recv_din[7:1]};
rx_state <= rx_state + |1;
rx_cnt <= 2*HALF_PERIOD;
if (rx_state == 8) begin
recv_shift_in <= 1;
rx_state <= 0;
end
end
end
reg [$clog2(2*HALF_PERIOD):0] tx_cnt;
reg [3:0] tx_state;
reg [7:0] tx_byte;
always @(posedge clk) begin
send_shift_out <= 0;
if (!resetn) begin
txd <= 1;
tx_state <= 0;
tx_cnt <= 0;
end else
if (tx_cnt) begin
tx_cnt <= tx_cnt - |1;
end else
if (tx_state == 0) begin
if (|send_used_slots) begin
txd <= 0;
send_shift_out <= 1;
tx_byte <= send_dout;
tx_cnt <= 2*HALF_PERIOD;
tx_state <= 1;
end
end else begin
txd <= tx_byte[0];
tx_byte <= tx_byte[7:1];
tx_cnt <= 2*HALF_PERIOD;
tx_state <= tx_state + |1;
if (tx_state == 9) begin
txd <= 1;
tx_state <= 0;
end
end
end
icosoc_mod_rs232_fifo send_fifo (
.clk (clk ),
.resetn (resetn ),
.din (send_din ),
.dout (send_dout ),
.shift_in (send_shift_in ),
.shift_out (send_shift_out ),
.used_slots(send_used_slots),
.free_slots(send_free_slots)
);
icosoc_mod_rs232_fifo recv_fifo (
.clk (clk ),
.resetn (resetn ),
.din (recv_din ),
.dout (recv_dout ),
.shift_in (recv_shift_in ),
.shift_out (recv_shift_out ),
.used_slots(recv_used_slots),
.free_slots(recv_free_slots)
);
always @(posedge clk) begin
ctrl_rdat <= 'bx;
ctrl_done <= 0;
recv_shift_out <= 0;
send_shift_in <= 0;
send_din <= 'bx;
// Register file:
// 0x00 shift data to/from send/recv fifos
// 0x04 number of unread bytes in recv fifo (read-only)
// 0x08 number of free bytes in send fifo (read-only)
if (resetn && !ctrl_done) begin
if (|ctrl_wr) begin
if (ctrl_addr == 0) begin
send_shift_in <= 1;
send_din <= ctrl_wdat;
end
ctrl_done <= 1;
end
if (ctrl_rd) begin
if (ctrl_addr == 0) begin
recv_shift_out <= 1;
ctrl_rdat <= recv_dout;
end
if (ctrl_addr == 4) ctrl_rdat <= recv_used_slots;
if (ctrl_addr == 8) ctrl_rdat <= send_free_slots;
ctrl_done <= 1;
end
end
end
endmodule
module icosoc_mod_rs232_fifo (
input clk,
input resetn,
input [7:0] din,
output [7:0] dout,
input shift_in,
input shift_out,
output reg [7:0] used_slots,
output reg [7:0] free_slots
);
reg [7:0] memory [0:255];
reg [7:0] wptr, rptr;
reg [7:0] memory_dout;
reg [7:0] pass_dout;
reg use_pass_dout;
assign dout = use_pass_dout ? pass_dout : memory_dout;
wire do_shift_in = shift_in && |free_slots;
wire do_shift_out = shift_out && |used_slots;
always @(posedge clk) begin
if (!resetn) begin
wptr <= 0;
rptr <= 0;
used_slots <= 0;
free_slots <= 255;
end else begin
memory[wptr] <= din;
wptr <= wptr + do_shift_in;
memory_dout <= memory[rptr + do_shift_out];
rptr <= rptr + do_shift_out;
use_pass_dout <= wptr == rptr;
pass_dout <= din;
if (do_shift_in && !do_shift_out) begin
used_slots <= used_slots + 1;
free_slots <= free_slots - 1;
end
if (!do_shift_in && do_shift_out) begin
used_slots <= used_slots - 1;
free_slots <= free_slots + 1;
end
end
end
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_ram.v
// Title : Pseudo dual-port RAM.
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : Options added to select EBRs (True-DP, Psuedo-DP, DQ, or
// : Distributed RAM).
// Version : 3.2
// : EBRs use SYNC resets instead of ASYNC resets.
// Version : 3.5
// : Added read-after-write hazard resolution when using true
// : dual-port EBRs
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_ram
(
// ----- Inputs -------
read_clk,
write_clk,
reset,
enable_read,
read_address,
enable_write,
write_address,
write_data,
write_enable,
// ----- Outputs -------
read_data
);
/*----------------------------------------------------------------------
Parameters
----------------------------------------------------------------------*/
parameter data_width = 1; // Width of the data ports
parameter address_width = 1; // Width of the address ports
/*----------------------------------------------------------------------
Inputs
----------------------------------------------------------------------*/
input read_clk; // Read clock
input write_clk; // Write clock
input reset; // Reset
input enable_read; // Access enable
input [address_width-1:0] read_address; // Read/write address
input enable_write; // Access enable
input [address_width-1:0] write_address;// Read/write address
input [data_width-1:0] write_data; // Data to write to specified address
input write_enable; // Write enable
/*----------------------------------------------------------------------
Outputs
----------------------------------------------------------------------*/
output [data_width-1:0] read_data; // Data read from specified addess
wire [data_width-1:0] read_data;
/*----------------------------------------------------------------------
Internal nets and registers
----------------------------------------------------------------------*/
reg [data_width-1:0] mem[0:(1<<address_width)-1]; // The RAM
reg [address_width-1:0] ra; // Registered read address
/*----------------------------------------------------------------------
Combinational Logic
----------------------------------------------------------------------*/
// Read port
assign read_data = mem[ra];
/*----------------------------------------------------------------------
Sequential Logic
----------------------------------------------------------------------*/
// Write port
always @(posedge write_clk)
if ((write_enable == `TRUE) && (enable_write == `TRUE))
mem[write_address] <= write_data;
// Register read address for use on next cycle
always @(posedge read_clk)
if (enable_read)
ra <= read_address;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_4_V
`define SKY130_FD_SC_MS__O2BB2AI_4_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_4_V
|
#include <bits/stdc++.h> using namespace std; long long int N, T; void solve() { cin >> N; vector<long long int> cnt(N + 1); long long int x; for (long long int i = 0; i < N; i++) { cin >> x; cnt[x]++; } long long int ans = 0; for (long long int s = 2; s <= 2 * N; s++) { long long int cur = 0; for (long long int i = 1; i < (s + 1) / 2; i++) { if (s - i > N) continue; else { cur += min(cnt[i], cnt[s - i]); } } if (s % 2 == 0) { cur += cnt[s / 2] / 2; } ans = max(ans, cur); } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> T; while (T--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int P = 1e9 + 7, N = 17, M = 16389, O = 131; int qp(int a, int b) { int r = 1; for (; b; b >>= 1, a = a * 1ll * a % P) if (b & 1) r = r * 1ll * a % P; return r; } int a[N], e[N][N], p[M], n, ll[O][O], lr[O][O], rl[O][O], rr[O][O]; int g(int x, int y) { int i, j, s = 1; for (i = 0; i < n; ++i) if (x >> i & 1) for (j = 0; j < n; ++j) if (y >> j & 1) s = s * 1ll * e[i][j] % P; return s; } int h(int x, int y) { return ll[x & 127][y & 127] * 1ll * lr[x & 127][y >> 7] % P * rl[x >> 7][y & 127] % P * rr[x >> 7][y >> 7] % P; } int main() { int m, i, j, w = 0; scanf( %d , &n); for (i = 0; i < n; ++i) scanf( %d , a + i); for (i = 0; i < n; ++i) for (j = 0; j < n; ++j) e[i][j] = a[i] * 1ll * qp(a[i] + a[j], P - 2) % P; for (i = 0; i < O; ++i) for (j = 0; j < O; ++j) ll[i][j] = lr[i][j] = rl[i][j] = rr[i][j] = 1; for (i = 0, m = 1 << min(n, 7); i < m; ++i) for (j = 0; j < m; ++j) if (!(i & j)) ll[i][j] = g(i, j); if (n > 7) { for (i = 0, m = 1 << n - 7; i < 128; ++i) for (j = 0; j < m; ++j) lr[i][j] = g(i, j << 7); for (i = 0; i < m; ++i) for (j = 0; j < 128; ++j) rl[i][j] = g(i << 7, j); for (i = 0; i < m; ++i) for (j = 0; j < m; ++j) if (!(i & j)) rr[i][j] = g(i << 7, j << 7); } for (i = 1, m = 1 << n; i < m; w = (w + p[i] * 1ll * h(i, m - 1 ^ i) % P * __builtin_popcount(i)) % P, ++i) for (p[i] = 1, j = i & i - 1; j; j = j - 1 & i) p[i] = (p[i] - p[j] * 1ll * h(j, i ^ j)) % P; printf( %d , (w + P) % P); return 0; }
|
#include <bits/stdc++.h> int main() { int n, m, min, max; scanf( %d %d %d %d , &n, &m, &min, &max); int arr[m]; for (int i = 0; i < m; i++) { scanf( %d , &arr[i]); } int chmin = 0, chmax = 0, wrong = 0; for (int i = 0; i < m; i++) { if (arr[i] == min) chmin = 1; if (arr[i] == max) chmax = 1; if (arr[i] > max || arr[i] < min) wrong = 1; } if (wrong == 1) printf( Incorrect n ); else if (chmin == 1 && chmax == 1) printf( Correct n ); else if (chmin == 1 || chmax == 1) { if (n - m >= 1) printf( Correct n ); else printf( Incorrect n ); } else { if (n - m >= 2) printf( Correct n ); else if (n - m >= 1 && min == max) printf( Correct n ); else printf( Incorrect n ); } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:200000000 ) using namespace std; template <typename T> inline T Abs(T x) { return (x >= 0) ? x : -x; } template <typename T> inline T sqr(T x) { return x * x; } template <typename T> inline string toStr(T x) { stringstream st; st << x; string s; st >> s; return s; } template <typename T> inline int bit(T mask, int b) { return (b >= 0 && (mask & (T(1) << b)) != 0) ? 1 : 0; } inline int nextInt() { int x; if (scanf( %d , &x) != 1) throw; return x; } inline long long nextInt64() { long long x; if (scanf( %lld , &x) != 1) throw; return x; } inline double nextDouble() { double x; if (scanf( %lf , &x) != 1) throw; return x; } const int INF = (int)1E9; const long long INF64 = (long long)1E18; const long double EPS = 1E-9; const long double PI = 3.1415926535897932384626433832795; const int MAXN = 500100; const int OSN = (1 << 19) - 1; int n, lst[MAXN], rst[MAXN], tree[2 * OSN + 10], tree0[2 * OSN + 10]; vector<int> g[MAXN], st; void DFS(int v, int prev) { lst[v] = int(st.size()); st.push_back(v); for (int i = 0; i < (int)(g[v].size()); i++) { int u = g[v][i]; if (u != prev) DFS(u, v); } rst[v] = int(st.size() - 1); } void update(int v, int value) { v += OSN; tree[v] = value; while (v > 0) { v = (v - 1) >> 1; tree[v] = max(tree[v], value); } } void update(int v, int l, int r, int ll, int rr, int value) { if (l > rr || ll > r || ll > rr) return; if (ll <= l && r <= rr) { tree0[v] = value; return; } int mid = (l + r) >> 1; update(2 * v + 1, l, mid, ll, rr, value); update(2 * v + 2, mid + 1, r, ll, rr, value); } int getMax(int v, int l, int r, int ll, int rr) { if (l > rr || ll > r || ll > rr) return 0; if (ll <= l && r <= rr) return tree[v]; int mid = (l + r) >> 1; return max(getMax(2 * v + 1, l, mid, ll, rr), getMax(2 * v + 2, mid + 1, r, ll, rr)); } int getMax(int v, int l, int r, int x) { if (l > x || x > r) return 0; if (l == r) return tree0[v]; int mid = (l + r) >> 1; int ans = tree0[v]; ans = max(ans, getMax(2 * v + 1, l, mid, x)); ans = max(ans, getMax(2 * v + 2, mid + 1, r, x)); return ans; } int check(int v) { int t0 = getMax(0, 0, OSN, lst[v], rst[v]); int t1 = getMax(0, 0, OSN, lst[v]); return int(t0 < t1); } int main() { n = nextInt(); for (int i = 0; i < (int)(n - 1); i++) { int v = nextInt() - 1; int u = nextInt() - 1; g[v].push_back(u); g[u].push_back(v); } DFS(0, 0); int q = nextInt(); for (int i = 0; i < (int)(q); i++) { int type = nextInt(); int v = nextInt() - 1; if (type == 1) update(0, 0, OSN, lst[v], rst[v], i + 1); if (type == 2) update(lst[v], i + 1); if (type == 3) printf( %d n , check(v)); } return 0; }
|
// test_usb_ft232.v
`timescale 1 ns / 1 ps
module test_usb32;
reg clk = 0;
reg reset = 1;
// FT232 interface
reg usb_clk = 0;
wire wr_n;
wire rd_n;
wire oe_n;
wire [7:0]data;
reg txe_n = 1;
reg rxf_n = 1;
wire siwu_n;
// avs_ctrl
reg avs_ctrl_address = 1'bx;
reg avs_ctrl_write = 0;
reg [7:0]avs_ctrl_writedata = 8'hxx;
reg avs_ctrl_read = 0;
wire [7:0]avs_ctrl_readdata;
// asi_uplink
wire asi_uplink_ready;
reg asi_uplink_valid = 0;
reg [31:0]asi_uplink_data = 32'hxxxxxxxx;
reg asi_uplink_startofpacket = 0;
reg asi_uplink_endofpacket = 0;
reg [1:0]asi_uplink_empty = 2'bxx;
// --- clk
always #10 clk = !clk;
initial #15 reset = 0;
task waitclk(input integer n);
begin
repeat (n) @(posedge clk);
end
endtask
task waitusbclk(input integer n);
begin
repeat (n) @(posedge usb_clk);
end
endtask
// === ft232 ==============================================================
// --- transmitter
always #8.333 usb_clk = !usb_clk;
reg [3:0]ft_cnt = 0;
always @(posedge usb_clk)
begin
txe_n <= ft_cnt < 3;
ft_cnt <= ft_cnt + 1;
end
// -- receiver
reg [7:0]ft_data = 0;
reg [2:0]ft_wait = 0;
initial
begin
waitusbclk(5);
forever @(posedge usb_clk)
begin
rxf_n <= ft_wait < 2;
ft_wait <= ft_wait + 1;
end
end
always @(posedge usb_clk) if (!rxf_n && !rd_n) ft_data = ft_data + 1;
assign data = oe_n ? 8'hzz : (rd_n ? 8'hxx : ft_data);
// log write access to ft232, log read access from ft232
reg [7:0]ft232_write;
reg [7:0]ft232_read;
always @(negedge usb_clk)
begin
ft232_write <= wr_n ? 8'hzz : (txe_n ? 8'hxx : data);
ft232_read <= rd_n ? 8'hzz : (rxf_n ? 8'hxx : data);
end
// === avs_ctrl ===========================================================
task avsWrite(input [7:0]value, input address);
begin
waitclk(1);
avs_ctrl_write <= 1;
avs_ctrl_address <= 1;
avs_ctrl_writedata <= value;
waitclk(1);
avs_ctrl_write <= 0;
avs_ctrl_address <= 1'bx;
avs_ctrl_writedata <= 8'hxx;
end
endtask
task avsRead(output [7:0]value, input address);
begin
waitclk(1);
avs_ctrl_read <= 1;
avs_ctrl_address <= address;
@(negedge clk);
value <= avs_ctrl_readdata;
waitclk(1);
avs_ctrl_read <= 0;
avs_ctrl_address <= 1'bx;
end
endtask
reg [7:0]ret;
reg [7:0]rxdata;
initial
begin
waitclk(5);
avsRead(ret, 1);
avsRead(ret, 1);
avsWrite(8'hfe, 1);
forever
begin
avsRead(ret, 1);
if (ret) avsRead(rxdata,0);
end
end
// log read/write from/to avs ctrl
reg [7:0]avs_read_0;
reg [7:0]avs_read_1;
reg [7:0]avs_write_0;
reg [7:0]avs_write_1;
always @(negedge clk)
begin
avs_read_0 <= (avs_ctrl_read && !avs_ctrl_address) ? avs_ctrl_readdata : 8'hzz;
avs_read_1 <= (avs_ctrl_read && avs_ctrl_address) ? avs_ctrl_readdata : 8'hzz;
avs_write_0 <= (avs_ctrl_write && !avs_ctrl_address) ? avs_ctrl_writedata : 8'hzz;
avs_write_1 <= (avs_ctrl_write && avs_ctrl_address) ? avs_ctrl_writedata : 8'hzz;
end
// === asi_uplink =========================================================
task asi_burst_data(input [7:0]value, input integer size);
begin
case (size)
0:
begin
asi_uplink_data <= 32'hxxxxxx;
asi_uplink_empty <= 2'bxx;
end
1:
begin
asi_uplink_data <= {value, 24'hxxxxxx};
asi_uplink_empty <= 3;
end
2:
begin
asi_uplink_data <= {value, value+8'h1, 16'hxxxx};
asi_uplink_empty <= 2;
end
3:
begin
asi_uplink_data <= {value, value+8'h1, value+8'h2, 8'hxx};
asi_uplink_empty <= 1;
end
default
begin
asi_uplink_data <= {value, value+8'h1, value+8'h2, value+8'h3};
asi_uplink_empty <= (size == 4) ? 2'b00 : 2'bxx;
end
endcase
end
endtask
task asi_burst(input [7:0]startvalue, input integer length);
begin
waitclk(1);
asi_uplink_startofpacket <= 1;
asi_uplink_valid <= 1;
while (length > 0)
begin
asi_burst_data(startvalue, length);
if (length <= 4) asi_uplink_endofpacket <= 1;
startvalue = startvalue + 4;
length = length - 4;
waitclk(1);
asi_uplink_startofpacket <= 0;
while (!asi_uplink_ready) waitclk(1);
end
asi_uplink_startofpacket <= 0;
asi_uplink_endofpacket <= 0;
asi_uplink_valid <= 0;
asi_uplink_data <= 32'hxxxxxxxx;
asi_uplink_empty <= 2'bxx;
asi_uplink_valid <= 0;
end
endtask
initial
begin
waitclk(10);
forever @(posedge clk)
begin
asi_burst(8'h20, 1);
waitclk(5);
asi_burst(8'h30, 2);
waitclk(5);
asi_burst(8'h40, 3);
waitclk(5);
asi_burst(8'h50, 4);
waitclk(5);
asi_burst(8'h80, 10);
waitclk(5);
asi_burst(8'hc0, 19);
avsWrite(1, 1);
waitclk(2);
asi_burst(8'h00, 301);
avsWrite(1, 1);
waitclk(10);
repeat (6)
begin
asi_burst(8'h80, 7);
waitclk(4);
end
asi_burst(8'h40, 17);
waitclk(200);
end
end
// log write to uplink sink
reg [7:0]uplink_data3;
reg [7:0]uplink_data2;
reg [7:0]uplink_data1;
reg [7:0]uplink_data0;
always @(negedge clk)
begin
if (asi_uplink_valid && asi_uplink_ready)
begin
uplink_data3 <= asi_uplink_data[31:24];
uplink_data2 <= (!asi_uplink_endofpacket || (asi_uplink_empty < 3)) ?
asi_uplink_data[23:16] : 8'hzz;
uplink_data1 <= (!asi_uplink_endofpacket || (asi_uplink_empty < 2)) ?
asi_uplink_data[15:8] : 8'hzz;
uplink_data0 <= (!asi_uplink_endofpacket || (asi_uplink_empty < 1)) ?
asi_uplink_data[7:0] : 8'hzz;
end
else
begin
uplink_data3 <= 8'hzz;
uplink_data2 <= 8'hzz;
uplink_data1 <= 8'hzz;
uplink_data0 <= 8'hzz;
end
end
usb32 DUT
(
.clk(clk),
.reset(reset),
.avs_ctrl_address(avs_ctrl_address),
.avs_ctrl_write(avs_ctrl_write),
.avs_ctrl_writedata(avs_ctrl_writedata),
.avs_ctrl_read(avs_ctrl_read),
.avs_ctrl_readdata(avs_ctrl_readdata),
.asi_uplink_ready(asi_uplink_ready),
.asi_uplink_valid(asi_uplink_valid),
.asi_uplink_data(asi_uplink_data),
.asi_uplink_startofpacket(asi_uplink_startofpacket),
.asi_uplink_endofpacket(asi_uplink_endofpacket),
.asi_uplink_empty(asi_uplink_empty),
.usb_clk(usb_clk),
.wr_n(wr_n),
.rd_n(rd_n),
.oe_n(oe_n),
.data(data),
.txe_n(txe_n),
.rxf_n(rxf_n),
.siwu_n(siwu_n)
);
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; const int M1 = 1000000007; const int M2 = 1000000087; int N; int H1[310000]; int P1[310000]; int H2[310000]; int P2[310000]; int HH1, HH2; int n, m; vector<int> g[100007]; string s[100007]; char t[300007]; int ans; void precalc() { H1[0] = H2[0] = 0; P1[0] = P2[0] = 1; for (int i = 1; i < 300007; i++) { P1[i] = (P1[i - 1] * 31LL) % M1; P2[i] = (P2[i - 1] * 37LL) % M2; } for (int i = 0, _n = (m); i < _n; ++i) { char c = t[i] - a + 1; HH1 = (HH1 * 31LL + c) % M1; HH2 = (HH2 * 37LL + c) % M2; } } void addChar(char c) { c = c - a + 1; H1[N + 1] = (H1[N] * 31LL + c) % M1; H2[N + 1] = (H2[N] * 37LL + c) % M2; N++; } bool isTail() { if (N < m) return false; int r = N - 1; int l = r - m + 1; int CH1 = H1[r + 1] - ((long long)H1[l] * P1[r - l + 1]) % M1; if (CH1 < 0) CH1 += M1; int CH2 = H2[r + 1] - ((long long)H2[l] * P2[r - l + 1]) % M2; if (CH2 < 0) CH2 += M2; return CH1 == HH1 && CH2 == HH2; } void dfs(int v) { for (int i = 0, _n = ((int)((s[v]).size())); i < _n; ++i) { addChar(s[v][i]); ans += isTail(); } for (int i = 0, _n = ((int)((g[v]).size())); i < _n; ++i) dfs(g[v][i]); N -= (int)((s[v]).size()); } void solution() { scanf( %d n , &n); for (int i = 0, _n = (n - 1); i < _n; ++i) { int p; scanf( %d %s n , &p, t); s[i + 1] = string(t); g[p - 1].push_back(i + 1); } m = strlen(gets(t)); precalc(); dfs(0); printf( %d n , ans); } int main() { solution(); return 0; }
|
#include <bits/stdc++.h> using namespace std; #define int long long //#define int unsigned int //#define pb push_back //#define mp make_pair #define mod 1000000007 #define double long double #define all(x) x.begin(), x.end() #define debug(x) cout << #x << = << x << n const int inf=1e18; const int maxu=200005; //int d; //vector <int> adj[maxu]; //vector <int> vis(maxu); //vector <vector <int>> v(maxu); /*int fun(int a,int b){ if(b==0)return 1; else if(a==1)return 1; int temp=fun(a,b/2)%mod; temp=(temp*temp)%mod; if(b%2==1)temp=(temp*a)%mod; return temp%mod; } int inv(int a,int b){ return (a*fun(b,mod-2))%mod; } void dfs(int s){ if(vis[s])return; vis[s]=1; for(auto u:adj[s]){ dfs(u); } }*/ signed main() { /* #ifndef ONLINE_JUDGE freopen( inputhsr.txt , r , stdin); freopen( outputhsr.txt , w , stdout); #endif */ ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int i,j,k=0,n,t=1,m,l=0; //cin>>t; while(t--){ cin>>n; int a[n+1]; for(i=1;i<=n;i++)cin>>a[i]; vector <vector<int>> v; for(i=1;i<=n;i++){ for(j=i+1;j<=n;j++){ int val=abs(a[j]-a[i]); if(a[i]<a[j]){ vector <int> v1={val,j,i}; v.push_back(v1); } else{ vector <int> v1={val,i,j}; v.push_back(v1); } } } sort(all(v)); reverse(all(v)); int ans=false; for(auto u:v){ cout<< ? <<u[1]<< <<u[2]<<endl; string s; cin>>s; if(s== Yes ){ cout<< ! <<u[1]<< <<u[2]<<endl; ans=true;break; } } if(!ans){ cout<< ! <<0<< <<0<<endl; } /* for(i=0;i<=n;i++)vis[i]=0; for(i=0;i<=n;i++){ adj[i].clear(); } */ /*string s; cin>>s; n=s.length();*/ //memset(a,0,sizeof(a)); //cout<<fixed<<setprecision(10)<<ans<< n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 400; int n, m, wynik, A[N], B[N]; map<double, bitset<120> > mapa; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 1; i <= n; i++) cin >> A[i]; for (int i = 1; i <= m; i++) cin >> B[i]; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { double pom = (A[i] + B[j]) / 2.0; mapa[pom][i - 1] = mapa[pom][n + j - 1] = true; } } for (auto u : mapa) for (auto v : mapa) wynik = max(wynik, (int)(u.second | v.second).count()); cout << wynik << endl; getchar(); getchar(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_TB_V
`define SKY130_FD_SC_LS__SDFSBP_TB_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfsbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__sdfsbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_TB_V
|
#include <bits/stdc++.h> using namespace std; long long n; long long b[500010], a[500010]; void solve() { cin >> n; for (int i = 0; i < n; i++) cin >> b[i]; long long sum = 0, flag = 1; for (int i = 0; i < n; i++) sum += b[i]; if (sum % (n * (n + 1) / 2)) flag = 0; sum /= n * (n + 1) / 2; for (int i = 0; i < n; i++) { long long dx = sum - b[(i + 1) % n] + b[i]; if (dx % n || dx <= 0) flag = 0; else a[(i + 1) % n] = dx / n; } if (flag) { cout << YES << n ; for (int i = 0; i < n; i++) cout << a[i] << ; cout << n ; } else cout << NO << n ; } int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); std::cout.tie(0); int _; cin >> _; while (_--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 1; int n, m; vector<int> A[MAXN]; int d[MAXN]; void dfs(int nod) { for (int i = 0; i < A[nod].size(); i++) { int v = A[nod][i]; if (d[v] == 0) { d[v] = d[nod] + 1; dfs(v); } } } int main() { cin >> n >> m; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; A[a].push_back(b); A[b].push_back(a); } d[1] = 1; dfs(1); int u = max_element(d + 1, d + n + 1) - d; fill(d + 1, d + n + 1, 0); d[u] = 1; dfs(u); int sol = *max_element(d + 1, d + n + 1); sol--; cout << sol << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2B_1_V
`define SKY130_FD_SC_LS__NAND2B_1_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2b_1 (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2b_1 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_TB_V
`define SKY130_FD_SC_LP__O32AI_TB_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__o32ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFINV_16_V
`define SKY130_FD_SC_HS__BUFINV_16_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufinv_16 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFINV_16_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sat May 27 21:26:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_stub.v
// Design : system_xlconstant_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xlconstant_0_0(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[23:0]" */;
output [23:0]dout;
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
reverse#(parameter width = 1) (
input [(width - 1):0] in, output [(width - 1):0] out
);
genvar ix;
generate
for (ix = 0; ix < width; ix = ix + 1) begin :Bit
assign out[ix] = in[width - 1 - ix];
end
endgenerate
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
lowMaskHiLo#(
parameter inWidth = 1,
parameter topBound = 1,
parameter bottomBound = 0
) (
input [(inWidth - 1):0] in,
output [(topBound - bottomBound - 1):0] out
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam numInVals = 1<<inWidth;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire signed [numInVals:0] c;
assign c[numInVals] = 1;
assign c[(numInVals - 1):0] = 0;
wire [(topBound - bottomBound - 1):0] reverseOut =
(c>>>in)>>(numInVals - topBound);
reverse#(topBound - bottomBound) reverse(reverseOut, out);
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
lowMaskLoHi#(
parameter inWidth = 1,
parameter topBound = 0,
parameter bottomBound = 1
) (
input [(inWidth - 1):0] in,
output [(bottomBound - topBound - 1):0] out
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam numInVals = 1<<inWidth;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire signed [numInVals:0] c;
assign c[numInVals] = 1;
assign c[(numInVals - 1):0] = 0;
wire [(bottomBound - topBound - 1):0] reverseOut =
(c>>>~in)>>(topBound + 1);
reverse#(bottomBound - topBound) reverse(reverseOut, out);
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
countLeadingZeros#(parameter inWidth = 1, parameter countWidth = 1) (
input [(inWidth - 1):0] in, output [(countWidth - 1):0] count
);
wire [(inWidth - 1):0] reverseIn;
reverse#(inWidth) reverse_in(in, reverseIn);
wire [inWidth:0] oneLeastReverseIn =
{1'b1, reverseIn} & ({1'b0, ~reverseIn} + 1);
genvar ix;
generate
for (ix = 0; ix <= inWidth; ix = ix + 1) begin :Bit
wire [(countWidth - 1):0] countSoFar;
if (ix == 0) begin
assign countSoFar = 0;
end else begin
assign countSoFar =
Bit[ix - 1].countSoFar | (oneLeastReverseIn[ix] ? ix : 0);
if (ix == inWidth) assign count = countSoFar;
end
end
endgenerate
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
compressBy2#(parameter inWidth = 1) (
input [(inWidth - 1):0] in, output [((inWidth - 1)/2):0] out
);
localparam maxBitNumReduced = (inWidth - 1)/2;
genvar ix;
generate
for (ix = 0; ix < maxBitNumReduced; ix = ix + 1) begin :Bit
assign out[ix] = |in[(ix*2 + 1):ix*2];
end
endgenerate
assign out[maxBitNumReduced] = |in[(inWidth - 1):maxBitNumReduced*2];
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
compressBy4#(parameter inWidth = 1) (
input [(inWidth - 1):0] in, output [(inWidth - 1)/4:0] out
);
localparam maxBitNumReduced = (inWidth - 1)/4;
genvar ix;
generate
for (ix = 0; ix < maxBitNumReduced; ix = ix + 1) begin :Bit
assign out[ix] = |in[(ix*4 + 3):ix*4];
end
endgenerate
assign out[maxBitNumReduced] = |in[(inWidth - 1):maxBitNumReduced*4];
endmodule
|
/*
******************************************************************************
* File Name : tb_ada_exu.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 17th, 2014
* Author : Angel Terrones <>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Testbench for the EXU (execution unit)
******************************************************************************
*/
`timescale 1ns / 1ns
`include "ada_defines.v"
`define cycle 10
module tb_ada_exu;
// inputs
reg clk;
reg rst;
reg [31:0] port_a;
reg [31:0] port_b;
reg [4:0] operation;
reg ex_stall;
reg ex_flush;
//outputs
wire [31:0] result;
wire exc_div_zero;
wire haz_ex_stall;
//--------------------------------------------------------------------------
// UUT
//--------------------------------------------------------------------------
ada_exu uut(
.clk(clk),
.rst(rst),
.port_a(port_a),
.port_b(port_b),
.operation(operation),
.ex_stall(ex_stall),
.ex_flush(ex_flush),
.result(result),
.exc_div_zero(exc_div_zero),
.haz_ex_stall(haz_ex_stall)
);
//--------------------------------------------------------------------------
// Setup
//--------------------------------------------------------------------------
initial begin
// Initialize Inputs
clk = 1;
rst = 1;
port_a = 0;
port_b = 0;
operation = 0;
ex_stall = 0;
ex_flush = 0;
// dump the wave file
$dumpfile("tb_exu.vcd");
$dumpvars;
end
//--------------------------------------------------------------------------
// clock
//--------------------------------------------------------------------------
always begin
#(`cycle/2) clk = !clk;
end
//--------------------------------------------------------------------------
// simulation
//--------------------------------------------------------------------------
initial begin
rst = #(5*`cycle)0;
@(posedge clk)
operation <= 5'b11111;
// the interesting part
@(posedge clk)
operation <= `ALU_OP_MULS;
port_a <= 32'h8000_0000;
port_b <= 32'h0400_0000;
@(posedge clk)
operation <= `ALU_OP_MULU;
port_a <= 32'd200;
port_b <= 32'd400;
@(posedge clk)
operation <= `ALU_OP_DIVS;
port_a <= 32'd2000;
port_b <= 32'd20;
@(posedge clk) operation <= `ALU_OP_ADD;
@(posedge clk) operation <= `ALU_OP_MULS;
ex_stall <= 1;
@(posedge clk) operation <= `ALU_OP_MULU;
ex_stall <= 1;
@(posedge clk) operation <= `ALU_OP_ADD;
#(35*`cycle);
@(posedge clk) operation <= `ALU_OP_MFH;
ex_stall <= 0;
@(posedge clk) operation <= `ALU_OP_MFL;
ex_stall <= 0;
port_a <= -32'd2000;
port_b <= 32'd25;
@(posedge clk) operation <= `ALU_OP_DIVS;
@(posedge clk) operation <= 5'b11111;
#(35*`cycle);
@(posedge clk) operation <= `ALU_OP_MFH;
@(posedge clk) operation <= `ALU_OP_MFL;
@(posedge clk) operation <= 5'b11111;
@(posedge clk) operation <= `ALU_OP_MTH;
port_a <= 32'hDEAD_BEEF;
@(posedge clk) operation <= `ALU_OP_MTL;
port_a <= 32'h0BAD_F00D;
@(posedge clk)
@(posedge clk)
@(posedge clk)
@(posedge clk)
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 4e6 + 7; const int inf = INT_MAX; const long long inff = 1e18; const long long mod = 1e9 + 7; int d, s; pair<int, int> dp[maxn]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cin >> d >> s; for (int i = 0; i <= (d + 1) * (s + 1); i++) dp[i] = make_pair(-1, 0); queue<int> q; q.push(0); while (!q.empty()) { int now = q.front(); int sum = now / d, r = now % d; q.pop(); for (int i = 0; i < 10; i++) { if (sum + i <= s && (dp[(sum + i) * d + (r * 10 + i) % d].first == -1)) { dp[(sum + i) * d + (r * 10 + i) % d] = make_pair(now, i); q.push((sum + i) * d + (r * 10 + i) % d); } } } int now = s * d; if (dp[now].first == -1) return cout << -1 << n , 0; else { vector<int> v; while (now) { v.push_back(dp[now].second); now = dp[now].first; } reverse((v).begin(), (v).end()); for (int i : v) cout << i; cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; int n, a[2006]; int one, g, mn = 1e9; int gcd(int _a, int _b) { return _b == 0 ? _a : gcd(_b, _a % _b); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); g = gcd(g, a[i]); if (a[i] == 1) one++; } if (one != 0) { printf( %d n , n - one); return 0; } if (g != 1) { puts( -1 ); return 0; } for (int i = 1; i <= n; i++) { int b = a[i]; for (int j = i + 1; j <= n; j++) { b = gcd(b, a[j]); if (b == 1) { mn = min(mn, j - i); break; } } } printf( %d n , mn + n - 1); return 0; }
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Int63 FloatClass.
(** * Definition of the interface for primitive floating-point arithmetic
This interface provides processor operators for the Binary64 format of the
IEEE standard. *)
(** ** Type definition for the co-domain of [compare] *)
Variant float_comparison : Set := FEq | FLt | FGt | FNotComparable.
Register float_comparison as kernel.ind_f_cmp.
Register float_class as kernel.ind_f_class.
(** ** The main type *)
(** [float]: primitive type for Binary64 floating-point numbers. *)
Primitive float := #float64_type.
(** ** Syntax support *)
Module Import PrimFloatNotationsInternalA.
Declare Scope float_scope.
Delimit Scope float_scope with float.
Bind Scope float_scope with float.
End PrimFloatNotationsInternalA.
Declare ML Module "float_syntax_plugin".
(** ** Floating-point operators *)
Primitive classify := #float64_classify.
Primitive abs := #float64_abs.
Primitive sqrt := #float64_sqrt.
Primitive opp := #float64_opp.
Primitive eqb := #float64_eq.
Primitive ltb := #float64_lt.
Primitive leb := #float64_le.
Primitive compare := #float64_compare.
Primitive mul := #float64_mul.
Primitive add := #float64_add.
Primitive sub := #float64_sub.
Primitive div := #float64_div.
Module Import PrimFloatNotationsInternalB.
Notation "- x" := (opp x) : float_scope.
Notation "x =? y" := (eqb x y) (at level 70, no associativity) : float_scope.
Notation "x <? y" := (ltb x y) (at level 70, no associativity) : float_scope.
Notation "x <=? y" := (leb x y) (at level 70, no associativity) : float_scope.
Notation "x ?= y" := (compare x y) (at level 70, no associativity) : float_scope.
Notation "x * y" := (mul x y) : float_scope.
Notation "x + y" := (add x y) : float_scope.
Notation "x - y" := (sub x y) : float_scope.
Notation "x / y" := (div x y) : float_scope.
End PrimFloatNotationsInternalB.
(** ** Conversions *)
(** [of_int63]: convert a primitive integer into a float value.
The value is rounded if need be. *)
Primitive of_int63 := #float64_of_int63.
(** Specification of [normfr_mantissa]:
- If the input is a float value with an absolute value inside $[0.5, 1.)$#[0.5, 1.)#;
- Then return its mantissa as a primitive integer.
The mantissa will be a 53-bit integer with its most significant bit set to 1;
- Else return zero.
The sign bit is always ignored. *)
Primitive normfr_mantissa := #float64_normfr_mantissa.
(** ** Exponent manipulation functions *)
(** [frshiftexp]: convert a float to fractional part in $[0.5, 1.)$#[0.5, 1.)#
and integer part. *)
Primitive frshiftexp := #float64_frshiftexp.
(** [ldshiftexp]: multiply a float by an integral power of 2. *)
Primitive ldshiftexp := #float64_ldshiftexp.
(** ** Predecesor/Successor functions *)
(** [next_up]: return the next float towards positive infinity. *)
Primitive next_up := #float64_next_up.
(** [next_down]: return the next float towards negative infinity. *)
Primitive next_down := #float64_next_down.
(** ** Special values (needed for pretty-printing) *)
Definition infinity := Eval compute in div (of_int63 1) (of_int63 0).
Definition neg_infinity := Eval compute in opp infinity.
Definition nan := Eval compute in div (of_int63 0) (of_int63 0).
Register infinity as num.float.infinity.
Register neg_infinity as num.float.neg_infinity.
Register nan as num.float.nan.
(** ** Other special values *)
Definition one := Eval compute in (of_int63 1).
Definition zero := Eval compute in (of_int63 0).
Definition neg_zero := Eval compute in (-zero)%float.
Definition two := Eval compute in (of_int63 2).
(** ** Predicates and helper functions *)
Definition is_nan f := negb (f =? f)%float.
Definition is_zero f := (f =? zero)%float. (* note: 0 =? -0 with floats *)
Definition is_infinity f := (abs f =? infinity)%float.
Definition is_finite (x : float) := negb (is_nan x || is_infinity x).
(** [get_sign]: return [true] for [-] sign, [false] for [+] sign. *)
Definition get_sign f :=
let f := if is_zero f then (one / f)%float else f in
(f <? zero)%float.
Module Export PrimFloatNotations.
Local Open Scope float_scope.
#[deprecated(since="8.13",note="use infix <? instead")]
Notation "x < y" := (x <? y) (at level 70, no associativity) : float_scope.
#[deprecated(since="8.13",note="use infix <=? instead")]
Notation "x <= y" := (x <=? y) (at level 70, no associativity) : float_scope.
#[deprecated(since="8.13",note="use infix =? instead")]
Notation "x == y" := (x =? y) (at level 70, no associativity) : float_scope.
Export PrimFloatNotationsInternalA.
Export PrimFloatNotationsInternalB.
End PrimFloatNotations.
|
#include <bits/stdc++.h> using namespace std; int b1[] = {0, 0, 1, -1}; int b2[] = {1, -1, 0, 0}; int d1[] = {-1, -1, -1, 0, 0, 1, 1, 1}; int d2[] = {-1, 0, 1, -1, 1, -1, 0, 1}; string st; const int mxn = 1e6; struct tp { int tt, cl, op; } tree[4 * mxn]; void build_tree(int s, int e, int index) { tp obj; obj.tt = obj.cl = obj.op = 0; if (s == e) { obj.cl = (st[s] == ) ); obj.op = (st[s] == ( ); tree[index] = obj; return; } int mid = (s + e) / 2; build_tree(s, mid, 2 * index); build_tree(mid + 1, e, 2 * index + 1); int min_blnc = min(tree[2 * index].op, tree[2 * index + 1].cl); obj.tt = tree[2 * index].tt + tree[2 * index + 1].tt + 2 * min_blnc; obj.cl = tree[2 * index].cl + tree[2 * index + 1].cl - min_blnc; obj.op = tree[2 * index].op + tree[2 * index + 1].op - min_blnc; tree[index] = obj; return; } tp query(int second, int se, int qs, int qe, int index) { tp obj; obj.tt = obj.cl = obj.op = 0; if (second >= qs and se <= qe) { return tree[index]; } if (qe < second || qs > se) return obj; int mid = (second + se) / 2; tp tp1 = query(second, mid, qs, qe, 2 * index); tp tp2 = query(mid + 1, se, qs, qe, 2 * index + 1); int min_blnc = min(tp1.op, tp2.cl); obj.tt = tp1.tt + tp2.tt + 2 * min_blnc; obj.cl = tp1.cl + tp2.cl - min_blnc; obj.op = tp1.op + tp2.op - min_blnc; return obj; } void solve() { cin >> st; int n = st.length(); build_tree(0, n - 1, 1); int q; cin >> q; while (q--) { int x, y; cin >> x >> y; x--, y--; tp res = query(0, n - 1, x, y, 1); cout << res.tt << endl; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t = 1; while (t--) { solve(); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:51:52 04/07/2015
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
module top(
input wire clk,
input wire [5:0] switch,
input wire [7:0]btn_in,
output wire [7:0]anode,
output wire [7:0]segment
);
wire[31:0] displaynum32;
wire[63:0] adderResult;
wire[63:0] minusResult;
wire[63:0] multiResult;
wire[63:0] divResult;
wire[31:0] intRemainder;
wire[63:0] fadderResult;
wire[63:0] fminusResult;
wire[63:0] fmultiResult;
wire[63:0] fdivResult;
wire[63:0] andResult;
wire[63:0] orResult;
wire[63:0] notResult;
wire[63:0] tempA,tempB;
wire[7:0] btn_out;
wire aSF,aCF,aOF,aPF,aZF;
wire mSF,mCF,mOF,mPF,mZF;
reg addMode;
reg minusMode;
reg[31:0] A,B;
reg[63:0] result;
initial begin
A=32'b0;
B=32'b0;
addMode=1'b0;
minusMode=1'b1;
end
pbdebounce p0(clk,btn_in[0],btn_out[0]);//去抖程序
pbdebounce p1(clk,btn_in[1],btn_out[1]);
pbdebounce p2(clk,btn_in[2],btn_out[2]);
pbdebounce p3(clk,btn_in[3],btn_out[3]);
pbdebounce p4(clk,btn_in[4],btn_out[4]);
pbdebounce p5(clk,btn_in[5],btn_out[5]);
pbdebounce p6(clk,btn_in[6],btn_out[6]);
pbdebounce p7(clk,btn_in[7],btn_out[7]);
always @(posedge btn_out[0]) begin //switch[0]高电平是A，低电平是B
if(switch[0])A[ 3: 0]<= A[ 3: 0] + 4'd1;
else B[ 3: 0]<= B[ 3: 0] + 4'd1;
end
always @(posedge btn_out[1]) begin
if(switch[0])A[ 7: 4]<= A[ 7: 4] + 4'd1;
else B[ 7: 4]<= B[ 7: 4] + 4'd1;
end
always @(posedge btn_out[2]) begin
if(switch[0])A[ 11: 8]<= A[ 11: 8] + 4'd1;
else B[ 11: 8]<= B[ 11: 8] + 4'd1;
end
always @(posedge btn_out[3]) begin
if(switch[0])A[ 15: 12]<= A[ 15: 12] + 4'd1;
else B[ 15: 12]<= B[ 15: 12] + 4'd1;
end
always @(posedge btn_out[4]) begin
if(switch[0])A[ 19: 16]<= A[ 19: 16] + 4'd1;
else B[ 19: 16]<= B[ 19: 16] + 4'd1;
end
always @(posedge btn_out[5]) begin
if(switch[0])A[ 23: 20]<= A[ 23: 20] + 4'd1;
else B[ 23: 20]<= B[ 23: 20] + 4'd1;
end
always @(posedge btn_out[6]) begin
if(switch[0])A[ 27: 24]<= A[ 27: 24] + 4'd1;
else B[ 27: 24]<= B[ 27: 24] + 4'd1;
end
always @(posedge btn_out[7]) begin
if(switch[0])A[ 31: 28]<= A[ 31: 28] + 4'd1;
else B[ 31: 28]<= B[ 31: 28] + 4'd1;
end
assign tempA={32'b0,A};
assign tempB={32'b0,B};
AdderAndSubber64 add64(.A(tempA),
.B(tempB),
.mode(addMode),
.result(adderResult),
.SF(aSF),
.CF(aCF),
.OF(aOF),
.PF(aPF),
.ZF(aZF)
);
AdderAndSubber64 minus64(.A(tempA),
.B(tempB),
.mode(minusMode),
.result(minusResult),
.SF(mSF),
.CF(mCF),
.OF(mOF),
.PF(mPF),
.ZF(mZF)
);
IntegerMultiplication multi32(.A(A),
.B(B),
.start(switch[1]),
.clk(clk),
.product(multiResult)
);
IntegerDivision div64(
.Dividend(tempA),
.Divisor(B),
.start(switch[1]),
.clk(clk),
.quotient(divResult),
.remainder(intRemainder)
);
floatadder fadd64(.op1(tempA),
.op2(tempB),
.res(fadderResult)
);
floatsub fsub64(.op1(tempA),
.op2(tempB),
.res(fminusResult)
);
floatingMulti fmulti32(.multiplierA(A),
.multiplierB(B),
.start(switch[1]),
.clk(clk),
.product(fmultiResult)
);
divider fdivider32(.divident(A),
.divisor(B),
.quotient(fdivResult)
);
always @(*) begin
case (switch[5:2])
`Plus:begin
result = adderResult;
end
`Minus:begin
result = minusResult;
end
`Multi:begin
result = multiResult;
end
`Div:begin
result = divResult;
end
`FloatPlus:begin
result = fadderResult;
end
`FloatMinus:begin
result = fminusResult;
end
`FloatMulti:begin
result = fmultiResult;
end
`FloatDiv:begin
result = fdivResult;
end
`AndLogic:begin
result = andResult;
end
`OrLogic:begin
result = orResult;
end
`NotLogic:begin
result = notResult;
end
default:begin
result = 64'b0;
end
endcase
end
assign displaynum32 = (A&{32{switch[0]}}&{32{~switch[1]}})
|(B&{32{~switch[0]}}&{32{~switch[1]}})
|(result[31:0]&{32{switch[1]}});
display32 dis32(
.clk(clk),
.disp_num(displaynum32),
.digit_anode(anode),
.segment(segment)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 500010; int ans[N], arr[N], MAX[N]; long long power_mod(long long x, long long y) { x %= 1000000007; long long res = 1; while (y) { if (y & 1) { res = (res * x) % 1000000007; } y /= 2; x = (x * x) % 1000000007; } return res; } void solve() { int n; cin >> n; vector<pair<int, int>> v(N); for (int i = 1; i <= n; i++) { cin >> v[i].first >> v[i].second; ans[i] = MAX[i] = 1; } sort(v.begin() + 1, v.begin() + n + 1); arr[n + 1] = v[n].second + 1; for (int i = 1; i <= n; i++) { arr[i] = v[i].first; } int ma = 0; for (int i = n; i >= 1; i--) { int up = upper_bound(arr + 1, arr + 2 + n, v[i].second) - arr; int p = ans[i]; ans[i] = max(ans[i], ans[i + 1]); ans[i] = max(ans[i], p + ans[up]); } int res = *max_element(ans, ans + n + 1); cout << res << n ; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int tc = 1; while (tc--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline bool getmin(T *a, const T &b) { if (b < *a) { *a = b; return true; } return false; } template <class T> inline bool getmax(T *a, const T &b) { if (b > *a) { *a = b; return true; } return false; } template <class T> inline void read(T *a) { char c; while (isspace(c = getchar())) { } bool flag = 0; if (c == - ) flag = 1, *a = 0; else *a = c - 48; while (isdigit(c = getchar())) *a = *a * 10 + c - 48; if (flag) *a = -*a; } const int mo = 1000000007; template <class T> T pow(T a, T b, int c = mo) { T res = 1; for (T i = 1; i <= b; i <<= 1, a = 1LL * a * a % c) if (b & i) res = 1LL * res * a % c; return res; } const int inf = 1000000000; const int N = 210000; struct node { int p, nextt, w; } edge[N]; int cnt; int head[N]; void ae(int a, int b, int c) { edge[++cnt].p = b; edge[cnt].nextt = head[a]; edge[cnt].w = c; head[a] = cnt; } queue<int> q; int d[N], tmp[N]; int n, m; int bfs(int u) { static vector<int> v; v.clear(); d[u] = 0; while (!q.empty()) q.pop(); q.push(u); int ans = 0, num = 0; while (!q.empty()) { int u = q.front(); q.pop(); ans += d[u]; v.push_back(u); ++num; for (int k = head[(u)]; k; k = edge[k].nextt) { int v = edge[k].p; if (d[v] != -1 && (d[u] ^ d[v]) != edge[k].w) return inf; else if (d[v] == -1) { d[v] = (d[u] ^ edge[k].w); q.push(v); } } } for (int i = (0); i <= (num - 1); ++i) if (num - ans < ans) d[v[i]] ^= 1; return min(ans, num - ans); } int solve() { for (int i = (1); i <= (n); ++i) d[i] = -1; int ans = 0; for (int i = (1); i <= (n); ++i) if (d[i] == -1) { int x = bfs(i); if (x == inf) return inf; else ans += x; } return ans; } int main() { cin >> n >> m; for (int i = (1); i <= (m); ++i) { int x, y; string s; cin >> x >> y >> s; int z = 0; if (s == R ) z = 1; ae(x, y, z); ae(y, x, z); } int ans = solve(); for (int i = (1); i <= (n); ++i) tmp[i] = d[i]; for (int i = (1); i <= (n); ++i) for (int k = head[(i)]; k; k = edge[k].nextt) edge[k].w ^= 1; int x = solve(); if (x < ans) { ans = x; for (int i = (1); i <= (n); ++i) tmp[i] = d[i]; } if (ans == inf) { cout << -1 << endl; } else { cout << ans << endl; for (int i = (1); i <= (n); ++i) if (tmp[i]) printf( %d , i); cout << endl; } return 0; }
|
`timescale 1ns / 1ps
/*
* Simple Brainfuck CPU in Verilog.
* Copyright (C) 2011 Sergey Gridasov <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module Nexys2Top(
input CLK_IN,
input RESET_IN,
input UART_RX,
output UART_TX
);
wire CLK_MAIN, RESET;
wire [7:0] CIN, COUT;
wire CRDA, CACK, CWR, CRDY;
ClockManager #(
.DELAY(16)
) clock (
.CLK_IN(CLK_IN),
.RESET_IN(RESET_IN),
.CLK_MAIN(CLK_MAIN),
.RESET(RESET)
);
BrainfuckWrapper #(
.IA_WIDTH(12)
) wrap (
.CLK(CLK_MAIN),
.RESET(RESET),
.CIN(CIN),
.COUT(COUT),
.CRDA(CRDA),
.CACK(CACK),
.CWR(CWR),
.CRDY(CRDY)
);
UART uart (
.CLK(CLK_MAIN),
.RESET(RESET),
.TX(UART_TX),
.RX(UART_RX),
.IN(COUT),
.OUT(CIN),
.RDA(CRDA),
.ACK(CACK),
.RDY(CRDY),
.WR(CWR)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int st[610], aim[(300010)], nxt[(300010)], ln; int flow[(300010)], con[(300010)], cost[(300010)]; int inq[610], dis[610]; int g[610], e[610]; int q[610]; int a[610]; int d[610 << 3], tag[610 << 3], dn; int num[610]; int N, source, remit; int ans; int n, m; void in_edge(int x, int y, int f, int c) { aim[ln] = y; nxt[ln] = st[x]; flow[ln] = 0; con[ln] = f; cost[ln] = c; st[x] = ln++; aim[ln] = x; nxt[ln] = st[y]; flow[ln] = con[ln] = 0; cost[ln] = -c; st[y] = ln++; } int calc(int x) { int ret = 0; while (x) ret += (x & 1), x >>= 1; return ret; } int spfa() { int qn = 1; for (int i = 0; i <= remit; i++) dis[i] = (10000000); memset(inq, 0, sizeof(inq)); dis[source] = 0; inq[source] = 1; q[0] = source; for (int p = 0; p != qn;) { int u = q[p]; p++; if (p == 610) p = 0; inq[u] = 0; for (int i = st[u]; i != -1; i = nxt[i]) if (flow[i] < con[i]) { int v = aim[i]; if (dis[u] + cost[i] < dis[v]) { dis[v] = dis[u] + cost[i]; g[v] = u; e[v] = i; if (!inq[v]) { inq[v] = 1; q[qn] = v; ++qn; if (qn == 610) qn = 0; } } } } if (dis[remit] == (10000000)) return 0; int delta = (10000000); for (int i = remit; i != source; i = g[i]) delta = min(delta, con[e[i]] - flow[e[i]]); for (int i = remit; i != source; i = g[i]) { int x = e[i]; flow[x] += delta; flow[x ^ 1] -= delta; } ans += delta * dis[remit]; return 1; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %d , a + i); source = n + n + m; remit = source + 1; memset(st, -1, sizeof(st)); ln = 0; for (int i = 0; i < m; i++) in_edge(source, (n << 1) + i, 1, 0); for (int i = 0; i < n; i++) { in_edge(source, n + i, 1, 0); in_edge(i, remit, 1, 0); } for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) in_edge((n << 1) + i, j, 1, calc(a[j])); } for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) if (a[i] == a[j]) in_edge(n + i, j, 1, 0); else in_edge(n + i, j, 1, calc(a[j])); ans = 0; while (spfa()) ; int dn = 0; for (int i = 0; i < n; i++) { int flag = 0; for (int j = st[i]; j != -1; j = nxt[j]) if (flow[j] < con[j]) { int v = aim[j]; if (v >= (n << 1) && v < source) { tag[dn] = 0; d[dn++] = i; tag[dn] = 1; d[dn++] = v - (n << 1); num[i] = v - (n << 1); } else if (v >= n && v <= (n << 1)) { int p = v - n; if (a[p] != a[i]) { tag[dn] = 0; d[dn++] = i; } tag[dn] = 1; d[dn++] = num[p]; num[i] = num[p]; } } } printf( %d %d n , dn, ans); for (int i = 0; i < dn; i++) if (!tag[i]) { printf( %c=%d n , a + num[d[i]], a[d[i]]); } else { printf( print(%c) n , a + d[i]); } return 0; }
|
#include <bits/stdc++.h> int main() { int n, m, i, j, s; char a[12][11]; scanf( %d%d , &n, &m); for (i = 0; i < n; i++) scanf( %s , a[i]); s = 0; for (i = 0; i < n; i++) for (j = 0; j < m; j++) if (a[i][j] == W ) { if (a[i - 1][j] == P ) { s++; a[i - 1][j] = . ; continue; } if (a[i + 1][j] == P ) { s++; a[i + 1][j] = . ; continue; } if (a[i][j - 1] == P ) { s++; a[i][j - 1] = . ; continue; } if (a[i][j + 1] == P ) { s++; a[i][j + 1] = . ; continue; } } printf( %d , s); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename num_t> inline void addmod(num_t& a, const long long& b, const int& m) { a = (a + b) % m; if (a < 0) a += m; } template <typename num_t> inline void update_max(num_t& a, const num_t& b) { a = max(a, b); } template <typename num_t> inline void update_min(num_t& a, const num_t& b) { a = min(a, b); } template <typename num_t> num_t gcd(num_t lhs, num_t rhs) { return !lhs ? rhs : gcd(rhs % lhs, lhs); } template <typename num_t> num_t pw(num_t n, num_t k, num_t mod) { num_t res = 1; for (; k > 0; k >>= 1) { if (k & 1) res = 1ll * res * n % mod; n = 1ll * n * n % mod; } return res; } const int inf = 1e9 + 7; const int mod = inf; const int MAX_N = 200000 + 7; const long long ll_inf = 9ll * inf * inf; int n, k; array<int, 5> arr[MAX_N]; int pre_calc[32][MAX_N]; int calc(array<int, 5>& arr, int mask) { int sum = 0; for (int i = (0), _b = (k); i < _b; ++i) if (mask & (1 << i)) sum += arr[i]; else sum -= arr[i]; return sum; } void update(int i, array<int, 5>& temp) { arr[i] = temp; for (int mask = (0), _b = (1 << k); mask < _b; ++mask) { pre_calc[mask][i] = calc(temp, mask); } } template <typename num_t> class SegmentTree { public: void init(int l, int r) { tree.resize((r - l + 1) << 1); node_index = 0; build_tree(tree[node_index++], l, r); } void update(int left_index, int right_index) { update_(tree[0], left_index, right_index); } num_t get(int left_index, int right_index) { if (right_index < left_index) return 0; return get(tree[0], left_index, right_index).best_value; } private: struct node { static const num_t nil = 0; node *left_child, *right_child; int left_index, right_index; array<int, 32> min_value; array<int, 32> max_value; int best_value = 0; bool inited = false; void push_down() { for (int i = (0), _b = (1 << k); i < _b; ++i) { min_value[i] = max_value[i] = left_index; } best_value = 0; inited = true; } inline int dist(array<int, 5>& lhs, array<int, 5>& rhs) { int sum = 0; for (int i = (0), _b = (k); i < _b; ++i) sum += abs(lhs[i] - rhs[i]); return sum; } void merge_node() { node &lhs = *left_child, &rhs = *right_child; merge_node(lhs, rhs); } void merge_node(node& lhs, node& rhs) { best_value = max(lhs.best_value, rhs.best_value); inited = true; if (lhs.inited && rhs.inited) { for (int i = (0), _b = (1 << k); i < _b; ++i) { update_max(best_value, dist(arr[lhs.max_value[i]], arr[rhs.min_value[i]])); update_max(best_value, dist(arr[rhs.max_value[i]], arr[lhs.min_value[i]])); if (pre_calc[i][lhs.max_value[i]] <= pre_calc[i][rhs.max_value[i]]) max_value[i] = rhs.max_value[i]; else max_value[i] = lhs.max_value[i]; if (pre_calc[i][lhs.min_value[i]] <= pre_calc[i][rhs.min_value[i]]) min_value[i] = lhs.min_value[i]; else min_value[i] = rhs.min_value[i]; } } else if (lhs.inited) { min_value = lhs.min_value; max_value = lhs.max_value; } else { min_value = rhs.min_value; max_value = rhs.max_value; } } void lazy_update() {} inline void init(int left, int right, node* left_child_, node* right_child_) { left_index = left; right_index = right; left_child = left_child_; right_child = right_child_; } int size() const { return right_index - left_index + 1; } }; vector<node> tree; int node_index = 0; void build_tree(node& root, int left, int right) { if (left == right) { root.init(left, right, nullptr, nullptr); root.push_down(); return; } int mid = (left + right) >> 1, lhs = node_index++, rhs = node_index++; build_tree(tree[lhs], left, mid); build_tree(tree[rhs], mid + 1, right); root.init(left, right, &tree[lhs], &tree[rhs]); root.merge_node(); } void update_(node& root, int u, int v) { if (u > root.right_index || v < root.left_index) return; if (u <= root.left_index && root.right_index <= v) { root.push_down(); } else { root.lazy_update(); update_(*root.left_child, u, v); update_(*root.right_child, u, v); root.merge_node(); } } node get(node& root, int u, int v) { if (u <= root.left_index && root.right_index <= v) return root; if (u > root.right_index || v < root.left_index) return node(); root.lazy_update(); auto lhs = get(*root.left_child, u, v); auto rhs = get(*root.right_child, u, v); node ans; ans.merge_node(lhs, rhs); return ans; } }; SegmentTree<int> segment_tree; void solve() { cin >> n >> k; for (int i = (0), _b = (n); i < _b; ++i) { array<int, 5> cur; for (int j = (0), _b = (k); j < _b; ++j) cin >> cur[j]; update(i, cur); } segment_tree.init(0, n - 1); int q; cin >> q; while (q-- > 0) { int op; cin >> op; if (op == 1) { int u; cin >> u; --u; array<int, 5> cur; for (int j = (0), _b = (k); j < _b; ++j) cin >> cur[j]; update(u, cur); segment_tree.update(u, u); } else { int u, v; cin >> u >> v; cout << segment_tree.get(u - 1, v - 1) << n ; } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); const bool multiple_test = false; int test = 1; if (multiple_test) cin >> test; for (int i = 0; i < test; ++i) { solve(); } }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_p4.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_p4(/*AUTOARG*/
// Outputs
pcx_spc7_grant_bufp4_pa, spc6_pcx_req_bufp4_pq,
spc6_pcx_atom_bufp4_pq, spc7_pcx_req_bufp4_pq,
spc7_pcx_atom_bufp4_pq,
// Inputs
spc6_pcx_req_bufpt_pq_l, spc6_pcx_atom_bufpt_pq_l,
spc7_pcx_req_bufpt_pq_l, spc7_pcx_atom_bufpt_pq_l,
pcx_spc7_grant_bufp3_pa_l
);
output [4:0] pcx_spc7_grant_bufp4_pa;
output [4:0] spc6_pcx_req_bufp4_pq;
output spc6_pcx_atom_bufp4_pq;
output [4:0] spc7_pcx_req_bufp4_pq;
output spc7_pcx_atom_bufp4_pq;
input [4:0] spc6_pcx_req_bufpt_pq_l;
input spc6_pcx_atom_bufpt_pq_l;
input [4:0] spc7_pcx_req_bufpt_pq_l;
input spc7_pcx_atom_bufpt_pq_l;
input [4:0] pcx_spc7_grant_bufp3_pa_l;
assign pcx_spc7_grant_bufp4_pa = ~pcx_spc7_grant_bufp3_pa_l;
assign spc6_pcx_req_bufp4_pq[4:0] = ~spc6_pcx_req_bufpt_pq_l[4:0];
assign spc6_pcx_atom_bufp4_pq = ~spc6_pcx_atom_bufpt_pq_l;
assign spc7_pcx_req_bufp4_pq[4:0] = ~spc7_pcx_req_bufpt_pq_l[4:0];
assign spc7_pcx_atom_bufp4_pq = ~spc7_pcx_atom_bufpt_pq_l;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, x; int cnt[100], b[105][105], sol[105][105], c[105][105], a[105][105]; inline void Mult_Mat(int a[][105], int b[][105]) { int i, j, k, s; for (i = 0; i < x; ++i) for (j = 0; j < x; ++j) { s = 0; for (k = 0; k < x; ++k) s = (1LL * s + 1LL * a[i][k] * b[k][j]) % 1000000007; c[i][j] = s; } for (i = 0; i < x; ++i) for (j = 0; j < x; ++j) a[i][j] = c[i][j]; } inline void Pow_Log(int a[][105], int p) { int i, j; for (i = 0; i < x; ++i) sol[i][i] = 1; while (p) { if (p & 1) { --p; Mult_Mat(sol, a); } p >>= 1; Mult_Mat(a, a); } for (i = 0; i < x; ++i) for (j = 0; j < x; ++j) a[i][j] = sol[i][j]; } int main() { int i, j, B, k, xx; cin.sync_with_stdio(0); cin >> n >> B >> k >> x; for (i = 1; i <= n; ++i) { cin >> xx; ++cnt[xx]; } for (i = 0; i < x; ++i) for (j = 0; j < 10; ++j) b[i][(i * 10 + j) % x] = (b[i][(i * 10 + j) % x] + cnt[j]) % 1000000007; Pow_Log(b, B); a[1][0] = 1; Mult_Mat(a, b); cout << a[1][k] << n ; return 0; }
|
#include <bits/stdc++.h> const int N = 1000001; using namespace std; char sub[N], s[N], l[N]; int a[10]; int main() { scanf( %s , s); int i, j, len1, len2; len1 = strlen(s); for (i = 0; i < len1; i++) a[s[i] - 0 ]++; scanf( %s , sub); len2 = strlen(sub); for (i = 0; i < len2; i++) a[sub[i] - 0 ]--; int lt = 1, rt = 1000000, mid, t, w; while (lt <= rt) { mid = (lt + rt) >> 1; t = mid; w = 0; while (t > 0) { w++; t /= 10; } if (mid + w == len1) break; else if (mid + w < len1) lt = mid + 1; else rt = mid - 1; } t = mid; while (t > 0) { a[t % 10]--; t /= 10; } bool ok = true; if (a[0] > 0 || sub[0] == 0 ) { ok = false; for (i = 1; i < 10; i++) if (a[i] > 0) break; if (i < 10) { ok = true; if (i < sub[0] - 0 ) { a[i]--; printf( %d , i); } else if (i > sub[0] - 0 ) { if (sub[0] != 0 ) { printf( %s , sub); for (i = 0; i < 10; i++) for (j = 1; j <= a[i]; j++) printf( %d , i); return 0; } printf( %d , i); a[i]--; } else { int p = 0, q; a[i]--; l[p++] = (char)(i + 0 ); for (i = 0; i < 10; i++) for (j = 1; j <= a[i]; j++) l[p++] = (char)(i + 0 ); q = p; if (p < len2) { for (i = 0; p < len2; i++) l[p++] = sub[i]; } for (i = 0; i < len2; i++) if (l[i] != sub[i]) break; if (i < len2 && sub[i] < l[i]) { l[q] = 0 ; sort(l, l + q); printf( %s%s , sub, l); return 0; } printf( %c , sub[0]); } } } int p = 0, q; for (i = 0; i < 10; i++) for (j = 1; j <= a[i]; j++) l[p++] = (char)(i + 0 ); l[p] = 0 ; if (!ok) { printf( %s%s , sub, l); return 0; } if (p == 0) { printf( %s , sub); return 0; } for (i = 0; i < p; i++) { if (l[i] < sub[0]) { printf( %c , l[i]); continue; } if (l[i] > sub[0]) { printf( %s , sub); printf( %s , l + i); return 0; } for (j = 1; j < len2; j++) if (sub[j] != sub[0]) break; if (j == len2 || sub[j] < sub[0]) { printf( %s , sub); printf( %s , l + i); return 0; } else { for (; l[i] == sub[0]; i++) printf( %c , l[i]); printf( %s , sub); printf( %s , l + i); return 0; } } printf( %s , sub); return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_p0_even.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name:
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cpx_buf_p0_even(/*AUTOARG*/
// Outputs
arbcp0_cpxdp_grant_ca, arbcp0_cpxdp_q0_hold_ca_l,
arbcp0_cpxdp_qsel0_ca, arbcp0_cpxdp_qsel1_ca_l,
arbcp0_cpxdp_shift_cx, arbcp2_cpxdp_grant_ca,
arbcp2_cpxdp_q0_hold_ca_l, arbcp2_cpxdp_qsel0_ca,
arbcp2_cpxdp_qsel1_ca_l, arbcp2_cpxdp_shift_cx,
arbcp4_cpxdp_grant_ca, arbcp4_cpxdp_q0_hold_ca_l,
arbcp4_cpxdp_qsel0_ca, arbcp4_cpxdp_qsel1_ca_l,
arbcp4_cpxdp_shift_cx, arbcp6_cpxdp_grant_ca,
arbcp6_cpxdp_q0_hold_ca_l, arbcp6_cpxdp_qsel0_ca,
arbcp6_cpxdp_qsel1_ca_l, arbcp6_cpxdp_shift_cx,
// Inputs
arbcp0_cpxdp_grant_bufp1_ca_l, arbcp0_cpxdp_q0_hold_bufp1_ca,
arbcp0_cpxdp_qsel0_bufp1_ca_l, arbcp0_cpxdp_qsel1_bufp1_ca,
arbcp0_cpxdp_shift_bufp1_cx_l, arbcp2_cpxdp_grant_bufp1_ca_l,
arbcp2_cpxdp_q0_hold_bufp1_ca, arbcp2_cpxdp_qsel0_bufp1_ca_l,
arbcp2_cpxdp_qsel1_bufp1_ca, arbcp2_cpxdp_shift_bufp1_cx_l,
arbcp4_cpxdp_grant_bufp1_ca_l, arbcp4_cpxdp_q0_hold_bufp1_ca,
arbcp4_cpxdp_qsel0_bufp1_ca_l, arbcp4_cpxdp_qsel1_bufp1_ca,
arbcp4_cpxdp_shift_bufp1_cx_l, arbcp6_cpxdp_grant_bufp1_ca_l,
arbcp6_cpxdp_q0_hold_bufp1_ca, arbcp6_cpxdp_qsel0_bufp1_ca_l,
arbcp6_cpxdp_qsel1_bufp1_ca, arbcp6_cpxdp_shift_bufp1_cx_l
);
output arbcp0_cpxdp_grant_ca;
output arbcp0_cpxdp_q0_hold_ca_l;
output arbcp0_cpxdp_qsel0_ca;
output arbcp0_cpxdp_qsel1_ca_l;
output arbcp0_cpxdp_shift_cx;
output arbcp2_cpxdp_grant_ca;
output arbcp2_cpxdp_q0_hold_ca_l;
output arbcp2_cpxdp_qsel0_ca;
output arbcp2_cpxdp_qsel1_ca_l;
output arbcp2_cpxdp_shift_cx;
output arbcp4_cpxdp_grant_ca;
output arbcp4_cpxdp_q0_hold_ca_l;
output arbcp4_cpxdp_qsel0_ca;
output arbcp4_cpxdp_qsel1_ca_l;
output arbcp4_cpxdp_shift_cx;
output arbcp6_cpxdp_grant_ca;
output arbcp6_cpxdp_q0_hold_ca_l;
output arbcp6_cpxdp_qsel0_ca;
output arbcp6_cpxdp_qsel1_ca_l;
output arbcp6_cpxdp_shift_cx;
input arbcp0_cpxdp_grant_bufp1_ca_l;
input arbcp0_cpxdp_q0_hold_bufp1_ca;
input arbcp0_cpxdp_qsel0_bufp1_ca_l;
input arbcp0_cpxdp_qsel1_bufp1_ca;
input arbcp0_cpxdp_shift_bufp1_cx_l;
input arbcp2_cpxdp_grant_bufp1_ca_l;
input arbcp2_cpxdp_q0_hold_bufp1_ca;
input arbcp2_cpxdp_qsel0_bufp1_ca_l;
input arbcp2_cpxdp_qsel1_bufp1_ca;
input arbcp2_cpxdp_shift_bufp1_cx_l;
input arbcp4_cpxdp_grant_bufp1_ca_l;
input arbcp4_cpxdp_q0_hold_bufp1_ca;
input arbcp4_cpxdp_qsel0_bufp1_ca_l;
input arbcp4_cpxdp_qsel1_bufp1_ca;
input arbcp4_cpxdp_shift_bufp1_cx_l;
input arbcp6_cpxdp_grant_bufp1_ca_l;
input arbcp6_cpxdp_q0_hold_bufp1_ca;
input arbcp6_cpxdp_qsel0_bufp1_ca_l;
input arbcp6_cpxdp_qsel1_bufp1_ca;
input arbcp6_cpxdp_shift_bufp1_cx_l;
assign arbcp0_cpxdp_grant_ca = ~ arbcp0_cpxdp_grant_bufp1_ca_l;
assign arbcp0_cpxdp_q0_hold_ca_l = ~ arbcp0_cpxdp_q0_hold_bufp1_ca;
assign arbcp0_cpxdp_qsel0_ca = ~ arbcp0_cpxdp_qsel0_bufp1_ca_l;
assign arbcp0_cpxdp_qsel1_ca_l = ~ arbcp0_cpxdp_qsel1_bufp1_ca;
assign arbcp0_cpxdp_shift_cx = ~ arbcp0_cpxdp_shift_bufp1_cx_l;
assign arbcp2_cpxdp_grant_ca = ~ arbcp2_cpxdp_grant_bufp1_ca_l;
assign arbcp2_cpxdp_q0_hold_ca_l = ~ arbcp2_cpxdp_q0_hold_bufp1_ca;
assign arbcp2_cpxdp_qsel0_ca = ~ arbcp2_cpxdp_qsel0_bufp1_ca_l;
assign arbcp2_cpxdp_qsel1_ca_l = ~ arbcp2_cpxdp_qsel1_bufp1_ca;
assign arbcp2_cpxdp_shift_cx = ~ arbcp2_cpxdp_shift_bufp1_cx_l;
assign arbcp4_cpxdp_grant_ca = ~ arbcp4_cpxdp_grant_bufp1_ca_l;
assign arbcp4_cpxdp_q0_hold_ca_l = ~ arbcp4_cpxdp_q0_hold_bufp1_ca;
assign arbcp4_cpxdp_qsel0_ca = ~ arbcp4_cpxdp_qsel0_bufp1_ca_l;
assign arbcp4_cpxdp_qsel1_ca_l = ~ arbcp4_cpxdp_qsel1_bufp1_ca;
assign arbcp4_cpxdp_shift_cx = ~ arbcp4_cpxdp_shift_bufp1_cx_l;
assign arbcp6_cpxdp_grant_ca = ~ arbcp6_cpxdp_grant_bufp1_ca_l;
assign arbcp6_cpxdp_q0_hold_ca_l = ~ arbcp6_cpxdp_q0_hold_bufp1_ca;
assign arbcp6_cpxdp_qsel0_ca = ~ arbcp6_cpxdp_qsel0_bufp1_ca_l;
assign arbcp6_cpxdp_qsel1_ca_l = ~ arbcp6_cpxdp_qsel1_bufp1_ca;
assign arbcp6_cpxdp_shift_cx = ~ arbcp6_cpxdp_shift_bufp1_cx_l;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; vector<long long> G[500005]; long long t1, d1, t2, d2; long long dis1[500005], dis2[500005]; long long inp[500005], in[500005]; stringstream ss; void dfs1(long long u, long long fa, long long d) { if (d > d1) { d1 = d; t1 = u; } for (long long i = 0; i < G[u].size(); i++) { if (G[u][i] == fa) continue; dfs1(G[u][i], u, d + 1); } } void dfs2(long long u, long long fa, long long d) { if (d > d2) { d2 = d; t2 = u; } dis1[u] = d; for (long long i = 0; i < G[u].size(); i++) { if (G[u][i] == fa) continue; dfs2(G[u][i], u, d + 1); } } void dfs3(long long u, long long fa, long long d) { dis2[u] = d; for (long long i = 0; i < G[u].size(); i++) { if (G[u][i] == fa) continue; dfs3(G[u][i], u, d + 1); } } void findpath(long long u, long long fa, long long t) { inp[u] = true; if (u == t) { memcpy(in, inp, sizeof inp); return; } for (long long i = 0; i < G[u].size(); i++) { if (G[u][i] == fa) continue; findpath(G[u][i], u, t); } inp[u] = false; } long long ans; bool del[500005]; long long deg[500005]; void dfs4(long long u, long long fa) { del[u] = true; if ((dis1[u] > dis2[u] || del[t2]) && !del[t1]) { ans += dis1[u]; ss << t1 << << u << << u << endl; } else if (!del[t2]) { ans += dis2[u]; ss << t2 << << u << << u << endl; } for (long long i = 0; i < G[u].size(); i++) { if (G[u][i] == fa) continue; if (in[G[u][i]]) dfs4(G[u][i], u); } } signed main() { cin >> n; for (long long i = 1; i <= n - 1; i++) { long long u, v; cin >> u >> v; G[u].push_back(v); G[v].push_back(u); deg[u]++; deg[v]++; } dfs1(1, 0, 0); dfs2(t1, 0, 0); dfs3(t2, 0, 0); findpath(t1, 0, t2); queue<long long> Q; for (long long i = 1; i <= n; i++) { if (deg[i] == 1) Q.push(i); } while (Q.size()) { long long i = Q.front(); Q.pop(); if (in[i]) continue; if (del[i]) continue; del[i] = true; if (dis1[i] > dis2[i]) { ans += dis1[i]; ss << t1 << << i << << i << endl; } else { ans += dis2[i]; ss << t2 << << i << << i << endl; } for (long long j = 0; j < G[i].size(); j++) { deg[G[i][j]]--; if (deg[G[i][j]] == 1) Q.push(G[i][j]); } } dfs4(t1, 0); cout << ans << endl; cout << ss.str() << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int q; cin >> q; while (q--) { string s; cin >> s; vector<char> v[2]; for (int i = 0; i < s.size(); i++) v[s[i] % 2].push_back(s[i]); int p1, p2; for (p1 = 0, p2 = 0; p1 < v[0].size() && p2 < v[1].size();) { if (v[0][p1] < v[1][p2]) cout << v[0][p1++]; else cout << v[1][p2++]; } while (p1 < v[0].size()) cout << v[0][p1++]; while (p2 < v[1].size()) cout << v[1][p2++]; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int dx[] = {1, 0, -1, 0, -1, 1, -1, 1}; int dy[] = {0, 1, 0, -1, -1, 1, 1, -1}; const double eps = 1e-6; const int N = 1e9; void moha() {} bool vis[1505][1505]; int comp[1505][1505][2]; char x[1505][1505]; int n, m; int row(int x) { return (x + n * 1500) % n; } int col(int y) { return (y + m * 1500) % m; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; int a, b; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> x[i][j]; if (x[i][j] == S ) { a = i; b = j; } } queue<pair<int, int> > q; q.push({a, b}); vis[a][b] = 1; comp[row(a)][col(b)][0] = a; comp[row(a)][col(b)][1] = b; while (!q.empty()) { pair<int, int> p = q.front(); q.pop(); for (int i = 0; i < 4; i++) { int xx = p.first + dx[i]; int yy = p.second + dy[i]; if (x[row(xx)][col(yy)] == # ) continue; if (vis[row(xx)][col(yy)]) { if (comp[row(xx)][col(yy)][0] != xx || comp[row(xx)][col(yy)][1] != yy) { cout << Yes << endl; return 0; } continue; } q.push({xx, yy}); vis[row(xx)][col(yy)] = 1; comp[row(xx)][col(yy)][0] = xx; comp[row(xx)][col(yy)][1] = yy; } } cout << No << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX4_1_V
`define SKY130_FD_SC_HS__MUX4_1_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux4_1 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux4_1 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX4_1_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:53:58 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_rst_ps7_0_100M_0_stub.v
// Design : design_1_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; map<pair<int, int>, bool> fuck; int n, m; char s[5]; int x, y; long long ans; int dx, dy; int main() { scanf( %d%d , &n, &m); scanf( %d%d , &x, &y); scanf( %s , s + 1); if (s[1] == U ) dx = -1; else dx = 1; if (s[2] == L ) dy = -1; else dy = 1; int fis = 0; int test = 1000000; while (test--) { pair<int, int> now = pair<int, int>(x, y); if (!fuck[now]) { fuck[now] = 1; fis++; } if (fis == n + m - 2) { cout << ans + 1; return 0; } int xl, yl, l; int ex, ey; if (dx == -1) xl = x - 1; else xl = n - x; if (dy == -1) yl = y - 1; else yl = m - y; if (xl < yl) { ex = -dx; ey = dy; l = xl; } else { if (xl > yl) { ey = -dy; ex = dx; l = yl; } else { ex = -dx; ey = -dy; l = yl; } } x += dx * l; y += dy * l; ans += 1ll * l; dx = ex; dy = ey; } printf( -1 n ); return 0; }
|
module main;
reg [7:0] a;
reg [2:0] adr, w_adr;
reg rst, clk, ae, wr;
(* ivl_synthesis_on *)
always @(posedge clk)
if (rst) begin
a <= 8'b00000000;
adr <= 3'b000;
end else if (ae) begin
adr <= w_adr;
end else if (wr) begin
adr <= adr + 1;
a[adr] <= 1;
end
(* ivl_synthesis_off *)
initial begin
clk = 0;
wr = 0;
ae = 0;
rst = 1;
#1 clk = 1;
#1 clk = 0;
if (a !== 8'b0000_0000 || adr !== 3'b000) begin
$display("FAILED - reset - a=%b, adr=%b", a, adr);
$finish;
end
rst = 0;
#1 clk = 1;
#1 clk = 0;
if (a !== 8'b0000_0000 || adr !== 3'b000) begin
$display("FAILED - pause - a=%b, adr=%b", a, adr);
$finish;
end
wr = 1;
#1 clk = 1;
#1 clk = 0;
if (a !== 8'b0000_0001 || adr !== 3'b001) begin
$display("FAILED - wr 1 - a=%b, adr=%b", a, adr);
$finish;
end
#1 clk = 1;
#1 clk = 0;
if (a !== 8'b0000_0011 || adr !== 3'b010) begin
$display("FAILED - wr 2 - a=%b, adr=%b", a, adr);
$finish;
end
ae = 1;
w_adr = 4;
#1 clk = 1;
#1 clk = 0;
if (a !== 8'b0000_0011 || adr !== 3'b100) begin
$display("FAILED - ae - a=%b, adr=%b", a, adr);
$finish;
end
ae = 0;
#1 clk = 1;
#1 clk = 0;
if (a !== 8'b0001_0011 || adr !== 3'b101) begin
$display("FAILED - ae - a=%b, adr=%b", a, adr);
$finish;
end
$display("PASSED");
end
endmodule // main
|
module tvout (
input pixel_clk,
input rst,
output reg [8:0] cntHS,
output reg [8:0] cntVS,
output wire vbl,
output wire hsync,
output wire out_sync
);
wire screen_sync = (cntHS < 37) ? 1'b0 : 1'b1;
wire in_vbl = ((cntVS >= 5) & (cntVS < 309)) ? 1'b0 : 1'b1;
reg vbl_sync;
reg interlace;
always @ (posedge pixel_clk) begin
if (rst) begin
cntHS <= 0;
cntVS <= 0;
interlace <= 0;
end else begin
if (cntHS == 511) begin
cntHS <= 0;
if ((cntVS == 312) || ((cntVS == 311) && interlace)) begin
cntVS <= 0;
interlace <= ~interlace;
end else cntVS <= cntVS + 1'b1;
end else cntHS <= cntHS + 1'b1;
if (cntVS < 2) begin
if ((cntHS < 240) || ((cntHS >= 256) && (cntHS < 496))) vbl_sync <= 0;
else vbl_sync <= 1;
end else if (cntVS == 2) begin
if ((cntHS < 240) || ((cntHS >= 256) && (cntHS < 272))) vbl_sync <= 0;
else vbl_sync <= 1;
end else if (cntVS == 312) begin
if ((cntHS < 16) || ((cntHS >= 256) && (cntHS < 496))) vbl_sync <= 0;
else vbl_sync <= 1;
end else begin
if ((cntHS < 16) || ((cntHS >= 256) && (cntHS < 272))) vbl_sync <= 0;
else vbl_sync <= 1;
end
end
end
assign vbl = in_vbl;
assign hsync = ~screen_sync;
assign out_sync = in_vbl?vbl_sync:screen_sync;
endmodule
|
#include <bits/stdc++.h> using namespace std; string str; bool judge(char c) { return (c == _ || islower(c) || isdigit(c) || isupper(c)); } int main() { int cnt = 0, count = 0, type = 0, len; cin >> str; type = 0; len = str.length(); for (int i = 0; i < len; i++) { char c = str[i]; if (c == @ ) { if (type == 1) { cout << NO << endl; return 0; } type = 1; if (cnt < 1 || cnt > 16) { cout << NO << endl; return 0; }; cnt = 0; } else if (c == / ) { if (type == 2) { cout << NO << endl; return 0; } type = 2; if (cnt < 1 || cnt > 16) { cout << NO << endl; return 0; } if (count < 1 || count > 32) { cout << NO << endl; return 0; } cnt = 0; } else if (c == . ) { if (type != 1) { cout << NO << endl; return 0; } if (cnt < 1 || cnt > 16) { cout << NO << endl; return 0; } cnt = 0; } else if (c > 127 || c < 33) { cout << NO << endl; return 0; } else if (type == 0) { if (judge(c)) { cnt++; continue; } else { cout << NO << endl; return 0; } } else if (type == 1) { if (judge(c)) { cnt++; count++; continue; } else { cout << NO << endl; return 0; } } else if (type == 2) { if (judge(c)) { cnt++; continue; } else { cout << NO << endl; return 0; } } } if (cnt < 0 || cnt > 16) { cout << NO << endl; return 0; } if (type >= 1 && cnt > 0) { cout << YES << endl; return 0; } else { cout << NO << endl; return 0; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int down[N], sz[N], up[N], n; vector<pair<int, bool> > adj[N]; void dfs(int s, int p) { sz[s] = 1; for (auto it : adj[s]) { if (it.first != p) { dfs(it.first, s); sz[s] += sz[it.first]; if (it.second) down[s] += sz[it.first]; else down[s] += down[it.first]; } } } void dfs2(int s, int p) { for (auto it : adj[s]) { if (it.first != p) { if (it.second) up[it.first] = n - sz[it.first]; else up[it.first] = down[s] - down[it.first] + up[s]; dfs2(it.first, s); } } } int main() { int i; scanf( %d , &n); for (i = 0; i < n - 1; i++) { int a, b, c, te; bool flag = true; scanf( %d%d%d , &a, &b, &c); while (c > 0) { if (c % 10 == 4 || c % 10 == 7) ; else flag = false; c /= 10; } adj[a - 1].push_back(make_pair(b - 1, flag)); adj[b - 1].push_back(make_pair(a - 1, flag)); } long long ans = 0; dfs(0, -1); dfs2(0, -1); for (i = 0; i < n; i++) { long long temp = up[i] + down[i]; ans += temp * (temp - 1); } cout << ans; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : Version : 2014.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 16-Bit Shift Register Look-Up-Table with Clock Enable
// /___/ /\ Filename : SRL16E.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`celldefine
module SRL16E #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [15:0] INIT = 16'h0000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output Q,
input A0,
input A1,
input A2,
input A3,
input CE,
input CLK,
input D
);
wire IS_CLK_INVERTED_BIN;
wire [3:0] A_in;
wire CE_in;
wire CLK_in;
wire D_in;
`ifdef XIL_TIMING
wire CE_dly;
wire CLK_dly;
wire D_dly;
assign CE_in = CE_dly;
assign CLK_in = IS_CLK_INVERTED_BIN ^ CLK_dly;
assign D_in = D_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_ce_clk_en_p;
wire sh_ce_clk_en_n;
`else
assign CE_in = CE ;
assign CLK_in = IS_CLK_INVERTED_BIN ^ CLK;
assign D_in = D ;
`endif
assign A_in = {A3, A2, A1, A0};
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED;
reg [15:0] data;
reg first_time = 1'b1;
initial
begin
assign data = INIT;
first_time <= #100000 1'b0;
while ((CLK_in !== 1'b0) && (first_time == 1'b1)) #1000;
deassign data;
end
always @(posedge CLK_in)
if (CE_in == 1'b1)
data[15:0] <= #100 {data[14:0], D_in};
assign Q = data[A_in];
`ifdef XIL_TIMING
always @(notifier)
data[0] = 1'bx;
assign sh_clk_en_p = ~IS_CLK_INVERTED_BIN;
assign sh_clk_en_n = IS_CLK_INVERTED_BIN;
assign sh_ce_clk_en_p = CE_in && ~IS_CLK_INVERTED_BIN;
assign sh_ce_clk_en_n = CE_in && IS_CLK_INVERTED_BIN;
specify
(A0 => Q) = (0:0:0, 0:0:0);
(A1 => Q) = (0:0:0, 0:0:0);
(A2 => Q) = (0:0:0, 0:0:0);
(A3 => Q) = (0:0:0, 0:0:0);
(CLK => Q) = (0:0:0, 0:0:0);
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly);
$setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,D_dly);
$setuphold (negedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,CLK_dly,CE_dly);
$setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_n,sh_ce_clk_en_n,CLK_dly,D_dly);
$setuphold (posedge CLK, negedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly);
$setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,D_dly);
$setuphold (posedge CLK, posedge CE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,CLK_dly,CE_dly);
$setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier,sh_ce_clk_en_p,sh_ce_clk_en_p,CLK_dly,D_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
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#include <bits/stdc++.h> const int N = 2000010; using namespace std; char s[N], t[N]; int main() { int n; scanf( %d , &n); scanf( %s%s , s, t); int a[5] = {}; for (int i = 0; i < 2 * n; i++) { a[((s[i] == 1 ) << 1) | (t[i] == 1 )]++; } int s0 = 0, s1 = 0; int t = 0; while (a[3]) { if (t == 0) s0++; else s1++; a[3]--; t ^= 1; } while (a[2]) { if (t == 0) s0++, a[2]--; else a[2]--; t ^= 1; } while (a[1]) { if (t == 1) s1++, a[1]--; else a[1]--; t ^= 1; } if (s0 > s1) puts( First ); else if (s0 == s1) puts( Draw ); else puts( Second ); return 0; }
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#include <bits/stdc++.h> using namespace std; int s, t, n; string str; bool flag = true, flag1 = true; int main() { scanf( %d , &n); cin >> str; for (int i = 0; i < n; i++) { if (str[i] == R && flag) { s = i; flag = false; } if (str[i] == L && flag1) { t = i; flag1 = false; } } if (flag1) { for (int i = 0; i < n; i++) if (str[i] == R ) t = i; printf( %d %d , s + 1, t + 2); return 0; } if (flag) { for (int i = 0; i < n; i++) if (str[i] == L ) s = i; printf( %d %d , s + 1, t); return 0; } printf( %d %d , s + 1, t); return 0; }
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// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Tue May 13 22:55:34 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/lab_6/ip/clk_base/clk_base_stub.v
// Design : clk_base
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_base(clk_raw, clk_250MHz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_raw,clk_250MHz,locked" */;
input clk_raw;
output clk_250MHz;
output locked;
endmodule
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#include <bits/stdc++.h> using namespace std; const int maxn = 105; int n; int a[maxn]; int p; double dp[maxn][maxn]; double release(int x) { double res = 1; for (register double i = x + 1; i <= n; i++) { res *= (i - x); res /= i; } return res; } signed main() { scanf( %d , &n); for (register int i = 1; i <= n; i++) { scanf( %d , &a[i]); } scanf( %d , &p); dp[0][0] = 1; for (register int i = 1; i <= n; i++) { for (register int j = n - 1; j >= 0; j--) { for (register int k = p - a[i]; k >= 0; k--) { dp[j + 1][k + a[i]] += dp[j][k]; } } } double ans = 0; for (register int i = 1; i <= n; i++) { for (register int j = 0; j <= p; j++) { if (dp[i][j]) { ans += dp[i][j] * release(i); } } } printf( %.10lf n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int Nmax = 1e6 + 7; int n; string s; int dp[Nmax]; vector<int> v; int ans, ans1, ans2; inline int get(string s) { int cnt = 0; int mx = 4 * n; ans = 0; for (int i = 0; i < n; i++) { if (s[i] == ) ) cnt--; else cnt++; if (cnt < mx) { mx = cnt; ans = i; } } int pos = ans; if (cnt != 0) return 0; s = s + s; dp[0] = 0; ans = 0; ans1 = 1, ans2 = 1; for (int i = pos + 1, j = 0; j < n; j++, i++) { if (s[i] == ( ) dp[j + 1] = dp[j] + 1; else dp[j + 1] = dp[j] - 1; } for (int i = 0; i <= n; i++) { if (!dp[i]) { v.push_back(i); ans++; } } ans--; int zero = ans; int sum = v.size(); for (int i = 0; i < sum - 1; i++) { int j = i + 1; int cnt = 0; for (int k = v[i]; k <= v[j]; k++) { if (dp[k] == 1) cnt++; } if (cnt > ans) { ans = cnt; ans1 = v[i] + 1, ans2 = v[j]; } } v.clear(); for (int i = 1; i <= n; i++) if (dp[i] == 1) v.push_back(i); sum = v.size(); for (int i = 0; i < sum - 1; i++) { int j = i + 1; int cnt = 0; for (int k = v[i]; k <= v[j]; k++) { if (dp[k] == 2) cnt++; if (dp[k] < 1) { cnt = 0; break; } } if (cnt + zero > ans) { ans = cnt + zero; ans1 = v[i] + 1, ans2 = v[j]; } } pos++; ans1 += pos, ans2 += pos; if (ans1 > n) ans1 %= n; if (ans2 > n) ans2 %= n; cout << ans << endl; cout << ans1 << << ans2 << endl; return ans; } int main() { cin >> n; cin >> s; int ans = 0, ans1 = 1, ans2 = 1; if (get(s) == 0) { cout << ans << endl; cout << ans1 << << ans2 << endl; return 0; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2I_PP_SYMBOL_V
`define SKY130_FD_SC_MS__MUX2I_PP_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux2i (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output Y ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2I_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__O2BB2AI_FUNCTIONAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> #define inf 0x3f3f3f3f #define IOS ios_base::sync_with_stdio(0); cin.tie(0); #define rep(i, a, n) for(int i = a; i <= n; ++ i) #define per(i, a, n) for(int i = n; i >= a; -- i) //#define ONLINE_JUDGE using namespace std; typedef long long ll; const int mod=1e9+7; template<typename T>void write(T x) { if(x<0) { putchar( - ); x=-x; } if(x>9) { write(x/10); } putchar(x%10+ 0 ); } template<typename T> void read(T &x) { x = 0;char ch = getchar();ll f = 1; while(!isdigit(ch)){if(ch == - )f*=-1;ch=getchar();} while(isdigit(ch)){x = x*10+ch-48;ch=getchar();}x*=f; } int gcd(int a,int b){return b==0?a:gcd(b,a%b);} int lcm(int a,int b){return a/gcd(a,b)*b;}; ll ksm(ll a,ll n){ ll ans=1; while(n){ if(n&1) ans=(ans*a)%mod; a=a*a%mod; n>>=1; } return ans%mod; } //============================================================== #define int ll const int maxn=1e3+100; int t,n,k,a[maxn]; ll cnt[maxn]; map<int,int>need; ll f[maxn],finv[maxn]; void init(){ f[0]=1; rep(i,1,maxn-1)f[i]=f[i-1]*i%mod; finv[maxn-1]=ksm(f[maxn-1],mod-2); per(i,0,maxn-2){ finv[i]=(finv[i+1]*(i+1))%mod; } } ll C(ll n,ll k){ return (f[n]*finv[n-k]%mod*finv[k]%mod)%mod; } signed main() { #ifndef ONLINE_JUDGE freopen( in.txt , r ,stdin); freopen( out.txt , w ,stdout); #endif //clock_t c1 = clock(); //=========================================================== read(t); init(); while(t--){ need.clear(); read(n),read(k); rep(i,1,n) read(a[i]); sort(a+1,a+1+n); int mx=0; ll ans=1; per(i,n-k+1,n)mx+=a[i],need[a[i]]++; rep(i,1,n)cnt[a[i]]++; for(auto x:need){ int now=x.first; int num=x.second; ans=(ans*C(cnt[now],num))%mod; } write(ans%mod),putchar( n ); fill(cnt,cnt+n+1,0); } //=========================================================== //std::cerr << Time: << clock() - c1 << ms << std::endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, a[100010], mx1 = -100010, mx2 = -100010 - 10, ans = 1, cnt[100010]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) { if (a[i] > mx1) { mx2 = mx1; mx1 = a[i]; cnt[a[i]]--; } else if (a[i] > mx2) { mx2 = a[i]; cnt[mx1]++; } } for (int i = 1; i <= n; i++) if (cnt[i] > cnt[ans]) ans = i; cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m; char a[55][55]; int dx[4] = {1, -1, 0, 0}, dy[4] = {0, 0, 1, -1}; vector<pair<int, int> > G[2555]; int vis[2555]; int bfs(int i, int j) { memset(vis, -1, sizeof vis); deque<pair<int, int> > q; q.push_front(make_pair(i * m + j, 0)); int mx = 0; while (!q.empty()) { pair<int, int> cur = q.front(); q.pop_front(); int u = cur.first, w = cur.second; vis[u] = w; if (a[u / m][u % m] == B ) mx = w; for (int k = 0; k < (int)G[u].size(); k++) { int v = G[u][k].first, w2 = G[u][k].second; if (vis[v] == -1) { vis[v] = w + w2; if (w2 == 0) q.push_front(make_pair(v, w)); else q.push_back(make_pair(v, w + w2)); } } } return mx; } int main() { bool ok = 0; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %s , a[i]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (a[i][j] == B ) ok = 1; if (!ok) { printf( 0 n ); return 0; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { for (int k = 0; k < 4; k++) { int newI = i + dx[k], newJ = j + dy[k]; if (newI < 0 || newJ < 0 || newI >= n || newJ >= m) continue; if (a[i][j] == a[newI][newJ]) G[i * m + j].push_back(make_pair(newI * m + newJ, 0)); else G[i * m + j].push_back(make_pair(newI * m + newJ, 1)); } } int mn = n * m + 1; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { mn = min(mn, bfs(i, j)); } printf( %d n , mn + 1); return 0; }
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#include <bits/stdc++.h> using namespace std; const long double PI = 3.14159265358979323846264338327950288419716939937510582097494459230; template <class T> int getbit(T s, int i) { return (s >> 1) & 1; } template <class T> T onbit(T s, int i) { return s | (T(1) << i); } template <class T> T offbit(T s, int i) { return s & (~(T(1) << i)); } template <class T> int cntbit(T s) { return __builtin_popcount(s); } long long N; long long modPow(long long a, long long b) { if (b == 0) return 1; if (b == 1) return a; long long tmp = modPow(a, b / 2); if (b % 2 == 0) return ((tmp * tmp) % 1000000007LL); return ((((tmp * tmp) % 1000000007LL) * a) % 1000000007LL); } void VarInput() { cin >> N; } void ProSolve() { long long ans = modPow(27, N) - modPow(7, N); while (ans < 0) ans += 1000000007LL; cout << ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); VarInput(); ProSolve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int par[100005], val[100005]; int lefm[100005], rim[100005]; int root = 0; vector<vector<int> > adjl; int n; void pre(int node) { if (adjl[node].size() == 0) { lefm[node] = val[node]; rim[node] = val[node]; return; } for (int i = (0); i < (adjl[node].size()); ++i) { pre(adjl[node][i]); if (val[adjl[node][i]] < val[node]) lefm[node] = lefm[adjl[node][i]]; else rim[node] = rim[adjl[node][i]]; } } double res[100005]; pair<int, int> qu[100005]; void query(int node, int left, int right, long long cost, int dep) { if (adjl[node].size() == 0) { for (int i = (left); i < (right); ++i) res[qu[i].second] += cost * 1. / dep; return; } int ind = lower_bound(qu + left, qu + right, make_pair(val[node], 0)) - qu; if (ind > left && adjl[node].size() == 2) query(adjl[node][0], left, ind, cost + lefm[adjl[node][1]], dep + 1); if (ind < right && adjl[node].size() == 2) query(adjl[node][1], ind, right, cost + rim[adjl[node][0]], dep + 1); } int main() { int x, y, k; scanf( %d , &n); adjl.clear(); adjl.resize(n); for (int i = (0); i < (n); ++i) { scanf( %d %d , &x, &y); x--; val[i] = y; par[i] = x; if (x >= 0) adjl[x].push_back(i); if (x < 0) root = i; } for (int i = (0); i < (adjl.size()); ++i) { if (adjl[i].size() == 2) if (val[adjl[i][0]] > val[adjl[i][1]]) swap(adjl[i][0], adjl[i][1]); if (adjl[i].size() == 1) throw 2; } pre(root); scanf( %d , &k); for (int i = (0); i < (k); ++i) scanf( %d , &qu[i].first), qu[i].second = i; sort(qu, qu + k); query(root, 0, k, 0, 0); for (int i = (0); i < (k); ++i) printf( %.12lf n , res[i]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2AI_0_V
`define SKY130_FD_SC_LP__O2BB2AI_0_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2ai_0 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2ai_0 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2AI_0_V
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#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; const int M = 205; const int MOD = 1e9 + 7; const int INF = 0x3f3f3f3f; struct node { int l, r, id; } p[N << 1]; bool cmp(node a, node b) { return a.r < b.r; } int sum[N << 4]; void update(int p, int L, int R, int pos) { if (L == R) { sum[pos]++; return; } int mid = (L + R) >> 1; if (p <= mid) update(p, L, mid, pos << 1); else update(p, mid + 1, R, pos << 1 | 1); sum[pos] = sum[pos << 1] + sum[pos << 1 | 1]; } int query(int k, int L, int R, int pos) { if (L == R) return L; int mid = (L + R) >> 1; if (k <= sum[pos << 1]) return query(k, L, mid, pos << 1); else return query(k - sum[pos << 1], mid + 1, R, pos << 1 | 1); } int n, k, x[N << 1]; vector<int> Ans; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) scanf( %d%d , &p[i].l, &p[i].r), p[i].id = i + 1, x[i * 2] = p[i].l, x[i * 2 + 1] = p[i].r; sort(p, p + n, cmp); sort(x, x + 2 * n); int m = unique(x, x + 2 * n) - x; for (int i = 0; i < n; i++) { p[i].l = lower_bound(x, x + m, p[i].l) - x; p[i].r = lower_bound(x, x + m, p[i].r) - x; } int ans = 0, st, ed; for (int i = n - 1; i >= 0; i--) { update(p[i].l, 0, m - 1, 1); if (sum[1] < k) continue; int pos = query(k, 0, m - 1, 1); int len = x[p[i].r] - x[pos] + 1; if (len > ans) ans = len, st = pos, ed = p[i].r; } if (!ans) { puts( 0 ); for (int i = 1; i <= k; i++) printf( %d , i); } else { printf( %d n , ans); for (int i = 0; i < n; i++) if (p[i].l <= st && ed <= p[i].r) Ans.push_back(p[i].id); sort(Ans.begin(), Ans.end()); for (int i = 0; i < k; i++) printf( %d , Ans[i]); } return 0; }
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#include <bits/stdc++.h> using namespace std; bool dp[5001][5001]; vector<int> bits[10001]; vector<pair<int, int> > cur; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string s, ans; cin >> s; int n = s.size(); dp[0][0] = 1; cur.push_back(make_pair(0, 0)); int cnt = 0; while ((1 << cnt) < n) cnt++; cnt--; ans = ; for (int i = 0; i < (1 << cnt); i++) for (int j = 0; j < cnt; j++) if ((i & (1 << j)) == 0) bits[i].push_back(j); int l = 1; int m = n; while (m > l) { m -= l; l *= 2; } while (ans.size() < m) { char min_chr = z ; for (int i = 0; i < cur.size(); i++) { auto x = cur[i]; for (auto j : bits[x.second]) { if (dp[x.first + (1 << j)][x.second | (1 << j)] == 0) { cur.push_back(make_pair(x.first + (1 << j), x.second | (1 << j))); dp[x.first + (1 << j)][x.second | (1 << j)] = 1; } } min_chr = min(min_chr, s[x.first]); } ans.push_back(min_chr); vector<pair<int, int> > tmp; for (auto x : cur) { if (s[x.first] == min_chr) { dp[x.first + 1][x.second] = 1; tmp.push_back(make_pair(x.first + 1, x.second)); } } cur = tmp; } cout << ans << n ; return 0; }
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//#############################################################################
//# Function: Carry Save Adder (9:2) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_csa92 #( parameter DW = 1) // data width
( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input
input [DW-1:0] in2,//input
input [DW-1:0] in3,//input
input [DW-1:0] in4,//input
input [DW-1:0] in5,//input
input [DW-1:0] in6,//input
input [DW-1:0] in7,//input
input [DW-1:0] in8,//input
input [DW-1:0] cin0,//carry in
input [DW-1:0] cin1,//carry in
input [DW-1:0] cin2,//carry in
input [DW-1:0] cin3,//carry in
input [DW-1:0] cin4,//carry in
input [DW-1:0] cin5,//carry in
output [DW-1:0] s, //sum
output [DW-1:0] c, //carry
output [DW-1:0] cout0, //carry out
output [DW-1:0] cout1, //carry out
output [DW-1:0] cout2, //carry out
output [DW-1:0] cout3, //carry out
output [DW-1:0] cout4, //carry out
output [DW-1:0] cout5 //carry out
);
wire [DW-1:0] s_int0;
wire [DW-1:0] s_int1;
wire [DW-1:0] s_int2;
oh_csa32 #(.DW(DW)) csa32_0 (.in0(in0[DW-1:0]),
.in1(in1[DW-1:0]),
.in2(in2[DW-1:0]),
.c(cout0[DW-1:0]),
.s(s_int0[DW-1:0]));
oh_csa32 #(.DW(DW)) csa32_1 (.in0(in3[DW-1:0]),
.in1(in4[DW-1:0]),
.in2(in5[DW-1:0]),
.c(cout1[DW-1:0]),
.s(s_int1[DW-1:0]));
oh_csa32 #(.DW(DW)) csa32_2 (.in0(in6[DW-1:0]),
.in1(in7[DW-1:0]),
.in2(in8[DW-1:0]),
.c(cout2[DW-1:0]),
.s(s_int2[DW-1:0]));
oh_csa62 #(.DW(DW)) csa62 (.in0(s_int0[DW-1:0]),
.in1(s_int1[DW-1:0]),
.in2(s_int2[DW-1:0]),
.in3(cin0[DW-1:0]),
.in4(cin1[DW-1:0]),
.in5(cin2[DW-1:0]),
.cin0(cin3[DW-1:0]),
.cin1(cin4[DW-1:0]),
.cin2(cin5[DW-1:0]),
.cout0(cout3[DW-1:0]),
.cout1(cout4[DW-1:0]),
.cout2(cout5[DW-1:0]),
.c(c[DW-1:0]),
.s(s[DW-1:0]));
endmodule // oh_csa92
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//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:05:32 EST 2014
//
//
// Ports:
// Name I/O size props
// RDY_s_request_put O 1
// s_response_get O 153
// RDY_s_response_get O 1
// RDY_p_put O 1
// g_get O 153
// RDY_g_get O 1
// pfk I 14
// CLK I 1 clock
// RST_N I 1 reset
// s_request_put I 153
// p_put I 153
// EN_s_request_put I 1
// EN_p_put I 1
// EN_s_response_get I 1
// EN_g_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTLPClientNode(pfk,
CLK,
RST_N,
s_request_put,
EN_s_request_put,
RDY_s_request_put,
EN_s_response_get,
s_response_get,
RDY_s_response_get,
p_put,
EN_p_put,
RDY_p_put,
EN_g_get,
g_get,
RDY_g_get);
input [13 : 0] pfk;
input CLK;
input RST_N;
// action method s_request_put
input [152 : 0] s_request_put;
input EN_s_request_put;
output RDY_s_request_put;
// actionvalue method s_response_get
input EN_s_response_get;
output [152 : 0] s_response_get;
output RDY_s_response_get;
// action method p_put
input [152 : 0] p_put;
input EN_p_put;
output RDY_p_put;
// actionvalue method g_get
input EN_g_get;
output [152 : 0] g_get;
output RDY_g_get;
// signals for module outputs
wire [152 : 0] g_get, s_response_get;
wire RDY_g_get, RDY_p_put, RDY_s_request_put, RDY_s_response_get;
// ports of submodule pktFork
wire [152 : 0] pktFork_iport_put, pktFork_oport0_get, pktFork_oport1_get;
wire pktFork_EN_iport_put,
pktFork_EN_oport0_get,
pktFork_EN_oport1_get,
pktFork_RDY_iport_put,
pktFork_RDY_oport0_get,
pktFork_RDY_oport1_get;
// ports of submodule pktMerge
wire [152 : 0] pktMerge_iport0_put, pktMerge_iport1_put, pktMerge_oport_get;
wire pktMerge_EN_iport0_put,
pktMerge_EN_iport1_put,
pktMerge_EN_oport_get,
pktMerge_RDY_iport0_put,
pktMerge_RDY_iport1_put,
pktMerge_RDY_oport_get;
// remaining internal signals
reg [1 : 0] CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1;
wire [13 : 0] x__h110;
// action method s_request_put
assign RDY_s_request_put = pktMerge_RDY_iport0_put ;
// actionvalue method s_response_get
assign s_response_get = pktFork_oport0_get ;
assign RDY_s_response_get = pktFork_RDY_oport0_get ;
// action method p_put
assign RDY_p_put = pktFork_RDY_iport_put ;
// actionvalue method g_get
assign g_get = pktMerge_oport_get ;
assign RDY_g_get = pktMerge_RDY_oport_get ;
// submodule pktFork
mkPktFork pktFork(.pfk(x__h110),
.CLK(CLK),
.RST_N(RST_N),
.iport_put(pktFork_iport_put),
.EN_iport_put(pktFork_EN_iport_put),
.EN_oport0_get(pktFork_EN_oport0_get),
.EN_oport1_get(pktFork_EN_oport1_get),
.RDY_iport_put(pktFork_RDY_iport_put),
.oport0_get(pktFork_oport0_get),
.RDY_oport0_get(pktFork_RDY_oport0_get),
.oport1_get(pktFork_oport1_get),
.RDY_oport1_get(pktFork_RDY_oport1_get));
// submodule pktMerge
mkPktMerge pktMerge(.CLK(CLK),
.RST_N(RST_N),
.iport0_put(pktMerge_iport0_put),
.iport1_put(pktMerge_iport1_put),
.EN_iport0_put(pktMerge_EN_iport0_put),
.EN_iport1_put(pktMerge_EN_iport1_put),
.EN_oport_get(pktMerge_EN_oport_get),
.RDY_iport0_put(pktMerge_RDY_iport0_put),
.RDY_iport1_put(pktMerge_RDY_iport1_put),
.oport_get(pktMerge_oport_get),
.RDY_oport_get(pktMerge_RDY_oport_get));
// submodule pktFork
assign pktFork_iport_put = p_put ;
assign pktFork_EN_iport_put = EN_p_put ;
assign pktFork_EN_oport0_get = EN_s_response_get ;
assign pktFork_EN_oport1_get =
pktMerge_RDY_iport1_put && pktFork_RDY_oport1_get ;
// submodule pktMerge
assign pktMerge_iport0_put = s_request_put ;
assign pktMerge_iport1_put = pktFork_oport1_get ;
assign pktMerge_EN_iport0_put = EN_s_request_put ;
assign pktMerge_EN_iport1_put =
pktMerge_RDY_iport1_put && pktFork_RDY_oport1_get ;
assign pktMerge_EN_oport_get = EN_g_get ;
// remaining internal signals
assign x__h110 =
{ CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1,
pfk[11:0] } ;
always@(pfk)
begin
case (pfk[13:12])
2'd0, 2'd1, 2'd2:
CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = pfk[13:12];
2'd3: CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = 2'd3;
endcase
end
endmodule // mkTLPClientNode
|
#include <bits/stdc++.h> using namespace std; long long* parent; long long* size; void make_set(long long v) { parent[v] = v; size[v] = 1; } long long find_set(long long v) { if (v == parent[v]) return v; return parent[v] = find_set(parent[v]); } void union_set(long long u, long long v) { long long p1, p2; p1 = find_set(u); p2 = find_set(v); if (p1 != p2) { if (size[p1] < size[p2]) swap(p1, p2); parent[p2] = p1; size[p1] += size[p2]; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, m; cin >> n >> m; vector<long long> vc(n + 1); parent = new long long[n + 1]; size = new long long[n + 1]; for (long long i = 1; i <= n; i++) { cin >> vc[i]; make_set(i); } long long a, b; for (long long i = 0; i < m; i++) { cin >> a >> b; union_set(a, b); } unordered_map<long long, long long> mp; vector<vector<long long> > ele(n + 1); vector<vector<long long> > ind(n + 1); long long k; long long p = 0, pp; for (long long i = 1; i <= n; i++) { k = find_set(i); if (mp[k] == 0) { p++; pp = p; mp[k] = p; } else { pp = mp[k]; } ele[pp].push_back(vc[i]); ind[pp].push_back(i); } for (long long i = 1; i <= p; i++) { sort(ele[i].begin(), ele[i].end(), greater<long long>()); sort(ind[i].begin(), ind[i].end()); for (long long j = 0; j < ele[i].size(); j++) { vc[ind[i][j]] = ele[i][j]; } } for (long long i = 1; i <= n; i++) cout << vc[i] << ; return 0; }
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