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// This module explicitly instantiates a chain of 1 to 4 SRL32s along with
// required MUXF7s and MUX8.
module srl32_chain_seg #
(
parameter N = 1, // Numbers of SRL32s in chain (from 1 to 4!)
parameter SITE = "" // Site to LOC all bels to
)
(
input wire CLK,
input wire CE,
input wire D,
input wire [4+$clog2(N):0] A,
output wire Q,
output wire Q31
);
// ============================================================================
// SRLs
wire [N-1:0] srl_d;
wire [N-1:0] srl_q;
wire [N-1:0] srl_q31;
assign srl_d[0] = D;
// SRLs
genvar i;
generate for(i=0; i<N; i=i+1) begin
(* KEEP, DONT_TOUCH *)
SRLC32E srl
(
.CLK (CLK),
.CE (CE),
.A (A[4:0]),
.D (srl_d[i]),
.Q (srl_q[i]),
.Q31 (srl_q31[i])
);
if (i > 0)
assign srl_d[i] = srl_q31[i-1];
end endgenerate
// ============================================================================
// Muxes
wire f7bmux_o;
wire f7amux_o;
wire f8mux_o;
generate
if (N == 2) begin
// F7AMUX
(* BEL="F7AMUX", KEEP, DONT_TOUCH *)
MUXF7 muxf7a
(
.I0 (srl_q[0]),
.I1 (srl_q[1]),
.S (A[5]),
.O (f7amux_o)
);
end else if (N >= 3) begin
// F7BMUX
(* BEL="F7BMUX", KEEP, DONT_TOUCH *)
MUXF7 muxf7b
(
.I0 (srl_q[0]),
.I1 (srl_q[1]),
.S (A[5]),
.O (f7bmux_o)
);
if (N == 3) begin
// F7AMUX
(* BEL="F7AMUX", KEEP, DONT_TOUCH *)
MUXF7 muxf7a
(
.I0 (srl_q[2]),
.I1 (),
.S (A[5]),
.O (f7amux_o)
);
end else if (N == 4) begin
// F7AMUX
(* BEL="F7AMUX", KEEP, DONT_TOUCH *)
MUXF7 muxf7a
(
.I0 (srl_q[2]),
.I1 (srl_q[3]),
.S (A[5]),
.O (f7amux_o)
);
end
// F8MUX
(* BEL="F8MUX", KEEP, DONT_TOUCH *)
MUXF8 muxf8
(
.I0 (f7bmux_o),
.I1 (f7amux_o),
.S (A[6]),
.O (f8mux_o)
);
end
endgenerate
// ============================================================================
// Output assignment
assign Q = (N == 1) ? srl_q[0] :
(N == 2) ? f7amux_o : f8mux_o;
assign Q31 = srl_q31[N-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; template <class T> void chkmin(T &x, const T &y) { if (y < x) { x = y; } } template <class T> void chkmax(T &x, const T &y) { if (y > x) { x = y; } } template <class T> void sort(vector<T> &a) { sort(a.begin(), a.end()); } template <class T, class Cmp> void sort(vector<T> &a, Cmp cmp) { sort(a.begin(), a.end(), cmp); } template <class T> void unique(vector<T> &a) { a.resize(unique(a.begin(), a.end()) - a.begin()); } int readInt() { int x = 0; char c = getchar(); while (!isdigit(c)) { c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } return x; } string readString() { string s; char c = getchar(); while (isspace(c)) { c = getchar(); } while (!isspace(c)) { s += c; c = getchar(); } return s; } void solve_single_test(int test_id = 1) { int a = readInt(); int b = readInt(); int n = a + b; int ans = 0; for (int l = 1, r; l <= n; l = r + 1) { int t = n / l; r = n / t; if ((a + t) / (t + 1) > a / t || (b + t) / (t + 1) > b / t) { continue; } int L = max(l, (a + t) / (t + 1) + (b + t) / (t + 1)); int R = min(r, a / t + b / t) + 1; if (L < R) { ans += R - L; } } printf( %d n , ans); } void solve_multiple_tests() { int n_tests; scanf( %d , &n_tests); for (int i = 1; i <= n_tests; ++i) { solve_single_test(i); } } int main() { solve_single_test(); return 0; }
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#include <bits/stdc++.h> using namespace std; int a, b, c, d; void solve() { double m = max((3.0) * a / (10.0), (double)(a - a * c / 250)); double v = max((3.0) * b / (10.0), (double)(b - b * d / 250)); if (m > v) cout << Misha << endl; if (m == v) cout << Tie << endl; if (m < v) cout << Vasya << endl; } int main() { while (cin >> a >> b >> c >> d) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int read() { int X = 0, w = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) w = -1; c = getchar(); } while (c >= 0 && c <= 9 ) X = X * 10 + c - 0 , c = getchar(); return X * w; } const int N = 100000 + 10; const long long inf = 0x3f3f3f3f3f3f3f3f; int n, a[N], b[N]; vector<int> E[N]; int rt[N], tot = 0; struct line { int k; long long b; } s[N]; struct node { int ls, rs, id; } t[N * 30]; long long f(int i, int x) { return 1ll * s[i].k * x + s[i].b; } void modify(int& o, int l, int r, int x) { if (!o) { o = ++tot, t[o].id = x; return; } if (l == r) { if (f(x, l) < f(t[o].id, l)) t[o].id = x; return; } int mid = (l + r) >> 1; if (s[x].k < s[t[o].id].k) { if (f(x, mid) < f(t[o].id, mid)) modify(t[o].ls, l, mid, t[o].id), t[o].id = x; else modify(t[o].rs, mid + 1, r, x); } else if (s[x].k > s[t[o].id].k) { if (f(x, mid) < f(t[o].id, mid)) modify(t[o].rs, mid + 1, r, t[o].id), t[o].id = x; else modify(t[o].ls, l, mid, x); } else if (s[x].b < s[t[o].id].b) t[o].id = x; } long long query(int o, int l, int r, int x) { if (!o) return inf; if (l == r) return f(t[o].id, l); int mid = (l + r) >> 1; long long res = f(t[o].id, x); if (x <= mid) res = min(res, query(t[o].ls, l, mid, x)); else res = min(res, query(t[o].rs, mid + 1, r, x)); return res; } int merge(int x, int y, int l, int r) { if (!x || !y) return x | y; if (l == r) return f(t[x].id, l) < f(t[y].id, l) ? x : y; int mid = (l + r) >> 1; t[x].ls = merge(t[x].ls, t[y].ls, l, mid); t[x].rs = merge(t[x].rs, t[y].rs, mid + 1, r); modify(x, l, r, t[y].id); return x; } long long dp[N]; void dfs(int u, int f) { if (f && E[u].size() == 1) dp[u] = 0; else { for (int v : E[u]) if (v != f) dfs(v, u), rt[u] = merge(rt[u], rt[v], -1e5, 1e5); dp[u] = query(rt[u], -1e5, 1e5, a[u]); } s[u] = (line){b[u], dp[u]}, modify(rt[u], -1e5, 1e5, u); } int main() { n = read(); for (int i = 1; i <= n; ++i) a[i] = read(); for (int i = 1; i <= n; ++i) b[i] = read(); for (int i = 1; i < n; ++i) { int u = read(), v = read(); E[u].emplace_back(v), E[v].emplace_back(u); } dfs(1, 0); for (int i = 1; i <= n; ++i) printf( %lld , dp[i]); puts( ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_4_V
`define SKY130_FD_SC_MS__O22AI_4_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o22ai_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_4_V
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#include <bits/stdc++.h> using namespace std; int s[65] = {0, 1, 1, 1, 2, 1, 2, 1, 5, 2, 2, 1, 5, 1, 2, 1, 14, 1, 5, 1, 5, 2, 2, 1, 15, 2, 2, 5, 4, 1, 4, 1, 51, 1, 2, 1, 14, 1, 2, 2, 14, 1, 6, 1, 4, 2, 2, 1, 52, 2, 5, 1, 5, 1, 15, 2, 13, 2, 2, 1, 13, 1, 2, 4, 267}; int n; int main() { scanf( %d , &n); printf( %d n , s[n]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int n, u, a[300001], x, y; long double ans = -1.0; int main() { cin >> n >> u; for (int i = 0; i < n; ++i) cin >> a[i]; y = 1; while (x < n - 2) { while (y < n - 1 && a[y + 1] - a[x] <= u) ++y; if (y - x >= 2 && a[y] - a[x] <= u) ans = max(ans, (long double)(a[y] - a[x + 1]) / (long double)(a[y] - a[x])); ++x; } printf( %.9Lf n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long inf = 1e18; const long double eps = 1e-8; const double pi = acos(-1); const long long hashh = 247; char s[203040]; long long p[203040], cnt[203040], hs[203040][2]; long long get(long long l, long long r) { return (hs[r][l & 1] - hs[l - 1][l & 1] * p[cnt[r] - cnt[l - 1]] % mod + mod) % mod; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); int n, q; cin >> n >> s + 1 >> q; p[0] = 1; for (int i = 1; i < n + 1; i++) { p[i] = p[i - 1] * hashh % mod; cnt[i] = cnt[i - 1]; hs[i][0] = hs[i - 1][0]; hs[i][1] = hs[i - 1][1]; if (s[i] == 0 ) { cnt[i]++; hs[i][0] = (hs[i - 1][0] * hashh + (i & 1) + 1) % mod; hs[i][1] = (hs[i - 1][1] * hashh + (i & 1 ^ 1) + 1) % mod; } } for (int i = 0; i < q; i++) { long long l1, l2, len; cin >> l1 >> l2 >> len; if (get(l1, l1 + len - 1) == get(l2, l2 + len - 1)) cout << Yes n ; else cout << No n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_TB_V
`define SKY130_FD_SC_HS__XOR3_TB_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 C = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 C = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 C = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 C = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__xor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_TB_V
`define SKY130_FD_SC_LP__O21BA_TB_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ba.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_lp__o21ba dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_TB_V
|
#include <bits/stdc++.h> using std::bitset; using std::cin; using std::cout; using std::endl; using std::make_pair; using std::map; using std::pair; using std::priority_queue; using std::queue; using std::set; using std::string; using std::stringstream; using std::vector; class MyTimer { public: void reset() {} void report() {} } myTimer; template <typename A, typename B> std::ostream &operator<<(std::ostream &cout, const pair<A, B> &x) { return cout << ( << x.first << , << x.second << ) ; } template <typename T1, typename T2> inline bool chmin(T1 &a, const T2 &b) { return a > b ? a = b, true : false; } template <typename T1, typename T2> inline bool chmax(T1 &a, const T2 &b) { return a < b ? a = b, true : false; } const int maxN = 100000 + 233; int n, m; int a[maxN], b[maxN], c[maxN], d[maxN], e[maxN]; int ans[maxN]; struct Q { int t; int x, y, L, R; Q(int t, int x, int y, int L, int R) : t(t), x(x), y(y), L(L), R(R) {} bool operator<(const Q &rhs) const { return x != rhs.x ? x < rhs.x : y != rhs.y ? y < rhs.y : t > rhs.t; } }; vector<Q> q, tmp; void initialize() { std::ios::sync_with_stdio(false); cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= n; ++i) cin >> b[i]; for (int i = 1; i <= n; ++i) cin >> c[i]; for (int i = 1; i <= m; ++i) cin >> d[i]; for (int i = 1; i <= m; ++i) cin >> e[i]; for (int i = 1; i <= n; ++i) { q.emplace_back(i, -c[i] + a[i], c[i] + a[i], a[i], b[i]); } for (int i = 1; i <= m; ++i) { q.emplace_back(-i, -e[i] + d[i], d[i] + e[i], d[i], d[i]); } vector<int> t; for (auto &p : q) t.push_back(p.L), t.push_back(p.R); std::sort(t.begin(), t.end()); t.erase(std::unique(t.begin(), t.end()), t.end()); for (auto &p : q) p.L = std::lower_bound(t.begin(), t.end(), p.L) - t.begin() + 1, p.R = std::lower_bound(t.begin(), t.end(), p.R) - t.begin() + 1; std::sort(q.begin(), q.end()); tmp.resize(q.size(), Q(0, 0, 0, 0, 0)); } int C[maxN * 3]; void add(int p, int x) { p += 2; for (int i = p; i <= n * 2 + m + 5; i += i & -i) C[i] += x; } int sum(int p) { p += 2; int r = 0; for (int i = p; i > 0; i -= i & -i) r += C[i]; return r; } void solve(int L, int R) { if (L >= R) return; int M = (L + R) >> 1; solve(L, M); solve(M + 1, R); int i = L, j = M + 1, qwq = L; const auto left = [&](const Q &p) { tmp[qwq++] = p; if (p.t > 0) add(p.L, 1), add(p.R + 1, -1); }; const auto right = [&](const Q &p) { tmp[qwq++] = p; if (p.t < 0) ans[-p.t] += sum(p.L); }; while (i <= M && j <= R) { if (q[i].y < q[j].y || (q[i].y == q[j].y && q[i].t > 0)) left(q[i++]); else right(q[j++]); } while (i <= M) left(q[i++]); while (j <= R) right(q[j++]); for (int k = L; k <= M; ++k) if (q[k].t > 0) add(q[k].L, -1), add(q[k].R + 1, 1); for (int k = L; k <= R; ++k) q[k] = tmp[k]; } int main() { initialize(); solve(0, (int)q.size() - 1); for (int i = 1; i <= m; ++i) printf( %d%c , ans[i], n [i == m]); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, ar[100010], flag = 1, cnt = 1; char s[100010]; scanf( %d , &n); getchar(); for (int i = 1; i <= n; i++) scanf( %c , &s[i]); for (int i = 1; i <= n; i++) scanf( %d , &ar[i]); for (int i = 1; i <= n; i++) { if (s[cnt] == > ) cnt += ar[cnt]; else cnt -= ar[cnt]; if (cnt > n || cnt < 1) { printf( FINITE n ); flag = 0; break; } } if (flag) printf( INFINITE n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__EDFXBP_PP_BLACKBOX_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXBP_PP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; struct Rec { pair<int, int> interval[4]; } recs[100005]; bool check(set<pair<pair<int, int>, int>> st[]) { int n = st[0].size(); if (n == 1) return true; set<pair<pair<int, int>, int>>::iterator iter[4]; for (int i = 0; i < 4; i++) iter[i] = st[i].begin(); vector<int> mxr(4, -inf); for (int i = 0; i < n - 1; i++) { for (int j = 0; j < 4; j++) { mxr[j] = max(mxr[j], iter[j]->first.second); iter[j]++; if (iter[j]->first.first >= mxr[j]) { set<pair<pair<int, int>, int>> mini[4]; vector<int> indexs; for (auto it = st[j].begin(); it != iter[j]; it++) { int index = it->second; indexs.push_back(index); } for (auto index : indexs) { for (int z = 0; z < 4; z++) { mini[z].insert(make_pair(recs[index].interval[z], index)); st[z].erase(make_pair(recs[index].interval[z], index)); } } if (check(mini) && check(st)) return true; return false; } } } return false; } int main() { ios::sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < n; i++) { int a, b, c, d; cin >> a >> b >> c >> d; recs[i].interval[0] = make_pair(a, c); recs[i].interval[1] = make_pair(b, d); recs[i].interval[2] = make_pair(-c, -a); recs[i].interval[3] = make_pair(-d, -b); } set<pair<pair<int, int>, int>> st[4]; for (int i = 0; i < 4; i++) { for (int j = 0; j < n; j++) st[i].insert(make_pair(recs[j].interval[i], j)); } puts(check(st) ? YES : NO ); return 0; }
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#include <bits/stdc++.h> using namespace std; void solve(); int main() { ios::sync_with_stdio(0); solve(); return 0; } int a[1000001]; void solve() { int n, m; cin >> n >> m; for (int i = 0; i < n; ++i) { int v; cin >> v; a[v]++; } for (int i = 0; i < m; ++i) { int v; cin >> v; a[v]--; } int ans = 0; int j = 0; for (int i = 1; i <= 1000000; ++i) { if (a[i] > 0) { j = max(j, i); bool f = 0; while (j <= 1000000 && !f) { if (a[j] < 0) { a[j]++; f = 1; } else j++; } ans += !f; } } cout << ans << n ; }
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#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; const vector<int> mods = {998244353, 1000000007, 1000000009}; const long long inf = 3e18; const double pi = acos(-1.0); const double eps = 0.0000001; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); template <class... K> using umap = unordered_map<K...>; template <class... K> using uset = unordered_set<K...>; double dp[200]; long long lad[200]; int main() { cin.sync_with_stdio(0); cin.tie(0); cout.precision(13); fill(&dp[0], &dp[0] + sizeof(dp) / sizeof(dp[0]), 0); for (long long i = (0); i < (10); ++i) for (long long j = (0); j < (10); ++j) { long long fw = i & 1; long long up; cin >> up; if (!up) continue; long long node = 10 * (9 - i) + (fw ? j : 9 - j); long long nxfw = (i + up) & 1; long long nx = 10 * (9 - i + up) + (nxfw ? j : 9 - j); lad[node] = nx; } dp[99] = 0.0; for (long long i = 98; i >= 0; i--) { double mv = 0; double ex = 0; for (long long j = (1); j < (7); ++j) { double nx = dp[i + j]; if (lad[i + j]) { nx = min(nx, dp[lad[i + j]]); } mv += 1.0 / 6 * nx; if (i + j > 99) ex++; } mv++; mv /= (1 - ex / 6.0); dp[i] = mv; } cout << dp[0] << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int v, e; vector<int> out[30005]; vector<int> ans; bool vis[30005]; void dfstree(int n) { for (auto x : out[n]) { if (!vis[x]) { vis[x] = true; dfstree(x); } } ans.push_back(n); } int main() { cin >> v >> e; for (int i = 0; i < e; i++) { int x, y; cin >> x >> y; out[x].push_back(y); } for (int i = 1; i < v + 1; i++) { if (!vis[i]) { vis[i] = true; dfstree(i); } } for (auto x : ans) cout << x << ; cout << n ; ; }
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#include <bits/stdc++.h> using namespace std; long long dp[2][52][52][52][52] = {{{{{0}}}}}; int d[52]; int n; const int MOD = 1e9 + 7; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; ++i) { cin >> d[i]; } dp[1][d[0] == 2][d[0] == 3][d[1] == 2][d[1] == 3] = 1; for (int i = 2; i < n; ++i) { memset(dp[i & 1], 0, sizeof dp[i & 1]); for (int p1 = 0; p1 <= n; ++p1) { for (int p2 = 0; p1 + p2 <= n; ++p2) { for (int c1 = 0; p1 + p2 + c1 <= n; ++c1) { for (int c2 = 0; p1 + p2 + c1 + c2 <= n; ++c2) { long long cur = dp[(i - 1) & 1][p1][p2][c1][c2]; if (!p1 and !p2) { dp[(i - 1) & 1][c1][c2][0][0] += cur; dp[(i - 1) & 1][c1][c2][0][0] %= MOD; continue; } for (int last_level = 0; last_level < 2; ++last_level) { long long ways; if (last_level) { if (p1) ways = p1--; else continue; } else { if (p2) p1++, ways = p2--; else continue; } if (d[i] == 2) { dp[i & 1][p1][p2][c1 + 1][c2] += cur * ways; dp[i & 1][p1][p2][c1 + 1][c2] %= MOD; if (c1) { dp[i & 1][p1][p2][c1 - 1][c2] += cur * ways * c1; dp[i & 1][p1][p2][c1 - 1][c2] %= MOD; } if (c2) { dp[i & 1][p1][p2][c1 + 1][c2 - 1] += cur * ways * c2; dp[i & 1][p1][p2][c1 + 1][c2 - 1] %= MOD; } } else { dp[i & 1][p1][p2][c1][c2 + 1] += cur * ways; dp[i & 1][p1][p2][c1][c2 + 1] %= MOD; dp[i & 1][p1][p2][c1][c2] += cur * ways * c1; dp[i & 1][p1][p2][c1][c2] %= MOD; if (c1 && c2) { dp[i & 1][p1][p2][c1][c2 - 1] += cur * ways * c2 * c1; dp[i & 1][p1][p2][c1][c2 - 1] %= MOD; } if (c1 > 1) { dp[i & 1][p1][p2][c1 - 2][c2] += cur * ways * (c1 * (c1 - 1)) >> 1; dp[i & 1][p1][p2][c1 - 2][c2] %= MOD; } if (c2) { dp[i & 1][p1][p2][c1 + 2][c2 - 1] += cur * ways * c2; dp[i & 1][p1][p2][c1 + 2][c2 - 1] %= MOD; } if (c2 > 1) { dp[i & 1][p1][p2][c1 + 2][c2 - 2] += cur * ways * (c2 * (c2 - 1)) >> 1; dp[i & 1][p1][p2][c1 + 2][c2 - 2] %= MOD; } } if (last_level) { p1++; } else { p2++; p1--; } } } } } } } cout << dp[(n - 1) & 1][0][0][0][0] << endl; }
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// XXX Icarus can't handle parameters being use in the header
`timescale 1ns/10ps
module simpledpram(clock,
wraddress, wrdata, wren,
rdaddress, rddata);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
parameter INIT_FILE = "somefile.mif";
parameter OFFSET = 0;
input clock;
input [(ADDR_WIDTH-1):0] rdaddress;
output reg [(DATA_WIDTH-1):0] rddata;
input [(DATA_WIDTH-1):0] wrdata;
input wren;
input [(ADDR_WIDTH-1):0] wraddress;
// Declare the RAM variable
(* ram_init_file = INIT_FILE *)
reg [DATA_WIDTH-1:0] ram[(1 << ADDR_WIDTH)-1:0];
parameter debug = 0;
always @ (posedge clock) begin
// Write
if (wren)
ram[wraddress] <= wrdata;
if (debug & wren)
$display("%x: ram[%x] (was %x) <= %x", OFFSET, wraddress,
ram[wraddress],
wrdata);
// Read (if rdaddress == wraddress, return OLD data). To return
// NEW data, use = (blocking write) rather than <= (non-blocking write)
// in the write assignment. NOTE: NEW data may require extra bypass
// logic around the RAM.
rddata <= ram[rdaddress];
end
initial #0 $readmemh({INIT_FILE,".data"}, ram);
endmodule
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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for ip_mux
*/
module test_ip_mux_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT-1:0] s_ip_hdr_valid = 0;
reg [S_COUNT*48-1:0] s_eth_dest_mac = 0;
reg [S_COUNT*48-1:0] s_eth_src_mac = 0;
reg [S_COUNT*16-1:0] s_eth_type = 0;
reg [S_COUNT*4-1:0] s_ip_version = 0;
reg [S_COUNT*4-1:0] s_ip_ihl = 0;
reg [S_COUNT*6-1:0] s_ip_dscp = 0;
reg [S_COUNT*2-1:0] s_ip_ecn = 0;
reg [S_COUNT*16-1:0] s_ip_length = 0;
reg [S_COUNT*16-1:0] s_ip_identification = 0;
reg [S_COUNT*3-1:0] s_ip_flags = 0;
reg [S_COUNT*13-1:0] s_ip_fragment_offset = 0;
reg [S_COUNT*8-1:0] s_ip_ttl = 0;
reg [S_COUNT*8-1:0] s_ip_protocol = 0;
reg [S_COUNT*16-1:0] s_ip_header_checksum = 0;
reg [S_COUNT*32-1:0] s_ip_source_ip = 0;
reg [S_COUNT*32-1:0] s_ip_dest_ip = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_ip_payload_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_ip_payload_axis_tkeep = 0;
reg [S_COUNT-1:0] s_ip_payload_axis_tvalid = 0;
reg [S_COUNT-1:0] s_ip_payload_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_ip_payload_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_ip_payload_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_ip_payload_axis_tuser = 0;
reg m_ip_hdr_ready = 0;
reg m_ip_payload_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
wire [S_COUNT-1:0] s_ip_hdr_ready;
wire [S_COUNT-1:0] s_ip_payload_axis_tready;
wire m_ip_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [3:0] m_ip_version;
wire [3:0] m_ip_ihl;
wire [5:0] m_ip_dscp;
wire [1:0] m_ip_ecn;
wire [15:0] m_ip_length;
wire [15:0] m_ip_identification;
wire [2:0] m_ip_flags;
wire [12:0] m_ip_fragment_offset;
wire [7:0] m_ip_ttl;
wire [7:0] m_ip_protocol;
wire [15:0] m_ip_header_checksum;
wire [31:0] m_ip_source_ip;
wire [31:0] m_ip_dest_ip;
wire [DATA_WIDTH-1:0] m_ip_payload_axis_tdata;
wire [KEEP_WIDTH-1:0] m_ip_payload_axis_tkeep;
wire m_ip_payload_axis_tvalid;
wire m_ip_payload_axis_tlast;
wire [ID_WIDTH-1:0] m_ip_payload_axis_tid;
wire [DEST_WIDTH-1:0] m_ip_payload_axis_tdest;
wire [USER_WIDTH-1:0] m_ip_payload_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_ip_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_ip_version,
s_ip_ihl,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_identification,
s_ip_flags,
s_ip_fragment_offset,
s_ip_ttl,
s_ip_protocol,
s_ip_header_checksum,
s_ip_source_ip,
s_ip_dest_ip,
s_ip_payload_axis_tdata,
s_ip_payload_axis_tkeep,
s_ip_payload_axis_tvalid,
s_ip_payload_axis_tlast,
s_ip_payload_axis_tid,
s_ip_payload_axis_tdest,
s_ip_payload_axis_tuser,
m_ip_hdr_ready,
m_ip_payload_axis_tready,
enable,
select
);
$to_myhdl(
s_ip_hdr_ready,
s_ip_payload_axis_tready,
m_ip_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_ip_version,
m_ip_ihl,
m_ip_dscp,
m_ip_ecn,
m_ip_length,
m_ip_identification,
m_ip_flags,
m_ip_fragment_offset,
m_ip_ttl,
m_ip_protocol,
m_ip_header_checksum,
m_ip_source_ip,
m_ip_dest_ip,
m_ip_payload_axis_tdata,
m_ip_payload_axis_tkeep,
m_ip_payload_axis_tvalid,
m_ip_payload_axis_tlast,
m_ip_payload_axis_tid,
m_ip_payload_axis_tdest,
m_ip_payload_axis_tuser
);
// dump file
$dumpfile("test_ip_mux_4.lxt");
$dumpvars(0, test_ip_mux_4);
end
ip_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// IP frame inputs
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_ip_version(s_ip_version),
.s_ip_ihl(s_ip_ihl),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(s_ip_identification),
.s_ip_flags(s_ip_flags),
.s_ip_fragment_offset(s_ip_fragment_offset),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_header_checksum(s_ip_header_checksum),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tid(s_ip_payload_axis_tid),
.s_ip_payload_axis_tdest(s_ip_payload_axis_tdest),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(m_ip_hdr_valid),
.m_ip_hdr_ready(m_ip_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_ip_payload_axis_tdata(m_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(m_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(m_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(m_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(m_ip_payload_axis_tlast),
.m_ip_payload_axis_tid(m_ip_payload_axis_tid),
.m_ip_payload_axis_tdest(m_ip_payload_axis_tdest),
.m_ip_payload_axis_tuser(m_ip_payload_axis_tuser),
// Control
.enable(enable),
.select(select)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[1050], b[1050]; int main() { int n, m, s = 0, d = 0; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> a[i]; b[i] = a[i]; } for (int i = 1; i <= n; i++) { sort(a, a + m); for (int j = 0; j < m; j++) { if (a[j] > 0) { s += a[j]; a[j]--; break; } } } for (int i = 1; i <= n; i++) { sort(b, b + m); for (int j = m - 1; j >= 0; j--) { if (b[j] > 0) { d += b[j]; b[j]--; break; } } } cout << d << << s; return 0; }
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#include <bits/stdc++.h> using namespace std; inline void read(int &x) { x = 0; int f = 1; char c = getchar(); while (c > 9 || c < 0 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); x *= f; } const int maxn = 100100; struct node { int v, nxt; } e[maxn]; int head[maxn], tot; inline void add(int x, int y) { tot++; e[tot].v = y; e[tot].nxt = head[x]; head[x] = tot; } struct AA { int s, num; }; map<string, int> h; vector<AA> ask[maxn]; set<int> hip[maxn]; int n, q, s, t, cnt, name[maxn], dep[maxn], son[maxn], size[maxn], ans[maxn]; bool vis[maxn]; char ch[30]; inline void dfs1(int x, int fa) { size[x] = 1; dep[x] = dep[fa] + 1; for (int i = head[x]; i; i = e[i].nxt) { int v = e[i].v; if (v == fa) continue; dfs1(v, x); size[x] += size[v]; if (son[x] == 0 || size[v] > size[son[x]]) son[x] = v; } } inline void calc(int x, int fa) { hip[dep[x]].insert(name[x]); for (int i = head[x]; i; i = e[i].nxt) { int v = e[i].v; if (v == fa || vis[v]) continue; calc(v, x); } } inline void dfs2(int x, int fa, int keep) { for (int i = head[x]; i; i = e[i].nxt) { int v = e[i].v; if (v == fa || v == son[x]) continue; dfs2(v, x, 0); } if (son[x]) dfs2(son[x], x, 1), vis[son[x]] = true; calc(x, fa); vis[son[x]] = false; for (int i = 0; i < ask[x].size(); i++) { if (dep[x] + ask[x][i].s <= n) ans[ask[x][i].num] = hip[dep[x] + ask[x][i].s].size(); } if (!keep) { for (int i = dep[x]; !hip[i].empty(); i++) { hip[i].clear(); } } } int main() { read(n); for (int i = 1; i <= n; i++) { scanf( %s , ch); if (h.find(ch) == h.end()) h[ch] = ++cnt; name[i] = h[ch]; read(s), add(s, i); } read(q); AA tmp; for (int i = 1; i <= q; i++) { read(s), read(t); tmp.s = t; tmp.num = i; ask[s].push_back(tmp); } dep[0] = -1; dfs1(0, 0); dfs2(0, 0, 1); for (int i = 1; i <= q; i++) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const int N = 2e5 + 5; const int SZ = 1e6 + 5; const long long INF = 2e9 + 5; int n, m, p; pair<int, long long> a[N], b[N]; pair<int, pair<int, long long> > mon[N]; long long tree[4 * SZ], lazy[4 * SZ], cost[SZ]; void Build(int c, int ss, int se) { if (ss == se) { tree[c] = cost[ss]; return; } int mid = (ss + se) >> 1; Build(c << 1, ss, mid); Build(c << 1 | 1, mid + 1, se); tree[c] = max(tree[c << 1], tree[c << 1 | 1]); } void Push(int c, int ss, int se) { if (lazy[c]) { tree[c] += lazy[c]; if (ss != se) { lazy[c << 1] += lazy[c]; lazy[c << 1 | 1] += lazy[c]; } lazy[c] = 0; } } void Set(int c, int ss, int se, int qs, int qe, long long val) { Push(c, ss, se); if (ss > se || qs > se || qe < ss) return; if (qs <= ss && se <= qe) { lazy[c] += val; Push(c, ss, se); return; } int mid = (ss + se) >> 1; Set(c << 1, ss, mid, qs, qe, val); Set(c << 1 | 1, mid + 1, se, qs, qe, val); tree[c] = max(tree[c << 1], tree[c << 1 | 1]); } long long Get(int c, int ss, int se, int qs, int qe) { Push(c, ss, se); if (ss > se || qs > se || qe < ss) return -INF; if (qs <= ss && se <= qe) return tree[c]; int mid = (ss + se) >> 1; return max(Get(c << 1, ss, mid, qs, qe), Get(c << 1 | 1, mid + 1, se, qs, qe)); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m >> p; for (int i = 1; i <= n; i++) cin >> a[i].first >> a[i].second; for (int i = 1; i <= m; i++) cin >> b[i].first >> b[i].second; for (int i = 1; i <= p; i++) cin >> mon[i].first >> mon[i].second.first >> mon[i].second.second; for (int i = 1; i < SZ; i++) cost[i] = -INF; for (int i = 1; i <= m; i++) { cost[b[i].first] = max(cost[b[i].first], -b[i].second); } sort(a + 1, a + 1 + n); sort(mon + 1, mon + 1 + p); Build(1, 1, SZ - 1); int j = 0; long long ans = -2 * INF; for (int i = 1; i <= n; i++) { while (j + 1 <= p && a[i].first > mon[j + 1].first) { j++; Set(1, 1, SZ - 1, mon[j].second.first + 1, SZ, mon[j].second.second); } ans = max(ans, -a[i].second + Get(1, 1, SZ - 1, 1, SZ - 1)); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int num, hight, temp, width = 0; cin >> num >> hight; vector<int> v; for (int i = 0; i < num; i++) { cin >> temp; v.push_back(temp); if (v[i] > hight) width += 2; else width++; } cout << width; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4BB_1_V
`define SKY130_FD_SC_MS__AND4BB_1_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4bb_1 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4bb_1 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4BB_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 21, inf = 1e7; int n, k, a[1 << N], pre[1 << N], ns, cs[1 << N]; inline int cmax(int x, int y) { if (x == -1 || y == -1) return x == -1 ? y : x; return a[x] > a[y] ? x : y; } bool E[1 << N][N]; void UPD(int x) { cs[x] = -1; for (int i = (0); i <= (n - 1); ++i) if (E[x][i]) { int nx = cmax(cs[x], x ^ (1 << i)); if (nx != cs[x]) pre[x] = x ^ (1 << i), cs[x] = x ^ (1 << i); } } int teshu[1 << N], g; void change(int u, int v) { int t = u ^ v; t = log2(t), E[u][t] ^= 1, E[v][t] ^= 1; } bool op[1 << N], vis[1 << N]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> k; for (int i = (0); i <= ((1 << n) - 1); ++i) cin >> a[i], op[i] = op[i >> 1] ^ (i & 1), cs[i] = -1; for (int i = (0); i <= ((1 << n) - 1); ++i) if (!op[i]) for (int j = (0); j <= (n - 1); ++j) E[i][j] = true; for (int i = (0); i <= ((1 << n) - 1); ++i) if (!op[i]) UPD(i); while (k--) { int x = -1, r = -1; for (int i = (0); i <= ((1 << n) - 1); ++i) if (!op[i] && cs[i] != -1 && (x == -1 || a[i] + a[cs[i]] >= r)) x = i, r = a[i] + a[cs[i]]; if (x == -1 || a[x] + a[cs[x]] <= 0) break; ns += a[x], ns += a[cs[x]]; int rn = x; while (rn != cs[x]) change(rn, pre[rn]), rn = pre[rn]; a[cs[x]] = a[x] = -inf; teshu[++g] = x, teshu[++g] = cs[x]; cs[cs[x]] = -1, cs[x] = -1; for (int i = (1); i <= (g); ++i) { int x = teshu[i]; for (int j = (0); j <= (n - 1); ++j) { int v = x ^ (1 << j); cs[v] = -1; if (!op[v]) UPD(v); } } for (int i = (1); i <= (g); ++i) { int u = teshu[i]; if (op[u] == 1) cs[u] = pre[u] = -1; else pre[u] = -1, UPD(u); } for (int i = (1); i <= (g); ++i) vis[teshu[i]] = false; for (int i = (1); i <= (g); ++i) { int x = -1; for (int j = (1); j <= (g); ++j) if (!vis[teshu[j]]) x = teshu[j]; for (int j = (1); j <= (g); ++j) if (!vis[teshu[j]] && cmax(cs[x], cs[teshu[j]]) != cs[x]) x = teshu[j]; vis[x] = true; for (int j = (0); j <= (n - 1); ++j) if (!E[x][j]) { int v = x ^ (1 << j); int nx = cmax(cs[x], cs[v]); if (nx != cs[v]) pre[v] = x, cs[v] = cs[x]; } } } cout << ns << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 210; const double eps = 1e-9; int n; int lsh[maxn * 2], ln, K; map<int, int> mt; int To[maxn]; int li[maxn], ri[maxn]; double f[2][maxn][maxn]; double ans[maxn][maxn]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d%d , &li[i], &ri[i]), lsh[++ln] = li[i], lsh[++ln] = ri[i]; sort(lsh + 1, lsh + ln + 1); lsh[0] = lsh[1] - 1; K = 0; for (int i = 1; i <= ln; i++) if (lsh[i] != lsh[i - 1]) To[mt[lsh[i]] = ++K] = lsh[i]; for (int i = 1; i <= n; i++) li[i] = mt[li[i]], ri[i] = mt[ri[i]]; for (int i = 1; i <= n; i++) { for (int x = li[i]; x < ri[i]; x++) { double inow = (double)(To[x + 1] - To[x]) / (To[ri[i]] - To[li[i]]); for (int x1 = 0; x1 <= n; x1++) for (int x2 = 0; x2 <= n; x2++) f[0][x1][x2] = f[1][x1][x2] = 0; int now = 1; f[now][0][0] = 1.0; for (int j = 1; j <= n; j++) { if (i == j) continue; int L = To[li[j]], R = To[ri[j]]; now = !now; if (x < li[j]) { for (int x1 = 0; x1 < j; x1++) for (int x2 = 0; x2 < j - x1; x2++) if (f[!now][x1][x2] > eps) { double tmp = f[!now][x1][x2]; f[!now][x1][x2] = 0; f[now][x1][x2] += tmp; } } else if (ri[j] <= x) { for (int x1 = 0; x1 < j; x1++) for (int x2 = 0; x2 < j - x1; x2++) if (f[!now][x1][x2] > eps) { double tmp = f[!now][x1][x2]; f[!now][x1][x2] = 0; f[now][x1 + 1][x2] += tmp; } } else { double p1 = (double)(To[x] - L) / (R - L), p2 = (double)(To[x + 1] - To[x]) / (R - L), p3 = (double)(R - To[x + 1]) / (R - L); for (int x1 = 0; x1 < j; x1++) for (int x2 = 0; x2 < j - x1; x2++) if (f[!now][x1][x2] > eps) { double tmp = f[!now][x1][x2]; f[!now][x1][x2] = 0; f[now][x1 + 1][x2] += tmp * p1; f[now][x1][x2 + 1] += tmp * p2; f[now][x1][x2] += tmp * p3; } } } for (int x1 = 0; x1 < n; x1++) for (int x2 = 0; x2 < n - x1; x2++) if (f[now][x1][x2] > eps) { double tmp = f[now][x1][x2], temp = 1.0 / (x2 + 1.0); for (int l = 0; l <= x2; l++) ans[i][x1 + l + 1] += inow * tmp * temp; } } } for (int i = 1; i <= n; i++) { for (int j = 1; j < n; j++) printf( %.10lf , ans[i][j]); printf( %.10lf n , ans[i][n]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<vector<int> > D; int main(int argc, char **argv) { cin >> n >> m; for (int i = 0; i < n; i++) { string t; cin >> t; D.push_back(vector<int>()); for (int j = 0; j < m; j++) { D[D.size() - 1].push_back(t[j] == 1 ); } } int c0[400][400], c1[400][400]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int k; for (k = 0;; k++) { if (i + k >= n || j + k >= m || D[i + k][j + k]) break; } c0[i][j] = k; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int k; for (k = 0;; k++) { if (i + k >= n || j - k < 0 || D[i + k][j - k]) break; } c1[i][j] = k; } int s = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (D[i][j]) continue; for (int k = 1;; k++) { if (j + k >= m || i + k >= n || D[i][j + k] || D[i + k][j]) break; if (c1[i][j + k] > k) s += 1; } for (int k = 1;; k++) { if (j - k < 0 || i + k >= n || D[i][j - k] || D[i + k][j]) break; if (c0[i][j - k] > k) s += 1; } for (int k = 1;; k++) { if (j + k >= m || i - k < 0 || D[i][j + k] || D[i - k][j]) break; if (c0[i - k][j] > k) s += 1; } for (int k = 1;; k++) { if (j - k < 0 || i - k < 0 || D[i][j - k] || D[i - k][j]) break; if (c1[i - k][j] > k) s += 1; } for (int k = 1;; k++) { if (i + k >= n || j + k >= m || j - k < 0 || D[i][j + k] || D[i][j - k]) break; if (c0[i][j - k] > k && c1[i][j + k] > k) s += 1; } for (int k = 1;; k++) { if (i - k < 0 || j + k >= m || j - k < 0 || D[i][j + k] || D[i][j - k]) break; if (c0[i - k][j] > k && c1[i - k][j] > k) s += 1; } for (int k = 1;; k++) { if (i - k < 0 || i + k >= n || j + k >= m || D[i - k][j] || D[i + k][j]) break; if (c0[i - k][j] > k && c1[i][j + k] > k) s += 1; } for (int k = 1;; k++) { if (i - k < 0 || i + k >= n || j - k >= m || D[i - k][j] || D[i + k][j]) break; if (c0[i][j - k] > k && c1[i - k][j] > k) s += 1; } } cout << s << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, i; while (scanf( %lld%lld , &n, &k) != EOF) { long long a[k + 1]; vector<pair<long long, long long> > v; for (i = 0; i < k; i++) { cin >> a[i], v.push_back(make_pair((n % a[i]), i + 1)); } sort(v.rbegin(), v.rend()); int j = v[k - 1].second; cout << j << << (n / a[j - 1]) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const unsigned int tb[32] = {13, 0, 27, 1, 28, 18, 23, 2, 29, 21, 19, 12, 24, 9, 14, 3, 30, 26, 17, 22, 20, 11, 8, 13, 25, 16, 10, 7, 15, 6, 5, 4}; int n, m, tot; priority_queue<long long, std::vector<long long>, std::greater<long long> > q1, q2, q3; void calc(priority_queue<long long, std::vector<long long>, std::greater<long long> >& q, long long& ans) { while (q.size() > 1) { if (q.size() >= 3) { long long x = q.top(); q.pop(); long long y = q.top(); q.pop(); long long z = q.top(); q.pop(); ans += x + y + z; q.push(x + y + z); } else { ans += q.top(); q.pop(); ans += q.top(); } } } int main() { int T = 1; for (int ci = 1; ci <= T; ++ci) { scanf( %d , &n); for (int i = 0; i < n; ++i) { int x; scanf( %d , &x); q1.push(x); q2.push(x); q3.push(x); } long long ans1 = 0, ans2 = 0, ans3 = 0; if (q1.size() >= 2) { int x = q1.top(); q1.pop(); int y = q1.top(); q1.pop(); ans1 = x + y; q1.push(x + y); } if (q2.size() >= 4) { int x = q2.top(); q2.pop(); int y = q2.top(); q2.pop(); ans2 = x + y; int u = q2.top(); q2.pop(); int v = q2.top(); q2.pop(); ans2 += u + v; q2.push(x + y); q2.push(u + v); } calc(q1, ans1); calc(q2, ans2); calc(q3, ans3); long long ans = min(min(ans1, ans2), ans3); cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> ostream& prnt(ostream& out, T v) { out << v.size() << n ; for (auto e : v) out << e << ; return out; } template <class T> ostream& operator<<(ostream& out, vector<T> v) { return prnt(out, v); } template <class T> ostream& operator<<(ostream& out, set<T> v) { return prnt(out, v); } template <class T1, class T2> ostream& operator<<(ostream& out, map<T1, T2> v) { return prnt(out, v); } template <class T1, class T2> ostream& operator<<(ostream& out, pair<T1, T2> p) { return out << ( << p.first << << p.second << ) ; } const int N = 100100; const int MOD = 666013; int n, k, m, g[N], ans, s, a, b; int main() { ios_base::sync_with_stdio(false); cin >> n >> s; for (int i = 1; i < n; i++) { cin >> a >> b; g[a]++; g[b]++; } for (int i = 1; i <= n; i++) if (g[i] == 1) ans++; cout << fixed << setprecision(7); cout << 2. * s / ans << n ; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100500; const int infi = (1 << 30); const long long infl = (1LL << 62); const double eps = 1e-9; const long long mod = 1000000007LL; const double pi = acos(-1.0); int n, k; int a[maxn], c[maxn]; int main() { cin >> n >> k; for (int i = 1; i < n; i++) a[i] = 1; a[0] = 0; for (int i = 0; i < k; i++) { for (int j = 0; j < n; j++) { int second = int(upper_bound(a, a + n, j - a[j] - 1) - a); if (second == n) second = n - 1; c[j] = second; } for (int j = 0; j < n; j++) { a[j] += a[c[j]]; } for (int j = n - 1; j >= 0; --j) cout << n - c[j] << ; cout << endl; } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pc_muxsel_mon.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ***************************************************************************
//
// File: pc_muxsel_mon.v
// Description: This monitor checks that the right mux sel is asserted for a
// thread running in the F-stage.
//
// ***************************************************************************
`include "ifu.h"
module pc_muxsel_mon(/*AUTOARG*/
// Inputs
clk, rst_l, pc_f, thr_f, t0pc_f, t1pc_f, t2pc_f, t3pc_f, inst_vld_f, dtu_fcl_running_s,
coreid
);
input clk;
input rst_l;
input [47:0] t0pc_f;
input [47:0] t1pc_f;
input [47:0] t2pc_f;
input [47:0] t3pc_f;
input [47:0] pc_f;
input inst_vld_f;
input dtu_fcl_running_s;
input [3:0] thr_f;
input [2:0] coreid;
reg enable;
initial begin
enable = 1;
if ($test$plusargs("turn_off_pc_muxsel_mon"))enable = 0;
end
always @(negedge clk)
begin
if (rst_l)
begin
if (inst_vld_f == 1'b1 && dtu_fcl_running_s == 1'b1)
begin
if (thr_f[0] == 1'b1)
begin
if (pc_f != t0pc_f)
begin
$display ("%d: C%d T0: pc_f = %h: t0pc_f = %h\n", $time, coreid, pc_f, t0pc_f);
if(enable)`MONITOR_PATH.fail("Wrong PC selected for thread 0");
else $display("Warning -> Wrong PC selected for thread 0");
end
end
else if (thr_f[1] == 1'b1)
begin
if (pc_f != t1pc_f)
begin
$display ("%d: C%d T1: pc_f = %h: t1pc_f = %h\n", $time, coreid, pc_f, t1pc_f);
if(enable)`MONITOR_PATH.fail("Wrong PC selected for thread 1");
else $display("Warning -> Wrong PC selected for thread 1");
end
end
else if (thr_f[2] == 1'b1)
begin
if (pc_f != t2pc_f)
begin
$display ("%d: C%d T2: pc_f = %h: t2pc_f = %h\n", $time, coreid, pc_f, t2pc_f);
if(enable)`MONITOR_PATH.fail("Wrong PC selected for thread 2");
else $display("Warning -> Wrong PC selected for thread 2");
end
end
else if (thr_f[3] == 1'b1)
begin
if (pc_f != t3pc_f)
begin
$display ("%d: C%d T3: pc_f = %h: t3pc_f = %h\n", $time, coreid, pc_f, t3pc_f);
if(enable)`MONITOR_PATH.fail("Wrong PC selected for thread 3");
else $display("Warning -> Wrong PC selected for thread 3");
end
end
end
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Fri Jul 15 16:37:20 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.4 2005/11/30 14:04:17 wig Exp $
// $Date: 2005/11/30 14:04:17 $
// $Log: ent_bb.v,v $
// Revision 1.4 2005/11/30 14:04:17 wig
// Updated testcase references
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No `defines in this module
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const int inf = 1e9; int n, m; int mp[3][N]; char ch[N]; struct node { int d1, d2, d3, d4; }; struct tree { int l, r; node d; } t[N * 5]; node merge(node a, node b) { node tmp; tmp.d1 = min(inf, min(a.d1 + b.d1, a.d2 + b.d3) + 1); tmp.d2 = min(inf, min(a.d1 + b.d2, a.d2 + b.d4) + 1); tmp.d3 = min(inf, min(a.d3 + b.d1, a.d4 + b.d3) + 1); tmp.d4 = min(inf, min(a.d3 + b.d2, a.d4 + b.d4) + 1); return tmp; } inline void build(int x, int l, int r) { t[x].l = l, t[x].r = r; if (l == r) { t[x].d.d1 = t[x].d.d2 = t[x].d.d3 = t[x].d.d4 = inf; if (mp[1][l]) t[x].d.d1 = 0; if (mp[2][l]) t[x].d.d4 = 0; if (mp[1][l] && mp[2][l]) t[x].d.d2 = t[x].d.d3 = 1; return; } int mid = (l + r) >> 1; build(x << 1, l, mid); build(x << 1 | 1, mid + 1, r); t[x].d = merge(t[x << 1].d, t[x << 1 | 1].d); } inline node query(int x, int l, int r) { if (l == t[x].l && r == t[x].r) return t[x].d; int mid = (t[x].l + t[x].r) >> 1; if (r <= mid) return query(x << 1, l, r); else if (l > mid) return query(x << 1 | 1, l, r); else return merge(query(x << 1, l, mid), query(x << 1 | 1, mid + 1, r)); } inline int ask(int x, int y) { int a = (x - 1) % n + 1, b = (y - 1) % n + 1; if (a > b) { swap(x, y); swap(a, b); } node tmp = query(1, a, b); if (x <= n && y <= n) return tmp.d1; if (x <= n && y > n) return tmp.d2; if (x > n && y <= n) return tmp.d3; if (x > n && y > n) return tmp.d4; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= 2; i++) { scanf( %s , ch); for (int j = 1; j <= n; j++) if (ch[j - 1] == . ) mp[i][j] = 1; } build(1, 1, n); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); int ans = ask(x, y); if (ans < inf) printf( %d n , ans); else printf( -1 n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, q, cnt, ans, w[13][100010], bi[20], g[13][100010], tot; bitset<4096> f[2 * 100010]; int main() { int i, s, a, b, j, k; for (i = bi[0] = 1; i < 20; i++) bi[i] = bi[i - 1] << 1; scanf( %d%d%d , &n, &m, &q); tot = m; for (i = 1; i <= m; i++) { for (s = 1; s <= n; s++) scanf( %d , &w[i][s]); for (s = 0; s < bi[m]; s++) if (s & bi[i - 1]) f[i][s] = 1; } for (i = 1; i <= m; i++) for (s = 1; s <= n; s++) for (k = 1; k <= m; k++) if (w[k][s] >= w[i][s]) g[i][s] |= bi[k - 1]; while (q--) { scanf( %d%d%d , &k, &a, &b); if (k == 1) f[++tot] = f[a] | f[b]; if (k == 2) f[++tot] = f[a] & f[b]; if (k == 3) { ans = 0; for (i = 1; i <= m; i++) if (f[a][g[i][b]]) ans = max(ans, w[i][b]); printf( %d n , ans); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int c[100010]; long long ans; int main() { int n, x; scanf( %d%d , &n, &x); for (int i = 1; i <= n; i++) scanf( %d , &c[i]); sort(c + 1, c + n + 1); if (n < x) { ans = 0; for (int i = 1; i <= n; i++) ans += (long long)c[i] * (x - i + 1); printf( %I64d , ans); return 0; } if (n >= x) { ans = 0; for (int i = 1; i <= x; i++) ans += (long long)i * c[x + 1 - i]; for (int i = x + 1; i <= n; i++) ans += c[i]; } printf( %I64d , ans); return 0; }
|
module test();
reg a, b;
wire a1, a2, a3, a4, a5, a6, a7;
assign (supply1, supply0) a1 = a;
tran t1(a1, a2);
tran t2(a2, a3);
tran t3(a3, a4);
tran t4(a4, a5);
tran t5(a5, a6);
tran t6(a6, a7);
wire a11, a12, a13, a14, a15, b11, b12, b13, b14, b15;
wire a21, a22, a23, a24, a25, b21, b22, b23, b24, b25;
wire a31, a32, a33, a34, a35, b31, b32, b33, b34, b35;
wire a41, a42, a43, a44, a45, b41, b42, b43, b44, b45;
wire a51, a52, a53, a54, a55, b51, b52, b53, b54, b55;
assign (supply1, supply0) a11 = a, b11 = b;
assign (supply1, strong0) a12 = a, b12 = b;
assign (supply1, pull0) a13 = a, b13 = b;
assign (supply1, weak0) a14 = a, b14 = b;
assign (supply1, highz0) a15 = a, b15 = b;
assign (strong1, supply0) a21 = a, b21 = b;
assign (strong1, strong0) a22 = a, b22 = b;
assign (strong1, pull0) a23 = a, b23 = b;
assign (strong1, weak0) a24 = a, b24 = b;
assign (strong1, highz0) a25 = a, b25 = b;
assign ( pull1, supply0) a31 = a, b31 = b;
assign ( pull1, strong0) a32 = a, b32 = b;
assign ( pull1, pull0) a33 = a, b33 = b;
assign ( pull1, weak0) a34 = a, b34 = b;
assign ( pull1, highz0) a35 = a, b35 = b;
assign ( weak1, supply0) a41 = a, b41 = b;
assign ( weak1, strong0) a42 = a, b42 = b;
assign ( weak1, pull0) a43 = a, b43 = b;
assign ( weak1, weak0) a44 = a, b44 = b;
assign ( weak1, highz0) a45 = a, b45 = b;
assign ( highz1, supply0) a51 = a, b51 = b;
assign ( highz1, strong0) a52 = a, b52 = b;
assign ( highz1, pull0) a53 = a, b53 = b;
assign ( highz1, weak0) a54 = a, b54 = b;
tran t11(a11, b11);
tran t12(a12, b12);
tran t13(a13, b13);
tran t14(a14, b14);
tran t15(a15, b15);
tran t21(a21, b21);
tran t22(a22, b22);
tran t23(a23, b23);
tran t24(a24, b24);
tran t25(a25, b25);
tran t31(a31, b31);
tran t32(a32, b32);
tran t33(a33, b33);
tran t34(a34, b34);
tran t35(a35, b35);
tran t41(a41, b41);
tran t42(a42, b42);
tran t43(a43, b43);
tran t44(a44, b44);
tran t45(a45, b45);
tran t51(a51, b51);
tran t52(a52, b52);
tran t53(a53, b53);
tran t54(a54, b54);
tran t55(a55, b55);
task display_strengths;
input ta, tb;
begin
a = ta;
b = tb;
#1;
$display("a = %b b = %b", a, b);
$display("a1(%v) a2(%v) a3(%v) a4(%v) a5(%v) a6(%v) a7(%v)", a1, a2, a3, a4, a5, a6, a7);
$display("t11(%v %v) t12(%v %v) t13(%v %v) t14(%v %v) t15(%v %v)", a11, b11, a12, b12, a13, b13, a14, b14, a15, b15);
$display("t21(%v %v) t22(%v %v) t23(%v %v) t24(%v %v) t25(%v %v)", a21, b21, a22, b22, a23, b23, a24, b24, a25, b25);
$display("t31(%v %v) t32(%v %v) t33(%v %v) t34(%v %v) t35(%v %v)", a31, b31, a32, b32, a33, b33, a34, b34, a35, b35);
$display("t41(%v %v) t42(%v %v) t43(%v %v) t44(%v %v) t45(%v %v)", a41, b41, a42, b42, a43, b43, a44, b44, a45, b45);
$display("t51(%v %v) t52(%v %v) t53(%v %v) t54(%v %v) t55(%v %v)", a51, b51, a52, b52, a53, b53, a54, b54, a55, b55);
end
endtask
initial begin
display_strengths(1'bz, 1'bz);
display_strengths(1'bx, 1'bz);
display_strengths(1'b0, 1'bz);
display_strengths(1'b1, 1'bz);
display_strengths(1'bz, 1'bx);
display_strengths(1'bx, 1'bx);
display_strengths(1'b0, 1'bx);
display_strengths(1'b1, 1'bx);
display_strengths(1'bz, 1'b0);
display_strengths(1'bx, 1'b0);
display_strengths(1'b0, 1'b0);
display_strengths(1'b1, 1'b0);
display_strengths(1'bz, 1'b1);
display_strengths(1'bx, 1'b1);
display_strengths(1'b0, 1'b1);
display_strengths(1'b1, 1'b1);
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring unsinged divider ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_uu.v,v 1.3 2002-10-31 12:52:55 rherveille Exp $
//
// $Date: 2002-10-31 12:52:55 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/23 09:07:03 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module div_uu(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width -1:0] z; // divident
input [d_width -1:0] d; // divisor
output [d_width -1:0] q; // quotient
reg [d_width-1:0] q;
output [d_width -1:0] s; // remainder
reg [d_width-1:0] s;
output div0;
reg div0;
output ovf;
reg ovf;
//
// functions
//
function [z_width:0] gen_s;
input [z_width:0] si;
input [z_width:0] di;
begin
if(si[z_width])
gen_s = {si[z_width-1:0], 1'b0} + di;
else
gen_s = {si[z_width-1:0], 1'b0} - di;
end
endfunction
function [d_width-1:0] gen_q;
input [d_width-1:0] qi;
input [z_width:0] si;
begin
gen_q = {qi[d_width-2:0], ~si[z_width]};
end
endfunction
function [d_width-1:0] assign_s;
input [z_width:0] si;
input [z_width:0] di;
reg [z_width:0] tmp;
begin
if(si[z_width])
tmp = si + di;
else
tmp = si;
assign_s = tmp[z_width-1:z_width-4];
end
endfunction
//
// variables
//
reg [d_width-1:0] q_pipe [d_width-1:0];
reg [z_width:0] s_pipe [d_width:0];
reg [z_width:0] d_pipe [d_width:0];
reg [d_width:0] div0_pipe, ovf_pipe;
//
// perform parameter checks
//
// synopsys translate_off
initial
begin
if(d_width !== z_width / 2)
$display("div.v parameter error (d_width != z_width/2).");
end
// synopsys translate_on
integer n0, n1, n2, n3;
// generate divisor (d) pipe
always @(d)
d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
always @(posedge clk)
if(ena)
for(n0=1; n0 <= d_width; n0=n0+1)
d_pipe[n0] <= #1 d_pipe[n0-1];
// generate internal remainder pipe
always @(z)
s_pipe[0] <= z;
always @(posedge clk)
if(ena)
for(n1=1; n1 <= d_width; n1=n1+1)
s_pipe[n1] <= #1 gen_s(s_pipe[n1-1], d_pipe[n1-1]);
// generate quotient pipe
always @(posedge clk)
q_pipe[0] <= #1 0;
always @(posedge clk)
if(ena)
for(n2=1; n2 < d_width; n2=n2+1)
q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]);
// flags (divide_by_zero, overflow)
always @(z or d)
begin
ovf_pipe[0] <= !(z[z_width-1:d_width] < d);
div0_pipe[0] <= ~|d;
end
always @(posedge clk)
if(ena)
for(n3=1; n3 <= d_width; n3=n3+1)
begin
ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
div0_pipe[n3] <= #1 div0_pipe[n3-1];
end
// assign outputs
always @(posedge clk)
if(ena)
ovf <= #1 ovf_pipe[d_width];
always @(posedge clk)
if(ena)
div0 <= #1 div0_pipe[d_width];
always @(posedge clk)
if(ena)
q <= #1 gen_q(q_pipe[d_width-1], s_pipe[d_width]);
always @(posedge clk)
if(ena)
s <= #1 assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(0); cin.tie(NULL); long long int T; cin >> T; while (T--) { long long int n; cin >> n; long long int a[n]; for (long long int i = 0; i < n; i++) cin >> a[i]; if (a[n - 1] > a[0]) cout << YES << n ; else cout << NO << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PS_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DFF_PS_SYMBOL_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$PS (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PS_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long M = 1000000007; const double pi = acos(-1); const int N = 2e5 + 10; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); ; long long n, k, m, d, q = 1, ans = 0; cin >> n >> k >> m >> d; for (long long i = 1; i < d + 1; i++) { long long mx1 = m; long long mx2 = n / q; long long w = min(mx1, mx2) * i; ans = max(ans, w); q += k; if (q > n) break; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, a[55], b[55], i, amin, bmin; long long int sum; scanf( %d , &t); while (t--) { scanf( %d , &n); amin = 0x3f3f3f3f; for (i = 0; i < n; i++) { scanf( %d , &a[i]); if (amin > a[i]) amin = a[i]; } bmin = 0x3f3f3f3f; for (i = 0; i < n; i++) { scanf( %d , &b[i]); if (bmin > b[i]) bmin = b[i]; } sum = 0; for (i = 0; i < n; i++) { int x = a[i] - amin; int y = b[i] - bmin; sum += max(x, y); } printf( %lld n , sum); } return 0; }
|
// $Id: tcnode_wrap.v 1661 2009-11-02 05:01:21Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// wrapper around pseudo-node
module tcnode_wrap
(clk, reset, router_address, port_id, flit_ctrl_out, flit_data_out,
flow_ctrl_in, flit_ctrl_in, flit_data_in, flow_ctrl_out, cfg_addr_prefixes,
cfg_req, cfg_write, cfg_addr, cfg_write_data, cfg_read_data, cfg_done,
error);
`include "c_functions.v"
`include "c_constants.v"
`include "vcr_constants.v"
`include "parameters.v"
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// total number of routers
localparam num_routers
= (num_nodes + num_nodes_per_router - 1) / num_nodes_per_router;
// number of routers in each dimension
localparam num_routers_per_dim = croot(num_routers, num_dimensions);
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// width required to select individual router in entire network
localparam router_addr_width = num_dimensions * dim_addr_width;
// connectivity within each dimension
localparam connectivity
= (topology == `TOPOLOGY_MESH) ?
`CONNECTIVITY_LINE :
(topology == `TOPOLOGY_TORUS) ?
`CONNECTIVITY_RING :
(topology == `TOPOLOGY_FBFLY) ?
`CONNECTIVITY_FULL :
-1;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// width of flit control signals
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + vc_idx_width + 1 + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + vc_idx_width + 1) :
-1;
// width of flow control signals
localparam flow_ctrl_width = 1 + vc_idx_width;
// select set of feedback polynomials used for LFSRs
parameter lfsr_index = 0;
// number of bits in address that are considered base address
parameter cfg_addr_prefix_width = 10;
// width of register selector part of control register address
parameter cfg_addr_suffix_width = 6;
// width of configuration bus addresses
localparam cfg_addr_width = cfg_addr_prefix_width + cfg_addr_suffix_width;
// number of distinct base addresses to which this node replies
parameter num_cfg_addr_prefixes = 2;
// width of configuration bus datapath
parameter cfg_data_width = 32;
// width of run cycle counter
parameter num_packets_width = 16;
// width of arrival rate LFSR
parameter arrival_rv_width = 16;
// width of message class selection LFSR
parameter mc_idx_rv_width = 4;
// width of resource class selection LFSR
parameter rc_idx_rv_width = 4;
// width of payload length selection LFSR
parameter plength_idx_rv_width = 4;
// number of selectable payload lengths
parameter num_plength_vals = 2;
// width of register that holds the number of outstanding packets
parameter packet_count_width = 8;
input clk;
input reset;
// current node's address
input [0:router_addr_width-1] router_address;
// router port to which this node is attached
input [0:port_idx_width-1] port_id;
// control signals for outgoing flit
output [0:flit_ctrl_width-1] flit_ctrl_out;
wire [0:flit_ctrl_width-1] flit_ctrl_out;
// flit data for outgoing flit
output [0:flit_data_width-1] flit_data_out;
wire [0:flit_data_width-1] flit_data_out;
// incoming flow control signals
input [0:flow_ctrl_width-1] flow_ctrl_in;
// control signals for incoming flit
input [0:flit_ctrl_width-1] flit_ctrl_in;
// flit data for incoming flit
input [0:flit_data_width-1] flit_data_in;
// outgoing flow control signals
output [0:flow_ctrl_width-1] flow_ctrl_out;
wire [0:flow_ctrl_width-1] flow_ctrl_out;
// address prefixes assigned to this node
input [0:num_cfg_addr_prefixes*cfg_addr_prefix_width-1] cfg_addr_prefixes;
// config register access pending
input cfg_req;
// config register access is write access
input cfg_write;
// select config register to access
input [0:cfg_addr_width-1] cfg_addr;
// data to be written to selected config register for write accesses
input [0:cfg_data_width-1] cfg_write_data;
// contents of selected config register for read accesses
output [0:cfg_data_width-1] cfg_read_data;
wire [0:cfg_data_width-1] cfg_read_data;
// config register access complete
output cfg_done;
wire cfg_done;
// internal error condition detected
output error;
wire error;
tc_node_mac
#(.num_flit_buffers(num_flit_buffers),
.num_header_buffers(num_header_buffers),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.routing_type(routing_type),
.dim_order(dim_order),
.lfsr_index(lfsr_index),
.cfg_addr_prefix_width(cfg_addr_prefix_width),
.cfg_addr_suffix_width(cfg_addr_suffix_width),
.num_cfg_addr_prefixes(num_cfg_addr_prefixes),
.cfg_data_width(cfg_data_width),
.num_packets_width(num_packets_width),
.arrival_rv_width(arrival_rv_width),
.mc_idx_rv_width(mc_idx_rv_width),
.rc_idx_rv_width(rc_idx_rv_width),
.plength_idx_rv_width(plength_idx_rv_width),
.num_plength_vals(num_plength_vals),
.packet_count_width(packet_count_width),
.reset_type(reset_type))
node
(.clk(clk),
.reset(reset),
.router_address(router_address),
.port_id(port_id),
.flit_ctrl_out(flit_ctrl_out),
.flit_data_out(flit_data_out),
.flow_ctrl_in(flow_ctrl_in),
.flit_ctrl_in(flit_ctrl_in),
.flit_data_in(flit_data_in),
.flow_ctrl_out(flow_ctrl_out),
.cfg_addr_prefixes(cfg_addr_prefixes),
.cfg_req(cfg_req),
.cfg_write(cfg_write),
.cfg_addr(cfg_addr),
.cfg_write_data(cfg_write_data),
.cfg_read_data(cfg_read_data),
.cfg_done(cfg_done),
.error(error));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_SYMBOL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_SYMBOL_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_SYMBOL_V
|
`timescale 1ns/1ps
module test();
reg clock, reset;
sopc sopc(
.clock(clock),
.reset(reset)
);
always #1 clock = ~clock;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
$dumpvars(0, sopc.cpu.register.storage[1]);
$readmemh("rom.txt", sopc.rom.storage);
clock = 1'b0;
reset = 1'b1;
#20 reset = 1'b0;
#10 `AR(1, 32'h00000005);
#2 `AR(1, 32'h00000004);
#2 `AR(1, 32'h00000004);
#2 `AR(1, 32'h00000004);
#2 `AR(1, 32'h00000004);
#2 `AR(1, 32'h00000004);
#2 `AR(1, 32'h00000003);
#2 `AR(1, 32'h00000003);
#2 `AR(1, 32'h00000003);
#2 `AR(1, 32'h00000003);
#2 `AR(1, 32'h00000003);
#2 `AR(1, 32'h00000002);
#2 `AR(1, 32'h00000002);
#2 `AR(1, 32'h00000002);
#2 `AR(1, 32'h00000002);
#2 `AR(1, 32'h00000002);
#2 `AR(1, 32'h00000001);
#2 `AR(1, 32'h00000001);
#2 `AR(1, 32'h00000001);
#2 `AR(1, 32'h00000001);
#2 `AR(1, 32'h00000001);
#2 `AR(1, 32'h00000000);
#2 `AR(1, 32'h00000000);
#2 `AR(1, 32'h00000000);
#2 `AR(1, 32'h00000001);
#2 `AR(1, 32'h00000002);
`PASS;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 10; int n; set<pair<pair<int, int>, int> > a; int ans[MAXN]; inline pair<pair<int, int>, int> mpi(int a, int b, int c) { return make_pair(make_pair(a, b), c); } void exit() { cout << Impossible ; exit(0); } int main() { cin >> n; for (int i = 1; i <= n; i++) { pair<pair<int, int>, int> x; scanf( %d , &x.first.second); x.first.first = x.first.second % 3; x.second = i; a.insert(x); } a.insert(mpi(1000, 1000, 1000)); a.insert(mpi(-1000, -1000, -1000)); pair<pair<int, int>, int> x; int olimp = 0; for (int i = 0; i < n; i++) { set<pair<pair<int, int>, int> >::iterator it = a.lower_bound(mpi(i % 3, i - olimp, 0)); x = *it; if (i % 3 != x.first.first) { it--; x = *it; } if (i % 3 != x.first.first) exit(); bool flag = false; while (i - olimp + 1 < x.first.second) { it--; x = *it; flag = true; } if (x.first.second < 0 || i % 3 != x.first.first) exit(); olimp = i + 1 - x.first.second; ans[i + 1] = x.second; a.erase(it); } cout << Possible << endl; for (int i = 1; i <= n; i++) printf( %d , ans[i]); }
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } int n; vector<int> nailed; struct evn { int pos, type, num; }; vector<evn> events; bool comp(const evn& a, const evn& b) { if (a.pos == b.pos && a.type == b.type) return a.num < b.num; if (a.pos == b.pos) return a.type == 0; return a.pos < b.pos; } int main() { srand(chrono::steady_clock::now().time_since_epoch().count()); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; nailed.resize(n, 0); int l, r; for (__typeof(n) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) { cin >> l >> r; if (r < l) swap(l, r); evn a, b; a.pos = l; a.num = i; a.type = 0; events.push_back(a); b.pos = r; b.num = i; b.type = 1; events.push_back(b); } sort(events.begin(), events.end(), comp); queue<int> pinned; vector<int> ans; for (auto it : events) { if (it.type) { if (nailed[it.num] == 0) { while (!pinned.empty()) { int ind = pinned.front(); nailed[ind] = 1; pinned.pop(); } nailed[it.num] = 1; ans.push_back(it.pos); } } else { pinned.push(it.num); } } cout << (int)(ans.size()) << n ; if ((int)(ans.size()) > 0) { for (auto it : ans) cout << it << ; } return 0; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ADC_ROM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module ADC_ROM (
address,
clock,
q);
input [10:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "ADC.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "ADC.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_ROM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int n, m; bool flag[21][21]; int deg[21], id[21]; vector<int> G[21]; inline int cmp(int x, int y) { return deg[x] != deg[y] ? deg[x] < deg[y] : x < y; } bool vis[21]; inline void dfs(int np) { vis[np] = 1; for (int &x : G[np]) { if (!vis[x]) { dfs(x); return; } } } int main() { scanf( %d%d , &n, &m); for (int i = 1, ti, tj; i <= m; i++) { scanf( %d%d , &ti, &tj); if (ti != tj) flag[ti][tj] = flag[tj][ti] = 1; } for (int i = 1; i <= n; i++) { id[i] = i; for (int j = 1; j <= n; j++) { if (flag[i][j]) deg[i]++, G[i].push_back(j); } } for (int i = 1; i <= n; i++) sort(G[i].begin(), G[i].end(), cmp); for (int i = 1; i <= n; i++) { memset(vis, 0, sizeof(vis)); dfs(i); int cnt = 0; for (int j = 1; j <= n; j++) cnt += vis[j]; if (cnt == n) { puts( Yes ); return 0; } } puts( No ); return 0; }
|
// Double buffering with dual-port RAM
// Uses dual-port RAM to write switches to one section, while reading another to control LEDs.
// Flip SW0 to swap the buffers.
module top (
input clk,
input [15:0] sw,
output [15:0] led,
// not used
input rx,
output tx
);
assign tx = rx; // TODO(#658): Remove this work-around
wire [4:0] addr;
wire ram_out;
wire ram_in;
RAM_SHIFTER #(
.IO_WIDTH(16),
.ADDR_WIDTH(5)
) shifter (
.clk(clk),
.in(sw),
.out(led),
.addr(addr),
.ram_out(ram_out),
.ram_in(ram_in)
);
RAM64X1D #(
.INIT(64'h96A5_96A5_96A5_96A5)
) ram0 (
.WCLK(clk),
.A5(sw[0]),
.A4(addr[4]),
.A3(addr[3]),
.A2(addr[2]),
.A1(addr[1]),
.A0(addr[0]),
.DPRA5(~sw[0]),
.DPRA4(addr[4]),
.DPRA3(addr[3]),
.DPRA2(addr[2]),
.DPRA1(addr[1]),
.DPRA0(addr[0]),
.DPO(ram_out),
.D(ram_in),
.WE(1'b1)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); ; long long t; cin >> t; while (t--) { long long n, x, m; cin >> n >> x >> m; long long c, d; long long l = x, r = x; while (m--) { cin >> c >> d; if (c <= l && d >= r) { l = c; r = d; } else if (c <= l && d <= r && d >= l) l = c; else if (l <= c && c <= r && d >= r) r = d; } cout << (r - l + 1) << n ; } return 0; }
|
`include "constants.vh"
`default_nettype none
module rrf_freelistmanager
(
input wire clk,
input wire reset,
input wire invalid1,
input wire invalid2,
input wire [1:0] comnum,
input wire prmiss,
input wire [`RRF_SEL-1:0] rrftagfix,
output wire [`RRF_SEL-1:0] rename_dst1,
output wire [`RRF_SEL-1:0] rename_dst2,
output wire allocatable,
input wire stall_DP, //= ~allocatable && ~prmiss
output reg [`RRF_SEL:0] freenum,
output reg [`RRF_SEL-1:0] rrfptr,
input wire [`RRF_SEL-1:0] comptr,
output reg nextrrfcyc
);
wire [1:0] reqnum = {1'b0, ~invalid1} + {1'b0, ~invalid2};
wire hi = (comptr > rrftagfix) ? 1'b1 : 1'b0;
wire [`RRF_SEL-1:0] rrfptr_next = rrfptr + reqnum;
assign allocatable = (freenum + comnum) < reqnum ? 1'b0 : 1'b1;
assign rename_dst1 = rrfptr;
assign rename_dst2 = rrfptr + (~invalid1 ? 1 : 0);
always @ (posedge clk) begin
if (reset) begin
freenum <= `RRF_NUM;
rrfptr <= 0;
nextrrfcyc <= 0;
end else if (prmiss) begin
rrfptr <= rrftagfix; //== prmiss_rrftag+1
freenum <= `RRF_NUM - ({hi, rrftagfix} - {1'b0, comptr});
nextrrfcyc <= 0;
end else if (stall_DP) begin
rrfptr <= rrfptr;
freenum <= freenum + comnum;
nextrrfcyc <= 0;
end else begin
rrfptr <= rrfptr_next;
freenum <= freenum + comnum - reqnum;
nextrrfcyc <= (rrfptr > rrfptr_next) ? 1'b1 : 1'b0;
end
end
endmodule // rrf_freelistmanager
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; inline int read() { int res = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -f; ch = getchar(); } while (isdigit(ch)) { res = (res << 1) + (res << 3) + (ch ^ 48); ch = getchar(); } return res * f; } const int N = 200005; int n, m, root; int ls[N], rs[N], val[N], key[N], cnt[N], add[N], ans[N]; inline void pushdown(int v) { if (add[v]) { add[ls[v]] += add[v]; add[rs[v]] += add[v]; val[ls[v]] += add[v]; val[rs[v]] += add[v]; add[v] = 0; } if (ans[v]) { ans[ls[v]] += ans[v]; ans[rs[v]] += ans[v]; cnt[ls[v]] += ans[v]; cnt[rs[v]] += ans[v]; ans[v] = 0; } } void split(int k, int &x, int &y, int v) { if (!k) { x = y = 0; return; } pushdown(k); if (val[k] < v) x = k, split(rs[k], rs[x], y, v); else y = k, split(ls[k], x, ls[y], v); } int merge(int x, int y) { if (!x || !y) return x + y; if (key[x] < key[y]) { pushdown(x); rs[x] = merge(rs[x], y); return x; } else { pushdown(y); ls[y] = merge(x, ls[y]); return y; } } int insert(int x, int y) { int rt1 = 0, rt2 = 0; split(x, rt1, rt2, val[y]); rt1 = merge(rt1, y); x = merge(rt1, rt2); return x; } int build(int v, int y) { if (!v) return y; pushdown(v); y = build(ls[v], y); y = build(rs[v], y); ls[v] = rs[v] = 0; return insert(y, v); } void dfs(int v) { if (!v) return; pushdown(v); dfs(ls[v]); dfs(rs[v]); } pair<int, int> a[N]; int main() { scanf( %d , &n); for (int i = 1, c, q; i <= n; i++) { scanf( %d%d , &c, &q); a[i] = make_pair(-q, c); } sort(a + 1, a + 1 + n); scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d , &val[i]); key[i] = rand(); root = insert(root, i); } for (int i = 1; i <= n; i++) { int c = a[i].second; int r1 = 0, r2 = 0, r3 = 0, r4 = 0; split(root, r1, r2, c); val[r2] -= c; add[r2] -= c; cnt[r2]++; ans[r2]++; split(r2, r3, r4, c - 1); r1 = build(r3, r1); root = merge(r1, r4); } dfs(root); for (int i = 1; i <= m; i++) printf( %d , cnt[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; typedef struct _lap { int p; int qu; } lap; bool cmp(const lap &a, const lap &b) { return a.p < b.p; } void remain() { int n; cin >> n; vector<lap> laps; for (int i = 0; i < n; ++i) { lap x; cin >> x.p >> x.qu; laps.push_back(x); } sort(laps.begin(), laps.end(), cmp); enum RE { HAPPY_ALEX, POOR_ALEX }; RE re = POOR_ALEX; for (int i = 0; i < laps.size() - 1; ++i) { if (!(laps[i].qu < laps[i + 1].qu)) { re = HAPPY_ALEX; break; } } if (re == HAPPY_ALEX) cout << Happy Alex ; else cout << Poor Alex ; } int main() { remain(); return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { cin.tie(0); cin.sync_with_stdio(0); int n; cin >> n; vector<string> a(2 * n - 2); map<string, vector<int>> m; for (int i = 0; i < 2 * n - 2; ++i) { cin >> a[i]; m[a[i]].emplace_back(i); } int x = -1, y = -1; for (int i = 0; i < 2 * n - 2; ++i) { auto const& s = a[i]; if ((int)s.size() == n - 1) { if (x == -1) x = i; else y = i; } } string ans(2 * n - 2, S ); string u = a[x]; string v = a[y]; map<string, int> cc1, cc2; for (int i = 0; i + 1 < n; ++i) { ++cc1[u.substr(0, i + 1)]; ++cc1[v.substr(i, n - 1 - i)]; ++cc2[v.substr(0, i + 1)]; ++cc2[u.substr(i, n - 1 - i)]; } bool can1 = true; bool can2 = true; for (auto const& [x, f] : m) { can1 &= (cc1[x] == int(f.size())); can2 &= (cc2[x] == int(f.size())); } if (not can1) { swap(cc1, cc2); swap(u, v); } for (int i = 0; i + 1 < n; ++i) { auto p1 = u.substr(0, i + 1); auto s1 = v.substr(i, n - 1 - i); int idx1 = m[p1].back(); m[p1].pop_back(); int idx2 = m[s1].back(); m[s1].pop_back(); ans[idx1] = P ; ans[idx2] = S ; } cout << ans; }
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#include <bits/stdc++.h> using namespace std; struct node { int x, num; } s[100009]; int mark[100009]; int cmp(node a, node b) { return a.x < b.x; } int main() { int n, m; while (scanf( %d %d , &n, &m) == 2) { int l, h; scanf( %d %d , &l, &h); for (int i = 0; i < n; i++) { int a, b; scanf( %d %d , &a, &b); s[i].x = a * l + b * h; s[i].num = i + 1; } sort(s, s + n, cmp); int ans = 0; int k = 0; for (int i = 0; i < n; i++) { m -= s[i].x; if (m < 0) break; ans++; mark[k++] = s[i].num; } printf( %d n , ans); for (int i = 0; i < ans; i++) { if (i == 0) printf( %d , mark[i]); else printf( %d , mark[i]); } printf( n ); } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_4_V
`define SKY130_FD_SC_LP__AND3_4_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_4_V
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#include <bits/stdc++.h> using namespace std; typedef pair<int, int> pii; typedef long long ll; typedef unsigned long long ull; template <typename T> bool umax(T& a, const T& b) { return b <= a ? false : (a = b, true); } template <typename T> bool umin(T& a, const T& b) { return b >= a ? false : (a = b, true); } template <typename T> void V2A(T a[], const vector<T>& b) { for (int i = 0; i < b.size(); i++) a[i] = b[i]; } template <typename T> void A2V(vector<T>& a, const T b[]) { for (int i = 0; i < a.size(); i++) a[i] = b[i]; } const double PI = acos(-1.0); const int INF = 1e9 + 7; const int maxn = 2e3 + 7; bool plot[maxn][maxn]; int r[maxn][maxn]; int n, m, k; int check(int row, int col) { if (col >= 0 && col < m) return true; return false; } int main() { cin >> n >> m >> k; for (int i = 0; i < k; i++) { int x, y; scanf( %d%d , &x, &y); x--; y--; if (!plot[x][y]) { printf( %d %d n , x + 1, y + 1); plot[x][y] = true; continue; } for (int d = 1; d <= 3; d++) { int Max = min(n, x + d + 1); for (int row = max(0, x - d); row < Max; row++) { int t = d - abs(x - row), col1 = y - t, col2 = y + t; if (check(row, col1)) umax(r[x][y], r[row][col1] - d); if (check(row, col2)) umax(r[x][y], r[row][col2] - d); } } for (int d = r[x][y] + 1;; d++) { int Max = min(n, x + d + 1); bool ok = false; for (int row = max(0, x - d); row < Max; row++) { int t = d - abs(x - row), col1 = y - t, col2 = y + t; if (check(row, col1) && !plot[row][col1]) { ok = true; printf( %d %d n , row + 1, col1 + 1); plot[row][col1] = true; break; } if (check(row, col2) && !plot[row][col2]) { ok = true; printf( %d %d n , row + 1, col2 + 1); plot[row][col2] = true; break; } } if (ok) { r[x][y] = d - 1; break; } } } return 0; }
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// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_fifo_index (clock, reset, enable, push, pop, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter depth = 1;
parameter push_width = 1;
parameter pop_width = 1;
parameter simultaneous_push_pop = 1; // Note: different position than in assert_fifo_index
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [push_width-1:0] push;
input [pop_width-1:0] pop;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_FIFO_INDEX";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (depth==0) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value for parameter depth which must be set to value greater than 0");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_fifo_index_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_fifo_index_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_fifo_index_psl_logic.v"
`else
`endmodule // ovl_fifo_index
`endif
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const double EPS = 1e-8; const int mod = 1e9 + 7; const int N = 1e6 + 10; const long long INF = 1e18; long long power(long long x, long long y) { long long t = 1; while (y > 0) { if (y % 2) y -= 1, t = t * x % mod; else y /= 2, x = x * x % mod; } return t; } vector<vector<pair<int, long long>>> G; set<pair<long long, int>> s; vector<long long> dis; vector<int> par; void dijkstra(int x) { int n = G.size(); dis.resize(n); par.resize(n); for (int i = 0; i < n; ++i) { dis[i] = INF; par[i] = -1; } dis[x] = 0; for (int i = 0; i < n; ++i) s.insert(make_pair(dis[i], i)); while (!s.empty()) { auto curr = s.begin(); int v = curr->second, val = curr->first; s.erase(s.begin()); for (auto u : G[v]) { if (dis[u.first] > dis[v] + u.second) { s.erase(make_pair(dis[u.first], u.first)); dis[u.first] = dis[v] + u.second; par[u.first] = v; s.insert(make_pair(dis[u.first], u.first)); } } } } int main() { int n, m; scanf( %d%d , &n, &m); G.resize(n); for (int i = 0; i < m; ++i) { int x, y; long long z; scanf( %d%d%lld , &x, &y, &z); x--, y--; G[x].push_back(make_pair(y, z)); G[y].push_back(make_pair(x, z)); } dijkstra(0); if (dis[n - 1] == INF) printf( -1 n ); else { stack<int> ans; ans.push(n - 1); int curr = n - 1; while (curr != 0) { curr = par[curr]; ans.push(curr); } while (!ans.empty()) { int x = ans.top() + 1; ans.pop(); printf( %d , x); } printf( n ); } return 0; }
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//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// client_request_get O 77 reg
// RDY_client_request_get O 1 reg
// RDY_client_response_put O 1 reg
// RDY_server_request_put O 1 reg
// server_response_get O 65 reg
// RDY_server_response_get O 1 reg
// trace_data_out_get O 427 reg
// RDY_trace_data_out_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// client_response_put I 65 reg
// server_request_put I 77 reg
// EN_client_response_put I 1
// EN_server_request_put I 1
// EN_client_request_get I 1
// EN_server_response_get I 1
// EN_trace_data_out_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkDM_CSR_Tap(CLK,
RST_N,
EN_client_request_get,
client_request_get,
RDY_client_request_get,
client_response_put,
EN_client_response_put,
RDY_client_response_put,
server_request_put,
EN_server_request_put,
RDY_server_request_put,
EN_server_response_get,
server_response_get,
RDY_server_response_get,
EN_trace_data_out_get,
trace_data_out_get,
RDY_trace_data_out_get);
input CLK;
input RST_N;
// actionvalue method client_request_get
input EN_client_request_get;
output [76 : 0] client_request_get;
output RDY_client_request_get;
// action method client_response_put
input [64 : 0] client_response_put;
input EN_client_response_put;
output RDY_client_response_put;
// action method server_request_put
input [76 : 0] server_request_put;
input EN_server_request_put;
output RDY_server_request_put;
// actionvalue method server_response_get
input EN_server_response_get;
output [64 : 0] server_response_get;
output RDY_server_response_get;
// actionvalue method trace_data_out_get
input EN_trace_data_out_get;
output [426 : 0] trace_data_out_get;
output RDY_trace_data_out_get;
// signals for module outputs
wire [426 : 0] trace_data_out_get;
wire [76 : 0] client_request_get;
wire [64 : 0] server_response_get;
wire RDY_client_request_get,
RDY_client_response_put,
RDY_server_request_put,
RDY_server_response_get,
RDY_trace_data_out_get;
// ports of submodule f_req_in
wire [76 : 0] f_req_in$D_IN, f_req_in$D_OUT;
wire f_req_in$CLR,
f_req_in$DEQ,
f_req_in$EMPTY_N,
f_req_in$ENQ,
f_req_in$FULL_N;
// ports of submodule f_req_out
wire [76 : 0] f_req_out$D_IN, f_req_out$D_OUT;
wire f_req_out$CLR,
f_req_out$DEQ,
f_req_out$EMPTY_N,
f_req_out$ENQ,
f_req_out$FULL_N;
// ports of submodule f_rsp
wire [64 : 0] f_rsp$D_IN, f_rsp$D_OUT;
wire f_rsp$CLR, f_rsp$DEQ, f_rsp$EMPTY_N, f_rsp$ENQ, f_rsp$FULL_N;
// ports of submodule f_trace_data
wire [426 : 0] f_trace_data$D_IN, f_trace_data$D_OUT;
wire f_trace_data$CLR,
f_trace_data$DEQ,
f_trace_data$EMPTY_N,
f_trace_data$ENQ,
f_trace_data$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_request,
CAN_FIRE_client_request_get,
CAN_FIRE_client_response_put,
CAN_FIRE_server_request_put,
CAN_FIRE_server_response_get,
CAN_FIRE_trace_data_out_get,
WILL_FIRE_RL_request,
WILL_FIRE_client_request_get,
WILL_FIRE_client_response_put,
WILL_FIRE_server_request_put,
WILL_FIRE_server_response_get,
WILL_FIRE_trace_data_out_get;
// remaining internal signals
wire [63 : 0] x__h577;
// actionvalue method client_request_get
assign client_request_get = f_req_out$D_OUT ;
assign RDY_client_request_get = f_req_out$EMPTY_N ;
assign CAN_FIRE_client_request_get = f_req_out$EMPTY_N ;
assign WILL_FIRE_client_request_get = EN_client_request_get ;
// action method client_response_put
assign RDY_client_response_put = f_rsp$FULL_N ;
assign CAN_FIRE_client_response_put = f_rsp$FULL_N ;
assign WILL_FIRE_client_response_put = EN_client_response_put ;
// action method server_request_put
assign RDY_server_request_put = f_req_in$FULL_N ;
assign CAN_FIRE_server_request_put = f_req_in$FULL_N ;
assign WILL_FIRE_server_request_put = EN_server_request_put ;
// actionvalue method server_response_get
assign server_response_get = f_rsp$D_OUT ;
assign RDY_server_response_get = f_rsp$EMPTY_N ;
assign CAN_FIRE_server_response_get = f_rsp$EMPTY_N ;
assign WILL_FIRE_server_response_get = EN_server_response_get ;
// actionvalue method trace_data_out_get
assign trace_data_out_get = f_trace_data$D_OUT ;
assign RDY_trace_data_out_get = f_trace_data$EMPTY_N ;
assign CAN_FIRE_trace_data_out_get = f_trace_data$EMPTY_N ;
assign WILL_FIRE_trace_data_out_get = EN_trace_data_out_get ;
// submodule f_req_in
FIFO2 #(.width(32'd77), .guarded(32'd1)) f_req_in(.RST(RST_N),
.CLK(CLK),
.D_IN(f_req_in$D_IN),
.ENQ(f_req_in$ENQ),
.DEQ(f_req_in$DEQ),
.CLR(f_req_in$CLR),
.D_OUT(f_req_in$D_OUT),
.FULL_N(f_req_in$FULL_N),
.EMPTY_N(f_req_in$EMPTY_N));
// submodule f_req_out
FIFO2 #(.width(32'd77), .guarded(32'd1)) f_req_out(.RST(RST_N),
.CLK(CLK),
.D_IN(f_req_out$D_IN),
.ENQ(f_req_out$ENQ),
.DEQ(f_req_out$DEQ),
.CLR(f_req_out$CLR),
.D_OUT(f_req_out$D_OUT),
.FULL_N(f_req_out$FULL_N),
.EMPTY_N(f_req_out$EMPTY_N));
// submodule f_rsp
FIFO2 #(.width(32'd65), .guarded(32'd1)) f_rsp(.RST(RST_N),
.CLK(CLK),
.D_IN(f_rsp$D_IN),
.ENQ(f_rsp$ENQ),
.DEQ(f_rsp$DEQ),
.CLR(f_rsp$CLR),
.D_OUT(f_rsp$D_OUT),
.FULL_N(f_rsp$FULL_N),
.EMPTY_N(f_rsp$EMPTY_N));
// submodule f_trace_data
FIFO2 #(.width(32'd427), .guarded(32'd1)) f_trace_data(.RST(RST_N),
.CLK(CLK),
.D_IN(f_trace_data$D_IN),
.ENQ(f_trace_data$ENQ),
.DEQ(f_trace_data$DEQ),
.CLR(f_trace_data$CLR),
.D_OUT(f_trace_data$D_OUT),
.FULL_N(f_trace_data$FULL_N),
.EMPTY_N(f_trace_data$EMPTY_N));
// rule RL_request
assign CAN_FIRE_RL_request =
f_req_in$EMPTY_N && f_req_out$FULL_N &&
(!f_req_in$D_OUT[76] || f_trace_data$FULL_N) ;
assign WILL_FIRE_RL_request = CAN_FIRE_RL_request ;
// submodule f_req_in
assign f_req_in$D_IN = server_request_put ;
assign f_req_in$ENQ = EN_server_request_put ;
assign f_req_in$DEQ = CAN_FIRE_RL_request ;
assign f_req_in$CLR = 1'b0 ;
// submodule f_req_out
assign f_req_out$D_IN = f_req_in$D_OUT ;
assign f_req_out$ENQ = CAN_FIRE_RL_request ;
assign f_req_out$DEQ = EN_client_request_get ;
assign f_req_out$CLR = 1'b0 ;
// submodule f_rsp
assign f_rsp$D_IN = client_response_put ;
assign f_rsp$ENQ = EN_client_response_put ;
assign f_rsp$DEQ = EN_server_response_get ;
assign f_rsp$CLR = 1'b0 ;
// submodule f_trace_data
assign f_trace_data$D_IN =
{ 235'h0EAAAAAAAAAAAAAAA955555554AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
x__h577,
f_req_in$D_OUT[63:0],
64'hAAAAAAAAAAAAAAAA } ;
assign f_trace_data$ENQ = WILL_FIRE_RL_request && f_req_in$D_OUT[76] ;
assign f_trace_data$DEQ = EN_trace_data_out_get ;
assign f_trace_data$CLR = 1'b0 ;
// remaining internal signals
assign x__h577 = { 52'd0, f_req_in$D_OUT[75:64] } ;
endmodule // mkDM_CSR_Tap
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#include <bits/stdc++.h> using namespace std; using ll = long long; struct dreapta { ll a, b; ll operator()(ll x) { return a * x + b; } }; bool useless(dreapta a, dreapta b, dreapta c) { assert(a.a >= b.a && b.a >= c.a); return (double)(b.b - a.b) / (a.a - b.a) > (double)(c.b - b.b) / (b.a - c.a); } class merging_batch { deque<dreapta> buf; public: merging_batch() {} ll query(ll x) { ll i = 0; for (ll step = 1 << 23; step; step /= 2) if (i + step < buf.size() && buf[i + step](x) <= buf[i + step - 1](x)) i += step; assert(i == buf.size() - 1 || buf[i](x) <= buf[i + 1](x)); return buf[i](x); } void add_right(dreapta x) { while (buf.size() > 1 && useless(buf.rbegin()[1], buf.back(), x)) buf.pop_back(); buf.push_back(x); } void add_left(dreapta x) { while (buf.size() > 1 && useless(x, buf[0], buf[1])) buf.pop_front(); buf.push_front(x); } void swap_with(merging_batch& rhs) { swap(buf, rhs.buf); } void merge_with(merging_batch& rhs) { if (buf.size() < rhs.buf.size()) { for (auto it = buf.rbegin(); it != buf.rend(); ++it) rhs.add_left(*it); swap(buf, rhs.buf); } else for (auto x : rhs.buf) add_right(x); } }; class undo_batch { ll top = 0; vector<dreapta> st = vector<dreapta>( 1000000 + 10, dreapta{1000ll * 1000 * 1000, 1000ll * 1000 * 1000 * 1000 * 1000}); struct modification { ll old_top, old_pos; dreapta d; }; vector<modification> undo_st; public: undo_batch() { top = 1; } void clear() { top = 1; } void print() { for (int i = 1; i < top; ++i) { cerr << ( << st[i].a << , << st[i].b << ) ; } cerr << endl; } ll query(ll x) { ll i = 0; for (ll step = 1 << 23; step; step /= 2) if (i + step < top && st[i + step](x) <= st[i + step - 1](x)) i += step; assert(i == top - 1 || st[i](x) <= st[i + 1](x)); return st[i](x); } void undo() { assert(!undo_st.empty()); top = undo_st.back().old_top; st[undo_st.back().old_pos] = undo_st.back().d; undo_st.pop_back(); } void add_right(dreapta d) { undo_st.push_back(modification{top, 0, 0}); ll ret = 0; for (ll step = 1 << 23; step; step /= 2) if (ret + step < top && (!useless(st[ret + step - 1], st[ret + step], d))) ret += step; top = ret + 2; undo_st.back().old_pos = ret + 1; undo_st.back().d = st[ret + 1]; st[ret + 1] = d; } }; void produce_state(const ll n, const vector<ll>& d, const vector<ll>& v, vector<ll>& ret) { static vector<ll> posz; static vector<merging_batch> mb; static undo_batch ub; posz.clear(); mb.clear(); ub.clear(); for (ll i = 0; i < n; ++i) { merging_batch x; x.add_right(dreapta{-i + 1, d[i]}); while (!posz.empty() && v[posz.back()] <= v[i]) { mb.back().merge_with(x); x.swap_with(mb.back()); mb.pop_back(); posz.pop_back(); ub.undo(); } posz.push_back(i); mb.push_back(move(x)); ub.add_right(dreapta{v[i], mb.back().query(v[i])}); ret[i + 1] = ub.query(i); } } int main() { ios::sync_with_stdio(false); cin.tie(0); ll n, k; cin >> n >> k; vector<ll> v(n); for (auto& x : v) cin >> x; vector<ll> state(n + 1, (ll)1e9 * (ll)1e9), tmp(n + 1, 0); state[0] = 0; tmp[0] = 0; for (ll i = 0; i < k; ++i) { produce_state(n, state, v, tmp); swap(state, tmp); } cout << state.back() << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int get(int l, int n) { int v1, v2; cout << ? << l << endl; fflush(stdout); cin >> v1; cout << ? << (l + n / 2 - 1) % n + 1 << endl; fflush(stdout); cin >> v2; return v2 - v1; } int main() { int n; cin >> n; int l, r; r = (n / 2 + 2) / 2; l = 1; int v_r, v_l; v_r = get(r, n); v_l = get(l, n); if (v_r == 0) { cout << ! << r << endl; return 0; } if (v_l == 0) { cout << ! << l << endl; return 0; } if (((v_r > 0) - (v_r < 0)) * ((v_l > 0) - (v_l < 0)) == 1) { int tmp = r; r = l + n / 2; l = tmp; } int m, v_m; while (r - l > 1) { m = (r + l) / 2; v_m = get(m, n); if (v_m == 0) { cout << ! << m << endl; return 0; } if (((v_m > 0) - (v_m < 0)) * ((v_l > 0) - (v_l < 0)) == 1) { l = m; v_l = v_m; } else { r = m; v_r = v_m; } } cout << ! << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[100001], p[100001]; int main() { int min = 1000, sum = 0, n, i, j; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d %d , &a[i], &p[i]); if (p[i] < min) { min = p[i]; } sum += a[i] * min; } printf( %d n , sum); return 0; }
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#include <bits/stdc++.h> using namespace std; const int inf = 109; const int mod = 1000000007; long long cnt[inf]; long long dp[inf]; long long temp[inf][inf]; long long sol[inf][inf]; long long bs[inf][inf]; int main() { int n, x, a; scanf( %d%d , &n, &x); for (int i = 0; i < n; ++i) { scanf( %d , &a); cnt[a]++; } dp[0] = 1; int all = 0; for (int i = 1; i <= 100; ++i) { for (int j = 1; j <= i; ++j) dp[i] = (dp[i] + dp[i - j] * cnt[j]) % mod; all = (all + dp[i]) % mod; } dp[0] = all; for (int i = 1; i <= 50; ++i) swap(dp[i], dp[101 - i]); for (int i = 1; i <= 100; ++i) sol[i][i] = 1, bs[0][i] = bs[1][i] = cnt[i]; sol[0][0] = bs[0][0] = 1; for (int i = 2; i <= 100; ++i) bs[i][i - 1] = 1; if (x <= 100) { int ad = 0; for (int i = 100; i > 0 && x > 0; --i, --x) ad = (ad + dp[i]) % mod; printf( %d n , ad + 1); return 0; } x -= 100; while (x) { if (x & 1) { for (int i = 0; i <= 100; ++i) for (int j = 0; j <= 100; ++j) { temp[i][j] = 0; for (int u = 0; u <= 100; ++u) temp[i][j] = (temp[i][j] + sol[i][u] * bs[u][j]) % mod; } for (int i = 0; i <= 100; ++i) for (int j = 0; j <= 100; ++j) sol[i][j] = temp[i][j]; } x = x >> 1; for (int i = 0; i <= 100; ++i) for (int j = 0; j <= 100; ++j) { temp[i][j] = 0; for (int u = 0; u <= 100; ++u) temp[i][j] = (temp[i][j] + bs[i][u] * bs[u][j]) % mod; } for (int i = 0; i <= 100; ++i) for (int j = 0; j <= 100; ++j) bs[i][j] = temp[i][j]; } int ans = 0; for (int i = 0; i <= 100; ++i) ans = (ans + sol[0][i] * dp[i]) % mod; printf( %d n , (ans + 1) % mod); }
|
#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) using namespace std; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline int msbp(int x) { return 31 - __builtin_clz(x); } inline int msb(int x) { return 1 << msbp(x); } const int INF = 0x3f3f3f3f; struct hash_pair { template <class T1, class T2> size_t operator()(const pair<T1, T2>& p) const { auto hash1 = hash<T1>{}(p.first); auto hash2 = hash<T2>{}(p.second); return hash1 ^ hash2; } }; const int N = 1e6 + 10; int parent[N], rnk[N]; int find(int x) { return parent[x] = (x == parent[x] ? x : find(parent[x])); } bool disjoint(int x, int y) { return find(x) != find(y); } void join(int x, int y) { if (!disjoint(x, y)) return; int xPar = find(x), yPar = find(y); int newPar, newChild; if (rnk[xPar] > rnk[yPar]) { newPar = xPar, newChild = yPar; } else if (rnk[xPar] < rnk[yPar]) { newPar = yPar, newChild = xPar; } else { newPar = xPar, newChild = yPar; ++rnk[xPar]; } parent[newChild] = newPar; } int n, m, b[N]; pair<int, int> a[N]; vector<pair<int, int>> all_vals; map<int, vector<int>> s; vector<int> g[N]; int d[N], dp[N]; void process_eq(vector<pair<int, int>>& cur) { map<int, int> val_map; for (auto [val, id] : cur) { if (val_map.count(val)) { join(id, val_map[val]); } else { val_map[val] = id; } } } void process(vector<int>& cur) { sort(cur.begin(), cur.end()); for (int i = 0; i < (cur.size() - 1); ++i) { if (cur[i] != cur[i + 1]) { g[cur[i]].push_back(cur[i + 1]); ++d[cur[i + 1]]; } } } signed main() { ios::sync_with_stdio(false); std::iota(parent, parent + N, 0); scanf( %d %d , &n, &m); for (int i = 0; i < (n); ++i) { for (int j = 0; j < (m); ++j) { scanf( %d , &a[i * m + j].first); s[a[i * m + j].first].push_back(i * m + j); } } vector<pair<int, int>> curm(m), curn(n); for (int i = 0; i < (n); ++i) { for (int j = 0; j < (m); ++j) curm[j] = {a[i * m + j].first, i * m + j}; process_eq(curm); } for (int j = 0; j < (m); ++j) { for (int i = 0; i < (n); ++i) curn[i] = {a[i * m + j].first, i * m + j}; process_eq(curn); } for (auto [val, ids] : s) { int cur = 1; for (int id : ids) { if (a[find(id)].second == 0) { all_vals.push_back({val, cur}); a[find(id)].second = cur++; } a[id].second = a[find(id)].second; } } sort(all_vals.begin(), all_vals.end()); map<pair<int, int>, int> id_map; for (int i = 0; i < (all_vals.size()); ++i) id_map[all_vals[i]] = i; for (int i = 0; i < (n); ++i) for (int j = 0; j < (m); ++j) b[i * m + j] = id_map[a[i * m + j]]; vector<int> ccurm(m), ccurn(n); for (int i = 0; i < (n); ++i) { for (int j = 0; j < (m); ++j) ccurm[j] = b[i * m + j]; process(ccurm); } for (int j = 0; j < (m); ++j) { for (int i = 0; i < (n); ++i) ccurn[i] = b[i * m + j]; process(ccurn); } queue<int> nxt; for (int x = 0; x < (all_vals.size()); ++x) { if (d[x] == 0) { nxt.push(x); dp[x] = 1; } } while (!nxt.empty()) { int cur = nxt.front(); nxt.pop(); for (auto v : g[cur]) { dp[v] = max(dp[v], dp[cur] + 1); --d[v]; if (d[v] == 0) { nxt.push(v); } } } for (int i = 0; i < (n); ++i) { for (int j = 0; j < (m); ++j) cout << dp[b[i * m + j]] << ; cout << n ; } return 0; }
|
//`timescale 1ns
module tb_fir ();
initial begin
$read_lib_saif("../saif/NangateOpenCellLibrary.saif");
$set_gate_level_monitoring("on");
$set_toggle_region(UUT);
$toggle_start;
end
wire CLK_i;
wire RST_n_i;
wire [8:0] DIN_i;
wire VIN_i;
//wire [15:0] H0_i;
//wire [15:0] H1_i;
//wire [15:0] H2_i;
//wire [15:0] H3_i;
wire [80:0] coeffs_i;
wire [17:0] DOUT_i;
wire VOUT_i;
wire END_SIM_i;
clk_gen CG(.END_SIM(END_SIM_i),
.CLK(CLK_i),
.RST_n(RST_n_i));
data_maker SM(.CLK(CLK_i),
.RST_n(RST_n_i),
.VOUT(VIN_i),
.DOUT(DIN_i),
/* .H0(H0_i),
.H1(H1_i),
.H2(H2_i),
.H3(H3_i), */
.coeffs(coeffs_i),
.END_SIM(END_SIM_i));
FIR_filter UUT(.CLK(CLK_i),
.RST_n(RST_n_i),
.DIN(DIN_i),
.VIN(VIN_i),
/* .H0(H0_i),
.H1(H1_i),
.H2(H2_i),
.H3(H3_i), */
.Coeffs(coeffs_i),
.DOUT(DOUT_i),
.VOUT(VOUT_i));
data_sink DS(.CLK(CLK_i),
.RST_n(RST_n_i),
.VIN(VOUT_i),
.DIN(DOUT_i));
always @ ( END_SIM_i ) begin
if (END_SIM_i) begin
$toggle_stop;
$toggle_report("../saif/FIR_filter_back.saif", 1.0e-9, "tb_fir.UUT");
end
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:48:31 MST 2014
// Date : Mon Feb 16 11:07:32 2015
// Host : austin_workstation_1 running 64-bit Fedora release 20 (Heisenbug)
// Command : write_verilog -force -mode synth_stub
// /home/luis/FIRMWARE/git/vhdl/ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_0_stub.v
// Design : axi_traffic_gen_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1157-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_traffic_gen_v2_0_top,Vivado 2014.4" *)
module axi_traffic_gen_0(s_axi_aclk, s_axi_aresetn, m_axi_lite_ch1_awaddr, m_axi_lite_ch1_awprot, m_axi_lite_ch1_awvalid, m_axi_lite_ch1_awready, m_axi_lite_ch1_wdata, m_axi_lite_ch1_wstrb, m_axi_lite_ch1_wvalid, m_axi_lite_ch1_wready, m_axi_lite_ch1_bresp, m_axi_lite_ch1_bvalid, m_axi_lite_ch1_bready, done, status)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,m_axi_lite_ch1_awaddr[31:0],m_axi_lite_ch1_awprot[2:0],m_axi_lite_ch1_awvalid,m_axi_lite_ch1_awready,m_axi_lite_ch1_wdata[31:0],m_axi_lite_ch1_wstrb[3:0],m_axi_lite_ch1_wvalid,m_axi_lite_ch1_wready,m_axi_lite_ch1_bresp[1:0],m_axi_lite_ch1_bvalid,m_axi_lite_ch1_bready,done,status[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
output [31:0]m_axi_lite_ch1_awaddr;
output [2:0]m_axi_lite_ch1_awprot;
output m_axi_lite_ch1_awvalid;
input m_axi_lite_ch1_awready;
output [31:0]m_axi_lite_ch1_wdata;
output [3:0]m_axi_lite_ch1_wstrb;
output m_axi_lite_ch1_wvalid;
input m_axi_lite_ch1_wready;
input [1:0]m_axi_lite_ch1_bresp;
input m_axi_lite_ch1_bvalid;
output m_axi_lite_ch1_bready;
output done;
output [31:0]status;
endmodule
|
module zscale_wrapper (
input wire clk,
input wire reset,
output wire [7:0] led
);
wire csr_resp_valid;
wire [63:0] csr_resp_data;
// BootMem AHB
wire [31:0] io_bootmem_haddr;
wire io_bootmem_hwrite;
wire [2:0] io_bootmem_hsize;
wire [2:0] io_bootmem_hburst;
wire [3:0] io_bootmem_hprot;
wire [1:0] io_bootmem_htrans;
wire io_bootmem_hmastlock;
wire [31:0] io_bootmem_hwdata;
wire [31:0] io_bootmem_hrdata;
wire io_bootmem_hsel;
wire io_bootmem_hreadyin;
wire io_bootmem_hreadyout;
wire io_bootmem_hresp;
// APB
wire [31:0] io_led_paddr;
wire io_led_pwrite;
wire io_led_psel;
wire io_led_penable;
wire [31:0] io_led_pwdata;
wire [31:0] io_led_prdata;
wire io_led_pready;
wire io_led_pslverr;
reg led_ready;
reg [31:0] led_reg;
assign led = led_reg[7:0];
ZscaleTop zs(
.clk(clk),
.reset(reset),
.io_host_reset(reset),
.io_host_id(1'b0),
.io_host_pcr_req_ready(),
.io_host_pcr_req_valid(1'b1),
.io_host_pcr_req_bits_rw(1'b0),
.io_host_pcr_req_bits_addr(12'h780), // tohost register
.io_host_pcr_req_bits_data(64'd0),
.io_host_pcr_rep_ready(1'b1),
.io_host_pcr_rep_valid(csr_resp_valid),
.io_host_pcr_rep_bits(csr_resp_data),
.io_host_ipi_req_ready(1'b1),
.io_host_ipi_req_valid(),
.io_host_ipi_req_bits(),
.io_host_ipi_rep_ready(),
.io_host_ipi_rep_valid(1'b0),
.io_host_ipi_rep_bits(),
.io_host_debug_stats_pcr(),
.io_bootmem_haddr(io_bootmem_haddr),
.io_bootmem_hwrite(io_bootmem_hwrite),
.io_bootmem_hsize(io_bootmem_hsize),
.io_bootmem_hburst(io_bootmem_hburst),
.io_bootmem_hprot(io_bootmem_hprot),
.io_bootmem_htrans(io_bootmem_htrans),
.io_bootmem_hmastlock(io_bootmem_hmastlock),
.io_bootmem_hwdata(io_bootmem_hwdata),
.io_bootmem_hrdata(io_bootmem_hrdata),
.io_bootmem_hsel(io_bootmem_hsel),
.io_bootmem_hreadyin(io_bootmem_hreadyin),
.io_bootmem_hreadyout(io_bootmem_hreadyout),
.io_bootmem_hresp(io_bootmem_hresp),
.io_led_paddr(io_led_paddr),
.io_led_pwrite(io_led_pwrite),
.io_led_psel(io_led_psel),
.io_led_penable(io_led_penable),
.io_led_pwdata(io_led_pwdata),
.io_led_prdata(io_led_prdata),
.io_led_pready(io_led_pready),
.io_led_pslverr(io_led_pslverr)
);
assign io_led_pslverr = 1'b0;
assign io_led_pready = led_ready;
assign io_led_prdata = led_reg;
always @(posedge reset or posedge clk)
begin
if (reset)
begin
led_reg = 32'h80;
led_ready = 1'b0;
end
else
begin
if (clk)
begin
if (led_ready && io_led_penable)
begin
led_reg = io_led_pwdata;
led_ready = 1'b0;
end
else
if (io_led_psel && io_led_paddr == 32'h80000000)
begin
led_ready = 1'b1;
end
else
begin
led_ready = 1'b0;
end
end
end
end
ROM bm (
.clk(clk),
.reset(reset),
.haddr(io_bootmem_haddr),
.hwrite(io_bootmem_hwrite),
.hsize(io_bootmem_hsize),
.hburst(io_bootmem_hburst),
.hprot(io_bootmem_hprot),
.htrans(io_bootmem_htrans),
.hmastlock(io_bootmem_hmastlock),
.hwdata(32'd0),
.hrdata(io_bootmem_hrdata),
.hsel(io_bootmem_hsel),
.hreadyin(io_bootmem_hreadyin),
.hreadyout(io_bootmem_hreadyout),
.hresp(io_bootmem_hresp)
);
endmodule
|
#include <bits/stdc++.h> int main() { char a[110], b[110]; scanf( %s%s , a, b); if (strcmp(a, b) == 0) printf( %s n , a); else printf( 1 n ); }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_6_1 (
Din,
Dout
);
input wire [39 : 0] Din;
output wire [15 : 0] Dout;
xlslice #(
.DIN_WIDTH(40),
.DIN_FROM(32),
.DIN_TO(17)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { char c = getchar(); int x = 0; bool f = 0; for (; !isdigit(c); c = getchar()) f ^= !(c ^ 45); for (; isdigit(c); c = getchar()) x = (x << 1) + (x << 3) + (c ^ 48); if (f) x = -x; return x; } const int M = 4e6 + 10; int n, maxn, pp[M], a[M], b[M], cnt, ppp[M]; int max1, max2, sum1, sum2, vis[M]; map<int, int> t; vector<int> e[M]; void dfs(int u) { if (vis[u]) return; vis[u] = 1, sum2++; max2 = max(max2, u); if (max1 < max2) swap(max1, max2); for (int i = 0; i < e[u].size(); i++) { int to = e[u][i]; sum1++; dfs(to); } } signed main() { n = read(); for (int i = 1; i <= n; i++) pp[++cnt] = a[i] = read(), pp[++cnt] = b[i] = read(); sort(pp + 1, pp + 1 + cnt); cnt = 0; for (int i = 1; i <= 2 * n; i++) if (pp[i] != pp[i - 1] || i == 1) t[pp[i]] = ++cnt, ppp[cnt] = pp[i]; for (int i = 1; i <= n; i++) a[i] = t[a[i]], b[i] = t[b[i]], e[a[i]].push_back(b[i]), e[b[i]].push_back(a[i]); for (int i = 1; i <= cnt; i++) if (!vis[i]) { max1 = max2 = sum1 = sum2 = 0; dfs(i); sum1 /= 2; if (sum2 == sum1) maxn = max(maxn, max1); else if (sum2 > sum1) maxn = max(maxn, max2); else return puts( -1 ), 0; } cout << ppp[maxn] << endl; return 0; }
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; . All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// lfsr.v: linear feedback shift register (LFSR); a periodic random counter //
// //
// Ameer M.S. Abdelhadi (; ), June 2012 //
////////////////////////////////////////////////////////////////////////////////////
module lfsr
#( parameter WID = 16 , // integer: register width, up to 168.
parameter INI = 0 ) // int/str: loaded when ald is high. defaults is all 1s. limited to 32 bits.
( input clk , // input clock
input enb , // clock enable
input rst , // async load (loads initial number)
output wire [WID:1] cnt ); // output random count number
// lfst feedback function
wire fb;
lfsr_fb #( .WID(WID) ) // integer: register width, up to 168.
lfsr_fb_inst ( .cnt(cnt) , // input clock
.fb (fb ) ); // output random count number
lpm_shiftreg #(
.LPM_WIDTH (WID ), // integer: width of the q ports.
.LPM_DIRECTION("LEFT"), // string : values are "LEFT", "RIGHT", and or "UNUSED". If omitted, the default is "LEFT".
.LPM_AVALUE (INI ) // int/str: loaded when aset is high. defaults is all 1s. limited to 32 bits.
) lfsr_reg (
.clock (clk), // positive-edge-triggered clock.
.enable (enb), // clock enable input.
.shiftin(fb ), // serial shift data input.
.aset (rst), // asynchronous set input (with LPM_AVALUE).
.q (cnt) // data output from the shift register.
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5; vector<int> graph[N]; int pa[N]; int getHeight(int u, int pre) { int res = 1; pa[u] = pre; for (auto e : graph[u]) { if (e == pre) { continue; } int subHeight = getHeight(e, u); res = max(res, subHeight + 1); } return res; } bool checkBanalance(int u, int pre, int &height) { if (graph[u].size() == 1) { height = 0; return true; } int h[2]; int idx = 0; for (auto e : graph[u]) { if (e == pre) { continue; } bool ret = checkBanalance(e, u, h[idx++]); if (!ret) { return false; } } height = h[0] + 1; if (h[0] != h[1]) { return false; } return true; } int d[N]; int maxDepth = 0; int maxNode = 0; int getDepth(int u, int pre) { d[u] = d[pre] + 1; pa[u] = pre; for (auto e : graph[u]) { if (e == pre) { continue; } getDepth(e, u); } if (d[u] > maxDepth) { maxDepth = d[u]; maxNode = u; } return d[u]; } int main() { int n; scanf( %d , &n); int nodeErase = (1 << n) - 1; int u, v; for (int i = 1; i <= (1 << n) - 3; i++) { scanf( %d%d , &u, &v); graph[u].push_back(v); graph[v].push_back(u); } if (n == 2) { printf( 2 n ); printf( 1 2 n ); return 0; } vector<int> cnt[5]; int res; int root; for (int i = 1; i <= (1 << n) - 2; i++) { int degree = graph[i].size(); if (degree > 4 || degree < 1) { do { printf( 0 n ); return 0; } while (0); ; } cnt[degree].push_back(i); } if (cnt[4].size() > 1 || cnt[2].size() > 2) { do { printf( 0 n ); return 0; } while (0); ; } else if (cnt[4].size() == 1) { if (cnt[2].size() != 1) { do { printf( 0 n ); return 0; } while (0); ; } root = cnt[2][0]; res = cnt[4][0]; getHeight(root, 0); pair<int, int> h[4]; int idx = 0; for (auto e : graph[res]) { if (e == pa[res]) { continue; } h[idx++] = make_pair(getHeight(e, res), e); } sort(h, h + 3); if (!(h[0].first == h[1].first && h[2].first == h[1].first + 1)) { do { printf( 0 n ); return 0; } while (0); ; } graph[h[0].second].push_back(nodeErase); graph[h[1].second].push_back(nodeErase); graph[res].push_back(nodeErase); graph[nodeErase].push_back(h[0].second); graph[nodeErase].push_back(h[1].second); graph[nodeErase].push_back(res); graph[res].erase(find(graph[res].begin(), graph[res].end(), h[0].second)); graph[res].erase(find(graph[res].begin(), graph[res].end(), h[1].second)); graph[h[0].second].erase( find(graph[h[0].second].begin(), graph[h[0].second].end(), res)); graph[h[1].second].erase( find(graph[h[1].second].begin(), graph[h[1].second].end(), res)); } else if (cnt[4].size() == 0 && cnt[2].size() == 2) { for (int i = 0; i < 2; i++) { root = cnt[2][i]; res = cnt[2][1 - i]; int h1 = getHeight(graph[root][0], 0); int h2 = getHeight(graph[root][1], 0); if (h1 == h2) { break; } } graph[res].push_back(nodeErase); graph[nodeErase].push_back(res); } else if (cnt[4].size() == 0 && cnt[2].size() == 0) { u = cnt[1][0]; getDepth(u, 0); int t = (maxDepth - 1) / 2; v = maxNode; for (int i = 0; i < t; i++) { v = pa[v]; } u = pa[v]; int height = 0; if (checkBanalance(u, v, height) && checkBanalance(v, u, height)) { if (u > v) { swap(u, v); } printf( 2 n%d %d n , u, v); return 0; } else { do { printf( 0 n ); return 0; } while (0); ; } } else { do { printf( 0 n ); return 0; } while (0); ; } int height = 0; bool ret = checkBanalance(root, 0, height); if (ret) { printf( 1 n%d n , res); } else { do { printf( 0 n ); return 0; } while (0); ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; struct edge { int v, next; } e[500100]; int head[100100], tot = 0; void Add(int u, int v) { e[tot].v = v; e[tot].next = head[u]; head[u] = tot++; } int res[100100]; int deep[100100]; int vis[100100]; void DFS(int u) { vis[u] = 1; for (int i = head[u]; i != -1; i = e[i].next) { int v = e[i].v; if (deep[v] <= 2 && !vis[v]) DFS(v); } } int main() { memset((head), (-1), sizeof(head)); scanf( %d , &n); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); Add(u, v); Add(v, u); deep[u]++; deep[v]++; } for (int i = 1; i <= n; i++) { if (deep[i] == 1) DFS(i); } for (int i = 1; i <= n; i++) { if (!vis[i]) { for (int j = head[i]; j != -1; j = e[j].next) { int v = e[j].v; if (vis[v]) { res[i] = min(res[i] + 1, 2); } } } } for (int u = 1; u <= n; u++) { if (!vis[u]) { int cnt = 0; for (int i = head[u]; i != -1; i = e[i].next) { int v = e[i].v; if (!vis[v] && deep[v] - res[v] > 1) cnt++; } if (cnt > 2) { cout << No << endl; return 0; } } } cout << Yes << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, b[1000010]; int main() { scanf( %d%d , &n, &k); int i; if (k * 3 > n || k == 1) puts( -1 ); else { for (i = 1; i <= (int)(k); ++i) b[i] = b[i + 2 * k] = i, b[i + k] = i - 1; b[k + 1] = k; for (i = 3 * k + 1; i <= n; ++i) b[i] = 1; for (i = 1; i <= (int)(n); ++i) printf( %d , b[i]); puts( ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MM = 10000000000000001; int n; long long a[200005]; int rs[200005]; long long lazy[4 * 200005]; pair<long long, int> it[4 * 200005]; pair<long long, int> minp(pair<long long, int> A, pair<long long, int> B) { if (A.first < B.first) return A; if (A.first > B.first) return B; if (A.second > B.second) return A; return B; } void build(int x, int l, int r) { if (l == r) { it[x] = make_pair(a[l], l); return; } int mid = (l + r) / 2; build(2 * x, l, mid); build(2 * x + 1, mid + 1, r); it[x] = minp(it[2 * x], it[2 * x + 1]); } void lazy_upd(int x, int l, int r) { it[x].first += lazy[x]; if (l != r) { lazy[2 * x] += lazy[x]; lazy[2 * x + 1] += lazy[x]; } lazy[x] = 0; } void update(int x, int l, int r, int u, int v, long long val) { lazy_upd(x, l, r); if ((r < u) || (v < l)) return; if ((u <= l) && (r <= v)) { lazy[x] += val; lazy_upd(x, l, r); return; } int mid = (l + r) / 2; update(2 * x, l, mid, u, v, val); update(2 * x + 1, mid + 1, r, u, v, val); it[x] = minp(it[2 * x], it[2 * x + 1]); } int main() { ios::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; build(1, 1, n); for (int i = 1; i <= n; i++) { pair<long long, int> p = it[1]; int id = p.second; rs[id] = i; update(1, 1, n, id, id, MM); update(1, 1, n, id + 1, n, -i); } for (int i = 1; i <= n; i++) cout << rs[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long ans = 0; int n; long long a[200200]; long long mn = 21000000000; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; mn = min(mn, a[i]); } int id; for (int i = n - 1; i >= 0; i--) { if (a[i] == mn) { id = i; break; } } for (int i = 0; i < n; i++) { ans += mn; a[i] -= mn; } long long s = 0, c = -1; for (int i = (id + 1) % n; i != id; i = (i + 1) % n) { if (a[i] == 0) { c = max(c, s); s = 0LL; a[i]--; } else { s++; } } c = max(c, s); cout << ans + c << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; if ((n - 2) % 3 == 0) { cout << 1 << << 2 << << n - 3 << endl; } else { cout << 1 << << 1 << << n - 2 << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3B_1_V
`define SKY130_FD_SC_MS__NAND3B_1_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand3b_1 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand3b_1 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3B_1_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "seq_gen/seq_gen.v"
`include "seq_gen/seq_gen_core.v"
`include "m26_rx/m26_rx.v"
`include "m26_rx/m26_rx_core.v"
`include "m26_rx/m26_rx_ch.v"
`include "utils/cdc_syncfifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/cdc_reset_sync.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "utils/IDDR_sim.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam SEQ_GEN_BASEADDR = 32'h1000;
localparam SEQ_GEN_HIGHADDR = 32'h3000-1;
localparam M26_RX_BASEADDR = 32'h3000;
localparam M26_RX_HIGHADDR = 32'h5000 - 1;
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000 - 1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
wire [7:0] SEQ_OUT;
seq_gen
#(
.BASEADDR(SEQ_GEN_BASEADDR),
.HIGHADDR(SEQ_GEN_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(8*1024),
.OUT_BITS(8)
) i_seq_gen
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(1'b0),
.SEQ_CLK(BUS_CLK),
.SEQ_OUT(SEQ_OUT)
);
wire FIFO_READ_RX;
wire FIFO_EMPTY_RX;
wire [31:0] FIFO_DATA_RX;
//safe clock domain crossing synchronization
reg [31:0] TIMESTAMP, timestamp_gray;
always@(posedge BUS_CLK)
TIMESTAMP <= 32'haa55bb44;
always@(posedge BUS_CLK)
timestamp_gray <= (TIMESTAMP>>1) ^ TIMESTAMP;
reg [31:0] timestamp_cdc0, timestamp_cdc1, timestamp_m26;
always@(posedge BUS_CLK) begin
timestamp_cdc0 <= timestamp_gray;
timestamp_cdc1 <= timestamp_cdc0;
end
integer gbi;
always@(*) begin
timestamp_m26[31] = timestamp_cdc1[31];
for(gbi =30; gbi >= 0; gbi = gbi -1) begin
timestamp_m26[gbi] = timestamp_cdc1[gbi] ^ timestamp_m26[gbi+1];
end
end
m26_rx
#(
.BASEADDR(M26_RX_BASEADDR),
.HIGHADDR(M26_RX_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_m26_rx
(
.CLK_RX(BUS_CLK),
.MKD_RX(SEQ_OUT[0]),
.DATA_RX(SEQ_OUT[2:1]),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ(FIFO_READ_RX),
.FIFO_EMPTY(FIFO_EMPTY_RX),
.FIFO_DATA(FIFO_DATA_RX),
.TIMESTAMP(timestamp_m26),
.LOST_ERROR()
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
assign FIFO_DATA = FIFO_DATA_RX;
assign FIFO_EMPTY = FIFO_EMPTY_RX;
assign FIFO_READ_RX = FIFO_READ;
bram_fifo
#(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
initial begin
$dumpfile("m26.vcd");
$dumpvars(0);
end
endmodule
|
module uvm;
class simple_item extends uvm_sequence_item;
rand int unsigned addr;
rand int unsigned data;
rand int unsigned delay;
constraint c1 { addr < 16'h2000; }
constraint c2 { data < 16'h1000; }
// UVM automation macros for general objects
`uvm_object_utils_begin(simple_item)
a = b;
c = d;
`uvm_field_int(addr, UVM_ALL_ON)
`uvm_field_int(data, UVM_ALL_ON)
`uvm_field_int(delay, UVM_ALL_ON)
`uvm_object_utils_end
// Constructor
function new (string name = "simple_item");
super.new(name);
endfunction : new
endclass : simple_item
class mydata extends uvm_object;
string str;
mydata subdata;
int field;
myenum e1;
int queue[$];
`uvm_object_utils(mydata)
`uvm_object_utils_begin(mydata) //requires ctor with default args
`uvm_field_string(str, UVM_DEFAULT)
`uvm_field_object(subdata, UVM_DEFAULT)
`uvm_field_int(field, UVM_DEC) //use decimal radix
`uvm_field_enum(myenum, e1, UVM_DEFAULT)
`uvm_field_queue_int(queue, UVM_DEFAULT)
`uvm_object_utils_end
`uvm_object_param_utils_begin(mydata) //requires ctor with default args
`uvm_field_string(str, UVM_DEFAULT)
`uvm_field_object(subdata, UVM_DEFAULT)
`uvm_field_int(field, UVM_DEC) //use decimal radix
`uvm_field_enum(myenum, e1, UVM_DEFAULT)
`uvm_field_queue_int(queue, UVM_DEFAULT)
`uvm_object_utils_end
endclass
class my_trans extends uvm_sequence_item;
rand bit [127:0] data [];
//---> Configuration
`uvm_object_utils_begin(my_trans)
`uvm_field_array_int ( data, UVM_ALL_ON)
`uvm_object_utils_end
function new (string name = "my_trans", uvm_sequencer_base sequencer = null, uvm_sequence parent_seq = null);
super.new(name, sequencer, parent_seq);
endfunction : new
endclass : my_trans
endmodule // uvm
module tt;
initial begin
while (1) begin
`uvm_do_with(aa, {bb == 0;})
`uvm_do(cc)
`uvm_do(cc)
end // while (1)
end // initial begin
endmodule // tt
|
#include <bits/stdc++.h> using namespace std; long long a, b, k, t, maxi, l, r, i, ans; long long dp0[200005]; long long dp1[200005]; long long s[200005]; int main() { cin >> a >> b >> k >> t; maxi = k * t; dp1[maxi] = 1; while (t) { t--; for (i = 0; i <= 2 * maxi; i++) { dp0[i] = dp1[i]; dp1[i] = 0; } for (i = 0; i <= 2 * maxi; i++) { l = i - k; if (l >= 0) { dp1[l] += dp0[i]; if (dp1[l] > 1000000007) dp1[l] -= 1000000007; } r = i + k + 1; if (r <= 2 * maxi) { dp1[r] -= dp0[i]; if (dp1[r] < 0) dp1[r] += 1000000007; } } for (i = 1; i <= 2 * maxi; i++) { dp1[i] += dp1[i - 1]; if (dp1[i] > 1000000007) dp1[i] -= 1000000007; } } s[0] = dp1[0]; for (i = 1; i <= 2 * maxi; i++) { s[i] = s[i - 1] + dp1[i]; if (s[i] > 1000000007) s[i] -= 1000000007; } for (i = 0; i <= 2 * maxi; i++) { r = a - b + i - 1; if (r < 0) continue; if (r > 2 * maxi) r = 2 * maxi; ans += (s[r] * dp1[i]) % 1000000007; if (ans > 1000000007) ans -= 1000000007; } cout << ans; return 0; }
|
//UART Version 3
/*
Distributed under the MIT license.
Copyright (c) 2014 Cospan Design LLC
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "project_defines.v"
`timescale 1 ns/1 ps
`define PRESCALER_COUNT 16
`define BIT_LENGTH 8
`define FULL_PERIOD (`PRESCALER_COUNT )
`define HALF_PERIOD (`PRESCALER_COUNT / 2)
module uart_v3 #(
parameter DEFAULT_BAUDRATE = 115200
)(
input clk,
input rst,
output reg tx,
input transmit,
input [7:0] tx_byte,
output is_transmitting,
input rx,
output reg rx_error,
output reg [7:0] rx_byte,
output reg received,
output is_receiving,
output [31:0] prescaler, //output this so the user can use it to calculate a baudrate
input set_clock_div,
input [31:0] user_clock_div,
output [31:0] default_clock_div
);
//Local Parameters
//Receive State Machine
localparam RX_IDLE = 0;
localparam RX_CHECK_START = 1;
localparam RX_READING = 2;
localparam RX_CHECK_STOP = 3;
localparam RX_DELAY_RESTART = 4;
localparam RX_ERROR = 5;
localparam RX_RECEIVED = 6;
//Transmit State Machine
localparam TX_IDLE = 0;
localparam TX_SENDING = 1;
localparam TX_FINISHED = 2;
//Registers/Wires
//Receive Register
reg [2:0] rx_state;
reg [3:0] rx_bit_count;
reg [7:0] rx_data;
reg [31:0] rx_clock_div;
reg [31:0] rx_clock_div_count;
reg [31:0] rx_prescaler_count;
//Transmit Register
reg [2:0] tx_state;
reg [3:0] tx_bit_count;
reg [7:0] tx_data;
reg [31:0] tx_clock_div;
reg [31:0] tx_prescaler_count;
reg [31:0] tx_clock_div_count;
//Submodules
//Asynchronous Logic
assign prescaler = `CLOCK_RATE / (`PRESCALER_COUNT);
assign default_clock_div = `CLOCK_RATE / (`PRESCALER_COUNT * DEFAULT_BAUDRATE);
assign is_receiving = (rx_state != RX_IDLE);
assign is_transmitting = (tx_state != TX_IDLE);
//Synchronous Logic
always @ (posedge clk) begin
if (rst || set_clock_div) begin
rx_state <= RX_IDLE;
rx_bit_count <= 0;
rx_clock_div_count <= 0;
rx_clock_div <= `FULL_PERIOD;
rx_data <= 0;
rx_byte <= 0;
rx_error <= 0;
if (set_clock_div) begin
rx_clock_div <= user_clock_div;
end
else begin
rx_clock_div <= default_clock_div;
end
end
else begin
//Strobed
received <= 0;
rx_error <= 0;
//have we passed the clock divider count
rx_clock_div_count <= rx_clock_div_count + 1;
if (rx_clock_div_count >= rx_clock_div) begin
rx_prescaler_count <= rx_prescaler_count + 1;
rx_clock_div_count <= 0;
end
//Receive State Machine
case (rx_state)
RX_IDLE: begin
//--*__ __|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|-- --
rx_prescaler_count <= 0;
rx_data <= 0;
rx_bit_count <= 0;
if (!rx) begin
rx_state <= RX_CHECK_START;
end
else begin
rx_clock_div_count <= 0;
end
end
RX_CHECK_START: begin
//--|__*__|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|-- --
if (rx_prescaler_count >= (`HALF_PERIOD)) begin
rx_prescaler_count <= 0;
if (!rx) begin
rx_state <= RX_READING;
end
else begin
rx_state <= RX_IDLE;
end
end
end
RX_READING: begin
//--|__ __|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|-- --
if (rx_prescaler_count >= (`FULL_PERIOD)) begin
rx_data <= {rx, rx_data[7:1]};
rx_prescaler_count <= 0;
if (rx_bit_count >= 7) begin
//Finished
rx_state <= RX_CHECK_STOP;
end
else begin
rx_bit_count <= rx_bit_count + 1;
end
end
end
RX_CHECK_STOP: begin
//--|__ __|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|--*--
if (rx_prescaler_count >= (`FULL_PERIOD)) begin
if (rx) begin
rx_byte <= rx_data;
//$display ("FOUND DATA!!!: %h", rx_data);
received <= 1;
rx_state <= RX_IDLE;
end
else begin
rx_error <= 1;
rx_state <= RX_IDLE;
end
end
end
default: begin
rx_state <= RX_IDLE;
end
endcase
end
end
always @ (posedge clk) begin
if (rst || set_clock_div) begin
tx <= 1;
tx_state <= TX_IDLE;
tx_data <= 0;
tx_bit_count <= 0;
tx_clock_div_count <= 0;
tx_prescaler_count <= 0;
if (set_clock_div) begin
tx_clock_div <= user_clock_div;
end
else begin
tx_clock_div <= default_clock_div;
end
end
else begin
//have we passed the clock divider count
tx_clock_div_count <= tx_clock_div_count + 1;
if (tx_clock_div_count >= tx_clock_div) begin
tx_prescaler_count <= tx_prescaler_count + 1;
tx_clock_div_count <= 0;
end
case (tx_state)
TX_IDLE: begin
tx <= 1;
tx_clock_div_count <= 1;
tx_prescaler_count <= 0;
if (transmit) begin
tx <= 0;
tx_data <= tx_byte;
tx_bit_count <= 0;
tx_state <= TX_SENDING;
end
end
TX_SENDING: begin
if (tx_prescaler_count >= (`FULL_PERIOD)) begin
tx_prescaler_count <= 0;
if (tx_bit_count < 8) begin
tx <= tx_data[0];
tx_data <= {1'b0, tx_data[7:1]};
tx_bit_count <= tx_bit_count + 1;
end
else begin
tx <= 1;
tx_state <= TX_FINISHED;
end
end
end
TX_FINISHED: begin
if (tx_prescaler_count >= (`FULL_PERIOD)) begin
tx_state <= TX_IDLE;
end
end
default: begin
tx_state <= TX_IDLE;
end
endcase
end
end
endmodule
|
module axis_control_if
#(
parameter C_S_AXIS_RXS_TDATA_WIDTH = 32,
parameter C_M_AXIS_TXC_TDATA_WIDTH = 32,
parameter ENABLE_LEN = 1
)
(
// Ports of Axi Master Bus Interface m_axis
input m_axis_txd_tvalid,
input m_axis_txd_tlast,
input m_axis_txd_tready,
input [11:0] tx_pkt_byte_cnt,
input tx_pkt_byte_cnt_vld,
input s_axis_rxs_aclk,
input s_axis_rxs_aresetn,
output s_axis_rxs_tready,
input [C_S_AXIS_RXS_TDATA_WIDTH-1 : 0] s_axis_rxs_tdata,
input [(C_S_AXIS_RXS_TDATA_WIDTH/8)-1 : 0] s_axis_rxs_tkeep,
input s_axis_rxs_tlast,
input s_axis_rxs_tvalid,
input m_axis_txc_aclk,
input m_axis_txc_aresetn,
output reg m_axis_txc_tvalid,
output reg [C_M_AXIS_TXC_TDATA_WIDTH-1 : 0] m_axis_txc_tdata,
output reg [(C_M_AXIS_TXC_TDATA_WIDTH/8)-1 : 0] m_axis_txc_tkeep,
output reg m_axis_txc_tlast,
input m_axis_txc_tready
);
reg len_fifo_rd_en;
wire [11:0] len_fifo_dout;
reg [2:0] tx_ctrl_state;
localparam WAIT_FOR_REQ = 1,
SEND_CTRL_PKTS = 2,
WAIT_FOR_END = 4;
reg [7:0] send_ctrl_words;
localparam WORD0 = 1,
WORD1 = 2,
WORD2 = 4,
WORD3 = 8,
WORD4 = 16,
WORD5 = 32;
assign s_axis_rxs_tready = 1'b1;
generate
if(ENABLE_LEN)begin
pkt_len_fifo_12x32 pkt_len_fifo
(
.clk (m_axis_txc_aclk),
.rst (!m_axis_txc_aresetn),
.din (tx_pkt_byte_cnt),
.wr_en(tx_pkt_byte_cnt_vld),
.rd_en(len_fifo_rd_en),
.dout (len_fifo_dout),
.full (),
.empty()
);
end
else begin
assign len_fifo_dout = 12'hFFF;
end
endgenerate
always @(posedge m_axis_txc_aclk)
if(!m_axis_txc_aresetn)begin
tx_ctrl_state <= WAIT_FOR_REQ;
send_ctrl_words <= WORD0;
m_axis_txc_tvalid <= 1'b0;
m_axis_txc_tdata <= 32'hFF_FF_FF_FF;
m_axis_txc_tkeep <= 4'hF;
m_axis_txc_tlast <= 1'b0;
len_fifo_rd_en <= 1'b0;
end
else begin
m_axis_txc_tvalid <= 1'b0;
m_axis_txc_tdata <= {24'h50000,len_fifo_dout};
m_axis_txc_tkeep <= 4'hF;
m_axis_txc_tlast <= 1'b0;
len_fifo_rd_en <= 1'b0;
case (tx_ctrl_state)
WAIT_FOR_REQ: begin
if(m_axis_txd_tvalid) begin
m_axis_txc_tvalid <= 1'b1;
tx_ctrl_state <= SEND_CTRL_PKTS;
end
end
SEND_CTRL_PKTS: begin
m_axis_txc_tvalid <= 1'b1;
if(m_axis_txc_tready) begin
case (send_ctrl_words)
WORD0: send_ctrl_words <= WORD1;
WORD1: send_ctrl_words <= WORD2;
WORD2: send_ctrl_words <= WORD3;
WORD3: send_ctrl_words <= WORD4;
WORD4: begin
send_ctrl_words <= WORD0;
m_axis_txc_tlast <= 1'b1;
len_fifo_rd_en <= 1'b1;
tx_ctrl_state <= WAIT_FOR_END;
end
endcase
end
end
WAIT_FOR_END: begin
if(m_axis_txd_tready && m_axis_txd_tlast)tx_ctrl_state <= WAIT_FOR_REQ;
end
endcase
end
endmodule
|
module user_io(
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
input [7:0] CORE_TYPE,
output [7:0] JOY0,
output [7:0] JOY1,
output [2:0] MOUSE_BUTTONS,
output KBD_MOUSE_STROBE,
output KMS_LEVEL,
output [1:0] KBD_MOUSE_TYPE,
output [7:0] KBD_MOUSE_DATA,
output [1:0] BUTTONS,
output [1:0] SWITCHES,
output [3:0] CONF
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [5:0] cnt;
reg [7:0] joystick0;
reg [7:0] joystick1;
reg [7:0] but_sw;
reg kbd_mouse_strobe;
reg kbd_mouse_strobe_level;
reg [1:0] kbd_mouse_type;
reg [7:0] kbd_mouse_data;
reg [2:0] mouse_buttons;
assign JOY0 = joystick0;
assign JOY1 = joystick1;
assign KBD_MOUSE_DATA = kbd_mouse_data; // 8 bit movement data
assign KBD_MOUSE_TYPE = kbd_mouse_type; // 0=mouse x,1=mouse y, 2=keycode, 3=OSD kbd
assign KBD_MOUSE_STROBE = kbd_mouse_strobe; // strobe, data valid on rising edge
assign KMS_LEVEL = kbd_mouse_strobe_level; // level change of kbd_mouse_strobe
assign MOUSE_BUTTONS = mouse_buttons; // state of the two mouse buttons
assign BUTTONS = but_sw[1:0];
assign SWITCHES = but_sw[3:2];
assign CONF = but_sw[7:4];
always@(negedge SPI_CLK) begin
if(cnt < 8)
SPI_MISO <= CORE_TYPE[7-cnt];
end
always@(posedge SPI_CLK) begin
kbd_mouse_strobe_level <= #1 kbd_mouse_strobe_level ^ kbd_mouse_strobe;
if(SPI_SS_IO == 1) begin
cnt <= 0;
end else begin
sbuf[6:1] <= sbuf[5:0];
sbuf[0] <= SPI_MOSI;
cnt <= cnt + 1;
if(cnt == 7) begin
cmd[7:1] <= sbuf;
cmd[0] <= SPI_MOSI;
end
if(cnt == 8) begin
if(cmd == 4)
kbd_mouse_type <= 2'b00; // first mouse axis
else if(cmd == 5)
kbd_mouse_type <= 2'b10; // keyboard
else if(cmd == 6)
kbd_mouse_type <= 2'b11; // OSD keyboard
end
// strobe is set whenever a valid byte has been received
kbd_mouse_strobe <= 0;
// first payload byte
if(cnt == 15) begin
if(cmd == 1) begin
but_sw[7:1] <= sbuf[6:0];
but_sw[0] <= SPI_MOSI;
end
if(cmd == 2) begin
joystick0[7:1] <= sbuf[6:0];
joystick0[0] <= SPI_MOSI;
end
if(cmd == 3) begin
joystick1[7:1] <= sbuf[6:0];
joystick1[0] <= SPI_MOSI;
end
// mouse, keyboard or OSD
if((cmd == 4)||(cmd == 5)||(cmd == 6)) begin
kbd_mouse_data[7:1] <= sbuf[6:0];
kbd_mouse_data[0] <= SPI_MOSI;
kbd_mouse_strobe <= 1;
end
end
// mouse handling
if(cmd == 4) begin
// second byte contains movement data
if(cnt == 23) begin
kbd_mouse_data[7:1] <= sbuf[6:0];
kbd_mouse_data[0] <= SPI_MOSI;
kbd_mouse_strobe <= 1;
kbd_mouse_type <= 2'b01;
end
// third byte contains the buttons
if(cnt == 31) begin
mouse_buttons[2:1] <= sbuf[1:0];
mouse_buttons[0] <= SPI_MOSI;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int n, m; pair<int, int> tl = {-100, -100}, br = {-100, -100}; cin >> n >> m; char paper[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> paper[i][j]; if (paper[i][j] == * && (tl.first == -100 && tl.second == -100)) tl = {i, j}; else if (j < tl.second && paper[i][j] == * ) tl = {tl.first, j}; if (paper[i][j] == * && (i >= br.first && j > br.second)) br = {i, j}; else if (paper[i][j] == * && (i > br.first)) br = {i, br.second}; else if (paper[i][j] == * && (j > br.second)) br = {br.first, j}; } } for (int i = tl.first; i <= br.first; i++) { for (int j = tl.second; j <= br.second; j++) { cout << paper[i][j]; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, k; cin >> n >> k; long long a; int g = 0; for (int i = 0; i < n; i++) { cin >> a; set<int> d; while (a) { if (a % 10 <= k) { d.insert(a % 10); } a /= 10; } if (d.size() == k + 1) { g++; } } cout << g; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:58:18 03/26/2016
// Design Name:
// Module Name: addr_gen
// Project Name:
// Target Devices:
// Tool versions:
// Description:µØÖ·²úÉúÆ÷£¬ÔÚ¼ÆËãʱΪmem²úÉú¶ÁдµÄµØÖ·
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module addr_gen(
clk_i,
//µØÖ·¼ÆÊýÓëÖØÖÃ
O_offset_cnt_en,
D_offset_cnt_en,
offset_reset,
//±íʾÕýÔÚ´«Ë͵ÄÊÇprev¡¢curr¡¢nextÆäÖеÄÒ»ÐÐ
prev_row_load,
curr_row_load,
next_row_load,
adr_o
);
input clk_i;
input O_offset_cnt_en;
input D_offset_cnt_en;
input offset_reset ;
input prev_row_load;
input curr_row_load;
input next_row_load;
output[21:0] adr_o ;
parameter WIDTH = 640;
reg[18:0] O_offset;
reg[18:0] D_offset;
wire[19:0] O_prev_addr;
wire[19:0] O_curr_addr;
wire[19:0] O_next_addr;
wire[19:0] D_addr;
/*******************************************************/
//³õʼ»¯
always @(posedge clk_i)
if(offset_reset)
O_offset <= 0;
else
if(O_offset_cnt_en)
O_offset <= O_offset+1;
/*******************************************************/
assign O_prev_addr = O_offset;
assign O_curr_addr = O_prev_addr + WIDTH/4;
assign O_next_addr = O_prev_addr + 2*WIDTH/4;
/*******************************************************/
always @(posedge clk_i)
if(offset_reset)
D_offset <= 0;
else
if(D_offset_cnt_en)
D_offset <= D_offset+1;
/*******************************************************/
assign D_addr[19:0] = D_offset;
/*******************************************************/
assign adr_o[21:2] = prev_row_load ? O_prev_addr :
curr_row_load ? O_curr_addr :
next_row_load ? O_next_addr :
D_addr;
assign adr_o[1:0] = 2'b00; //ÒòΪoffsetÿ´Î¼ÓÒ»£¬¶øÿ´Î¶Á³öµÄÊý¾ÝΪ4¸ö×Ö½Ú£¬ËùÒÔÊä³öʱ³Ë4£¬Ï൱ÓÚµØַÿ´Î¼ÓËÄ
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m, k; long long zero = 0; cin >> n >> m >> k; long long x, s; cin >> x >> s; long long a[m], b[m], c[k], d[k]; long long i, j; long long ans = n * x; for (i = 0; i < m; i++) { cin >> a[i]; } for (i = 0; i < m; i++) { cin >> b[i]; if (b[i] <= s) { ans = min(ans, n * a[i]); } } for (i = 0; i < k; i++) { cin >> c[i]; } for (i = 0; i < k; i++) { cin >> d[i]; if (d[i] <= s) { ans = min(ans, x * max(zero, n - c[i])); } } for (i = 0; i < m; i++) { if (b[i] <= s) { long long p = s - b[i]; auto it = upper_bound(d, d + k, p); if (it != d) { it--; } else { continue; } long long reduce = c[it - d]; reduce = min(n, reduce); long long temp = (n - reduce) * a[i]; ans = min(ans, temp); } } cout << ans; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) const long long INF = 1e9; const long long mod = 1e9 + 7; const long long LINF = 1e14; using namespace std; long long n, l; vector<long long> c; vector<int> b; int main() { std::ios::sync_with_stdio(false); cin >> n >> l; c.resize(n); cin >> c[0]; for (long long i = (1); i < (n); i++) { cin >> c[i]; c[i] = min(c[i - 1] * 2, c[i]); } while (l > 0) b.push_back(l % 2), l /= 2; while (c.size() < b.size()) c.push_back(c.back() * 2); while (b.size() < c.size()) b.push_back(0); c.push_back(c.back() * 2); n = b.size(); vector<long long> d(n + 1, LINF); d[0] = 0; for (long long i = (1); i < (n + 1); i++) { d[i] = min(d[i - 1], c[i - 1]); if (b[i - 1] == 1) d[i] += c[i - 1]; } cout << min(d[n], c.back()) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> a[10005]; int main() { int n, x, k = 0; cin >> n; x = (sqrt(1.0 + 8 * n) + 1) / 2; cout << x << endl; for (int i = 1; i <= x; i++) for (int j = i + 1; j <= x; j++) a[i].push_back(++k), a[j].push_back(k); for (int i = 1; i <= x; i++, cout << endl) for (int j = 0; j < a[i].size(); j++) cout << a[i][j] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 10; const double eps = 1e-6; int n, m; int sum, res; int f[21][1 << 21], col[MAX]; char s[MAX]; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %s , s); for (int j = 0; j < m; j++) if (s[j] == 1 ) col[j] |= (s[j] == 1 ) << i; } for (int i = 0; i < m; i++) f[0][col[i]]++; for (int i = 1; i <= n; i++) { for (int j = 0; j < 1 << n; j++) { sum = i < 2 ? 0 : (i - 2 - n) * f[i - 2][j]; for (int k = 0; k < n; k++) sum += f[i - 1][j ^ (1 << k)]; f[i][j] = sum / i; } } res = n * m; for (int i = 0; i < 1 << n; i++) { sum = 0; for (int j = 0; j <= n; j++) sum += (j < n - j ? j : n - j) * f[j][i]; res = res < sum ? res : sum; } printf( %d , res); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAH_BEHAVIORAL_V
`define SKY130_FD_SC_MS__FAH_BEHAVIORAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fah (
COUT,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAH_BEHAVIORAL_V
|
/* ****************************************************************************
-- (C) Copyright 2018 Kevin M. Hubbard - All rights reserved.
-- Source file: deep_sump_hyperram.v
-- Date: July 2018
-- Author: khubbard
-- Description: Deep Sump extension to sump2.v logic analyzer. This uses a FIFO
-- and a slow deep memory ( either internal or external ) for
-- extending event capture window in a parallel storage path.
-- Language: Verilog-2001
-- Simulation: Mentor-Modelsim
-- Synthesis: Xilint-XST,Xilinx-Vivado,Lattice-Synplify
-- License: This project is licensed with the CERN Open Hardware Licence
-- v1.2. You may redistribute and modify this project under the
-- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
-- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED
-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL
-- v.1.2 for applicable Conditions.
--
-- Revision History:
-- Ver# When Who What
-- ---- -------- -------- --------------------------------------------------
-- 0.1 04.29.18 khubbard Creation
-- ***************************************************************************/
`default_nettype none // Strictly enforce all nets to be declared
// Note: The RAM depth len+bits is for 64bits.
// Take total number of bits and divide by 64 to get depth_len
module deep_sump_hyperram #
(
parameter depth_len = 65536,
parameter depth_bits = 16
)
(
input wire reset,
input wire a_clk,
input wire b_clk,
input wire a_we,
input wire [depth_bits-1:0] a_addr,
input wire [63:0] a_di,
output reg a_overrun,
input wire b_rd_req,
input wire [depth_bits-1:0] b_addr,
output reg [63:0] b_do,
input wire [7:0] dram_dq_in,
output wire [7:0] dram_dq_out,
output wire dram_dq_oe_l,
input wire dram_rwds_in,
output wire dram_rwds_out,
output wire dram_rwds_oe_l,
output wire dram_ck,
output wire dram_rst_l,
output wire dram_cs_l,
output wire [7:0] sump_dbg
);
reg [107:0] fifo_din;
reg fifo_wr_en;
reg fifo_rd_en;
wire [107:0] fifo_dout;
reg [107:0] fifo_dout_q;
wire fifo_full;
wire fifo_almost_full;
wire fifo_overflow;
wire fifo_empty;
wire fifo_almost_empty;
wire fifo_valid;
reg fifo_valid_p1;
reg fifo_valid_p2;
reg hr_rd_req;
reg hr_wr_req;
reg hr_mem_or_reg;
reg [3:0] hr_wr_byte_en;
reg [31:0] hr_addr;
reg [5:0] hr_rd_num_dwords;
reg [31:0] hr_wr_d;
wire [31:0] hr_rd_d;
reg [63:0] hr_rd_d_sr;
wire hr_rd_rdy;
wire hr_busy;
wire hr_burst_wr_rdy;
reg [7:0] hr_latency_1x;
reg [7:0] hr_latency_2x;
reg [7:0] hr_wr_sr;
reg cfg_done_jk;
reg dword_two_jk;
reg [15:0] fifo_rd_en_sr;
wire lat_2x;
//-----------------------------------------------------------------------------
// Deep Sump pushes write address+data to a FIFO.
//-----------------------------------------------------------------------------
always @( posedge a_clk )
begin
fifo_din <= 108'd0;
fifo_din[depth_bits-1+64:64] <= a_addr[depth_bits-1:0];
fifo_din[63:0] <= a_di[63:0];
fifo_wr_en <= a_we;
a_overrun <= fifo_full | fifo_almost_full;// mark capture as invalid
if ( fifo_almost_full == 1 || fifo_full == 1 ) begin
fifo_wr_en <= 0;
end
end // always
//-----------------------------------------------------------------------------
// Instead of waiting 150uS from Power On to configure the HyperRAM, wait
// until the 1st time FIFO goes not-empty from Reset and then issue the cfg.
// Default 6 Clock 166 MHz Latency, latency1x=0x12, latency2x=0x16
// CfgReg0 write(0x00000800, 0x8f1f0000);
// Configd 3 Clock 83 MHz Latency, latency1x=0x04, latency2x=0x0a
// CfgReg0 write(0x00000800, 0x8fe40000);
//
// The FIFO with Deep Sump writes gets popped whenever HyperRAM is available.
// Deep Sump read requests are multi cycle. They come in on the b_clk domain
//-----------------------------------------------------------------------------
always @( posedge b_clk )
begin
hr_wr_sr <= { hr_wr_sr[6:0], hr_wr_req };
hr_latency_1x <= 8'h04;
hr_latency_2x <= 8'h0a;
hr_rd_num_dwords <= 6'd2;
hr_wr_byte_en <= 4'hF;
hr_rd_req <= 0;
hr_wr_req <= 0;
hr_mem_or_reg <= 0;
fifo_rd_en <= 0;
fifo_rd_en_sr <= { fifo_rd_en_sr[14:0], fifo_rd_en };
fifo_valid_p1 <= fifo_valid;
fifo_valid_p2 <= fifo_valid_p1;
b_do <= hr_rd_d_sr[63:0];
if ( hr_busy == 0 && hr_wr_sr == 8'd0 ) begin
if ( cfg_done_jk == 1 && b_rd_req == 1 ) begin
hr_addr <= 32'd0;
hr_addr[depth_bits-1+1:0] <= {b_addr[depth_bits-1:0],1'b0};// Note 64->32
hr_rd_req <= 1;
end
end
if ( hr_rd_rdy == 1 ) begin
hr_rd_d_sr <= { hr_rd_d_sr[31:0], hr_rd_d[31:0] };
end
// Configure HyperRAM optimal latency on 1st FIFO push after powerup
if ( cfg_done_jk == 0 && fifo_empty == 0 ) begin
cfg_done_jk <= 1;
hr_addr <= 32'h00000800;
hr_wr_d <= 32'h8fe40000;
hr_mem_or_reg <= 1;// Config Reg Write instead of DRAM Write
hr_wr_req <= 1;
end
// When FIFO has data, pop 32bits of Address and 64bits of Data and then
// Push those 2 DWORDs of Data to HyperRAM as a burst.
if ( hr_busy == 0 && hr_wr_sr == 8'd0 &&
fifo_rd_en_sr == 16'd0 && fifo_rd_en == 0 ) begin
if ( cfg_done_jk == 1 && fifo_empty == 0 ) begin
fifo_rd_en <= 1;// Pop Addr+Data off of FIFO for a HyperRAM Write
end
end
if ( fifo_valid == 1 && fifo_valid_p1 == 0 ) begin
fifo_dout_q <= fifo_dout[107:0];
end
// 1st DWORD is sent to DRAM as soon as FIFO pops it
if ( fifo_valid_p1 == 1 && fifo_valid_p2 == 0 ) begin
hr_addr <= { fifo_dout_q[94:64], 1'b0 };// Burst Address. Note 64->32
hr_wr_d <= fifo_dout_q[63:32];// Burst Data DWORD-1
dword_two_jk <= 1;// Queue up for the 2nd DWORD
hr_wr_req <= 1;
end
// 2nd DWORD is the burst. It just waits for hr_burst_wr_rdy
if ( dword_two_jk == 1 && hr_burst_wr_rdy == 1 ) begin
hr_addr <= { fifo_dout_q[94:64],1'b0};// Don't Care, just saves gates
hr_wr_d <= fifo_dout_q[31:0]; // Burst Data DWORD-2
dword_two_jk <= 0;
hr_wr_req <= 1;
end
if ( reset == 1 ) begin
cfg_done_jk <= 0;
dword_two_jk <= 0;
end
end // always
//-----------------------------------------------------------------------------
// Rate converting FIFO for HyperRAM DRAM access.
//
// Push Side
// wr_clk _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_
// wr_en _____/ \___
// din -----< >---
// almost_full
// overflow
//
// Pop Side
// rd_clk _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_
// rd_en _____________________/ \__________
// valid _____________________________/ \__
// dout -----------------------------< >--
// empty
// almost_empty
//-----------------------------------------------------------------------------
fifo_xilinx_512x108 u_fifo_xilinx_512x108
(
.rst ( reset ),
.wr_clk ( a_clk ),
.rd_clk ( b_clk ),
.din ( fifo_din[107:0] ),
.wr_en ( fifo_wr_en ),
.rd_en ( fifo_rd_en ),
.dout ( fifo_dout[107:0] ),
.full ( fifo_full ),
.almost_full ( fifo_almost_full ),
.overflow ( fifo_overflow ),
.empty ( fifo_empty ),
.almost_empty ( fifo_almost_empty ),
.valid ( fifo_valid )
);
assign sump_dbg[0] = fifo_wr_en;
assign sump_dbg[1] = fifo_rd_en;
//assign sump_dbg[2] = fifo_full;
//assign sump_dbg[2] = fifo_almost_full;
assign sump_dbg[2] = dram_rwds_in;
assign sump_dbg[3] = lat_2x;
assign sump_dbg[4] = hr_wr_req;
assign sump_dbg[5] = hr_rd_req;
assign sump_dbg[6] = hr_busy;
assign sump_dbg[7] = ~dram_cs_l;
//-----------------------------------------------------------------------------
// Bridge to a HyperRAM
//-----------------------------------------------------------------------------
hyper_xface u_hyper_xface
(
.reset ( reset ),
.clk ( b_clk ),
.rd_req ( hr_rd_req ),
.wr_req ( hr_wr_req ),
.mem_or_reg ( hr_mem_or_reg ),
.wr_byte_en ( hr_wr_byte_en ),
.addr ( hr_addr[31:0] ),
.rd_num_dwords ( hr_rd_num_dwords[5:0] ),
.wr_d ( hr_wr_d[31:0] ),
.rd_d ( hr_rd_d[31:0] ),
.rd_rdy ( hr_rd_rdy ),
.busy ( hr_busy ),
.lat_2x ( lat_2x ),
.burst_wr_rdy ( hr_burst_wr_rdy ),
.latency_1x ( hr_latency_1x[7:0] ),
.latency_2x ( hr_latency_2x[7:0] ),
.dram_dq_in ( dram_dq_in[7:0] ),
.dram_dq_out ( dram_dq_out[7:0] ),
.dram_dq_oe_l ( dram_dq_oe_l ),
.dram_rwds_in ( dram_rwds_in ),
.dram_rwds_out ( dram_rwds_out ),
.dram_rwds_oe_l ( dram_rwds_oe_l ),
.dram_ck ( dram_ck ),
.dram_rst_l ( dram_rst_l ),
.dram_cs_l ( dram_cs_l ),
.sump_dbg ( )
);// module hyper_xface
endmodule // deep_sump_hyperram
|
/*
* Copyright 2015, Stephen A. Rodgers. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
// A parallel input shift register clocked on falling edge
`default_nettype none
`timescale 1ns/1ns
// Main test module
module testbench;
reg clk;
reg rstn;
reg datain_ch0;
reg datain_ch1;
reg datain_ch2;
reg datain_ch3;
integer i;
wire serialout;
wire testout0;
wire testout1;
wire testout2;
wire testout3;
root test_root(
.clk(clk),
.rstn(rstn),
.datain_ch0(datain_ch0),
.datain_ch1(datain_ch1),
.datain_ch2(datain_ch2),
.datain_ch3(datain_ch3),
.serialout(serialout),
.testout0(testout0),
.testout1(testout1),
.testout2(testout2),
.testout3(testout3)
);
initial begin
$dumpvars(0, testbench);
clk = 0;
rstn = 0;
datain_ch0 = 0;
datain_ch1 = 0;
datain_ch2 = 0;
datain_ch3 = 0;
#10
rstn = 1;
#
datain_ch1 = 1;
#1090
datain_ch0 = 1;
#610
datain_ch0 = 0;
#8300
datain_ch1 = 0;
//datain_ch0 = 1;
//#2
//datain_ch0 = 0;
#10000000 $finish;
end
always #5 clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300009; map<short, int> f[maxn]; int a[maxn], n, K, p, q, d; int sum[maxn], i, j, k; int main() { scanf( %d%d , &n, &K); d = n / K; for (i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); for (i = 2; i <= n; i++) sum[i] = sum[i - 1] + a[i] - a[i - 1]; f[0][0] = 0; for (i = 1; i <= n; i++) { for (k = 0; k <= 1; k++) { if (i >= d) for (map<short, int>::iterator j = f[i - d].begin(); j != f[i - d].end(); j++) if (j->first + k <= n % K) { if (!f[i].count(j->first + k)) f[i][j->first + k] = j->second + sum[i] - sum[i - d + 1]; else f[i][j->first + k] = min(f[i][j->first + k], j->second + sum[i] - sum[i - d + 1]); } d++; } if (i >= d) f[i - d].clear(); d -= 2; } printf( %d , f[n][n % K]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; const int INF = 0x3f3f3f3f; int arr[N]; int dq[N * 2]; int main() { int n; scanf( %d , &n); int dl = N, dr = N - 1; for (int i = 0; i < n; i++) { scanf( %d , &arr[i]); if (arr[i] == 1) { dr++; dq[dr] = i; } } long long ans = 0; int l = 0; for (int i = n - 1; i >= 0; i--) { int sz = dr - dl + 1; if (arr[i] >= 3 && (arr[i] & 1)) { ans++; arr[i] -= 3; } while (dl <= dr) { if (arr[i] <= 1) break; if (dq[dr] >= i) { dr--; continue; } arr[dq[dr]]--; arr[i] -= 2; ans++; dr--; } if (!arr[i]) continue; while (l < i) { if (!arr[l]) { l++; continue; } if (arr[l] * 2 >= arr[i]) { ans += arr[i] / 2; arr[l] -= arr[i] / 2; arr[i] = 0; if (arr[l] == 1) { dl--; dq[dl] = l; } break; } else { ans += arr[l]; arr[i] -= arr[l] * 2; arr[l] = 0; l++; } } if (arr[i]) ans += arr[i] / 3; } printf( %I64d n , ans); return 0; }
|
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