text
stringlengths 59
71.4k
|
|---|
`timescale 1ns / 10ps // I have made changes in this file (Ilia). Fixed zero_flag for synthesis.
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:07:56 02/12/2015
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu (
final_output,carry_output, zero_flag,
opcode_inputs, reset_in, clk
);
parameter OPCODE_LENGTH = 4;
parameter DATA_WIDTH = 8;
parameter VECTOR_LENGTH = OPCODE_LENGTH + DATA_WIDTH + DATA_WIDTH;
parameter NOP = 4'b0000;
parameter ADD = 4'b0001;
parameter SUBTRACT = 4'b0010;
parameter MULT = 4'b0011;
parameter DIVIDE = 4'b0100;
parameter AND = 4'b0110;
parameter OR = 4'b0111;
parameter ZERO_TEST = 4'b1001;
parameter GREATER_THAN = 4'b1010;
parameter EQUAL = 4'b1011;
parameter LESS_THAN = 4'b1100;
output reg [DATA_WIDTH-1:0] final_output;
output reg carry_output;
output zero_flag;
input [VECTOR_LENGTH-1:0] opcode_inputs;
input reset_in;
input clk;
reg [VECTOR_LENGTH-1:0] prev_opcode_inputs;
// including the necessary task files
task CRAFA_module(
output reg sum,carry,
input in1,in2,carry_in
);
reg intermediate, gen, propagate;
begin
propagate = in1 ^ in2;
sum = propagate ^ carry_in;
gen = in1 & in2;
intermediate = propagate & carry_in;
carry = intermediate | gen;
end
endtask
task CRA4bit(
output reg [3:0] cra_sum,
output reg cra_carry_out,
input [3:0] in1,in2,
input carry_in
);
reg carry1,carry2,carry3;
begin
CRAFA_module (cra_sum[0],carry1,in1[0],in2[0],carry_in);
CRAFA_module (cra_sum[1],carry2,in1[1],in2[1],carry1);
CRAFA_module (cra_sum[2],carry3,in1[2],in2[2],carry2);
CRAFA_module (cra_sum[3],cra_carry_out,in1[3],in2[3],carry3);
end
endtask
task CRA8bit(
output reg [7:0] cra_sum,
output reg cra_carry_out,
input [7:0] in1,in2,
input carry_in
);
reg carry1;
begin
CRA4bit (cra_sum[3:0],carry1,in1[3:0],in2[3:0],carry_in);
CRA4bit (cra_sum[7:4],cra_carry_out,in1[7:4],in2[7:4],carry1);
end
endtask
task cra8_task(
output [DATA_WIDTH-1:0] adder_output,
output adder_carryout,
input [DATA_WIDTH-1:0] adder_in1, adder_in2,
input adder_carryin
);
begin
CRA8bit(adder_output,adder_carryout,adder_in1,adder_in2,adder_carryin);
end
endtask
task scra8_task(
output [DATA_WIDTH-1:0] sub_output,
output sub_c_b_out,
input [DATA_WIDTH-1:0] sub_in1,sub_in2,
input sub_c_b_in
);
reg [DATA_WIDTH-1:0]temp;
begin
temp = ~sub_in2 + 8'b1;
CRA8bit(sub_output,sub_c_b_out, sub_in1, temp, sub_c_b_in);
end
endtask
task CSAFA_module(
output reg sum,carry,
input in1,in2,carry_in
);
reg intermediate, gen, propagate;
begin
propagate = in1 ^ in2;
sum = propagate ^ carry_in;
gen = in1 & in2;
intermediate = propagate & carry_in;
carry = intermediate | gen;
end
endtask
task and_mux(
output reg carry_out,
input reg propagate1, propagate2, propagate3, propagate4, carry_in, csa_carry
);
reg temp_and;
begin
temp_and = propagate1 & propagate2 & propagate3 & propagate4;
if(temp_and)
begin
carry_out = carry_in;
end else
begin
carry_out = csa_carry;
end
end
endtask
task gen_propagate(
output reg [3:0]propagate,
input [3:0]in1,in2
);
begin
propagate[0] = in1[0] & in2[0];
propagate[1] = in1[1] & in2[1];
propagate[2] = in1[2] & in2[2];
propagate[3] = in1[3] & in2[3];
end
endtask
task CSA4bit(
output reg [3:0] csa_sum,
output reg csa_carry_out,
input [3:0] in1,in2,
input carry_in
);
reg carry1,carry2,carry3,carry4;
reg [3:0]propagate;
begin
gen_propagate (propagate, in1, in2);
CSAFA_module (csa_sum[0],carry1,in1[0],in2[0],carry_in);
CSAFA_module (csa_sum[1],carry2,in1[1],in2[1],carry1);
CSAFA_module (csa_sum[2],carry3,in1[2],in2[2],carry2);
CSAFA_module (csa_sum[3],carry4,in1[3],in2[3],carry3);
and_mux (csa_carry_out,propagate[0],propagate[1],propagate[2],propagate[3],carry_in,carry4);
end
endtask
task CSA8bit(
output reg [7:0] csa_sum,
output reg csa_carry_out,
input [7:0] in1,in2,
input carry_in
);
reg carry1;
begin
CSA4bit (csa_sum[3:0],carry1,in1[3:0],in2[3:0],carry_in);
CSA4bit (csa_sum[7:4],csa_carry_out,in1[7:4],in2[7:4],carry1);
end
endtask
task csa8_task(
output [DATA_WIDTH-1:0] adder_output,
output adder_carryout,
input [DATA_WIDTH-1:0] adder_in1, adder_in2,
input adder_carryin
);
begin
CSA8bit(adder_output,adder_carryout,adder_in1,adder_in2,adder_carryin);
end
endtask
task scsa8_task(
output [DATA_WIDTH-1:0] sub_output,
output sub_c_b_out,
input [DATA_WIDTH-1:0] sub_in1,sub_in2,
input sub_c_b_in
);
reg [DATA_WIDTH-1:0]temp;
begin
temp = ~sub_in2 + 8'b1;
CSA8bit(sub_output,sub_c_b_out, sub_in1, temp, sub_c_b_in);
end
endtask
reg [DATA_WIDTH-1:0]input1; // storing the 1st operand from the input vector
reg [DATA_WIDTH-1:0]input2; // storing the 2nd operand from the input vector
reg [OPCODE_LENGTH-1:0]opcode; // storing the opcode from the input vector
reg carry_in; // initial carry in
always @(posedge clk)
begin
if(reset_in)
begin
carry_in = 1'b0;
carry_output = 1'b0;
final_output = 8'b0;
prev_opcode_inputs = 0;
end else
begin
if(prev_opcode_inputs != opcode_inputs)
begin
prev_opcode_inputs = opcode_inputs;
opcode = opcode_inputs[VECTOR_LENGTH-1:VECTOR_LENGTH-OPCODE_LENGTH]; // opcode from the input vector
input1 = opcode_inputs[VECTOR_LENGTH-OPCODE_LENGTH-1:VECTOR_LENGTH-OPCODE_LENGTH-DATA_WIDTH]; // 1st operand from the input vector
input2 = opcode_inputs[VECTOR_LENGTH-OPCODE_LENGTH-DATA_WIDTH-1:VECTOR_LENGTH-OPCODE_LENGTH-DATA_WIDTH-DATA_WIDTH]; // 2nd operand from the input vector
$display("opcode: %d", opcode);
case (opcode)
NOP: begin
// $display ("NOP");
// nop_task(final_output);
final_output = 16'b0;
end
ADD: begin
// can be changed from the alu.vh file
`ifdef CSA_ADDITION
// $display ("CSA ADD");
CSA8bit(final_output,carry_output,input1, input2, carry_in);
`else
// $display ("CRA ADD");
CRA8bit(final_output,carry_output, input1, input2, carry_in);
`endif
end
SUBTRACT: begin
`ifdef CSA_ADDITION
// $display ("CSA SUB");
scsa8_task(final_output,carry_output,input1, input2, carry_in);
`else
// $display ("CRA SUB");
scra8_task(final_output,carry_output,input1, input2, carry_in);
`endif
end
AND: begin
// $display ("AND");
// and_task(final_output, carry_output, input1, input2);
carry_output = 1'b0;
final_output = input1 & input2;
end
OR: begin
// $display ("OR");
// or_task(final_output, carry_output, input1, input2);
carry_output = 1'b0;
final_output = input1 | input2;
end
ZERO_TEST: begin
// $display ("ZERO");
// zero_test_task(final_output, carry_output, input1);
carry_output = 1'b0;
if(input1 == 16'b0)
final_output = 16'b1;
else
final_output = 16'b0;
end
GREATER_THAN: begin
// $display ("GREATER THAN");
// greater_than_task(final_output, carry_output, input1, input2);
carry_output = 1'b0;
if(input1 > input2)
final_output = 16'b1;
else
final_output = 16'b0;
end
EQUAL: begin
// $display ("EQUAL");
// equal_task(final_output, carry_output, input1, input2);
carry_output = 1'b0;
if(input1 == input2)
final_output = 16'b1;
else
final_output = 16'b0;
end
LESS_THAN: begin
// $display ("LESS THAN");
// less_than_task(final_output, carry_output, input1, input2);
carry_output = 1'b0;
if(input1 < input2)
final_output = 16'b1;
else
final_output = 16'b0;
end
default: final_output = final_output;
endcase
// $display("final_out: %d, input1: %d, input1: %d", final_output, input1, input2);
end
end
end
assign zero_flag = final_output ? 1'b0 : 1'b1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_PP_SYMBOL_V
`define SKY130_FD_SC_MS__OR2_PP_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/23/2016 12:29:09 PM
// Design Name:
// Module Name: Week8Lab
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Week8Lab(
input Clk,
output reg [6:0] Cathodes,
output reg [3:0] Anode
);
reg[1:0 ] digit = 2'b00;
reg [27:0] Count;
reg Rate;
// Initialization
initial begin
Count = 0;
Rate = 0;
end
// Converts to 240 Hz
always @ (posedge Clk)
begin
if (Count == 216666)
begin
Rate = ~Rate;
Count = 0;
end
else
begin
Count = Count + 1;
end
end
// Turns on each led at 240hz per second
always @ (posedge Rate)
begin
case (digit)
// 4
2'b00: begin
Anode[0] = 0;
Anode[1] = 1;
Anode[2] = 1;
Anode[3] = 1;
Cathodes[0] = 1;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 1;
Cathodes[4] = 1;
Cathodes[5] = 0;
Cathodes[6] = 0;
end
// 3
2'b01: begin
Anode[0] = 1;
Anode[1] = 0;
Anode[2] = 1;
Anode[3] = 1;
Cathodes[0] = 0;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 0;
Cathodes[4] = 1;
Cathodes[5] = 1;
Cathodes[6] = 0;
end
// 2
2'b10: begin
Anode[0] = 1;
Anode[1] = 1;
Anode[2] = 0;
Anode[3] = 1;
Cathodes[0] = 0;
Cathodes[1] = 0;
Cathodes[2] = 1;
Cathodes[3] = 0;
Cathodes[4] = 0;
Cathodes[5] = 1;
Cathodes[6] = 0;
end
// 1
2'b11: begin
Anode[0] = 1;
Anode[1] = 1;
Anode[2] = 1;
Anode[3] = 0;
Cathodes[0] = 1;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 1;
Cathodes[4] = 1;
Cathodes[5] = 1;
Cathodes[6] = 1;
end
endcase
digit = digit + 1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SDFBBP_BEHAVIORAL_PP_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBP_BEHAVIORAL_PP_V
|
// Converts the 256-bit DMA master to the 64-bit PCIe slave
// Doesn't handle any special cases - the GUI validates that the parameters are consistant with our assumptions
module dma_pcie_bridge
(
clk,
reset,
// DMA interface (slave)
dma_address,
dma_read,
dma_readdata,
dma_readdatavalid,
dma_write,
dma_writedata,
dma_burstcount,
dma_byteenable,
dma_waitrequest,
// PCIe interface (master)
pcie_address,
pcie_read,
pcie_readdata,
pcie_readdatavalid,
pcie_write,
pcie_writedata,
pcie_burstcount,
pcie_byteenable,
pcie_waitrequest
);
// Parameters set from the GUI
parameter DMA_WIDTH = 256;
parameter PCIE_WIDTH = 64;
parameter DMA_BURSTCOUNT = 6;
parameter PCIE_BURSTCOUNT = 10;
parameter PCIE_ADDR_WIDTH = 30; // Byte-address width required
parameter ADDR_OFFSET = 0;
// Derived parameters
localparam DMA_WIDTH_BYTES = DMA_WIDTH / 8;
localparam PCIE_WIDTH_BYTES = PCIE_WIDTH / 8;
localparam WIDTH_RATIO = DMA_WIDTH / PCIE_WIDTH;
localparam ADDR_SHIFT = $clog2( WIDTH_RATIO );
localparam DMA_ADDR_WIDTH = PCIE_ADDR_WIDTH - $clog2( DMA_WIDTH_BYTES );
// Global ports
input clk;
input reset;
// DMA slave ports
input [DMA_ADDR_WIDTH-1:0] dma_address;
input dma_read;
output [DMA_WIDTH-1:0 ]dma_readdata;
output dma_readdatavalid;
input dma_write;
input [DMA_WIDTH-1:0] dma_writedata;
input [DMA_BURSTCOUNT-1:0] dma_burstcount;
input [DMA_WIDTH_BYTES-1:0] dma_byteenable;
output dma_waitrequest;
// PCIe master ports
output [31:0] pcie_address;
output pcie_read;
input [PCIE_WIDTH-1:0] pcie_readdata;
input pcie_readdatavalid;
output pcie_write;
output [PCIE_WIDTH-1:0] pcie_writedata;
output [PCIE_BURSTCOUNT-1:0] pcie_burstcount;
output [PCIE_WIDTH_BYTES-1:0] pcie_byteenable;
input pcie_waitrequest;
// Address decoding into byte-address
wire [31:0] dma_byte_address;
assign dma_byte_address = (dma_address * DMA_WIDTH_BYTES);
// Read logic - Buffer the pcie words into a full-sized dma word. The
// last word gets passed through, the first few words are stored
reg [DMA_WIDTH-1:0] r_buffer; // The last PCIE_WIDTH bits are not used and will be swept away
reg [$clog2(WIDTH_RATIO)-1:0] r_wc;
reg [DMA_WIDTH-1:0] r_demux;
wire [DMA_WIDTH-1:0] r_data;
wire r_full;
wire r_waitrequest;
// Full indicates that a full word is ready to be passed on to the DMA
// as soon as the next pcie-word arrives
assign r_full = &r_wc;
// True when a read request is being stalled (not a function of this unit)
assign r_waitrequest = pcie_waitrequest;
// Groups the previously stored words with the next read data on the pcie bus
assign r_data = {pcie_readdata, r_buffer[DMA_WIDTH-PCIE_WIDTH-1:0]};
// Store the first returned words in a buffer, keep track of which word
// we are waiting for in the word counter (r_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_wc <= {$clog2(DMA_WIDTH){1'b0}};
r_buffer <= {(DMA_WIDTH){1'b0}};
end
else
begin
r_wc <= pcie_readdatavalid ? (r_wc + 1) : r_wc;
if(pcie_readdatavalid)
r_buffer[ r_wc*PCIE_WIDTH +: PCIE_WIDTH ] <= pcie_readdata;
end
end
// Write logic - First word passes through, last words are registered
// and passed on to the fabric in order. Master is stalled until the
// full write has been completed (in PCIe word sized segments)
reg [$clog2(WIDTH_RATIO)-1:0] w_wc;
wire [PCIE_WIDTH_BYTES-1:0] w_byteenable;
wire [PCIE_WIDTH-1:0] w_writedata;
wire w_waitrequest;
wire w_sent;
// Indicates the successful transfer of a pcie-word to PCIe
assign w_sent = pcie_write && !pcie_waitrequest;
// Select the appropriate word to send downstream
assign w_writedata = dma_writedata[w_wc*PCIE_WIDTH +: PCIE_WIDTH];
assign w_byteenable = dma_byteenable[w_wc*PCIE_WIDTH_BYTES +: PCIE_WIDTH_BYTES];
// True when avalon is waiting, or the full word has not been written
assign w_waitrequest = (pcie_write && !(&w_wc)) || pcie_waitrequest;
// Keep track of which word segment we are sending in the word counter (w_wc)
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
w_wc <= {$clog2(DMA_WIDTH){1'b0}};
else
w_wc <= w_sent ? (w_wc + 1) : w_wc;
end
// Shared read/write logic
assign pcie_address = ADDR_OFFSET + dma_byte_address;
assign pcie_read = dma_read;
assign pcie_write = dma_write;
assign pcie_writedata = w_writedata;
assign pcie_burstcount = (dma_burstcount << ADDR_SHIFT);
assign pcie_byteenable = pcie_write ? w_byteenable : dma_byteenable;
assign dma_readdata = r_data;
assign dma_readdatavalid = r_full && pcie_readdatavalid;
assign dma_waitrequest = r_waitrequest || w_waitrequest;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_5_data_stream_1_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_5_data_stream_1_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_5_data_stream_1_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_5_data_stream_1_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`default_nettype none
module nkmd_ddr3_mig_if(
input wire clk,
input wire rst,
// MIG interface
output wire mig_cmd_clk,
output wire mig_cmd_en,
output wire [2:0] mig_cmd_instr,
output wire [5:0] mig_cmd_bl,
output wire [29:0] mig_cmd_byte_addr,
input wire mig_cmd_empty,
input wire mig_cmd_full,
output wire mig_wr_clk,
output wire mig_wr_en,
output wire [3:0] mig_wr_mask,
output wire [31:0] mig_wr_data,
input wire mig_wr_full,
input wire mig_wr_empty,
input wire [6:0] mig_wr_count,
input wire mig_wr_underrun,
input wire mig_wr_error,
output wire mig_rd_clk,
output wire mig_rd_en,
input wire [31:0] mig_rd_data,
input wire mig_rd_full,
input wire mig_rd_empty,
input wire [6:0] mig_rd_count,
input wire mig_rd_overflow,
input wire mig_rd_error,
// To nkmm bus
input wire [31:0] data_i,
output wire [31:0] data_o,
input wire [15:0] addr_i,
input wire we_i);
localparam SPAD_OFFSET = 4'h1;
reg [31:0] spad [1023:0];
wire [9:0] offset_i;
assign offset_i = addr_i[9:0];
reg [24:0] dma_dram_word_addr_ff;
reg [9:0] dma_spad_addr_ff;
reg [5:0] dma_burst_len_ff;
wire dma_complete;
reg [31:0] out_ff;
always @(posedge clk) begin
if (rst) begin
dma_dram_word_addr_ff <= 25'h0000;
dma_spad_addr_ff <= 10'h000;
dma_burst_len_ff <= 6'h00;
end else begin
if (addr_i[15:12] == SPAD_OFFSET) begin
if (we_i)
spad[offset_i] <= data_i;
out_ff <= spad[offset_i];
end else if (addr_i == 16'hc100) begin
if (we_i)
dma_dram_word_addr_ff <= data_i[26:2];
out_ff <= {5'b00000, dma_dram_word_addr_ff, 2'b00};
end else if (addr_i == 16'hc101) begin
if (we_i)
dma_spad_addr_ff <= data_i[9:0];
out_ff <= {12'b0, dma_spad_addr_ff};
end else if (addr_i == 16'hc102) begin
if (we_i)
dma_burst_len_ff <= data_i[5:0];
out_ff <= {26'b0, dma_burst_len_ff};
end else if (addr_i == 16'hc103) begin
out_ff <= {31'b0, dma_complete};
end else begin
out_ff <= 32'h0;
end
end
end
assign data_o = out_ff;
reg [5:0] dma_state_ff;
localparam ST_INIT = 0;
localparam ST_FILL_WRBUF = 1;
localparam ST_EMIT_WR_CMD = 2;
localparam ST_EMIT_RD_CMD = 3;
localparam ST_WAIT_RD_DATA = 4;
reg [5:0] dma_burst_left_ff;
always @(posedge clk) begin
if (rst) begin
dma_state_ff <= ST_INIT;
end else begin
case (dma_state_ff)
ST_INIT: begin
dma_burst_left_ff <= dma_burst_len_ff;
if (we_i && addr_i == 16'hc103) begin
if (data_i[0] == 1'b1) begin
dma_spad_addr_ff <= dma_spad_addr_ff + 1;
dma_state_ff <= ST_FILL_WRBUF;
end else begin
dma_state_ff <= ST_EMIT_RD_CMD;
end
end
end
ST_FILL_WRBUF: begin
if (dma_burst_left_ff != 6'h00) begin
dma_spad_addr_ff <= dma_spad_addr_ff + 1;
dma_burst_left_ff <= dma_burst_left_ff - 1;
dma_state_ff <= ST_FILL_WRBUF;
end else begin
dma_state_ff <= ST_EMIT_WR_CMD;
end
end
ST_EMIT_WR_CMD: begin
dma_state_ff <= ST_INIT;
end
ST_EMIT_RD_CMD: begin
dma_state_ff <= ST_WAIT_RD_DATA;
end
ST_WAIT_RD_DATA: begin
if (mig_rd_count == 6'h00) begin // FIXME: mig_rd_empty?
dma_state_ff <= ST_WAIT_RD_DATA;
end else begin
spad[dma_spad_addr_ff] <= mig_rd_data;
if (dma_burst_left_ff != 6'h00) begin
dma_spad_addr_ff <= dma_spad_addr_ff + 1;
dma_burst_left_ff <= dma_burst_left_ff - 1;
dma_state_ff <= ST_WAIT_RD_DATA;
end else begin
dma_state_ff <= ST_INIT;
end
end
end
endcase
end
end
assign dma_complete = dma_state_ff == ST_INIT;
assign mig_cmd_clk = clk;
assign mig_cmd_en = (dma_state_ff == ST_EMIT_RD_CMD || dma_state_ff == ST_EMIT_WR_CMD) ? 1'b1 : 1'b0;
assign mig_cmd_instr = (dma_state_ff == ST_EMIT_RD_CMD) ? 3'b011 : 3'b010;
assign mig_cmd_bl = dma_burst_len_ff;
assign mig_cmd_byte_addr[29:0] = {3'b000, dma_dram_word_addr_ff, 2'b00};
// FIXME: wait until mig_cmd_empty or !mig_cmd_full?
assign mig_wr_clk = clk;
assign mig_wr_en = (dma_state_ff == ST_FILL_WRBUF);
assign mig_wr_mask = 4'b0000;
reg [31:0] mig_wr_data_ff;
always @(posedge clk)
mig_wr_data_ff <= spad[dma_spad_addr_ff];
assign mig_wr_data = mig_wr_data_ff;
// mig_wr_full, mig_wr_empty, mig_wr_count, mig_wr_underrun, mig_wr_error
assign mig_rd_clk = clk;
assign mig_rd_en = (dma_state_ff == ST_WAIT_RD_DATA) ? 1'b1 : 1'b0;
// mig_rd_full, mig_rd_empty, mig_rd_overflow, mig_rd_error
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long powm(long long a, long long n) { long long base = 1; a %= MOD; while (n) { if (n & 1) base = base * a % MOD; a = a * a % MOD; n >>= 1; } return base; } int main() { long long a, b, t; cin >> a >> b >> t; if ((a & 1) != (b & 1) && t == -1) { cout << 0 << endl; return 0; } long long ans = powm(2, a - 1); ans = powm(ans, b - 1); cout << ans << endl; }
|
/****************************************************************************
Register File
- Has two read ports (a and b) and one write port (c)
- sel chooses the register to be read/written
****************************************************************************/
module reg_file(clk,resetn,
a_reg, a_readdataout, a_en,
b_reg, b_readdataout, b_en,
c_reg, c_writedatain, c_we);
parameter WIDTH=32;
parameter NUMREGS=32;
parameter LOG2NUMREGS=5;
input clk;
input resetn;
input a_en;
input b_en;
input [LOG2NUMREGS-1:0] a_reg,b_reg,c_reg;
output [WIDTH-1:0] a_readdataout, b_readdataout;
input [WIDTH-1:0] c_writedatain;
input c_we;
altsyncram reg_file1(
.wren_a (c_we&(|c_reg)),
.clock0 (clk),
.clock1 (clk),
.clocken1 (a_en),
.address_a (c_reg[LOG2NUMREGS-1:0]),
.address_b (a_reg[LOG2NUMREGS-1:0]),
.data_a (c_writedatain),
.q_b (a_readdataout)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.wren_b (1'b0),
.rden_b(1'b1),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
reg_file1.operation_mode = "DUAL_PORT",
reg_file1.width_a = WIDTH,
reg_file1.widthad_a = LOG2NUMREGS,
reg_file1.numwords_a = NUMREGS,
reg_file1.width_b = WIDTH,
reg_file1.widthad_b = LOG2NUMREGS,
reg_file1.numwords_b = NUMREGS,
reg_file1.lpm_type = "altsyncram",
reg_file1.width_byteena_a = 1,
reg_file1.outdata_reg_b = "UNREGISTERED",
reg_file1.indata_aclr_a = "NONE",
reg_file1.wrcontrol_aclr_a = "NONE",
reg_file1.address_aclr_a = "NONE",
reg_file1.rdcontrol_reg_b = "CLOCK1",
reg_file1.address_reg_b = "CLOCK1",
reg_file1.address_aclr_b = "NONE",
reg_file1.outdata_aclr_b = "NONE",
reg_file1.read_during_write_mode_mixed_ports = "OLD_DATA",
reg_file1.ram_block_type = "AUTO",
reg_file1.intended_device_family = "Stratix";
//Reg file duplicated to avoid contention between 2 read
//and 1 write
altsyncram reg_file2(
.wren_a (c_we&(|c_reg)),
.clock0 (clk),
.clock1 (clk),
.clocken1 (b_en),
.address_a (c_reg[LOG2NUMREGS-1:0]),
.address_b (b_reg[LOG2NUMREGS-1:0]),
.data_a (c_writedatain),
.q_b (b_readdataout)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.rden_b(1'b1),
.wren_b (1'b0),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
reg_file2.operation_mode = "DUAL_PORT",
reg_file2.width_a = WIDTH,
reg_file2.widthad_a = LOG2NUMREGS,
reg_file2.numwords_a = NUMREGS,
reg_file2.width_b = WIDTH,
reg_file2.widthad_b = LOG2NUMREGS,
reg_file2.numwords_b = NUMREGS,
reg_file2.lpm_type = "altsyncram",
reg_file2.width_byteena_a = 1,
reg_file2.outdata_reg_b = "UNREGISTERED",
reg_file2.indata_aclr_a = "NONE",
reg_file2.wrcontrol_aclr_a = "NONE",
reg_file2.address_aclr_a = "NONE",
reg_file2.rdcontrol_reg_b = "CLOCK1",
reg_file2.address_reg_b = "CLOCK1",
reg_file2.address_aclr_b = "NONE",
reg_file2.outdata_aclr_b = "NONE",
reg_file2.read_during_write_mode_mixed_ports = "OLD_DATA",
reg_file2.ram_block_type = "AUTO",
reg_file2.intended_device_family = "Stratix";
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/30 21:00:17
// Design Name:
// Module Name: lab5_2_4_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab5_2_4_tb(
);
reg D,Clk,ce,reset;
wire Q;
lab5_2_4 dut(D,Clk,reset,ce,Q);
initial
begin
for(Clk = 0;Clk >= 0;Clk=Clk+1)
begin
#10;
end
end
initial
begin
D = 0;
#20 D = 1;
#80 D = 0;
#120 D = 1;
end
initial
begin
ce = 0;
#60 ce = 1;
#20 ce = 0;
#100 ce = 1;
#20 ce = 0;
#60 ce = 1;
#20 ce = 0;
end
initial
begin
reset = 0;
#120 reset = 1;
#20 reset = 0;
end
endmodule
|
// cog_ram
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module cog_ram
(
input clk,
input ena,
input w,
input [8:0] a,
input [31:0] d,
output reg [31:0] q
);
// 512 x 32 ram
reg [511:0] [31:0] r;
always @(posedge clk)
begin
if (ena && w)
r[a] <= d;
if (ena)
q <= r[a];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFXBP_PP_BLACKBOX_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1000000000 + 7; const double esp = 1e-13; const double pi = 3.141592653589; int n, m, f[100 + 10][100 + 10]; char a[100 + 10][100 + 10]; int main() { ios ::sync_with_stdio(false); cin >> n >> m; for (int i = (1), _b = (n); i <= _b; i++) for (int j = (1), _b = (m); j <= _b; j++) cin >> a[i][j]; memset(f, 0, sizeof(f)); for (int i = (1), _b = (n); i <= _b; i++) for (int j = (1), _b = (m); j <= _b; j++) { for (int k = (1), _b = (m); k <= _b; k++) if (a[i][j] == a[i][k] && j != k) f[i][j] = 1, f[i][k] = 1; for (int k = (1), _b = (n); k <= _b; k++) if (a[i][j] == a[k][j] && i != k) f[i][j] = 1, f[k][j] = 1; } for (int i = (1), _b = (n); i <= _b; i++) for (int j = (1), _b = (m); j <= _b; j++) if (f[i][j] == 0) cout << a[i][j]; }
|
#include <bits/stdc++.h> int m(int a) { int ret = 0, i = 1; while (a > 0) { if (a % 10 == 4 || a % 10 == 7) { ret += (i * (a % 10)), i *= 10; } a /= 10; } return ret; } int main() { int a, b; while (scanf( %d%d , &a, &b) != EOF) { while (1) { a++; if (m(a) == b) { printf( %d n , a); return 0; } } } }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_jbusl_jbus.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cl_jbusl_jbus(cluster_grst_l ,so ,dbginit_l ,si ,se ,
adbginit_l ,gdbginit_l ,arst_l ,grst_l ,cluster_cken ,gclk ,rclk );
output cluster_grst_l ;
output so ;
output dbginit_l ;
output rclk ;
input si ;
input se ;
input adbginit_l ;
input gdbginit_l ;
input arst_l ;
input grst_l ;
input cluster_cken ;
input gclk ;
wire [3:0] noclk ;
wire [2:0] clk3 ;
wire [1:0] clk4 ;
wire clk5 ;
wire cclk ;
bw_clk_cclk_inv_64x xc3a (
.clkout (clk3[0] ),
.clkin (clk4[0] ) );
bw_clk_cclk_inv_64x xc3b (
.clkout (clk3[1] ),
.clkin (clk4[0] ) );
bw_clk_cclk_inv_128x xgriddrv_3_ (
.clkout (rclk ),
.clkin (clk3[0] ) );
bw_clk_cclk_inv_128x xgriddrv_11_ (
.clkout (noclk[2] ),
.clkin (clk3[2] ) );
bw_clk_cclk_inv_64x xc4a (
.clkout (clk4[0] ),
.clkin (clk5 ) );
bw_clk_cclk_inv_64x xc4b (
.clkout (clk4[1] ),
.clkin (clk5 ) );
bw_clk_cclk_inv_128x xgriddrv_2_ (
.clkout (rclk ),
.clkin (clk3[0] ) );
bw_clk_cclk_hdr_48x xCCHdr (
.rst_l (cluster_grst_l ),
.dbginit_l (dbginit_l ),
.clk (cclk ),
.so (so ),
.gclk (gclk ),
.cluster_cken (cluster_cken ),
.arst_l (arst_l ),
.grst_l (grst_l ),
.adbginit_l (adbginit_l ),
.gdbginit_l (gdbginit_l ),
.si (si ),
.se (se ),
.rclk (rclk ) );
bw_clk_cclk_inv_128x xgriddrv_9_ (
.clkout (noclk[0] ),
.clkin (clk3[2] ) );
bw_clk_cclk_inv_128x xgriddrv_1_ (
.clkout (rclk ),
.clkin (clk3[0] ) );
terminator I26_0_ (
.TERM (noclk[0] ) );
bw_clk_cclk_inv_128x xgriddrv_8_ (
.clkout (rclk ),
.clkin (clk3[2] ) );
bw_clk_cclk_inv_128x xgriddrv_0_ (
.clkout (rclk ),
.clkin (clk3[0] ) );
bw_clk_cclk_inv_128x xgriddrv_10_ (
.clkout (noclk[1] ),
.clkin (clk3[2] ) );
bw_clk_cclk_inv_48x xc5 (
.clkout (clk5 ),
.clkin (cclk ) );
terminator I26_1_ (
.TERM (noclk[1] ) );
bw_clk_cclk_inv_128x xgriddrv_7_ (
.clkout (rclk ),
.clkin (clk3[1] ) );
terminator I25 (
.TERM (noclk[3] ) );
terminator I26_2_ (
.TERM (noclk[2] ) );
bw_clk_cclk_inv_128x xgriddrv_6_ (
.clkout (rclk ),
.clkin (clk3[1] ) );
bw_clk_cclk_inv_128x xgriddrv_5_ (
.clkout (rclk ),
.clkin (clk3[1] ) );
bw_clk_cclk_inv_128x xgriddrv_4_ (
.clkout (rclk ),
.clkin (clk3[1] ) );
bw_clk_cclk_inv_64x x0 (
.clkout (clk3[2] ),
.clkin (clk4[1] ) );
bw_clk_cclk_inv_64x x1 (
.clkout (noclk[3] ),
.clkin (clk4[1] ) );
endmodule
|
// chris_slave.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module chris_slave (
input wire [3:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire LEDR // LEDR.ledr
);
// TODO: Auto-generated HDL template
reg [31:0] reg_out;
assign avs_s0_readdata = reg_out;
reg Reg_Status_Read;
reg Reg_Status_Write;
reg [31:0] reg_value[8:0];
reg led_out;
reg [31:0] reg_res;
//
//
//
assign avs_s0_waitrequest = Reg_Status_Read&Reg_Status_Write;
assign LEDR = led_out;
reg reg_module_caculation_end;
reg reg_modue_caculating_start;
reg reg_module_end;
reg reg_module_start;
convolution_core instance_convolution(.clk(clock_clk),
.reset(reset_reset),
.value0(reg_value[0]),
.value1(reg_value[1]),
.value2(reg_value[2]),
.value3(reg_value[3]),
.value4(reg_value[4]),
.value5(reg_value[5]),
.value6(reg_value[6]),
.value7(reg_value[7]),
.value8(reg_value[8]),
.caculating_start(reg_modue_caculating_start),
.caculating_done(reg_module_caculation_end),
.res_done(reg_module_end),
.ret(reg_res)
);
reg [3:0] reg_current_status, reg_next_status;
parameter IDLE = 4'b0001;
parameter CALCULATING = 4'b0010;
parameter WAITTING = 4'b0100;
parameter FINISH = 4'b1000;
// machine status
always@(posedge clock_clk)
begin
if(reset_reset)
reg_current_status <= IDLE;
else
reg_current_status <= reg_next_status;
end
// machine's next status
always@(reg_current_status or reg_read_done or reg_module_caculation_end or reg_write_done or reset_reset)
begin
if(reset_reset)
reg_next_status = IDLE;
else
begin
case(reg_current_status)
IDLE:reg_next_status = reg_read_done?CALCULATING:IDLE;
CALCULATING:reg_next_status = reg_module_caculation_end?WAITTING:CALCULATING;
WAITTING:reg_next_status = reg_write_done?FINISH:WAITTING;
FINISH: reg_next_status = IDLE;
default: reg_next_status = IDLE;
endcase
end
end
always@(posedge clock_clk) begin
if (reset_reset) begin
led_out <= 1'b0;
end else begin
case(reg_current_status)
IDLE: begin
reg_module_start<= 1'b0;
reg_module_end <= 1'b0;
reg_modue_caculating_start <= 1'b0;
end
CALCULATING: begin
led_out <= 1'b1;
reg_module_start <= 1'b1;
reg_modue_caculating_start <= 1'b1;
end
WAITTING:begin
reg_modue_caculating_start <= 1'b0;
reg_module_end <= 1'b1;
end
FINISH:begin
reg_module_start <= 1'b0;
reg_module_end <= 1'b0;
reg_modue_caculating_start <= 1'b0;
led_out <= 1'b0;
end
default:begin
end
endcase
end
end
// WRITE LOGIC
//
reg reg_read_done;
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Write <= 1'b1;
reg_value[0] <= 32'h00000000;
reg_value[1] <= 32'h00000000;
reg_value[2] <= 32'h00000000;
reg_value[3] <= 32'h00000000;
reg_value[4] <= 32'h00000000;
reg_value[5] <= 32'h00000000;
reg_value[6] <= 32'h00000000;
reg_value[7] <= 32'h00000000;
reg_value[8] <= 32'h00000000;
reg_read_done <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_write) begin
case (avs_s0_address[3:0])
4'b0000: reg_value[0] <= avs_s0_writedata;
4'b0001: reg_value[1] <= avs_s0_writedata;
4'b0010: reg_value[2] <= avs_s0_writedata;
4'b0011: reg_value[3] <= avs_s0_writedata;
4'b0100: reg_value[4] <= avs_s0_writedata;
4'b0101: reg_value[5] <= avs_s0_writedata;
4'b0110: reg_value[6] <= avs_s0_writedata;
4'b0111: reg_value[7] <= avs_s0_writedata;
4'b1000:begin
reg_value[8] <= avs_s0_writedata;
reg_read_done <= 1'b1; // read done;
end
endcase
Reg_Status_Write <= 1'b1;
end else if (avs_s0_waitrequest && avs_s0_write && reg_module_start == 1'b0)begin
Reg_Status_Write <= 1'b0;
end else begin
//revert reg_read_done to 0 at here when it's done /
if(reg_module_end) begin
reg_read_done <= 1'b0;
end
Reg_Status_Write <= 1'b1;
end
//
// x and z values are don't-care's
// READ LOGIC
reg reg_write_done;
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Read <= 1'b1;
end else if (!avs_s0_waitrequest && avs_s0_read) begin
Reg_Status_Read <= 1'b1;
reg_write_done <= 1'b1;
end else if(avs_s0_waitrequest && avs_s0_read && reg_module_caculation_end) begin
case (avs_s0_address[3:0])
4'b0000: reg_out <= reg_value[0];
4'b0001: reg_out <= reg_value[1];
4'b0010: reg_out <= reg_value[2];
4'b0011: reg_out <= reg_value[3];
4'b0100: reg_out <= reg_value[4];
4'b0101: reg_out <= reg_value[5];
4'b0110: reg_out <= reg_value[6];
4'b0111: reg_out <= reg_value[7];
4'b1000: reg_out <= reg_value[8];
4'b1001: reg_out <= reg_res;
default:reg_out <= 32'hffffffff;
endcase
Reg_Status_Read <= 1'b0;
end else begin
Reg_Status_Read <= 1'b1;
if (reg_module_end) begin
reg_write_done <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> int getbit(T s, int i) { return (s >> i) & 1; } template <class T> T onbit(T s, int i) { return s | (T(1) << i); } template <class T> T offbit(T s, int i) { return s & (~(T(1) << i)); } template <class T> int cntbit(T s) { return __builtin_popcount(s); } template <class T> T gcd(T a, T b) { T r; while (b != 0) { r = a % b; a = b; b = r; } return a; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } int n, m; vector<int> V[200005]; int res[200005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; for (int i = (1); i <= (n); ++i) { int x; cin >> x; V[x].push_back(i); } int RR = 1; for (int i = (1); i <= (m); ++i) { int x; cin >> x; if (V[x].size() > 1 && RR == 1) { RR = 2; } else if (V[x].size() == 0) { RR = 0; } if (RR == 1) { res[i] = V[x][0]; } } if (!RR) { cout << Impossible << endl; } else if (RR == 1) { cout << Possible << endl; for (int i = (1); i <= (m); ++i) cout << res[i] << ; } else { cout << Ambiguity << endl; } return 0; }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
module altera_up_video_dma_to_stream (
// Inputs
clk,
reset,
stream_ready,
master_readdata,
master_readdatavalid,
master_waitrequest,
reading_first_pixel_in_frame,
reading_last_pixel_in_frame,
// Bidirectional
// Outputs
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_arbiterlock,
master_read,
inc_address,
reset_address
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter MDW = 15; // Avalon master's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input stream_ready;
input [MDW:0] master_readdata;
input master_readdatavalid;
input master_waitrequest;
input reading_first_pixel_in_frame;
input reading_last_pixel_in_frame;
// Bidirectional
// Outputs
output [DW: 0] stream_data;
output stream_startofpacket;
output stream_endofpacket;
output [EW: 0] stream_empty;
output stream_valid;
output master_arbiterlock;
output master_read;
output inc_address;
output reset_address;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam STATE_0_IDLE = 2'h0,
STATE_1_WAIT_FOR_LAST_PIXEL = 2'h1,
STATE_2_READ_BUFFER = 2'h2,
STATE_3_MAX_PENDING_READS_STALL = 2'h3;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [(DW+2):0] fifo_data_in;
wire fifo_read;
wire fifo_write;
wire [(DW+2):0] fifo_data_out;
wire fifo_empty;
wire fifo_full;
wire fifo_almost_empty;
wire fifo_almost_full;
// Internal Registers
reg [ 3: 0] pending_reads;
reg startofpacket;
// State Machine Registers
reg [ 1: 0] s_dma_to_stream;
reg [ 1: 0] ns_dma_to_stream;
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset & ~master_waitrequest)
s_dma_to_stream <= STATE_0_IDLE;
else
s_dma_to_stream <= ns_dma_to_stream;
end
always @(*)
begin
case (s_dma_to_stream)
STATE_0_IDLE:
begin
if (reset)
ns_dma_to_stream = STATE_0_IDLE;
else if (fifo_almost_empty)
ns_dma_to_stream = STATE_2_READ_BUFFER;
else
ns_dma_to_stream = STATE_0_IDLE;
end
STATE_1_WAIT_FOR_LAST_PIXEL:
begin
if (pending_reads == 4'h0)
ns_dma_to_stream = STATE_0_IDLE;
else
ns_dma_to_stream = STATE_1_WAIT_FOR_LAST_PIXEL;
end
STATE_2_READ_BUFFER:
begin
if (~master_waitrequest)
begin
if (reading_last_pixel_in_frame)
ns_dma_to_stream = STATE_1_WAIT_FOR_LAST_PIXEL;
else if (fifo_almost_full)
ns_dma_to_stream = STATE_0_IDLE;
else if (pending_reads >= 4'hC)
ns_dma_to_stream = STATE_3_MAX_PENDING_READS_STALL;
else
ns_dma_to_stream = STATE_2_READ_BUFFER;
end
else
ns_dma_to_stream = STATE_2_READ_BUFFER;
end
STATE_3_MAX_PENDING_READS_STALL:
begin
if (pending_reads <= 4'h7)
ns_dma_to_stream = STATE_2_READ_BUFFER;
else if (fifo_almost_full)
ns_dma_to_stream = STATE_0_IDLE;
else
ns_dma_to_stream = STATE_3_MAX_PENDING_READS_STALL;
end
default:
begin
ns_dma_to_stream = STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset)
pending_reads <= 4'h0;
else if (master_read & ~master_waitrequest)
begin
if (~master_readdatavalid)
pending_reads <= pending_reads + 1'h1;
end
else if (master_readdatavalid & (pending_reads != 4'h0))
pending_reads <= pending_reads - 1'h1;
end
always @(posedge clk)
begin
if (reset)
startofpacket <= 1'b0;
else if ((s_dma_to_stream == STATE_0_IDLE) & (reading_first_pixel_in_frame))
startofpacket <= 1'b1;
else if (master_readdatavalid)
startofpacket <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_data = fifo_data_out[DW:0];
assign stream_startofpacket = fifo_data_out[DW+1];
assign stream_endofpacket = fifo_data_out[DW+2];
assign stream_empty = 'h0;
assign stream_valid = ~fifo_empty;
assign master_arbiterlock = !((s_dma_to_stream == STATE_2_READ_BUFFER) |
(s_dma_to_stream == STATE_3_MAX_PENDING_READS_STALL));
assign master_read = (s_dma_to_stream == STATE_2_READ_BUFFER);
assign inc_address = master_read & ~master_waitrequest;
assign reset_address = inc_address & reading_last_pixel_in_frame;
// Internal Assignments
assign fifo_data_in[DW:0] = master_readdata[DW:0];
assign fifo_data_in[DW+1] = startofpacket;
assign fifo_data_in[DW+2] = (s_dma_to_stream == STATE_1_WAIT_FOR_LAST_PIXEL) &
(pending_reads == 4'h1);
assign fifo_write = master_readdatavalid & ~fifo_full;
assign fifo_read = stream_ready & stream_valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Image_Buffer (
// Inputs
.clock (clk),
.sclr (reset),
.data (fifo_data_in),
.wrreq (fifo_write),
.rdreq (fifo_read),
// Outputs
.q (fifo_data_out),
.empty (fifo_empty),
.full (fifo_full),
.almost_empty (fifo_almost_empty),
.almost_full (fifo_almost_full),
// synopsys translate_off
.aclr (),
.usedw ()
// synopsys translate_on
);
defparam
Image_Buffer.add_ram_output_register = "OFF",
Image_Buffer.almost_empty_value = 32,
Image_Buffer.almost_full_value = 96,
Image_Buffer.intended_device_family = "Cyclone II",
Image_Buffer.lpm_numwords = 128,
Image_Buffer.lpm_showahead = "ON",
Image_Buffer.lpm_type = "scfifo",
Image_Buffer.lpm_width = DW + 3,
Image_Buffer.lpm_widthu = 7,
Image_Buffer.overflow_checking = "OFF",
Image_Buffer.underflow_checking = "OFF",
Image_Buffer.use_eab = "ON";
endmodule
|
#include <bits/stdc++.h> using namespace std; long long num[300010]; long long sum[300010]; int n; bool cmp(int a, int b) { return a > b; } int main() { while (~scanf( %d , &n)) { for (int i = 0; i < n; i++) cin >> num[i]; sort(num, num + n, cmp); sum[0] = num[0]; for (int i = 1; i < n; i++) { sum[i] = sum[i - 1] + num[i]; } long long ans = sum[n - 1]; for (int i = n - 2; i >= 0; i--) ans += sum[i] + num[n - 1 - i]; cout << ans << endl; } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 3-State Diffential Signaling I/O Buffer
// /___/ /\ Filename : IOBUFDS_DIFF_OUT_DCIEN.v
// \ \ / \ Timestamp : Thu Apr 29 14:59:30 PDT 2010
// \___\/\___\
//
// Revision:
// 04/29/10 - Initial version.
// 03/28/11 - CR 603466 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUFDS_DIFF_OUT_DCIEN (O, OB, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, TM, TS);
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
output OB;
inout IO;
inout IOB;
input DCITERMDISABLE;
input I;
input IBUFDISABLE;
input TM;
input TS;
// define constants
localparam MODULE_NAME = "IOBUFDS_DIFF_OUT_DCIEN";
wire t1, t2, out_val, out_b_val;
wire T_OR_IBUFDISABLE_1;
wire T_OR_IBUFDISABLE_2;
tri0 GTS = glbl.GTS;
or O1 (t1, GTS, TM);
bufif0 B1 (IO, I, t1);
or O2 (t2, GTS, TS);
notif0 N2 (IOB, I, t2);
reg O_int, OB_int;
reg DQS_BIAS_BINARY = 1'b0;
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS_DIFF_OUT_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
#1 $finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUFDS_DIFF_OUT_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on IOBUFDS_DIFF_OUT_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DQS_BIAS);
#1 $finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2")) begin
$display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
#1 $finish;
end
end
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
assign out_b_val = 1'b1;
end
"ULTRASCALE" : begin
assign out_val = 1'b0;
assign out_b_val = 1'bx;
end
default : begin
assign out_val = 1'b0;
assign out_b_val = 1'b0;
end
endcase
endgenerate
always @(IO or IOB or DQS_BIAS_BINARY) begin
if (IO == 1'b1 && IOB == 1'b0) begin
O_int <= IO;
OB_int <= ~IO;
end
else if (IO == 1'b0 && IOB == 1'b1) begin
O_int <= IO;
OB_int <= ~IO;
end
else if ((IO === 1'bz || IO == 1'b0) && (IOB === 1'bz || IOB == 1'b1)) begin
if (DQS_BIAS_BINARY == 1'b1) begin
O_int <= 1'b0;
OB_int <= 1'b1;
end else begin
O_int <= 1'bx;
OB_int <= 1'bx;
end
end
else begin
O_int <= 1'bx;
OB_int <= 1'bx;
end
end
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign T_OR_IBUFDISABLE_1 = ~TM || IBUFDISABLE;
assign T_OR_IBUFDISABLE_2 = ~TS || IBUFDISABLE;
assign O = (T_OR_IBUFDISABLE_1 == 1'b1) ? out_val : (T_OR_IBUFDISABLE_1 == 1'b0) ? O_int : 1'bx;
assign OB = (T_OR_IBUFDISABLE_2 == 1'b1) ? out_b_val : (T_OR_IBUFDISABLE_2 == 1'b0) ? OB_int : 1'bx;
end
"FALSE" : begin
assign O = O_int;
assign OB = OB_int;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(DCITERMDISABLE => OB) = (0:0:0, 0:0:0);
(DCITERMDISABLE => IO) = (0:0:0, 0:0:0);
(DCITERMDISABLE => IOB) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(I => IOB) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IO => OB) = (0:0:0, 0:0:0);
(IO => IOB) = (0:0:0, 0:0:0);
(IOB => O) = (0:0:0, 0:0:0);
(IOB => OB) = (0:0:0, 0:0:0);
(IOB => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => OB) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(IBUFDISABLE => IOB) = (0:0:0, 0:0:0);
(TM => O) = (0:0:0, 0:0:0);
(TM => OB) = (0:0:0, 0:0:0);
(TM => IO) = (0:0:0, 0:0:0);
(TM => IOB) = (0:0:0, 0:0:0);
(TS => O) = (0:0:0, 0:0:0);
(TS => OB) = (0:0:0, 0:0:0);
(TS => IO) = (0:0:0, 0:0:0);
(TS => IOB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
//wb_gpio.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
8/31/2012
-Changed some of the naming for clarity
10/29/2011
-added an 'else' statement that so either the
reset HDL will be executed or the actual code
not both
10/23/2011
-fixed the wbs_ack_i to o_wbs_ack
-added the default entries for read and write
to illustrate the method of communication
-added license
9/10/2011
-removed the duplicate wbs_dat_i
-added the wbs_sel_i port
*/
/*
Use this to tell sycamore how to populate the Device ROM table
so that users can interact with your slave
META DATA
identification of your device 0 - 65536
DRT_ID: 1
flags (read drt.txt in the slave/device_rom_table directory 1 means
a standard device
DRT_FLAGS: 1
number of registers this should be equal to the nubmer of ???
parameters
DRT_SIZE: 5
USER_PARAMETER: DEFAULT_INTERRUPT_MASK
USER_PARAMETER: DEFAULT_INTERRUPT_EDGE
*/
module wb_gpio#(
parameter DEFAULT_INTERRUPT_MASK = 0,
parameter DEFAULT_INTERRUPT_EDGE = 0
)(
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int,
input [31:0] gpio_in
);
localparam GPIO = 32'h00000000;
localparam GPIO_OUTPUT_ENABLE = 32'h00000001;
localparam INTERRUPTS = 32'h00000002;
localparam INTERRUPT_ENABLE = 32'h00000003;
localparam INTERRUPT_EDGE = 32'h00000004;
//gpio registers
reg [31:0] gpio_direction;
wire [31:0] gpio;
//interrupt registers
reg [31:0] interrupts;
reg [31:0] interrupt_mask;
reg [31:0] interrupt_edge;
reg clear_interrupts;
endmodule
|
// Chuck Benz, Hollis, NH Copyright (c)2002
//
// The information and description contained herein is the
// property of Chuck Benz.
//
// Permission is granted for any reuse of this information
// and description as long as this copyright notice is
// preserved. Modifications may be made as long as this
// notice is preserved.
// per Widmer and Franaszek
module encode (datain, dispin, dataout, dispout) ;
input [8:0] datain ;
input dispin ; // 0 = neg disp; 1 = pos disp
output [9:0] dataout ;
output dispout ;
wire ai = datain[0] ;
wire bi = datain[1] ;
wire ci = datain[2] ;
wire di = datain[3] ;
wire ei = datain[4] ;
wire fi = datain[5] ;
wire gi = datain[6] ;
wire hi = datain[7] ;
wire ki = datain[8] ;
wire aeqb = (ai & bi) | (!ai & !bi) ;
wire ceqd = (ci & di) | (!ci & !di) ;
wire l22 = (ai & bi & !ci & !di) |
(ci & di & !ai & !bi) |
( !aeqb & !ceqd) ;
wire l40 = ai & bi & ci & di ;
wire l04 = !ai & !bi & !ci & !di ;
wire l13 = ( !aeqb & !ci & !di) |
( !ceqd & !ai & !bi) ;
wire l31 = ( !aeqb & ci & di) |
( !ceqd & ai & bi) ;
// The 5B/6B encoding
wire ao = ai ;
wire bo = (bi & !l40) | l04 ;
wire co = l04 | ci | (ei & di & !ci & !bi & !ai) ;
wire do = di & ! (ai & bi & ci) ;
wire eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai) ;
wire io = (l22 & !ei) |
(ei & !di & !ci & !(ai&bi)) | // D16, D17, D18
(ei & l40) |
(ki & ei & di & ci & !bi & !ai) | // K.28
(ei & !di & ci & !bi & !ai) ;
// pds16 indicates cases where d-1 is assumed + to get our encoded value
wire pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31) ;
// nds16 indicates cases where d-1 is assumed - to get our encoded value
wire nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai) ;
// ndos6 is pds16 cases where d-1 is + yields - disp out - all of them
wire ndos6 = pd1s6 ;
// pdos6 is nds16 cases where d-1 is - yields + disp out - all but one
wire pdos6 = ki | (ei & !l22 & !l13) ;
// some Dx.7 and all Kx.7 cases result in run length of 5 case unless
// an alternate coding is used (referred to as Dx.A7, normal is Dx.P7)
// specifically, D11, D13, D14, D17, D18, D19.
wire alt7 = fi & gi & hi & (ki |
(dispin ? (!ei & di & l31) : (ei & !di & l13))) ;
wire fo = fi & ! alt7 ;
wire go = gi | (!fi & !gi & !hi) ;
wire ho = hi ;
wire jo = (!hi & (gi ^ fi)) | alt7 ;
// nd1s4 is cases where d-1 is assumed - to get our encoded value
wire nd1s4 = fi & gi ;
// pd1s4 is cases where d-1 is assumed + to get our encoded value
wire pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))) ;
// ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some
wire ndos4 = (!fi & !gi) ;
// pdos4 is nd1s4 cases where d-1 is - yields + disp out
wire pdos4 = fi & gi & hi ;
// only legal K codes are K28.0->.7, K23/27/29/30.7
// K28.0->7 is ei=di=ci=1,bi=ai=0
// K23 is 10111
// K27 is 11011
// K29 is 11101
// K30 is 11110 - so K23/27/29/30 are ei & l31
wire illegalk = ki &
(ai | bi | !ci | !di | !ei) & // not K28.0->7
(!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7
// now determine whether to do the complementing
// complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set
wire compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin) ;
// disparity out of 5b6b is disp in with pdso6 and ndso6
// pds16 indicates cases where d-1 is assumed + to get our encoded value
// ndos6 is cases where d-1 is + yields - disp out
// nds16 indicates cases where d-1 is assumed - to get our encoded value
// pdos6 is cases where d-1 is - yields + disp out
// disp toggles in all ndis16 cases, and all but that 1 nds16 case
wire disp6 = dispin ^ (ndos6 | pdos6) ;
wire compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6) ;
assign dispout = disp6 ^ (ndos4 | pdos4) ;
assign dataout = {(jo ^ compls4), (ho ^ compls4),
(go ^ compls4), (fo ^ compls4),
(io ^ compls6), (eo ^ compls6),
(do ^ compls6), (co ^ compls6),
(bo ^ compls6), (ao ^ compls6)} ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBN_1_V
`define SKY130_FD_SC_HD__DLRBN_1_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrbn_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrbn_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBN_1_V
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-8; const int mxn = 100033; const int mod = 1e9 + 7; inline int read() { int x = 0, f = 1; char c = getchar(); while (!isdigit(c)) f = c == - ? -1 : 1, c = getchar(); while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); return x * f; } inline long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long ksm(long long a, long long b, long long mod) { long long ans = 1; while (b) { if (b & 1) ans = (ans * a) % mod; a = (a * a) % mod; b >>= 1; } return ans; } long long inv2(long long a, long long mod) { return ksm(a, mod - 2, mod); } void exgcd(long long a, long long b, long long &x, long long &y, long long &d) { if (!b) { d = a; x = 1; y = 0; } else { exgcd(b, a % b, y, x, d); y -= x * (a / b); } } int dx[] = {0, 1, 0, -1}; int dy[] = {1, 0, -1, 0}; int n, a[1010]; map<int, int> ct; int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); std::cout.tie(0); ; int t; cin >> t; while (t--) { cin >> n; int flg = 0; ct.clear(); for (int i = 1; i <= n; ++i) { cin >> a[i]; ct[a[i]]++; if (ct[a[i]] >= 2) flg = 1; } if (flg) cout << YES << endl; else cout << NO << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:25:35 10/11/2015
// Design Name:
// Module Name: UART_tx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_tx (
input clock, // clock de la placa a 50MHz
input reset,
input s_tick, // del baud rate generator a 9600bps
input tx_start, // flag de comienzo de envío (LÓGICA NEGATIVA)
input [7:0] data_in, // buffer de entrada de datos paralelo
output reg tx, // salida serie de datos
output reg tx_done // flag de finalización de envío
);
localparam [1:0] IDLE = 0,
START = 1,
SEND = 2,
STOP = 3;
localparam B_start=1'b0,
B_stop= 1'b1;
reg [1:0] current_state, next_state;
reg [2:0] B_sent;
reg [7:0] d_in; // buffer local
//algoritmo de cambio de estado
always @(posedge clock, posedge reset)
begin
if(reset) begin
current_state <= IDLE;
end
else
current_state <= next_state;
end
// algoritmo de próximo de estado
/* always @* begin
case(current_state)
IDLE: next_state <= tx_start? IDLE : START;
START: next_state <= SEND;
SEND: next_state <= (B_sent>=8)? STOP : SEND;
STOP: next_state <= IDLE;
endcase
end
*/
// contadores
always @(posedge clock) begin
case(current_state)
IDLE: begin
tx_done = 0;
tx= 1;
if(~tx_start) begin // tx_start actúa por nivel bajo
next_state = START;
end
else next_state = IDLE;
end
START: begin
d_in = data_in;
B_sent = 0;
if(s_tick) begin
tx = B_start;
next_state = SEND;
end
end
SEND: begin
if(s_tick) begin
tx = d_in[B_sent];
if(B_sent == 7) begin
next_state = STOP;
end
else begin
B_sent = B_sent + 3'b1;
end
end
end
STOP: begin
if(s_tick) begin
tx = B_stop;
tx_done = 1;
next_state=IDLE;
end
else if (tx_done==1) begin
tx_done=0;
end
end
endcase
end
/* //algoritmo de salida
always @* begin
tx_done<= 0;
tx <= B_stop;
case(current_state)
START: tx <= B_start;
SEND: tx <= d_in[B_sent];
STOP: tx_done <= 1;
endcase
end
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > vec; int grid1[2050], grid2[2050]; int main() { int n; cin >> n; int r = 0, c = 0; long long ans = 0; for (int i = 1; i <= n; i++) { int x, y; cin >> x >> y; ans += grid1[x + y]; grid1[x + y]++; ans += grid2[x - y + 1000]; grid2[x - y + 1000]++; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, x1, x2; struct server { int c, ind; bool b1, b2; int r1, r2; } * *srv; void qs(server** a, int l, int r) { int i = l, j = r; int p = a[(l + r) >> 1]->c; do { while (i < r && a[i]->c < p) i++; while (j > l && a[j]->c > p) j--; if (i <= j) swap(a[i++], a[j--]); } while (i <= j); if (i < r) qs(a, i, r); if (j > l) qs(a, l, j); } int main() { scanf( %d %d %d , &n, &x1, &x2); srv = new server*[n]; for (int i = 0; i < n; i++) { srv[i] = new server; scanf( %d , &srv[i]->c); srv[i]->ind = i; } qs(srv, 0, n - 1); for (int i = n - 1; i >= 0; i--) { srv[i]->r1 = ((long long)x1 + (long long)srv[i]->c - (long long)1) / (long long)srv[i]->c; srv[i]->r2 = ((long long)x2 + (long long)srv[i]->c - (long long)1) / (long long)srv[i]->c; if (i < n - 1 && srv[i + 1]->b1) srv[i]->b1 = 1; else if (srv[i]->r1 <= n - i) srv[i]->b1 = 1; else srv[i]->b1 = 0; if (i < n - 1 && srv[i + 1]->b2) srv[i]->b2 = 1; else if (srv[i]->r2 <= n - i) srv[i]->b2 = 1; else srv[i]->b2 = 0; } for (int i = 0; i < n - 1; i++) { if (srv[i]->r1 < n - i && srv[i + srv[i]->r1]->b2) { for (int j = i + srv[i]->r1; j < n; j++) { if (srv[j]->r2 <= n - j) { printf( Yes n ); printf( %d %d n , srv[i]->r1, srv[j]->r2); for (int k = 0; k < srv[i]->r1; k++) printf( %d , srv[i + k]->ind + 1); printf( n ); for (int k = 0; k < srv[j]->r2; k++) printf( %d , srv[j + k]->ind + 1); printf( n ); return 0; } } } } for (int i = 0; i < n - 1; i++) { if (srv[i]->r2 < n - i && srv[i + srv[i]->r2]->b1) { for (int j = i + srv[i]->r2; j < n; j++) { if (srv[j]->r1 <= n - j) { printf( Yes n ); printf( %d %d n , srv[j]->r1, srv[i]->r2); for (int k = 0; k < srv[j]->r1; k++) printf( %d , srv[j + k]->ind + 1); printf( n ); for (int k = 0; k < srv[i]->r2; k++) printf( %d , srv[i + k]->ind + 1); printf( n ); return 0; } } } } printf( No n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class T> ostream& operator<<(ostream& os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; return os << ] ; } template <class T> ostream& operator<<(ostream& os, set<T> second) { os << { ; for (auto s : second) os << s << ; return os << } ; } template <class T> ostream& operator<<(ostream& os, multiset<T> second) { os << { ; for (auto s : second) os << s << ; return os << } ; } template <class L, class R> ostream& operator<<(ostream& os, map<L, R> M) { os << { ; for (auto m : M) os << ( << m.first << : << m.second << ) ; return os << } ; } template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } void solve() { int n; cin >> n; vector<long long> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; if (i) a[i] += a[i - 1]; } long long sm = a[n - 1]; if (sm == 1) { cout << -1 n ; return; } vector<long long> divs; for (long long d = 2; d * d <= sm; ++d) { if (sm % d) continue; divs.push_back(d); while (sm % d == 0) { sm /= d; } } if (sm != 1) divs.push_back(sm); long long ans = LLONG_MAX; for (long long d : divs) { long long ta = 0; for (int i = 0; i < n - 1; ++i) { ta += min(a[i] % d, d - a[i] % d); } ans = min(ans, ta); } cout << ans << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int T = 1, tc = 1; while (T--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } int main() { long long a[300005], p[300005]; long long n, m; cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) cin >> p[i]; long long g = 0; for (int i = 1; i < n; i++) { g = gcd(g, a[i] - a[i - 1]); } for (int i = 0; i < m; i++) { if (g % p[i] == 0) { cout << YES << endl; cout << a[0] << << i + 1 << endl; return 0; } } cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 55; int n, siz[N]; vector<int> e[N]; double f[N][N], sav[N], C[N][N], fac[N]; void dfs(int x, int fa) { siz[x] = 0, f[x][0] = 1; for (const int &v : e[x]) if (v != fa) { dfs(v, x), ++siz[v]; double sum = 0, o; for (int a = (0); a <= (siz[v]); a++) o = f[v][a], f[v][a] = f[v][a] * (siz[v] - a) + sum / 2, sum += o; for (int a = (0); a <= (siz[x]); a++) for (int b = (0); b <= (siz[v]); b++) sav[a + b] += C[a + b][a] * C[(siz[x] - a) + (siz[v] - b)][siz[x] - a] * f[x][a] * f[v][b]; siz[x] += siz[v]; for (int a = (0); a <= (siz[x]); a++) f[x][a] = sav[a], sav[a] = 0; } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.precision(12), cout << fixed; cin >> n; fac[0] = C[0][0] = 1; for (int i = (1); i <= (n); i++) fac[i] = fac[i - 1] * i, C[i][0] = 1; for (int i = (1); i <= (n); i++) for (int j = (1); j <= (i); j++) C[i][j] = C[i - 1][j] + C[i - 1][j - 1]; for (int i = 1, u, v; i < n; i++) cin >> u >> v, e[u].push_back(v), e[v].push_back(u); for (int i = (1); i <= (n); i++) memset(f, 0, sizeof(f)), dfs(i, -1), cout << f[i][n - 1] / fac[n - 1] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long n; cin >> n; string s = ROYGBIV ; long long x = n - 7; string st = GBIV ; long long i = 0; while (i < x) { s += st[(i % 4)]; i++; } cout << s << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int INF = 1000 * 1000 * 1000 + 7; const long long LINF = INF * (long long)INF; const int MAX = 2 * 1000 * 100 + 47; struct Item { int a, t, ind; bool operator<(const Item& a) const { return t < a.t; } }; Item A[MAX]; int n, t; bool ok(int k) { long long time = 0; int cnt = 0; for (int i = (0); i < (n); i++) { int a = A[i].a; int tt = A[i].t; if (a >= k && time + tt <= t) { cnt++; time += tt; } } return cnt >= k; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> t; for (int i = (0); i < (n); i++) { cin >> A[i].a >> A[i].t; A[i].ind = i; } sort(A, A + n); int l = 0, r = n + 1; while (r - l > 1) { int c = (r + l) / 2; if (ok(c)) { l = c; } else { r = c; } } int cnt = l; cout << cnt << n << cnt << n ; for (int i = (0); i < (n); i++) { if (cnt == 0) break; if (A[i].a >= l) { cnt--; cout << A[i].ind + 1 << ; } } }
|
#include <bits/stdc++.h> using namespace std; int bef[100050]; int main() { string s, s1; cin >> s; int len = s.size(); int last_a = -1; int now = 0; for (int i = 0; i < len; i++) { if (s[i] != a ) { s1 += s[i]; bef[now] = i; now++; } else { last_a = i; } } if (now % 2 == 1) cout << :( << endl; else { for (int i = 0; i < now / 2; i++) { if (s1[i] != s1[i + now / 2]) { cout << :( << endl; return 0; } } if (last_a == -1 || bef[now / 2] > last_a || now == 0) { for (int i = 0; i < (now != 0 ? bef[now / 2] : len); i++) { cout << s[i]; } cout << endl; } else { cout << :( << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<long long, long long> a[300001]; long long n, k, s, m; bool b[300001]; inline long long read() { long long sum = 0, x = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) x = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { sum = sum * 10 + ch - 0 ; ch = getchar(); } return sum * x; } inline void write(long long x) { if (x < 0) { putchar( - ); x = -x; } if (x > 9) write(x / 10); putchar(x % 10 + 0 ); return; } inline bool cmp(pair<long long, long long> a, pair<long long, long long> b) { return a.first > b.first; } signed main() { n = read(); k = read(); for (register long long i = 1; i <= n; ++i) a[i].second = i; for (m = 1; m <= n; ++m) { for (register long long j = m * 2; j <= n; j += m) ++a[j].first; s += a[m].first; if (s >= k) break; } if (s < k) { puts( No ); return 0; } sort(a + 1, a + m, cmp); long long t = m; for (register long long i = 1; i <= m; ++i) { if (a[i].second > m / 2 && s - a[i].first >= k) { s -= a[i].first; b[a[i].second] = true; t--; } if (s == k) break; } puts( Yes ); write(t); putchar( n ); for (register long long i = 1; i <= m; ++i) if (!b[i]) { write(i); putchar( ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; for (int test = 0; test < q; test++) { int a, b, c, d, k; cin >> a >> b >> c >> d >> k; int pen = (a - 1) / c + 1, pencil = (b - 1) / d + 1; if (pen + pencil > k) { cout << -1 << n ; } else { cout << pen << << pencil << n ; } } }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 2010; int n, m; long long f[N][N], g[N][N], h[N][N], o[N][N], p[N][N], ans; int main() { cin >> n >> m; memset(f, 0, sizeof(f)); memset(g, 0, sizeof(g)); memset(h, 0, sizeof(h)); memset(o, 0, sizeof(o)); for (int i = 1; i <= n; ++i) { for (int j = 2; j <= m; ++j) { (f[i][j] += 1 + g[i - 1][j] * j % mod + h[i - 1][j]) %= mod; o[i][j] = (f[i][j] - f[i - 1][j]) % mod; } for (int j = 2; j <= m; ++j) { g[i][j] = (g[i][j - 1] + f[i][j]) % mod; h[i][j] = (h[i][j - 1] + f[i][j] * (1 - j) % mod) % mod; } } memset(p, 0, sizeof(p)); for (int i = 1; i <= n; ++i) for (int j = 2; j <= m; ++j) p[i][j] = (p[i - 1][j] + o[i][j]) % mod; ans = 0; for (int i = 1; i <= n; ++i) for (int j = 2; j <= m; ++j) { (ans += (m - j + 1) * o[i][j] % mod * p[n - i + 1][j] % mod) %= mod; } cout << (ans + mod) % mod << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,unroll-loops ) #pragma GCC target( avx,avx2,fma ) using namespace std; template <typename T> using vc = vector<T>; template <typename T> using uset = unordered_set<T>; template <typename A, typename B> using umap = unordered_map<A, B>; template <typename T> using pq = priority_queue<T>; template <typename T> using minpq = priority_queue<T, vc<T>, greater<T>>; template <typename T> inline void sort(vc<T>& v) { sort(v.begin(), v.end()); } template <typename T, typename Comp> inline void sort(vc<T>& v, Comp c) { sort(v.begin(), v.end(), c); } using ll = long long; using ull = unsigned long long; using pii = pair<ll, ll>; using vi = vc<ll>; using vii = vc<pii>; constexpr char el = n ; constexpr char sp = ; constexpr ll INF = 0x3f3f3f3f; constexpr ll LLINF = 0x3f3f3f3f3f3f3f3fLL; ll xh, yh, xs, ys, n; inline bool evan(ll a, ll b) { return a < 0 && b > 0 || a > 0 && b < 0; } signed main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout << fixed; cin >> xh >> yh; cin >> xs >> ys; cin >> n; ll ans = 0; while (n--) { ll a, b, c; cin >> a >> b >> c; if (evan(a * xh + b * yh + c, a * xs + b * ys + c)) ans++; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int N = 50 + 5; int n, dp[N][N][N][N]; char g[N][N]; int dfs(int x, int y, int h, int w) { if (dp[x][y][h][w] != -1) return dp[x][y][h][w]; if (h == 1 && w == 1) return dp[x][y][h][w] = g[x][y] == # ; if (h == 0 || w == 0) return dp[x][y][h][w] = 0; dp[x][y][h][w] = max(h, w); for (int i = 0; i <= h; ++i) { dp[x][y][h][w] = min(dp[x][y][h][w], dfs(x, y, i, w) + dfs(x + i, y, h - i, w)); } for (int j = 0; j <= w; ++j) { dp[x][y][h][w] = min(dp[x][y][h][w], dfs(x, y, h, j) + dfs(x, y + j, h, w - j)); } return dp[x][y][h][w]; } int main() { memset(dp, -1, sizeof(dp)); cin >> n; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { cin >> g[i][j]; } } printf( %d , dfs(1, 1, n, n)); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n, k; cin >> n >> k; vector<int> *dist = new vector<int>[n]; int len = 0; for (int i = 0; i < n; i++) { int d; cin >> d; dist[d].push_back(i); len = max(len, d); } if (dist[0].size() != 1) { cout << -1; return 0; } for (int i = 1; i <= len; i++) { if (dist[i].empty() || dist[i].size() > (long long)dist[i - 1].size() * (k - (i != 1))) { cout << -1; return 0; } } cout << n - 1 << endl; for (int i = 1; i <= len; i++) { int counter = 0; int index = 0; for (int child : dist[i]) { if (counter == k - (i != 1)) { counter = 0; index++; } cout << dist[i - 1][index] + 1 << << child + 1 << endl; counter++; } } return 0; }
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_gtwiz_userclk_rx #(
parameter integer P_CONTENTS = 0,
parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
)(
input wire gtwiz_userclk_rx_srcclk_in,
input wire gtwiz_userclk_rx_reset_in,
output wire gtwiz_userclk_rx_usrclk_out,
output wire gtwiz_userclk_rx_usrclk2_out,
output wire gtwiz_userclk_rx_active_out
);
// -------------------------------------------------------------------------------------------------------------------
// Local parameters
// -------------------------------------------------------------------------------------------------------------------
// Convert integer parameters with known, limited legal range to a 3-bit local parameter values
localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
// -------------------------------------------------------------------------------------------------------------------
// Receiver user clocking network conditional generation, based on parameter values in module instantiation
// -------------------------------------------------------------------------------------------------------------------
generate if (1) begin: gen_gtwiz_userclk_rx_main
// Use BUFG_GT instance(s) to drive RXUSRCLK and RXUSRCLK2, inferred for integral source to RXUSRCLK frequency ratio
if (P_CONTENTS == 0) begin
// Drive RXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to RXUSRCLK
// frequency ratio
BUFG_GT bufg_gt_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_rx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK_DIV),
.I (gtwiz_userclk_rx_srcclk_in),
.O (gtwiz_userclk_rx_usrclk_out)
);
// If RXUSRCLK and RXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
// RXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the RXUSRCLK2 frequency.
if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
assign gtwiz_userclk_rx_usrclk2_out = gtwiz_userclk_rx_usrclk_out;
else begin
BUFG_GT bufg_gt_usrclk2_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_rx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK2_DIV),
.I (gtwiz_userclk_rx_srcclk_in),
.O (gtwiz_userclk_rx_usrclk2_out)
);
end
// Indicate active helper block functionality when the BUFG_GT divider is not held in reset
(* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_meta = 1'b0;
(* ASYNC_REG = "TRUE" *) reg gtwiz_userclk_rx_active_sync = 1'b0;
always @(posedge gtwiz_userclk_rx_usrclk2_out, posedge gtwiz_userclk_rx_reset_in) begin
if (gtwiz_userclk_rx_reset_in) begin
gtwiz_userclk_rx_active_meta <= 1'b0;
gtwiz_userclk_rx_active_sync <= 1'b0;
end
else begin
gtwiz_userclk_rx_active_meta <= 1'b1;
gtwiz_userclk_rx_active_sync <= gtwiz_userclk_rx_active_meta;
end
end
assign gtwiz_userclk_rx_active_out = gtwiz_userclk_rx_active_sync;
end
end
endgenerate
endmodule
|
`default_nettype none
module multiple_blocking_gate (clk, ctrl, din, sel, dout);
input wire clk;
input wire [4:0] ctrl;
input wire [1:0] din;
input wire [0:0] sel;
output reg [31:0] dout;
reg [5:0] a;
reg [0:0] b;
reg [2:0] c;
always @(posedge clk)
begin
a = (ctrl)+(1);
b = (sel)-(1);
c = ~(din);
dout = (dout)+(1);
case (({(a)*(b)})+(0))
0:
dout[31:0] = c;
1:
dout[31:1] = c;
2:
dout[31:2] = c;
3:
dout[31:3] = c;
4:
dout[31:4] = c;
5:
dout[31:5] = c;
6:
dout[31:6] = c;
7:
dout[31:7] = c;
8:
dout[31:8] = c;
9:
dout[31:9] = c;
10:
dout[31:10] = c;
11:
dout[31:11] = c;
12:
dout[31:12] = c;
13:
dout[31:13] = c;
14:
dout[31:14] = c;
15:
dout[31:15] = c;
16:
dout[31:16] = c;
17:
dout[31:17] = c;
18:
dout[31:18] = c;
19:
dout[31:19] = c;
20:
dout[31:20] = c;
21:
dout[31:21] = c;
22:
dout[31:22] = c;
23:
dout[31:23] = c;
24:
dout[31:24] = c;
25:
dout[31:25] = c;
26:
dout[31:26] = c;
27:
dout[31:27] = c;
28:
dout[31:28] = c;
29:
dout[31:29] = c;
30:
dout[31:30] = c;
31:
dout[31:31] = c;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int ar[500009], br[500009]; int main() { long long int a, b, c, i, j = 0, k = 9999999999999; string s; cin >> a; getchar(); cin >> s; for (i = 0; i < a; i++) { cin >> ar[i]; } for (i = 0; i < a - 1; i++) { if (s[i] == R && s[i + 1] == L ) { k = min(k, (ar[i + 1] - ar[i])); } } if (k == 9999999999999) { cout << -1 ; } else cout << (k / 2) << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_8_V
`define SKY130_FD_SC_HDLL__A21O_8_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_8 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_8 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_8_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int x; cin >> x; vector<int> first(x); vector<int> second(x); int sum_f = 0; for (int i = 0; i < x; i++) { cin >> first[i]; sum_f += first[i]; } int sum_s = 0; for (int i = 0; i < x; i++) { cin >> second[i]; sum_s += second[i]; } if (sum_s > sum_f) { cout << No ; } else cout << Yes ; return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: spu_mald.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: state machine for load requests to L2.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
module spu_mald (
/*outputs*/
spu_mald_rstln,
spu_mald_maaddr_addrinc,
spu_mald_memwen,
spu_mald_mpa_addrinc,
spu_mald_ldreq,
spu_mald_done,
spu_mald_force_mpa_add16,
spu_mald_done_set,
/*inputs*/
ld_inprog,
ldreq_ack,
ln_received,
len_neqz,
mactl_ldop,
spu_maaddr_mpa1maddr0,
spu_mactl_iss_pulse_dly,
spu_wen_ma_unc_err_pulse,
spu_mactl_stxa_force_abort,
se,
reset,
rclk);
// ---------------------------------------------------------
input reset;
input rclk;
input se;
input ld_inprog;
input ldreq_ack;
input ln_received;
input len_neqz;
input mactl_ldop;
input spu_maaddr_mpa1maddr0;
input spu_mactl_iss_pulse_dly;
input spu_wen_ma_unc_err_pulse;
input spu_mactl_stxa_force_abort;
// ---------------------------------------------------------
output spu_mald_rstln;
output spu_mald_maaddr_addrinc;
output spu_mald_memwen;
output spu_mald_mpa_addrinc;
output spu_mald_ldreq;
output spu_mald_done;
output spu_mald_force_mpa_add16;
output spu_mald_done_set;
// ---------------------------------------------------------
wire tr2wait4ln_frm_ldreq;
// ---------------------------------------------------------
/*******************************
there are 8 states:
000001 idle
000010 ld1_req
000100 ld2_req
001000 wait_4ln1
010000 wait_4ln2
100000 mamem_wr
********************************/
wire local_stxa_abort;
// ------------------------------------------------------
// we need a state set to indcate ld is done, and when an
// masync gets issued later, then the load asi is returned.
wire spu_mald_done_wen = (spu_mald_done | spu_wen_ma_unc_err_pulse | local_stxa_abort) &
mactl_ldop;
wire spu_mald_done_rst = reset | spu_mactl_iss_pulse_dly;
dffre_s #(1) spu_mald_done_ff (
.din(1'b1) ,
.q(spu_mald_done_set),
.en(spu_mald_done_wen),
.rst(spu_mald_done_rst), .clk (rclk), .se(se), .si(), .so());
// ------------------------------------------------------
// ------------------------------------------------------
// ------------------------------------------------------
// ------------------------------------------------------
// ------------------------------------------------------
wire state_reset = reset | spu_mald_done | spu_wen_ma_unc_err_pulse |
local_stxa_abort;
// ------------------------------------------------------
dff_s #(1) idle_state_ff (
.din(nxt_idle_state) ,
.q(cur_idle_state),
.clk (rclk), .se(se), .si(), .so());
dffr_s #(1) ldreq_state_ff (
.din(nxt_ldreq_state) ,
.q(cur_ldreq_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) wait4ln_state_ff (
.din(nxt_wait4ln_state) ,
.q(cur_wait4ln_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) mamemwr_state_ff (
.din(nxt_mamemwr_state) ,
.q(cur_mamemwr_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
dffr_s #(1) chk4mpa1maddr0_state_ff (
.din(nxt_chk4mpa1maddr0_state) ,
.q(cur_chk4mpa1maddr0_state),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
// ------------------------------------------------------
// ------------------------------------------------------
wire start_ldop = spu_mactl_iss_pulse_dly & mactl_ldop;
// --------------------------------------------------------------
// transition to idle state.
assign spu_mald_done = cur_chk4mpa1maddr0_state & ~len_neqz;
assign nxt_idle_state = (
state_reset |
(spu_mald_done) |
(cur_idle_state & ~start_ldop));
// --------------------------------------------------------------
// transition to ldreq state.
assign nxt_ldreq_state = (
(cur_chk4mpa1maddr0_state & ~spu_maaddr_mpa1maddr0 & len_neqz) |
(cur_idle_state & start_ldop) |
(cur_ldreq_state & ~ldreq_ack));
assign spu_mald_rstln = (cur_mamemwr_state & ld_inprog & len_neqz) | local_stxa_abort |
spu_wen_ma_unc_err_pulse;
// --------------------------------------------------------------
// transition to wait4ln state.
//assign tr2wait4ln_frm_ldreq = cur_ldreq_state & ldreq_ack & ln_received;
assign tr2wait4ln_frm_ldreq = cur_ldreq_state & ldreq_ack ;
assign nxt_wait4ln_state = (
(tr2wait4ln_frm_ldreq) |
(cur_wait4ln_state & ~ln_received));
// --------------------------------------------------------------
// transition to mamemwr state.
wire tr2mamemwr_frm_wait4ln = cur_wait4ln_state & ln_received;
wire tr2mamemwr_frm_chk4mpa1maddr0 = cur_chk4mpa1maddr0_state & spu_maaddr_mpa1maddr0 & len_neqz;
wire mald_memwen = ( tr2mamemwr_frm_wait4ln |
tr2mamemwr_frm_chk4mpa1maddr0) & len_neqz;
// added this delay for the Parity Gen. added extra cycle.
wire mald_memwen_dly;
dffr_s #(1) wen_dly_ff (
.din(mald_memwen) ,
.q(mald_memwen_dly),
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
assign nxt_mamemwr_state = ( mald_memwen_dly );
assign local_stxa_abort = mald_memwen_dly & spu_mactl_stxa_force_abort;
// --------------------------------------------------------------
// transition to chk4mpa1maddr0 state.
assign nxt_chk4mpa1maddr0_state = (
(cur_mamemwr_state) );
// --------------------------------------------------------------
// **************************************************************
// --------------------------------------------------------------
assign spu_mald_memwen = nxt_mamemwr_state;
assign spu_mald_maaddr_addrinc = cur_mamemwr_state;
assign spu_mald_mpa_addrinc = cur_mamemwr_state ;
assign spu_mald_force_mpa_add16 = 1'b0 ;
assign spu_mald_ldreq = cur_ldreq_state ;
endmodule
|
#include <bits/stdc++.h> using namespace std; typedef long double LD; typedef long long ll; #define int ll #define ff(i,a,b) for (int i = a; i < b; i++) #define bf(i,a,b) for (int i = a; i >= b; i--) #define all(v) v.begin(),v.end() #define show(a) for(auto xyz:a)cout<<xyz<< ;cout<<endl; #define F first #define S second #define pb push_back #define mp make_pair #define lb lower_bound #define ub upper_bound #define yes cout<< YES <<endl #define no cout<< NO <<endl #define one cout<< -1 <<endl #define pi 3.141592653589793238 #define err() cout<< ================================== <<endl; #define errA(A) for(auto i:A) cout<<i<< ;cout<<endl; #define err1(a) cout<<#a<< <<a<<endl #define err2(a,b) cout<<#a<< <<a<< <<#b<< <<b<<endl #define err3(a,b,c) cout<<#a<< <<a<< <<#b<< <<b<< <<#c<< <<c<<endl #define err4(a,b,c,d) cout<<#a<< <<a<< <<#b<< <<b<< <<#c<< <<c<< <<#d<< <<d<<endl #define intmx INT_MAX #define intmi INT_MIN const int MOD=1e9+7; void solve(){ int n,l,r; cin>>n>>l>>r; map<int,int> left,right; ff(i,0,n){ int x; cin>>x; if(i<=l-1) left[x]++; else right[x]++; } for(auto &i:left){ int x=min(i.S,right[i.F]); i.S-=x; right[i.F]-=x; //cout<<i.F<< <<i.S<<endl; } int cntl=0,cntr=0; for(auto i:left) cntl+=i.S; for(auto i:right) cntr+=i.S; int ans=0; if(cntl<=cntr){ ans+=cntl; int d=(cntr-cntl)/2; int cnt=0; for(auto i:right){ cnt+=i.S/2; } if(cnt<d){ ans+=cnt; ans+=2*(d-cnt); } else ans+=d; } else{ ans+=cntr; int d=(cntl-cntr)/2; int cnt=0; for(auto i:left){ cnt+=i.S/2; } if(cnt<d){ ans+=cnt; ans+=2*(d-cnt); } else ans+=d; } cout<<ans<<endl; } signed main() { int t=1; ios_base::sync_with_stdio(false); cin.tie(NULL); cin>>t; while(t--){ solve(); } }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int a[1005][1005]; int main() { int h, w; cin >> h >> w; vector<int> r(h), c(w); for (int i = 0; i < h; i++) { cin >> r[i]; } for (int i = 0; i < w; i++) { cin >> c[i]; } memset(a, -1, sizeof(a)); for (int i = 0; i < h; i++) { for (int j = 0; j < r[i]; j++) { a[i][j] = 1; } a[i][r[i]] = 0; } for (int i = 0; i < w; i++) { for (int j = 0; j < c[i]; j++) { if (a[j][i] == 0) { cout << 0 << endl; return 0; } a[j][i] = 1; } if (a[c[i]][i] == 1) { cout << 0 << endl; return 0; } a[c[i]][i] = 0; } int ans = 1; for (int i = 0; i < h; i++) { for (int j = 0; j < w; j++) { if (a[i][j] == -1) { ans = (1ll * 2 * ans) % mod; } } } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DFRTP_PP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; list<pair<int, long long> > l; long long get(int x) { long long ans = 0; for (list<pair<int, long long> >::iterator it = l.begin(), e = l.end(); it != e; ++it) { ans = max(ans, it->second); if (x <= it->first) { break; } x -= it->first; } return ans; } void update(int ox, long long v) { int x = ox; list<pair<int, long long> >::iterator now = l.begin(), e = l.end(); for (; now != e; ++now) { if (x < now->first) { break; } x -= now->first; } while (l.begin() != now) { l.pop_front(); } l.begin()->first = l.begin()->first - x; l.push_front(make_pair(ox, v)); } int main() { int n, m; cin >> n; l.clear(); for (int i = 1; i <= n; i++) { long long t; cin >> t; l.push_back(make_pair(1, t)); } cin >> m; for (int i = 0; i < m; i++) { int w; long long h; cin >> w >> h; long long ans = get(w); cout << ans << n ; update(w, ans + h); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__MUX2_PP_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, g; cin >> n >> g; g %= 4 * n; long long xx, yy; cin >> xx >> yy; long long x[n], y[n]; for (int(i) = int(0); i < int(n); ++i) cin >> x[i] >> y[i]; for (int(i) = int(1); i < int(g + 1); ++i) { long long dx = xx - x[(i - 1) % n]; long long dy = yy - y[(i - 1) % n]; xx -= 2 * dx; yy -= 2 * dy; } cout << xx << << yy << endl; }
|
`timescale 1ns/1ps
module test();
reg clock, reset;
sopc sopc(
.clock(clock),
.reset(reset)
);
always #1 clock = ~clock;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
$dumpvars(0, sopc.cpu.register.storage[1]);
$dumpvars(0, sopc.cpu.register.storage[2]);
$dumpvars(0, sopc.cpu.register.storage[3]);
$dumpvars(0, sopc.cpu.register.storage[4]);
$readmemh("rom.txt", sopc.rom.storage);
clock = 1'b0;
reset = 1'b1;
#20 reset = 1'b0;
#10 `AR(1, 32'h01010000); `AR(2, 32'hxxxxxxxx); `AR(3, 32'hxxxxxxxx); `AR(4, 32'hxxxxxxxx);
#2 `AR(1, 32'h01010101); `AR(2, 32'hxxxxxxxx); `AR(3, 32'hxxxxxxxx); `AR(4, 32'hxxxxxxxx);
#2 `AR(1, 32'h01010101); `AR(2, 32'h01011101); `AR(3, 32'hxxxxxxxx); `AR(4, 32'hxxxxxxxx);
#2 `AR(1, 32'h01011101); `AR(2, 32'h01011101); `AR(3, 32'hxxxxxxxx); `AR(4, 32'hxxxxxxxx);
#2 `AR(1, 32'h01011101); `AR(2, 32'h01011101); `AR(3, 32'h00000000); `AR(4, 32'hxxxxxxxx);
#2 `AR(1, 32'h00000000); `AR(2, 32'h01011101); `AR(3, 32'h00000000); `AR(4, 32'hxxxxxxxx);
#2 `AR(1, 32'h00000000); `AR(2, 32'h01011101); `AR(3, 32'h00000000); `AR(4, 32'h0000FF00);
#2 `AR(1, 32'h0000FF00); `AR(2, 32'h01011101); `AR(3, 32'h00000000); `AR(4, 32'h0000FF00);
#2 `AR(1, 32'hFFFF00FF); `AR(2, 32'h01011101); `AR(3, 32'h00000000); `AR(4, 32'h0000FF00);
`PASS;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221AI_1_V
`define SKY130_FD_SC_LS__O221AI_1_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221ai_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221AI_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); long long n, m, l; cin >> n >> m >> l; vector<long long> a(n); vector<pair<long long, long long>> lr(n); long long ans = 0, old = -1000; long long flag = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; if (a[i] > l) { if (flag == 0) ans++; flag = 1; } if (a[i] <= l && flag == 1) { flag = 0; } } while (m--) { long long tp; cin >> tp; if (tp == 0) { cout << ans << endl; } else { long long p, d; cin >> p >> d; if (n > 1) { if (a[p - 1] <= l && a[p - 1] + d > l) { if (p - 1 > 0 && p - 1 < n - 1) { if (a[p - 2] > l && a[p] > l) ans--; else if (a[p - 2] <= l && a[p] > l) ans += 0; else if (a[p - 2] > l && a[p] <= l) ans += 0; else ans++; } else if (p - 1 == 0) { if (a[p] > l) ans += 0; else if (a[p] <= l) ans++; } else { if (a[p - 2] > l) ans += 0; else if (a[p - 2] <= l) ans++; } } } else { if (a[p - 1] <= l && a[p - 1] + d > l) ans++; } a[p - 1] += d; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a, b; int ans, nn; char x[100010]; int change(int t) { int rtn = 0, bit = 1; while (t) { rtn += (t % 10) * bit; bit *= ans; t /= 10; } return rtn; } int main() { scanf( %d%d , &a, &b); int aa = a, bb = b; while (aa) { ans = max(ans, aa % 10); aa /= 10; } while (bb) { ans = max(ans, bb % 10); bb /= 10; } ans += 1; a = change(a); b = change(b); a += b; while (a) { x[nn++] = a % ans + 0 ; a /= ans; } printf( %d , nn); return 0; }
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : ram_1p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Single Port Ram Model
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module db_ram_1p (
clk ,
cen_i ,
oen_i ,
wen_i ,
addr_i ,
data_i ,
data_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width = 128;
parameter Addr_Width = 8 ;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk ; // clock input
input cen_i; // chip enable, low active
input oen_i; // data output enable, low active
input wen_i; // write enable, low active
input [Addr_Width-1:0] addr_i; // address input
input [Word_Width-1:0] data_i; // data input
output [Word_Width-1:0] data_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] data_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// mem write
always @(posedge clk) begin
if(!cen_i && !wen_i)
mem_array[addr_i] <= data_i;
end
// mem read
always @(posedge clk) begin
if (!cen_i && wen_i)
data_r <= mem_array[addr_i];
else
data_r <= 'bx;
end
assign data_o = oen_i ? 'bz : data_r;
endmodule
|
//deps: fifo.v
`timescale 1ns/1ps
module fifo_tb;
parameter FIFO_WIDTH = 8;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire empty; // From fifo of fifo.v
wire full; // From fifo of fifo.v
wire [FIFO_WIDTH-1:0] output_data; // From fifo of fifo.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg clk; // To fifo of fifo.v
reg [FIFO_WIDTH-1:0] input_data; // To fifo of fifo.v
reg rd; // To fifo of fifo.v
reg rst; // To fifo of fifo.v
reg wr; // To fifo of fifo.v
// End of automatics
fifo fifo(/*AUTOINST*/
// Outputs
.output_data (output_data[FIFO_WIDTH-1:0]),
.empty (empty),
.full (full),
// Inputs
.clk (clk),
.rst (rst),
.rd (rd),
.wr (wr),
.input_data (input_data[FIFO_WIDTH-1:0]));
initial begin
clk = 0;
input_data = 0;
rd = 0;
rst = 1;
wr = 0;
$dumpfile("dump.vcd");
$dumpvars;
end
always #5 clk <= ~clk;
initial begin
#10 rst <= 0;
input_data <= 8'h67;
wr <= 1;
#10 wr <= 0;
#10 input_data <= 8'h4d;
wr <= 1;
#10 input_data <= 8'hef;
#10 input_data <= 8'h01;
#10 input_data <= 8'h02;
#10 input_data <= 8'h03;
#10 input_data <= 8'h04;
#10 input_data <= 8'h05;
#10 wr <= 0;
rd <= 1;
#80 rd <= 0;
#30 $finish;
end
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
// calculates d=a/b
// a = b*d + r
module jt10_adpcm_div #(parameter dw=16)(
input rst_n,
input clk, // CPU clock
input cen,
input start, // strobe
input [dw-1:0] a,
input [dw-1:0] b,
output reg [dw-1:0] d,
output reg [dw-1:0] r,
output working
);
reg [dw-1:0] cycle;
assign working = cycle[0];
wire [dw:0] sub = { r[dw-2:0], d[dw-1] } - b;
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
cycle <= 'd0;
end else if(cen) begin
if( start ) begin
cycle <= ~16'd0;
r <= 16'd0;
d <= a;
end else if(cycle[0]) begin
cycle <= { 1'b0, cycle[dw-1:1] };
if( sub[dw] == 0 ) begin
r <= sub[dw-1:0];
d <= { d[dw-2:0], 1'b1};
end else begin
r <= { r[dw-2:0], d[dw-1] };
d <= { d[dw-2:0], 1'b0 };
end
end
end
endmodule // jt10_adpcm_div
|
#include <bits/stdc++.h> using namespace std; int question, r, speed, st, en, len, did; double lft, rht, middle, dist, p; inline double euclid_dist(double a, double b) { return sqrt(a * a + b * b); } inline bool check(double dis) { p = 1.0 * dis / r; return r * euclid_dist(1 - cos(p), sin(p)) >= len - dis; } int main() { scanf( %d%d%d , &question, &r, &speed); for (register int i = 1; i <= question; i++) { scanf( %d%d , &st, &en); len = en - st; lft = 0; rht = len; did = 0; while (lft < rht && did <= 50) { middle = (lft + rht) / 2.0; switch (check(middle)) { case true: dist = middle; rht = middle; break; case false: lft = middle; break; } did++; } dist /= speed; printf( %0.12lf n , dist); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000009; vector<long long> vec; long long powmod(long long a, long long m) { long long ret = 1 % MOD; for (; m; m >>= 1) { if (m & 1) { ret *= a; if (ret >= MOD) ret %= MOD; } a *= a; if (a >= MOD) a %= MOD; } return ret; } int main() { long long n, m, k; vec.clear(); cin >> n >> m >> k; m = n - m; if (m >= n) { cout << 0 << endl; return 0; } long long p = (long long)(n / k); if (m >= p) { cout << n - m << endl; return 0; } long long pos = n - m * k; long long div = pos / k; long long mod = pos % k; long long mul = (powmod(2, div) - 1) * k % MOD * 2 % MOD; mul = (mul + MOD) % MOD; mul = (mul + mod) % MOD; long long ans = (mul + n - pos - m) % MOD; ans = (ans + MOD) % MOD; cout << ans << endl; return 0; }
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame length measurement
*/
module axis_frame_len #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 64,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Width of length counter
parameter LEN_WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI monitor
*/
input wire [KEEP_WIDTH-1:0] monitor_axis_tkeep,
input wire monitor_axis_tvalid,
input wire monitor_axis_tready,
input wire monitor_axis_tlast,
/*
* Status
*/
output wire [LEN_WIDTH-1:0] frame_len,
output wire frame_len_valid
);
reg [LEN_WIDTH-1:0] frame_len_reg = 0, frame_len_next;
reg frame_len_valid_reg = 1'b0, frame_len_valid_next;
reg frame_reg = 1'b0, frame_next;
assign frame_len = frame_len_reg;
assign frame_len_valid = frame_len_valid_reg;
integer offset, i, bit_cnt;
always @* begin
frame_len_next = frame_len_reg;
frame_len_valid_next = 1'b0;
frame_next = frame_reg;
if (monitor_axis_tready && monitor_axis_tvalid) begin
// valid transfer cycle
if (monitor_axis_tlast) begin
// end of frame
frame_len_valid_next = 1'b1;
frame_next = 1'b0;
end else if (!frame_reg) begin
// first word after end of frame
frame_len_next = 0;
frame_next = 1'b1;
end
// increment frame length by number of words transferred
if (KEEP_ENABLE) begin
bit_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i;
end
frame_len_next = frame_len_next + bit_cnt;
end else begin
frame_len_next = frame_len_next + 1;
end
end
end
always @(posedge clk) begin
if (rst) begin
frame_len_reg <= 0;
frame_len_valid_reg <= 0;
frame_reg <= 1'b0;
end else begin
frame_len_reg <= frame_len_next;
frame_len_valid_reg <= frame_len_valid_next;
frame_reg <= frame_next;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool vv[2000][2000]; int main() { int n; string s; cin >> s; long long left[2000], right[2000]; for (int i = 0; i < s.length(); i++) { vv[i][i] = true; } int sm = 1, cp = s.length() - 1; for (; sm < s.length(); sm++) { for (int i = sm, j = 0; i < s.length(); i++, j++) { if (s[j] == s[j + sm] && (sm == 1 || vv[j + 1][j + sm - 1])) { vv[j][j + sm] = true; } else { vv[j][j + sm] = false; } } } for (int i = 0; i < s.length(); i++) { left[i] = 1; right[i] = 1; for (int j = 0; j < i; j++) { if (vv[j][i]) left[i]++; if (vv[s.length() - (i + 1)][s.length() - (j + 1)]) right[i]++; } } long long res = 0, right_sum = 0; for (int i = 0; i < s.length() - 1; i++) right_sum += right[i]; for (int i = 0; i < s.length() - 1; i++) { res += left[i] * right_sum; right_sum -= right[s.length() - (i + 2)]; } cout << res << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_SYMBOL_V
`define SKY130_FD_SC_HS__NOR2B_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int dx[4] = {1, 0, -1, 0}; int dy[4] = {0, 1, 0, -1}; char E[1005][1005]; int N, M; struct Node { int step[3]; } s[1005][1005]; struct use { int x, y; }; void bfs(int x) { queue<use> que; use u, v; for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { if (E[i][j] == x + 1 ) { u.x = i, u.y = j; s[i][j].step[x] = 0; que.push(u); } } } while (!que.empty()) { u = que.front(); que.pop(); for (int i = 0; i < 4; i++) { v = u; v.x += dx[i]; v.y += dy[i]; if (v.x >= 0 && v.x < N && v.y >= 0 && v.y < M && E[v.x][v.y] != # ) { int t; if (E[v.x][v.y] == . ) t = 1; else t = 0; if (s[v.x][v.y].step[x] == -1 || s[u.x][u.y].step[x] + t < s[v.x][v.y].step[x]) { s[v.x][v.y].step[x] = s[u.x][u.y].step[x] + t; que.push(v); } } } } } int main() { scanf( %d %d , &N, &M); for (int i = 0; i < N; i++) scanf( %s , E[i]); memset(s, -1, sizeof(s)); for (int i = 0; i < 3; i++) bfs(i); int ans = 1 << 30; for (int i = 0; i < N; i++) for (int j = 0; j < M; j++) { if (s[i][j].step[0] != -1 && s[i][j].step[1] != -1 && s[i][j].step[2] != -1) { int t; if (E[i][j] == . ) t = 1; else t = 0; ans = min(ans, s[i][j].step[0] + s[i][j].step[1] + s[i][j].step[2] - t * 2); } } if (ans == 1 << 30) { puts( -1 ); exit(0); } printf( %d n , ans); return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Mon Oct 24 15:17:36 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.2 2005/10/24 15:50:24 wig Exp $
// $Date: 2005/10/24 15:50:24 $
// $Log: ent_ac.v,v $
// Revision 1.2 2005/10/24 15:50:24 wig
// added 'reg detection to ::out column
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.64 2005/10/20 17:28:26 lutscher Exp
//
// Generator: mix_0.pl Revision: 1.38 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No `defines in this module
module ent_ac
//
// Generated module inst_ac
//
(
port_ac_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
reg port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-27 19:57:00
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 3
`define STOP_SW2 4
module Simple_KOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output reg [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
mult #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
mult #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, q; int A[600006]; int gcd(int a, int b) { return !b ? a : gcd(b, a % b); } map<pair<int, int>, int> M; int L[600006], R[600006], lst[600006], cn; struct que { int l, r, idx; } Q[600006]; vector<int> bc[600006]; int T[600006]; void ad(int x, int c) { while (x <= cn) T[x] += c, x += (x & -x); } int sum(int x) { int ret = 0; while (x > 0) ret += T[x], x -= (x & -x); return ret; } int ans[600006]; void solve() { cin >> n; for (int i = (1), iend = (n); i <= iend; ++i) { int k; scanf( %d , &k); L[i] = cn + 1; int px, py, tx, ty, x, y, sx, sy; scanf( %d%d , &px, &py); sx = px, sy = py; for (int j = (1), jend = (k); j <= jend; ++j) { if (j != k) scanf( %d%d , &x, &y); else x = sx, y = sy; tx = x, ty = y; x -= px, y -= py; int g = gcd(abs(x), abs(y)); x /= g, y /= g; ++cn; lst[cn] = M[make_pair(x, y)]; bc[lst[cn]].push_back(cn); M[make_pair(x, y)] = cn; px = tx, py = ty; } R[i] = cn; } cin >> q; for (int i = (1), iend = (q); i <= iend; ++i) { int l, r; scanf( %d%d , &l, &r); l = L[l], r = R[r]; Q[i] = (que){l, r, i}; } sort(Q + 1, Q + 1 + q, [](que a, que b) { return a.l < b.l; }); int cur = 1; for (int i = (0), iend = (cn); i <= iend; ++i) { while (cur <= q && Q[cur].l == i) { ans[Q[cur].idx] = sum(Q[cur].r) - sum(Q[cur].l - 1); ++cur; } for (int x : bc[i]) ad(x, 1); } for (int i = (1), iend = (q); i <= iend; ++i) printf( %d n , ans[i]); } signed main() { solve(); }
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`ifdef SMV
`include "../or1200/or1200_defines.v"
`else
`include "or1200_defines.v"
`endif
module ovl_combo_wrapped(
clk,
rst,
enable,
num_cks,
start_event,
test_expr,
select,
prevConfigInvalid,
out,
out_delayed,
configInvalid
);
parameter num_cks_max = 7;
parameter num_cks_width = 3;
input clk;
input rst;
input enable;
input [num_cks_width-1:0] num_cks;
input start_event;
input test_expr;
input [1:0] select;
input prevConfigInvalid;
output out;
output out_delayed;
output configInvalid;
reg out_delayed;
wire [2:0] result_3bit_comb;
`ifdef SMV
ovl_combo ovl_combo (.num_cks_max(7),
.num_cks_width(3),
.clock(clk),
.reset(rst),
.enable(enable),
.num_cks(num_cks),
.start_event(start_event),
.test_expr(test_expr),
.select(select),
.fire_comb(result_3bit_comb)
);
`else // !`ifdef SMV
ovl_combo #(
.num_cks_max(7),
.num_cks_width(3)
) ovl_combo(
.clock(clk),
.reset(rst),
.enable(enable),
.num_cks(num_cks),
.start_event(start_event),
.test_expr(test_expr),
.select(select),
.fire_comb(result_3bit_comb)
);
`endif // !`ifdef SMV
always @(posedge clk)
if(rst == `OR1200_RST_VALUE)
out_delayed <= 1'b0;
else if(enable)
out_delayed <= result_3bit_comb[0];
// It is invalid if num_cks == 0 and next or on edge format selected
//(CKS) Fixed a bug! was prevConfigInvalid & ...
assign configInvalid = prevConfigInvalid | (~|num_cks & ~select[1]);
//(CKS) I added the &configInvalid
assign out = result_3bit_comb[0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_M_V
`define SKY130_FD_SC_LP__AND3_M_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_m (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_m (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_M_V
|
#include <bits/stdc++.h> using namespace std; const int MX = 100009; int arr[MX]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) scanf( %d , arr + i); int add = 0; for (int i = 0; i < m; ++i) { int cmd; scanf( %d , &cmd); if (cmd == 1) { int idx, val; scanf( %d%d , &idx, &val); --idx; arr[idx] = val - add; } else if (cmd == 2) { int val; scanf( %d , &val); add += val; } else { int idx; scanf( %d , &idx); --idx; printf( %d n , arr[idx] + add); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; const int maxlog = 24; int par[maxn][maxlog], h[maxn]; int siz[maxn]; bool mark[maxn]; int n; vector<int> adj[maxn]; void dfs(int x) { mark[x] = 1; for (int i = 0; i < adj[x].size(); i++) { int child = adj[x][i]; if (!mark[child]) { par[child][0] = x; h[child] = h[x] + 1; dfs(child); siz[x] += siz[child] + 1; } } } int LCAH(int fi, int se) { for (int i = maxlog - 1; i >= 0; i--) if (par[fi][i] != par[se][i]) { fi = par[fi][i]; se = par[se][i]; } return n - siz[fi] - siz[se] - 2; } int LCA(int fi, int se) { for (int i = maxlog - 1; i >= 0; i--) if (h[par[fi][i]] >= h[se]) fi = par[fi][i]; if (fi == se) return fi; for (int i = maxlog - 1; i >= 0; i--) if (par[fi][i] != par[se][i]) { fi = par[fi][i]; se = par[se][i]; } return par[fi][0]; } int main() { cin >> n; for (int i = 1; i < n; i++) { int fi, se; cin >> fi >> se; adj[fi].push_back(se); adj[se].push_back(fi); } dfs(1); for (int j = 1; j < maxlog; j++) for (int i = 1; i <= n; i++) par[i][j] = par[par[i][j - 1]][j - 1]; int q; cin >> q; while (q--) { int fi, se; cin >> fi >> se; if (h[fi] < h[se]) swap(fi, se); int dis = h[fi] + h[se] - 2 * h[LCA(fi, se)]; if (fi == se) cout << n << endl; else if (dis % 2 == 1) cout << 0 << endl; else if (h[fi] == h[se]) { cout << LCAH(fi, se) << endl; } else { dis /= 2; se = fi; for (int i = maxlog - 1; i >= 0; i--) { if ((1 << i) & dis) { fi = par[fi][i]; } } int k = dis - 1; for (int i = maxlog - 1; i >= 0; i--) { if ((1 << i) & k) { se = par[se][i]; } } cout << siz[fi] - siz[se] << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, p; cin >> t; for (; t > 0; t--) { cin >> n >> p; int br = 0; for (int r = 1; r <= n; r++) { for (int i = 1; i <= n; i++) { cout << i << << (i + r - 1) % n + 1 << endl; br++; if (br == 2 * n + p) goto st; } } st:; } return 0; }
|
module pcierc_test_eval_top (
// Clock and Reset
input wire refclkp, // 100MHz from board
input wire refclkn, // 100MHz from board
output wire sys_clk_125, // 125MHz output clock from core
input wire rst_n,
// ASIC side pins for PCSA. These pins must exist for the PCS core.
input wire hdinp0, // exemplar attribute hdinp0 NOPAD true
input wire hdinn0, // exemplar attribute hdinp0 NOPAD true
output wire hdoutp0, // exemplar attribute hdoutp0 NOPAD true
output wire hdoutn0, // exemplar attribute hdoutp0 NOPAD true
// From TX user Interface
input wire tx_req_vc0, // VC0 Request from User
input wire [15:0] tx_data_vc0, // VC0 Input data from user logic
input wire tx_st_vc0, // VC0 start of pkt from user logic.
input wire tx_end_vc0, // VC0 End of pkt from user logic.
input wire tx_nlfy_vc0, // VC0 End of nullified pkt from user logic.
input wire ph_buf_status_vc0, // VC0 Indicate the Full/alm.Full status of the PH buffers
input wire pd_buf_status_vc0, // VC0 Indicate PD Buffer has got space less than Max Pkt size
input wire nph_buf_status_vc0, // VC0 For NPH
input wire npd_buf_status_vc0, // VC0 For NPD
input wire cplh_buf_status_vc0, // VC0 For CPLH
input wire cpld_buf_status_vc0, // VC0 For CPLD
input wire ph_processed_vc0, // VC0 TL has processed one TLP Header - PH Type
input wire pd_processed_vc0, // VC0 TL has processed one TLP Data - PD TYPE
input wire nph_processed_vc0, // VC0 For NPH
input wire npd_processed_vc0, // VC0 For NPD
input wire cplh_processed_vc0, // VC0 For CPLH
input wire cpld_processed_vc0, // VC0 For CPLD
// To TX User Interface
output wire tx_rdy_vc0, // VC0 TX ready indicating signal
output wire [8:0] tx_ca_ph_vc0, // VC0 Available credit for Posted Type Headers
output wire [12:0] tx_ca_pd_vc0, // VC0 For Posted - Data
output wire [8:0] tx_ca_nph_vc0, // VC0 For Non-posted - Header
output wire [12:0] tx_ca_npd_vc0, // VC0 For Non-posted - Data
output wire [8:0] tx_ca_cplh_vc0, // VC0 For Completion - Header
output wire [12:0] tx_ca_cpld_vc0, // VC0 For Completion - Data
// To RX User Interface
output wire [15:0] rx_data_vc0, // VC0 Receive data
output wire rx_st_vc0, // VC0 Receive data start
output wire rx_end_vc0, // VC0 Receive data end
output wire rx_pois_tlp_vc0 , // VC0 poisoned tlp received
output wire rx_malf_tlp_vc0 , // VC0 malformed TLP in received data
// FROM TRN
output wire inta_n , // INTA interrupt
output wire intb_n , // INTB interrupt
output wire intc_n , // INTC interrupt
output wire intd_n , // INTD interrupt
output wire ftl_err_msg , // Fata error message received
output wire nftl_err_msg , // non-Fatal error message received
output wire cor_err_msg // Correctable error message received
)/* synthesis black_box_pad_pin = "HDINP0, HDINN0, HDOUTP0, HDOUTN0, REFCLKP, REFCLKN" */;
// =============================================================================
// Define Wires & Regs
// =============================================================================
// =============================================================================
//
//// =============================================================================
pcierc_test_top u1_pcie_top(
// Clock and Reset
.refclkp ( refclkp ) ,
.refclkn ( refclkn ) ,
.sys_clk_125 ( sys_clk_125 ) ,
.rst_n ( rst_n ),
.hdinp0 ( hdinp0 ),
.hdinn0 ( hdinn0 ),
.hdoutp0 ( hdoutp0 ),
.hdoutn0 ( hdoutn0 ),
.phy_force_cntl ( 4'b0000 ),
.phy_ltssm_cntl ( 13'h0000 ),
// Power Management Interface
.tx_dllp_val ( 2'd0 ),
.tx_pmtype ( 3'd0 ),
.tx_vsd_data ( 24'd0 ),
// From TX user Interface
.tx_req_vc0 ( tx_req_vc0 ),
.tx_data_vc0 ( tx_data_vc0 ),
.tx_st_vc0 ( tx_st_vc0 ),
.tx_end_vc0 ( tx_end_vc0 ),
.tx_nlfy_vc0 ( tx_nlfy_vc0 ),
.ph_buf_status_vc0 ( ph_buf_status_vc0 ),
.pd_buf_status_vc0 ( pd_buf_status_vc0 ),
.nph_buf_status_vc0 ( nph_buf_status_vc0 ),
.npd_buf_status_vc0 ( npd_buf_status_vc0 ),
.cplh_buf_status_vc0 ( cplh_buf_status_vc0 ),
.cpld_buf_status_vc0 ( cpld_buf_status_vc0 ),
.ph_processed_vc0 ( ph_processed_vc0 ),
.pd_processed_vc0 ( pd_processed_vc0 ),
.nph_processed_vc0 ( nph_processed_vc0 ),
.npd_processed_vc0 ( npd_processed_vc0 ),
.cplh_processed_vc0 ( cplh_processed_vc0 ),
.cpld_processed_vc0 ( cpld_processed_vc0 ),
.pd_num_vc0 ( 8'd1 ),
.npd_num_vc0 ( 8'd1 ),
.cpld_num_vc0 ( 8'd1 ),
// User Loop back data
.tx_lbk_data ( 16'd0 ),
.tx_lbk_kcntl ( 2'd0 ),
.tx_lbk_rdy ( ),
.rx_lbk_data ( ),
.rx_lbk_kcntl ( ),
// Power Management
.tx_dllp_sent ( ),
.rxdp_pmd_type ( ),
.rxdp_vsd_data ( ),
.rxdp_dllp_val ( ),
//-------- Outputs
// To TX User Interface
.tx_rdy_vc0 ( tx_rdy_vc0),
.tx_ca_ph_vc0 ( tx_ca_ph_vc0),
.tx_ca_pd_vc0 ( tx_ca_pd_vc0),
.tx_ca_nph_vc0 ( tx_ca_nph_vc0),
.tx_ca_npd_vc0 ( tx_ca_npd_vc0),
.tx_ca_cplh_vc0 ( tx_ca_cplh_vc0),
.tx_ca_cpld_vc0 ( tx_ca_cpld_vc0),
// To RX User Interface
.rx_data_vc0 ( rx_data_vc0),
.rx_st_vc0 ( rx_st_vc0),
.rx_end_vc0 ( rx_end_vc0),
.rx_pois_tlp_vc0 ( rx_pois_tlp_vc0 ),
.rx_malf_tlp_vc0 ( rx_malf_tlp_vc0 ),
// From DLL
.dll_status ( ),
// From PHY
.phy_cfgln_sum ( ),
.phy_pol_compliance ( ),
.phy_ltssm_state ( ),
.phy_ltssm_substate ( ),
// From TRN
.inta_n ( inta_n ) ,
.intb_n ( intb_n ) ,
.intc_n ( intc_n ) ,
.intd_n ( intd_n ) ,
.ftl_err_msg ( ftl_err_msg ) ,
.nftl_err_msg ( nftl_err_msg ) ,
.cor_err_msg ( cor_err_msg )
) ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, mod = 1, cnt = 0, i, min; cin >> n; vector<int> v{1, 5, 10, 20, 100}; while (n) { min = INT_MAX; for (i = 0; i < 5; ++i) { if (n / v[i] >= 1) { if (min > n / v[i]) { min = n / v[i]; mod = n % v[i]; } } } cnt += min; n = mod; } cout << cnt; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_2_V
`define SKY130_FD_SC_LP__EBUFN_2_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_2_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 5; const int MOD = 1e4 + 7; int n, m, q; int main() { scanf( %d , &q); while (q--) { int a, b; scanf( %d%d , &a, &b); int delt = abs(a - b); int ans = delt / 10 + (delt % 10 != 0); printf( %d n , ans); } return 0; }
|
`define WIDTH_P 3
`define ELS_P 4
`define SEED_P 1000
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
All the elements in the memory are written once and the first ELS_P/4
elements are re-written with w_v_i kept LOW to check if those elements are
overwritten.
2. PARAMETERIZATION
The synthesis of the design is not much influenced by data width WIDTH_P.
But the parameter ELS_P must be varied to include different cases, powers of 2
and non power of 2 for example. SEED_P may be varied to generate different
streams of random numbers that are written into the memory. A minimum
set of tests might be WIDTH_P=1,4,5 and ELS_P=1,2,3,4,5,8.
***************************************************************************/
module test_bsg;
#(
parameter width_p = `WIDTH_P,
parameter els_p = `ELS_P,
parameter addr_width_p = `BSG_SAFE_CLOG2(`ELS_P),
parameter cycle_time_p = 20,
parameter seed_p = `SEED_P,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
initial
begin
$display("\n");
$display("testing bsg_mem_2r1w with ...");
$display("WIDTH_P: %0d", width_p);
$display("ELS_P: %0d", els_p);
/*$monitor("count: %0d", count
, " w_addr_i: %b", test_input_wdata
, " w_addr_i: %b", test_input_waddr
, " w_v_i: %b", test_input_wv
, " r0_data_o: %b", test_output_rdata0
, " r1_data_o: %b", test_output_rdata1
);*/
end
// clock and reset generation
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
logic [width_p-1:0] test_input_wdata, test_output_rdata0, test_output_rdata1;
logic [addr_width_p-1:0] test_input_waddr, test_input_raddr0, test_input_raddr1;
logic test_input_wv;
bsg_mem_2r1w #( .width_p (width_p)
, .els_p (els_p)
, .read_write_same_addr_p(1)
) DUT
( .w_clk_i (clk)
, .w_reset_i(reset)
, .w_v_i (test_input_wv)
, .w_addr_i (test_input_waddr)
, .w_data_i (test_input_wdata)
, .r0_addr_i(test_input_raddr0)
, .r0_v_i (1'b1)
, .r1_addr_i(test_input_raddr1)
, .r1_v_i (1'b1)
, .r0_data_o(test_output_rdata0)
, .r1_data_o(test_output_rdata1)
);
// random test data generation;
// generates a new random number after every +ve clock edge
bsg_nonsynth_random_gen #( .width_p(width_p)
, .seed_p (seed_p)
) random_gen
( .clk_i (clk)
, .reset_i(reset)
, .yumi_i (1'b1)
, .data_o (test_input_wdata)
);
logic [addr_width_p:0] count; // no. of cycles after reset
logic [width_p-1:0] prev_input, prev_input_r; // 2 previous data inputs
logic [(els_p/4):0][width_p-1:0] temp; // stores inital (els_p/4)+1 values
// written in first pass for verification
// in second pass
logic finish_r;
always_ff @(posedge clk)
begin
if(reset)
begin
test_input_wv <= 1'b1;
test_input_waddr <= addr_width_p'(0);
test_input_raddr0 <= addr_width_p'(0);
test_input_raddr1 <= (els_p >= 2)? {addr_width_p'(0), 1'b1}:0;
prev_input <= width_p'(0);
count <= 0;
finish_r <= 1'b0;
end
else
begin
if(count == els_p+(els_p/4)+1)
finish_r <= 1'b1;
if(finish_r)
$finish;
if(count >= 2)
begin
test_input_raddr0 <= (test_input_raddr0 + 1) % els_p;
test_input_raddr1 <= (test_input_raddr1 + 1) % els_p;
end
if(count <= (els_p/4))
begin
temp[count] <= test_input_wdata;
end
if(count >= (els_p-1))
begin
test_input_wv <= 1'b0;
end
count <= (count + 1);
test_input_waddr <= (test_input_waddr + 1) % els_p;
prev_input <= test_input_wdata;
prev_input_r <= prev_input;
end
end
always_ff @(posedge clk)
begin
if(count>=2 && count<=els_p)
begin
assert(test_output_rdata1 == prev_input)
else $error("error in reading address: %b", test_input_raddr1);
assert(test_output_rdata0 == prev_input_r)
else $error("error in reading address: %b", test_input_raddr0);
end
if(count == els_p+1)
begin
assert(test_output_rdata1 == temp[test_input_raddr1])
else $error("error in reading address: %b", test_input_raddr1);
assert(test_output_rdata0 == prev_input_r)
else $error("error in reading address: %b", test_input_raddr0);
end
if(count > els_p+1)
begin
assert(test_output_rdata1 == temp[test_input_raddr1])
else $error("error in reading address: %b", test_input_raddr1);
assert(test_output_rdata0 == temp[test_input_raddr0])
else $error("error in reading address: %b", test_input_raddr0);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { stringstream ss; string s; cin >> s; for (int i = 0; i < s.length(); i++) { switch (s[i]) { case > : ss << 1000; break; case < : ss << 1001; break; case + : ss << 1010; break; case - : ss << 1011; break; case . : ss << 1100; break; case , : ss << 1101; break; case [ : ss << 1110; break; case ] : ss << 1111; break; default: break; } } string ans = ss.str(); int os = 1; long long jawab = 0; for (int i = ans.length() - 1; i >= 0; i--) { if (ans[i] == 1 ) jawab = (jawab + os) % 1000003; os = (os * 2) % 1000003; } cout << jawab << endl; return 0; }
|
// Problem: A. Meximization // Contest: Codeforces - Codeforces Round #708 (Div. 2) // URL: https://codeforces.com/contest/1497/problem/A // Memory Limit: 256 MB // Time Limit: 1000 ms // // Powered by CP Editor (https://cpeditor.org) #include <bits/stdc++.h> using INT=int; //#define int long long #define pb push_back #define eb emplace_back #define all(a) (a).begin(),(a).end() using namespace std; auto &_=std::ignore; using ll=long long; using vi=vector<int>; using vll=vector<ll>; using vvi=vector<vector<int>>; using vvll=vector<vector<ll>>; using pii=pair<int,int>; using pll=pair<ll,ll>; constexpr struct{ template<class T> constexpr operator T()const {return numeric_limits<T>::max();} } INF; constexpr struct{ template<class T> constexpr operator T()const {return numeric_limits<T>::min();} } MINF; template<class T> auto _format(ostream &os,const char *c,const T& cv)->decltype(os<<cv,c+1){ os << cv; while (*c!= } ) c++; return c+1; } template<size_t i,class T> auto _format(ostream &os,const char *c,const T& cv)->decltype( typename enable_if<i==tuple_size<T>::value>::type(1),c+1){return c;} template<size_t i=0,class T> auto _format(ostream &os,const char *c,const T& cv)->decltype( typename enable_if<i!=tuple_size<T>::value>::type(1),c+1){ while (*c!= { ) os << *c++; c=_format(os,c,get<i>(cv)); return _format<i+1>(os,c,cv); } template<class T> auto _format(ostream &os,const char *c,const T& cv)->decltype(begin(cv),c+1){ const char *ct=c+1; size_t ic=0; for (auto &i:cv){ const char *cc=c+1; while (*cc!= { ){ if (*cc== i ) os << ic,cc++; else os << *cc++; } cc=_format(os,cc,i); while (*cc!= } ) os << *cc++; ct=cc; ic++; } return ct+1; } string format(const char *c){return string(c);} template<class T,class ...Args> string format(const char *c,const T &a,Args&& ...rest){ ostringstream os; while (*c!= { &&*c!= 0 ) os<< *c++; if (*c== { ) c=_format(os,c,a); return os.str()+format(c,forward<Args>(rest)...); } template<class ...Args> ostream& print(Args&& ...rest){return cout<<format(forward<Args>(rest)...);} #ifdef LOCAL #define debug(...) cerr<<format(__VA_ARGS__) #else #define debug(...) cerr #endif template<class T> void _read(istream& is,T &a){is>>a;} void _read(istream& is,ll &a){ a=0;bool f=false;char c; while (!isdigit(c=is.get())&&is.good()) f=c== - ; if (!is.good()) return ; do a=(a<<3)+(a<<1)+c- 0 ; while (isdigit(c=is.get())); if (f) a=-a; } void read(){} template<class T,class ...Args> void read(T& a,Args& ...args){_read(cin,a);read(args...);} template<class T> void reada(vector<T>& v,size_t n){ v.reserve(n); for (size_t i=0;i<n;i++){ T a;cin>>a; v.emplace_back(move(a)); } } template<class T1,class T2> bool cmin(T1 &a,const T2 b){return a>b?a=b,1:0;} template<class T1,class T2> bool cmax(T1 &a,const T2 b){return a<b?a=b,1:0;} template<class T1,class T2,class ...T3> bool cmin(T1 &a,const T2 b,const T3 ...rest){return cmin(a,b)|cmin(a,rest...);} template<class T1,class T2,class ...T3> bool cmax(T1 &a,const T2 b,const T3 ...rest){return cmax(a,b)|cmax(a,rest...);} bool MULTIDATA=true; struct solution{ int n;map<int,int> m; void scan(){ read(n); vi v; reada(v,n); for (auto i:v) m[i]++; } int solve(){ for (auto mi:m) if (mi.second){ cout << mi.first << ; m[mi.first]--; } for (auto mi:m) for (int k=0;k<mi.second;k++) cout << mi.first << ; cout << endl; return 0; } }; INT main(){ cin.tie(0); ios::sync_with_stdio(false); int T=1; if (MULTIDATA) read(T); while (T--){ auto a=unique_ptr<solution>(new solution()); a->scan(); a->solve(); if (!cin.good()) break; } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize trapv using namespace std; void solveEachTest(long long int T35TC453N = 1) { unsigned long long int a, b; cin >> a >> b; bool ok = true; bitset<64> xandy((a - b) / 2); bitset<64> xxory(b); unsigned long long int x = (a - b) / 2; unsigned long long int y = x + b; if (a < b) ok = false; for (auto i = (0); (((1) < 0) ? (i) > (64) : (i) < (64)); (i) += (1)) { if (xandy[i] == 1 and xxory[i] == 1) { ok = false; break; } } if (!ok) cout << -1 ; else cout << x << << y; cout << n ; return; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); long long int T3X0 = 0, T353 = 1; solveEachTest(T353 - T3X0); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copied from: http://www.fpga4fun.com/Debouncer2.html
// Create Date: 07:35:15 10/30/2014
// Module Name: PushButton_Debouncer
//////////////////////////////////////////////////////////////////////////////////
module debouncer(
input clk,
input rst,
input PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal
// from which we make three outputs, all synchronous to the clock
output reg PB_state, // 1 as long as the push-button is active (down)
output PB_down, // 1 for one clock cycle when the push-button goes down (i.e. just pushed)
output PB_up // 1 for one clock cycle when the push-button goes up (i.e. just released)
);
// First use two flip-flops to synchronize the PB signal the "clk" clock domain
reg PB_sync_0; always @(posedge clk) PB_sync_0 <= ~PB; // invert PB to make PB_sync_0 active high
reg PB_sync_1; always @(posedge clk) PB_sync_1 <= PB_sync_0;
reg [15:0] PB_cnt;
// When the push-button is pushed or released, we increment the counter
// The counter has to be maxed out before we decide that the push-button state has changed
wire PB_idle = (PB_state==PB_sync_1);
wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's
always @(posedge clk or posedge rst) begin
if( rst ) begin
PB_cnt <= 16'h0;
PB_state <= 1'b0;
end
else
if(PB_idle)
PB_cnt <= 16'h0; // nothing's going on
else
begin
PB_cnt <= PB_cnt + 1'd1; // something's going on, increment the counter
if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed!
end
end
assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state;
assign PB_up = ~PB_idle & PB_cnt_max & PB_state;
endmodule
|
//------------------------------------------------------------------
//-- User test program for the Icezum Alhambra v1.1 board
//-- (c) Juan Gonzalez-Gomez (Obijuan). Nov-2016
//------------------------------------------------------------------
//-- Released under the GPL license
//------------------------------------------------------------------
`default_nettype none
//-- Top entity
//-- All the 4 sub-circuits are instantiated and the leds and tx signal
//-- multiplexed among them
module top(input wire CLK,
input wire SW1,
input wire SW2,
input wire RX,
output wire TX,
output wire LED0, LED1, LED2, LED3,
LED4, LED5, LED6, LED7);
//-- Test circuit 0: PWM on the leds
wire [7:0] led_ct0;
pwm_led CT0 (
.clk(CLK),
.ledb(led_ct0)
);
//-- Test circuit 1: Knight rider effect on the leds
wire [7:0] led_ct1;
kitt CT1 (
.clk(CLK),
.ledb(led_ct1)
);
//-- Test circuit 2: Serial tranmission (115200 bauds)
wire [7:0] led_ct2 = 8'hAA;
wire tx_ct2;
txstr CT2 (
.clk(CLK),
.go(sw2),
.tx(tx_ct2)
);
//-- Test circuit 4: Serial echo (The received char is display in the leds)
wire [7:0] led_ct3;
wire tx_ct3;
echo CT3 (
.clk(CLK),
.rx(RX),
.tx(tx_ct3),
.ledb(led_ct3)
);
//-- Multiplexer for accessing the leds and the tx signal
wire [7:0] ledb;
reg [1:0] sel_cto = 0;
always @ ( * ) begin
case (sel_cto)
0: begin
ledb = led_ct0;
TX = 1'b1; //-- No tx is used
end
1: begin
ledb = led_ct1;
TX = 1'b1; //-- No tx is used
end
2: begin
ledb = led_ct2;
TX = tx_ct2;
end
3: begin
ledb = led_ct3;
TX = tx_ct3;
end
default: begin
ledb = 0;
TX = 1'b1;
end
endcase
end
//-- Selector Circuit
always @ ( posedge CLK) begin
if (sw1) begin
sel_cto <= sel_cto + 1;
end
end
//-- Button 1
wire sw1;
debounce_pulse deb1 (
.clk(CLK),
.sw_in(SW1),
.sw_out(sw1)
);
//-- Button 2
wire sw2;
debounce_pulse deb2 (
.clk(CLK),
.sw_in(SW2),
.sw_out(sw2)
);
//-- Output the data to the leds
assign {LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0} = ledb;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k; cin >> n; long long int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int sum = 0; for (int i = 0; i < n - 1; i++) sum += (a[n - 1] - a[i]); cout << sum; }
|
(** * Rel: Properties of Relations *)
(* $Date: 2013-04-01 09:15:45 -0400 (Mon, 01 Apr 2013) $ *)
Require Export SfLib.
(** A (binary) _relation_ is just a parameterized proposition. As you know
from your undergraduate discrete math course, there are a lot of
ways of discussing and describing relations _in general_ -- ways
of classifying relations (are they reflexive, transitive, etc.),
theorems that can be proved generically about classes of
relations, constructions that build one relation from another,
etc. Let us pause here to review a few that will be useful in
what follows. *)
(** A (binary) relation _on_ a set [X] is a proposition parameterized by two
[X]s -- i.e., it is a logical assertion involving two values from
the set [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Somewhat confusingly, the Coq standard library hijacks the generic
term "relation" for this specific instance. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, while the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-that-or-equal-to
relation which we usually write like this [n1 <= n2]. *)
Print le.
(* ====>
Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m
*)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(* ######################################################### *)
(** * Basic Properties of Relations *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., if [R x
y1] and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined in Logic.v is a
partial function. *)
(* Print next_nat.
(* ====>
Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n)
*)
Check next_nat : relation nat.
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity. Qed. *)
(** However, the [<=] relation on numbers is not a partial function.
This can be shown by contradiction. In short: Assume, for a
contradiction, that [<=] is a partial function. But then, since
[0 <= 0] and [0 <= 1], it follows that [0 = 1]. This is nonsense,
so our assumption was contradictory. *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense.
Case "Proof of assertion".
apply Hc with (x := 0).
apply le_n.
apply le_S. apply le_n.
inversion Nonsense. Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in Logic.v is not a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] defined in Logic.v is a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
Case "le_n". apply Hnm.
Case "le_S". apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using le_trans. Do this.*)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
apply le_S. apply le_n.
apply H. Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~(S n <= n)]
A formal proof of this is an optional exercise below, but try
the informal proof without doing the formal proof first.
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, here are a few more common ones.
A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
Case "refl". apply le_reflexive.
split.
Case "antisym". apply le_antisymmetric.
Case "transitive.". apply le_trans. Qed.
(* ########################################################### *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y ->
clos_refl_trans R y z ->
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
Case "->".
intro H. induction H.
SCase "le_n". apply rt_refl.
SCase "le_S".
apply rt_trans with m. apply IHle. apply rt_step. apply nn.
Case "<-".
intro H. induction H.
SCase "rt_step". inversion H. apply le_S. apply le_n.
SCase "rt_refl". apply le_n.
SCase "rt_trans".
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is
natural -- it says, explicitly, that the reflexive and transitive
closure of [R] is the least relation that includes [R] and that is
closed under rules of reflexivity and transitivity. But it turns
out that this definition is not very convenient for doing
proofs -- the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions.
Here is a more useful definition... *)
Inductive refl_step_closure {X:Type} (R: relation X) : relation X :=
| rsc_refl : forall (x : X), refl_step_closure R x x
| rsc_step : forall (x y z : X),
R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
(** (Note that, aside from the naming of the constructors, this
definition is the same as the [multi] step relation used in many
other chapters.) *)
(** (The following [Tactic Notation] definitions are explained in
Imp.v. You can ignore them if you haven't read that chapter
yet.) *)
Tactic Notation "rt_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rt_step" | Case_aux c "rt_refl"
| Case_aux c "rt_trans" ].
Tactic Notation "rsc_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rsc_refl" | Case_aux c "rsc_step" ].
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [refl_step_closure] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Theorem rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> refl_step_closure R x y.
Proof.
intros X R x y H.
apply rsc_step with y. apply H. apply rsc_refl. Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Theorem rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
refl_step_closure R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> refl_step_closure R x y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
|
#include <bits/stdc++.h> using namespace std; int main() { int kase, ks = 0; int i, j, k; int n; int arr[1000]; string s; cin >> n; for (i = 1; i < n + 1; i++) cin >> arr[i]; int q; cin >> q; int x, y; while (q--) { cin >> x >> y; if (x > 1) arr[x - 1] += (y - 1); if (x < n) arr[x + 1] += (arr[x] - y); arr[x] = 0; } for (i = 1; i < n + 1; i++) cout << arr[i] << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR2_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int p, d; cin >> p >> d; long long int temp = 1; long long int po[19]; for (int i = 0; i <= 18; ++i) { po[i] = temp; temp *= 10; } int i = 1; temp = p; while (1) { long long int t = temp % po[i]; t /= po[i - 1]; long long int x = temp; x -= (t * po[i - 1]); x += (9 * po[i - 1]); if (p - x >= 0 && p - x <= d) { i++; temp = x; continue; } if ((p - x + po[i]) <= d && x - po[i] >= 0) { x -= po[i]; temp = x; i++; } else break; } cout << temp; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 5e5 + 10; int a[N]; int dp[2][N]; int minv[N]; int sum[N]; int n, k, p; class BIT { int a[110]; public: void init() { memset((a), (0x1f), sizeof(a)); } inline int lowbit(int x) { return x & -x; } void add(int x, int v) { x = p - x; while (x < 110) { a[x] = min(a[x], v); x += lowbit(x); } } int sum(int x) { int ret = INF; while (x) { ret = min(ret, a[x]); x -= lowbit(x); } return ret; } } b; template <class T> inline void readint(T &ret) { char c; ret = 0; while ((c = getchar()) < 0 || c > 9 ) ; while (c >= 0 && c <= 9 ) { ret = ret * 10 + (c - 0 ), c = getchar(); } } int main() { readint(n); readint(k); readint(p); int o = 0; for (int i = 1; i <= n; i++) { readint(a[i]); a[i] %= p; sum[i] = sum[i - 1] + a[i]; dp[o][i] = (a[i] + dp[o][i - 1]) % p; } for (int i = 2; i <= k; i++) { o ^= 1; b.init(); memset((dp[o]), (0x1f), sizeof(dp[o])); b.add(0, sum[i - 1]); int tot = 0; for (int j = i; j <= n; j++) { tot = (tot + a[j]); if (tot >= p) tot -= p; dp[o][j] = min(b.sum(tot) - p, b.sum(p)) + tot; int t = (p - tot); if (t == p) t = 0; b.add(t, dp[o ^ 1][j] + t); } } printf( %d n , dp[o][n]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007ll; const double EPS = 1e-11; int n; char s[1252525]; int cntright[1252525]; int cntleft[1252525]; int revright[1252525]; int revleft[1252525]; long long sumright[1252525]; long long sumleft[1252525]; int main() { scanf( %d , &n); scanf( %s , s); for (int i = 0; i < (int)(n); ++i) { if (s[i] == U ) { cntright[i + 1] = cntright[i] + 1; cntleft[i + 1] = cntleft[i]; revright[cntright[i + 1]] = i + 1; } else { cntright[i + 1] = cntright[i]; cntleft[i + 1] = cntleft[i] + 1; revleft[cntleft[i + 1]] = i + 1; } } for (int i = 0; i < (int)(n); ++i) { if (s[i] == U ) { sumright[i + 1] = sumright[i] + (n - i); sumleft[i + 1] = sumleft[i]; } else { sumright[i + 1] = sumright[i]; sumleft[i + 1] = sumleft[i] + (i + 1); } } for (int q = 0; q < (int)(n); ++q) { int l = cntright[q]; int r = cntleft[n] - cntleft[q + 1]; if (s[q] == U ) { if (r > l) { int rightbnd = l + 1; int leftbnd = l; int rrr = revleft[cntleft[q + 1] + rightbnd]; int lll = 0; long long ans = 0ll; ans += (sumright[q] - sumright[lll] - (long long)leftbnd * (n - q)) * 2ll; ans += (sumleft[rrr] - sumleft[q + 1] - (long long)rightbnd * (q + 1)) * 2ll; ans += q + 1; printf( %I64d , ans); } else { int rightbnd = r; int leftbnd = r; int rrr = n; int lll = revright[cntright[q] - leftbnd]; long long ans = 0ll; ans += (sumright[q] - sumright[lll] - (long long)leftbnd * (n - q)) * 2ll; ans += (sumleft[rrr] - sumleft[q + 1] - (long long)rightbnd * (q + 1)) * 2ll; ans += n - q; printf( %I64d , ans); } } else { if (l > r) { int rightbnd = r; int leftbnd = r + 1; int rrr = n; int lll = revright[cntright[q] - leftbnd]; long long ans = 0ll; ans += (sumright[q] - sumright[lll] - (long long)leftbnd * (n - q)) * 2ll; ans += (sumleft[rrr] - sumleft[q + 1] - (long long)rightbnd * (q + 1)) * 2ll; ans += n - q; printf( %I64d , ans); } else { int rightbnd = l; int leftbnd = l; int rrr = revleft[cntleft[q + 1] + rightbnd]; int lll = 0; long long ans = 0ll; ans += (sumright[q] - sumright[lll] - (long long)leftbnd * (n - q)) * 2ll; ans += (sumleft[rrr] - sumleft[q + 1] - (long long)rightbnd * (q + 1)) * 2ll; ans += q + 1; printf( %I64d , ans); } } if (q != n - 1) { putchar( ); } else { putchar( n ); } } return 0; }
|
#include <bits/stdc++.h> void print_row(int s, int *l, int size) { int i = s + 1; printf( %d , l[s]); while (i < size) printf( %d , l[i++]); i = 0; while (i < s) printf( %d , l[i++]); printf( n ); } int main() { int n, k; scanf( %d %d , &n, &k); int l[n]; l[0] = k; for (int i = 1; i < n; i++) l[i] = 0; for (int i = 0; i < n; i++) print_row(i, l, n); return 0; }
|
`timescale 1ns/1ps
module search_engine(
clk,
reset,
key_in_valid,
key_in,
bv_out_valid,
bv_out,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out
);
input clk;
input reset;
input key_in_valid;
input [71:0] key_in;
output wire bv_out_valid;
output wire [35:0] bv_out;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output reg localbus_ack_n;
output reg [31:0] localbus_data_out;
reg set_valid[0:7];
reg read_valid[0:7];
reg [8:0] addr;
wire data_out_valid[0:7];
wire [35:0] data_out[0:7];
wire stage_enable[0:1];
wire bv_valid_temp[0:7];
wire [35:0] bv_temp[0:7];
//---state----//
reg [3:0] set_state;
parameter idle = 4'd0,
ram_set = 4'd1,
ram_read = 4'd2,
wait_read = 4'd3,
wait_back = 4'd4;
//--------------reg--------------//
//--set--//
reg [31:0] localbus_addr;
reg [35:0] set_data_temp;
wire[35:0] data_out_temp;
wire data_out_valid_temp;
reg [35:0] data_out_temp_reg;
assign data_out_valid_temp = (data_out_valid[0] == 1'b1)? 1'b1:
(data_out_valid[1] == 1'b1)? 1'b1:
(data_out_valid[2] == 1'b1)? 1'b1:
(data_out_valid[3] == 1'b1)? 1'b1:
(data_out_valid[4] == 1'b1)? 1'b1:
(data_out_valid[5] == 1'b1)? 1'b1:
(data_out_valid[6] == 1'b1)? 1'b1:
(data_out_valid[7] == 1'b1)? 1'b1:
1'b0;
assign data_out_temp = (data_out_valid[0] == 1'b1)? data_out[0]:
(data_out_valid[1] == 1'b1)? data_out[1]:
(data_out_valid[2] == 1'b1)? data_out[2]:
(data_out_valid[3] == 1'b1)? data_out[3]:
(data_out_valid[4] == 1'b1)? data_out[4]:
(data_out_valid[5] == 1'b1)? data_out[5]:
(data_out_valid[6] == 1'b1)? data_out[6]:
(data_out_valid[7] == 1'b1)? data_out[7]:
36'b0;
//-----------------------set_state---------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_state <= idle;
set_valid[0] <= 1'b0;set_valid[1] <= 1'b0;set_valid[2] <= 1'b0;
set_valid[3] <= 1'b0;set_valid[4] <= 1'b0;set_valid[5] <= 1'b0;
set_valid[6] <= 1'b0;set_valid[7] <= 1'b0;
read_valid[0]<= 1'b0;read_valid[1]<= 1'b0;read_valid[2]<= 1'b0;
read_valid[3]<= 1'b0;read_valid[4]<= 1'b0;read_valid[5]<= 1'b0;
read_valid[6]<= 1'b0;read_valid[7]<= 1'b0;
set_data_temp <= 36'b0;
localbus_ack_n <= 1'b1;
localbus_data_out <= 32'b0;
end
else
begin
case(set_state)
idle:
begin
if(localbus_ale == 1'b1)
begin
localbus_addr <= localbus_data;
if(localbus_rd_wr == 1'b0)
begin
set_state <= ram_set;
end
else
begin
set_state <= ram_read;
end
end
end
ram_set:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'd0: set_data_temp[35:32] <= localbus_data[3:0];
1'd1:
begin
set_data_temp[31:0] <= localbus_data;
addr <= localbus_addr[11:3];
case(localbus_addr[14:12])
3'd0: set_valid[0] <= 1'b1;
3'd1: set_valid[1] <= 1'b1;
3'd2: set_valid[2] <= 1'b1;
3'd3: set_valid[3] <= 1'b1;
3'd4: set_valid[4] <= 1'b1;
3'd5: set_valid[5] <= 1'b1;
3'd6: set_valid[6] <= 1'b1;
3'd7: set_valid[7] <= 1'b1;
endcase
end
endcase
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
ram_read:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'b0:
begin
addr <= localbus_addr[11:3];
case(localbus_addr[14:12])
3'd0: read_valid[0] <= 1'b1;
3'd1: read_valid[1] <= 1'b1;
3'd2: read_valid[2] <= 1'b1;
3'd3: read_valid[3] <= 1'b1;
3'd4: read_valid[4] <= 1'b1;
3'd5: read_valid[5] <= 1'b1;
3'd6: read_valid[6] <= 1'b1;
3'd7: read_valid[7] <= 1'b1;
endcase
end
1'b1: localbus_data_out <= data_out_temp_reg[31:0];
endcase
if(localbus_addr[0] == 1'b0)
begin
set_state <= wait_read;
end
else
begin
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
end
wait_read:
begin
read_valid[0]<= 1'b0;read_valid[1]<= 1'b0;read_valid[2]<= 1'b0;
read_valid[3]<= 1'b0;read_valid[4]<= 1'b0;read_valid[5]<= 1'b0;
read_valid[6]<= 1'b0;read_valid[7]<= 1'b0;
if(data_out_valid_temp == 1'b1)begin
localbus_data_out <={28'b0,data_out_temp[35:32]};
data_out_temp_reg <= data_out_temp;
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
end
wait_back:
begin
set_valid[0] <= 1'b0;set_valid[1] <= 1'b0;set_valid[2] <= 1'b0;
set_valid[3] <= 1'b0;set_valid[4] <= 1'b0;set_valid[5] <= 1'b0;
set_valid[6] <= 1'b0;set_valid[7] <= 1'b0;
if(localbus_cs_n == 1'b1)
begin
localbus_ack_n <= 1'b1;
set_state <= idle;
end
end
default:
begin
set_state <= idle;
end
endcase
end
end
generate
genvar i;
for(i=0; i<8; i= i+1) begin : lookup_bit
lookup_bit lb(
.clk(clk),
.reset(reset),
.set_valid(set_valid[i]),
.set_data(set_data_temp[35:0]),
.read_valid(read_valid[i]),
.addr(addr),
.data_out_valid(data_out_valid[i]),
.data_out(data_out[i]),
.key_valid(key_in_valid),
.key(key_in[((i+1)*9-1):i*9]),
.bv_valid(bv_valid_temp[i]),
.bv(bv_temp[i])
);
end
endgenerate
bv_and_8 bv_and_8(
.clk(clk),
.reset(reset),
.bv_in_valid(bv_valid_temp[0]),
.bv_1(bv_temp[0]),
.bv_2(bv_temp[1]),
.bv_3(bv_temp[2]),
.bv_4(bv_temp[3]),
.bv_5(bv_temp[4]),
.bv_6(bv_temp[5]),
.bv_7(bv_temp[6]),
.bv_8(bv_temp[7]),
.bv_out_valid(bv_out_valid),
.bv_out(bv_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 5e5 + 10; long long N, arr[maxn], use[maxn]; signed main() { ios::sync_with_stdio(false); cin.tie(0); cin >> N; for (register long long i = 1; i <= N; ++i) { cin >> arr[i]; } sort(arr + 1, arr + 1 + N); long long pos = N / 2, l = pos + 1, r = N, ans = N; while (pos >= 1) { if (l <= r && arr[pos] * 2 <= arr[r]) { --ans, --r; } pos--; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 110000; long long a[M], b[M], c[M], be[M]; long long n, d, x; long long getNextX() { x = (x * 37 + 10007) % 1000000007; return x; } void initAB() { long long i; for (i = 0; i < n; i = i + 1) { a[i] = i + 1; } for (i = 0; i < n; i = i + 1) { swap(a[i], a[getNextX() % (i + 1)]); } for (i = 0; i < n; i = i + 1) { if (i < d) b[i] = 1; else b[i] = 0; } for (i = 0; i < n; i = i + 1) { swap(b[i], b[getNextX() % (i + 1)]); } } int main() { long long i, j, k; while (~scanf( %I64d%I64d%I64d , &n, &d, &x)) { initAB(); vector<int> vt; memset(be, 0, sizeof(be)); int cnt = 0; for (i = 0; i < n; i++) if (b[i]) cnt++; if (cnt <= sqrt(n)) { for (i = 0; i < n; i++) if (b[i]) vt.push_back(i); for (i = 0; i < n; i++) { long long mx = 0; for (j = 0; j < vt.size(); j++) { k = vt[j]; if (k > i) break; c[i] = max(c[i], a[i - k]); } } } else { vector<pair<int, int> > vc; for (i = 0; i < n; i++) vc.push_back(make_pair(a[i], i)); sort(vc.begin(), vc.end()); for (i = 0; i < n; i++) { for (j = n - 1; j >= 0; j--) { if (vc[j].second <= i && b[i - vc[j].second]) { c[i] = vc[j].first; break; } } } } for (i = 0; i < n; i++) cout << c[i] << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_PP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_PP_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #(PAR) m1();
m3 #(PAR) m3();
mnooverride #(10) mno();
input clk;
integer cyc=1;
reg [4:0] bitsel;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
bitsel = 0;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 1;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 2;
if (PAR[bitsel]!==1'b0) $stop;
end
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m1;
localparam PAR1MINUS1 = PAR1DUP-2-1;
localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly
parameter PAR1 = 0;
m2 #(PAR1MINUS1) m2 ();
endmodule
module m2;
parameter PAR2 = 10;
initial begin
$display("%x",PAR2);
if (PAR2 !== 2) $stop;
end
endmodule
module m3;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 3) $stop;
end
endmodule
module mnooverride;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 10) $stop;
end
endmodule
|
`include "defines.vh"
module divrem_tb;
reg clk = 0;
wire rst;
reg go = 0;
reg [15:0] num = 0;
reg [15:0] den = 0;
wire m1_ready;
wire m1_error;
wire [15:0] m1_quot;
wire [15:0] m1_rem;
reg [15:0] quot;
reg [15:0] rem;
por por_inst(
.clk(clk),
.rst(rst));
divrem dm1(
.clk(clk),
.go(go),
.rst(rst),
.num(num),
.den(den),
.ready(m1_ready),
.error(m1_error),
.quot(m1_quot),
.rem(m1_rem));
always #5 clk = !clk;
initial begin
wait (!rst);
for (num = 0; num < 20; num = num + 1)
for (den = 0; den < 20; den = den + 1) begin
@(negedge clk);
go = 1;
@(posedge clk);
@(negedge clk) go = 0;
#100;
rem = num / den;
quot = num % den;
if (!m1_ready) begin
$fatal(1, "FAILED -- A=%d, B=%d, READY=0", num, den);
end else if (den != 0 && (`isunknown(m1_quot) || `isunknown(m1_rem))) begin
$fatal(1, "FAILED -- A=%d, B=%d, UNDEF (%d %d)", num, den, m1_quot, m1_rem);
end else if (rem != m1_quot) begin
$fatal(1, "FAILED -- A=%d, B=%d, DIV=%d (should be %d)", num, den, m1_quot, rem);
end else if (quot != m1_rem) begin
$fatal(1, "FAILED -- A=%d, B=%d, MOD=%d (should be %d)", num, den, m1_rem, quot);
end
end
$display("divrem_tb ENDED");
$finish;
end
// initial
// $monitor("%t: go=%den, ready=%den, error=%den, quot=%h, rem=%h", $time, go, m1_ready, m1_error, m1_quot, m1_rem);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; long long a[50]; long long inv[50]; long long Finv[50]; long long n, s; void init() { inv[1] = 1; for (int i = 2; i <= 50; i++) { inv[i] = (mod - mod / i) * inv[mod % i] % mod; } Finv[0] = 1; for (int i = 1; i <= 50; i++) { Finv[i] = Finv[i - 1] % mod * inv[i] % mod; } } long long C(long long n, long long m) { if (n < 0 || m < 0 || m > n) return 0; long long res = 1; for (long long i = n; i > n - m; i--) { res = (i % mod * res) % mod; } res = res % mod * Finv[m] % mod; return res % mod; } int main() { init(); cin >> n >> s; for (int i = 0; i < n; i++) { cin >> a[i]; } long long res = 0; for (long long i = 0; i < (1ll << n); i++) { long long tmp = s; long long cnt = 0; for (long long j = 0; j < n; j++) { if ((1ll << j) & i) { tmp -= a[j] + 1; cnt++; } } if (tmp < 0) continue; if (cnt & 1) { res = (((res - C(tmp + n - 1, n - 1)) % mod + mod) % mod) % mod; } else { res = (res + C(tmp + n - 1, n - 1) % mod) % mod; } } cout << res << endl; }
|
//wb_gpio.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000002
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_gpio
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x02
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x01
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.cospandesign.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:8
USER_PARAMETER: DEFAULT_INTERRUPT_MASK
USER_PARAMETER: DEFAULT_INTERRUPT_EDGE
USER_PARAMETER: DEFAULT_INTERRUPT_BOTH_EDGE
USER_PARAMETER: DEFAULT_INTERRUPT_TIMEOUT
*/
`include "project_defines.v"
module wb_gpio#(
parameter DEFAULT_INTERRUPT_MASK = 0,
parameter DEFAULT_INTERRUPT_EDGE = 0,
parameter DEFAULT_INTERRUPT_BOTH_EDGE = 0,
parameter DEFAULT_INTERRUPT_TIMEOUT = 0
)(
input clk,
input rst,
//output [31:0] debug,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int,
output reg [31:0] gpio_out,
input [31:0] gpio_in
);
localparam GPIO = 32'h00000000;
localparam GPIO_OUTPUT_ENABLE = 32'h00000001;
localparam INTERRUPTS = 32'h00000002;
localparam INTERRUPT_ENABLE = 32'h00000003;
localparam INTERRUPT_EDGE = 32'h00000004;
localparam INTERRUPT_BOTH_EDGE = 32'h00000005;
localparam INTERRUPT_TIMEOUT = 32'h00000006;
localparam READ_CLOCK_RATE = 32'h00000007;
//gpio registers
reg [31:0] gpio_direction;
wire [31:0] gpio;
//interrupt registers
reg [31:0] interrupts;
reg [31:0] interrupt_enable;
reg [31:0] interrupt_edge;
reg [31:0] interrupt_both_edge;
reg [31:0] interrupt_timeout_count;
reg [31:0] interrupt_count;
reg clear_interrupts;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : tsbuf
assign gpio[i] = gpio_direction[i] ? gpio_out[i] : gpio_in[i];
end
endgenerate
//blocks
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h00000000;
o_wbs_ack <= 0;
//reset gpio's
gpio_out <= 32'h00000000;
gpio_direction <= 32'h00000000;
//reset interrupts
interrupt_enable <= DEFAULT_INTERRUPT_MASK;
interrupt_edge <= DEFAULT_INTERRUPT_EDGE;
interrupt_both_edge <= DEFAULT_INTERRUPT_BOTH_EDGE;
interrupt_timeout_count <= DEFAULT_INTERRUPT_TIMEOUT;
clear_interrupts <= 0;
end
else begin
clear_interrupts <= 0;
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
GPIO: begin
$display("user wrote %h", i_wbs_dat);
gpio_out <= i_wbs_dat & gpio_direction;
end
GPIO_OUTPUT_ENABLE: begin
$display("%h ->gpio_direction", i_wbs_dat);
gpio_direction <= i_wbs_dat;
end
INTERRUPTS: begin
$display("trying to write %h to interrupts?!", i_wbs_dat);
//can't write to the interrupt
end
INTERRUPT_ENABLE: begin
$display("%h -> interrupt enable", i_wbs_dat);
interrupt_enable <= i_wbs_dat;
clear_interrupts <= 1;
end
INTERRUPT_EDGE: begin
$display("%h -> interrupt_edge", i_wbs_dat);
interrupt_edge <= i_wbs_dat;
clear_interrupts <= 1;
end
INTERRUPT_BOTH_EDGE: begin
$display("%h -> interrupt_both_edge", i_wbs_dat);
interrupt_both_edge <= i_wbs_dat;
clear_interrupts <= 1;
end
INTERRUPT_TIMEOUT: begin
interrupt_timeout_count <= i_wbs_dat;
end
default: begin
end
endcase
end
else begin
if (!o_wbs_ack) begin //Fix double reads
//read request
case (i_wbs_adr)
GPIO: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= gpio;
clear_interrupts <= 1;
end
GPIO_OUTPUT_ENABLE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= gpio_direction;
end
INTERRUPTS: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupts;
clear_interrupts <= 1;
end
INTERRUPT_ENABLE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupt_enable;
end
INTERRUPT_EDGE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupt_edge;
end
INTERRUPT_BOTH_EDGE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupt_both_edge;
end
INTERRUPT_TIMEOUT: begin
o_wbs_dat <= interrupt_timeout_count;
end
READ_CLOCK_RATE: begin
o_wbs_dat <= `CLOCK_RATE;
end
default: begin
o_wbs_dat <= 32'h00;
end
endcase
end
end
o_wbs_ack <= 1;
end
end
end
end
//interrupts
reg [31:0] prev_gpio_in;
//this is the change
wire [31:0] pos_gpio_edge;
wire [31:0] neg_gpio_edge;
assign neg_gpio_edge = ((~interrupt_edge | interrupt_both_edge) & (interrupt_enable & ( prev_gpio_in & ~gpio_in)));
assign pos_gpio_edge = (( interrupt_edge | interrupt_both_edge) & (interrupt_enable & (~prev_gpio_in & gpio_in)));
/*
initial begin
$monitor ("%t, interrupts: %h, mask: %h, edge: %h, gpio_edge: %h", $time, interrupts, interrupt_enable, interrupt_edge, gpio_edge);
end
*/
/*
assign debug[0] = gpio[2];
assign debug[1] = gpio[3];
assign debug[2] = interrupt_enable[2];
assign debug[3] = interrupt_enable[3];
assign debug[4] = interrupt_edge[2];
assign debug[5] = interrupt_edge[3];
assign debug[6] = prev_gpio_in[2];
assign debug[7] = prev_gpio_in[3];
assign debug[8] = pos_gpio_edge[2];
assign debug[9] = pos_gpio_edge[3];
assign debug[10] = neg_gpio_edge[2];
assign debug[11] = neg_gpio_edge[3];
assign debug[12] = interrupts[2];
assign debug[13] = interrupts[3];
assign debug[14] = clear_interrupts;
*/
always @ (posedge clk) begin
if (rst) begin
interrupt_count <= 0;
interrupts <= 32'h00000000;
o_wbs_int <= 0;
end
else begin
//user requests to clear the interrupts
if (clear_interrupts) begin
interrupts <= 32'h00000000;
end
if ((pos_gpio_edge > 0) || (neg_gpio_edge > 0)) begin
//check to see if there was a negative or postive edge that occured
interrupts <= (pos_gpio_edge | neg_gpio_edge);
$display ("found an interrupt in the slave");
end
//Implement timeout behavior
if (interrupts == 0) begin
interrupt_count <= 0;
end
if ((interrupts > 0) && (interrupt_timeout_count > 0)) begin
if (interrupt_count < interrupt_timeout_count) begin
interrupt_count <= interrupt_count + 1;
end
else begin
interrupts <= 32'h00000000;
interrupt_count <= 0;
end
end
//Set the wishbone interrupt pin on this module
if (interrupts > 0) begin
o_wbs_int <= 1;
end
else begin
o_wbs_int <= 0;
end
prev_gpio_in <= gpio_in;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100 + 10; char s[maxn][maxn]; int main() { int a, b; for (int i = 0; i < 11; i++) gets(s[i]); scanf( %d%d , &a, &b); int r = (a - 1) % 3, c = (b - 1) % 3; int flag = 0; for (int i = r * 3 + r; i < (r + 1) * 3 + r; i++) { for (int j = c * 3 + c; j < (c + 1) * 3 + c; j++) { if (s[i][j] == . ) { flag = 1; break; } } } if (flag) { for (int i = r * 3 + r; i < (r + 1) * 3 + r; i++) { for (int j = c * 4; j < c * 4 + 3; j++) { if (s[i][j] == . ) s[i][j] = ! ; } } for (int i = 0; i < 11; i++) printf( %s n , s[i]); } else { for (int i = 0; i < 11; i++) { for (int j = 0; j < 11; j++) if (s[i][j] == . ) s[i][j] = ! ; } for (int i = 0; i < 11; i++) printf( %s n , s[i]); } return 0; }
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_interrupt.v
// Title : Interrupt logic
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_interrupt (
// ----- Inputs -------
clk_i,
rst_i,
// From external devices
interrupt,
// From pipeline
stall_x,
`ifdef CFG_DEBUG_ENABLED
non_debug_exception,
debug_exception,
`else
exception,
`endif
eret_q_x,
`ifdef CFG_DEBUG_ENABLED
bret_q_x,
`endif
csr,
csr_write_data,
csr_write_enable,
// ----- Outputs -------
interrupt_exception,
// To pipeline
csr_read_data
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input [interrupts-1:0] interrupt; // Interrupt pins
input stall_x; // Stall X pipeline stage
`ifdef CFG_DEBUG_ENABLED
input non_debug_exception; // Non-debug related exception has been raised
input debug_exception; // Debug-related exception has been raised
`else
input exception; // Exception has been raised
`endif
input eret_q_x; // Return from exception
`ifdef CFG_DEBUG_ENABLED
input bret_q_x; // Return from breakpoint
`endif
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output interrupt_exception; // Request to raide an interrupt exception
wire interrupt_exception;
output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR
reg [`LM32_WORD_RNG] csr_read_data;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
//pragma attribute asserted preserve_signal true
`endif
wire [interrupts-1:0] interrupt_n_exception;
// Interrupt CSRs
reg ie; // Interrupt enable
reg eie; // Exception interrupt enable
`ifdef CFG_DEBUG_ENABLED
reg bie; // Breakpoint interrupt enable
`endif
`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
wire [interrupts-1:0] ip; // Interrupt pending
`else
reg [interrupts-1:0] ip; // Interrupt pending
`endif
reg [interrupts-1:0] im; // Interrupt mask
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Determine which interrupts have occured and are unmasked
assign interrupt_n_exception = ip & im;
// Determine if any unmasked interrupts have occured
assign interrupt_exception = (|interrupt_n_exception) & ie;
// Determine which interrupts are currently being asserted or are already pending
`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
assign ip = interrupt;
`else
assign asserted = ip | interrupt;
`endif
assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
assign ip_csr_read_data = ip;
assign im_csr_read_data = im;
generate
if (interrupts > 1)
begin
// CSR read
always @(*)
begin
case (csr)
`ifdef CFG_MMU_ENABLED
`LM32_CSR_PSW,
`endif
`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
`LM32_CSR_IP: csr_read_data = ip;
`LM32_CSR_IM: csr_read_data = im;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
end
else
begin
// CSR read
always @(*)
begin
case (csr)
`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
`LM32_CSR_IP: csr_read_data = ip;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
end
endgenerate
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
generate
if (interrupts > 1)
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
`endif
im <= {interrupts{1'b0}};
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= {interrupts{1'b0}};
`endif
end
else
begin
// Set IP bit when interrupt line is asserted
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= asserted;
`endif
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
ie <= eie;
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if ( (csr == `LM32_CSR_IE)
`ifdef CFG_MMU_ENABLED
|| (csr == `LM32_CSR_PSW)
`endif
)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IM)
im <= csr_write_data[interrupts-1:0];
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
`endif
end
end
end
end
end
else
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
`endif
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= {interrupts{1'b0}};
`endif
end
else
begin
// Set IP bit when interrupt line is asserted
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= asserted;
`endif
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
ie <= eie;
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if ( (csr == `LM32_CSR_IE)
`ifdef CFG_MMU_ENABLED
|| (csr == `LM32_CSR_PSW)
`endif
)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
`endif
end
end
end
end
end
endgenerate
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.