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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) { unsigned long long int a, b, c, d; cin >> a >> b >> c >> d; unordered_map<unsigned long long int, unsigned long long int> mp, mp1; for (int i = 0; i <= 100000; i++) { ++mp[b + (i * a)]; ++mp1[d + (i * c)]; } for (int i = 0; i <= 100000; i++) { if (mp[i] && mp1[i]) { cout << i; return 0; } } cout << -1; } }
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#include <bits/stdc++.h> using namespace std; multiset<long long> h[1000005]; int main() { int q; scanf( %d , &q); while (q--) { char op, s[20]; long long a; scanf( %c , &op); if (op == + ) { scanf( %lld , &a); int idx = 0, k = 0; for (long long x = a; x > 0; x /= 10, k++) { int d = x % 10; idx |= (d & 1) << k; } h[idx].insert(a); } else if (op == - ) { scanf( %lld , &a); int idx = 0, k = 0; for (long long x = a; x > 0; x /= 10, k++) { int d = x % 10; idx |= (d & 1) << k; } h[idx].erase(h[idx].find(a)); } else { scanf( %s , s); reverse(s, s + strlen(s)); int idx = 0; for (int k = 0; s[k]; k++) idx |= (s[k] - 0 ) << k; printf( %d n , (int)h[idx].size()); } } }
|
module sub1 (/*AUTOARG*/
// Inputs
bus1
);
input [0:3] bus1;
endmodule
module sub2 (/*AUTOARG*/
// Inputs
bus2
);
input [0:3] bus2;
endmodule
module sub3 (/*AUTOARG*/
// Outputs
bus1, bus2
);
output [0:3] bus1;
output [4:7] bus2;
endmodule
module top (/*AUTOARG*/);
wire [4:7] bus2; // From sub3 of sub3.v
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [0:3] bus1; // From sub3 of sub3.v
// End of automatics
sub1 sub1 (/*AUTOINST*/
// Inputs
.bus1 (bus1[0:3]));
sub2 sub2 (/*AUTOINST*/
// Inputs
.bus2 (bus2[0:3]));
sub3 sub3 (/*AUTOINST*/
// Outputs
.bus1 (bus1[0:3]),
.bus2 (bus2));
endmodule
// Local Variables:
// verilog-auto-inst-vector:nil
// End:
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
module test_ram;
// Inputs
reg clk;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg [197:0] data;
// Outputs
wire [197:0] out;
wire done;
// Instantiate the Unit Under Test (UUT)
tiny uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
// write
sel = 1; w = 1;
data = 198'h115a25886512165251569195908560596a6695612620504191;
addr = 0;
#(`P);
data = 198'h1559546442405a181195655549614540592955a15a26984015;
addr = 3;
#(`P);
// not write
w = 0;
data = 198'h12222222222222222222222222222222222222222222222222;
addr = 3;
#(`P);
// read
sel = 1; w = 0;
addr = 0;
#(`P);
if (out !== 198'h115a25886512165251569195908560596a6695612620504191)
$display("E");
addr = 3;
#(`P);
if (out !== 198'h1559546442405a181195655549614540592955a15a26984015)
$display("E");
#(`P);
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> int du[100010], fa[100010], s1[100010], s2[100010]; int find(int x) { if (x != fa[x]) fa[x] = find(fa[x]); return fa[x]; } int main() { int n, m, x, y, i, j, k, sum; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) fa[i] = i; memset(du, 0, sizeof(du)); memset(s1, 0, sizeof(s1)); memset(s2, 0, sizeof(s2)); for (i = 1; i <= m; i++) { scanf( %d%d , &x, &y); j = find(x); k = find(y); du[x]++; du[y]++; if (j != k) { if (j < k) fa[k] = j; else fa[j] = k; } } for (i = 1; i <= n; i++) { j = find(i); s1[j] = s1[j] + du[i]; s2[j]++; } sum = 0; for (i = 1; i <= n; i++) if (s2[i] != 0) { j = s1[i] / 2; if (j < s2[i]) sum = sum + s2[i] - j; } printf( %d n , sum); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: LKB
// Engineer: Leonhard Neuhaus
//
// Create Date: 18.02.2016 11:42:49
// Design Name:
// Module Name: red_pitaya_lpf_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ()
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_lpf_block
#(
parameter SHIFTBITS = 4,//shift can be from 0 to 15 bits
parameter SIGNALBITS = 14, //bitwidth of signals
parameter MINBW = 10 //minimum allowed filter bandwidth
)
(
input clk_i,
input rstn_i ,
input [SHIFTBITS:0] shift,
input filter_on,
input highpass,
input signed [SIGNALBITS-1:0] signal_i,
output signed [SIGNALBITS-1:0] signal_o
);
`define CLOG2(x) \
(x < 2) ? 1 : \
(x < 4) ? 2 : \
(x < 8) ? 3 : \
(x < 16) ? 4 : \
(x < 32) ? 5 : \
(x < 64) ? 6 : \
(x < 128) ? 7 : \
(x < 256) ? 8 : \
(x < 512) ? 9 : \
(x < 1024) ? 10 : \
(x < 2048) ? 11 : \
(x < 2**12) ? 12 : \
(x < 2**13) ? 13 : \
(x < 2**14) ? 14 : \
(x < 2**15) ? 15 : \
(x < 2**16) ? 16 : \
(x < 2**17) ? 17 : \
(x < 2**18) ? 18 : \
(x < 2**19) ? 19 : \
(x < 2**20) ? 20 : \
(x < 2**21) ? 21 : \
(x < 2**22) ? 22 : \
(x < 2**23) ? 23 : \
(x < 2**24) ? 24 : \
(x < 2**25) ? 25 : \
(x < 2**26) ? 26 : \
(x < 2**27) ? 27 : \
(x < 2**28) ? 28 : \
(x < 2**29) ? 29 : \
(x < 2**30) ? 30 : \
(x < 2**31) ? 31 : \
(x <= 2**32) ? 32 : \
-1
localparam MAXSHIFT = `CLOG2(125000000/MINBW); // gives an effective limit of 10 MHz (divided by 4 pi)
reg signed [SIGNALBITS+MAXSHIFT-1:0] y;
reg signed [SIGNALBITS+MAXSHIFT-1:0] delta; //we need this cumbersome imperfect implementation with a delta buffer to introduce some delay so the code works at 125 MHZ
wire signed [SIGNALBITS+MAXSHIFT-1:0] shifted_delta;
wire signed [SIGNALBITS-1:0] y_out;
wire filter_off;
assign y_out = y[MAXSHIFT+SIGNALBITS-1:MAXSHIFT];
assign shifted_delta = delta<<((shift<MAXSHIFT) ? shift : MAXSHIFT);
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
y <= {MAXSHIFT+SIGNALBITS{1'b0}};
delta <= {MAXSHIFT+SIGNALBITS{1'b0}};
end
else begin
delta <= signal_i - y_out;
y <= y + shifted_delta;
end
end
assign signal_o = (filter_on == 1'b0) ? signal_i : ( (highpass==1'b0) ? y_out : delta);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4BB_BLACKBOX_V
`define SKY130_FD_SC_MS__AND4BB_BLACKBOX_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and4bb (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4BB_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000000; long long powmod(long long a, long long b) { long long res = 1; a %= mod; for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } const int N = 201000; struct node { long long fib[4]; int fg; } nd[N * 4]; int fib[N], a[N]; int n, ty, l, r, v, m; long long ret[2], ans; void build(int p, int l, int r) { if (l == r) { nd[p].fib[0] = fib[l]; nd[p].fib[1] = fib[l + 1]; nd[p].fib[2] = nd[p].fib[0] * a[l] % mod; nd[p].fib[3] = nd[p].fib[1] * a[l] % mod; } else { int md = (l + r) >> 1; build(p + p, l, md); build(p + p + 1, md + 1, r); for (int i = 0; i < 4; i++) nd[p].fib[i] = (nd[p + p].fib[i] + nd[p + p + 1].fib[i]) % mod; } } void setp(int p, int w) { nd[p].fg += w; nd[p].fib[2] = (nd[p].fib[2] + nd[p].fib[0] * w) % mod; nd[p].fib[3] = (nd[p].fib[3] + nd[p].fib[1] * w) % mod; } void push(int p) { if (nd[p].fg) { setp(p + p, nd[p].fg); setp(p + p + 1, nd[p].fg); nd[p].fg = 0; } } void modify(int p, int l, int r, int x, long long w) { if (l == r) { nd[p].fib[2] = fib[l] * w % mod; nd[p].fib[3] = fib[l + 1] * w % mod; } else { push(p); int md = (l + r) >> 1; if (x <= md) modify(p + p, l, md, x, w); else modify(p + p + 1, md + 1, r, x, w); for (int i = 2; i < 4; i++) nd[p].fib[i] = (nd[p + p].fib[i] + nd[p + p + 1].fib[i]) % mod; } } void add(int p, int l, int r, int tl, int tr, int w) { if (l == tl && r == tr) setp(p, w); else { push(p); int md = (l + r) >> 1; if (tr <= md) add(p + p, l, md, tl, tr, w); else if (tl > md) add(p + p + 1, md + 1, r, tl, tr, w); else add(p + p, l, md, tl, md, w), add(p + p + 1, md + 1, r, md + 1, tr, w); for (int i = 2; i < 4; i++) nd[p].fib[i] = (nd[p + p].fib[i] + nd[p + p + 1].fib[i]) % mod; } } void query(int p, int l, int r, int tl, int tr) { if (l == tl && r == tr) { for (int i = 2; i < 4; i++) ret[i - 2] = (ret[i - 2] + nd[p].fib[i]) % mod; } else { push(p); int md = (l + r) >> 1; if (tr <= md) query(p + p, l, md, tl, tr); else if (tl > md) query(p + p + 1, md + 1, r, tl, tr); else query(p + p, l, md, tl, md), query(p + p + 1, md + 1, r, md + 1, tr); } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i < n + 1; i++) scanf( %d , a + i); fib[0] = fib[1] = 1; for (int i = 2; i < n + 10; i++) fib[i] = (fib[i - 1] + fib[i - 2]) % mod; build(1, 1, n); for (int i = 0; i < m; i++) { scanf( %d , &ty); if (ty == 1) { scanf( %d%d , &l, &v); modify(1, 1, n, l, v); } else if (ty == 2) { scanf( %d%d , &l, &r); ret[0] = ret[1] = 0; query(1, 1, n, l, r); ans = (fib[l] * ret[0] - fib[l - 1] * ret[1]) % mod; if (l % 2 == 1) ans *= -1; if (ans < 0) ans += mod; printf( %I64d n , ans); } else { scanf( %d%d%d , &l, &r, &v); add(1, 1, n, l, r, v); } } }
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#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:102400000,102400000 ) const int INF = 0x3f3f3f3f3f, mod = 1e9 + 7; const double eps = 1e-6, PI = acos(-1); template <typename T> inline void read(T &x) { x = 0; T f = 1; char ch; do { ch = getchar(); if (ch == - ) f = -1; } while (ch < 0 || ch > 9 ); do x = x * 10 + ch - 0 , ch = getchar(); while (ch <= 9 && ch >= 0 ); x *= f; } long long n, m; int main() { read(n), read(m); long long min1 = max(0LL, n - m * 2); if (m == 0) { printf( %lld %lld n , n, n); return 0; } long long max1 = 0; for (int i = 2; i <= n; i++) { long long now = 1LL * i * (i - 1) / 2; if (m <= now) { max1 = n - i; break; } } printf( %lld %lld n , min1, max1); return 0; }
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#include <bits/stdc++.h> using namespace std; const long double pi = acos(-1); struct point { long double x, y; point(long double x = 0, long double y = 0) : x(x), y(y) {} point operator+(const point &o) const { return point(x + o.x, y + o.y); } point operator-(const point &o) const { return point(x - o.x, y - o.y); } point &operator+=(const point &o) { x += o.x, y += o.y; return *this; } point &operator-=(const point &o) { x -= o.x, y -= o.y; return *this; } long double operator*(const point &o) const { return (x * o.x + y * o.y); } point operator*(long double c) const { return point(x * c, y * c); } point &operator*=(long double c) { x *= c, y *= c; return *this; } long double snorm() { return (x * x + y * y); } }; point operator*(long double c, point A) { return A * c; } long double dist(point A, point B) { return sqrt((A - B).snorm()); } long double dist(point X, point A, point B) { A -= X, B -= X; long double t = (A.snorm() - A * B) / (B - A).snorm(); if (t < 0 || t > 1) return sqrt(min(A.snorm(), B.snorm())); return sqrt((t * (B - A) + A).snorm()); } int N; point P, a[100100]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> N >> P.x >> P.y; cout << fixed << setprecision(10); int i; for (i = 1; i <= N; i++) cin >> a[i].x >> a[i].y; a[N + 1] = a[1]; long double maxd = 0, mind = (1 << 30); for (i = 1; i <= N; i++) { maxd = max(maxd, dist(P, a[i])); mind = min(mind, dist(P, a[i], a[i + 1])); } cout << pi * (maxd * maxd - mind * mind) << n ; return 0; }
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 02:34:37 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zybo_zynq_design_processing_system7_0_0_stub.v
// Design : zybo_zynq_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
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#include <bits/stdc++.h> int main(void) { int n; int a[1100]; while (scanf( %d , &n) == 1) { for (int i = 0; i < n; i++) scanf( %d , a + i); int cnt = 1, ans = 0; int j = 0; if (n <= 2) { printf( %d n , ans); break; } if (a[0] > a[1]) j = -1; else if (a[0] == a[1]) j = 0; else j = 1; while (cnt < n - 1) { if (j == -1) { for (; cnt < n - 1 && a[cnt] > a[cnt + 1]; cnt++) ; if (cnt == n - 1) break; if (a[cnt] > a[cnt + 1]) j = -1; else if (a[cnt] == a[cnt + 1]) j = 0; else { ans++; j = 1; } } if (j == 0) { for (; cnt < n - 1 && a[cnt] == a[cnt + 1]; cnt++) ; if (cnt == n - 1) break; if (a[cnt] > a[cnt + 1]) j = -1; else if (a[cnt] == a[cnt + 1]) j = 0; else j = 1; } if (j == 1) { for (; cnt < n - 1 && a[cnt] < a[cnt + 1]; cnt++) ; if (cnt == n - 1) break; if (a[cnt] > a[cnt + 1]) { ans++; j = -1; } else if (a[cnt] == a[cnt + 1]) j = 0; else j = 1; } } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int n, c[N], k = 1e5; char a[N], b[N]; void solve(int p, int coef) { if (a[p - 1] + coef < 0 || a[p - 1] + coef > 9 ) { solve(p - 1, -coef); } a[p - 1] += coef; a[p] += coef; printf( %d %d n , p - 1, coef); if (!--k) { exit(0); } } int main() { scanf( %d%s%s , &n, a + 1, b + 1); copy(a + 1, a + 1 + n, c + 1); long long answer = 0; for (int i = 1; i < n; ++i) { if (c[i] != b[i]) { answer += abs(c[i] - (int)b[i]); c[i + 1] += (int)b[i] - c[i]; } } if (c[n] != b[n]) { return puts( -1 ); } else { printf( %lld n , answer); if (answer < k) { k = answer; } for (int i = n; i; --i) { for (; a[i] != b[i]; solve(i, a[i] < b[i] ? 1 : -1)) ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, k, i, dis = 10000000, temp, a[1000]; int main() { cin >> n >> m >> k; for (i = 0; i < n; ++i) cin >> a[i]; for (i = 0; i < n; ++i) { if (a[i] != 0 && a[i] <= k) { if (m <= i) temp = (i - m + 1) * 10; else temp = (m - i - 1) * 10; if (dis > temp) dis = temp; } } cout << dis; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, sum = 0; cin >> n; bool isLR = false; char a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] == L || a[i] == R ) isLR = true; } bool flag = false; int count = 0; for (int i = 0; i < n; i++) { if (a[i] == . && flag == true) count++; else if (a[i] == L ) flag = true; else if (a[i] == R ) { sum += count; count = 0; flag = false; } } flag = false; count = 0; for (int i = 0; i < n; i++) { if (a[i] == . && flag == true) count++; else if (a[i] == R ) flag = true; else if (a[i] == L ) { if (count % 2 != 0) sum++; count = 0; flag = false; } } count = 0; for (int i = 0; i < n; i++) { if (a[i] == . ) count++; else if (a[i] == L ) break; else if (a[i] == R ) { sum += count; break; } } count = 0; for (int i = n - 1; i >= 0; i--) { if (a[i] == . ) count++; else if (a[i] == R ) break; else if (a[i] == L ) { sum += count; break; } } if (isLR == true) cout << sum; else cout << n; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 50010; string g[N]; int q, n, m, ro[N], co[N]; int main() { cin.tie(0); ios_base::sync_with_stdio(0); cin >> q; while (q--) { cin >> n >> m; for (int i = 0; i < n; ++i) cin >> g[i]; for (int i = 0; i < n; ++i) { ro[i] = 0; for (int j = 0; j < m; ++j) ro[i] += g[i][j] == . ; } for (int i = 0; i < m; ++i) { co[i] = 0; for (int j = 0; j < n; ++j) co[i] += g[j][i] == . ; } int ans = n * m; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { int here = ro[i] + co[j] - (g[i][j] == . ); ans = min(ans, here); } } cout << ans << n ; } return 0; }
|
//-----------------------------------------------------------------------------
// Title : 10/100/1G Ethernet FIFO for 8-bit Client Interface
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : eth_fifo_8.v
// Version : 1.3
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//------------------------------------------------------------------------
// Description: This is the top-level wrapper for the 10/100/1G Ethernet
// FIFO. The top level wrapper consists of individual FIFOs
// on the transmitter path and on the receiver path.
//
// Each path consists of an 8-bit LocalLink-to-8-bit
// client-interface FIFO.
//------------------------------------------------------------------------
`timescale 1ps / 1ps
module eth_fifo_8 (
// Transmit FIFO MAC TX Interface
tx_clk, // MAC transmit clock
tx_reset, // Synchronous reset (tx_clk)
tx_enable, // Clock enable for tx_clk
tx_data, // Data to MAC transmitter
tx_data_valid, // Valid signal to MAC transmitter
tx_ack, // Ack signal from MAC transmitter
tx_underrun, // Underrun signal to MAC transmitter
tx_collision, // Collsion signal from MAC transmitter
tx_retransmit, // Retransmit signal from MAC transmitter
// Transmit FIFO LocalLink Interface
tx_ll_clock, // Local link write clock
tx_ll_reset, // synchronous reset (tx_ll_clock)
tx_ll_data_in, // Data to Tx FIFO
tx_ll_sof_in_n, // sof indicator to FIFO
tx_ll_eof_in_n, // eof indicator to FIFO
tx_ll_src_rdy_in_n, // src ready indicator to FIFO
tx_ll_dst_rdy_out_n, // dst ready indicator from FIFO
tx_fifo_status, // FIFO memory status
tx_overflow, // FIFO overflow indicator from FIFO
// Receive FIFO MAC RX Interface
rx_clk, // MAC receive clock
rx_reset, // Synchronous reset (rx_clk)
rx_enable, // Clock enable for rx_clk
rx_data, // Data from MAC receiver
rx_data_valid, // Valid signal from MAC receiver
rx_good_frame, // Good frame indicator from MAC receiver
rx_bad_frame, // Bad frame indicator from MAC receiver
rx_overflow, // FIFO overflow indicator from FIFO
// Receive FIFO LocalLink Interface
rx_ll_clock, // Local link read clock
rx_ll_reset, // synchronous reset (rx_ll_clock)
rx_ll_data_out, // Data from Rx FIFO
rx_ll_sof_out_n, // sof indicator from FIFO
rx_ll_eof_out_n, // eof indicator from FIFO
rx_ll_src_rdy_out_n, // src ready indicator from FIFO
rx_ll_dst_rdy_in_n, // dst ready indicator to FIFO
rx_fifo_status // FIFO memory status
);
//---------------------------------------------------------------------------
// Define Interface Signals
//---------------------------------------------------------------------------
parameter FULL_DUPLEX_ONLY = 0;
// Transmit FIFO MAC TX Interface
input tx_clk;
input tx_reset;
input tx_enable;
output [7:0] tx_data;
output tx_data_valid;
input tx_ack;
output tx_underrun;
input tx_collision;
input tx_retransmit;
// Transmit FIFO LocalLink Interface
input tx_ll_clock;
input tx_ll_reset;
input [7:0] tx_ll_data_in;
input tx_ll_sof_in_n;
input tx_ll_eof_in_n;
input tx_ll_src_rdy_in_n;
output tx_ll_dst_rdy_out_n;
output [3:0] tx_fifo_status;
output tx_overflow;
// Receive FIFO MAC RX Interface
input rx_clk;
input rx_reset;
input rx_enable;
input [7:0] rx_data;
input rx_data_valid;
input rx_good_frame;
input rx_bad_frame;
output rx_overflow;
// Receive FIFO LocalLink Interface
input rx_ll_clock;
input rx_ll_reset;
output [7:0] rx_ll_data_out;
output rx_ll_sof_out_n;
output rx_ll_eof_out_n;
output rx_ll_src_rdy_out_n;
input rx_ll_dst_rdy_in_n;
output [3:0] rx_fifo_status;
assign tx_underrun = 1'b0;
// Transmitter FIFO
tx_client_fifo_8 #(
.FULL_DUPLEX_ONLY (FULL_DUPLEX_ONLY)
)
tx_fifo_i (
.rd_clk (tx_clk),
.rd_sreset (tx_reset),
.rd_enable (tx_enable),
.tx_data (tx_data),
.tx_data_valid (tx_data_valid),
.tx_ack (tx_ack),
.tx_collision (tx_collision),
.tx_retransmit (tx_retransmit),
.overflow (tx_overflow),
.wr_clk (tx_ll_clock),
.wr_sreset (tx_ll_reset),
.wr_data (tx_ll_data_in),
.wr_sof_n (tx_ll_sof_in_n),
.wr_eof_n (tx_ll_eof_in_n),
.wr_src_rdy_n (tx_ll_src_rdy_in_n),
.wr_dst_rdy_n (tx_ll_dst_rdy_out_n),
.wr_fifo_status (tx_fifo_status)
);
// Receiver FIFO
rx_client_fifo_8 rx_fifo_i (
.wr_clk (rx_clk),
.wr_enable (rx_enable),
.wr_sreset (rx_reset),
.rx_data (rx_data),
.rx_data_valid (rx_data_valid),
.rx_good_frame (rx_good_frame),
.rx_bad_frame (rx_bad_frame),
.overflow (rx_overflow),
.rd_clk (rx_ll_clock),
.rd_sreset (rx_ll_reset),
.rd_data_out (rx_ll_data_out),
.rd_sof_n (rx_ll_sof_out_n),
.rd_eof_n (rx_ll_eof_out_n),
.rd_src_rdy_n (rx_ll_src_rdy_out_n),
.rd_dst_rdy_n (rx_ll_dst_rdy_in_n),
.rx_fifo_status (rx_fifo_status)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int ans[400] = { 1, 9, 245, 126565, 54326037, 321837880, 323252721, 754868154, 328083248, 838314395, 220816781, 893672292, 166441208, 251255697, 114256285, 118775501, 482714697, 11784725, 460862131, 550384565, 106742050, 425241115, 626692854, 674266678, 320014275, 345949512, 527320049, 897822749, 137190263, 491039182, 810384961, 482023334, 658099864, 886790989, 845381174, 371433224, 278969124, 420088324, 696766322, 388302635, 141033366, 46387851, 932125021, 278342766, 371131134, 922501918, 110778457, 506223573, 806353719, 391845991, 923507761, 780307355, 109951115, 830090230, 605558495, 344686604, 988110893, 944684429, 715019947, 799898820, 384672708, 907325090, 758952329, 550672104, 368337206, 394915145, 401744167, 923781939, 831857516, 407845661, 329267374, 927004007, 891609656, 897919613, 481297880, 737337940, 651873737, 287246681, 973133651, 679864988, 784719328, 820504764, 875613823, 806512665, 164851642, 500228957, 951814419, 447763649, 273141670, 979349615, 964027956, 809510400, 276634497, 116631976, 426739449, 175282420, 885948162, 62270880, 974395255, 675165056, 759589968, 837957573, 931897605, 152352780, 585420109, 1772087, 333401718, 898833639, 745874265, 786209423, 691982338, 498790927, 473374639, 274302623, 971280670, 241671319, 13070005, 302088807, 550276351, 436592588, 631667314, 548656698, 730626984, 146295220, 674398632, 400383348, 454138904, 786220712, 118620797, 233440672, 217349271, 274853536, 310607544, 105221205, 769566615, 853585061, 800665807, 695377419, 924327065, 388199705, 551624811, 721435546, 501720515, 308465454, 825369234, 396065729, 451899519, 295058424, 142088952, 473485086, 378771634, 734511215, 462404399, 959198328, 337668263, 794122911, 38911400, 951992982, 472696081, 373904752, 105884826, 630251717, 28980684, 845136347, 353665773, 691661192, 19922354, 231463797, 757917231, 242739918, 979036950, 713722080, 234689388, 2243164, 209872853, 240808787, 539523346, 425797848, 913772061, 224613100, 421742777, 222232478, 92712941, 215137570, 949901408, 274827432, 15162482, 593145989, 274574232, 239282092, 762720192, 804146934, 500629424, 565985054, 81127381, 671811155, 655565571, 890331075, 237994348, 743647404, 667160634, 713914299, 668506729, 741341289, 277636808, 762781382, 14272789, 902864131, 567443405, 149113383, 648844381, 825489976, 933016723, 192288078, 734493315, 240985733, 861817693, 762711459, 525904609, 532463481, 377133989, 620711079, 772561562, 980733194, 227599811, 162774370, 209512798, 787116594, 3509258, 748795368, 378035466, 612938915, 802091952, 857679599, 481748937, 493370392, 358420805, 48301629, 412001241, 463126722, 509578422, 967799131, 994766554, 687287243, 863623583, 771554899, 690911527, 855314994, 923686429, 246862514, 192479791, 133487041, 703444043, 295281758, 801816257, 920762934, 749306433, 973004841, 848644684, 560026478, 952127278, 616654635, 839390326, 975154012, 409583672, 635350249, 343228425, 335331602, 223826406, 952341037, 589677800, 249747234, 555694261, 137143500, 628190328, 461598392, 431912756, 29349807, 759199489, 783281228, 781971312, 915823407, 388508707, 718062705, 27424111, 309999451, 963383322, 831185229, 132910888, 347028136, 850484840, 223055285, 142335980, 144754000, 772005560, 81796039, 167696020, 79454283, 172772542, 201056991, 484957644, 716630285, 763194701, 211505841, 903448791, 926964672, 257752668, 482951716, 411539070, 620249847, 592476107, 170473128, 814662613, 898000271, 57354872, 361106091, 488697643, 889007954, 138725767, 684860983, 36248116, 304610143, 137633385, 413715776, 99010024, 779653665, 100387568, 286328069, 564731826, 621740468, 943513219, 506666491, 249987886, 553719884, 769853086, 337485319, 702455584, 809637762, 755400257, 892290368, 502180086, 364275817, 118162370, 873374339, 261271695, 970132574, 744105500, 434447173, 117975095, 383088393, 625447969, 180281249, 545367713, 133236931, 360175662, 148087453, 806871297, 498529036, 886076476, 65645000, 465138299, 967109895, 331362616, 472283705, 796894900, 199697765, 503759892, 472807906, 187586706, 941198065, 782234442, 57693411, 18678611, 82626204, 395317191, 570588915, 152519440, 449852456, 63696518, 763741345, 878748386, 494317541, 444782633, 93316211, 929164666, 529288371, 165769871, 730546850, 955877127, 994202767, 492009567, 275683011, 415902127, 95725776, 718047399, 786963365, 73091278, 986172399, 174591541, 913259286}; int main() { scanf( %d , &n); printf( %d , ans[n - 1]); return 0; }
|
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
// GPMC to FIFO
//
// Reads frames from BRAM pages and writes them into FIFO interface.
// The GPMC is asynchronously alerted when a BRAM page is available.
//
// EM_CLK:
// A GPMC write transaction consists of one EM_CLK cycle (idle low).
//
// EM_WE:
// Write enable is actually the combination of ~NWE & ~NCS.
// The write enable is active for the entire transaction.
//
// EM_D:
// Data is set on the rising edge and written into BRAM on the falling edge.
//
// EM_A:
// Address is set on the rising edge and read by BRAM on the falling edge.
////////////////////////////////////////////////////////////////////////
module gpmc_to_fifo
#(parameter PTR_WIDTH = 2, parameter ADDR_WIDTH = 10, parameter LAST_ADDR = 10'h3ff)
(input [15:0] EM_D, input [ADDR_WIDTH:1] EM_A, input EM_CLK, input EM_WE,
input clk, input reset, input clear, input arst,
output [17:0] data_o, output src_rdy_o, input dst_rdy_i,
output reg have_space);
//states for the GPMC side of things
reg gpmc_state;
reg [ADDR_WIDTH:1] addr;
reg [PTR_WIDTH:0] gpmc_ptr, next_gpmc_ptr;
localparam GPMC_STATE_START = 0;
localparam GPMC_STATE_FILL = 1;
//states for the FIFO side of things
reg [1:0] fifo_state;
reg [ADDR_WIDTH-1:0] counter;
reg [ADDR_WIDTH-1:0] last_counter;
reg [ADDR_WIDTH-1:0] last_xfer;
reg [PTR_WIDTH:0] fifo_ptr;
localparam FIFO_STATE_CLAIM = 0;
localparam FIFO_STATE_EMPTY = 1;
localparam FIFO_STATE_PRE = 2;
//------------------------------------------------------------------
// State machine to control the data from GPMC to BRAM
//------------------------------------------------------------------
always @(negedge EM_CLK or posedge arst) begin
if (arst) begin
gpmc_state <= GPMC_STATE_START;
gpmc_ptr <= 0;
next_gpmc_ptr <= 0;
addr <= 0;
end
else if (EM_WE) begin
addr <= EM_A + 1;
case(gpmc_state)
GPMC_STATE_START: begin
if (EM_A == 0) begin
gpmc_state <= GPMC_STATE_FILL;
next_gpmc_ptr <= gpmc_ptr + 1;
end
end
GPMC_STATE_FILL: begin
if (addr == LAST_ADDR) begin
gpmc_state <= GPMC_STATE_START;
gpmc_ptr <= next_gpmc_ptr;
addr <= 0;
end
end
endcase //gpmc_state
end //EM_WE
end //always
//------------------------------------------------------------------
// A block ram is available to empty when the pointers dont match.
//------------------------------------------------------------------
wire [PTR_WIDTH:0] safe_gpmc_ptr;
cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_gpmc_ptr
(.clk(clk), .rst(reset | clear), .in(gpmc_ptr), .out(safe_gpmc_ptr));
wire bram_available_to_empty = safe_gpmc_ptr != fifo_ptr;
//------------------------------------------------------------------
// Glich free generation of have space signal:
// High when the fifo pointer has not caught up to the gpmc pointer.
//------------------------------------------------------------------
wire [PTR_WIDTH:0] safe_next_gpmc_ptr;
cross_clock_reader #(.WIDTH(PTR_WIDTH+1)) read_next_gpmc_ptr
(.clk(clk), .rst(reset | clear), .in(next_gpmc_ptr), .out(safe_next_gpmc_ptr));
wire [PTR_WIDTH:0] fifo_ptr_next = fifo_ptr + 1;
always @(posedge clk)
if (reset | clear) have_space <= 0;
else have_space <= (fifo_ptr ^ (1 << PTR_WIDTH)) != safe_next_gpmc_ptr;
//------------------------------------------------------------------
// State machine to control the data from BRAM to FIFO
//------------------------------------------------------------------
always @(posedge clk) begin
if (reset | clear) begin
fifo_state <= FIFO_STATE_CLAIM;
fifo_ptr <= 0;
counter <= 0;
end
else begin
case(fifo_state)
FIFO_STATE_CLAIM: begin
if (bram_available_to_empty && data_o[16]) fifo_state <= FIFO_STATE_PRE;
counter <= 0;
end
FIFO_STATE_PRE: begin
fifo_state <= FIFO_STATE_EMPTY;
counter <= counter + 1;
end
FIFO_STATE_EMPTY: begin
if (src_rdy_o && dst_rdy_i && data_o[17]) begin
fifo_state <= FIFO_STATE_CLAIM;
fifo_ptr <= fifo_ptr + 1;
counter <= 0;
end
else if (src_rdy_o && dst_rdy_i) begin
counter <= counter + 1;
end
end
endcase //fifo_state
end
end //always
wire enable = (fifo_state != FIFO_STATE_EMPTY) || dst_rdy_i;
assign src_rdy_o = fifo_state == FIFO_STATE_EMPTY;
//instantiate dual ported bram for async read + write
ram_2port #(.DWIDTH(16),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
(.clka(~EM_CLK),.ena(1'b1),.wea(EM_WE),
.addra({gpmc_ptr[PTR_WIDTH-1:0], addr}),.dia(EM_D),.doa(),
.clkb(clk),.enb(enable),.web(1'b0),
.addrb({fifo_ptr[PTR_WIDTH-1:0], counter}),.dib(18'h3ffff),.dob(data_o[15:0]));
//store the vita length -> last xfer count
always @(posedge clk) begin
if (src_rdy_o && dst_rdy_i && data_o[16]) begin
last_xfer <= {data_o[ADDR_WIDTH-2:0], 1'b0};
end
end
//logic for start and end of frame
always @(posedge clk) if (enable) last_counter <= counter;
assign data_o[17] = !data_o[16] && ((last_counter + 1'b1) == last_xfer);
assign data_o[16] = last_counter == 0;
endmodule // gpmc_to_fifo
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long arr[n]; for (long long i = 0; i < n; i++) cin >> arr[i]; long long p = 0; while (p < n) { if (arr[p] < p) break; p++; } --p; long long s = n - 1; while (s >= 0) { if (arr[s] < n - s - 1) break; s--; } ++s; if (s <= p || (s == p + 1 && arr[s] != arr[p])) cout << Yes ; else cout << No ; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b >> c; bool flag = 0; int by1, by2; int x, y; for (int i = 0; i <= a; i++) { x = a - i; y = i; by1 = b - x; by2 = c - y; if (by1 == by2 and by1 >= 0) { flag = 1; break; } } if (flag) cout << x << << by1 << << y << endl; else cout << Impossible << endl; }
|
#include <bits/stdc++.h> int main() { long long n; while (~scanf( %I64d , &n)) { long long m = sqrt(n); long long m1 = sqrt(m); long long i; long long sum; int flag = 0; for (i = m + 1; i >= m + 1 - 100; i--) { sum = 0; long long b = i; while (b) { sum += b % 10; b /= 10; } long long num = sum * i + i * i; if (num == n) { printf( %I64d n , i); flag = 1; break; } } if (flag == 0) { printf( -1 n ); } } }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
module altera_up_edge_detection_sobel_operator (
// Inputs
clk,
reset,
data_in,
data_en,
// Bidirectionals
// Outputs
data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter WIDTH = 640; // Image width in pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 8: 0] data_in;
input data_en;
// Bidirectionals
// Outputs
output [ 9: 0] data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 8: 0] shift_reg_out[ 1: 0];
// Internal Registers
reg [ 8: 0] original_line_1[ 2: 0];
reg [ 8: 0] original_line_2[ 2: 0];
reg [ 8: 0] original_line_3[ 2: 0];
reg [11: 0] gx_level_1[ 3: 0];
reg [11: 0] gx_level_2[ 1: 0];
reg [11: 0] gx_level_3;
reg [11: 0] gy_level_1[ 3: 0];
reg [11: 0] gy_level_2[ 1: 0];
reg [11: 0] gy_level_3;
reg [11: 0] gx_magnitude;
reg [11: 0] gy_magnitude;
reg [ 1: 0] gx_sign;
reg [ 1: 0] gy_sign;
reg [11: 0] g_magnitude;
reg gy_over_gx;
reg [ 9: 0] result;
// State Machine Registers
// Integers
integer i;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Sobel Operator
//
// [ -1 0 1 ] [ 1 2 1 ]
// Gx [ -2 0 2 ] Gy [ 0 0 0 ]
// [ -1 0 1 ] [ -1 -2 -1 ]
//
// |G| = |Gx| + |Gy|
always @(posedge clk)
begin
if (reset == 1'b1)
begin
for (i = 2; i >= 0; i = i-1)
begin
original_line_1[i] <= 9'h000;
original_line_2[i] <= 9'h000;
original_line_3[i] <= 9'h000;
end
gx_level_1[0] <= 12'h000;
gx_level_1[1] <= 12'h000;
gx_level_1[2] <= 12'h000;
gx_level_1[3] <= 12'h000;
gx_level_2[0] <= 12'h000;
gx_level_2[1] <= 12'h000;
gx_level_3 <= 12'h000;
gy_level_1[0] <= 12'h000;
gy_level_1[1] <= 12'h000;
gy_level_1[2] <= 12'h000;
gy_level_1[3] <= 12'h000;
gy_level_2[0] <= 12'h000;
gy_level_2[1] <= 12'h000;
gy_level_3 <= 12'h000;
gx_magnitude <= 12'h000;
gy_magnitude <= 12'h000;
gx_sign <= 2'h0;
gy_sign <= 2'h0;
g_magnitude <= 12'h000;
gy_over_gx <= 1'b0;
result <= 9'h000;
end
else if (data_en == 1'b1)
begin
for (i = 2; i > 0; i = i-1)
begin
original_line_1[i] <= original_line_1[i-1];
original_line_2[i] <= original_line_2[i-1];
original_line_3[i] <= original_line_3[i-1];
end
original_line_1[0] <= data_in;
original_line_2[0] <= shift_reg_out[0];
original_line_3[0] <= shift_reg_out[1];
// Calculate Gx
gx_level_1[0] <= {3'h0,original_line_1[0]} + {3'h0,original_line_3[0]};
gx_level_1[1] <= {2'h0,original_line_2[0], 1'b0};
gx_level_1[2] <= {3'h0,original_line_1[2]} + {3'h0,original_line_3[2]};
gx_level_1[3] <= {2'h0,original_line_2[2], 1'b0};
gx_level_2[0] <= gx_level_1[0] + gx_level_1[1];
gx_level_2[1] <= gx_level_1[2] + gx_level_1[3];
gx_level_3 <= gx_level_2[0] - gx_level_2[1];
// Calculate Gy
gy_level_1[0] <= {3'h0,original_line_1[0]} + {3'h0,original_line_1[2]};
gy_level_1[1] <= {2'h0,original_line_1[1], 1'b0};
gy_level_1[2] <= {3'h0,original_line_3[0]} + {3'h0,original_line_3[2]};
gy_level_1[3] <= {2'h0,original_line_3[1], 1'b0};
gy_level_2[0] <= gy_level_1[0] + gy_level_1[1];
gy_level_2[1] <= gy_level_1[2] + gy_level_1[3];
gy_level_3 <= gy_level_2[0] - gy_level_2[1];
// Calculate the magnitude and sign of Gx and Gy
gx_magnitude <= (gx_level_3[11]) ? (~gx_level_3) + 12'h001 : gx_level_3;
gy_magnitude <= (gy_level_3[11]) ? (~gy_level_3) + 12'h001 : gy_level_3;
gx_sign <= {gx_sign[0], gx_level_3[11]};
gy_sign <= {gy_sign[0], gy_level_3[11]};
// Calculate the magnitude G
g_magnitude <= gx_magnitude + gy_magnitude;
gy_over_gx <= (gx_magnitude >= gy_magnitude) ? 1'b0 : 1'b1;
// Calculate the final result
result[9] <= gx_sign[1] ^ gy_sign[1];
result[8] <= gx_sign[1] ^ gy_sign[1] ^ gy_over_gx;
result[7:0] <= (g_magnitude[11:10] == 2'h0) ? g_magnitude[9:2] : 8'hFF;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign data_out = result;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_edge_detection_data_shift_register shift_register_1 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (data_in),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[0]),
.taps ()
);
defparam
shift_register_1.DW = 9,
shift_register_1.SIZE = WIDTH;
altera_up_edge_detection_data_shift_register shift_register_2 (
// Inputs
.clock (clk),
.clken (data_en),
.shiftin (shift_reg_out[0]),
// Bidirectionals
// Outputs
.shiftout (shift_reg_out[1]),
.taps ()
);
defparam
shift_register_2.DW = 9,
shift_register_2.SIZE = WIDTH;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1123456; template <typename T> T sqr(T x) { return x * x; } template <typename T> void vout(T s) { cout << s << n ; exit(0); } long long bp(long long a, long long n) { long long res = 1; while (n) { if (n % 2) res *= a; a *= a; n >>= 1; } return res; } char akel_sosat[1001][1001]; int main() { ios_base ::sync_with_stdio(0); cin.tie(0); long long n; cin >> n; string a; cin >> a; long long kol = 0, mx = 0; for (int i = 0; i < n; i++) { if (a[i] == [ ) kol++; else kol--; mx = max(mx, kol); } long long m = mx * 2 + 3; long long l = 1, len = mx; for (int i = 1; i <= 1000; i++) for (int j = 0; j < 1001; j++) akel_sosat[i][j] = ; long long st = 0; for (int i = 0; i < n; i++, st++) { if (a[i] == [ ) { akel_sosat[l][st] = + ; akel_sosat[l][st + 1] = - ; long long l1 = len * 2 - 1; for (int j = l + 1; j <= l + l1; j++) akel_sosat[j][st] = | ; akel_sosat[l + l1 + 1][st] = + ; akel_sosat[l + l1 + 1][st + 1] = - ; len--; l++; } else { if (a[i] != a[i - 1]) st += 3; l--; len++; akel_sosat[l][st] = + ; akel_sosat[l][st - 1] = - ; long long l1 = len * 2 - 1; for (int j = l + 1; j <= l + l1; j++) akel_sosat[j][st] = | ; akel_sosat[l + l1 + 1][st] = + ; akel_sosat[l + l1 + 1][st - 1] = - ; } } for (int i = 1; i <= m; i++) { for (int j = 0; j < st; j++) cout << akel_sosat[i][j]; cout << n ; } cerr << Time execute: << clock() / (double)CLOCKS_PER_SEC << sec << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct vec { long double x, y; bool operator==(const vec &a) const { return x == a.x && y == a.y; } bool operator<(const vec &a) const { if (a.x != x) return x < a.x; return y < a.y; } vec operator+(const vec &a) const { return {x + a.x, y + a.y}; } vec operator*(const long double &a) const { return {x * a, y * a}; } vec operator-(const vec &a) const { return {x - a.x, y - a.y}; } vec operator/(const long double &a) const { return {x / a, y / a}; } long double len() const { return sqrt(x * x + y * y); } long double dot(const vec &a) const { return x * a.x + y * a.y; } long double crs(const vec &a) const { return x * a.y - y * a.x; } vec proj(const vec &a) const { return (a / a.len()) * (*this).dot(a) / a.len(); } }; struct P { int x, y; bool operator<(const P &a) const { if (x != a.x) return x > a.x; return y < a.y; } }; bool as(P a, P b) { return a.x < b.x; } long long x, y, z, mod = 1000000007; vector<int> v1, v, v2; int i, n, m, k, a, d, b, c, dx[10] = {1, 0, -1, 0}, dy[10] = {0, 1, 0, -1}; int e[511112]; int l[511155]; int o[511110]; int j[511112]; stack<int> s; queue<int> q, q1; P u[533111]; string r, r1; map<int, int> p, p1; int main() { scanf( %d %d , &a, &b); for (int t = 1; t <= a; t++) scanf( %d , &j[t]); for (int t = 1; t <= b; t++) { v.clear(); scanf( %d , &n); d = n; e[d] = 1 - e[d]; n = j[n]; if (n == 1) { c -= o[n]; if (e[d]) o[n]++; else o[n]--; c += o[n]; goto qwe; } m = n; for (int i = 2; i * i <= n; i++) { if (n % i == 0) { v.push_back(i); for (; n % i == 0; n /= i) ; } } if (n > 1) v.push_back(n); n = m; c -= o[n]; if (e[d]) o[n]++; else o[n]--; c += o[n]; for (int i = 1; i < (1 << v.size()); i++) { int k = 0, p = 1; for (int t = i, j = 0; t; j++, k += t % 2, k %= 2, t /= 2) if (t % 2) p *= v[j]; if (e[d]) { if (k) x += l[p]; else x -= l[p]; l[p]++; } else { l[p]--; if (k) x -= l[p]; else x += l[p]; } } qwe:; printf( %lld n , (long long)c * (c - 1) / 2 - x); } }
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* The output from this program should be:
* 1001
* 0100
* 0010
* 1001
* 1100
*/
module main;
reg [7:0] foo;
initial begin
foo = 8'b11001001;
$display("%b", foo[3:0]);
$display("%b", foo[4:1]);
$display("%b", foo[5:2]);
$display("%b", foo[6:3]);
$display("%b", foo[7:4]);
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.14159265358979323846; const double eps = (1e-9); int dcmp(double x, double y) { return fabs(x - y) <= eps ? 0 : x < y ? -1 : 1; } int n, m; int mem[200000]; int minMoves(int x) { if (x == m) return 0; int& ret = mem[x]; if (ret != -1) return ret; ret = (1 << 20); if (x < m) ret = min(ret, 1 + minMoves(x * 2)); if (x > 1) ret = min(ret, 1 + minMoves(x - 1)); return ret; } int main() { ios_base::sync_with_stdio(false); memset(mem, -1, sizeof(mem)); cin >> n >> m; cout << minMoves(n); return 0; }
|
// Library - static, Cell - th24w2, View - schematic
// LAST TIME SAVED: May 23 16:48:28 2014
// NETLIST TIME: May 23 16:48:54 2014
`timescale 1ns / 1ns
module th24w2 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th24w2";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N15 ( .d(net051), .g(b), .s(net038), .b(cds_globals.gnd_));
nfet_b N14 ( .d(net051), .g(d), .s(net039), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net051), .g(d), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net039), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N16 ( .d(net038), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net051), .g(c), .s(net44), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net44), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net051), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net032));
pfet_b P13 ( .b(cds_globals.vdd_), .g(y), .s(net041), .d(net051));
pfet_b P5 ( .b(cds_globals.vdd_), .g(d), .s(net032), .d(net041));
pfet_b P12 ( .b(cds_globals.vdd_), .g(c), .s(net49), .d(net032));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(net47), .d(net051));
pfet_b P3 ( .b(cds_globals.vdd_), .g(d), .s(net47), .d(net051));
pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net051);
endmodule
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#include <bits/stdc++.h> using namespace std; bool comp(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } long long gcd(long long a, long long b) { if (!b) return a; return gcd(b, a % b); } int main() { long long n, k; cin >> n >> k; long long lx[43]; if (k == 1) cout << Yes n ; else { if (k > 42ll) cout << No n ; else { lx[1] = 1; for (long long i = 2; i < 43; i++) { lx[i] = lx[i - 1] * (i / gcd(lx[i - 1], i)); } if ((n + 1) % lx[k] == 0) cout << Yes n ; else cout << No n ; } } }
|
#include <bits/stdc++.h> using namespace std; string to_string(string s) { return + s + ; } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } void test_case() { int n, l, r; cin >> n >> l >> r; vector<int> mn(n + 1); int rem = l - 1; for (int i = rem + 1; i <= n; ++i) { mn[i] = 1; } for (int i = rem, nxt = 2; i >= 1; --i, nxt *= 2) { mn[i] = nxt; } vector<int> mx(n + 1); for (int i = 1, unq = 0, nxt = 1; i <= n; ++i) { mx[i] = nxt; ++unq; if (unq < r) { nxt *= 2; } } cout << accumulate(mn.begin(), mn.end(), 0) << << accumulate(mx.begin(), mx.end(), 0) << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); test_case(); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle; initial toggle=0;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
alpha a1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
alpha a2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
tsk t1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= '0;
if (cyc==3) begin
toggle <= '1;
end
else if (cyc==5) begin
`ifdef VERILATOR
$c("call_task();");
`else
call_task();
`endif
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task call_task;
/* verilator public */
t1.center_task(1'b1);
endtask
endmodule
module alpha (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.a*",2)
// t.a1 and t.a2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't even get added
// verilator coverage_block_off
$write("");
end
end
endmodule
module beta (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
if (0) begin
// CHECK_COVER(-1,"top.v.b*",0)
// Make sure that we don't optimize away zero buckets
end
if (toggle) begin
// CHECK_COVER(-1,"top.v.b*",2)
// t.b1 and t.b2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't
// verilator coverage_block_off
$write("");
end
end
endmodule
module tsk (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
center_task(1'b0);
end
task center_task;
input external;
begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.t1",1)
end
if (external) begin
// CHECK_COVER(-1,"top.v.t1",1)
$write("[%0t] Got external pulse\n", $time);
end
end
endtask
endmodule
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
// verilator coverage_off
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// because under coverage_module_off
end
end
// verilator coverage_on
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.o1",1)
// because under coverage_module_off
end
end
endmodule
|
/*
* Copyright (c) Mercury Federal Systems, Inc., Arlington VA., 2009-2010
*
* Mercury Federal Systems, Incorporated
* 1901 South Bell Street
* Suite 402
* Arlington, Virginia 22202
* United States of America
* Telephone
* FAX
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
`default_nettype none
`ifdef OLDER
// autocreated by expandPorts.tcl 2.0 and portUtil.tcl 2.0
module wbr (
dif_Clk,
dif_m2s_MReset_n,
control_Clk,
control_m2s_MReset_n,
ctl_MCmd,
ctl_MAddrSpace,
ctl_MByteEn,
ctl_MAddr,
ctl_Mdata,
ctl_Sresp,
ctl_Sdata,
ctl_SThreadBusy,
ctl_SFlag,
ctl_MFlag,
dif_Mcmd,
dif_MreqLast,
dif_MburstPrecise,
dif_MburstLength,
dif_Mdata,
dif_MreqInfo,
dif_SThreadBusy,
chan_Mcmd,
chan_MreqLast,
chan_MburstPrecise,
chan_MburstLength,
chan_Mdata,
chan_MreqInfo,
chan_SThreadBusy );
input dif_Clk;
input dif_m2s_MReset_n;
input control_Clk;
input control_m2s_MReset_n;
// ====================
// Method = ctl_putreq
// input => ctl_req 53 OCWip::WciReq#(13)
input [ 2 : 0 ] ctl_Mcmd;
input ctl_MaddrSpace;
input [ 3 : 0 ] ctl_MbyteEn;
input [ 12 : 0 ] ctl_Maddr;
input [ 31 : 0 ] ctl_Mdata;
// ====================
// Method = ctl_resp
// result => ctl_resp 34 OCWip::WciResp
output [ 1 : 0 ] ctl_Sresp; // ctl_resp[33:32]
output [ 31 : 0 ] ctl_Sdata; // ctl_resp[31:0]
// ====================
// Method = ctl_sThreadBusy
// result => ctl_SThreadBusy 1 Bool
output ctl_SThreadBusy;
// ====================
// Method = ctl_sFlag
// result => ctl_SFlag 2 Bit#(2)
output [ 1 : 0 ] ctl_SFlag;
// ====================
// Method = ctl_mFlag
// input => ctl_MFlag 2 Bit#(2)
input [ 1 : 0 ] ctl_MFlag;
// ====================
// Method = dif_put
// input => dif_req 36 {OCWip::WsiReq#(12, 18, 0, 1, 0)}
input [ 2 : 0 ] dif_Mcmd;
input dif_MreqLast;
input dif_MburstPrecise;
input [ 11 : 0 ] dif_MburstLength;
input [ 17 : 0 ] dif_Mdata;
input dif_MreqInfo;
// ====================
// Method = dif_sThreadBusy
// result => dif_SThreadBusy 1 Bool
output dif_SThreadBusy;
// ====================
// Method = chan_get
// result => chan_req 50 {OCWip::WsiReq#(12, 32, 0, 1, 0)}
output [ 2 : 0 ] chan_Mcmd; // chan_req[49:47]
output chan_MreqLast; // chan_req[46:46]
output chan_MburstPrecise; // chan_req[45:45]
output [ 11 : 0 ] chan_MburstLength; // chan_req[44:33]
output [ 31 : 0 ] chan_Mdata; // chan_req[32:1]
output chan_MreqInfo; // chan_req[0:0]
// ====================
// Method = chan_sThreadBusy
// enable => chan_SThreadBusy 1 Bit#(1)
input chan_SThreadBusy;
wire [ 1 : 0 ] ctl_Sresp; // ctl_resp[33:32]
wire [ 31 : 0 ] ctl_Sdata; // ctl_resp[31:0]
wire ctl_SThreadBusy;
wire [ 1 : 0 ] ctl_SFlag;
wire dif_SThreadBusy;
wire [ 2 : 0 ] chan_Mcmd; // chan_req[49:47]
wire chan_MreqLast; // chan_req[46:46]
wire chan_MburstPrecise; // chan_req[45:45]
wire [ 11 : 0 ] chan_MburstLength; // chan_req[44:33]
wire [ 31 : 0 ] chan_Mdata; // chan_req[32:1]
wire chan_MreqInfo; // chan_req[0:0]
`else
`define NOT_EMPTY_wbr
`include "wbr_defs.v"
`endif
mkRcvrWorker _mkRcvrWorker (
.dif_Clk( dif_Clk ),
.dif_m2s_MReset_n( dif_MReset_n ),
.control_Clk( ctl_Clk ),
.control_m2s_MReset_n( ctl_MReset_n ),
.wci_s_req( { ctl_MCmd,ctl_MAddrSpace,ctl_MByteEn,ctl_MAddr,ctl_MData } ),
.wci_s_resp( { ctl_SResp,ctl_SData } ),
.wci_s_SThreadBusy( ctl_SThreadBusy ),
.wci_s_SFlag( ctl_SFlag ),
.wci_s_MFlag( ctl_MFlag ),
// Note we feed the lower 16 bit value from the input as the high order 16 bits of the
// underlying 18 bit input path (until we fix the input to cycle through the 16 bit values in
// each input word
.dif_req( { dif_MCmd,dif_MReqLast,dif_MBurstPrecise,dif_MBurstLength,dif_MData[15:0],2'b0,dif_MReqInfo } ),
.dif_SThreadBusy( dif_SThreadBusy ),
.chan_req( { chan_MCmd,chan_MReqLast,chan_MBurstPrecise,chan_MBurstLength,chan_MData,chan_MReqInfo } ),
.chan_SThreadBusy( chan_SThreadBusy )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_TB_V
`define SKY130_FD_SC_LP__NOR3_TB_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_TB_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ROM_Sin.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ROM_Sin (
address,
clock,
q);
input [15:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "prn5.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 50000,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 16,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "prn5.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "50000"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "prn5.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "50000"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Sin.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Sin.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Sin.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Sin.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Sin_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Sin_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Sin_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_Sin_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Fri Jul 8 09:16:27 2016
// Host : jalapeno running 64-bit unknown
// Command : write_verilog -force -mode synth_stub {/home/hhassan/git/GateKeeper/FPGA
// Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/shd_fifo_stub.v}
// Design : shd_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_0_1,Vivado 2015.4" *)
module shd_fifo(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[127:0],wr_en,rd_en,dout[127:0],full,empty" */;
input rst;
input wr_clk;
input rd_clk;
input [127:0]din;
input wr_en;
input rd_en;
output [127:0]dout;
output full;
output empty;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> using vc = vector<T>; template <class T> using vvc = vc<vc<T>>; template <class T> void mkuni(vector<T>& v) { sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); } long long rand_int(long long l, long long r) { static mt19937_64 gen(chrono::steady_clock::now().time_since_epoch().count()); return uniform_int_distribution<long long>(l, r)(gen); } template <class T> void print(T x, int suc = 1) { cout << x; if (suc == 1) cout << n ; else cout << ; } template <class T> void print(const vector<T>& v, int suc = 1) { for (int i = 0; i < v.size(); i++) print(v[i], i == (int)(v.size()) - 1 ? suc : 2); } const int INF = 0x3f3f3f3f; const int MAXN = 2e5 + 7; const int maxn = 2e6 + 7; int a[MAXN], b[MAXN]; int mx[maxn]; struct e { int u, v, w; } Edge[maxn]; bool cmp(e a, e b) { return a.w > b.w; } int fa[maxn]; int find(int x) { return (x == fa[x] ? x : fa[x] = find(fa[x])); } int main() { int n, m, cnt = 0; cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= m; ++i) cin >> b[i]; for (int i = 1; i <= n + m + 1; ++i) fa[i] = i; long long s = 0; for (int i = 1; i <= n; ++i) { int sz; cin >> sz; for (int j = 1; j <= sz; ++j) { int u; cin >> u; Edge[++cnt] = {u, i + m, a[i] + b[u]}; s += (a[i] + b[u]); } } long long sum = 0; sort(Edge + 1, Edge + cnt + 1, cmp); for (int i = 1; i <= cnt; ++i) { int u = Edge[i].u, v = Edge[i].v, w = Edge[i].w; int fu = find(u), fv = find(v); if (fu == fv) continue; fa[fu] = fv; sum += w; } cout << s - sum << endl; }
|
#include <bits/stdc++.h> using namespace std; template <typename... T> inline void inp(T &...args) { ((cin >> args), ...); } template <typename T> inline istream &operator>>(istream &in, vector<T> &a) { for (auto &x : a) in >> x; return in; } template <typename T, typename U> inline istream &operator>>(istream &in, pair<T, U> &a) { in >> a.first >> a.second; return in; } const long long int MX = 1e6 + 10; const long long int Mod = 998244353; inline long long int md(long long int x, long long int M = Mod) { x %= M; return ((x < 0) ? (x + M) : x); } vector<long long int> fact(MX), invfact(MX), inv(MX); void init_fact(long long int m = Mod) { inv[0] = 0; inv[1] = fact[0] = fact[1] = invfact[0] = invfact[1] = 1; for (long long int i = 2; i < MX; i++) { fact[i] = md(fact[i - 1] * i, m); inv[i] = m - (m / i) * inv[m % i] % m; invfact[i] = md(inv[i] * invfact[i - 1], m); } } long long int NPR(long long int n, long long int r) { if (0 <= r and r <= n) { return md(fact[n] * invfact[n - r]); } return 0; } long long int NCR(long long int n, long long int r) { if (0 <= r and r <= n) { return md(fact[n] * md(invfact[r] * invfact[n - r])); } return 0; } void solve(int &T) { long long int n, k; cin >> n >> k; vector<pair<long long int, long long int>> a; for (long long int i = (0); ((1) > 0 ? i < (n) : i > (n)); i += (1)) { long long int x, y; cin >> x >> y; a.push_back({x, 1}); a.push_back({y + 1, -1}); } sort((a).begin(), (a).end()); long long int cnt = 0, ans = 0; for (long long int i = (0); ((1) > 0 ? i < (2 * n) : i > (2 * n)); i += (1)) { if (a[i].second == 1) { if (cnt >= k - 1) { ans = md(ans + NCR(cnt, k - 1)); } cnt++; } else { cnt--; } } cout << ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); init_fact(); int t = 1; for (int i = 1; i <= t; i++) { if (0) cerr << Case # << i << n ; solve(i); } return 0; }
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
module jt51_lin2exp(
input [15:0] lin,
output reg [9:0] man,
output reg [2:0] exp
);
always @(*) begin
casez( lin[15:9] )
// negative numbers
7'b10?????: begin
man = lin[15:6];
exp = 3'd7;
end
7'b110????: begin
man = lin[14:5];
exp = 3'd6;
end
7'b1110???: begin
man = lin[13:4];
exp = 3'd5;
end
7'b11110??: begin
man = lin[12:3];
exp = 3'd4;
end
7'b111110?: begin
man = lin[11:2];
exp = 3'd3;
end
7'b1111110: begin
man = lin[10:1];
exp = 3'd2;
end
7'b1111111: begin
man = lin[ 9:0];
exp = 3'd1;
end
// positive numbers
7'b01?????: begin
man = lin[15:6];
exp = 3'd7;
end
7'b001????: begin
man = lin[14:5];
exp = 3'd6;
end
7'b0001???: begin
man = lin[13:4];
exp = 3'd5;
end
7'b00001??: begin
man = lin[12:3];
exp = 3'd4;
end
7'b000001?: begin
man = lin[11:2];
exp = 3'd3;
end
7'b0000001: begin
man = lin[10:1];
exp = 3'd2;
end
7'b0000000: begin
man = lin[ 9:0];
exp = 3'd1;
end
default: begin
man = lin[9:0];
exp = 3'd1;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__OR3B_BEHAVIORAL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or3b (
X ,
A ,
B ,
C_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
/**
* udp_dff$PS_pp$PKG$sN: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$PS_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int N, K; int hardcode[11] = {0, 1, 0, 1, 2, 0, 2, 0, 1, 0, 1}; int get_sprague_1(int val) { int tmp = val; while (tmp % 4 == 0) { tmp /= 4; } if (val <= 10) { return hardcode[val]; } else if (tmp == 6 || (val % 4 == 0 && tmp % 2 == 1 && tmp != 3)) { return 2; } else { return (val + 1) % 2; } } int get_sprague_2(int val) { if (val == 1) { return 1; } else if (val == 2) { return 2; } else { return (val + 1) % 2; } } int main() { cin.tie(0); cin.sync_with_stdio(0); cin >> N >> K; int xorv = 0; if (K % 2 == 1) { for (int a = 1; a <= N; a++) { int x; cin >> x; xorv ^= get_sprague_1(x); } } else { for (int a = 1; a <= N; a++) { int x; cin >> x; xorv ^= get_sprague_2(x); } } if (xorv == 0) { cout << Nicky ; } else { cout << Kevin ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_4_V
`define SKY130_FD_SC_LP__NOR3_4_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3_4 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3_4 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_4_V
|
#include <bits/stdc++.h> using namespace std; int n; int main() { ios_base::sync_with_stdio(false); int n, x[10], y[10], nx[10], ny[10]; cin >> n; for (int i = 0; i < n; i++) cin >> x[i] >> y[i] >> nx[i] >> ny[i]; int mnx = 1000000, mny = 1000000, mxx = 0, mxy = 0; for (int i = 0; i < n; i++) { mnx = min(mnx, x[i]); mny = min(mny, y[i]); mxx = max(mxx, nx[i]); mxy = max(mxy, ny[i]); } long long area = (mxx - mnx) * (mxy - mny); long long realarea = 0; for (int i = 0; i < n; i++) { realarea += (nx[i] - x[i]) * (ny[i] - y[i]); } if (mxx - mnx == mxy - mny && area == realarea) printf( YES ); else printf( NO ); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_1_V
`define SKY130_FD_SC_LS__AND2_1_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_1_V
|
#include <bits/stdc++.h> using namespace std; class sparse_table { vector<int> values; vector<int> maxk; vector<vector<int> > st; void build(const vector<int>& a) { values = a; int n = a.size(); st.resize(maxk[n] + 1); st[0].resize(n); for (int i = 0; i < n; i++) st[0][i] = i; for (int i = 1; i <= maxk[n]; i++) { st[i].resize(n - (1 << i) + 1); for (int j = 0; j < (int)st[i].size(); j++) { if (values[st[i - 1][j]] < values[st[i - 1][j + (1 << (i - 1))]]) st[i][j] = st[i - 1][j]; else st[i][j] = st[i - 1][j + (1 << (i - 1))]; } } } public: sparse_table(const vector<int>& vec) { int n = vec.size(); maxk.resize(n + 1, 0); for (int i = 2; i < n + 1; i++) maxk[i] = maxk[i / 2] + 1; build(vec); } sparse_table() {} int get(int l, int r) { if (values[st[maxk[r - l]][l]] < values[st[maxk[r - l]][r - (1 << maxk[r - l])]]) return st[maxk[r - l]][l]; else return st[maxk[r - l]][r - (1 << maxk[r - l])]; } }; int n; vector<vector<int> > graph; vector<int> vec; vector<int> height; vector<int> first; vector<int> tin, tout, parent; int cur_time = 0; void dfs(int u, int par, int hg) { height[u] = hg; vec.push_back(u); first[u] = vec.size() - 1; tin[u] = cur_time++; parent[u] = par; for (int v : graph[u]) if (v != par) { vec.push_back(u); dfs(v, u, hg + 1); } tout[u] = cur_time++; } sparse_table st; void precalc_lca() { vec.clear(); height.clear(); first.clear(); height.resize(n); first.resize(n); tin.resize(n); tout.resize(n); parent.resize(n); dfs(0, -1, 0); vector<int> to_st(vec.size()); for (int i = 0; i < (int)vec.size(); i++) to_st[i] = height[vec[i]]; st = sparse_table(to_st); } int lca(int u, int v) { int a = min(first[u], first[v]); int b = max(first[u], first[v]); return vec[st.get(a, b + 1)]; } int dist(int u, int v) { return height[u] + height[v] - 2 * height[lca(u, v)]; } bool is_child(int u, int v) { return tin[u] <= tin[v] && tout[v] <= tout[u]; } int c1 = 0, c2 = 0, x = 0; int add_vertex(int v) { if (c1 == c2) { if (dist(c1, v) == x + 1) { x++; if (is_child(c1, v)) { auto it = upper_bound( graph[c1].begin(), graph[c1].end(), v, [](const int& i, const int& j) -> bool { return tin[i] < tin[j]; }); assert(it != graph[c1].begin()); it--; c2 = *it; } else { c2 = parent[c1]; } } } else { if (dist(c1, v) == x + 1) { c1 = c2; } else if (dist(c2, v) == x + 1) { c2 = c1; } } if (c1 == c2) { return 2 * x; } else { return 2 * x - 1; } } int main() { cin >> n; graph.resize(n); for (int i = 1; i < n; i++) { int a; cin >> a; a--; graph[a].push_back(i); graph[i].push_back(a); } precalc_lca(); for (int i = 1; i < n; i++) { cout << add_vertex(i) << ; } cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_BLACKBOX_V
`define SKY130_FD_SC_MS__OR2_BLACKBOX_V
/**
* or2: 2-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n; bool ison[100010]; char temp[100]; int q, t; int isprime[100010]; int prime[100010]; vector<int> pr[100010]; void preprocess() { fill(isprime, isprime + 100010, 0); fill(ison, ison + 100010, false); fill(prime, prime + 100010, -1); for (int i = 2; i < 100010; i++) { if (isprime[i]) { continue; } pr[i].push_back(i); for (int j = i + i; j < 100010; j += i) { pr[j].push_back(i); isprime[j] = i; } } } void solve1(int a) { if (ison[a]) { printf( Already on n ); return; } int len = pr[a].size(); int i; for (i = 0; i < len; i++) { int val = pr[a][i]; if (prime[val] == -1) { continue; } else { printf( Conflict with %d n , prime[val]); return; } } for (i = 0; i < len; i++) { int val = pr[a][i]; prime[val] = a; } ison[a] = true; printf( Success n ); } void solve2(int b) { if (!ison[b]) { printf( Already off n ); return; } int len = pr[b].size(); int i, val; for (i = 0; i < len; i++) { val = pr[b][i]; prime[val] = -1; } ison[b] = false; printf( Success n ); } int main() { scanf( %d%d , &n, &q); preprocess(); for (int i = 0; i < q; i++) { scanf( %s , temp); scanf( %d , &t); if (temp[0] == + ) { solve1(t); } else { solve2(t); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-6; const double pi = acos(-1); int sign(double k) { if (k > eps) return 1; else if (k < -eps) return -1; return 0; } int cmp(double k1, double k2) { return sign(k1 - k2); } int inmid(double k1, double k2, double k3) { return sign(k1 - k3) * sign(k2 - k3) <= 0; } struct point { double x, y; point operator+(const point &k1) const { return (point){k1.x + x, k1.y + y}; } point operator-(const point &k1) const { return (point){x - k1.x, x - k1.y}; } point operator*(double &k1) const { return (point){x * k1, y * k1}; } point operator/(double &k1) const { return (point){x / k1, y / k1}; } int operator==(const point &k1) const { return cmp(x, k1.x) == 0 && cmp(y, k1.y) == 0; } double abs() { return sqrt(x * x + y * y); } double abs2() { return x * x + y * y; } double dis(point k1) { return ((*this) - k1).abs(); } }; struct osc { double ang; int v; }; bool osccmp(osc a, osc b) { int res = cmp(a.ang, b.ang); if (res == -1) return 1; if (res == 0 && a.v > b.v) return 1; return 0; } int n, K; int sz; osc angle[400050]; point a[100050]; bool check(double R) { sz = 0; int now = 0; for (int i = 1; i <= n; i++) { double d = a[i].abs() / 2; if (cmp(d, R) == 1) continue; double t = atan2(a[i].y, a[i].x); if (t < 0) t += 2 * pi; double dt = acos(d / R); double f = t - dt, s = t + dt; if (cmp(f, 0.0) == -1) f += 2 * pi; if (cmp(s, 2 * pi) == 1) s -= 2 * pi; if (cmp(f, s) == 1 || cmp(f, 0.0) == 0) now++; angle[++sz] = (osc){f, 1}; angle[++sz] = (osc){s, -1}; } sort(angle + 1, angle + sz + 1, osccmp); for (int i = 1; i <= sz; i++) { now += angle[i].v; if (now >= K) return 1; } return 0; } int main() { ios_base::sync_with_stdio(false); cin >> n >> K; for (int i = 1; i <= n; i++) { int x, y; cin >> x >> y; if (x == 0 && y == 0) { K--; i--; n--; continue; } a[i] = (point){(double)x, (double)y}; } if (K <= 0) { cout << fixed << setprecision(10) << 0.0 << n ; return 0; } double l = 0, r = 200000; for (int round = 1; round <= 100; round++) { double mid = (l + r) / 2; if (check(mid)) r = mid; else l = mid; } cout << fixed << setprecision(10) << l << n ; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Power Management ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PM according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// - add support for dynamic clock gating ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_pm.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_pm(
// RISC Internal Interface
clk, rst, pic_wakeup, spr_write, spr_addr, spr_dat_i, spr_dat_o,
// Power Management Interface
pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input pic_wakeup; // Wakeup from the PIC
input spr_write; // SPR Read/Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
//
// Power Management Interface
//
input pm_cpustall; // Stall the CPU
output [3:0] pm_clksd; // Clock Slowdown factor
output pm_dc_gate; // Gate DCache clock
output pm_ic_gate; // Gate ICache clock
output pm_dmmu_gate; // Gate DMMU clock
output pm_immu_gate; // Gate IMMU clock
output pm_tt_gate; // Gate Tick Timer clock
output pm_cpu_gate; // Gate main RISC/CPU clock
output pm_wakeup; // Activate (de-gate) all clocks
output pm_lvolt; // Lower operating voltage
`ifdef OR1200_PM_IMPLEMENTED
//
// Power Management Register bits
//
reg [3:0] sdf; // Slow-down factor
reg dme; // Doze Mode Enable
reg sme; // Sleep Mode Enable
reg dcge; // Dynamic Clock Gating Enable
//
// Internal wires
//
wire pmr_sel; // PMR select
//
// PMR address decoder (partial decoder)
//
`ifdef OR1200_PM_PARTIAL_DECODING
assign pmr_sel = (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) ? 1'b1 : 1'b0;
`else
assign pmr_sel = ((spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) &&
(spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_PM_OFS_PMR)) ? 1'b1 : 1'b0;
`endif
//
// Write to PMR and also PMR[DME]/PMR[SME] reset when
// pic_wakeup is asserted
//
always @(posedge clk or posedge rst)
if (rst)
{dcge, sme, dme, sdf} <= 7'b0;
else if (pmr_sel && spr_write) begin
sdf <= #1 spr_dat_i[`OR1200_PM_PMR_SDF];
dme <= #1 spr_dat_i[`OR1200_PM_PMR_DME];
sme <= #1 spr_dat_i[`OR1200_PM_PMR_SME];
dcge <= #1 spr_dat_i[`OR1200_PM_PMR_DCGE];
end
else if (pic_wakeup) begin
dme <= #1 1'b0;
sme <= #1 1'b0;
end
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = sdf;
assign spr_dat_o[`OR1200_PM_PMR_DME] = dme;
assign spr_dat_o[`OR1200_PM_PMR_SME] = sme;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = dcge;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
//
// Generate pm_clksd
//
assign pm_clksd = sdf;
//
// Statically generate all clock gate outputs
// TODO: add dynamic clock gating feature
//
assign pm_cpu_gate = (dme | sme) & ~pic_wakeup;
assign pm_dc_gate = pm_cpu_gate;
assign pm_ic_gate = pm_cpu_gate;
assign pm_dmmu_gate = pm_cpu_gate;
assign pm_immu_gate = pm_cpu_gate;
assign pm_tt_gate = sme & ~pic_wakeup;
//
// Assert pm_wakeup when pic_wakeup is asserted
//
assign pm_wakeup = pic_wakeup;
//
// Assert pm_lvolt when pm_cpu_gate or pm_cpustall are asserted
//
assign pm_lvolt = pm_cpu_gate | pm_cpustall;
`else
//
// When PM is not implemented, drive all outputs as would when PM is disabled
//
assign pm_clksd = 4'b0;
assign pm_cpu_gate = 1'b0;
assign pm_dc_gate = 1'b0;
assign pm_ic_gate = 1'b0;
assign pm_dmmu_gate = 1'b0;
assign pm_immu_gate = 1'b0;
assign pm_tt_gate = 1'b0;
assign pm_wakeup = 1'b1;
assign pm_lvolt = 1'b0;
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = 4'b0;
assign spr_dat_o[`OR1200_PM_PMR_DME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_SME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = 1'b0;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
`endif
endmodule
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#include <bits/stdc++.h> using namespace std; using namespace std; int k; string ad; vector<string> c(string s) { vector<string> ans; int last = 0; for (long long i = 0; i < (s.size()); i++) { if (s[i] == || s[i] == - || i == s.size() - 1) { ans.push_back(s.substr(last, i - last + 1)); last = i + 1; } } return ans; } vector<string> v; bool check(int mid) { int nlen = 0; int cnt = 1; for (long long i = 0; i < (v.size()); i++) { if (v[i].size() > mid) { return false; } if (nlen + v[i].size() <= mid) { nlen += v[i].size(); } else { nlen = v[i].size(); cnt++; } } if (cnt <= k) { return true; } return false; } int main() { cin >> k; cin.ignore(); getline(cin, ad, n ); v = c(ad); int l = 0, r = ad.size(); while (l < r) { int mid = (l + r) >> 1; if (!check(mid)) { l = mid + 1; } else { r = mid; } } cout << r; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21A_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O21A_PP_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21A_PP_BLACKBOX_V
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`include "defines.v"
/****
* Compares 4 input ports based on their age and source
* and outputs 4 priorities. The priorities contain the
* port number that is that priority with p0 being the
* highest and p3 being the lowest. Compares based on age
* with highest more priority and then based on source
* in the case of a tie.
****/
module priority_comparator(
input `control_w control0,
input `control_w control1,
input `control_w control2,
input `control_w control3,
output [1:0] priority0,
output [1:0] priority1,
output [1:0] priority2,
output [1:0] priority3);
wire `age_w ha00, ha01, ha10, ha11, ha20;
wire `src_w hs00, hs01, hs10, hs11, hs20;
wire `age_w la00, la01, la10, la11, la20;
wire `src_w ls00, ls01, ls10, ls11, ls20;
wire [1:0] hp00, hp01, hp10, hp11, hp20;
wire [1:0] lp00, lp01, lp10, lp11, lp20;
wire hv00, hv01, hv10, hv11, hv20;
wire lv00, lv01, lv10, lv11, lv20;
// Stage 0
pc_cell cmp00(.age0(control0[`age_f]),
.age1(control1[`age_f]),
.src0(control0[`src_f]),
.src1(control1[`src_f]),
.valid0(control0[`valid_f]),
.valid1(control1[`valid_f]),
.portno0(2'b00),
.portno1(2'b01),
.age_h(ha00),
.age_l(la00),
.src_h(hs00),
.src_l(ls00),
.valid_h(hv00),
.valid_l(lv00),
.portno_h(hp00),
.portno_l(lp00));
pc_cell cmp01(.age0(control2[`age_f]),
.age1(control3[`age_f]),
.src0(control2[`src_f]),
.src1(control3[`src_f]),
.valid0(control2[`valid_f]),
.valid1(control3[`valid_f]),
.portno0(2'b10),
.portno1(2'b11),
.age_h(ha01),
.age_l(la01),
.src_h(hs01),
.src_l(ls01),
.valid_h(hv01),
.valid_l(lv01),
.portno_h(hp01),
.portno_l(lp01));
// Stage 1
pc_cell cmp10(.age0(ha00),
.age1(ha01),
.src0(hs00),
.src1(hs01),
.valid0(hv00),
.valid1(hv01),
.portno0(hp00),
.portno1(hp01),
.age_h(ha10),
.age_l(la10),
.src_h(hs10),
.src_l(ls10),
.valid_h(hv10),
.valid_l(lv10),
.portno_h(priority0),
.portno_l(lp10));
pc_cell cmp11(.age0(la00),
.age1(la01),
.src0(ls00),
.src1(ls01),
.valid0(lv00),
.valid1(lv01),
.portno0(lp00),
.portno1(lp01),
.age_h(ha11),
.age_l(la11),
.src_h(hs11),
.src_l(ls11),
.valid_h(hv11),
.valid_l(lv11),
.portno_h(hp11),
.portno_l(priority3));
// Stage 2
pc_cell cmp20(.age0(la10),
.age1(ha11),
.src0(ls10),
.src1(hs11),
.valid0(lv10),
.valid1(hv11),
.portno0(lp10),
.portno1(hp11),
.age_h(ha20),
.age_l(la20),
.src_h(hs20),
.src_l(ls20),
.valid_h(hv20),
.valid_l(lv20),
.portno_h(priority1),
.portno_l(priority2));
endmodule
/****
* @brief This is a small cell to compare two incoming requests
* and discern which one has higher priority first based
* on age and then based on the source destination.
* We do oldest first and in the case of a tie we do
* highest source node address.
* The entire module is combinational
*
****/
module pc_cell (
input `age_w age0,
input `age_w age1,
input `src_w src0,
input `src_w src1,
input valid0,
input valid1,
input [1:0] portno0,
input [1:0] portno1,
output `age_w age_h,
output `age_w age_l,
output `src_w src_h,
output `src_w src_l,
output valid_h,
output valid_l,
output [1:0] portno_h,
output [1:0] portno_l);
wire winner;
assign winner = (valid0 && ~valid1) ? 1'b0 :
(~valid0 && valid1) ? 1'b1 :
(~valid0 && ~valid1) ? 1'b1 :
(age0 > age1) ? 1'b0 :
(age0 < age1) ? 1'b1 :
(src0 > src1) ? 1'b0 :
(src0 < src1) ? 1'b1 : 1'b1;
assign portno_h = (winner == 1'b1) ? portno1 : portno0;
assign portno_l = (winner == 1'b1) ? portno0 : portno1;
assign valid_h = (winner == 1'b1) ? valid1 : valid0;
assign valid_l = (winner == 1'b1) ? valid0: valid1;
assign age_h = (winner == 1'b1) ? age1 : age0;
assign age_l = (winner == 1'b1) ? age0 : age1;
assign src_h = (winner == 1'b1) ? src1 : src0;
assign src_l = (winner == 1'b1) ? src0 : src1;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long n, k; cin >> n >> k; long long n1 = n - (k - 1); if (n1 > 0 && n1 % 2 == 1) { cout << YES n ; for (long long i = 0; i < k - 1; i++) cout << 1 ; cout << n1 << n ; continue; } long long n2 = n - 2 * (k - 1); if (n2 > 0 && n2 % 2 == 0) { cout << YES n ; for (long long i = 0; i < k - 1; i++) cout << 2 ; cout << n2 << n ; continue; } cout << NO n ; } }
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#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; long long v[n + 10]; for (long long i = 0; i < n; i++) { cin >> v[i]; } sort(v, v + n); k--; long long div = k / n; long long cnt = 0; long long val = v[div]; for (long long i = 0; i < n; i++) { if (v[i] == val) cnt++; if (v[i] < val) k = k - n; } long long amt = cnt; long long now = k / amt; cout << val << << v[now] << endl; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAP_12_V
`define SKY130_FD_SC_LP__DECAP_12_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 12 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decap_12 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decap_12 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAP_12_V
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#include <bits/stdc++.h> using namespace std; const long long inf = (1LL << 60) - 1; int dx[] = {-1, 1, 0, 0}; int dy[] = {0, 0, -1, 1}; void solve() { long long n, x, y, k, c = 0; cin >> n >> x >> y; for (long long i = 0; i < n; i++) { cin >> k; if (k <= x) c++; } if (x > y) cout << n << n ; else cout << (c + 1) / 2 << n ; } int main() { ios::sync_with_stdio(0); cout.tie(0); ; solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const long long MOD = 1e9 + 7; const int N = 1e6; int T, n, r, A[1005]; void solve() { cin >> n >> r; for (int i = 1; i <= n; i++) { cin >> A[i]; } int ans = 0; int z; for (int i = 1; i <= n; i = z + r) { bool can_warm = false; z = -1; int left = max(i - r + 1, 0), right = min(i + r, n + 1); for (int j = left; j < right; j++) { if (A[j]) { can_warm = true; z = j; } } if (!can_warm) { cout << -1; return; } ans++; } cout << ans; } int(main)() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); T = 1; while (T--) { solve(); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_BLACKBOX_V
`define SKY130_FD_SC_LP__A311OI_BLACKBOX_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a311oi (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:128777216 ) const int null = 0; using namespace std; template <class T> int size(const T &a) { return int(a.size()); } template <class T> T abs(const T &a) { return (a < 0 ? -a : a); } template <class T> T sqr(const T &a) { return a * a; } const int max_n = 52, mod = 1000000007; int dist[max_n][max_n][2]; int dp[max_n][max_n][2]; bool was[max_n][max_n][2]; struct Pos { int i, j, s; int d; void init(int i, int j, int s, int d) { this->i = i; this->j = j; this->s = s; this->d = d; was[i][j][s] = true; dist[i][j][s] = d; } } q[max_n * max_n * 2]; int cmn[max_n][max_n]; int main() { int n, k; scanf( %d %d , &n, &k); for (int i = 0; i <= n; i++) { cmn[0][i] = 1; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { cmn[i][j] = cmn[i - 1][j - 1] + cmn[i][j - 1]; } } k /= 50; int c0 = 0, c1 = 0; for (int i = 0; i < n; i++) { int t; scanf( %d , &t); if (t == 50) { c0++; } else { c1++; } } q[0].init(0, 0, 1, 0); dp[0][0][1] = 1; for (int d = 0, u = 1; d < u; d++) { Pos p = q[d]; int mc0, mc1; if (p.s) { mc0 = c0 - p.i; mc1 = c1 - p.j; } else { mc0 = p.i; mc1 = p.j; } long long cnt = dp[p.i][p.j][p.s]; for (int i = 0; i <= mc0; i++) { for (int j = 0; j <= mc1; j++) { if (i + j > 0 && i + j * 2 <= k) { int c0, c1, s0 = p.s ^ 1; if (p.s) { c0 = p.i + i; c1 = p.j + j; } else { c0 = p.i - i; c1 = p.j - j; } long long cur = cnt * cmn[i][mc0] % mod * cmn[j][mc1] % mod; if (!was[c0][c1][s0]) { q[u++].init(c0, c1, s0, p.d + 1); dp[c0][c1][s0] = cur; } else if (p.d + 1 == dist[c0][c1][s0]) { dp[c0][c1][s0] = (cur + dp[c0][c1][s0]) % mod; } } } } } if (!was[c0][c1][0]) { printf( -1 n0 n ); return 0; } printf( %d n%d n , dist[c0][c1][0], dp[c0][c1][0]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; const long double E = 1e-7; unsigned char ccc; bool _minus = false; template <typename T> inline T sqr(T t) { return (t * t); } inline void read(long long &n) { n = 0; _minus = false; while (true) { ccc = getchar(); if (ccc == || ccc == n ) break; if (ccc == - ) { _minus = true; continue; } n = n * 10 + ccc - 0 ; } if (_minus) n *= -1; } inline void read(int &n) { n = 0; _minus = false; while (true) { ccc = getchar(); if (ccc == || ccc == n ) break; if (ccc == - ) { _minus = true; continue; } n = n * 10 + ccc - 0 ; } if (_minus) n *= -1; } char wwww[19]; int kkkk; inline void write(long long y) { long long x = y; kkkk = 0; if (!x) ++kkkk, wwww[kkkk] = 0 ; else while (x) { ++kkkk; wwww[kkkk] = char(x % 10 + 0 ); x /= 10; } for (int i = kkkk; i >= 1; --i) putchar(wwww[i]); putchar( ); } long long d, k, a, b, t; long long get(long long x) { long long ans = max(0LL, x - 1) * t + x * k * a + (d - x * k) * b; return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; srand(time(NULL)); cout.precision(10); cout << fixed; cin >> d >> k >> a >> b >> t; long long ans = ((d - 1) / k) * t + d * a; long long l = 0, r = d / k; while (l + 10 < r) { long long l1 = (l + l + r) / 3, r1 = (l + r + r) / 3; if (get(l1) < get(r1)) { r = r1; } else { l = l1; } } for (long long i = l; i <= r; i++) ans = min(ans, get(i)); cout << ans << n ; }
|
#include <bits/stdc++.h> bool fun(long long a); using namespace std; int main() { long long num, num1, num2; cin >> num; if (num % 2 == 0) { num1 = num / 2; num2 = num / 2; while (!fun(num1) || !fun(num2)) { num1 -= 1; num2 += 1; } } else { num1 = num / 2; num2 = num / 2 + 1; while (!fun(num1) || !fun(num2)) { num1 -= 1; num2 += 1; } } cout << num1 << << num2; } bool fun(long long a) { int c = 0; for (int i = 2; i < a; i++) { if (a % i == 0) { c = 1; break; } } return c == 1; }
|
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7; int base[2] = {31, 33}; int pw[2][1000005], a[2][1000005]; char s[1000005]; int n, ans[1000005]; bool func(int x, int y, int xx, int yy) { for (int i = 0; i <= 1; i++) { if (((a[i][y] - 1ll * a[i][x - 1] * pw[i][y - x + 1]) % mod + mod) % mod != ((a[i][yy] - 1ll * a[i][xx - 1] * pw[i][yy - xx + 1]) % mod + mod) % mod) return 0; } return 1; } int main() { scanf( %d %s , &n, s + 1); for (int i = 0; i <= 1; i++) { pw[i][0] = 1; for (int j = 1; j < 1000005; j++) pw[i][j] = 1ll * pw[i][j - 1] * base[i] % mod; for (int j = 1; j <= n; j++) a[i][j] = (1ll * a[i][j - 1] * base[i] + s[j] - a ) % mod; } int l, r; int up = (n + 1) / 2; ans[up + 1] = -1; for (int k = up; k; k--) { l = k, r = n - k + 1; ans[k] = ans[k + 1] + 2; while (ans[k] >= r - l + 1) ans[k] -= 2; while (ans[k] > 0) { if (func(l, l + ans[k] - 1, r - ans[k] + 1, r)) break; ans[k] -= 2; } } for (int i = 1; i <= up; i++) printf( %d , ans[i]); }
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#include <bits/stdc++.h> const long long mod = 1000000007; using namespace std; int main() { long long ax, ay, bx, by, tx, ty; scanf( %I64d , &(ax)); scanf( %I64d , &(ay)); scanf( %I64d , &(bx)); scanf( %I64d , &(by)); scanf( %I64d , &(tx)); scanf( %I64d , &(ty)); long long n; scanf( %I64d , &(n)); vector<pair<long long, long long>> bot(n); vector<double> toT(n); vector<pair<double, int>> toA(n), toB(n); double sum = 0; for (int(i) = 0; (i) < n; (i)++) { scanf( %I64d , &(bot[i].first)); scanf( %I64d , &(bot[i].second)); toT[i] = sqrt((double)((bot[i].first - tx) * (bot[i].first - tx) + (bot[i].second - ty) * (bot[i].second - ty))); sum += 2 * toT[i]; toA[i].first = sqrt((double)((bot[i].first - ax) * (bot[i].first - ax) + (bot[i].second - ay) * (bot[i].second - ay))); toA[i].first -= toT[i]; toA[i].second = i; toB[i].first = sqrt((double)((bot[i].first - bx) * (bot[i].first - bx) + (bot[i].second - by) * (bot[i].second - by))); toB[i].first -= toT[i]; toB[i].second = i; } sort((toA).begin(), (toA).end()); sort((toB).begin(), (toB).end()); double ans = 1e18; for (int i = 0; i < n; i++) { int j = toA[i].second; int k = toB[0].second; double tmp = sum + toA[i].first; ans = min(ans, tmp); tmp = sum + toB[i].first; ans = min(ans, tmp); if (j != k) tmp = sum + toA[i].first + toB[0].first; else tmp = sum + toA[i].first + toB[1].first; j = toB[i].second; ans = min(ans, tmp); k = toA[0].second; if (j != k) tmp = sum + toA[0].first + toB[i].first; else tmp = sum + toA[1].first + toB[i].first; ans = min(ans, tmp); } printf( %.10f , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long t, i, j, k, l, m, n, p, q, r, s = 0, a, b, c, d, ans = 0, x, y; cin >> n >> k; string s1; cin >> s1; for (i = 0; i < n; i++) { if (s1[i] == G ) { p = i; } else if (s1[i] == T ) { q = i; } } if (abs(p - q) % k != 0) { cout << NO n ; return 0; } a = min(p, q); b = max(p, q); for (i = a; i <= b; i += k) { if (s1[i] == # ) { cout << NO n ; return 0; } } cout << YES n ; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; int n, m; unsigned long long A, B, C; struct E { int u, v; E(int u, int v) : u(u), v(v) {} }; struct Graph { int n, m, deg[maxn], cur[maxn]; unsigned long long hash_[maxn]; vector<E> edge; vector<int> small[maxn], large[maxn]; vector<int> G[maxn]; void init(int n) { this->n = n, m = 0; edge.clear(); for (int i = 0; i < n; ++i) { small[i].clear(); large[i].clear(); G[i].clear(); } } void add_edge(int u, int v) { if (u > v) swap(u, v); edge.push_back(E(u, v)); G[u].push_back(v); G[v].push_back(u); small[v].push_back(u); large[u].push_back(v); hash_[m++] = (unsigned long long)u * n + v; } unsigned long long sum0() { unsigned long long s = 0; for (int i = 0; i < n; ++i) { s += A * i * ((unsigned long long)(n - 1 - i) * (n - 2 - i) / 2); s += B * i * i * (n - 1 - i); s += C * i * ((unsigned long long)i * (i - 1) / 2); } return s; } unsigned long long sum1() { unsigned long long s = 0; for (E e : edge) { int u = e.u, v = e.v; s += A * ((unsigned long long)u * (u - 1) / 2) + B * u * u + C * v * u; s += A * u * (v - u - 1) + B * ((unsigned long long)(u + v) * (v - u - 1) / 2) + C * v * (v - u - 1); s += A * u * (n - 1 - v) + B * v * (n - 1 - v) + C * ((unsigned long long)(n + v) * (n - 1 - v) / 2); } return s; } unsigned long long sum2() { for (int i = 0; i < n; ++i) { sort(small[i].begin(), small[i].end()); sort(large[i].begin(), large[i].end()); } unsigned long long s = 0; for (int i = 0; i < n; ++i) { unsigned long long scnt = small[i].size(); unsigned long long lcnt = large[i].size(); s += A * i * ((unsigned long long)lcnt * (lcnt - 1) / 2); for (int j = 0; j < lcnt; ++j) s += large[i][j] * (B * (lcnt - 1 - j) + C * j); s += B * i * scnt * lcnt; for (int j = 0; j < scnt; ++j) s += small[i][j] * A * lcnt; for (int j = 0; j < lcnt; ++j) s += large[i][j] * C * scnt; s += C * i * ((unsigned long long)scnt * (scnt - 1) / 2); for (int j = 0; j < scnt; ++j) s += small[i][j] * (A * (scnt - 1 - j) + B * j); } return s; } unsigned long long sum3() { sort(hash_, hash_ + m); hash_[m] = -1; for (int i = 0; i < n; ++i) deg[i] = G[i].size(); unsigned long long s = 0; for (int i = 0; i < n; ++i) { int sz = 0; for (int v : G[i]) if (deg[v] > deg[i] || (deg[v] == deg[i] && v > i)) cur[sz++] = v; sort(cur, cur + sz); int l = 0; for (int j = 0; j < sz; ++j) for (int k = j + 1; k < sz; ++k) { int u = cur[j], v = cur[k]; unsigned long long hash = (unsigned long long)u * n + v; int pos = lower_bound(hash_ + l, hash_ + m, hash) - hash_; l = pos; if (hash_[pos] == hash) s += fun(i, u, v); } } return s; } unsigned long long sum() { return sum0() - sum1() + sum2() - sum3(); } unsigned long long fun(int a, int b, int c) { int mx = max(a, c); int mn = min(a, b); return B * (a + b + c) + (A - B) * mn + (C - B) * mx; } } graph; int main(void) { while (~scanf( %d%d , &n, &m)) { scanf( %llu%llu%llu , &A, &B, &C); graph.init(n); for (int i = 0; i < m; ++i) { int u, v; scanf( %d%d , &u, &v); graph.add_edge(u, v); } printf( %llu n , graph.sum()); } return 0; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:02:05 12/03/2016
// Design Name:
// Module Name: animation
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module animationV(clk, rst, height, ram_address, ram_data, mode, on_off);
input clk, rst, mode, on_off; //0 is home mode; 1 is party mode
input [8:0] ram_address;
output reg [47:0] ram_data;
reg [23:0] top, bottom;
input[3:0] height;
reg [4:0] inner_height;
reg [23:0] color;
reg addsub;
//parameter height = 9;
initial begin
top<=0;
bottom<=0;
ram_data <=0;
inner_height<=0;
color<=0;
addsub<=0;
end
//Top half of panel is controlled by last 24 bits of ram_data
always @ (posedge clk) begin
if ( mode == 1'b1) begin
if (ram_address == 0) begin
color<= color+1'b1;
inner_height<={0,height};
end
bottom <= {24{1'b0}};
top <= {24{1'b0}};
if (ram_address > 512 - 1 - $unsigned(inner_height)* 32 ) begin
top <= color;
//bottom <= {24{1'b0}};
end
if (ram_address < $unsigned(inner_height) * 32) begin
//top <= {24{1'b0}};
bottom <= color;
end
ram_data <= {bottom, top};
end
else begin
if (on_off == 1'b1) begin
ram_data <= {8'd179, 8'd255, 8'd255, 8'd179, 8'd255, 8'd255};
end
else begin
ram_data <= 48'b0;
end
end
end
endmodule
|
module xillyvga_core
(
input S_AXI_ACLK,
input [31:0] S_AXI_ARADDR,
input S_AXI_ARESETN,
input S_AXI_ARVALID,
input [31:0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input S_AXI_BREADY,
input S_AXI_RREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
input clk_in,
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_arready,
input m_axi_awready,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
input [31:0] m_axi_rdata,
input m_axi_rlast,
input [1:0] m_axi_rresp,
input m_axi_rvalid,
input m_axi_wready,
output S_AXI_ARREADY,
output S_AXI_AWREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [31:0] m_axi_araddr,
output [1:0] m_axi_arburst,
output [3:0] m_axi_arcache,
output [3:0] m_axi_arlen,
output [2:0] m_axi_arprot,
output [2:0] m_axi_arsize,
output m_axi_arvalid,
output [31:0] m_axi_awaddr,
output [1:0] m_axi_awburst,
output [3:0] m_axi_awcache,
output [3:0] m_axi_awlen,
output [2:0] m_axi_awprot,
output [2:0] m_axi_awsize,
output m_axi_awvalid,
output m_axi_bready,
output m_axi_rready,
output [31:0] m_axi_wdata,
output m_axi_wlast,
output [3:0] m_axi_wstrb,
output m_axi_wvalid,
output vga_clk,
output [7:0] vga_blue,
output [7:0] vga_green,
output vga_hsync,
output [7:0] vga_red,
output vga_de,
output vga_vsync
);
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Inspired by the post by Ulf Samuelsson
* http://www.velocityreviews.com/forums/t25846-p4-how-to-count-zeros-in-registers.html
*
* The idea is to use a divide-and-conquer approach to process a 2^N bit number.
* We split the number in two equal halves of 2^(N-1) bits :
* MMMMLLLL
* then, we check if MMMM is all 0's.
* If it is,
* then the number of leading zeros is 2^(N-1) + CLZ(LLLL)
* If it is not,
* then the number of leading zeros is CLZ(MMMM)
* Recursion stops with CLZ(0)=1 and CLZ(1)=0.
*
* If the input is not all zeros, we never propagate a carry and
* the additions can be replaced by OR's,
* giving the result bit per bit.
*
* In this implementation, we assume that d[0] = 1, yielding the result 31
* when the input is actually all 0's.
*/
module pfpu_clz32(
input [31:0] d,
output [4:0] clz
);
assign clz[4] = d[31:16] == 16'd0;
wire [15:0] d1 = clz[4] ? d[15:0] : d[31:16];
assign clz[3] = d1[15:8] == 8'd0;
wire [7:0] d2 = clz[3] ? d1[7:0] : d1[15:8];
assign clz[2] = d2[7:4] == 4'd0;
wire [3:0] d3 = clz[2] ? d2[3:0] : d2[7:4];
assign clz[1] = d3[3:2] == 2'd0;
wire [1:0] d4 = clz[1] ? d3[1:0] : d3[3:2];
assign clz[0] = d4[1] == 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int mirror(int num) { int res = 0; for (int i = 0; i < 4; ++i) { res |= (num & (1 << i)) << (7 - i - i); res |= (num & (1 << (7 - i))) >> (7 - i - i); } return res; } int main() { int num; string s; vector<int> res; getline(cin, s); num = (0 + 256 - mirror((int)s[0])) % 256; res.push_back(num); for (int i = 1; i < s.size(); ++i) { num = (-mirror(s[i]) + 256 + mirror(s[i - 1])) % 256; res.push_back(num); } for (int i = 0; i < res.size(); ++i) { cout << res[i] << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O21A_PP_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline int size(const T& c) { return c.size(); } template <class T> inline int length(const T& c) { return c.length(); } unsigned long long l, r, k, m; vector<unsigned long long> can; struct matrix { unsigned long long val[2][2]; friend matrix operator*(const matrix a, const matrix b) { matrix ret; for (int i = (0), _b = ((2) - 1); i <= _b; i++) for (int j = (0), _b = ((2) - 1); j <= _b; j++) { ret.val[i][j] = 0; for (int k = (0), _b = ((2) - 1); k <= _b; k++) ret.val[i][j] = (ret.val[i][j] + a.val[i][k] * b.val[k][j]) % m; } return ret; } friend matrix operator^(const matrix a, const unsigned long long n) { if (n == 1) return a; matrix ret = a ^ (n / 2); ret = ret * ret; if (n % 2 == 1) ret = ret * a; return ret; } }; unsigned long long fibo(unsigned long long n) { if (n <= 2) return 1 % m; else if (n == 3) return 2 % m; else { matrix a; a.val[0][0] = 0; a.val[0][1] = 1; a.val[1][0] = 1; a.val[1][1] = 1; n -= 3; a = a ^ n; return (a.val[1][0] + 2 * a.val[1][1]) % m; } } int main() { while (cin >> m >> l >> r >> k) { can.clear(); for (unsigned long long i = 1; i * i <= r; i++) { (can).push_back((i)); (can).push_back((r / i)); if (i * i <= l) if (l % i == 0) (can).push_back((l / i)); else (can).push_back((l / (i - 1))); } unsigned long long ret = 1; for (int i = (0), _b = ((can.size()) - 1); i <= _b; i++) { unsigned long long a = l / can[i]; if (l % can[i] != 0) a++; unsigned long long b = r / can[i]; if (b - a + 1 >= k) ret = max(ret, can[i]); } cout << fibo(ret) << endl; } return 0; }
|
// -*- mode: Verilog; verilog-auto-lineup-declaration: nil; -*-
//-----------------------------------------------------------------------------
// Title : Synchronous FIFO
// Project : Common
//-----------------------------------------------------------------------------
// File : sync_fifo.v
//-----------------------------------------------------------------------------
// Description : Synchronous FIFO using BRAM.
//
// Implements a variable width/depth synchronous FIFO. The synthesis
// tool may choose to implement the memory as a block RAM.
//-----------------------------------------------------------------------------
// Copyright 1994-2009 Beyond Circuits. All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE BEYOND CIRCUITS ``AS IS'' AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
// SHALL BEYOND CIRCUITS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//------------------------------------------------------------------------------
`timescale 1ns/1ns
module sync_fifo
#(
parameter depth = 32,
parameter width = 32,
// Need the log of the parameters as parameters also due to an XST bug.
parameter log2_depth = log2(depth),
parameter log2_depthp1 = log2(depth+1)
)
(
input clk,
input reset,
input wr_enable,
input rd_enable,
output reg empty,
output reg full,
output [width-1:0] rd_data,
input [width-1:0] wr_data,
output reg [log2_depthp1-1:0] count
);
// log2 -- return the log base 2 of value.
function integer log2;
input [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
// increment -- add one to value modulo depth.
function [log2_depth-1:0] increment;
input [log2_depth-1:0] value;
begin
if (value == depth-1)
increment = 0;
else
increment = value+1;
end
endfunction
// writing -- true when we write to the RAM.
wire writing = wr_enable && (rd_enable || !full);
// reading -- true when we are reading from the RAM.
wire reading = rd_enable && !empty;
// rd_ptr -- the read pointer.
reg [log2_depth-1:0] rd_ptr;
// next_rd_ptr -- the next value for the read pointer.
// We need to name this combinational value because it
// is needed to use the write-before-read style RAM.
reg [log2_depth-1:0] next_rd_ptr;
always @(*)
if (reset)
next_rd_ptr = 0;
else if (reading)
next_rd_ptr = increment(rd_ptr);
else
next_rd_ptr = rd_ptr;
always @(posedge clk)
rd_ptr <= next_rd_ptr;
// wr_ptr -- the write pointer
reg [log2_depth-1:0] wr_ptr;
// next_wr_ptr -- the next value for the write pointer.
reg [log2_depth-1:0] next_wr_ptr;
always @(*)
if (reset)
next_wr_ptr = 0;
else if (writing)
next_wr_ptr = increment(wr_ptr);
else
next_wr_ptr = wr_ptr;
always @(posedge clk)
wr_ptr <= next_wr_ptr;
// count -- the number of valid entries in the FIFO.
always @(posedge clk)
if (reset)
count <= 0;
else if (writing && !reading)
count <= count+1;
else if (reading && !writing)
count <= count-1;
// empty -- true if the FIFO is empty.
// Note that this doesn't depend on count so if the count
// output is unused the logic for computing the count can
// be optimized away.
always @(posedge clk)
if (reset)
empty <= 1;
else if (reading && next_wr_ptr == next_rd_ptr && !full)
empty <= 1;
else
if (writing && !reading)
empty <= 0;
// full -- true if the FIFO is full.
// Again, this is not dependent on count.
always @(posedge clk)
if (reset)
full <= 0;
else if (writing && next_wr_ptr == next_rd_ptr)
full <= 1;
else if (reading && !writing)
full <= 0;
// We need to infer a write first style RAM so that when
// the FIFO is empty the write data can flow through to
// the read side and be available the next clock cycle.
reg [width-1:0] mem [depth-1:0];
always @(posedge clk)
begin
if (writing)
mem[wr_ptr] <= wr_data;
rd_ptr <= next_rd_ptr;
end
assign rd_data = mem[rd_ptr];
endmodule
|
#include <bits/stdc++.h> using namespace std; struct pp { long long cost; bool operator<(const pp &temp) const { return cost < temp.cost; } }; map<pp, int> hs; int n, c[2]; pp now; map<pp, int> solve(int n) { map<pp, int> ret, ms; map<pp, int>::iterator it; pp u, now; ret.clear(); if (n <= 3) { now.cost = c[0]; ret[now]++; now.cost = c[1]; ret[now]++; } if (n == 2) return ret; if (n > 3) ret = solve(n / 2); int nc = 0, vl; while (n > 3 && nc < n / 2) { it = ret.begin(); if (nc + it->second >= n / 2) vl = n / 2 - nc; else vl = it->second; u = it->first; ret[u] -= vl; if (ret[u] == 0) ret.erase(u); nc += vl; now = u; now.cost += c[0]; ret[now] += vl; now = u; now.cost += c[1]; ret[now] += vl; } if (n & 1) { it = ret.begin(); u = it->first; ret[u]--; if (ret[u] == 0) ret.erase(u); now = u; now.cost += c[0]; ret[now]++; now = u; now.cost += c[1]; ret[now]++; } return ret; } int main() { scanf( %d%d%d , &n, &c[0], &c[1]); if (c[0] == 0 || c[1] == 0) { printf( %lld n , (long long)(n - 1) * (long long)max(c[0], c[1])); return 0; } hs = solve(n); map<pp, int>::iterator it; pp u; long long ans = 0; for (it = hs.begin(); it != hs.end(); it++) { u = it->first; ans += (long long)u.cost * (long long)hs[u]; } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> struct node { int x, y; int dir, len; } arr[1100 * 1100], st[1100]; int n, m, tot, vis[1100][1100], cnt; int srow[1100][1100], scol[1100][1100]; int dir[4] = {1, -1, -1, 1}; char mmap[1100][1100]; void Initial() { int i, j, k; for (i = 1; i <= n; ++i) for (j = 1; j <= m; ++j) srow[i][j] = srow[i][j - 1] + vis[i][j]; for (j = 1; j <= m; ++j) for (i = 1; i <= n; ++i) scol[i][j] = scol[i - 1][j] + vis[i][j]; } int GetDir(char c) { if (c == N ) return 0; if (c == S ) return 1; if (c == W ) return 2; if (c == E ) return 3; } int Isok(int in) { int i, j, k, x, y; x = st[in].x, y = st[in].y; for (i = 1; i <= tot; ++i) { int td = arr[i].dir, tl = arr[i].len; if (td == 0) { if (x - tl <= 0) return 0; if (scol[x][y] - scol[x - tl - 1][y] > 0) return 0; x -= tl; } else if (td == 1) { if (x + tl >= n + 1) return 0; if (scol[x + tl][y] - scol[x - 1][y] > 0) return 0; x += tl; } else if (td == 2) { if (y - tl <= 0) return 0; if (srow[x][y] - srow[x][y - tl - 1] > 0) return 0; y -= tl; } else { if (y + tl >= m + 1) return 0; if (srow[x][y + tl] - srow[x][y - 1] > 0) return 0; y += tl; } } cnt++; return 1; } int main() { int i, j, k; while (scanf( %d%d , &n, &m) != EOF) { for (i = 0; i < 26; ++i) st[i].x = -1; for (i = 1; i <= n; ++i) { scanf( %s , mmap[i] + 1); for (j = 1; j <= m; ++j) { if (mmap[i][j] >= A && mmap[i][j] <= Z ) st[mmap[i][j] - A ].x = i, st[mmap[i][j] - A ].y = j; vis[i][j] = mmap[i][j] == # ? 1 : 0; } } Initial(); scanf( %d , &tot); for (i = 1; i <= tot; ++i) { char str[20]; scanf( %s %d , str, &arr[i].len); arr[i].dir = GetDir(str[0]); } cnt = 0; for (i = 0; i < 26; ++i) if (st[i].x != -1 && Isok(i)) printf( %c , i + A ); if (cnt == 0) printf( no solution n ); printf( n ); } }
|
/* A alu module*/
module ALU(inputA, inputB, ALUop, result, zero);
input [31:0] inputA, inputB;
input [2:0] ALUop;
output [31:0] result;
reg [31:0] result;
output zero;
reg zero;
/*whenever input or ALUop changes*/
always @(inputA or inputB or ALUop)
begin
/*it supports AND, OR, ADD, SLT with a zero output*/
casez(ALUop)
3'b110: result = inputA - inputB;
3'b010: result = inputA + inputB;
3'bz00: result = inputA & inputB;
3'b?01: result = inputA | inputB;
3'b?11:
if ( inputA - inputB >= 0 )
result = 1;
else
result = 0;
endcase
if (inputA == inputB)
zero = 1;
else
zero = 0;
end
endmodule
module ALUTestbench;
reg [31:0] inputA, inputB;
reg [2:0] ALUop;
wire [31:0] result;
wire zero;
ALU UUT(inputA, inputB, ALUop, result, zero);
initial begin
#20 inputA = 5;
inputB = 6;
ALUop = 3'b000;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b001;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b010;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b110;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b011;
#40 inputA = 9;
inputB = 3;
ALUop = 3'b011;
#40 inputA = 6;
inputB = 6;
ALUop = 3'b001;
#40 inputA = -8;
inputB = 6;
ALUop = 3'b001;
end
initial
#340 $stop;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long GI(long long &a) { return scanf( %I64d , &a); } long long n, i, j, k, tmp, m; long long arr[100100]; string s, s1; int32_t main() { getline(cin, s1); getline(std::cin, s); k = 0; for (long long i = 0; i < s1.length(); i++) k = k * 10 + s1[i] - 0 ; n = s.length(); long long cur = 0; vector<long long> l; long long mm = 0; for ((i) = 0; (i) < (long long)(n); ++i) { cur++; if (s[i] == - || s[i] == ) { l.push_back(cur); mm = (mm > cur ? mm : cur); cur = 0; } } if (cur > 0) { l.push_back(cur); mm = max(mm, cur); } long long le = mm, r = 1000000, mid; while (le < r) { mid = (le + r) / 2; long long cnt = 0; long long last = 1000000; for (long long i = 0; i < l.size(); i++) { if (last + l[i] > mid) { cnt++; last = l[i]; } else last = last + l[i]; } if (cnt <= k) r = mid; else le = mid + 1; } cout << le; }
|
#include <bits/stdc++.h> using namespace std; long long t = 1, T; void print2d(vector<vector<long long>> &v) { for (long long i = 0; i < v.size(); i++) { for (long long x : v[i]) { cout << x << ; } cout << n ; } } void print(vector<long long> &a) { for (long long x : a) { cout << x << ; } cout << n ; return; } long long fun(long long x, long long y) { return x * x + y * y; } void solve() { long long n; cin >> n; vector<long long> a(n, 0); vector<long long> freq(n + 1, 0); long long x; for (long long i = 0; i < n; i++) { cin >> a[i]; freq[a[i]]++; } set<long long> v; for (long long i = 0; i < n; i++) { for (long long j = i + 1; j < n; j++) { v.insert(a[i] + a[j]); } } long long ans = 0; for (long long sum : v) { long long i, j; if (sum & 1) { i = sum / 2; j = i + 1; } else i = j = sum / 2; long long rep = 0; while (i >= 1 && j <= n) { if (i == j) { rep += freq[i] / 2; i--; j++; } else { rep += min(freq[i], freq[j]); i--; j++; } } ans = max(ans, rep); } cout << ans << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> t; T = t; while (t--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBP_1_V
`define SKY130_FD_SC_LP__SDFBBP_1_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfbbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfbbp_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfbbp_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBP_1_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = 0x3f3f3f3f3f3f3f3f; template <typename T> inline void read(T& X) { X = 0; int w = 0; char ch = 0; while (!isdigit(ch)) { w |= ch == - ; ch = getchar(); } while (isdigit(ch)) X = (X << 3) + (X << 1) + (ch ^ 48), ch = getchar(); if (w) X = -X; } long long a[20], p[20]; int main() { int t; for (int i = 0; i <= 9; i++) p[i] = pow(10, i); scanf( %d , &t); while (t--) { long long k, n; long long ans = 0; scanf( %lld %lld , &n, &k); for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); a[i] = p[a[i]]; } for (int i = 1; i <= n; i++) { if (i == n) { ans = ans + (k + 1) * a[i]; break; } long long now = (a[i + 1] - a[i]) / a[i]; if (now <= k) { ans = ans + a[i + 1] - a[i]; k = k - now; } else { ans = ans + a[i] * (k + 1); break; } } printf( %lld n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int i, j; int arr1[n], arr2[n], p[n]; for (i = 1; i <= n; i++) cin >> arr1[i]; for (i = 1; i <= n; i++) cin >> arr2[i]; for (i = 1; i <= n; i++) p[arr1[i]] = arr2[i]; for (i = 1; i <= n; i++) cout << p[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; long long a3, b3; bool check1(long long a1, long long b1, long long a2, long long b2) { if ((a2 * a3 + b2 * b3 + a1 * b3 - a3 * b1) % (a3 * a3 + b3 * b3)) return false; if ((a2 * b3 - b2 * a3 - a1 * a3 - b1 * b3) % (a3 * a3 + b3 * b3)) return false; return true; } bool check2(long long a1, long long b1, long long a2, long long b2) { if ((a2 * a3 + b2 * b3 - a1 * a3 - b1 * b3) % (a3 * a3 + b3 * b3)) return false; if ((a1 * b3 - b1 * a3 - a2 * b3 + b2 * a3) % (a3 * a3 + b3 * b3)) return false; return true; } bool check(long long a1, long long b1, long long a2, long long b2) { if (a1 == a2 && b1 == b2) return true; if (b1 == a2 && -a1 == b2) return true; if (-a1 == a2 && -b1 == b2) return true; if (-b1 == a2 && a1 == b2) return true; return false; } int main() { long long a1, a2, b1, b2; while (~scanf( %lld%lld%lld%lld%lld%lld , &a1, &b1, &a2, &b2, &a3, &b3)) { if (a3 == b3 && a3 == 0) { puts(check(a1, b1, a2, b2) ? YES : NO ); } else { int ok = 0; ok += check(a1, b1, a2, b2); ok += check1(a1, b1, a2, b2); ok += check1(a1, b1, b2, -a2); ok += check1(a1, b1, -a2, -b2); ok += check1(a1, b1, -b2, a2); ok += check2(a1, b1, a2, b2); ok += check2(a1, b1, b2, -a2); ok += check2(a1, b1, -a2, -b2); ok += check2(a1, b1, -b2, a2); puts(ok ? YES : NO ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int SIZE = 100011; const int MAX = 1e9; int mi[SIZE << 2], a[SIZE]; void init(int L, int R, int id) { mi[id] = MAX; if (L == R) return; int mm = (L + R) >> 1; init(L, mm, id << 1); init(mm + 1, R, (id << 1) + 1); } void ins(int L, int R, int id, int x, int v) { if (L == R) { mi[id] = v; return; } int mm = (L + R) >> 1; if (x <= mm) ins(L, mm, id << 1, x, v); else ins(mm + 1, R, (id << 1) + 1, x, v); mi[id] = min(mi[id << 1], mi[(id << 1) | 1]); } int qq(int L, int R, int id, int l1, int rr) { if (L >= l1 && R <= rr) return mi[id]; if (R < l1 || L > rr) return MAX; int mm = (L + R) >> 1; return min(qq(L, mm, id << 1, l1, rr), qq(mm + 1, R, (id << 1) | 1, l1, rr)); } int main() { int n, s, l; scanf( %d%d%d , &n, &s, &l); init(0, n, 1); ins(0, n, 1, 0, 0); multiset<int> H; int lt = 1, an; for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); a[i] = x; H.insert(x); while (*H.rbegin() - *H.begin() > s) { H.erase(H.find(a[lt++])); } if (i - lt + 1 >= l) { ins(0, n, 1, i, an = qq(0, n, 1, lt - 1, i - l) + 1); } else an = MAX; } if (an >= MAX) puts( -1 ); else printf( %d n , an); return 0; }
|
//-----------------------------------------------------
// Design Name : encoder_using_case
// File Name : encoder_using_case.v
// Function : Encoder using Case
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module encoder_using_case(
binary_out , // 4 bit binary Output
encoder_in , // 16-bit Input
enable // Enable for the encoder
);
output [3:0] binary_out ;
input enable ;
input [15:0] encoder_in ;
reg [3:0] binary_out ;
always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
case (encoder_in)
16'h0002 : binary_out = 1;
16'h0004 : binary_out = 2;
16'h0008 : binary_out = 3;
16'h0010 : binary_out = 4;
16'h0020 : binary_out = 5;
16'h0040 : binary_out = 6;
16'h0080 : binary_out = 7;
16'h0100 : binary_out = 8;
16'h0200 : binary_out = 9;
16'h0400 : binary_out = 10;
16'h0800 : binary_out = 11;
16'h1000 : binary_out = 12;
16'h2000 : binary_out = 13;
16'h4000 : binary_out = 14;
16'h8000 : binary_out = 15;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_2_V
`define SKY130_FD_SC_MS__XNOR3_2_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog wrapper for xnor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__xnor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xnor3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xnor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_2_V
|
// ======================================================================
// DES encryption/decryption testbench
// tests according to NIST 800-17 special publication
// Copyright (C) 2012 Torsten Meissner
//-----------------------------------------------------------------------
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
// ======================================================================
`timescale 1ns/1ps
module tb_tdes;
// set dumpfile
initial begin
$dumpfile ("tb_tdes.vcd");
$dumpvars (0, tb_tdes);
end
reg reset;
reg clk = 0;
reg mode;
reg [0:63] key1;
reg [0:63] key2;
reg [0:63] key3;
reg [0:63] datain;
reg validin;
integer index;
integer outdex;
integer errors;
wire [0:63] dataout;
wire validout;
wire ready;
reg [0:63] test_data [0:18];
reg [0:63] test_answers [0:18];
// read in test data files
initial begin
$readmemh("test_data.txt", test_data);
end
// setup simulation
initial begin
reset = 1;
#1 reset = 0;
#20 reset = 1;
end
// generate clock with 100 mhz
always #5 clk = !clk;
// init the register values
initial
forever @(negedge reset) begin
//disable stimuli;
disable checker;
mode <= 0;
validin <= 0;
key1 <= 0;
key2 <= 0;
key3 <= 0;
datain <= 0;
errors = 0;
end
// stimuli generator process
initial
forever @(negedge reset) begin
index = 0;
wait (reset);
while (index < 19) begin
@(posedge clk)
if (ready) begin
mode <= 0;
validin <= 1;
datain <= test_data[index];
key1 <= 64'h1111111111111111;
key2 <= 64'h5555555555555555;
key3 <= 64'h9999999999999999;
index = index + 1;
@(posedge clk)
validin <= 0;
end
end
index = 0;
while (index < 19) begin
@(posedge clk)
if (ready) begin
mode <= 1;
validin <= 1;
datain <= test_answers[index];
key1 <= 64'h1111111111111111;
key2 <= 64'h5555555555555555;
key3 <= 64'h9999999999999999;
index = index + 1;
@(posedge clk)
validin <= 0;
end
end
@(posedge clk)
validin <= 0;
mode <= 0;
datain <= 0;
key1 <= 0;
key2 <= 0;
key3 <= 0;
end
// checker process
always begin : checker
wait (reset)
outdex = 0;
// encryption tests
outdex = 0;
while (outdex < 19) begin
@(posedge clk)
if (validout) begin
test_answers[outdex] = dataout;
outdex = outdex + 1;
end
end
// decryption tests
outdex = 0;
while (outdex < 19) begin
@(posedge clk)
if (validout) begin
// detected an error -> print error message
// increment error counter
if (dataout != test_data[outdex]) begin
$display ("error, output was %h - should have been %h", dataout, test_data[outdex]);
errors = errors + 1;
end
outdex = outdex + 1;
end
end
if (errors) begin
$display ("simulation finished, %0d errors detected :(", errors);
end else begin
$display ("simulation tests finished, no errors detected :)");
end
$display ("#############");
@(posedge clk)
$finish;
end
// dut
tdes i_tdes (
.reset_i(reset),
.clk_i(clk),
.mode_i(mode),
.key1_i(key1),
.key2_i(key2),
.key3_i(key3),
.data_i(datain),
.valid_i(validin),
.data_o(dataout),
.valid_o(validout),
.ready_o(ready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long int n, m; cin >> n >> m; long long int st = n / 2; if (n & 1) st++; for (long long int i = (st); i < n + 1; i++) { if (i % m == 0) { cout << i; return; } } cout << -1; } signed main() { ios::sync_with_stdio(0), cin.tie(0); long long int tt = 1; for (long long int i = (0); i < tt; i++) solve(), cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, a, b, dp[300][300]; long long s; vector<pair<long long, long long> > v; long long r, tr; long long gs(long long a, long long b, long long c) { long long s = 0; s = (v[b].first - v[a].first) * (v[c].second - v[a].second) - (v[b].second - v[a].second) * (v[c].first - v[a].first); return s; } int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 0; i < n; i++) { cin >> a >> b; v.push_back(make_pair(a, b)); } for (int i = 0; i < n; i++) s += v[(i + 1) % n].first * v[i].second - v[(i + 1) % n].second * v[i].first; if (s < 0) reverse(v.begin(), v.end()); for (int i = 0; i < n; i++) dp[i][(i + 1) % n] = 1; for (int span = 2; span < n; span++) { for (int l = 0; l < n; l++) { r = l + span; r %= n; for (int q = l + 1; q < l + span; q++) { tr = q % n; if (gs(l, r, tr) > 0) dp[l][r] = (dp[l][r] + dp[l][tr] * dp[tr][r]) % 1000000007; } } } cout << dp[0][n - 1] << endl; cin.get(); cin.get(); return 0; }
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_interp
#(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7)
(input clock,
input reset,
input enable,
input [7:0] rate,
input strobe_in,
input strobe_out,
input [bw-1:0] signal_in,
output reg [bw-1:0] signal_out);
integer i;
localparam maxbitgain = (N-1)*log2_of_max_rate;
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
reg [bw+maxbitgain-1:0] pipeline [0:N-1];
sign_extend #(bw,bw+maxbitgain)
ext_input (.in(signal_in),.out(signal_in_ext));
//FIXME Note that this section has pipe and diff reversed
// It still works, but is confusing
always @(posedge clock)
if(reset | ~enable)
for(i=0;i<N;i=i+1)
integrator[i] <= 0;
else if (enable & strobe_out)
begin
if(strobe_in)
integrator[0] <= integrator[0] + pipeline[N-1];
for(i=1;i<N;i=i+1)
integrator[i] <= integrator[i] + integrator[i-1];
end
always @(posedge clock)
if(reset | ~enable)
begin
for(i=0;i<N;i=i+1)
begin
differentiator[i] <= 0;
pipeline[i] <= 0;
end
end
else if (enable && strobe_in)
begin
differentiator[0] <= signal_in_ext;
pipeline[0] <= signal_in_ext - differentiator[0];
for(i=1;i<N;i=i+1)
begin
differentiator[i] <= pipeline[i-1];
pipeline[i] <= pipeline[i-1] - differentiator[i];
end
end
wire [bw-1:0] signal_out_unreg;
cic_int_shifter #(bw)
cic_int_shifter(rate,integrator[N-1],signal_out_unreg);
always @(posedge clock)
signal_out <= signal_out_unreg;
endmodule // cic_interp
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[500010], ar; bool vis[500010]; int u, v, n, m, s, res = 0; void dfs(int cur) { vis[cur] = true; for (auto i : adj[cur]) if (!vis[i]) dfs(i); ar.push_back(cur); } int main() { scanf( %d%d%d , &n, &m, &s); for (int i = 0; i < m; ++i) { scanf( %d%d , &u, &v); adj[u].push_back(v); } dfs(s); for (int i = 1; i <= n; ++i) { if (!vis[i]) dfs(i); } memset(vis, false, sizeof vis); for (int i = n - 1; i >= 0; --i) { if (!vis[ar[i]]) { if (s != ar[i]) res++; dfs(ar[i]); } } printf( %d n , res); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCON_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__FAHCON_FUNCTIONAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
// Local signals
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire u_vpwr_vgnd1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , u_vpwr_vgnd1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCON_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int ans = 1; for (int i = 6; i <= n; i++) { if (n % i == 0) { int k1 = 0, k0 = 0; int f = 0; int x = i; while (x > 1 and f == 0) { int x2 = x % 2; if (x2 == 1 and k0 > 0) k1++; else if (x2 == 0 and k1 == 0) k0++; else f = 1; x /= 2; } if (k1 - k0 == 0 and f == 0) ans = i; } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; queue<int> fila[100000 + 10]; int bit[100000 + 10]; int rsp[100000 + 10]; pair<pair<int, int>, int> q[100000 + 10]; int v[100000 + 10]; int ls[100000 + 10]; void add(int p, int v) { if (p == 0) return; for (; p <= 100000; p += (p & (-p))) bit[p] += v; } int get(int p) { int ret = 0; for (; p > 0; p -= (p & (-p))) ret += bit[p]; return ret; } int main() { int n, m; scanf( %d %d , &n, &m); memset(bit, 0, sizeof(bit)); for (int i = 1; i <= n; i++) scanf( %d , &v[i]), ls[i] = -1, fila[i].push(0); for (int i = 1; i <= m; i++) { scanf( %d %d , &q[i - 1].first.second, &q[i - 1].first.first); q[i - 1].second = i - 1; } sort(q, q + m); int ind = 0; for (int i = 1; i <= n; i++) { if (v[i] <= n) { if (ls[v[i]] != -1) { add(ls[v[i]] + 1, -1); add(fila[v[i]].front() + 1, +1); } if (fila[v[i]].size() == v[i]) { add(fila[v[i]].front() + 1, +1); ls[v[i]] = fila[v[i]].front(); fila[v[i]].pop(); fila[v[i]].push(i); add(fila[v[i]].front() + 1, -1); } else fila[v[i]].push(i); } while (ind < m && q[ind].first.first == i) { rsp[q[ind].second] = get(q[ind].first.second); ind++; } } for (int i = 0; i < m; i++) { printf( %d n , rsp[i]); } return 0; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the communication channel
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
/*
`include "syntheziedviterbi.v"
`include "viterbi_decoder.sdf"
`include "cencoder.v"
`include "noisegen.v"
`include "xor2.v"
`include "pipe.v"
`include "pipe2.v"
*/
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
// ============================================================
module tb_syn_communication_channel();
/**
* Description of module to model a communication channel
*
* This includes 3 stages in the communications channel
* @stage 1: Data from the transmitter (TX) is encoded.
* @stage 2: Data is "transmitted" across the communication
* channel, and gets corrupted with noise.
* Noise in the communication channel is modeled
* by pseudo-random noise that corrupts some of
* the data bits
* @stage 3: Data is received at the receiver (RX), and is
* subsequently decoded.
*/
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the communication channel
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// ============================================================
// Declare "wire" signals: outputs from the DUT
// Outputs from the communication channel
wire d; // Output data signal
wire [1:0] c; // Encoded data
wire [1:0] cx; // Corrupted encoded data
wire b; // Original data
// -----------------------------------------------------------
// Encoded data output from the convolutional encoder
wire [1:0] r_c;
//wire [255:0] rf;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// ------------------------------------------------------------
// Inputs to the communication channel
//reg [255:0] r; // Original data: 256 stream of bits
reg r[0:255]; // Original data: 256 stream of bits
reg rr;
/**
* Randomly generated number to determine if data bit should
* be corrupted
*/
reg [7:0] e;
reg clock; // Clock input to all flip-flops
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 1st stage of the communication
* channel
*/
// Original data input & input to the convolutional encoder
reg r_b;
// Encoded data output from the convolutional encoder
// reg [1:0] r_c;
/**
* Propagated randomly generated number to determine if data
* bit should be corrupted - propagated value from the input
* to the communications channel
*/
reg [7:0] r_e;
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 2nd stage of the communication
* channel
*/
// Propagated values of the encoded data; also, input to XOR gate
reg [1:0] rr_c;
/**
* Further propagated randomly generated number to determine
* if data bit should be corrupted - propagated value from the
* input to the communications channel
*/
reg [7:0] r_e1;
/**
* Randomly generated error that determines the corruption of
* the data bits
*
* Random number will corrupt the encoded data bits based on
* the XOR operator - invert the bits of the encoded data if
* they are different from the random error bits
*
* Also, input to XOR gate to generated corrupted encoded bits
*/
wire [1:0] r_e2;
/**
* Corrupted encoded data bits - model corruption of data during
* transmission of the data in the communications channel
*/
wire [1:0] r_cx;
// Propagated original data input
reg r_b1;
/** ########################################################
#
# IMPORTANT!!!: MODIFY THE error_level HERE!!!
#
########################################################
***
*
* Error level that will be used to generate noise that will
* be used to corrupt encoded data bits
*
* Randomly generated error bits will be compared with this
* error level
*/
reg [7:0] error_level;
// ------------------------------------------------------------
// Inputs to the 3rd stage of the communication channel
// Further propagated values of the encoded data
reg [1:0] rr_c1;
// Propagated values of the corrupted encoded data
reg [1:0] r_cx1;
// Propagated original data input
reg r_b2;
// Reset signal for the flip-flops and registers
reg rset;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 9'd256;
// ============================================================
// Declare and instantiate modules for the communication channel
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
d,r_cx1,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,r_b,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the noise generator so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "ng"
*/
noise_generator ng (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_e1,r_e2,error_level);
// ------------------------------------------------------------
/**
* Instantiate an instance of the 2-bit 2-input XOR gate so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor22"
*/
xor2_2bit xor22 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c,r_e2,r_cx);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_c"
*/
pipeline_buffer_2bit pipe_c (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c1,c,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_cx"
*/
pipeline_buffer_2bit pipe_cx (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_cx1,cx,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_b"
*/
pipeline_buffer pipe_b (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b2,b,clock,rset);
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
// Period = 10 clock cycles
end
// ============================================================
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clock)
begin
if(rset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=rr;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 2nd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c<=0;
r_e1<=0;
r_b1<=0;
end
else
begin
rr_c<=r_c;
r_e1<=r_e;
r_b1<=r_b;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 3rd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c1<=0;
r_cx1<=0;
r_b2<=0;
end
else
begin
rr_c1<=rr_c;
r_cx1<=r_cx;
r_b2<=r_b1;
end
end
// ------------------------------------------------------------
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
error_level=8'd5;
rset=1;
// @t=20,
#20
rset=0;
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/// $readmemb("testfile.bit",rf);
/**
* IMPORTANT NOTE:
* Start to process inputs from the input file after
* 30 clock cycles
*/
for(count=0;count<size_of_input;count=count+1)
begin
#10
$display("Next");
e=$random;
rr=r[count];
if(rr_c != r_cx)
begin
$display($time,"rr_c NOT EQUAL to r_cx");
end
if(count==150)
begin
rset=1;
end
else if(count==151)
begin
rset=0;
end
end
// Problem with d and error_level
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
`ifndef __DEFINE__
`define __DEFINE__
`ifndef intN
`define intN 32
`endif
`ifndef symN
`define symN 1
`endif
`ifndef anyN
`define anyN `intN
`endif
`ifndef addrN
`define addrN 16
`endif
`define intT [`intN-1:0]
`define symT [`symN-1:0]
`define anyT [`anyN-1:0]
`define addrT [`addrN-1:0]
`define sync_ports \
input wire clk, input wire nrst, \
input wire in_valid, output wire in_ready, \
output wire out_valid, input wire out_ready
`define id(x) x
`define concat_(a, b) `id(a)``_``b
`define stringify(x) `"x`"
`define rename(dst, src) wire src; assign dst = src
`define top_sync(ready) \
assign in_ready = ready
`define loop_sync(ready) \
reg active = `false; \
assign in_ready = ~active & ready
`define sync_wire(name) `concat_(`current_inst, name)
`define inst(t, n, p) \
`define current_inst n \
t p t``_``n
`define inst_sync(t, n, p) \
`define current_inst n \
wire `sync_wire(out_valid); \
t p t``_``n
`define apply(f, x) `f x
`define start_block(name) \
`define block name \
`define end_block(name) \
`undef block \
`define sync(valid, ready) \
.clk(clk), \
.nrst(nrst), \
.in_valid(valid), \
.out_valid(`sync_wire(out_valid)), \
.in_ready(`sync_wire(in_ready)), \
.out_ready(ready)
`define fst_(x, y) (x)
`define snd_(x, y) (y)
`define fst(p) `fst_``p
`define snd(p) `snd_``p
`define input(type, N, index) `input_``type(N, index)
`define input_simple(N, index) input wire [N-1:0] `id(in)``index
`define output(type, N, index) `output_``type(N, index)
`define output_simple(N, index) output wire [N-1:0] `id(out)``index
`define in(type, index, name) `in_``type(index, name)
`define out(type, index, name) `out_``type(index, name)
`define in_simple(index, name) .`id(in)``index(name)
`define out_simple(index, name) .`id(out)``index(name)
`define alias(type, N, name, index) `alias_``type(N, name, index)
`define alias_simple(N, name, other) wire [N-1:0] name = other
`define variable(type, N, name, in) `variable_``type(N, name, in)
`define variable_simple(N, name, in) reg [N-1:0] name
`define wire(type, N, name) `wire_``type(N, name)
`define wire_simple(N, name) wire [N-1:0] name
`define reg(type, N, name) `reg_``type(N, name)
`define reg_simple(N, name) reg [N-1:0] name
`define const(type, N, name, val) `const_``type(N, name, val)
`define const_simple(N, name, val) localparam [N-1:0] name = val
`define input_stream(N, index) input wire [N-1:0] in``index, input wire in``index``_valid, output wire in``index``_ready
`define output_stream(N, index) output wire [N-1:0] out``index, output wire out``index``_valid, input wire out``index``_ready
`define output_null_stream(N, index) output wire out``index``_valid, input wire out``index``_ready
`define in_stream(index, name) .in``index(name), .in``index``_valid(name``_valid), .in``index``_ready(name``_ready)
`define in_dup_stream(index, name) .in``index(name), .in``index``_valid(`concat_(`current_inst, name``_valid)), .in``index``_ready(`concat_(`current_inst, name``_ready))
`define in_null_stream(index, name) .in``index``_valid(name``_valid), .in``index``_ready(name``_ready)
`define in_dup_null_stream(index, name) .in``index``_valid(`concat_(`current_inst, name``_valid)), .in``index``_ready(`concat_(`current_inst, name``_ready))
`define out_stream(index, name) .out``index(name), .out``index``_valid(name``_valid), .out``index``_ready(name``_ready)
`define out_null_stream(index, name) .out``index``_valid(name``_valid), .out``index``_ready(name``_ready)
`define alias_stream(N, name, other) \
wire [N-1:0] name = other; \
wire name``_valid = other``_valid; wire name``_ready; \
assign other``_ready = name``_ready
`define variable_stream(N, name, in) \
wire [N-1:0] name = in; \
reg name``_valid_reg; \
wire name``_valid = in``_valid; \
`rename(in``_ready, name``_ready)
`define wire_stream(N, name) wire [N-1:0] name; wire name``_valid; wire name``_ready
`define wire_null_stream(N, name) wire name``_valid; wire name``_ready
`define reg_stream(N, name) reg [N-1:0] name; reg name``_valid; wire name``_ready
`define const_stream(N, name, val) localparam [N-1:0] name = val; localparam name``_valid = `true
`define const_nil(name) localparam name = 0; localparam name``_valid = `true; wire name``_ready
`define null_const_nil(name) localparam name``_valid = `true; wire name``_ready
`define in_alias(name, other) wire name; assign other = name
`define in_alias_vec(name, other) wire [$bits(other)-1:0] name; assign other = name
`define assign_stream(inst, name) \
`in_alias(inst``_``name``_ready, name``_ready); \
wire inst``_``name``_valid = name``_valid
`define assign_Array(inst, name) \
`assign_stream(inst, name); \
`in_alias_vec(inst``_``name``_addr, name``_addr); \
`in_alias_vec(inst``_``name``_di, name``_di); \
`in_alias(inst``_``name``_we, name``_we)
/* ------------------------------------------------------ *
ARRAY BUS
* ------------------------------------------------------ *
addr: address (*)
we: write enable (*)
di: data in (*)
(no suffix): data out
valid: data out is valid
ready: ready for data
NOTES:
-> when not ready, pass back signals:
addr, we, di, and ready
-> (*) => must be valid when ready
-> addr, we & di must be terminated low
to allow OR'ing and selecting with valid
* ------------------------------------------------------ */
// master
`define input_Array(N, index) \
output wire [`fst(N)-1:0] in``index``_addr, \
output wire in``index``_we, \
output wire [`snd(N)-1:0] in``index``_di, \
input wire [`snd(N)-1:0] in``index, \
input wire in``index``_valid, \
output wire in``index``_ready
// slave
`define output_Array(N, index) \
input wire [`fst(N)-1:0] out``index``_addr, \
input wire out``index``_we, \
input wire [`snd(N)-1:0] out``index``_di, \
output wire [`snd(N)-1:0] out``index, \
output wire out``index``_valid, \
input wire out``index``_ready
`define in_Array(index, name) \
.in``index``_addr(name``_addr), \
.in``index``_we(name``_we), \
.in``index``_di(name``_di), \
.in``index(name), \
.in``index``_valid(name``_valid), \
.in``index``_ready(name``_ready)
`define in_dup_Array(index, name) \
.in``index``_addr(`concat_(`current_inst, name``_addr)), \
.in``index``_we(`concat_(`current_inst, name``_we)), \
.in``index``_di(`concat_(`current_inst, name``_di)), \
.in``index(name), \
.in``index``_valid(`concat_(`current_inst, name``_valid)), \
.in``index``_ready(`concat_(`current_inst, name``_ready))
`define out_Array(index, name) \
.out``index``_addr(name``_addr), \
.out``index``_we(name``_we), \
.out``index``_di(name``_di), \
.out``index(name), \
.out``index``_valid(name``_valid), \
.out``index``_ready(name``_ready)
`define wire_Array(N, name) \
wire [`fst(N)-1:0] name``_addr; \
wire name``_we; \
wire [`snd(N)-1:0] name``_di; \
wire [`snd(N)-1:0] name; \
wire name``_valid; \
wire name``_ready
`define alias_Array(N, name, other) \
wire [`fst(N)-1:0] name``_addr; \
assign other``_addr = name``_addr; \
wire name``_we; \
assign other``_we = name``_we; \
wire [`snd(N)-1:0] name``_di; \
assign other``_di = name``_di; \
wire [`snd(N)-1:0] name = other; \
wire name``_valid = other``_valid; \
wire name``_ready; \
assign other``_ready = name``_ready
`define to_bus(name) {name``_addr, name``_we, name``_di, name``_ready}
`define true 1'b1
`define false 1'b0
`define nil (~(`intN'd0))
`define assert(n, x) \
`define current_inst n \
wire `sync_wire(out_valid) = (x)
`define set(x) x <= `true
`define reset(x) x <= `false
`define valid(x) (! (& x))
`define returned_to(name) (returned && return_addr == label_``name)
// make sure all labels are declared
`default_nettype none
`define testbench(tb_name, timeout) \
reg in_valid = 0; \
reg out_ready = 1; \
reg nrst = 0; \
reg clk = 0; \
reg start = 0; \
always begin \
#0.5 clk = !clk; \
end \
initial begin \
$dumpfile(`dumpfile); \
$dumpvars(0, tb_name); \
# timeout; \
$display("timed out"); \
$finish; \
end \
always @(posedge clk) begin \
if(in_ready & in_valid) begin \
`reset(in_valid); \
end \
end
`define wait_for(valid) \
@(posedge clk); \
while(!(valid)) @(posedge clk)
`define in_ready(inst) \
wire inst``_in_ready; \
wire in_ready = inst``_in_ready
`define start \
@(posedge clk); \
nrst = `false; \
@(posedge clk); \
nrst = `true; \
@(posedge clk); \
#0.01 in_valid = `true
`endif
`define dup_signals_stream(N, inst, name) \
wire inst``_``name``_valid; \
wire inst``_``name``_ready
`define dup_signals_Array(N, inst, name) \
wire inst``_``name``_valid; \
wire inst``_``name``_ready; \
wire [`fst(N)-1:0] inst``_``name``_addr; \
wire [`snd(N)-1:0] inst``_``name``_di; \
wire inst``_``name``_we
`define dup_signals(type, N, inst, name) `dup_signals_``type(N, inst, name)
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`timescale 1ns/1ns
module unitTestDelta();
reg clk;
wire rst;
reg [31:0] b;
wire inv;
wire assert_delta;
initial begin
clk = 1'b0;
b = 32'b0;
end
assign rst = 1'b0;
assign inv = 1'b0;
always begin
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h5;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h3;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
b = b + 32'h4;
#10 clk = ~clk;
#10 clk = ~clk;
end
ovl_delta_wrapped oad(
.clk(clk),
.rst(rst),
.min(8'h0),
.max(8'h4),
.test_expr(b),
.prevConfigInvalid(inv),
.out(assert_edge)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_6sig_x2_async.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_6sig_x2_async(ps_select_i_l ,testmode_l_i_l ,
test_mode_i_l ,testmode_l_i_r ,test_mode_i_r ,serial_out ,serial_in
,afo ,pad_clk_so ,async_pad_0 ,async_pad_1 ,afi ,vrefcode_i_l ,
vrefcode_i_r ,dq_pad ,io_dram_data_in ,io_dram_data_in_hi ,data_neg
,data_pos ,dqs_pad ,ps_select_i_r ,bso ,ctl_data_0 ,pad_clk_si ,
bypass_enable_i_l ,vdd_h ,strobe_i_r ,lpf_code_i_r ,
burst_length_four_i_r ,dram_io_ptr_clk_inv_i_r ,
dram_io_pad_enable_i_r ,dram_io_drive_enable_i_r ,rst_l_i_r , arst_l_i_r,
pad_pos_cnt_i_r ,pad_neg_cnt_i_r ,dram_io_channel_disabled_i_r ,
dram_io_drive_data_i_r ,cbu_i_r ,cbd_i_r ,se_i_r ,mode_ctrl_i_r ,
shift_dr_i_r ,clock_dr_i_r ,hiz_n_i_r ,update_dr_i_r ,strobe_i_l ,
lpf_code_i_l ,burst_length_four_i_l ,dram_io_ptr_clk_inv_i_l ,
dram_io_pad_enable_i_l ,dram_io_drive_enable_i_l ,ctl_data_1 ,
rst_l_i_l , arst_l_i_l, pad_pos_cnt_i_l ,pad_neg_cnt_i_l ,
dram_io_channel_disabled_i_l ,dram_io_drive_data_i_l ,cbu_i_l ,
cbd_i_l ,se_i_l ,mode_ctrl_i_l ,shift_dr_i_l ,clock_dr_i_l ,
hiz_n_i_l ,update_dr_i_l ,rclk ,bypass_enable_i_r ,bsi );
output [7:0] serial_out ;
output [7:0] afi ;
output [7:0] io_dram_data_in ;
output [7:0] io_dram_data_in_hi ;
input [7:0] serial_in ;
input [7:0] afo ;
input [7:0] vrefcode_i_l ;
input [7:0] vrefcode_i_r ;
input [7:0] data_neg ;
input [7:0] data_pos ;
input [4:0] lpf_code_i_r ;
input [1:0] dram_io_ptr_clk_inv_i_r ;
input [1:0] pad_pos_cnt_i_r ;
input [1:0] pad_neg_cnt_i_r ;
input [8:1] cbu_i_r ;
input [8:1] cbd_i_r ;
input [4:0] lpf_code_i_l ;
input [1:0] dram_io_ptr_clk_inv_i_l ;
input [1:0] pad_pos_cnt_i_l ;
input [1:0] pad_neg_cnt_i_l ;
input [8:1] cbu_i_l ;
input [8:1] cbd_i_l ;
inout [7:0] dq_pad ;
inout [1:0] dqs_pad ;
output pad_clk_so ;
output bso ;
input ps_select_i_l ;
input testmode_l_i_l ;
input test_mode_i_l ;
input testmode_l_i_r ;
input test_mode_i_r ;
input ps_select_i_r ;
input ctl_data_0 ;
input pad_clk_si ;
input bypass_enable_i_l ;
input vdd_h ;
input strobe_i_r ;
input burst_length_four_i_r ;
input dram_io_pad_enable_i_r ;
input dram_io_drive_enable_i_r ;
input rst_l_i_r ;
input arst_l_i_r ;
input dram_io_channel_disabled_i_r ;
input dram_io_drive_data_i_r ;
input se_i_r ;
input mode_ctrl_i_r ;
input shift_dr_i_r ;
input clock_dr_i_r ;
input hiz_n_i_r ;
input update_dr_i_r ;
input strobe_i_l ;
input burst_length_four_i_l ;
input dram_io_pad_enable_i_l ;
input dram_io_drive_enable_i_l ;
input ctl_data_1 ;
input rst_l_i_l ;
input arst_l_i_l ;
input dram_io_channel_disabled_i_l ;
input dram_io_drive_data_i_l ;
input se_i_l ;
input mode_ctrl_i_l ;
input shift_dr_i_l ;
input clock_dr_i_l ;
input hiz_n_i_l ;
input update_dr_i_l ;
input rclk ;
input bypass_enable_i_r ;
input bsi ;
inout async_pad_0 ;
inout async_pad_1 ;
wire clk_out0 ;
wire clk_out1 ;
wire dll_s0 ;
wire dll_s1 ;
wire bs0 ;
wire strobe0 ;
wire strobe1 ;
wire dl_clk_in0 ;
wire dl_clk_in1 ;
wire pad_clk_s0 ;
wire dl_clk_out0 ;
wire dl_clk_out1 ;
bw_io_ddr_6sig_async ddr_6sig0 (
.serial_out ({serial_out[3:0] } ),
.serial_in ({serial_in[3:0] } ),
.vrefcode ({vrefcode_i_l } ),
.io_dram_data_in_hi ({io_dram_data_in_hi[3:0] } ),
.afo ({afo[3:0] } ),
.afi ({afi[3:0] } ),
.dram_io_ptr_clk_inv ({dram_io_ptr_clk_inv_i_l } ),
.dq_pad ({dq_pad[3:0] } ),
.io_dram_data_in ({io_dram_data_in[3:0] } ),
.data_pos ({data_pos[3:0] } ),
.data_neg ({data_neg[3:0] } ),
.pad_neg_cnt ({pad_neg_cnt_i_l } ),
.pad_pos_cnt ({pad_pos_cnt_i_l } ),
.cbu ({cbu_i_l } ),
.cbd ({cbd_i_l } ),
.testmode_l (testmode_l_i_l ),
.test_mode (test_mode_i_l ),
.async_pad (async_pad_0 ),
.clk_out (clk_out0 ),
.mode_ctrl (mode_ctrl_i_l ),
.pad_clk_si (pad_clk_si ),
.rclk (rclk ),
.pad_clk_so (dll_s0 ),
.bypass_enable (bypass_enable_i_l ),
.ps_select (ps_select_i_l ),
.dqs_pad (dqs_pad[0] ),
.clk_sel (dl_clk_in0 ),
.vdd_h (vdd_h ),
.se (se_i_l ),
.bso (bs0 ),
.bsi (bsi ),
.hiz_n (hiz_n_i_l ),
.clock_dr (clock_dr_i_l ),
.shift_dr (shift_dr_i_l ),
.data (ctl_data_0 ),
.dram_io_drive_data (dram_io_drive_data_i_l ),
.dram_io_channel_disabled (dram_io_channel_disabled_i_l ),
.update_dr (update_dr_i_l ),
.rst_l (rst_l_i_l ),
.arst_l (arst_l_i_l ),
.dram_io_pad_enable (dram_io_pad_enable_i_l ),
.dram_io_drive_enable (dram_io_drive_enable_i_l ),
.dqs_read (dl_clk_out0 ),
.burst_length_four (burst_length_four_i_l ) );
bw_io_ddr_6sig_async ddr_6sig1 (
.serial_out ({serial_out[7:4] } ),
.serial_in ({serial_in[7:4] } ),
.vrefcode ({vrefcode_i_r } ),
.io_dram_data_in_hi ({io_dram_data_in_hi[7:4] } ),
.afo ({afo[7:4] } ),
.afi ({afi[7:4] } ),
.dram_io_ptr_clk_inv ({dram_io_ptr_clk_inv_i_r } ),
.dq_pad ({dq_pad[7:4] } ),
.io_dram_data_in ({io_dram_data_in[7:4] } ),
.data_pos ({data_pos[7:4] } ),
.data_neg ({data_neg[7:4] } ),
.pad_neg_cnt ({pad_neg_cnt_i_r } ),
.pad_pos_cnt ({pad_pos_cnt_i_r } ),
.cbu ({cbu_i_r } ),
.cbd ({cbd_i_r } ),
.testmode_l (testmode_l_i_r ),
.test_mode (test_mode_i_r ),
.async_pad (async_pad_1 ),
.clk_out (clk_out1 ),
.mode_ctrl (mode_ctrl_i_r ),
.pad_clk_si (pad_clk_s0 ),
.rclk (rclk ),
.pad_clk_so (dll_s1 ),
.bypass_enable (bypass_enable_i_r ),
.ps_select (ps_select_i_r ),
.dqs_pad (dqs_pad[1] ),
.clk_sel (dl_clk_in1 ),
.vdd_h (vdd_h ),
.se (se_i_r ),
.bso (bso ),
.bsi (bs0 ),
.hiz_n (hiz_n_i_r ),
.clock_dr (clock_dr_i_r ),
.shift_dr (shift_dr_i_r ),
.data (ctl_data_1 ),
.dram_io_drive_data (dram_io_drive_data_i_r ),
.dram_io_channel_disabled (dram_io_channel_disabled_i_r ),
.update_dr (update_dr_i_r ),
.rst_l (rst_l_i_r ),
.arst_l (arst_l_i_r ),
.dram_io_pad_enable (dram_io_pad_enable_i_r ),
.dram_io_drive_enable (dram_io_drive_enable_i_r ),
.dqs_read (dl_clk_out1 ),
.burst_length_four (burst_length_four_i_r ) );
bw_ioslave_dl io_slave_dl0 (
.lpf_out ({lpf_code_i_l } ),
.dqs_in (dl_clk_in0 ),
.si (dll_s0 ),
.se (se_i_l ),
.strobe (strobe0 ),
.so (pad_clk_s0 ),
.dqs_out (dl_clk_out0 ) );
bw_ioslave_dl io_slave_dl1 (
.lpf_out ({lpf_code_i_r } ),
.dqs_in (dl_clk_in1 ),
.si (dll_s1 ),
.se (se_i_r ),
.strobe (strobe1 ),
.so (pad_clk_so ),
.dqs_out (dl_clk_out1 ) );
bw_io_ddr_testmux testmux0 (
.strobe_out (strobe0 ),
.clk (clk_out0 ),
.testmode_l (testmode_l_i_l ),
.strobe (strobe_i_l ) );
bw_io_ddr_testmux testmux1 (
.strobe_out (strobe1 ),
.clk (clk_out1 ),
.testmode_l (testmode_l_i_r ),
.strobe (strobe_i_r ) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O31AI_PP_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o31ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_PP_SYMBOL_V
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: dtysky:user:DATA_MEM:1.0
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module MIPS_CPU_DATA_MEM_0_1 (
addr,
data_in,
clk,
we,
data_out
);
input wire [31 : 0] addr;
input wire [31 : 0] data_in;
input wire clk;
input wire we;
output wire [31 : 0] data_out;
DATA_MEM inst (
.addr(addr),
.data_in(data_in),
.clk(clk),
.we(we),
.data_out(data_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200010; int a[MAXN]; int b[MAXN]; int tmp[MAXN]; int main() { int n; cin >> n; int aidx; for (int i = 0; i < n; i++) { cin >> tmp[i]; if (tmp[i] == 0) aidx = i; } for (int i = 0; i < n; i++) a[i] = tmp[(i + aidx) % n]; int bidx; for (int i = 0; i < n; i++) { cin >> tmp[i]; if (tmp[i] == 0) bidx = i; } for (int i = 0; i < n; i++) b[i] = tmp[(i + bidx) % n]; for (int i = 0; i < n - 1; i++) { a[i] = a[i + 1]; b[i] = b[i + 1]; } for (int i = 0; i < n - 1; i++) if (b[i] == a[0]) bidx = i; for (int i = 0; i < n - 1; i++) if (a[i] != b[(i + bidx) % (n - 1)]) { cout << NO << endl; return 0; } cout << YES << endl; }
|
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