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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLYGATE4SD3_FUNCTIONAL_PP_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd3 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD3_FUNCTIONAL_PP_V
|
//============================================================
//
// Hsiang-Yi Chung
// March 2016
//
// This is the top level of the radar dsp module
//
//============================================================
module Radar_top(
input clk,
input reset_n,
input [11:0] adc_in,
output [11:0] mag_out1,
output [11:0] mag_out2,
output next_data,
output data,
output clk_div_16,
//for debugging
output fft_next_out,
output [11:0] avg_out1,
output [11:0] avg_out2,
output [11:0] win_out1,
output [11:0] win_out2,
input fft_next,
input fft_reset
);
wire clk_div_32, win_next, reset_fft;
clk_div clk_div_inst (.clk(clk), .clk_div_16(clk_div_16), .clk_div_32(clk_div_32));
windowing window_inst(.in1(avg_out1), .in2(avg_out2), .clk(clk_div_16),
.out1(win_out1), .out2(win_out2), .next(win_next), .fft_reset(reset_fft));
FFT_Mag fft_inst(.clk(clk_div_32), .reset(reset_fft), .next(win_next),
.X0(win_out1), .X1(0), .X2(win_out2), .X3(0),
.mag1(mag_out1), .mag2(mag_out2), .next_out(fft_next_out));
Average_Filter avg_filter_inst(.in(adc_in), .clk(clk), .reset_n(reset_n),
.out1(avg_out1), .out2(avg_out2));
SerialInterface serialInterface_inst(.clk(clk_div_16), .next_out(fft_next_out), .reset_n(reset_n),
.fft_out1(mag_out1), .fft_out2(mag_out2), .next_data(next_data), .data(data));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DFRTN_BEHAVIORAL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRTN_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = (int)(1e6); char S[N + 1], T[N + 1]; vector<int> multiply(vector<int> a, vector<int> b) { int n = (int)a.size(); vector<int> ret; for (int i = 0; i < n; i++) ret.push_back(a[b[i]]); return ret; } vector<int> pow(vector<int> a, int b) { int n = (int)a.size(); vector<int> ret; if (b == 0) { for (int i = 0; i < n; i++) ret.push_back(i); return ret; } if (b % 2 == 1) return multiply(pow(a, b - 1), a); ret = pow(a, b / 2); return multiply(ret, ret); } void solve(int k, int d, int n) { vector<int> P, vet, ret; for (int i = 0; i < d; i++) for (int j = i; j < k; j += d) if (j > 0) P.push_back(j); P.push_back(0); for (int i = 0; i < k; i++) vet.push_back(i); for (int i = 0, x = 0; i + k <= n; i++) { ret.push_back(vet[x]); vet[x] = i + k; x = P[x]; } vector<int> aux = pow(P, n - k + 1); for (int i = 0; i < k - 1; i++) ret.push_back(vet[aux[i]]); for (int i = 0; i < n; i++) T[i] = S[i]; for (int i = 0; i < n; i++) S[i] = T[ret[i]]; printf( %s n , S); } int main() { scanf( %s , S); int t; scanf( %d , &t); while (t-- > 0) { int k, d; scanf( %d %d , &k, &d); solve(k, d, strlen(S)); } return 0; }
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:54:18 08/11/2009
// Design Name:
// Module Name: STATUS_OUT
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
/////
///// Generate four patterns for specific states
///// Idle 00000000
///// Reset 01010101
///// FIFO full 00001111
///// Training_done 00110011
/////
/////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_STATUS_OUT( CLK,
RESET, // input indicating whether channel is reset, reset pulse of the whole lvds channel
MODULE_RST, // reset pulse for this module only, should be shorter than RESET
FIFO_FULL, // input indicating whether FIFO is FULL
TRAINING_DONE, // input indicating whether TRAINING is done
STATUS,
INT_SAT // coded status output
);
/////////////////////////////////////////////////////////////////////////////////
input CLK;
input MODULE_RST;
input RESET,
FIFO_FULL,
TRAINING_DONE;
output STATUS;
/////////////////////////////////////////////////////////////////////////////////
reg STATUS;
output reg [1:0] INT_SAT;
parameter RST = 2'b00;
parameter FULL = 2'b01;
parameter DONE = 2'b10;
parameter IDLE = 2'b11;
reg [2:0] counter;
wire MODULE_RST_one;
rising_edge_detect MODULE_RESET_one_inst(
.clk(CLK),
.rst(1'b0),
.in(MODULE_RST),
.one_shot_out(MODULE_RST_one)
);
/////////////////////////////////////////////////////////////////////////////////
/// Determine which state it is
always @ ( posedge CLK ) begin
if ( counter == 3'b000 ) begin
if ( RESET == 1'b1 ) begin
INT_SAT <= RST;
end
else if ( FIFO_FULL == 1'b1 & TRAINING_DONE == 1'b1 ) begin
INT_SAT <= FULL;
end
else if ( TRAINING_DONE == 1'b1 ) begin
INT_SAT <= DONE;
end
else begin
INT_SAT <= IDLE;
end
end
end
/////////////////////////////////////////////////////////////////////////////////
/// Counter runs
always @ ( posedge CLK ) begin
// if ( MODULE_RST == 1'b1 ) begin // Jiansong: how can it send out reset status
if ( MODULE_RST_one == 1'b1 ) begin
counter <= 3'b000;
end
else begin
counter <= counter + 3'b001;
end
end
/////////////////////////////////////////////////////////////////////////////////
/// pattern encode
/// Idle 00000000
/// Reset 01010101
/// FIFO_full 00001111
/// Train Done 00110011
always @ ( posedge CLK) begin
if ( INT_SAT == RST ) begin
if ( counter == 3'b000 | counter == 3'b010 | counter == 3'b100 | counter == 3'b110 ) begin
STATUS <= 1'b0;
end
else if (counter == 3'b001 | counter == 3'b011 | counter == 3'b101 | counter == 3'b111 ) begin
STATUS <= 1'b1;
end
end
else if ( INT_SAT == FULL) begin
if (counter == 3'b000 | counter == 3'b001 | counter == 3'b010 | counter == 3'b011 ) begin
STATUS <= 1'b0;
end
else if ( counter == 3'b100 | counter == 3'b101 | counter == 3'b110 | counter == 3'b111 ) begin
STATUS <= 1'b1;
end
end
else if ( INT_SAT == DONE) begin
if ( counter == 3'b000 | counter == 3'b001 | counter == 3'b100 | counter == 3'b101 ) begin
STATUS <= 1'b0;
end
else if ( counter == 3'b010 | counter == 3'b011 | counter == 3'b110 | counter == 3'b111 )begin
STATUS <= 1'b1;
end
end
else if ( INT_SAT == IDLE) begin
STATUS <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k; long long get(long long x, long long y) { if (x <= y * 2) return 0; long long s1 = 1, s2 = 0, p1 = x, p2 = x - 1, ans = 0; while (p2 >= y * 2) { if (p2 == y * 2) return s1 + ans; ans += s1 + s2; if (p1 & 1) s1 = s1 * 2 + s2; else s2 = s2 * 2 + s1; p1 /= 2; p2 = p1 - 1; } return ans; } long long solve(long long l, long long r, long long x, long long k) { long long mid = (l + r) / 2; if (k == 1) return mid; long long X = get(mid - l, x), Y = get(r - mid, x + 1); if (k > X + Y + 1) return solve(mid + 1, r, x, k - X - 1); return solve(l, mid - 1, x, k - Y - 1); } signed main() { scanf( %lld%lld , &n, &k); if (k == 1) { puts( 1 ); return 0; } if (k == 2) { printf( %lld n , n); return 0; } n -= 2; k -= 2; long long l = 0, r = n; while (l < r) { long long mid = (l + r + 1) / 2; if (get(n, mid) < k) r = mid - 1; else l = mid; } printf( %lld n , 1 + solve(1, n, l, k)); }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module scales video streams on the DE boards. *
* *
******************************************************************************/
module Video_System_Video_Scaler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's Data Width
parameter EW = 0; // Frame's Empty Width
parameter WIW = 9; // Incoming frame's width's address width
parameter HIW = 7; // Incoming frame's height's address width
parameter WIDTH_IN = 640;
parameter WIDTH_DROP_MASK = 4'b0101;
parameter HEIGHT_DROP_MASK = 4'b0000;
parameter MH_WW = 8; // Multiply height's incoming width's address width
parameter MH_WIDTH_IN = 320; // Multiply height's incoming width
parameter MH_CW = 0; // Multiply height's counter width
parameter MW_CW = 0; // Multiply width's counter width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire internal_valid;
wire internal_ready;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_out_empty = 'h0;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_scaler_shrink Shrink_Frame (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_valid (stream_in_valid),
.stream_out_ready (stream_out_ready),
// Bidirectional
// Outputs
.stream_in_ready (stream_in_ready),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_valid (stream_out_valid)
);
defparam
Shrink_Frame.DW = DW,
Shrink_Frame.WW = WIW,
Shrink_Frame.HW = HIW,
Shrink_Frame.WIDTH_IN = WIDTH_IN,
Shrink_Frame.WIDTH_DROP_MASK = WIDTH_DROP_MASK,
Shrink_Frame.HEIGHT_DROP_MASK = HEIGHT_DROP_MASK;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long bigmod(long long b, long long p, long long md) { if (p == 0) return 1; if (p % 2 == 1) { return ((b % md) * bigmod(b, p - 1, md)) % md; } else { long long y = bigmod(b, p / 2, md); return (y * y) % md; } } int cnt[70]; char getchar(int a) { if (a >= 0 && a <= 9) return 0 + a; else if (a >= 10 && a <= 35) return a + a - 10; else return A + a - 36; } int main() { int n; cin >> n; string str; cin >> str; for (int i = 0; i < n; i++) { if (str[i] >= 0 && str[i] <= 9 ) cnt[str[i] - 0 ]++; else if (str[i] >= a && str[i] <= z ) cnt[str[i] - a + 10]++; else cnt[str[i] - A + 36]++; } vector<int> odd; for (int i = 0; i <= 61; i++) { if (cnt[i] % 2) { odd.push_back(i); } } if (odd.size() == 0) { cout << 1 << endl; deque<char> dq; for (int i = 0; i <= 61; i++) { while (cnt[i]) { dq.push_back(getchar(i)); dq.push_front(getchar(i)); cnt[i] -= 2; } } for (auto it = dq.begin(); it != dq.end(); it++) cout << *it; cout << endl; return 0; } int sz = 0; for (int i = odd.size(); i <= str.size(); i += 2) { if (str.size() % i) continue; sz = str.size() / i; if (sz % 2) break; } int total = str.size() / sz; cout << total << endl; int c = 0; while (c != total) { deque<char> dq; if (c < odd.size()) dq.push_back(getchar(odd[c])), cnt[odd[c]]--; else { for (int i = 0; i <= 61; i++) { if (cnt[i]) { dq.push_back(getchar(i)); cnt[i]--; break; } } } for (int i = 0; i <= 61; i++) { while (cnt[i] >= 2 && dq.size() < sz) { dq.push_back(getchar(i)); dq.push_front(getchar(i)); cnt[i] -= 2; } } for (auto it = dq.begin(); it != dq.end(); it++) cout << *it; cout << ; c++; } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3,unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; mt19937 rnd(time(nullptr)); const int N = 1e5 + 5; unordered_set<int> g[N]; bool check(int v) { for (auto i : g[v]) for (auto j : g[v]) if (i != j && !g[i].count(j)) return false; cout << 2 n << v << ; for (auto i : g[v]) cout << i << ; cout << n ; return true; } void solve() { int n, m, k; cin >> n >> m >> k; for (int i = 1; i <= n; ++i) g[i].clear(); for (int i = 0; i < m; ++i) { int u, v; cin >> u >> v; g[u].insert(v), g[v].insert(u); } set<pair<int, int> > st; for (int i = 1; i <= n; ++i) { st.insert({g[i].size(), i}); } if ((long long)k * (k - 1) > 2 * m) { cout << -1 n ; return; } while (st.size()) { pair<int, int> v = *st.begin(); if (v.first >= k) break; if (v.first == k - 1 && check(v.second)) return; st.erase(st.begin()); for (auto to : g[v.second]) { st.erase({g[to].size(), to}); g[to].erase(v.second); st.insert({g[to].size(), to}); } } if (st.size()) { cout << 1 << st.size() << n ; for (auto v : st) cout << v.second << ; cout << n ; } else cout << -1 n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) solve(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBN_SYMBOL_V
`define SKY130_FD_SC_LS__SDFBBN_SYMBOL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long dot(complex<long long> c1, complex<long long> c2) { return imag(c1 * conj(c2)); } double dot(complex<double> c1, complex<double> c2) { return imag(c1 * conj(c2)); } long long point(complex<long long> c1, complex<long long> c2) { return real(c1 * conj(c2)); } double point(complex<double> c1, complex<double> c2) { return real(c1 * conj(c2)); } void solve() { long double n, pi2, alpha, res; pi2 = acos(0.0); cin >> n; alpha = pi2 * (n - 1.0) / n; res = tan(alpha); cout << res << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t, cases; cin >> cases; cout << fixed << setprecision(10); for (t = 0; t < cases; t++) { solve(); } }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_1_V
`define SKY130_FD_SC_LS__FAH_1_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fah_1 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fah_1 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; if (n == 5) { cout << YES n ; cout << 3 - 1 = 2 << n ; cout << 2 + 2 = 4 << n ; cout << 4 * 5 = 20 << n ; cout << 20 + 4 = 24 << n ; } else if (n < 4) cout << NO n ; else { cout << YES n ; if (n % 4 == 0) { cout << 1 * 2 = 2 << n ; cout << 3 * 4 = 12 << n ; cout << 2 * 12 = 24 << n ; for (int i = 1; i < n / 4; ++i) { cout << i * 4 + 1 << - << i * 4 + 2 << = -1 << n ; cout << i * 4 + 4 << - << i * 4 + 3 << = 1 << n ; cout << -1 + 1 = 0 << n ; cout << 24 + 0 = 24 << n ; } } else if (n % 4 == 2) { cout << 4 * 6 = 24 << n ; cout << 2 * 1 = 2 << n ; cout << 5 - 3 = 2 << n ; cout << 2 - 2 = 0 << n ; cout << 24 + 0 = 24 << n ; for (int i = 1; i < n / 4; ++i) { cout << i * 4 + 5 << - << i * 4 + 6 << = -1 << n ; cout << i * 4 + 4 << - << i * 4 + 3 << = 1 << n ; cout << -1 + 1 = 0 << n ; cout << 24 + 0 = 24 << n ; } } else if (n % 4 == 3) { cout << 4 * 6 = 24 << n ; cout << 2 * 1 = 2 << n ; cout << 3 - 2 = 1 << n ; cout << 7 - 5 = 2 << n ; cout << 2 - 1 = 1 << n ; cout << 24 * 1 = 24 << n ; for (int i = 1; i < n / 4; ++i) { cout << i * 4 + 4 << - << i * 4 + 5 << = -1 << n ; cout << i * 4 + 7 << - << i * 4 + 6 << = 1 << n ; cout << -1 + 1 = 0 << n ; cout << 24 + 0 = 24 << n ; } } else { cout << 4 * 6 = 24 << n ; cout << 2 * 1 = 2 << n ; cout << 3 - 2 = 1 << n ; cout << 7 - 5 = 2 << n ; cout << 2 - 1 = 1 << n ; cout << 9 - 8 = 1 << n ; cout << 1 * 1 = 1 << n ; cout << 24 * 1 = 24 << n ; for (int i = 1; i < n / 4 - 1; ++i) { cout << i * 4 + 8 << - << i * 4 + 9 << = -1 << n ; cout << i * 4 + 7 << - << i * 4 + 6 << = 1 << n ; cout << -1 + 1 = 0 << n ; cout << 24 + 0 = 24 << n ; } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111O_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A2111O_PP_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using vl = vector<ll>; using pll = pair<ll, ll>; using vll = vector<pll>; using MAP = map<ll, ll>; using sl = set<ll>; using sll = set<pll>; using MAPs = map<ll, sl>; using MAPv = map<ll, vl>; const ll inf = LLONG_MAX; const ll mod = 1e9 + 7; const ll N = 2e5 + 5; int dx8[] = {0, 1, 1, 1, 0, -1, -1, -1}, dy8[] = {1, 1, 0, -1, -1, -1, 0, 1}; int dx4[] = {0, 1, 0, -1}, dy4[] = {1, 0, -1, 0}; int n, a[N]; void MAIN() { cin >> n; vector<int> v; for (int i = 0; i < n; i++) cin >> a[i], v.push_back(a[i]); sort((v).begin(), (v).end()); int ind1 = 0, ind2 = 0, cnt = 0; for (int i = 0; i < n; i++) { if (a[i] != v[i]) { cnt++; if (!ind1) ind1 = i; else ind2 = i; } } if (cnt > 2) { cout << NO n ; return; } swap(a[ind1], a[ind2]); for (int i = 0; i < n - 1; i++) { if (a[i] > a[i + 1]) { cout << NO n ; return; } } cout << YES n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t = 1; while (t-- > 0) { MAIN(); } }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module gen_pipe
#(
parameter PIPE_WIDTH = 9'd32,
PIPE_DEPTH = 5'd4
)
(
input clk,
input [PIPE_WIDTH -1 :0] din,
output [PIPE_WIDTH -1 :0] dout
);
reg [PIPE_WIDTH - 1:0] pipe_reg [PIPE_DEPTH - 1:0];
reg [9:0] n;
always @(posedge clk) begin
for(n=(PIPE_DEPTH[9:0] - 10'h1); n!=10'h0; n=n-10'h1)
pipe_reg[n] <= pipe_reg[n-10'h1];
pipe_reg[0] <= din;;
end
assign dout = pipe_reg[PIPE_DEPTH - 1];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int sz = 2e5 + 10; int pr[sz], si[sz], ar[sz][3]; bool us[sz]; bool comp(int a, int b) { return ar[a][2] > ar[b][2]; } int find_se(int v) { if (pr[v] == v) return v; else { pr[v] = find_se(pr[v]); return pr[v]; } } void unite(int v, int v2) { if (v != v2) { if (si[v] < si[v2]) swap(v, v2); pr[v2] = v, si[v] += si[v2]; } } int main() { int n, m, an = 0; cin >> n >> m; int p[m]; for (int a = 0; a < n; a++) { pr[a] = a, si[a] = 1, us[a] = 0; } for (int a = 0; a < m; a++) { p[a] = a; for (int b = 0; b < 3; b++) scanf( %d , &ar[a][b]); ar[a][0]--, ar[a][1]--; } sort(p, p + m, comp); for (int a = 0; a < m; a++) { int i = p[a]; int l = find_se(ar[i][0]), r = find_se(ar[i][1]), va = ar[i][2]; if (l == r) { if (us[l] == 0) { us[l] = 1, an += va; } } else if (us[l] == 1 and us[r] == 0) { us[r] = 1, an += va; } else if (us[l] == 0 and us[r] == 1) { us[l] = 1, an += va; } else if (us[l] == 0 and us[r] == 0) { unite(l, r), an += va; } } cout << an; }
|
//Author: AnandRaj uux #include <bits/stdc++.h> using namespace std; typedef long long ll; typedef long double ld; typedef pair<int,int> pii; typedef vector<int> vi; typedef vector<vi> vvi; typedef vector<pii> vpii; typedef pair<ll,ll> pll; typedef vector<ll> vl; typedef vector<vl> vvl; typedef vector<pll> vpll; #define fastio ios_base::sync_with_stdio(0);cin.tie(0);cout.tie(0); #define test() int t;cin>>t;while(t--) #define all(v) v.begin(),v.end() #define prinp(p) cout<<p.first<< <<p.second<<endl #define prinv(V) for(auto v:V) cout<<v<< ;cout<<endl #define take(V,f,n) for(int in=f;in<f+n;in++) cin>>V[in] #define what(x) cerr<<#x<< = <<x<<endl #define KStest() int t,t1;cin>>t;t1=t;while(t--) #define KScout cout<< Case # <<t1-t<< : mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int MOD = 1e9+7,MAX = 1e6+5; const ll INF = 1e18+5; vvi A; bool can = true; vi TS; vi vis,inStack; void dfs(int x, int parent) { vis[x] = true; inStack[x] = true; for(auto v:A[x]) { if (vis[v] && inStack[v]) { can = false; return; } if(!vis[v]) { dfs(v, x); } } inStack[x] = false; TS.push_back(x); } int main() { int n,m,k; cin>>n>>m>>k; A.resize(n+1); vector<string> P(n+1); map<string,int> Sp; take(P,1,n); for(int i=1;i<=n;i++) Sp[P[i]] = i; vis.resize(n+1); inStack.resize(n+1); vector<int> MT(m+1); vector<string> S(m+1); for(int i=1;i<=m;i++) { cin>>S[i]>>MT[i]; set<string> X; X.insert( ); for(int j=0;j<k;j++) { set<string> XX; for(auto x:X) { XX.insert(x+ _ ); XX.insert(x+S[i][j]); } X = XX; } if(X.count(P[MT[i]])==0) {can = false;break;} for(auto x:X) { if(Sp.find(x)==Sp.end() || Sp[x]==MT[i]) continue; else { A[MT[i]].push_back(Sp[x]); } } } // for(int i=1;i<=n;i++) // { // prinv(A[i]); // } for(int i=1;i<=n;i++) { if(!vis[i]) dfs(i,-1); } if(can) { cout<< YES <<endl; reverse(all(TS)); prinv(TS); } else cout<< NO <<endl; }
|
#include <bits/stdc++.h> using namespace std; long long save[100005]; long long aa[100005]; int hihi[100005]; int main() { int n; scanf( %d , &n); memset(aa, 0, sizeof(aa)); memset(aa, 0, sizeof(aa)); int first = 0, second = 0, sum = 1; long long a; scanf( %I64d , &a); if (a != 1) { printf( -1 n ); return 0; } hihi[second] = 1; aa[second++] = 1; for (int i = 1; i < n; i++) { scanf( %I64d , &a); if (a == 1) hihi[second] = 1, aa[second++] = 1, sum = second; else if (a == aa[second] * 2) hihi[second]++, aa[second++] = a; else if (second != 0 && a == aa[second - 1] * 2) hihi[0]++, aa[0] = a, second = 1; else { save[first++] = a; } } if (first > sum) { printf( -1 n ); return 0; } int Min, Max = sum + 1; int add = first; for (int i = sum - 1; i >= 0 && add <= i + 1; i--) add += hihi[i], Min = i; long long v[100005]; while (Min < Max - 1) { memset(v, 0, sizeof(v)); int xx = 0; for (xx = 0; xx < first; xx++) v[xx] = save[xx]; int mid = (Max + Min) / 2; for (int i = mid; i < sum; i++) { for (long long j = 1; j <= aa[i]; j *= 2) v[xx++] = j, assert(xx < 100000); ; } sort(v, v + xx); reverse(v, v + xx); int ok = 1; for (int i = 0; i < xx; i++) { if (v[i] > aa[i] * 2) ok = 0; } if (ok) { Max = mid; } else { Min = mid; } } if (Min == sum) { printf( -1 n ); } else { printf( %d , Min + 1); for (int i = Min + 2; i <= sum; i++) printf( %d , i); } }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File : de3d_tc_tag_set.v
// Author : Frank Bruno
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module de3d_tc_tag_set
(
// Inputs
input de_clk, /* drawing engine clock */
input de_rstn, /* drawing engine reset */
input ee_s0_hit, /* load even, even set s0 */
input ee_s1_hit, /* load even, even set s1 */
input eo_s0_hit, /* load even, odd set s0 */
input eo_s1_hit, /* load even, odd set s1 */
input oe_s0_hit, /* load odd, even set s0 */
input oe_s1_hit, /* load odd, even set s1 */
input oo_s0_hit, /* load odd, odd set s0 */
input oo_s1_hit, /* load odd, odd set s1 */
input [4:0] ee_tag_adr_wr, /* set bit address even, even. */
input [4:0] eo_tag_adr_wr, /* set bit address even, odd. */
input [4:0] oe_tag_adr_wr, /* set bit address odd, even. */
input [4:0] oo_tag_adr_wr, /* set bit address odd, odd. */
input [4:0] ee_tag_adr_rd, /* set bit address even, even. */
input [4:0] eo_tag_adr_rd, /* set bit address even, odd. */
input [4:0] oe_tag_adr_rd, /* set bit address odd, even. */
input [4:0] oo_tag_adr_rd, /* set bit address odd, odd. */
// Outputs
output ee_lru, /* set bit for even, even. */
output eo_lru, /* set bit for even, odd. */
output oe_lru, /* set bit for odd, even. */
output oo_lru /* set bit for odd, odd. */
);
/* Registers ****************************************************/
reg [31:0] ee_set_reg; /* set bit for (even, even) */
reg [31:0] eo_set_reg; /* set bit for (even, odd) */
reg [31:0] oe_set_reg; /* set bit for (odd, even) */
reg [31:0] oo_set_reg; /* set bit for (odd, odd) */
assign ee_lru = ee_set_reg[ee_tag_adr_rd];
assign eo_lru = eo_set_reg[eo_tag_adr_rd];
assign oe_lru = oe_set_reg[oe_tag_adr_rd];
assign oo_lru = oo_set_reg[oo_tag_adr_rd];
wire [31:0] sel_ee;
wire [31:0] sel_eo;
wire [31:0] sel_oe;
wire [31:0] sel_oo;
assign sel_ee = 32'b1 << (ee_tag_adr_wr);
assign sel_eo = 32'b1 << (eo_tag_adr_wr);
assign sel_oe = 32'b1 << (oe_tag_adr_wr);
assign sel_oo = 32'b1 << (oo_tag_adr_wr);
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)ee_set_reg <= 0;
else if(ee_s0_hit)ee_set_reg <= ee_set_reg | sel_ee;
else if(ee_s1_hit)ee_set_reg <= ee_set_reg & ~sel_ee;
end
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)eo_set_reg <= 0;
else if(eo_s0_hit)eo_set_reg <= eo_set_reg | sel_eo;
else if(eo_s1_hit)eo_set_reg <= eo_set_reg & ~sel_eo;
end
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)oe_set_reg <= 0;
else if(oe_s0_hit)oe_set_reg <= oe_set_reg | sel_oe;
else if(oe_s1_hit)oe_set_reg <= oe_set_reg & ~sel_oe;
end
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)oo_set_reg <= 0;
else if(oo_s0_hit)oo_set_reg <= oo_set_reg | sel_oo;
else if(oo_s1_hit)oo_set_reg <= oo_set_reg & ~sel_oo;
end
endmodule
|
`timescale 1ns/10ps
`include "pipeconnect.h"
`define TARGET_LOG 0
`define READER_LOG 1
`define WRITER_LOG 1
/*
Notation:
_ low, 0
~ high, 1
/ posedge
\ negedge
. unknown,undetermined,unimportant
# valid data (held stable)
< changing
> --
*/
/*
Fasttarget presents the request address as the result data after one
cycle. Wait is never asserted.
WISHBONE - no wait states
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata _____________<#### D1 ####><#### D2 ####>____________________
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata ___________________________<#### D1 ####><#### D2 ####>______
PIPECONNECT - some wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_______________________________________
wait _____________/~~~~~~~~~~~~\________________________________________________
readdata _________________________________________<#### D1 ####><#### D2 ####>______
*/
module fasttarget // PIPECONNECT, no wait
(input wire clk,
input wire rst,
input wire `REQ req,
output reg `RES res);
parameter name = 1;
always @(posedge clk) begin
res`WAIT <= 0;
res`RD <= ~rst && req`R ? req`A : 0;
if (`TARGET_LOG & req`R)
$display("Target%1d", name);
end
endmodule
/*
PIPECONNECT - 1 wait state
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ##################>...........
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\/~~~~~~~~~~~~~~~~~~~~~~~~~~\___________
wait _____________/~~~~~~~~~~~~\______________/~~~~~~~~~~~~\____________________
readdata _________________________________________<#### D1 ####>______________<#### D2 ####>______
_~_~_~_~_~_
.AAAABBBB..
_~~~~~~~~__
_~~__~~____
_____aa__bb
*/
module slowtarget // PIPECONNECT, 1 wait
(input wire clk,
input wire rst,
input wire `REQ req,
output wire `RES res);
parameter name = 1;
reg [31:0] readData;
reg ready;
assign res`RD = readData;
assign res`WAIT = req`R & ~ready;
always @(posedge clk)
if (rst) begin
readData <= 0;
ready <= 0;
//$display("target in reset");
end else begin
if (`TARGET_LOG & req`R & ready)
$display("Target%1d", name);
readData <= ready ? req`A : 0;
ready <= req`R & ~ready;
//$display("target %d %d", ready, res`WAIT);
end
endmodule
/*
Simple master waits for a result before issuing new request
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock /~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ...<#####req 1###>...........................<#####req 2
read ___/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait ________________________________________________________
readdata ______________________<#############>___________________
*/
/*
Streaming master keeps one outstanding command
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#####req 1###>.............<#####req 2
read ________/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait _____________________________________________________________
readdata ___________________________<#############>___________________
*/
module reader
(input wire clk,
input wire rst,
output reg `REQ req,
input wire `RES res);
parameter name = 1;
reg [31:0] counter, data;
reg [31:0] dataExpect;
reg dataValid;
wire pause = ^counter[1:0];
always @(posedge clk)
if (rst) begin
counter <= name << 16;
req <= 0;
dataValid <= 0;
dataExpect <= 0;
end else begin
dataExpect <= data;
dataValid <= req`R & ~res`WAIT;
if (dataValid) begin
if (dataExpect != res`RD) begin
if (`READER_LOG)
$display("%6d init%1d got %x, expected %x !!! BAD!",
$time, name, res`RD, dataExpect);
end else begin
if (`READER_LOG)
$display("%6d init%1d got %x as expected", $time, name, res`RD);
end
end
if (~res`WAIT) begin
counter <= counter + name;
if (pause) begin
req`R <= 0;
end else begin
req`R <= 1;
req`A <= counter;
data <= counter;
if (`READER_LOG)
$display("%6d init%1d requests %x", $time, name, counter);
end
end else begin
if (`READER_LOG)
$display("%6d init%1d waits", $time, name);
end
end
endmodule
module writer
(input wire clk,
input wire rst,
output reg `REQ req,
input wire `RES res);
parameter name = 1;
reg [31:0] counter, data;
wire pause = ^counter[2:1];
always @(posedge clk)
if (rst) begin
counter <= name << 16;
req <= 0;
end else begin
if (~res`WAIT) begin
counter <= counter + name;
if (pause) begin
req`W <= 0;
end else begin
req`W <= 1;
req`A <= counter;
req`WD <= counter;
if (`WRITER_LOG)
$display("%6d writer%1d requests %x", $time, name, counter);
end
end else begin
if (`WRITER_LOG)
$display("%6d writer%1d waits", $time, name);
end
end
endmodule
module main();
reg rst, clk;
wire `REQ req, req1, req2, reqA, reqB;
wire `RES res, res1, res2, resA, resB;
wire [31:0] addr1 = req1`A;
wire read1 = req1`R;
wire wai1 = res1`WAIT;
wire [31:0] data1 = res1`RD;
wire [31:0] addr2 = req2`A;
wire read2 = req2`R;
wire wai2 = res2`WAIT;
wire [31:0] data2 = res2`RD;
reader #(1) reader1(clk, rst, req1, res1);
writer #(2) writer2(clk, rst, req2, res2);
slowtarget #(1) target1(clk, rst, reqA, resA);
slowtarget #(2) target2(clk, rst, reqB, resB);
xbar2x2 xbar(clk,
addr1[2], req1, res1,
addr2[2], req2, res2,
reqA, resA,
reqB, resB);
always # 5 clk = ~clk;
initial begin
$monitor(// "%d%d %4d 1: %x %d %d %x 2: %x %d %d %x",
"%4d 1: %x %d %d %x 2: %x %d %d %x",
// rst, clk,
$time,
addr1, read1, wai1, data1,
addr2, read2, wai2, data2);
clk = 1;
rst = 1;
#15 rst = 0;
#20000 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool check(int left, int right, int m) { left ^= right; if (left > m) return false; else return true; } void solve() { int n, m; cin >> n >> m; if (n > m) { cout << 0 << n ; return; } int ans = 0; for (int i = 0; i < 31; ++i) { if ((1 << i) & n) continue; else { ans ^= (1 << i); if ((ans ^ n) > m) break; } } for (int i = 30; i >= 0; --i) { if ((1 << i) & ans) { int num = ans ^ (1 << i); if ((num ^ n) > m) { ans ^= (1 << i); } } } cout << ans << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int test; cin >> test; while (test--) { solve(); } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:24:41 04/15/2016
// Design Name: Alejandro Morales
// Module Name: control_digitos
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module control_digitos_1
(
input [7:0] estado,
input [3:0]RG1_Dec,
input [3:0]RG2_Dec,
input [3:0]RG3_Dec,
input escribiendo,
input en_out,
input wire clk,
input wire [3:0] dig0_Dec,
input [3:0] direccion,
output reg [3:0] dig_Dec_Ho, dig_Dec_min, dig_Dec_seg, dig_Dec_mes, dig_Dec_dia, dig_Dec_an, dig_Dec_Ho_Ti, dig_Dec_min_Ti, dig_Dec_seg_Ti
);
always @(posedge clk)
if (~escribiendo)
if (en_out)
case (direccion)
4'b0000://horas
dig_Dec_Ho<=dig0_Dec;
4'b0001://minutos
dig_Dec_min<=dig0_Dec;
4'b0010://segundos
dig_Dec_seg<=dig0_Dec;
4'b0011://meses
dig_Dec_mes<=dig0_Dec;
4'b0100://dias
dig_Dec_dia<=dig0_Dec;
4'b0101://años
dig_Dec_an<=dig0_Dec;
4'b0110://Horas timer
begin
if (dig0_Dec==4'b1111)
dig_Dec_Ho_Ti<=4'b0000;
else
dig_Dec_Ho_Ti<=dig0_Dec;
end
4'b0111://minutos timer
dig_Dec_min_Ti<=dig0_Dec;
4'b1000: //segundos timer
dig_Dec_seg_Ti<=dig0_Dec;
default:
begin
dig_Dec_Ho<=dig_Dec_Ho;
dig_Dec_min<=dig_Dec_min;
dig_Dec_seg<=dig_Dec_seg;
dig_Dec_mes<=dig_Dec_mes;
dig_Dec_an<=dig_Dec_an;
dig_Dec_dia<=dig_Dec_dia;
dig_Dec_Ho_Ti<=dig_Dec_Ho_Ti;
dig_Dec_min_Ti<=dig_Dec_min_Ti;
dig_Dec_seg_Ti<=dig_Dec_seg_Ti;
end
endcase
else
begin
dig_Dec_Ho<=dig_Dec_Ho;
dig_Dec_min<=dig_Dec_min;
dig_Dec_seg<=dig_Dec_seg;
dig_Dec_mes<=dig_Dec_mes;
dig_Dec_dia<=dig_Dec_dia;
dig_Dec_an<=dig_Dec_an;
dig_Dec_Ho_Ti<=dig_Dec_Ho_Ti;
dig_Dec_min_Ti<=dig_Dec_min_Ti;
dig_Dec_seg_Ti<=dig_Dec_seg_Ti;
end
else
case (estado)
8'h7d:
begin
if (direccion==4'b0011)
dig_Dec_mes<=RG2_Dec;
else
if (direccion==4'b0100)
dig_Dec_dia<=RG1_Dec;
else
if (direccion==4'b0101)
dig_Dec_an<=RG3_Dec;
else
begin
dig_Dec_mes<=dig_Dec_mes;
dig_Dec_dia<=dig_Dec_dia;
dig_Dec_an<=dig_Dec_an;
end
end
8'h6c:
begin
if (direccion==4'b0000)
dig_Dec_Ho<=RG3_Dec;
else
if (direccion==4'b0001)
dig_Dec_min<=RG2_Dec;
else
if (direccion==4'b0010)
dig_Dec_seg<=RG1_Dec;
else
begin
dig_Dec_Ho<=dig_Dec_Ho;
dig_Dec_min<=dig_Dec_min;
dig_Dec_seg<=dig_Dec_seg;
end
end
8'h75:
begin
if (direccion==4'b0110)
dig_Dec_Ho_Ti<=RG3_Dec;
else
if (direccion==4'b0111)
dig_Dec_min_Ti<=RG2_Dec;
else
if (direccion==4'b1000)
dig_Dec_seg_Ti<=RG1_Dec;
else
begin
dig_Dec_Ho_Ti<=dig_Dec_Ho_Ti;
dig_Dec_min_Ti<=dig_Dec_min_Ti;
dig_Dec_seg_Ti<=dig_Dec_seg_Ti;
end
end
default:
begin
dig_Dec_Ho<=dig_Dec_Ho;
dig_Dec_min<=dig_Dec_min;
dig_Dec_seg<=dig_Dec_seg;
dig_Dec_mes<=dig_Dec_mes;
dig_Dec_dia<=dig_Dec_dia;
dig_Dec_an<=dig_Dec_an;
dig_Dec_Ho_Ti<=dig_Dec_Ho_Ti;
dig_Dec_min_Ti<=dig_Dec_min_Ti;
dig_Dec_seg_Ti<=dig_Dec_seg_Ti;
end
endcase
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : cmm_intr.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
`define FFD 1
module cmm_intr (
signaledint, // Outputs
intr_req_valid,
intr_req_type,
intr_rdy,
cfg_interrupt_n, // Inputs
cfg_interrupt_assert_n,
cfg_interrupt_di,
cfg_interrupt_mmenable,
msi_data,
intr_vector,
command,
msi_control,
msi_laddr,
msi_haddr,
intr_grant,
cfg,
rst,
clk
) /* synthesis syn_hier ="hard"*/;
//This indicates (to Status register) that a Legacy Interrupt has been sent
output signaledint; // Outputs
output intr_req_valid;
output [1:0] intr_req_type;
output intr_rdy;
output [7:0] intr_vector;
input cfg_interrupt_assert_n;
input [7:0] cfg_interrupt_di;
input [15:0] msi_data;
input [2:0] cfg_interrupt_mmenable;
input cfg_interrupt_n; // Inputs
input [15:0] command;
input [15:0] msi_control;
input [31:0] msi_laddr;
input [31:0] msi_haddr;
input intr_grant;
input [1023:0] cfg;
input rst;
input clk;
reg signaledint; // Outputs
wire intr_rdy;
reg q_intr_req_valid;
reg [1:0] q_intr_req_type;
// notes
// msi_control[0] is msi_mode
// 64 bit address capable bit 7 of message control
// This design supports only one message
// command [10] is interrupt disable
parameter [1:0] IDLE = 2'b00;
parameter [1:0] SEND_MSI = 2'b01;
parameter [1:0] SEND_ASSERT = 2'b10;
parameter [1:0] SEND_DEASSERT = 2'b11;
wire msi_64;
wire msi_mode;
wire intx_mode;
wire bus_master_en;
wire intr_req;
reg allow_int;
reg [1:0] state;
reg [1:0] next_state;
assign msi_64 = msi_control[7] && (msi_haddr != 0);
assign msi_mode = msi_control[0];
assign intx_mode = ~command[10];
assign bus_master_en = command[2];
assign intr_req = !cfg_interrupt_n && allow_int;
reg intr_req_q = 0;
reg intr_rdyx = 0;
reg cfg_interrupt_assert_n_q = 1;
reg [7:0] cfg_interrupt_di_q = 0;
reg [7:0] intr_vector = 0;
always @(posedge clk or posedge rst) begin
if (rst) begin
intr_req_q <= #`FFD 1'b0;
allow_int <= #`FFD 1'b0;
intr_rdyx <= #`FFD 1'b0;
cfg_interrupt_assert_n_q <= #`FFD 1'b1;
end else begin
intr_req_q <= #`FFD intr_req;
allow_int <= #`FFD ((msi_mode && bus_master_en) || (!msi_mode && intx_mode));
intr_rdyx <= #`FFD (state != IDLE) && intr_grant;
cfg_interrupt_assert_n_q <= #`FFD cfg_interrupt_assert_n;
end
end
always @(posedge clk) begin
cfg_interrupt_di_q <= #`FFD cfg_interrupt_di;
end
always @(posedge clk) begin
//This override will permit the user to alter all 8 MSI bits
if (cfg[467]) begin
intr_vector <= #`FFD cfg_interrupt_di_q[7:0];
end else if (intr_req_q) begin
casez ({msi_mode,cfg_interrupt_mmenable})
4'b0???: intr_vector <= #`FFD cfg_interrupt_di_q[7:0];
4'b1000: intr_vector <= #`FFD msi_data[7:0];
4'b1001: intr_vector <= #`FFD {msi_data[7:1],cfg_interrupt_di_q[0]};
4'b1010: intr_vector <= #`FFD {msi_data[7:2],cfg_interrupt_di_q[1:0]};
4'b1011: intr_vector <= #`FFD {msi_data[7:3],cfg_interrupt_di_q[2:0]};
4'b1100: intr_vector <= #`FFD {msi_data[7:4],cfg_interrupt_di_q[3:0]};
4'b1101: intr_vector <= #`FFD {msi_data[7:5],cfg_interrupt_di_q[4:0]};
default: intr_vector <= #`FFD {msi_data[7:5],cfg_interrupt_di_q[4:0]};
endcase
end
end
wire intr_req_valid = q_intr_req_valid;
wire [1:0] intr_req_type = q_intr_req_type;
reg intr_rdy_q;
always @(posedge clk) begin
if (rst) begin
intr_rdy_q <= #`FFD 0;
end else begin
intr_rdy_q <= #`FFD intr_rdy;
end
end
wire send_assert;
wire send_deassert;
wire send_msi;
assign send_assert = !msi_mode && intr_req_q && ~cfg_interrupt_assert_n_q &&
~(intr_rdy || intr_rdy_q);
assign send_deassert= !msi_mode && intr_req_q && cfg_interrupt_assert_n_q &&
~(intr_rdy || intr_rdy_q);
assign send_msi = msi_mode && intr_req_q &&
~(intr_rdy || intr_rdy_q);
always @(posedge clk) begin
if (rst) begin
state <= #`FFD IDLE;
end
else begin
state <= #`FFD next_state;
end
end
always @*
begin
next_state = IDLE;
signaledint = 0;
q_intr_req_type = 0;
q_intr_req_valid = 0;
case (state) // synthesis full_case parallel_case
IDLE : begin
q_intr_req_type = 0;
q_intr_req_valid = 0;
signaledint = 0;
if (send_msi) begin
next_state = SEND_MSI;
end
else if (send_assert) begin
next_state = SEND_ASSERT;
end
else if (send_deassert) begin
next_state = SEND_DEASSERT;
end
else begin
next_state = IDLE;
end
end
SEND_MSI : begin
q_intr_req_type = msi_64 ? 2'b11 : 2'b10;
if (intr_grant) begin
q_intr_req_valid = 0;
next_state = IDLE;
signaledint = 0;
end
else begin
q_intr_req_valid = 1;
next_state = SEND_MSI;
signaledint = 0;
end
end
SEND_ASSERT : begin
q_intr_req_type = 2'b00;
if (intr_grant) begin
q_intr_req_valid = 0;
next_state = IDLE;
signaledint = 1;
end
else begin
q_intr_req_valid = 1;
next_state = SEND_ASSERT;
signaledint = 0;
end
end
SEND_DEASSERT : begin
q_intr_req_type = 2'b01;
if (intr_grant) begin
q_intr_req_valid = 0;
next_state = IDLE;
signaledint = 1;
end
else begin
q_intr_req_valid = 1;
next_state = SEND_DEASSERT;
signaledint = 0;
end
end
endcase
end
assign intr_rdy = intr_rdyx;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTN_SYMBOL_V
`define SKY130_FD_SC_LS__DLXTN_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTN_SYMBOL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
module offset_to_mask
#(parameter C_MASK_SWAP = 1,
parameter C_MASK_WIDTH = 4)
(
input OFFSET_ENABLE,
input [clog2s(C_MASK_WIDTH)-1:0] OFFSET,
output [C_MASK_WIDTH-1:0] MASK
);
`include "functions.vh"
reg [7:0] _rMask,_rMaskSwap;
wire [3:0] wSelect;
assign wSelect = {OFFSET_ENABLE,{{(3-clog2s(C_MASK_WIDTH)){1'b0}},OFFSET}};
assign MASK = (C_MASK_SWAP)? _rMaskSwap[7 -: C_MASK_WIDTH]: _rMask[C_MASK_WIDTH-1:0];
always @(*) begin
_rMask = 0;
_rMaskSwap = 0;
/* verilator lint_off CASEX */
casex(wSelect)
default: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b1111_1111;
end
4'b1000: begin
_rMask = 8'b0000_0001;
_rMaskSwap = 8'b1111_1111;
end
4'b1001: begin
_rMask = 8'b0000_0011;
_rMaskSwap = 8'b0111_1111;
end
4'b1010: begin
_rMask = 8'b0000_0111;
_rMaskSwap = 8'b0011_1111;
end
4'b1011: begin
_rMask = 8'b0000_1111;
_rMaskSwap = 8'b0001_1111;
end
4'b1100: begin
_rMask = 8'b0001_1111;
_rMaskSwap = 8'b0000_1111;
end
4'b1101: begin
_rMask = 8'b0011_1111;
_rMaskSwap = 8'b0000_0111;
end
4'b1110: begin
_rMask = 8'b0111_1111;
_rMaskSwap = 8'b0000_0011;
end
4'b1111: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b0000_0001;
end
endcase // casez ({OFFSET_MASK,OFFSET})
/* verilator lint_on CASEX */
end
endmodule
|
`timescale 1ns / 100ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:41:52 05/03/2020
// Design Name: tipi_top
// Module Name: C:/Users/jgpar/Documents/TI99/TIPI/VS-TIPI-CPLD/vs-tipi-top-tb.v
// Project Name: vs-tipi
// Target Device: xc95144xl
// Tool versions: ISE 14.1
// Description:
//
// Verilog Test Fixture created by ISE for module: tipi_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module vs_tipi_top_tb;
// Inputs
reg [0:3] crub;
reg r_clk;
reg r_cd;
reg r_dout;
reg r_le;
reg r_rt;
reg ti_cruclk;
reg ti_dbin;
reg ti_memen;
reg ti_we;
reg ti_ph3;
reg [0:15] ti_a;
// Outputs
wire led0;
wire db_dir;
wire db_en;
wire dsr_b0;
wire dsr_b1;
wire dsr_en;
wire dram_a0;
wire dram_en;
wire r_din;
wire r_reset;
wire ti_cruin;
wire ti_extint;
// Bidirs
wire [0:7] tp_d;
// Instantiate the Unit Under Test (UUT)
tipi_top uut (
.led0(led0),
.crub(crub),
.db_dir(db_dir),
.db_en(db_en),
.dsr_b0(dsr_b0),
.dsr_b1(dsr_b1),
.dsr_en(dsr_en),
.dram_a0(dram_a0),
.dram_en(dram_en),
.r_clk(r_clk),
.r_cd(r_cd),
.r_dout(r_dout),
.r_le(r_le),
.r_rt(r_rt),
.r_din(r_din),
.r_reset(r_reset),
.ti_cruclk(ti_cruclk),
.ti_dbin(ti_dbin),
.ti_memen(ti_memen),
.ti_we(ti_we),
.ti_ph3(ti_ph3),
.ti_cruin(ti_cruin),
.ti_extint(ti_extint),
.ti_a(ti_a),
.tp_d(tp_d)
);
initial begin
// Initialize Inputs
crub = 4'b1110;
r_clk = 0;
r_cd = 0;
r_dout = 0;
r_le = 0;
r_rt = 0;
ti_cruclk = 0;
ti_dbin = 0;
ti_memen = 0;
ti_we = 0;
ti_ph3 = 0;
ti_a = 0;
end
// always
// #10 ti_ph3 = !ti_ph3;
// always
// #10 ti_cruclk = !ti_cruclk;
initial begin
// Wait 100 ns for global reset to finish, set to rest state
#100
assign ti_a = 16'h0000;
assign ti_memen = 1;
assign ti_we = 1;
// set CRU bits
#10
assign ti_cruclk = 1;
assign ti_a = 16'h1101; // set CRU bit 0 to 0 on CRUCLK
#10
assign ti_cruclk = 0;
#10
assign ti_cruclk = 1;
assign ti_a = 16'h1103; // set CRU bit 1 to 0
#10
assign ti_cruclk = 0;
#10
assign ti_cruclk = 1;
assign ti_a = 16'h1105; // set CRU bit 2 to 0
#10
assign ti_cruclk = 0;
#10
assign ti_cruclk = 1;
assign ti_a = 16'h1107; // set CRU bit 3 to 0
#10
assign ti_cruclk = 0;
// read CRU bit
assign ti_ph3 = 1;
#10
assign ti_a = 16'h1100; // Read CRU bit 0 on CRU IN
#10
assign ti_ph3 = 0; // clock in read
// read addresses
assign ti_memen = 0;
assign ti_dbin = 1;
#25
assign ti_a = 16'h0000; // invald address
#25
assign ti_a = 16'h2000; // DRAM address
#25
assign ti_a = 16'h3FFF; // DRAM address
#25
assign ti_a = 16'h4000; // DSR address
#25
assign ti_a = 16'h5FF7; // DSR address
#25
assign ti_a = 16'h5FF9; // CRU bit 0 address
#25
assign ti_a = 16'h5FFB; // CRU bit 0 address
#25
assign ti_a = 16'h5FFD; // CRU bit 0 address
#25
assign ti_a = 16'h5FFF; // CRU bit 0 address
#25
assign ti_a = 16'h6000;
#25
assign ti_a = 16'h9FFF;
#25
assign ti_a = 16'hA000;
#25
assign ti_a = 16'hBFFF;
#25
assign ti_a = 16'hC000;
#25
assign ti_a = 16'hDFFF;
#25
assign ti_a = 16'hE000;
#25
assign ti_a = 16'hFFFF;
#50
assign ti_a = 16'hFFFF; // idle state
assign ti_dbin = 0;
assign ti_memen = 1;
assign ti_we = 1;
// write states
#25
assign ti_a = 16'hFFFF;
assign ti_dbin = 0;
assign ti_memen = 0;
assign ti_we = 1;
#25
assign ti_a = 16'hFFFF;
assign ti_dbin = 0;
assign ti_memen = 0;
assign ti_we = 0;
#25
assign ti_a = 16'hFFFF;
assign ti_dbin = 0;
assign ti_memen = 0;
assign ti_we = 1;
#25
assign ti_a = 16'hFFFF; // idle state
assign ti_dbin = 0;
assign ti_memen = 1;
assign ti_we = 1;
// $monitor("At ",%time, dram_en, dram_a0, db_en, db_dir, led0, dsr_en, dsr_b0, dsr_b1)
end
endmodule
|
// $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
//====================================================================
module CmpEng (/*AUTOARG*/);
input clk;
input reset_l;
// ****************************************************************
/*AUTOREG*/
/*AUTOWIRE*/
// ********* Prefetch FSM definitions ****************************
reg [3:0] m_cac_state_r;
reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
reg m_wid1_r;
reg [2:0] m_wid3_r;
reg [5:2] m_wid4_r_l;
logic [4:1] logic_four;
logic [PARAM-1:0] paramed;
`define M 2
`define L 1
parameter MS = 2;
parameter LS = 1;
reg [MS:LS] m_param_r;
reg [`M:`L] m_def2_r;
always @ (posedge clk) begin
if (~reset_l) begin
m_cac_state_r <= CAC_IDLE;
m_cac_sel_r <= CSEL_PF;
/*AUTORESET*/
end
else begin
m_wid1_r <= 0;
m_wid3_r <= 0;
m_wid4_r_l <= 0;
m_param_r <= 0;
m_def2_r <= 0;
logic_four <= 4;
paramed <= 1;
end
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// verilog-auto-sense-defines-constant: t
// verilog-auto-reset-widths: t
// verilog-active-low-regexp: "_l$"
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_1_V
`define SKY130_FD_SC_LP__A21OI_1_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21oi_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, b, one, two; string a; one = 0; two = 0; cin >> n >> a; for (b = 0; b < n; b++) { if (a[b] == 1 ) { one++; } else { two++; } } if (one > two) { cout << one - two; } else { cout << two - one; } }
|
`timescale 1ns/1ns
// TB specific - UNUSED
module ser_video(
input nRESET,
input CLK_SERVID,
input CLK_6MB,
input [6:0] VIDEO_R,
input [6:0] VIDEO_G,
input [6:0] VIDEO_B,
output VIDEO_R_SER,
output VIDEO_G_SER,
output VIDEO_B_SER,
output VIDEO_CLK_SER,
output VIDEO_LAT_SER
);
reg [6:0] R_SR;
reg [6:0] G_SR;
reg [6:0] B_SR;
reg [2:0] BIT_CNT;
reg [1:0] VIDEO_LOAD;
assign VIDEO_CLK_SER = CLK_SERVID;
assign VIDEO_LAT_SER = ~|{BIT_CNT[2:1]};
assign VIDEO_R_SER = R_SR[6];
assign VIDEO_G_SER = G_SR[6];
assign VIDEO_B_SER = B_SR[6];
// Pix --------------------------------================================...
// 6MB |'''''''''''''''|_______________|'''''''''''''''|_______________...
// 48M '|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|...
// 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
// LAT _|'''''''|_______________________|'''''''|_______________________...
// CNT -0000111122223333444455556666777700001111222233334444555566667777
always @(negedge CLK_SERVID)
begin
if (!nRESET)
begin
R_SR <= 7'b0000000; // Clear SRs
G_SR <= 7'b0000000;
B_SR <= 7'b0000000;
BIT_CNT <= 3'b000;
end
else
begin
VIDEO_LOAD <= {VIDEO_LOAD[0], CLK_6MB};
if (VIDEO_LOAD == 2'b01) // Rising edge of CLK_6MB
begin
R_SR <= VIDEO_R; // Load SRs
G_SR <= VIDEO_G;
B_SR <= VIDEO_B;
BIT_CNT <= 3'b000;
end
else
begin
R_SR <= {R_SR[5:0], 1'b0}; // Shift
G_SR <= {G_SR[5:0], 1'b0};
B_SR <= {B_SR[5:0], 1'b0};
BIT_CNT <= BIT_CNT + 1'b1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { float a1, b1, c1, a2, b2, c2; cin >> a1 >> b1 >> c1 >> a2 >> b2 >> c2; if (!b1 && !b2) { if ((!a1 && c1) || (!a1 && c2)) { cout << 0 << endl; return 0; } if ((!c1 && !c2) || (!a1 && !a2) || c1 / a1 == c2 / a2) { cout << -1 << endl; return 0; } else { cout << 0 << endl; return 0; } } else if ((!b1 && !a1 && !c1) || (!b2 && !a2 && !c2)) { cout << -1 << endl; return 0; } else if ((!b1 && !a1) || (!b2 && !a2)) { cout << 0 << endl; return 0; } else if (!b1 || !b2) { cout << 1 << endl; return 0; } if (a1 / b1 == a2 / b2 && c1 / b1 == c2 / b2) cout << -1 << endl; else if (a1 / b1 == a2 / b2) cout << 0 << endl; else cout << 1 << endl; return 0; }
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2017 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable. tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_iff :
forall A B:Prop, decidable A -> decidable B ->
~ (A <-> B) -> (A /\ ~ B) \/ (~ A /\ B).
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(* Functional relations on decidable co-domains are decidable *)
Theorem dec_functional_relation :
forall (X Y : Type) (A:X->Y->Prop), (forall y y' : Y, decidable (y=y')) ->
(forall x, exists! y, A x y) -> forall x y, decidable (A x y).
Proof.
intros X Y A Hdec H x y.
destruct (H x) as (y',(Hex,Huniq)).
destruct (Hdec y y') as [->|Hnot]; firstorder.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
#include <bits/stdc++.h> using namespace std; const int maxx = 5e5 + 7; long long a[maxx], prime[maxx], cnt[maxx], sum, tedad; bool mark[maxx]; int main() { int n, q; cin >> n >> q; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 2; i < maxx; i++) { if (prime[i] == 0) for (int j = i; j < maxx; j += i) prime[j] = i; } while (q--) { int ind, adad, ans = 0; cin >> ind; ind--; adad = a[ind]; vector<int> v; while (adad > 1) { int p = prime[adad]; v.push_back(p); while (adad % p == 0) adad /= p; } int sz = (int)v.size(); for (int mask = 0; mask < (1 << sz); mask++) { if (!mark[ind]) { int t = 1; for (int i = 0; i < sz; i++) if ((mask >> i) & 1) t *= v[i]; if (__builtin_popcount(mask) % 2 == 0) ans += cnt[t]; else ans -= cnt[t]; cnt[t]++; } else { int t = 1; for (int i = 0; i < sz; i++) if ((mask >> i) & 1) t *= v[i]; cnt[t]--; if (__builtin_popcount(mask) % 2 == 0) ans += cnt[t]; else ans -= cnt[t]; } } if (!mark[ind]) { mark[ind] = true; sum += ans; tedad++; } else { mark[ind] = false; sum -= ans; tedad--; } cout << sum << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } int res[101] = {0}; for (int i = 0; i < n; i++) { res[arr[i]]++; } int cnt[101] = {0}; for (int i = 0; i < 101; i++) { if (res[i] >= 1) { res[i]--; cnt[i]++; } } int f, s; for (int i = 0; i < 101; i++) { if (res[i] == 0) { f = i; break; } } for (int i = 0; i < 101; i++) { if (cnt[i] == 0) { s = i; break; } } cout << f + s << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int N = 1010; int dp[N][N][2]; int bits[N]; int t, k; long long dfs(int len, int pos, int num, bool mark) { int maxx; long long sum; if (!len) { if (num == 1) { return true; } else { return false; } } if (!mark && dp[len][pos][num] != -1) { return dp[len][pos][num]; } if (mark) { maxx = bits[len]; } else { maxx = 9; } sum = 0; for (int i = 0; i <= maxx; i++) { if (i == 4 || i == 7) { sum += dfs(len - 1, len, (pos && pos - len <= k) | num, mark && i == maxx); } else { sum += dfs(len - 1, pos, num, mark && i == maxx); } } sum %= MOD; if (!mark) { dp[len][pos][num] = sum; } return sum; } long long f(string s) { int len; len = 0; for (int i = s.size() - 1; i >= 0; i--) { len++; bits[len] = s[i] - 0 ; } return dfs(len, 0, 0, 1); } bool check(string &s) { int p; p = 0; for (int i = 1; i <= s.size(); i++) { if (s[i - 1] == 4 || s[i - 1] == 7 ) { if (!p || i - p > k) { p = i; } else if (i - p <= k) { return true; } } } return false; } int main() { string l, r; long long ans; while (scanf( %d%d , &t, &k) == 2) { memset(dp, -1, sizeof(dp)); for (int i = 0; i < t; i++) { cin >> l >> r; ans = f(r) - f(l) + (check(l) ? 1 : 0); printf( %lld n , (ans % MOD + MOD) % MOD); } } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:64777216 ) using namespace std; const long long maxn = 100001; const long long maxk = 200001; const long long maxx = 10001; const long long secret_number = 87468267; const long long inf = 1e18; const int iinf = 2147483647 / 2; const double pi = 3.141592653589793238462643383279502884; const double eps = 1e-7; const string something_very_long = aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaa ; const string govno = g ; const int maxp = 101; int n, p, q; int pr[maxp]; int main() { cin.sync_with_stdio(0); cin >> n >> p >> q; string s; cin >> s; for (int i = 0; i < maxp; ++i) pr[i] = -2; pr[0] = 0; queue<int> qq; qq.push(0); while (!qq.empty()) { int cur = qq.front(); qq.pop(); if ((cur + p <= s.length()) && (pr[cur + p] == -2)) pr[cur + p] = cur, qq.push(cur + p); if ((cur + q <= s.length()) && (pr[cur + q] == -2)) pr[cur + q] = cur, qq.push(cur + q); } stack<string> v; int cur = s.length(); if (pr[cur] == -2) { cout << -1; return 0; } while (true) { if (cur != 0) { v.push(s.substr(pr[cur], cur - pr[cur])); cur = pr[cur]; } else break; } cout << v.size() << n ; while (!v.empty()) { string aa = v.top(); v.pop(); cout << aa << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int n = s.length(); for (int i = 1; i < n - 1; i++) if (s[i] == s[i - 1] && s[i] == s[i + 1]) { if (s[i] == a ) s[i] = b ; else s[i] = a ; } for (int i = 1; i < n; i++) if (s[i] == s[i - 1]) { if (s[i] == a ) { if (i != n - 1 && s[i + 1] != b ) s[i] = b ; else s[i] = c ; } else if (s[i + 1] != a ) s[i] = a ; else if (s[i] != b ) s[i] = b ; else s[i] = c ; } cout << s; }
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet MAC/PHY combination
*/
module eth_mac_phy_10g_tx #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter PTP_TAG_WIDTH = 16,
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
output wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag,
output wire m_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH * 32 != DATA_WIDTH) begin
$error("Error: HDR_WIDTH must be equal to DATA_WIDTH/32");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_tx_data;
wire [HDR_WIDTH-1:0] encoded_tx_hdr;
axis_baser_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_ENABLE(PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.USER_WIDTH(USER_WIDTH)
)
axis_baser_tx_inst (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.ptp_ts(ptp_ts),
.m_axis_ptp_ts(m_axis_ptp_ts),
.m_axis_ptp_ts_tag(m_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow),
.ifg_delay(ifg_delay)
);
eth_phy_10g_tx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE)
)
eth_phy_10g_tx_if_inst (
.clk(clk),
.rst(rst),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
`resetall
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: fbfifo.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
`timescale 1ns/10ps
module fbfifo (
data,
wren,
wraddress,
rdaddress,
clock,
q);
input [31:0] data;
input wren;
input [5:0] wraddress;
input [5:0] rdaddress;
input clock;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
parameter debug = 0;
always @(posedge clock) if (debug) begin
$display("fbfifo rdaddress %x -> %x", rdaddress, sub_wire0);
if (wren)
$display("fbfifo wraddress %x <- %x", wraddress, data);
end
altsyncram altsyncram_component (
.clocken0(1),
.clock0 (clock),
.address_a (wraddress),
.address_b (rdaddress),
.wren_a (wren),
.byteena_a (~0),
.data_a (data),
.q_b (sub_wire0));
defparam
altsyncram_component.intended_device_family = "Cyclone",
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.width_a = 32,
altsyncram_component.widthad_a = 6,
altsyncram_component.numwords_a = 64,
altsyncram_component.width_b = 32,
altsyncram_component.widthad_b = 6,
altsyncram_component.numwords_b = 64,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.wrcontrol_aclr_a = "NONE",
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.ram_block_type = "AUTO";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL wraddress[5..0]
// Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL rdaddress[5..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0
// Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
module vcache_blocking
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(id_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(dma_data_width_p)
//, parameter string rom_filename_lp =
, parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p)
)
(
input clk_i
, input reset_i
, output logic cache_v_o // cache request processed
, output logic [dma_pkt_width_lp-1:0] dma_pkt_o
, output logic dma_pkt_v_o
, input dma_pkt_yumi_i
, input [dma_data_width_p-1:0] dma_data_i
, input dma_data_v_i
, output logic dma_data_ready_o
, output logic [dma_data_width_p-1:0] dma_data_o
, output logic dma_data_v_o
, input dma_data_yumi_i
, output time first_access_time_o
, output integer load_count_o
, output integer store_count_o
, output logic done_o
);
// trace replay
typedef struct packed {
logic[1:0] op;
logic [addr_width_p-1:0] addr;
logic [data_width_p-1:0] data;
} payload_s;
localparam payload_width_lp = $bits(payload_s);
localparam rom_addr_width_lp = 20;
logic tr_v_lo;
payload_s tr_data_lo;
logic tr_yumi_li;
logic [rom_addr_width_lp-1:0] rom_addr;
logic [payload_width_lp+4-1:0] rom_data;
logic tr_done_lo;
bsg_trace_replay #(
.payload_width_p(payload_width_lp)
,.rom_addr_width_p(rom_addr_width_lp)
) tr0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(1'b1)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(tr_done_lo)
,.error_o()
);
// test rom
bsg_nonsynth_test_rom #(
.filename_p(`BSG_STRINGIFY(`TRACE))
,.data_width_p(payload_width_lp+4)
,.addr_width_p(rom_addr_width_lp)
) trom0 (
.addr_i(rom_addr)
,.data_o(rom_data)
);
// the vcache
`declare_bsg_cache_pkt_s(addr_width_p,data_width_p);
bsg_cache_pkt_s cache_pkt;
logic cache_pkt_v_li;
logic cache_pkt_ready_lo;
bsg_cache #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
,.dma_data_width_p(dma_data_width_p)
) vcache (
.clk_i(clk_i)
,.reset_i(reset_i)
,.cache_pkt_i(cache_pkt)
,.v_i(cache_pkt_v_li)
,.ready_o(cache_pkt_ready_lo)
,.data_o()
,.v_o(cache_v_o)
,.yumi_i(cache_v_o) // accept right away
,.dma_pkt_o(dma_pkt_o)
,.dma_pkt_v_o(dma_pkt_v_o)
,.dma_pkt_yumi_i(dma_pkt_yumi_i)
,.dma_data_i(dma_data_i)
,.dma_data_v_i(dma_data_v_i)
,.dma_data_ready_o(dma_data_ready_o)
,.dma_data_o(dma_data_o)
,.dma_data_v_o(dma_data_v_o)
,.dma_data_yumi_i(dma_data_yumi_i)
,.v_we_o()
);
assign cache_pkt_v_li = tr_v_lo;
assign tr_yumi_li = cache_pkt_ready_lo & tr_v_lo;
always_comb begin
case (tr_data_lo.op)
2'b00: cache_pkt.opcode = LW;
2'b01: cache_pkt.opcode = SW;
2'b10: cache_pkt.opcode = TAGST;
default: cache_pkt.opcode = LW;
endcase
end
assign cache_pkt.mask = 4'b1111;
assign cache_pkt.data = tr_data_lo.data;
assign cache_pkt.addr = tr_data_lo.addr;
// tracker
integer sent_r;
integer recv_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
sent_r <= 0;
recv_r <= 0;
end
else begin
if (tr_yumi_li) sent_r++;
if (cache_v_o) recv_r++;
end
end
assign done_o = (sent_r == recv_r) & tr_done_lo;
logic first_access_sent_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
first_access_sent_r <= 1'b0;
load_count_o <= 0;
store_count_o <= 0;
end
else begin
if (cache_pkt_v_li & cache_pkt_ready_lo & (cache_pkt.opcode == LW | cache_pkt.opcode == SW)) begin
if (cache_pkt.opcode == LW) load_count_o <= load_count_o + 1;
if (cache_pkt.opcode == SW) store_count_o <= store_count_o + 1;
if (~first_access_sent_r) begin
first_access_sent_r <= 1'b1;
first_access_time_o <= $time;
$display("t=%0t, first access sent.", $time);
end
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(vcache_blocking)
|
#include <bits/stdc++.h> using namespace std; const int MX = 1e5 + 69; const int inf = 1e9 + 5; const long long mod = 1e9 + 7; const long double eps = 1e-10; vector<int> v[MX]; int par[24][MX]; int depth[MX]; void dfs(int x, int p) { for (auto g : v[x]) { if (g == p) { continue; } depth[g] = depth[x] + 1; dfs(g, x); par[0][g] = x; } } int lca(int x, int y) { if (depth[x] > depth[y]) swap(x, y); int i = 22; while (depth[x] < depth[y]) { if (depth[par[i][y]] >= depth[x]) { y = par[i][y]; } i--; } for (int i = 22; i >= 0; i--) { if (par[i][x] != par[i][y]) { x = par[i][x]; y = par[i][y]; } } if (x != y) { x = par[0][x]; y = par[0][y]; } return x; } int dis(int a, int b) { return (depth[a] + depth[b] - 2 * depth[lca(a, b)]); } int cal(int a, int b, int c) { int ret = 0; int q1 = lca(a, b); int q2 = lca(a, c); int q3 = lca(b, c); if (depth[q1] >= max(depth[q2], depth[q3])) { ret = dis(lca(a, b), c); } else { ret = dis((depth[q2] >= depth[q3] ? q2 : q3), c); } return ret; } int main() { depth[0] = -1; int n, q; cin >> n >> q; for (int i = 2; i <= n; i++) { int b; scanf( %d , &b); v[i].push_back(b); v[b].push_back(i); } dfs(1, -1); for (int i = 1; i < 23; i++) { for (int j = 1; j <= n; j++) { par[i][j] = par[i - 1][par[i - 1][j]]; } } while (q--) { int ans = 0; int a, b, c; scanf( %d%d%d , &a, &b, &c); ans = max(cal(a, b, c), max(cal(a, c, b), cal(b, c, a))); printf( %d n , ans + 1); } return 0; }
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 04:56:41 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_rst_ps7_0_50M_0_stub.v
// Design : design_1_rst_ps7_0_50M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, l, d; cin >> n >> d >> m >> l; long long x = 0; long long L = -m; long long R = -m + l; for (int i = 0; i < n; i++) { L += m; R += m; if (x + d < L) break; long long o = (R - x) / d; x = x + d * o; } cout << x + d; return 0; }
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
//
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module icache_tag_ram
(
// Inputs
input clk_i
,input rst_i
,input [ 7:0] addr_i
,input [ 19:0] data_i
,input wr_i
// Outputs
,output [ 19:0] data_o
);
//-----------------------------------------------------------------
// Single Port RAM 0KB
// Mode: Read First
//-----------------------------------------------------------------
reg [19:0] ram [255:0] /*verilator public*/;
reg [19:0] ram_read_q;
// Synchronous write
always @ (posedge clk_i)
begin
if (wr_i)
ram[addr_i] <= data_i;
ram_read_q <= ram[addr_i];
end
assign data_o = ram_read_q;
endmodule
|
/*
Copyright (c) 2013-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream FIFO
*/
module axis_fifo #
(
// FIFO depth in words
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of output pipeline registers
parameter PIPELINE_OUTPUT = 2,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_ENABLE set
parameter FRAME_FIFO = 0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames marked bad
// Requires FRAME_FIFO set
parameter DROP_BAD_FRAME = 0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO set
parameter DROP_WHEN_FULL = 0
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Status
*/
output wire status_overflow,
output wire status_bad_frame,
output wire status_good_frame,
output wire status_full,
output wire status_empty
);
parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
// check configuration
initial begin
if (PIPELINE_OUTPUT < 1) begin
$error("Error: PIPELINE_OUTPUT must be at least 1 (instance %m)");
$finish;
end
if (FRAME_FIFO && !LAST_ENABLE) begin
$error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)");
$finish;
end
if (DROP_BAD_FRAME && !FRAME_FIFO) begin
$error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set (instance %m)");
$finish;
end
if (DROP_WHEN_FULL && !FRAME_FIFO) begin
$error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set (instance %m)");
$finish;
end
if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin
$error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)");
$finish;
end
end
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}};
reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [WIDTH-1:0] mem_read_data_reg;
reg mem_read_data_valid_reg = 1'b0;
wire [WIDTH-1:0] s_axis;
reg [WIDTH-1:0] m_axis_pipe_reg[PIPELINE_OUTPUT-1:0];
reg [PIPELINE_OUTPUT-1:0] m_axis_tvalid_pipe_reg = 1'b0;
// full when first MSB different but rest same
wire full = wr_ptr_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
wire full_cur = wr_ptr_cur_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
// empty when pointers match exactly
wire empty = wr_ptr_reg == rd_ptr_reg;
// overflow within packet
wire full_wr = wr_ptr_reg == (wr_ptr_cur_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
reg drop_frame_reg = 1'b0;
reg overflow_reg = 1'b0;
reg bad_frame_reg = 1'b0;
reg good_frame_reg = 1'b0;
assign s_axis_tready = FRAME_FIFO ? (!full_cur || full_wr || DROP_WHEN_FULL) : !full;
generate
assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep;
if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast;
if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid;
if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest;
if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser;
endgenerate
assign m_axis_tvalid = m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1];
assign m_axis_tdata = m_axis_pipe_reg[PIPELINE_OUTPUT-1][DATA_WIDTH-1:0];
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
assign m_axis_tlast = LAST_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][LAST_OFFSET] : 1'b1;
assign m_axis_tid = ID_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_pipe_reg[PIPELINE_OUTPUT-1][USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
assign status_overflow = overflow_reg;
assign status_bad_frame = bad_frame_reg;
assign status_good_frame = good_frame_reg;
assign status_full = FRAME_FIFO ? full_cur || full_wr : full;
assign status_empty = empty;
// Write logic
always @(posedge clk) begin
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
// transfer in
if (!FRAME_FIFO) begin
// normal FIFO mode
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_reg <= wr_ptr_reg + 1;
end else if (full_cur || full_wr || drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_reg <= 1'b1;
if (s_axis_tlast) begin
// end of frame, reset write pointer
wr_ptr_cur_reg <= wr_ptr_reg;
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b1;
end
end else begin
mem[wr_ptr_cur_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_cur_reg <= wr_ptr_cur_reg + 1;
if (s_axis_tlast) begin
// end of frame
if (DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
// bad packet, reset write pointer
wr_ptr_cur_reg <= wr_ptr_reg;
bad_frame_reg <= 1'b1;
end else begin
// good packet, update write pointer
wr_ptr_reg <= wr_ptr_cur_reg + 1;
good_frame_reg <= 1'b1;
end
end
end
end
if (rst) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
end
end
// Read logic
integer j;
always @(posedge clk) begin
if (m_axis_tready) begin
// output ready; invalidate stage
m_axis_tvalid_pipe_reg[PIPELINE_OUTPUT-1] <= 1'b0;
end
for (j = PIPELINE_OUTPUT-1; j > 0; j = j - 1) begin
if (m_axis_tready || ((~m_axis_tvalid_pipe_reg) >> j)) begin
// output ready or bubble in pipeline; transfer down pipeline
m_axis_tvalid_pipe_reg[j] <= m_axis_tvalid_pipe_reg[j-1];
m_axis_pipe_reg[j] <= m_axis_pipe_reg[j-1];
m_axis_tvalid_pipe_reg[j-1] <= 1'b0;
end
end
if (m_axis_tready || ~m_axis_tvalid_pipe_reg) begin
// output ready or bubble in pipeline; read new data from FIFO
m_axis_tvalid_pipe_reg[0] <= 1'b0;
m_axis_pipe_reg[0] <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
if (!empty) begin
// not empty, increment pointer
m_axis_tvalid_pipe_reg[0] <= 1'b1;
rd_ptr_reg <= rd_ptr_reg + 1;
end
end
if (rst) begin
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
m_axis_tvalid_pipe_reg <= {PIPELINE_OUTPUT{1'b0}};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 102, M = 102 * 102; int n, m; vector<pair<int, int> > g[N]; char ans[N][N]; char dp[N][N][28] = {0}; void input() { cin >> n >> m; for (int i = (0); i < (m); ++i) { int u, v; char ch; cin >> u >> v >> ch; u--, v--; g[u].push_back(make_pair(v, ch - a )); } } int dfs(int u, int v, char c) { if (dp[u][v][c] != 0) return dp[u][v][c]; for (auto x : g[u]) { int h = x.first; char k = x.second; int win = 0; if (k >= c) { win = dfs(v, h, k); if (win == 2) { dp[u][v][c] = 1; return 1; } } } dp[u][v][c] = 2; return 2; } void solve() { for (int i = (0); i < (n); ++i) { for (int j = (0); j < (n); ++j) { ans[i][j] = ((dfs(i, j, 0) == 1) ? A : B ); } } } void output() { for (int i = (0); i < (n); ++i) { for (int j = (0); j < (n); ++j) { cout << ans[i][j]; } cout << n ; } } int main() { input(); solve(); output(); }
|
#include <bits/stdc++.h> using namespace std; long long a[501][501]; bool visited[501]; int main() { long long n; cin >> n; for (long long i = 0; i < n; i++) { visited[i] = false; for (long long j = 0; j < n; j++) { cin >> a[i][j]; } } vector<long long> order(n); for (long long i = 0; i < n; i++) { cin >> order[i]; order[i]--; } visited[order[n - 1]] = true; vector<long long> values; for (long long k = 0; k < n; k++) { long long ans = 0; long long p = order[n - k - 1]; visited[p] = true; for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { a[i][j] = min(a[i][j], a[i][p] + a[p][j]); if (visited[i] && visited[j] && visited[p]) { ans += a[i][j]; } } } values.push_back(ans); } for (long long i = 0; i < n; i++) { cout << values[n - 1 - i] << ; } }
|
#include <bits/stdc++.h> using namespace std; int a, b; int x; int main() { scanf( %d%d%d , &a, &b, &x); if (a >= b) for (int i = 0; i <= x - 2; i++) { printf( %d , i & 1); a -= !(i & 1); b -= (i & 1); } else { for (int i = 1; i <= x - 1; i++) { printf( %d , i & 1); a -= !(i & 1); b -= (i & 1); } x++; } if (x & 1) { for (int i = 0; i < a; i++) printf( 0 ); for (int i = 0; i < b; i++) printf( 1 ); } else { for (int i = 0; i < b; i++) printf( 1 ); for (int i = 0; i < a; i++) printf( 0 ); } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[3000010], v[2 * 1000010 + 5]; int main() { int n, k, i, mn, ans, j; scanf( %d%d , &n, &k); for (i = 0; i < n; i++) scanf( %d , &a[i]); mn = a[0]; for (i = 1; i < n; i++) mn = min(mn, a[i]); if (mn <= k + 1) { cout << mn; return 0; } ans = k + 1; for (i = 0; i < n; i++) v[a[i]]++; for (i = 1; i <= 2 * 1000010; i++) v[i] += v[i - 1]; for (i = k + 2; i <= mn; i++) { int cnt = 0; for (j = i; j <= 1000010; j += i) cnt += (v[j + k] - v[j - 1]); if (cnt == n) ans = i; } printf( %d n , ans); return 0; }
|
// File: mm_vgasys.v
// Generated by MyHDL 0.9dev
// Date: Sat Mar 22 22:03:29 2014
`timescale 1ns/1ns
module mm_vgasys (
clock,
reset,
vselect,
hsync,
vsync,
red,
green,
blue,
pxlen,
active
);
input clock;
input reset;
input vselect;
output hsync;
reg hsync;
output vsync;
reg vsync;
output [9:0] red;
wire [9:0] red;
output [9:0] green;
wire [9:0] green;
output [9:0] blue;
wire [9:0] blue;
output pxlen;
reg pxlen;
output active;
reg active;
reg [2:0] gvga_vga_state;
reg [19:0] gvga_vcd;
reg [9:0] gvga_hpxl;
reg [8:0] gvga_vpxl;
reg [29:0] gvga_vmem_red;
reg [10:0] gvga_hcd;
reg [29:0] gvga_vmem_blue;
reg [29:0] gvga_vmem_green;
reg [29:0] gbar_pval;
reg [31:0] gbar_ssel;
always @(posedge clock) begin: MM_VGASYS_GVGA_RTL_SYNC
reg signed [3-1:0] xcnt;
reg [11-1:0] hcnt;
reg [20-1:0] vcnt;
if (reset == 0) begin
gvga_vpxl <= 0;
gvga_vcd <= 0;
vsync <= 0;
gvga_hpxl <= 0;
hsync <= 0;
pxlen <= 0;
gvga_hcd <= 0;
hcnt = 0;
vcnt = 0;
xcnt = 0;
end
else begin
hcnt = (hcnt + 1);
vcnt = (vcnt + 1);
if ((vcnt == 833333)) begin
vcnt = 0;
hcnt = 0;
end
else if ((vcnt > 768000)) begin
hcnt = (1600 - 1);
end
else if ((hcnt >= 1600)) begin
hcnt = 0;
end
xcnt = (xcnt + 1);
if ((hcnt == 1)) begin
xcnt = 1;
end
else if ((xcnt == 2)) begin
xcnt = 0;
end
if (((xcnt == 0) && (hcnt <= 1250))) begin
pxlen <= 1'b1;
end
else begin
pxlen <= 1'b0;
end
if (((hcnt >= (1250 + 50)) && (hcnt < ((1250 + 50) + 200)))) begin
hsync <= 1'b0;
end
else begin
hsync <= 1'b1;
end
if (((vcnt >= (768000 + 17000)) && (vcnt < ((768000 + 17000) + 3200)))) begin
vsync <= 1'b0;
end
else begin
vsync <= 1'b1;
end
if ((($signed({1'b0, gvga_hpxl}) < (640 - 1)) && (xcnt == 0) && (hcnt <= 1250))) begin
gvga_hpxl <= (gvga_hpxl + 1);
end
else if ((hcnt > (1250 + 50))) begin
gvga_hpxl <= 0;
end
if ((($signed({1'b0, hcnt}) >= (1600 - 1)) && (vcnt < 768000))) begin
gvga_vpxl <= (gvga_vpxl + 1);
end
else if ((vcnt > (768000 + 17000))) begin
gvga_vpxl <= 0;
end
gvga_hcd <= hcnt;
gvga_vcd <= vcnt;
end
end
always @(gvga_vcd, hsync, gvga_hcd, vsync) begin: MM_VGASYS_GVGA_RTL_STATE
if ((!hsync)) begin
gvga_vga_state = 3'b011;
end
else if ((!vsync)) begin
gvga_vga_state = 3'b110;
end
else if ((gvga_hcd < 1250)) begin
gvga_vga_state = 3'b001;
end
else if (((gvga_vcd >= 768000) && (gvga_vcd < (768000 + 17000)))) begin
gvga_vga_state = 3'b101;
end
else if (((gvga_vcd >= (768000 + 17000)) && (gvga_vcd < ((768000 + 17000) + 3200)))) begin
// pass
end
else if (((gvga_vcd >= ((768000 + 17000) + 3200)) && (gvga_vcd < 833333))) begin
gvga_vga_state = 3'b111;
end
else if (((gvga_hcd >= 1250) && (gvga_hcd < (1250 + 50)))) begin
gvga_vga_state = 3'b010;
end
else if (((gvga_hcd >= (1250 + 50)) && (gvga_hcd < ((1250 + 50) + 200)))) begin
// pass
end
else if (((gvga_hcd >= ((1250 + 50) + 200)) && (gvga_hcd < (((1250 + 50) + 200) + 100)))) begin
gvga_vga_state = 3'b100;
end
if ((gvga_hcd < 1250)) begin
active = 1'b1;
end
else begin
active = 1'b0;
end
end
assign red = gvga_vmem_red;
assign green = gvga_vmem_green;
assign blue = gvga_vmem_blue;
always @(gvga_hpxl) begin: MM_VGASYS_GBAR_RTL_PVAL
integer ii;
integer sel;
sel = 0;
for (ii=0; ii<8; ii=ii+1) begin
if (($signed({1'b0, gvga_hpxl}) > (ii * 80))) begin
sel = ii;
end
end
gbar_ssel = sel;
case (sel)
0: gbar_pval = ;
1: gbar_pval = ;
2: gbar_pval = ;
3: gbar_pval = ;
4: gbar_pval = ;
5: gbar_pval = ;
6: gbar_pval = 1023;
default: gbar_pval = 0;
endcase
end
always @(posedge clock) begin: MM_VGASYS_GBAR_RTL_RGB
if (reset == 0) begin
gvga_vmem_blue <= 0;
gvga_vmem_green <= 0;
gvga_vmem_red <= 0;
end
else begin
gvga_vmem_red <= ((gbar_pval >>> 20) & 1023);
gvga_vmem_green <= ((gbar_pval >>> 10) & 1023);
gvga_vmem_blue <= (gbar_pval & 1023);
end
end
endmodule
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 14.0 cbx_altiobuf_out 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_stratixiii 2014:06:05:09:45:41:SJ cbx_stratixv 2014:06:05:09:45:41:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
/*
-- ============================================================================
-- FILE NAME : bus_addr_dec.v
-- DESCRIPTION : AhXfR[_
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "bus.h"
/********** W
[ **********/
module bus_addr_dec (
/********** AhX **********/
input wire [`WordAddrBus] s_addr, // AhX
/********** `bvZNg **********/
output reg s0_cs_, // oXX[u0Ô
output reg s1_cs_, // oXX[u1Ô
output reg s2_cs_, // oXX[u2Ô
output reg s3_cs_, // oXX[u3Ô
output reg s4_cs_, // oXX[u4Ô
output reg s5_cs_, // oXX[u5Ô
output reg s6_cs_, // oXX[u6Ô
output reg s7_cs_ // oXX[u7Ô
);
/********** oXX[uCfbNX **********/
wire [`BusSlaveIndexBus] s_index = s_addr[`BusSlaveIndexLoc];
/********** oXX[u}`vNT **********/
always @(*) begin
/* `bvZNgÌú» */
s0_cs_ = `DISABLE_;
s1_cs_ = `DISABLE_;
s2_cs_ = `DISABLE_;
s3_cs_ = `DISABLE_;
s4_cs_ = `DISABLE_;
s5_cs_ = `DISABLE_;
s6_cs_ = `DISABLE_;
s7_cs_ = `DISABLE_;
/* AhXÉηéX[uÌIð */
case (s_index)
`BUS_SLAVE_0 : begin // oXX[u0Ô
s0_cs_ = `ENABLE_;
end
`BUS_SLAVE_1 : begin // oXX[u1Ô
s1_cs_ = `ENABLE_;
end
`BUS_SLAVE_2 : begin // oXX[u2Ô
s2_cs_ = `ENABLE_;
end
`BUS_SLAVE_3 : begin // oXX[u3Ô
s3_cs_ = `ENABLE_;
end
`BUS_SLAVE_4 : begin // oXX[u4Ô
s4_cs_ = `ENABLE_;
end
`BUS_SLAVE_5 : begin // oXX[u5Ô
s5_cs_ = `ENABLE_;
end
`BUS_SLAVE_6 : begin // oXX[u6Ô
s6_cs_ = `ENABLE_;
end
`BUS_SLAVE_7 : begin // oXX[u7Ô
s7_cs_ = `ENABLE_;
end
endcase
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
sgmii_rxp,
sgmii_rxn,
sgmii_txp,
sgmii_txn,
phy_rstn,
mgt_clk_p,
mgt_clk_n,
mdio_mdc,
mdio_mdio,
fan_pwm,
linear_flash_addr,
linear_flash_adv_ldn,
linear_flash_ce_n,
linear_flash_oen,
linear_flash_wen,
linear_flash_dq_io,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
input sgmii_rxp;
input sgmii_rxn;
output sgmii_txp;
output sgmii_txn;
output phy_rstn;
input mgt_clk_p;
input mgt_clk_n;
output mdio_mdc;
inout mdio_mdio;
output fan_pwm;
output [26:1] linear_flash_addr;
output linear_flash_adv_ldn;
output linear_flash_ce_n;
output linear_flash_oen;
output linear_flash_wen;
inout [15:0] linear_flash_dq_io;
inout [ 6:0] gpio_lcd;
inout [20:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [35:0] hdmi_data;
output spdif;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// default logic
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_sw_led (
.dio_t (gpio_t[20:0]),
.dio_i (gpio_o[20:0]),
.dio_o (gpio_i[20:0]),
.dio_p (gpio_bd));
// instantiations
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.linear_flash_dq_io(linear_flash_dq_io),
.gpio_lcd_tri_io (gpio_lcd),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio0_i (gpio_i[31:0]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio1_i (gpio_i[63:32]),
.hdmi_36_data (hdmi_data),
.hdmi_36_data_e (hdmi_data_e),
.hdmi_36_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_36_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mb_intr_06 (1'b0),
.mb_intr_12 (1'b0),
.mb_intr_13 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mgt_clk_clk_n (mgt_clk_n),
.mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn),
.phy_sd (1'b1),
.sgmii_rxn (sgmii_rxn),
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),
.sgmii_txp (sgmii_txp),
.spdif (spdif),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int main() { int N; cin >> N; if (N % 2 == 0) cout << -1 << endl; else { for (int i = 0; i < N; i++) cout << i << (i == N - 1 ? n : ); for (int i = 0; i < N; i++) cout << ((long long)(N - 2) * i) % N << (i == N - 1 ? n : ); for (int i = 0; i < N; i++) cout << ((long long)(N - 2) * i + i) % N << (i == N - 1 ? n : ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100030; const long long MODD = 1000000009; int ctr[128]; void do_case() { int n, k; cin >> n >> k; string s; cin >> s; for (int i = 0; i < s.size(); i++) ctr[s[i]]++; sort(ctr, ctr + 128); reverse(ctr, ctr + 128); long long ans = 0; for (int i = 0; i < 128; i++) { long long v = min(k, ctr[i]); ans += v * v; k -= v; } cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); do_case(); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool check(string& a, string& b) { if (a.size() != b.size()) return false; int ind1 = -1, ind2 = -1; bool check = false; bool buck[26] = {0}; int count = 0; for (int i = 0; i < a.size(); i++) { if (a[i] != b[i]) { count++; if (count > 2) return false; if (ind1 == -1) ind1 = i; else ind2 = i; } else { if (buck[a[i] - a ]) check = true; else buck[a[i] - a ] = true; } } if (count == 1) return false; if (count == 0) { return check; } return (a[ind1] == b[ind2]) && (a[ind2] == b[ind1]); } int main() { string a, b; cin >> a; cin >> b; if (check(a, b)) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int NMAX = 100005; int n, k; char s[NMAX]; int sum[NMAX]; int get(int l, int r) { l = max(1, l); r = min(r, n); return sum[r] - sum[l - 1]; } int main() { cin.sync_with_stdio(false); cin >> n >> k; cin >> (s + 1); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + (s[i] == 0 ); int ans = 1 << 30; for (int i = 1; i <= n; i++) if (s[i] == 0 ) { int l = 1; int r = n; int sol = -1; while (l <= r) { int mi = (l + r) / 2; if (get(i - mi, i - 1) + get(i + 1, i + mi) >= k) { sol = mi; r = mi - 1; } else l = mi + 1; } if (sol != -1) ans = min(ans, sol); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 520; long long gi() { long long x = 0, o = 1; char ch = getchar(); while (!isdigit(ch) && ch != - ) ch = getchar(); if (ch == - ) o = -1, ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x * o; } int k, n, t, x[N], y[N]; long long a[N][N], b[N][N]; int main() { cin >> k; n = 1 << k; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) a[i][j] = gi(); cin >> t; for (int i = 1; i <= t; i++) x[i] = gi(), y[i] = gi(); for (int i = t; i; i--) x[i] = (x[i] - x[1] + n) % n, y[i] = (y[i] - y[1] + n) % n; for (int i = 1; i <= k; i++) { for (int j = 0; j < n; j++) for (int k = 0; k < n; k++) for (int l = 1; l <= t; l++) b[j][k] ^= a[(j - x[l] + n) % n][(k - y[l] + n) % n]; memcpy(a, b, sizeof(b)); memset(b, 0, sizeof(b)); for (int j = 1; j <= t; j++) x[j] = x[j] * 2 % n, y[j] = y[j] * 2 % n; } int ans = 0; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (a[i][j]) ++ans; cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; int x = a; while ((a / x + b / x) < n) x--; if (a < x) cout << a; else if (b < x) cout << b; else cout << x; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:58:59 04/05/2017
// Design Name:
// Module Name: Timing
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Timing(
output reg bunch_strb,
input store_strb,
input clk,
input [7:0] b1_strobe,
input [7:0] b2_strobe,
input [1:0] no_bunches,
input [3:0] no_samples,
input [7:0] sample_spacing,
output reg LUTcond
);
//parameter no_bunches=2;
//parameter no_samples=1;
//parameter sample_spacing=100; // Number of samples between consecutive bunches
reg [4:0] bunch_counter=0;
initial bunch_strb=0;
(* equivalent_register_removal = "no"*) reg [7:0] i;
reg [7:0] start_bunch_strb=0;
reg [7:0] end_bunch_strb=0;
//reg LUTcond;
// ***** Generate bunch strobe *****
always @ (posedge clk) begin
LUTcond<=i==b2_strobe+1|| i== b2_strobe+sample_spacing+1;
if (store_strb) begin
i<=i+1;
end
else i<=0;
end
reg cond1,cond1_a, cond2, cond3;
always @ (posedge clk) begin
cond1_a<=bunch_counter==no_bunches; // If haven't exceeded number of bunches
cond1<=cond1_a;
cond2<=i==start_bunch_strb; // To send bunch strobe high
cond3<=i==end_bunch_strb; // To send bunch strobe low
if (~store_strb) begin
bunch_counter<=0;
start_bunch_strb<=b1_strobe-2;
end_bunch_strb<=b1_strobe+no_samples-2; // Bunch strobe stays high for no_samples samples
end
else if (cond1) begin
end
else begin
if (cond2) bunch_strb<=1;
else if (cond3) begin
bunch_strb<=0;
bunch_counter<=bunch_counter+1;
start_bunch_strb<=start_bunch_strb+sample_spacing; // Calculate sample numbers for next bunch
end_bunch_strb<=end_bunch_strb+sample_spacing; // Calculate sample numbers for next bunch
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; int a[MAXN], deg[MAXN]; set<pair<int, int> > s; int main() { int n, sum = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> deg[i] >> a[i]; if (deg[i]) s.insert(make_pair(deg[i], i)); sum += deg[i]; } cout << sum / 2 << endl; while (s.size()) { pair<int, int> x = *s.begin(); s.erase(x); int t = a[x.second]; cout << x.second << << t << endl; s.erase(make_pair(deg[t], t)); deg[t]--; a[t] ^= x.second; if (deg[t]) s.insert(make_pair(deg[t], t)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long> num; void solve() { int n; cin >> n; char arr[2][n]; for (int i = 0; i < 2; i++) { for (int j = 0; j < n; j++) { cin >> arr[i][j]; } } int row = 0, col = 0; int visited[2][n]; memset(visited, false, sizeof(visited)); while (col < n - 1) { visited[row][col] = true; if (!visited[row][col + 1] && arr[row][col + 1] != 1 ) col++; else if (!visited[1 - row][col] && arr[1 - row][col] != 1 ) { row = 1 - row; } else if (!visited[1 - row][col + 1] && arr[1 - row][col + 1] != 1 ) { row = 1 - row; col++; } else { break; } } if (col == n - 1) cout << Yes << endl; else cout << No << endl; } int main() { int t; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> const int oo = 0x3f3f3f3f; template <typename T> inline bool chkmax(T &a, T b) { return a < b ? a = b, true : false; } template <typename T> inline bool chkmin(T &a, T b) { return a > b ? a = b, true : false; } template <typename T> T read(T &first) { int f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (first = 0; isdigit(ch); ch = getchar()) first = 10 * first + ch - 0 ; return first *= f; } template <typename T> void write(T first) { if (first == 0) { putchar( 0 ); return; } if (first < 0) { putchar( - ); first = -first; } static char s[20]; int top = 0; for (; first; first /= 10) s[++top] = first % 10 + 0 ; while (top) putchar(s[top--]); } const int MAXN = 2e5 + 5; const int CNT = 60; int N; std::pair<int, int> A[MAXN]; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } inline int count(int i, int j) { return gcd(std::abs(A[j].first - A[i].first), std::abs(A[j].second - A[i].second)); } inline long long cross(const std::pair<int, int> &a, const std::pair<int, int> &b) { return (long long)a.first * b.second - (long long)a.second * b.first; } void input() { read(N); for (int i = 0; i < N; ++i) { read(A[i].first); read(A[i].second); } } void solve() { memcpy(A + N, A, sizeof(*A) * N); long long a = 0, b = 0; for (int i = 0; i < N; ++i) { a += cross(A[i], A[i + 1]); b += count(i, i + 1); } long double coef[MAXN]; long double tnn = pow((long double)2, -N); for (int i = 2; i <= CNT && i < N - 1; ++i) { coef[i] = pow((long double)2, -i - 1) - tnn; } long double ans = 0.5 * a - 0.5 * b + 1; long double contrib = 0; for (int i = 0; i < N; ++i) { a = cross(A[i], A[i + 1]); b = count(i, i + 1); for (int k = 2; k <= CNT && k < N - 1; ++k) { int j = i + k; a += cross(A[j - 1], A[j]); b += count(j - 1, j); long long a0 = cross(A[j], A[i]); long long b0 = count(j, i); contrib += (0.5 * (a + a0) - 0.5 * (b + b0) + b0) * coef[k]; } } ans -= contrib / (1 - tnn - N * tnn - (long long)N * (N - 1) / 2 * tnn); printf( %.15f n , (double)ans); } int main() { input(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const int MOD = 1e9 + 7; const int N = 2e2 + 10, M = 1e6 + 10; const int alp = 10; vector<pair<int, int> > pos; pair<int, int> s[M]; int n, m, q, a[N][N], f[N][N], h[N][N], len[N][N], dx[10], dy[10], deg[N][N], g[M]; string str; bool check(int x, int y) { return x > 0 && x <= n && y > 0 && y <= m; } void DFS(int sx, int sy) { int top = 1, spe = 0; int v = 0; s[1] = pair<int, int>(sx, sy); while (!spe) { int cx = s[top].first, cy = s[top].second; h[cx][cy] = top; int nx = cx + dx[a[cx][cy]], ny = cy + dy[a[cx][cy]]; if (!check(nx, ny)) spe = top; else { if (f[nx][ny]) { spe = top + 1; v = f[nx][ny]; s[top + 1] = pair<int, int>(nx, ny); break; } if (!h[nx][ny]) s[++top] = pair<int, int>(nx, ny); else spe = h[nx][ny]; } } for (auto i = spe; i <= top; i++) v |= (1 << (a[s[i].first][s[i].second])); for (auto i = 1; i <= top; i++) f[s[i].first][s[i].second] = v; for (auto i = spe - 1; i >= 1; i--) len[s[i].first][s[i].second] = len[s[i + 1].first][s[i + 1].second] + 1; } void prepare() { cin >> n >> m >> q; for (auto i = 1; i <= n; i++) { cin >> str; for (auto j = 1; j <= m; j++) a[i][j] = str[j - 1] - 0 ; } for (auto i = 0; i < alp; i++) cin >> dx[i] >> dy[i]; for (auto i = 1; i <= n; i++) for (auto j = 1; j <= m; j++) { int nx = i + dx[a[i][j]], ny = j + dy[a[i][j]]; if (check(nx, ny)) deg[nx][ny]++; } for (auto i = 1; i <= n; i++) for (auto j = 1; j <= m; j++) if (!deg[i][j]) { DFS(i, j); pos.push_back(pair<int, int>(i, j)); } for (auto i = 1; i <= n; i++) for (auto j = 1; j <= m; j++) if (!f[i][j]) { DFS(i, j); pos.push_back(pair<int, int>(i, j)); } } string solve() { int n1 = str.length(); g[n1] = 0; for (auto i = n1 - 1; i >= 0; i--) g[i] = g[i + 1] | (1 << (str[i] - 0 )); for (auto x : pos) { int cur = 0; pair<int, int> cx = x; while (cur < n1 && len[cx.first][cx.second]) { int v = a[cx.first][cx.second]; if (str[cur] - 0 == v) cur++; int nx = cx.first + dx[v], ny = cx.second + dy[v]; cx = pair<int, int>(nx, ny); } if ((g[cur] & f[cx.first][cx.second]) == g[cur]) return YES ; } return NO ; } int main() { prepare(); while (q--) { cin >> str; cout << solve() << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int n; cin >> n; long long int s = 0; for (long long int i = 0; i < n; i++) { long long int x; cin >> x; s += x; } if (s % n == 0) cout << n; else cout << n - 1; }
|
Require Import ExtLib.Structures.Applicative.
Require Import Temporal.DiscreteLogic.
Require Import ChargeCore.Tactics.Tactics.
Set Implicit Arguments.
Set Strict Implicit.
Definition lift1 {T U : Type} {F : Type -> Type}
{Ap : Applicative.Applicative F}
(f : T -> U) (x : F T) : F U :=
Applicative.ap (Applicative.pure f) x.
Definition lift2 {T U V : Type} {F : Type -> Type}
{Ap : Applicative.Applicative F}
(f : T -> U -> V) (x : F T) (y : F U) : F V :=
Applicative.ap (lift1 (F:=F) f x) y.
(*
Class Arith (T : Type) : Type :=
{ plus : T -> T -> T
; minus : T -> T -> T
; mult : T -> T -> T
}.
Instance Arith_nat : Arith nat :=
{ plus := Nat.add
; minus := Nat.sub
; mult := Nat.mul
}.
Instance Arith_lift {T U} {A : Arith T} : Arith (U -> T) :=
{ plus := fun a b x => plus (a x) (b x)
; minus := fun a b x => minus (a x) (b x)
; mult := fun a b x => mult (a x) (b x)
}.
*)
Record State : Type :=
{ x : nat }.
Definition Sys : TraceProp State :=
now (lift2 eq x (pure 1))
//\\ always (starts (lift2 eq (pre x) (post x))).
(** TODO: Move **)
Definition beforeProp (P : StateProp State) (Q : ActionProp State) : Prop :=
before State P -|- Q.
Definition beforeVal {T} (P : StateVal State T) (Q : ActionVal State T)
: Prop :=
forall st st', P st = Q st st'.
Theorem beforeProp_lift2 {T U} (f : T -> U -> Prop) x y x' y'
: beforeVal x x' -> beforeVal y y' ->
beforeProp (lift2 f x y) (lift2 f x' y').
Proof.
unfold beforeVal, beforeProp.
simpl. intros.
unfold before.
split.
Transparent ILInsts.ILFun_Ops.
{ do 3 red. simpl. destruct t0.
rewrite <- H. rewrite <- H0. auto. }
{ do 3 red. simpl. destruct t0.
rewrite <- H. rewrite <- H0. auto. }
Qed.
Theorem beforeVal_pre {T} (get : State -> T) :
beforeVal get (pre get).
Proof. red. reflexivity. Qed.
Theorem beforeVal_pure {T} (x : T) :
beforeVal (pure x) (pure x).
Proof. red. reflexivity. Qed.
Require Import Coq.Classes.Morphisms.
Notation "[] e" := (always e) (at level 30).
Goal |-- Sys -->> [] (now (lift2 eq x (pure 1))).
Proof.
unfold Sys.
charge_intros.
eapply hybrid_induction.
{ charge_assumption. }
{ charge_assumption. }
{ apply always_tauto.
rewrite <- curry.
rewrite now_starts_discretely_and.
rewrite next_now.
rewrite starts_impl.
eapply starts_tauto.
unfold before, after, pre, post. simpl.
destruct 2; congruence. }
Qed.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A2BB2OI_BLACKBOX_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 5; const long long MOD = 1e9 + 7; const long long INF = 1e18; signed main() { int n; cin >> n; vector<long long> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } multiset<long long> kek; long long ans = 0; for (int i = n - 1; i >= 0; i--) { if (a[i] == -1) { break; } kek.insert(a[i]); if ((i & (i + 1)) == 0) { ans += *(kek.begin()); kek.erase(kek.begin()); } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1024000000,1024000000 ) using namespace std; struct edge { int v, next; } e[200010]; int ecnt = 0, head[100010]; int n; int d[100010]; int leg[100010]; void addedge(int a, int b) { e[++ecnt].v = b; e[ecnt].next = head[a]; head[a] = ecnt; } void del(int x) { while (d[x] <= 2) { d[x] = 0; int xx = x; for (int i = head[x]; ~i; i = e[i].next) { if (d[e[i].v]) { x = e[i].v; break; } } if (x == xx) break; } leg[x]++; } bool solve() { for (int i = (1); i <= (n); i++) { if (d[i]) { int cnt = 0; for (int j = head[i]; ~j; j = e[j].next) { int v = e[j].v; if (d[v]) { if (leg[v] > 2) cnt++; else if (d[v] - leg[v] > 1) cnt++; } } if (cnt > 2) return false; } } return true; } int main() { cin >> n; memset((head), (-1), sizeof(head)); memset((d), (0), sizeof(d)); memset((leg), (0), sizeof(leg)); for (int i = (1); i <= (n - 1); i++) { int u, v; scanf( %d%d , &u, &v); addedge(u, v); addedge(v, u); d[u]++; d[v]++; } for (int i = (1); i <= (n); i++) { if (d[i] == 1) del(i); } puts(solve() ? Yes : No ); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> ostream &operator<<(ostream &os, pair<T1, T2> &p); template <class T> ostream &operator<<(ostream &os, vector<T> &v); template <class T> ostream &operator<<(ostream &os, set<T> &v); template <class T1, class T2> ostream &operator<<(ostream &os, map<T1, T2> &v); const long long mod = 100000007; const int N = 15; int n, k; bool check(vector<int> &a, int x) { bool flag = true; vector<int> v; for (int i = 0; i < n; i++) { if (v.size() == k) break; if ((int)v.size() % 2) { v.push_back(a[i]); } else if (a[i] <= x) { v.push_back(a[i]); } } if (v.size() == k) { return true; } v.clear(); for (int i = 0; i < n; i++) { if (v.size() == k) break; if ((int)v.size() % 2 == 0) { v.push_back(a[i]); } else if (a[i] <= x) { v.push_back(a[i]); } } if (v.size() == k) { return true; } return false; } void TEST_CASES(int cas) { scanf( %d %d , &n, &k); vector<int> a(n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } int low = *min_element(a.begin(), a.end()), high = *max_element(a.begin(), a.end()); int ans = -1; while (low <= high) { int mid = (low + high) / 2; ; ; if (check(a, mid)) { high = mid - 1; ans = mid; } else { low = mid + 1; } } printf( %d n , ans); } int main() { int t = 1, cas = 0; while (t--) { TEST_CASES(++cas); } return 0; } template <class T1, class T2> ostream &operator<<(ostream &os, pair<T1, T2> &p) { os << { << p.first << , << p.second << } ; return os; } template <class T> ostream &operator<<(ostream &os, vector<T> &v) { os << [ ; for (int i = 0; i < v.size(); i++) { os << v[i] << ; } os << ] ; return os; } template <class T> ostream &operator<<(ostream &os, set<T> &v) { os << [ ; for (T i : v) { os << i << ; } os << ] ; return os; } template <class T1, class T2> ostream &operator<<(ostream &os, map<T1, T2> &v) { for (auto i : v) { os << Key : << i.first << , Value : << i.second << endl; } return os; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD3_TB_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD3_TB_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlygate4sd3.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__dlygate4sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD3_TB_V
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module BRAM #(parameter AWIDTH = 9,
parameter DWIDTH = 32)
(clk,
rce,
ra,
rq,
wce,
wa,
wd);
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
reg [DWIDTH-1:0] memory[0:AWIDTH-1];
always @(posedge clk) begin
if (rce)
rq <= memory[ra];
if (wce)
memory[wa] <= wd;
end
integer i;
initial
begin
for(i = 0; i < AWIDTH-1; i = i + 1)
memory[i] = 0;
end
endmodule
module BRAM_32x512(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 9;
parameter DWIDTH = 32;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_32x512 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
module BRAM_16x1024(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 10;
parameter DWIDTH = 16;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_16x1024 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
module BRAM_8x2048(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 11;
parameter DWIDTH = 8;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_8x2048 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
module BRAM_4x4096(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 12;
parameter DWIDTH = 4;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_4x4096 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n = 6, m = 8; vector<string> a(n); vector<vector<int>> u; vector<int> loc(m); loc = {3, 3, -1, 4, 4, -1, 3, 3}; u.push_back(loc); u.push_back(loc); loc = {2, 2, -1, 3, 3, -1, 2, 2}; u.push_back(loc); u.push_back(loc); loc = {1, 1, -1, 2, 2, -1, 1, 1}; u.push_back(loc); u.push_back(loc); for (int i = 0; i < n; i++) { cin >> a[i]; } int max = 0, x, y; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == . && u[i][j] > max) { x = i; y = j; max = u[i][j]; } } } a[x][y] = P ; for (auto i : a) { cout << i << n ; } }
|
#include <bits/stdc++.h> using namespace std; vector<int> v[30]; string s[100010]; char aver[300010]; long long f(int p, int ch, int si) { int mi = 99999999; if (v[ch].size() == 0) return s[si].size(); for (int i = 0; i < v[ch].size(); i++) mi = min(mi, abs(p - v[ch][i])); return mi; } int main() { long long n, k; cin >> n >> k; cin >> aver; for (int i = 1; i <= n; i++) cin >> s[i]; for (long long i = 0; i < k; i++) v[aver[i] - a ].push_back(i); for (int i = 1; i <= n; i++) { long long F = 0; for (int j = 0; j < s[i].size(); j++) { if (s[i][j] != aver[j]) { F += f(j, s[i][j] - a , i); } } cout << F << endl; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, m; cin >> n >> m; vector<vector<long long> > a(m, vector<long long>(n)); for (long long i = 0; i <= n - 1; i++) { for (long long j = 0; j <= m - 1; j++) { cin >> a[j][i]; a[j][i]--; } } long long ans = 0; for (long long i = 0; i <= m - 1; i++) { vector<long long> temp(n, 0); for (long long j = 0; j <= n - 1; j++) { if (a[i][j] % m == i) { long long x = a[i][j] / m; if (x < n) { temp[(j - x + n) % n]++; } } } long long lol = INT_MAX; for (long long j = 0; j <= n - 1; j++) { lol = min(lol, (n - temp[j] + j)); } ans += lol; } cout << ans << n ; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; for (long long i = 1; i <= t; i++) { solve(); } return 0; }
|
module quantum(
input clk,
input rst,
input hwrite,
input [31:0] hwdata,
input [31:0] haddr,
input hsel,
output reg[31:0] hrdata,
output[127:0] data,
input [127:0] ro_data
);
reg[15:0] dataA[7:0];
assign data = {dataA[7], dataA[6], dataA[5], dataA[4],
dataA[3], dataA[2], dataA[1], dataA[0]};
wire[15:0] rodataA[7:0];
assign {rodataA[7], rodataA[6], rodataA[5], rodataA[4],
rodataA[3], rodataA[2], rodataA[1], rodataA[0]} = {
ro_data[127:112], ro_data[111:96],
ro_data[95 :80], ro_data[79:64],
ro_data[63 :48], ro_data[47:32],
ro_data[31 :16], ro_data[15:0]
};
reg ctr;
reg write;
wire[2:0] raddr = haddr[4:2];
always @(*) begin
if (haddr[15:0] >= 'h20 && haddr[15:0] < 'h40) begin
hrdata = rodataA[raddr];
end else if (haddr[15:0] < 'h20) begin
hrdata = dataA[raddr];
end else begin
hrdata = 0;
end
end
always @(posedge clk) begin
if (rst) begin
ctr <= 0;
write <= 0;
end else if (ctr) begin
ctr <= 0;
if (write && haddr[15:0] < 'h20)
dataA[raddr] <= hwdata;
end else begin
ctr <= hsel;
write <= hwrite;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, q; cin >> n >> m; if (m) q = min(m, n - m); else q = 1; cout << q << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
// bug749
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
genvar g;
for (g=1; g<3; ++g) begin : gblk
sub2 #(.IN(g)) u ();
//sub #(.IN(g)) u2 ();
end
sub1 #(.IN(0)) u ();
always @ (posedge clk) begin
if (t.u.IN != 0) $stop;
if (t.u.FLAVOR != 1) $stop;
//if (t.u2.IN != 0) $stop; // This should be not found
if (t.gblk[1].u.IN != 1) $stop;
if (t.gblk[2].u.IN != 2) $stop;
if (t.gblk[1].u.FLAVOR != 2) $stop;
if (t.gblk[2].u.FLAVOR != 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub1 (/*AUTOARG*/);
parameter [31:0] IN = 99;
parameter FLAVOR = 1;
`ifdef TEST_VERBOSE
initial $display("%m");
`endif
endmodule
module sub2 (/*AUTOARG*/);
parameter [31:0] IN = 99;
parameter FLAVOR = 2;
`ifdef TEST_VERBOSE
initial $display("%m");
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 100, MOD = 1e9 + 9, INF = 1e15, SQ = 370, LOG = 30; int n, m, x, y, x2, y2, z, t, now, l, r; int ans, dp[4][4 * N]; bool lazy[4 * N]; string s; void bld(int b, int e, int pos) { if (b == e - 1) { if (s[b] == 7 ) { dp[3][pos]++; } else { dp[2][pos]++; } dp[0][pos] = dp[1][pos] = 1; return; } int lch = pos << 1, rch = lch + 1, mid = e + b >> 1; bld(b, mid, lch); bld(mid, e, rch); dp[3][pos] = dp[3][lch] + dp[3][rch]; dp[2][pos] = dp[2][lch] + dp[2][rch]; dp[1][pos] = max(dp[3][lch] + dp[1][rch], dp[1][lch] + dp[2][rch]); dp[0][pos] = max(dp[2][lch] + dp[0][rch], dp[0][lch] + dp[3][rch]); } void shift(int pos, int lch, int rch) { lazy[lch] = !lazy[lch]; lazy[rch] = !lazy[rch]; lazy[pos] = false; swap(dp[0][lch], dp[1][lch]); swap(dp[2][lch], dp[3][lch]); swap(dp[0][rch], dp[1][rch]); swap(dp[2][rch], dp[3][rch]); } void upd(int b, int e, int pos) { if (b >= y || e <= x) return; if (x <= b && e <= y) { lazy[pos] = !lazy[pos]; swap(dp[0][pos], dp[1][pos]); swap(dp[2][pos], dp[3][pos]); return; } int lch = pos << 1, rch = lch + 1, mid = e + b >> 1; if (lazy[pos]) shift(pos, lch, rch); upd(b, mid, lch); upd(mid, e, rch); dp[3][pos] = dp[3][lch] + dp[3][rch]; dp[2][pos] = dp[2][lch] + dp[2][rch]; dp[1][pos] = max(dp[3][lch] + dp[1][rch], dp[1][lch] + dp[2][rch]); dp[0][pos] = max(dp[2][lch] + dp[0][rch], dp[0][lch] + dp[3][rch]); } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m >> s; bld(0, n, 1); while (m--) { cin >> s; if (s == count ) { cout << dp[0][1] << n ; } else { cin >> x >> y; x--; upd(0, n, 1); } } }
|
//wbs_spi.v
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000005
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_spi
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x05
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x01
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:12
*/
`include "project_defines.v"
`include "spi_defines.v"
`include "timescale.v"
`unconnected_drive pull0
module wb_spi #(
parameter SPI_CHAR_LEN_BITS = 8
)(
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int,
// SPI signals
output [31:0] ss_pad_o, // slave select
//output ss_pad_o, // slave select
output sclk_pad_o, // serial clock
output mosi_pad_o, // master out slave in
input miso_pad_i // master in slave out
);
localparam SPI_MAX_CHAR = 2 ** SPI_CHAR_LEN_BITS;
localparam SPI_MAX_REG_SIZE = SPI_MAX_CHAR / 32;
//parameters
localparam SPI_CTRL = 0;
localparam SPI_CLOCK_RATE = 1;
localparam SPI_DIVIDER = 2;
localparam SPI_SS = 3;
localparam SPI_BIT_COUNT = 4;
localparam SPI_MAX_BITSIZE = 5;
localparam SPI_RX_DATA = 6;
localparam SPI_TX_DATA = ((SPI_RX_DATA) + (SPI_MAX_REG_SIZE));
//Registers/Wires
reg [31:0] divider = 100; // Divider register
reg [31:0] ctrl = 0; // Control and status register
reg [31:0] ss = 0; // Slave select register
//reg ss = 0; // Slave select register
reg [31:0] char_len= 8; // char len
wire [SPI_MAX_CHAR - 1:0] rx_data; // Rx register
wire [SPI_MAX_CHAR - 1:0] tx_data;
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire inv_clk; // invert clock
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
wire sclk;
wire [31:0] read_reg_pos;
wire [31:0] write_reg_pos;
reg [31:0] tx_data_array [(SPI_MAX_REG_SIZE - 1):0];
wire [31:0] rx_data_array [(SPI_MAX_REG_SIZE - 1):0];
integer i;
//Submodules
spi_clkgen clgen (
.clk_in (clk ),
.rst (rst ),
.go (go ),
.enable (tip ),
.last_clk (last_bit ),
.divider (divider ),
.clk_out (sclk ),
.pos_edge (pos_edge ),
.neg_edge (neg_edge )
);
spi_shift #(
.SPI_CHAR_LEN_BITS (SPI_CHAR_LEN_BITS )
) shift (
.clk (clk ),
.rst (rst ),
.len (char_len ),
.lsb (lsb ),
.go (go ),
.pos_edge (pos_edge ),
.neg_edge (neg_edge ),
.rx_negedge (rx_negedge ),
.tx_negedge (tx_negedge ),
.tip (tip ),
.last (last_bit ),
.s_clk (sclk ),
.s_in (miso_pad_i ),
.s_out (mosi_pad_o ),
.mosi_data (tx_data ),
.miso_data (rx_data )
);
//Asynchronous Logic
genvar gv;
generate
for (gv = 0; gv < SPI_MAX_REG_SIZE; gv = gv + 1) begin : wb_spi_init
assign tx_data[((gv << 5) + 31): (gv << 5)] = tx_data_array[(SPI_MAX_REG_SIZE - 1) - gv];
assign rx_data_array[(SPI_MAX_REG_SIZE - 1) - gv] = rx_data[(gv << 5) + 31: (gv << 5)];
end
endgenerate
// Address decoder
assign read_reg_valid = ((i_wbs_adr >= SPI_RX_DATA) && (i_wbs_adr < SPI_TX_DATA));
assign read_reg_pos = read_reg_valid ? (i_wbs_adr - SPI_RX_DATA): 0;
assign write_reg_valid = (i_wbs_adr >= SPI_TX_DATA) && (i_wbs_adr < (SPI_TX_DATA + (SPI_MAX_REG_SIZE)));
assign write_reg_pos = write_reg_valid ? (i_wbs_adr - SPI_TX_DATA): 0;
assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
assign go = ctrl[`SPI_CTRL_GO];
assign lsb = ctrl[`SPI_CTRL_LSB];
assign ie = ctrl[`SPI_CTRL_IE];
assign ass = ctrl[`SPI_CTRL_ASS];
assign inv_clk = ctrl[`SPI_CTRL_INV_CLK];
assign ss_pad_o = ~((ss & {32{tip & ass}}) | (ss & {32{!ass}}));
//assign ss_pad_o = ~((ss & tip & ass) | (ss & !ass));
//assign ss_pad_o = !ss;
assign sclk_pad_o = inv_clk ? ~sclk : sclk;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h00000000;
o_wbs_ack <= 0;
char_len <= 0;
ctrl <= 0;
divider <= 100;
ss <= 0;
for (i = 0; i < SPI_MAX_REG_SIZE; i = i + 1) begin
tx_data_array[i] <= i;
end
end
else begin
//interrupts
if (ie && tip && last_bit && pos_edge) begin
o_wbs_int <= 1;
end
else if (o_wbs_ack) begin
o_wbs_int <= 0;
end
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (go && last_bit && pos_edge) begin
ctrl[`SPI_CTRL_GO] <= 0;
end
if (i_wbs_stb & i_wbs_cyc & !o_wbs_ack) begin
//master is requesting somethign
if (i_wbs_we && !tip) begin
//write request
case (i_wbs_adr)
SPI_CTRL: begin
ctrl <= i_wbs_dat;
end
SPI_BIT_COUNT: begin
char_len <= i_wbs_dat;
end
SPI_DIVIDER: begin
divider <= i_wbs_dat;
end
SPI_SS: begin
//ss <= i_wbs_dat[0];
ss <= i_wbs_dat;
end
default: begin
end
endcase
if (write_reg_valid) begin
tx_data_array[write_reg_pos] <= i_wbs_dat;
end
end
else begin
//read request
case (i_wbs_adr)
SPI_CTRL: begin
o_wbs_dat <= ctrl;
end
SPI_BIT_COUNT: begin
o_wbs_dat <= char_len;
end
SPI_DIVIDER: begin
o_wbs_dat <= divider;
end
SPI_SS: begin
//o_wbs_dat <= {31'h0, ss};
o_wbs_dat <= ss;
end
SPI_CLOCK_RATE: begin
o_wbs_dat <= `CLOCK_RATE;
end
SPI_MAX_BITSIZE: begin
o_wbs_dat <= SPI_MAX_CHAR;
end
default: begin
o_wbs_dat <= 32'bx;
end
endcase
if (read_reg_valid) begin
o_wbs_dat <= rx_data_array[read_reg_pos];
end
end
o_wbs_ack <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e6 + 6; vector<int> adj[MAX]; bool visited[MAX]; void dfs(int source, int &nodes, int &total) { total += adj[source].size(); visited[source] = true; nodes++; for (auto &each : adj[source]) { if (!visited[each]) { dfs(each, nodes, total); } } } int main() { int n, m; scanf( %d %d , &n, &m); for (int i = int(0); i < int(m); i++) { int a, b; scanf( %d %d , &a, &b); adj[a].push_back(b); adj[b].push_back(a); } for (int i = int(1); i < int(n + 1); i++) { if (!visited[i]) { int total = 0; int nodes = 0; dfs(i, nodes, total); if (total != (1LL * nodes * (nodes - 1))) { puts( NO ); return 0; } } } puts( YES ); return 0; }
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
module qa_contents
#(
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] in_data,
input wire in_nd,
input wire [MWIDTH-1:0] in_m,
input wire [`MSG_WIDTH-1:0] in_msg,
input wire in_msg_nd,
output wire [WIDTH-1:0] out_data,
output reg out_nd,
output reg [MWIDTH-1:0] out_m,
output wire [`MSG_WIDTH-1:0] out_msg,
output wire out_msg_nd,
output reg error
);
wire [WIDTH/2-1:0] x;
wire [WIDTH/2-1:0] y;
wire [WIDTH/2-1:0] z;
assign x = in_data[WIDTH-1:WIDTH/2];
assign y = in_data[WIDTH/2-1:0];
assign out_data = {{WIDTH/2{1'b0}}, z};
always @ (posedge clk)
if (~rst_n)
error <= 1'b0;
else
begin
out_nd <= in_nd;
end
multiply #(WIDTH/2) multiply_0
(.clk(clk),
.rst_n(rst_n),
.x(x),
.y(y),
.z(z)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; /*DEBUGGER*/ #define deb(x) cout << #x << = << x << endl #define deb2(x, y) cout << #x << = << x << , << #y << = << y << endl typedef long long ll; typedef pair<int, int> pii; typedef pair<ll, ll> pll; typedef pair<string, string> pss; typedef vector<int> vi; typedef vector<vi> vvi; typedef vector<pii> vii; typedef vector<ll> vll; typedef vector<vll> vvll; #define fl(i, a, n) for (int i = a; i < n; i++) #define fll(i, a, n) for (ll i = a; i < n; i++) #define tr(it, a) for (auto it = a.begin(); it != a.end(); it++) #define all(c) c.begin(), c.end() #define sz(a) int((a).size()) #define pb push_back #define mp make_pair #define F first #define S second #define getUnique(c) {sort(all(c));c.erase(unique(all(c)), c.end())} #define MOD 1000000007 #define PI 3.14159265358979323846 #define INF 2000000000000000000 /*TEMPLATES*/ template <typename A> ostream &operator<<(ostream &cout, vector<A> const &v) { cout << [ ; for (int i = 0; i < sz(v); i++) { if (i) cout << , ; cout << v[i]; } return cout << ] ; } template <typename A, typename B> ostream &operator<<(ostream &cout, pair<A, B> const &p) { return cout << ( << p.F << , << p.S << ) ; } template <typename A, typename B> istream &operator>>(istream &cin, pair<A, B> &p) { cin >> p.F; return cin >> p.S; } /*NUMBER THEORY*/ namespace number_theory { ll gcd(ll x, ll y) { if (x == 0) return y; if (y == 0) return x; return gcd(y, x % y); } bool isPrime(ll n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (ll i = 5; i * i <= n; i += 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } bool prime[15000105]; void sieve(int n) { for (ll i = 0; i <= n; i++) prime[i] = 1; for (ll p = 2; p * p <= n; p++) { if (prime[p] == true) { for (ll i = p * p; i <= n; i += p) prime[i] = false; } } prime[1] = prime[0] = 0; } vll primelist; bool __primes_generated__ = 0; void genprimes(int n) { __primes_generated__ = 1; sieve(n + 1); for (ll i = 2; i <= n; i++) if (prime[i]) primelist.push_back(i); } vll factors(ll n) { if (!__primes_generated__) { exit(1); } vll facs; for (ll i = 0; primelist[i] * primelist[i] <= n && i < primelist.size(); i++) { if (n % primelist[i] == 0) { while (n % primelist[i] == 0) { n /= primelist[i]; facs.pb(primelist[i]); } } } if (n > 1) { facs.pb(n); } sort(all(facs)); return facs; } } using namespace number_theory; void kkvanonymous() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); genprimes(1.5e6); //#ifdef ONLINE_JUDGE // freopen( input.txt , r , stdin); // freopen( output.txt , w , stdout); //#endif } bool sortbysec(const pair<int,int> &a, const pair<int,int> &b) { return (a.second < b.second); } void solve(){ ll a,b,n; cin>>a>>b>>n; vll p(n); vll h(n); ll m=-1; fll(i,0,n){ cin>>p[i]; m=max(m,p[i]); } fll(i,0,n){ cin>>h[i]; } fll(i,0,n){ ll t=ceil(double(h[i])/a); b-=p[i]*t; } if(b+m>0) cout<< YES n ; else cout<< NO n ; } int main() { #ifdef kkvanonymous_time auto begin = chrono::high_resolution_clock::now(); #endif kkvanonymous(); int t = 1; cin>>t; while (t--) solve(); #ifdef kkvanonymous_time auto end = chrono::high_resolution_clock::now(); cout << setprecision(4) << fixed; cout << nExecution time: << chrono::duration_cast<std::chrono::duration<double>>(end - begin).count() << seconds << endl; #endif return 0; }
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2017 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
#include <bits/stdc++.h> using namespace std; int record[300000]; int main() { map<pair<int, int>, int> m; memset(record, 0, sizeof(record)); int n, p; scanf( %d%d , &n, &p); map<pair<int, int>, int>::iterator iter; for (int i = 0; i < n; i++) { int a, b; scanf( %d%d , &a, &b); record[a]++; record[b]++; if (a > b) m[make_pair(b, a)]++; else m[make_pair(a, b)]++; } long long ans = 0; for (iter = m.begin(); iter != m.end(); iter++) { int x = (iter->first).first; int y = (iter->first).second; if (record[x] + record[y] - iter->second < p && record[x] + record[y] >= p) ans--; } sort(record + 1, record + n + 1); int ed = n; for (int st = 1; st <= n; st++) { while (record[st] + record[ed] >= p && ed > st) ed--; ans += min(n - ed, n - st); } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> namespace std { long long abs(long long x) { return x < 0 ? -x : x; } } // namespace std using namespace std; void dprintf(char* format, ...) { fprintf(stderr, DEBUG: ); va_list argp; va_start(argp, format); vfprintf(stderr, format, argp); va_end(argp); fprintf(stderr, n ); } struct Exception { const char* message; const int line; Exception(const char* m, int l) : message(m), line(l) {} }; static char stringReader[2097152]; static inline bool ReadLine() { char* ptr = fgets(stringReader, sizeof(stringReader), stdin); if (ptr == 0) return false; int N = strlen(stringReader); if (stringReader[N - 1] == n ) stringReader[N - 1] = 0; return true; } const long long ooLL = 0x3f3f3f3f3f3f3f3fLL; const int oo = 0x3f3f3f3f; const double eps = 1e-9; int main() { try { int N; scanf( %d , &N); int nt = 0; int sol = oo; vector<int> cnt(2 * N + 1, 0); char t[1024]; scanf( %s , t); for (int i = 0; i < N; ++i) { if (t[i] == T ) { ++nt; cnt[i + 1] = cnt[i + N + 1] = 1; } } for (int i = 1; i <= 2 * N; ++i) { cnt[i] += cnt[i - 1]; } int nh = N - nt; for (int i = 1; i <= N; ++i) { int have = cnt[i + nt - 1] - cnt[i - 1]; sol = min(sol, nt - have); } printf( %d n , sol); return 0; } catch (const Exception& exception) { fprintf(stderr, ****************************** n ); fprintf(stderr, ERROR.%d: %s n , exception.line, exception.message); fprintf(stderr, ****************************** n ); throw exception; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_4_V
`define SKY130_FD_SC_LS__NOR2_4_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int x, y, n; scanf( %d%d%d , &x, &y, &n); for (int i = 0; i < n; i++) y += x ^= y ^= x ^= y; printf( %d n , x); }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Freeze logic ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Generates all freezes and stalls inside RISC ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`define OR1200_NO_FREEZE 3'd0
`define OR1200_FREEZE_BYDC 3'd1
`define OR1200_FREEZE_BYMULTICYCLE 3'd2
`define OR1200_WAIT_LSU_TO_FINISH 3'd3
`define OR1200_WAIT_IC 3'd4
//
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
//
module or1200_freeze(
// Clock and reset
clk, rst,
// Internal i/f
multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
lsu_unstall, du_stall, mac_stall,
force_dslot_fetch, abort_ex,
genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze,
icpu_ack_i, icpu_err_i
);
//
// I/O
//
input clk;
input rst;
input [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
input flushpipe;
input extend_flush;
input lsu_stall;
input if_stall;
input lsu_unstall;
input force_dslot_fetch;
input abort_ex;
input du_stall;
input mac_stall;
output genpc_freeze;
output if_freeze;
output id_freeze;
output ex_freeze;
output wb_freeze;
input icpu_ack_i;
input icpu_err_i;
//
// Internal wires and regs
//
wire multicycle_freeze;
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt;
reg flushpipe_r;
//
// Pipeline freeze
//
// Rules how to create freeze signals:
// 1. Not overwriting pipeline stages:
// Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more
// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
//
// 2. Inserting NOPs in the middle of pipeline only if supported:
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
//assign genpc_freeze = du_stall | flushpipe_r | lsu_stall;
assign genpc_freeze = du_stall | flushpipe_r;
assign if_freeze = id_freeze | extend_flush;
//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall | mac_stall;
assign ex_freeze = wb_freeze;
//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex;
//
// registered flushpipe
//
always @(posedge clk or posedge rst)
if (rst)
flushpipe_r <= #1 1'b0;
else if (icpu_ack_i | icpu_err_i)
// else if (!if_stall)
flushpipe_r <= #1 flushpipe;
else if (!flushpipe)
flushpipe_r <= #1 1'b0;
//
// Multicycle freeze
//
assign multicycle_freeze = |multicycle_cnt;
//
// Multicycle counter
//
always @(posedge clk or posedge rst)
if (rst)
multicycle_cnt <= #1 2'b00;
else if (|multicycle_cnt)
multicycle_cnt <= #1 multicycle_cnt - 2'd1;
else if (|multicycle & !ex_freeze)
multicycle_cnt <= #1 multicycle;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long n, m; cin >> n >> m; long long a[n][m], f1 = 0; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { cin >> a[i][j]; if (a[i][j] > 4) f1 = 1; } } if (f1) { cout << NO << endl; continue; } for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { long long c = a[i][j]; if ((i == 0 && j == 0) || (i == 0 && j == m - 1) || (i == n - 1 && j == m - 1) || (i == n - 1 && j == 0)) { if (c > 2) f1 = 1; else a[i][j] = 2; } else if ((i == n - 1 || i == 0 || j == 0 || j == m - 1)) { if (a[i][j] > 3) f1 = 1; else a[i][j] = 3; } else a[i][j] = 4; } } if (f1) { cout << NO << endl; continue; } else { cout << YES << endl; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { cout << a[i][j] << ; } cout << endl; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; using namespace std; const int maxn = 3e5 + 5; int level[maxn * 2], num[maxn * 2], par[maxn * 2]; char s[maxn * 2]; stack<int> stk; int main() { int n, cnt = 0; scanf( %d , &n); scanf( %s , s + 1); for (int i = 1; i <= n; i++) { if (stk.empty()) stk.push(i); else { int c = stk.top(); if (s[i] == ) && s[c] == ( ) stk.pop(); else stk.push(i); } s[i + n] = s[i]; cnt = cnt + ((s[i] == ( ) ? (1) : (-1)); } if (cnt) return 0 & printf( 0 n1 1 n ); int j = 1; while (!stk.empty()) { int c = stk.top(); if (s[c] == ) ) break; stk.pop(); j = c; } for (int i = 1; i <= n * 2; i++) level[i] = -1, num[i] = 0; while (!stk.empty()) stk.pop(); for (int i = j; i <= j + n - 1; i++) { if (stk.empty()) { stk.push(i); level[i] = 1; cnt++; } else { int c = stk.top(); if (s[i] == ) && s[c] == ( ) { stk.pop(); par[c] = i; } else { stk.push(i); level[i] = stk.size(); } } } int i = j; while (i <= j + n - 1) { if (level[i] == 1) { int r = par[i], k = i; while (i < r) { if (level[i] == 2) num[k]++; i++; } } i++; } i = j; while (i <= j + n - 1) { if (level[i] == 2) { int r = par[i], k = i; while (i < r) { if (level[i] == 3) num[k]++; i++; } } i++; } int ans = 0, l, r; for (int i = j; i <= j + n - 1; i++) { if (level[i] == 1) { if (ans < (num[i] + 1)) { ans = num[i] + 1; l = i % n; r = par[i] % n; } } else if (level[i] == 2) { if (ans < (cnt + num[i] + 1)) { ans = cnt + num[i] + 1; l = i % n; r = par[i] % n; } } } if (ans < cnt) ans = cnt, l = 1, r = 1; if (l == 0) l = n; if (r == 0) r = n; printf( %d n%d %d n , ans, l, r); return 0; }
|
#include <iostream> #include <iomanip> #include <cstdio> #include <cstdlib> #include <algorithm> #include <cmath> #include <vector> #include <set> #include <map> #include <unordered_set> #include <unordered_map> #include <queue> #include <ctime> #include <cassert> #include <complex> #include <string> #include <cstring> #include <chrono> #include <random> #include <bitset> using namespace std; #define ll long long #define pi pair<int,int> #define pll pair<ll,ll> #define ld long double const int INF = 1e9 + 7; long long MOD; const int N = 405; long long dp[N][N]; long long ncr[N][N]; long long p2[N]; void solve(){ int n; cin >> n >> MOD; /* Trivial observation : If the number of segments of `x` is k and the sizes are x_1 , x_2 , ... , x_k. Then, the number of ways is X! / (x_1! x_2!... x_k!) 2^(x_1 - 1) 2^(x_2 - 1) .. */ p2[0] = 1LL; for(int i = 1; i < N; i++){ p2[i] = p2[i - 1] * 2LL % MOD; } ncr[1][0] = ncr[1][1] = 1; for(int i = 2; i < N; i++){ for(int r = 0; r <= i; r++){ if(r == 0 || r == i) ncr[i][r] = 1; else ncr[i][r] = (ncr[i - 1][r] + ncr[i - 1][r - 1]) % MOD; } } dp[1][1] = 1; for(int i = 2; i <= n; i++){ for(int manual = 0; manual <= i; manual++){ for(int last = 1; last <= min(manual , i); last++){ if(i - last - 1 >= 0){ dp[i][manual] += dp[i - last - 1][manual - last] * ncr[manual][last] % MOD * p2[last - 1] % MOD; dp[i][manual] %= MOD; } else{ assert(i == last); dp[i][manual] = p2[i - 1]; } } } } long long ans = 0; for(int manual = 1; manual <= n; manual++){ ans += dp[n][manual]; ans %= MOD; } cout << ans << endl; } int main(){ ios :: sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int tt = 1; #ifdef SIEVE construct(); #endif for(int tc = 1; tc <= tt; tc++){ // cout << Case # << tc << : ; solve(); } }
|
#include <bits/stdc++.h> using namespace std; long long powmod(long long base, long long exp) { base %= ((int)1e9 + 7); long long result = 1; while (exp > 0) { if (exp & 1) result = (result * base) % ((int)1e9 + 7); base = (base * base) % ((int)1e9 + 7); exp >>= 1; } return result % ((int)1e9 + 7); } long long inv(long long x) { return powmod(x, ((int)1e9 + 7) - 2) % ((int)1e9 + 7); } long long sum_to(long long x) { if (x < 0) return 0; return (((x * (x + 1)) % ((int)1e9 + 7)) * inv(2)) % ((int)1e9 + 7); } long long sq(long long x) { return (x * x) % ((int)1e9 + 7); } long long sumodd(long long o) { long long x = o / 2; x %= ((int)1e9 + 7); return sq(x + 1) % ((int)1e9 + 7); } long long sumeven(long long e) { e /= 2; e %= ((int)1e9 + 7); return (2 * sum_to(e)) % ((int)1e9 + 7); } long long f(long long x) { if (x == 0) return 0; if (x == 1) return 1; if (x == 2) return 3; long long k = 0; for (;; k++) if ((1LL << k) - 1 > x) break; k--; long long e = 2, o = 1; long long adde = 4, addo = 2; for (int i = int(0); i < int(k / 2 - 1); i++) { e += adde; o += addo; adde *= 4; addo *= 4; } long long d = x - ((1LL << k) - 1); if (k & 1) o = (o + addo); if (k & 1) { o = (o + 2 * ((1LL << (k - 1)) - 1)); e = (e + 2 * ((1LL << (k - 2)) - 1)); e = (e + 2 * d); } else { o = (o + 2 * ((1LL << (k - 2)) - 1)); e = (e + 2 * ((1LL << (k - 1)) - 1)); o = (o + 2 * d); } return ((sumodd(o) + sumeven(e)) % ((int)1e9 + 7) + ((int)1e9 + 7)) % ((int)1e9 + 7); } int main() { ios::sync_with_stdio(false); long long l, r; cin >> l >> r; cout << (f(r) - f(l - 1) + ((int)1e9 + 7)) % ((int)1e9 + 7) << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_BLACKBOX_V
`define SKY130_FD_SC_LP__INVKAPWR_BLACKBOX_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__invkapwr (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx ) #pragma GCC target( avx,tune=native ) using namespace std; class CodeHash { public: string precise(double number, int prec) { stringstream ss; ss << fixed << setprecision(prec) << number; return ss.str(); } }; class ScanReader { private: FILE *stream; char buffer[1 << 11]; bool is_digit[1 << 8]; int index, total; int scan() { if (index >= total) { index = 0; total = fread(buffer, 1, 1 << 11, stream); if (total <= 0) return -1; } return buffer[index++]; } bool iswhitespace(int n) { if (n == || n == n || n == t || n == r || n == -1) return true; return false; } public: ScanReader(FILE *stream) { this->stream = stream; index = total = 0; for (int i = 0; i < 1 << 8; i++) is_digit[i] = isdigit(i); } int scanInt() { int integer = 0, temp = scan(); while (iswhitespace(temp)) temp = scan(); int neg = 1; if (temp == - ) neg *= -1, temp = scan(); while (!iswhitespace(temp)) if (is_digit[temp]) integer *= 10, integer += (temp - 0 ), temp = scan(); return neg * integer; } long long scanLong() { long long integer = 0; int temp = scan(); while (iswhitespace(temp)) temp = scan(); int neg = 1; if (temp == - ) neg *= -1, temp = scan(); while (!iswhitespace(temp)) if (is_digit[temp]) integer *= 10, integer += (temp - 0 ), temp = scan(); return neg * integer; } string scanString() { string ss = ; int temp = scan(); while (iswhitespace(temp)) temp = scan(); while (!iswhitespace(temp)) ss += temp, temp = scan(); return ss; } double scanDouble() { int c = scan(); while (iswhitespace(c)) c = scan(); int sgn = 1; if (c == - ) sgn = -1, c = scan(); double res = 0; while (!iswhitespace(c) && c != . ) { if (c == e || c == E ) return res * pow(10, scanInt()); res *= 10; res += c - 0 ; c = scan(); } if (c == . ) { c = scan(); double m = 1; while (!iswhitespace(c)) { if (c == e || c == E ) { return res * pow(10, scanInt()); } m /= 10; res += (c - 0 ) * m; c = scan(); } } return res * sgn; } }; class PrintWriter { private: FILE *stream; static const int BUFFER_SIZE = (1 << 11) - 1; static const int MAX_OUT_SIZE = 23; int size; char buffer[BUFFER_SIZE]; void write(long long v) { if (v < 0) buffer[size++] = - , v *= -1; if (v < 10) buffer[size++] = v + 48; else { write(v / 10); buffer[size++] = v % 10 + 48; } } public: PrintWriter(FILE *stream) { this->size = 0; this->stream = stream; } void close() { if (size) fwrite(buffer, 1, size, stream); } void println(long long s) { if ((size ^ BUFFER_SIZE) < MAX_OUT_SIZE) { fwrite(buffer, 1, size, stream); size = 0; } write(s); buffer[size++] = n ; } void print(long long s) { if ((size ^ BUFFER_SIZE) < MAX_OUT_SIZE) { fwrite(buffer, 1, size, stream); size = 0; } write(s); buffer[size++] = ; } void println(string s) { if ((size ^ BUFFER_SIZE) < MAX_OUT_SIZE) { fwrite(buffer, 1, size, stream); size = 0; } for (int i = 0; i < s.length(); i++) { buffer[size++] = s[i]; if ((size ^ BUFFER_SIZE) < MAX_OUT_SIZE) { fwrite(buffer, 1, size, stream); size = 0; } } buffer[size++] = n ; } void print(string s) { if ((size ^ BUFFER_SIZE) < MAX_OUT_SIZE) { fwrite(buffer, 1, size, stream); size = 0; } for (int i = 0; i < s.length(); i++) { buffer[size++] = s[i]; if ((size ^ BUFFER_SIZE) < MAX_OUT_SIZE) { fwrite(buffer, 1, size, stream); size = 0; } } buffer[size++] = ; } }; FILE *fi = stdin; FILE *fo = stdout; ScanReader *in = new ScanReader(fi); PrintWriter *out = new PrintWriter(fo); CodeHash *ch = new CodeHash(); int main() { multiset<int> mt; multiset<int> mt1; multiset<int> mt2; int n = in->scanInt(); long long ans = 1; long long mod = 1000000007; while (n--) { string s = in->scanString(); int tt = in->scanInt(); if (s.length() == 3) { if (!mt.empty() && *mt.begin() < tt) mt.insert(tt); else if (!mt1.empty() && *mt1.rbegin() > tt) mt1.insert(tt); else mt2.insert(tt); } else { if ((!mt.empty() && *mt.begin() < tt) || (!mt1.empty() && *mt1.rbegin() > tt)) { out->println(0); out->close(); return 0; } if ((!mt.empty() && *mt.begin() == tt)) mt.erase(mt.begin()); if ((!mt1.empty() && *mt1.rbegin() == tt)) mt1.erase(--mt1.end()); while (!mt2.empty()) { int tl = *mt2.begin(); mt2.erase(mt2.begin()); if (tl < tt) { mt1.insert(tl); } else if (tl > tt) { mt.insert(tl); } else { ans = (ans * 2) % mod; } } } } out->println((ans * (mt2.size() + 1)) % mod); out->close(); return 0; }
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module TriState
(
// Outputs
O,
// Inouts
IO,
// Inputs
OE, I
);
parameter width = 1;
input OE;
input [width-1:0] I;
output [width-1:0] O;
inout [width-1:0] IO;
assign IO = (OE) ? I : { width { 1'bz } };
assign O = IO;
endmodule // TriState
|
//
// Copyright 2015 Ettus Research
//
module noc_block_exmodrec #(
parameter NOC_ID = 64'hABCD080D2EC00000,
parameter STR_SINK_FIFOSIZE = 11)
(
input bus_clk, input bus_rst,
input ce_clk, input ce_rst,
input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
output [63:0] debug
);
////////////////////////////////////////////////////////////
//
// RFNoC Shell
//
////////////////////////////////////////////////////////////
wire [31:0] set_data;
wire [7:0] set_addr;
wire set_stb;
reg [63:0] rb_data;
wire [7:0] rb_addr;
wire [63:0] cmdout_tdata, ackin_tdata;
wire cmdout_tlast, cmdout_tvalid, cmdout_tready, ackin_tlast, ackin_tvalid, ackin_tready;
wire [63:0] str_sink_tdata, str_src_tdata;
wire str_sink_tlast, str_sink_tvalid, str_sink_tready, str_src_tlast, str_src_tvalid, str_src_tready;
wire [15:0] src_sid;
wire [15:0] next_dst_sid, resp_out_dst_sid;
wire [15:0] resp_in_dst_sid;
wire clear_tx_seqnum;
noc_shell #(
.NOC_ID(NOC_ID),
.STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE))
noc_shell (
.bus_clk(bus_clk), .bus_rst(bus_rst),
.i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
.o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
// Computer Engine Clock Domain
.clk(ce_clk), .reset(ce_rst),
// Control Sink
.set_data(set_data), .set_addr(set_addr), .set_stb(set_stb),
.rb_stb(1'b1), .rb_data(rb_data), .rb_addr(rb_addr),
// Control Source
.cmdout_tdata(cmdout_tdata), .cmdout_tlast(cmdout_tlast), .cmdout_tvalid(cmdout_tvalid), .cmdout_tready(cmdout_tready),
.ackin_tdata(ackin_tdata), .ackin_tlast(ackin_tlast), .ackin_tvalid(ackin_tvalid), .ackin_tready(ackin_tready),
// Stream Sink
.str_sink_tdata(str_sink_tdata), .str_sink_tlast(str_sink_tlast), .str_sink_tvalid(str_sink_tvalid), .str_sink_tready(str_sink_tready),
// Stream Source
.str_src_tdata(str_src_tdata), .str_src_tlast(str_src_tlast), .str_src_tvalid(str_src_tvalid), .str_src_tready(str_src_tready),
// Stream IDs set by host
.src_sid(src_sid), // SID of this block
.next_dst_sid(next_dst_sid), // Next destination SID
.resp_in_dst_sid(resp_in_dst_sid), // Response destination SID for input stream responses / errors
.resp_out_dst_sid(resp_out_dst_sid), // Response destination SID for output stream responses / errors
// Misc
.vita_time('d0), .clear_tx_seqnum(clear_tx_seqnum),
.debug(debug));
////////////////////////////////////////////////////////////
//
// AXI Wrapper
// Convert RFNoC Shell interface into AXI stream interface
//
////////////////////////////////////////////////////////////
wire [31:0] m_axis_data_tdata;
wire [127:0] m_axis_data_tuser;
wire m_axis_data_tlast;
wire m_axis_data_tvalid;
wire m_axis_data_tready;
wire [31:0] s_axis_data_tdata;
wire [127:0] s_axis_data_tuser;
wire s_axis_data_tlast;
wire s_axis_data_tvalid;
wire s_axis_data_tready;
axi_wrapper #(
.SIMPLE_MODE(0))
axi_wrapper (
.clk(ce_clk), .reset(ce_rst),
.clear_tx_seqnum(clear_tx_seqnum),
.next_dst(next_dst_sid),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.i_tdata(str_sink_tdata), .i_tlast(str_sink_tlast), .i_tvalid(str_sink_tvalid), .i_tready(str_sink_tready),
.o_tdata(str_src_tdata), .o_tlast(str_src_tlast), .o_tvalid(str_src_tvalid), .o_tready(str_src_tready),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tlast(m_axis_data_tlast),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tuser(m_axis_data_tuser),
.s_axis_data_tdata(s_axis_data_tdata),
.s_axis_data_tlast(s_axis_data_tlast),
.s_axis_data_tvalid(s_axis_data_tvalid),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tuser(s_axis_data_tuser),
.m_axis_config_tdata(),
.m_axis_config_tlast(),
.m_axis_config_tvalid(),
.m_axis_config_tready(),
.m_axis_pkt_len_tdata(),
.m_axis_pkt_len_tvalid(),
.m_axis_pkt_len_tready());
////////////////////////////////////////////////////////////
//
// User code
//
////////////////////////////////////////////////////////////
// NoC Shell registers 0 - 127,
// User register address space starts at 128
localparam SR_USER_REG_BASE = 128;
// Control Source Unused
assign cmdout_tdata = 64'd0;
assign cmdout_tlast = 1'b0;
assign cmdout_tvalid = 1'b0;
assign ackin_tready = 1'b1;
// Settings registers
//
// - The settings register bus is a simple strobed interface.
// - Transactions include both a write and a readback.
// - The write occurs when set_stb is asserted.
// The settings register with the address matching set_addr will
// be loaded with the data on set_data.
// - Readback occurs when rb_stb is asserted. The read back strobe
// must assert at least one clock cycle after set_stb asserts /
// rb_stb is ignored if asserted on the same clock cycle of set_stb.
// Example valid and invalid timing:
// __ __ __ __
// clk __| |__| |__| |__| |__
// _____
// set_stb ___| |________________
// _____
// rb_stb _________| |__________ (Valid)
// _____
// rb_stb _______________| |____ (Valid)
// __________________________
// rb_stb (Valid if readback data is a constant)
// _____
// rb_stb ___| |________________ (Invalid / ignored, same cycle as set_stb)
//
// localparam [7:0] SR_TEST_REG_0 = SR_USER_REG_BASE;
// localparam [7:0] SR_TEST_REG_1 = SR_USER_REG_BASE + 8'd1;
localparam RB_SIZE_INPUT = 129;
localparam RB_SIZE_OUTPUT = 130;
wire [15:0] const_size_in, const_size_out;
// Readback registers
// rb_stb set to 1'b1 on NoC Shell
always @(posedge ce_clk) begin
case(rb_addr)
RB_SIZE_INPUT : rb_data <= {48'd0, const_size_in};
RB_SIZE_OUTPUT : rb_data <= {48'd0, const_size_out};
default : rb_data <= 64'h0BADC0DE0BADC0DE;
endcase
end
// *************************************************
// Neural Net Wrapper
//
// + Force resize input and output packets
// + Save off tuser for the output packet
// *************************************************
wire [31:0] in_data_tdata, out_data_tdata;
wire in_data_tlast, out_data_tlast;
wire in_data_tvalid, out_data_tvalid;
wire in_data_tready, out_data_tready;
nnet_vector_wrapper inst_nnet_wrapper (
.clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum),
.next_dst_sid(next_dst_sid),
.pkt_size_in(const_size_in), .pkt_size_out(const_size_out),
// Interface from axi_wrapper
.i_tdata(m_axis_data_tdata),
.i_tlast(m_axis_data_tlast),
.i_tvalid(m_axis_data_tvalid),
.i_tready(m_axis_data_tready),
.i_tuser(m_axis_data_tuser),
.o_tdata(s_axis_data_tdata),
.o_tlast(s_axis_data_tlast),
.o_tvalid(s_axis_data_tvalid),
.o_tready(s_axis_data_tready),
.o_tuser(s_axis_data_tuser),
// Interface to the HLS neural net block
.m_axis_data_tdata(in_data_tdata),
.m_axis_data_tlast(in_data_tlast),
.m_axis_data_tvalid(in_data_tvalid),
.m_axis_data_tready(in_data_tready),
.s_axis_data_tdata(out_data_tdata),
.s_axis_data_tlast(out_data_tlast),
.s_axis_data_tvalid(out_data_tvalid),
.s_axis_data_tready(out_data_tready));
// *************************************************
// RF-Neural-NOC
//
// + Insert the HLS generated block below
// + Connect the "in_data" and "out_data" busses
// + Connect packet_size indicators
// *************************************************
// Assign out_data_tdata MSBs to 0. Currently only using 16 bit data
assign out_data_tdata[31:16] = 0;
// Assign tlast = 0... currently not propagated in the HLS ports
assign out_data_tlast = 1'b0;
// ex_modrec inst_example_modrec (
// .ap_clk(ce_clk), .ap_rst(ce_rst),
// .const_size_in(const_size_in), .const_size_out(const_size_out),
// .data_V_V_dout(in_data_tdata), .data_V_V_empty_n(in_data_tvalid), .data_V_V_read(in_data_tready),
// .res_V_V_din(out_data_tdata), .res_V_V_full_n(out_data_tready), .res_V_V_write(out_data_tvalid));
ex_modrec inst_example_modrec (
.ap_clk(ce_clk), .ap_rst_n(~ce_rst),
.const_size_in(const_size_in), .const_size_out(const_size_out),
.data_V_V_TDATA(in_data_tdata), .data_V_V_TVALID(in_data_tvalid), .data_V_V_TREADY(in_data_tready),
.res_V_V_TDATA(out_data_tdata), .res_V_V_TVALID(out_data_tvalid), .res_V_V_TREADY(out_data_tready));
endmodule
|
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