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#include <bits/stdc++.h> using namespace std; const int MAXN = 207; int n, f[MAXN]; long long mmc_atual = 1; vector<int> folhas, Gr[MAXN]; bool in_cycle[MAXN], mrk[MAXN]; int marca_ciclo(int u) { if (in_cycle[u]) return 0; in_cycle[u] = true; return 1 + marca_ciclo(f[u]); } void dfsr(int u) { mrk[u] = true; bool flag = true; for (int i = 0; i < (int)Gr[u].size(); i++) { int viz = Gr[u][i]; flag = false; if (mrk[viz]) continue; dfsr(viz); } if (flag) folhas.push_back(u); } int dfs(int u) { if (in_cycle[u]) return 0; return 1 + dfs(f[u]); } long long mdc(long long a, long long b) { return (a == 0) ? b : mdc(b % a, a); } long long mmc(long long a, long long b) { return (a / mdc(a, b)) * b; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (int i = 1; i <= n; i++) { cin >> f[i]; Gr[f[i]].push_back(i); } long long ans = 1; long long mx_chain = 0; for (int i = 1; i <= n; i++) { if (!mrk[i]) { int turtoise = i; int hare = i; do { turtoise = f[turtoise]; hare = f[f[hare]]; } while (turtoise != hare); int tam_ciclo = marca_ciclo(hare); mmc_atual = mmc(mmc_atual, (long long)tam_ciclo); dfsr(hare); } } for (int i = 0; i < (int)folhas.size(); i++) { int tam_chain = dfs(folhas[i]); mx_chain = max(mx_chain, (long long)tam_chain); } if (mx_chain % mmc_atual != 0) mx_chain = (mx_chain - mx_chain % mmc_atual) + mmc_atual; ans = max(mmc_atual, mx_chain); cout << ans << endl; }
|
/**
* ALU.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "aludefs.v"
module ALU #(parameter WIDTH=8) (
input wire [WIDTH - 1 : 0] op1,
input wire [WIDTH - 1 : 0] op2,
input wire [`ALUCTLW - 1: 0] ctl,
input wire [`FWIDTH - 1 : 0] flags_in,
output wire [WIDTH - 1 : 0] result,
output wire [`FWIDTH - 1 : 0] flags_out
);
/* internal signals */
reg [`FWIDTH - 1 : 0] flags;
reg [WIDTH - 1 : 0] alu_out;
wire msb1, msb2, msb3;
/* ALU output */
assign flags_out = flags;
assign result = alu_out;
/* internal wiring */
assign msb1 = op1[WIDTH - 1];
assign msb2 = op2[WIDTH - 1];
assign msb3 = result[WIDTH - 1];
/* ALU multiplexer and behaviour */
always @(*) begin
flags = {`FWIDTH{1'b0}};
case(ctl)
3'b000: begin /* add: op1 + op2 */
/* sum and carry */
{flags[`CARRY_FLAG], alu_out} = op1 + op2;
/* overflow detect */
flags[`OVERFLOW_FLAG] = ((~msb1) & (~msb2) & msb3)
| (msb1 & msb2 & (~msb3));
/* negative flag */
flags[`NEGATIVE_FLAG] = msb3;
end
3'b001: begin /* add with carry: op1 + op2 + carry_in */
/* sum and carry */
{flags[`CARRY_FLAG], alu_out} = op1 + op2 + flags_in[`CARRY_FLAG];
/* overflow detect */
flags[`OVERFLOW_FLAG] = ((~msb1) & (~msb2) & msb3)
| (msb1 & msb2 & (~msb3));
/* negative flag */
flags[`NEGATIVE_FLAG] = msb3;
end
3'b010: begin /* subtract: op2 - op1 */
{flags[`CARRY_FLAG], alu_out} = op2 - op1;
/* overflow detect */
flags[`OVERFLOW_FLAG] = ((~msb1) & (~msb2) & msb3)
| (msb1 & msb2 & (~msb3));
/* negative flag */
flags[`NEGATIVE_FLAG] = msb3;
end
3'b011: begin /* subtract with carry */
{flags[`CARRY_FLAG], alu_out} = op2 - op1 - flags_in[`CARRY_FLAG];
/* overflow detect */
flags[`OVERFLOW_FLAG] = ((~msb1) & (~msb2) & msb3)
| (msb1 & msb2 & (~msb3));
/* negative flag */
flags[`NEGATIVE_FLAG] = msb3;
end
3'b100: begin /* nand */
alu_out = ~(op1 & op2);
end
3'b101: begin /* nor */
alu_out = ~(op1 | op2);
end
3'b110: begin /* xor */
alu_out = op1 ^ op2;
end
3'b111: begin /* shift right arithmetic */
alu_out = {op1[WIDTH - 1], op1[WIDTH - 1 : 1]};
flags[`CARRY_FLAG] = op1[0];
end
default:
alu_out = {WIDTH{1'b0}};
endcase
flags[`ZERO_FLAG] = ~|alu_out;
end
endmodule
`include "aluundefs.v"
/* vim: set ts=4 tw=79 syntax=verilog */
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 20:41:53 01/18/2012
// Design Name:
// Module Name: videoctl
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module video_counters(
input clk,
output reg video_vsync = 1,
output reg video_hsync = 1,
output video_on,
output reg [10:1] hpos = 0,
output reg [9:1] vpos = 0);
integer hcnt = 0, vcnt = 0;
reg video_von = 0, video_hon = 0;
assign video_on = video_von & video_hon;
always @(posedge video_hsync) begin
vcnt <= vcnt + 1;
vpos <= video_von?vpos + 1: 0;
case (vcnt)
2: video_vsync = 1;
31: video_von = 1;
511: video_von = 0;
521: begin vcnt <=0; video_vsync = 0; end
endcase
end
always @(posedge clk) begin
if (!video_hon) hcnt <= hcnt - 1;
else hpos <= hpos + 1;
if (hpos == 639) video_hon <= 0;
if (hpos == 640) begin
if (!hcnt) begin
hcnt <= 96;
video_hsync <= 0;
hpos <= 0;
end
end else if (!hcnt) begin
if (!video_hsync) begin
video_hsync <= 1;
hcnt <= 48;
end else if (!video_hon) begin
video_hon <= 1;
hcnt <= 16;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void read(T &x) { x = 0; char c = getchar(); int flag = 0; while (c < 0 || c > 9 ) flag |= (c == - ), c = getchar(); while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); if (flag) x = -x; } template <class T> T _max(T a, T b) { return a > b ? a : b; } template <class T> T _min(T a, T b) { return a < b ? a : b; } template <class T> bool checkmax(T &a, T b) { return b > a ? a = b, 1 : 0; } template <class T> bool checkmin(T &a, T b) { return b < a ? a = b, 1 : 0; } const int N = 100005; int n; long long a[N]; int sg(long long x) { if (x <= 3) return 0; else if (x <= 15) return 1; else if (x <= 81) return 2; else if (x <= 6723) return 0; else if (x <= 50625) return 3; else if (x <= (long long)2562890625) return 1; else return 2; } void init() { read(n); for (int i = 1; i <= n; ++i) { read(a[i]); } } void solve() { int ans = 0; for (int i = 1; i <= n; ++i) { ans ^= sg(a[i]); } if (ans) printf( Furlo n ); else printf( Rublo n ); } int main() { int T = 1; while (T--) { init(); solve(); } return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_data_pipeline
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The TX Data pipeline module takes arbitrarily 32-bit aligned data
// from the WR_TX_DATA interface and shifts the data so that it is 0-bit
// aligned. This data is presented on a set of N fifos, where N =
// (C_DATA_WIDTH/32). Each fifo provides it's own VALID signal and is
// controlled by a READY signal. Each fifo also provides an independent DATA bus
// and additional END_FLAG signal which inidicates that the dword provided in this
// fifo is the last dword in the current payload. The START_FLAG signal indicates
// that the dword at index N = 0 is the start of a new packet.
//
// The TX Data Pipeline is built from two modules: tx_data_shift.v and
// tx_data_fifo.v. See these modules for more information.
//
// Author: Dustin Richmond (@darichmond)
//----------------------------------------------------------------------------
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_data_pipeline
#(parameter C_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_PAYLOAD_DWORDS = 256,
parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA")
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: WR TX DATA
input WR_TX_DATA_VALID,
input [C_DATA_WIDTH-1:0] WR_TX_DATA,
input WR_TX_DATA_START_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET,
input WR_TX_DATA_END_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET,
output WR_TX_DATA_READY,
// Interface: TX DATA FIFOS
input [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_READY,
output [C_DATA_WIDTH-1:0] RD_TX_DATA,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS,
output RD_TX_DATA_START_FLAG,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID,
output RD_TX_DATA_PACKET_VALID);
wire wRdTxDataValid;
wire wRdTxDataReady;
wire wRdTxDataStartFlag;
wire [C_DATA_WIDTH-1:0] wRdTxData;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wRdTxDataWordValid;
/*AUTOWIRE*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
tx_data_shift
#(.C_PIPELINE_OUTPUT (0),
/*AUTOINSTPARAM*/
// Parameters
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_VENDOR (C_VENDOR))
tx_shift_inst
(// Outputs
.RD_TX_DATA (wRdTxData),
.RD_TX_DATA_VALID (wRdTxDataValid),
.RD_TX_DATA_START_FLAG (wRdTxDataStartFlag),
.RD_TX_DATA_WORD_VALID (wRdTxDataWordValid),
.RD_TX_DATA_END_FLAGS (wRdTxDataEndFlags),
// Inputs
.RD_TX_DATA_READY (wRdTxDataReady),
/*AUTOINST*/
// Outputs
.WR_TX_DATA_READY (WR_TX_DATA_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_TX_DATA_VALID (WR_TX_DATA_VALID),
.WR_TX_DATA (WR_TX_DATA[C_DATA_WIDTH-1:0]),
.WR_TX_DATA_START_FLAG (WR_TX_DATA_START_FLAG),
.WR_TX_DATA_START_OFFSET (WR_TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_END_FLAG (WR_TX_DATA_END_FLAG),
.WR_TX_DATA_END_OFFSET (WR_TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]));
// TX Data Fifo
tx_data_fifo
#(// Parameters
.C_PIPELINE_INPUT (1),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
txdf_inst
(// Outputs
.WR_TX_DATA_READY (wRdTxDataReady),
.RD_TX_DATA (RD_TX_DATA[C_DATA_WIDTH-1:0]),
.RD_TX_DATA_START_FLAG (RD_TX_DATA_START_FLAG),
.RD_TX_DATA_WORD_VALID (RD_TX_DATA_WORD_VALID[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_END_FLAGS (RD_TX_DATA_END_FLAGS[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_PACKET_VALID (RD_TX_DATA_PACKET_VALID),
// Inputs
.WR_TX_DATA (wRdTxData),
.WR_TX_DATA_VALID (wRdTxDataValid),
.WR_TX_DATA_START_FLAG (wRdTxDataStartFlag),
.WR_TX_DATA_WORD_VALID (wRdTxDataWordValid),
.WR_TX_DATA_END_FLAGS (wRdTxDataEndFlags),
.RD_TX_DATA_WORD_READY (RD_TX_DATA_WORD_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_0_V
`define SKY130_FD_SC_LP__O21A_0_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21a_0 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21a_0 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_0_V
|
`timescale 1ns/1ns
module testbench;
parameter ADDRWIDTH = 4;
wire w_error, r_error;
reg rst_n = 1'b0;
reg w_clk = 1'b0;
reg r_clk = 1'b0;
wire #2 w_en = !w_full;
reg r_en = 1'b0;
wire w_full;
wire r_valid;
wire [ADDRWIDTH:0] r_counter;
wire [ADDRWIDTH:0] w_counter;
wire [7:0] dout;
reg [7:0] din = 8'd0, expected = 8'd0;
//
`include `PATTERN
//========================================
//
// Instantiation: asyn_fifo_xlx
//
//========================================
asyn_fifo_xlx #(
.FWFTEN ( FWFTEN ),
.ADDRWIDTH ( ADDRWIDTH ),
.DATAWIDTH ( 8 ),
.FIFODEPTH ( FIFODEPTH )
) dut (
.w_rst_n ( rst_n ), // I
.w_clk ( w_clk ), // I
.w_en ( w_en ), // I
.w_full ( w_full ), // O
.w_error ( w_error ), // O
.w_counter ( w_counter ), // O [ADDRWIDTH:0]
.w_data ( din ), // I [DATAWIDTH-1:0]
.r_rst_n ( rst_n ), // I
.r_clk ( r_clk ), // I
.r_en ( r_en ), // I
.r_valid ( r_valid ), // O
.r_error ( r_error ), // O
.r_counter ( r_counter ), // O [ADDRWIDTH:0]
.r_data ( dout ) // O [DATAWIDTH-1:0]
); // instantiation of asyn_fifo_xlx
always #5 w_clk = !w_clk;
always #3 r_clk = !r_clk;
initial begin
$dumpfile("fifo.dump");
$dumpvars(0,testbench);
end
initial begin
#10 rst_n = 1'b1;
@(negedge w_clk)
din = 8'hFF;
repeat(100) @(negedge w_clk)
if (!w_full) din = din + 1'b1;
end
initial begin
// test FULL
@(posedge w_full);
@(negedge r_clk) r_en = 1'b1;
// test Empty
if (FWFTEN == 0) wait(r_valid == 1);
@(r_valid == 0);
// test FWFT
@(negedge r_clk) r_en = 1'b0;
//
if (FWFTEN == 0) wait(w_full == 1);
else @(dout);
@(negedge r_clk) r_en = 1'b1;
//
#360 $finish;
end
initial begin
$display("\n Time : w_full (r_valid, dout) (w_counter, r_counter) (r_addr, rbin2) - (rptr-b, rptr-d)");
forever @(negedge r_clk) begin
$display("%6.0f : %b (%b %h) (%2d %2d) (%2d %2d) - %b %d", $time,
w_full, r_valid, dout, w_counter, r_counter, dut.r_ram_addr,
dut.fifo_controller_inst.read_inst.rbin2,
dut.fifo_controller_inst.read_inst.rptr, dut.fifo_controller_inst.read_inst.rptr);
if (r_valid && (expected != dout) ) begin
$display("data mismatched at time %6.3f : dout = %h, expected = %h", $time, dout, expected);
expected = dout;
end
if (r_valid && r_en)
expected = expected + 1'b1;
end
end
//
endmodule
|
#include <bits/stdc++.h> using namespace std; int triangle(long long n) { if (n == 1) return 1; else return n + triangle(n - 1); } int heart(long long a) { if (a == 1) return 1; else return (6 * (a - 1)) + heart(a - 1); } int balls(long long a) { if (a == 1) return 1; else return heart(a) + (triangle(a - 1) * 6); } int main() { long long a, b; cin >> a; b = balls(a); cout << b; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int minutes[n]; int result = -1; int lastN = 0; for (int i = 0; i < n; i++) { cin >> minutes[i]; if (i == 0 && minutes[0] > 15) { result = 15; } else if (result < 0 && minutes[i] - minutes[i - 1] > 15) { result = minutes[i - 1] + 15; } } if (result < 0) { result = minutes[n - 1] + 15; } if (result > 90) { result = 90; } cout << result; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long INFF = 0x3f3f3f3f3f3f3f3fll; const long long M = 1e9 + 7; const long long maxn = 1e6 + 7; const double pi = acos(-1.0); const double eps = 0.0000000001; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <typename T> inline void pr2(T x, int k = 64) { long long i; for (i = 0; i < k; i++) fprintf(stderr, %d , (x >> i) & 1); putchar( ); } template <typename T> inline void add_(T &A, int B) { A += B; (A >= M) && (A -= M); } template <typename T> inline void mul_(T &A, long long B) { (A *= B) %= M; } template <typename T> inline void mod_(T &A, long long B = M) { A %= M; } template <typename T> inline void max_(T &A, T B) { (A < B) && (A = B); } template <typename T> inline void min_(T &A, T B) { (A > B) && (A = B); } template <typename T> inline T abs(T a) { return a > 0 ? a : -a; } template <typename T> inline T powMM(T a, T b) { T ret = 1; for (; b; b >>= 1ll, a = (long long)a * a % M) if (b & 1) ret = (long long)ret * a % M; return ret; } int n, m, q; char str[maxn]; int TaskA(); void Task_one() { TaskA(); } void Task_T() { int T; scanf( %d , &T); while (T--) TaskA(); } void Task_more_n() { while (~scanf( %d , &n)) TaskA(); } void Task_more_n_m() { while (~scanf( %d%d , &n, &m)) TaskA(); } void Task_more_n_m_q() { while (~scanf( %d%d%d , &n, &m, &q)) TaskA(); } void Task_more_string() { while (~scanf( %s , str)) TaskA(); } int A[maxn]; int TaskA() { int i, t, k; scanf( %d%d , &n, &k); t = k; for (i = 1; i <= n; i++) scanf( %d , &A[i]), t = gcd(t, A[i]); printf( %d n , k / t); for (i = 0; i < k / t; i++) printf( %d , i * t); return 0; } void initialize() {} int main() { int startTime = clock(); initialize(); fprintf(stderr, /--- initializeTime: %ld milliseconds ---/ n , clock() - startTime); Task_one(); }
|
`timescale 1ns/1ns
module zmc(
input SDRD0,
input [1:0] SDA_L,
input [15:8] SDA_U,
output [21:11] MA
);
// Initialize ?
// Z80 ROM Region Reg
// 1E = F000~F7FF = F000~F7FF 1111 (0)
// 0E = E000~EFFF = E000~EFFF 1110 (1)
// 06 = C000~DFFF = C000~DFFF 110x (2)
// 02 = 8000~BFFF = 8000~BFFF 10xx (3)
// IIII Iiii
// MMMM M
// 0001 1110 -> 00 0xxx 1111 0--- ---- ----
// 0000 1110 -> 00 xxxx 1110 ---- ---- ----
// 0000 0110 -> 0x xxxx 110- ---- ---- ----
// 0000 0010 -> xx xxxx 10-- ---- ---- ----
// MA: xx xxxx xxxx x--- ---- ----
wire BANKSEL = SDA_U[15:8]; // SDA15 used for something else ?
reg [7:0] RANGE_0; // 2048 ? Can only access max. 512kB ROM
reg [7:0] RANGE_1; // 1024 ? Can only access max. 1MB ROM
reg [7:0] RANGE_2; // 512 ? Can only access max. 2MB ROM
reg [7:0] RANGE_3;
assign MA = SDA_U[15] ? // In mapped region ?
~SDA_U[14] ?
{RANGE_3, SDA_U[13:11]} : // 8000~BFFF
~SDA_U[13] ?
{1'b0, RANGE_2, SDA_U[12:11]} : // C000~DFFF
~SDA_U[12] ?
{2'b00, RANGE_1, SDA_U[11]} : // E000~EFFF
{3'b000, RANGE_0} : // F000~F7FF
{6'b000000, SDA_U[15:11]}; // Pass through
always @(posedge SDRD0)
begin
case (SDA_L)
0: RANGE_0 <= BANKSEL;
1: RANGE_1 <= BANKSEL;
2: RANGE_2 <= BANKSEL;
3: RANGE_3 <= BANKSEL;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; int a[maxn], n, s, b[maxn], num[maxn], len; int ufs[maxn], meme[maxn]; inline int find(int u) { if (ufs[u] == u) return u; else return ufs[u] = find(ufs[u]); } inline void join(int u, int v, int e) { u = find(u), v = find(v); if (u == v) return; ufs[v] = u; meme[u] = e; } vector<vector<int> > mema; vector<pair<int, int> > adj[maxn]; vector<int> curm; inline void dfs(int u) { while (adj[u].size()) { int v = adj[u].back().first, id = adj[u].back().second; adj[u].pop_back(); dfs(v); curm.push_back(id); } } int main() { cin >> n >> s; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); num[++len] = a[i]; } sort(num + 1, num + len + 1); len = unique(num + 1, num + len + 1) - num - 1; for (int i = 1; i <= n; i++) { a[i] = lower_bound(num + 1, num + len + 1, a[i]) - num; b[i] = a[i]; ufs[i] = i; } sort(b + 1, b + n + 1); int cnt = 0; for (int i = 1; i <= n; i++) { if (a[i] != b[i]) { cnt++; join(a[i], b[i], i); } } if (cnt > s) { cout << -1 << endl; return 0; } if (cnt == 0) { cout << 0 << endl; return 0; } if (s - cnt > 1) { for (int i = 1; i <= len; i++) { if (ufs[i] == i && meme[i] != 0) { curm.push_back(meme[i]); if (curm.size() == s - cnt) break; } } if (curm.size() > 1) { mema.push_back(curm); int lstv = a[curm.back()]; for (int i = curm.size() - 1; i >= 1; i--) { a[curm[i]] = a[curm[i - 1]]; } a[curm[0]] = lstv; } } for (int i = 1; i <= n; i++) { if (a[i] != b[i]) { adj[a[i]].push_back(make_pair(b[i], i)); } } for (int i = 1; i <= len; i++) { if (adj[i].size() != 0) { curm.clear(); dfs(i); mema.push_back(curm); } } cout << mema.size() << endl; for (int i = 0; i < mema.size(); i++) { cout << mema[i].size() << endl; for (int j = 0; j < mema[i].size(); j++) { printf( %d , mema[i][j]); } cout << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:26:36 07/12/2015
// Design Name:
// Module Name: MemoryAdapter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MemoryAdapter
( input PixelClk2,
output reg [23:0] ExtAddr,
output reg [15:0] ExtDataWrite,
output reg [1:0] ExtDataMask,
input [15:0] ExtDataRead,
output reg ExtOP,
output reg ExtReq,
input ExtReady,
input [24:0] Address,
input [31:0] DataWrite,
output reg [31:0] DataRead,
input [1:0] DataSize, // 01: 8bit - 11: 32bit - 00|10: 16bit
input ReadWrite,
input Request,
output reg Ready
);
integer Status;
reg [24:0] SaveAddr;
reg [31:0] SaveData;
reg [1:0] SaveSize;
reg SaveOP;
initial
begin
Status = 0;
ExtReq = 0;
DataRead = 0;
ExtAddr = 0;
ExtDataWrite = 0;
ExtDataMask = 0;
ExtOP = 0;
Ready = 0;
end
always @(posedge PixelClk2)
begin
case(Status)
0: begin
Ready = 1;
Status = 1;
end
1: begin
if (Request == 1)
begin
SaveAddr = Address;
SaveData = DataWrite;
SaveSize = (DataSize == 2'b00) ? 2'b10 : DataSize;
SaveOP = ReadWrite;
Ready = 0;
Status = 2;
end
else Status = 1;
end
2: begin
if (ExtReady == 1)
begin
case(SaveOP)
1: begin // WRITE
case(SaveSize)
2'b01: begin // Byte
ExtAddr = SaveAddr[24:1];
ExtDataWrite = (SaveAddr[0]==0) ? {8'h00,SaveData[7:0]} : {SaveData[7:0],8'h00};
ExtDataMask = (SaveAddr[0]==0) ? 2'b10 : 2'b01;
ExtOP = 1;
ExtReq = 1;
Status = 3;
end
2'b11: begin // Double
ExtAddr = {SaveAddr[24:2],1'b0};
ExtDataWrite = SaveData[15:0];
ExtDataMask = 2'b00;
ExtOP = 1;
ExtReq = 1;
Status = 6;
end
default: begin // Word
ExtAddr = SaveAddr[24:1];
ExtDataWrite = SaveData[15:0];
ExtDataMask = 2'b00;
ExtOP = 1;
ExtReq = 1;
Status = 3;
end
endcase
end
default: begin // READ
case(SaveSize)
2'b01: begin // Byte
ExtAddr = SaveAddr[24:1];
ExtDataMask = 2'b00;
ExtOP = 0;
ExtReq = 1;
Status = 5;
end
2'b11: begin // Double
ExtAddr = {SaveAddr[24:2],1'b0};
ExtDataMask = 2'b00;
ExtOP = 0;
ExtReq = 1;
Status = 8;
end
default: begin // Word
ExtAddr = SaveAddr[24:1];
ExtDataMask = 2'b00;
ExtOP = 0;
ExtReq = 1;
Status = 4;
end
endcase
end
endcase
end
else Status = 2;
end
3: begin
if (ExtReady == 0) Status = 0;
else Status = 3;
end
4: begin
if (ExtReady == 0)
begin
DataRead = {16'h0000,ExtDataRead};
Status = 0;
end
else Status = 4;
end
5: begin
if (ExtReady == 0)
begin
DataRead = (SaveAddr[0]==1) ? {24'h000000,ExtDataRead[7:0]} : {24'h000000,ExtDataRead[15:8]};
Status = 0;
end
else Status = 5;
end
6: begin
if (ExtReady == 0) Status = 7;
else Status = 6;
end
7: begin
if (ExtReady == 1)
begin
ExtAddr = {SaveAddr[24:2],1'b1};
ExtDataWrite = SaveData[31:16];
ExtDataMask = 2'b00;
ExtOP = 1;
ExtReq = 1;
Status = 3;
end
else Status = 7;
end
8: begin
if (ExtReady == 0)
begin
DataRead[15:0] = ExtDataRead;
Status = 9;
end
else Status = 8;
end
9: begin
if (ExtReady == 1)
begin
ExtAddr = {SaveAddr[24:2],1'b1};
ExtDataMask = 2'b00;
ExtOP = 0;
ExtReq = 1;
Status = 10;
end
else Status = 9;
end
10: begin
if (ExtReady == 0)
begin
DataRead[31:16] = ExtDataRead;
Status = 0;
end
else Status = 10;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = (int)3e5 + 10; struct node { int nxt, to; } edg[maxn * 2]; int head[maxn], num; int f[maxn], n, a[maxn]; void add(int a, int b) { edg[++num].to = b; edg[num].nxt = head[a]; head[a] = num; } int k = 0; void dfs(int root) { if (head[root] == 0) { f[root] = 1; k++; return; } if (a[root] == 1) f[root] = 1e7; int t = head[root]; while (t != 0) { dfs(edg[t].to); if (a[root] == 1) { f[root] = min(f[root], f[edg[t].to]); } else { f[root] += f[edg[t].to]; } t = edg[t].nxt; } } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 2; i <= n; i++) { int fat; cin >> fat; add(fat, i); } dfs(1); cout << k + 1 - f[1]; return 0; }
|
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1 ns/1ps
module node_tb();
reg clk = 0;
reg [2:0] weight = 0;
reg [7:0] dataIn = 0;
wire dataOut;
node UUT(
.clk (clk),
.en (1'b1),
.weight (weight),
.dataIn (dataIn),
.dataOut (dataOut)
);
always
#5 clk = ~clk;
always begin
dataIn = 8'd5;
#50 weight = 3'd1;
#50 weight = 3'd2;
#50 weight = 3'd3;
#50 weight = 3'd4;
#50 weight = 3'd5;
#50 weight = 3'd6;
#50 weight = 3'd7;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2B_FUNCTIONAL_PP_V
|
//////////////////////////////////////////////////////////////////
// //
// Clock and Resets //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Takes in the 200MHx board clock and generates the main //
// system clock. For the FPGA this is done with a PLL. //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`include "system_config_defines.v"
//
// Clocks and Resets Module
//
module clocks_resets (
input i_brd_rst,
input i_brd_clk_n,
input i_brd_clk_p,
input i_ddr_calib_done,
output o_sys_rst,
output o_sys_clk,
output o_clk_200
);
wire calib_done_33mhz;
wire rst0;
assign o_sys_rst = rst0 || !calib_done_33mhz;
`ifdef XILINX_FPGA
localparam RST_SYNC_NUM = 25;
wire pll_locked;
wire clkfbout_clkfbin;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
reg [RST_SYNC_NUM-1:0] ddr_calib_done_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
wire pll_clk;
(* KEEP = "TRUE" *) wire brd_clk_ibufg;
IBUFGDS # (
.DIFF_TERM ( "TRUE" ),
.IOSTANDARD ( "LVDS_25" )) // SP605 on chip termination of LVDS clock
u_ibufgds_brd
(
.I ( i_brd_clk_p ),
.IB ( i_brd_clk_n ),
.O ( brd_clk_ibufg )
);
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
assign calib_done_33mhz = ddr_calib_done_sync_r[RST_SYNC_NUM-1];
assign o_clk_200 = brd_clk_ibufg;
`ifdef XILINX_SPARTAN6_FPGA
// ======================================
// Xilinx Spartan-6 PLL
// ======================================
PLL_ADV #
(
.BANDWIDTH ( "OPTIMIZED" ),
.CLKIN1_PERIOD ( 5 ),
.CLKIN2_PERIOD ( 1 ),
.CLKOUT0_DIVIDE ( 1 ),
.CLKOUT1_DIVIDE ( ),
.CLKOUT2_DIVIDE ( `AMBER_CLK_DIVIDER ), // = 800 MHz / LP_CLK_DIVIDER
.CLKOUT3_DIVIDE ( 1 ),
.CLKOUT4_DIVIDE ( 1 ),
.CLKOUT5_DIVIDE ( 1 ),
.CLKOUT0_PHASE ( 0.000 ),
.CLKOUT1_PHASE ( 0.000 ),
.CLKOUT2_PHASE ( 0.000 ),
.CLKOUT3_PHASE ( 0.000 ),
.CLKOUT4_PHASE ( 0.000 ),
.CLKOUT5_PHASE ( 0.000 ),
.CLKOUT0_DUTY_CYCLE ( 0.500 ),
.CLKOUT1_DUTY_CYCLE ( 0.500 ),
.CLKOUT2_DUTY_CYCLE ( 0.500 ),
.CLKOUT3_DUTY_CYCLE ( 0.500 ),
.CLKOUT4_DUTY_CYCLE ( 0.500 ),
.CLKOUT5_DUTY_CYCLE ( 0.500 ),
.COMPENSATION ( "INTERNAL" ),
.DIVCLK_DIVIDE ( 1 ),
.CLKFBOUT_MULT ( 4 ), // 200 MHz clock input, x4 to get 800 MHz MCB
.CLKFBOUT_PHASE ( 0.0 ),
.REF_JITTER ( 0.005000 )
)
u_pll_adv
(
.CLKFBIN ( clkfbout_clkfbin ),
.CLKINSEL ( 1'b1 ),
.CLKIN1 ( brd_clk_ibufg ),
.CLKIN2 ( 1'b0 ),
.DADDR ( 5'b0 ),
.DCLK ( 1'b0 ),
.DEN ( 1'b0 ),
.DI ( 16'b0 ),
.DWE ( 1'b0 ),
.REL ( 1'b0 ),
.RST ( i_brd_rst ),
.CLKFBDCM ( ),
.CLKFBOUT ( clkfbout_clkfbin ),
.CLKOUTDCM0 ( ),
.CLKOUTDCM1 ( ),
.CLKOUTDCM2 ( ),
.CLKOUTDCM3 ( ),
.CLKOUTDCM4 ( ),
.CLKOUTDCM5 ( ),
.CLKOUT0 ( ),
.CLKOUT1 ( ),
.CLKOUT2 ( pll_clk ),
.CLKOUT3 ( ),
.CLKOUT4 ( ),
.CLKOUT5 ( ),
.DO ( ),
.DRDY ( ),
.LOCKED ( pll_locked )
);
`endif
`ifdef XILINX_VIRTEX6_FPGA
// ======================================
// Xilinx Virtex-6 PLL
// ======================================
MMCM_ADV #
(
.CLKIN1_PERIOD ( 5 ), // 200 MHz
.CLKOUT2_DIVIDE ( `AMBER_CLK_DIVIDER ),
.CLKFBOUT_MULT_F ( 6 ) // 200 MHz x 6 = 1200 MHz
)
u_pll_adv
(
.CLKFBOUT ( clkfbout_clkfbin ),
.CLKFBOUTB ( ),
.CLKFBSTOPPED ( ),
.CLKINSTOPPED ( ),
.CLKOUT0 ( ),
.CLKOUT0B ( ),
.CLKOUT1 ( ),
.CLKOUT1B ( ),
.CLKOUT2 ( pll_clk ),
.CLKOUT2B ( ),
.CLKOUT3 ( ),
.CLKOUT3B ( ),
.CLKOUT4 ( ),
.CLKOUT5 ( ),
.CLKOUT6 ( ),
.DRDY ( ),
.LOCKED ( pll_locked ),
.PSDONE ( ),
.DO ( ),
.CLKFBIN ( clkfbout_clkfbin ),
.CLKIN1 ( brd_clk_ibufg ),
.CLKIN2 ( 1'b0 ),
.CLKINSEL ( 1'b1 ),
.DCLK ( 1'b0 ),
.DEN ( 1'b0 ),
.DWE ( 1'b0 ),
.PSCLK ( 1'd0 ),
.PSEN ( 1'd0 ),
.PSINCDEC ( 1'd0 ),
.PWRDWN ( 1'd0 ),
.RST ( i_brd_rst ),
.DI ( 16'b0 ),
.DADDR ( 7'b0 )
);
`endif
BUFG u_bufg_sys_clk (
.O ( o_sys_clk ),
.I ( pll_clk )
);
// ======================================
// Synchronous reset generation
// ======================================
assign rst_tmp = i_brd_rst | ~pll_locked;
// synthesis attribute max_fanout of rst0_sync_r is 10
always @(posedge o_sys_clk or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
always @(posedge o_sys_clk or posedge rst_tmp)
if (rst_tmp)
ddr_calib_done_sync_r <= {RST_SYNC_NUM{1'b0}};
else
ddr_calib_done_sync_r <= {ddr_calib_done_sync_r[RST_SYNC_NUM-2:0], i_ddr_calib_done};
`endif
`ifndef XILINX_FPGA
real brd_clk_period = 6000; // use starting value of 6000pS
real pll_clk_period = 1000; // use starting value of 1000pS
real brd_temp;
reg pll_clk_beh;
reg sys_clk_beh;
integer pll_div_count = 0;
// measure input clock period
initial
begin
@ (posedge i_brd_clk_p)
brd_temp = $time;
@ (posedge i_brd_clk_p)
brd_clk_period = $time - brd_temp;
pll_clk_period = brd_clk_period / 4;
end
// Generate an 800MHz pll clock based off the input clock
always @( posedge i_brd_clk_p )
begin
pll_clk_beh = 1'd1;
# ( pll_clk_period / 2 )
pll_clk_beh = 1'd0;
# ( pll_clk_period / 2 )
pll_clk_beh = 1'd1;
# ( pll_clk_period / 2 )
pll_clk_beh = 1'd0;
# ( pll_clk_period / 2 )
pll_clk_beh = 1'd1;
# ( pll_clk_period / 2 )
pll_clk_beh = 1'd0;
# ( pll_clk_period / 2 )
pll_clk_beh = 1'd1;
# ( pll_clk_period / 2 )
pll_clk_beh = 1'd0;
end
// Divide the pll clock down to get the system clock
always @( pll_clk_beh )
begin
if ( pll_div_count == (
`AMBER_CLK_DIVIDER
* 2 ) - 1 )
pll_div_count <= 'd0;
else
pll_div_count <= pll_div_count + 1'd1;
if ( pll_div_count == 0 )
sys_clk_beh = 1'd1;
else if ( pll_div_count ==
`AMBER_CLK_DIVIDER
)
sys_clk_beh = 1'd0;
end
assign o_sys_clk = sys_clk_beh;
assign rst0 = i_brd_rst;
assign calib_done_33mhz = 1'd1;
assign o_clk_200 = i_brd_clk_p;
`endif
endmodule
|
module memory (
input clk,
input [15:0] in,
input [14:0] address,
input [12:0] screen_read_address,
input load,
input [7:0] keyboard,
output [15:0] out,
// Screen
//output [12:0] screen_address, // ram address to write the pixel data
//output [15:0] screen_data, // pixel values for ram address in the buffer
//output screen_we, // load the screen data into the screen address
output [15:0] read_value,
output ready
);
reg [31:0] timer = 32'b0;
reg r_ready = 1'b0;
assign ready = r_ready; // Set to ready when memory is initialised.
reg r_screen_we;
wire screen_we;
reg [12:0] r_screen_write_address = 13'b0;
wire [12:0] screen_write_address;
assign screen_write_address = r_screen_write_address;
reg [14:0] r_screen_address;
reg [15:0] r_screen_data;
//assign screen_data = r_screen_data;
//assign screen_data = in;
//assign screen_address = r_screen_address[12:0];
//assign screen_address = address[12:0];
assign screen_we = r_screen_we;
//assign screen_we = 1'b1;
reg [15:0] r_out = 16'b0;
assign out = r_out;
reg [15:0] r_in;
reg[15:0] r_mem_ram;
wire [13:0] write_address, read_address;
wire [15:0] ram_q;
reg ram_we;
ram_16 ram16(
.q(ram_q), // from ram
.d(in), // to ram
.write_address(address[13:0]), // where to write in ram
.read_address(address[13:0]), // where to read from
.we(ram_we), // do a write
.clk(clk)
);
// Screen ram
vga_ram vgaram(
.q(read_value), // from ram
.d(in), // to ram
.write_address(address[12:0]), // where to write in ram
.read_address(screen_read_address), // where to read from
.we(screen_we), // do a write
.clk(clk)
);
always @(posedge clk) begin
if (timer == 32'd25000000) begin
// ready
r_ready <= 1'b1;
end else begin
timer <= timer + 32'b1;
end
end
always @(posedge clk) begin
if (address == 15'd24576) begin
r_out <= keyboard;
end if (address < 15'd16384) begin
r_out <= ram_q;
end
end
always @ (posedge clk) begin
ram_we = 1'b0;
if (load) begin
if (address < 15'd16384) begin
ram_we = 1'b1;
end
end
end
always @ (posedge clk) begin
if (load) begin
if (address >= 15'd16384) begin
r_screen_we <= 1'b1;
r_screen_write_address <= address - 15'd16384;
end else begin
r_screen_we <= 1'b0;
end
end else begin
r_screen_we <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long x, y, p, q; int main() { int t; scanf( %d , &t); int x, y, p, q; while (t--) { scanf( %d %d %d %d , &x, &y, &p, &q); if (p == q) { printf( %d n , x == y ? 0 : -1); continue; } if (p == 0) { printf( %d n , x == 0 ? 0 : -1); continue; } long long s, d; s = x % p == 0 ? (x / p) : (x / p + 1); d = (y - x) % (q - p) == 0 ? ((y - x) / (q - p)) : ((y - x) / (q - p) + 1); printf( %lld n , (max(s, d)) * q - y); } }
|
#include<bits/stdc++.h> using namespace std; int a, b; bool check(int cnt) { int cnt6 = cnt/6; int cnt2 = cnt/2 - cnt6; int cnt3 = cnt/3 - cnt6; if(cnt2 <= a) { cnt6 -= a-cnt2; } if(cnt3 <= b) { cnt6 -= b-cnt3; } return cnt6 >= 0; } int main() { #ifdef DEBUG a = 0, b = 1000000; #elif not defined(DEBUG) cin>>a>>b; #endif int l = max(a<<1, b*3); int r = l<<1; while(l+100<r) { int mid = (l+r)>>1; if(check(mid)) r = mid; else l = mid; } for(int i = l;i<=r;i++) if(check(i)) { cout<<i<<endl; break; } return 0; }
|
/*
* blocksyn1.v
* This tests synthesis where statements in a block override previous
* statements in a block and also uses other previous statements in the
* block. Note in this example that the flag assignment is completely
* overruled by the conditional that is directly after it.
*/
module main;
reg [1:0] out;
reg flag;
reg [1:0] sel;
(* ivl_synthesis_on, ivl_combinational *)
always @*
begin
out = 2'b00;
case (sel)
2'b00: out = 2'b11;
2'b01: out = 2'b10;
2'b10: out = 2'b01;
endcase // case(sel)
// This flag is overridded by the true clause, so the
// synthesizer should move the first assignment to the
// else clause of the if.
flag = 1'b0;
if (out == 2'b00)
flag = 1'b1;
end
reg [2:0] idx;
reg test;
(* ivl_synthesis_off *)
initial begin
for (idx = 0 ; idx < 7 ; idx = idx + 1) begin
sel = idx[1:0];
#1 if (out !== ~sel) begin
$display("FAILED -- sel=%b, out=%b, flag=%b", sel, out, flag);
$finish;
end
test = (out == 2'b00)? 1'b1 : 1'b0;
if (test !== flag) begin
$display("FAILED -- test=%b, sel=%b, out=%b, flag=%b",
test, sel, out, flag);
$finish;
end
end // for (idx = 0 ; idx < 7 ; idx = idx + 1)
$display("PASSED");
end // initial begin
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DFBBN_FUNCTIONAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr/sky130_fd_sc_lp__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_lp__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_lp__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBN_FUNCTIONAL_V
|
// -*- Mode: Verilog -*-
// Filename : burst_00.v
// Description : Test burst read/write interfacing
// Author : Philip Tracton
// Created On : Tue Jun 28 11:31:45 2016
// Last Modified By: Philip Tracton
// Last Modified On: Tue Jun 28 11:31:45 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "simulation_includes.vh"
module test_case (/*AUTOARG*/ ) ;
//
// Test Configuration
// These parameters need to be set for each test case
//
parameter simulation_name = "burst_00";
parameter number_of_tests = 15;
reg err;
reg [31:0] data_out;
reg [15:0] i;
reg [15:0] index ;
//
// Can't pass memories to tasks, so gigantic arrays!
//
reg [(16*7):0] write_mem = 0;
reg [(16*7):0] read_mem = 0;
initial begin
$display("Test 00 Case");
`TB.master_bfm.reset;
@(posedge `WB_RST);
@(negedge `WB_RST);
@(posedge `WB_CLK);
@(negedge `ADXL362_RESET);
`SIMPLE_SPI_INIT;
`ADXL362_WRITE_DOUBLE_REGISTER(`ADXL362_THRESH_ACT_LOW, 16'h6507);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_THRESH_ACT_LOW, 16'h507);
repeat(100) @(posedge `WB_CLK);
for (i = 0; i< 14; i= i+1) begin
write_mem[(i*8)+7 -: 8] = i | 8'h80;
end
repeat(100) @(posedge `WB_CLK);
`ADXL362_WRITE_BURST_REGISTERS(`ADXL362_THRESH_ACT_LOW, write_mem, 14);
repeat(50) @(posedge `WB_CLK);
`ADXL362_READ_BURST_REGISTERS(`ADXL362_THRESH_ACT_LOW, read_mem, 14);
//$display("Read Mem 0x%x", read_mem);
`TEST_COMPARE("Reg 0", 8'h80, read_mem[7:0]);
`TEST_COMPARE("Reg 1", 8'h01, read_mem[15:8]);
`TEST_COMPARE("Reg 2", 8'h82, read_mem[23:16]);
`TEST_COMPARE("Reg 3", 8'h83, read_mem[31:24]);
`TEST_COMPARE("Reg 4", 8'h04, read_mem[39:32]);
`TEST_COMPARE("Reg 5", 8'h85, read_mem[47:40]);
`TEST_COMPARE("Reg 6", 8'h86, read_mem[55:48]);
`TEST_COMPARE("Reg 7", 8'h00, read_mem[63:56]);
`TEST_COMPARE("Reg 8", 8'h08, read_mem[71:64]);
`TEST_COMPARE("Reg 9", 8'h89, read_mem[79:72]);
`TEST_COMPARE("Reg 10", 8'h8a, read_mem[87:80]);
`TEST_COMPARE("Reg 11", 8'h8b, read_mem[95:88]);
`TEST_COMPARE("Reg 12", 8'h8c, read_mem[103:96]);
`TEST_COMPARE("Reg 13", 8'h8d, read_mem[111:104]);
/* -----\/----- EXCLUDED -----\/-----
$display("MEM 0: 0x%x", read_mem[07:00]);
$display("MEM 1: 0x%x", read_mem[15:08]);
$display("MEM 2: 0x%x", read_mem[23:16]);
$display("MEM 3: 0x%x", read_mem[31:24]);
$display("MEM 4: 0x%x", read_mem[39:32]);
$display("MEM 5: 0x%x", read_mem[47:40]);
$display("MEM 6: 0x%x", read_mem[55:48]);
$display("MEM 7: 0x%x", read_mem[63:56]);
$display("MEM 8: 0x%x", read_mem[71:64]);
$display("MEM 9: 0x%x", read_mem[79:72]);
$display("MEM 10: 0x%x", read_mem[87:80]);
$display("MEM 11: 0x%x", read_mem[95:88]);
$display("MEM 12: 0x%x", read_mem[103:96]);
$display("MEM 13: 0x%x", read_mem[111:104]);
-----/\----- EXCLUDED -----/\----- */
repeat(10) @(posedge `WB_CLK);
`TEST_COMPLETE;
end
endmodule // test_case
|
////JAI SHREE RAM//// #include <iostream> #include<bits/stdc++.h> using namespace std; const long long int INF = (long long)1e15; const long long int mod = 1e9+7; #define ll long long #define f(i,a,b) for(int i=a;i<b;i++) #define pb push_back #define all(c) c.begin(),c.end() #define rall(c) c.rbegin(),c.rend() #define yes cout<< YES n #define no cout<< NO n #define sd second #define ft first // bool cmp(const pair<int,int> &a, const pair<int,int> &b) { //return (a.sd>=b.sd); return abs(a.ft)+abs(a.sd) < abs(b.ft)+abs(b.sd); } void solve() { int n;cin>>n; int o=0; n*=2; f(i,0,n){ int x;cin>>x; if(x%2) o++; } if(o==n/2) yes; else no; } int main() { //ios_base::sync_with_stdio(false); cin.tie(0);cout.tie(0); int t=1; cin>>t; while(t--) { solve(); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:18:20 PM
// Design Name:
// Module Name: Mux_Array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// synopsys dc_script_begin
//
// synopsys dc_script_end
module Multiplexer_AC
# (parameter W = 32)
(
input wire ctrl,
input wire [W-1:0] D0,
input wire [W-1:0] D1,
output reg [W-1:0] S
);
always @(ctrl, D0, D1)
case (ctrl)
1'b0: S <= D0;
1'b1: S <= D1;
endcase
endmodule
module Rotate_Mux_Array
#(parameter SWR=26)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
output wire [SWR-1:0] Data_o
);
genvar j;//Create a variable for the loop FOR
generate for (j=0; j <= SWR-1; j=j+1) begin : MUX_ARRAY
case (j)
SWR-1-j:begin : MUX_ARRAY11
assign Data_o[j]=Data_i[SWR-1-j];
end
default:begin : MUX_ARRAY12
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[SWR-1-j]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
module DW_rbsh_inst #(parameter SWR = 8, parameter EWR = 3) ( Data_i, Shift_Value_i, inst_SH_TC, Data_o );
//Barrel Shifter with Preferred Right Direction
input [SWR-1 : 0] Data_i;
input [EWR-1 : 0] Shift_Value_i;
input inst_SH_TC;
output [SWR-1 : 0] Data_o;
// Instance of DW_rbsh
DW_rbsh #(SWR, EWR) U1 (
.A(Data_i),
.SH(Shift_Value_i),
.SH_TC(inst_SH_TC),
.B(Data_o) );
endmodule
module Mux_Array_DW
#(parameter SWR=26, parameter EWR=5)
(
input wire clk,
input wire rst,
input wire [SWR-1:0] Data_i,
input wire FSM_left_right_i,
input wire [EWR-1:0] Shift_Value_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
////ge
wire [SWR:0] Data_array[EWR+1:0];
assign Data_array [0] = {Data_i, bit_shift_i};
//////////////////7
genvar k;//Level
///////////////////77777
Rotate_Mux_Array #(.SWR(SWR+1)) first_rotate(
.Data_i(Data_array [0] ),
.select_i(FSM_left_right_i),
.Data_o(Data_array [1][SWR:0])
);
DW_rbsh_inst #(
.SWR(SWR+1),
.EWR(EWR)
) inst_DW_rbsh_inst (
.Data_i (Data_array [2][SWR:0]),
.Shift_Value_i (Shift_Value_i),
.inst_SH_TC (FSM_left_right_i),
.Data_o (Data_array [3][SWR:0])
);
Rotate_Mux_Array #(.SWR(SWR+1) last_rotate(
.Data_i(Data_array [4][SWR:0]),
.select_i(FSM_left_right_i),
.Data_o(Data_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long dp[255][255]; long long p[255], q[255], C[255][255]; int N; long long K; void init() { cin >> N >> K; p[0] = q[0] = C[0][0] = 1; for (int i = 1; i <= 250; i++) { p[i] = p[i - 1] * K % MOD; q[i] = q[i - 1] * (K - 1) % MOD; C[i][0] = 1; for (int j = 1; j <= i; j++) { C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % MOD; } } } void solve() { dp[0][0] = 1; for (int r = 1; r <= N; r++) { for (int c = 1; c <= N; c++) { for (int a = 0; a <= c; a++) { if (a == c) { dp[r][c] = (dp[r][c] + ((p[c] + MOD - q[c]) * q[N - c] % MOD * dp[r - 1][c] % MOD)) % MOD; } else { dp[r][c] = (dp[r][c] + (C[N - a][c - a] * p[a] % MOD * q[N - c] % MOD * dp[r - 1][a] % MOD)) % MOD; } } } } cout << dp[N][N] << n ; } int main() { init(); solve(); }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int n = s.length(); bool ok = false; for (int i = 0; i < n - 1; i++) { if (s[i] == A && s[i + 1] == B ) { for (int j = i + 2; j < n - 1; j++) { if (s[j] == B && s[j + 1] == A ) { ok = true; break; } } } if (ok) break; } if (ok) { cout << YES n ; return 0; } for (int i = 0; i < n - 1; i++) { if (s[i] == B && s[i + 1] == A ) { for (int j = i + 2; j < n - 1; j++) { if (s[j] == A && s[j + 1] == B ) { ok = true; break; } } } if (ok) break; } if (ok) cout << YES n ; else cout << NO n ; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1 << 28; const double INF = 1e12, EPS = 1e-9; int n, m, c[101]; void run() { cin >> n >> m; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; for (; a <= b; a++) c[a]++; } for (int i = 1; i <= n; i++) if (c[i] != 1) { cout << i << << c[i] << endl; return; } cout << OK << endl; } int main() { run(); }
|
module soc_system (
button_pio_external_connection_export,
clk_clk,
dipsw_pio_external_connection_export,
hps_0_f2h_cold_reset_req_reset_n,
hps_0_f2h_debug_reset_req_reset_n,
hps_0_f2h_stm_hw_events_stm_hwevents,
hps_0_f2h_warm_reset_req_reset_n,
hps_0_h2f_reset_reset_n,
hps_0_hps_io_hps_io_emac1_inst_TX_CLK,
hps_0_hps_io_hps_io_emac1_inst_TXD0,
hps_0_hps_io_hps_io_emac1_inst_TXD1,
hps_0_hps_io_hps_io_emac1_inst_TXD2,
hps_0_hps_io_hps_io_emac1_inst_TXD3,
hps_0_hps_io_hps_io_emac1_inst_RXD0,
hps_0_hps_io_hps_io_emac1_inst_MDIO,
hps_0_hps_io_hps_io_emac1_inst_MDC,
hps_0_hps_io_hps_io_emac1_inst_RX_CTL,
hps_0_hps_io_hps_io_emac1_inst_TX_CTL,
hps_0_hps_io_hps_io_emac1_inst_RX_CLK,
hps_0_hps_io_hps_io_emac1_inst_RXD1,
hps_0_hps_io_hps_io_emac1_inst_RXD2,
hps_0_hps_io_hps_io_emac1_inst_RXD3,
hps_0_hps_io_hps_io_sdio_inst_CMD,
hps_0_hps_io_hps_io_sdio_inst_D0,
hps_0_hps_io_hps_io_sdio_inst_D1,
hps_0_hps_io_hps_io_sdio_inst_CLK,
hps_0_hps_io_hps_io_sdio_inst_D2,
hps_0_hps_io_hps_io_sdio_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D0,
hps_0_hps_io_hps_io_usb1_inst_D1,
hps_0_hps_io_hps_io_usb1_inst_D2,
hps_0_hps_io_hps_io_usb1_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D4,
hps_0_hps_io_hps_io_usb1_inst_D5,
hps_0_hps_io_hps_io_usb1_inst_D6,
hps_0_hps_io_hps_io_usb1_inst_D7,
hps_0_hps_io_hps_io_usb1_inst_CLK,
hps_0_hps_io_hps_io_usb1_inst_STP,
hps_0_hps_io_hps_io_usb1_inst_DIR,
hps_0_hps_io_hps_io_usb1_inst_NXT,
hps_0_hps_io_hps_io_spim1_inst_CLK,
hps_0_hps_io_hps_io_spim1_inst_MOSI,
hps_0_hps_io_hps_io_spim1_inst_MISO,
hps_0_hps_io_hps_io_spim1_inst_SS0,
hps_0_hps_io_hps_io_uart0_inst_RX,
hps_0_hps_io_hps_io_uart0_inst_TX,
hps_0_hps_io_hps_io_i2c0_inst_SDA,
hps_0_hps_io_hps_io_i2c0_inst_SCL,
hps_0_hps_io_hps_io_i2c1_inst_SDA,
hps_0_hps_io_hps_io_i2c1_inst_SCL,
hps_0_hps_io_hps_io_gpio_inst_GPIO09,
hps_0_hps_io_hps_io_gpio_inst_GPIO35,
hps_0_hps_io_hps_io_gpio_inst_GPIO40,
hps_0_hps_io_hps_io_gpio_inst_GPIO53,
hps_0_hps_io_hps_io_gpio_inst_GPIO54,
hps_0_hps_io_hps_io_gpio_inst_GPIO61,
led_pio_external_connection_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n);
input [3:0] button_pio_external_connection_export;
input clk_clk;
input [3:0] dipsw_pio_external_connection_export;
input hps_0_f2h_cold_reset_req_reset_n;
input hps_0_f2h_debug_reset_req_reset_n;
input [27:0] hps_0_f2h_stm_hw_events_stm_hwevents;
input hps_0_f2h_warm_reset_req_reset_n;
output hps_0_h2f_reset_reset_n;
output hps_0_hps_io_hps_io_emac1_inst_TX_CLK;
output hps_0_hps_io_hps_io_emac1_inst_TXD0;
output hps_0_hps_io_hps_io_emac1_inst_TXD1;
output hps_0_hps_io_hps_io_emac1_inst_TXD2;
output hps_0_hps_io_hps_io_emac1_inst_TXD3;
input hps_0_hps_io_hps_io_emac1_inst_RXD0;
inout hps_0_hps_io_hps_io_emac1_inst_MDIO;
output hps_0_hps_io_hps_io_emac1_inst_MDC;
input hps_0_hps_io_hps_io_emac1_inst_RX_CTL;
output hps_0_hps_io_hps_io_emac1_inst_TX_CTL;
input hps_0_hps_io_hps_io_emac1_inst_RX_CLK;
input hps_0_hps_io_hps_io_emac1_inst_RXD1;
input hps_0_hps_io_hps_io_emac1_inst_RXD2;
input hps_0_hps_io_hps_io_emac1_inst_RXD3;
inout hps_0_hps_io_hps_io_sdio_inst_CMD;
inout hps_0_hps_io_hps_io_sdio_inst_D0;
inout hps_0_hps_io_hps_io_sdio_inst_D1;
output hps_0_hps_io_hps_io_sdio_inst_CLK;
inout hps_0_hps_io_hps_io_sdio_inst_D2;
inout hps_0_hps_io_hps_io_sdio_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D0;
inout hps_0_hps_io_hps_io_usb1_inst_D1;
inout hps_0_hps_io_hps_io_usb1_inst_D2;
inout hps_0_hps_io_hps_io_usb1_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D4;
inout hps_0_hps_io_hps_io_usb1_inst_D5;
inout hps_0_hps_io_hps_io_usb1_inst_D6;
inout hps_0_hps_io_hps_io_usb1_inst_D7;
input hps_0_hps_io_hps_io_usb1_inst_CLK;
output hps_0_hps_io_hps_io_usb1_inst_STP;
input hps_0_hps_io_hps_io_usb1_inst_DIR;
input hps_0_hps_io_hps_io_usb1_inst_NXT;
output hps_0_hps_io_hps_io_spim1_inst_CLK;
output hps_0_hps_io_hps_io_spim1_inst_MOSI;
input hps_0_hps_io_hps_io_spim1_inst_MISO;
output hps_0_hps_io_hps_io_spim1_inst_SS0;
input hps_0_hps_io_hps_io_uart0_inst_RX;
output hps_0_hps_io_hps_io_uart0_inst_TX;
inout hps_0_hps_io_hps_io_i2c0_inst_SDA;
inout hps_0_hps_io_hps_io_i2c0_inst_SCL;
inout hps_0_hps_io_hps_io_i2c1_inst_SDA;
inout hps_0_hps_io_hps_io_i2c1_inst_SCL;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO09;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO35;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO40;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO53;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO54;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO61;
output [7:0] led_pio_external_connection_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, temp = 0; char x[5][5]; for (i = 0; i < 3; i++) gets(x[i]); for (i = 0; i < 3; i++) for (j = 0; j < 3; j++) if (x[i][j] != x[2 - i][2 - j]) temp = 1; if (temp == 1) printf( NO n ); else printf( YES n ); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
//
// Create Date: 13:26:15 10/03/2016
// Module Name: MUX_tb
// Project Name: MIPS
// Description: Testing MIPS 2-to-1 MUX implementation in verilog.
//
// Dependencies: MUX.v
//
////////////////////////////////////////////////////////////////////////////////
module MUX_tb;
// Declare inputs.
reg [31:0] A, B;
reg sel;
// Declare outputs.
wire [31:0] Y;
// Instantiate the MUX module.
MUX mux(.a(A), .b(B), .sel(sel), .y(Y));
initial begin
// Initialize inputs.
A = 0;
B = 0;
sel = 0;
// Provide test values.
A = 32'hAAAAAAAA;
B = 32'h55555555;
sel = 1'b1;
#10;
A = 32'h00000000;
#10;
sel = 1'b1;
#10;
B = 32'hFFFFFFFF;
#5;
A = 32'hA5A5A5A5;
#5;
sel = 1'b0;
B = 32'hDDDDDDDD;
#5;
sel = 1'bx;
// Terminate.
$finish;
end
// Whenever a change occurs to A, B or sel, display information.
always @ (A or B or sel)
#1 $display("At t = %0d sel %b A = %h B = %h Y = %h",
$time, sel, A, B, Y);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_SYMBOL_V
`define SKY130_FD_SC_HD__MUX2I_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__mux2i (
//# {{data|Data Signals}}
input A0,
input A1,
output Y ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; bool vis[100010]; vector<int> dp[5][100010]; int k, l; int a[6][6]; int dfs(int now) { int i, j, x = 0, sum = 0; for (i = 0; i < now; i++) x = x * 10 + a[now][i]; if (i == l - 1) return dp[1][x].size(); for (i = 0; i < dp[l - now][x].size(); i++) { int tem = dp[l - now][x][i]; for (j = l - 1; j >= now; j--) { a[j][now] = a[now][j] = tem % 10; tem /= 10; } sum += dfs(now + 1); } return sum; } int main() { int i, j, n; int m = sqrt(100000.5); for (i = 2; i <= m; i++) if (!vis[i]) { for (j = i * i; j <= 100000; j += i) vis[j] = 1; } for (i = 2; i < 100000; i++) if (!vis[i]) { int tem = i; tem /= 10; for (j = 1; j <= 4; j++) { dp[j][tem].push_back(i); tem /= 10; } } scanf( %d , &n); char str[7]; for (j = 1; j <= n; j++) { scanf( %s , str); l = strlen(str); for (i = 0; str[i] != 0 ; i++) { a[0][i] = a[i][0] = str[i] - 0 ; } printf( %d n , dfs(1)); } }
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module alu_slice_msb(a, b, c, less, sel, ovrflw, out, set);
input a, b, c, less;
input [2:0] sel;
output out, ovrflw, set;
wire overflow;
wire sum, ANDresult,less, ORresult, b_inv;
reg out;
assign b_inv = sel[2] ^ b;
assign ANDresult = a & b;
assign ORresult = a | b;
assign ovrflw = overflow ^ c;
fulladder f1(a, b_inv, c, sum, overflow);
assign set = sum;
always @(a or b or c or less or sel)
begin
case(sel[1:0])
2'b00: out = ANDresult;
2'b01: out = ORresult;
2'b10: out = sum;
2'b11: out = less;
endcase
end
endmodule
|
/*
-- ============================================================================
-- FILE NAME : bus_master_mux.v
-- DESCRIPTION : oX}X^}`vNT
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "bus.h"
/********** W
[ **********/
module bus_master_mux (
/********** oX}X^M **********/
// oX}X^0Ô
input wire [`WordAddrBus] m0_addr, // AhX
input wire m0_as_, // AhXXg[u
input wire m0_rw, // ÇÝ^«
input wire [`WordDataBus] m0_wr_data, // «Ýf[^
input wire m0_grnt_, // oXOg
// oX}X^1Ô
input wire [`WordAddrBus] m1_addr, // AhX
input wire m1_as_, // AhXXg[u
input wire m1_rw, // ÇÝ^«
input wire [`WordDataBus] m1_wr_data, // «Ýf[^
input wire m1_grnt_, // oXOg
// oX}X^2Ô
input wire [`WordAddrBus] m2_addr, // AhX
input wire m2_as_, // AhXXg[u
input wire m2_rw, // ÇÝ^«
input wire [`WordDataBus] m2_wr_data, // «Ýf[^
input wire m2_grnt_, // oXOg
// oX}X^3Ô
input wire [`WordAddrBus] m3_addr, // AhX
input wire m3_as_, // AhXXg[u
input wire m3_rw, // ÇÝ^«
input wire [`WordDataBus] m3_wr_data, // «Ýf[^
input wire m3_grnt_, // oXOg
/********** oXX[u¤ÊM **********/
output reg [`WordAddrBus] s_addr, // AhX
output reg s_as_, // AhXXg[u
output reg s_rw, // ÇÝ^«
output reg [`WordDataBus] s_wr_data // «Ýf[^
);
/********** oX}X^}`vNT **********/
always @(*) begin
/* oX ðÁÄ¢é}X^ÌIð */
if (m0_grnt_ == `ENABLE_) begin // oX}X^0Ô
s_addr = m0_addr;
s_as_ = m0_as_;
s_rw = m0_rw;
s_wr_data = m0_wr_data;
end else if (m1_grnt_ == `ENABLE_) begin // oX}X^0Ô
s_addr = m1_addr;
s_as_ = m1_as_;
s_rw = m1_rw;
s_wr_data = m1_wr_data;
end else if (m2_grnt_ == `ENABLE_) begin // oX}X^0Ô
s_addr = m2_addr;
s_as_ = m2_as_;
s_rw = m2_rw;
s_wr_data = m2_wr_data;
end else if (m3_grnt_ == `ENABLE_) begin // oX}X^0Ô
s_addr = m3_addr;
s_as_ = m3_as_;
s_rw = m3_rw;
s_wr_data = m3_wr_data;
end else begin // ftHgl
s_addr = `WORD_ADDR_W'h0;
s_as_ = `DISABLE_;
s_rw = `READ;
s_wr_data = `WORD_DATA_W'h0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_SYMBOL_V
`define SKY130_FD_SC_HDLL__O221AI_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o221ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int maxi = -1000000050; int f, t; int loli = -1000000050; for (int i = 0; i < n; i++) { cin >> f >> t; if (t > k) { loli = f - (t - k); } else loli = f; if (loli > maxi) maxi = loli; } cout << maxi << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int n, m, k, s = 0, sx, sy, num; char grid[600][600]; bool vis[600][600]; long long int dx[4] = {0, 0, -1, 1}; long long int dy[4] = {-1, 1, 0, 0}; bool check(long long int x, long long int y) { if (x >= 0 && x < n && y >= 0 && y < m && grid[x][y] == . && !vis[x][y]) return 1; return 0; } void dfs(long long int x, long long int y) { vis[x][y] = 1; grid[x][y] = M ; if (num >= s - k) return; for (long long int i = 0; i < 4; i++) { long long int nx = x + dx[i]; long long int ny = y + dy[i]; if (num >= s - k) { break; } if (check(nx, ny)) { num++; dfs(nx, ny); } } } int main() { cin >> n >> m >> k; memset(vis, 0, sizeof vis); for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { cin >> grid[i][j]; if (grid[i][j] == . ) { s++; sx = i; sy = j; } } } num = 1; dfs(sx, sy); for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { if (grid[i][j] == . ) grid[i][j] = X ; if (grid[i][j] == M ) grid[i][j] = . ; cout << grid[i][j]; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> const int mod = 1000000007; const int gmod = 3; const int inf = 1039074182; const double eps = 1e-9; const long long llinf = 2LL * inf * inf; template <typename T1, typename T2> inline void chmin(T1 &x, T2 b) { if (b < x) x = b; } template <typename T1, typename T2> inline void chmax(T1 &x, T2 b) { if (b > x) x = b; } inline void chadd(int &x, int b) { x += b - mod; x += (x >> 31 & mod); } template <typename T1, typename T2> inline void chadd(T1 &x, T2 b) { x += b; if (x >= mod) x -= mod; } template <typename T1, typename T2> inline void chmul(T1 &x, T2 b) { x = 1LL * x * b % mod; } template <typename T1, typename T2> inline void chmod(T1 &x, T2 b) { x %= b, x += b; if (x >= b) x -= b; } template <typename T> inline T mabs(T x) { return (x < 0 ? -x : x); } using namespace std; using namespace std; template <typename T> ostream &operator<<(ostream &cout, vector<T> vec) { cout << { ; for (int i = 0; i < (int)vec.size(); i++) { cout << vec[i]; if (i != (int)vec.size() - 1) cout << , ; } cout << } ; return cout; } template <typename T1, typename T2> ostream &operator<<(ostream &cout, pair<T1, T2> p) { cout << ( << p.first << , << p.second << ) ; return cout; } template <typename T, typename T2> ostream &operator<<(ostream &cout, set<T, T2> s) { vector<T> t; for (auto x : s) t.push_back(x); cout << t; return cout; } template <typename T, typename T2> ostream &operator<<(ostream &cout, multiset<T, T2> s) { vector<T> t; for (auto x : s) t.push_back(x); cout << t; return cout; } template <typename T> ostream &operator<<(ostream &cout, queue<T> q) { vector<T> t; while (q.size()) { t.push_back(q.front()); q.pop(); } cout << t; return cout; } template <typename T1, typename T2, typename T3> ostream &operator<<(ostream &cout, map<T1, T2, T3> m) { for (auto &x : m) { cout << Key: << x.first << << Value: << x.second << endl; } return cout; } template <typename T1, typename T2> void operator+=(pair<T1, T2> &x, const pair<T1, T2> y) { x.first += y.first; x.second += y.second; } template <typename T1, typename T2> pair<T1, T2> operator+(const pair<T1, T2> &x, const pair<T1, T2> &y) { return make_pair(x.first + y.first, x.second + y.second); } template <typename T1, typename T2> pair<T1, T2> operator-(const pair<T1, T2> &x, const pair<T1, T2> &y) { return make_pair(x.first - y.first, x.second - y.second); } template <typename T1, typename T2> pair<T1, T2> operator-(pair<T1, T2> x) { return make_pair(-x.first, -x.second); } template <typename T> vector<vector<T>> operator~(vector<vector<T>> vec) { vector<vector<T>> v; int n = vec.size(), m = vec[0].size(); v.resize(m); for (int i = 0; i < m; i++) { v[i].resize(n); } for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { v[i][j] = vec[j][i]; } } return v; } void print0x(int x) { std::vector<int> vec; while (x) { vec.push_back(x & 1); x >>= 1; } std::reverse(vec.begin(), vec.end()); for (int i = 0; i < (int)vec.size(); i++) { std::cout << vec[i]; } std::cout << ; } template <typename T> void print0x(T x, int len) { std::vector<int> vec; while (x) { vec.push_back(x & 1); x >>= 1; } reverse(vec.begin(), vec.end()); for (int i = (int)vec.size(); i < len; i++) { putchar( 0 ); } for (size_t i = 0; i < vec.size(); i++) { std::cout << vec[i]; } std::cout << ; } vector<string> vec_splitter(string s) { s += , ; vector<string> res; while (!s.empty()) { res.push_back(s.substr(0, s.find( , ))); s = s.substr(s.find( , ) + 1); } return res; } void debug_out(vector<string> __attribute__((unused)) args, __attribute__((unused)) int idx, __attribute__((unused)) int LINE_NUM) { cerr << endl; } template <typename Head, typename... Tail> void debug_out(vector<string> args, int idx, int LINE_NUM, Head H, Tail... T) { if (idx > 0) cerr << , ; else cerr << Line( << LINE_NUM << ) ; stringstream ss; ss << H; cerr << args[idx] << = << ss.str(); debug_out(args, idx + 1, LINE_NUM, T...); } struct DSUAE { int *f; inline void clear(int n) { for (int i = 0; i < n; i++) { f[i] = i; } } inline void init(int n) { f = new int[n + 5]; clear(n); } inline int find(int x) { return (f[x] == x ? x : f[x] = find(f[x])); } inline void merge(int x, int y) { x = find(x); y = find(y); if (x == y) return; if (x & 1) f[x] = y; else f[y] = x; } }; struct DSU { int *f; int *depth; int *sz; inline void clear(int n) { for (int i = 0; i < n; i++) { f[i] = i; depth[i] = 1; sz[i] = 1; } } inline void init(int n) { f = new int[n + 5]; depth = new int[n + 5]; sz = new int[n + 5]; clear(n); } inline int find(int x) { return (f[x] == x ? x : f[x] = find(f[x])); } inline int getSize(int x) { return sz[find(x)]; } inline int merge(int x, int y) { x = find(x); y = find(y); if (x == y) return false; if (depth[x] > depth[y]) { f[y] = x; sz[x] += sz[y]; } else if (depth[y] > depth[x]) { f[x] = y; sz[y] += sz[x]; } else { sz[y] += sz[x]; f[x] = y; depth[y]++; } return true; } inline int same(int x, int y) { return (find(x) == find(y)); } ~DSU() { delete f; delete depth; delete sz; } }; struct PersistentDSU : public DSU { int find(int x) { return (x == f[x] ? x : find(f[x])); } inline int merge(int x, int y) { x = find(x); y = find(y); if (x == y) return false; if (depth[x] > depth[y]) { f[y] = x; sz[x] += sz[y]; } else if (depth[y] > depth[x]) { f[x] = y; sz[y] += sz[x]; } else { sz[y] += sz[x]; f[x] = y; depth[y]++; } return true; } }; using namespace std; int n; char c[55][55]; DSUAE dsu; vector<int> scc[55]; vector<vector<int>> a; int b[55][55]; int p[55]; int main() { double t = clock(); scanf( %d , &n); dsu.init(n); for (int i = 0; i < n; i++) scanf( %s , c[i]); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (c[i][j] == A ) dsu.merge(i, j); } } for (int i = 0; i < n; i++) scc[dsu.find(i)].push_back(i); int now = 0; for (int i = 0; i < n; i++) { if (scc[i].empty()) continue; for (auto x : scc[i]) { for (auto y : scc[i]) { if (c[x][y] == X ) { cout << -1 << endl; exit(0); }; } } if (scc[i].size() > 1) now += scc[i].size(); else now += 1; if (scc[i].size() > 1) a.push_back(scc[i]); } n = a.size(); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i == j) continue; bool noXor = true; for (auto x : a[i]) { for (auto y : a[j]) { noXor &= (c[x][y] != X ); } } if (!noXor) b[i][j] = 1; else b[i][j] = 0; } } for (int i = 0; i < n; i++) p[i] = i; int res = inf; while ((clock() - t) / CLOCKS_PER_SEC <= 0.001) { random_shuffle(p, p + n); vector<vector<int>> v; for (int i = 0; i < n; i++) { int x = p[i]; int found = false; for (auto &vv : v) { int ok = true; for (auto &u : vv) { ok &= (b[u][x] == 0); } if (ok) { found = true; vv.push_back(x); break; } } if (!found) { v.push_back(vector<int>{x}); } } chmin(res, v.size()); } cout << res + now - 1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; scanf( %d%d , &a, &b); for (int i = b + 1; i <= a + b + 1; i++) printf( %d , i); for (int i = b; i >= 1; i--) printf( %d , i); return 0; }
|
#include <bits/stdc++.h> using ll = long long; using ull = unsigned long long; using std::cin; using std::cout; void print() {} template <typename T, typename... Args> void print(T t, Args... args) { cout << t << , print(args...); } template <typename... Args> void println(Args... args) { print(args...), cout << n ; } void printF(const char *format) { cout << format; } template <typename T, typename... Args> void printF(const char *format, T t, Args... args) { while (*format != % && *format) cout.put(*format++); if (*format++ == 0 ) return; cout << t; printF(format, args...); } ll getTotalBright(const std::vector<ll> &v, ll time, ll C) { ll ret = 0; for (ll i = 0; i < C + 1; ++i) { ret += v[i] * ((time + i) % (C + 1)); } return ret; } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); int N, Q, C, x1, y1, x2, y2, s; int time; cin >> N >> Q >> C; std::array<std::array<std::vector<ll>, 101>, 101> grid; for (auto &row : grid) for (auto &col : row) col.resize(C + 1, 0); for (int i = 0; i < N; ++i) { cin >> x1 >> y1 >> s; grid[x1][y1][s]++; } for (int i = 1; i < 101; ++i) { for (int h = 0; h <= C; ++h) { grid[i][0][h] += grid[i - 1][0][h]; grid[0][i][h] += grid[0][i - 1][h]; } } for (int i = 1; i < 101; ++i) { for (int j = 1; j < 101; ++j) { for (int h = 0; h <= C; ++h) { grid[i][j][h] += grid[i - 1][j][h] + grid[i][j - 1][h] - grid[i - 1][j - 1][h]; } } } for (int q = 0; q < Q; ++q) { cin >> time >> x1 >> y1 >> x2 >> y2; ll bright = 0; bright += getTotalBright(grid[x2][y2], time, C); bright -= getTotalBright(grid[x1 - 1][y2], time, C); bright -= getTotalBright(grid[x2][y1 - 1], time, C); bright += getTotalBright(grid[x1 - 1][y1 - 1], time, C); println(bright); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32O_BLACKBOX_V
`define SKY130_FD_SC_HD__A32O_BLACKBOX_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int i = 0; char a; char A[] = hello ; while (cin >> a && a != n ) { if (a == A[i]) i++; } if (i == 5) cout << YES << endl; else cout << NO << endl; }
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_cmd.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
// User interface command port.
module mig_7series_v1_8_ui_cmd #
(
parameter TCQ = 100,
parameter ADDR_WIDTH = 33,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter RANKS = 4,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
app_rdy, use_addr, rank, bank, row, col, size, cmd, hi_priority,
rd_accepted, wr_accepted, data_buf_addr,
// Inputs
rst, clk, accept_ns, rd_buf_full, wr_req_16, app_addr, app_cmd,
app_sz, app_hi_pri, app_en, wr_data_buf_addr, rd_data_buf_addr_r
);
input rst;
input clk;
input accept_ns;
input rd_buf_full;
input wr_req_16;
wire app_rdy_ns = accept_ns && ~rd_buf_full && ~wr_req_16;
//synthesis attribute max_fanout of app_rdy_r is 10;
(* keep = "true", max_fanout = 10 *) reg app_rdy_r = 1'b0 /* synthesis syn_maxfan = 10 */;
always @(posedge clk) app_rdy_r <= #TCQ app_rdy_ns;
output wire app_rdy;
assign app_rdy = app_rdy_r;
input [ADDR_WIDTH-1:0] app_addr;
input [2:0] app_cmd;
input app_sz;
input app_hi_pri;
input app_en;
reg [ADDR_WIDTH-1:0] app_addr_r1 = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] app_addr_r2 = {ADDR_WIDTH{1'b0}};
reg [2:0] app_cmd_r1;
reg [2:0] app_cmd_r2;
reg app_sz_r1;
reg app_sz_r2;
reg app_hi_pri_r1;
reg app_hi_pri_r2;
reg app_en_r1;
reg app_en_r2;
wire [ADDR_WIDTH-1:0] app_addr_ns1 = app_rdy_r && app_en ? app_addr : app_addr_r1;
wire [ADDR_WIDTH-1:0] app_addr_ns2 = app_rdy_r ? app_addr_r1 : app_addr_r2;
wire [2:0] app_cmd_ns1 = app_rdy_r ? app_cmd : app_cmd_r1;
wire [2:0] app_cmd_ns2 = app_rdy_r ? app_cmd_r1 : app_cmd_r2;
wire app_sz_ns1 = app_rdy_r ? app_sz : app_sz_r1;
wire app_sz_ns2 = app_rdy_r ? app_sz_r1 : app_sz_r2;
wire app_hi_pri_ns1 = app_rdy_r ? app_hi_pri : app_hi_pri_r1;
wire app_hi_pri_ns2 = app_rdy_r ? app_hi_pri_r1 : app_hi_pri_r2;
wire app_en_ns1 = ~rst && (app_rdy_r ? app_en : app_en_r1);
wire app_en_ns2 = ~rst && (app_rdy_r ? app_en_r1 : app_en_r2);
always @(posedge clk) begin
if (rst) begin
app_addr_r1 <= #TCQ {ADDR_WIDTH{1'b0}};
app_addr_r2 <= #TCQ {ADDR_WIDTH{1'b0}};
end else begin
app_addr_r1 <= #TCQ app_addr_ns1;
app_addr_r2 <= #TCQ app_addr_ns2;
end
app_cmd_r1 <= #TCQ app_cmd_ns1;
app_cmd_r2 <= #TCQ app_cmd_ns2;
app_sz_r1 <= #TCQ app_sz_ns1;
app_sz_r2 <= #TCQ app_sz_ns2;
app_hi_pri_r1 <= #TCQ app_hi_pri_ns1;
app_hi_pri_r2 <= #TCQ app_hi_pri_ns2;
app_en_r1 <= #TCQ app_en_ns1;
app_en_r2 <= #TCQ app_en_ns2;
end // always @ (posedge clk)
wire use_addr_lcl = app_en_r2 && app_rdy_r;
output wire use_addr;
assign use_addr = use_addr_lcl;
output wire [RANK_WIDTH-1:0] rank;
output wire [BANK_WIDTH-1:0] bank;
output wire [ROW_WIDTH-1:0] row;
output wire [COL_WIDTH-1:0] col;
output wire size;
output wire [2:0] cmd;
output wire hi_priority;
assign col = app_rdy_r
? app_addr_r1[0+:COL_WIDTH]
: app_addr_r2[0+:COL_WIDTH];
generate
begin
if (MEM_ADDR_ORDER == "ROW_BANK_COLUMN")
begin
assign row = app_rdy_r
? app_addr_r1[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH]
: app_addr_r2[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH];
assign bank = app_rdy_r
? app_addr_r1[COL_WIDTH+:BANK_WIDTH]
: app_addr_r2[COL_WIDTH+:BANK_WIDTH];
end
else
begin
assign row = app_rdy_r
? app_addr_r1[COL_WIDTH+:ROW_WIDTH]
: app_addr_r2[COL_WIDTH+:ROW_WIDTH];
assign bank = app_rdy_r
? app_addr_r1[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH]
: app_addr_r2[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH];
end
end
endgenerate
assign rank = (RANKS == 1)
? 1'b0
: app_rdy_r
? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
: app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign size = app_rdy_r
? app_sz_r1
: app_sz_r2;
assign cmd = app_rdy_r
? app_cmd_r1
: app_cmd_r2;
assign hi_priority = app_rdy_r
? app_hi_pri_r1
: app_hi_pri_r2;
wire request_accepted = use_addr_lcl && app_rdy_r;
wire rd = app_cmd_r2[1:0] == 2'b01;
wire wr = app_cmd_r2[1:0] == 2'b00;
wire wr_bytes = app_cmd_r2[1:0] == 2'b11;
wire write = wr || wr_bytes;
output wire rd_accepted;
assign rd_accepted = request_accepted && rd;
output wire wr_accepted;
assign wr_accepted = request_accepted && write;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r;
output wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
assign data_buf_addr = ~write ? rd_data_buf_addr_r : wr_data_buf_addr;
endmodule // ui_cmd
// Local Variables:
// verilog-library-directories:(".")
// End:
|
#include <bits/stdc++.h> using namespace std; int n; inline int f(int a) { int n1 = n; bool y = 0; while (n1 != 0) { int h = a; int u = n1 % 10; n1 = n1 / 10; while (h != 0) { int j = h % 10; h = h / 10; if (u == j) { y = 1; break; } } } return y; } int main() { cin >> n; int ans = 0; for (int i = 1; i * i <= n; i++) { if (n % i == 0) { int i2 = n / i; if (f(i) == 1) ans++; if (f(i2) == 1 && i2 != i) ans++; } } cout << ans << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
/*
Copyright 2010, 2011 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
David Fritz
SRAM interface
31.12.2010
*/
//
// Taken from PLP verilog source.
//////////////////////////////////////////////////////////////////////////////////
module sram_interface(rst, clk, addr, dout, rdy, sram_clk, sram_adv, sram_cre, sram_ce, sram_oe, sram_we, sram_lb, sram_ub, sram_data, sram_addr);
input clk, rst;
input [23:0] addr;
//input drw;
//input [31:0] din;
output reg [15:0] dout;
output rdy;
output sram_clk, sram_adv, sram_cre, sram_ce, sram_oe, sram_lb, sram_ub;
output [22:0] sram_addr;
output sram_we;
inout [15:0] sram_data;
/* some sram signals are static */
assign sram_clk = 0;
assign sram_adv = 0;
assign sram_cre = 0;
assign sram_ce = 0;
assign sram_oe = 0; /* sram_we overrides this signal */
assign sram_ub = 0;
assign sram_lb = 0;
reg [2:0] state = 3'b000;
assign sram_data = 16'hzzzz;
assign sram_addr = addr[22:0]; //{addr[23:1],1'b0};
assign sram_we = 1; // never write
assign rdy = (state == 3'b000);
always @(posedge clk) begin
if (!rst) begin
if (state == 3'b010) dout <= sram_data;
//if (state == 3'b100) dout[15:0] <= sram_data;
if (state == 3'b010)
state <= 3'b000;
else
state <= state + 1;
end else begin
state <= 3'b000;
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fmcomms7_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio,
spi_dir);
// 4 wire
input [ 2:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
output spi_dir;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_dir = ~spi_enable_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// The IEEE standard allows the out-of-bounds part-selects to be flagged as
// compile-time errors. If they are not, this test should pass.
module top;
reg [3:0][3:0] array;
reg failed = 0;
initial begin
array = 16'h4321;
$display("%h", array[-2+:2]); if (array[-2+:2] !== 8'hxx) failed = 1;
$display("%h", array[-1+:2]); if (array[-1+:2] !== 8'h1x) failed = 1;
$display("%h", array[ 0+:2]); if (array[ 0+:2] !== 8'h21) failed = 1;
$display("%h", array[ 1+:2]); if (array[ 1+:2] !== 8'h32) failed = 1;
$display("%h", array[ 2+:2]); if (array[ 2+:2] !== 8'h43) failed = 1;
$display("%h", array[ 3+:2]); if (array[ 3+:2] !== 8'hx4) failed = 1;
$display("%h", array[ 4+:2]); if (array[ 4+:2] !== 8'hxx) failed = 1;
$display("%h", array[-1-:2]); if (array[-1-:2] !== 8'hxx) failed = 1;
$display("%h", array[ 0-:2]); if (array[ 0-:2] !== 8'h1x) failed = 1;
$display("%h", array[ 1-:2]); if (array[ 1-:2] !== 8'h21) failed = 1;
$display("%h", array[ 2-:2]); if (array[ 2-:2] !== 8'h32) failed = 1;
$display("%h", array[ 3-:2]); if (array[ 3-:2] !== 8'h43) failed = 1;
$display("%h", array[ 4-:2]); if (array[ 4-:2] !== 8'hx4) failed = 1;
$display("%h", array[ 5-:2]); if (array[ 5-:2] !== 8'hxx) failed = 1;
$display("%h", array[-1:-2]); if (array[-1:-2] !== 8'hxx) failed = 1;
$display("%h", array[ 0:-1]); if (array[ 0:-1] !== 8'h1x) failed = 1;
$display("%h", array[ 1:0 ]); if (array[ 1:0 ] !== 8'h21) failed = 1;
$display("%h", array[ 2:1 ]); if (array[ 2:1 ] !== 8'h32) failed = 1;
$display("%h", array[ 3:2 ]); if (array[ 3:2 ] !== 8'h43) failed = 1;
$display("%h", array[ 4:3 ]); if (array[ 4:3 ] !== 8'hx4) failed = 1;
$display("%h", array[ 5:4 ]); if (array[ 5:4 ] !== 8'hxx) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int *b = new int[n]; int max_val = 0; for (int i = 0; i < n; i++) { cin >> b[i]; if (i == 0) { } else if (i == 1) { b[i] = b[0] + b[1]; max_val = (b[0] > b[1]) ? b[0] : b[1]; } else { b[i] = max_val + b[i]; if (max_val < b[i]) max_val = b[i]; } cout << b[i] << ; } cout << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DECAP_BEHAVIORAL_PP_V
|
/*
File: parallella_gpio_emio.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013-2014 Adapteva, Inc.
Contributed by Fred Huettig
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
// Implements GPIO pins from the PS/EMIO
// Works with 7010 (24 pins) or 7020 (48 pins) and
// either single-ended or differential IO
module parallella_gpio_emio
(/*AUTOARG*/
// Outputs
PS_GPIO_I,
// Inouts
GPIO_P, GPIO_N,
// Inputs
PS_GPIO_O, PS_GPIO_T
);
parameter NUM_GPIO_PAIRS = 24; // 12 or 24
parameter DIFF_GPIO = 0; // 0 or 1
parameter NUM_PS_SIGS = 64;
inout [NUM_GPIO_PAIRS-1:0] GPIO_P;
inout [NUM_GPIO_PAIRS-1:0] GPIO_N;
output [NUM_PS_SIGS-1:0] PS_GPIO_I;
input [NUM_PS_SIGS-1:0] PS_GPIO_O;
input [NUM_PS_SIGS-1:0] PS_GPIO_T;
genvar m;
generate
if( DIFF_GPIO == 1 ) begin: GPIO_DIFF
IOBUFDS
#(
.DIFF_TERM("TRUE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("LVDS_25"),
.SLEW("FAST")
)
GPIOBUF_DS [NUM_GPIO_PAIRS-1:0]
(
.O(PS_GPIO_I), // Buffer output
.IO(GPIO_P), // Diff_p inout (connect directly to top-level port)
.IOB(GPIO_N), // Diff_n inout (connect directly to top-level port)
.I(PS_GPIO_O), // Buffer input
.T(PS_GPIO_T) // 3-state enable input, high=input, low=output
);
end else begin: GPIO_SE // single-ended
wire [NUM_GPIO_PAIRS-1:0] gpio_i_n, gpio_i_p;
wire [NUM_GPIO_PAIRS-1:0] gpio_o_n, gpio_o_p;
wire [NUM_GPIO_PAIRS-1:0] gpio_t_n, gpio_t_p;
// Map P/N pins to single-ended signals
for(m=0; m<NUM_GPIO_PAIRS; m=m+2) begin : assign_se_sigs
assign PS_GPIO_I[2*m] = gpio_i_n[m];
assign PS_GPIO_I[2*m+1] = gpio_i_n[m+1];
assign PS_GPIO_I[2*m+2] = gpio_i_p[m];
assign PS_GPIO_I[2*m+3] = gpio_i_p[m+1];
assign gpio_o_n[m] = PS_GPIO_O[2*m];
assign gpio_o_n[m+1] = PS_GPIO_O[2*m+1];
assign gpio_o_p[m] = PS_GPIO_O[2*m+2];
assign gpio_o_p[m+1] = PS_GPIO_O[2*m+3];
assign gpio_t_n[m] = PS_GPIO_T[2*m];
assign gpio_t_n[m+1] = PS_GPIO_T[2*m+1];
assign gpio_t_p[m] = PS_GPIO_T[2*m+2];
assign gpio_t_p[m+1] = PS_GPIO_T[2*m+3];
end // block: assign_se_sigs
IOBUF
#(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("LVCMOS25"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
GPIOBUF_SE_N [NUM_GPIO_PAIRS-1:0]
(
.O(gpio_i_n), // Buffer output
.IO(GPIO_N), // Buffer inout port (connect directly to top-level port)
.I(gpio_o_n), // Buffer input
.T(gpio_t_n) // 3-state enable input, high=input, low=output
);
IOBUF
#(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("LVCMOS25"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
GPIOBUF_SE_P [NUM_GPIO_PAIRS-1:0]
(
.O(gpio_i_p), // Buffer output
.IO(GPIO_P), // Buffer inout port (connect directly to top-level port)
.I(gpio_o_p), // Buffer input
.T(gpio_t_p) // 3-state enable input, high=input, low=output
);
end // block: GPIO_SE
endgenerate
// Tie unused PS signals back to themselves
genvar n;
generate for(n=NUM_GPIO_PAIRS*2; n<48; n=n+1) begin : unused_ps_sigs
assign PS_GPIO_I[n]
= PS_GPIO_O[n] &
~PS_GPIO_T[n];
end
endgenerate
endmodule // parallella_gpio_emio
|
#include <bits/stdc++.h> #pragma GCC optimize( -O3 ) using namespace std; const long long mod = 998244353; struct edge { int u, v, cap; edge() {} edge(int _u, int _v, int _cap) : u(_u), v(_v), cap(_cap) {} int get(int t) { return t ^ u ^ v; } }; const int inf = 1e9; struct edkarp { vector<edge> edges; vector<vector<int>> adj; int n; void init(int _n) { n = _n; adj.assign(n, vector<int>(0)); } inline int comp(int i) { return i ^ 1; } inline int par(int i, int ed) { return edges[ed].get(i); } void add(int u, int v, int c) { adj[u].emplace_back(edges.size()); edges.emplace_back(u, v, c); adj[v].emplace_back(edges.size()); edges.emplace_back(u, v, 0); } int bfs(int st, int tar, vector<int> &p) { p.assign(n, -1); p[st] = -2; queue<pair<int, int>> q; q.push(make_pair(st, inf)); while (!q.empty()) { int i = q.front().first, flow = q.front().second; q.pop(); for (auto &x : adj[i]) { if (p[par(i, x)] == -1 && edges[x].cap) { p[par(i, x)] = x; int nf = min(flow, edges[x].cap); if (par(i, x) == tar) { return nf; } q.push(make_pair(par(i, x), nf)); } } } return 0; } int maxflow(int st, int tar) { vector<int> p(n); int flow = 0; int nf; while (nf = bfs(st, tar, p)) { flow += nf; int cr = tar; while (cr != st) { edges[p[cr]].cap -= nf; edges[comp(p[cr])].cap += nf; cr = par(cr, p[cr]); } } return flow; } }; struct edgeg { int u, v, c, lo; bool in_loop = false; edgeg() {} edgeg(int _u, int _v, int _c) : u(_u), v(_v), c(_c), lo(-1) {} int get(int t) { return t ^ u ^ v; } }; const int N = 1e4 + 5; int n, m, u, v, c, vis[N], p[N], vis1[N]; vector<int> adj[N]; vector<bool> avai; vector<vector<int>> loops; vector<edgeg> edges; edkarp fo; inline int geta(int x, int edge_num) { return edges[edge_num].get(x); } void dfs(int i, int par) { vis[i] = 1; vis1[i] = 1; for (int x : adj[i]) { int u = geta(i, x); if (u == par) continue; if (vis[u]) { if (!vis1[u]) continue; edges[x].in_loop = true; vector<int> clrs; clrs.push_back(edges[x].c); u = i; while (u != geta(i, x)) { edges[p[u]].in_loop = true; clrs.push_back(edges[p[u]].c); u = geta(u, p[u]); } sort(clrs.begin(), clrs.end()); auto it = unique(clrs.begin(), clrs.end()); if (it != clrs.end()) { for (auto it1 = clrs.begin(); it1 != it; it1++) { avai[*it1] = 1; } } else { loops.push_back(clrs); } } else { p[u] = x; dfs(u, i); } } vis1[i] = 0; } void solve() { cin >> n >> m; avai.assign(m, 0); for (int i = 0; i < m; i++) { cin >> u >> v >> c; u--, v--, c--; adj[u].push_back(edges.size()); adj[v].push_back(edges.size()); edges.emplace_back(u, v, c); } fill(vis, vis + n, 0); fill(vis1, vis1 + n, 0); dfs(0, -1); int cr = 0; for (int i = 0; i < (int)edges.size(); i++) { if (!edges[i].in_loop) { avai[edges[i].c] = 1; } } fo.init((int)loops.size() + m + 2); for (int i = 0; i < (int)loops.size(); i++) { fo.add(0, i + 1, (int)loops[i].size() - 1); for (int c : loops[i]) { if (avai[c]) continue; fo.add(i + 1, (int)loops.size() + 1 + c, 1); } } int flow = 0; for (int i = 0; i < m; i++) { flow += avai[i]; } for (int i = (int)loops.size() + 1; i <= (int)loops.size() + m; i++) { fo.add(i, (int)loops.size() + m + 1, 1); } flow += fo.maxflow(0, (int)loops.size() + m + 1); cout << flow << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; while (t--) { solve(); } }
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// file: ibert_7series_gtx_0.v
//////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 2012.3
// \ \ Application : IBERT 7Series
// / / Filename : example_ibert_7series_gtx_0
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Module example_ibert_7series_gtx_0
// Generated by Xilinx IBERT_7S
//////////////////////////////////////////////////////////////////////////////
`define C_NUM_QUADS 1
`define C_REFCLKS_USED 1
module onetswitch_top
(
// GT top level ports
output [(4*`C_NUM_QUADS)-1:0] TXN_O,
output [(4*`C_NUM_QUADS)-1:0] TXP_O,
input [(4*`C_NUM_QUADS)-1:0] RXN_I,
input [(4*`C_NUM_QUADS)-1:0] RXP_I,
input [`C_REFCLKS_USED-1:0] GTREFCLK0P_I,
input [`C_REFCLKS_USED-1:0] GTREFCLK0N_I,
input [`C_REFCLKS_USED-1:0] GTREFCLK1P_I,
input [`C_REFCLKS_USED-1:0] GTREFCLK1N_I
);
//
// Ibert refclk internal signals
//
wire [`C_NUM_QUADS-1:0] gtrefclk0_i;
wire [`C_NUM_QUADS-1:0] gtrefclk1_i;
wire [`C_REFCLKS_USED-1:0] refclk0_i;
wire [`C_REFCLKS_USED-1:0] refclk1_i;
//
// Refclk IBUFDS instantiations
//
IBUFDS_GTE2 u_buf_q2_clk0
(
.O (refclk0_i[0]),
.ODIV2 (),
.CEB (1'b0),
.I (GTREFCLK0P_I[0]),
.IB (GTREFCLK0N_I[0])
);
IBUFDS_GTE2 u_buf_q2_clk1
(
.O (refclk1_i[0]),
.ODIV2 (),
.CEB (1'b0),
.I (GTREFCLK1P_I[0]),
.IB (GTREFCLK1N_I[0])
);
//
// Refclk connection from each IBUFDS to respective quads depending on the source selected in gui
//
assign gtrefclk0_i[0] = refclk0_i[0];
assign gtrefclk1_i[0] = refclk1_i[0];
//
// IBERT core instantiation
//
ibert_7series_gtx_0 u_ibert_core
(
.TXN_O(TXN_O),
.TXP_O(TXP_O),
.RXN_I(RXN_I),
.RXP_I(RXP_I),
.GTREFCLK0_I(gtrefclk0_i),
.GTREFCLK1_I(gtrefclk1_i)
);
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = (2e5 + 5); const int mod = 1e9 + 7; long long int n, a[N], x; vector<vector<int>> g; long long int pow_mod_m(long long int a, long long int n) { if (!n) return 1; long long int pt = pow_mod_m(a, n / 2); pt *= pt; pt %= mod; if (n & 1) pt *= a, pt %= mod; return pt; } struct LCA { vector<int> height, euler, first, segtree; vector<bool> visited; int n; LCA(vector<vector<int>> &adj, int root = 0) { n = adj.size(); height.resize(n); first.resize(n); euler.reserve(2 * n); visited.assign(n, false); dfs(adj, root); int m = euler.size(); segtree.resize(4 * m); build(1, 0, m - 1); } void dfs(vector<vector<int>> &adj, int node, int h = 0) { visited[node] = 1; height[node] = h; first[node] = euler.size(); euler.push_back(node); for (auto to : adj[node]) { if (!visited[to]) { dfs(adj, to, h + 1); euler.push_back(node); } } } void build(int node, int b, int e) { if (b == e) segtree[node] = euler[b]; else { int m = (b + e) >> 1; build(node << 1, b, m); build(node << 1 | 1, m + 1, e); int l = segtree[node << 1], r = segtree[node << 1 | 1]; segtree[node] = (height[l] < height[r]) ? l : r; } } int query(int node, int b, int e, int L, int R) { if (b > R || e < L) return -1; if (b >= L and e <= R) return segtree[node]; int mid = (b + e) >> 1; int left = query(node << 1, b, mid, L, R); int right = query(node << 1 | 1, mid + 1, e, L, R); if (left == -1) return right; if (right == -1) return left; return (height[left] < height[right]) ? left : right; } int lca(int u, int v) { int left = first[u], right = first[v]; if (left > right) swap(left, right); return query(1, 0, euler.size() - 1, left, right); } int dist(int u, int v) { int lca_u_v = lca(u, v); return height[u] + height[v] - 2 * height[lca_u_v]; } }; long long int ceil(long long int m) { return x % m == 0 ? x / m : x / m + 1; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int ts = 1; cin >> ts; while (ts--) { cin >> n >> x; bool flag = 0; for (long long int i = 0; i < n; ++i) { cin >> a[i]; if (x == a[i]) flag = 1; } if (flag) cout << 1 << n ; else cout << max(2ll, ceil(*max_element(a, a + n))) << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A211O_FUNCTIONAL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a211o (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { vector<string> a; vector<string> z; string s; while (cin >> s) { a.push_back(s); } int ans = 0; sort(a.begin(), a.end()); for (int r = 0; r < 720; r++) { if (a[0].length() + a[5].length() == a[3].length() + 1 && a[1].length() + a[4].length() == a[2].length() + 1 && a[2][a[1].length() - 1] == a[3][a[0].length() - 1]) { if (a[0][0] == a[1][0] && a[5][a[5].length() - 1] == a[4][a[4].length() - 1] && a[3][0] == a[1][a[1].length() - 1] && a[2][0] == a[0][a[0].length() - 1] && a[2][a[2].length() - 1] == a[5][0] && a[3][a[3].length() - 1] == a[4][0]) { string t = ; t = t + a[0]; for (int i = 0; i < a[3].length() - a[0].length(); i++) { t = t + . ; } t = t + n ; for (int i = 1; i < a[1].length() - 1; i++) { t = t + a[1][i]; for (int j = 0; j < a[0].length() - 2; j++) { t = t + . ; } t = t + a[2][i]; for (int j = 0; j < a[3].length() - a[0].length(); j++) { t = t + . ; } t = t + n ; } t = t + a[3]; t = t + n ; for (int i = 0; i < a[2].length() - a[1].length() - 1; i++) { for (int j = 0; j < a[3].length() - a[5].length(); j++) { t = t + . ; } t = t + a[2][a[1].length() + i]; for (int j = 0; j < a[5].length() - 2; j++) { t = t + . ; } t = t + a[4][i + 1]; t = t + n ; } for (int j = 0; j < a[3].length() - a[5].length(); j++) { t = t + . ; } t = t + a[5] + n ; ans = 1; z.push_back(t); } } next_permutation(a.begin(), a.end()); } if (ans == 0) cout << Impossible << endl; else { sort(z.begin(), z.end()); cout << z[0] << endl; } return 0; }
|
#include <bits/stdc++.h> int main() { long n; scanf( %ld n , &n); std::vector<long> blocks(n + 2); for (long p = 1; p <= n; p++) { scanf( %ld , &blocks[p]); } for (long p = 1; p <= n; p++) { blocks[p] = std::min(blocks[p], 1 + blocks[p - 1]); } for (long p = n; p >= 0; p--) { blocks[p] = std::min(blocks[p], 1 + blocks[p + 1]); } long final(0); for (long p = 1; p <= n; p++) { final = std::max(final, blocks[p]); } printf( %ld n , final); return 0; }
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#include <bits/stdc++.h> using namespace std; int a[10]; int main() { int ans = 0; for (int i = 0; i < 6; i++) scanf( %d , &a[i]); if (a[2] == a[4]) { swap(a[0], a[3]); swap(a[1], a[2]); swap(a[4], a[5]); } for (int i = a[0] + a[0] - 1 + 2, j = 0; j < max(a[1], a[5]); i += 2, j++) { if (j == min(a[1], a[5])) i--; else if (j > min(a[1], a[5])) i -= 2; ans += i; } for (int i = a[3] + a[3] - 1 + 2, j = 0; j < min(a[2], a[4]); i += 2, j++) { ans += i; } printf( %d n , ans); return 0; }
|
`timescale 1ns / 1ps
/*
* File : Processor.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers ()
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 23-Jul-2011 GEA Initial design.
* 2.0 26-May-2012 GEA Release version with CP0.
* 2.01 1-Nov-2012 GEA Fixed issue with Jal.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The top-level MIPS32 Processor. This file is mostly the instantiation
* and wiring of the building blocks of the processor according to the
* hardware design diagram. It contains very little logic itself.
*/
module ITMR_Processor(
input clock,
input reset,
input [4:0] Interrupts, // 5 general-purpose hardware interrupts
input NMI, // Non-maskable interrupt
// Data Memory Interface
input [31:0] DataMem_In,
input DataMem_Ready,
output DataMem_Read,
output [3:0] DataMem_Write, // 4-bit Write, one for each byte in word.
output [29:0] DataMem_Address, // Addresses are words, not bytes.
output [31:0] DataMem_Out,
// Instruction Memory Interface
input [31:0] InstMem_In,
output [29:0] InstMem_Address, // Addresses are words, not bytes.
input InstMem_Ready,
output InstMem_Read
);
genvar i;
parameter N = 3;
/*** Voting Signals ***/
wire Vote_DataMem_Read[N-1:0];
wire [3:0] Vote_DataMem_Write[N-1:0];
wire [29:0] Vote_DataMem_Address[N-1:0];
wire [31:0] Vote_DataMem_Out[N-1:0];
wire [29:0] Vote_InstMem_Address[N-1:0];
wire Vote_InstMem_Read[N-1:0];
(* DONT_TOUCH = "TRUE" *)wire [1853:0] Vote_in [N-1:0];
(* DONT_TOUCH = "TRUE" *)wire [1853:0] Vote_out [N-1:0];
/*** MIPS Processors ***/
generate
for (i = 0; i < N; i = i + 1) begin : Processors
(* DONT_TOUCH = "TRUE" *)Processor MIPS32 (
.clock (clock),
.reset (reset),
.Interrupts (Interrupts),
.NMI (NMI),
.DataMem_In (DataMem_In),
.DataMem_Ready (DataMem_Ready),
.DataMem_Read (Vote_DataMem_Read[i]),
.DataMem_Write (Vote_DataMem_Write[i]),
.DataMem_Address (Vote_DataMem_Address[i]),
.DataMem_Out (Vote_DataMem_Out[i]),
.InstMem_In (InstMem_In),
.InstMem_Address (Vote_InstMem_Address[i]),
.InstMem_Ready (InstMem_Ready),
.InstMem_Read (Vote_InstMem_Read[i]),
.Vote_in (Vote_in[i]),
.Vote_out (Vote_out[i]));
/*** Processor Internal Voters ***/
(* DONT_TOUCH = "TRUE" *)Processor_Voter Processor_Voter (
.Vote_0_in (Vote_out[0]),
.Vote_1_in (Vote_out[1]),
.Vote_2_in (Vote_out[2]),
.Vote_out (Vote_in[i]));
end
endgenerate
/*** Output Voter ***/
Output_Voter Output_Voter (
.Vote_Pipe_A_DataMem_Read (Vote_DataMem_Read[N-1]),
.Vote_Pipe_A_DataMem_Write (Vote_DataMem_Write[N-1]),
.Vote_Pipe_A_DataMem_Address (Vote_DataMem_Address[N-1]),
.Vote_Pipe_A_DataMem_Out (Vote_DataMem_Out[N-1]),
.Vote_Pipe_A_InstMem_Address (Vote_InstMem_Address[N-1]),
.Vote_Pipe_A_InstMem_Read (Vote_InstMem_Read[N-1]),
.Vote_Pipe_B_DataMem_Read (Vote_DataMem_Read[N-2]),
.Vote_Pipe_B_DataMem_Write (Vote_DataMem_Write[N-2]),
.Vote_Pipe_B_DataMem_Address (Vote_DataMem_Address[N-2]),
.Vote_Pipe_B_DataMem_Out (Vote_DataMem_Out[N-2]),
.Vote_Pipe_B_InstMem_Address (Vote_InstMem_Address[N-2]),
.Vote_Pipe_B_InstMem_Read (Vote_InstMem_Read[N-2]),
.Vote_Pipe_C_DataMem_Read (Vote_DataMem_Read[N-3]),
.Vote_Pipe_C_DataMem_Write (Vote_DataMem_Write[N-3]),
.Vote_Pipe_C_DataMem_Address (Vote_DataMem_Address[N-3]),
.Vote_Pipe_C_DataMem_Out (Vote_DataMem_Out[N-3]),
.Vote_Pipe_C_InstMem_Address (Vote_InstMem_Address[N-3]),
.Vote_Pipe_C_InstMem_Read (Vote_InstMem_Read[N-3]),
.DataMem_Read (DataMem_Read),
.DataMem_Write (DataMem_Write),
.DataMem_Address (DataMem_Address),
.DataMem_Out (DataMem_Out),
.InstMem_Address (InstMem_Address),
.InstMem_Read (InstMem_Read));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i; int a, b; int draw = 0, awin = 0, bwin = 0; cin >> a >> b; for (i = 1; i < 7; i++) { if (abs(i - a) == abs(i - b)) draw++; else if (abs(i - a) > abs(i - b)) bwin++; else awin++; } cout << awin << << draw << << bwin << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int m; struct Edge { int x; int y; int t; Edge(int x, int y, int t) : x(x), y(y), t(t) {} void print() { cout << x << << y << << t << endl; } }; vector<Edge> edges; vector<int> edge_idx[200005]; int in_digree[200005]; queue<int> Q; int order[200005]; int main() { int i, j, k; int x, y, z; int t; cin >> t; while (0 < t--) { edges.clear(); while (!Q.empty()) Q.pop(); for (i = 0; i < n; i++) edge_idx[i].clear(); memset(in_digree, 0, sizeof(in_digree)); cin >> n >> m; for (i = 0; i < m; i++) { cin >> z >> x >> y; x--; y--; Edge e(x, y, z); if (e.x != x || e.y != y || e.t != z) return -1; edge_idx[x].push_back(edges.size()); edge_idx[y].push_back(edges.size()); edges.push_back(e); if (z) { in_digree[y] += 1; } } for (i = 0; i < n; i++) { if (in_digree[i] == 0) { Q.push(i); } } int cnt = 0; k = 0; while (!Q.empty()) { x = Q.front(); Q.pop(); order[x] = k++; cnt++; for (i = 0; i < edge_idx[x].size(); i++) { Edge e = edges[edge_idx[x][i]]; z = -1; if (e.t == 1 && e.x == x) { y = e.y; if (--in_digree[y] == 0) Q.push(y); } } } if (cnt != n) { cout << NO n ; } else { cout << YES n ; for (i = 0; i < edges.size(); i++) { Edge e = edges[i]; if (order[e.x] < order[e.y]) { cout << e.x + 1 << << e.y + 1 << endl; } else { cout << e.y + 1 << << e.x + 1 << endl; } } } } return 0; }
|
//#############################################################################
//# Purpose: Low power standby state machine #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_standby #( parameter PD = 5, // cycles to stay awake after "wakeup"
parameter N = 5) // project name
(
input clkin, //clock input
input nreset,//async active low reset
input [N-1:0] wakeup, //wake up event vector
input idle, //core is in idle
output clkout //clock output
);
//Wire declarations
reg [PD-1:0] wakeup_pipe;
reg idle_reg;
wire state_change;
wire clk_en;
wire [N-1:0] wakeup_pulse;
wire wakeup_now;
// Wake up on any external event change
oh_edge2pulse #(.DW(N))
oh_edge2pulse (.out (wakeup_pulse[N-1:0]),
.clk (clkin),
.nreset (nreset),
.in (wakeup[N-1:0]));
assign wakeup_now = |(wakeup_pulse[N-1:0]);
// Stay away for PD cycles
always @ (posedge clkin or negedge nreset)
if(!nreset)
wakeup_pipe[PD-1:0] <= 'b0;
else
wakeup_pipe[PD-1:0] <= {wakeup_pipe[PD-2:0], wakeup_now};
// Clock enable
assign clk_en = wakeup_now | //immediate wakeup
(|wakeup_pipe[PD-1:0]) | //anything in pipe
~idle; //core not in idle
// Clock gating cell
oh_clockgate oh_clockgate (.eclk(clkout),
.clk(clkin),
.en(clk_en),
.te(1'b0));
endmodule // oh_standby
|
#include <bits/stdc++.h> using namespace std; long long powmod(long long base, long long exponent, long long mod) { long long ans = 1; while (exponent) { if (exponent & 1) ans = (ans * base) % mod; base = (base * base) % mod; exponent /= 2; } return ans; } long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } const int upperlimit = 71; const int mod = 998244353; long long fact[upperlimit]; long long invfact[upperlimit]; vector<long long> pdv; void func(long long n) { for (int i = 2; i <= sqrt(n); i++) { if (n % i == 0) pdv.push_back(i); while (n % i == 0) n /= i; } if (n > 1) pdv.push_back(n); } int pw(long long n, long long i) { int ans = 0; while (n % i == 0) { ans++; n /= i; } return ans; } int main() { fact[0] = 1; invfact[0] = 1; for (int i = 1; i < upperlimit; i++) { fact[i] = fact[i - 1]; fact[i] *= i; fact[i] %= mod; invfact[i] = powmod(fact[i], mod - 2, mod); } long long d, u, v; int q; long long temp = 1; int lol = 0; scanf( %lld , &d); func(d); scanf( %d , &q); while (q--) { scanf( %lld , &u); scanf( %lld , &v); long long gc = gcd(u, v); temp = 1; lol = 0; for (int i = 0; i < pdv.size(); i++) { int gg = abs(pw(gc, pdv[i]) - pw(u, pdv[i])); temp *= invfact[gg]; temp %= mod; lol += gg; } temp *= fact[lol]; temp %= mod; lol = 0; for (int i = 0; i < pdv.size(); i++) { int gg = abs(pw(gc, pdv[i]) - pw(v, pdv[i])); temp *= invfact[gg]; temp %= mod; lol += gg; } temp *= fact[lol]; temp %= mod; printf( %lld n , temp); } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module example_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 5,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle,
output wire [31:0] mode
);
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of mode
// bit 31~0 - mode[31:0] (Read/Write)
// 0x14 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 5'h00,
ADDR_GIE = 5'h04,
ADDR_IER = 5'h08,
ADDR_ISR = 5'h0c,
ADDR_MODE_DATA_0 = 5'h10,
ADDR_MODE_CTRL = 5'h14,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
RDIDLE = 2'd0,
RDDATA = 2'd1,
ADDR_BITS = 5;
//------------------------Local signal-------------------
reg [1:0] wstate;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire int_ap_idle;
wire int_ap_ready;
reg int_ap_done;
reg int_ap_start;
reg int_auto_restart;
reg int_gie;
reg [1:0] int_ier;
reg [1:0] int_isr;
reg [31:0] int_mode;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRIDLE;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDIDLE;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
ADDR_MODE_DATA_0: begin
rdata <= int_mode[31:0];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign int_ap_idle = ap_idle;
assign int_ap_ready = ap_ready;
assign mode = int_mode;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (int_ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
// int_mode[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_mode[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_MODE_DATA_0)
int_mode[31:0] <= (WDATA[31:0] & wmask) | (int_mode[31:0] & ~wmask);
end
end
//------------------------Memory logic-------------------
endmodule
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << endl; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void run_case() { long long lim = 1, n, i, j, k, cnt = 0, sum = 0; cin >> n; vector<long long int> a(n); for (i = 0; i < n; i++) cin >> a[i], lim *= 3; for (i = 1; i < lim; i++) { k = i; sum = 0; for (j = 0; j < n; j++) { cnt = k % 3; if (cnt == 1) sum += a[j]; if (cnt == 2) sum -= a[j]; k /= 3; } if (sum == 0) { cout << YES << endl; return; } } cout << NO << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int tc; cin >> tc; while (tc--) { run_case(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int MOD = 1e9 + 7; vector<int> prefix_function(vector<int> s) { int n = s.size(); vector<int> pi(n); pi[0] = 0; for (int i = 1; i < n; ++i) { int j = pi[i - 1]; while (j > 0 && s[i] != s[j]) { j = pi[j - 1]; } if (s[i] == s[j]) { ++j; } pi[i] = j; } return pi; } vector<int> res_vector(vector<int> s, vector<int> t) { vector<int> res = s; res.push_back(2 * INF); for (int i = 0; i < t.size(); ++i) { res.push_back(t[i]); } return res; } vector<int> process(vector<int> res, vector<int> pi, int n) { vector<int> ans(res.size()); for (int i = n + 1; i < res.size(); ++i) { ++ans[pi[i]]; } for (int i = res.size() - 1; i >= n + 1; --i) { ans[pi[i - 1]] += ans[i]; } return ans; } int main() { ios::sync_with_stdio(0); int n, w; cin >> n >> w; if (w == 1) { cout << n << endl; return 0; } vector<int> a(n - 1); int last; cin >> last; for (int i = 0; i < n - 1; ++i) { int temp; cin >> temp; a[i] = temp - last; last = temp; } cin >> last; vector<int> b(w - 1); for (int i = 0; i < w - 1; ++i) { int temp; cin >> temp; b[i] = temp - last; last = temp; } vector<int> res = res_vector(b, a); vector<int> pi = prefix_function(res); vector<int> ans = process(res, pi, b.size()); cout << ans[w - 1] << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 400010; inline long long read() { long long s = 0, w = 1; register char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = (s << 3) + (s << 1) + (ch - 0 ), ch = getchar(); return s * w; } void print(long long x) { if (x < 0) x = -x, putchar( - ); if (x > 9) print(x / 10); putchar(x % 10 + 0 ); } long long n, deg[N], root, cnt; struct Node { long long a, b, c; } h[N]; long long head[N], maxE; struct Edge { long long nxt, to, rdis; } e[N << 1]; inline void Add(long long u, long long v, long long w) { e[++maxE].nxt = head[u]; head[u] = maxE; e[maxE].to = v; e[maxE].rdis = w; } long long DFS(long long x, long long fa, long long w) { long long res; long long p, q; res = p = q = 0; for (long long i = head[x]; i; i = e[i].nxt) { if (e[i].to == fa) continue; res += e[i].rdis; long long gt = DFS(e[i].to, x, e[i].rdis); (p ? q : p) = gt; } if (x == root) return p; if (!p) p = x, h[++cnt] = (Node){p, root, w}; else { h[++cnt] = (Node){p, q, (res - w) / 2}; h[++cnt] = (Node){p, root, (w - res) / 2}; h[++cnt] = (Node){q, root, (w - res) / 2}; } return p; } signed main() { n = read(); for (register long long i = 1; i < n; i++) { long long u, v, w; u = read(), v = read(), w = read(); Add(u, v, w), Add(v, u, w); deg[u]++, deg[v]++; } for (register long long i = 1; i <= n; i++) { if (deg[i] == 2) { puts( NO ); return 0; } if (deg[i] == 1) root = i; } puts( YES ); DFS(root, 0, 0); printf( %lld n , cnt); for (register long long i = 1; i <= cnt; i++) printf( %lld %lld %lld n , h[i].a, h[i].b, h[i].c); return 0; }
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#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; const int N = 3e5 + 5; const int INF = 1e9 + 7; vector<int> graph[N]; multiset<int, greater<int>> st; int n, a, b, dat[N], ans, cur; void rem(int val) { auto it = st.find(val); st.erase(it); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); ans = INF; cin >> n; for (int i = (0); i < (n); i++) { cin >> dat[i]; st.insert(dat[i]); } for (int i = (0); i < (n - 1); i++) { cin >> a >> b; --a; --b; graph[a].push_back(b); graph[b].push_back(a); } for (int i = (0); i < (n); i++) { rem(dat[i]); for (auto it : graph[i]) rem(dat[it]); cur = -INF; cur = max(cur, dat[i]); if (!st.empty()) cur = max(cur, *st.begin() + 2); st.insert(dat[i]); for (auto it : graph[i]) { st.insert(dat[it]); cur = max(cur, dat[it] + 1); } ans = min(ans, cur); } cout << ans << n ; return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// SERDES Interface
// LS-Byte is sent first, MS-Byte is second
// Invalid K Codes
// K0.0 000-00000 Error detected
// K31.7 111-11111 Loss of input signal
// Valid K Codes
// K28.0 000-11100
// K28.1 001-11100 Alternate COMMA?
// K28.2 010-11100
// K28.3 011-11100
// K28.4 100-11100
// K28.5 101-11100 Standard COMMA?
// K28.6 110-11100
// K28.7 111-11100 Bad COMMA?
// K23.7 111-10111
// K27.7 111-11011
// K29.7 111-11101
// K30.7 111-11110
module serdes_tx
#(parameter FIFOSIZE = 9)
(input clk,
input rst,
// TX HW Interface
output ser_tx_clk,
output reg [15:0] ser_t,
output reg ser_tklsb,
output reg ser_tkmsb,
// TX Stream Interface
input [31:0] rd_dat_i,
input [3:0] rd_flags_i,
output rd_ready_o,
input rd_ready_i,
// Flow control interface
input inhibit_tx,
input send_xon,
input send_xoff,
output sent,
// FIFO Levels
output [15:0] fifo_occupied,
output fifo_full,
output fifo_empty,
// DEBUG
output [31:0] debug
);
localparam K_COMMA = 8'b101_11100; // 0xBC K28.5
localparam K_IDLE = 8'b001_11100; // 0x3C K28.1
localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6
localparam K_PKT_END = 8'b100_11100; // 0x9C K28.4
localparam K_XON = 8'b010_11100; // 0x5C K28.2
localparam K_XOFF = 8'b011_11100; // 0x7C K28.3
localparam K_LOS = 8'b111_11111; // 0xFF K31.7
localparam K_ERROR = 8'b000_00000; // 0x00 K00.0
localparam D_56 = 8'b110_00101; // 0xC5 D05.6
assign ser_tx_clk = clk;
localparam IDLE = 3'd0;
localparam RUN1 = 3'd1;
localparam RUN2 = 3'd2;
localparam DONE = 3'd3;
localparam SENDCRC = 3'd4;
localparam WAIT = 3'd5;
reg [2:0] state;
reg [15:0] CRC;
wire [15:0] nextCRC;
reg [3:0] wait_count;
// Internal FIFO, size 9 is 2K, size 10 is 4K bytes
wire sop_o, eop_o;
wire [31:0] data_o;
wire rd_sop_i = rd_flags_i[0];
wire rd_eop_i = rd_flags_i[1];
wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused
wire have_data, empty, read;
fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
(.clk(clk),.reset(rst),.clear(0),
.datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o),
.dataout({sop_o,eop_o,data_o}), .dst_rdy_i(read), .src_rdy_o(have_data),
.space(), .occupied(fifo_occupied) );
assign fifo_full = ~rd_ready_o;
assign empty = ~have_data;
assign fifo_empty = empty;
// FIXME Implement flow control
reg [15:0] second_word;
reg [33:0] pipeline;
assign read = (~send_xon & ~send_xoff & (state==RUN2)) | ((state==IDLE) & ~empty & ~sop_o);
assign sent = send_xon | send_xoff;
// 2nd half of above probably not necessary. Just in case we get junk between packets
always @(posedge clk)
if(rst)
begin
state <= IDLE;
wait_count <= 0;
{ser_tkmsb,ser_tklsb,ser_t} <= 18'd0;
//{2'b10,K_COMMA,K_COMMA};
// make tkmsb and tklsb different so they can go in IOFFs
end
else
if(send_xon)
{ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XON,K_XON};
else if(send_xoff)
{ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XOFF,K_XOFF};
else
case(state)
IDLE :
begin
if(sop_o & ~empty & ~inhibit_tx)
begin
{ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_START,K_PKT_START};
state <= RUN1;
end
else
{ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56};
end
RUN1 :
begin
if(empty | inhibit_tx)
{ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56};
else
begin
{ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[15:0]};
state <= RUN2;
end
end
RUN2 :
begin
{ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[31:16]};
if(eop_o)
state <= DONE;
else
state <= RUN1;
end
DONE :
begin
{ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_END,K_PKT_END};
state <= SENDCRC;
end
SENDCRC :
begin
{ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,CRC};
state <= WAIT;
wait_count <= 4'd15;
end
WAIT :
begin
{ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56};
if(wait_count == 0)
state <= IDLE;
else
wait_count <= wait_count - 1;
end
default
state <= IDLE;
endcase // case(state)
always @(posedge clk)
if(rst)
CRC <= 16'hFFFF;
else if(state == IDLE)
CRC <= 16'hFFFF;
else if( (~empty & ~inhibit_tx & (state==RUN1)) || (state==RUN2) )
CRC <= nextCRC;
CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, nextCRC);
assign debug = { 28'd0, state[2:0] };
endmodule // serdes_tx
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#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int INF = (int)1e9; const long long LINF = (long long)1e18; const long double PI = 2 * acos((long double)0); long long gcd(long long a, long long b) { long long r; while (b) { r = a % b; a = b; b = r; } return a; } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } long long fpow(long long n, long long k, int p = MOD) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } template <class T> void setmin(T& a, T val) { if (a > val) a = val; } template <class T> void setmax(T& a, T val) { if (a < val) a = val; } void addmod(int& a, int val, int p = MOD) { if ((a = (a + val)) >= p) a -= p; } void submod(int& a, int val, int p = MOD) { if ((a = (a - val)) < 0) a += p; } int mult(int a, int b, int p = MOD) { return (long long)a * b % p; } int inv(int a, int p = MOD) { return fpow(a, p - 2, p); } const int maxn = 200010; long long n, d, m; long long x[maxn]; long long p[maxn]; long long st[4 * maxn]; void build(int node, int L, int R) { if (L == R) { st[node] = p[L]; return; } build(node << 1, L, (L + R) >> 1); build((node << 1) + 1, ((L + R) >> 1) + 1, R); st[node] = min(st[node << 1], st[(node << 1) + 1]); } long long query(int node, int l, int r, int L, int R) { if (l > R || r < L) return LINF; if (l <= L && r >= R) return st[node]; return min(query(node << 1, l, r, L, (L + R) >> 1), query((node << 1) + 1, l, r, ((L + R) >> 1) + 1, R)); } void solve() { cin >> d >> n >> m; vector<pair<int, int> > v; for (int i = (1); i < (m + 1); i++) { cin >> x[i] >> p[i]; v.push_back(make_pair(x[i], p[i])); } sort((v).begin(), (v).end()); for (int i = (1); i < (m + 1); i++) { x[i] = v[i - 1].first; p[i] = v[i - 1].second; } x[m + 1] = d; build(1, 0, m + 1); int cur = 0; long long ans = 0, r = 0; while (cur < m + 1) { if (x[cur] + n < x[cur + 1]) { cout << -1; return; } int lo = cur + 1, hi = upper_bound(x, x + m + 2, x[cur] + n) - x - 1; while (lo < hi) { int mid = (lo + hi) >> 1; if (query(1, cur + 1, mid, 0, m + 1) > p[cur]) lo = mid + 1; else hi = mid; } if (query(1, cur + 1, lo, 0, m + 1) <= p[cur]) { ans += p[cur] * max(0LL, x[lo] - x[cur] - r); r = max(0LL, x[cur] + r - x[lo]); cur = lo; } else { ans += (n - r) * p[cur]; r = x[cur] + n - x[cur + 1]; cur++; } } cout << ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; bool comp(int a, int b) { return (a > b); } int gcd(int a, int b) { if (b == 0) return a; else return gcd(b, a % b); } int main(void) { long long int n, m, k; cin >> n >> m >> k; if (k > (n + m - 2)) { cout << -1 ; return 0; } long long int ans; if (m > n) swap(n, m); if (k <= m - 1) ans = max(m / (k + 1) * n, n / (k + 1) * m); else if (k <= n - 1) ans = n / (k + 1) * m; else ans = m / (k - n + 2); cout << ans; return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast,unroll-loops,no-stack-protector ) using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int N = 3005; map<int, vector<int> > dif; vector<int> mod[8]; int a[N]; int n; template <class C, class F> struct Mcmf { static constexpr F eps = (F)1e-9; struct Edge { int u, v, inv; F cap, flow; C cost; Edge(int u, int v, C cost, F cap, int inv) : u(u), v(v), cost(cost), cap(cap), flow(0), inv(inv) {} }; int second, t, tm, n, m = 0; vector<vector<Edge> > g; vector<Edge*> prev; vector<C> cost; vector<int> state; Mcmf(int n, int ss = -1, int tt = -1) : n(n), g(n + 5), cost(n + 5), state(n + 5), prev(n + 5) { second = n + 1; tm = n + 2; t = n + 3; } void add(int u, int v, C cost, F cap) { g[u].push_back(Edge(u, v, cost, cap, int(g[v].size()))); g[v].push_back(Edge(v, u, -cost, 0, int(g[u].size()) - 1)); m += 2; } bool bfs() { fill(begin(state), end(state), 2); fill(begin(cost), end(cost), numeric_limits<C>::max()); fill(begin(prev), end(prev), nullptr); deque<int> qu; qu.push_back(second); state[second] = 1, cost[second] = 0; while (int(qu.size())) { int u = qu.front(); qu.pop_front(); state[u] = 0; for (Edge& e : g[u]) if (e.cap - e.flow > eps) if (cost[u] + e.cost < cost[e.v]) { cost[e.v] = cost[u] + e.cost; prev[e.v] = &e; if (state[e.v] == 0 || (int(qu.size()) && cost[qu.front()] > cost[e.v])) qu.push_front(e.v); else if (state[e.v] == 2) qu.push_back(e.v); state[e.v] = 1; } } return cost[t] != numeric_limits<C>::max(); } pair<C, F> minCostFlow() { C cost = 0; F flow = 0; while (bfs()) { F nflow = numeric_limits<F>::max(); for (Edge* e = prev[t]; e != nullptr; e = prev[e->u]) nflow = min(nflow, e->cap - e->flow); for (Edge* e = prev[t]; e != nullptr; e = prev[e->u]) { e->flow += nflow; g[e->v][e->inv].flow -= nflow; cost += e->cost * nflow; } flow += nflow; } return make_pair(cost, flow); } }; int main() { cin.tie(0)->sync_with_stdio(0), cout.tie(0); cin >> n; for (auto i = (0) - ((0) > (n)); i != n - ((0) > (n)); i += 1 - 2 * ((0) > (n))) cin >> a[i]; Mcmf<int, int> mcmf(2 * n); for (auto i = (0) - ((0) > (n)); i != n - ((0) > (n)); i += 1 - 2 * ((0) > (n))) { mcmf.add(mcmf.second, (i), 0, 1); mcmf.add((i), (n + (i)), -1, 1); mcmf.add((n + (i)), mcmf.tm, 0, 1); for (auto j = (i + 1) - ((i + 1) > (n)); j != n - ((i + 1) > (n)); j += 1 - 2 * ((i + 1) > (n))) if (a[i] % 7 == a[j] % 7 || abs(a[i] - a[j]) <= 1) mcmf.add((n + (i)), (j), 0, 1); } mcmf.add(mcmf.tm, mcmf.t, 0, 4); auto best = mcmf.minCostFlow(); ; cout << -best.first << n ; return 0; }
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///////////////////////////////////////////////////////////////////////////
//
// To test:
// (a) The use & representation of time variables
// (b) The display of time variables
//
// Compile and run the program
// iverilog tt_clean.v
// vvp a.out
//
// VISUALLY INSPECT the displays. (There ain't no way to automate this)
//
///////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
`define PCI_CLK_PERIOD 15.0 // 66 Mhz
module top;
reg PCI_Clk;
reg fail;
initial PCI_Clk <= 0;
always #(`PCI_CLK_PERIOD/2) PCI_Clk <= ~PCI_Clk;
initial begin
fail = 0;
$display("\n\t\t==> CHECK THIS DISPLAY ==>\n");
$display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD);
$display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD);
if($time !== 0) fail = 1;
if (fail == 1)
$display("$time=%0d (0)", $time);
delay_pci(3);
if($simtime !== 4500) fail = 1;
if($time !== 45) fail = 1;
if (fail == 1)
$display("$time=%0d (45)", $time);
#15;
if($simtime !== 6000) fail = 1;
if($time !== 60) fail = 1;
#(`PCI_CLK_PERIOD);
if($simtime !== 7500) fail = 1;
if($time !== 75) fail = 1;
#(`PCI_CLK_PERIOD *2);
if($simtime !== 10500) fail = 1;
if($time !== 105) fail = 1;
$timeformat(-9,2,"ns",20);
$display("after setting timeformat:");
$display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD);
$display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD);
delay_pci(3);
if($simtime !== 15000) fail = 1;
if($time !== 150) fail = 1;
#15;
if($simtime !== 16500) fail = 1;
if($time !== 165) fail = 1;
#(`PCI_CLK_PERIOD);
if($simtime !== 18000) fail = 1;
if($time !== 180) fail = 1;
#(`PCI_CLK_PERIOD *2);
if($simtime !== 21000) fail = 1;
if($time !== 210) fail = 1;
$display("\t\t**********************************************");
if(fail) $display("\t\t****** time representation test BAD *******");
else $display("\t\t****** time representation test OK *******");
$display("\t\t**********************************************\n");
$finish;
end
task delay_pci;
input delta;
integer delta;
integer ii;
begin
#(`PCI_CLK_PERIOD * delta);
end
endtask
endmodule
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#include <bits/stdc++.h> using namespace std; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } const int INF = (((1 << 30) - 1) << 1) + 1; const int nINF = 1 << 31; pair<long long, long long> egcd(long long a, long long b, pair<long long, long long> x = {1, 0}, pair<long long, long long> y = {0, 1}) { return (b == 0) ? x : egcd(b, a % b, y, {x.first - a / b * y.first, x.second - a / b * y.second}); } long long modInv(long long a, long long n) { return ((egcd(a, n).first % n) + n) % n; } const long long M = 998244353; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long mult(long long a, long long b) { return (a * b) % M; } long long add(long long a, long long b) { return (a + b) % M; } struct frac { long long n, d; void simp() { long long g = gcd(n, d); n /= g; d /= g; } frac(long long in_n, long long in_d) { n = in_n, d = in_d; simp(); } frac operator+(frac& oth) { frac ret(n * oth.d + d * oth.n, d * oth.d); ret.simp(); return ret; } }; const int N = 2e5 + 10; int n, p[N], m = 0, l[N], have[N]; long long bit[N]; long long getSum(int i) { long long sum = 0; ++i; while (i > 0) { sum += bit[i]; i -= i & (-i); } return sum; } void updateBIT(int i, long long val) { ++i; while (i <= n + 5) { bit[i] += val; i += i & (-i); } } signed main() { ios::sync_with_stdio(false); cin >> n; for (int i = 0; i < (n); i++) { cin >> p[i]; if (p[i] != -1) have[p[i]] = 1; else ++m; } for (int i = (1); i <= (n); i++) { l[i] = l[i - 1]; if (!have[i]) ++l[i]; } long long k = 0; frac einv(0, 1); frac lm(0, 1); long long lmi = 0; long long inv = 0; long long ans = 0; for (int i = 0; i < (n); i++) { int x = p[i]; if (x != -1) { int above = getSum(n) - getSum(x); inv += above; ans = add(ans, above); updateBIT(x, 1); if (m) { frac ex((m - l[x]) * k, m); frac cex(l[x], m); einv = einv + ex; lm = lm + cex; lmi = add(lmi, mult(cex.n, modInv(cex.d, M))); ans = add(ans, mult(ex.n, modInv(ex.d, M))); } } else { einv = einv + lm; ans = add(ans, lmi); frac ex(k, 2); einv = einv + ex; ans = add(ans, mult(ex.n, modInv(ex.d, M))); ++k; } } frac kinv(inv, 1); cout << ans << endl; return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] par1; // From a1 of t_param_first_a.v
wire [4:0] par2; // From a2 of t_param_first_a.v
wire [4:0] par3; // From a3 of t_param_first_a.v
wire [4:0] par4; // From a4 of t_param_first_a.v
wire [1:0] varwidth1; // From a1 of t_param_first_a.v
wire [2:0] varwidth2; // From a2 of t_param_first_a.v
wire [3:0] varwidth3; // From a3 of t_param_first_a.v
wire [3:0] varwidth4; // From a4 of t_param_first_a.v
// End of automatics
/*t_param_first_a AUTO_TEMPLATE (
.par (par@[]));
.varwidth (varwidth@[]));
*/
parameter XX = 2'bXX;
parameter THREE = 3;
t_param_first_a #(1,5) a1
(
// Outputs
.varwidth (varwidth1[1:0]),
/*AUTOINST*/
// Outputs
.par (par1[4:0])); // Templated
t_param_first_a #(2,5) a2
(
// Outputs
.varwidth (varwidth2[2:0]),
/*AUTOINST*/
// Outputs
.par (par2[4:0])); // Templated
t_param_first_a #(THREE,5) a3
(
// Outputs
.varwidth (varwidth3[3:0]),
/*AUTOINST*/
// Outputs
.par (par3[4:0])); // Templated
t_param_first_a #(THREE,5) a4
(
// Outputs
.varwidth (varwidth4[3:0]),
/*AUTOINST*/
// Outputs
.par (par4[4:0])); // Templated
parameter THREE_BITS_WIDE = 3'b011;
parameter THREE_2WIDE = 2'b11;
parameter ALSO_THREE_WIDE = THREE_BITS_WIDE;
parameter THREEPP_32_WIDE = 2*8*2+3;
parameter THREEPP_3_WIDE = 3'd4*3'd4*3'd2+3'd3; // Yes folks VCS says 3 bits wide
// Width propagation doesn't care about LHS vs RHS
// But the width of a RHS/LHS on a upper node does affect lower nodes;
// Thus must double-descend in width analysis.
// VCS 7.0.1 is broken on this test!
parameter T10 = (3'h7+3'h7)+4'h0; //initial if (T10!==4'd14) $stop;
parameter T11 = 4'h0+(3'h7+3'h7); //initial if (T11!==4'd14) $stop;
// Parameters assign LHS is affectively width zero.
parameter T12 = THREE_2WIDE + THREE_2WIDE; initial if (T12!==2'd2) $stop;
parameter T13 = THREE_2WIDE + 3; initial if (T13!==32'd6) $stop;
// Must be careful about LSB's with extracts
parameter [39:8] T14 = 32'h00_1234_56; initial if (T14[24:16]!==9'h34) $stop;
//
parameter THREEPP_32P_WIDE = 3'd4*3'd4*2+3'd3;
parameter THREE_32_WIDE = 3%32;
parameter THIRTYTWO = 2; // Param is 32 bits
parameter [40:0] WIDEPARAM = 41'h12_3456789a;
parameter [40:0] WIDEPARAM2 = WIDEPARAM;
reg [7:0] eightb;
reg [3:0] fourb;
wire [7:0] eight = 8'b00010000;
wire [1:0] eight2two = eight[THREE_32_WIDE+1:THREE_32_WIDE];
wire [2:0] threebits = ALSO_THREE_WIDE;
// surefire lint_off CWCCXX
initial _ranit = 0;
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
$write("[%0t] t_param: Running\n", $time);
//
$write(" %d %d %d\n", par1,par2,par3);
if (par1!==5'd1) $stop;
if (par2!==5'd2) $stop;
if (par3!==5'd3) $stop;
if (par4!==5'd3) $stop;
if (varwidth1!==2'd2) $stop;
if (varwidth2!==3'd2) $stop;
if (varwidth3!==4'd2) $stop;
if (varwidth4!==4'd2) $stop;
if (threebits !== 3'b011) $stop;
if (eight !== 8'b00010000) $stop;
if (eight2two !== 2'b10) $stop;
$write(" Params = %b %b\n %b %b\n",
THREEPP_32_WIDE,THREEPP_3_WIDE,
THIRTYTWO, THREEPP_32P_WIDE);
if (THREEPP_32_WIDE !== 32'h23) $stop;
if (THREEPP_3_WIDE !== 3'h3) $stop;
if (THREEPP_32P_WIDE !== 32'h23) $stop;
if (THIRTYTWO[1:0] !== 2'h2) $stop;
if (THIRTYTWO !== 32'h2) $stop;
if (THIRTYTWO !== 2) $stop;
if ((THIRTYTWO[1:0]+2'b00) !== 2'b10) $stop;
if ({1'b1,{THIRTYTWO[1:0]+2'b00}} !== 3'b110) $stop;
if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1'bx!=0 && !=1
//
// Example of assignment LHS affecting expression widths.
// verilator lint_off WIDTH
// surefire lint_off ASWCMB
// surefire lint_off ASWCBB
eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop;
fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop;
fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop;
// verilator lint_on WIDTH
// surefire lint_on ASWCMB
// surefire lint_on ASWCBB
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long INFF = 0x3f3f3f3f3f3f3f3f; const double pi = acos(-1.0); const double eps = 1e-9; const long long mod = 1e9 + 7; int read() { int x = 0, f = 1; char ch = getchar(); while (ch< 0 | ch> 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } void Out(int aa) { if (aa > 9) Out(aa / 10); putchar(aa % 10 + 0 ); } int x[505], y[505]; int dp[1010][1010]; int n, m, k; bool check(int t) { vector<int> X, Y; X.push_back(1), X.push_back(n + 1); Y.push_back(1), Y.push_back(m + 1); for (int i = 1; i <= k; i++) { X.push_back(max(x[i] - t, 1)), X.push_back(min(n + 1, x[i] + t + 1)); Y.push_back(max(1, y[i] - t)), Y.push_back(min(m + 1, y[i] + t + 1)); } sort(X.begin(), X.end()); X.erase(unique(X.begin(), X.end()), X.end()); sort(Y.begin(), Y.end()); Y.erase(unique(Y.begin(), Y.end()), Y.end()); memset(dp, 0, sizeof(dp)); for (int i = 1; i <= k; i++) { int l1 = lower_bound(X.begin(), X.end(), max(x[i] - t, 1)) - X.begin(); int l2 = lower_bound(X.begin(), X.end(), min(x[i] + t + 1, n + 1)) - X.begin(); int r1 = lower_bound(Y.begin(), Y.end(), max(y[i] - t, 1)) - Y.begin(); int r2 = lower_bound(Y.begin(), Y.end(), min(y[i] + t + 1, m + 1)) - Y.begin(); dp[l1][r1]++, dp[l2][r2]++; dp[l1][r2]--; dp[l2][r1]--; } int l = n + 1, r = 0; int u = m + 1, d = 0; for (int i = 0; i < X.size() - 1; i++) for (int j = 0; j < Y.size() - 1; j++) { if (i && j) dp[i][j] += -dp[i - 1][j - 1] + dp[i][j - 1] + dp[i - 1][j]; else if (i) dp[i][j] += dp[i - 1][j]; else if (j) dp[i][j] += dp[i][j - 1]; if (dp[i][j]) continue; l = min(l, X[i]); r = max(r, X[i + 1] - 1); u = min(u, Y[j]); d = max(d, Y[j + 1] - 1); } return max(r - l, d - u) <= 2 * t; } int main() { n = read(), m = read(), k = read(); for (int i = 1; i <= k; i++) x[i] = read(), y[i] = read(); int l = 0, r = max(n, m); int ans = r; while (r >= l) { int mid = (l + r) / 2; if (check(mid)) ans = mid, r = mid - 1; else l = mid + 1; } Out(ans); return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T> bool uin(T &a, T b) { return (a > b ? a = b, true : false); } template <class T> bool uax(T &a, T b) { return (a < b ? a = b, true : false); } int const X = 8; int const L = 16; int const N = 41; long long const INF = 3e18 + 41; int x, k, n, q; int c[N]; int p[N], w[N]; long long d[(1 << X)][(1 << X)][L]; long long ans; bool bit(int m, int i) { return (m & (1 << i)); } int xorbit(int m, int i) { return (m ^ (1 << i)); } int dx[(1 << X)][(1 << X)]; unordered_map<int, int> a; vector<pair<int, long long>> e[(1 << X)][L]; void build() { for (int i = 0; i < (1 << X); ++i) for (int j = 0; j < (1 << X); ++j) for (int o = 0; o < L; ++o) d[i][j][o] = INF; memset(dx, 255, sizeof(dx)); for (int i = 0; i < (1 << k); ++i) { if (!bit(i, 0)) { int m0 = i; int m1 = (m0 >> 1); uin(d[m0][m1][0], 0ll); } else { int m0 = i; for (int j = 1; j < k + 1; ++j) { if (bit(m0, j)) continue; int m1 = xorbit(m0, j); m1 = xorbit(m1, 0); m1 >>= 1; if (uin(d[m0][m1][0], (long long)c[j - 1])) dx[m0][m1] = j; } } } for (int o = 1; o < L; ++o) { for (int t = 0; t < (1 << k); ++t) { for (int i = 0; i < (1 << k); ++i) { for (int j = 0; j < (1 << k); ++j) { uin(d[i][j][o], d[i][t][o - 1] + d[t][j][o - 1]); } } } } for (int o = 0; o < L; ++o) { for (int i = 0; i < (1 << X); ++i) for (int j = 0; j < (1 << X); ++j) if (d[i][j][o] < INF) { e[i][o].push_back(make_pair(j, d[i][j][o])); } } } long long f[(1 << X)], nf[(1 << X)]; void solve() { int p1 = 0; int x0 = 0; for (int i = 0; i < (1 << X); ++i) f[i] = INF; f[(1 << x) - 1] = 0; while (x0 < n - x) { while (p1 < q && x0 > p[p1]) ++p1; int s; for (int i = L - 1; i >= 0; --i) { s = i; if (x0 + (1 << i) + k - 1 > n - 1) continue; if (p1 != q && x0 + (1 << i) + k - 1 >= p[p1]) continue; break; } for (int i = 0; i < (1 << k); ++i) nf[i] = INF; for (int i = 0; i < (1 << k); ++i) { if (f[i] == INF) continue; for (pair<int, long long> p : e[i][s]) { long long v = f[i] + p.second; if (s == 0 && dx[i][p.first] != -1 && a.find(x0 + dx[i][p.first]) != a.end()) { v += a[x0 + dx[i][p.first]]; } uin(nf[p.first], v); } } memcpy(f, nf, sizeof(f)); x0 += (1 << s); } ans = f[(1 << x) - 1]; } int main() { scanf( %d %d %d %d , &x, &k, &n, &q); for (int i = 0; i < k; ++i) scanf( %d , &c[i]); for (int i = 0; i < q; ++i) { scanf( %d %d , &p[i], &w[i]); --p[i]; a[p[i]] = w[i]; } for (int i = 0; i < q; ++i) for (int j = i + 1; j < q; ++j) if (p[j] < p[i]) { swap(p[j], p[i]); swap(w[j], w[i]); } build(); solve(); printf( %I64d n , ans); return 0; }
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/////////////////////////////
//LAB01 29/05 - Atividade 1//
/////////////////////////////
module Mod_Teste(
input CLOCK_27,
input CLOCK_50,
input [3:0] KEY,
input [17:0] SW,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
output [8:0] LEDG,
output [17:0] LEDR,
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0, // GPIO Connection 0
inout [35:0] GPIO_1
);
assign GPIO_1 = 36'hzzzzzzzzz;
assign GPIO_0 = 36'hzzzzzzzzz;
// LCD
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
LCD_TEST LCD0 (
// Host Side
.iCLK ( CLOCK_50 ),
.iRST_N ( KEY[0] ),
// Data to display
.d0(CONST_bus), // 4 dígitos canto superior esquerdo
.d1(), // 4 dígitos superior meio
.d2(CONST_bus), // 4 dígitos canto superior direito
.d3(ADDR_bus), // 4 dígitos canto inferior esquerdo
.d4(DATA_bus), // 4 dígitos inferior meio
.d5(D_bus_internal), // 4 dígitos canto inferior direito
// LCD Side
.LCD_DATA( LCD_DATA ),
.LCD_RW( LCD_RW ),
.LCD_EN( LCD_EN ),
.LCD_RS( LCD_RS )
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter OPCODE_WIDTH = 7;
parameter INSTR_WIDTH = WORD_WIDTH;
parameter CNTRL_WIDTH = 3*DR_WIDTH+11;
wire RST_key = KEY[0];
wire CLK_key = KEY[3];
//reg RST_key;
//reg CLK_key;
wire [WORD_WIDTH-1:0] ADDR_bus, DATA_bus, DATA_in_bus, CONST_bus, PC_out, INSTRM_out, D_bus_internal;
wire [CNTRL_WIDTH-1:0] CNTRL_bus;
wire [3:0] FLAG_bus;
assign DATA_in_bus = SW[17:3];
assign LEDR = VIEWER_MUX_OUT[19:2];
assign LEDG = VIEWER_MUX_OUT[1:0];
ControlUnit CU0(
.CNTRL_out(CNTRL_bus),
.CONST_out(CONST_bus),
.PC_out(PC_out),
.INSTRM_in(INSTRM_out),
.INSTR_in(ADDR_bus),
.FLAG_in(FLAG_bus),
.RST_in(RST_key),
.CLK_in(CLK_key)
);
defparam CU0.WORD_WIDTH = WORD_WIDTH;
defparam CU0.DR_WIDTH = DR_WIDTH;
InstructionMemory IM0(
.INSTR_in(PC_out),
.INSTR_out(INSTRM_out)
);
defparam IM0.WORD_WIDTH = WORD_WIDTH;
defparam IM0.DR_WIDTH = DR_WIDTH;
Datapath DP0(
.FLAG_out(FLAG_bus),
.A_bus(ADDR_bus),
.D_bus(DATA_bus),
.D_bus_internal(D_bus_internal),
.D_in(DATA_in_bus),
.CNTRL_in(CNTRL_bus),
.CONST_in(CONST_bus),
.CLK(CLK_key)
);
defparam DP0.WORD_WIDTH = WORD_WIDTH;
defparam DP0.DR_WIDTH = DR_WIDTH;
/*
DataMemory DM0(
.Data_out(DATA_in_bus),
.Addr_in(ADDR_bus),
.Data_in(DATA_bus),
.CNTRL_in(CNTRL_bus)
);
*/
wire [3:0] VIEWER_MUX_OUT0;
wire [3:0] VIEWER_MUX_OUT1;
wire [3:0] VIEWER_MUX_OUT2;
wire [3:0] VIEWER_MUX_OUT3;
wire [3:0] VIEWER_MUX_OUT4;
reg [CNTRL_WIDTH-1:0] VIEWER_MUX_OUT;
assign VIEWER_MUX_OUT4 = VIEWER_MUX_OUT[19:16];
assign VIEWER_MUX_OUT3 = VIEWER_MUX_OUT[15:12];
assign VIEWER_MUX_OUT2 = VIEWER_MUX_OUT[11:8];
assign VIEWER_MUX_OUT1 = VIEWER_MUX_OUT[7:4];
assign VIEWER_MUX_OUT0 = VIEWER_MUX_OUT[3:0];
Decoder_Binary2HexSevenSegments B2H7S0(
.out(HEX0),
.in(VIEWER_MUX_OUT0)
);
Decoder_Binary2HexSevenSegments B2H7S1(
.out(HEX1),
.in(VIEWER_MUX_OUT1)
);
Decoder_Binary2HexSevenSegments B2H7S2(
.out(HEX2),
.in(VIEWER_MUX_OUT2)
);
Decoder_Binary2HexSevenSegments B2H7S3(
.out(HEX3),
.in(VIEWER_MUX_OUT3)
);
Decoder_Binary2HexSevenSegments B2H7S4(
.out(HEX4),
.in(VIEWER_MUX_OUT4)
);
/*
initial begin
CLK_key <= 0;
RST_key <= 1;
repeat (50) begin
#(5) CLK_key <= !CLK_key;
end
end
initial begin
#100 $finish;
end
*/
always@(SW[2:0], DATA_in_bus, D_bus_internal, ADDR_bus, DATA_bus, CNTRL_bus, PC_out, INSTRM_out) begin
case(SW[2:0])
3'b000: VIEWER_MUX_OUT = DATA_in_bus;
3'b001: VIEWER_MUX_OUT = D_bus_internal;
3'b010: VIEWER_MUX_OUT = ADDR_bus;
3'b011: VIEWER_MUX_OUT = DATA_bus;
3'b100: VIEWER_MUX_OUT = CNTRL_bus;
3'b101: VIEWER_MUX_OUT = PC_out;
3'b110: VIEWER_MUX_OUT = INSTRM_out;
//3'b111: VIEWER_MUX_OUT = INSTRM_out;
default: VIEWER_MUX_OUT = D_bus_internal;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; vector<vector<int>> v(200001, vector<int>(32)); for (int i = 0; i < 2e5 + 1; i++) { for (int j = 0; j < 32; j++) { if (i & (1 << j)) v[i][j] = 1; } } for (int i = 1; i < 2e5 + 1; i++) { for (int j = 0; j < 32; j++) { v[i][j] += v[i - 1][j]; } } while (t--) { int l, r; cin >> l >> r; int ans = 1e9; for (int i = 0; i < 32; i++) { if ((1 << i) <= r) { ans = min(ans, r - v[r][i] - l + 1 + v[l - 1][i]); } } cout << ans << endl; } return 0; }
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_tck the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_instance_index = 0,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_ir_width = 2,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_mfg_id = 110,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_sim_action = "",
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_sim_n_scan = 0,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_sim_total_length = 0,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_type_id = 135,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 150001; int t[MAX_N]; int main() { int n, k, q; cin >> n >> k >> q; for (int i = 0; i < n; ++i) { cin >> t[i]; } set<int> s; for (int i = 0; i < q; ++i) { int x, y; cin >> x >> y; if (x == 1) { s.insert(-t[y - 1]); if (s.size() > k) { auto it = s.begin(); for (int j = 0; j < k; ++j) it++; s.erase(it); } } else { cout << (s.find(-t[y - 1]) == s.end() ? NO : YES ) << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, k, a[100100], sum = 0, Min = 1e6; int main() { cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { if (a[i] < 0 && k) a[i] *= -1, k--; Min = min(Min, abs(a[i])); sum += a[i]; } if (k & 1) sum -= Min * 2; cout << sum; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MOD = 998244353, N = 1e6 + 5; long long fact[N], d[N]; long long f(int x) { if (x == 0) return 1; if (fact[x] != 0) return fact[x]; return fact[x] = (x * f(x - 1)) % MOD; } int main() { d[1] = 1; for (int i = 2; i < N; i++) { d[i] = (1ll * i * (f(i - 1) - 1 + d[i - 1])) % MOD; } int n; cin >> n; cout << d[n]; return 0; }
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#include <bits/stdc++.h> using namespace std; int N, R; int result = INT_MAX; char opt[] = TB ; int turns; int sLast; char rChar[1000001]; int main() { int x, y; cin >> N >> R; if (N == 1 && R == 1) { cout << 0 << endl << T << endl; return 0; } for (int i = 1; i < R; i++) { x = i; y = R; int *smaller, *larger; int mistakes = 0; int times = 0; int turn_over = 0; while (x > 0 && y > 0) { if (x > y) { larger = &x; smaller = &y; } else { larger = &y; smaller = &x; } mistakes += *larger / *smaller - 1; times += *larger / *smaller; turn_over++; *larger %= *smaller; } if (x + y == 1 && times == N) { mistakes--; turn_over++; if (mistakes < result) { result = mistakes; sLast = i; turns = turn_over; } } } if (result == INT_MAX) { cout << IMPOSSIBLE << endl; } else { cout << result << endl; if (turns & 1) { x = R; y = sLast; } else { x = sLast; y = R; } for (int i = N - 1; i > 0; i--) { if (x > y) { rChar[i] = T ; x -= y; } else { rChar[i] = B ; y -= x; } } rChar[0] = T ; cout << rChar << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long int N = 1e6 + 5; const long long int INF = 1e18; const long long int MOD = 1e9 + 7; int a[N], has[N], hol[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long int n, m, k, u, v; cin >> n >> m >> k; a[1] = 1; long long int last; for (long long int i = 1; i <= m; i++) { cin >> hol[i]; has[hol[i]] = 1; } for (long long int i = 1; i <= k; i++) { cin >> u >> v; if (has[u] && a[u]) { cout << u << endl; exit(0); } if (has[v] && a[v]) { cout << v << endl; exit(0); } swap(a[u], a[v]); if (has[u] && a[u]) { cout << u << endl; exit(0); } if (has[v] && a[v]) { cout << v << endl; exit(0); } } for (long long int i = 1; i <= n; i++) { if (a[i]) { cout << i << endl; exit(0); } } }
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#include <bits/stdc++.h> using namespace std; const int N = 10000; const int M = 1000000; const int inf = 1e9; struct Edge { int v, w, cost, next; } g[M]; int head[N], st, ed, flow, cost, cnt; void init() { memset(head, -1, sizeof(head)); flow = cost = cnt = 0; } void addEdge(int u, int v, int w, int cost) { g[cnt].v = v, g[cnt].w = w, g[cnt].cost = cost, g[cnt].next = head[u], head[u] = cnt++; g[cnt].v = u, g[cnt].w = 0, g[cnt].cost = -cost, g[cnt].next = head[v], head[v] = cnt++; } bool spfaFlow(int n) { vector<int> dis(n + 1, inf); vector<bool> vis(n + 1, false); vector<int> path(n + 1, -1); dis[st] = 0; vis[st] = true; queue<int> q; q.push(st); while (!q.empty()) { int u = q.front(); q.pop(); vis[u] = false; for (int i = head[u]; ~i; i = g[i].next) { int v = g[i].v; if (g[i].w && dis[v] > dis[u] + g[i].cost) { dis[v] = dis[u] + g[i].cost; path[v] = i; if (!vis[v]) { vis[v] = true; q.push(v); } } } } int mxflow = inf; if (path[ed] != -1) { for (int u = ed; u != st; u = g[path[u] ^ 1].v) { mxflow = min(mxflow, g[path[u]].w); } flow += mxflow; for (int u = ed; u != st; u = g[path[u] ^ 1].v) { g[path[u]].w -= mxflow; g[path[u] ^ 1].w += mxflow; cost += mxflow * g[path[u]].cost; } } return path[ed] != -1; } int minCost(int n) { while (spfaFlow(n)) ; return cost; } int main(int argc, char *argv[]) { int n; cin >> n; string s; cin >> s; vector<int> b(n + 1); for (int i = 1; i <= n; i++) { cin >> b[i]; } int N = 26 + n * 26 + (n / 2) * 26 + (n / 2); st = N + 1, ed = N + 2; init(); vector<int> cnt(255); for (auto c : s) { cnt[c]++; } int Z = n * 26 + (n / 2) * 27; for (int i = a ; i <= z ; i++) { addEdge(st, Z + i - a + 1, cnt[i], 0); for (int j = 1; j <= n; j++) { addEdge(Z + i - a + 1, (i - a ) * n + j, 1, i == s[j - 1] ? -b[j] : 0); } } for (int i = 0; i < 26; i++) { for (int j = 1; j <= n / 2; j++) { int ux = i * n + j, uy = i * n + n + 1 - j; addEdge(ux, n * 26 + (n / 2) * i + j, 1, 0); addEdge(uy, n * 26 + (n / 2) * i + j, 1, 0); addEdge(n * 26 + (n / 2) * i + j, n * 26 + (n / 2) * 26 + j, 1, 0); } } for (int j = 1; j <= n / 2; j++) { addEdge(n * 26 + (n / 2) * 26 + j, ed, 2, 0); } cout << -minCost(N + 2) << endl; return 0; }
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#include <bits/stdc++.h> #pragma GCC target( pclmul ) using ul = std::uint32_t; using ull = std::uint64_t; using li = std::int32_t; using ll = std::int64_t; using llf = long double; using uss = std::uint8_t; const ul tau = 15; const ul fib[] = { 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233, 377, 610, 987, 1597, 2584, 4181, 6765, 10946, 17711, 28657, 46368, 75025, 121393, 196418, 317811, 514229, 832040, 1346269, 2178309, 3524578, 5702887, 9227465, 14930352, 24157817, 39088169, 63245986}; const ul sz = fib[tau]; char f[tau + 1][sz + 1]; ul ord[sz + sz]; class sam_t { public: ul las; class node { public: ul ch[2]; ul len = 0; ul fa = 0; ul cnt = 0; node() { std::memset(ch, 0, sizeof(ch)); } }; std::vector<node> st = std::vector<node>(sz + sz); void add(ul c) { ul p = las; ul np = las = st.size(); st.push_back(node()); st[np].len = st[p].len + 1; for (; p && !st[p].ch[c]; p = st[p].fa) { st[p].ch[c] = np; } if (!p) { st[np].fa = 1; } else { ul q = st[p].ch[c]; if (st[q].len == st[p].len + 1) { st[np].fa = q; } else { ul nq = st.size(); st.push_back(node()); st[nq] = st[q]; st[nq].cnt = 0; st[nq].len = st[p].len + 1; st[q].fa = st[np].fa = nq; for (; p && st[p].ch[c] == q; p = st[p].fa) { st[p].ch[c] = nq; } } } } void init() { las = 1; st.resize(0); st.resize(2); } }; sam_t sams[tau + 1]; ul n, m; ull k; const ul maxn = 200; ull lambda[maxn + 1][4]; const ul maxm = 200; ul tim = 0; char ans[maxm + 2]; ul currs[4]; ul nexts0[4]; ul nexts1[4]; ull getnum(ul st[4]) { ull ret = 0; for (ul i = 0; i != 4; ++i) { ret += lambda[n][i] * sams[tau - i].st[st[i]].cnt; } return ret; } int main() { f[0][1] = 0 ; f[1][1] = 1 ; std::scanf( %u%llu%u , &n, &k, &m); for (ul x = 2; x <= std::min(n, tau); ++x) { std::memcpy(f[x] + 1, f[x - 2] + 1, fib[x - 2]); std::memcpy(f[x] + fib[x - 2] + 1, f[x - 1] + 1, fib[x - 1]); } if (n <= tau) { sams[n].init(); for (ul i = 1; i <= fib[n]; ++i) { sams[n].add(f[n][i] - 0 ); ++sams[n].st[sams[n].las].cnt; } for (ul i = 1; i != sams[n].st.size(); ++i) { ord[i] = i; } std::sort(ord + 1, ord + sams[n].st.size(), [&](ul a, ul b) { return sams[n].st[a].len < sams[n].st[b].len; }); for (ul it = sams[n].st.size() - 1; it >= 2; --it) { ul i = ord[it]; sams[n].st[sams[n].st[i].fa].cnt += sams[n].st[i].cnt; } ul curr = 1; ull cc = sams[n].st[1].cnt; while (tim < m) { ul next0 = sams[n].st[curr].ch[0]; ul next1 = sams[n].st[curr].ch[1]; ull cn0 = sams[n].st[next0].cnt; ull cn1 = sams[n].st[next1].cnt; if (cc - cn0 - cn1 >= k) { break; } else { k -= cc - cn0 - cn1; } if (cn0 >= k) { ++tim; ans[tim] = 0 ; curr = next0; cc = cn0; } else { ++tim; ans[tim] = 1 ; curr = next1; k -= cn0; cc = cn1; } } std::printf(ans + 1); std::putchar( n ); } else { for (ul x = tau - 3; x <= tau; ++x) { sams[x].init(); for (ul i = 1; i <= fib[x]; ++i) { sams[x].add(f[x][i] - 0 ); ++sams[x].st[sams[x].las].cnt; } for (ul i = 1; i != sams[x].st.size(); ++i) { ord[i] = i; } std::sort(ord + 1, ord + sams[x].st.size(), [&](ul a, ul b) { return sams[x].st[a].len < sams[x].st[b].len; }); for (ul it = sams[x].st.size() - 1; it >= 2; --it) { ul i = ord[it]; sams[x].st[sams[x].st[i].fa].cnt += sams[x].st[i].cnt; } lambda[x][tau - x] = 1; } for (ul x = tau + 1; x <= n; ++x) { for (ul i = 0; i != 4; ++i) { lambda[x][i] = lambda[x - 1][i] + lambda[x - 2][i] + lambda[x - 2][i] - lambda[x - 3][i] - lambda[x - 4][i]; } } for (ul i = 0; i != 4; ++i) { currs[i] = 1; } ull cc = getnum(currs); while (tim < m) { for (ul i = 0; i != 4; ++i) { nexts0[i] = sams[tau - i].st[currs[i]].ch[0]; nexts1[i] = sams[tau - i].st[currs[i]].ch[1]; } ull cn0 = getnum(nexts0); ull cn1 = getnum(nexts1); if (cc - cn0 - cn1 >= k) { break; } else { k -= cc - cn0 - cn1; } if (cn0 >= k) { ++tim; ans[tim] = 0 ; std::memcpy(currs, nexts0, sizeof(currs)); cc = cn0; } else { ++tim; ans[tim] = 1 ; std::memcpy(currs, nexts1, sizeof(currs)); k -= cn0; cc = cn1; } } std::printf(ans + 1); std::putchar( n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<vector<int> > v(200002); bool ab[200002]; int dist[200002]; queue<int> q; int cur, i, n, h[200002], r[200002], p[200002]; void dfs() { while (!q.empty()) { cur = q.front(); q.pop(); ab[cur] = true; for (i = 0; i < v[cur].size(); i++) if (ab[v[cur][i]] == false) { ab[v[cur][i]] = true; q.push(v[cur][i]); dist[v[cur][i]] = dist[cur] + 1; } } } int a, b; int main() { cin >> n; pair<int, int> fg[n]; for (i = 1; i < n; i++) { cin >> a >> b; fg[i] = make_pair(a, b); v[a].push_back(b); v[b].push_back(a); } q.push(1); ab[1] = true; dfs(); for (i = 1; i < n; i++) { if (dist[fg[i].first] < dist[fg[i].second]) p[fg[i].second] = fg[i].first; else p[fg[i].first] = fg[i].second; } for (i = 0; i < n; i++) { cin >> h[i]; r[h[i]] = i + 1; } for (i = 1; i < n; i++) if ((r[p[h[i]]] < r[p[h[i - 1]]]) || (dist[h[i]] < dist[h[i - 1]])) { cout << NO ; return 0; } cout << YES ; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; int a, b, k, v; bool check(int x) { return min(x * k, (x + b)) * v >= a ? true : false; } int main() { scanf( %d%d%d%d , &k, &a, &b, &v); for (int i = 1; i <= 1000; i++) { if (check(i)) { printf( %d n , i); return 0; } } }
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#include <bits/stdc++.h> using namespace std; long long n, v[500005], lastLeft[500005], lastRight[500005], solLeft[500005], solRight[500005], sol[500005]; int main() { cin >> n; for (int i = 1; i <= n; ++i) { cin >> v[i]; } for (int i = 1; i <= n; ++i) { lastLeft[i] = 0; } for (int i = n; i >= 1; --i) { lastRight[i] = n + 1; } stack<pair<long long, long long> > st1; st1.push({1, v[1]}); for (int i = 2; i <= n; ++i) { while (!st1.empty() && v[i] <= st1.top().second) st1.pop(); if (!st1.empty()) lastLeft[i] = st1.top().first; st1.push({i, v[i]}); } stack<pair<long long, long long> > st2; st2.push({n, v[n]}); for (int i = n - 1; i >= 1; --i) { while (!st2.empty() && v[i] <= st2.top().second) st2.pop(); if (!st2.empty()) lastRight[i] = st2.top().first; st2.push({i, v[i]}); } long long big = 0; for (int varf = 1; varf <= n; ++varf) { solLeft[varf] = solLeft[lastLeft[varf]] + abs(lastLeft[varf] - varf) * v[varf]; } for (int varf = n; varf >= 1; --varf) { solRight[varf] = solRight[lastRight[varf]] + abs(lastRight[varf] - varf) * v[varf]; } for (int varf = 1; varf <= n; ++varf) { if (solLeft[varf] + solRight[varf] - v[varf] > big) big = solLeft[varf] + solRight[varf] - v[varf]; } for (int varf = 1; varf <= n; ++varf) { if (solLeft[varf] + solRight[varf] - v[varf] == big) { sol[varf] = v[varf]; for (int i = varf - 1; i >= 1; --i) { sol[i] = min(sol[i + 1], v[i]); } for (int i = varf + 1; i <= n; ++i) { sol[i] = min(sol[i - 1], v[i]); } for (int i = 1; i <= n; ++i) cout << sol[i] << ; return 0; } } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__EINVP_PP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_PP_SYMBOL_V
|
// USED ONLY TO SELECT PL BLOCKED STATUS
// OPTIMISE FOR XY ROUTING
/* autovdoc@
*
* component@ unary_select_pair
* what@ A sort of mux!
* authors@ Robert Mullins
* date@ 5.3.04
* revised@ 5.3.04
* description@
*
* Takes two unary (one-hot) encoded select signals and selects one bit of the input.
*
* Implements the following:
*
* {\tt selectedbit=datain[binary(sela)*WB+binary(selb)]}
*
* pin@ sel_a, WA, in, select signal A (unary encoded)
* pin@ sel_b, WB, in, select signal B (unary encoded)
* pin@ data_in, WA*WB, in, input data
* pin@ selected_bit, 1, out, selected data bit (see above)
*
* param@ WA, >1, width of select signal A
* param@ WB, >1, width of select signal B
*
* autovdoc@
*/
module unary_select_pair (sel_a, sel_b, data_in, selected_bit);
parameter input_port = 0; // from 'input_port' to 'sel_a' output port
parameter WA = 4;
parameter WB = 4;
input [WA-1:0] sel_a;
input [WB-1:0] sel_b;
input [WA*WB-1:0] data_in;
output selected_bit;
genvar i,j;
wire [WA*WB-1:0] selected;
generate
for (i=0; i<WA; i=i+1) begin:ol
for (j=0; j<WB; j=j+1) begin:il
assign selected[i*WB+j] = (LAG_route_valid_turn(input_port, i)) ?
data_in[i*WB+j] & sel_a[i] & sel_b[j] : 1'b0;
/*
// i = output_port
// assume XY routing and that data never leaves on port it entered
if ((input_port==i) || (((input_port==`NORTH)||(input_port==`SOUTH)) &&
((i==`EAST)||(i==`WEST)))) begin
assign selected[i*WB+j]=1'b0;
end else begin
assign selected[i*WB+j]=data_in[i*WB+j] & sel_a[i] & sel_b[j];
end
*/
end
end
endgenerate
assign selected_bit=|selected;
endmodule // unary_select_pair
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; int ans = 1e9; for (int i = 1; i * i <= n; i++) { ans = min(ans, i - 1 + (n - i + i - 1) / i); } cout << ans << n ; } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41O_SYMBOL_V
`define SKY130_FD_SC_HD__A41O_SYMBOL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, t; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> t; while (t--) { cin >> n; if (n <= 2) { cout << 0 << endl; continue; } else { int x; x = n / 2; if (n % 2 == 0) x--; cout << x << endl; } } }
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#include <bits/stdc++.h> using namespace std; template <typename T> T Abs(T first) { return (first < 0 ? -first : first); } template <typename T> T Sqr(T first) { return (first * first); } string plural(string s) { return (int((s).size()) && s[int((s).size()) - 1] == x ? s + en : s + s ); } const int INF = (int)1e9; const long double EPS = 1e-12; const long double PI = acos(-1.0); bool Read(int &first) { char c, r = 0, n = 0; first = 0; for (;;) { c = getchar(); if ((c < 0) && (!r)) return (0); if ((c == - ) && (!r)) n = 1; else if ((c >= 0 ) && (c <= 9 )) first = first * 10 + c - 0 , r = 1; else if (r) break; } if (n) first = -first; return (1); } bool ReadLL(long long &first) { char c, r = 0, n = 0; first = 0; for (;;) { c = getchar(); if ((c < 0) && (!r)) return (0); if ((c == - ) && (!r)) n = 1; else if ((c >= 0 ) && (c <= 9 )) first = first * 10 + c - 0 , r = 1; else if (r) break; } if (n) first = -first; return (1); } long long A[200005], X[200005], B[200005]; int C[200005]; int ord[200005], cor[200005]; int main() { if (0) freopen( in.txt , r , stdin); int N, M; long long K; int i, j, k, a, b, c, first, second, z, m; long long v; Read(N), ReadLL(K); for (i = 0; i < N; i++) ReadLL(A[i]); memset(C, 0, sizeof(C)); for (i = 0; i < N; i++) { ReadLL(X[i]), X[i]--; C[X[i]]++; } for (i = 0; i < N; i++) if (i && X[i] < X[i - 1]) goto Imp; if (X[N - 1] != N - 1) goto Imp; j = k = 0; for (i = 0; i < N; i++) { k += C[i]; if (k > i + 1) goto Imp; if (k == i + 1) { for (a = j; a <= i; a++) if (X[a] != i) goto Imp; if (j && B[j - 1] >= A[j] + K) goto Imp; for (a = j; a <= i - 1; a++) B[a] = A[a + 1] + K; if (i == j) B[i] = A[i] + K; else B[i] = B[i - 1] + 1; j = i + 1; } } if (0) { memset(cor, -1, sizeof(cor)); for (i = 0; i < N; i++) ord[i] = i; do { for (i = 0; i < N; i++) if (B[ord[i]] < A[i] + K) goto Bad; for (i = 0; i < N; i++) cor[i] = max(cor[i], ord[i]); Bad:; } while (next_permutation(ord, ord + N)); for (i = 0; i < N; i++) if (X[i] != cor[i]) break; if (i == N) { } else { printf( WRONG n ); } } printf( Yes n ); for (i = 0; i < N; i++) { if (i) printf( ); cout << B[i]; } printf( n ); return (0); Imp:; printf( No n ); return (0); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CONB_PP_SYMBOL_V
`define SKY130_FD_SC_HD__CONB_PP_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__conb (
//# {{data|Data Signals}}
output HI ,
output LO ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CONB_PP_SYMBOL_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.2 Build 209 09/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom (
address,
clock,
q);
parameter init_file = ""; //PG
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
parameter ram_type = "AUTO"; // M10K MLAB AUTO
input [13:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = init_file,
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = lpm_hint,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 14,
altsyncram_component.width_a = 8,
altsyncram_component.ram_block_type = ram_type,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "rom/rom.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "rom/rom.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> const int MAXN = 2e5 + 7; struct Edge { int t, next; } edge[MAXN << 1]; int head[MAXN], cnt; int size[MAXN]; int dfn[MAXN], pos[MAXN], ts = 0; int n, m; int dist[MAXN], deep[MAXN]; int f[MAXN][19]; int t1 = 1, t2 = 1; struct SegmentTree; struct Questions; SegmentTree *newNode(int, int, SegmentTree *, SegmentTree *); struct SegmentTree { int l, r, mid; SegmentTree *lc, *rc; int val, add, max; static SegmentTree *build(int l, int r) { SegmentTree *ret = NULL; if (l == r) { ret = newNode(l, r, NULL, NULL); ret->val = ret->max = dist[pos[l]]; return ret; } else { int mid = l + (r - l) / 2; ret = newNode(l, r, build(l, mid), build(mid + 1, r)); ret->pushUp(); return ret; } } void pushUp() { max = std::max(lc->max, rc->max); } void pushDown() { if (add) { lc->plus(add), rc->plus(add); add = 0; } } void plus(int a) { if (l == r) val += a; add += a; max += a; } void solveAdd(int left, int right, int delta) { if (l == left && r == right) return plus(delta); pushDown(); if (right <= mid) lc->solveAdd(left, right, delta); else if (left > mid) rc->solveAdd(left, right, delta); else lc->solveAdd(left, mid, delta), rc->solveAdd(mid + 1, right, delta); pushUp(); } int queryMax(int left, int right) { if (l == left && r == right) return max; pushDown(); if (right <= mid) return lc->queryMax(left, right); else if (left > mid) return rc->queryMax(left, right); else return std::max(lc->queryMax(left, mid), rc->queryMax(mid + 1, right)); } } * root, pool[MAXN], *tail = pool; SegmentTree *newNode(int l, int r, SegmentTree *lc, SegmentTree *rc) { SegmentTree *ret = ++tail; ret->l = l, ret->r = r, ret->mid = l + (r - l) / 2; ret->lc = lc, ret->rc = rc; ret->val = 0, ret->add = 0, ret->max = INT_MIN; return ret; } struct Questions { int u, v, mid; } q[MAXN]; struct Ans { int r, node, pos, ans; } a1[MAXN], a2[MAXN]; std::vector<Ans> v1[MAXN], v2[MAXN]; void add(int u, int v) { cnt++; edge[cnt].t = v; edge[cnt].next = head[u]; head[u] = cnt; } void dfs1(int u, int pre) { f[u][0] = pre; dfn[u] = ++ts; size[u] = 1; pos[ts] = u; for (int e = head[u]; e; e = edge[e].next) { int v = edge[e].t; if (v == pre) continue; dist[v] = dist[u] + 1; deep[v] = deep[u] + 1; dfs1(v, u); size[u] += size[v]; } } int getLca(int x, int y) { if (deep[x] > deep[y]) std::swap(x, y); for (int i = 18; i >= 0; i--) { if (deep[f[y][i]] >= deep[x]) y = f[y][i]; } if (x == y) return x; for (int i = 18; i >= 0; i--) { if (f[x][i] != f[y][i]) { x = f[x][i]; y = f[y][i]; } } return f[x][0]; } int getMid(int u, int len) { int e = 0; while (len) { if (len & 1) u = f[u][e]; len >>= 1; e++; } return u; } void dfs2(int u, int pre) { while (a1[t1].r == u && t1 <= m) { a1[t1].ans = root->queryMax(dfn[a1[t1].node], dfn[a1[t1].node] + size[a1[t1].node] - 1); t1++; } while (a2[t2].r == u && t2 <= m) { if (dfn[a2[t2].node] > 1) a2[t2].ans = std::max(a2[t2].ans, root->queryMax(1, dfn[a2[t2].node] - 1)); if (dfn[a2[t2].node] + size[a2[t2].node] - 1 < n) a2[t2].ans = std::max( a2[t2].ans, root->queryMax(dfn[a2[t2].node] + size[a2[t2].node], n)); t2++; } for (int e = head[u]; e; e = edge[e].next) { int v = edge[e].t; if (v == pre) continue; root->solveAdd(dfn[v], dfn[v] + size[v] - 1, -1); if (dfn[v] > 1) root->solveAdd(1, dfn[v] - 1, 1); if (dfn[v] + size[v] - 1 < n) root->solveAdd(dfn[v] + size[v], n, 1); dfs2(v, u); root->solveAdd(dfn[v], dfn[v] + size[v] - 1, 1); if (dfn[v] > 1) root->solveAdd(1, dfn[v] - 1, -1); if (dfn[v] + size[v] - 1 < n) root->solveAdd(dfn[v] + size[v], n, -1); } } bool cmp1(Ans x, Ans y) { if (dfn[x.r] == dfn[y.r]) return dfn[x.node] < dfn[y.node]; return dfn[x.r] < dfn[y.r]; } bool cmp2(Ans x, Ans y) { return x.pos < y.pos; } int main(int argc, char *argv[]) { scanf( %d , &n); int u, v; for (int i = 1; i <= n - 1; i++) { scanf( %d %d , &u, &v); add(u, v); add(v, u); } deep[1] = 1; dfs1(1, 0); root = SegmentTree::build(1, n); for (int j = 1; j <= 18; j++) { for (int i = 1; i <= n; i++) { f[i][j] = f[f[i][j - 1]][j - 1]; } } int lca, len, mid; scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d %d , &u, &v); lca = getLca(u, v); len = dist[u] + dist[v] - 2 * dist[lca]; if (deep[u] < deep[v]) std::swap(u, v); mid = getMid(u, (len - 1) / 2); q[i] = Questions{u, v, mid}; a1[i] = Ans{u, mid, i, INT_MIN}; a2[i] = Ans{v, mid, i, INT_MIN}; } std::sort(a1 + 1, a1 + m + 1, cmp1); std::sort(a2 + 1, a2 + m + 1, cmp1); dfs2(1, 0); std::sort(a1 + 1, a1 + m + 1, cmp2); std::sort(a2 + 1, a2 + m + 1, cmp2); for (int i = 1; i <= m; i++) { printf( %d n , std::max(a1[i].ans, a2[i].ans)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); long long n; cin >> n; vector<vector<long long> > p(2, vector<long long>(n)), suf(2, vector<long long>(n + 1)), ebalVLevo(2, vector<long long>(n + 1)), ebalVPravo(2, vector<long long>(n + 1)); for (long long i = 0; i < 2; i++) { for (long long j = 0; j < n; j++) { cin >> p[i][j]; } } for (long long i = 0; i < 2; i++) { suf[i][n - 1] = p[i][n - 1]; for (long long j = n - 2; j >= 0; j--) { suf[i][j] = suf[i][j + 1] + p[i][j]; } } for (long long i = 0; i < 2; i++) { ebalVPravo[i][0] = (n)*p[i][0]; for (long long j = 1; j < n; j++) { ebalVPravo[i][j] = ebalVPravo[i][j - 1] + p[i][j] * (n + j); } } for (long long i = 0; i < 2; i++) { ebalVLevo[i][n - 1] = p[i][n - 1]; for (long long j = n - 2; j >= 0; j--) { ebalVLevo[i][j] = ebalVLevo[i][j + 1] + p[i][j] * (n - j); } } long long sum = 0; long long ans = 0; long long i = 0, j = 0; bool lastI = false; for (long long t = 0; t < 2 * n; t++) { sum += t * p[i][j]; long long tmp = sum; long long tmpR = ebalVPravo[i][n - 1] - ebalVPravo[i][j] - (n - t + j) * suf[i][j + 1]; long long tmpL = 0; long long tmpLL = 0; if (t == 0) { tmpL = ebalVLevo[1][j] + (t + (n - j) - 1) * suf[1][j]; } else if (i == 0) { tmpL = ebalVLevo[1][j + 1] + (t + (n - j) - 1) * suf[1][j + 1]; } else if (i == 1) { tmpL = ebalVLevo[0][j + 1] + (t + (n - j) - 1) * suf[0][j + 1]; } ans = max(ans, tmp + tmpL + tmpR); if (!lastI) { if (!i) { i++; } else { i--; } lastI = true; } else { j++; lastI = false; } } cout << ans; return 0; }
|
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