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`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.reinterpret-f64.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.reinterpret-f64_tb.vcd");
$dumpvars(0, cpu_tb);
if(HAS_FPU && USE_64B) begin
#30
`assert(result, 64'hc000000000000000);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else if(HAS_FPU) begin
#12
`assert(trap, `NO_64B);
end
else begin
#12
`assert(trap, `NO_FPU);
end
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long i; long long n, m, k, l; cin >> n >> m >> k >> l; long long no = 0; long long yes = 0; long long j = (l + k); long long ans = ((j - 1) / m) + 1; if (((ans * m)) > n) no = 1; if (no) cout << -1 ; else cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; vector<vector<int>> g(n); for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; --x; --y; g[x].push_back(y); g[y].push_back(x); } vector<bool> alive(n, true); vector<int> sz(n); vector<int> pv(n); vector<pair<int, int>> ret; vector<int> all; vector<int> tin(n); vector<int> tout(n); int T = -1; function<void(int)> Dfs = [&](int v) { all.push_back(v); tin[v] = ++T; sz[v] = 1; for (int u : g[v]) { if (alive[u] && u != pv[v]) { pv[u] = v; Dfs(u); sz[v] += sz[u]; } } tout[v] = ++T; }; function<void(int)> Solve = [&](int v) { all.clear(); pv[v] = -1; Dfs(v); int total = sz[v]; while (true) { bool found = false; for (int u : g[v]) { if (alive[u] && pv[u] == v && 2 * sz[u] >= total) { v = u; found = true; break; } } if (!found) { break; } } alive[v] = false; set<int> best; for (int u : g[v]) { if (alive[u]) { all.clear(); pv[u] = -1; Dfs(u); set<int> cur; for (int w : g[u]) { if (alive[w]) { cur.insert(w); } } if (cur.size() > best.size()) { best = cur; } } } all.clear(); pv[v] = -1; Dfs(v); for (int u : all) { if (u != v && pv[u] != v && best.find(u) == best.end()) { ret.emplace_back(u, v); } } vector<int> children; for (int u : g[v]) { if (alive[u]) { children.push_back(u); } } for (int u : children) { Solve(u); } }; Solve(0); assert((int)ret.size() <= 10 * n); cout << ret.size() << n ; for (auto& p : ret) { cout << p.first + 1 << << p.second + 1 << n ; } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; int n, m, jm; long long ans; int main() { cin >> n >> m >> jm; ans = ceil(1.0 * n / jm) * ceil(1.0 * m / jm) * ((n - 1) % jm + 1) * ((m - 1) % jm + 1); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int d[n]; int total = 0; for (int i = 0; i < n; i++) { cin >> d[i]; total += d[i]; } int s, t; cin >> s >> t; if (s == t) { cout << 0; return 0; } if (s > t) swap(s, t); int ans = 0; for (int i = s; i < t; i++) { ans += d[i - 1]; } cout << min(ans, total - ans); }
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description: For those situations where you need to attach one PPFIFO with another
*
* Changes:
*/
module adapter_ppfifo_2_ppfifo #(
parameter DATA_WIDTH = 32
)(
input clk,
input rst,
input i_read_ready,
output reg o_read_activate,
input [23:0] i_read_size,
input [DATA_WIDTH - 1:0] i_read_data,
output reg o_read_stb,
input [1:0] i_write_ready,
output reg [1:0] o_write_activate,
input [23:0] i_write_size,
output reg o_write_stb,
output [DATA_WIDTH - 1:0] o_write_data
);
//registes/wires
reg [23:0] read_count;
reg [23:0] write_count;
assign o_write_data = i_read_data;
always @ (posedge clk) begin
o_read_stb <= 0;
o_write_stb <= 0;
if (rst) begin
o_write_activate <= 0;
o_read_activate <= 0;
write_count <= 0;
read_count <= 0;
end
else begin
if (i_read_ready && !o_read_activate) begin
read_count <= 0;
o_read_activate <= 1;
end
if ((i_write_ready > 0) && (o_write_activate == 0)) begin
write_count <= 0;
if (i_write_ready[0]) begin
o_write_activate[0] <= 1;
end
else begin
o_write_activate[1] <= 1;
end
end
//Both FIFOs are available
if (o_read_activate && (o_write_activate > 0)) begin
if ((write_count < i_write_size) && (read_count < i_read_size))begin
o_write_stb <= 1;
o_read_stb <= 1;
write_count <= write_count + 1;
read_count <= read_count + 1;
end
else begin
if (write_count >= i_write_size) begin
o_write_activate <= 0;
end
if (read_count >= i_read_size) begin
//Both FIFOs should be released, this way the output is never blocked on the input
o_read_activate <= 0;
o_write_activate <= 0;
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> int const maxn = 255; int const mod = 1e9 + 7; long long a[maxn]; long long c[maxn][maxn]; long long pow(long long a, long long b, long long p) { long long r = 1; while (b) { if (b & 1) r = (r * a) % p; a = (a * a) % p; b >>= 1; } return r; } int main() { int n, k, i, j; for (i = 0; i < maxn; i++) { c[i][0] = c[i][i] = 1; for (j = 1; j < i; j++) c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % mod; } scanf( %d%d , &n, &k); for (i = 1; i <= n; i++) a[i] = pow(pow(k, i, mod) - pow(k - 1, i, mod), n, mod); long long ans = a[n]; for (i = 1; i <= n; i++) { if (i & 1) ans = (ans - ((c[n][i] * pow(k - 1, i * n, mod)) % mod * a[n - i]) % mod + mod) % mod; else ans = (ans + ((c[n][i] * pow(k - 1, i * n, mod)) % mod * a[n - i]) % mod) % mod; } printf( %lld n , ans); return 0; }
|
`timescale 1 ns / 1 ps
`include "defines.v"
`ifndef ICE
`define REGFILE_REGISTERED_OUT 1
`endif
module regfile
#(parameter [0:0] MICROOPS_ENABLED = 1)
(input clk,
input rst,
input [31:0] PC,
input [4:0] addr1,
input [4:0] addr2,
input [4:0] addrw,
`ifdef REGFILE_REGISTERED_OUT
output reg [31:0] out1,
output reg [31:0] out2,
`else
output [31:0] out1,
output [31:0] out2,
`endif
input [4:0] dbgreg,
input dbgreg_en,
input [31:0] wdata,
input we,
input [31:0] clkcounter);
reg [31:0] mem [0:31];
wire [31:0] out1_next;
wire [31:0] out2_next;
// PC+1 if microops enabled, otherwise PC+2
wire [31:0] delta1;
wire [31:0] delta2;
assign delta1 = MICROOPS_ENABLED?1:2;
`ifdef REGFILE_REGISTERED_OUT
assign delta2 = 0;
`else
assign delta2 = -1;
`endif
assign out1_next = addr1==0?0:
(addr1==1?1:
(addr1==31?(PC+(delta1+delta2)):
(addrw==addr1?wdata:mem[addr1])));
assign out2_next = addr2==0?0:
(addr2==1?1:
(addr2==31?(PC+(delta1+delta2)):
(addrw==addr2?wdata:mem[addr2])));
`ifndef REGFILE_REGISTERED_OUT
assign out1 = out1_next;
assign out2 = out2_next;
`endif
always @(posedge clk)
begin
if (we) begin
mem[addrw] <= wdata;
end
`ifdef REGFILE_REGISTERED_OUT
out1 <= out1_next;
out2 <= out2_next;
`endif
if (dbgreg_en)
$write("[R%0d=%0d]", dbgreg, mem[dbgreg]);
end
endmodule
|
//----------------------------------------------------------------------------
// RGB Block Ram - Sub Level Module
//-----------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
//----------------------------------------------------------------------------
// Filename: rgb_bram.v
//
// Description:
// -- This module is contains 3 RAMB16_S9_S18 for line storage.
// -- The RGB BRAMs hold one line of the 480 lines required for 640x480
// resolution.
// -- 1 RAMB16_S9_S18 for RED Pixels
// -- 1 RAMB16_S9_S18 GREEN Pixels
// -- 1 RAMB16_S9_S18 BLUE Pixels
// -- RED PLB TRANSFER [1,5] -> RED RAMB16_S9_S18 PORT B
// -- GREEN PLB TRANSFER [2,6] -> GREEN RAMB16_S9_S18 PORT B
// -- BLUE PLB TRANSFER [3,7] -> BLUE RAMB16_S9_S36 PORT B
// -- Data is written to the B PORTS of the BRAM by the PLB bus.
// -- Data is read from the A PORTS of the BRAM by the TFT
//
// Design Notes:
// TFT READ LOGIC
// -- BRAM_TFT_rd is generated two clock cycles early wrt DE
// -- BRAM_TFT_oe is generated one clock cycles early wrt DE
// -- These two signals control the TFT side read from BRAM to HW
// PLB WRITE LOGIC
// -- Enables and Write Enables for BRAM are controlled by the plb_if.v
// -- module. The R_en,G_en,B_en,R_we,G_we,B_we are trigger on the same
// -- clock edge. Enables for RGB BRAM may need to be adjusted for timing.
//
//
//-----------------------------------------------------------------------------
// Structure:
// -- RGB_BRAM.v
//
//-----------------------------------------------------------------------------
// Author: CJN
// History:
// CJN, MM 3/02 -- First Release
// CJN -- Second Release
// -- PLB Side Update
//
//
//
//-----------------------------------------------------------------------------
///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/ 100 ps
module rgb_bram(
tft_on_reg, // I
// BRAM_TFT READ PORT A clock and reset
tft_clk, // I
tft_rst, // I
// PLB_BRAM WRITE PORT B clock and reset
plb_clk, // I
plb_rst, // I
// BRAM_TFT READ Control
BRAM_TFT_rd, // I
BRAM_TFT_oe, // I
// PLB_BRAM Write Control
PLB_BRAM_data, // I [0:63]
PLB_BRAM_addr_en, // I
PLB_BRAM_addr_lsb, // I [0:1]
PLB_BRAM_we, // I
// RGB Outputs
R0,R1,R2,R3,R4,R5, // O
G0,G1,G2,G3,G4,G5, // O
B0,B1,B2,B3,B4,B5 // O
);
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input tft_on_reg;
input tft_clk;
input tft_rst;
input plb_clk;
input plb_rst;
input BRAM_TFT_rd;
input BRAM_TFT_oe;
input [0:63] PLB_BRAM_data;
input [0:1] PLB_BRAM_addr_lsb;
input PLB_BRAM_addr_en;
input PLB_BRAM_we;
output R0,R1,R2,R3,R4,R5;
output G0,G1,G2,G3,G4,G5;
output B0,B1,B2,B3,B4,B5;
///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////
wire [0:1] nc0,nc1,nc2,nc3,nc4,nc5;
wire [5:0] BRAM_TFT_R_data;
wire [5:0] BRAM_TFT_G_data;
wire [5:0] BRAM_TFT_B_data;
reg R0,R1,R2,R3,R4,R5;
reg G0,G1,G2,G3,G4,G5;
reg B0,B1,B2,B3,B4,B5;
reg [0:9] BRAM_TFT_addr;
reg [0:6] PLB_BRAM_addr;
reg tc;
///////////////////////////////////////////////////////////////////////////////
// READ Logic BRAM Address Generator TFT Side
///////////////////////////////////////////////////////////////////////////////
// BRAM_TFT_addr Counter (0-639d)
always @(posedge tft_clk)
begin
if (tft_rst | ~BRAM_TFT_rd) begin
BRAM_TFT_addr = 10'b0;
tc = 1'b0;
end
else begin
if (BRAM_TFT_rd & tc == 0) begin
if (BRAM_TFT_addr == 10'd639) begin
BRAM_TFT_addr = 10'b0;
tc = 1'b1;
end
else begin
BRAM_TFT_addr = BRAM_TFT_addr + 1;
tc = 1'b0;
end
end
end
end
///////////////////////////////////////////////////////////////////////////////
// WRITE Logic for the BRAM PLB Side
///////////////////////////////////////////////////////////////////////////////
// BRAM_TFT_addr Counter (0-79d)
always @(posedge plb_clk)
begin
if (plb_rst) begin
PLB_BRAM_addr = 7'b0;
end
else begin
if (PLB_BRAM_addr_en) begin
if (PLB_BRAM_addr == 7'd79) begin
PLB_BRAM_addr = 7'b0;
end
else begin
PLB_BRAM_addr = PLB_BRAM_addr + 1;
end
end
end
end
///////////////////////////////////////////////////////////////////////////////
// BRAM
///////////////////////////////////////////////////////////////////////////////
RAMB16_S18_S36 RGB_BRAM (
// TFT Side Port A
.ADDRA (BRAM_TFT_addr), // I [9:0]
.CLKA (tft_clk), // I
.DIA (16'b0), // I [15:0]
.DIPA (2'b0), // I [1:0]
.DOA ({BRAM_TFT_R_data, BRAM_TFT_G_data, BRAM_TFT_B_data[5:2]}), // O [15:0]
.DOPA (BRAM_TFT_B_data[1:0]), // O [1:0]
.ENA (BRAM_TFT_rd), // I
.SSRA (~tft_on_reg | tft_rst | ~BRAM_TFT_rd), // | ~BRAM_TFT_oe // I
.WEA (1'b0), // I
// PLB Side Port B
.ADDRB ({PLB_BRAM_addr,PLB_BRAM_addr_lsb}), // I [8:0]
.CLKB (plb_clk), // I
.DIB ({PLB_BRAM_data[40:45], PLB_BRAM_data[48:53], PLB_BRAM_data[56:59],
PLB_BRAM_data[8:13], PLB_BRAM_data[16:21], PLB_BRAM_data[24:27]}), // I [31:0]
.DIPB ({PLB_BRAM_data[60:61], PLB_BRAM_data[28:29]}), // I [3:0]
.DOB (), // O [31:0]
.DOPB (), // O [3:0]
.ENB (PLB_BRAM_we), // I
.SSRB (1'b0), // I
.WEB (PLB_BRAM_we) // I
);
///////////////////////////////////////////////////////////////////////////////
// Register RGB BRAM output data
///////////////////////////////////////////////////////////////////////////////
always @(posedge tft_clk)
if (!BRAM_TFT_oe)
begin
R0 = 1'b0;
R1 = 1'b0;
R2 = 1'b0;
R3 = 1'b0;
R4 = 1'b0;
R5 = 1'b0;
G0 = 1'b0;
G1 = 1'b0;
G2 = 1'b0;
G3 = 1'b0;
G4 = 1'b0;
G5 = 1'b0;
B0 = 1'b0;
B1 = 1'b0;
B2 = 1'b0;
B3 = 1'b0;
B4 = 1'b0;
B5 = 1'b0;
end
else
begin
R0 = BRAM_TFT_R_data[0];
R1 = BRAM_TFT_R_data[1];
R2 = BRAM_TFT_R_data[2];
R3 = BRAM_TFT_R_data[3];
R4 = BRAM_TFT_R_data[4];
R5 = BRAM_TFT_R_data[5];
G0 = BRAM_TFT_G_data[0];
G1 = BRAM_TFT_G_data[1];
G2 = BRAM_TFT_G_data[2];
G3 = BRAM_TFT_G_data[3];
G4 = BRAM_TFT_G_data[4];
G5 = BRAM_TFT_G_data[5];
B0 = BRAM_TFT_B_data[0];
B1 = BRAM_TFT_B_data[1];
B2 = BRAM_TFT_B_data[2];
B3 = BRAM_TFT_B_data[3];
B4 = BRAM_TFT_B_data[4];
B5 = BRAM_TFT_B_data[5];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int BIT = (1 << 17), M = 110, N = 25; int n, m, cnt[BIT], a[M]; long long f[BIT][N], b[N], p[N], year; void solve(int x) { memset(f, 0, sizeof(f)); f[0][0] = 1; int maxb = (1 << n); for (int i = 0; i < maxb; i++) { for (int j = 0; j <= n; j++) { int y = cnt[i] + 1; if (b[y]) { if ((a[b[y]] & i) != a[b[y]]) continue; if ((1 << (b[y] - 1) & i) == (1 << b[y] - 1)) continue; f[i | (1 << b[y] - 1)][j] += f[i][j]; } else { for (int k = 1; k <= n; k++) { if (!(i & (1 << k - 1))) { if ((a[k] & i) != a[k]) continue; if (k == x) f[i | (1 << k - 1)][y] += f[i][j]; else f[i | (1 << k - 1)][j] += f[i][j]; } } } } } } int main() { scanf( %d%lld%d , &n, &year, &m); year -= 2000; for (int i = 1; i < BIT; i++) cnt[i] = cnt[i ^ (i & (-i))] + 1; for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); a[y] |= (1 << x - 1); } for (int i = 1; i <= n; i++) { solve(i); long long sum = 0; for (int j = 1; j <= n; j++) { if (!b[j] && sum + f[(1 << n) - 1][j] >= year) { b[j] = i; p[i] = j; year -= sum; break; } sum += f[(1 << n) - 1][j]; } if (!p[i]) { puts( The times have changed ); return 0; } } for (int i = 1; i <= n; i++) printf( %lld , p[i]); puts( ); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [6:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b001};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_SYMBOL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_SYMBOL_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s25 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_SYMBOL_V
|
// DESCRIPTION: Verilator Test: Top level testbench for VCS or other fully Verilog compliant simulators
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`timescale 1 ns / 1ns
module bench;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [39:0] out_quad; // From top of top.v
wire [1:0] out_small; // From top of top.v
wire [69:0] out_wide; // From top of top.v
wire passed; // From top of top.v
// End of automatics
reg clk;
reg fastclk;
reg reset_l;
reg [1:0] in_small;
reg [39:0] in_quad;
reg [69:0] in_wide;
// Test cases
top top (/*AUTOINST*/
// Outputs
.passed (passed),
.out_small (out_small[1:0]),
.out_quad (out_quad[39:0]),
.out_wide (out_wide[69:0]),
// Inputs
.clk (clk),
.fastclk (fastclk),
.reset_l (reset_l),
.in_small (in_small[1:0]),
.in_quad (in_quad[39:0]),
.in_wide (in_wide[69:0]));
//surefire lint_off STMINI
//surefire lint_off STMFVR
//surefire lint_off DLYONE
integer fh;
// surefire lint_off CWECBB
initial begin
reset_l = 1'b1; // Want to catch negedge
fastclk = 0;
clk = 0;
forever begin
in_small = 0;
in_wide = 0;
$write("[%0t] %x %x %x %x %x\n", $time, clk, reset_l, passed, out_small, out_wide);
if (($time % 10) == 3) clk = 1'b1;
if (($time % 10) == 8) clk = 1'b0;
if ($time>10) reset_l = 1'b1;
else if ($time > 1) reset_l = 1'b0;
if ($time>60 || passed === 1'b1) begin
if (passed !== 1'b1) begin
$write("A Test failed!!!\n");
$stop;
end
else begin
$write("*-* All Finished *-*\n"); // Magic if using perl's Log::Detect
fh = $fopen("test_passed.log");
$fclose(fh);
end
$finish;
end
#1;
fastclk = !fastclk;
end
end
endmodule
// Local Variables:
// verilog-library-directories:("." "../test_v")
// compile-command: "vlint --brief -f ../test_v/input.vc bench.v"
// End:
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 5; unordered_map<long long, long long> m1, mp; long long m, k, n, s; bool check() { for (auto it : mp) { if (it.second > m1[it.first]) return false; } return true; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) { cin >> m >> k >> n >> s; long long a[m]; long long i, j; for (int i = 0; i <= m - 1; i++) { cin >> a[i]; } long long b[s]; for (int i = 0; i <= s - 1; i++) { cin >> b[i]; mp[b[i]]++; } long long del = m - n * k; long long req = del + k; for (i = 0; i < m; i += k) { m1.clear(); for (j = i; j < min(m, i + req); j++) { m1[a[j]]++; } if (check()) { cout << del << n ; for (j = i; j < min(i + req, m); j++) { if (del > 0 && m1[a[j]] > mp[a[j]]) { cout << j + 1 << ; del--; m1[a[j]]--; } } return 0; } } cout << -1 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> idb[100002]; int dp[301]; int main() { int n, m, s, e; cin >> n >> m >> s >> e; vector<int> a(n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 0; i < m; i++) { int b; scanf( %d , &b); idb[b].push_back(i); } int ans = 0; memset(dp, 127, sizeof dp); dp[0] = 0; for (int i = 0; i < n; i++) { for (int j = 300; j >= 1; j--) { int pos2array = dp[j - 1]; int nextPos = lower_bound(idb[a[i]].begin(), idb[a[i]].end(), pos2array) - idb[a[i]].begin(); if (nextPos == idb[a[i]].size()) continue; int abspos2ar = idb[a[i]][nextPos]; dp[j] = min(dp[j], abspos2ar + 1); if (i + 1 + dp[j] + j * e <= s) ans = max(ans, j); } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e6 + 5; long long n, k, a[N], res; void solo() { cin >> n; for (int i = 1; i <= n; i++) cout << i + 1 << ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; cin >> t; while (t--) { solo(); cout << endl; } cerr << n << (double)clock() / CLOCKS_PER_SEC * 1000 << ms ; }
|
module generator(clk, out1, out2, out3, out4, out5, out6,out7,out8);
input wire clk;
output wire out1,out2,out3,out4,out5,out6,out7,out8;
reg [129:0] d1_max; initial d1_max <= 130'd956;
divmod div1(.clk(clk), .max_val(d1_max[ 9: 0]), .out_clk(out1));
divmod div2(.clk(clk), .max_val(d1_max[19:10]), .out_clk(out2));
divmod div3(.clk(clk), .max_val(d1_max[29:20]), .out_clk(out3));
divmod div4(.clk(clk), .max_val(d1_max[39:30]), .out_clk(out4));
divmod div5(.clk(clk), .max_val(d1_max[49:40]), .out_clk(out5));
divmod div6(.clk(clk), .max_val(d1_max[59:50]), .out_clk(out6));
divmod div7(.clk(clk), .max_val(d1_max[69:60]), .out_clk(out7));
divmod div8(.clk(clk), .max_val(d1_max[79:70]), .out_clk(out8));
always @ (posedge clk) d1_max <= d1_max + 1'b1;
//frqdivmod #(.DIV(73)) div1(.clk(clk), .s_out(out1));
//wire reset_div5;
//reg [2:0] div5; initial div5 <= 3'd0;
//assign reset_div5 = div5[2] & !div5[1] & !div5[0];
//
//always @ (posedge clk) begin
// div5 <= (reset_div5) ? 3'd0 : div5 + 1'b1;
//end
//assign out = reset_div5;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira
//
// Create Date: 08/31/2016 03:34:58 PM
// Design Name:
// Module Name: KOA_c
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Recursive Karasuba Parameterized Algorithm
//
// Dependencies:
//
// Revision:
// Revision 0.03 - File Created
// Additional Comments: La primera version de este modulo se puede encontrar en la misma carpeta madre.
// The reason for a second version is the way the numbers with lenght lower than 8 are treated. Here, we change that
// by using an at the start before the case, so a multiplier below l = 7 is never instatiated.
//
// Revision 0.04
//
// 1. Width of KOA multipliers in the even case was fixed from the original version
// 2. Zero padding in the adders was fixed.
// 3. Changed the adder-sub description
//////////////////////////////////////////////////////////////////////////////////
module KOA_c_2
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 54, parameter precision = 1)
(
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
wire [SW/2+1:0] result_A_adder;
wire [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = (SW/2-3)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
if ((SW<=18) && (precision == 0)) begin
assign sgf_result_o = Data_A_i * Data_B_i;
end else if ((SW<=7) && (precision == 1)) begin
assign sgf_result_o = Data_A_i * Data_B_i;
end else begin
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
KOA_c_2 #(.SW(SW/2), .precision(precision) /*,.level(level1)*/) left(
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_c_2 #(.SW(SW/2), .precision(precision)/*,.level(level1)*/) right(
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.sgf_result_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
KOA_c_2 #(.SW(SW/2+1), .precision(precision)/*,.level(level1)*/) middle (
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.sgf_result_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
assign S_A[2*(SW/2)+1:0] = Q_middle[2*(SW/2)+1:0] - {zero1, Q_left};
assign S_B[2*(SW/2)+1:0] = S_A[2*(SW/2)+1:0] - {zero1, Q_right[2*(SW/2)-1:0]};
assign Result[4*(SW/2):0] = {Q_left,Q_right[2*(SW/2)-1:0]} + {leftside1,S_B[2*(SW/2)+1:0],rightside1};
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
KOA_c_2 #(.SW(SW/2), .precision(precision)/*,.level(level2)*/) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2+1]),
.Data_B_i(Data_B_i[SW-1:SW/2+1]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_c_2 #(.SW((SW/2)+1), .precision(precision)/*,.level(level2)*/) right_lower(
/// Modificacion: Tamaño de puerto cambia de SW/2+1 a SW/2+2. El compilador lo pide por alguna razon.
.Data_A_i(Data_A_i[SW/2:0]),
.Data_B_i(Data_B_i[SW/2:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//multiplication for middle
KOA_c_2 #(.SW(SW/2+2), .precision(precision)/*,.level(level2)*/) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
assign S_A = Q_middle - Q_left;
assign S_B = S_A - Q_right;
assign Result[4*(SW/2)+2:0] = {Q_left,Q_right} - {leftside2,S_B,rightside2};
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
endcase
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { return (b == 0) ? a : gcd(b, a % b); } template <typename T> T lcm(T a, T b) { return a * (b / gcd(a, b)); } template <typename T> T mod_exp(T b, T p, T m) { T x = 1; while (p) { if (p & 1) x = (x * b) % m; b = (b * b) % m; p = p >> 1; } return x; } template <typename T> T invFermat(T a, T p) { return mod_exp(a, p - 2, p); } template <typename T> T exp(T b, T p) { T x = 1; while (p) { if (p & 1) x = (x * b); b = (b * b); p = p >> 1; } return x; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; int a, b; cin >> a >> b; if (a == 0 && b == 0) { cout << NO << n ; } else if (abs(a - b) <= 1) cout << YES << n ; else cout << NO << n ; return 0; }
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: alu_add.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alu_add (
dataa,
datab,
result);
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
lpm_add_sub LPM_ADD_SUB_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.add_sub (),
.cin (),
.clken (),
.clock (),
.cout (),
.overflow ()
// synopsys translate_on
);
defparam
LPM_ADD_SUB_component.lpm_direction = "ADD",
LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
LPM_ADD_SUB_component.lpm_representation = "UNSIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
LPM_ADD_SUB_component.lpm_width = 8;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "8"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_add.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_add.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_add.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_add.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_add_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alu_add_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; int n, k; double dp[205][35][35]; vector<int> p; pair<int, int> rev(int x, int y, int rx, int ry) { if (x >= rx && x <= ry) { x = rx + (ry - rx) - (x - rx); } if (y >= rx && y <= ry) { y = rx + (ry - rx) - (y - rx); } return make_pair(x, y); } int main() { cin >> n >> k; p.resize(n); for (int i = 0; i < n; i++) { cin >> p[i]; } for (int i = 0; i < n; i++) { for (int j = i; j < n; j++) { dp[0][i][j] = 1.0; } } double pp = 2.0 / (n * (n + 1)); for (int q = 1; q <= k; q++) { for (int i = 0; i < n; i++) { for (int j = i; j < n; j++) { for (int k = 0; k < n; k++) { for (int l = k; l < n; l++) { pair<int, int> xy = rev(i, j, k, l); if (xy.first < xy.second) { dp[q][i][j] += dp[q - 1][xy.first][xy.second] * pp; } else { dp[q][i][j] += (1.0 - dp[q - 1][xy.second][xy.first]) * pp; } } } } } } double ans = 0; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (p[i] < p[j]) { ans += 1.0 - dp[k][i][j]; } else { ans += dp[k][i][j]; } } } printf( %.9lf n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0N_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__INPUTISO0N_PP_BLACKBOX_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0N_PP_BLACKBOX_V
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module drives the vga dac on Altera's DE2 Board. *
* *
******************************************************************************/
module altera_up_avalon_video_vga_timing (
// inputs
clk,
reset,
red_to_vga_display,
green_to_vga_display,
blue_to_vga_display,
color_select,
// bidirectional
// outputs
read_enable,
end_of_active_frame,
end_of_frame,
// dac pins
vga_blank, // VGA BLANK
vga_c_sync, // VGA COMPOSITE SYNC
vga_h_sync, // VGA H_SYNC
vga_v_sync, // VGA V_SYNC
vga_data_enable, // VGA DEN
vga_red, // VGA Red[9:0]
vga_green, // VGA Green[9:0]
vga_blue, // VGA Blue[9:0]
vga_color_data // VGA Color[9:0] for TRDB_LCM
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter PW = 10; // Number of bits for pixels
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
parameter LW = 10; // Number of bits for lines
parameter LINE_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [CW: 0] red_to_vga_display;
input [CW: 0] green_to_vga_display;
input [CW: 0] blue_to_vga_display;
input [ 3: 0] color_select;
// Bidirectionals
// Outputs
output read_enable;
output reg end_of_active_frame;
output reg end_of_frame;
// dac pins
output reg vga_blank; // VGA BLANK
output reg vga_c_sync; // VGA COMPOSITE SYNC
output reg vga_h_sync; // VGA H_SYNC
output reg vga_v_sync; // VGA V_SYNC
output reg vga_data_enable; // VGA DEN
output reg [CW: 0] vga_red; // VGA Red[9:0]
output reg [CW: 0] vga_green; // VGA Green[9:0]
output reg [CW: 0] vga_blue; // VGA Blue[9:0]
output reg [CW: 0] vga_color_data; // VGA Color[9:0] for TRDB_LCM
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
//reg clk_en;
reg [PW:1] pixel_counter;
reg [LW:1] line_counter;
reg early_hsync_pulse;
reg early_vsync_pulse;
reg hsync_pulse;
reg vsync_pulse;
reg csync_pulse;
reg hblanking_pulse;
reg vblanking_pulse;
reg blanking_pulse;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
vga_c_sync <= 1'b1;
vga_blank <= 1'b1;
vga_h_sync <= 1'b1;
vga_v_sync <= 1'b1;
vga_red <= {(CW + 1){1'b0}};
vga_green <= {(CW + 1){1'b0}};
vga_blue <= {(CW + 1){1'b0}};
vga_color_data <= {(CW + 1){1'b0}};
end
else
begin
vga_blank <= ~blanking_pulse;
vga_c_sync <= ~csync_pulse;
vga_h_sync <= ~hsync_pulse;
vga_v_sync <= ~vsync_pulse;
// vga_data_enable <= hsync_pulse | vsync_pulse;
vga_data_enable <= ~blanking_pulse;
if (blanking_pulse)
begin
vga_red <= {(CW + 1){1'b0}};
vga_green <= {(CW + 1){1'b0}};
vga_blue <= {(CW + 1){1'b0}};
vga_color_data <= {(CW + 1){1'b0}};
end
else
begin
vga_red <= red_to_vga_display;
vga_green <= green_to_vga_display;
vga_blue <= blue_to_vga_display;
vga_color_data <= ({(CW + 1){color_select[0]}} & red_to_vga_display) |
({(CW + 1){color_select[1]}} & green_to_vga_display) |
({(CW + 1){color_select[2]}} & blue_to_vga_display);
end
end
end
// Internal Registers
always @ (posedge clk)
begin
if (reset)
begin
pixel_counter <= H_TOTAL - 3; // {PW{1'b0}};
line_counter <= V_TOTAL - 1; // {LW{1'b0}};
end
else
begin
// last pixel in the line
if (pixel_counter == (H_TOTAL - 1))
begin
pixel_counter <= {PW{1'b0}};
// last pixel in last line of frame
if (line_counter == (V_TOTAL - 1))
line_counter <= {LW{1'b0}};
// last pixel but not last line
else
line_counter <= line_counter + LINE_COUNTER_INCREMENT;
end
else
pixel_counter <= pixel_counter + PIXEL_COUNTER_INCREMENT;
end
end
always @ (posedge clk)
begin
if (reset)
begin
end_of_active_frame <= 1'b0;
end_of_frame <= 1'b0;
end
else
begin
if ((line_counter == (V_ACTIVE - 1)) &&
(pixel_counter == (H_ACTIVE - 2)))
end_of_active_frame <= 1'b1;
else
end_of_active_frame <= 1'b0;
if ((line_counter == (V_TOTAL - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
end_of_frame <= 1'b1;
else
end_of_frame <= 1'b0;
end
end
always @ (posedge clk)
begin
if (reset)
begin
early_hsync_pulse <= 1'b0;
early_vsync_pulse <= 1'b0;
hsync_pulse <= 1'b0;
vsync_pulse <= 1'b0;
csync_pulse <= 1'b0;
end
else
begin
// start of horizontal sync
if (pixel_counter == (H_ACTIVE + H_FRONT_PORCH - 2))
early_hsync_pulse <= 1'b1;
// end of horizontal sync
else if (pixel_counter == (H_TOTAL - H_BACK_PORCH - 2))
early_hsync_pulse <= 1'b0;
// start of vertical sync
if ((line_counter == (V_ACTIVE + V_FRONT_PORCH - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
early_vsync_pulse <= 1'b1;
// end of vertical sync
else if ((line_counter == (V_TOTAL - V_BACK_PORCH - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
early_vsync_pulse <= 1'b0;
hsync_pulse <= early_hsync_pulse;
vsync_pulse <= early_vsync_pulse;
csync_pulse <= early_hsync_pulse ^ early_vsync_pulse;
end
end
always @ (posedge clk)
begin
if (reset)
begin
hblanking_pulse <= 1'b1;
vblanking_pulse <= 1'b1;
blanking_pulse <= 1'b1;
end
else
begin
if (pixel_counter == (H_ACTIVE - 2))
hblanking_pulse <= 1'b1;
else if (pixel_counter == (H_TOTAL - 2))
hblanking_pulse <= 1'b0;
if ((line_counter == (V_ACTIVE - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
vblanking_pulse <= 1'b1;
else if ((line_counter == (V_TOTAL - 1)) &&
(pixel_counter == (H_TOTAL - 2)))
vblanking_pulse <= 1'b0;
blanking_pulse <= hblanking_pulse | vblanking_pulse;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign read_enable = ~blanking_pulse;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// TODO: Check if all pins are listed OK
module aes_cart(
// PROG top
input nPORTADRS,
input nSDPOE, SDPMPX,
input [11:8] SDPA,
inout [7:0] SDPAD,
input nRESET,
input CLK_68KCLKB,
input nPORTWEL, nPORTWEU, nPORTOEL, nPORTOEU,
input nROMOEL, nROMOEU,
input nAS, M68K_RW,
inout [15:0] M68K_DATA,
// PROG bottom
input [19:1] M68K_ADDR,
input nROMOE,
output nROMWAIT, nPWAIT1, nPWAIT0, PDTACK,
inout [7:0] SDRAD,
input [9:8] SDRA_L,
input [23:20] SDRA_U,
input SDRMPX, nSDROE,
input CLK_4MB,
// CHA top
input CLK_24M,
input nSDROM, nSDMRD,
input [15:0] SDA,
input SDRD1, SDRD0,
input [23:0] PBUS,
input CA4, LOAD, H, EVEN, S2H1,
input CLK_12M,
input PCK2B, PCK1B,
// CHA bottom
output [7:0] FIXD,
output DOTA, DOTB,
output [3:0] GAD,
output [3:0] GBD,
inout [7:0] SDD,
input CLK_8M
);
aes_prog PROG(nPORTADRS, nSDPOE, SDPMPX, SDPA, SDPAD, nRESET, CLK_68KCLKB, nPORTWEL, nPORTWEU,
nPORTOEL, nPORTOEU, nROMOEL, nROMOEU, nAS, M68K_RW, M68K_DATA, M68K_ADDR, nROMOE,
nROMWAIT, nPWAIT1, nPWAIT0, PDTACK, SDRAD, SDRA_L, SDRA_U, SDRMPX, nSDROE, CLK_4MB);
aes_cha CHA(CLK_24M, nSDROM, nSDMRD, SDA, SDRD1, SDRD0, PBUS, CA4, LOAD, H, EVEN, S2H1, CLK_12M,
PCK2B, PCK1B, FIXD, DOTA, DOTB, GAD, GBD, SDD, CLK_8M);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct _ { _() { ios_base::sync_with_stdio(0); } } _; template <class T> void PV(T a, T b) { while (a != b) cout << *a++, cout << (a != b ? : n ); } template <class T> inline bool chmin(T &a, T b) { return a > b ? a = b, 1 : 0; } template <class T> inline bool chmax(T &a, T b) { return a < b ? a = b, 1 : 0; } const int inf = 0x3f3f3f3f; const int mod = int(1e9) + 7; const int N = 3 * 111111; int n, q; int d[N]; int p[N]; int v[N]; void add(int first, int t) { if (first == 0) return; while (first <= n) { v[first] += t; first += first & (first ^ (first - 1)); } } int sum(int first) { int r = 0; while (first > 0) { r += v[first]; first -= first & (first ^ (first - 1)); } return r; } int main() { cin >> n; p[0] = 0, p[n + 1] = n + 1; for (int i = 1; i <= n; i++) cin >> d[i], p[d[i]] = i; for (int i = 1; i <= n; i++) if (p[d[i] - 1] > i) add(d[i], 1); cin >> q; while (q--) { int op, l, r, t; cin >> op >> l >> r; if (op == 1) { cout << sum(r) - sum(l) + 1 << endl; } else { if (d[l] > d[r]) { t = p[d[r] - 1]; if (l < t && t < r) add(d[r], 1); t = p[d[r] + 1]; if (l < t && t < r) add(d[r] + 1, -1); t = p[d[l] + 1]; if (l < t && t < r) add(d[l] + 1, 1); t = p[d[l] - 1]; if (l < t && t < r) add(d[l], -1); if (d[l] == d[r] + 1) add(d[l], -1); } else if (d[l] < d[r]) { t = p[d[l] - 1]; if (l < t && t < r) add(d[l], -1); t = p[d[l] + 1]; if (l < t && t < r) add(d[l] + 1, 1); t = p[d[r] + 1]; if (l < t && t < r) add(d[r] + 1, -1); t = p[d[r] - 1]; if (l < t && t < r) add(d[r], 1); if (d[l] == d[r] - 1) add(d[r], 1); } swap(d[l], d[r]); p[d[l]] = l, p[d[r]] = r; } } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// i2cSlave.v ////
//// ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// You will need to modify this file to implement your
//// interface.
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "i2cSlave_define.v"
module i2cSlave (
clk,
rst,
sda,
scl,
regAddr,
dataToRegIF,
writeEn,
dataFromRegIF
);
input clk;
input rst;
inout sda;
input scl;
output [7:0] regAddr;
output [7:0] dataToRegIF;
output writeEn;
input [7:0] dataFromRegIF;
// local wires and regs
reg sdaDeb;
reg sclDeb;
reg [`DEB_I2C_LEN-1:0] sdaPipe;
reg [`DEB_I2C_LEN-1:0] sclPipe;
reg [`SCL_DEL_LEN-1:0] sclDelayed;
reg [`SDA_DEL_LEN-1:0] sdaDelayed;
reg [1:0] startStopDetState;
wire clearStartStopDet;
wire sdaOut;
wire sdaIn;
reg [1:0] rstPipe;
wire rstSyncToClk;
reg startEdgeDet;
assign sda = (sdaOut == 1'b0) ? 1'b0 : 1'bz;
assign sdaIn = sda;
// sync rst rsing edge to clk
always @(posedge clk) begin
if (rst == 1'b1)
rstPipe <= 2'b11;
else
rstPipe <= {rstPipe[0], 1'b0};
end
assign rstSyncToClk = rstPipe[1];
// debounce sda and scl
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
sdaPipe <= {`DEB_I2C_LEN{1'b1}};
sdaDeb <= 1'b1;
sclPipe <= {`DEB_I2C_LEN{1'b1}};
sclDeb <= 1'b1;
end
else begin
sdaPipe <= {sdaPipe[`DEB_I2C_LEN-2:0], sdaIn};
sclPipe <= {sclPipe[`DEB_I2C_LEN-2:0], scl};
if (&sclPipe[`DEB_I2C_LEN-1:1] == 1'b1)
sclDeb <= 1'b1;
else if (|sclPipe[`DEB_I2C_LEN-1:1] == 1'b0)
sclDeb <= 1'b0;
if (&sdaPipe[`DEB_I2C_LEN-1:1] == 1'b1)
sdaDeb <= 1'b1;
else if (|sdaPipe[`DEB_I2C_LEN-1:1] == 1'b0)
sdaDeb <= 1'b0;
end
end
// delay scl and sda
// sclDelayed is used as a delayed sampling clock
// sdaDelayed is only used for start stop detection
// Because sda hold time from scl falling is 0nS
// sda must be delayed with respect to scl to avoid incorrect
// detection of start/stop at scl falling edge.
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
sclDelayed <= {`SCL_DEL_LEN{1'b1}};
sdaDelayed <= {`SDA_DEL_LEN{1'b1}};
end
else begin
sclDelayed <= {sclDelayed[`SCL_DEL_LEN-2:0], sclDeb};
sdaDelayed <= {sdaDelayed[`SDA_DEL_LEN-2:0], sdaDeb};
end
end
// start stop detection
always @(posedge clk) begin
if (rstSyncToClk == 1'b1) begin
startStopDetState <= `NULL_DET;
startEdgeDet <= 1'b0;
end
else begin
if (sclDeb == 1'b1 && sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
startEdgeDet <= 1'b1;
else
startEdgeDet <= 1'b0;
if (clearStartStopDet == 1'b1)
startStopDetState <= `NULL_DET;
else if (sclDeb == 1'b1) begin
if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b1 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b0)
startStopDetState <= `STOP_DET;
else if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
startStopDetState <= `START_DET;
end
end
end
serialInterface u_serialInterface (
.clk(clk),
.rst(rstSyncToClk | startEdgeDet),
.dataIn(dataFromRegIF),
.dataOut(dataToRegIF),
.writeEn(writeEn),
.regAddr(regAddr),
.scl(sclDelayed[`SCL_DEL_LEN-1]),
.sdaIn(sdaDeb),
.sdaOut(sdaOut),
.startStopDetState(startStopDetState),
.clearStartStopDet(clearStartStopDet)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
//bug765; disappears if add this wire
//wire [7:0] a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]); // favor low values
wire [7:0] a = crc[7:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] y; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.y (y[15:0]),
// Inputs
.a (a[7:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {48'h0, y};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
y,
// Inputs
a
);
input signed [7:0] a;
output [15:0] y;
// verilator lint_off WIDTH
assign y = ~66'd0 <<< {4{a}};
// verilator lint_on WIDTH
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[102] = {0}; int main() { int n, m, i, ans = 0, x, l, r, num, mid; cin >> n >> m; for (i = 0; i < m; i++) { cin >> x; a[x]++; } sort(a + 1, a + 101); l = 1; r = 10000; while (l <= r) { num = 0; mid = (l + r) >> 1; for (i = 100; i > 0; i--) { if (a[i] < mid) break; num += a[i] / mid; } if (num >= n) { ans = mid; l = mid + 1; } else r = mid - 1; } cout << ans << endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: in_arb_regs.v 5077 2009-02-22 20:17:46Z grg $
//
// Module: in_arb_regs.v
// Project: NF2.1
// Description: Demultiplexes, stores and serves register requests
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module in_arb_regs
#( parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
input state,
input out_wr,
input [CTRL_WIDTH-1:0] out_ctrl,
input [DATA_WIDTH-1:0] out_data,
input out_rdy,
input eop,
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
localparam NUM_REGS_USED = 8; /* don't forget to update this when adding regs */
localparam ADDR_WIDTH = log2(NUM_REGS_USED);
// ------------- Wires/reg ------------------
wire [ADDR_WIDTH-1:0] addr;
wire [`IN_ARB_REG_ADDR_WIDTH - 1:0] reg_addr;
wire [`UDP_REG_ADDR_WIDTH-`IN_ARB_REG_ADDR_WIDTH - 1:0] tag_addr;
wire addr_good;
wire tag_hit;
reg in_pkt;
reg second_word;
reg state_latched;
reg out_rdy_latched;
reg [CTRL_WIDTH-1:0] last_pkt_ctrl_0;
reg [DATA_WIDTH-1:0] last_pkt_data_0;
reg [CTRL_WIDTH-1:0] last_pkt_ctrl_1;
reg [DATA_WIDTH-1:0] last_pkt_data_1;
reg [`CPCI_NF2_DATA_WIDTH-1:0] eop_cnt;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data;
wire first_word;
// -------------- Logic --------------------
assign addr = reg_addr_in[ADDR_WIDTH-1:0];
assign reg_addr = reg_addr_in[`IN_ARB_REG_ADDR_WIDTH-1:0];
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:`IN_ARB_REG_ADDR_WIDTH];
assign addr_good = reg_addr[`IN_ARB_REG_ADDR_WIDTH-1:ADDR_WIDTH] == 'h0 &&
addr < NUM_REGS_USED;
assign tag_hit = tag_addr == `IN_ARB_BLOCK_ADDR;
// Record the various inputs for later output
always @(posedge clk)
begin
// EOP -- resets on read (or write)
if (reset || (reg_req_in && tag_hit && addr == `IN_ARB_NUM_PKTS_SENT))
eop_cnt <= 'h0;
else if (eop)
eop_cnt <= eop_cnt + 'h1;
if (reset) begin
state_latched <= 0;
out_rdy_latched <= 0;
last_pkt_ctrl_0 <= 'h0;
last_pkt_data_0 <= 'h0;
last_pkt_ctrl_1 <= 'h0;
last_pkt_data_1 <= 'h0;
end
else begin
state_latched <= state;
out_rdy_latched <= out_rdy;
if (first_word && out_wr) begin
last_pkt_ctrl_0 <= out_ctrl;
last_pkt_data_0 <= out_data;
end
if (second_word && out_wr) begin
last_pkt_ctrl_1 <= out_ctrl;
last_pkt_data_1 <= out_data;
end
end // else: !if(reset)
end // always @ (posedge clk)
// Location tracking
assign first_word = !in_pkt && !(|out_ctrl);
always @(posedge clk)
begin
if (reset) begin
in_pkt <= 0;
second_word <= 0;
end
else begin
if (first_word && out_wr)
in_pkt <= 1'b1;
else if (in_pkt && |out_ctrl && out_wr)
in_pkt <= 1'b0;
if(first_word && out_wr) begin
second_word <= 1;
end
else if(second_word==1 && out_wr) begin
second_word <= 0;
end
end
end
// Select the register data for output
always @*
begin
if (reset) begin
reg_data = 'h0;
end
else begin
case (addr)
`IN_ARB_NUM_PKTS_SENT: reg_data = eop_cnt;
`IN_ARB_STATE: reg_data = {{(`CPCI_NF2_DATA_WIDTH-2){1'b0}}, out_rdy_latched, state_latched};
`IN_ARB_LAST_PKT_WORD_0_LO: reg_data = last_pkt_data_0[31:0];
`IN_ARB_LAST_PKT_WORD_0_HI: reg_data = last_pkt_data_0[63:32];
`IN_ARB_LAST_PKT_CTRL_0: reg_data = last_pkt_ctrl_0;
`IN_ARB_LAST_PKT_WORD_1_LO: reg_data = last_pkt_data_1[31:0];
`IN_ARB_LAST_PKT_WORD_1_HI: reg_data = last_pkt_data_1[63:32];
`IN_ARB_LAST_PKT_CTRL_1: reg_data = last_pkt_ctrl_1;
endcase // case (reg_cnt)
end
end
// Register I/O
always @(posedge clk) begin
// Never modify the address/src
reg_rd_wr_L_out <= reg_rd_wr_L_in;
reg_addr_out <= reg_addr_in;
reg_src_out <= reg_src_in;
if( reset ) begin
reg_req_out <= 1'b0;
reg_ack_out <= 1'b0;
reg_data_out <= 'h0;
end
else begin
if(reg_req_in && tag_hit) begin
if(addr_good) begin
reg_data_out <= reg_data;
end
else begin
reg_data_out <= 32'hdead_beef;
end
// requests complete after one cycle
reg_ack_out <= 1'b1;
end
else begin
reg_ack_out <= reg_ack_in;
reg_data_out <= reg_data_in;
end
reg_req_out <= reg_req_in;
end // else: !if( reset )
end // always @ (posedge clk)
endmodule // in_arb_regs
|
#include <bits/stdc++.h> using namespace std; int N; vector<pair<int, int> > VX[5]; vector<pair<int, int> > VY[5]; int X[101010]; int Y[101010]; int C[101010]; void ref() { for (int i = 1; i <= N; i++) swap(X[i], Y[i]); } bool f(int m, int a, int b, int c) { int x1 = VX[a][m - 1].first + 1; int x2 = VX[c][N / 3 - m].first - 1; int cnt = 0; for (auto& i : VX[b]) { if (x1 <= i.first && i.first <= x2) cnt++; } return cnt >= m; } bool g(int m, int a, int b, int c) { int y = VY[c][m - 1].second + 1; int x; int cnt = 0; for (auto& i : VX[a]) { if (i.second < y) continue; cnt++; if (cnt >= m) { x = i.first + 1; break; } } if (cnt < m) return false; cnt = 0; for (auto& i : VX[b]) { if (i.second >= y && i.first >= x) cnt++; } return cnt >= m; } bool h(int m, int a, int b, int c) { int y = VY[c][N / 3 - m].second - 1; int x; int cnt = 0; for (auto& i : VX[a]) { if (i.second > y) continue; cnt++; if (cnt >= m) { x = i.first + 1; break; } } if (cnt < m) return false; cnt = 0; for (auto& i : VX[b]) { if (i.second <= y && i.first >= x) cnt++; } return cnt >= m; } int main() { scanf( %d , &N); for (int i = 1; i <= N; i++) { scanf( %d%d%d , &X[i], &Y[i], &C[i]); } int l = 1, r = N / 3; while (l <= r) { int m = l + r >> 1; bool ok = false; for (int z = 0; z < 2; z++) { for (int i = 1; i <= 3; i++) { VX[i].clear(); VY[i].clear(); } for (int i = 1; i <= N; i++) { VX[C[i]].emplace_back(X[i], Y[i]); VY[C[i]].emplace_back(X[i], Y[i]); } for (int i = 1; i <= 3; i++) { sort(VX[i].begin(), VX[i].end()); sort(VY[i].begin(), VY[i].end(), [&](const pair<int, int> a, const pair<int, int> b) { return a.second < b.second; }); } if (f(m, 1, 2, 3)) { ok = true; break; } if (f(m, 1, 3, 2)) { ok = true; break; } if (f(m, 2, 1, 3)) { ok = true; break; } if (f(m, 2, 3, 1)) { ok = true; break; } if (f(m, 3, 1, 2)) { ok = true; break; } if (f(m, 3, 2, 1)) { ok = true; break; } if (g(m, 1, 2, 3)) { ok = true; break; } if (g(m, 1, 3, 2)) { ok = true; break; } if (g(m, 2, 1, 3)) { ok = true; break; } if (g(m, 2, 3, 1)) { ok = true; break; } if (g(m, 3, 1, 2)) { ok = true; break; } if (g(m, 3, 2, 1)) { ok = true; break; } if (h(m, 1, 2, 3)) { ok = true; break; } if (h(m, 1, 3, 2)) { ok = true; break; } if (h(m, 2, 1, 3)) { ok = true; break; } if (h(m, 2, 3, 1)) { ok = true; break; } if (h(m, 3, 1, 2)) { ok = true; break; } if (h(m, 3, 2, 1)) { ok = true; break; } ref(); } if (ok) l = m + 1; else r = m - 1; } printf( %d n , r * 3); return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 5457 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w256,
w257,
w64,
w321,
w5136,
w5457;
assign w1 = i_data0;
assign w256 = w1 << 8;
assign w257 = w1 + w256;
assign w321 = w257 + w64;
assign w5136 = w321 << 4;
assign w5457 = w321 + w5136;
assign w64 = w1 << 6;
assign o_data0 = w5457;
//multiplier_block area estimate = 4770.05771526471;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 200005; int l[MAX_N], r[MAX_N]; int a[MAX_N]; int n; int F[MAX_N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) { l[i] = i; while (a[l[i] - 1] >= a[i]) l[i] = l[l[i] - 1]; } for (int i = n; i >= 1; i--) { r[i] = i; while (a[r[i] + 1] >= a[i]) r[i] = r[r[i] + 1]; } for (int i = 1; i <= n; i++) F[r[i] - l[i] + 1] = max(F[r[i] - l[i] + 1], a[i]); for (int i = n; i >= 1; i--) F[i] = max(F[i], F[i + 1]); for (int i = 1; i <= n; i++) printf( %d , F[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 10; const int MAXM = 1e6 + 10; const int MAXLOG = 20; struct Edge { int x, y, w; int id; } edge[MAXM]; int T, n, m, i; int val; vector<pair<int, int> > e[MAXN]; int fa[MAXN], anc[MAXN][MAXLOG], dep[MAXN]; int ans[MAXM]; int mx[MAXN][MAXLOG]; bool on_mst[MAXM]; inline bool cmp(Edge a, Edge b) { return a.w < b.w; } inline int get_root(int x) { if (fa[x] == x) return x; return fa[x] = get_root(fa[x]); } inline void kruskal() { int i, x, y, sx, sy; int w; for (i = 1; i <= n; i++) fa[i] = i; sort(edge + 1, edge + m + 1, cmp); for (i = 1; i <= m; i++) { x = edge[i].x; y = edge[i].y; w = edge[i].w; sx = get_root(x); sy = get_root(y); if (sx != sy) { fa[sx] = sy; on_mst[edge[i].id] = 1; e[x].push_back(make_pair(y, w)); e[y].push_back(make_pair(x, w)); } } } inline void build(int u) { int i, v; for (i = 1; i < MAXLOG; i++) { anc[u][i] = anc[anc[u][i - 1]][i - 1]; mx[u][i] = max(mx[u][i - 1], mx[anc[u][i - 1]][i - 1]); } for (i = 0; i < e[u].size(); i++) { v = e[u][i].first; if (anc[u][0] != v) { dep[v] = dep[u] + 1; anc[v][0] = u; mx[v][0] = e[u][i].second; build(v); } } } inline int get(int x, int y) { int i, t; int ans = 0; if (dep[x] > dep[y]) swap(x, y); t = dep[y] - dep[x]; for (i = 0; i < MAXLOG; i++) { if (t & (1 << i)) { ans = max(ans, mx[y][i]); y = anc[y][i]; } } if (x == y) return ans; for (i = MAXLOG - 1; i >= 0; i--) { if (anc[x][i] != anc[y][i]) { ans = max(ans, max(mx[x][i], mx[y][i])); x = anc[x][i]; y = anc[y][i]; } } return max(ans, max(mx[x][0], mx[y][0])); } int main() { scanf( %d%d , &n, &m); if (m == n - 1) return 0; for (i = 1; i <= m; i++) { scanf( %d%d%d , &edge[i].x, &edge[i].y, &edge[i].w); edge[i].id = i; } kruskal(); build(1); for (int i = 1; i <= m; ++i) { if (!on_mst[edge[i].id]) ans[edge[i].id] = get(edge[i].x, edge[i].y); } for (int i = 1; i <= m; ++i) if (!on_mst[i]) printf( %d n , ans[i]); return 0; }
|
module butterfly3_8(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
input signed [27:0] i_4;
input signed [27:0] i_5;
input signed [27:0] i_6;
input signed [27:0] i_7;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [27:0] b_0;
wire signed [27:0] b_1;
wire signed [27:0] b_2;
wire signed [27:0] b_3;
wire signed [27:0] b_4;
wire signed [27:0] b_5;
wire signed [27:0] b_6;
wire signed [27:0] b_7;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_7;
assign b_1=i_1+i_6;
assign b_2=i_2+i_5;
assign b_3=i_3+i_4;
assign b_4=i_3-i_4;
assign b_5=i_2-i_5;
assign b_6=i_1-i_6;
assign b_7=i_0-i_7;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
endmodule
|
#include <bits/stdc++.h> using namespace std; __attribute__((constructor)) void Init() { ios_base::sync_with_stdio(false), cin.tie(0), cout << fixed; } constexpr int N = 5e3; char A[N + 2], B[N + 2]; int16_t dp[2][N + 1]; int main() { int n, m, t = 0, ans = 0; cin >> n >> m >> &A[1] >> &B[1]; for (int i = 1; i <= n; ++i, t = 1 - t) { for (int j = 1; j <= m; ++j) { int s = dp[1 - t][j - 1] + 4 * (A[i] == B[j]) - 2; dp[t][j] = max(0, max(s, max(dp[t][j - 1], dp[1 - t][j]) - 1)); ; ans = max<int>(ans, dp[t][j]); } } cout << ans << endl; return 0; }
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHR_3 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
input RST_N;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
always @(posedge CLK) begin
if (RST_N == 0) begin
r <= RESET_VAL;
end else begin
r <= wire_3;
end
end
endmodule
|
// just an example with frequencies. not to be used!
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
// baeckler - 02-15-2007
module vga_driver (
r,g,b,
current_x,current_y,request,
vga_r,vga_g,vga_b,vga_hs,vga_vs,vga_blank,vga_clock,
clk27,rst27);
input [9:0] r,g,b;
output [9:0] current_x;
output [9:0] current_y;
output request;
output [9:0] vga_r, vga_g, vga_b;
output vga_hs, vga_vs, vga_blank, vga_clock;
input clk27, rst27;
////////////////////////////////////////////////////////////
// Horizontal Timing
parameter H_FRONT = 16; // 600ns
parameter H_SYNC = 96; // 3.5us
parameter H_BACK = 48; // 1.8us
parameter H_ACT = 640;//
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
// Vertical Timing
parameter V_FRONT = 11;
parameter V_SYNC = 2;
parameter V_BACK = 31;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
////////////////////////////////////////////////////////////
reg [9:0] h_cntr, v_cntr, current_x, current_y;
reg h_active, v_active, vga_hs, vga_vs;
assign vga_blank = h_active & v_active;
assign vga_clock = ~clk27;
assign vga_r = r;
assign vga_g = g;
assign vga_b = b;
assign request = ((h_cntr>=H_BLANK && h_cntr<H_TOTAL) &&
(v_cntr>=V_BLANK && v_cntr<V_TOTAL));
always @(posedge clk27) begin
if(rst27) begin
h_cntr <= 0;
v_cntr <= 0;
vga_hs <= 1'b1;
vga_vs <= 1'b1;
current_x <= 0;
current_y <= 0;
h_active <= 1'b0;
v_active <= 1'b0;
end
else begin
if(h_cntr != H_TOTAL) begin
h_cntr <= h_cntr + 1'b1;
if (h_active) current_x <= current_x + 1'b1;
if (h_cntr == H_BLANK-1) h_active <= 1'b1;
end
else begin
h_cntr <= 0;
h_active <= 1'b0;
current_x <= 0;
end
if(h_cntr == H_FRONT-1) begin
vga_hs <= 1'b0;
end
if (h_cntr == H_FRONT+H_SYNC-1) begin
vga_hs <= 1'b1;
if(v_cntr != V_TOTAL) begin
v_cntr <= v_cntr + 1'b1;
if (v_active) current_y <= current_y + 1'b1;
if (v_cntr == V_BLANK-1) v_active <= 1'b1;
end
else begin
v_cntr <= 0;
current_y <= 0;
v_active <= 1'b0;
end
if(v_cntr == V_FRONT-1) vga_vs <= 1'b0;
if(v_cntr == V_FRONT+V_SYNC-1) vga_vs <= 1'b1;
end
end
end
endmodule
|
module mstore
#(
parameter N = 0,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
input wire in_nd,
input wire [MWIDTH-1:0] in_m,
input wire in_read,
output wire [MWIDTH-1:0] out_m,
output reg error
);
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
localparam integer LOG_N = clog2(N);
reg [LOG_N-1:0] addr;
wire [LOG_N-1:0] next_addr;
reg [MWIDTH-1:0] RAM[N-1:0];
reg filling;
assign next_addr = addr+1;
assign out_m = (in_read)?RAM[next_addr]:RAM[addr];
always @ (posedge clk)
if (~rst_n)
begin
addr <= {LOG_N{1'b0}};
error <= 1'b0;
filling <= 1'b1;
end
else
begin
// If we have new data make sure we're in the filling
// state and write the data.
if (in_nd)
if (~filling)
error <= 1'b1;
else
RAM[addr] <= in_m;
// If a value has been read make sure we're not in the
// filling state.
else if (in_read)
if (filling)
error <= 1'b1;
// If we have new data or data has been read then we
// increment the position.
if (in_nd | in_read)
if (addr == N-1)
begin
addr <= {LOG_N{1'b0}};
filling <= ~filling;
end
else
addr <= addr + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; vector<vector<int> > G; vector<vector<int> > ID; vector<vector<int> > ans; void addp(int id, int t) { while (ans.size() <= t) ans.push_back(vector<int>()); ans[t].push_back(id); } void solve(int from, int lab, int v) { int ctr = 0; for (int i = 0; i < G[v].size(); ++i) { if (ctr == lab) ++ctr; if (G[v][i] == from) continue; addp(ID[v][i], ctr); solve(v, ctr++, G[v][i]); } } int main() { ios::sync_with_stdio(0); cin >> n; G = vector<vector<int> >(n, vector<int>()); ID = vector<vector<int> >(n, vector<int>()); for (int i = 1; i < n; ++i) { int a, b; cin >> a >> b; G[--a].push_back(--b); G[b].push_back(a); ID[a].push_back(i); ID[b].push_back(i); } solve(-1, -1, 0); cout << ans.size() << n ; for (int i = 0; i < ans.size(); ++i) { cout << ans[i].size(); for (int j = 0; j < ans[i].size(); ++j) cout << << ans[i][j]; cout << n ; } return 0; }
|
//----------------------------------------------------------------------------
//-- Unidad de transmision serie asincrona
//------------------------------------------
//-- (C) BQ. September 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Comprobado su funcionamiento a todas las velocidades estandares:
//-- 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//--- Modulo de transmision serie
//--- La salida tx ESTA REGISTRADA
module uart_tx (
input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
input wire rstn, //-- Reset global (activo nivel bajo)
input wire start, //-- Activar a 1 para transmitir
input wire [7:0] data, //-- Byte a transmitir
output reg tx, //-- Salida de datos serie (hacia el PC)
output wire ready //-- Transmisor listo / ocupado
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
//-- Señal de start registrada
reg start_r;
//-- Reloj para la transmision
wire clk_baud;
//-- Bitcounter
reg [3:0] bitc;
//-- Datos registrados
reg [7:0] data_r;
//--------- Microordenes
wire load; //-- Carga del registro de desplazamiento. Puesta a 0 del
//-- contador de bits
wire baud_en; //-- Habilitar el generador de baudios para la transmision
//-------------------------------------
//-- RUTA DE DATOS
//-------------------------------------
//-- Registrar la entrada start
//-- (para cumplir con las reglas de diseño sincrono)
always @(posedge clk)
start_r <= start;
always @(posedge clk)
if (start == 1 && state == IDLE)
data_r <= data;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- 1 bit start + 8 bits datos + 1 bit stop
reg [9:0] shifter;
//-- Cuando la microorden load es 1 se carga la trama
//-- con load 0 se desplaza a la derecha y se envia un bit, al
//-- activarse la señal de clk_baud que marca el tiempo de bit
//-- Se introducen 1s por la izquierda
always @(posedge clk)
//-- Reset
if (rstn == 0)
shifter <= 10'b11_1111_1111;
//-- Modo carga
else if (load == 1)
shifter <= {data_r,2'b01};
//-- Modo desplazamiento
else if (load == 0 && clk_baud == 1)
shifter <= {1'b1, shifter[9:1]};
//-- Contador de bits enviados
//-- Con la microorden load (=1) se hace un reset del contador
//-- con load = 0 se realiza la cuenta de los bits, al activarse
//-- clk_baud, que indica el tiempo de bit
always @(posedge clk)
if (load == 1)
bitc <= 0;
else if (load == 0 && clk_baud == 1)
bitc <= bitc + 1;
//-- Sacar por tx el bit menos significativo del registros de desplazamiento
//-- ES UNA SALIDA REGISTRADA, puesto que tx se conecta a un bus sincrono
//-- y hay que evitar que salgan pulsos espureos (glitches)
always @(posedge clk)
tx <= shifter[0];
//-- Divisor para obtener el reloj de transmision
baudgen #(BAUD)
BAUD0 (
.clk(clk),
.clk_ena(baud_en),
.clk_out(clk_baud)
);
//------------------------------
//-- CONTROLADOR
//------------------------------
//-- Estados del automata finito del controlador
localparam IDLE = 0; //-- Estado de reposo
localparam START = 1; //-- Comienzo de transmision
localparam TRANS = 2; //-- Estado: transmitiendo dato
//-- Estados del autómata del controlador
reg [1:0] state;
//-- Transiciones entre los estados
always @(posedge clk)
//-- Reset del automata. Al estado inicial
if (rstn == 0)
state <= IDLE;
else
//-- Transiciones a los siguientes estados
case (state)
//-- Estado de reposo. Se sale cuando la señal
//-- de start se pone a 1
IDLE:
if (start_r == 1)
state <= START;
else
state <= IDLE;
//-- Estado de comienzo. Prepararse para empezar
//-- a transmitir. Duracion: 1 ciclo de reloj
START:
state <= TRANS;
//-- Transmitiendo. Se esta en este estado hasta
//-- que se hayan transmitido todos los bits pendientes
TRANS:
if (bitc == 11)
state <= IDLE;
else
state <= TRANS;
//-- Por defecto. NO USADO. Puesto para
//-- cubrir todos los casos y que no se generen latches
default:
state <= IDLE;
endcase
//-- Generacion de las microordenes
assign load = (state == START) ? 1 : 0;
assign baud_en = (state == IDLE) ? 0 : 1;
//-- Señal de salida. Esta a 1 cuando estamos en reposo (listos
//-- para transmitir). En caso contrario esta a 0
assign ready = (state == IDLE) ? 1 : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isprime(long long n) { if (n < 2) return false; if (n == 2) return true; if (n % 2 == 0) return false; for (int i = 3; i * i <= n; i = i + 2) { if (n % i == 0) return false; } return true; } int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int temp = -1, cnt = 0; for (int i = 0; i < n; i++) { if (temp != a[i] && a[i] != 0) { cnt++; temp = a[i]; } } cout << cnt; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { char a[10][10]; char b[10][10]; vector<char> v, l; long long int i, count = 0, j; for (i = 0; i < 2; i++) { for (j = 0; j < 2; j++) { cin >> a[i][j]; } } v.push_back(a[0][0]); v.push_back(a[0][1]); v.push_back(a[1][1]); v.push_back(a[1][0]); for (i = 0; i < 2; i++) { for (j = 0; j < 2; j++) { cin >> b[i][j]; } } l.push_back(b[0][0]); l.push_back(b[0][1]); l.push_back(b[1][1]); l.push_back(b[1][0]); int flag = 0; v.erase(remove(v.begin(), v.end(), X ), v.end()); l.erase(remove(l.begin(), l.end(), X ), l.end()); for (i = 0; i < 3; i++) { if (equal(v.begin(), v.end(), l.begin())) { flag = 1; break; } else { vector<char>::iterator k = v.begin() + 2; char la = *k; v.insert(v.begin(), *k); v.erase(v.begin() + 3); } } if (flag) cout << YES n ; else cout << NO n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int MinDist(int n, int k, const string& s) { int first_cow_pos = 0; while (first_cow_pos < n && s[first_cow_pos] == 1 ) { ++first_cow_pos; } int last_cow_pos = first_cow_pos; int rooms = 1; while (rooms < k + 1) { ++last_cow_pos; if (s[last_cow_pos] == 0 ) { ++rooms; } } int farmer_pos = first_cow_pos; int delta = last_cow_pos - first_cow_pos; for (int i = first_cow_pos + 1; i <= last_cow_pos; ++i) { if (s[i] == 0 && i - first_cow_pos < delta && last_cow_pos - i < delta) { delta = max(i - first_cow_pos, last_cow_pos - i); farmer_pos = i; } } --rooms; for (++first_cow_pos; first_cow_pos < n; ++first_cow_pos) { if (s[first_cow_pos] == 1 ) { continue; } while (rooms < k + 1 && last_cow_pos < n) { ++last_cow_pos; if (last_cow_pos == n) { break; } if (s[last_cow_pos] == 0 ) { ++rooms; } } if (last_cow_pos == n) { break; } int npos = max(farmer_pos, first_cow_pos); int cur_delta = max(farmer_pos - first_cow_pos, last_cow_pos - farmer_pos); while (npos < last_cow_pos) { ++npos; if (s[npos] == 1 ) { continue; } if (npos - first_cow_pos < cur_delta && last_cow_pos - npos < cur_delta) { cur_delta = max(npos - first_cow_pos, last_cow_pos - npos); farmer_pos = npos; } else if (npos - first_cow_pos >= cur_delta) { break; } } delta = min(delta, cur_delta); --rooms; } return delta; } int MinDistSlow(int n, int k, const string& s) { int result = n; for (int fcp = 0; fcp < n; ++fcp) { if (s[fcp] == 1 ) { continue; } int lcp = fcp; int rooms = 1; while (rooms < k + 1 && lcp < n) { ++lcp; if (lcp == n) { break; } if (s[lcp] == 0 ) { ++rooms; } } if (lcp == n) { break; } for (int fp = fcp; fp <= lcp; ++fp) { if (s[fp] == 1 ) { continue; } int delta = max(fp - fcp, lcp - fp); if (delta < result) { result = delta; } } } return result; } int main() { int n, k; cin >> n >> k; string s; char buffer[1000000]; scanf( %s , buffer); s = buffer; int delta = MinDist(n, k, s); cout << delta << endl; return 0; }
|
`timescale 1ns / 1ps
/**
* C_PWM_CNT_WIDTH: 16bits, [0,65535], if using mV as units, range to 65V
* with 150M clock, 60K denominator means 0.4ms, frequency: 2.5kHZ,
* climbing time can reach 60K * 60K / 150M = 25s.
* if inc/dec has 32bits (16bits fractional part), climbing time can reach
* 25s * 60K = 40hours
*/
module DISCHARGE_ctl #
(
parameter integer C_DEFAULT_VALUE = 0,
parameter integer C_PWM_CNT_WIDTH = 16,
parameter integer C_FRACTIONAL_WIDTH = 16,
parameter integer C_NUMBER_WIDTH = 32
) (
input wire clk,
input wire resetn,
output wire def_val,
output wire exe_done,
input wire [C_PWM_CNT_WIDTH-1:0] denominator, // >= 3
input wire [C_PWM_CNT_WIDTH-1:0] numerator0,
input wire [C_PWM_CNT_WIDTH-1:0] numerator1,
input wire [C_NUMBER_WIDTH-1:0] number0,
input wire [C_NUMBER_WIDTH-1:0] number1,
input wire [C_PWM_CNT_WIDTH+C_FRACTIONAL_WIDTH-1:0] inc0,
output wire o_resetn,
output wire drive
);
localparam integer STATE_IDLE = 0;
localparam integer STATE_PRE = 1;
localparam integer STATE_INC = 2;
localparam integer STATE_KEEP = 3;
reg[1:0] pwm_state;
assign def_val = C_DEFAULT_VALUE;
assign o_resetn = resetn;
reg[C_PWM_CNT_WIDTH+C_FRACTIONAL_WIDTH-1:0] numerator_ext;
reg[C_PWM_CNT_WIDTH-1:0] cnt;
reg eop; // end of period
reg eop_p1;
always @ (posedge clk) begin
if (resetn == 0)
cnt <= 0;
else begin
if (cnt == 0)
cnt <= denominator - 1;
else
cnt <= cnt - 1;
end
end
always @ (posedge clk) begin
if (resetn == 0)
eop_p1 <= 0;
else if (eop_p1)
eop_p1 <= 0;
else if (cnt == 2)
eop_p1 <= 1;
end
always @ (posedge clk) begin
if (resetn == 0)
eop <= 0;
else
eop <= eop_p1;
end
reg out_drive;
assign drive = out_drive;
wire[C_PWM_CNT_WIDTH-1:0] numerator;
assign numerator = numerator_ext[C_PWM_CNT_WIDTH+C_FRACTIONAL_WIDTH-1:C_FRACTIONAL_WIDTH];
always @ (posedge clk) begin
if (resetn == 0)
out_drive <= C_DEFAULT_VALUE;
else if (pwm_state != STATE_IDLE) begin
if (cnt == 0) begin
if (numerator != denominator)
out_drive <= ~C_DEFAULT_VALUE;
end
else if (cnt == numerator)
out_drive <= C_DEFAULT_VALUE;
end
end
reg[C_NUMBER_WIDTH-1:0] peroid_cnt;
always @ (posedge clk) begin
if (resetn == 0)
pwm_state <= STATE_IDLE;
else if (eop_p1 && ~exe_done) begin
case (pwm_state)
STATE_IDLE:
pwm_state <= STATE_PRE;
STATE_PRE: begin
if (peroid_cnt <= 1) begin
pwm_state <= STATE_INC;
end
end
STATE_INC: begin
if (numerator <= numerator1) begin
pwm_state <= STATE_KEEP;
end
end
STATE_KEEP: begin
if (peroid_cnt <= 1) begin
pwm_state <= STATE_IDLE;
end
end
endcase
end
end
always @ (posedge clk) begin
if (resetn == 0)
numerator_ext <= 0;
else if (eop_p1 && ~exe_done) begin
case (pwm_state)
STATE_IDLE: begin
numerator_ext <= {numerator0, {(C_FRACTIONAL_WIDTH){1'b0}}};
peroid_cnt <= number0;
end
STATE_PRE: begin
numerator_ext <= {numerator0, {(C_FRACTIONAL_WIDTH){1'b0}}};
peroid_cnt <= peroid_cnt - 1;
end
STATE_INC: begin
if (numerator <= numerator1) begin
numerator_ext <= {numerator1, {(C_FRACTIONAL_WIDTH){1'b0}}};
peroid_cnt <= number1;
end
else begin
numerator_ext <= numerator_ext - inc0;
peroid_cnt <= 0;
end
end
STATE_KEEP: begin
numerator_ext <= {numerator1, {(C_FRACTIONAL_WIDTH){1'b0}}};
peroid_cnt <= peroid_cnt - 1;
end
endcase
end
end
reg end_of_transaction;
assign exe_done = end_of_transaction;
always @ (posedge clk) begin
if (resetn == 0)
end_of_transaction <= 0;
else if (eop_p1 && pwm_state == STATE_KEEP && peroid_cnt <= 1)
end_of_transaction <= 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND2_PP_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int gcd(int f, int s) { if (s == 0) return f; else return gcd(s, f % s); } int const N = 200005; long long const mod = 1000 * 1000 * 1000 + 7; map<string, long long> m; string s[N]; int main() { int a; cin >> a; if (a < 6) printf( -1 n ); else { printf( 1 2 n1 3 n1 4 n ); for (int i = 5; i <= a; i++) printf( 2 %d n , i); } for (int i = 1; i < a; i++) printf( %d %d n , i, i + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int md = 1e9 + 7; const long long int N = 55; long long int a[N]; long long int dp[N][N]; vector<pair<long long int, long long int>> v; long long int mask; long long int rec(long long int n, long long int k) { long long int s = 0; if (dp[n][k] != -1) return dp[n][k]; v.emplace_back(pair<long long int, long long int>{n, k}); if (k == 1) { for (long long int i = 1; i <= n; i++) s += a[i]; return dp[n][k] = ((s & mask) == mask); } for (long long int i = n; i >= k; i--) { s += a[i]; if ((s & mask) == mask) if (rec(i - 1, k - 1)) return dp[n][k] = 1; } return dp[n][k] = 0; } signed main() { ios::sync_with_stdio(0); long long int n, k; cin >> n >> k; for (long long int i = 1; i <= n; i++) cin >> a[i]; long long int ans = 0; long long int c = pow(2, 56); for (long long int i = 0; i < N; i++) for (long long int j = 0; j < N; j++) dp[i][j] = -1; for (long long int i = 56; i >= 0; i--) { mask = ans + c; if (rec(n, k)) ans += c; c >>= 1; for (auto it : v) dp[it.first][it.second] = -1; v.clear(); } cout << ans; return 0; }
|
module score_counter
(
input wire clk, reset,
input wire d_inc, d_dec, d_clr,
// inc -- increase (hit signal)
// dec -- decrease by 2 (kill signal)
// cle -- simple clear signal
output wire [3:0] dig0, dig1
);
// signal declaration
reg [3:0] dig0_reg, dig1_reg, dig0_next, dig1_next;
// well, common sense, hah?
// simple state machine like textbook
// registers
always @(posedge clk, posedge reset)
if (reset)
begin
dig1_reg <= 0;
dig0_reg <= 0;
end
else
begin
dig1_reg <= dig1_next;
dig0_reg <= dig0_next;
end
// next-state logic
always @*
begin
dig0_next = dig0_reg;
dig1_next = dig1_reg;
if (d_clr)
begin
dig0_next = 0;
dig1_next = 0;
end
else if (d_inc)
if (dig0_reg==9)
begin
dig0_next = 0;
if (dig1_reg==9)
dig1_next = 0;
else
dig1_next = dig1_reg + 1;
end
else // dig0 not 9
dig0_next = dig0_reg + 1;
else if (d_dec)
if((dig1_reg == 0) && (dig0_reg < 2))
begin
dig0_next = 0;
dig1_next = 1;
end
else if((dig1_reg > 0) && (dig0_reg == 1))
begin
dig1_next = dig1_reg - 1;
dig0_next = 9;
end
else if((dig1_reg > 0) && (dig0_reg == 0))
begin
dig1_next = dig1_reg - 1;
dig0_next = 8;
end
else
dig0_next = dig0_reg - 2;
end
// output
assign dig0 = dig0_reg;
assign dig1 = dig1_reg;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:48:24 03/26/2016
// Design Name: Top
// Module Name: G:/ceshi/lab5_box/test_for_top.v
// Project Name: lab5_box
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_top;
// Inputs
reg inclk;
reg reset;
// Outputs
wire [7:0] led;
wire [7:0] switch;
// Instantiate the Unit Under Test (UUT)
Top uut (
.inclk(inclk),
.reset(reset),
.led(led),
.switch(switch)
);
always #50 inclk = ~inclk;
initial begin
// Initialize Inputs
inclk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#75 reset = 0;
// Add stimulus here
end
endmodule
|
module master(
input wire [6:0] address,
input wire [7:0] register,
input wire refresh_clk,
input wire sys_clk,
input wire mode,
input wire en,
input wire reset,
input wire Start,
input wire Stop,
input wire repeat_start,
output reg [7:0] out,
output reg ack,
inout wire sda,
inout wire scl
);
reg [3:0] state;
reg [4:0] counter;
wire sda_in, scl_in;
reg sda_enable, sda_out, scl_enable, scl_out, clk_enable, sda_output, sda_en;
assign sda = ( sda_en ) ? (sda_output) ? 1'bz : 1'b0 : 1'bz;
assign sda_in = sda;
assign scl = ( scl_enable ) ? ( clk_enable ) ? (sys_clk) ? 1'bz : 1'b0 : scl_out : 1'bZ;
assign scl_in = scl;
always@(posedge refresh_clk)
begin
sda_en <= sda_enable;
sda_output <= sda_out;
end
always@(posedge sys_clk or negedge reset)
begin
if( ~reset )
begin
state <= 0;
sda_enable <= 0;
sda_out <= 0;
scl_enable <= 0;
clk_enable <= 0;
scl_out <= 0;
out <= 0;
counter <= 0;
ack <= 1'b0;
end
else
begin
case( state )
0:
begin
if((( Start || repeat_start ) ) && ( en ))
begin
state <= 1;
sda_enable <= 1'b1;
sda_out <= 1'b0;
scl_enable <= 1'b0;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 0;
sda_enable <= 1'b0;
sda_out <= 1'b0;
scl_enable <= 1'b0;
clk_enable <= 1'b0;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
1:
begin
if(counter < 7)
begin
state <= 1;
sda_enable <= 1'b1;
sda_out <= address[6-counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= counter + 1;
ack <= 1'b0;
end
else
begin
state <= 2;
sda_enable <= 1'b1;
sda_out <= mode;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
2:
begin
state <= 3;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b1;
end
3:
begin
if( ~sda_in )
begin
if( mode )
begin
state <= 4;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 5;
sda_enable <= 1'b1;
sda_out <= register[7 - counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
else
begin
state <= 7;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
4:
begin
if(counter < 7)
begin
state <= 4;
sda_enable <= 1'b0;
sda_out <= 1'b0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out[7-counter] <= sda_in;
counter <= counter + 1;
ack <= 1'b0;
end
else
begin
if( Stop )
begin
state <= 7;
sda_enable <= 1'b1;
sda_out <= 1'b1;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out[7-counter] <= sda_in;
counter <= 0;
ack <= 1'b1;
end
else
begin
state <= 8;
sda_enable <= 1'b1;
sda_out <= 1'b0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out[7-counter] <= sda_in;
counter <= 0;
ack <= 1'b1;
end
end
end
5:
begin
if(counter < 8)
begin
state <= 5;
sda_enable <= 1'b1;
sda_out <= register[7 - counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= counter + 1;
ack <= 1'b0;
end
else
begin
state <= 6;
sda_enable <= 1'b0;
sda_out <= 1'b0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b1;
end
end
6:
begin
if(( Stop ) || ( sda_in ))
begin
state <= 7;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else if( repeat_start )
begin
state <= 0;
sda_enable <= 1'b1;
sda_out <= 1;
scl_enable <= 1'b1;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 5;
sda_enable <= 1'b1;
sda_out <= register[7 - counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= counter + 1;
ack <= 1'b0;
end
end
7:
begin
state <= 9;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
8:
begin
if( repeat_start )
begin
state <= 0;
sda_enable <= 1'b1;
sda_out <= 1;
scl_enable <= 1'b1;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 4;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
9:
begin
state <= 15;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
15:
begin
state <= 15;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b0;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long arr[101], N, T; void Input() { cin >> N; memset(arr, 0, sizeof arr); for (int i = 0; i < N; i++) { long long tmp; cin >> tmp; arr[tmp]++; } } void Solve() { int one = 0, two = 0; for (int i = 0; i <= 100; i++) { if (arr[i] >= 2 && one == two) { one++; two++; } else if (arr[i] >= 1) { one++; } else { break; } } cout << one + two << n ; } int main() { cin >> T; for (int i = 0; i < T; i++) { Input(); Solve(); } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000 * 1000 + 20; int a[N], x[N], y[N], visited[N], h[N], mark[N], n, t = 0, dady[N]; vector<int> ans, adj[N]; void dfs_mark(int v) { visited[v] = 1; for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i]; if (visited[u] == 0) { dfs_mark(u); mark[v] += mark[u]; } } } void dfs(int v) { visited[v] = 1; for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i]; if (visited[u] == 0 and mark[u] == 1) { ans.push_back(u); dfs(u); } } } void dfs_child(int v) { visited[v] = 1; if (adj[v].size() == 1 and v != 1) { t++; } for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i]; if (visited[u] == 0) { dady[u] = v; dfs_child(u); } } } void masir(int v) { if (v != 1) { ans.push_back(dady[v]); masir(dady[v]); } } int main() { cin >> n; for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } dfs_child(1); fill(visited, visited + n + 1, 0); int c, l = 1; ans.push_back(1); for (int i = 0; i < t; i++) { cin >> c; fill(visited, visited + n + 1, 0); fill(mark, mark + n + 1, 0); mark[c] = 1; dfs_mark(l); fill(visited, visited + n + 1, 0); dfs(l); l = c; } masir(c); if (ans.size() > 2 * n - 1) { cout << -1; return 0; } for (int i = 0; i < ans.size(); i++) { cout << ans[i] << ; } }
|
#include <bits/stdc++.h> int n, m; int table[(1 << 20) + 10]; int lowbit[(1 << 20) + 10]; int ba[35][35]; int cost[35][35]; int same[35][35]; char st[35][35]; int min(int x, int y) { if (x < y) return x; else return y; } int main() { int i, a, j; scanf( %d%d n , &n, &m); for (i = 1; i <= n; i++) { scanf( %s n , st[i] + 1); } for (i = 1; i <= n; i++) { for (a = 1; a <= m; a++) { scanf( %d , &ba[i][a]); } } for (i = 1; i <= n; i++) { for (a = 1; a <= m; a++) { int coma = 0; for (j = 1; j <= n; j++) { if (st[i][a] == st[j][a]) { same[i][a] |= 1 << (j - 1); cost[i][a] += ba[j][a]; if (coma < ba[j][a]) coma = ba[j][a]; } } cost[i][a] -= coma; } } for (i = 1; i <= 1 << n; i++) { table[i] = 100000000; for (a = 1; a <= n; a++) { if (i >> (a - 1) & 1) { lowbit[i] = a; break; } } } table[0] = 0; for (a = 1; a < 1 << n; a++) { for (i = 1; i <= m; i++) { table[a] = min(table[a], table[a ^ (1 << (lowbit[a] - 1))] + ba[lowbit[a]][i]); table[a] = min(table[a], table[a & (a ^ same[lowbit[a]][i])] + cost[lowbit[a]][i]); } } printf( %d n , table[(1 << n) - 1]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { set<char> c; int mul = 0; long long ans = 1; bool f = false; string s; cin >> s; for (int i = 0; i < s.length(); i++) { if (s[i] == ? ) ans *= 10; else if (s[i] >= 65 && s[i] <= 74) c.insert(s[i]); } if (s[0] >= 65 && s[0] <= 74 || s[0] == ? ) f = true; for (int i = 0; i < c.size(); i++) ans *= (10 - i); if (f == true) ans *= 0.9; cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTN_1_V
`define SKY130_FD_SC_MS__DLXTN_1_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxtn_1 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxtn_1 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTN_1_V
|
#include <bits/stdc++.h> const int MAXN = 200000; using namespace std; inline int read() { int x = 0, w = 1; char c = ; while (c < 0 || c > 9 ) { c = getchar(); if (c == - ) w = -1; } while (c >= 0 && c <= 9 ) { x = (x << 1) + (x << 3) + (c ^ 48); c = getchar(); } return x * w; } int n, a[MAXN + 5]; void init() { n = read(); for (int i = 1; i <= n; ++i) a[i] = read(); } int mx, mxi, ans[MAXN + 5], len; map<int, int> dp; int main() { init(); for (int i = 1; i <= n; ++i) { dp[a[i]] = dp[a[i] - 1] + 1; if (dp[a[i]] > mx) { mx = dp[a[i]]; mxi = a[i]; } } printf( %d n , mx); for (int i = n; i > 0; --i) if (mxi == a[i]) { --mxi; ans[++len] = i; } for (int i = len; i > 0; --i) printf( %d , ans[i]); printf( n ); return 0; }
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
module RCB_FRL_OSERDES_MSG(OQ, clk, clkdiv, DI, OCE, SR);
output OQ;
input clk, clkdiv;
input [7:0] DI;
input OCE, SR;
wire SHIFT1, SHIFT2;
OSERDES OSERDES_inst1 (
.OQ(OQ), // 1-bit data path output
.SHIFTOUT1(), // 1-bit data expansion output
.SHIFTOUT2(), // 1-bit data expansion output
.TQ(), // 1-bit 3-state control output
.CLK(clk), // 1-bit clock input
.CLKDIV(clkdiv), // 1-bit divided clock input
.D1(DI[7]), // 1-bit parallel data input
.D2(DI[6]), // 1-bit parallel data input
.D3(DI[5]), // 1-bit parallel data input
.D4(DI[4]), // 1-bit parallel data input
.D5(DI[3]), // 1-bit parallel data input
.D6(DI[2]), // 1-bit parallel data input
.OCE(OCE), // 1-bit clock enable input
.REV(1'b0), // 1-bit reverse SR input
.SHIFTIN1(SHIFT1), // 1-bit data expansion input
.SHIFTIN2(SHIFT2), // 1-bit data expansion input
.SR(SR), // 1-bit set/reset input
.T1(), // 1-bit parallel 3-state input
.T2(), // 1-bit parallel 3-state input
.T3(), // 1-bit parallel 3-state input
.T4(), // 1-bit parallel 3-state input
.TCE(1'b1) // 1-bit 3-state signal clock enable input
);
defparam OSERDES_inst1.DATA_RATE_OQ = "DDR";
defparam OSERDES_inst1.DATA_RATE_TQ = "DDR";
defparam OSERDES_inst1.DATA_WIDTH = 8;
defparam OSERDES_inst1.SERDES_MODE = "MASTER";
defparam OSERDES_inst1.TRISTATE_WIDTH = 1;
OSERDES OSERDES_inst2 (
.OQ(), // 1-bit data path output
.SHIFTOUT1(SHIFT1), // 1-bit data expansion output
.SHIFTOUT2(SHIFT2), // 1-bit data expansion output
.TQ(), // 1-bit 3-state control output
.CLK(clk), // 1-bit clock input
.CLKDIV(clkdiv), // 1-bit divided clock input
.D1(), // 1-bit parallel data input
.D2(), // 1-bit parallel data input
.D3(DI[1]), // 1-bit parallel data input
.D4(DI[0]), // 1-bit parallel data input
.D5(), // 1-bit parallel data input
.D6(), // 1-bit parallel data input
.OCE(OCE), // 1-bit clock enable input
.REV(1'b0), // 1-bit reverse SR input
.SHIFTIN1(), // 1-bit data expansion input
.SHIFTIN2(), // 1-bit data expansion input
.SR(SR), // 1-bit set/reset input
.T1(), // 1-bit parallel 3-state input
.T2(), // 1-bit parallel 3-state input
.T3(), // 1-bit parallel 3-state input
.T4(), // 1-bit parallel 3-state input
.TCE(1'b1) // 1-bit 3-state signal clock enable input
);
defparam OSERDES_inst2.DATA_RATE_OQ = "DDR";
defparam OSERDES_inst2.DATA_RATE_TQ = "DDR";
defparam OSERDES_inst2.DATA_WIDTH = 8;
defparam OSERDES_inst2.SERDES_MODE = "SLAVE";
defparam OSERDES_inst2.TRISTATE_WIDTH = 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int r[100005], t, n, m, ans = 0; vector<int> id[100005]; set<int> v; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d , &t); v.insert(t); id[t].push_back(i); r[t] = max(r[t], i); } for (auto it : v) { int sum = 0; for (int i = 0; i < id[it].size() && sum < 2; i++) { t = 0; if (id[it][i] < r[it - 1]) t++; if (id[it][i] < r[it + 1]) t++; sum = max(sum, t); } ans += sum; } printf( %d n , n * 3 - 2 - ans - v.size()); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100000; const int delt = 255; long long fa[N], fb[N], fc[N]; int main() { ios::sync_with_stdio(false); string a, b, c; cin >> a; cin >> b; cin >> c; for (int i = 0; i < a.size(); i++) { fa[a[i] + delt]++; } for (int i = 0; i < b.size(); i++) { fb[b[i] + delt]++; } for (int i = 0; i < c.size(); i++) { fc[c[i] + delt]++; } pair<long long, pair<long long, long long> > ans = {0, {0, 0}}; for (int j = 0; j <= a.size(); j++) { long long kb = j; bool was = 0; for (char i = a ; i <= z ; i++) { if (fa[i + delt] < kb * fb[i + delt]) { was = 1; break; } } if (was) continue; long long kc = (long long)1e15; for (char i = a ; i <= z ; i++) { if (fc[i + delt] > 0) kc = min(kc, (fa[i + delt] - kb * fb[i + delt]) / fc[i + delt]); } ans = max(ans, make_pair(kb + kc, make_pair(kb, kc))); } for (char i = a ; i <= z ; i++) { fa[i + delt] -= ans.second.first * fb[i + delt]; fa[i + delt] -= ans.second.second * fc[i + delt]; } string str = ; for (int i = 0; i < ans.second.first; i++) { str += b; } for (int i = 0; i < ans.second.second; i++) { str += c; } for (char i = a ; i <= z ; i++) { while (fa[i + delt] > 0) { str += i; fa[i + delt]--; } } cout << str << n ; return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc #(
parameter csr_addr = 4'h0,
/*
* The depth of the SDRAM array, in bytes.
* Capacity (in bytes) is 2^sdram_depth.
*/
parameter sdram_depth = 26,
/*
* The number of column address bits of the SDRAM.
*/
parameter sdram_columndepth = 9
) (
input sys_clk,
input sys_clk_n,
input sys_rst,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Simple FML 4x64 interface to the memory contents */
input [sdram_depth-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_eack,
input [7:0] fml_sel,
input [63:0] fml_di,
output [63:0] fml_do,
/* SDRAM interface.
* The SDRAM clock should be driven synchronously to the system clock.
* It is not generated inside this core so you can take advantage of
* architecture-dependent clocking resources to generate a clean
* differential clock.
*/
output reg sdram_cke,
output reg sdram_cs_n,
output reg sdram_we_n,
output reg sdram_cas_n,
output reg sdram_ras_n,
output reg [12:0] sdram_adr,
output reg [1:0] sdram_ba,
output [3:0] sdram_dm,
inout [31:0] sdram_dq,
inout [3:0] sdram_dqs
);
/* Register all control signals. */
wire sdram_cke_r;
wire sdram_cs_n_r;
wire sdram_we_n_r;
wire sdram_cas_n_r;
wire sdram_ras_n_r;
wire [12:0] sdram_adr_r;
wire [1:0] sdram_ba_r;
always @(posedge sys_clk) begin
sdram_cke <= sdram_cke_r;
sdram_cs_n <= sdram_cs_n_r;
sdram_we_n <= sdram_we_n_r;
sdram_cas_n <= sdram_cas_n_r;
sdram_ras_n <= sdram_ras_n_r;
sdram_ba <= sdram_ba_r;
sdram_adr <= sdram_adr_r;
end
/* Mux the control signals according to the "bypass" selection.
* CKE always comes from the control interface.
*/
wire bypass;
wire sdram_cs_n_bypass;
wire sdram_we_n_bypass;
wire sdram_cas_n_bypass;
wire sdram_ras_n_bypass;
wire [12:0] sdram_adr_bypass;
wire [1:0] sdram_ba_bypass;
wire sdram_cs_n_mgmt;
wire sdram_we_n_mgmt;
wire sdram_cas_n_mgmt;
wire sdram_ras_n_mgmt;
wire [12:0] sdram_adr_mgmt;
wire [1:0] sdram_ba_mgmt;
assign sdram_cs_n_r = bypass ? sdram_cs_n_bypass : sdram_cs_n_mgmt;
assign sdram_we_n_r = bypass ? sdram_we_n_bypass : sdram_we_n_mgmt;
assign sdram_cas_n_r = bypass ? sdram_cas_n_bypass : sdram_cas_n_mgmt;
assign sdram_ras_n_r = bypass ? sdram_ras_n_bypass : sdram_ras_n_mgmt;
assign sdram_adr_r = bypass ? sdram_adr_bypass : sdram_adr_mgmt;
assign sdram_ba_r = bypass ? sdram_ba_bypass : sdram_ba_mgmt;
/* Control interface */
wire sdram_rst;
wire [2:0] tim_rp;
wire [2:0] tim_rcd;
wire tim_cas;
wire [10:0] tim_refi;
wire [3:0] tim_rfc;
wire [1:0] tim_wr;
wire idelay_rst;
wire idelay_ce;
wire idelay_inc;
wire idelay_cal;
hpdmc_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.bypass(bypass),
.sdram_rst(sdram_rst),
.sdram_cke(sdram_cke_r),
.sdram_cs_n(sdram_cs_n_bypass),
.sdram_we_n(sdram_we_n_bypass),
.sdram_cas_n(sdram_cas_n_bypass),
.sdram_ras_n(sdram_ras_n_bypass),
.sdram_adr(sdram_adr_bypass),
.sdram_ba(sdram_ba_bypass),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_cas(tim_cas),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.tim_wr(tim_wr),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc),
.idelay_cal(idelay_cal)
);
/* SDRAM management unit */
wire read;
wire write;
wire [3:0] concerned_bank;
wire read_safe;
wire write_safe;
wire [3:0] precharge_safe;
hpdmc_mgmt #(
.sdram_depth(sdram_depth),
.sdram_columndepth(sdram_columndepth)
) mgmt (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.stb(fml_stb),
.we(fml_we),
.address(fml_adr[sdram_depth-1:3]),
.ack(fml_eack),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.sdram_cs_n(sdram_cs_n_mgmt),
.sdram_we_n(sdram_we_n_mgmt),
.sdram_cas_n(sdram_cas_n_mgmt),
.sdram_ras_n(sdram_ras_n_mgmt),
.sdram_adr(sdram_adr_mgmt),
.sdram_ba(sdram_ba_mgmt)
);
/* Data path controller */
wire direction;
hpdmc_datactl datactl(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.direction(direction),
.tim_cas(tim_cas),
.tim_wr(tim_wr)
);
/* Data path */
hpdmc_ddrio ddrio(
.sys_clk(sys_clk),
.sys_clk_n(sys_clk_n),
.direction(direction),
/* Bit meaning is the opposite between
* the FML selection signal and SDRAM DM pins.
*/
.mo(~fml_sel),
.do(fml_di),
.di(fml_do),
.sdram_dm(sdram_dm),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc),
.idelay_cal(idelay_cal)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int solve() { long long int n; cin >> n; vector<bool> dp(2 * n + 1, 0); vector<long long int> p(2 * n); vector<long long int> nums; long long int cover = 0; vector<long long int> inv(2 * n + 1); for (long long int j = 0; j < 2 * n; j++) { cin >> p[j]; inv[p[j]] = j; if (p[j] == 2 * n) { cover = j; } } nums.push_back(2 * n - cover); for (long long int j = 2 * n - 1; j >= 1; j--) { if (inv[j] > cover) { continue; } else { nums.push_back(cover - inv[j]); cover = inv[j]; } } sort(nums.begin(), nums.end()); dp[nums[0]] = 1; dp[0] = 1; long long int k = nums.size(); for (long long int j = 1; j < k; j++) { vector<long long int> f(2 * n + 1, 0); for (long long int i = 0; i <= 2 * n; i++) { f[i] = dp[i]; if (i - nums[j] >= 0) { f[i] = dp[i] || dp[i - nums[j]]; } } for (long long int i = 0; i <= 2 * n; i++) { dp[i] = f[i]; } } if (!dp[n]) { cout << NO n ; } else { cout << YES n ; } return 0; } signed main() { ios::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct node { int u , v , w; node(){} node(int u,int v,int w): u(u) , v(v) , w(w){}; bool operator < (const node &o) const { return w < o.w; } }; struct dsu { int par[200010]; void init() { for (int i = 1 ; i <= 200000 ; ++i) par[i] = i; } int fin(int u) { if (u != par[u]) par[u] = fin(par[u]); return par[u]; } bool join(int u , int v) { u = fin(u); v = fin(v); if (u == v) return false; if (par[u] > par[v]) swap(u , v); par[u] = v; return true; } } a , b; set < int > vertex; vector < int > g[200010]; vector < node > edge; long long rest; void DFS(int u) { vertex.erase(u); sort(g[u].begin(),g[u].end()); int v = 0; while (1) { auto it = vertex.lower_bound(v); if (it == vertex.end()) return; v = *it; if (!binary_search(g[u].begin(),g[u].end(),v)) { a.join(u , v); DFS(v); rest--; } v++; } } int main() { ios::sync_with_stdio(0); cin.tie(0);cout.tie(0); long long n , m; int x = 0; cin >> n >> m; rest = n * (n - 1) / 2 - m; for (int i = 1 ; i <= m ; ++i) { int u , v , w; cin >> u >> v >> w; x ^= w; g[u].push_back(v); g[v].push_back(u); edge.emplace_back(u , v , w); } a.init();b.init(); for (int i = 1 ; i <= n ; ++i) vertex.insert(i); for (int i = 1 ; i <= n ; ++i) if (vertex.count(i)) DFS(i); if (rest > 0) x = 0; int res = 0; sort(edge.begin(),edge.end()); for (auto p : edge) { int u = p.u , v = p.v , w = p.w; if (a.join(u , v)) { res += w; b.join(u , v); } else if (b.join(u , v)) x = min(x , w); } cout << res + x; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
`define SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C );
buf buf0 (X , xnor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_V
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module clips video streams on the DE boards. If the incoming image is *
* the wrong size, the circuit will discard or add pixels as necessary. *
* *
******************************************************************************/
module altera_up_video_clipper_drop (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's Data Width
parameter EW = 0; // Image's Empty Width
parameter IMAGE_WIDTH = 640; // Image in width in pixels
parameter IMAGE_HEIGHT = 480; // Image in height in lines
parameter WW = 9; // Image in width address width
parameter HW = 8; // Image in height address width
parameter DROP_PIXELS_AT_START = 0;
parameter DROP_PIXELS_AT_END = 0;
parameter DROP_LINES_AT_START = 0;
parameter DROP_LINES_AT_END = 0;
parameter ADD_DATA = 16'h0; // Data for added pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EW: 0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam STATE_0_WAIT_FOR_START = 2'h0,
STATE_1_RUN_CLIPPER = 2'h1,
STATE_2_ADD_MISSING_PART = 2'h2;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire increment_counters;
wire full_frame_endofpacket;
wire new_startofpacket;
wire new_endofpacket;
wire pass_inner_frame;
// Internal Registers
// State Machine Registers
reg [ 1: 0] s_video_clipper_drop;
reg [ 1: 0] ns_video_clipper_drop;
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_video_clipper_drop <= STATE_0_WAIT_FOR_START;
else
s_video_clipper_drop <= ns_video_clipper_drop;
end
always @(*)
begin
case (s_video_clipper_drop)
STATE_0_WAIT_FOR_START:
begin
if (stream_in_startofpacket & stream_in_valid)
ns_video_clipper_drop = STATE_1_RUN_CLIPPER;
else
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
end
STATE_1_RUN_CLIPPER:
begin
if (increment_counters & full_frame_endofpacket)
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
else if (increment_counters & stream_in_endofpacket)
ns_video_clipper_drop = STATE_2_ADD_MISSING_PART;
else
ns_video_clipper_drop = STATE_1_RUN_CLIPPER;
end
STATE_2_ADD_MISSING_PART:
begin
if (increment_counters & full_frame_endofpacket)
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
else
ns_video_clipper_drop = STATE_2_ADD_MISSING_PART;
end
default:
begin
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
if (s_video_clipper_drop == STATE_2_ADD_MISSING_PART)
stream_out_data <= ADD_DATA;
else
stream_out_data <= stream_in_data;
stream_out_startofpacket <= new_startofpacket;
stream_out_endofpacket <= new_endofpacket;
stream_out_empty <= stream_in_empty;
if (s_video_clipper_drop == STATE_1_RUN_CLIPPER)
stream_out_valid <= pass_inner_frame & stream_in_valid;
else if (s_video_clipper_drop == STATE_2_ADD_MISSING_PART)
stream_out_valid <= pass_inner_frame;
else
stream_out_valid <= 1'b0;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready =
(s_video_clipper_drop == STATE_0_WAIT_FOR_START) ?
~(stream_in_startofpacket & stream_in_valid) :
(s_video_clipper_drop == STATE_1_RUN_CLIPPER) ?
~pass_inner_frame | stream_out_ready | ~stream_out_valid :
1'b0;
// Internal Assignments
assign increment_counters =
(s_video_clipper_drop == STATE_1_RUN_CLIPPER) ?
stream_in_valid & stream_in_ready :
(s_video_clipper_drop == STATE_2_ADD_MISSING_PART) ?
~pass_inner_frame | stream_out_ready | ~stream_out_valid :
1'b0;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_clipper_counters Clipper_Drop_Counters (
// Inputs
.clk (clk),
.reset (reset),
.increment_counters (increment_counters),
// Bi-Directional
// Outputs
.start_of_outer_frame (),
.end_of_outer_frame (full_frame_endofpacket),
.start_of_inner_frame (new_startofpacket),
.end_of_inner_frame (new_endofpacket),
.inner_frame_valid (pass_inner_frame)
);
defparam
Clipper_Drop_Counters.IMAGE_WIDTH = IMAGE_WIDTH,
Clipper_Drop_Counters.IMAGE_HEIGHT = IMAGE_HEIGHT,
Clipper_Drop_Counters.WW = WW,
Clipper_Drop_Counters.HW = HW,
Clipper_Drop_Counters.LEFT_OFFSET = DROP_PIXELS_AT_START,
Clipper_Drop_Counters.RIGHT_OFFSET = DROP_PIXELS_AT_END,
Clipper_Drop_Counters.TOP_OFFSET = DROP_LINES_AT_START,
Clipper_Drop_Counters.BOTTOM_OFFSET = DROP_LINES_AT_END;
endmodule
|
#include <bits/stdc++.h> int g[1010][1010]; int main() { int n, k, ans, i, j; while (~scanf( %d%d , &n, &k)) { ans = 0; memset(g, 0, sizeof(g)); for (i = 0; i < n; i++) for (j = i + 1; j <= i + k; j++) g[i][j % n] = 1, ans++; int flag = 1; for (i = 0; i < n; i++) for (j = 0; j < n; j++) if (g[i][j] && g[j][i]) flag = 0; if (flag) { printf( %d n , ans); for (i = 0; i < n; i++) for (j = 0; j < n; j++) if (g[i][j]) printf( %d %d n , i + 1, j + 1); } else puts( -1 ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t = 1; cin >> t; while (t--) { long long int n, i, j; cin >> n; long long int a = n / 3, b = n / 3; if (n % 3 == 1) cout << a + 1 << << b; else if (n % 3 == 2) cout << a << << b + 1; else cout << a << << b; cout << endl; } return 0; }
|
//*******************************************************************************************************************************************************/
// Module Name: mult
// Module Type: Multiplexer
// Author: Shreyas Vinod
// Purpose: Multiplexers for Neptune I v3.0
// Description: Combinatorial 2 to 1 and 4 to 1 multiplexers for use in Neptune I v3.0.
//*******************************************************************************************************************************************************/
module mult_2_to_1(sel, a_in, b_in, out);
// Parameter Definitions
parameter width = 'd16; // Data Width
// Inputs
input wire sel;
input wire [width-1:0] a_in, b_in;
// Outputs
output reg [width-1:0] out;
// Multiplexing Block
always@(sel, a_in, b_in) begin
case(sel) // synthesis parallel_case
1'b0: out [width-1:0] = a_in [width-1:0];
1'b1: out [width-1:0] = b_in [width-1:0];
default: out [width-1:0] = {width{1'b0}};
endcase
end
endmodule
module mult_4_to_1(sel, a_in, b_in, c_in, d_in, out);
// Parameter Definitions
parameter width = 'd16; // Data Width
// Inputs
input wire [1:0] sel;
input wire [width-1:0] a_in, b_in, c_in, d_in;
// Outputs
output reg [width-1:0] out;
// Multiplexing Block
always@(sel, a_in, b_in, c_in, d_in) begin
case(sel) // synthesis parallel_case
2'b00: out [width-1:0] = a_in [width-1:0];
2'b01: out [width-1:0] = b_in [width-1:0];
2'b10: out [width-1:0] = c_in [width-1:0];
2'b11: out [width-1:0] = d_in [width-1:0];
default: out [width-1:0] = {width{1'b0}};
endcase
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 14:20:02 10/03/2016
// Module Name: INSTR_MEM
// Project Name: MIPS
// Description: MIPS Instruction Memory implementation in verilog.
//
// Dependencies: None
//
////////////////////////////////////////////////////////////////////////////////
module INSTR_MEM(input clk, input [31:0] addr, output reg [31:0] data);
// Declare the memory block.
reg [31:0] MEM [128:0];
// Initialize memory.
initial begin
/* SET 1 - Using NOPs to mitigate data hazards.
MEM[0] <= 32'b100011_00000_00001_0000_0000_0000_0001; // LW r1 , 1(r0)
MEM[1] <= 32'b100011_00000_00010_0000_0000_0000_0010; // LW r2 , 2(r0)
MEM[2] <= 32'b100011_00000_00011_0000_0000_0000_0011; // LW r3 , 3(r0)
MEM[3] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[4] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[5] <= 32'b000000_00001_00010_00001_00000_100000; // ADD r1, r1, r2
MEM[6] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[7] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[8] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[9] <= 32'b000000_00001_00011_00001_00000_100000; // ADD r1, r1, r3
MEM[10] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[11] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[12] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[13] <= 32'b000000_00001_00001_00001_00000_100000; // ADD r1, r1, r1
MEM[14] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[15] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[16] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[17] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[18] <= 32'b000000_00001_00000_00001_00000_100000; // ADD r1, r1, r0
MEM[19] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[20] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[21] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[22] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[23] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
*/
/* SET 2 - Using ordering of instructions to mitigate data hazards.
MEM[0] <= 32'b100011_00000_00001_0000_0000_0000_0001; // LW r1, 1(r0)
MEM[1] <= 32'b100011_00000_00010_0000_0000_0000_0010; // LW r2, 2(r0)
MEM[2] <= 32'b100011_00000_00011_0000_0000_0000_0011; // LW r3, 3(r0)
MEM[3] <= 32'b100011_00000_00100_0000_0000_0000_0100; // LW r4, 4(r0)
MEM[4] <= 32'b100011_00000_00101_0000_0000_0000_0101; // LW r5, 5(r0)
MEM[5] <= 32'b101011_00000_00001_0000_0000_0000_0110; // SW r1, 6(r0)
MEM[6] <= 32'b101011_00000_00010_0000_0000_0000_0111; // SW r2, 7(r0)
MEM[7] <= 32'b101011_00000_00011_0000_0000_0000_1000; // SW r3, 8(r0)
MEM[8] <= 32'b101011_00000_00100_0000_0000_0000_1001; // SW r4, 9(r0)
MEM[9] <= 32'b101011_00000_00101_0000_0000_0000_1010; // SW r5, 10(r0)
*/
/* SET 3 - Using forwarding to mitigate data hazards. */
MEM[0] <= 32'b1000_0000_0000_0000_0000_0000_0000_0000; // NOP
MEM[1] <= 32'b001000_00001_00001_0000000000000001; // ADD r1, r1, 1
MEM[2] <= 32'b001000_00010_00010_0000000000000010; // ADD r2, r2, 2
end
// Assign the contents at the requested memory address to data.
always @ *
begin
data <= MEM[addr];
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file hram.v when simulating
// the core, hram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module hram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [6 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [6 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(7),
.C_ADDRB_WIDTH(7),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(128),
.C_READ_DEPTH_B(128),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(128),
.C_WRITE_DEPTH_B(128),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Top level module for simple memory access. See lsu_top.v.
//
// Properties - Coalesced: No, Ordered: N/A, Hazard-Safe: Yes, Pipelined: No
// (see lsu_top.v for details)
//
// Description: Simple un-pipelined memory access. Low throughput.
//
// Simple read unit:
// Accept read requests on the upstream interface. When a request is
// received, set the pending register to true to stall any subsequent
// requests until the transaction is complete. Since an avalon master
// cannot stall a response, staging registers are used at the output to
// provide a storage location until the downstream block is ready to accept
// data. Once the output registers are cleared and there are no pending
// requests, accept a new transaction.
module lsu_simple_read
(
clk, reset, o_stall, i_valid, i_address, i_stall, o_valid, o_readdata,
o_active, // Debugging signal
avm_address, avm_read, avm_readdata, avm_waitrequest, avm_byteenable,
avm_readdatavalid
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
// - indicates how many bits of the address
// are '0' due to the request alignment
parameter HIGH_FMAX=1;
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam MIN_BYTE_SELECT_BITS = BYTE_SELECT_BITS == 0 ? 1 : BYTE_SELECT_BITS;
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
// Downstream interface
input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;
/***************
* Architecture *
***************/
reg pending;
wire read_accepted;
wire rdata_accepted;
wire sr_stall;
wire ready;
wire [WIDTH-1:0] rdata;
wire [MIN_BYTE_SELECT_BITS-1:0] byte_address;
reg [MIN_BYTE_SELECT_BITS-1:0] byte_select;
// Ready for new data if we have access to the downstream registers and there
// is no pending memory transaction
assign ready = !sr_stall && !pending;
wire [AWIDTH-1:0] f_avm_address;
wire f_avm_read;
wire f_avm_waitrequest;
// Avalon signals - passed through from inputs
assign f_avm_address = (i_address[AWIDTH-1:BYTE_SELECT_BITS] << BYTE_SELECT_BITS);
assign f_avm_read = i_valid && ready;
assign avm_byteenable = {MWIDTH_BYTES{1'b1}};
// Upstream stall if we aren't ready for new data, or the avalon interface
// is stalling.
assign o_stall = f_avm_waitrequest || !ready;
// Pick out the byte address
// Explicitly set alignment address bits to 0 to help synthesis optimizations.
generate
if (BYTE_SELECT_BITS == 0) begin
assign byte_address = 1'b0;
end
else begin
assign byte_address = ((i_address[MIN_BYTE_SELECT_BITS-1:0] >> ALIGNMENT_ABITS) << ALIGNMENT_ABITS);
end
endgenerate
// State registers
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
pending <= 1'b0;
byte_select <= 'x; // don't need to reset
end
else
begin
// A requst remains pending until we receive valid data; and a request
// becomes pending if we accept a new valid input
pending <= pending ? !avm_readdatavalid : (i_valid && !o_stall && !avm_readdatavalid);
// Remember which bytes to select out of the wider global memory bus.
byte_select <= pending ? byte_select : byte_address;
end
end
// Mux in the appropriate response bits
assign rdata = avm_readdata[8*byte_select +: WIDTH];
// Output staging register - required so that we can guarantee there is
// a place to store the readdata response
acl_staging_reg #(
.WIDTH(WIDTH)
) staging_reg (
.clk(clk),
.reset(reset),
.i_data(rdata),
.i_valid(avm_readdatavalid),
.o_stall(sr_stall),
.o_data(o_readdata),
.o_valid(o_valid),
.i_stall (i_stall)
);
generate
if(HIGH_FMAX)
begin
// Pipeline the interface
acl_data_fifo #(
.DATA_WIDTH(AWIDTH),
.DEPTH(2),
.IMPL("ll_reg")
) avm_buffer (
.clock(clk),
.resetn(!reset),
.data_in(f_avm_address),
.valid_in(f_avm_read),
.data_out(avm_address),
.valid_out( avm_read ),
.stall_in( avm_waitrequest ),
.stall_out( f_avm_waitrequest )
);
end
else
begin
// No interface pipelining
assign f_avm_waitrequest = avm_waitrequest;
assign avm_address = f_avm_address;
assign avm_read = f_avm_read;
end
endgenerate
assign o_active=pending;
endmodule
// Simple write unit:
// Accept write requests on the upstream interface. When a request is
// received, pass it through to the avalon bus. Once avalon accepts
// the request, set the output valid bit to true and stall until
// the downstream block acknowledges the successful write.
module lsu_simple_write
(
clk, reset, o_stall, i_valid, i_address, i_writedata, i_stall, o_valid, i_byteenable,
o_active, // Debugging signal
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the request
parameter MWIDTH_BYTES=32; // Width of the global memory bus
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam NUM_SEGMENTS=2**SEGMENT_SELECT_BITS;
localparam SEGMENT_WIDTH=8*(2**ALIGNMENT_ABITS);
localparam SEGMENT_WIDTH_BYTES=(2**ALIGNMENT_ABITS);
parameter USE_BYTE_EN=0;
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
input [WIDTH_BYTES-1:0] i_byteenable;
// Downstream interface
input i_stall;
output o_valid;
output o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output reg [MWIDTH-1:0] avm_writedata;
output reg [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
/***************
* Architecture *
***************/
reg write_pending;
wire write_accepted;
wire ready;
wire sr_stall;
// Avalon interface
assign avm_address = ((i_address >> BYTE_SELECT_BITS) << BYTE_SELECT_BITS);
assign avm_write = ready && i_valid;
// Mux in the correct data
generate if( SEGMENT_SELECT_BITS > 0 )
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_select;
assign segment_select = i_address[BYTE_SELECT_BITS-1:ALIGNMENT_ABITS];
always@(*)
begin
avm_writedata = {MWIDTH{1'bx}};
avm_writedata[segment_select*SEGMENT_WIDTH +: WIDTH] = i_writedata;
avm_byteenable = {MWIDTH_BYTES{1'b0}};
avm_byteenable[segment_select*SEGMENT_WIDTH_BYTES +: WIDTH_BYTES] = USE_BYTE_EN ? i_byteenable : {WIDTH_BYTES{1'b1}};
end
end
else
begin
always@(*)
begin
avm_writedata = {MWIDTH{1'bx}};
avm_writedata[0 +: WIDTH] = i_writedata;
avm_byteenable = {MWIDTH_BYTES{1'b0}};
avm_byteenable[0 +: WIDTH_BYTES] = USE_BYTE_EN ? i_byteenable : {WIDTH_BYTES{1'b1}};
end
end
endgenerate
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
write_pending <= 1'b0;
end
else
begin
write_pending <= (write_accepted || write_pending) && !avm_writeack;
end
end
// Control logic
assign ready = !sr_stall && !write_pending;
assign write_accepted = avm_write && !avm_waitrequest;
assign o_stall = !ready || avm_waitrequest;
// Output staging register - required so that we can guarantee there is
// a place to store the valid bit
acl_staging_reg #(
.WIDTH(1)
) staging_reg (
.clk(clk),
.reset(reset),
.i_data(1'b0),
.i_valid(avm_writeack),
.o_stall(sr_stall),
.o_data(),
.o_valid(o_valid),
.i_stall (i_stall)
);
assign o_active=write_pending;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_BLACKBOX_V
/**
* udp_isolatchhv_pp$PLG$S: Power isolating latch (for HV). Includes
* VPWR, LVPWR, and VGND power pins with
* active high sleep pin (SLEEP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S (
UDP_OUT,
UDP_IN ,
VPWR ,
LVPWR ,
VGND ,
SLEEP
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
input LVPWR ;
input VGND ;
input SLEEP ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m, k; vector<vector<int> > g; vector<vector<int> > revg; int active[1000005]; int del; int limx, limy, limz; unordered_set<int> visited; void add(int a, int b) { if (active[a] && active[b]) { g[a].push_back(b); revg[b].push_back(a); } } int get(int a, int b, int c) { return a * m * k + b * k + c; } bool downlimit(int v) { if (v == del) return false; int z(v % k); v /= k; int y(v % m); int x(v / m); return x <= limx && y <= limy && z <= limz; } void dfs(int v) { visited.insert(v); for (int i(0), _l((int)(((int)g[v].size())) - 1); i <= _l; ++i) { int to(g[v][i]); if (downlimit(to)) dfs(to); } } void solve() { memset((active), 0, sizeof(active)); scanf( %d%d%d n , &n, &m, &k); g.resize(n * m * k); revg.resize(n * m * k); for (int i(0), _l((int)(n)-1); i <= _l; ++i) for (int j(0), _l((int)(m)-1); j <= _l; ++j) { string s; getline(cin, s); for (int q(0), _l((int)(k)-1); q <= _l; ++q) active[get(i, j, q)] = (s[q] == 1 ); if (j == m - 1) getline(cin, s); } for (int i(0), _l((int)(n)-1); i <= _l; ++i) for (int j(0), _l((int)(m)-1); j <= _l; ++j) for (int q(0), _l((int)(k)-1); q <= _l; ++q) { if (i < n - 1) add(get(i, j, q), get(i + 1, j, q)); if (j < m - 1) add(get(i, j, q), get(i, j + 1, q)); if (q < k - 1) add(get(i, j, q), get(i, j, q + 1)); } int ans(0); for (int x(0), _l((int)(n)-1); x <= _l; ++x) for (int y(0), _l((int)(m)-1); y <= _l; ++y) for (int z(0), _l((int)(k)-1); z <= _l; ++z) { int v(get(x, y, z)); del = v; limx = x + 1, limy = y + 1, limz = z + 1; bool frogs(false); for (int i(0), _l((int)(((int)revg[v].size())) - 1); i <= _l; ++i) { int from(revg[v][i]); visited.clear(); dfs(from); for (int j(0), _l((int)(((int)g[v].size())) - 1); j <= _l; ++j) { int to(g[v][j]); if (!visited.count(to)) frogs = true; if (frogs) break; } if (frogs) break; } ans += frogs; } printf( %d n , ans); } int main() { solve(); return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Mar 28 02:08:39 2017
// Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_stub.v
// Design : dds_compiler_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0_13,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid,
s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [23:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
(* abc9_box *)
module MISTRAL_MUL27X27(input [26:0] A, input [26:0] B, output [53:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 3732;
(B *> Y) = 3928;
endspecify
wire [53:0] A_, B_;
if (A_SIGNED)
assign A_ = $signed(A);
else
assign A_ = $unsigned(A);
if (B_SIGNED)
assign B_ = $signed(B);
else
assign B_ = $unsigned(B);
assign Y = A_ * B_;
endmodule
(* abc9_box *)
module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 3180;
(B *> Y) = 3982;
endspecify
wire [35:0] A_, B_;
if (A_SIGNED)
assign A_ = $signed(A);
else
assign A_ = $unsigned(A);
if (B_SIGNED)
assign B_ = $signed(B);
else
assign B_ = $unsigned(B);
assign Y = A_ * B_;
endmodule
(* abc9_box *)
module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
// TODO: Cyclone 10 GX timings; the below are for Cyclone V
specify
(A *> Y) = 2818;
(B *> Y) = 3051;
endspecify
wire [17:0] A_, B_;
if (A_SIGNED)
assign A_ = $signed(A);
else
assign A_ = $unsigned(A);
if (B_SIGNED)
assign B_ = $signed(B);
else
assign B_ = $unsigned(B);
assign Y = A_ * B_;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long t, n, i, b[1010], ta, tb, k1, a[1010], tem, x[1010], y[1010], k2, tom; vector<long long> v[1010]; void dfs(long long aa, long long bb) { b[aa] = bb; long long ii; for (ii = 0; ii < v[aa].size(); ii++) if (!b[v[aa][ii]]) dfs(v[aa][ii], bb); } int main() { cin >> t; while (t--) { cin >> n; for (i = 1; i <= n; i++) v[i].clear(); for (i = 1; i <= n; i++) b[i] = 0; for (i = 1; i < n; i++) { cin >> ta >> tb; v[ta].push_back(tb); v[tb].push_back(ta); } for (i = 1; i <= n; i++) b[i] = 0; for (i = 1; i <= n; i++) x[i] = 0; for (i = 1; i <= n; i++) y[i] = 0; cin >> k1; for (i = 1; i <= k1; i++) { cin >> a[i]; b[a[i]] = a[i]; x[a[i]] = 1; } for (i = 1; i <= k1; i++) dfs(a[i], a[i]); cin >> k2; for (i = 1; i <= k2; i++) { cin >> ta; y[ta] = 1; } cout << B << ta << endl; cin >> tem; if (x[tem]) cout << C << tem << endl; else { cout << A << b[tem] << endl; cin >> tom; if (y[tom]) cout << C << b[tem] << endl; else cout << C << -1 << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.1415926535897932384626433832795; const double EPS = 1e-9; set<int> good; void gen(int x) { good.insert(x); if (x > 100 * 1000 * 1000) { return; } gen(10 * x + 4); gen(10 * x + 7); } vector<pair<int, int> > swaps; void addSwap(int i, int j) { if (i != j) { swaps.push_back(pair<int, int>(i, j)); } } bool fail; vector<pair<int, int> > solve(const vector<int>& seq____) { vector<int> seq = seq____; swaps.clear(); fail = false; int where_good = -1; int n = seq.size(); bool sorted = true; for (int i = 0; i < n; ++i) { if (i > 0 && seq[i] < seq[i - 1]) { sorted = false; } if (good.count(seq[i])) { where_good = i; } } if (where_good == -1) { if (!sorted) { fail = true; } return swaps; } int goodNumber = seq[where_good]; int amountLess = 0; for (int i = 0; i < n; ++i) { if (seq[i] < goodNumber) { ++amountLess; } } vector<int> positions; for (int i = 0; i < n; ++i) { if (i != amountLess) { positions.push_back(i); } } set<pair<int, int> > unsorted; for (int i = 0; i < n; ++i) { if (i == where_good) { continue; } unsorted.insert(pair<int, int>(seq[i], i)); } int idInPositions = 0; while (!unsorted.empty()) { pair<int, int> cur = *unsorted.begin(); unsorted.erase(unsorted.begin()); if (cur.second == positions[idInPositions]) { ++idInPositions; continue; } int firstSwapPosition = positions[idInPositions]; bool firstErased = unsorted.count( pair<int, int>(seq[firstSwapPosition], firstSwapPosition)); unsorted.erase(pair<int, int>(seq[firstSwapPosition], firstSwapPosition)); swap(seq[where_good], seq[firstSwapPosition]); if (firstErased) { unsorted.insert(pair<int, int>(seq[where_good], where_good)); } addSwap(where_good, positions[idInPositions]); where_good = firstSwapPosition; int secondSwapPosition = cur.second; bool secondErased = unsorted.count( pair<int, int>(seq[secondSwapPosition], secondSwapPosition)); unsorted.erase(pair<int, int>(seq[secondSwapPosition], secondSwapPosition)); swap(seq[where_good], seq[secondSwapPosition]); if (secondErased) { unsorted.insert(pair<int, int>(seq[where_good], where_good)); } addSwap(where_good, secondSwapPosition); where_good = secondSwapPosition; ++idInPositions; } return swaps; } int main() { int n; gen(4); gen(7); while (cin >> n) { vector<int> seq(n); for (int i = 0; i < seq.size(); ++i) { scanf( %d , &seq[i]); } vector<pair<int, int> > res = solve(seq); if (fail) { cout << -1 << endl; } else { cout << res.size() << endl; for (int i = 0; i < res.size(); ++i) { printf( %d %d n , res[i].first + 1, res[i].second + 1); } } cout << endl; } return 0; }
|
`timescale 1ns/1ns
module ddc_chain_tb();
reg clk, rst;
initial rst = 1;
initial #1000 rst = 0;
initial clk = 0;
always #5 clk = ~clk;
initial $dumpfile("ddc_chain_tb.vcd");
initial $dumpvars(0,ddc_chain_tb);
reg signed [23:0] adc_in;
wire signed [15:0] adc_out_i, adc_out_q;
always @(posedge clk)
begin
$display(adc_in);
$display(adc_out_i);
$display(adc_out_q);
end
reg run;
reg set_stb;
reg [7:0] set_addr;
reg [31:0] set_data;
ddc_chain #(.BASE(0)) ddc_chain
(.clk(clk),.rst(rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.adc_i(adc_in), .adc_ovf_i(0),
.adc_q(0), .adc_ovf_q(0),
.sample({adc_out_i,adc_out_q}),
.run(run), .strobe(), .debug());
initial
begin
run <= 0;
@(negedge rst);
@(posedge clk);
set_addr <= 1;
set_data <= {16'd64,16'd64}; // set gains
set_stb <= 1;
@(posedge clk);
set_addr <= 2;
set_data <= {16'd0,8'd3,8'd1}; // set decim
set_stb <= 1;
@(posedge clk);
set_addr <= 0;
//set_data <= {32'h0000_0000};
set_data <= {32'h01CA_C083}; // 700 kHz
set_stb <= 1;
@(posedge clk);
set_stb <= 0;
@(posedge clk);
run <= 1;
end
always @(posedge clk)
//adc_in <= 24'd1000000;
adc_in <= 24'h80_0000;
/*
always @(posedge clk)
if(rst)
adc_in <= 0;
else
adc_in <= adc_in + 4;
//adc_in <= (($random % 473) + 23)/4;
*/
endmodule // ddc_chain_tb
|
`timescale 1 ps / 1 ps
`include "ov7670_marker_tracker_ip_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module ov7670_marker_tracker_ip_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
task automatic COMPARE_LITE_DATA;
input expected;
input actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
$stop;
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB4_S16 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_32x24(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 24;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
wire [31:24] unconnected;
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({3'h0, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({3'h0, addr}),
.DI({8'h00, di[23:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[23:16]})
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB4_S16
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A22O_PP_BLACKBOX_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_SYMBOL_V
/**
* lpflow_inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_SYMBOL_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always @ (event_expression) reg_lvalue = boolean_expr ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1,value2;
initial
begin
# 1;
if(value1 != 4'bxxxx)
$display("FAILED - 3.1.4I - initial value not xxxx;\n");
value2 = 4'b1;
#10 ;
if(value1 != 4'h5)
$display("FAILED - 3.1.4I - always @ (event_expression) reg_lvalue = boolean_expr;\n");
value2 = 4'b0;
#10 ;
if(value1 != 4'hA)
$display("FAILED - 3.1.4I - always @ (event_expression) reg_lvalue = boolean_expr;\n");
else
begin
$display("PASSED\n");
end
$finish;
end
always # 10 value1 = ~value1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(NULL), cout.tie(NULL); int a, b, c; cin >> a >> b >> c; cout << ((a + c - 1) * (b + c - 1) - c * (c - 1)) << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O21AI_PP_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21AI_PP_SYMBOL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_reader_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Reads data from the scatter gather list buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGR64_RD_0 2'b01
`define S_SGR64_RD_1 2'b11
`define S_SGR64_RD_WAIT 2'b10
`define S_SGR64_CAP_0 2'b00
`define S_SGR64_CAP_1 2'b01
`define S_SGR64_CAP_RDY 2'b10
`timescale 1ns/1ns
module sg_list_reader_64 #(
parameter C_DATA_WIDTH = 9'd64
)
(
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output VALID, // Scatter gather element data is valid
output EMPTY, // Scatter gather elements empty
input REN, // Scatter gather element data read enable
output [63:0] ADDR, // Scatter gather element address
output [31:0] LEN // Scatter gather element length (in words)
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rRdState=`S_SGR64_RD_0, _rRdState=`S_SGR64_RD_0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rCapState=`S_SGR64_CAP_0, _rCapState=`S_SGR64_CAP_0;
reg [C_DATA_WIDTH-1:0] rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rLen=0, _rLen=0;
reg rFifoValid=0, _rFifoValid=0;
reg rDataValid=0, _rDataValid=0;
assign BUF_DATA_REN = rRdState[0]; // Not S_SGR64_RD_WAIT
assign VALID = rCapState[1]; // S_SGR64_CAP_RDY
assign EMPTY = (BUF_DATA_EMPTY & rRdState[0]); // Not S_SGR64_RD_WAIT
assign ADDR = rAddr;
assign LEN = rLen;
// Capture address and length as it comes out of the FIFO
always @ (posedge CLK) begin
rRdState <= #1 (RST ? `S_SGR64_RD_0 : _rRdState);
rCapState <= #1 (RST ? `S_SGR64_CAP_0 : _rCapState);
rData <= #1 _rData;
rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
end
always @ (*) begin
_rRdState = rRdState;
_rCapState = rCapState;
_rAddr = rAddr;
_rLen = rLen;
_rData = BUF_DATA;
_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
_rDataValid = rFifoValid;
case (rCapState)
`S_SGR64_CAP_0: begin
if (rDataValid) begin
_rAddr = rData;
_rCapState = `S_SGR64_CAP_1;
end
end
`S_SGR64_CAP_1: begin
if (rDataValid) begin
_rLen = rData[31:0];
_rCapState = `S_SGR64_CAP_RDY;
end
end
`S_SGR64_CAP_RDY: begin
if (REN)
_rCapState = `S_SGR64_CAP_0;
end
default: begin
_rCapState = `S_SGR64_CAP_0;
end
endcase
case (rRdState)
`S_SGR64_RD_0: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR64_RD_1;
end
`S_SGR64_RD_1: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR64_RD_WAIT;
end
`S_SGR64_RD_WAIT: begin // Wait for the data to be consumed
if (REN)
_rRdState = `S_SGR64_RD_0;
end
default: begin
_rRdState = `S_SGR64_RD_0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s; scanf( %d %d , &n, &s); long long arr[n]; for (int i = 0; i < n; i++) scanf( %lld , &arr[i]); sort(arr, arr + n); long long val = arr[n / 2]; long long cnt = abs(s - val); for (int i = 0; i < (n / 2); i++) { if (arr[i] > s) { cnt += abs(arr[i] - s); } } for (int i = (n / 2) + 1; i < n; i++) { if (arr[i] < s) { cnt += abs(arr[i] - s); } } cout << cnt << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } template <typename T> void Print(T a[], T n) { for (int i = 0; i < n; i++) { cout << a[i] << ; } cout << endl; } void solve() { int n; cin >> n; string s, t; cin >> s >> t; if (s == t) { cout << 0 << n ; return; } int same1 = 0, diff1 = 0, same = 0; for (int i = 0; i < n; i++) { if (s[i] == t[i]) { same++; if (s[i] == 1 ) same1++; } else { if (s[i] == 1 ) diff1++; } } int diff = n - same; if (same == n) { cout << 0 << n ; return; } int ans = INT_MAX; if (same1 - 1 == same - same1) { ans = min(ans, same); } if (diff1 == diff - diff1) { ans = min(ans, diff); } if (ans != INT_MAX) cout << ans << n ; else cout << -1 << n ; } void solve1() { int n; cin >> n; string s, t; cin >> s >> t; if (s == t) { cout << 0 << n ; return; } int same1 = 0, diff1 = 0, same = 0; for (int i = 0; i < n; i++) { if (s[i] == t[i]) { same++; if (s[i] == 1 ) same1++; } else { if (s[i] == 1 ) diff1++; } } int diff = n - same; int ans = INT_MAX; if (diff % 2 == 0) { int one = (diff + 1) / 2; if (diff1 == one) { ans = min(ans, diff); } } if (same % 2 != 0) { int one = (same + 1) / 2; if (same1 == one) { ans = min(ans, same); } } if (ans == INT_MAX) cout << -1 << n ; else cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false), cin.tie(NULL); int t; cin >> t; while (t--) solve1(); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/18/2016 10:56:00 PM
// Design Name:
// Module Name: merge
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "global.vh"
`ifdef CARPOOL_LK_AHEAD_RC_PS
`define HAS_MERGE
`endif
`ifdef CARPOOL
`define HAS_MERGE
`endif
`ifdef HAS_MERGE
module merge(
hs_0,
srcList_0,
addr_0, //could be flowID
dst_0,
flitID_0,
hs_1,
srcList_1,
addr_1, //could be flowID
dst_1,
flitID_1,
hs_2,
srcList_2,
addr_2, //could be flowID
dst_2,
flitID_2,
hs_3,
srcList_3,
addr_3, //could be flowID
dst_3,
flitID_3,
hs_4,
srcList_4,
addr_4, //could be flowID
dst_4,
flitID_4,
kill,
srcList_new_0,
srcList_new_1,
srcList_new_2,
srcList_new_3,
srcList_new_4
);
input hs_0, hs_1, hs_2, hs_3, hs_4;
input [`SRC_LIST_WIDTH-1:0] srcList_0, srcList_1, srcList_2, srcList_3, srcList_4;
input [`MEM_ADDR_WIDTH-1:0] addr_0, addr_1, addr_2, addr_3, addr_4;
input [`DST_WIDTH-1:0] dst_0, dst_1, dst_2, dst_3, dst_4;
input [`NUM_FLIT_WDITH-1:0] flitID_0, flitID_1, flitID_2, flitID_3, flitID_4;
output [`NUM_PORT-1:0] kill;
output [`SRC_LIST_WIDTH-1:0] srcList_new_0, srcList_new_1, srcList_new_2, srcList_new_3, srcList_new_4;
// merge[i][j] = 1 indicate flit at port j merge with port i
wire [`NUM_PORT-1:0] merge [0:`NUM_PORT-2];
assign merge[0][0] = 1'b0;
assign merge[0][1] = hs_0 && hs_1 && (addr_0 == addr_1) && (dst_0 == dst_1) && (flitID_0 == flitID_1);
assign merge[0][2] = hs_0 && hs_2 && (addr_0 == addr_2) && (dst_0 == dst_2) && (flitID_0 == flitID_2);
assign merge[0][3] = hs_0 && hs_3 && (addr_0 == addr_3) && (dst_0 == dst_3) && (flitID_0 == flitID_3);
assign merge[0][4] = hs_0 && hs_4 && (addr_0 == addr_4) && (dst_0 == dst_4) && (flitID_0 == flitID_4);
assign merge[1][0] = 1'b0;
assign merge[1][1] = 1'b0;
assign merge[1][2] = hs_1 && hs_2 && (addr_1 == addr_2) && (dst_1 == dst_2) && (flitID_1 == flitID_2);
assign merge[1][3] = hs_1 && hs_3 && (addr_1 == addr_3) && (dst_1 == dst_3) && (flitID_1 == flitID_3);
assign merge[1][4] = hs_1 && hs_4 && (addr_1 == addr_4) && (dst_1 == dst_4) && (flitID_1 == flitID_4);
assign merge[2][0] = 1'b0;
assign merge[2][1] = 1'b0;
assign merge[2][2] = 1'b0;
assign merge[2][3] = hs_2 && hs_3 && (addr_2 == addr_3) && (dst_2 == dst_3) && (flitID_2 == flitID_3);
assign merge[2][4] = hs_2 && hs_4 && (addr_2 == addr_4) && (dst_2 == dst_4) && (flitID_2 == flitID_4);
assign merge[3][0] = 1'b0;
assign merge[3][1] = 1'b0;
assign merge[3][2] = 1'b0;
assign merge[3][3] = 1'b0;
assign merge[3][4] = hs_3 && hs_4 && (addr_3 == addr_4) && (dst_3 == dst_4) && (flitID_3 == flitID_4);
assign kill [0] = 1'b0;
assign kill [1] = merge[0][1];
assign kill [2] = merge[0][2] | merge[1][2];
assign kill [3] = merge[0][3] | merge[1][3] | merge[2][3];
assign kill [4] = merge[0][4] | merge[1][4] | merge[2][4] | merge[3][4];
// if a flit is merged with any other flit, use the updated srcList.
assign srcList_new_0 = merge[0][1] ? (srcList_0 | srcList_1) :
merge[0][2] ? (srcList_0 | srcList_2) :
merge[0][3] ? (srcList_0 | srcList_3) :
merge[0][4] ? (srcList_0 | srcList_4) : srcList_0;
assign srcList_new_1 = merge[1][2] ? (srcList_1 | srcList_2) :
merge[1][3] ? (srcList_1 | srcList_3) :
merge[1][4] ? (srcList_1 | srcList_4) : srcList_1;
assign srcList_new_2 = merge[2][3] ? (srcList_2 | srcList_3) :
merge[2][4] ? (srcList_2 | srcList_4) : srcList_2;
assign srcList_new_3 = merge[3][4] ? (srcList_3 | srcList_4) : srcList_3;
assign srcList_new_4 = srcList_4;
endmodule
`endif // Merge
|
#include <bits/stdc++.h> using namespace std; int ans; int father[1100]; int find(int x) { if (father[x] == x) return x; father[x] = find(father[x]); return father[x]; } bool Union(int x, int y) { int f1 = find(x); int f2 = find(y); if (f1 == f2) return false; if (f1 < f2) father[f1] = f2; else father[f2] = f1; ans++; return true; } int n, m; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) father[i] = i; for (int i = 1; i <= m; i++) { int x, y; cin >> x >> y; if (!Union(x, y)) { cout << no << endl; return 0; } } if (m != n - 1) cout << no << endl; else cout << yes << endl; return 0; }
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_ddrc.v
*
* Date : 2012-11
*
* Description : Module that acts as controller for sparse memory (DDR).
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_ddrc(
rstn,
sw_clk,
/* Goes to port 0 of DDR */
ddr_wr_ack_port0,
ddr_wr_dv_port0,
ddr_rd_req_port0,
ddr_rd_dv_port0,
ddr_wr_addr_port0,
ddr_wr_data_port0,
ddr_wr_bytes_port0,
ddr_rd_addr_port0,
ddr_rd_data_port0,
ddr_rd_bytes_port0,
ddr_wr_qos_port0,
ddr_rd_qos_port0,
/* Goes to port 1 of DDR */
ddr_wr_ack_port1,
ddr_wr_dv_port1,
ddr_rd_req_port1,
ddr_rd_dv_port1,
ddr_wr_addr_port1,
ddr_wr_data_port1,
ddr_wr_bytes_port1,
ddr_rd_addr_port1,
ddr_rd_data_port1,
ddr_rd_bytes_port1,
ddr_wr_qos_port1,
ddr_rd_qos_port1,
/* Goes to port2 of DDR */
ddr_wr_ack_port2,
ddr_wr_dv_port2,
ddr_rd_req_port2,
ddr_rd_dv_port2,
ddr_wr_addr_port2,
ddr_wr_data_port2,
ddr_wr_bytes_port2,
ddr_rd_addr_port2,
ddr_rd_data_port2,
ddr_rd_bytes_port2,
ddr_wr_qos_port2,
ddr_rd_qos_port2,
/* Goes to port3 of DDR */
ddr_wr_ack_port3,
ddr_wr_dv_port3,
ddr_rd_req_port3,
ddr_rd_dv_port3,
ddr_wr_addr_port3,
ddr_wr_data_port3,
ddr_wr_bytes_port3,
ddr_rd_addr_port3,
ddr_rd_data_port3,
ddr_rd_bytes_port3,
ddr_wr_qos_port3,
ddr_rd_qos_port3
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
output ddr_wr_ack_port0;
input ddr_wr_dv_port0;
input ddr_rd_req_port0;
output ddr_rd_dv_port0;
input[addr_width-1:0] ddr_wr_addr_port0;
input[max_burst_bits-1:0] ddr_wr_data_port0;
input[max_burst_bytes_width:0] ddr_wr_bytes_port0;
input[addr_width-1:0] ddr_rd_addr_port0;
output[max_burst_bits-1:0] ddr_rd_data_port0;
input[max_burst_bytes_width:0] ddr_rd_bytes_port0;
input [axi_qos_width-1:0] ddr_wr_qos_port0;
input [axi_qos_width-1:0] ddr_rd_qos_port0;
output ddr_wr_ack_port1;
input ddr_wr_dv_port1;
input ddr_rd_req_port1;
output ddr_rd_dv_port1;
input[addr_width-1:0] ddr_wr_addr_port1;
input[max_burst_bits-1:0] ddr_wr_data_port1;
input[max_burst_bytes_width:0] ddr_wr_bytes_port1;
input[addr_width-1:0] ddr_rd_addr_port1;
output[max_burst_bits-1:0] ddr_rd_data_port1;
input[max_burst_bytes_width:0] ddr_rd_bytes_port1;
input[axi_qos_width-1:0] ddr_wr_qos_port1;
input[axi_qos_width-1:0] ddr_rd_qos_port1;
output ddr_wr_ack_port2;
input ddr_wr_dv_port2;
input ddr_rd_req_port2;
output ddr_rd_dv_port2;
input[addr_width-1:0] ddr_wr_addr_port2;
input[max_burst_bits-1:0] ddr_wr_data_port2;
input[max_burst_bytes_width:0] ddr_wr_bytes_port2;
input[addr_width-1:0] ddr_rd_addr_port2;
output[max_burst_bits-1:0] ddr_rd_data_port2;
input[max_burst_bytes_width:0] ddr_rd_bytes_port2;
input[axi_qos_width-1:0] ddr_wr_qos_port2;
input[axi_qos_width-1:0] ddr_rd_qos_port2;
output ddr_wr_ack_port3;
input ddr_wr_dv_port3;
input ddr_rd_req_port3;
output ddr_rd_dv_port3;
input[addr_width-1:0] ddr_wr_addr_port3;
input[max_burst_bits-1:0] ddr_wr_data_port3;
input[max_burst_bytes_width:0] ddr_wr_bytes_port3;
input[addr_width-1:0] ddr_rd_addr_port3;
output[max_burst_bits-1:0] ddr_rd_data_port3;
input[max_burst_bytes_width:0] ddr_rd_bytes_port3;
input[axi_qos_width-1:0] ddr_wr_qos_port3;
input[axi_qos_width-1:0] ddr_rd_qos_port3;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_wr_4 ddr_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_wr_qos_port0),
.qos2(ddr_wr_qos_port1),
.qos3(ddr_wr_qos_port2),
.qos4(ddr_wr_qos_port3),
.prt_dv1(ddr_wr_dv_port0),
.prt_dv2(ddr_wr_dv_port1),
.prt_dv3(ddr_wr_dv_port2),
.prt_dv4(ddr_wr_dv_port3),
.prt_data1(ddr_wr_data_port0),
.prt_data2(ddr_wr_data_port1),
.prt_data3(ddr_wr_data_port2),
.prt_data4(ddr_wr_data_port3),
.prt_addr1(ddr_wr_addr_port0),
.prt_addr2(ddr_wr_addr_port1),
.prt_addr3(ddr_wr_addr_port2),
.prt_addr4(ddr_wr_addr_port3),
.prt_bytes1(ddr_wr_bytes_port0),
.prt_bytes2(ddr_wr_bytes_port1),
.prt_bytes3(ddr_wr_bytes_port2),
.prt_bytes4(ddr_wr_bytes_port3),
.prt_ack1(ddr_wr_ack_port0),
.prt_ack2(ddr_wr_ack_port1),
.prt_ack3(ddr_wr_ack_port2),
.prt_ack4(ddr_wr_ack_port3),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd_4 ddr_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ddr_rd_qos_port0),
.qos2(ddr_rd_qos_port1),
.qos3(ddr_rd_qos_port2),
.qos4(ddr_rd_qos_port3),
.prt_req1(ddr_rd_req_port0),
.prt_req2(ddr_rd_req_port1),
.prt_req3(ddr_rd_req_port2),
.prt_req4(ddr_rd_req_port3),
.prt_data1(ddr_rd_data_port0),
.prt_data2(ddr_rd_data_port1),
.prt_data3(ddr_rd_data_port2),
.prt_data4(ddr_rd_data_port3),
.prt_addr1(ddr_rd_addr_port0),
.prt_addr2(ddr_rd_addr_port1),
.prt_addr3(ddr_rd_addr_port2),
.prt_addr4(ddr_rd_addr_port3),
.prt_bytes1(ddr_rd_bytes_port0),
.prt_bytes2(ddr_rd_bytes_port1),
.prt_bytes3(ddr_rd_bytes_port2),
.prt_bytes4(ddr_rd_bytes_port3),
.prt_dv1(ddr_rd_dv_port0),
.prt_dv2(ddr_rd_dv_port1),
.prt_dv3(ddr_rd_dv_port2),
.prt_dv4(ddr_rd_dv_port3),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_sparse_mem ddr();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ddr.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ddr.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
module traffic_light_controller ( clk, reset, north_south, east_west );
output [2:0] north_south;
output [2:0] east_west;
input clk, reset;
wire N80, N81, N82, N83, N85, N96, n40, n41, n42, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
n78, n79, n80, n81, n82, n83;
wire [2:0] traffic_light_state;
assign north_south[0] = N85;
assign east_west[0] = N96;
DFF_X1 \counter_reg[0] ( .D(N80), .CK(clk), .Q(n81), .QN(n50) );
DFF_X1 \counter_reg[1] ( .D(N81), .CK(clk), .Q(n82), .QN(n46) );
DFF_X1 \counter_reg[2] ( .D(N82), .CK(clk), .QN(n45) );
DFF_X1 \counter_reg[3] ( .D(N83), .CK(clk), .Q(n83) );
DFF_X1 \traffic_light_state_reg[0] ( .D(n42), .CK(clk), .Q(
traffic_light_state[0]), .QN(n48) );
DFF_X1 \traffic_light_state_reg[2] ( .D(n41), .CK(clk), .Q(
traffic_light_state[2]), .QN(n47) );
DFF_X1 \traffic_light_state_reg[1] ( .D(n40), .CK(clk), .Q(
traffic_light_state[1]), .QN(n49) );
NAND2_X1 U51 ( .A1(n51), .A2(n52), .ZN(n42) );
INV_X1 U52 ( .A(N96), .ZN(n52) );
MUX2_X1 U53 ( .A(n53), .B(n54), .S(traffic_light_state[0]), .Z(n51) );
NOR2_X1 U54 ( .A1(n53), .A2(n55), .ZN(n54) );
OAI22_X1 U55 ( .A1(n47), .A2(n56), .B1(reset), .B2(n57), .ZN(n41) );
AOI21_X1 U56 ( .B1(n58), .B2(n59), .A(N96), .ZN(n57) );
NOR2_X1 U57 ( .A1(traffic_light_state[0]), .A2(n53), .ZN(n58) );
OAI21_X1 U58 ( .B1(n53), .B2(n60), .A(n61), .ZN(n40) );
OAI21_X1 U59 ( .B1(n53), .B2(n48), .A(traffic_light_state[1]), .ZN(n61) );
AOI211_X1 U60 ( .C1(traffic_light_state[2]), .C2(n48), .A(n55), .B(
north_south[1]), .ZN(n60) );
OR2_X1 U61 ( .A1(reset), .A2(east_west[1]), .ZN(n55) );
INV_X1 U62 ( .A(n56), .ZN(n53) );
OAI211_X1 U63 ( .C1(n62), .C2(n63), .A(n64), .B(n65), .ZN(n56) );
AOI211_X1 U64 ( .C1(traffic_light_state[2]), .C2(n66), .A(reset), .B(n67),
.ZN(n65) );
AND3_X1 U65 ( .A1(n83), .A2(n68), .A3(N85), .ZN(n67) );
OAI21_X1 U66 ( .B1(n49), .B2(n69), .A(traffic_light_state[0]), .ZN(n66) );
AOI22_X1 U67 ( .A1(east_west[1]), .A2(n70), .B1(n59), .B2(n81), .ZN(n64) );
INV_X1 U68 ( .A(north_south[1]), .ZN(n63) );
NOR2_X1 U69 ( .A1(n71), .A2(n72), .ZN(N83) );
XNOR2_X1 U70 ( .A(n83), .B(n68), .ZN(n71) );
AOI211_X1 U71 ( .C1(n45), .C2(n62), .A(n72), .B(n68), .ZN(N82) );
NOR2_X1 U72 ( .A1(n45), .A2(n62), .ZN(n68) );
NOR2_X1 U73 ( .A1(n73), .A2(n72), .ZN(N81) );
INV_X1 U74 ( .A(n74), .ZN(n72) );
AOI21_X1 U75 ( .B1(n75), .B2(n76), .A(reset), .ZN(n74) );
NAND2_X1 U76 ( .A1(n50), .A2(n59), .ZN(n75) );
AOI21_X1 U78 ( .B1(n81), .B2(n46), .A(n70), .ZN(n73) );
AOI211_X1 U79 ( .C1(n76), .C2(n77), .A(reset), .B(n81), .ZN(N80) );
NAND2_X1 U80 ( .A1(traffic_light_state[1]), .A2(n47), .ZN(n77) );
AOI211_X1 U81 ( .C1(n62), .C2(north_south[1]), .A(N85), .B(n78), .ZN(n76) );
INV_X1 U82 ( .A(n79), .ZN(n78) );
AOI22_X1 U83 ( .A1(N96), .A2(n69), .B1(east_west[1]), .B2(n80), .ZN(n79) );
INV_X1 U84 ( .A(n70), .ZN(n80) );
NOR2_X1 U85 ( .A1(n46), .A2(n81), .ZN(n70) );
NOR2_X1 U86 ( .A1(east_west[2]), .A2(traffic_light_state[1]), .ZN(
east_west[1]) );
NAND4_X1 U87 ( .A1(n83), .A2(n46), .A3(n45), .A4(n50), .ZN(n69) );
NOR2_X1 U88 ( .A1(n49), .A2(east_west[2]), .ZN(N96) );
NAND2_X1 U89 ( .A1(traffic_light_state[2]), .A2(traffic_light_state[0]),
.ZN(east_west[2]) );
NOR2_X1 U90 ( .A1(north_south[2]), .A2(traffic_light_state[0]), .ZN(N85) );
NOR2_X1 U91 ( .A1(n48), .A2(north_south[2]), .ZN(north_south[1]) );
NAND2_X1 U92 ( .A1(n47), .A2(n49), .ZN(north_south[2]) );
NAND2_X1 U93 ( .A1(n81), .A2(n82), .ZN(n62) );
endmodule
|
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 15.0.2 Build 153 07/15/2015 SJ Web Edition"
// CREATED "Sun Oct 25 12:01:05 2015"
module vga_export(
CLOCK_50,
KEY,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HSYNC,
VGA_VSYNC
);
input wire CLOCK_50;
input wire [0:0] KEY;
output wire VGA_RED;
output wire VGA_GREEN;
output wire VGA_BLUE;
output wire VGA_HSYNC;
output wire VGA_VSYNC;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire [15:0] SYNTHESIZED_WIRE_4;
wire [10:0] SYNTHESIZED_WIRE_5;
wire [10:0] SYNTHESIZED_WIRE_6;
wire [15:0] SYNTHESIZED_WIRE_7;
vga_bw b2v_inst(
.CLOCK_PIXEL(SYNTHESIZED_WIRE_0),
.RESET(SYNTHESIZED_WIRE_9),
.PIXEL(SYNTHESIZED_WIRE_2),
.VGA_RED(VGA_RED),
.VGA_GREEN(VGA_GREEN),
.VGA_BLUE(VGA_BLUE),
.VGA_HS(VGA_HSYNC),
.VGA_VS(VGA_VSYNC),
.PIXEL_H(SYNTHESIZED_WIRE_5),
.PIXEL_V(SYNTHESIZED_WIRE_6));
frame_buffer b2v_inst1(
.clk(CLOCK_50),
.load(SYNTHESIZED_WIRE_3),
.data_in(SYNTHESIZED_WIRE_4),
.vga_h(SYNTHESIZED_WIRE_5),
.vga_v(SYNTHESIZED_WIRE_6),
.write_address(SYNTHESIZED_WIRE_7),
.pixel_out(SYNTHESIZED_WIRE_2));
image_generator b2v_inst5(
.clk(CLOCK_50),
.reset(SYNTHESIZED_WIRE_9),
.load(SYNTHESIZED_WIRE_3),
.address(SYNTHESIZED_WIRE_7),
.out(SYNTHESIZED_WIRE_4));
clock_25 b2v_pixel_clock_25(
.CLOCK_50(CLOCK_50),
.CLOCK_25(SYNTHESIZED_WIRE_0));
assign SYNTHESIZED_WIRE_9 = ~KEY;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:10:30 02/08/2016
// Design Name:
// Module Name: Hazard_unit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Hazard_unit(
//DATA HAZARDS
//datos
input wire [4:0] RsE, //rs en etapa ex
input wire [4:0] RtE, //rt en etapa ex
input wire [4:0] WriteRegM,
input wire [4:0] WriteRegWB,
//control
input wire RegWriteM,
input wire RegWriteWB,
//outputs
output reg [1:0] ForwardAE,
output reg [1:0] ForwardBE,
//LWSTALL
//datos
input wire [4:0] RsD, //rs en etapa decode
input wire [4:0] RtD, //rt en etapa decode, tambien usa RtE
//RtE, ya esta definido
//control
input wire MemtoRegEX, //para saber si es una lw
//RegWriteM, ya esta definido
//RegWriteWB, ya esta definido
//outputs
output reg stallF,
output reg stallD,
output reg flushIDEX,
//ForwardAE, ya esta definido
//ForwardBE, ya esta definido
//JUMP
//data
input wire [5:0] Opcode,
input wire [5:0] Func,
//output
output reg flushIFID,
//BRANCH
//data
//RsD, ya esta definido
//RtD, ya esta definido
input wire [4:0] WriteRegEX,
//WriteRegE, ya esta definido
//control
//RegWriteM, ya esta definido
input wire MemtoRegM,
input wire RegWriteE,
input wire branch_ID,
input wire branch_taken_ID,
//output
//flushIDEX, ya esta definido
output reg ForwardAD,
output reg ForwardBD
);
//LW Y BRANCH STALL
reg lwstall;
reg branchstall;
always@(*)
begin
lwstall = ((RtE == RsD) | (RtE == RtD)) & MemtoRegEX;
branchstall = (branch_ID & RegWriteE & (WriteRegEX == RsD | WriteRegEX == RtD)) |
(branch_ID & MemtoRegM & (WriteRegM == RsD | WriteRegM == RtD));
stallF = (lwstall | branchstall);
stallD = (lwstall | branchstall);
flushIDEX = (lwstall | branchstall);
end
//Forwarding
always@(*)
begin
if ((RsE != 5'b00000) & (RsE == WriteRegM) & RegWriteM)
ForwardAE = 2'b10;
else if ((RsE != 5'b00000) & (RsE == WriteRegWB) & RegWriteWB)
ForwardAE = 2'b01;
else
ForwardAE = 2'b00;
if ((RtE != 5'b00000) & (RtE == WriteRegM) & RegWriteM)
ForwardBE = 2'b10;
else if ((RtE != 5'b00000) & (RtE == WriteRegWB) & RegWriteWB)
ForwardBE = 2'b01;
else
ForwardBE = 2'b00;
end
//Jumps y branches
always@(*)
begin
if ((Opcode == 6'b000010) | //J
(Opcode == 6'b000011) | //JAL
(((Opcode == 6'b000100) |(Opcode == 6'b000101)) & branch_taken_ID)| //BEQ BNE
(Opcode == 6'b000000 & Func == 6'b001000) |// JR
(Opcode == 6'b000000 & Func == 6'b001001) )// JALR
flushIFID = 1'b1;
else
flushIFID = 1'b0;
if (stallD == 1'b1) //si hay un stall no se flushea
flushIFID = 1'b0;
end
always@(*)
begin
if ((RsD != 0) & (RsD == WriteRegM | WriteRegEX) & RegWriteM)
ForwardAD = 1'b1;
else
ForwardAD = 1'b0;
if ((RtD != 0) & (RtD == WriteRegM | WriteRegEX) & RegWriteM)
ForwardBD = 1'b1;
else
ForwardBD = 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, M; vector<pair<int, int> > V; int main(int argc, const char *argv[]) { cin >> N >> M; for (int i = 0, x, y; i < M; i++) { cin >> x >> y; V.push_back(pair<int, int>(x, y)); } sort(V.begin(), V.end()); vector<pair<int, int> > currI; currI.push_back(pair<int, int>(1, 1)); int currRow = 0; for (int i = 0; i < V.size();) { pair<int, int> p = V[i]; vector<pair<int, int> > newI; if (p.first > currRow + 1 && currI.size()) { int left = currI[0].first; currI.clear(); currI.push_back(pair<int, int>(left, N)); } currRow = p.first; vector<pair<int, int> > temp; int last = 0; while (i < V.size() && V[i].first == p.first) { temp.push_back(pair<int, int>(last + 1, V[i].second - 1)); last = V[i].second; i++; } temp.push_back(pair<int, int>(last + 1, N)); int j = 0; for (auto x : temp) { while (j < currI.size() && currI[j].second < x.first) j++; if (j < currI.size()) { int x1 = max(x.first, currI[j].first), x2 = x.second; if (x2 >= x1) { newI.push_back(pair<int, int>(x1, x2)); } } } currI = newI; } bool poss = false; if (currI.size() > 0) { pair<int, int> l = currI[currI.size() - 1]; poss = (currRow < N && l.second <= N); poss = poss || (currRow == N && l.second == N); } if (poss) { cout << 2 * (N - 1) << endl; } else { cout << -1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, i, j = 0, c1 = 0, c0 = 0; string a, b; vector<long long int> v0, v1; cin >> n; cin >> a; cin >> b; for (i = 0; i < n; i++) { if (b[i] == 0 ) { if (a[i] == 1 ) v1.push_back(i); else v0.push_back(i); } if (a[i] == 0 ) c0++; else c1++; } j = v0.size() * c1; j += (v1.size() * c0); j -= (v1.size() * v0.size()); cout << j << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int lim = 1e6; int inf = 1e8; void err(istream_iterator<string> it) { cerr << endl; } template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << t ; err(++it, args...); } template <typename T1, typename T2> ostream& operator<<(ostream& c, pair<T1, T2>& v) { c << ( << v.first << , << v.second << ) ; return c; } template <template <class...> class TT, class... T> ostream& operator<<(ostream& out, TT<T...>& c) { out << { ; for (auto& x : c) out << x << ; out << } ; return out; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; int ans = 0; for (int i = 6; i >= 0; i--) { int k = pow(2, i); int j = 0; vector<int> a, b; for (int r = 1; r <= n; r++) { if ((r / k) % 2 == 0) { a.push_back(r); } else { b.push_back(r); } } if (a.size() == 0 or b.size() == 0) continue; cout << a.size() << << b.size() << ; for (int j = 0; j < a.size(); j++) { cout << a[j] << ; } for (int j = 0; j < b.size(); j++) { cout << b[j] << ; } cout << endl; int tmpans; cin >> tmpans; ans = max(ans, tmpans); } cout << -1 << << ans << endl; } }
|
/*
* File: pippo_timer.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
Ò»£¬ÊµÏÖPowerPC Embedded ArchitectureµÄ¶þ¸öÎïÀí¼ÆÊýÆ÷ºÍÈý¸ö¶¨Ê±Æ÷Âß¼£º
ÎïÀí¼ÆÊýÆ÷Time Base£º64룬µÝÔö£»TBµÄeventÓУº
Watchdog events: TBL[28], TBL[24], TBL[20], TBL[16];
FIT events: TBL[20], TBL[16], TBL[12], TBL[8];
ÎïÀí¼ÆÊýÆ÷PIT£º32룬µÝ¼õ£»µ±¼ì²âµ½È«Áãʱ£¬·¢³öPIT event
¶þ£¬ÊµÏÖPowerPC Embedded ArchitectureµÄ¶¨Ê±Æ÷¼Ä´æÆ÷ºÍÏà¹ØÂß¼
Timer Status Register(TSR)
Timer Control Register(TCR)
Task.I
[TBV]tsr[enw]ÔÚÿ´Îwatchdog timeout·¢ÉúʱÖÃÆð£¿
[TBD]tsr[pis]ÊÇÔÚÖжϷ¢Éúºó²ÅÖÃÆ𣿻¹ÊÇ·¢³öÖжÏÇëÇó¼´¿É£¿
²Î¿¼ÖжÏSPECµÄTimerÏà¹Ø²¿·Ö£¬È·¶¨eventºÍtsrÉèÖõÈʱÐò
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module pippo_timer(
clk, rst,
tbl, tbu, pit, tsr, tcr,
tbl_we, tbu_we, pit_we, tsr_we, tcr_we,
spr_dat_i,
sig_pit, sig_fit, sig_watchdog,
rqt_core_rst, rqt_sys_rst, rqt_chip_rst
);
input clk;
input rst;
// spr write access
input tbl_we;
input tbu_we;
input pit_we;
input tsr_we;
input tcr_we;
input [31:0] spr_dat_i;
// spr read access
output [31:0] tbl;
output [31:0] tbu;
output [31:0] pit;
output [31:0] tsr;
output [31:0] tcr;
// interrupt request
output sig_fit;
output sig_pit;
output sig_watchdog;
// reset request
output rqt_core_rst;
output rqt_sys_rst;
output rqt_chip_rst;
//
// physical counter and control register
//
reg [32:0] tbl;
reg [31:0] tbu;
reg [31:0] pit;
reg [31:0] pit_lastload;
reg [31:0] tsr;
reg [31:0] tcr;
wire watchdog_timeout;
wire [1:0] event_watchdog_rst;
wire event_watchdog, event_pit, event_fit;
// tsr & tcr
wire [1:0] tsr_wrs;
wire tsr_enw, tsr_wis, tsr_pis, tsr_fis;
wire [1:0] tcr_wrc;
wire [1:0] tcr_wp;
wire [1:0] tcr_fp;
wire tcr_wie, tcr_pie, tcr_fie, tcr_are;
wire [32:0] tbl_new;
//
// timer status register
// note: tsr is set by hardware, read and clear(write-to-clear) by software
//
always @(posedge clk or `pippo_RST_EVENT rst)
if (rst == `pippo_RST_VALUE)
tsr <= 32'd0;
else if (tsr_we)
tsr <= tsr & ~spr_dat_i;
else
tsr <= {watchdog_timeout, event_watchdog, event_watchdog_rst, event_pit, event_fit, tsr[25:0]};
// tsr output
assign tsr_enw = tsr[`pippo_TSR_ENW_BITS]; // enable next watchdog
assign tsr_wis = tsr[`pippo_TSR_WIS_BITS]; // watchdog interrupt status
assign tsr_wrs = tsr[`pippo_TSR_WRS_BITS]; // watchdog reset status
assign tsr_pis = tsr[`pippo_TSR_PIS_BITS]; // pit interrupt status
assign tsr_fis = tsr[`pippo_TSR_FIS_BITS]; // fit interrupt status
//
// timer control register
// note: tcr_wrc can only be clear by rst
// [TBV] how about write to wrc twice by different value?
//
always @(posedge clk or `pippo_RST_EVENT rst)
if (rst == `pippo_RST_VALUE)
tcr <= 32'd0;
else if (tcr_we)
tcr <= {spr_dat_i[31:30], tcr_wrc | spr_dat_i[`pippo_TCR_WRC_BITS], spr_dat_i[27:0]};
assign tcr_wp = tcr[`pippo_TCR_WP_BITS]; // watchdog period
assign tcr_wrc = tcr[`pippo_TCR_WRC_BITS]; // watchdog reset control
assign tcr_wie = tcr[`pippo_TCR_WIE_BITS]; // watchdog interrupt enable
assign tcr_pie = tcr[`pippo_TCR_PIE_BITS]; // pit interrupt enable
assign tcr_fp = tcr[`pippo_TCR_FP_BITS]; // fit period
assign tcr_fie = tcr[`pippo_TCR_FIE_BITS]; // fit interrupt enable
assign tcr_are = tcr[`pippo_TCR_ARE_BITS]; // auto reload enable
//
// Time Base
//
assign tbl_new = tbl + 33'd1;
always @(posedge clk or `pippo_RST_EVENT rst)
if (rst == `pippo_RST_VALUE)
tbl <= 33'd0;
else if (tbl_we)
tbl <= {1'b0, spr_dat_i};
else
tbl <= tbl_new;
assign tbl_carry = tbl_new[32] ^ tbl[32];
always @(posedge clk or `pippo_RST_EVENT rst)
if (rst == `pippo_RST_VALUE)
tbu <= 32'd0;
else if (tbu_we)
tbu <= spr_dat_i;
else
tbu <= tbu + tbl_carry;
//
// watchdog timeout
//
assign watchdog_timeout =
((tcr_wp == 2'b00) & tbl[17]) | ((tcr_wp == 2'b01) & tbl[21]) |
((tcr_wp == 2'b10) & tbl[25]) | ((tcr_wp == 2'b11) & tbl[29]);
assign event_watchdog = watchdog_timeout & ~tsr_wis & tsr_enw; // [tbv]
assign sig_watchdog = watchdog_timeout & ~tsr_wis & tsr_enw & tcr_wie;
// watchdog reset logic
assign rqt_core_rst = watchdog_timeout & tsr_wis & tsr_enw & (tcr_wrc == 2'b01);
assign rqt_chip_rst = watchdog_timeout & tsr_wis & tsr_enw & (tcr_wrc == 2'b10);
assign rqt_sys_rst = watchdog_timeout & tsr_wis & tsr_enw & (tcr_wrc == 2'b11);
assign event_watchdog_rst[1] = rqt_sys_rst | rqt_chip_rst;
assign event_watchdog_rst[0] = rqt_core_rst | rqt_sys_rst;
//
// FIT
//
assign event_fit =
((tcr_fp == 2'b00) & tbl[9]) | ((tcr_fp == 2'b01) & tbl[13]) |
((tcr_fp == 2'b10) & tbl[17]) | ((tcr_fp == 2'b11) & tbl[21]);
assign sig_fit = event_fit & tcr_fie;
//
// PIT
//
always @(posedge clk or `pippo_RST_EVENT rst)
if (rst == `pippo_RST_VALUE)
pit_lastload <= 32'd0;
else if (pit_we)
pit_lastload <= spr_dat_i;
always @(posedge clk or `pippo_RST_EVENT rst)
if (rst == `pippo_RST_VALUE)
pit <= 32'd0;
else if (pit_we)
pit <= spr_dat_i;
else if (event_pit & tcr_are)
pit <= pit_lastload;
else if (|pit)
pit <= pit - 32'd1;
assign event_pit = ~(|pit[31:1]) & pit[0];
assign sig_pit = event_pit & tcr_pie;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_ctl_edgelogic.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_ctl_edgelogic(/*AUTOARG*/
// Outputs
ctl_pad_clk_so, to_pad,
// Inputs
clk, rst_l, ctl_pad_clk_se, ctl_pad_clk_si, data, testmode_l
);
//////////////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////////////
input clk;
input rst_l;
input testmode_l;
input ctl_pad_clk_se;
input ctl_pad_clk_si;
input data;
//////////////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////////////
output ctl_pad_clk_so;
output to_pad;
//////////////////////////////////////////////////////////////////////////
// CODE
//////////////////////////////////////////////////////////////////////////
// CREATING MUX FOR TEST CLOCK
wire tclk = testmode_l ? ~clk : clk;
// INSTANTIATING PAD LOGIC
dffrl_s #(1) flop_data(
.din(data),
.q(to_pad),
.rst_l(rst_l),
.clk(tclk), .si(ctl_pad_clk_si), .so(ctl_pad_clk_so), .se(ctl_pad_clk_se));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PS_TB_V
`define SKY130_FD_SC_MS__UDP_DFF_PS_TB_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_dff_ps.v"
module top();
// Inputs are registered
reg D;
reg SET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 D = 1'b1;
#80 SET = 1'b1;
#100 D = 1'b0;
#120 SET = 1'b0;
#140 SET = 1'b1;
#160 D = 1'b1;
#180 SET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__udp_dff$PS dut (.D(D), .SET(SET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PS_TB_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module converts video streams between RGB color formats. *
* *
******************************************************************************/
module niosII_system_video_rgb_resampler_0 (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 15;
parameter ODW = 29;
parameter IEW = 0;
parameter OEW = 1;
parameter ALPHA = 10'h3FF;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [ODW:0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign r = {stream_in_data[15:11], stream_in_data[15:11]};
assign g = {stream_in_data[10: 5], stream_in_data[10: 7]};
assign b = {stream_in_data[ 4: 0], stream_in_data[ 4: 0]};
assign a = ALPHA;
assign converted_data[29:20] = r[ 9: 0];
assign converted_data[19:10] = g[ 9: 0];
assign converted_data[ 9: 0] = b[ 9: 0];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
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