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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_4_V
`define SKY130_FD_SC_LP__CLKINV_4_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_4_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module reads and writes data to the RS232 connector on Altera's *
* DE-series Development and Education Boards. *
* *
******************************************************************************/
module niosII_system_rs232_0 (
// Inputs
clk,
reset,
address,
chipselect,
byteenable,
read,
write,
writedata,
UART_RXD,
// Bidirectionals
// Outputs
irq,
readdata,
UART_TXD
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 434;
parameter HALF_BAUD_TICK_COUNT = 217;
parameter TDW = 10; // Total data width
parameter DW = 8; // Data width
parameter ODD_PARITY = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input address;
input chipselect;
input [ 3: 0] byteenable;
input read;
input write;
input [31: 0] writedata;
input UART_RXD;
// Bidirectionals
// Outputs
output reg irq;
output reg [31: 0] readdata;
output UART_TXD;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_fifo_read_en;
wire [ 7: 0] read_available;
wire read_data_valid;
wire [(DW-1):0] read_data;
wire parity_error;
wire write_data_parity;
wire [ 7: 0] write_space;
// Internal Registers
reg read_interrupt_en;
reg write_interrupt_en;
reg read_interrupt;
reg write_interrupt;
reg write_fifo_write_en;
reg [(DW-1):0] data_to_uart;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
irq <= 1'b0;
else
irq <= write_interrupt | read_interrupt;
end
always @(posedge clk)
begin
if (reset)
readdata <= 32'h00000000;
else if (chipselect)
begin
if (address == 1'b0)
readdata <=
{8'h00,
read_available,
read_data_valid,
5'h00,
parity_error,
1'b0,
read_data[(DW - 1):0]};
else
readdata <=
{8'h00,
write_space,
6'h00,
write_interrupt,
read_interrupt,
6'h00,
write_interrupt_en,
read_interrupt_en};
end
end
always @(posedge clk)
begin
if (reset)
read_interrupt_en <= 1'b0;
else if ((chipselect) && (write) && (address) && (byteenable[0]))
read_interrupt_en <= writedata[0];
end
always @(posedge clk)
begin
if (reset)
write_interrupt_en <= 1'b0;
else if ((chipselect) && (write) && (address) && (byteenable[0]))
write_interrupt_en <= writedata[1];
end
always @(posedge clk)
begin
if (reset)
read_interrupt <= 1'b0;
else if (read_interrupt_en == 1'b0)
read_interrupt <= 1'b0;
else
read_interrupt <= (&(read_available[6:5]) | read_available[7]);
end
always @(posedge clk)
begin
if (reset)
write_interrupt <= 1'b0;
else if (write_interrupt_en == 1'b0)
write_interrupt <= 1'b0;
else
write_interrupt <= (&(write_space[6:5]) | write_space[7]);
end
always @(posedge clk)
begin
if (reset)
write_fifo_write_en <= 1'b0;
else
write_fifo_write_en <=
chipselect & write & ~address & byteenable[0];
end
always @(posedge clk)
begin
if (reset)
data_to_uart <= 'h0;
else
data_to_uart <= writedata[(DW - 1):0];
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign parity_error = 1'b0;
assign read_fifo_read_en = chipselect & read & ~address & byteenable[0];
assign write_data_parity = (^(data_to_uart)) ^ ODD_PARITY;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_in_deserializer RS232_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset),
.serial_data_in (UART_RXD),
.receive_data_en (read_fifo_read_en),
// Bidirectionals
// Outputs
.fifo_read_available (read_available),
.received_data_valid (read_data_valid),
.received_data (read_data)
);
defparam
RS232_In_Deserializer.CW = CW,
RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Deserializer.TDW = TDW,
RS232_In_Deserializer.DW = (DW - 1);
altera_up_rs232_out_serializer RS232_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset),
.transmit_data (data_to_uart),
.transmit_data_en (write_fifo_write_en),
// Bidirectionals
// Outputs
.fifo_write_space (write_space),
.serial_data_out (UART_TXD)
);
defparam
RS232_Out_Serializer.CW = CW,
RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Serializer.TDW = TDW,
RS232_Out_Serializer.DW = (DW - 1);
endmodule
|
module top
(
// Clocks
input wire clk1,
input wire clk2,
// Dummy data input
input wire [1:0] i_d,
input wire i_t,
// OSERDES output(s)
inout wire [1:0] out,
// Dummy outputs
output wire o_d
);
// ============================================================================
wire clk;
wire clkdiv;
BUFG bufg1 (.I(clk1), .O(clk));
BUFG bufg2 (.I(clk2), .O(clkdiv));
// ============================================================================
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge clk)
rst_sr <= rst_sr >> 1;
wire rst = rst_sr[0];
// ============================================================================
wire [1:0] iq;
wire [1:0] oq;
wire [1:0] tq;
// Dummy outputs
assign o_d = |iq;
// OBUFT is not yet supported in SymbiFlow
/*
OBUFT obuft_0 (
.I (oq[0]),
.T (tq[0]),
.O (out[0])
);
OBUFT obuft_1 (
.I (oq[1]),
.T (tq[1]),
.O (out[1])
);
*/
// IOBUFs
IOBUF iobuf_0 (
.O (iq[0]),
.I (oq[0]),
.T (tq[0]),
.IO (out[0])
);
IOBUF iobuf_1 (
.O (iq[1]),
.I (oq[1]),
.T (tq[1]),
.IO (out[1])
);
/*
OBUF obuf_0 (
.I (oq[0]),
.O (out[0])
);
OBUF obuf_1 (
.I (oq[1]),
.O (out[1])
);
*/
// OSERDES with inverters intended to be disabled
(* KEEP, DONT_TOUCH *)
OSERDESE2 #
(
.IS_D2_INVERTED (0),
.IS_D4_INVERTED (0),
.IS_D6_INVERTED (0),
.IS_D8_INVERTED (0),
.IS_T1_INVERTED (0),
.IS_T2_INVERTED (0),
.IS_T3_INVERTED (0),
.IS_T4_INVERTED (0),
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (8),
.TRISTATE_WIDTH (1)
)
oserdes_0
(
.CLK (clk),
.CLKDIV (clkdiv),
.RST (rst),
.OCE (1'b1),
// D1-D2 routed
// D3-D4 const0
// D5-D6 const1
// D7-D8 unconnected
.D1 (i_d[0]),
.D2 (i_d[1]),
.D3 (1'b0),
.D4 (1'b0),
.D5 (1'b1),
.D6 (1'b1),
.D7 (),
.D8 (),
.OQ (oq[0]),
.TCE (1'b1),
// T1 - routed
// T2 - const0
// T3 - const1
// T4 - unconnected
.T1 (i_t),
.T2 (1'b0),
.T3 (1'b1),
.T4 (),
.TQ (tq[0])
);
// OSERDES with inverters intended to be enabled
(* KEEP, DONT_TOUCH *)
OSERDESE2 #
(
.IS_D2_INVERTED (1),
.IS_D4_INVERTED (1),
.IS_D6_INVERTED (1),
.IS_D8_INVERTED (1),
.IS_T1_INVERTED (1),
.IS_T2_INVERTED (1),
.IS_T3_INVERTED (1),
.IS_T4_INVERTED (1),
.DATA_RATE_OQ ("SDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (8),
.TRISTATE_WIDTH (1)
)
oserdes_1
(
.CLK (clk),
.CLKDIV (clkdiv),
.RST (rst),
.OCE (1'b1),
// D1-D2 routed
// D3-D4 const0
// D5-D6 const1
// D7-D8 unconnected
.D1 (i_d[0]),
.D2 (i_d[1]),
.D3 (1'b0),
.D4 (1'b0),
.D5 (1'b1),
.D6 (1'b1),
.D7 (),
.D8 (),
.OQ (oq[1]),
.TCE (1'b1),
// T1 - routed
// T2 - const0
// T3 - const1
// T4 - unconnected
.T1 (i_t),
.T2 (1'b0),
.T3 (1'b1),
.T4 (),
.TQ (tq[1])
);
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Thu May 1 20:55:21 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_108MHz/clk_108MHz_funcsim.v
// Design : clk_108MHz
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_108MHz,clk_wiz_v5_1,{component_name=clk_108MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_108MHz
(clk_100MHz,
clk_108MHz,
locked);
input clk_100MHz;
output clk_108MHz;
output locked;
(* IBUF_LOW_PWR *) wire clk_100MHz;
wire clk_108MHz;
wire locked;
clk_108MHzclk_108MHz_clk_wiz U0
(.clk_100MHz(clk_100MHz),
.clk_108MHz(clk_108MHz),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "clk_108MHz_clk_wiz" *)
module clk_108MHzclk_108MHz_clk_wiz
(clk_100MHz,
clk_108MHz,
locked);
input clk_100MHz;
output clk_108MHz;
output locked;
(* IBUF_LOW_PWR *) wire clk_100MHz;
wire clk_100MHz_clk_108MHz;
wire clk_108MHz;
wire clk_108MHz_clk_108MHz;
wire clkfbout_buf_clk_108MHz;
wire clkfbout_clk_108MHz;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_108MHz),
.O(clkfbout_buf_clk_108MHz));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_100MHz),
.O(clk_100MHz_clk_108MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_108MHz_clk_108MHz),
.O(clk_108MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.125000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(9.375000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_108MHz),
.CLKFBOUT(clkfbout_clk_108MHz),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_100MHz_clk_108MHz),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_108MHz_clk_108MHz),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S2S_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYMETAL6S2S_BLACKBOX_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlymetal6s2s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S2S_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 100; const int maxpow = 1 << 17; const int inf = 1e9 + 7; long long h[maxn]; int par[maxn]; struct node { pair<int, int> a; node(pair<int, int> _a) : a(_a) {} node() : a(0, -1) {} void merge(node x, node y) { a = max(x.a, y.a); } }; node tree[maxpow * 2]; node query(int i, int ns, int ne, int qs, int qe) { if (qe <= ns || qs >= ne) { return node(); } if (ns >= qs && ne <= qe) { return tree[i]; } int mid = (ns + ne) / 2; node res1 = query(2 * i, ns, mid, qs, qe); node res2 = query(2 * i + 1, mid, ne, qs, qe); node res; res.merge(res1, res2); return res; } void update(int i, int ns, int ne, int qs, pair<int, int> v) { if (qs + 1 <= ns || qs >= ne) { return; } if (ns + 1 == ne) { tree[i] = node(v); return; } int mid = (ns + ne) / 2; update(2 * i, ns, mid, qs, v); update(2 * i + 1, mid, ne, qs, v); tree[i].merge(tree[2 * i], tree[2 * i + 1]); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, d; cin >> n >> d; vector<long long> a; for (long long i = 0; i < n; i++) { cin >> h[i]; a.push_back(h[i]); } sort(a.begin(), a.end()); a.erase(unique(a.begin(), a.end()), a.end()); pair<int, int> mx(-1, -1); for (int i = 0; i < n; i++) { int left = lower_bound(a.begin(), a.end(), h[i] - d + 1) - a.begin(); int right = lower_bound(a.begin(), a.end(), h[i] + d) - a.begin(); int cur = lower_bound(a.begin(), a.end(), h[i]) - a.begin(); node ans1 = query(1, 0, maxpow, 0, left); node ans2 = query(1, 0, maxpow, right, n); pair<int, int> ans = max(ans1.a, ans2.a); ans.first += 1; par[i] = ans.second; ans.second = i; mx = max(mx, ans); update(1, 0, maxpow, cur, ans); } cout << mx.first << endl; int ind = mx.second; vector<int> res; while (ind != -1) { res.push_back(ind); ind = par[ind]; } reverse(res.begin(), res.end()); for (int i = 0; i < res.size(); i++) { cout << res[i] + 1 << ; } cout << endl; }
|
/**
\file "interleave-a.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
Added inverters in prsim to check for proper event interleaving.
$Id: interleave-a.v,v 1.3 2010/04/06 00:08:31 fang Exp $
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ interleave-a.haco-c
$prsim("interleave-a.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("watchall");
$prsim_cmd("timing after");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$to_prsim("TOP.out3", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #6 $finish;
initial
$monitor("@%6.3f: out=%d,%d,%d,%d,%d", $realtime,
out0, out1, out2, out3, out);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long, pair<long long, long long> > > edges; vector<long long> wt(100005); long long sz[100005], parent[100005]; long long ans = 0; long long n, m; void make_set() { for (long long i = 1; i <= n; i++) { sz[i] = 1; parent[i] = i; } } long long findParent(long long x) { if (x == parent[x]) return x; return findParent(parent[x]); } void merge_sets(long long x, long long y, long long w) { x = findParent(x); y = findParent(y); if (x == y) return; ans += w * sz[x] * sz[y]; if (sz[x] > sz[y]) { parent[y] = x; sz[x] += sz[y]; } else { parent[x] = y; sz[y] += sz[x]; } } int main() { cin >> n >> m; for (long long i = 1; i <= n; i++) cin >> wt[i]; for (long long i = 1; i <= m; i++) { long long x, y; cin >> x >> y; edges.push_back(make_pair(min(wt[x], wt[y]), make_pair(x, y))); } sort(edges.begin(), edges.end()); reverse(edges.begin(), edges.end()); make_set(); for (long long i = 0; i < m; i++) { merge_sets(edges[i].second.first, edges[i].second.second, edges[i].first); } double anss = (double)ans; anss /= (double)n; anss /= (double)(n - 1); anss *= 2.00; cout << fixed << setprecision(10) << anss << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21AI_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_2_V
`define SKY130_FD_SC_MS__NAND2_2_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_2_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_ctu_pad_cluster.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Unit Name: bw_ctu_pad_cluster
// Block Name: ctu_pad_cluster
//
//-----------------------------------------------------------------------------
`include "sys.h"
module bw_ctu_pad_cluster (
// Inouts:
jclk , // Differential System Clock Inputs
tsr_testio , // Tempsensor test signals
vddo , // 1.5V vdd
vdda // 1.8V analog vdd
);
inout [1:0] jclk;
inout [1:0] tsr_testio;
inout vddo;
inout vdda;
//synopsys translate_off
//synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int s, x, y, a, b; cin >> s >> x >> y >> a >> b; if ((x * s) + (2 * a) < (y * s) + (2 * b)) { cout << First ; return 0; } if ((x * s) + (2 * a) > (y * s) + (2 * b)) { cout << Second ; return 0; } if ((x * s) + (2 * a) == (y * s) + (2 * b)) { cout << Friendship ; return 0; } return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4k_18.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_4k_18 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [17:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [17:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire [17:0] sub_wire3;
wire [11:0] sub_wire4;
wire rdempty = sub_wire0;
wire [11:0] wrusedw = sub_wire1[11:0];
wire wrfull = sub_wire2;
wire [17:0] q = sub_wire3[17:0];
wire [11:0] rdusedw = sub_wire4[11:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.q (sub_wire3),
.rdusedw (sub_wire4)
// synopsys translate_off
,
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.add_ram_output_register = "OFF",
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 18,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "18"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "18"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_18_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_1_V
`define SKY130_FD_SC_LP__SDFRTP_1_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_1_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) const double PI = acos(-1); using namespace std; const int MAX = 100 * 1000 + 10; int A[MAX], B[MAX], n, pos[MAX]; int diff[MAX << 1]; int mx[MAX], mn[MAX]; deque<int> dq; const int oo = 1 << 28; int main() { scanf( %d , &n); for (int i = 0; i < (n); i++) { scanf( %d , A + i); pos[A[i]] = i; } for (int i = 0; i < (n); i++) scanf( %d , B + i); map<int, int> M; for (int i = 0; i < (n); i++) M[i - pos[B[i]]]++; int offset = 0; for (int i = 0; i < (n); i++) { auto p = M.lower_bound(offset); int ans = INT_MAX; if (p != M.end()) ans = abs(p->first - offset); if (p != M.begin()) { --p; ans = min(ans, abs(p->first - offset)); } printf( %d n , ans); offset++; int x = i - pos[B[i]]; M[x]--; if (M[x] == 0) M.erase(x); x = (i + n) - pos[B[i]]; M[x]++; } return 0; }
|
module ID_EX(input clk,
input reset,
input [1:0] WB_in,
input [1:0] M_in,
input [3:0] EX_in,
input [31:0] RDdata1_in,
input [31:0] RDdata2_in,
input [31:0] sign_extended_in,
input [4:0] Inst_25_to_21_in,
input [4:0] Inst_20_to_16_in,
input [4:0] Inst_15_to_11_in,
input [5:0] Inst_5_to_0_in,
input [31:0] pc_plus4_in,
input hold_i,
output reg[1:0] WB_out,
output reg[1:0] M_out,
output reg ALUSrc_out,
output reg [1:0] ALUOp_out,
output reg RegDst_out,
output reg[31:0] RDdata1_out,
output reg[31:0] RDdata2_out,
output reg[31:0] sign_extended_out,
output reg[4:0] Inst_25_to_21_out,
output reg[4:0] Inst_20_to_16_out,
output reg[4:0] Inst_15_to_11_out,
output reg[5:0] Inst_5_to_0_out);
always@(posedge reset)begin
WB_out = 0;
M_out = 0;
ALUSrc_out = 0;
ALUOp_out = 0;
RegDst_out = 0;
RDdata1_out = 0;
RDdata2_out = 0;
sign_extended_out = 0;
Inst_15_to_11_out = 0;
Inst_20_to_16_out = 0;
Inst_25_to_21_out = 0;
Inst_5_to_0_out = 0;
end
always@(posedge clk)begin
if(hold_i) begin
WB_out <= WB_out;
M_out <= M_out;
ALUSrc_out <= ALUSrc_out;
ALUOp_out <= ALUOp_out;
RegDst_out <= RegDst_out;
RDdata1_out <= RDdata1_out;
RDdata2_out <= RDdata2_out;
sign_extended_out <= sign_extended_out;
Inst_15_to_11_out <= Inst_15_to_11_out;
Inst_20_to_16_out <= Inst_20_to_16_out;
Inst_25_to_21_out <= Inst_25_to_21_out;
Inst_5_to_0_out <= Inst_5_to_0_out;
end
else begin
WB_out <= WB_in;
M_out <= M_in;
ALUSrc_out <= EX_in[0];
ALUOp_out <= EX_in[2:1];
RegDst_out <= EX_in[3];
RDdata1_out <= RDdata1_in;
RDdata2_out <= RDdata2_in;
sign_extended_out <= sign_extended_in;
Inst_15_to_11_out <= Inst_15_to_11_in;
Inst_20_to_16_out <= Inst_20_to_16_in;
Inst_25_to_21_out <= Inst_25_to_21_in;
Inst_5_to_0_out <= Inst_5_to_0_in;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLCLKP_2_V
`define SKY130_FD_SC_LS__DLCLKP_2_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlclkp_2 (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlclkp_2 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLCLKP_2_V
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4 port arbitrated multiplexer
*/
module axis_arb_mux_4 #
(
parameter DATA_WIDTH = 8,
// arbitration type: "PRIORITY" or "ROUND_ROBIN"
parameter ARB_TYPE = "PRIORITY",
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "HIGH"
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [DATA_WIDTH-1:0] input_0_axis_tdata,
input wire input_0_axis_tvalid,
output wire input_0_axis_tready,
input wire input_0_axis_tlast,
input wire input_0_axis_tuser,
input wire [DATA_WIDTH-1:0] input_1_axis_tdata,
input wire input_1_axis_tvalid,
output wire input_1_axis_tready,
input wire input_1_axis_tlast,
input wire input_1_axis_tuser,
input wire [DATA_WIDTH-1:0] input_2_axis_tdata,
input wire input_2_axis_tvalid,
output wire input_2_axis_tready,
input wire input_2_axis_tlast,
input wire input_2_axis_tuser,
input wire [DATA_WIDTH-1:0] input_3_axis_tdata,
input wire input_3_axis_tvalid,
output wire input_3_axis_tready,
input wire input_3_axis_tlast,
input wire input_3_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
wire [3:0] request;
wire [3:0] acknowledge;
wire [3:0] grant;
wire grant_valid;
wire [1:0] grant_encoded;
assign acknowledge[0] = input_0_axis_tvalid & input_0_axis_tready & input_0_axis_tlast;
assign request[0] = input_0_axis_tvalid & ~acknowledge[0];
assign acknowledge[1] = input_1_axis_tvalid & input_1_axis_tready & input_1_axis_tlast;
assign request[1] = input_1_axis_tvalid & ~acknowledge[1];
assign acknowledge[2] = input_2_axis_tvalid & input_2_axis_tready & input_2_axis_tlast;
assign request[2] = input_2_axis_tvalid & ~acknowledge[2];
assign acknowledge[3] = input_3_axis_tvalid & input_3_axis_tready & input_3_axis_tlast;
assign request[3] = input_3_axis_tvalid & ~acknowledge[3];
// mux instance
axis_mux_4 #(
.DATA_WIDTH(DATA_WIDTH)
)
mux_inst (
.clk(clk),
.rst(rst),
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tvalid(input_0_axis_tvalid & grant[0]),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tvalid(input_1_axis_tvalid & grant[1]),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tvalid(input_2_axis_tvalid & grant[2]),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tvalid(input_3_axis_tvalid & grant[3]),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.enable(grant_valid),
.select(grant_encoded)
);
// arbiter instance
arbiter #(
.PORTS(4),
.TYPE(ARB_TYPE),
.BLOCK("ACKNOWLEDGE"),
.LSB_PRIORITY(LSB_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, pos; long long a[200005], sum[200005], ans; vector<long long> vec; int main() { cin.tie(0), ios::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; sum[i] = a[i]; sum[i] += sum[i - 1]; if (a[i] > 1) vec.push_back(i); } a[n + 1] = 1; vec.push_back(n + 1); for (int i = 1; i <= n; i++) { pos = i; long long tich = a[i]; while (1) { int it = lower_bound(vec.begin(), vec.end(), pos + 1) - vec.begin(); int l = pos, r = vec[it] - 1, mid; if (tich % k == 0) { long long val = tich / k; while (l < r) { mid = (l + r) / 2; if (sum[mid] - sum[i - 1] >= val) r = mid; else l = mid + 1; } if (l >= pos && sum[l] - sum[i - 1] == val) { ans++; } } long long amount = LLONG_MAX / a[vec[it]]; if (tich >= amount) break; tich *= a[vec[it]]; pos = vec[it]; if (pos == n + 1) break; } } cout << ans; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
bit global_bit;
module t (clk);
input clk;
integer cyc=0;
typedef struct packed {
bit b1;
bit b0;
} strp_t;
typedef struct packed {
strp_t x1;
strp_t x0;
} strp_strp_t;
typedef union packed {
strp_t x1;
strp_t x0;
} unip_strp_t;
typedef bit [2:1] arrp_t;
typedef arrp_t [4:3] arrp_arrp_t;
typedef strp_t [4:3] arrp_strp_t;
typedef bit arru_t [2:1];
typedef arru_t arru_arru_t [4:3];
typedef arrp_t arru_arrp_t [4:3];
typedef strp_t arru_strp_t [4:3];
strp_t v_strp;
strp_strp_t v_strp_strp;
unip_strp_t v_unip_strp;
arrp_t v_arrp;
arrp_arrp_t v_arrp_arrp;
arrp_strp_t v_arrp_strp;
arru_t v_arru;
arru_arru_t v_arru_arru;
arru_arrp_t v_arru_arrp;
arru_strp_t v_arru_strp;
real v_real;
real v_arr_real [2];
string v_string;
p #(.PARAM(2)) p2 ();
p #(.PARAM(3)) p3 ();
always @ (posedge clk) begin
cyc <= cyc + 1;
v_strp <= ~v_strp;
v_strp_strp <= ~v_strp_strp;
v_unip_strp <= ~v_unip_strp;
v_arrp_strp <= ~v_arrp_strp;
v_arrp <= ~v_arrp;
v_arrp_arrp <= ~v_arrp_arrp;
v_real <= v_real + 0.1;
v_string <= "foo";
v_arr_real[0] <= v_arr_real[0] + 0.2;
v_arr_real[1] <= v_arr_real[1] + 0.3;
for (integer b=3; b<=4; b++) begin
v_arru[b] <= ~v_arru[b];
v_arru_strp[b] <= ~v_arru_strp[b];
v_arru_arrp[b] <= ~v_arru_arrp[b];
for (integer a=3; a<=4; a++) begin
v_arru_arru[a][b] = ~v_arru_arru[a][b];
end
end
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module p;
parameter PARAM = 1;
initial global_bit = 1;
endmodule
|
`timescale 1ns / 1ps
module mac_fifo_test();
parameter IN_WIDTH = 8;
parameter OUT_WIDTH = 32;
reg reset;
reg [IN_WIDTH-1:0] data_in;
reg data_in_clock;
reg data_in_enable;
reg data_in_start;
reg data_in_end;
wire [OUT_WIDTH-1:0] data_out;
reg data_out_clock;
reg data_out_enable;
wire data_out_start;
wire data_out_end;
reg error;
reg retry;
reg [OUT_WIDTH-1:0] tempdata;
integer i;
mac_fifo #(
.DATA_IN_WIDTH (IN_WIDTH),
.DATA_OUT_WIDTH (OUT_WIDTH),
.FIFO_DEPTH (12)
)
ff (
.reset(reset),
// IN PORT
.data_in(data_in),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
.data_in_start(data_in_start),
.data_in_end(data_in_end),
// OUT PORT
.data_out(data_out),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable),
.data_out_start(data_out_start),
.data_out_end(data_out_end),
.retry(retry),
.error(error)
);
initial
begin
reset = 1;
data_in = 0;
data_in_clock = 0;
data_in_enable = 0;
data_out_clock = 0;
data_out_enable = 0;
data_in_start = 0;
data_in_end = 0;
error = 0;
retry = 0;
tempdata = 0;
#15 reset = 0;
push(8'h01,1,0,0);
push(8'h02,0,0,0);
push(8'h03,0,0,0);
push(8'h04,0,0,0);
push(8'h05,0,0,0);
push(8'h06,0,0,0);
push(8'h07,0,0,0);
push(8'h08,0,0,0);
push(8'h09,0,0,0);
push(8'h0A,0,0,0);
push(8'h0B,0,0,0);
push(8'h0C,0,0,0);
push(8'h0D,0,0,0);
push(8'h0E,0,0,0);
push(8'h0F,0,0,0);
push(8'h10,0,0,0);
push(8'h11,0,0,0);
push(8'h12,0,0,0);
push(8'h13,0,0,0);
push(8'h14,0,1,0);
push(8'h11,1,0,0);
push(8'h22,0,0,0);
push(8'h33,0,0,0);
push(8'h44,0,0,1);
push(8'h55,1,0,0);
push(8'h66,0,0,0);
push(8'h77,0,0,0);
push(8'h88,0,0,0);
push(8'h99,0,0,0);
push(8'hAA,0,0,0);
push(8'hBB,0,0,0);
push(8'hCC,0,0,0);
push(8'hDD,0,0,0);
push(8'hEE,0,0,0);
push(8'hFF,0,1,0);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
$finish;
end
always
#5 data_in_clock = ~data_in_clock;
always
#40 data_out_clock = ~data_out_clock;
task push;
input[IN_WIDTH-1:0] data;
input data_start;
input data_end;
input frame_error;
begin
data_in = data;
data_in_enable = 1;
data_in_start = data_start;
data_in_end = data_end;
error = frame_error;
@(posedge data_in_clock);
#1 data_in_enable = 0;
data_in_start = 0;
data_in_end = 0;
error = 0;
$display("Pushed: %x Start: %b End: %b",data, data_start, data_end );
end
endtask
task pop;
output [OUT_WIDTH-1:0] data;
begin
data_out_enable = 1;
@(posedge data_out_clock);
#1 data_out_enable = 0;
data = data_out;
$display("Popped %x Start: %b End: %b", data, data_out_start, data_out_end);
end
endtask
endmodule
|
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20
module test_padder;
// Inputs
reg clk;
reg reset;
reg [63:0] in;
reg in_ready;
reg is_last;
reg [2:0] byte_num;
reg f_ack;
// Outputs
wire buffer_full;
wire [575:0] out;
wire out_ready;
// Var
integer i;
// Instantiate the Unit Under Test (UUT)
padder uut (
.clk(clk),
.reset(reset),
.in(in),
.in_ready(in_ready),
.is_last(is_last),
.byte_num(byte_num),
.buffer_full(buffer_full),
.out(out),
.out_ready(out_ready),
.f_ack(f_ack)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
in = 0;
in_ready = 0;
is_last = 0;
byte_num = 0;
f_ack = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
// pad an empty string, should not eat next input
reset = 1; #(`P); reset = 0;
#(7*`P); // wait some cycles
if (buffer_full !== 0) error;
in_ready = 1;
is_last = 1;
#(`P);
in_ready = 1; // next input
is_last = 1;
#(`P);
in_ready = 0;
is_last = 0;
while (out_ready !== 1)
#(`P);
check({8'h1, 560'h0, 8'h80});
f_ack = 1; #(`P); f_ack = 0;
for(i=0; i<5; i=i+1)
begin
#(`P);
if (buffer_full !== 0) error; // should be 0
end
// pad an (576-8) bit string
reset = 1; #(`P); reset = 0;
#(4*`P); // wait some cycles
in_ready = 1;
byte_num = 7; /* should have no effect */
is_last = 0;
for (i=0; i<8; i=i+1)
begin
in = 64'h1234567890ABCDEF;
#(`P);
end
is_last = 1;
#(`P);
in_ready = 0;
is_last = 0;
check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890ABCD81 });
// pad an (576-64) bit string
reset = 1; #(`P); reset = 0;
// don't wait any cycle
in_ready = 1;
byte_num = 7; /* should have no effect */
is_last = 0;
for (i=0; i<8; i=i+1)
begin
in = 64'h1234567890ABCDEF;
#(`P);
end
is_last = 1;
byte_num = 0;
#(`P);
in_ready = 0;
is_last = 0;
check({ {8{64'h1234567890ABCDEF}}, 64'h0100000000000080 });
// pad an (576*2-16) bit string
reset = 1; #(`P); reset = 0;
in_ready = 1;
byte_num = 7; /* should have no effect */
is_last = 0;
for (i=0; i<9; i=i+1)
begin
in = 64'h1234567890ABCDEF;
#(`P);
end
if (out_ready !== 1) error;
check({9{64'h1234567890ABCDEF}});
#(`P/2);
if (buffer_full !== 1) error; // should not eat
#(`P/2);
in = 64'h999; // should not eat this
#(`P/2);
if (buffer_full !== 1) error; // should not eat
#(`P/2);
f_ack = 1; #(`P); f_ack = 0;
if (out_ready !== 0) error;
// feed next (576-16) bit
for (i=0; i<8; i=i+1)
begin
in = 64'h1234567890ABCDEF; #(`P);
end
byte_num = 6;
is_last = 1;
in = 64'h1234567890ABCDEF; #(`P);
if (out_ready !== 1) error;
check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890AB0180 });
is_last = 0;
// eat these bits
f_ack = 1; #(`P); f_ack = 0;
// should not provide any more bits, if user provides nothing
in_ready = 0;
is_last = 0;
for (i=0; i<10; i=i+1)
begin
if (out_ready === 1) error;
#(`P);
end
in_ready = 0;
$display("Good!");
$finish;
end
always #(`P/2) clk = ~ clk;
task error;
begin
$display("E");
$finish;
end
endtask
task check;
input [575:0] wish;
begin
if (out !== wish)
begin
$display("out:%h wish:%h", out, wish);
error;
end
end
endtask
endmodule
`undef P
|
module top;
reg pass = 1'b1;
reg in;
wire bf1, bf2, nt1, nt2, pd1, pd2, pu1, pu2;
initial begin
// $monitor(bf1, bf2,, nt1, nt2,, pd1, pd2,, pu1, pu2,, in);
if (bf1 !== 1'bz && bf2 !== 1'bz) begin
$display("Buffer failed, expected 2'bzz, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'bz && nt2 !== 1'bz) begin
$display("Inverter (not) failed, expected 2'bzz, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
in = 1'b0;
#1;
if (bf1 !== 1'b0 && bf2 !== 1'b0) begin
$display("Buffer failed, expected 2'b00, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'b1 && nt2 !== 1'b1) begin
$display("Inverter (not) failed, expected 2'b11, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
in = 1'b1;
#1;
if (bf1 !== 1'b1 && bf2 !== 1'b1) begin
$display("Buffer failed, expected 2'b11, got %b%b", bf1, bf2);
pass = 1'b0;
end
if (nt1 !== 1'b0 && nt2 !== 1'b0) begin
$display("Inverter (not) failed, expected 2'b00, got %b%b", nt1, nt2);
pass = 1'b0;
end
if (pd1 !== 1'b0 && pd2 !== 1'b0) begin
$display("Pull down failed, expected 2'b00, got %b%b", pd1, pd2);
pass = 1'b0;
end
if (pu1 !== 1'b1 && pu2 !== 1'b1) begin
$display("Pull up failed, expected 2'b11, got %b%b", pu1, pu2);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
buf (bf1, bf2, in);
not (nt1, nt2, in);
pulldown (pd1, pd2);
pullup (pu1, pu2);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; vector<int> arr(n); for (auto &x : arr) cin >> x; int height = 1; for (int i = 0; i < n; i++) { if (i > 0 and !arr[i - 1] and !arr[i]) { cout << -1 << n ; return; } height += arr[i] + (i > 0 and arr[i] and arr[i - 1] ? 4 : 0); } cout << height << endl; } int main(int argc, char const *argv[]) { int tc; cin >> tc; while (tc--) { solve(); } return 0; }
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`timescale 1ns/1ps
`define STRINGIFY(x) `"x`"
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk_a;
reg rce_a;
reg [`ADDR_WIDTH-1:0] ra_a;
wire [`DATA_WIDTH-1:0] rq_a;
reg wce_a;
reg [`ADDR_WIDTH-1:0] wa_a;
reg [`DATA_WIDTH-1:0] wd_a;
reg clk_b;
reg rce_b;
reg [`ADDR_WIDTH-1:0] ra_b;
wire [`DATA_WIDTH-1:0] rq_b;
reg wce_b;
reg [`ADDR_WIDTH-1:0] wa_b;
reg [`DATA_WIDTH-1:0] wd_b;
initial clk_a = 0;
initial clk_b = 0;
initial ra_a = 0;
initial ra_b = 0;
initial rce_a = 0;
initial rce_b = 0;
initial forever #(PERIOD / 2.0) clk_a = ~clk_a;
initial begin
#(PERIOD / 4.0);
forever #(PERIOD / 2.0) clk_b = ~clk_b;
end
initial begin
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
end
integer a;
integer b;
reg done_a;
reg done_b;
initial done_a = 1'b0;
initial done_b = 1'b0;
wire done_sim = done_a & done_b;
reg [`DATA_WIDTH-1:0] expected_a;
reg [`DATA_WIDTH-1:0] expected_b;
always @(posedge clk_a) begin
expected_a <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH{1'b1}};
end
always @(posedge clk_b) begin
expected_b <= (b | (b << 20) | 20'h55000) & {`DATA_WIDTH{1'b1}};
end
wire error_a = a != 0 ? rq_a !== expected_a : 0;
wire error_b = b != (1<<`ADDR_WIDTH) / 2 ? rq_b !== expected_b : 0;
integer error_a_cnt = 0;
integer error_b_cnt = 0;
always @ (posedge clk_a)
begin
if (error_a)
error_a_cnt <= error_a_cnt + 1'b1;
end
always @ (posedge clk_b)
begin
if (error_b)
error_b_cnt <= error_b_cnt + 1'b1;
end
// PORT A
initial #(1) begin
// Write data
for (a = 0; a < (1<<`ADDR_WIDTH) / 2; a = a + ADDR_INCR) begin
@(negedge clk_a) begin
wa_a = a;
wd_a = a | (a << 20) | 20'h55000;
wce_a = 1;
end
@(posedge clk_a) begin
#(PERIOD/10) wce_a = 0;
end
end
// Read data
for (a = 0; a < (1<<`ADDR_WIDTH) / 2; a = a + ADDR_INCR) begin
@(negedge clk_a) begin
ra_a = a;
rce_a = 1;
end
@(posedge clk_a) begin
#(PERIOD/10) rce_a = 0;
if ( rq_a !== expected_a) begin
$display("%d: PORT A: FAIL: mismatch act=%x exp=%x at %x", $time, rq_a, expected_a, a);
end else begin
$display("%d: PORT A: OK: act=%x exp=%x at %x", $time, rq_a, expected_a, a);
end
end
end
done_a = 1'b1;
end
// PORT B
initial #(1) begin
// Write data
for (b = (1<<`ADDR_WIDTH) / 2; b < (1<<`ADDR_WIDTH); b = b + ADDR_INCR) begin
@(negedge clk_b) begin
wa_b = b;
wd_b = b | (b << 20) | 20'h55000;
wce_b = 1;
end
@(posedge clk_b) begin
#(PERIOD/10) wce_b = 0;
end
end
// Read data
for (b = (1<<`ADDR_WIDTH) / 2; b < (1<<`ADDR_WIDTH); b = b + ADDR_INCR) begin
@(negedge clk_b) begin
ra_b = b;
rce_b = 1;
end
@(posedge clk_b) begin
#(PERIOD/10) rce_b = 0;
if ( rq_b !== expected_b) begin
$display("%d: PORT B: FAIL: mismatch act=%x exp=%x at %x", $time, rq_b, expected_b, b);
end else begin
$display("%d: PORT B: OK: act=%x exp=%x at %x", $time, rq_b, expected_b, b);
end
end
end
done_b = 1'b1;
end
// Scan for simulation finish
always @(posedge clk_a, posedge clk_b) begin
if (done_sim)
$finish_and_return( (error_a_cnt == 0 & error_b_cnt == 0) ? 0 : -1 );
end
case (`STRINGIFY(`TOP))
"BRAM_TDP_32x512": begin
BRAM_TDP_32x512 #() bram (
.clk_a(clk_a),
.rce_a(rce_a),
.ra_a(ra_a),
.rq_a(rq_a),
.wce_a(wce_a),
.wa_a(wa_a),
.wd_a(wd_a),
.clk_b(clk_b),
.rce_b(rce_b),
.ra_b(ra_b),
.rq_b(rq_b),
.wce_b(wce_b),
.wa_b(wa_b),
.wd_b(wd_b)
);
end
"BRAM_TDP_16x1024": begin
BRAM_TDP_16x1024 #() bram (
.clk_a(clk_a),
.rce_a(rce_a),
.ra_a(ra_a),
.rq_a(rq_a),
.wce_a(wce_a),
.wa_a(wa_a),
.wd_a(wd_a),
.clk_b(clk_b),
.rce_b(rce_b),
.ra_b(ra_b),
.rq_b(rq_b),
.wce_b(wce_b),
.wa_b(wa_b),
.wd_b(wd_b)
);
end
"BRAM_TDP_8x2048": begin
BRAM_TDP_8x2048 #() bram (
.clk_a(clk_a),
.rce_a(rce_a),
.ra_a(ra_a),
.rq_a(rq_a),
.wce_a(wce_a),
.wa_a(wa_a),
.wd_a(wd_a),
.clk_b(clk_b),
.rce_b(rce_b),
.ra_b(ra_b),
.rq_b(rq_b),
.wce_b(wce_b),
.wa_b(wa_b),
.wd_b(wd_b)
);
end
"BRAM_TDP_4x4096": begin
BRAM_TDP_4x4096 #() bram (
.clk_a(clk_a),
.rce_a(rce_a),
.ra_a(ra_a),
.rq_a(rq_a),
.wce_a(wce_a),
.wa_a(wa_a),
.wd_a(wd_a),
.clk_b(clk_b),
.rce_b(rce_b),
.ra_b(ra_b),
.rq_b(rq_b),
.wce_b(wce_b),
.wa_b(wa_b),
.wd_b(wd_b)
);
end
endcase
endmodule
|
/*
Copyright (C) {2014} {Ganesh Ajjanagadde} <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`default_nettype none
module pixel_map(input clk,
input signed[67:0] p1_inv,
input signed[68:0] p2_inv,
input signed[78:0] p3_inv,
input signed[67:0] p4_inv,
input signed[68:0] p5_inv,
input signed[78:0] p6_inv,
input signed[58:0] p7_inv,
input signed[59:0] p8_inv,
input signed[70:0] p9_inv,
input signed[78:0] dec_numx_horiz,
input signed[78:0] dec_numy_horiz,
input signed[70:0] dec_denom_horiz,
input[11:0] pixel_in,
output reg[11:0] pixel_out,
output[16:0] ntsc_out_addr,
output reg vga_in_wr,
output[16:0] vga_in_addr);
// instantiate an address mapper (for the vga_in)
addr_map addr_map_vga(.hcount(cur_x),
.vcount(cur_y),
.addr(vga_in_addr));
always @(posedge clk) begin
vga_in_wr <= 1;
if ((cur_x == 639) && (cur_y == 479)) begin
cur_x <= 0;
cur_y <= 0;
end
else if ((cur_x == 639) && (cur_y != 479)) begin
cur_x <= 0;
cur_y <= cur_y + 1;
end
else if (cur_x != 639) begin
cur_x <= cur_x + 1;
cur_y <= cur_y;
end
end
endmodule
|
module OpcodeBufferTest;
`include "Framework.v"
reg reset;
reg clk;
always #10 clk = ~clk;
reg [31:0] addrA;
wire [31:0] addrB;
reg writeEnable = 0;
reg [7:0] dataIn;
reg requestA;
wire requestB;
wire [7:0] outA;
wire [7:0] outB;
wire busyA;
wire busyB;
wire [15:0] displayIn = 0;
wire [31:0] displayAddr;
wire displayWE;
Display dsp(clk, displayIn);
wire [31:0] mmioInB;
wire [31:0] mmioAddrB;
wire mmioWEB;
SimpleMmu mmu(clk, reset, addrA, addrB, writeEnable, dataIn, requestA, requestB, outA, outB, busyA, busyB,
displayIn,displayAddr,displayWE, mmioInB, mmioAddrB, mmioWEB);
reg [31:0] ip;
wire busy;
wire [31:0] opcode;
reg startLoading;
OpcodeBuffer ob(clk, reset, ip, startLoading, outB, busyB, busy, opcode, addrB, requestB);
initial begin
$dumpfile("timing.vcd");
$dumpvars(0,mmu,ob);
reset = 1;
clk = 0;
#20 reset = 0;
ip = 0;
startLoading = 1;
#300 @(negedge busy) $display("Got opcode: %h = %h", ip, opcode);
#10 startLoading = 0;
ip = 4;
startLoading = 1;
#300 @(negedge busy) $display("Got opcode: %h = %h", ip, opcode);
ip = 8;
startLoading = 1;
#300 @(negedge busy) $display("Got opcode: %h = %h", ip, opcode);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline char gc() { static const long long L = 233333; static char sxd[L], *sss = sxd, *ttt = sxd; if (sss == ttt) { ttt = (sss = sxd) + fread(sxd, 1, L, stdin); if (sss == ttt) { return EOF; } } return *sss++; } inline char readalpha() { char c = gc(); for (; !isalpha(c); c = gc()) ; return c; } inline char readchar() { char c = gc(); for (; c == ; c = gc()) ; return c; } template <class T> inline bool read(T& x) { bool flg = false; char c = gc(); x = 0; for (; !isdigit(c); c = gc()) { if (c == - ) { flg = true; } else if (c == EOF) { return false; } } for (; isdigit(c); c = gc()) { x = (x << 1) + (x << 3) + (c ^ 48); } if (flg) { x = -x; } return true; } template <class T> inline void write(T x) { if (x < 0) { putchar( - ); x = -x; } if (x < 10) { putchar(x | 48); return; } write(x / 10); putchar((x % 10) | 48); } const int maxn = 20; const int maxl = 1000005; int n; int f[1 << maxn]; int g[1 << maxn]; char s[maxl]; int main() { scanf( %s , s + 1); n = strlen(s + 1); for (int i = 1; i <= n; ++i) { int now = i, nowzt = 0; while (now) { if (nowzt & (1 << (s[now] - a ))) { break; } nowzt |= (1 << (s[now] - a )); now--; f[nowzt] = i - now; } } int ans = 0; for (int i = 0; i < 1 << 20; ++i) { g[i] = f[i]; } for (int i = 0; i < 1 << 20; ++i) { for (int j = 0; j < 20; ++j) { g[i | (1 << j)] = max(g[i], g[i | (1 << j)]); } } for (int i = 0; i < 1 << 20; ++i) { ans = max(ans, f[i] + g[((1 << 20) - 1) ^ i]); } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, a[1231231]; long long mark[1231231]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; mark[1] = 1; for (int i = 2; i <= n; i++) { mark[i] = mark[i - 1]; mark[i] = max(mark[i], a[i] + 1); } for (int i = n - 1; i >= 1; i--) { mark[i] = max(mark[i], mark[i + 1] - 1); } long long ans = 0; for (int i = 1; i <= n; i++) { ans += max(0ll, (mark[i] - 1 - a[i])); } cout << ans << endl; }
|
`timescale 1 ns / 1 ps
module edge_detector #
(
parameter integer PULSE_WIDTH = 1
)
(
input wire din,
input wire clk,
output wire dout
);
reg din_next;
always @(posedge clk) begin
din_next <= din;
end
generate
if (PULSE_WIDTH == 1)
begin : ONE
assign dout = !din_next && din;
end
if (PULSE_WIDTH > 1)
begin : MORE_THAN_ONE
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer CNT_WIDTH = clogb2(PULSE_WIDTH);
reg [CNT_WIDTH-1:0] cnt;
reg counting;
always @(posedge clk) begin
if (!din_next && din) begin
cnt <= cnt + 1;
counting <= 1;
end else begin
if (counting && cnt < PULSE_WIDTH) begin
cnt <= cnt + 1;
end else begin
counting <= 0;
cnt <= 0;
end
end
end
assign dout = (counting || (!din_next && din));
end
endgenerate
endmodule
|
`timescale 1ns/10ps
module Computer_System_System_PLL_sys_pll(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("100.000000 MHz"),
.phase_shift1("-3000 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; map<char, int> freq; vector<int> vec; vector<char> vec2; int main() { int n, k; cin >> n >> k; string s, ans, update, alpha = abcdefghijklmnopqrstuvwxyz ; cin >> s; int size = s.size(); for (int i = 0; i < 26; i++) { for (int j = 0; j < size; j++) { if (k > 0) { if (s[j] == alpha[i]) { k--; s[j] = 0 ; } } } } for (int i = 0; i < size; i++) { if (s[i] != 0 ) { ans += s[i]; } } cout << ans << endl; return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:19:38 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_led_controller_0_1_stub.v
// Design : led_controller_design_led_controller_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp,
s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output [7:0]LEDs_out;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> inline void smin(A &a, const B &b) { if (a > b) a = b; } struct point { double x, y, z; inline point(double x = 0, double y = 0, double z = 0) : x(x), y(y), z(z) {} inline point operator-(point a) { return point(x - a.x, y - a.y, z - a.z); } inline double al() { return atan2(y, x); } inline double nor2() { return *this * *this; } inline double nor() { return sqrt(*this * *this); } inline double operator*(point a) { return x * a.x + y * a.y + z * a.z; } inline void input() { scanf( %lf %lf %lf , &x, &y, &z); } inline void print() { printf( %lf %lf %lf n , x, y, z); } } A, B, A_, B_, F; double r, h, R; double all = 6.283185307179586476925286766559; double _120 = 2.0943951023931954923084289221863; double _150 = 2.2689280275926284500007979990352; inline double dist(point a, point b) { double al = fabs(a.al() - b.al()); smin(al, all - al); double da = (a - F).nor2(), db = (b - F).nor2(); return sqrt(da + db - 2 * sqrt(da * db) * cos(r * al / R)); } inline double calc_A() { double ans = 1e100; for (double st_ = 0; st_ < all; st_ += _120) { double st = st_, ed = st + _120 + 0.1; while (ed - st > 1e-6) { double a = (st + st + ed) / 3; B_ = {r * cos(a), r * sin(a)}; double val_a = (A_ - B_).nor() + dist(B, B_); double b = (st + ed + ed) / 3; B_ = {r * cos(b), r * sin(b)}; double val_b = (A_ - B_).nor() + dist(B, B_); if (val_a < val_b) ed = b; else st = a; } double al = (st + ed) / 2; B_ = {r * cos(al), r * sin(al)}; smin(ans, (A_ - B_).nor() + dist(B, B_)); } return ans; } int main() { scanf( %lf %lf , &r, &h); F = point(0, 0, h); R = sqrt(r * r + h * h); A.input(), B.input(); if (A.z > B.z) swap(A, B); double ans; if (B.z < 1e-6) ans = (A - B).nor(); else if (A.z < 1e-6) A_ = A, ans = calc_A(); else { ans = dist(A, B); for (double st_ = 0; st_ < all; st_ += _120) { double st = st_, ed = st + _120 + 0.1; while (ed - st > 1e-6) { double a = (st + st + ed) / 3; A_ = {r * cos(a), r * sin(a)}; double val_a = dist(A, A_) + calc_A(); double b = (st + ed + ed) / 3; A_ = {r * cos(b), r * sin(b)}; double val_b = dist(A, A_) + calc_A(); if (val_a < val_b) ed = b; else st = a; } double al = (st + ed) / 2; A_ = {r * cos(al), r * sin(al)}; smin(ans, dist(A, A_) + calc_A()); } } printf( %.6lf , ans); }
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#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c, d; cin >> a >> b >> c >> d; long long w, x, y, z; bool f = 1; if (a == c && f) { w = a + abs(d - b); x = b; y = a + abs(d - b); z = d; f = 0; } if (b == d && f) { w = a; x = b + abs(a - c); y = c; z = b + abs(a - c); f = 0; } else if (f) { if (abs(a - c) == abs(b - d)) { w = a; x = d; y = c; z = b; f = 0; } else { cout << -1 << endl; ; } } if (!f) cout << w << << x << << y << << z << endl; ; }
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//==================================================================================================
// Filename : RecursiveKOA_Weighted.v
// Created On : 2016-10-28 08:47:05
// Last Modified : 2016-10-28 09:00:39
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-28 08:46:19
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module WRecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
submidRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
submidRecursiveKOA #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
`ifdef Segmentation1
submidRecursiveKOA #(.SW((SW/2)+1)) middle (
`endif
`ifdef Segmentation2
submidRecursiveKOA2 #(.SW((SW/2)+1)) middle (
`endif
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
submidRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
submidRecursiveKOA #(.SW((SW/2)+1)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
`ifdef Segmentation1
submidRecursiveKOA #(.SW(SW/2+2)) middle (
`endif
`ifdef Segmentation2
submidRecursiveKOA2 #(.SW(SW/2+2)) middle (
`endif
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; long long dp[1001][2001][4]; long long solve(long long n, long long k, long long i) { if (dp[n][k][i] != -1) { return dp[n][k][i]; } if (k < 1 || k > 2 * n) return 0; if (i == 0) { dp[n][k][i] = solve(n - 1, k, 0) + solve(n - 1, k - 1, 1) + solve(n - 1, k - 1, 2) + solve(n - 1, k - 2, 3); } else if (i == 1) { dp[n][k][i] = solve(n - 1, k, 0) + solve(n - 1, k, 1) + solve(n - 1, k - 1, 2) + solve(n - 1, k, 3); } else if (i == 2) { dp[n][k][i] = solve(n - 1, k, 0) + solve(n - 1, k - 1, 1) + solve(n - 1, k, 2) + solve(n - 1, k, 3); } else { dp[n][k][i] = solve(n - 1, k - 2, 0) + solve(n - 1, k - 1, 1) + solve(n - 1, k - 1, 2) + solve(n - 1, k, 3); } dp[n][k][i] %= mod; return dp[n][k][i]; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); memset(dp, -1, sizeof dp); long long n, k; cin >> n >> k; dp[1][1][0] = dp[1][1][3] = 0; dp[1][1][1] = dp[1][1][2] = 1; dp[1][2][0] = dp[1][2][3] = 1; dp[1][2][1] = dp[1][2][2] = 0; cout << (solve(n, k, 0) + solve(n, k, 1) + solve(n, k, 2) + solve(n, k, 3)) % mod << endl; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_6_2 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [23 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(30),
.DIN_TO(7)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
//--------------------------------------------------------------------------------
// sampler.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Produces samples from input applying a programmable divider to the clock.
// Sampling rate can be calculated by:
//
// r = f / (d + 1)
//
// Where r is the sampling rate, f is the clock frequency and d is the value
// programmed into the divider register.
//
// As of version 0.6 sampling on an extClock_mode clock is also supported. If extclock_mode
// is set '1', the extClock_mode clock will be used to sample data. (Divider is
// ignored for this.)
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis (IED) - mygizmos.org
//
`timescale 1ns/100ps
module sampler (
clock, extClock_mode,
wrDivider, config_data,
validIn, dataIn,
// outputs
validOut, dataOut, ready50);
input clock; // internal clock
input extClock_mode; // clock selection
input wrDivider; // write divider register
input [23:0] config_data; // configuration data
input validIn; // dataIn is valid
input [31:0] dataIn; // 32 input channels
output validOut; // new sample ready
output [31:0] dataOut; // sampled data
output ready50;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
//
// Registers...
//
reg validOut, next_validOut;
reg [31:0] dataOut, next_dataOut;
reg ready50, next_ready50; // low rate sample signal with 50% duty cycle
reg [23:0] divider, next_divider;
reg [23:0] counter, next_counter; // Made counter decrementing. Better synth.
wire counter_zero = ~|counter;
//
// Generate slow sample reference...
//
initial
begin
divider = 0;
counter = 0;
validOut = 0;
dataOut = 0;
end
always @ (posedge clock)
begin
divider = next_divider;
counter = next_counter;
validOut = next_validOut;
dataOut = next_dataOut;
end
always @*
begin
#1;
next_divider = divider;
next_counter = counter;
next_validOut = FALSE;
next_dataOut = dataOut;
if (extClock_mode)
begin
next_validOut = validIn;
next_dataOut = dataIn;
end
else if (validIn && counter_zero)
begin
next_validOut = TRUE;
next_dataOut = dataIn;
end
//
// Manage counter divider for internal clock sampling mode...
//
if (wrDivider)
begin
next_divider = config_data[23:0];
next_counter = next_divider;
next_validOut = FALSE; // reset
end
else if (validIn)
if (counter_zero)
next_counter = divider;
else next_counter = counter-1'b1;
end
//
// Generate ready50 50% duty cycle sample signal...
//
always @(posedge clock)
begin
ready50 = next_ready50;
end
always @*
begin
#1;
next_ready50 = ready50;
if (wrDivider)
next_ready50 = FALSE; // reset
else if (counter_zero)
next_ready50 = TRUE;
else if (counter == divider[23:1])
next_ready50 = FALSE;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; class Computational_Geometry { public: void init(); void solve(); Computational_Geometry() { EPS = 1e-10; Pi = acos(-1.0); } private: struct node { long long x, y; } point[100010], line[100010]; struct inter { double x, y; } q[100010], p[100010]; int n, m; double EPS, Pi; friend bool operator==(const node &, const node &); friend node operator-(const node &, const node &); friend long long operator*(const node &, const node &); }; bool operator==(const Computational_Geometry::node &a, const Computational_Geometry::node &b) { return (a.x == b.x && a.y == b.y); } Computational_Geometry::node operator-(const Computational_Geometry::node &a, const Computational_Geometry::node &b) { Computational_Geometry::node d; d.x = a.x - b.x; d.y = a.y - b.y; return d; } long long operator*(const Computational_Geometry::node &a, const Computational_Geometry::node &b) { return a.x * b.y - a.y * b.x; } void Computational_Geometry::init() { cin >> n; for (int i = 1; i <= n; i++) cin >> point[i].x >> point[i].y; for (int i = 2; i <= n; i++) line[i] = point[i] - point[1]; } void Computational_Geometry::solve() { bool flag = true; cin >> m; for (int i = 1; i <= m; i++) { if (!flag) continue; node p, now; cin >> p.x >> p.y; now = p - point[1]; if (now * line[2] <= 0 || now * line[n] >= 0) flag = false; int l = 2, r = n - 1; while (l <= r) { int mid = (l + r) / 2; if (now * line[mid + 1] <= 0) r = mid - 1; else l = mid + 1; } if ((p - point[l]) * (point[l + 1] - point[l]) <= 0) flag = false; } if (flag) cout << YES << endl; else cout << NO << endl; } int main() { ios::sync_with_stdio(false); Computational_Geometry ans; ans.init(); ans.solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, G, R, d[100127], w[100127], rt, tot = 0, mi[100127 * 20], c[100127 * 20][2]; long long f[100127], s[100127], ans; void change(int &p, int l, int r, int x, int v) { if (!p) p = ++tot; mi[p] = v; if (l == r) return; int mid = (1ll * l + r) >> 1; (x <= mid) ? change(c[p][0], l, mid, x, v) : change(c[p][1], mid + 1, r, x, v); } int Ask(int p, int l, int r, int L, int R) { if (R < L) return n + 1; if ((!p) || (R < l) || (r < L)) return n + 1; if ((L <= l) && (r <= R)) return mi[p]; int mid = (1ll * l + r) >> 1; return min(Ask(c[p][0], l, mid, L, R), Ask(c[p][1], mid + 1, r, L, R)); } inline int Get(int v) { if (v >= R) return Ask(rt, 0, R + G - 1, (v + G) % (R + G), v - 1); return min(Ask(rt, 0, R + G - 1, v + G, R + G - 1), Ask(rt, 0, R + G - 1, 0, v - 1)); } inline long long calc(int x, int y, int v) { if (y == n + 1) return 0; v = (v + s[y] - s[x]) % (R + G); return R + G - v; } int main() { scanf( %d%d%d , &n, &G, &R); int i, p, x; for (i = 1; i <= n + 1; i++) scanf( %d , &d[i]); w[n + 1] = n + 1; f[n + 1] = 0; for (i = 2; i <= n + 1; i++) s[i] = s[i - 1] + d[i]; for (i = n; i >= 1; i--) { w[i] = Get(s[i] % (R + G)); change(rt, 0, R + G - 1, s[i] % (R + G), i); } for (i = n; i >= 1; i--) f[i] = f[w[i]] + s[w[i]] - s[i] + calc(i, w[i], 0); scanf( %d , &m); while (m--) { scanf( %d , &x); ans = d[1] + x; x = (x + d[1]) % (G + R); if (x >= G) { ans += R + G - x; x = 0; } p = Get((R + G - x) % (R + G)); ans += f[p] + s[p] + calc(1, p, x); printf( %lld n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; const int INF = 1e7; struct info { pair<int, int> x = {-INF, -1}; }; struct segtree { int n; vector<info> t; segtree(int n) { this->n = n; t.resize(n * 4); } void Merge(info &node, info &l, info &r) { node.x = max(l.x, r.x); } void update(int node, int l, int r, int i, int j, int add) { if (l > j || r < i) { return; } if (l >= i && r <= j) { t[node].x = {add, i}; return; } int mid = (l + r) / 2; update(node * 2, l, mid, i, j, add); update(node * 2 + 1, mid + 1, r, i, j, add); Merge(t[node], t[node * 2], t[node * 2 + 1]); } void update(int l, int add) { update(1, 0, n - 1, l, l, add); } info query(int node, int l, int r, int i, int j) { if (l > j || r < i) { info x; return x; } if (l >= i && r <= j) { return t[node]; } int mid = (l + r) / 2; info x = query(node * 2, l, mid, i, j); info y = query(node * 2 + 1, mid + 1, r, i, j); info ret; Merge(ret, x, y); return ret; } pair<int, int> query(int l, int r) { info ret = query(1, 0, n - 1, l, r); return ret.x; } }; int n; int a[N]; int b[N]; int dist[N][2]; vector<int> adj[N]; bool vis[N][2]; int p[N][2]; int go[N][2]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n; segtree seg(n + 1); for (int i = 0; i <= n; i++) { dist[i][0] = INF; dist[i][1] = INF; seg.update(i, INF); } for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= n; i++) { cin >> b[i]; } priority_queue<pair<int, pair<int, int> > > pq; pq.push({0, {n, 0}}); dist[n][0] = 0; dist[n][1] = 0; seg.update(n, 0); while (!pq.empty()) { pair<int, pair<int, int> > t = pq.top(); pq.pop(); int v = t.second.first; int state = t.second.second; if (vis[v][state]) continue; vis[v][state] = 1; if (state == 1) { int koi = v + b[v]; if (dist[koi][0] > dist[v][1]) { dist[koi][0] = dist[v][1]; go[koi][0] = v; pq.push({-dist[koi][0], {koi, 0}}); } continue; } int l = v - a[v]; int r = v; while (true) { pair<int, int> x = seg.query(l, r); if (x.first <= dist[v][0] + 1) { break; } int koi = x.second; dist[koi][1] = dist[v][0] + 1; go[koi][1] = v; seg.update(koi, dist[koi][1]); pq.push({-dist[koi][1], {koi, 1}}); } } if (dist[0][0] >= INF) { cout << -1 n ; return 0; } cout << dist[0][0] << n ; pair<int, int> now = {0, 0}; vector<int> ans; while (1) { if (now.second == 1) { ans.push_back(now.first); } if (now.first == n) { break; } now.first = go[now.first][now.second]; now.second ^= 1; }; reverse(ans.begin(), ans.end()); for (int i : ans) cout << i << ; cout << n ; return 0; }
|
`timescale 1ns/1ns
module CPU_tb ();
reg clk, rst_n, rx;
reg [7:0] switch;
wire tx;
wire [7:0] led;
wire [6:0] digi[3:0];
CPU cpu(
.clk(clk), .rst_n(rst_n),
.switch(switch),
.led(led),
.rx(rx), .tx(tx),
.digi_out1(digi[0]),
.digi_out2(digi[1]),
.digi_out3(digi[2]),
.digi_out4(digi[3])
);
initial begin
clk = 1'b1;
rst_n = 1'b1;
rx = 1'b1;
switch = 8'h69;
#1 rst_n = 1'b0;
#1 rst_n = 1'b1;
#1 rx = 1'b0; // start
#104166 rx = 1'b0;
#104166 rx = 1'b1;
#104166 rx = 1'b0;
#104166 rx = 1'b1;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b1;// end
#104166 rx = 1'b0;// start
#104166 rx = 1'b1;
#104166 rx = 1'b0;
#104166 rx = 1'b1;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b0;
#104166 rx = 1'b1;// end
end
initial
forever #18.5 clk <= ~clk;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:29:40 04/18/2014
// Design Name:
// Module Name: display
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module display(
input wire clk,
input wire [15:0] digit,//disp_num
output reg [ 3:0] node, //4 bit select
output reg [ 7:0] segment);//segment(dot)
reg [3:0] code = 4'b0;
reg [15:0] count = 15'b0;
always @(posedge clk) begin
case (count[15:14])
//divide frequence
2'b00 : begin
node <= 4'b1110;
code <= digit[3:0];
end
2'b01 : begin
node <= 4'b1101;
code <= digit[7:4];
end
2'b10 : begin
node <= 4'b1011;
code <= digit[11:8];
end
2'b11 : begin
node <= 4'b0111;
code <= digit[15:12];
end
endcase
case (code)
4'b0000: segment <= 8'b11000000;
4'b0001: segment <= 8'b11111001;
4'b0010: segment <= 8'b10100100;
4'b0011: segment <= 8'b10110000;
4'b0100: segment <= 8'b10011001;
4'b0101: segment <= 8'b10010010;
4'b0110: segment <= 8'b10000010;
4'b0111: segment <= 8'b11111000;
4'b1000: segment <= 8'b10000000;
4'b1001: segment <= 8'b10010000;
4'b1010: segment <= 8'b10001000;
4'b1011: segment <= 8'b10000011;
4'b1100: segment <= 8'b11000110;
4'b1101: segment <= 8'b10100001;
4'b1110: segment <= 8'b10000110;
4'b1111: segment <= 8'b10001110;
default: segment <= 8'b00000000;
endcase
count <= count + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = int(3e5), mod = int(1e9) + 7; int n; int a[N], c[N]; long long t[N]; long long x[N], pref[N]; long double p[N]; long long suf[N]; void upd(int v, int val) { v += n - 1; t[v] += val; c[v]++; while (v > 1) { v >>= 1; t[v] = t[v + v] + t[v + v + 1]; c[v] = c[v + v] + c[v + v + 1]; } } long long get(int l, int r) { l += n - 1; r += n - 1; long long res = 0; while (l <= r) { if (l & 1) res += t[l]; if (!(r & 1)) res += t[r]; l = (l + 1) >> 1; r = (r - 1) >> 1; } return res; } int cnt(int l, int r) { l += n - 1; r += n - 1; int res = 0; while (l <= r) { if (l & 1) res += c[l]; if (!(r & 1)) res += c[r]; l = (l + 1) >> 1; r = (r - 1) >> 1; } return res; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } long long all = 1ll * n * (n + 1) / 2; long double res = 0; for (int i = 1; i <= n; i++) { long long cur = get(1, a[i] - 1); long double p = (cur + 0.0) * (n - i + 1) / all; res += p * 0.5; cur = get(a[i] + 1, n); p = (cur + 0.0) * (n - i + 1) / all; res += cnt(a[i] + 1, n); res -= p * 0.5; upd(a[i], i); } printf( %.12lf , double(res)); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, x, dd[270000]; int main() { cin >> n >> x; int limit = (1 << n) - 1; vector<int> Q; Q.push_back(0); for (int i = 1; i <= limit; i++) { if (i == x) continue; if (dd[i]) continue; Q.push_back(i); dd[(i ^ x)] = 1; } cout << Q.size() - 1 << endl; for (int i = 1; i < Q.size(); i++) { cout << (Q[i] ^ Q[i - 1]) << ; } }
|
/*
* LatticeMico32
* JTAG Test Access Port For Xilinx Sparan-6 Devices
*
* Copyright (C) 2010 Michael Walle
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module jtag_tap(
output tck,
output tdi,
input tdo,
output shift,
output update,
output reset
);
wire g_shift;
wire g_update;
assign shift = g_shift & sel;
assign update = g_update & sel;
BSCAN_SPARTAN6 #(
.JTAG_CHAIN(1)
) bscan (
.CAPTURE(),
.DRCK(tck),
.RESET(reset),
.RUNTEST(),
.SEL(sel),
.SHIFT(g_shift),
.TCK(),
.TDI(tdi),
.TMS(),
.UPDATE(g_update),
.TDO(tdo)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> struct Seg { const T ID = 0; T comb(T a, T b) { return a + b; } long long n; vector<T> seg; void init(long long _n) { n = _n; seg.assign(2 * n, ID); } void pull(long long p) { seg[p] = comb(seg[2 * p], seg[2 * p + 1]); } void upd(long long p, T val) { seg[p += n] = val; for (p /= 2; p; p /= 2) pull(p); } T query(long long l, long long r) { T ra = ID, rb = ID; for (l += n, r += n + 1; l < r; l /= 2, r /= 2) { if (l & 1) ra = comb(ra, seg[l++]); if (r & 1) rb = comb(seg[--r], rb); } return comb(ra, rb); } }; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); long long m; cin >> m; string s; cin >> s; long long n = s.size(); long long a[n]; for (long long i = 0; i < n; ++i) { a[i] = s[i] - a ; } vector<long long> ans; set<array<long long, 2>> ranges; Seg<long long> st; st.init(n); for (long long i = 0; i < n; ++i) { if (i + m - 1 >= n) break; ranges.insert({i, i + m - 1}); } for (long long i = 0; i < 26; ++i) { bool fin = 1; for (long long j = 0; j < n; ++j) { if (a[j] == i) { st.upd(j, 1); } } for (auto [l, r] : ranges) { fin &= st.query(l, r) > 0; } if (fin) { vector<long long> pos; for (long long j = 0; j < n; ++j) { if (a[j] == i) { st.upd(j, 0); pos.push_back(j); } } for (auto [l, r] : ranges) { if (st.query(l, r)) continue; auto lb = --(lower_bound((pos).begin(), (pos).end(), r + 1)); st.upd(*lb, 1); ans.push_back(i); } break; } else { for (long long j = 0; j < n; ++j) { if (a[j] == i) { ans.push_back(i); } } vector<array<long long, 2>> rem; for (auto [l, r] : ranges) { if (st.query(l, r)) { rem.push_back({l, r}); } } for (auto [l, r] : rem) { ranges.erase({l, r}); } } } for (long long i : ans) { cout << (char)(i + a ); } cout << n ; }
|
#include <bits/stdc++.h> using namespace std; struct BookInfo { int t; int a; int b; int i; }; struct CombinedBook { int t; BookInfo b1; BookInfo b2; bool isCombined; }; int main() { ios_base::sync_with_stdio(0); cout << fixed << setprecision(10); cerr << fixed << setprecision(10); cin.tie(0); int n, k; cin >> n >> k; vector<BookInfo> allBooks; int aliceLikes = 0; int bobLikes = 0; for (int i = 0; i < n; i++) { BookInfo info; cin >> info.t >> info.a >> info.b; info.i = i + 1; if (info.a) { aliceLikes++; } if (info.b) { bobLikes++; } allBooks.push_back(info); } if (aliceLikes < k || bobLikes < k) { cout << -1 << endl; return 0; } sort(allBooks.begin(), allBooks.end(), [](const BookInfo &a, const BookInfo &b) -> bool { return a.t < b.t; }); vector<BookInfo> aliceBooks; vector<BookInfo> bobBooks; vector<CombinedBook> combined; vector<BookInfo> other; for (BookInfo &book : allBooks) { if (book.a && book.b) { CombinedBook item; item.t = book.t; item.b1 = book; item.b2 = book; item.isCombined = false; combined.push_back(item); } else if (!book.a && !book.b) { other.push_back(book); } else if (book.a) { aliceBooks.push_back(book); } else if (book.b) { bobBooks.push_back(book); } } for (int i = 0; i < n; i++) { if (i < aliceBooks.size() && i < bobBooks.size()) { CombinedBook item; item.isCombined = true; item.b1 = aliceBooks[i]; item.b2 = bobBooks[i]; item.t = item.b1.t + item.b2.t; combined.push_back(item); } else if (i < aliceBooks.size()) { other.push_back(aliceBooks[i]); } else if (i < bobBooks.size()) { other.push_back(bobBooks[i]); } } if (combined.size() < k) { cout << -1 << endl; return 0; } sort(combined.begin(), combined.end(), [](const CombinedBook &a, const CombinedBook &b) -> bool { return a.t < b.t; }); vector<int> result; int sum = 0; int leftLikes = k; for (int i = 0; i < k; i++) { sum += combined[i].t; } cout << sum << endl; }
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#include <bits/stdc++.h> using namespace std; template <typename T, typename U> std::istream& operator>>(std::istream& i, pair<T, U>& p) { i >> p.first >> p.second; return i; } template <typename T> std::istream& operator>>(std::istream& i, vector<T>& t) { for (auto& v : t) { i >> v; } return i; } template <typename T, typename U> std::ostream& operator<<(std::ostream& o, const pair<T, U>& p) { o << p.first << << p.second; return o; } template <typename T> std::ostream& operator<<(std::ostream& o, const vector<T>& t) { if (t.empty()) o << n ; for (size_t i = 0; i < t.size(); ++i) { o << t[i] << n [i == t.size() - 1]; } return o; } template <typename T> using minheap = priority_queue<T, vector<T>, greater<T>>; template <typename T> using maxheap = priority_queue<T, vector<T>, less<T>>; template <typename T> bool in(T a, T b, T c) { return a <= b && b < c; } unsigned int logceil(long long first) { return first ? 8 * sizeof(long long) - __builtin_clzll(first) : 0; } namespace std { template <typename T, typename U> struct hash<pair<T, U>> { hash<T> t; hash<U> u; size_t operator()(const pair<T, U>& p) const { return t(p.first) ^ (u(p.second) << 7); } }; } // namespace std template <typename T, typename F> T bsh(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { l = m + 1; r = m; } else { h = m - 1; } } return r; } template <typename F> double bshd(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { l = m; } else { h = m; } } return (l + h) / 2; } template <typename T, typename F> T bsl(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { h = m - 1; r = m; } else { l = m + 1; } } return r; } template <typename F> double bsld(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { h = m; } else { l = m; } } return (l + h) / 2; } template <typename T> T gcd(T a, T b) { if (a < b) swap(a, b); return b ? gcd(b, a % b) : a; } template <typename T> class vector2 : public vector<vector<T>> { public: vector2() {} vector2(size_t a, size_t b, T t = T()) : vector<vector<T>>(a, vector<T>(b, t)) {} }; template <typename T> class vector3 : public vector<vector2<T>> { public: vector3() {} vector3(size_t a, size_t b, size_t c, T t = T()) : vector<vector2<T>>(a, vector2<T>(b, c, t)) {} }; template <typename T> class vector4 : public vector<vector3<T>> { public: vector4() {} vector4(size_t a, size_t b, size_t c, size_t d, T t = T()) : vector<vector3<T>>(a, vector3<T>(b, c, d, t)) {} }; template <typename T> class vector5 : public vector<vector4<T>> { public: vector5() {} vector5(size_t a, size_t b, size_t c, size_t d, size_t e, T t = T()) : vector<vector4<T>>(a, vector4<T>(b, c, d, e, t)) {} }; template <typename T> struct Fenwick { explicit Fenwick(unsigned int N = 0, T t = T()) : N(1u << logceil(N)), F(this->N, t), t(t) {} explicit Fenwick(const vector<T>& A, T t = T()) : N(1u << logceil(A.size())), F(A), t(t) { F.resize(N); fill(F.begin() + A.size(), F.end(), t); for (int i = 0; i < N; i++) { int j = i + lsb(i + 1); if (j < N) F[j] += F[i]; } } void add(int i, T v) { while (i <= N) { F[i] += v; i += lsb(i + 1); } } T sum(int i) const { T sum(t); while (i) { sum += F[i - 1]; i -= lsb(i); } return sum; } T range(int i, int j) const { j++; T s(t); while (j > i) { s += F[j - 1]; j -= lsb(j); } while (i > j) { s -= F[i - 1]; i -= lsb(i); } return s; } T get(int i) const { return range(i, i); } void set(int i, T v) { add(i, v - get(i)); } constexpr int lsb(int i) const { return i & -i; } unsigned int N; vector<T> F; T t; int max_lower(T v) { if (F[0] >= v) return 0; if (F[N - 1] < v) return N - 1; int first = 0; T a = t; for (int s = N >> 1; s > 0; s >>= 1) if (a + F[first + s - 1] < v) { a += F[first + s - 1]; first += s; } return first; } }; template <typename T> struct Fenwick2 { explicit Fenwick2(unsigned int N = 0, T t = T()) : N(1u << logceil(N)), F(this->N, this->N, t), t(t) {} void add(int first, int second, T v) { while (first <= N) { int z = second; while (z <= N) { F[first][z] += v; z += lsb(z + 1); } first += lsb(first + 1); } } T sum(int first, int second) { T sum(t); while (first <= N) { int z = second; while (z <= N) { sum += F[first][z]; z -= lsb(z + 1); } first -= lsb(first + 1); } return sum; } T range(int x1, int y1, int x2, int y2) { T ans = sum(x2, y2); if (x1) ans -= sum(x1 - 1, y2); if (y1) ans -= sum(x2, y1 - 1); if (x1 && y1) ans += sum(x1 - 1, y1 - 1); return ans; } constexpr int lsb(int i) const { return i & -i; } unsigned int N; vector2<T> F; T t; }; class FNiyazAndSmallDegrees { public: int N, X; vector<map<int, int>> E; vector<map<int, int>> ZZ; vector<int> D, V; vector<Fenwick<int>> CNT; vector<Fenwick<long long>> SUM; void add(int hiDeg, int idInFenwick, int cost) { CNT[hiDeg].add(idInFenwick, 1); SUM[hiDeg].add(idInFenwick, cost); } long long sumLowest(int hiDeg, int cnt) { if (cnt <= 0) return 0LL; int id = CNT[hiDeg].max_lower(cnt); if (id == CNT[hiDeg].N - 1) return 1e12; return SUM[hiDeg].sum(id + 1); } pair<long long, long long> solve(int u, int p, long long parentCost) { V[u] = X; long long tot = 0; vector<long long> Q; for (std::pair<int, int> v : E[u]) { if (v.first != p) { auto sol = solve(v.first, u, v.second); tot += sol.first; Q.push_back(sol.second); } } sort(Q.begin(), Q.end()); long long ans1 = 1e12, ans2 = 1e12, pref = 0; vector<long long> sumL(Q.size() + 2); int toRem = D[u] - X; for (int i = 0; i <= Q.size() + 1; ++i) sumL[i] = sumLowest(u, toRem - i); for (int i = 0; i <= Q.size(); ++i) { ans1 = min(ans1, pref + sumL[i]); ans2 = min(ans2, pref + sumL[i + 1]); if (i != Q.size()) pref += Q[i]; } return {tot + ans1, ans2 - ans1 + parentCost}; } void solve(istream& cin, ostream& cout) { cin >> N; E.resize(N); D.resize(N); ZZ.resize(N); for (int i = 0; i < N - 1; ++i) { int a, b, c; cin >> a >> b >> c; --a; --b; E[a][b] = c; E[b][a] = c; } map<int, vector<int>> ByDeg; for (int i = 0; i < N; ++i) { D[i] = E[i].size(); ByDeg[D[i]].push_back(i); vector<std::pair<int, int>> ByCost; for (std::pair<int, int> e : E[i]) ByCost.emplace_back(e.second, e.first); sort(ByCost.begin(), ByCost.end()); for (int j = 0; j < D[i]; ++j) ZZ[i][ByCost[j].second] = j; CNT.emplace_back(D[i], 0); SUM.emplace_back(D[i], 0LL); } V.assign(N, -1); vector<long long> Cost(N, 0LL); for (X = 0; X < N; ++X) { for (int v : ByDeg[X]) { for (std::pair<int, int> q : E[v]) { add(q.first, ZZ[q.first][v], q.second); E[q.first].erase(v); } } ByDeg.erase(X); for (auto& bd : ByDeg) { for (int v : bd.second) { if (V[v] != X) { auto ans = solve(v, -1, 1e12); Cost[X] += ans.first + min(0LL, ans.second); } } } } cout << Cost; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); FNiyazAndSmallDegrees solver; std::istream& in(std::cin); std::ostream& out(std::cout); solver.solve(in, out); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long MAX = 1e3 + 20; long long inf = (long long)1e15; long long mod = (long long)1e9 + 7; long long n, cntr[MAX], cntc[MAX], l[MAX][MAX], used[MAX]; void swpr(long long ind1, long long ind2) { swap(cntr[ind1], cntr[ind2]); for (int i = 1; i <= n; i++) swap(l[ind1][i], l[ind2][i]); } void swpc(long long ind1, long long ind2) { swap(cntc[ind1], cntc[ind2]); for (int i = 1; i <= n; i++) swap(l[i][ind1], l[i][ind2]); } void solve() { cin >> n; for (int i = 0; i < n - 1; i++) { long long x, y; cin >> x >> y; l[x][y] = 1; cntr[x]++; cntc[y]++; } vector<pair<long long, pair<long long, long long>>> ans; long long need = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (cntr[j] == need && !used[j]) { used[i] = 1; need = 0; if (i != j) { swpr(i, j); ans.push_back({1, {i, j}}); } break; } } need++; } for (int i = 2; i <= n; i++) { long long start = (i - 1) - cntr[i] + 1; long long bord = start; while (bord <= n) { if (l[i][bord] == 1) { if (bord != start) { swpc(start, bord); ans.push_back({2, {start, bord}}); } start++; } bord++; } } cout << ans.size() << n ; for (int i = 0; i < ans.size(); i++) { cout << ans[i].first << << ans[i].second.first << << ans[i].second.second << n ; } } int main() { mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); ios::sync_with_stdio(0); long long q; q = 1; while (q--) solve(); return 0; }
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//===----------------------------------------------------------------------===//
//
// Parameterized FIFO with input and output registers and ACL pipeline
// protocol ports. This "FIFO" stores no data and only hands out a sequence of
// numbers from 0..DEPTH-1 (tokens) in round robin fashion.
//
//===----------------------------------------------------------------------===//
module acl_token_fifo_counter
#(
parameter integer DEPTH = 32, // >0
parameter integer STRICT_DEPTH = 1, // 0|1
parameter integer ALLOW_FULL_WRITE = 0 // 0|1
)
(
clock,
resetn,
data_out, // the width of this signal is set by this module, it is the
// responsibility of the top module to make sure the signal
// widths match across this interface.
valid_in,
valid_out,
stall_in,
stall_out,
empty,
full
);
// This fifo is based on acl_valid_fifo
// However, there are 2 differences:
// 1. The fifo is intialized as full
// 2. We keep another counter to serve as the actual token
// STRICT_DEPTH increases FIFO depth to a power of 2 + 1 depth.
// No data, so just build a counter to count the number of valids stored in this "FIFO".
//
// The counter is constructed to count up to a MINIMUM value of DEPTH entries.
// * Logical range of the counter C0 is [0, DEPTH].
// * empty = (C0 <= 0)
// * full = (C0 >= DEPTH)
//
// To have efficient detection of the empty condition (C0 == 0), the range is offset
// by -1 so that a negative number indicates empty.
// * Logical range of the counter C1 is [-1, DEPTH-1].
// * empty = (C1 < 0)
// * full = (C1 >= DEPTH-1)
// The size of counter C1 is $clog2((DEPTH-1) + 1) + 1 => $clog2(DEPTH) + 1.
//
// To have efficient detection of the full condition (C1 >= DEPTH-1), change the
// full condition to C1 == 2^$clog2(DEPTH-1), which is DEPTH-1 rounded up
// to the next power of 2. This is only done if STRICT_DEPTH == 0, otherwise
// the full condition is comparison vs. DEPTH-1.
// * Logical range of the counter C2 is [-1, 2^$clog2(DEPTH-1)]
// * empty = (C2 < 0)
// * full = (C2 == 2^$clog2(DEPTH - 1))
// The size of counter C2 is $clog2(DEPTH-1) + 2.
// * empty = MSB
// * full = ~[MSB] & [MSB-1]
localparam COUNTER_WIDTH = (STRICT_DEPTH == 0) ?
((DEPTH > 1 ? $clog2(DEPTH-1) : 0) + 2) :
($clog2(DEPTH) + 1);
input clock;
input resetn;
output [COUNTER_WIDTH-1:0] data_out;
input valid_in;
output valid_out;
input stall_in;
output stall_out;
output empty;
output full;
logic [COUNTER_WIDTH - 1:0] valid_counter /* synthesis maxfan=1 dont_merge */;
logic incr, decr;
// The logical range for the token is [0,REAL_DEPTH-1], where REAL_DEPTH
// is the actual depth of the fifo taking STRICT_DEPTH into account
// This counter is 1-bit less wide than valid_counter because it is
// unsigned
logic [COUNTER_WIDTH - 2:0] token;
logic token_max;
assign data_out = token;
assign token_max = (STRICT_DEPTH == 0) ?
(~token[$bits(token) - 1] & token[$bits(token) - 2]) :
(token == DEPTH - 1);
assign empty = valid_counter[$bits(valid_counter) - 1];
assign full = (STRICT_DEPTH == 0) ?
(~valid_counter[$bits(valid_counter) - 1] & valid_counter[$bits(valid_counter) - 2]) :
(valid_counter == DEPTH - 1);
assign incr = valid_in & ~stall_out; // push
assign decr = valid_out & ~stall_in; // pop
assign valid_out = ~empty;
assign stall_out = ALLOW_FULL_WRITE ? (full & stall_in) : full;
always @( posedge clock or negedge resetn )
if( !resetn )
begin
valid_counter <= (STRICT_DEPTH == 0) ? (2^$clog2(DEPTH-1)) : DEPTH - 1; // full
token <= 0;
end
else
begin
valid_counter <= valid_counter + incr - decr;
if (decr) // increment token, if popping
token <= token_max ? 0 : token+1;
end
endmodule
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// instantiations
ad_iobuf #(
.DATA_WIDTH(15)
) i_gpio_bd (
.dio_t(gpio_t[14:0]),
.dio_i(gpio_o[14:0]),
.dio_o(gpio_i[14:0]),
.dio_p(gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.ps_intr_13 (1'b0),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes switch and button inputs with a slow sampled shift register
*/
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = 24'd0;
reg [N-1:0] debounce_reg[WIDTH-1:0];
reg [WIDTH-1:0] state;
/*
* The synchronized output is the state register
*/
assign out = state;
integer k;
always @(posedge clk) begin
if (rst) begin
cnt_reg <= 0;
state <= 0;
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= 0;
end
end else begin
if (cnt_reg < RATE) begin
cnt_reg <= cnt_reg + 24'd1;
end else begin
cnt_reg <= 24'd0;
end
if (cnt_reg == 24'd0) begin
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
end
end
for (k = 0; k < WIDTH; k = k + 1) begin
if (|debounce_reg[k] == 0) begin
state[k] <= 0;
end else if (&debounce_reg[k] == 1) begin
state[k] <= 1;
end else begin
state[k] <= state[k];
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int nd, na; int nm; int atq[124], def[124], meu[124]; int foi[124]; int killAll() { memset(foi, 0, sizeof(foi)); for (int i = 0; i < nd; i++) { int j = 0; while (j < nm && (meu[j] <= def[i] || foi[j] == 1)) j++; if (j == nm) return 0; else foi[j] = 1; } int ans = 0; for (int i = 0; i < na; i++) { int j = 0; while (j < nm && (meu[j] < atq[i] || foi[j])) j++; if (j == nm) return 0; if (meu[j] >= atq[i] && !foi[j]) { ans += meu[j] - atq[i]; foi[j] = 1; } } for (int j = 0; j < nm; j++) if (!foi[j]) ans += meu[j]; return ans; } int killAtq() { int me = min(nm, na); int ans = 0; for (int k = 1; k <= me; k++) { int j = nm - k; int aux = 0; for (int i = 0; i < k; i++, j++) { if (meu[j] >= atq[i]) { aux += meu[j] - atq[i]; } } ans = max(ans, aux); } return ans; } int main() { char s[124]; scanf( %d %d , &n, &m); nd = na = nm = 0; int p; for (int i = 0; i < n; i++) { scanf( %s %d , s, &p); if (!strcmp( ATK , s)) atq[na++] = p; if (!strcmp( DEF , s)) def[nd++] = p; } for (int i = 0; i < m; i++) { scanf( %d , &p); meu[nm++] = p; } sort(atq, atq + na); sort(def, def + nd); sort(meu, meu + nm); printf( %d n , max(killAll(), killAtq())); return 0; }
|
//date:2016/3/11
//engineer:ZhaiShaoMin
//module name:inter registers between inst fetch stage and inst decode stage
module core_if_id(//input
clk,
rst,
// stall,
if_id_we,
if_flush,
pc_plus_4,
inst_word,
//used for update Branch predictor
pc,
pred_target,
delayed_PHT,
delayed_BHR,
btb_type,
btb_v,
//output
pc_plus_4_out,
inst_word_out,
pc_out,
pred_target_out,
delayed_PHT_out,
delayed_BHR_out,
btb_type_out,
btb_v_out
);
//input
input clk;
input rst;
input [31:0] pc_plus_4;
input [31:0] inst_word;
input [31:0] pc;
input [31:0] pred_target;
input [1:0] delayed_PHT;
input [2:0] delayed_BHR;
input [1:0] btb_type;
input btb_v;
//input stall;
input if_id_we;
input if_flush;
//output
output [31:0] pc_plus_4_out;
output [31:0] inst_word_out;
output [31:0] pc_out;
output [31:0] pred_target_out;
output [1:0] delayed_PHT_out;
output [2:0] delayed_BHR_out;
output [1:0] btb_type_out;
output btb_v_out;
//reg
reg [31:0] inst_word_out;
reg [31:0] pc_plus_4_out;
reg [31:0] pc_out;
reg [31:0] pred_target_out;
reg [1:0] delayed_PHT_out;
reg [2:0] delayed_BHR_out;
reg [1:0] btb_type_out;
reg btb_v_out;
always@(posedge clk)
begin
if(rst||if_flush)
begin
pc_plus_4_out<=32'h0000;
inst_word_out<=32'h0000;
pc_out<=32'h0000;
pred_target_out<=32'h0000;
delayed_PHT_out<=2'b00;
delayed_BHR_out<=3'b000;
btb_type_out<=2'b00;
btb_v_out<=1'b0;
end
else if(if_id_we)
begin
pc_plus_4_out<=pc_plus_4;
inst_word_out<=inst_word;
pc_out<=pc;
pred_target_out<=pred_target;
delayed_PHT_out<=delayed_PHT;
delayed_BHR_out<=delayed_BHR;
btb_type_out<=btb_type;
btb_v_out<=btb_v;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__XOR3_FUNCTIONAL_PP_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR3_FUNCTIONAL_PP_V
|
// This file is part of multiexp-a5gx.
//
// multiexp-a5gx is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
`timescale 1ns / 1ps
module multiexp_top_sim ();
reg clk;
reg clkin_100_p;
reg pcie_perstn;
reg aclr;
reg wren_reg, flush_reg, readout_reg, restart_reg;
wire [13:0] cusedw_in, cusedw_out;
wire [31:0] cq_in, cdata_out;
reg [31:0] fifo_in;
wire crden, cempty;
wire cfull = '0;
assign cusedw_out = '0;
wire [3:0] status_leds;
initial begin
flush_reg = '0;
readout_reg = '0;
clkin_100_p = '1;
clk = '1;
pcie_perstn = '0;
wren_reg = '0;
aclr = '1;
//#1 pcie_perstn = '1;
#1 aclr = '0;
wren_reg = '1;
/* TESTING LOAD_ERAM
#1024 wren_reg = '0;
pcie_perstn = '1;
#16640 wren_reg = '1;
#16640 wren_reg = '0;
//*/
/* TESTING SET_ADDR and LOAD_TRAM */
#640 flush_reg = '1;
#8 readout_reg = '1;
#8 flush_reg = '0;
#8 readout_reg = '0;
restart_reg = '1;
#8 restart_reg = '0;
#640 flush_reg = '1;
#8 readout_reg = '1;
#8 flush_reg = '0;
#8 readout_reg = '0;
#8 wren_reg = '0; // 85 words in fifo
#1 pcie_perstn = '1;
//*/
/* TESTING READ_RESULT or FLUSH_RESULTS or START_MULT
#8 wren_reg = '0;
pcie_perstn = '1;
//*/
/* 2 words in the input pipe
#8 readout_reg = '1;
#16 wren_reg = '0;
//*/
end
always @(posedge clk or posedge aclr) begin
if (aclr) begin
/* TESTING LOAD_ERAM
fifo_in <= 32'h04000000;
*/
/* TESTING SET_ADDR */
fifo_in <= 32'h10000000;
//*/
/* TESTING READ_RESULT
fifo_in <= 32'h2000BEEF;
//*/
/* TESTING FLUSH_RESULTS
fifo_in <= 32'h40000000;
//*/
/* TESTING START_MULTIPLICATION
fifo_in <= 32'h80000000;
//*/
end else begin
/* TESTING LOAD_ERAM
if (wren_reg) begin
fifo_in <= fifo_in + 1'b1;
end else begin
fifo_in <= fifo_in;
end
//*/
/* TESTING SET_ADDR and LOAD_TRAM */
if (restart_reg) begin
fifo_in <= 32'h10000000;
end else if (flush_reg & ~readout_reg) begin
fifo_in <= 32'h08000000;
end else if (flush_reg & readout_reg) begin
fifo_in <= 32'h08100000;
end else if (readout_reg) begin
fifo_in <= 32'h80000000;
end else if (wren_reg) begin
fifo_in <= fifo_in + 1'b1;
end else begin
fifo_in <= fifo_in;
end
//*/
/* TESTING READ_RESULT or FLUSH_RESULTS or START_MULT
fifo_in <= fifo_in;
//*/
/*
if (readout_reg) begin
fifo_in <= 32'h20000000;
end else begin
fifo_in <= fifo_in;
end
*/
//fifo_in <= 32'h20000000;
end
end
always @(clk) clk <= #4 ~clk;
always @(clkin_100_p) clkin_100_p <= #5 ~clkin_100_p;
scfifo #( .add_ram_output_register ("ON")
, .intended_device_family ("Arria V")
, .lpm_numwords (8192)
, .lpm_showahead ("OFF")
, .lpm_type ("scfifo")
, .lpm_width (32)
, .lpm_widthu (13)
, .overflow_checking ("ON")
, .underflow_checking ("ON")
, .use_eab ("ON")
) f_di ( .clock (clk) // general
, .aclr (aclr)
, .q (cq_in)
, .rdreq (crden)
, .empty (cempty)
, .wrreq (wren_reg)
, .data (fifo_in)
, .usedw (cusedw_in[12:0])
, .full (cusedw_in[13])
, .sclr (1'b0)
, .almost_full ()
, .almost_empty ()
);
wire [12:0] ddr3_a;
wire [2:0] ddr3_ba;
wire [3:0] ddr3_dm;
wire [31:0] ddr3_dq;
wire [3:0] ddr3_dqs_p;
wire [3:0] ddr3_dqs_n;
wire ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_csn, ddr3_rasn, ddr3_casn, ddr3_wen, ddr3_rstn, ddr3_odt;
multiexp_top #( .fifo_widthu (13)
, .n_mult (2)
) imult
( .clk (clk)
, .pcie_perstn (pcie_perstn)
, .pcie_ready (1'b1)
, .user_resetn (1'b1)
, .pll_core_locked (1'b1)
, .fifo_datai (cq_in)
, .fifo_empty (cempty)
, .fifo_rden (crden)
, .fifo_usedw_in (cusedw_in)
, .pcie_writing (1'b1)
, .fifo_datao (cdata_out)
, .fifo_wren (cwren)
, .fifo_usedw_out (cusedw_out)
, .status_leds (status_leds)
, .ddr3_a (ddr3_a)
, .ddr3_ba (ddr3_ba)
, .ddr3_ck_p (ddr3_ck_p)
, .ddr3_ck_n (ddr3_ck_n)
, .ddr3_cke (ddr3_cke)
, .ddr3_csn (ddr3_csn)
, .ddr3_dm (ddr3_dm)
, .ddr3_rasn (ddr3_rasn)
, .ddr3_casn (ddr3_casn)
, .ddr3_wen (ddr3_wen)
, .ddr3_rstn (ddr3_rstn)
, .ddr3_dq (ddr3_dq)
, .ddr3_dqs_p (ddr3_dqs_p)
, .ddr3_dqs_n (ddr3_dqs_n)
, .ddr3_odt (ddr3_odt)
, .ddr3_oct_rzq ()
, .clkin_100_p (clkin_100_p)
);
alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en #(
.MEM_IF_ADDR_WIDTH (13),
.MEM_IF_ROW_ADDR_WIDTH (13),
.MEM_IF_COL_ADDR_WIDTH (10),
.MEM_IF_CONTROL_WIDTH (1),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_BANKADDR_WIDTH (3),
.MEM_IF_DQ_WIDTH (32),
.MEM_IF_CK_WIDTH (1),
.MEM_IF_CLK_EN_WIDTH (1),
.MEM_TRCD (8),
.MEM_TRTP (4),
.MEM_DQS_TO_CLK_CAPTURE_DELAY (450),
.MEM_CLK_TO_DQS_CAPTURE_DELAY (100000),
.MEM_IF_ODT_WIDTH (1),
.MEM_IF_LRDIMM_RM (0),
.MEM_MIRROR_ADDRESSING_DEC (0),
.MEM_REGDIMM_ENABLED (0),
.MEM_LRDIMM_ENABLED (0),
.DEVICE_DEPTH (1),
.MEM_NUMBER_OF_DIMMS (1),
.MEM_NUMBER_OF_RANKS_PER_DIMM (1),
.MEM_GUARANTEED_WRITE_INIT (0),
.MEM_VERBOSE (1),
.REFRESH_BURST_VALIDATION (0),
.MEM_INIT_EN (0),
.MEM_INIT_FILE (""),
.DAT_DATA_WIDTH (32)
) m0 (
.mem_a (ddr3_a), // memory.mem_a
.mem_ba (ddr3_ba), // .mem_ba
.mem_ck (ddr3_ck_p), // .mem_ck
.mem_ck_n (ddr3_ck_n), // .mem_ck_n
.mem_cke (ddr3_cke), // .mem_cke
.mem_cs_n (ddr3_csn), // .mem_cs_n
.mem_dm (ddr3_dm), // .mem_dm
.mem_ras_n (ddr3_rasn), // .mem_ras_n
.mem_cas_n (ddr3_casn), // .mem_cas_n
.mem_we_n (ddr3_wen), // .mem_we_n
.mem_reset_n (ddr3_rstn), // .mem_reset_n
.mem_dq (ddr3_dq), // .mem_dq
.mem_dqs (ddr3_dqs_p), // .mem_dqs
.mem_dqs_n (ddr3_dqs_n), // .mem_dqs_n
.mem_odt (ddr3_odt) // .mem_odt
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps(1e-8), Inf(1e10); const double pi(3.14159265358979); const int N = 6060; struct point { double x, y; } p[N + N] = {}; int n, q, k = 0, a, b, x[N] = {}; double ans[N] = {}; void init() { cin >> n >> q >> a >> b; for (int i = 1; i <= n; ++i) cin >> x[i]; } void work() { p[++k] = {1.0, 2.0 * (-x[1])}; p[++k] = {Inf, 2.0 * (Inf - x[1])}; ans[1] = x[1]; double zero = x[1]; for (int i = 2, d = 1; i <= n; ++i) { for (int j = k; j > d; --j) p[j + 2] = p[j]; k += 2; p[d + 1] = {zero, 0}; p[d + 2] = {zero, 0}; for (int j = 1; j <= d + 1; ++j) p[j].x += a; for (int j = d + 2; j <= k; ++j) p[j].x += b; for (int j = 1; j <= k; ++j) p[j].y += 2 * (p[j].x - x[i]); if (p[1].y > 0) zero = p[1].x, d = 0; else { for (d = 1; p[d].y * p[d + 1].y > 0; ++d) ; zero = (-p[d].y) / (p[d + 1].y - p[d].y) * (p[d + 1].x - p[d].x) + p[d].x; } ans[i] = zero; } ans[n] = min<double>(ans[n], q); for (int i = n - 1; i >= 1; --i) { ans[i] = max(ans[i + 1] - b, ans[i]); ans[i] = min(ans[i + 1] - a, ans[i]); } double sum = 0; for (int i = 1; i <= n; ++i) sum += (x[i] - ans[i]) * (x[i] - ans[i]); for (int i = 1; i <= n; ++i) printf( %.6f , ans[i]); printf( n%.6f n , sum); } int main() { init(); work(); return 0; }
|
module Control(
Inst_i,
Branch_o,
Jump_o,
Control_o
);
input [5:0] Inst_i;
output reg Branch_o,Jump_o;
output reg [7:0] Control_o;
//WB
// Control_o[0] is RegWrite
// Control_o[1] is MemtoReg
//M
// Control_o[2] is MemRead
// Control_o[3] is MemWrite
//EX
// Control_o[4] is ALUSrc
// Control_o[5][6] is ALUOp 2 bit
// Control_o[7] is RegDst
always@(*) begin // R-type
Branch_o = 0;
Jump_o = 0;
if(Inst_i == 6'b000000)begin
Control_o[0] = 1;
Control_o[1] = 0;
Control_o[2] = 0;
Control_o[3] = 0;
Control_o[4] = 0;
Control_o[6:5] = 2'b10;
Control_o[7] = 1;
end
if(Inst_i == 6'b001000)begin // addi
Control_o[0] = 1;
Control_o[1] = 0;
Control_o[2] = 0;
Control_o[3] = 0;
Control_o[4] = 1;
Control_o[6:5] = 2'b00;
Control_o[7] = 0;
end
if(Inst_i == 6'b101011)begin // sw
Control_o[0] = 0;
Control_o[1] = 0;// don't care
Control_o[2] = 0;
Control_o[3] = 1;
Control_o[4] = 1;
Control_o[6:5] = 2'b00;
Control_o[7] = 0; // don't care
end
if(Inst_i == 6'b100011)begin // lw
Control_o[0] = 1;
Control_o[1] = 1;
Control_o[2] = 1;
Control_o[3] = 0;
Control_o[4] = 1;
Control_o[6:5] = 2'b00;
Control_o[7] = 0;
end
if(Inst_i == 6'b000010)begin // j
Jump_o = 1;
Control_o[0] = 0;
Control_o[1] = 0; // don't care
Control_o[2] = 0;
Control_o[3] = 0;
Control_o[4] = 0;
Control_o[6:5] = 2'b00;
Control_o[7] = 0; // don't care
end
if(Inst_i == 6'b000100)begin // beq
Branch_o = 1;
Control_o[0] = 0;
Control_o[1] = 0; // don't care
Control_o[2] = 0;
Control_o[3] = 0;
Control_o[4] = 0;
Control_o[6:5] = 2'b01;
Control_o[7] = 0; // don't care
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class A> void pr(A a) { cout << a; cout << n ; } template <class A, class B> void pr(A a, B b) { cout << a << ; pr(b); } template <class A, class B, class C> void pr(A a, B b, C c) { cout << a << ; pr(b, c); } template <class A, class B, class C, class D> void pr(A a, B b, C c, D d) { cout << a << ; pr(b, c, d); } template <class A> void PR(A a, long long n) { for (long long i = (long long)(0); i < (long long)(n); i++) { if (i) cout << ; cout << a[i]; } cout << n ; } long long check(long long n, long long m, long long x, long long y) { return x >= 0 && x < n && y >= 0 && y < m; } const long long MAX = 1e9 + 7, MAXL = 1LL << 61, dx[4] = {-1, 0, 1, 0}, dy[4] = {0, 1, 0, -1}; void Main() { int T; cin >> T; while (T--) { long long n; string s; cin >> n >> s; long long ans = n; for (long long i = (long long)(0); i < (long long)(n); i++) { if (s[i] == 1 ) { ans = max(ans, (i + 1) * 2); ans = max(ans, (n - i) * 2); } } pr(ans); } } int main() { ios::sync_with_stdio(0); cin.tie(0); Main(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; int a[n + 1]; for (int i = 1; i <= n; ++i) cin >> a[i]; int ans = 0; for (int i = 0; i < m; ++i) { int u, v; cin >> u >> v; ans += min(a[u], a[v]); } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; long long a[N], b[N], x[N]; int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, t; cin >> n >> t; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= n; ++i) cin >> x[i]; for (int i = 1; i <= n; ++i) if (x[i] < i || x[i] < x[i - 1]) return puts( No ), 0; for (int i = 1; i < n; ++i) if (x[i] != x[i + 1] && x[i] != i) return puts( No ), 0; a[n + 1] = a[n] + 5; for (int i = 1; i <= n; ++i) { if (x[i] == i) b[i] = a[i + 1] + t - 1; else b[i] = a[i + 1] + t; if (b[i] == b[i - 1]) return puts( No ), 0; } cout << Yes << endl; for (int i = 1; i <= n; ++i) cout << b[i] << ; cout << n ; return 0; }
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** This Verilog HDL file is used for synthesis in chaining DMA design example
//*
//* This file provides the top level for synthesis
//*/
module pcie_hip_s4gx_gen2_x4_128_example_chaining_top (
// inputs:
free_100MHz,
local_rstn_ext,
pcie_rstn,
refclk,
req_compliance_push_button_n,
rx_in0,
rx_in1,
rx_in2,
rx_in3,
usr_sw,
// outputs:
L0_led,
alive_led,
comp_led,
gen2_led,
lane_active_led,
tx_out0,
tx_out1,
tx_out2,
tx_out3
)
;
output L0_led;
output alive_led;
output comp_led;
output gen2_led;
output [ 3: 0] lane_active_led;
output tx_out0;
output tx_out1;
output tx_out2;
output tx_out3;
input free_100MHz;
input local_rstn_ext;
input pcie_rstn;
input refclk;
input req_compliance_push_button_n;
input rx_in0;
input rx_in1;
input rx_in2;
input rx_in3;
input [ 7: 0] usr_sw;
reg L0_led;
reg [ 24: 0] alive_cnt;
reg alive_led;
wire any_rstn;
reg any_rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102" */;
reg any_rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102" */;
wire clk_out_buf;
reg comp_led;
reg gen2_led;
wire gen2_speed;
reg [ 3: 0] lane_active_led;
wire local_rstn;
wire [ 3: 0] open_lane_width_code;
wire [ 3: 0] open_phy_sel_code;
wire [ 3: 0] open_ref_clk_sel_code;
wire phystatus_ext;
wire [ 1: 0] powerdown_ext;
wire req_compliance_soft_ctrl;
wire [ 7: 0] rxdata0_ext;
wire [ 7: 0] rxdata1_ext;
wire [ 7: 0] rxdata2_ext;
wire [ 7: 0] rxdata3_ext;
wire rxdatak0_ext;
wire rxdatak1_ext;
wire rxdatak2_ext;
wire rxdatak3_ext;
wire rxelecidle0_ext;
wire rxelecidle1_ext;
wire rxelecidle2_ext;
wire rxelecidle3_ext;
wire rxpolarity0_ext;
wire rxpolarity1_ext;
wire rxpolarity2_ext;
wire rxpolarity3_ext;
wire [ 2: 0] rxstatus0_ext;
wire [ 2: 0] rxstatus1_ext;
wire [ 2: 0] rxstatus2_ext;
wire [ 2: 0] rxstatus3_ext;
wire rxvalid0_ext;
wire rxvalid1_ext;
wire rxvalid2_ext;
wire rxvalid3_ext;
wire safe_mode;
wire set_compliance_mode;
wire [ 39: 0] test_in;
wire test_in_32_hip;
wire test_in_5_hip;
wire [ 8: 0] test_out_icm;
wire tx_out0;
wire tx_out1;
wire tx_out2;
wire tx_out3;
wire txcompl0_ext;
wire txcompl1_ext;
wire txcompl2_ext;
wire txcompl3_ext;
wire [ 7: 0] txdata0_ext;
wire [ 7: 0] txdata1_ext;
wire [ 7: 0] txdata2_ext;
wire [ 7: 0] txdata3_ext;
wire txdatak0_ext;
wire txdatak1_ext;
wire txdatak2_ext;
wire txdatak3_ext;
wire txdetectrx_ext;
wire txelecidle0_ext;
wire txelecidle1_ext;
wire txelecidle2_ext;
wire txelecidle3_ext;
assign safe_mode = 1;
assign local_rstn = safe_mode | local_rstn_ext;
assign any_rstn = pcie_rstn & local_rstn;
assign test_in[39 : 33] = 0;
assign set_compliance_mode = usr_sw[0];
assign req_compliance_soft_ctrl = 0;
assign test_in[32] = test_in_32_hip;
assign test_in[31 : 9] = 0;
assign test_in[8 : 6] = safe_mode ? 4'b010 : usr_sw[3 : 1];
assign test_in[5] = test_in_5_hip;
assign test_in[4 : 0] = 5'b01000;
//reset Synchronizer
always @(posedge clk_out_buf or negedge any_rstn)
begin
if (any_rstn == 0)
begin
any_rstn_r <= 0;
any_rstn_rr <= 0;
end
else
begin
any_rstn_r <= 1;
any_rstn_rr <= any_rstn_r;
end
end
//LED logic
always @(posedge clk_out_buf or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
alive_cnt <= 0;
alive_led <= 0;
comp_led <= 0;
L0_led <= 0;
lane_active_led <= 0;
end
else
begin
alive_cnt <= alive_cnt +1;
alive_led <= alive_cnt[24];
comp_led <= ~(test_out_icm[4 : 0] == 5'b00011);
L0_led <= ~(test_out_icm[4 : 0] == 5'b01111);
lane_active_led[3 : 0] <= ~(test_out_icm[8 : 5]);
end
end
//Gen2 LED logic
always @(posedge clk_out_buf or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
gen2_led <= 0;
else
gen2_led <= ~gen2_speed;
end
altpcierd_compliance_test pcie_compliance_test_enable
(
.local_rstn (local_rstn_ext),
.pcie_rstn (pcie_rstn),
.refclk (refclk),
.req_compliance_push_button_n (req_compliance_push_button_n),
.req_compliance_soft_ctrl (req_compliance_soft_ctrl),
.set_compliance_mode (set_compliance_mode),
.test_in_32_hip (test_in_32_hip),
.test_in_5_hip (test_in_5_hip)
);
pcie_hip_s4gx_gen2_x4_128_example_chaining_pipen1b core
(
.core_clk_out (clk_out_buf),
.free_100MHz (free_100MHz),
.gen2_speed (gen2_speed),
.lane_width_code (open_lane_width_code),
.local_rstn (local_rstn),
.pcie_rstn (pcie_rstn),
.phy_sel_code (open_phy_sel_code),
.phystatus_ext (phystatus_ext),
.pipe_mode (1'b0),
.pld_clk (clk_out_buf),
.powerdown_ext (powerdown_ext),
.ref_clk_sel_code (open_ref_clk_sel_code),
.refclk (refclk),
.rx_in0 (rx_in0),
.rx_in1 (rx_in1),
.rx_in2 (rx_in2),
.rx_in3 (rx_in3),
.rxdata0_ext (rxdata0_ext),
.rxdata1_ext (rxdata1_ext),
.rxdata2_ext (rxdata2_ext),
.rxdata3_ext (rxdata3_ext),
.rxdatak0_ext (rxdatak0_ext),
.rxdatak1_ext (rxdatak1_ext),
.rxdatak2_ext (rxdatak2_ext),
.rxdatak3_ext (rxdatak3_ext),
.rxelecidle0_ext (rxelecidle0_ext),
.rxelecidle1_ext (rxelecidle1_ext),
.rxelecidle2_ext (rxelecidle2_ext),
.rxelecidle3_ext (rxelecidle3_ext),
.rxpolarity0_ext (rxpolarity0_ext),
.rxpolarity1_ext (rxpolarity1_ext),
.rxpolarity2_ext (rxpolarity2_ext),
.rxpolarity3_ext (rxpolarity3_ext),
.rxstatus0_ext (rxstatus0_ext),
.rxstatus1_ext (rxstatus1_ext),
.rxstatus2_ext (rxstatus2_ext),
.rxstatus3_ext (rxstatus3_ext),
.rxvalid0_ext (rxvalid0_ext),
.rxvalid1_ext (rxvalid1_ext),
.rxvalid2_ext (rxvalid2_ext),
.rxvalid3_ext (rxvalid3_ext),
.test_in (test_in),
.test_out_icm (test_out_icm),
.tx_out0 (tx_out0),
.tx_out1 (tx_out1),
.tx_out2 (tx_out2),
.tx_out3 (tx_out3),
.txcompl0_ext (txcompl0_ext),
.txcompl1_ext (txcompl1_ext),
.txcompl2_ext (txcompl2_ext),
.txcompl3_ext (txcompl3_ext),
.txdata0_ext (txdata0_ext),
.txdata1_ext (txdata1_ext),
.txdata2_ext (txdata2_ext),
.txdata3_ext (txdata3_ext),
.txdatak0_ext (txdatak0_ext),
.txdatak1_ext (txdatak1_ext),
.txdatak2_ext (txdatak2_ext),
.txdatak3_ext (txdatak3_ext),
.txdetectrx_ext (txdetectrx_ext),
.txelecidle0_ext (txelecidle0_ext),
.txelecidle1_ext (txelecidle1_ext),
.txelecidle2_ext (txelecidle2_ext),
.txelecidle3_ext (txelecidle3_ext)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHETAP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DECAPHETAP_PP_BLACKBOX_V
/**
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__decaphetap (
VPWR,
VGND,
VPB
);
input VPWR;
input VGND;
input VPB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHETAP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; void sync_stdio() { cin.tie(NULL); ios_base::sync_with_stdio(false); } struct Sync_stdio { Sync_stdio() { cin.tie(NULL); ios_base::sync_with_stdio(false); } } _sync_stdio; int intersect(pair<int, int> a, pair<int, int> b) { return !(b.second <= a.first || a.second <= b.first); } int main() { int a, ta, b, tb; scanf( %d%d%d%d , &a, &ta, &b, &tb); int h, m; scanf( %d:%d , &h, &m); int tm = h * 60 + m; int START = 5 * 60; int END = 24 * 60; int res = 0; for (int i = START; i < END; i += b) { if (intersect({tm, tm + ta}, {i, i + tb})) { ++res; } } printf( %d , res); return 0; }
|
// vim:set shiftwidth=3 softtabstop=3 expandtab:
module register_file (rsel, wsel, rdata, wdata, wen, rst, clk);
input [5:0] rsel, wsel;
output [32:0] rdata;
input [32:0] wdata;
input wen, rst, clk;
register zero(.wen(wen), .rst(rst), .clk(clk));
register at(.wen(wen), .rst(rst), .clk(clk));
register v0(.wen(wen), .rst(rst), .clk(clk));
register v1(.wen(wen), .rst(rst), .clk(clk));
register a0(.wen(wen), .rst(rst), .clk(clk));
register a1(.wen(wen), .rst(rst), .clk(clk));
register a2(.wen(wen), .rst(rst), .clk(clk));
register a3(.wen(wen), .rst(rst), .clk(clk));
register t0(.wen(wen), .rst(rst), .clk(clk));
register t1(.wen(wen), .rst(rst), .clk(clk));
register t2(.wen(wen), .rst(rst), .clk(clk));
register t3(.wen(wen), .rst(rst), .clk(clk));
register t4(.wen(wen), .rst(rst), .clk(clk));
register t5(.wen(wen), .rst(rst), .clk(clk));
register t6(.wen(wen), .rst(rst), .clk(clk));
register t7(.wen(wen), .rst(rst), .clk(clk));
register s0(.wen(wen), .rst(rst), .clk(clk));
register s1(.wen(wen), .rst(rst), .clk(clk));
register s2(.wen(wen), .rst(rst), .clk(clk));
register s3(.wen(wen), .rst(rst), .clk(clk));
register s4(.wen(wen), .rst(rst), .clk(clk));
register s5(.wen(wen), .rst(rst), .clk(clk));
register s6(.wen(wen), .rst(rst), .clk(clk));
register s7(.wen(wen), .rst(rst), .clk(clk));
register t8(.wen(wen), .rst(rst), .clk(clk));
register t9(.wen(wen), .rst(rst), .clk(clk));
register k0(.wen(wen), .rst(rst), .clk(clk));
register k1(.wen(wen), .rst(rst), .clk(clk));
register gp(.wen(wen), .rst(rst), .clk(clk));
register sp(.wen(wen), .rst(rst), .clk(clk));
register fp(.wen(wen), .rst(rst), .clk(clk));
register ra(.wen(wen), .rst(rst), .clk(clk));
assign zero.in = 0;
always @(posedge clk) begin
if(wen) begin
case(wsel)
0: zero.in = wdata;
1: at.in = wdata;
2: v0.in = wdata;
3: v1.in = wdata;
4: a0.in = wdata;
5: a1.in = wdata;
6: a2.in = wdata;
7: a3.in = wdata;
8: t0.in = wdata;
9: t1.in = wdata;
10: t2.in = wdata;
11: t3.in = wdata;
12: t4.in = wdata;
13: t5.in = wdata;
14: t6.in = wdata;
15: t7.in = wdata;
16: s0.in = wdata;
17: s1.in = wdata;
18: s2.in = wdata;
19: s3.in = wdata;
20: s4.in = wdata;
21: s5.in = wdata;
22: s6.in = wdata;
23: s7.in = wdata;
24: t8.in = wdata;
25: t9.in = wdata;
26: k0.in = wdata;
27: k1.in = wdata;
28: gp.in = wdata;
29: sp.in = wdata;
30: fp.in = wdata;
31: ra.in = wdata;
endcase
end else begin
case(rsel)
0: rdata = zero.out;
1: rdata = at.out;
2: rdata = v0.out;
3: rdata = v1.out;
4: rdata = a0.out;
5: rdata = a1.out;
6: rdata = a2.out;
7: rdata = a3.out;
8: rdata = t0.out;
9: rdata = t1.out;
10: rdata = t2.out;
11: rdata = t3.out;
12: rdata = t4.out;
13: rdata = t5.out;
14: rdata = t6.out;
15: rdata = t7.out;
16: rdata = s0.out;
17: rdata = s1.out;
18: rdata = s2.out;
19: rdata = s3.out;
20: rdata = s4.out;
21: rdata = s5.out;
22: rdata = s6.out;
23: rdata = s7.out;
24: rdata = t8.out;
25: rdata = t9.out;
26: rdata = k0.out;
27: rdata = k1.out;
28: rdata = gp.out;
29: rdata = sp.out;
30: rdata = fp.out;
31: rdata = ra.out;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; int tmp; int ans = 0; cin >> n; for (int i = 1; i <= n; i++) { for (int j = 1; j <= i; j++) { tmp = i * i + j * j; if (tmp <= n * n && int(sqrt(tmp)) * int(sqrt(tmp)) == tmp) { ans++; } } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a[100 * 100 + 5]; pair<int, int> as[100 * 10000 + 5]; pair<int, int> ass[100 * 1000 * 7 + 5]; int p = 0; int badbakhti(int l, int r) { if (r - l < 2) { return 1; } int h = -10000 * 100000, e = (r + l) / 2; h = a[e].first; for (int i = l; i < r; i++) { if (i != e) { as[p].first = a[e].first; as[p].second = a[i].second; p++; } } badbakhti(l, e); badbakhti(e, r); return 1; } int main() { int n; cin >> n; int d, q; for (int i = 0; i < n; i++) { cin >> d >> q; a[i] = make_pair(d, q); as[p] = make_pair(d, q); p++; } sort(a, a + n); badbakhti(0, n); sort(as, as + p); int u = 0, er = 0; for (int i = 0; i < p; i++) { u = i; while (as[i].first == as[u].first && as[i].second == as[u].second) u++; ass[er].first = as[i].first; ass[er].second = as[i].second; er++; i = u - 1; } cout << er << endl; for (int i = 0; i < er; i++) { cout << ass[i].first << << ass[i].second << endl; } }
|
module test_def(a, y);
`define MSB_LSB_SEP :
`define get_msb(off, len) ((off)+(len)-1)
`define get_lsb(off, len) (off)
`define sel_bits(offset, len) `get_msb(offset, len) `MSB_LSB_SEP `get_lsb(offset, len)
input [31:0] a;
output [7:0] y;
assign y = a[`sel_bits(16, 8)];
endmodule
// ---------------------------------------------------
module test_ifdef(a, y);
input [2:0] a;
output reg [31:0] y;
always @* begin
y = 0;
`undef X
`ifdef X
y = y + 42;
`else
`undef A
`undef B
`ifdef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`undef A
`define B
`ifdef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`define A
`undef B
`ifdef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`define A
`define B
`ifdef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
// ------------------------------------
`undef A
`undef B
`ifndef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`undef A
`define B
`ifndef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`define A
`undef B
`ifndef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`define A
`define B
`ifndef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
// ------------------------------------
`undef A
`ifdef A
y = (y << 1) | a[0];
`else
y = (y << 1) | a[2];
`endif
`define A
`ifdef A
y = (y << 1) | a[0];
`else
y = (y << 1) | a[2];
`endif
// ------------------------------------
`undef A
`ifndef A
y = (y << 1) | a[0];
`else
y = (y << 1) | a[2];
`endif
`define A
`ifndef A
y = (y << 1) | a[0];
`else
y = (y << 1) | a[2];
`endif
`endif
`define X
`ifdef X
`undef A
`undef B
`ifdef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`undef A
`define B
`ifdef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`define A
`undef B
`ifdef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`define A
`define B
`ifdef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
// ------------------------------------
`undef A
`undef B
`ifndef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`undef A
`define B
`ifndef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`define A
`undef B
`ifndef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
`define A
`define B
`ifndef A
y = (y << 1) | a[0];
`elsif B
y = (y << 1) | a[1];
`else
y = (y << 1) | a[2];
`endif
// ------------------------------------
`undef A
`ifdef A
y = (y << 1) | a[0];
`else
y = (y << 1) | a[2];
`endif
`define A
`ifdef A
y = (y << 1) | a[0];
`else
y = (y << 1) | a[2];
`endif
// ------------------------------------
`undef A
`ifndef A
y = (y << 1) | a[0];
`else
y = (y << 1) | a[2];
`endif
`define A
`ifndef A
y = (y << 1) | a[0];
`else
y = (y << 1) | a[2];
`endif
`else
y = y + 42;
`endif
end
endmodule
`define SIZE 4 // comment supported in this part
module test_comment_in_macro ( din_a, dout_a );
input [`SIZE-1:0] din_a;
output [`SIZE-1:0] dout_a;
assign dout_a = din_a | `SIZE'ha;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 1 << 13; const int N = 13; long long dp[M][N][2][2]; bool used[M][N][2][2]; vector<int> digits_hour, digits_minuts; long long solve(int mask, int pos, bool flag1, bool flag2) { int h = digits_hour.size(); int min = digits_minuts.size(); if (pos == h + min) { return 1LL; } long long &ans = dp[mask][pos][flag1][flag2]; if (used[mask][pos][flag1][flag2]) { return ans; } used[mask][pos][flag1][flag2] = true; if (pos >= h) { for (int t = 0; t < 7; t++) { int el = 1 << t; if ((mask & el) == 0) { if (flag2 || digits_minuts[pos - h] >= t) { ans += solve(mask | el, pos + 1, flag1, flag2 || (digits_minuts[pos - h] > t)); } } } } else { for (int t = 0; t < 7; t++) { int el = 1 << t; if ((mask & el) == 0) { if (flag1 || digits_hour[pos] >= t) { ans += solve(mask | el, pos + 1, flag1 || (digits_hour[pos] > t), flag2); } } } } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n, m; scanf( %d %d , &n, &m); n--, m--; if (n == 0) { digits_hour.push_back(0); } if (m == 0) { digits_minuts.push_back(0); } while (n) { digits_hour.push_back(n % 7); n /= 7; } reverse(digits_hour.begin(), digits_hour.end()); while (m) { digits_minuts.push_back(m % 7); m /= 7; } reverse(digits_minuts.begin(), digits_minuts.end()); printf( %lld n , solve(0, 0, false, false)); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void umax(T &a, T b) { if (a < b) a = b; } const int maxn = 100 + 10; const int INF = 1e9 + 7; char a[maxn][maxn]; int c[maxn], d[maxn]; inline void solve(void) { int n; cin >> n; for (int i = (0); i < (n); i++) cin >> a[i]; for (int i = (0); i < (n); i++) cin >> c[i]; vector<int> ans; for (int i = (0); i < (n); i++) { if (d[i] != c[i]) continue; queue<int> v; v.push(i); while (!v.empty()) { int node = v.front(); ans.push_back(node); v.pop(); for (int j = (0); j < (n); j++) { if (a[node][j] == 1 ) { d[j]++; if (d[j] == c[j]) v.push(j); } } } } cout << ans.size() << endl; for (int i = (0); i < (ans.size()); i++) cout << ans[i] + 1 << ; } void init() { ios::sync_with_stdio(false); cin.tie(nullptr); } int main(int argc, const char *argv[]) { solve(); return 0; }
|
/*
* lzw - Simple, Logarithmic Right Shift
* Copyright (C) 2015 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_RIGHT_SHIFT
`else
`define INC_RIGHT_SHIFT
`timescale 1 ns / 100 ps
module RightShift(
ovalue,
ivalue,
amount
);
parameter LOGWORD=0;
localparam WORD=(1<<LOGWORD);
output reg [WORD-1:0] ovalue; // shifted value
input [WORD-1:0] ivalue; // original value
input [LOGWORD-1:0] amount; // amount by which to shift right
reg [WORD-1:0] rank [LOGWORD+1-1:0]; // intermediate shifts; +1 is aliased to ivalue
always @(*) begin
rank[LOGWORD] <= ivalue;
end
genvar i;
genvar j;
generate
for(i=0; i<LOGWORD; i=i+1) begin : i_right_shift // iterates over logarithmically-spaced ranks
always @(*) begin
if(amount[i]) begin
rank[i] <= rank[i+1][WORD-1:(1<<i)];
end
else begin
rank[i] <= rank[i+1];
end
end
end
endgenerate
always @(*) begin
ovalue <= rank[0];
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int n; long double V; long double vx[111111], vy[111111]; int m, N; struct point { long double x, y; bool operator<(const point &b) const { return (x != b.x) ? (x < b.x) : (y > b.y); } } ans[111111], a[111111]; pair<long double, int> k[111111], b[111111], c[111111]; long double cs[111111]; int main() { double V2; scanf( %d%lf , &n, &V2); V = V2; for (int i = 1; i <= n; ++i) { double ang; scanf( %lf , &ang); long double t = ang; long double x = cos(t) * V * sin(t) * V / (0.5 * (9.8)); ans[i].x = x; ans[i].y = 0; k[i] = make_pair(tan(ang), i); } scanf( %d , &m); long double mn = 1e9; int arc = 0; for (int i = 1; i <= m; ++i) { double x, y; scanf( %lf%lf , &x, &y); a[i].x = x; a[i].y = y; long double A = 0.5 * (9.8) * x * x; long double B = -x * V * V; long double C = 0.5 * x * x * (9.8) + y * V * V; long double D = B * B - 4 * A * C; if (D < 0) { if (x < mn) { mn = x; arc = i; } } else { b[++N] = make_pair((sqrt(D) - B) / 2 / A, i); c[N] = make_pair((-sqrt(D) - B) / 2 / A, i); } } sort(k + 1, k + 1 + n); sort(b + 1, b + 1 + N); int j = 0; long double mn2 = mn; for (int i = 1; i <= n; ++i) { for (; j < N && b[j + 1].first <= k[i].first;) { ++j; mn = min(a[b[j].second].x, mn); } int pos = k[i].second; if (mn < ans[pos].x) { ans[pos].x = mn; ans[pos].y = mn * k[i].first - 0.5 * (9.8) * mn * mn * (1 + k[i].first * k[i].first) / V / V; } } sort(c + 1, c + 1 + N); j = N + 1; mn = mn2; for (int i = n; i >= 1; --i) { for (; j > 1 && c[j - 1].first >= k[i].first;) mn = min(a[c[--j].second].x, mn); int pos = k[i].second; if (mn < ans[pos].x) { ans[pos].x = mn; ans[pos].y = mn * k[i].first - 0.5 * (9.8) * mn * mn * (1 + k[i].first * k[i].first) / V / V; } } for (int i = 1; i <= n; ++i) { double x = ans[i].x, y = ans[i].y; printf( %lf %lf n , x, y); } }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SOC_NIOS_II_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int cap = 1e5 + 10; int main() { long long a[cap]; a[1] = 0; long long n, m; long long Max, Min; cin >> n >> m; if (m == 0) Max = n; else { for (int i = 2; i <= n; i++) { a[i] = a[i - 1] + i - 1; if (a[i] >= m) { Max = n - i; break; } } } Min = n - m * 2; if (Min < 0) Min = 0; cout << Min << << Max << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7, LIM = 1e5; unsigned long long int fact[2 * LIM + 1]; unsigned long long int binpow(long long int x, int y) { unsigned long long int res = 1; while (y > 0) { if (y & 1) res = (res * x) % MOD; y >>= 1; x = (x * x) % MOD; } return res; } unsigned long long int inv_mod(unsigned long long int n) { return binpow(n, MOD - 2); } unsigned long long int com(int n, int r) { return (((fact[n] * inv_mod(fact[r])) % MOD) * inv_mod(fact[n - r])) % MOD; } bool comp(pair<int, int> p, pair<int, int> q) { if (p.first == q.first) return p.second < q.second; return p.first < q.first; } int main() { fact[0] = 1; for (int i = 1; i <= 2 * LIM; i++) { fact[i] = (i * fact[i - 1]) % MOD; } int h, w, n; cin >> h >> w >> n; vector<pair<int, int>> pts(n + 1); for (int i = 0; i < n; i++) { int r, c; cin >> r >> c; pts[i] = {r, c}; } pts[n] = {h, w}; sort(pts.begin(), pts.end(), comp); unsigned long long int dp[n + 1]; for (int i = 0; i <= n; i++) { dp[i] = com(pts[i].first + pts[i].second - 2, pts[i].first - 1); for (int j = 0; j < i; j++) { if (pts[j].first <= pts[i].first && pts[j].second <= pts[i].second) { dp[i] = (dp[i] + MOD - (dp[j] * com(pts[i].first - pts[j].first + pts[i].second - pts[j].second, pts[i].first - pts[j].first)) % MOD) % MOD; } } } cout << dp[n]; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_BLACKBOX_V
`define SKY130_FD_SC_LS__O21BA_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long n, k, l, r, sz, i, len, q, p, mid, anspos, ans[1000001]; long long mxl, mxr; long long pos[1000001], t[1000001], pr[100001]; struct Pair { long long pos; long long x; long long d; }; Pair a[100001], b[100001]; bool cmp(Pair p1, Pair p2) { return p1.x < p2.x; } bool cmd(Pair p1, Pair p2) { return p1.pos < p2.pos; } long long binl(long long L, long long R, long long height) { long long otv = -1; while (L <= R) { mid = L + R; mid /= 2; if (b[mid].x > height) R = mid - 1; else otv = mid, L = mid + 1; } return otv; } long long binr(long long L, long long R, long long height) { long long otv = -1; while (L <= R) { mid = L + R; mid /= 2; if (b[mid].x < height) L = mid + 1; else otv = mid, R = mid - 1; } return otv; } long long tree(long long L, long long R) { long long nn = 0; while (L <= R) { if (L % 2 == 1) nn = max(nn, t[L]); if (R % 2 == 0) nn = max(nn, t[R]); L = (L + 1) / 2; R = (R - 1) / 2; } return nn; } void update(long long x) { x /= 2; while (x) { t[x] = max(t[x * 2], t[x * 2 + 1]); x /= 2; } } int main() { cin >> n >> k; sz = 1; while (sz < n) sz *= 2; for (i = 1; i <= n; i++) { cin >> a[i].x; a[i].pos = i; b[i] = a[i]; } sort(b + 1, b + n + 1, cmp); for (int i = 1; i <= n; i++) pos[b[i].pos] = i, pr[i] = b[i].pos; for (int i = 1; i <= n; i++) { int l = binl(1, pos[i] - 1, a[i].x - k); int r = binr(pos[i] + 1, n, a[i].x + k); int mxl = 0, mxr = 0; if (l > 0) mxl = tree(sz, l + sz - 1); if (r > 0) mxr = tree(r + sz - 1, n + sz - 1); t[pos[i] + sz - 1] = max(mxl, mxr) + 1; update(pos[i] + sz - 1); a[pr[pos[i]]].d = t[pos[i] + sz - 1]; } sort(b + 1, b + n + 1, cmd); cout << t[1] << endl; for (int i = 1; i <= n; i++) { if (a[i].d == t[1]) { p = i; break; } } ans[++q] = p; for (int j = p; j >= 1; j--) { if (a[j].d == a[p].d - 1 && abs(a[j].x - a[p].x) >= k) { ans[++q] = j; p = j; } } for (int i = q; i >= 1; i--) cout << ans[i] << ; return 0; }
|
module counter_16bit (En, Clk, Clr, Q);
input En, Clk, Clr;
output [15:0] Q;
wire [15:0] T, Qs;
t_flipflop T0 (En, Clk, Clr, Qs[0]);
assign T[0] = En & Qs[0];
t_flipflop T1 (T[0], Clk, Clr, Qs[1]);
assign T[1] = T[0] & Qs[1];
t_flipflop T2 (T[1], Clk, Clr, Qs[2]);
assign T[2] = T[1] & Qs[2];
t_flipflop T3 (T[2], Clk, Clr, Qs[3]);
assign T[3] = T[2] & Qs[3];
t_flipflop T4 (T[3], Clk, Clr, Qs[4]);
assign T[4] = T[3] & Qs[4];
t_flipflop T5 (T[4], Clk, Clr, Qs[5]);
assign T[5] = T[4] & Qs[5];
t_flipflop T6 (T[5], Clk, Clr, Qs[6]);
assign T[6] = T[5] & Qs[6];
t_flipflop T7 (T[6], Clk, Clr, Qs[7]);
assign T[7] = T[6] & Qs[7];
t_flipflop T8 (T[7], Clk, Clr, Qs[8]);
assign T[8] = T[7] & Qs[8];
t_flipflop T9 (T[8], Clk, Clr, Qs[9]);
assign T[9] = T[8] & Qs[9];
t_flipflop T10 (T[9], Clk, Clr, Qs[10]);
assign T[10] = T[9] & Qs[10];
t_flipflop T11 (T[10], Clk, Clr, Qs[11]);
assign T[11] = T[10] & Qs[11];
t_flipflop T12 (T[11], Clk, Clr, Qs[12]);
assign T[12] = T[11] & Qs[12];
t_flipflop T13 (T[12], Clk, Clr, Qs[13]);
assign T[13] = T[12] & Qs[13];
t_flipflop T14 (T[13], Clk, Clr, Qs[14]);
assign T[14] = T[13] & Qs[14];
t_flipflop T15 (T[14], Clk, Clr, Qs[15]);
//assign T[15] = T[14] & Qs[15];
assign Q = Qs;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, w1[555][555], w2[555][555], w3[555][555], gl, Pre[300011], anslen; char ch; struct AnsNode { int x, y, z; void init(int _x, int _y, int _z) { x = _x, y = _y, z = _z; } } Ans[1000111]; struct Node { int x, y; void init(int _x, int _y) { x = _x, y = _y; } } gg[300011]; void Read(int &res) { for (ch = getchar(); ch != . && ch != # ; ch = getchar()) ; res = (ch == . ); } void Work(int nowx, int nowy) { int i, dx, dy; gg[gl = 1].init(nowx, nowy); w2[nowx][nowy] = 1; for (i = 1; i <= gl; ++i) { dx = gg[i].x, dy = gg[i].y; if (dx > 1 && w1[dx - 1][dy] && w2[dx - 1][dy] == 0) { w2[dx - 1][dy] = 1; gg[++gl].init(dx - 1, dy); Pre[gl] = i; } if (dx < n && w1[dx + 1][dy] && w2[dx + 1][dy] == 0) { w2[dx + 1][dy] = 1; gg[++gl].init(dx + 1, dy); Pre[gl] = i; } if (dy > 1 && w1[dx][dy - 1] && w2[dx][dy - 1] == 0) { w2[dx][dy - 1] = 1; gg[++gl].init(dx, dy - 1); Pre[gl] = i; } if (dy < m && w1[dx][dy + 1] && w2[dx][dy + 1] == 0) { w2[dx][dy + 1] = 1; gg[++gl].init(dx, dy + 1); Pre[gl] = i; } } for (i = gl; i > 1; --i) { dx = gg[Pre[i]].x, dy = gg[Pre[i]].y; if (w3[dx][dy] == 0) { Ans[++anslen].init(1, dx, dy); w3[dx][dy] = 1; } if (w3[gg[i].x][gg[i].y] == 1) Ans[++anslen].init(0, gg[i].x, gg[i].y); if (w3[gg[i].x][gg[i].y] < 2) Ans[++anslen].init(2, gg[i].x, gg[i].y); w3[gg[i].x][gg[i].y] = 2; } if (w3[dx][dy] == 0) { Ans[++anslen].init(1, nowx, nowy); w3[nowx][nowy] = 1; } } int main() { int i, j; scanf( %d%d , &n, &m); for (i = 1; i <= n; ++i) for (j = 1; j <= m; ++j) Read(w1[i][j]); memset(w2, 0, sizeof(w2)); memset(w3, 0, sizeof(w3)); anslen = 0; for (i = 1; i <= n; ++i) for (j = 1; j <= m; ++j) if (w2[i][j] == 0 && w1[i][j] != 0) Work(i, j); cout << anslen << endl; for (i = 1; i <= anslen; ++i) { if (Ans[i].x == 0) printf( D %d %d n , Ans[i].y, Ans[i].z); else if (Ans[i].x == 1) printf( B %d %d n , Ans[i].y, Ans[i].z); else printf( R %d %d n , Ans[i].y, Ans[i].z); } return 0; }
|
#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) const long long INF = 0x3f3f3f3f3f3f3f3f; const long long llinf = (1LL << 62); const int inf = (1 << 30); const long long nmax = 3e5 + 50; const int mod = 1e9 + 7; const int lim = 1e6; using namespace std; int n, m, a[nmax], b[nmax], st[4 * lim + 50], i, t, x, lzy[4 * lim + 50], q; void push(int nod, int l, int r) { if (l > r) return; if (!lzy[nod]) return; st[nod] += lzy[nod]; if (l != r) { lzy[nod * 2] += lzy[nod]; lzy[nod * 2 + 1] += lzy[nod]; } lzy[nod] = 0; } void upd(int nod, int l, int r, int tl, int tr, int v) { push(nod, l, r); if (tl <= l && r <= tr) { lzy[nod] += v; push(nod, l, r); return; } int mid = (l + r) / 2; if (tl <= mid) upd(nod * 2, l, mid, tl, tr, v); if (mid < tr) upd(nod * 2 + 1, mid + 1, r, tl, tr, v); push(nod * 2, l, mid); push(nod * 2 + 1, mid + 1, r); st[nod] = max(st[nod * 2], st[nod * 2 + 1]); } int qry(int nod, int l, int r) { push(nod, l, r); if (l == r) return l; int mid = (l + r) / 2; push(2 * nod, l, mid); push(2 * nod + 1, mid + 1, r); if (st[2 * nod + 1] > 0) return qry(2 * nod + 1, mid + 1, r); return qry(2 * nod, l, mid); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cerr.tie(0); cout.tie(0); cin >> n >> m; for (i = 1; i <= n; i++) { cin >> a[i]; upd(1, 1, lim, 1, a[i], 1); } for (i = 1; i <= m; i++) { cin >> b[i]; upd(1, 1, lim, 1, b[i], -1); } cin >> q; while (q--) { cin >> t >> i >> x; if (t == 1) { upd(1, 1, lim, 1, a[i], -1); a[i] = x; upd(1, 1, lim, 1, a[i], 1); } else { upd(1, 1, lim, 1, b[i], 1); b[i] = x; upd(1, 1, lim, 1, b[i], -1); } if (st[1] <= 0) cout << -1 << n ; else cout << qry(1, 1, lim) << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_SYMBOL_V
`define SKY130_FD_SC_HS__EBUFN_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_SYMBOL_V
|
#include <bits/stdc++.h> int n, fac[1000005], inv[1000005], ans; int qpow(int a, long long b) { int s = 1; for (; b; b >>= 1, a = 1ll * a * a % 998244353) if (b & 1) s = 1ll * s * a % 998244353; return s; } int C(int n, int m) { return 1ll * fac[n] * inv[n - m] % 998244353 * inv[m] % 998244353; } int add(int x, int y) { return (x += y) >= 998244353 ? x -= 998244353 : x; } int sub(int x, int y) { return (x -= y) < 0 ? x += 998244353 : x; } int main() { scanf( %d , &n), fac[0] = 1; for (register int i = 1; i <= n; ++i) fac[i] = 1ll * fac[i - 1] * i % 998244353; inv[n] = qpow(fac[n], 998244353 - 2); for (register int i = n; i; --i) inv[i - 1] = 1ll * inv[i] * i % 998244353; ans = sub(qpow(3, 1ll * n * n), qpow(sub(qpow(3, n), 3), n)); for (register int i = 1; i <= n; ++i) { int s = 1ll * C(n, i) * add(3ll * qpow(qpow(3, n - i) - 1, n) % 998244353, 1ll * sub(qpow(3, i), 3) * qpow(3, 1ll * n * (n - i)) % 998244353) % 998244353; if (i & 1) ans = add(ans, s); else ans = sub(ans, s); } printf( %d n , ans); }
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/X_INV.v,v 1.5 2005/03/14 21:05:15 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Inverter
// /___/ /\ Filename : INV.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:55 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module INV (O, I);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
not n1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
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#include <bits/stdc++.h> using namespace std; template <typename T, size_t N> int SIZE(const T (&t)[N]) { return N; } template <typename T> int SIZE(const T(&t)) { return t.size(); } string to_string(char b) { return + string({b}) + ; } string to_string(bool b) { return (b ? true : false ); } string to_string(const string &t, int x1 = 0, int x2 = 1e9) { string ret = ; for (int i = min(x1, SIZE(t)), _i = min(x2, SIZE(t) - 1); i <= _i; ++i) { ret += t[i]; } return + ret + ; } string to_string(const char *t) { string ret(t); return to_string(ret); } template <size_t N> string to_string(const bitset<N> &t, int x1 = 0, int x2 = 1e9) { string ret = ; for (int i = min(x1, SIZE(t)), _i = min(x2, SIZE(t) - 1); i <= _i; ++i) { ret += t[i] + 0 ; } return + ret + ; } template <typename T, typename... Coords> string to_string(const T(&t), int x1 = 0, int x2 = 1e9, Coords... C); template <typename T, typename S> string to_string(const pair<T, S>(&t)) { return ( + to_string(t.first) + , + to_string(t.second) + ) ; } template <typename T, typename... Coords> string to_string(const T(&t), int x1, int x2, Coords... C) { string ret = [ ; x1 = min(x1, SIZE(t)); auto e = begin(t); advance(e, x1); for (int i = x1, _i = min(x2, SIZE(t) - 1); i <= _i; ++i) { ret += (i != x1 ? , : ) + to_string(*e, C...); e = next(e); } return ret + ] ; } void dbgm() { ; } template <typename T, typename... S> void dbgm(T t, S... s) { cout << to_string(t) << | ; dbgm(s...); } void dbgs() { ; } template <typename T, typename... S> void dbgs(T t, S... s) { cout << t << ; dbgs(s...); } const long long N = 2e5 + 3, M = 1e9 + 7; int v[N], h[N]; int main() { int n, m; cin >> n >> m; for (int i = 1, _i = n; i <= _i; ++i) { int x; cin >> x; v[i] = x; } sort(v + 1, v + 1 + n); int pt = 0, hans = 0; for (int i = 1, _i = m; i <= _i; ++i) { int x1, x2, y; cin >> x1 >> x2 >> y; if (x1 == 1) { if (x2 == 1e9) { hans++; } else { h[++pt] = x2; } } } m = pt; sort(h + 1, h + 1 + m, greater<int>()); int j = n; int ans = 1e9; for (int i = 1, _i = m + 1; i <= _i; ++i) { while (v[j] > h[i]) { --j; } ans = min(ans, j + max(i - 1, 0)); } dbgs(ans + hans); }
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#include <bits/stdc++.h> using namespace std; int main() { int N(0), aSum(0), bSum(0), cap(0), last(0), out(0); cin >> N; for (int i = 0; i < N; i++) { int a(0), b(0); cin >> a >> b; aSum += a; bSum += b; cap = bSum - aSum; if (cap >= out) out = cap; } cout << out << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int main() { long long f = 0, g = 1; int n; cin >> n; for (int i = 2; i <= n; i++) { long long k = f; f = 3 * g % mod; g = (k + 2 * g) % mod; } printf( %lld , f); return 0; }
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#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; int main() { long long int t, n, i, j, m, d, k, q, y, z, l, r, a, b, c; cin >> t; while (t--) { string str; cin >> str; n = str.length(); z = 0; int p = 0; m = 0; int x = 0; for (i = 0; i < (n); ++i) { z++; if (str[i] == + ) p++; else m++; if (x + p - m < 0) { x++; z += (i + 1); } } cout << z << n ; } }
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// File: UpDown_CounterTBV.v
// Generated by MyHDL 0.10
// Date: Tue Aug 14 06:51:27 2018
`timescale 1ns/10ps
module UpDown_CounterTBV (
);
// myHDL -> Verilog Testbench for `Down_Counter` module
reg clk = 0;
reg rst = 0;
reg Trig = 0;
wire [4:0] count;
reg [0:0] Dir = 1'b0;
reg [4:0] Down_Counter0_0_1_count_i = 17;
always @(posedge clk, negedge rst) begin: UPDOWN_COUNTERTBV_DOWN_COUNTER0_0_1_LOGIC
if (rst) begin
Down_Counter0_0_1_count_i <= 17;
Trig <= 0;
end
else if ((Down_Counter0_0_1_count_i == 0)) begin
Trig <= 1;
Down_Counter0_0_1_count_i <= 17;
end
else begin
Down_Counter0_0_1_count_i <= (Down_Counter0_0_1_count_i - 1);
end
end
assign count = Down_Counter0_0_1_count_i;
always @(rst, clk, Trig, count) begin: UPDOWN_COUNTERTBV_PRINT_DATA
$write("%h", clk);
$write(" ");
$write("%h", rst);
$write(" ");
$write("%h", Trig);
$write(" ");
$write("%h", count);
$write("\n");
end
initial begin: UPDOWN_COUNTERTBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: UPDOWN_COUNTERTBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
case (i)
'h19: begin
Dir <= 1'b1;
end
'h2a: begin
rst <= 1;
end
(-'h1): begin
rst <= 0;
end
default: begin
// pass
end
endcase
if ((i == 59)) begin
$finish;
end
i = i + 1;
@(posedge clk);
end
end
endmodule
|
/*
* Command Buffer
*
* Serial input to parallel output
*
* Check correctness of the received command
*
* Enable/Disable CRC-5 and CRC-16 Encoder/Decoder
*
* Enable to processing the command if the received command is valid
*
* This design of baseband processor is improved by TSMC 0.18 um CMOS standard process
* it does not support EEPROM, so we chose ROM to be the baseband processor's memory
* because we use ROM to be the memory, we are not able to verify the Write command
*/
`timescale 1us / 1ns
module cmd_buf
(
output reg [7:0]cmd,
output [51:0]param,
output package_complete,
output en_crc5,
output en_crc16,
input clk_cmd,
input rst_for_new_package,
input bits_in,
input sync
);
// --- mandatory command of EPC Gen2 protocol ---
parameter QueryRep = 8'b0000_1100;
parameter ACK = 8'b0000_1101;
parameter Query = 8'b0011_1000;
parameter QueryAdjust = 8'b0011_1001;
parameter Select = 8'b0011_1010;
parameter NAK = 8'b1100_0000;
parameter Req_RN = 8'b1100_0001;
parameter Read = 8'b1100_0010;
//parameter Write = 8'b1100_0011;
parameter Kill = 8'b1100_0100;
parameter Lock = 8'b1100_0101;
reg cmd_complete;
reg [52:0]param_tmp;
assign param = param_tmp[51:0];
assign en_crc5 = (cmd_complete & cmd != Query)? 1'b0 : 1'b1;
assign en_crc16 = (cmd_complete & cmd != Select & cmd != Req_RN & cmd != Read & cmd != Kill & cmd != Lock)? 1'b0 : 1'b1;
assign package_complete = (cmd == QueryRep & param_tmp[2])? 1'b1 :
(cmd == ACK & param_tmp[16])? 1'b1 :
(cmd == Query & param_tmp[18])? 1'b1 :
(cmd == QueryAdjust & param_tmp[5])? 1'b1 :
(cmd == Select & param_tmp[52])? 1'b1 :
(cmd == NAK)? 1'b1 :
(cmd == Req_RN & param_tmp[32])? 1'b1 :
(cmd == Read & param_tmp[50])? 1'b1 :
(cmd == Kill & param_tmp[51])? 1'b1 :
(cmd == Lock & param_tmp[52])? 1'b1 : 1'b0;
always@(*) begin
if(cmd == QueryRep | cmd == ACK | cmd == Query |
cmd == QueryAdjust | cmd == Select | cmd == NAK |
cmd == Req_RN | cmd == Read | cmd == Kill | cmd == Lock) cmd_complete = 1'b1;
else cmd_complete = 1'b0;
end
always@(posedge clk_cmd or negedge rst_for_new_package) begin
if(~rst_for_new_package) cmd <= 8'b0000_0011;
else begin
if(sync & ~cmd_complete) cmd <= {cmd[6:0], bits_in};
end
end
always@(posedge clk_cmd or negedge rst_for_new_package) begin
if(~rst_for_new_package) param_tmp <= 53'b1;
else begin
if(cmd_complete & ~package_complete) param_tmp <= {param_tmp[51:0], bits_in};
end
end
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// valid O 1
// word_fst O 64
// word_snd O 5
// verbosity I 4
// CLK I 1 clock
// RST_N I 1 reset
// req_opcode I 7
// req_f7 I 7
// req_rm I 3
// req_rs2 I 5
// req_v1 I 64
// req_v2 I 64
// req_v3 I 64
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFBox_Top(verbosity,
CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_opcode,
req_f7,
req_rm,
req_rs2,
req_v1,
req_v2,
req_v3,
EN_req,
valid,
word_fst,
word_snd);
input [3 : 0] verbosity;
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [6 : 0] req_opcode;
input [6 : 0] req_f7;
input [2 : 0] req_rm;
input [4 : 0] req_rs2;
input [63 : 0] req_v1;
input [63 : 0] req_v2;
input [63 : 0] req_v3;
input EN_req;
// value method valid
output valid;
// value method word_fst
output [63 : 0] word_fst;
// value method word_snd
output [4 : 0] word_snd;
// signals for module outputs
wire [63 : 0] word_fst;
wire [4 : 0] word_snd;
wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid;
// ports of submodule fbox_core
wire [63 : 0] fbox_core$req_v1,
fbox_core$req_v2,
fbox_core$req_v3,
fbox_core$word_fst;
wire [6 : 0] fbox_core$req_f7, fbox_core$req_opcode;
wire [4 : 0] fbox_core$req_rs2, fbox_core$word_snd;
wire [2 : 0] fbox_core$req_rm;
wire fbox_core$EN_req,
fbox_core$EN_server_reset_request_put,
fbox_core$EN_server_reset_response_get,
fbox_core$RDY_server_reset_request_put,
fbox_core$RDY_server_reset_response_get,
fbox_core$valid;
// rule scheduling signals
wire CAN_FIRE_req,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
WILL_FIRE_req,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get;
// action method server_reset_request_put
assign RDY_server_reset_request_put =
fbox_core$RDY_server_reset_request_put ;
assign CAN_FIRE_server_reset_request_put =
fbox_core$RDY_server_reset_request_put ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
fbox_core$RDY_server_reset_response_get ;
assign CAN_FIRE_server_reset_response_get =
fbox_core$RDY_server_reset_response_get ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = fbox_core$valid ;
// value method word_fst
assign word_fst = fbox_core$word_fst ;
// value method word_snd
assign word_snd = fbox_core$word_snd ;
// submodule fbox_core
mkFBox_Core fbox_core(.verbosity(verbosity),
.CLK(CLK),
.RST_N(RST_N),
.req_f7(fbox_core$req_f7),
.req_opcode(fbox_core$req_opcode),
.req_rm(fbox_core$req_rm),
.req_rs2(fbox_core$req_rs2),
.req_v1(fbox_core$req_v1),
.req_v2(fbox_core$req_v2),
.req_v3(fbox_core$req_v3),
.EN_server_reset_request_put(fbox_core$EN_server_reset_request_put),
.EN_server_reset_response_get(fbox_core$EN_server_reset_response_get),
.EN_req(fbox_core$EN_req),
.RDY_server_reset_request_put(fbox_core$RDY_server_reset_request_put),
.RDY_server_reset_response_get(fbox_core$RDY_server_reset_response_get),
.valid(fbox_core$valid),
.word_fst(fbox_core$word_fst),
.word_snd(fbox_core$word_snd));
// submodule fbox_core
assign fbox_core$req_f7 = req_f7 ;
assign fbox_core$req_opcode = req_opcode ;
assign fbox_core$req_rm = req_rm ;
assign fbox_core$req_rs2 = req_rs2 ;
assign fbox_core$req_v1 = req_v1 ;
assign fbox_core$req_v2 = req_v2 ;
assign fbox_core$req_v3 = req_v3 ;
assign fbox_core$EN_server_reset_request_put = EN_server_reset_request_put ;
assign fbox_core$EN_server_reset_response_get =
EN_server_reset_response_get ;
assign fbox_core$EN_req = EN_req ;
endmodule // mkFBox_Top
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#include <bits/stdc++.h> using namespace std; long long a, x = 1e18; int main() { cin >> a; cout << a - x % a * 9 % a * 9 % a << << a - x % a * 9 % a * 9 % a + x - 1; return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; int add(int a, int b) { long long x = a + b; if (x >= 998244353) x -= 998244353; if (x < 0) x += 998244353; return x; } long long mul(long long a, long long b) { return (a * b) % 998244353; } long long pw(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = (ans * a) % 998244353; a = (a * a) % 998244353; b >>= 1; } return ans; } int n; long long dp[2][1000002]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; dp[1][0] = 1; dp[0][0] = 1; for (int i = 1; i <= n; ++i) { int x = (i - 1); if (x % 2 == 0) { int par = (1 + x / 2) % 2; dp[par][i] = mul(dp[!par][x / 2], dp[0][x / 2]); } else { for (int j = x / 2; j <= 1 + x / 2; j++) { int par = (1 + j) % 2; dp[par][i] = mul(dp[!par][j], dp[0][i - j - 1]); } } } cout << (dp[1][n] + dp[0][n]) % 998244353; return 0; }
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#include <bits/stdc++.h> using namespace std; int get() { int f = 0, v = 0; char ch; while (!isdigit(ch = getchar())) if (ch == - ) break; if (ch == - ) f = 1; else v = ch - 0 ; while (isdigit(ch = getchar())) v = v * 10 + ch - 0 ; if (f) return -v; else return v; } const int maxn = 100005, inf = 314000000; vector<int> rule[maxn], g[maxn], belong[maxn]; struct data { int t, v; data() {} data(int _t, int _v) { t = _t, v = _v; } inline bool operator<(const data &b) const { return v > b.v; } }; priority_queue<data> Q; int T[maxn], cnt[maxn], n, m, a[maxn], b[maxn], val[maxn], vis[maxn]; void init() { m = get(), n = get(); memset(a, 60, sizeof(a)); for (int i = 1; i <= m; i++) { int x = get(), y = get(), t; g[x].push_back(i), rule[i].push_back(x); while (y--) if ((t = get()) < 0) val[i]++; else rule[i].push_back(t), belong[t].push_back(i), T[i]++; if (!T[i]) a[x] = min(a[x], val[i]); cnt[i] = val[i]; } } int dfs(int x) { if (vis[x]) return b[x]; vis[x] = 1; for (int i = 0; i < g[x].size(); i++) { int id = g[x][i], flag = 1, tot = cnt[id]; for (int j = 1; j < rule[id].size() && flag; j++) if (a[rule[id][j]] > inf) flag = 0; if (!flag) continue; flag = 0; for (int j = 1; j < rule[id].size(); j++) { int p = rule[id][j], v; if (vis[p] == 1) { flag = 1; break; } v = dfs(p); if (v == -2) { flag = 1; break; } tot = min(tot + v, inf); } if (flag) { b[x] = -2; break; } b[x] = max(b[x], tot); } vis[x] = 2; return b[x]; } void work() { for (int i = 1; i <= n; i++) if (a[i] < 1e9) Q.push(data(i, a[i])); while (!Q.empty()) { data tp = Q.top(); Q.pop(); int t = tp.t, v = tp.v; if (a[t] != v) continue; for (int i = 0; i < belong[t].size(); i++) { int p = belong[t][i], s = rule[p][0]; val[p] = min(val[p] + v, inf); T[p]--; if (!T[p] && a[s] > val[p]) Q.push(data(s, a[s] = val[p])); } } for (int i = 1; i <= n; i++) if (a[i] <= inf) dfs(i); for (int i = 1; i <= n; i++) if (a[i] > inf) puts( -1 -1 ); else printf( %d %d n , a[i], b[i]); } int main() { init(); work(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> v; for (int i = 1; i <= 20; ++i) { int first = ((1 << i) - 1) * (1 << (i - 1)); if (first > 1e5) break; v.push_back(first); } for (int i = v.size() - 1; i >= 0; --i) { if (n % v[i] == 0) return cout << v[i], 0; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, ans; float x, dis, t; struct ponto { float ini, fim; bool operator<(const ponto &lhs) const { return lhs.ini > ini; } } p[1010]; int main() { scanf( %d%f , &n, &t); ans = 2; for (int i = 0; i < n; i++) { scanf( %f%f , &x, &dis); dis /= 2.0; p[i].ini = x - dis; p[i].fim = x + dis; } sort(p, p + n); for (int i = 1; i < n; i++) { if (p[i - 1].fim + t < p[i].ini) ans += 2; else if (p[i - 1].fim + t == p[i].ini) ans++; } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int a[1000000 * 2][2], g[1000000], v[1000000], d[20], f[1000000], e[20]; int n; void ins(int x, int y) { static int sum = 1; a[++sum][0] = y, a[sum][1] = g[x], g[x] = sum; } int gcd(int x, int y) { return !y ? x : gcd(y, x % y); } void dfs(int x, int Gcd, int fa) { int dd[20], ee[20]; for (int i = 0; i < 20; i++) dd[i] = d[i], ee[i] = e[i]; for (int i = g[x]; i; i = a[i][1]) if (a[i][0] != fa) { int Gcd1 = gcd(Gcd, v[a[i][0]]); for (int j = 1; j <= d[0]; j++) d[j] = gcd(v[a[i][0]] / Gcd1, d[j]), e[j] = gcd(e[j], v[a[i][0]]); if (Gcd1 != Gcd) d[++d[0]] = Gcd / Gcd1, e[d[0]] = Gcd; if (x == 1) d[++d[0]] = v[a[i][0]] / Gcd1, e[d[0]] = v[a[i][0]]; int tot = 0; for (int j = 1; j <= d[0]; j++) if (d[j] != 1) d[++tot] = d[j], e[tot] = e[j]; d[0] = tot; f[a[i][0]] = Gcd1; for (int j = 1; j <= d[0]; j++) f[a[i][0]] = max(f[a[i][0]], Gcd1 * d[j]); dfs(a[i][0], Gcd1, x); for (int j = 0; j < 20; j++) d[j] = dd[j], e[j] = ee[j]; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &v[i]); for (int i = 1; i < n; i++) { int x, y; scanf( %d %d , &x, &y); ins(x, y), ins(y, x); } f[1] = v[1]; dfs(1, v[1], 0); for (int i = 1; i <= n; i++) { printf( %d , f[i]); if (i != n) printf( ); } return 0; }
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/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "DeepGATE_include.v"
module convLayerControl #(
parameter SIZE = 16'd125, //number of processing units in this tile
parameter LOOP = 16'd100, //nodes calculated per processing unit
parameter PRV_SIZE = 16'd10, //number of processing units in previous tile
parameter PRV_LOOP = 16'd10, //number of loops in previous tile
parameter FILTER_X = 16'd10,
parameter FILTER_Y = 16'd10,
parameter STRIDE = 16'd1
)(
input clk,
input rstIn,
input dataAvailable,
input ramFull,
output reg enable = 0,
output reg transfer = 0,
output reg tileIdle = 0,
output reg rstNodes = 0,
output reg dataRead = 0,
output reg [15:0] iterationCnt = 0
);
localparam READY = 4'b0001,
PROCESS = 4'b0010,
TRANSFER = 4'b0100,
WAIT = 4'b1000;
reg [3:0] CURRENT_STATE = READY;
reg ramWait = 0;
reg [$clog2(LOOP):0] loopCnt = 0;
/*
Control FSM for each tile.
In state READY the tile waits for data from the previous tile to become
available. In PROCESS, the tile computes the output of each node using
successive add-multiply ops. These outputs are passed through a combinational
approximation of the sigmoid function in one cycle and then TRANSFERred
to RAM. The PROCESS/TRANSFER cycle repeats a LOOP number of times, after
which the state machine enters the WAIT state, where the module idles until
the following tile compute its outputs based on the data in the aforementioned
RAM.
*/
always@(posedge clk) begin
if(rstIn) begin
enable <= 0;
transfer <= 0;
iterationCnt <= 0;
loopCnt <= 0;
tileIdle <= 0;
ramWait <= 0;
rstNodes <= 1;
CURRENT_STATE <= READY;
end
else begin
rstNodes <= 0;
case(CURRENT_STATE)
READY: begin
tileIdle <= 1;
if(dataAvailable) begin
tileIdle <= 0;
dataRead <= 1;
CURRENT_STATE <= PROCESS;
end
end
PROCESS: begin
iterationCnt <= iterationCnt + 1'd1;
if(iterationCnt == PRV_SIZE*PRV_LOOP - 1)
dataRead <= 0;
if(iterationCnt < PRV_SIZE*PRV_LOOP)
enable <= 1;
else begin
enable <= 0;
iterationCnt <= 0;
loopCnt <= loopCnt + 1'b1;
transfer <= 1;
CURRENT_STATE <= TRANSFER;
end
end
TRANSFER: begin
iterationCnt <= iterationCnt + 1'b1;
if(iterationCnt == SIZE - 1'b1) begin
iterationCnt <= 0;
transfer <= 0;
rstNodes <= 1;
if(loopCnt < LOOP) begin
dataRead <= 1;
CURRENT_STATE <= PROCESS;
end
else begin
CURRENT_STATE <= WAIT;
loopCnt <= 0;
end
end
end
WAIT: begin
ramWait <= 1;
if(!ramFull && ramWait) begin
ramWait <= 0;
tileIdle <= 1;
CURRENT_STATE <= READY;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct cell { int x, y, cost; cell(int i, int j, int k) { x = i; y = j; cost = k; } }; int main() { int n, m, s; scanf( %d%d%d , &n, &m, &s); s--; int t1, t2, t3; vector<vector<pair<int, int> > > g(n); vector<int> qq(m), w(m), e(m); for (int i = 0; i < m; ++i) { scanf( %d%d%d , &t1, &t2, &t3); t1--; t2--; qq[i] = t1; w[i] = t2; e[i] = t3; g[t1].push_back(make_pair(t2, t3)); g[t2].push_back(make_pair(t1, t3)); } int l; scanf( %d , &l); vector<int> d(n, 1000000000); d[s] = 0; queue<int> q; q.push(s); d[s] = 0; while (!q.empty()) { int v = q.front(); q.pop(); for (unsigned int i = 0; i < g[v].size(); i++) { int to = g[v][i].first, len = g[v][i].second; if (d[v] + len < d[to]) { d[to] = d[v] + len; q.push(to); } } } int ans = 0; for (int i = 0; i < n; ++i) if (d[i] == l) ans++; for (int i = 0; i < m; ++i) { int x = qq[i], y = w[i], z = e[i]; int k1 = l - d[x]; if (k1 > 0 && k1 != z) { int res = min(d[x] + k1, z - k1 + d[y]); if (res == l) ans++; } int k2 = l - d[y]; if (k2 > 0 && k2 != z - k1 && k2 != z) { int res = min(d[y] + k2, z - k2 + d[x]); if (res == l) ans++; } } cout << ans << endl; return 0; }
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