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// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_7_1 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [15 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(15),
.DIN_TO(0)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2005; const int MOD = 1e9 + 7; int a[N][N]; vector<pair<int, pair<int, int> > > vv; int p[N], dist[N][N]; std::vector<pair<int, int> > v[N]; int visit[N]; int root(int x) { while (x != p[x]) { p[x] = p[p[x]]; x = p[x]; } return x; } void join(int x, int y) { p[root(y)] = root(x); } void dfs(int node, int dis, int start) { visit[node] = start; if (a[start][node] != dis) { printf( NO ); exit(0); } for (auto i : v[node]) { if (visit[i.first] != start) { dfs(i.first, dis + i.second, start); } } } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { scanf( %d , &a[i][j]); if (a[i][j] && i == j) { printf( NO ); return 0; } if (!a[i][j] && i != j) { printf( NO ); return 0; } if (i < j && a[i][j]) { vv.push_back({a[i][j], {i, j}}); } } } sort(vv.begin(), vv.end()); int ct = 0; for (int i = 1; i <= n; i++) p[i] = i; for (auto i : vv) { int wt = i.first, l = i.second.first, r = i.second.second; if (root(l) != root(r)) { join(l, r); v[l].push_back({r, wt}); v[r].push_back({l, wt}); ct++; if (ct == n - 1) break; } } for (int i = 1; i <= n; i++) { dfs(i, 0, i); } printf( YES ); return 0; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module gpio_sbus #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter IO_WIDTH = 8,
parameter IO_DIRECTION = 0,
parameter IO_TRI = 0
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output wire [7:0] BUS_DATA_OUT,
input wire BUS_RD,
input wire BUS_WR,
inout wire [IO_WIDTH-1:0] IO
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
sbus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) sbus_to_ip (
.BUS_CLK(BUS_CLK),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA_IN(BUS_DATA_IN),
.BUS_DATA_OUT(BUS_DATA_OUT),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
gpio_core #(
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(IO_WIDTH),
.IO_DIRECTION(IO_DIRECTION),
.IO_TRI(IO_TRI)
) core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_DATA_OUT(IP_DATA_OUT),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.IO(IO)
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:28 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_rst_ps7_0_100M_0_stub.v
// Design : ip_design_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; string second; cin >> n >> second; string t = second; bool ok = 1; vector<int> vec; for (int i = 0; i < n; i++) { if (second[i] == W ) continue; if (i + 1 < n && second[i + 1] == second[i]) { vec.push_back(i); second[i] = second[i + 1] = W ; continue; } bool foo = 1; int to = -1; for (int j = i + 1; j < n; j++) if (second[j] == second[i]) { to = j; break; } for (int j = i + 1; j < to; j++) if (second[j] == second[i]) foo = 0; if (to == -1) foo = 0; if (foo) { for (int j = i; j < to; j++) { vec.push_back(j); second[j] = W ; } second[to] = W ; continue; } ok = 0; break; } if (ok) { cout << (int)vec.size() << endl; for (auto i : vec) cout << i + 1 << ; cout << endl; return 0; } ok = 1; vec.clear(); second = t; for (int i = 0; i < n; i++) { if (second[i] == B ) continue; if (i + 1 < n && second[i + 1] == second[i]) { vec.push_back(i); second[i] = second[i + 1] = B ; continue; } bool foo = 1; int to = -1; for (int j = i + 1; j < n; j++) if (second[j] == second[i]) { to = j; break; } for (int j = i + 1; j < to; j++) if (second[j] == second[i]) foo = 0; if (to == -1) foo = 0; if (foo) { for (int j = i; j < to; j++) { vec.push_back(j); second[j] = B ; } second[to] = B ; continue; } ok = 0; break; } if (ok) { cout << (int)vec.size() << endl; for (auto i : vec) cout << i + 1 << ; cout << endl; return 0; } cout << -1 << endl; return 0; }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module tb_aceusb();
reg sys_clk;
reg sys_rst;
reg ace_clk;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [6:0] aceusb_a;
wire [15:0] aceusb_d;
wire aceusb_oe_n;
wire aceusb_we_n;
wire ace_clkin;
wire ace_mpce_n;
wire ace_mpirq;
wire usb_cs_n;
wire usb_hpi_reset_n;
wire usb_hpi_int;
aceusb dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_ack_o(wb_ack_o),
.aceusb_a(aceusb_a),
.aceusb_d(aceusb_d),
.aceusb_oe_n(aceusb_oe_n),
.aceusb_we_n(aceusb_we_n),
.ace_clkin(ace_clk),
.ace_mpce_n(ace_mpce_n),
.ace_mpirq(ace_mpirq),
.usb_cs_n(usb_cs_n),
.usb_hpi_reset_n(usb_hpi_reset_n),
.usb_hpi_int(usb_hpi_int)
);
assign aceusb_d = aceusb_oe_n ? 16'h1234 : 16'hzzzz;
initial begin
$dumpfile("aceusb.vcd");
$dumpvars(1, dut);
end
/* Generate ~33MHz SystemACE clock */
initial ace_clk <= 0;
always #7.5 ace_clk <= ~ace_clk;
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 1;
while(~wb_ack_o) begin
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
i = i + 1;
end
$display("Write address %h completed in %d cycles", address, i);
/* Let the core release its ack */
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
wb_we_i = 1'b1;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 1;
while(~wb_ack_o) begin
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
i = i + 1;
end
$display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
/* Let the core release its ack */
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
end
endtask
initial begin
sys_rst = 1'b1;
sys_clk = 1'b0;
wb_adr_i = 32'h00000000;
wb_dat_i = 32'h00000000;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
sys_rst = 1'b0;
wbwrite(32'h00000180, 32'hcafebabe);
wbread(32'h00000020);
$finish;
end
endmodule
|
/**
* bsg_cache_to_axi_tx.v
*
* @author tommy
*/
`include "bsg_defines.v"
module bsg_cache_to_axi_tx
#(parameter `BSG_INV_PARAM(num_cache_p)
,parameter `BSG_INV_PARAM(data_width_p)
,parameter `BSG_INV_PARAM(block_size_in_words_p)
,parameter tag_fifo_els_p=num_cache_p
,parameter `BSG_INV_PARAM(axi_id_width_p)
,parameter `BSG_INV_PARAM(axi_addr_width_p)
,parameter `BSG_INV_PARAM(axi_data_width_p)
,parameter `BSG_INV_PARAM(axi_burst_len_p)
,parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
,parameter axi_strb_width_lp=(axi_data_width_p>>3)
,parameter data_width_ratio_lp=(axi_data_width_p/data_width_p)
)
(
input clk_i
,input reset_i
,input v_i
,output logic yumi_o
,input [lg_num_cache_lp-1:0] tag_i
,input [axi_addr_width_p-1:0] axi_addr_i
// cache dma write channel
,input [num_cache_p-1:0][data_width_p-1:0] dma_data_i
,input [num_cache_p-1:0] dma_data_v_i
,output logic [num_cache_p-1:0] dma_data_yumi_o
// axi write address channel
,output logic [axi_id_width_p-1:0] axi_awid_o
,output logic [axi_addr_width_p-1:0] axi_awaddr_o
,output logic [7:0] axi_awlen_o
,output logic [2:0] axi_awsize_o
,output logic [1:0] axi_awburst_o
,output logic [3:0] axi_awcache_o
,output logic [2:0] axi_awprot_o
,output logic axi_awlock_o
,output logic axi_awvalid_o
,input axi_awready_i
// axi write data channel
,output logic [axi_data_width_p-1:0] axi_wdata_o
,output logic [axi_strb_width_lp-1:0] axi_wstrb_o
,output logic axi_wlast_o
,output logic axi_wvalid_o
,input axi_wready_i
// axi write response channel
,input [axi_id_width_p-1:0] axi_bid_i
,input [1:0] axi_bresp_i
,input axi_bvalid_i
,output logic axi_bready_o
);
// tag fifo
//
logic tag_fifo_v_li;
logic tag_fifo_ready_lo;
logic tag_fifo_v_lo;
logic tag_fifo_yumi_li;
logic [lg_num_cache_lp-1:0] tag_lo;
bsg_fifo_1r1w_small #(
.width_p(lg_num_cache_lp)
,.els_p(tag_fifo_els_p)
) tag_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(tag_fifo_v_li)
,.ready_o(tag_fifo_ready_lo)
,.data_i(tag_i)
,.v_o(tag_fifo_v_lo)
,.data_o(tag_lo)
,.yumi_i(tag_fifo_yumi_li)
);
// suppress unused
//
wire [axi_id_width_p-1:0] unused_bid = axi_bid_i;
wire [1:0] unused_bresp = axi_bresp_i;
wire unused_bvalid = axi_bvalid_i;
// tag
//
// yumi when both tag_fifo and axi_aw are ready
assign yumi_o = v_i & axi_awready_i & tag_fifo_ready_lo;
// tag_fifo is valid when axi_aw is ready
assign tag_fifo_v_li = v_i & axi_awready_i;
// axi write address channel
//
assign axi_awid_o = {axi_id_width_p{1'b0}};
assign axi_awaddr_o = axi_addr_i;
assign axi_awlen_o = (8)'(axi_burst_len_p-1); // burst len
assign axi_awsize_o = (3)'(`BSG_SAFE_CLOG2(axi_data_width_p>>3));
assign axi_awburst_o = 2'b01; // incr
assign axi_awcache_o = 4'b0000; // non-bufferable
assign axi_awprot_o = 2'b00; // unprivileged
assign axi_awlock_o = 1'b0; // normal access
// axi_aw is valid when tag_fifo is ready
assign axi_awvalid_o = v_i & tag_fifo_ready_lo;
// axi write data channel
//
logic sipo_v_li;
logic sipo_ready_lo;
logic [data_width_p-1:0] sipo_data_li;
logic [$clog2(data_width_ratio_lp+1)-1:0] sipo_yumi_cnt_li;
logic [data_width_ratio_lp-1:0] sipo_v_lo;
logic [num_cache_p-1:0] cache_sel;
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux (
.i(tag_lo)
,.v_i(tag_fifo_v_lo)
,.o(cache_sel)
);
assign sipo_data_li = dma_data_i[tag_lo];
assign dma_data_yumi_o = cache_sel & dma_data_v_i & {num_cache_p{sipo_ready_lo}};
bsg_serial_in_parallel_out #(
.width_p(data_width_p)
,.els_p(data_width_ratio_lp)
) sipo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.valid_i(sipo_v_li)
,.data_i(sipo_data_li)
,.ready_o(sipo_ready_lo)
,.valid_o(sipo_v_lo)
,.data_o(axi_wdata_o)
,.yumi_cnt_i(sipo_yumi_cnt_li)
);
assign axi_wvalid_o = &sipo_v_lo;
assign sipo_v_li = tag_fifo_v_lo & dma_data_v_i[tag_lo];
assign sipo_yumi_cnt_li = axi_wvalid_o & axi_wready_i
? ($clog2(data_width_ratio_lp+1))'(data_width_ratio_lp)
: '0;
assign axi_wstrb_o = {axi_strb_width_lp{1'b1}};
// word counter
//
logic [`BSG_SAFE_CLOG2(block_size_in_words_p)-1:0] word_count_lo;
logic word_up_li;
logic word_clear_li;
bsg_counter_clear_up #(
.max_val_p(block_size_in_words_p-1)
,.init_val_p(0)
) word_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(word_clear_li)
,.up_i(word_up_li)
,.count_o(word_count_lo)
);
logic pop_word;
assign pop_word = dma_data_v_i[tag_lo] & dma_data_yumi_o[tag_lo] & tag_fifo_v_lo;
always_comb begin
if (word_count_lo == block_size_in_words_p-1) begin
word_clear_li = pop_word;
word_up_li = 1'b0;
tag_fifo_yumi_li = pop_word;
end
else begin
word_clear_li = 1'b0;
word_up_li = pop_word;
tag_fifo_yumi_li = 1'b0;
end
end
// burst counter
//
logic [`BSG_SAFE_CLOG2(axi_burst_len_p)-1:0] burst_count_lo;
logic burst_up_li;
logic burst_clear_li;
bsg_counter_clear_up #(
.max_val_p(axi_burst_len_p-1)
,.init_val_p(0)
) burst_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(burst_clear_li)
,.up_i(burst_up_li)
,.count_o(burst_count_lo)
);
always_comb begin
if (burst_count_lo == axi_burst_len_p-1) begin
burst_clear_li = axi_wvalid_o & axi_wready_i;
burst_up_li = 1'b0;
axi_wlast_o = axi_wvalid_o;
end
else begin
burst_clear_li = 1'b0;
burst_up_li = axi_wvalid_o & axi_wready_i;
axi_wlast_o = 1'b0;
end
end
// axi write response channel
//
assign axi_bready_o = 1'b1; // don't really care about the resp.
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_axi_tx)
|
//revision date: 2013/6/1
module udiv
#(parameter aw = 18,
parameter bw = 10)(
input [aw -1:0] a,
input [bw -1:0] b,
output [aw-1:0] quo,
output [bw-1:0] res,
output divide_by_0
);
assign divide_by_0 = b == 0 ? 1'b1:1'b0;
integer i;
reg frac;
reg [aw-1:0] quo_temp;
reg [bw:0] am [0:aw-1];
reg [bw:0] at [0:aw-1];
reg [bw:0] a_end;
wire signed [bw:0] sb;
assign sb = {1'b0,b};
always
begin
quo_temp[aw-1] = 0;
at[aw-2] = {{(bw-1){1'b0}},a[aw-1:aw-2]};
for(i=aw-3;i>=0;i=i-1)
begin
am[i+1] = at[i+1] - sb;
quo_temp[i+1] = ~am[i+1][bw];
if(quo_temp[i+1])
at[i] = {am[i+1][bw-1:0],a[i]};
else
at[i] = {at[i+1][bw-1:0],a[i]};
end
//lsb
am[0] = at[0] - sb;
quo_temp[0] = ~am[0][bw];
if (quo_temp[0])
a_end = am[0];
else
a_end = at[0];
end
assign quo = b == 0? {aw{1'b1}}:
b == 1? a:quo_temp;
assign res = b == 0? 0:
(b == 1? 0:a_end[bw-1:0]);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 110; int a[MAXN]; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } int main() { int n, i; while (scanf( %d , &n) == 1) { scanf( %d , &a[0]); int temp = a[0]; int mmax = a[0]; for (i = 1; i < n; i++) { scanf( %d , &a[i]); temp = gcd(temp, a[i]); mmax = max(a[i], mmax); } int ans = mmax / temp - n; if (ans & 1) printf( Alice n ); else printf( Bob n ); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NAND4_FUNCTIONAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4 (
VPWR,
VGND,
Y ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; void getZarr(const string &str, int Z[]) { int n = str.length(); int L, R, k; L = R = 0; for (int i = 1; i < n; ++i) { if (i > R) { L = R = i; while (R < n && str[R - L] == str[R]) R++; Z[i] = R - L; R--; } else { k = i - L; if (Z[k] < R - i + 1) Z[i] = Z[k]; else { L = i; while (R < n && str[R - L] == str[R]) R++; Z[i] = R - L; R--; } } } } void search(const string &text, const string &pattern, int Z[]) { string concat = pattern + text; int l = concat.length(); getZarr(concat, Z); for (int i = 0; i < (int)text.size(); ++i) Z[i] = Z[i + (int)pattern.size()]; } const int mod = 998244353; string a, l, r; int Z1[(int)2e6 + 5]; int Z2[(int)2e6 + 5]; long long cs[1000000 + 2]; int main() { ios::sync_with_stdio(0); cin.tie(0), cout.tie(0); cin >> a >> l >> r; search(a, l, Z1); search(a, r, Z2); cs[a.size()] = 1; for (int i = (int)a.size() - 1; i >= 0; --i) { const long long curr = [&](const int &i) { if (a[i] == 0 ) return l != 0 ? 0 : cs[i + 1] - cs[i + 2]; int lo = i + (int)l.size(); int hi = i + (int)r.size(); if (lo > (int)a.size()) return 0LL; if (Z1[i] < (int)l.size() && a[i + Z1[i]] < l[Z1[i]]) lo++; if (hi > (int)a.size()) hi = (int)a.size(); else { if (Z2[i] < (int)r.size()) { if (a[i + Z2[i]] > r[Z2[i]]) { hi--; } } } if (lo > hi) return 0LL; return cs[lo] - cs[hi + 1]; }(i); cs[i] = (curr + cs[i + 1]) % mod; } const long long ans = ((cs[0] - cs[1]) % mod + mod) % mod; cout << ans << n ; return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_fifo
*/
module test_axis_frame_fifo_64;
// Parameters
parameter DEPTH = 512;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire status_overflow;
wire status_bad_frame;
wire status_good_frame;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
status_overflow,
status_bad_frame,
status_good_frame
);
// dump file
$dumpfile("test_axis_frame_fifo_64.lxt");
$dumpvars(0, test_axis_frame_fifo_64);
end
axis_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O2,unroll-loops ) using namespace std; const int inf = 1000000010; const long long INF = 10000000000000010LL; const int mod = 1000000007; const int MAXN = 300010, LOG = 20; int n, m, k, u, v, x, y, t, a, b, ans; int par[MAXN], h[MAXN], leaf[MAXN]; vector<int> G[MAXN]; void dfs(int node) { h[node] = h[par[node]] + 1; leaf[node] = 1; for (int v : G[node]) if (!h[v]) { par[v] = node; dfs(v); leaf[node] = 0; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m >> k; while (m--) { cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } dfs(1); for (int v = 1; v <= n; v++) if (h[v] * k >= n) { cout << PATH << h[v] << n ; while (v) { cout << v << ; v = par[v]; } return 0; } cout << CYCLES n ; for (int v = 2; v <= n && k; v++) if (leaf[v]) { k--; int done = 0, x = 0, y = 0; for (int u : G[v]) if (u != par[v]) { if ((h[v] - h[u] + 1) % 3) { cout << h[v] - h[u] + 1 << n ; x = v; while (1) { cout << x << ; if (x == u) break; x = par[x]; } cout << n ; done = 1; break; } if (x) y = u; else x = u; } if (done) continue; assert(x && y); cerr << { << x << , << y << } = { << (x) << , << (y) << } << endl; if (h[x] < h[y]) swap(x, y); cout << h[x] - h[y] + 2 << n ; while (1) { cout << x << ; if (x == y) break; x = par[x]; } cout << v << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 10; int a[N], nx[N]; long long pr[N]; int main() { int n, q; scanf( %d %d , &n, &q); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), a[i + n] = a[i]; for (int i = 1; i <= n + n; i++) pr[i] = pr[i - 1] + a[i]; while (q--) { long long b; scanf( %lld , &b); int now = 1; int mx = n + n + 1, id; for (int i = 1; i <= n + n; i++) { while (now <= n + n && pr[i - 1] + b >= pr[now]) now++; nx[i] = now; if (nx[i] - i >= n) nx[i] = i + n; if (nx[i] <= n + n && mx > nx[i] - i) { mx = nx[i] - i; id = i; } } int ans = n + n; for (int i = id; i < nx[id]; i++) { int p = i; int res = 0; while (p < i + n) { res++; if (nx[p] > i + n && res > 1) { if (pr[i + n - 1] - pr[p - 1] + pr[nx[i] - 1] - pr[i - 1] <= b) res--; } p = nx[p]; } ans = min(ans, res); } printf( %d n , ans); } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
|
module DramWriter(
input fclk,
input rst_n,
//AXI port
output M2S_AXI_ACLK,
output reg [31:0] M2S_AXI_AWADDR,
input M2S_AXI_AWREADY,
output reg M2S_AXI_AWVALID,
output [63:0] M2S_AXI_WDATA,
output [7:0] M2S_AXI_WSTRB,
input M2S_AXI_WREADY,
output M2S_AXI_WVALID,
output M2S_AXI_WLAST,
input [1:0] M2S_AXI_BRESP,
input M2S_AXI_BVALID,
output M2S_AXI_BREADY,
output [3:0] M2S_AXI_AWLEN,
output [1:0] M2S_AXI_AWSIZE,
output [1:0] M2S_AXI_AWBURST,
//Control config
input wr_frame_valid,
output reg wr_frame_ready,
input [31:0] wr_FRAME_BYTES,
input [31:0] wr_BUF_ADDR,
output [1:0] debug_astate,
//RAM port
input din_burst_valid,
input [63:0] din,
output din_ready,
input din_valid
);
assign M2S_AXI_ACLK = fclk;
assign M2S_AXI_AWLEN = 4'b1111; // 16 transfers??
assign M2S_AXI_AWSIZE = 2'b11; // Represents 8 Bytes per "Transfer" (64 bit wide data bus)
assign M2S_AXI_AWBURST = 2'b01; // Represents Type "Incr"
assign M2S_AXI_WSTRB = 8'b11111111;
reg [31:0] BUF_ADDR;
reg [31:0] FRAME_BYTES;
`REG(fclk, BUF_ADDR, 0, wr_frame_valid && wr_frame_ready ? wr_BUF_ADDR : BUF_ADDR)
`REG(fclk, FRAME_BYTES, 0, wr_frame_valid && wr_frame_ready ? wr_FRAME_BYTES : FRAME_BYTES)
wire frame_done;
assign frame_done = (M2S_AXI_AWADDR + 128)==(BUF_ADDR+FRAME_BYTES);
localparam A_IDLE=0, A_FRAME_IDLE=1, A_FRAME_WAIT=2;
//ADDR logic
reg [1:0] a_state;
assign debug_astate = a_state;
always @(posedge fclk or negedge rst_n) begin
if (rst_n == 0) begin
a_state <= A_IDLE;
M2S_AXI_AWVALID <= 0;
M2S_AXI_AWADDR <= 0;
wr_frame_ready <= 0 ;
end
else begin
M2S_AXI_AWVALID <= 0;
wr_frame_ready <= 0 ;
case(a_state)
A_IDLE: begin
wr_frame_ready <= 1;
if (wr_frame_valid) begin
M2S_AXI_AWADDR <= wr_BUF_ADDR;
a_state <= A_FRAME_IDLE;
end
end
A_FRAME_IDLE: begin
if (din_burst_valid && M2S_AXI_AWREADY) begin
a_state <= A_FRAME_WAIT;
M2S_AXI_AWVALID <= 1 ;
end
end
A_FRAME_WAIT: begin
if (w_state == W_IDLE) begin
M2S_AXI_AWADDR <= M2S_AXI_AWADDR+128;
a_state <= frame_done ? A_IDLE : A_FRAME_IDLE ;
end
end
endcase
end
end
localparam W_IDLE=0, W_WAIT=1;
//WRITE logic
reg [3:0] b_count;
reg w_state;
always @(posedge fclk or negedge rst_n) begin
if (rst_n == 0) begin
w_state <= W_IDLE;
b_count <= 0;
end
else case(w_state)
W_IDLE: begin
if (a_state==A_FRAME_IDLE && din_burst_valid && M2S_AXI_AWREADY) begin
b_count <= 4'd15;
w_state <= W_WAIT;
end
end
W_WAIT: begin
if (M2S_AXI_WREADY && M2S_AXI_WVALID) begin
if(b_count == 4'h0) begin
w_state <= W_IDLE;
end
b_count <= b_count - 1'b1;
end
end
endcase
end
assign M2S_AXI_WLAST = (b_count == 4'h0);
assign M2S_AXI_WVALID = (w_state == W_WAIT) && din_valid;
assign din_ready = (w_state == W_WAIT) && M2S_AXI_WREADY;
assign M2S_AXI_BREADY = 1'b1;
assign M2S_AXI_WDATA = din;
endmodule : DramWriter
|
/* Tests unused logic removal to ensure no useful logic is removed from the circuit */
module bm_arithmetic_unused_bits(clk,
add_31_16_in0, add_31_16_in1, add_31_16_out,
add_15_0_in0, add_15_0_in1, add_15_0_out,
add_31_24_in0, add_31_24_in1, add_31_24_out,
add_7_0_in0, add_7_0_in1, add_7_0_out,
sub_31_16_in0, sub_31_16_in1, sub_31_16_out,
sub_15_0_in0, sub_15_0_in1, sub_15_0_out,
sub_31_24_in0, sub_31_24_in1, sub_31_24_out,
sub_7_0_in0, sub_7_0_in1, sub_7_0_out,
mult_31_16_in0, mult_31_16_in1, mult_31_16_out,
mult_15_0_in0, mult_15_0_in1, mult_15_0_out,
mult_31_24_in0, mult_31_24_in1, mult_31_24_out,
mult_7_0_in0, mult_7_0_in1, mult_7_0_out
);
input clk;
input [31:0] add_31_16_in0, add_31_16_in1;
output [15:0] add_31_16_out;
input [31:0] add_15_0_in0, add_15_0_in1;
output [15:0] add_15_0_out;
input [31:0] add_31_24_in0, add_31_24_in1;
output [7:0] add_31_24_out;
input [31:0] add_7_0_in0, add_7_0_in1;
output [7:0] add_7_0_out;
input [31:0] sub_31_16_in0, sub_31_16_in1;
output [15:0] sub_31_16_out;
input [31:0] sub_15_0_in0, sub_15_0_in1;
output [15:0] sub_15_0_out;
input [31:0] sub_31_24_in0, sub_31_24_in1;
output [7:0] sub_31_24_out;
input [31:0] sub_7_0_in0, sub_7_0_in1;
output [7:0] sub_7_0_out;
input [31:0] mult_31_16_in0, mult_31_16_in1;
output [15:0] mult_31_16_out;
input [31:0] mult_15_0_in0, mult_15_0_in1;
output [15:0] mult_15_0_out;
input [31:0] mult_31_24_in0, mult_31_24_in1;
output [7:0] mult_31_24_out;
input [31:0] mult_7_0_in0, mult_7_0_in1;
output [7:0] mult_7_0_out;
wire [31:0] add_31_16_temp;
wire [31:0] add_15_0_temp;
wire [31:0] add_31_24_temp;
wire [31:0] add_7_0_temp;
wire [31:0] sub_31_16_temp;
wire [31:0] sub_15_0_temp;
wire [31:0] sub_31_24_temp;
wire [31:0] sub_7_0_temp;
wire [31:0] mult_31_16_temp;
wire [31:0] mult_15_0_temp;
wire [31:0] mult_31_24_temp;
wire [31:0] mult_7_0_temp;
assign add_31_16_temp = add_31_16_in0 + add_31_16_in1;
always @(posedge clk) add_31_16_out <= add_31_16_temp[31:16];
assign add_15_0_temp = add_15_0_in0 + add_15_0_in1;
always @(posedge clk) add_15_0_out <= add_15_0_temp[15:0];
assign add_31_24_temp = add_31_24_in0 + add_31_24_in1;
always @(posedge clk) add_31_24_out <= add_31_24_temp[31:24];
assign add_7_0_temp = add_7_0_in0 + add_7_0_in1;
always @(posedge clk) add_7_0_out <= add_7_0_temp[7:0];
assign sub_31_16_temp = sub_31_16_in0 - sub_31_16_in1;
always @(posedge clk) sub_31_16_out <= sub_31_16_temp[31:16];
assign sub_15_0_temp = sub_15_0_in0 - sub_15_0_in1;
always @(posedge clk) sub_15_0_out <= sub_15_0_temp[15:0];
assign sub_31_24_temp = sub_31_24_in0 - sub_31_24_in1;
always @(posedge clk) sub_31_24_out <= sub_31_24_temp[31:24];
assign sub_7_0_temp = sub_7_0_in0 - sub_7_0_in1;
always @(posedge clk) sub_7_0_out <= sub_7_0_temp[7:0];
assign mult_31_16_temp = mult_31_16_in0 * mult_31_16_in1;
always @(posedge clk) mult_31_16_out <= mult_31_16_temp[31:16];
assign mult_15_0_temp = mult_15_0_in0 * mult_15_0_in1;
always @(posedge clk) mult_15_0_out <= mult_15_0_temp[15:0];
assign mult_31_24_temp = mult_31_24_in0 * mult_31_24_in1;
always @(posedge clk) mult_31_24_out <= mult_31_24_temp[31:24];
assign mult_7_0_temp = mult_7_0_in0 * mult_7_0_in1;
always @(posedge clk) mult_7_0_out <= mult_7_0_temp[7:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int ans = 0; vector<int> vx[200005]; bool vu[200005]; int n, k; int dfs(int v, int p) { int aa = 0, aa2 = 0; for (int i = 0; i < vx[v].size(); i++) { if (vx[v][i] == p) continue; int pr = dfs(vx[v][i], v); aa += pr; aa2 += min(pr, 2 * k - pr); } ans += aa2; if (vu[v]) aa++; return aa; } int main() { for (int i = 0; i < 200005; i++) vu[i] = 0; cin >> n >> k; int u, v; for (int i = 0; i < k; i++) { cin >> u >> v; vu[u] = vu[v] = 1; } for (int i = 1; i < n; i++) { cin >> u >> v; vx[u].push_back(v); vx[v].push_back(u); } dfs(1, -1); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const double eps = 1e-9; char mapp[110][110]; int main() { cin.sync_with_stdio(false); int n, m; int ans, cnt; int x1, x2, y1, y2; while (cin >> n >> m) { ans = 0; x1 = 0x3f3f3f3f, x2 = -1, y1 = 0x3f3f3f3f, y2 = -1; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> mapp[i][j]; if (mapp[i][j] == B ) { x1 = min(x1, i); y1 = min(y1, j); x2 = max(x2, i); y2 = max(y2, j); ans++; } } } if (x1 == 0x3f3f3f3f) { cout << 1 << endl; } else { cnt = max(x2 - x1, y2 - y1) + 1; if (cnt > n || cnt > m) { cout << -1 << endl; continue; } cout << cnt * cnt - ans << endl; } } return 0; }
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// test_simulation_shifter_left_16_test.v
module f1_test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT);
assign OUT = IN << SHIFT;
endmodule
// test_simulation_shifter_left_32_test.v
module f2_test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT);
assign OUT = IN << SHIFT;
endmodule
// test_simulation_shifter_left_4_test.v
module f3_test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT);
assign OUT = IN << SHIFT;
endmodule
// test_simulation_shifter_left_64_test.v
module f4_test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT);
assign OUT = IN << SHIFT;
endmodule
// test_simulation_shifter_left_8_test.v
module f5_test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT);
assign OUT = IN << SHIFT;
endmodule
// test_simulation_shifter_right_16_test.v
module f6_test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT);
assign OUT = IN >> SHIFT;
endmodule
// test_simulation_shifter_right_32_test.v
module f7_test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT);
assign OUT = IN >> SHIFT;
endmodule
// test_simulation_shifter_right_4_test.v
module f8_test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT);
assign OUT = IN >> SHIFT;
endmodule
// test_simulation_shifter_right_64_test.v
module f9_test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT);
assign OUT = IN >> SHIFT;
endmodule
// test_simulation_shifter_right_8_test.v
module f10_test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT);
assign OUT = IN >> SHIFT;
endmodule
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// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 255;
endmodule
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#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { while (a) b %= a, swap(a, b); return b; } char x[1000005], y[1000005]; int aux[1000005][26]; int main() { long long n, m; cin >> n >> m; scanf( %s %s , x, y); int lenx = strlen(x), leny = strlen(y); long long mdc = gcd(lenx, leny); long long mmc = lenx / mdc * leny; long long diff = mmc; for (int i = (0); i < (leny); ++i) ++aux[i % mdc][y[i] - a ]; for (int i = (0); i < (lenx); ++i) diff -= aux[i % mdc][x[i] - a ]; cout << diff * (n * lenx / mmc) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { double a, b, c; cin >> a >> b >> c; cout << (int)ceil(c * (a - b) / b); }
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#include <bits/stdc++.h> using namespace std; const int MAXN = -1; struct disk { long long L; double p; disk(long long L = 0, double p = 0.) : L(L), p(p) {} }; bool operator<(disk a, disk b) { return (a.L * a.p * (1 - b.p)) > (b.L * b.p * (1 - a.p)); } int n; vector<disk> P; int main() { while (cin >> n) { P.resize(n); for (int i = (0); i < (int)(n); i++) scanf( %lld %lf , &P[i].L, &P[i].p), P[i].p /= 100; sort(P.begin(), P.end()); double ans = 0., E = 0.; for (int i = ((int)n) - 1; i >= 0; i--) { disk D = P[i]; ans += D.L * (1 + E * D.p); E = D.p * E + (1 - D.p) * (E + 1); } printf( %.6f n , ans); } return 0; }
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#include <bits/stdc++.h> struct node { int* children; node() { children = new int[2]; children[0] = children[1] = -1; } int& operator[](int i) { return children[i]; } }; struct trie { std::vector<node> nodes; int root; trie() { nodes.push_back(node()); root = 0; } void insert(long long x) { int u = this->root; for (int i = 41; i >= 0; --i) { int v = ((x & (1LL << i)) ? 1 : 0); int next = nodes[u][v]; if (next == -1) { next = nodes[u][v] = nodes.size(); nodes.push_back(node()); } u = next; } } long long maximize(long long x) { int u = this->root; long long ans = 0; for (int i = 41; i >= 0; --i) { int cnt = 0, v; if (nodes[u][0] != -1) { cnt++; v = 0; } if (nodes[u][1] != -1) { cnt++; v = 1; } if (cnt == 0) return ans; else if (cnt == 1) { if (v) ans ^= (1LL << i); u = nodes[u][v]; } else { v = (x & (1LL << i) ? 1 : 0) ^ 1; if (v) ans ^= (1LL << i); u = nodes[u][v]; } } return ans; } }; int N; long long partial_xor[100001]; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); std::cout.tie(NULL); std::cin >> N; for (int i = 0; i < N; ++i) { std::cin >> partial_xor[i]; if (i) partial_xor[i] ^= partial_xor[i - 1]; } long long xor_sum = partial_xor[N - 1]; long long ans = xor_sum; trie t; for (int i = 0; i < N; ++i) { ans = std::max(ans, partial_xor[i]); if (i) { ans = std::max(ans, partial_xor[i - 1] ^ xor_sum); ans = std::max(ans, t.maximize(partial_xor[i - 1]) ^ partial_xor[i - 1]); } t.insert(partial_xor[i] ^ xor_sum); } std::cout << ans << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; namespace my_template { const long double PI = 3.14159265358979323846264338327950288419716939937510582097494L; template <typename T> pair<T, T> operator+(const pair<T, T> &a, const pair<T, T> &b) { return pair<T, T>(a.first + b.first, a.second + b.second); } template <typename T> pair<T, T> operator-(const pair<T, T> &a, const pair<T, T> &b) { return pair<T, T>(a.first - b.first, a.second - b.second); } template <typename T> T operator*(const pair<T, T> &a, const pair<T, T> &b) { return (a.first * b.first + a.second * b.second); } template <typename T> T operator^(const pair<T, T> &a, const pair<T, T> &b) { return (a.first * b.second - a.second * b.first); } template <typename T> void print(vector<T> vec, string name = ) { cout << name; for (auto u : vec) cout << u << ; cout << n ; } } // namespace my_template using namespace my_template; const int MOD = 1000000007; const long long INF = std::numeric_limits<long long>::max(); const int MX = 500101; int N; vector<pair<int, int>> sk; vector<int> color; struct node { int l, r; int did; int lazy; int dp, seg; node *left = nullptr; node *right = nullptr; node(int a, int b) : l(a), r(b), did(0), lazy(0), dp(0), seg(0) { if (l != r) { left = new node(l, (l + r) / 2); right = new node((l + r) / 2 + 1, r); } } inline void push() { if (!lazy) return; did += lazy; if (l != r) { left->lazy += lazy; right->lazy += lazy; } else { seg += lazy; assert(did == dp + seg); } lazy = 0; } void upd(int pos, int val) { push(); if (l == r) { dp = max(dp, val); did = dp + seg; return; } else if (pos <= (l + r) / 2) left->upd(pos, val); else right->upd(pos, val); left->push(); right->push(); did = max(left->did, right->did); } void add(int a, int b, int val) { push(); if (r < a or b < l) return; else if (a <= l and r <= b) { lazy += val; push(); return; } else { left->add(a, b, val); right->add(a, b, val); left->push(); right->push(); did = max(left->did, right->did); } } int get(int a, int b) { push(); if (r < a or b < l) return 0; else if (a <= l and r <= b) { return did; } else { return max(left->get(a, b), right->get(a, b)); } } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> N; { vector<pair<pair<int, int>, int>> temp(N); for (int i = 0; i < N; ++i) { cin >> temp[i].first.first >> temp[i].first.second >> temp[i].second; } sort(temp.begin(), temp.end(), [](const pair<pair<int, int>, int> &a, const pair<pair<int, int>, int> &b) { return a.first.second < b.first.second or (a.first.second == b.first.second and a.first.first > b.first.first); }); sk.resize(N); color.resize(N); for (int i = 0; i < N; ++i) { sk[i] = temp[i].first; color[i] = temp[i].second - 1; } } int big = 0; { map<int, int> rem; for (int i = 0; i < N; ++i) { rem[sk[i].first] = 1; rem[sk[i].second] = 1; } int piv = 1; for (auto &&u : rem) u.second = piv++; for (int i = 0; i < N; ++i) { sk[i].first = rem[sk[i].first]; sk[i].second = rem[sk[i].second]; big = max(big, sk[i].second); } } node *dp[2]; dp[0] = new node(0, big + 10); dp[1] = new node(0, big + 10); int ats = 0; for (int i = 0; i < N; ++i) { int c = color[i]; int first = sk[i].first; int second = sk[i].second; int curr = dp[1 - c]->get(0, first - 1) + 1; dp[1 - c]->add(0, first - 1, 1); dp[c]->upd(second, curr); ats = max(ats, curr); } printf( %d n , ats); }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBN_SYMBOL_V
`define SKY130_FD_SC_LP__SDFBBN_SYMBOL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBN_SYMBOL_V
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// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_asin(clock, resetn, enable, dataa, result);
input clock, resetn, enable;
input [31:0] dataa;
output [31:0] result;
fp_asin core(
.sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout(result[31]),
.exponentout(result[30:23]),
.mantissaout(result[22:0])
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:30 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_0_stub.v
// Design : zynq_design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0, FTMT_P2F_TRIGACK_0, FTMT_P2F_TRIG_0, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,FTMT_F2P_TRIG_0,FTMT_F2P_TRIGACK_0,FTMT_P2F_TRIGACK_0,FTMT_P2F_TRIG_0,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; using ii = pair<long long, long long>; using ll = long long; using ull = unsigned long long; using ld = long double; using vec = vector<long long>; using vecc = vector<vector<long long> >; namespace royyaha { template <typename T> void pr(const T& x) { cout << x; } template <typename T1, typename T2> void pr(const pair<T1, T2>& x) { cout << x.first << << x.second; } template <typename T, typename... Args> void pr(const T& x, const Args&... rest) { pr(x); pr(rest...); } template <typename T> void ou(const T& x) { pr(x); cout << endl; } template <typename T, typename... Args> void ou(const T& x, const Args&... rest) { pr(x, ); ou(rest...); } template <typename T> void ou(const vector<T>& v, long long n = 0) { n = (n ? n : v.size()); for (auto it = v.begin(); it != v.begin() + n; ++it) { if (it + 1 == v.end()) ou(*it); else pr(*it, ); } } } // namespace royyaha using namespace royyaha; bool intersection(ii a, ii b) { return !(a.first > b.second || a.second < b.first); } const long long maxn = 2e5 + 50; vec depth(maxn); vec son(maxn); vec e[maxn]; void dfs(long long u, long long pre) { depth[u] = depth[pre] + 1; son[u] = 1; for (auto v : e[u]) if (v != pre) { dfs(v, u); son[u] += son[v]; } } signed main() { long long n, k; cin >> n >> k; for (long long i = 0; i < n - 1; ++i) { long long u, v; cin >> u >> v; u--, v--; e[u].push_back(v); e[v].push_back(u); } dfs(0, 0); vec f(n); for (long long i = 0; i < n; ++i) f[i] = depth[i] - son[i]; sort(f.begin(), f.end()); reverse(f.begin(), f.end()); cout << accumulate(f.begin(), f.begin() + k, 0ll) << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = int(2e6) + 12, mod = int(1e9) + 7; int n, z[N]; char second[N]; int Z(string x) { int m = int(x.size()); string t = x; reverse((t).begin(), (t).end()); string second = x + # + t; int res = 0; for (int i = 1, l = 0, r = 0; i < second.size(); i++) { z[i] = 0; if (i <= r) z[i] = min(r - i + 1, z[i - l]); while (i + z[i] < second.size() && second[z[i]] == second[i + z[i]]) z[i]++; if (i + z[i] - 1 > r) l = i, r = i + z[i] - 1; if (i > m && i + z[i] == int(second.size())) { res = max(res, z[i]); } } return res; } void solve() { scanf( n%s , second + 1); n = strlen(second + 1); int l = 1, r = n; while (l <= r) { if (second[l] == second[r]) { l++; r--; } else break; } string a = ; for (int i = l; i <= r; i++) { a += second[i]; } string b = a; string ans = ; reverse((b).begin(), (b).end()); int z1 = Z(a); int z2 = Z(b); for (int i = 1; i < l; i++) ans += second[i]; if (z1 > z2) { for (int i = 0; i < z1; i++) ans += a[i]; } else { for (int i = 0; i < z2; i++) ans += b[i]; } for (int i = max(r + 1, l); i <= n; i++) ans += second[i]; for (int i = 0; i < ans.size(); i++) { putchar(ans[i]); } puts( ); } int main() { int T = 1; scanf( %d , &T); while (T--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long n; cin >> n; set<int> used; for (int i = 2; i * i <= n; i++) { if (n % i == 0 && !used.count(i)) { used.insert(i); n /= i; break; } } for (int i = 2; i * i <= n; i++) { if (n % i == 0 && !used.count(i)) { used.insert(i); n /= i; break; } } if (used.size() < 2 || used.count(n) || n == 1) { cout << NO << endl; } else { cout << YES << n ; used.insert(n); for (auto it : used) cout << it << ; cout << endl; } } }
|
/************************
* Willard Wider
* 6-5-17
* ELEC3725
* alu32.v
* building a 32 bit ALU
************************/
`timescale 1ns / 1ps//Unit time
//The top module of the entire project. The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over to the next circuit/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a previous circuit
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;//acts as an inversion for the xnor so it can be processed as xor
g = a & bint;//used for overflow, uses xor and a value from a. covers case of last bit being high
p = a ^ bint;//xor, for xor and xnor
cint = S[1] & c;//for add or sub, already processed by the lacs
//if it's supposed to be a 1, it will be a 1 if the command is add or subtract
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;//or
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);//nor
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;//and
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
// megafunction wizard: %LPM_COUNTER%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: rda_bitcounter.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2.16 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rda_bitcounter (
aclr,
clk_en,
clock,
cnt_en,
sset,
cout,
q);
input aclr;
input clk_en;
input clock;
input cnt_en;
input sset;
output cout;
output [4:0] q;
wire sub_wire0;
wire [4:0] sub_wire1;
wire cout = sub_wire0;
wire [4:0] q = sub_wire1[4:0];
lpm_counter LPM_COUNTER_component (
.aclr (aclr),
.clk_en (clk_en),
.clock (clock),
.cnt_en (cnt_en),
.sset (sset),
.cout (sub_wire0),
.q (sub_wire1),
.aload (1'b0),
.aset (1'b0),
.cin (1'b1),
.data ({5{1'b0}}),
.eq (),
.sclr (1'b0),
.sload (1'b0),
.updown (1'b1));
defparam
LPM_COUNTER_component.lpm_direction = "DOWN",
LPM_COUNTER_component.lpm_port_updown = "PORT_UNUSED",
LPM_COUNTER_component.lpm_svalue = "29",
LPM_COUNTER_component.lpm_type = "LPM_COUNTER",
LPM_COUNTER_component.lpm_width = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "1"
// Retrieval info: PRIVATE: Direction NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "1"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "5"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "DOWN"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_SVALUE STRING "29"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
// Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL "cout"
// Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL "q[4..0]"
// Retrieval info: USED_PORT: sset 0 0 0 0 INPUT NODEFVAL "sset"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
// Retrieval info: CONNECT: @sset 0 0 0 0 sset 0 0 0 0
// Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
// Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rda_bitcounter.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rda_bitcounter.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rda_bitcounter.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rda_bitcounter.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rda_bitcounter_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rda_bitcounter_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; using ll = long long; struct par { ll l; ll r; }; int n; ll s; par mas[200100]; bool cmp(par a, par b) { return (a.l < b.l); } bool good(ll m) { vector<par> grp1; vector<par> grp2; vector<par> grp3; for (int i = 0; i < n; i++) { if (mas[i].r < m) grp1.push_back(mas[i]); else if (m <= mas[i].l) grp2.push_back(mas[i]); else grp3.push_back(mas[i]); } int rem = max(0, (n + 1) / 2 - (int)grp2.size()); if (rem > grp3.size()) return false; ll sum = 0; for (auto el : grp1) sum += el.l; for (auto el : grp2) sum += el.l; if (grp3.size() > 0) sort(grp3.begin(), grp3.end(), cmp); for (int i = 1; i <= rem; i++) sum += m; for (int i = 0; i < grp3.size() - rem; i++) sum += grp3[i].l; return (sum <= s); } ll bin_s() { ll l = 1, r = 1e9; ll m; while (l < r) { m = (l + r + 1) / 2; if (good(m)) l = m; else r = m - 1; } return l; } void solve() { cin >> n >> s; for (int i = 0; i < n; i++) { cin >> mas[i].l >> mas[i].r; } ll med = bin_s(); cout << med << n ; return; } int main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); int t; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k = 0; string ans = ; cin >> n; while (n > 1) { ans += 8 ; k += 1; n -= 2; } if (n == 1) { ans += 9 ; k++; n--; } if (k < 19) cout << ans; else cout << -1; return 0; }
|
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* "is_last" == 0 means byte number is 8, no matter what value "byte_num" is. */
/* if "in_ready" == 0, then "is_last" should be 0. */
/* the user switch to next "in" only if "ack" == 1. */
module padder(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready, f_ack);
input clk, reset;
input [63:0] in;
input in_ready, is_last;
input [2:0] byte_num;
output buffer_full; /* to "user" module */
output reg [575:0] out; /* to "f_permutation" module */
output out_ready; /* to "f_permutation" module */
input f_ack; /* from "f_permutation" module */
reg state; /* state == 0: user will send more input data
* state == 1: user will not send any data */
reg done; /* == 1: out_ready should be 0 */
reg [8:0] i; /* length of "out" buffer */
wire [63:0] v0; /* output of module "padder1" */
reg [63:0] v1; /* to be shifted into register "out" */
wire accept, /* accept user input? */
update;
assign buffer_full = i[8];
assign out_ready = buffer_full;
assign accept = (~ state) & in_ready & (~ buffer_full); // if state == 1, do not eat input
assign update = (accept | (state & (~ buffer_full))) & (~ done); // don't fill buffer if done
always @ (posedge clk)
if (reset)
out <= 0;
else if (update)
out <= {out[575-64:0], v1};
always @ (posedge clk)
if (reset)
i <= 0;
else if (f_ack | update)
i <= {i[7:0], 1'b1} & {9{~ f_ack}};
/* if (f_ack) i <= 0; */
/* if (update) i <= {i[7:0], 1'b1}; // increase length */
always @ (posedge clk)
if (reset)
state <= 0;
else if (is_last)
state <= 1;
always @ (posedge clk)
if (reset)
done <= 0;
else if (state & out_ready)
done <= 1;
padder1 p0 (in, byte_num, v0);
always @ (*)
begin
if (state)
begin
v1 = 0;
v1[7] = v1[7] | i[7]; /* "v1[7]" is the MSB of its last byte */
end
else if (is_last == 0)
v1 = in;
else
begin
v1 = v0;
v1[7] = v1[7] | i[7];
end
end
endmodule
|
//************************************
// Designed by: Wenyi Xu
// Last updated: 15/10/21
//************************************
module word_com(clk, rst, data_in, letter_in);
parameter letter_size = 8;
parameter word_length = 128; // 128-bit 128/8 = 16 letters in one word
parameter word_num = 63; // This value affects the row_pt
// FSM parameters
parameter START = 4'b0000;
parameter IDLE = 4'b0001;
parameter COMBINE = 4'b0010;
input clk;
input rst;
input data_in; // When data_in==1 COMBINE, when data_in==0 IDLE
input [letter_size-1:0] letter_in; // The incoming letters
// output reg out_en; // Tell te key_comp that word_com is sending data out
// output reg [31:0] data_out; // Output 32-bit data to key_comp
reg [word_length-1:0] mem_word [word_num-1:0]; // The internal mem to store the combined words
reg [5:0] row_pt; // Needs to point from 0 to 63
reg [7:0] col_pt; // Needs to point from 0 to 127 and some margin
reg [6:0] i; // Index the mem_word
reg [3:0] current_state;
reg [3:0] next_state;
// reg data_in_reg;
// always@(posedge clk or negedge rst)
// if(!rst)
// data_in_reg <= 0;
// else
// data_in_reg <= data_in;
always@(posedge clk or negedge rst)
if(!rst)
current_state <= START;
else
current_state <= next_state;
always@*
begin
case(current_state)
START: begin
if(data_in == 1) next_state = COMBINE;
else next_state = START;
end
IDLE: begin
if(data_in == 1) next_state = COMBINE;
else next_state = IDLE;
end
COMBINE: begin
if(data_in == 0) next_state = IDLE;
else next_state = COMBINE;
end
default: begin
next_state = START;
end
endcase
end
always@(posedge clk)
case(current_state)
START: begin
row_pt <= 0;
col_pt <= 0;
//mem_word[0] = 128'b0;
for(i=0; i<=63; i=i+1)
mem_word[i] <= 128'b0;
end
IDLE: begin
end
COMBINE: begin
if( (letter_in==8'h00)&&(col_pt==0)) begin
row_pt <= row_pt;
end
else if ( (letter_in==8'h00)&&(col_pt!=0) ) begin
// Start from a new row, combine a new word.
row_pt <= row_pt + 1;
col_pt <= 0;
end
else if (col_pt == 128) begin
row_pt <= row_pt + 1;
col_pt <= 0;
end
else if(data_in == 1) begin
mem_word[row_pt] <= mem_word[row_pt] + (letter_in<<col_pt);
col_pt <= col_pt + 8;
end
else begin
end
end
default: begin
end
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T max(T a, T b, T c) { return max(a, max(b, c)); } int nextInt() { int x = 0, p = 1; char c; do { c = getchar(); } while (c <= 32); if (c == - ) { p = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * p; } const int max_len = 100500, max_alpha = 26; int t[max_len][max_alpha]; int szT; int newT() { return ++szT; } int n, k, root; char s[max_len]; bool win[max_len], lose[max_len]; void addTrie(char* s) { int len = strlen(s); int v = root; for (int i = 0; i < len; i++) { int c = s[i] - a ; if (t[v][c] == 0) t[v][c] = newT(); v = t[v][c]; } } void dfs(int v) { win[v] = false; lose[v] = false; bool isLeaf = true; for (int i = 0; i < max_alpha; i++) { if (t[v][i] != 0) { isLeaf = false; int to = t[v][i]; dfs(to); win[v] |= !win[to]; lose[v] |= !lose[to]; } } if (isLeaf) { lose[v] = true; } } void answer(bool res) { puts(res ? First : Second ); exit(0); } int main() { n = nextInt(); k = nextInt(); root = newT(); for (int i = 1; i <= n; i++) { scanf( %s , s); addTrie(s); } dfs(root); if (k == 1) answer(win[root]); else if (!win[root]) answer(win[root]); else if (lose[root]) answer(win[root]); else if (k % 2 == 1) answer(win[root]); else answer(!win[root]); }
|
#include <bits/stdc++.h> #define int long long #pragma GCC target ( avx2 ) #pragma GCC optimization ( O3 ) #pragma GCC optimization ( unroll-loops ) /*#include <ext/pb_ds/assoc_container.hpp> #include <ext/pb_ds/tree_policy.hpp> using namespace __gnu_pbds; #define ordered_set tree<int, null_type,less<int>, rb_tree_tag,tree_order_statistics_node_update>*/ using namespace std; signed main() { //ios_base::sync_with_stdio(0); //cin.tie(0); //cout.tie(0); int n; cin >> n; int a[n]; for (int i = 0; i < n; ++i) cin >> a[i]; vector <pair <int, pair <int, int> > > goga; for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { if (a[i] > a[j]) goga.push_back({a[i] - a[j], {i, j}}); else goga.push_back({a[j] - a[i], {j, i}}); } } sort(goga.begin(), goga.end()); reverse(goga.begin(), goga.end()); for (int i = 0; i < goga.size(); ++i) { if (goga[i].first >= 0 && i < goga.size()) { int first = goga[i].second.first, second = goga[i].second.second; cout << ? << first + 1 << << second + 1 << endl; string lol; cin >> lol; if (lol == Yes ) { cout << ! << first + 1 << << second + 1 << endl; return 0; } } } cout << ! << 0 << << 0 << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 5e10 + 5; int main() { bool flag = 0; int n, ans = 0, k; cin >> n; int arr[n + 5]; for (int i = 0; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n); k = n / 2; for (int i = 0; i < n / 2; i++) { for (int j = k; j < n; j++) { if (arr[i] * 2 <= arr[j]) { ans++; k = j + 1; break; } if (j == n - 1) { flag = 1; } } if (flag) break; } cout << n - ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 9; int n, vl, ans, tmp[110000], ret[110000]; void redo(vector<int>& a) { int i, j, s, p, q, nn = 0; for (i = 0; i < a.size(); i++) { if (nn == 0 || a[nn - 1] < a[i]) a[nn++] = a[i]; } a.resize(nn); } void dfs(int id, vector<int>& a, int now) { int i, j, s, p, q; if (ans <= now) return; for (i = 0; i < a.size(); i++) { if (a[i] != 0) break; } if (i >= a.size()) { ans = now; for (i = 0; i < now; i++) ret[i] = tmp[i]; return; } if (id >= 18) return; bool you = false; for (i = 0; i < a.size(); i++) { if (abs(a[i]) & (1 << id)) { you = true; break; } } if (!you) dfs(id + 1, a, now); else { vector<int> na; na.resize(a.size()); tmp[now] = (1 << id); for (i = 0; i < a.size(); i++) { if (abs(a[i]) & (1 << id)) na[i] = a[i] - (1 << id); else na[i] = a[i]; } sort(na.begin(), na.end()); redo(na); dfs(id + 1, na, now + 1); tmp[now] = -(1 << id); na.resize(a.size()); for (i = 0; i < a.size(); i++) { if (abs(a[i]) & (1 << id)) na[i] = a[i] + (1 << id); else na[i] = a[i]; } sort(na.begin(), na.end()); redo(na); dfs(id + 1, na, now + 1); } } int main() { vector<int> a; a.clear(); scanf( %d , &n); int i, j, s, p, q; for (i = 0; i < n; i++) { scanf( %d , &vl); a.push_back(vl); } sort(a.begin(), a.end()); redo(a); ans = inf; dfs(0, a, 0); printf( %d n , ans); for (i = 0; i < ans; i++) printf( %d , ret[i]); printf( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; long long read() { long long w = 0, f = 1; char c = ; while (c < 0 || c > 9 ) c = getchar(), f = c == - ? -1 : f; while (c >= 0 && c <= 9 ) w = w * 10 + c - 48, c = getchar(); return w * f; } long long read14() { char c = getchar(); while (c != U && c != D && c != L && c != R ) c = getchar(); if (c == U ) return 1; if (c == D ) return 2; if (c == L ) return 3; return 4; } long long n, m, p[200005], dl[200005], dr[200005]; vector<long long> a[200005], e[200005]; long long pos(long long x, long long y) { if (x >= 1 && x <= n && y >= 1 && y <= m) return (x - 1) * m + y; return n * m + 1 + ((x + y) & 1); } long long minn[200005 << 2], tag[200005 << 2], val[200005 << 2]; void build(long long p, long long l, long long r) { if (l == r) { val[p] = 1; return; } long long mid = (l + r) >> 1; build(p << 1, l, mid); build(p << 1 | 1, mid + 1, r); val[p] = val[p << 1] + val[p << 1 | 1]; } void down(long long p, long long l, long long r) { if (!tag[p]) return; minn[p << 1] += tag[p]; minn[p << 1 | 1] += tag[p]; tag[p << 1] += tag[p]; tag[p << 1 | 1] += tag[p]; tag[p] = 0; } void update(long long p, long long x, long long y, long long v, long long l, long long r) { if (x <= l && y >= r) { minn[p] += v, tag[p] += v; return; } down(p, l, r); long long mid = (l + r) >> 1; if (x <= mid) update(p << 1, x, y, v, l, mid); if (y > mid) update(p << 1 | 1, x, y, v, mid + 1, r); if (minn[p << 1] == minn[p << 1 | 1]) val[p] = val[p << 1] + val[p << 1 | 1]; else if (minn[p << 1] < minn[p << 1 | 1]) val[p] = val[p << 1]; else val[p] = val[p << 1 | 1]; minn[p] = min(minn[p << 1], minn[p << 1 | 1]); } long long now, ans; void dfs1(long long u) { dl[u] = ++now; for (auto v : e[u]) dfs1(v); dr[u] = now; } void dfs2(long long u, long long rt) { if (u != rt) update(1, dl[p[u]], dr[p[u]], 1, 1, now), ans -= val[1] - 1; for (auto v : e[u]) dfs2(v, rt); if (u != rt) update(1, dl[p[u]], dr[p[u]], -1, 1, now); } signed main() { n = read(), m = read(), ans = n * n * m * m / 4; for (long long i = 1; i <= n; i++) { a[i].push_back(0); for (long long j = 1; j <= m; j++) { a[i].push_back(read14()); if (a[i][j] == 1) e[pos(i + 2, j)].push_back(pos(i, j)), p[pos(i, j)] = pos(i + 1, j); if (a[i][j] == 2) e[pos(i - 2, j)].push_back(pos(i, j)), p[pos(i, j)] = pos(i - 1, j); if (a[i][j] == 3) e[pos(i, j + 2)].push_back(pos(i, j)), p[pos(i, j)] = pos(i, j + 1); if (a[i][j] == 4) e[pos(i, j - 2)].push_back(pos(i, j)), p[pos(i, j)] = pos(i, j - 1); } } dfs1(n * m + 1); build(1, 1, now); dfs2(n * m + 2, n * m + 2); printf( %lld , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int i = 0; ios_base::sync_with_stdio(false); cin.tie(NULL); vector<int> ans; int n; int m; cin >> n >> m; int a[110]; int b[20]; memset(a, 0, sizeof a); memset(b, 0, sizeof b); for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < m; i++) { int t; cin >> t; b[t] = 1; } for (int i = 0; i < n; i++) { if (b[a[i]] == 1) ans.push_back(a[i]); } for (int i = 0; i < ans.size(); i++) { cout << ans[i] << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, ans; bool pr[100003]; bool mark[100003]; vector<int> v; vector<int> e; vector<pair<int, int> > res; int main() { scanf( %d , &n); for (int i = 2; i <= n; i++) if (!pr[i]) { v.push_back(i); for (int j = 2 * i; j <= n; j += i) pr[j] = true; } int sz = v.size(); for (int i = 1; i < sz && v[i] <= n / 2; i++) { vector<int> tmp; for (int j = v[i]; j <= n; j += v[i]) if (!mark[j]) tmp.push_back(j); int cnt = tmp.size(); if (cnt % 2 == 0) { for (int j = 0; j < cnt; j += 2) { res.push_back(pair<int, int>(tmp[j], tmp[j + 1])); mark[tmp[j]] = mark[tmp[j + 1]] = true; } } else if (cnt >= 3) { res.push_back(pair<int, int>(tmp[0], tmp[2])); mark[tmp[0]] = mark[tmp[2]] = true; for (int j = 3; j < cnt; j += 2) { res.push_back(pair<int, int>(tmp[j], tmp[j + 1])); mark[tmp[j]] = mark[tmp[j + 1]] = true; } } } for (int i = 2; i <= n; i += 2) if (!mark[i]) e.push_back(i); int cnt = e.size(); for (int i = 0; i + 1 < cnt; i += 2) res.push_back(pair<int, int>(e[i], e[i + 1])); ans = res.size(); printf( %d n , ans); for (int i = 0; i < ans; i++) printf( %d %d n , res[i].first, res[i].second); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 5, inf = 1e9 + 7; long long n, k; string s, t; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); long long i, j, a, b, ans = 0; cin >> n >> k >> s >> t; ans = n; i = 0; while (i < n && s[i] == t[i]) i++; long long t1 = 0, t2 = 0, a1 = 1, a2 = 1; k--; if (i < n && k) { ans += n - i; k--; i++; } for (; i < n; i++) { if (s[i] == a ) { ans += min(k, t1 + 1) * (n - i); k -= min(k, t1 + 1); t1 = t1 * 2 + 1; } else { ans += min(k, t1) * (n - i); k -= min(k, t1); t1 *= 2; } if (t[i] == a ) { ans += min(k, t2) * (n - i); k -= min(k, t2); t2 *= 2; } else { ans += min(k, t2 + 1) * (n - i); k -= min(k, t2 + 1); t2 = t2 * 2 + 1; } if (!k) break; } cout << ans; }
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#include <bits/stdc++.h> using namespace std; long long a[100005]; long long d[800][800], g[800][800]; int w[100]; vector<long long> v; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); long long x = a[i]; int cnt = 0; while (x) { if (x % 2) w[cnt]++; cnt++; x /= 2; } } for (int i = 0; i < 70; i++) { if (w[i] >= 3) { printf( 3 n ); return 0; } } v.push_back(0); for (int i = 1; i <= n; i++) { if (a[i]) v.push_back(a[i]); } n = v.size() - 1; if (n > 300) { printf( 3 n ); return 0; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) d[i][j] = g[i][j] = 0x3f3f3f3f; } for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { if (v[i] & v[j]) d[i][j] = 1, d[j][i] = 1, g[i][j] = 1, g[j][i] = 1; } } long long ans = 0x3f3f3f3f; for (int k = 1; k <= n; k++) { for (int i = 1; i < k; i++) { for (int j = i + 1; j < k; j++) ans = min(ans, d[i][j] + g[i][k] + g[k][j]); } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) d[i][j] = min(d[i][j], d[i][k] + d[k][j]); } } if (ans == 0x3f3f3f3f) ans = -1; printf( %lld n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O22AI_BEHAVIORAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int n; int a[6], b[6], ord[6], c[6]; vector<pair<int, int> > v, nv; struct S { vector<pair<int, int> > v; int from; S(vector<pair<int, int> > v, int from) : v(v), from(from) {} S() {} }; vector<S> s; void pr(int a, int b) { if (a == 1) { printf( inc %d n , ord[b] + 1); } else { printf( dec %d n , ord[b] + 1); } } S hor, ver, res; bool invI, invJ; void _incI() { assert(ver.from < (int)ver.v.size()); res.v.push_back(ver.v[ver.from++]); } void _decI() { assert(ver.from > 0); pair<int, int> p = ver.v[--ver.from]; p.first = -p.first; res.v.push_back(p); } void _incJ() { assert(hor.from < (int)hor.v.size()); res.v.push_back(hor.v[hor.from++]); } void _decJ() { assert(hor.from > 0); pair<int, int> p = hor.v[--hor.from]; p.first = -p.first; res.v.push_back(p); } void decI() { if (invI) _incI(); else _decI(); } void incI() { if (invI) _decI(); else _incI(); } void decJ() { if (invJ) _incJ(); else _decJ(); } void incJ() { if (invJ) _decJ(); else _incJ(); } S merge() { res.v.clear(); res.from = 0; int i = ver.from; int j = hor.from; int n = (int)ver.v.size() + 1; int m = (int)hor.v.size() + 1; assert(i % 2 == j % 2); invI = invJ = false; if (i % 2 == 1) { for (int jj = j; jj >= 0; --jj) { if (jj & 1) { for (int _ = 0; _ < (int)(i); ++_) decI(); } else { for (int _ = 0; _ < (int)(i); ++_) incI(); } if (jj != 0) decJ(); else incI(); } for (int ii = i + 1; ii < n; ++ii) { if (ii & 1) { for (int _ = 0; _ < (int)(j); ++_) decJ(); } else { for (int _ = 0; _ < (int)(j); ++_) incJ(); } if (ii != n - 1) incI(); else incJ(); } for (int jj = j + 1; jj < m; ++jj) { if (jj & 1) { for (int _ = 0; _ < (int)(n - 1); ++_) incI(); } else { for (int _ = 0; _ < (int)(n - 1); ++_) decI(); } if (jj != m - 1) incJ(); } } else { if (i == n - 1) { i = 0; invI = true; } if (j == 0) { j = m - 1; invJ = true; } for (int _ = 0; _ < (int)(i); ++_) decI(); decJ(); for (int ii = 0; ii < (int)(i + 1); ++ii) { if (ii & 1) { for (int _ = 0; _ < (int)(j - 1); ++_) incJ(); } else { for (int _ = 0; _ < (int)(j - 1); ++_) decJ(); } incI(); } for (int jj = 0; jj < (int)(j + 1); ++jj) { if (jj & 1) { for (int _ = 0; _ < (int)(n - i - 2); ++_) decI(); } else { for (int _ = 0; _ < (int)(n - i - 2); ++_) incI(); } if (jj != j) incJ(); } if (j != m - 1) { incJ(); for (int jj = j + 1; jj < m; ++jj) { if (jj & 1) { for (int _ = 0; _ < (int)(n - 1); ++_) decI(); } else { for (int _ = 0; _ < (int)(n - 1); ++_) incI(); } if (jj != m - 1) incJ(); } } } return res; } int main() { cin >> n; for (int i = 0; i < (int)(n); ++i) cin >> a[i]; for (int i = 0; i < (int)(n); ++i) cin >> b[i]; if (n == 1) { if (a[0] == 2) { cout << Cycle << endl; if (b[0] == 1) { cout << inc 1 << endl; cout << dec 1 << endl; } else { cout << dec 1 << endl; cout << inc 1 << endl; } } else { if (b[0] == 1) { cout << Path << endl; for (int i = 0; i < (int)(a[0] - 1); ++i) { cout << inc 1 n ; } } else if (b[0] == a[0]) { cout << Path << endl; for (int i = 0; i < (int)(a[0] - 1); ++i) { cout << dec 1 n ; } } else { cout << No << endl; } } return 0; } for (int i = 0; i < (int)(n); ++i) ord[i] = i; for (int i = 0; i < (int)(n - 1); ++i) if (a[i] % 2 == 0) { swap(a[i], a[n - 1]); swap(b[i], b[n - 1]); swap(ord[i], ord[n - 1]); break; } if (a[n - 1] % 2 == 0) { for (int i = 0; i < (int)(n - 1); ++i) { nv.clear(); for (int j = 0; j < (int)(a[i]); ++j) { if (j & 1) { reverse(v.begin(), v.end()); for (pair<int, int> p : v) { nv.push_back(make_pair(-p.first, p.second)); } reverse(v.begin(), v.end()); } else { for (pair<int, int> p : v) { nv.push_back(p); } } if (j != a[i] - 1) { nv.push_back(make_pair(1, i)); } } v = nv; } nv.clear(); for (pair<int, int> p : v) { nv.push_back(p); } for (int i = 0; i < (int)(a[n - 1] - 1); ++i) { nv.push_back(make_pair(1, n - 1)); if (i & 1) { for (int j = 1; j < (int)v.size(); ++j) { nv.push_back(v[j]); } } else { for (int j = (int)v.size() - 1; j >= 1; --j) { nv.push_back(make_pair(-v[j].first, v[j].second)); } } } nv.push_back(make_pair(-v[0].first, v[0].second)); for (int i = 0; i < (int)(a[n - 1] - 1); ++i) { nv.push_back(make_pair(-1, n - 1)); } for (int i = 0; i < (int)(n); ++i) c[i] = 1; v = nv; int ind = 0; while (true) { bool ok = true; for (int j = 0; j < (int)(n); ++j) if (c[j] != b[j]) { ok = false; break; } if (ok) break; c[v[ind].second] += v[ind].first; ++ind; } printf( Cycle n ); for (int i = ind; i < (int)v.size(); ++i) { pr(v[i].first, v[i].second); } for (int i = 0; i < ind; ++i) { pr(v[i].first, v[i].second); } return 0; } int sum = 0; for (int i = 0; i < (int)(n); ++i) sum += b[i] - 1; if (sum % 2 == 1) { cout << No << endl; return 0; } cout << Path << endl; for (int i = 0; i < (int)(n); ++i) { vector<pair<int, int> > cur; for (int j = 0; j < (int)(a[i] - 1); ++j) { cur.push_back(make_pair(1, i)); } s.push_back(S(cur, b[i] - 1)); } while ((int)s.size() > 1) { bool done = false; for (int i = 0; i < (int)(s.size()); ++i) { for (int j = 0; j < (int)(i); ++j) { if ((s[i].from + s[j].from) % 2 == 0) { hor = s[i]; ver = s[j]; s[i] = merge(); swap(s[j], s.back()); s.pop_back(); done = true; break; } } if (done) { break; } } assert(done); } for (pair<int, int> p : s[0].v) { pr(p.first, p.second); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21A_1_V
`define SKY130_FD_SC_LS__O21A_1_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21a_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21a_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21A_1_V
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC TAG RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of data cache tag rams. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_tag.v,v $
// Revision 1.1 2008/05/07 22:43:21 daughtry
// Initial Demo RTL check-in
//
// Revision 1.5 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.4 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_dc_tag(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, tag_v, tag
);
parameter dw = `OR1200_DCTAG_W;
parameter aw = `OR1200_DCTAG;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input we;
input [dw-1:0] datain;
output tag_v;
output [dw-2:0] tag;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
`ifdef OR1200_NO_DC
//
// Data cache not implemented
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of TAG RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_256x21 dc_tag0(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_512x20 dc_tag0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq({tag, tag_v})
);
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__EINVN_BEHAVIORAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 260, mo = 777777777; int f[30][N][N], c[N * 2][N * 2], n, k, ans; int power(int x, int y) { int s = 1; for (; y; y /= 2, x = 1ll * x * x % mo) if (y & 1) s = 1ll * s * x % mo; return s; } int main() { scanf( %d%d , &n, &k); k = n - k; for (int i = 0; i <= n; i++) c[i][0] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= i; j++) c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % mo; f[0][0][0] = 1; for (int i = n; i >= 1; i--) for (int v = min(22, n / i); v >= 0; v--) for (int v1 = k; v1 >= 0; v1--) for (int v2 = n - k; v2 >= 0; v2--) { int tmp = 1ll * f[v][v1][v2] * c[v1 + v2 + i][i] % mo; if (v1 + i <= k) (((f[v + 1][v1 + i][v2]) += (tmp)) >= mo ? f[v + 1][v1 + i][v2] -= mo : 233); ; if (v2 + i <= n - k) (((f[v + 1][v1][v2 + i]) += (mo - tmp)) >= mo ? f[v + 1][v1][v2 + i] -= mo : 233); ; } for (int v = 0; v <= min(n, 23); v++) for (int v2 = 0; v2 <= n - k; v2++) (((ans) += (1ll * f[v][k][v2] * c[n][k + v2] % mo * power(n - v, n - k - v2) % mo)) >= mo ? ans -= mo : 233); ; printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; template <class T> string toStr(const T &x) { stringstream s; s << x; return s.str(); } template <class T> int toInt(const T &x) { stringstream s; s << x; int r; s >> r; return r; } vector<string> pals; bool check(string s) { for (int i = 0, j = s.size() - 1; i < s.size() / 2; i++, j--) { if (s[i] != s[j]) return false; } return true; } void gen() { for (int i = 0; i < 24; ++i) { for (int j = 0; j < 60; ++j) { string t1 = i < 10 ? 0 : ; string t2 = j < 10 ? 0 : ; string t = t1 + toStr(i) + : + t2 + toStr(j); if (check(t)) pals.push_back(t); } } } int main() { gen(); string line; cin >> line; if (line > 23:32 ) cout << 00:00 << endl; else { vector<string>::iterator it = upper_bound(pals.begin(), pals.end(), line); cout << pals[(it - pals.begin())] << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BOI_SYMBOL_V
`define SKY130_FD_SC_MS__A21BOI_SYMBOL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21boi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BOI_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__SDFRTP_FUNCTIONAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_FUNCTIONAL_PP_V
|
`include "v2k_typedef_yee_inc.v"
module v2k_typedef_yee
(/*AUTOARG*/
// Outputs
sub2_out_pixel, ready, sub1_to_sub2_and_top,
// Inputs
sub1_in_pixel, reset, pixel_ff, cp
);
//-----------------------
// Output definitions
//
output logic_t sub1_to_sub2_and_top; // Explicit output port
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output logic_t ready; // From itest_sub2 of v2k_typedef_yee_sub2.v
output pixel24_t sub2_out_pixel; // From itest_sub2 of v2k_typedef_yee_sub2.v
// End of automatics
//-----------------------
// Input definitions
//
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input logic_t cp; // To itest_sub1 of v2k_typedef_yee_sub1.v, ...
input logic_t pixel24_t pixel_ff; // To itest_sub2 of v2k_typedef_yee_sub2.v
input logic_t reset; // To itest_sub1 of v2k_typedef_yee_sub1.v, ...
input pixel24_t sub1_in_pixel; // To itest_sub1 of v2k_typedef_yee_sub1.v
// End of automatics
//-----------------------
// Wire definitions
//
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
pixel24_t sub1_out_pixel; // From itest_sub1 of v2k_typedef_yee_sub1.v
logic_t sub1_to_sub2; // From itest_sub1 of v2k_typedef_yee_sub1.v
// End of automatics
//-----------------------
// Module instantiations
//
v2k_typedef_yee_sub1 itest_sub1
(/*AUTOINST*/
// Outputs
.sub1_out_pixel (sub1_out_pixel),
.sub1_to_sub2 (sub1_to_sub2),
.sub1_to_sub2_and_top (sub1_to_sub2_and_top),
// Inputs
.sub1_in_pixel (sub1_in_pixel),
.cp (cp),
.reset (reset));
/*v2k_typedef_yee_sub2 AUTO_TEMPLATE (
.sub2_in_pixel (sub1_out_pixel),
)
*/
v2k_typedef_yee_sub2 itest_sub2
(/*AUTOINST*/
// Outputs
.sub2_out_pixel (sub2_out_pixel),
.ready (ready),
// Inputs
.sub2_in_pixel (sub1_out_pixel), // Templated
.cp (cp),
.reset (reset),
.sub1_to_sub2 (sub1_to_sub2),
.sub1_to_sub2_and_top (sub1_to_sub2_and_top),
.pixel_ff (pixel_ff));
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 19574 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w128,
w129,
w2048,
w2047,
w8256,
w10303,
w516,
w9787,
w19574;
assign w1 = i_data0;
assign w10303 = w2047 + w8256;
assign w128 = w1 << 7;
assign w129 = w1 + w128;
assign w19574 = w9787 << 1;
assign w2047 = w2048 - w1;
assign w2048 = w1 << 11;
assign w516 = w129 << 2;
assign w8256 = w129 << 6;
assign w9787 = w10303 - w516;
assign o_data0 = w19574;
//multiplier_block area estimate = 6592.92476670735;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( unroll-loops ) using namespace std; const long long MOD = 998244353; const long long INF = 0x7f7f7f7f7f7f7f7f; const int INFi = 0x7f7f7f7f; const long long N = 150001; vector<long long> adj[N]; long long vis[N] = {}; int dx8[] = {0, 1, 1, 1, 0, -1, -1, -1}, dy8[] = {1, 1, 0, -1, -1, -1, 0, 1}; int dx4[] = {0, 1, 0, -1}, dy4[] = {1, 0, -1, 0}; int t = 1; long long n, a[2 * N + 10], fact[2 * N + 10]; long long mult(long long a, long long b) { return (a % MOD * b % MOD) % MOD; } long long add(long long a, long long b) { return (a % MOD + b % MOD) % MOD; } long long subt(long long a, long long b) { return (a % MOD - b % MOD + MOD) % MOD; } long long fastModInv(long long x) { long long res = 1; long long y = MOD - 2; while (y) { if (y & 1) res = mult(res, x); y >>= 1; x = mult(x, x); } return res; } void MAIN() { cin >> n; long long ans = 0; for (long long i = 1; i <= 2 * n; i++) cin >> a[i], a[i] = 2 * a[i]; sort(a + 1, a + 1 + 2 * n); long long val = (fact[2 * n - 1] * fastModInv(fact[2 * n - 1 - n + 1]) % MOD) * fastModInv(fact[n - 1]) % MOD; for (long long i = 1; i <= n; i++) ans = subt(ans, val * a[i] % MOD); for (long long i = n + 1; i <= 2 * n; i++) ans = add(ans, val * a[i] % MOD); cout << ans << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed; cout << setprecision(10); ; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); ; fact[0] = 1; for (long long i = 1; i <= 2 * N; i++) fact[i] = fact[i - 1] * i % MOD; while (t--) { MAIN(); } }
|
#include <bits/stdc++.h> using namespace std; bool debug = 1; int n, m, k; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; long long ln, lk, lm; int dp[1 << 20], s[105], t[105]; string ac[105]; int main() { scanf( %d , &n); for (int(i) = 0; (i) < (int)(n); (i)++) scanf( %d , s + i); sort(s, s + n); reverse(s, s + n); scanf( %d , &m); for (int(i) = 0; (i) < (int)(m); (i)++) cin >> ac[i] >> t[i]; for (int i = 1; i < (1 << m); i++) { int id = m - __builtin_popcount(i); dp[i] = t[id] == 1 ? -(1e8) : ((1e8)); for (int j = 0; j < m; j++) { if ((1 << j) & i) { if (t[id] == 1) { dp[i] = max(dp[i], (ac[id] == p ? s[j] : 0) + dp[i - (1 << j)]); } else { dp[i] = min(dp[i], (ac[id] == p ? -s[j] : 0) + dp[i - (1 << j)]); } } } } cout << dp[(1 << m) - 1] << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; while (cin >> a >> b) { if (a == 0 && b == 0) cout << NO << endl; else { c = abs(a - b); if (c == 0 || c == 1) cout << YES << endl; else cout << NO << endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int mod = (int)1e9 + 7; const int N_ = (int)1e6 + 2; long long Hash_a[N_]; long long Hash_b[N_]; long long pow26[N_]; string a, b; long long n; long long get_hash_a(long long x, long long y) { return (Hash_a[y] - Hash_a[x - 1] * pow26[y - x + 1] + 1LL * mod * mod) % mod; } long long get_hash_b(long long x, long long y) { return (Hash_b[y] - Hash_b[x - 1] * pow26[y - x + 1] + 1LL * mod * mod) % mod; } bool F(long long L1, long long R1, long long L2, long long R2) { int len = R1 - L1 + 1; if (len % 2 == 1) { return get_hash_a(L1, R1) == get_hash_b(L2, R2); } else { if (get_hash_a(L1, R1) == get_hash_b(L2, R2)) return true; int R_1 = L1 + len / 2 - 1; int L_1 = R_1 + 1; int R_2 = L2 + len / 2 - 1; int L_2 = R_2 + 1; if (F(L1, R_1, L_2, R2) && F(L_1, R1, L2, R_2)) return true; if (F(L1, R_1, L2, R_2) && F(L_1, R1, L_2, R2)) return true; return false; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> a >> b; n = a.size(); pow26[0] = 1; for (int i = 1; i <= n; i++) { Hash_a[i] = (Hash_a[i - 1] * 26 + (a[i - 1] - a + 1)) % mod; Hash_b[i] = (Hash_b[i - 1] * 26 + (b[i - 1] - a + 1)) % mod; pow26[i] = pow26[i - 1] * 26; pow26[i] %= mod; } if (F(1, n, 1, n)) cout << YES ; else cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; char ch = getchar(); bool positive = 1; for (; ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) positive = 0; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; return positive ? x : -x; } int N, K; int a[105], b[105], s[105]; int t[105]; inline void trans_one(int p[]) { for (int i = 1; i <= N; ++i) t[i] = p[a[i]]; for (int i = 1; i <= N; ++i) p[i] = t[i]; } inline void trans_two(int p[]) { for (int i = 1; i <= N; ++i) t[a[i]] = p[i]; for (int i = 1; i <= N; ++i) p[i] = t[i]; } inline bool equal(int a[], int b[]) { for (int i = 1; i <= N; ++i) if (a[i] != b[i]) return 0; return 1; } int main() { N = read(), K = read(); for (int i = 1; i <= N; ++i) a[i] = read(); for (int i = 1; i <= N; ++i) s[i] = read(); for (int i = 1; i <= N; ++i) b[i] = i; if (equal(b, s)) return printf( NO n ), 0; int l = 1 << 30, r = 1 << 30; for (int i = 1; i <= K + 1; ++i) { trans_one(b); if (equal(b, s)) { r = i; break; } } for (int i = 1; i <= N; ++i) b[i] = i; for (int i = 1; i <= K + 1; ++i) { trans_two(b); if (equal(b, s)) { l = i; break; } } if (l % 2 == K % 2 && K >= l) { if (l > 1 || r > 1 || K - l == 0) return printf( YES n ), 0; } if (r % 2 == K % 2 && K >= r) { if (r > 1 || l > 1 || K - r == 0) return printf( YES n ), 0; } printf( NO n ); return 0; }
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#include <bits/stdc++.h> using namespace std; void read(int &val) { int x = 0; int bz = 1; char c; for (c = getchar(); (c < 0 || c > 9 ) && c != - ; c = getchar()) ; if (c == - ) { bz = -1; c = getchar(); } for (; c >= 0 && c <= 9 ; c = getchar()) x = x * 10 + c - 48; val = x * bz; } const int INF = 0x3f3f3f3f; const int maxn = 1e6 + 100; const int mod = 998244353; long long a[maxn], b[maxn]; int n, k; long long sum[maxn], tim[maxn]; struct node { int id; bool operator<(const node bb) const { return tim[id] > tim[bb.id]; } }; bool check(long long mid) { priority_queue<node> q; for (int i = 1; i <= n; i++) { tim[i] = a[i] / b[i]; sum[i] = a[i]; q.push(node{i}); } for (int i = 0; i <= k - 1; i++) { node top = q.top(); q.pop(); int xx = top.id; if (tim[xx] < i) return false; if (tim[xx] >= k) return true; sum[xx] += mid; tim[xx] = sum[xx] / b[xx]; if (tim[xx] < i) return false; q.push(node{xx}); } return true; } int main() { read(n); read(k); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); for (int i = 1; i <= n; i++) scanf( %lld , &b[i]); long long ans = -1, l = 0, r = 1e13; while (l <= r) { long long mid = l + r >> 1; if (check(mid)) { ans = mid; r = mid - 1; } else l = mid + 1; } printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 2, MAX2 = 2e6 + 4; int ans[MAX], val[MAX], depth[MAX]; vector<int> G[MAX], d[MAX2], occ[MAX2]; void init(int a) { if (d[a].size()) return; for (int i = 2; i * i <= a; i++) { if (a % i == 0) { d[a].push_back(a / i); if (i * i != a) d[a].push_back(i); } } if (a != 1) d[a].push_back(a); } void dfs(int vv, int par, int dv = 0) { ans[vv] = -1, depth[vv] = dv; int v = val[vv]; for (int i = 0; i < d[v].size(); i++) { int u = d[v][i]; if (not occ[u].empty()) { int x = occ[u].back(); if (ans[vv] == -1 or depth[ans[vv]] < depth[x]) ans[vv] = x; } occ[u].push_back(vv); } for (int i = 0; i < G[vv].size(); i++) { int u = G[vv][i]; if (u == par) continue; dfs(u, vv, dv + 1); } for (int i = 0; i < d[v].size(); i++) { int u = d[v][i]; occ[u].pop_back(); } } int main() { int n, q; cin >> n >> q; for (int i = 1; i < n + 1; i++) { scanf( %d , val + i); init(val[i]); } for (int i = 0; i < n - 1; i++) { int a, b; scanf( %d %d , &a, &b); G[a].push_back(b); G[b].push_back(a); } dfs(1, 0); while (q--) { int type; scanf( %d , &type); if (type == 1) { int x; scanf( %d , &x); printf( %d n , ans[x]); } else { int x, v; scanf( %d %d , &x, &v); val[x] = v; init(val[x]); dfs(1, 0); } } return 0; }
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/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_10g_fifo
*/
module test_eth_mac_10g_fifo_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH/8);
parameter AXIS_DATA_WIDTH = DATA_WIDTH;
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8);
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
parameter TX_FRAME_FIFO = 1;
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
parameter TX_DROP_WHEN_FULL = 0;
parameter RX_FIFO_DEPTH = 4096;
parameter RX_FIFO_PIPELINE_OUTPUT = 2;
parameter RX_FRAME_FIFO = 1;
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg logic_clk = 0;
reg logic_rst = 0;
reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg rx_axis_tready = 0;
reg [DATA_WIDTH-1:0] xgmii_rxd = 0;
reg [CTRL_WIDTH-1:0] xgmii_rxc = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire tx_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [DATA_WIDTH-1:0] xgmii_txd;
wire [CTRL_WIDTH-1:0] xgmii_txc;
wire tx_error_underflow;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
logic_clk,
logic_rst,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
rx_axis_tready,
xgmii_rxd,
xgmii_rxc,
ifg_delay
);
$to_myhdl(
tx_axis_tready,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
xgmii_txd,
xgmii_txc,
tx_error_underflow,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame
);
// dump file
$dumpfile("test_eth_mac_10g_fifo_64.lxt");
$dumpvars(0, test_eth_mac_10g_fifo_64);
end
eth_mac_10g_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.logic_clk(logic_clk),
.logic_rst(logic_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_error_underflow(tx_error_underflow),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.ifg_delay(ifg_delay)
);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse2 ) using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; vector<long long> cnt(n + 1, 0); bool ch = 1; for (long long i = 0; i < n - 1; i++) { long long a, b; cin >> a >> b; if (a == n && b == n) ch = 0; cnt[a]++; cnt[b]++; } if (cnt[n] != n - 1) ch = 0; vector<vector<long long> > g(n + 1); vector<long long> v1; vector<long long> v2; for (long long i = n - 1; i >= 1; i--) { if (cnt[i]) v1.push_back(i); else v2.push_back(i); } long long s2 = v2.size(); long long j = 0; for (long long i = 0; i < v1.size(); i++) { long long d = cnt[v1[i]] - 1; long long p = n; while (d && j < s2) { g[p].push_back(v2[j]); p = v2[j]; if (p > v1[i]) ch = 0; j++; d--; } if (d) ch = 0; g[p].push_back(v1[i]); } if (j != s2) ch = 0; if (ch) { cout << YES << n ; for (long long i = 1; i <= n; i++) { for (auto it : g[i]) { cout << i << << it << n ; } } } else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; long long dp[26][2][2]; long long need; bool hasone = 0; int ans[55]; inline void upd(long long &a, long long b) { a += b; } inline long long getval(int p, int v) { memset(dp, 0, sizeof(dp)); dp[0][0][0] = 1; for (int i = 0; i < (n + 1) / 2; i++) { for (int x = 0; x < 2; x++) { for (int y = 0; y < 2; y++) { if (!dp[i][x][y]) continue; for (int a = 0; a < 2; a++) { if (!i && a) continue; if (i <= p && a != ans[i]) continue; for (int b = 0; b < 2; b++) { if ((n - 1 - i) <= p && b != ans[n - 1 - i]) continue; if (i == n - 1 - i && a != b) continue; if (a > b && !x) continue; if (a > !b && !y) continue; upd(dp[i + 1][x | (a < b)][y | (a < !b)], dp[i][x][y]); } } } } } return dp[(n + 1) / 2][0][0] + dp[(n + 1) / 2][0][1] + dp[(n + 1) / 2][1][0] + dp[(n + 1) / 2][1][1] - !hasone; } int main() { cin >> n >> need; dp[0][0][0] = 1; for (int i = 0; i < (n + 1) / 2; i++) { for (int x = 0; x < 2; x++) { for (int y = 0; y < 2; y++) { if (!dp[i][x][y]) continue; for (int a = 0; a < 2; a++) { if (!i && a) continue; for (int b = 0; b < 2; b++) { if (i == n - 1 - i && a != b) continue; if (a > b && !x) continue; if (a > !b && !y) continue; upd(dp[i + 1][x | (a < b)][y | (a < !b)], dp[i][x][y]); } } } } } long long all = dp[(n + 1) / 2][0][0] + dp[(n + 1) / 2][0][1] + dp[(n + 1) / 2][1][0] + dp[(n + 1) / 2][1][1]; all--; if (all < need) { printf( -1 n ); return 0; } for (int i = 0; i < n; i++) { ans[i] = 0; long long num = getval(i, ans[i]); if (num < need || (i == n - 1 && !hasone)) { ans[i] = 1; need -= num; hasone = 1; } } for (int i = 0; i < n; i++) printf( %d , ans[i]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBP_TB_V
`define SKY130_FD_SC_HD__DFBBP_TB_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfbbp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 RESET_B = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 RESET_B = 1'b0;
#340 SET_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SET_B = 1'b1;
#540 RESET_B = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SET_B = 1'bx;
#680 RESET_B = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__dfbbp dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBP_TB_V
|
module timer(
input CLK,
input switch_up,
input switch_dn,
input switch_cancel,
input switch_start_stop,
output [7:0] SEG,
output [3:0] DIGIT,
output BUZZER
);
wire s_up, s_dn, s_cancel, s_start_stop;
debouncer d1(.CLK (CLK), .switch_input (switch_up), .trans_up (s_up));
debouncer d2(.CLK (CLK), .switch_input (switch_dn), .trans_up (s_dn));
debouncer d3(.CLK (CLK), .switch_input (switch_cancel), .trans_up (s_cancel));
debouncer d4(.CLK (CLK), .switch_input (switch_start_stop), .trans_up (s_start_stop));
reg alarm_on = 0;
alarm a(.CLK (CLK), .BUZZER (BUZZER), .enable (alarm_on));
reg [3:0] secs = 0;
reg [3:0] ten_secs = 0;
reg [3:0] mins = 1;
reg [3:0] mins_stored;
reg [3:0] unused_digit = 4'd10; // digits above 9 not displayed
reg [25:0] prescaler = 0;
display_7_seg display(.CLK (CLK),
.units (secs), .tens (ten_secs), .hundreds (mins), .thousands (unused_digit),
.SEG (SEG), .DIGIT (DIGIT));
// States
localparam SETTING = 0, RUNNING = 1, BEEPING = 2;
reg [1:0] state = SETTING;
always @(posedge CLK)
begin
case (state)
SETTING : begin
handle_settings();
if (s_start_stop)
begin
mins_stored <= mins;
state <= RUNNING;
end
end
RUNNING : begin
decrement_time();
if (s_start_stop)
begin
state <= SETTING;
end
if (s_cancel)
begin
reset_time();
state <= SETTING;
end
if ((secs == 0) & (ten_secs == 0) & (mins == 0))
begin
alarm_on <= 1;
state <= BEEPING;
end
end
BEEPING : begin
if (s_cancel)
begin
alarm_on <= 0;
state <= SETTING;
reset_time();
end
end
endcase
end
task handle_settings;
begin
if (s_up)
begin
mins <= mins + 1;
if (mins == 9)
begin
mins <= 1;
end
end
if (s_dn)
begin
mins <= mins - 1;
if (mins == 1)
begin
mins <= 9;
end
end
end
endtask
task decrement_time;
begin
prescaler <= prescaler + 1;
if (prescaler == 26'd31999999) // 32 MHz to 1Hz
begin
prescaler <= 0;
secs <= secs - 1;
if (secs < 1)
begin
secs <= 9;
ten_secs <= ten_secs - 1;
if (ten_secs < 1)
begin
ten_secs <= 5;
mins <= mins - 1;
end
end
end
end
endtask
task reset_time;
begin
secs <= 0;
ten_secs <= 0;
mins <= mins_stored;
end
endtask
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module read data from the Audio ADC on the Altera DE2 board. *
* *
******************************************************************************/
module altera_up_audio_in_deserializer (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
done_channel_sync,
serial_audio_in_data,
read_left_audio_data_en,
read_right_audio_data_en,
// Bidirectionals
// Outputs
left_audio_fifo_read_space,
right_audio_fifo_read_space,
left_channel_data,
right_channel_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15;
parameter BIT_COUNTER_INIT = 5'h0F;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
input done_channel_sync;
input serial_audio_in_data;
input read_left_audio_data_en;
input read_right_audio_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] left_audio_fifo_read_space;
output reg [ 7: 0] right_audio_fifo_read_space;
output [DW: 0] left_channel_data;
output [DW: 0] right_channel_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire valid_audio_input;
wire left_channel_fifo_is_empty;
wire right_channel_fifo_is_empty;
wire left_channel_fifo_is_full;
wire right_channel_fifo_is_full;
wire [ 6: 0] left_channel_fifo_used;
wire [ 6: 0] right_channel_fifo_used;
// Internal Registers
reg [DW: 0] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
left_audio_fifo_read_space <= 8'h00;
else
begin
left_audio_fifo_read_space[7] <= left_channel_fifo_is_full;
left_audio_fifo_read_space[6:0] <= left_channel_fifo_used;
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
right_audio_fifo_read_space <= 8'h00;
else
begin
right_audio_fifo_read_space[7] <= right_channel_fifo_is_full;
right_audio_fifo_read_space[6:0] <= right_channel_fifo_used;
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_in_shift_reg <= 'h0;
else if (bit_clk_rising_edge & valid_audio_input)
data_in_shift_reg <=
{data_in_shift_reg[(DW - 1):0],
serial_audio_in_data};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_audio_bit_counter Audio_Out_Bit_Counter (
// Inputs
.clk (clk),
.reset (reset),
.bit_clk_rising_edge (bit_clk_rising_edge),
.bit_clk_falling_edge (bit_clk_falling_edge),
.left_right_clk_rising_edge (left_right_clk_rising_edge),
.left_right_clk_falling_edge (left_right_clk_falling_edge),
// Bidirectionals
// Outputs
.counting (valid_audio_input)
);
defparam
Audio_Out_Bit_Counter.BIT_COUNTER_INIT = BIT_COUNTER_INIT;
altera_up_sync_fifo Audio_In_Left_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_right_clk_falling_edge & ~left_channel_fifo_is_full & done_channel_sync),
.write_data (data_in_shift_reg),
.read_en (read_left_audio_data_en & ~left_channel_fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (left_channel_fifo_is_empty),
.fifo_is_full (left_channel_fifo_is_full),
.words_used (left_channel_fifo_used),
.read_data (left_channel_data)
);
defparam
Audio_In_Left_Channel_FIFO.DW = DW,
Audio_In_Left_Channel_FIFO.DATA_DEPTH = 128,
Audio_In_Left_Channel_FIFO.AW = 6;
altera_up_sync_fifo Audio_In_Right_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_right_clk_rising_edge & ~right_channel_fifo_is_full & done_channel_sync),
.write_data (data_in_shift_reg),
.read_en (read_right_audio_data_en & ~right_channel_fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (right_channel_fifo_is_empty),
.fifo_is_full (right_channel_fifo_is_full),
.words_used (right_channel_fifo_used),
.read_data (right_channel_data)
);
defparam
Audio_In_Right_Channel_FIFO.DW = DW,
Audio_In_Right_Channel_FIFO.DATA_DEPTH = 128,
Audio_In_Right_Channel_FIFO.AW = 6;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int dem = 0; int n; int tong = 0; int s; cin >> n; for (int i = 9; i >= 1; i--) { if (n % i == 0) { s = i; break; } } int z; z = n / s; cout << z << endl; while (z) { cout << s << ; z--; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Sun Jun 18 18:41:11 2017
// Host : DESKTOP-GKPSR1F running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v
// Design : clk_wiz_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, reset, locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,reset,locked,clk_in1" */;
output clk_out1;
input reset;
output locked;
input clk_in1;
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[1000001], t[1000001]; long long z[1000001], c[1000001]; int main() { int n, k; scanf( %d%d%s%s , &n, &k, s + 1, t + 1); if (k == 1) { printf( %d n , k * n); return 0; } int o = 1; while (o <= n && s[o] == t[o]) o++; if (o > n) { printf( %d n , n); return 0; } long long ans = n + (n - o + 1); k -= 2; o++; while (o <= n) { if (s[o] == a ) z[n - o + 1]++; if (t[o] == b ) z[n - o + 1]++; o++; } for (int i = n; i; i--) { z[i] += c[i]; c[i - 1] += c[i]; int kk = min(1ll * k, z[i]); ans += 1ll * i * kk; k -= kk; c[i - 1] += kk; } printf( %I64d n , ans); }
|
`timescale 1ns / 1ps
/*
-- Module Name: DES Sbox 2
-- Description: Sbox 2 del algoritmo DES
-- Dependencies: -- none
-- Parameters: -- none
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 05 de Junio 2015
*/
module des_sbox2
(
// -- inputs ------------------------------------------------- >>>>>
input wire [0:5] right_xor_key_segment_din,
// -- outputs ------------------------------------------------ >>>>>
output reg [0:3] sbox_dout
);
always @(*)
case ({right_xor_key_segment_din[0], right_xor_key_segment_din[5]})
2'b00:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd15;
4'd1: sbox_dout = 4'd1;
4'd2: sbox_dout = 4'd8;
4'd3: sbox_dout = 4'd14;
4'd4: sbox_dout = 4'd6;
4'd5: sbox_dout = 4'd11;
4'd6: sbox_dout = 4'd3;
4'd7: sbox_dout = 4'd4;
4'd8: sbox_dout = 4'd9;
4'd9: sbox_dout = 4'd7;
4'd10: sbox_dout = 4'd2;
4'd11: sbox_dout = 4'd13;
4'd12: sbox_dout = 4'd12;
4'd13: sbox_dout = 4'd0;
4'd14: sbox_dout = 4'd5;
4'd15: sbox_dout = 4'd10;
endcase
2'b01:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd3;
4'd1: sbox_dout = 4'd13;
4'd2: sbox_dout = 4'd4;
4'd3: sbox_dout = 4'd7;
4'd4: sbox_dout = 4'd15;
4'd5: sbox_dout = 4'd2;
4'd6: sbox_dout = 4'd8;
4'd7: sbox_dout = 4'd14;
4'd8: sbox_dout = 4'd12;
4'd9: sbox_dout = 4'd0;
4'd10: sbox_dout = 4'd1;
4'd11: sbox_dout = 4'd10;
4'd12: sbox_dout = 4'd6;
4'd13: sbox_dout = 4'd9;
4'd14: sbox_dout = 4'd11;
4'd15: sbox_dout = 4'd5;
endcase
2'b10:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd0;
4'd1: sbox_dout = 4'd14;
4'd2: sbox_dout = 4'd7;
4'd3: sbox_dout = 4'd11;
4'd4: sbox_dout = 4'd10;
4'd5: sbox_dout = 4'd4;
4'd6: sbox_dout = 4'd13;
4'd7: sbox_dout = 4'd1;
4'd8: sbox_dout = 4'd5;
4'd9: sbox_dout = 4'd8;
4'd10: sbox_dout = 4'd12;
4'd11: sbox_dout = 4'd6;
4'd12: sbox_dout = 4'd9;
4'd13: sbox_dout = 4'd3;
4'd14: sbox_dout = 4'd2;
4'd15: sbox_dout = 4'd15;
endcase
2'b11:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd13;
4'd1: sbox_dout = 4'd8;
4'd2: sbox_dout = 4'd10;
4'd3: sbox_dout = 4'd1;
4'd4: sbox_dout = 4'd3;
4'd5: sbox_dout = 4'd15;
4'd6: sbox_dout = 4'd4;
4'd7: sbox_dout = 4'd2;
4'd8: sbox_dout = 4'd11;
4'd9: sbox_dout = 4'd6;
4'd10: sbox_dout = 4'd7;
4'd11: sbox_dout = 4'd12;
4'd12: sbox_dout = 4'd0;
4'd13: sbox_dout = 4'd5;
4'd14: sbox_dout = 4'd14;
4'd15: sbox_dout = 4'd9;
endcase
endcase // right_xor_key_segment_din[0], right_xor_key_segment_din[5]
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
des_sbox2 sbox2
(
// -- inputs ------------------------------------------------- >>>>>
.right_xor_key_segment_din (right_xor_key_segment),
// -- outputs ------------------------------------------------ >>>>>
sbox_dout (sbox_dout)
);
*/
|
#include <bits/stdc++.h> using namespace std; int main() { long long int q; cin >> q; while (q--) { long long int n; cin >> n; long long int x, y; int l, u, r, s; long long int nl = -100000, nu = 100000, nr = 100000, ns = -100000; for (long long int i = 0; i < n; i++) { cin >> x >> y >> l >> u >> r >> s; if (l == 0 && nl <= x) { nl = x; } if (u == 0 && nu >= y) { nu = y; } if (r == 0 && nr >= x) { nr = x; } if (s == 0 && ns <= y) { ns = y; } } if (ns <= nu && nl <= nr) { std::cout << 1 << << nl << << ns << std::endl; } else { std::cout << 0 << std::endl; } } }
|
#include <bits/stdc++.h> using namespace std; int a, b, diff, n_div; int main() { int i; cin >> a >> b; diff = a - b; if (diff < 0) { cout << 0 << endl; } else if (diff == 0) { cout << infinity << endl; return 0; } else { for (i = 1; i * i <= diff; i++) if (diff % i == 0) { if (i > b) n_div++; if (diff / i > b && diff / i != i) n_div++; } cout << n_div << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O311A_BEHAVIORAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; vector<int> childs[100000 + 1]; long long s[100000 + 1]; int p[100000 + 1]; long long a[100000 + 1]; bool flag = false; void fill(int v, long long prevsum) { if (s[v] != -1) { a[v] = s[v] - prevsum; if (a[v] < 0) flag = true; for (int i = 0; i < childs[v].size(); ++i) { fill(childs[v][i], s[v]); } } else { long long mi = 1000000001; for (int i = 0; i < childs[v].size(); ++i) { mi = min(mi, s[childs[v][i]]); } if (mi == 1000000001) mi = prevsum; a[v] = mi - prevsum; if (a[v] < 0) flag = true; for (int i = 0; i < childs[v].size(); ++i) { fill(childs[v][i], mi); } } } int main() { int n; cin >> n; for (int i = 0; i < n; ++i) { childs[i].clear(); } for (int i = 2; i < n + 1; ++i) { cin >> p[i]; childs[p[i]].push_back(i); } for (int i = 1; i < n + 1; ++i) { cin >> s[i]; } fill(1, 0); if (flag) cout << -1 << endl; else { long long sum = 0; for (int i = 1; i < n + 1; ++i) { sum += a[i]; } cout << sum << endl; } }
|
#include <bits/stdc++.h> using namespace std; vector<long long> v[70]; int n; long long ans[100010], cur = 0; int main() { cin >> n; for (int i = 1; i <= n; i++) { long long x; cin >> x; for (int j = 60; j >= 0; j--) if ((x >> j) & 1) { v[j].push_back(x); break; } } for (int i = 1; i <= n; i++) { bool flag = 0; for (int j = 0; j <= 60; j++) if (!(cur & (1ll << j)) && !v[j].empty()) { cur ^= (ans[i] = v[j].back()); v[j].pop_back(); flag = 1; break; } if (!flag) { cout << No << endl; return 0; } } cout << Yes << endl; for (int i = 1; i <= n; i++) cout << ans[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long b, long long y) { return b > 0 ? gcd(y % b, b) : y; } long long lcm(long long b, long long y) { return b * y / gcd(b, y); } double dis(double x1, double x2, double y1, double y2) { double ans = (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); return sqrt(ans); } double random(double start, double en) { return start + (en - start) * rand() / (RAND_MAX + 1.0); } map<int, vector<int> > a; map<int, int> b; map<int, vector<int> >::iterator it; void dfs(int x) { if (b[x]) return; b[x] = 1; cout << x << ; for (int i = 0; i < a[x].size(); i++) { dfs(a[x][i]); } return; } int main() { int n; while (cin >> n) { for (int i = 1; i <= n; i++) { int x, y; cin >> x >> y; a[x].push_back(y); a[y].push_back(x); } int t; for (it = a.begin(); it != a.end(); it++) { if (it->second.size() == 1) { t = it->first; break; } } dfs(t); } }
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [15:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // SNES ROM access
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output obc1_enable
);
parameter [2:0]
FEAT_MSU1 = 3,
FEAT_213F = 4
;
wire [23:0] SRAM_SNES_ADDR;
/* currently supported mappers:
Index Mapper
000 HiROM
001 LoROM
010 ExHiROM (48-64Mbit)
*/
/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
Offset 6000-7fff */
assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]));
assign IS_SAVERAM = SAVERAM_MASK[0]
&(((MAPPER == 3'b000
|| MAPPER == 3'b010)
? (!SNES_ADDR[22]
& SNES_ADDR[21]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
)
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xff
* Offset 0000-7fff for ROM >= 32 MBit, otherwise 0000-ffff */
:(MAPPER == 3'b001)
? (&SNES_ADDR[22:20]
& (~SNES_ROMSEL)
& (~SNES_ADDR[15] | ~ROM_MASK[21])
)
: 1'b0));
assign IS_WRITABLE = IS_SAVERAM;
assign SRAM_SNES_ADDR = ((MAPPER == 3'b000)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
:(MAPPER == 3'b001)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[14:0]}
& SAVERAM_MASK)
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK))
:(MAPPER == 3'b010)
?(IS_SAVERAM
? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]}
& SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
& ROM_MASK))
: 24'b0);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign ROM_SEL = 1'b0;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
assign obc1_enable = (~SNES_ADDR[22]) & (SNES_ADDR[15:11] == 5'b01111);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A5A);
assign branch1_enable = (SNES_ADDR == 24'h002A13);
assign branch2_enable = (SNES_ADDR == 24'h002A4D);
endmodule
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#include <bits/stdc++.h> using namespace std; int cnt[15]; int s[15]; char c[1 << 20]; int need[15]; int digits(int first) { return !first ? 0 : 1 + digits(first / 10); } int main(void) { int n; string str; cin >> (c + 1) >> str; n = strlen(c + 1); for (auto it : str) ++need[it - 0 ]; for (int i = 1; i <= n; ++i) ++cnt[c[i] - 0 ]; for (int nr = 1; nr < n; ++nr) if (digits(nr) + nr == n) { for (int i = 0; i <= 9; ++i) s[i] = cnt[i]; int sum = nr; while (sum) --s[sum % 10], sum /= 10; int can = 1; for (int i = 0; i <= 9; ++i) if (s[i] < need[i]) can = 0; int prim = 1; for (int i = 0; i <= 9; ++i) s[i] -= need[i]; for (; prim <= 9; ++prim) if (s[prim] || (prim == str[0] - 0 && !s[prim])) break; if (prim == 10) can = 0; if (can) { string ans1 = , ans2 = ; int ct = 0; while (ct + 1 < str.length() && str[ct] == str[ct + 1]) ++ct; int after = -1; if (ct + 1 >= str.length() || str[ct] > str[ct + 1]) after = 0; else after = 1; string str1 = str, str2 = str; if (prim == str[0] - 0 ) { ans1 += str1; str1 = ; } for (int i = 0; i <= 9; ++i) cnt[i] -= need[i]; ans2 += prim + 0 ; int sum = nr; while (sum) --cnt[sum % 10], sum /= 10; --cnt[prim]; for (int i = 0; i <= 9; ++i) while (s[i] > 0) --s[i], ans1 += i + 0 ; for (int i = 0; i <= 9; ++i) { if (!str2.empty()) { if (after && i > str2[0] - 0 ) ans2 += str2, str2 = ; else if (!after && i >= str2[0] - 0 ) ans2 += str2, str2 = ; } while (cnt[i] > 0) --cnt[i], ans2 += i + 0 ; } for (int i = 0; i <= 9; ++i) if (cnt[i] < 0) ans2 = ; if (ans1.length() == ans2.length()) cout << min(ans1, ans2) << n ; else { if (ans2 == ) cout << ans1 << n ; else cout << ans2 << n ; } return 0; } } assert(cnt[0] == 1 && cnt[1] == 1 && n == 2); cout << 0 n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int a[1000005]; int main() { int t, n; cin >> t; while (t--) { cin >> n; int g = 0, s = 0, b = 0; int m = n / 2; for (int i = 1; i <= n; i++) { cin >> a[i]; } int i = 1; while (a[i] == a[1] && i <= m) { i++; g++; } int j = i; while (a[i] == a[j] && i <= m) { i++; s++; } while (s <= g && i <= m) { int k = i; while (a[i] == a[k] && i <= m) { s++; i++; } } while (a[i] != a[m + 1] && i <= m) { b++; i++; } if (g >= s || g >= b) { cout << 0 0 0 n ; continue; } cout << g << << s << << b << << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); string str; cin >> str; int n = str.length(); map<char, int> mp; for (int i = 0; i < n; i++) { mp[str[i]]++; } if (mp.size() % 2 == 1) cout << IGNORE HIM! ; else cout << CHAT WITH HER! ; cout << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; void doRoutine() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } void minus1(string &s) { long long i = (long long)s.size() - 1; while (i >= 0 && s[i] == 0 ) { s[i] = 9 ; --i; } --s[i]; if (i == 0 && s[i] == 0 ) { s.erase(s.begin()); } } void solve_ez(string &s) { long long n = s.size(); string t(n - 2, 9 ); cout << t << endl; } void solve(string &s) { if (s.size() % 2 == 1) { cout << string((long long)s.size() - 1, 9 ) << endl; return; } long long n = s.size(); vector<long long> pref(n + 1); for (long long i = 0; i < n; ++i) { pref[i + 1] = pref[i] + (s[i] - 0 ); } vector<long long> odd(10); long long max_pref = 0; for (long long i = 0; i < n; ++i) { long long dig = s[i] - 0 ; odd[dig] = (odd[dig] + 1) % 2; vector<long long> odds; for (long long c = 0; c < 10; ++c) { if (odd[c]) { odds.push_back(c); } } bool ok = false; long long cnt = odds.size(); if (n - i - 1 >= cnt) { if (pref[n - cnt] - pref[i + 1] > 0) { ok = true; } else { ok = true; for (long long j = 0; j < cnt; ++j) { long long s_dig = (s[n - cnt + j] - 0 ); long long cur_dig = odds[j]; if (cur_dig < s_dig) { break; } else if (cur_dig > s_dig) { ok = false; } } } } if (!ok) { break; } else { max_pref = i + 1; } } if (max_pref == n) { cout << s << endl; return; } for (long long c = (s[max_pref] - 0 ) - 1; c >= (max_pref == 0 ? 1 : 0); --c) { fill(odd.begin(), odd.end(), 0); for (long long i = 0; i < max_pref; ++i) { long long dig = s[i] - 0 ; odd[dig] = (odd[dig] + 1) % 2; } odd[c] = (odd[c] + 1) % 2; vector<long long> odds; for (long long x = 9; x >= 0; --x) { if (odd[x]) { odds.push_back(x); } } if ((long long)odds.size() <= n - max_pref - 1) { string res; for (long long i = 0; i < max_pref; ++i) { res.push_back(s[i]); } res.push_back((char)(c + 0 )); for (long long i = 0; i < n - max_pref - 1 - (long long)odds.size(); ++i) { res.push_back( 9 ); } for (auto el : odds) { res.push_back((char)(el + 0 )); } cout << res << endl; return; } } solve_ez(s); } signed main() { doRoutine(); long long n; cin >> n; while (n--) { string s; cin >> s; minus1(s); solve(s); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1005; struct Edge { int u, v, w, id; Edge() {} Edge(int a, int b, int c, int d) : u(a), v(b), w(c), id(d) {} bool operator<(const Edge e) const { return w > e.w; } } e[maxn * maxn]; int fa[maxn << 1]; int Find(int x) { return fa[x] == x ? fa[x] : (fa[x] = Find(fa[x])); } void Merge(int a, int b) { int x = Find(a); int y = Find(b); fa[x] = y; } int main() { int n, m, q; while (scanf( %d%d%d , &n, &m, &q) != EOF) { int u, v, w; for (int i = 0; i < m; i++) { scanf( %d %d %d , &u, &v, &w); e[i] = Edge(u, v, w, i + 1); } sort(e, e + m); while (q--) { int flag = 0; for (int i = 1; i <= 2 * n; i++) fa[i] = i; scanf( %d%d , &u, &v); for (int i = 0; i < m; i++) { if (e[i].id < u || e[i].id > v) continue; if (Find(e[i].u) == Find(e[i].v)) { printf( %d n , e[i].w); flag = 1; break; } else { Merge(e[i].u, e[i].v + n); Merge(e[i].v, e[i].u + n); } } if (!flag) printf( -1 n ); } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int n, s; long long a[maxn], b[maxn], c[maxn]; vector<int> p[2]; bool cmp1(int i, int j) { return b[i] - c[i] > b[j] - c[j]; } bool cmp2(int i, int j) { return c[i] - b[i] > c[j] - b[j]; } int main() { scanf( %d%d , &n, &s); long long tot = 0, A = 0, B = 0, v1 = 0, v2 = 0; p[0].clear(); p[1].clear(); for (int i = 0; i < n; i++) { scanf( %I64d%I64d%I64d , a + i, b + i, c + i); tot += a[i]; if (b[i] > c[i]) { p[0].push_back(i); A += a[i] * b[i]; v1 += a[i]; } else { p[1].push_back(i); B += a[i] * c[i]; v2 += a[i]; } } sort(p[0].begin(), p[0].end(), cmp1); sort(p[1].begin(), p[1].end(), cmp2); long long ans = 0; long long c1 = v1 / s + (v1 % s ? 1 : 0); long long c2 = v2 / s + (v2 % s ? 1 : 0); tot = tot / s + (tot % s ? 1 : 0); if (c1 + c2 > tot) { long long tmp = A + B; long long now = v1 % s; for (int i = p[0].size() - 1; i >= 0; i--) { now -= a[p[0][i]]; long long cnt = a[p[0][i]]; if (now < 0) cnt = a[p[0][i]] + now; tmp += (c[p[0][i]] - b[p[0][i]]) * cnt; if (now <= 0) break; } ans = max(ans, tmp); tmp = A + B; now = v2 % s; for (int i = p[1].size() - 1; i >= 0; i--) { now -= a[p[1][i]]; long long cnt = a[p[1][i]]; if (now < 0) cnt = a[p[1][i]] + now; tmp += (b[p[1][i]] - c[p[1][i]]) * cnt; if (now <= 0) break; } ans = max(ans, tmp); } else ans = A + B; printf( %I64d n , ans); return 0; }
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`timescale 1ns/10ps
/*
功能：读写地址生成
输入：nrst-0复位
clk-时钟
wr_en-允许写
wr_inc-1写地址自增
load_w2r-加载写地址到读地址
rd_inc-读地址自增
rd_step-读地址自增大小，有符号数，负数为地址减小
输出：addr_wr-写地址
addr_rd-读地址
wr_end-1写满（写地址到达读地址）
修改：eleqian 2016-01-22
*/
module addr_gen(nrst, clk, wr_en, wr_inc, load_w2r, rd_inc, rd_step, addr_wr, addr_rd, wr_end);
input nrst;
input clk;
input wr_en;
input wr_inc;
input load_w2r;
input rd_inc;
input [7:0] rd_step;
output [17:0] addr_wr;
output [17:0] addr_rd;
output wr_end;
wire [17:0] addr_wr;
wire [17:0] addr_rd;
wire [17:0] rd_step_ex;
reg wr_end;
wire wr_inc_sig;
wire reach;
// 写地址返回到读地址表示写满，实现预触发深度调整是触发后立即修改读地址到需要位置
assign reach = (addr_wr == addr_rd);
assign wr_inc_sig = wr_en & wr_inc & ~wr_end;
assign rd_step_ex = {{11{rd_step[7]}}, rd_step[6:0]};
// 写地址自增
cntn #(18) u_wrcnt(.nrst(nrst), .clk(clk),
.en(wr_inc_sig), .step(1), .load(0), .cin(0), .cnt(addr_wr));
// 触发时设置读地址为写地址，否则自增或自减
cntn #(18) u_rdcnt(.nrst(nrst), .clk(clk),
.en(rd_inc), .step(rd_step_ex), .load(load_w2r), .cin(addr_wr), .cnt(addr_rd));
// 生成采样完成信号，在停止采样时清除
always @(posedge clk or negedge nrst) begin
if (~nrst) begin
wr_end <= 1'b0;
end else if (reach) begin
wr_end <= 1'b1;
end else if (~wr_en) begin
wr_end <= 1'b0;
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; void solve() { long long n, x; cin >> n >> x; long long a[n]; for (auto &i : a) cin >> i; long long pre[n + 1]; pre[0] = 0; for (long long i = 1; i <= n; i++) pre[i] = (pre[i - 1] + a[i - 1]) % x; long long ans = 0; for (long long i = 1; i <= n; i++) { if (pre[i] != 0) ans = max(ans, i); } for (long long i = n; i >= 0; i--) { if (pre[i] != pre[n]) ans = max(ans, n - i); } if (ans == 0) cout << -1 << n ; else cout << ans << n ; } int32_t main() { long long t; cin >> t; while (t--) solve(); }
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#include <bits/stdc++.h> using namespace std; ifstream fin( Sisend.txt ); int n, c; bool b[100005]; vector<int> v, v1; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cerr.tie(0); cin >> n; for (int(i) = (0); ((i)) < ((n)); ((i))++) { cin >> c; v.emplace_back(c); } sort(v.rbegin(), v.rend()); int l = 1, r = v.size() / 2 + 1; int vas = 0; v1.emplace_back(v[0]); while (r < v.size()) { while (r < v.size() and v[r] == v[l]) r++; v1.emplace_back(v[r]), v1.emplace_back(v[l]); b[r] = 1; vas++; l++; r++; } while (l < v.size()) { if (!b[l]) { v1.emplace_back(v[l]); } l++; } cout << vas << endl; for (int i : v1) cout << i << ; }
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#include <bits/stdc++.h> template <typename T> inline void read(T &x) { x = 0; char c = getchar(); bool flag = false; while (!isdigit(c)) { if (c == - ) flag = true; c = getchar(); } while (isdigit(c)) x = x * 10 + (c ^ 48), c = getchar(); if (flag) x = -x; } using namespace std; int n, q, nn; bitset<2011> bt[1011][2], h[2011]; int htot; int ans[2011], pos[2011]; inline void Gauss() { int nw = 1; for (int i = 1; i < nn; ++i) { int id = -1; for (int hang = nw; hang <= htot; ++hang) if (h[hang][i]) { id = hang; break; } if (id == -1) continue; swap(h[id], h[nw]); pos[i] = nw; for (int hang = 1; hang <= htot; ++hang) if (hang != nw && h[hang][i]) { h[hang] = h[hang] ^ h[nw]; } ++nw; if (nw > htot) break; } for (int i = 1; i <= htot; ++i) if (h[i][nn]) { bool flag = false; for (int j = 1; j < nn; ++j) if (h[i][j]) { flag = true; break; } if (!flag) { puts( NO ); exit(0); } } for (int i = 1; i < nn; ++i) { ans[i] = h[pos[i]][nn]; } puts( YES ); for (int i = 1; i <= n; ++i) { if (ans[i] == 0 && ans[i + n] == 0) putchar( . ); else if (ans[i] == 1 && ans[i + n] == 0) putchar( R ); else if (ans[i] == 0 && ans[i + n] == 1) putchar( B ); else putchar( Y ); } putchar( n ); } int main() { read(n), read(q); nn = n + n + 1; for (int i = 1; i <= n; ++i) bt[i][0][i] = bt[i][1][i + n] = 1; for (int i = 1; i <= q; ++i) { char opt[6]; scanf( %s , opt); if (opt[0] == m ) { int k; read(k); htot += 2; for (int j = 1; j <= k; ++j) { int p; read(p); h[htot - 1] ^= bt[p][0]; h[htot] ^= bt[p][1]; } char res[3]; scanf( %s , res); if (res[0] == W ) h[htot - 1][nn] = 0, h[htot][nn] = 0; else if (res[0] == R ) h[htot - 1][nn] = 1, h[htot][nn] = 0; else if (res[0] == B ) h[htot - 1][nn] = 0, h[htot][nn] = 1; else h[htot - 1][nn] = 1, h[htot][nn] = 1; } else if (opt[0] == R && opt[1] == Y ) { int k; read(k); for (int j = 1; j <= k; ++j) { int p; read(p); bt[p][1] = bt[p][1] ^ bt[p][0]; } } else if (opt[0] == R && opt[1] == B ) { int k; read(k); for (int j = 1; j <= k; ++j) { int p; read(p); swap(bt[p][0], bt[p][1]); } } else if (opt[0] == Y && opt[1] == B ) { int k; read(k); for (int j = 1; j <= k; ++j) { int p; read(p); bt[p][0] = bt[p][0] ^ bt[p][1]; } } } Gauss(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1 << 12 | 5, Q = 1 << 16 | 5; int n, q, B, a[N], p[N], cnt, id[Q]; vector<pair<int, int>> opt; struct node { int n; vector<int> pos; vector<vector<int>> id; node(int _n = 0) { n = _n; pos.resize(n); id.resize(n); for (auto &v : id) { v.resize(n); } } inline int get(int l, int r) { l = lower_bound(pos.begin(), pos.end(), l) - pos.begin(); r = upper_bound(pos.begin(), pos.end(), r) - pos.begin() - 1; return l <= r ? id[l][r] : 0; } } sqr[N]; inline int merge(int x, int y) { int res; if (x && y) { opt.push_back({x, y}); res = ++cnt; } else { res = x | y; } return res; } node solve(int l, int r, int s) { if (l == r) { node res(1); res.pos = {p[s + l]}; res.id = {{p[s + l]}}; return res; } int mid = l + r >> 1; node x = solve(l, mid, s); node y = solve(mid + 1, r, s); node z(x.n + y.n); merge(x.pos.begin(), x.pos.end(), y.pos.begin(), y.pos.end(), z.pos.begin()); for (int i = 0; i < z.n; ++i) { for (int j = i; j < z.n; ++j) { int l = z.pos[i], r = z.pos[j]; z.id[i][j] = merge(x.get(l, r), y.get(l, r)); } } return z; } int main() { scanf( %d%d , &n, &q); B = sqrt(q); cnt = n; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); p[a[i]] = i; } for (int i = 1, j = 1; i <= n; i += B, ++j) { sqr[j] = solve(0, min(i + B - 1, n) - i, i); } for (int t = 1; t <= q; ++t) { int l, r; scanf( %d%d , &l, &r); for (int i = 1, j = 1; i <= n; i += B, ++j) { id[t] = merge(id[t], sqr[j].get(l, r)); } } printf( %d n , cnt); for (auto x : opt) { printf( %d %d n , x.first, x.second); } for (int t = 1; t <= q; ++t) { printf( %d%c , id[t], n [t == q]); } return 0; }
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#include <bits/stdc++.h> using namespace std; string s; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int n, p, l = -1, r = 0, i, j, ans = 0; cin >> n >> p; cin >> s; n--, p--; if (p > n / 2) p = n - p; for (i = 0; i <= n / 2; i++) { if (s[i] != s[n - i]) { long long int dif = abs(s[i] - s[n - i]); ans += min(dif, 26 - dif); if (l < 0) l = i; else r = i; } } ans += min(abs(p - l), abs(p - r)); ans += max((r - l), 0LL); cout << (l < 0 ? 0 : ans) << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; const int maxn = 1e6 + 6; int a[maxn]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int pt = 0; if (n & 1) { for (int i = 2; i <= n; i += 2) { a[pt++] = i; } for (int i = n - 1; i >= 2; i -= 2) { a[pt++] = i; } for (int i = 1; i <= n; i += 2) { a[pt++] = i; } for (int i = n - 2; i >= 1; i -= 2) { a[pt++] = i; } a[pt++] = n; } else { for (int i = 1; i <= n; i += 2) { a[pt++] = i; } for (int i = n - 1; i >= 1; i -= 2) { a[pt++] = i; } for (int i = 2; i <= n; i += 2) { a[pt++] = i; } for (int i = n - 2; i >= 2; i -= 2) { a[pt++] = i; } a[pt++] = n; } for (int i = 0; i < pt; i++) { cout << a[i] << ; } cout << n ; }
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#include <bits/stdc++.h> using namespace std; void solve() { long long int n, i, count = 0; vector<long long int> v; string s1, s2, s3, reverses1, reverses2, reverses3; cin >> s1 >> s2 >> s3; reverses1 = s1; reverses2 = s2; reverses3 = s3; reverse(s1.begin(), s1.end()); reverse(s2.begin(), s2.end()); reverse(s3.begin(), s3.end()); if (reverses1 == s3 && reverses2 == s2 && reverses3 == s1) cout << YES << n ; else cout << NO << n ; } void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); } int main() { fast(); int t = 1; while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; long long int a[2005]; long long int cnt[2005]; long long int b[2005]; long long int vis[2005]; vector<long long int> v; vector<long long int> vv; vector<long long int> ans; long long int prime[2005]; bool pr[2005]; set<char> st; priority_queue<long long int> bob; priority_queue<long long int> ali; priority_queue<long long int> bth; queue<long long int> q; map<long long int, long long int> mp; long long int taken[105]; map<long long int, long long int>::iterator it; map<long long int, vector<long long int> > ck; string ss, tt; long long int pos[205]; long long int afs[205]; long long int pre[2005]; long long int aa[2005]; long long int cs[27]; long long int ct[27]; long long int power(long long int k, long long int i) { long long int res = 1; for (long long int j = 1; j <= i; j++) { res = res * k; } return res; } int main() { long long int n, i, j, k, t, m; cin >> t; long long int minis; long long int res; long long int x, y; long long int pp; string fg; long long int l, r; long long int h; long long int p, q; string tt; while (t--) { v.clear(); cin >> n; cin >> ss >> tt; string fg; long long int kk = n; res = 0; for (i = n - 1; i >= 0; i--) { if (ss[i] == tt[i]) { kk--; continue; } else { if (ss[0] == tt[i]) { res = res + 1; v.push_back(1); if (ss[0] == 0 ) ss[0] = 1 ; else ss[0] = 0 ; } fg.clear(); for (j = 0; j <= i; j++) { if (ss[j] == 0 ) fg.push_back( 1 ); else fg.push_back( 0 ); } reverse(fg.begin(), fg.end()); res = res + 1; v.push_back(kk); for (j = 0; j <= i; j++) { ss[j] = fg[j]; } } kk--; } cout << res << ; for (i = 0; i < v.size(); i++) cout << v[i] << ; cout << n ; } return 0; }
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#include <bits/stdc++.h> static int solve(); using ll = long long; int main(int argc, char* argv[]) { int tc = 1; scanf( %d , &tc); while (tc--) solve(); return 0; } static constexpr int MOD = 998244353; static int solve() { int n, x, y; scanf( %d %d %d , &n, &x, &y); int sum = x + y; int min_pos, max_pos; if (sum == n + n) { min_pos = n; max_pos = n; } else if (sum <= n) { min_pos = 1; max_pos = sum - 1; } else { min_pos = sum - n + 1; max_pos = n; } printf( %d %d n , min_pos, max_pos); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { string n; int count = 0; cin >> n; stack<char> s; for (int i = 0; i < n.length(); i++) { if (n[i] == ( ) { s.push(n[i]); } else if (n[i] == ) ) { if (s.size() != 0) { char tops = s.top(); s.pop(); if (tops == ( ) { count += 2; } } } } cout << count << endl; return 0; }
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