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// board has 8 LED segment for display numbers
// print out the current tick which increments
// every number of second based on the clock
// use 4 button switch for reset and toggle of the
// step value. 18 LEDR is used for displaying the
// current step
`define NSEG 8
`define NLEDR 18
module ledhex
(
input wire [3:0] key,
input wire clk,
output reg [`NLEDR-1:0] ledr,
output reg [`NSEG*7-1:0] hex
);
task clear();
integer i;
for (i = 0; i < `NSEG*7; i = i + 1) begin
hex[i] = 1;
end
endtask
task digit(input integer hp, input integer n);
reg [7:0] v;
integer i;
begin
case (n)
0: v = 7'b1000000;
1: v = 7'b1111001;
2: v = 7'b0100100;
3: v = 7'b0110000;
4: v = 7'b0011001;
5: v = 7'b0010010;
6: v = 7'b0000010;
7: v = 7'b1111000;
8: v = 7'b0000000;
9: v = 7'b0010000;
default: v = 7'b1111111;
endcase
hp = hp*7;
for (i = 0; i < 7; i = i + 1) begin
hex[hp+i] = v[i];
end
end
endtask
task print(input integer n);
integer i;
begin
clear();
for (i = 0; i < `NSEG; i = i + 1) begin
digit(i, n % 10);
n = n / 10;
end
end
endtask
parameter CLK_FREQ = 50_000_000;
parameter EV_MAX = CLK_FREQ / 25;
parameter CNT_MAX = CLK_FREQ;
parameter MAX_NUM = 100_000_000;
reg [31:0] cnt, ev, val, step;
integer i;
initial begin
cnt = 0;
ev = 0;
val = 0;
step = 1;
end
always @ (posedge clk) begin
if (cnt >= CNT_MAX) begin
cnt = 0;
val = (val + step) % MAX_NUM;
end
else
cnt = cnt + 1;
if (ev >= EV_MAX) begin
ev = 0;
if (key[0] == 1'b0)
val = 0;
if (key[1] == 1'b0)
step = 1;
if (key[2] == 1'b0)
step = (step + 1) % MAX_NUM;
if (key[3] == 1'b0 && step > 0)
step = step - 1;
end
else
ev = ev + 1;
for (i = 0; i < `NLEDR; i = i + 1)
ledr[i] = (step >> i) & 1;
print(val);
end
endmodule
|
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module or_32(
input [31:0] a, //input values
input [31:0] b,
output [31:0] out //output value
);
//output is the OR of a and b
assign out[0] = a[0] | b[0];
assign out[1] = a[1] | b[1];
assign out[2] = a[2] | b[2];
assign out[3] = a[3] | b[3];
assign out[4] = a[4] | b[4];
assign out[5] = a[5] | b[5];
assign out[6] = a[6] | b[6];
assign out[7] = a[7] | b[7];
assign out[8] = a[8] | b[8];
assign out[9] = a[9] | b[9];
assign out[10] = a[10] | b[10];
assign out[11] = a[11] | b[11];
assign out[12] = a[12] | b[12];
assign out[13] = a[13] | b[13];
assign out[14] = a[14] | b[14];
assign out[15] = a[15] | b[15];
assign out[16] = a[16] | b[16];
assign out[17] = a[17] | b[17];
assign out[18] = a[18] | b[18];
assign out[19] = a[19] | b[19];
assign out[20] = a[20] | b[20];
assign out[21] = a[21] | b[21];
assign out[22] = a[22] | b[22];
assign out[23] = a[23] | b[23];
assign out[24] = a[24] | b[24];
assign out[25] = a[25] | b[25];
assign out[26] = a[26] | b[26];
assign out[27] = a[27] | b[27];
assign out[28] = a[28] | b[28];
assign out[29] = a[29] | b[29];
assign out[30] = a[30] | b[30];
assign out[31] = a[31] | b[31];
endmodule
|
// USED ONLY TO SELECT VC BLOCKED STATUS
// OPTIMISE FOR XY ROUTING
/* autovdoc@
*
* component@ unary_select_pair
* what@ A sort of mux!
* authors@ Robert Mullins
* date@ 5.3.04
* revised@ 5.3.04
* description@
*
* Takes two unary (one-hot) encoded select signals and selects one bit of the input.
*
* Implements the following:
*
* {\tt selectedbit=datain[binary(sela)*WB+binary(selb)]}
*
* pin@ sel_a, WA, in, select signal A (unary encoded)
* pin@ sel_b, WB, in, select signal B (unary encoded)
* pin@ data_in, WA*WB, in, input data
* pin@ selected_bit, 1, out, selected data bit (see above)
*
* param@ WA, >1, width of select signal A
* param@ WB, >1, width of select signal B
*
* autovdoc@
*/
module unary_select_pair (sel_a, sel_b, data_in, selected_bit);
parameter input_port = 0; // from 'input_port' to 'sel_a' output port
parameter WA = 4;
parameter WB = 4;
input [WA-1:0] sel_a;
input [WB-1:0] sel_b;
input [WA*WB-1:0] data_in;
output selected_bit;
genvar i,j;
wire [WA*WB-1:0] selected;
generate
for (i=0; i<WA; i=i+1) begin:ol
for (j=0; j<WB; j=j+1) begin:il
assign selected[i*WB+j] = (NW_route_valid_turn(input_port, i)) ?
data_in[i*WB+j] & sel_a[i] & sel_b[j] : 1'b0;
/*
// i = output_port
// assume XY routing and that data never leaves on port it entered
if ((input_port==i) || (((input_port==`NORTH)||(input_port==`SOUTH)) &&
((i==`EAST)||(i==`WEST)))) begin
assign selected[i*WB+j]=1'b0;
end else begin
assign selected[i*WB+j]=data_in[i*WB+j] & sel_a[i] & sel_b[j];
end
*/
end
end
endgenerate
assign selected_bit=|selected;
endmodule // unary_select_pair
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This bursting write master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post full length bursts until
the length register reaches a value less than a full burst. A single final
burst is then posted when enough data has been buffered and then the done bit
will be asserted.
To use this master you must simply drive the control signals into this block,
and also write the data to the exposed write FIFO. To read from the exposed FIFO
use the 'user_write_buffer' signal to push data into the FIFO 'user_buffer_data'.
The signal 'user_buffer_full' is asserted whenever the exposed buffer is full.
You should not attempt to write data to the exposed FIFO if it is full.
*/
// altera message_off 10230
module burst_write_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_write_base,
control_write_length,
control_go,
control_done,
// user logic inputs and outputs
user_write_buffer,
user_buffer_data,
user_buffer_full,
// master inputs and outputs
master_address,
master_write,
master_byteenable,
master_writedata,
master_burstcount,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32; // must be at least twice MAXBURSTCOUNT in order to be efficient
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location; // this only makes sense to enable when MAXBURSTCOUNT = 1
input [ADDRESSWIDTH-1:0] control_write_base;
input [ADDRESSWIDTH-1:0] control_write_length;
input control_go;
output wire control_done;
// user logic inputs and outputs
input user_write_buffer;
input [DATAWIDTH-1:0] user_buffer_data;
output wire user_buffer_full;
// master inputs and outputs
input master_waitrequest;
output reg [ADDRESSWIDTH-1:0] master_address;
output wire master_write;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [DATAWIDTH-1:0] master_writedata;
output reg [BURSTCOUNTWIDTH-1:0] master_burstcount;
// internal control signals
reg control_fixed_location_d1;
reg [ADDRESSWIDTH-1:0] length;
wire final_short_burst_enable; // when the length is less than MAXBURSTCOUNT * # of bytes per word (BYTEENABLEWIDTH) (i.e. end of the transfer)
wire final_short_burst_ready; // when there is enough data in the FIFO for the final burst
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address; // represents the word offset within the burst boundary
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire first_short_burst_enable; // when the transfer doesn't start on a burst boundary
wire first_short_burst_ready; // when there is enough data in the FIFO to get the master back into burst alignment
wire full_burst_ready; // when there is enough data in the FIFO for a full burst
wire increment_address; // this increments the 'address' register when write is asserted and waitrequest is de-asserted
wire burst_begin; // used to register the registers 'burst_address' and 'burst_count_d1' as well as drive the master_address and burst_count muxes
wire read_fifo;
wire [FIFODEPTH_LOG2-1:0] fifo_used; // going to combined used with the full bit
wire [BURSTCOUNTWIDTH-1:0] burst_count; // watermark of the FIFO, it has a latency of 2 cycles
reg [BURSTCOUNTWIDTH-1:0] burst_counter;
reg first_transfer; // need to keep track of the first burst so that we don't incorrectly increment the address
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// set when control_go fires, and reset once the first burst starts
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
first_transfer <= 0;
end
else
begin
if (control_go == 1)
begin
first_transfer <= 1;
end
else if (burst_begin == 1)
begin
first_transfer <= 0;
end
end
end
// master address (held constant during burst)
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
master_address <= 0;
end
else
begin
if (control_go == 1)
begin
master_address <= control_write_base;
end
else if ((first_transfer == 0) & (burst_begin == 1) & (control_fixed_location_d1 == 0))
begin
master_address <= master_address + (master_burstcount * BYTEENABLEWIDTH); // we don't want address + BYTEENABLEWIDTH for the first access
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if (control_go == 1)
begin
length <= control_write_length;
end
else if (increment_address == 1)
begin
length <= length - BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// register the master burstcount (held constant during burst)
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
master_burstcount <= 0;
end
else
begin
if (burst_begin == 1)
begin
master_burstcount <= burst_count;
end
end
end
// burst counter. This is set to the burst count being posted then counts down when each word
// of data goes out. If it reaches 0 (i.e. not reloaded after 1) then the master stalls due to
// a lack of data to post a new burst.
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
burst_counter <= 0;
end
else
begin
if (control_go == 1)
begin
burst_counter <= 0;
end
else if (burst_begin == 1)
begin
burst_counter <= burst_count;
end
else if (increment_address == 1) // decrements each write, burst_counter will only hit 0 if burst begin doesn't fire on the next cycle
begin
burst_counter <= burst_counter - 1;
end
end
end
// burst boundaries are on the master "width * maximum burst count". The burst boundary word address will be used to determine how far off the boundary the transfer starts from.
assign burst_boundary_word_address = ((master_address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
// first short burst enable will only be active on the first transfer (if applicable). It will either post the amount of words remaining to reach the end of the burst
// boundary or post the remainder of the transfer whichever is shorter. If the transfer is very short and not aligned on a burst boundary then the same logic as the final short transfer is used
assign first_short_burst_enable = (burst_boundary_word_address != 0) & (first_transfer == 1);
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : final_short_burst_count);
assign first_short_burst_ready = (fifo_used > first_short_burst_count) | ((fifo_used == first_short_burst_count) & (burst_counter == 0));
// when there isn't enough data for a full burst at the end of the transfer a short burst is sent out instead
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign final_short_burst_count = (length/BYTEENABLEWIDTH);
assign final_short_burst_ready = (fifo_used > final_short_burst_count) | ((fifo_used == final_short_burst_count) & (burst_counter == 0)); // this will add a one cycle stall between bursts, since fifo_used has a cycle of latency, this only affects the last burst
// since the fifo has a latency of 1 we need to make sure we don't under flow
assign full_burst_ready = (fifo_used > MAXBURSTCOUNT) | ((fifo_used == MAXBURSTCOUNT) & (burst_counter == 0)); // when fifo used watermark equals the burst count the statemachine must stall for one cycle, this will make sure that when a burst begins there really is enough data present in the FIFO
assign master_byteenable = -1; // all ones, always performing word size accesses
assign control_done = (length == 0);
assign master_write = (control_done == 0) & (burst_counter != 0); // burst_counter = 0 means the transfer is done, or not enough data in the fifo for a new burst
// fifo controls and the burst_begin responsible for timing most of the circuit, burst_begin starts the writing statemachine
assign burst_begin = (((first_short_burst_enable == 1) & (first_short_burst_ready == 1))
| ((final_short_burst_enable == 1) & (final_short_burst_ready == 1))
| (full_burst_ready == 1))
& (control_done == 0) // since the FIFO can have data before the master starts we need to disable this bit from firing when length = 0
& ((burst_counter == 0) | ((burst_counter == 1) & (master_waitrequest == 0) & (length > (MAXBURSTCOUNT * BYTEENABLEWIDTH)))); // need to make a short final burst doesn't start right after a full burst completes.
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // alignment correction gets priority, if the transfer is short and unaligned this will cover both
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (master_write == 1) & (master_waitrequest == 0); // writing is occuring without wait states
assign read_fifo = increment_address;
// write data feed by user logic
scfifo the_user_to_master_fifo (
.aclr (reset),
.usedw (fifo_used),
.clock (clk),
.data (user_buffer_data),
.almost_full (user_buffer_full),
.q (master_writedata),
.rdreq (read_fifo),
.wrreq (user_write_buffer)
);
defparam the_user_to_master_fifo.lpm_width = DATAWIDTH;
defparam the_user_to_master_fifo.lpm_numwords = FIFODEPTH;
defparam the_user_to_master_fifo.lpm_showahead = "ON";
defparam the_user_to_master_fifo.almost_full_value = (FIFODEPTH - 2);
defparam the_user_to_master_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_user_to_master_fifo.add_ram_output_register = "OFF"; // makes timing the burst begin single simplier
defparam the_user_to_master_fifo.underflow_checking = "OFF";
defparam the_user_to_master_fifo.overflow_checking = "OFF";
endmodule
|
//
// Copyright 2015 Ettus Research LLC
//
module noc_block_addsub #(
parameter NOC_ID = 64'hADD0_0000_0000_0000,
parameter STR_SINK_FIFOSIZE = 11) // Use VHDL version of AddSub module
(
input bus_clk, input bus_rst,
input ce_clk, input ce_rst,
input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
output [63:0] debug
);
localparam MTU = 10;
/////////////////////////////////////////////////////////////
//
// RFNoC Shell
//
////////////////////////////////////////////////////////////
wire [63:0] cmdout_tdata, ackin_tdata;
wire cmdout_tlast, cmdout_tvalid, cmdout_tready, ackin_tlast, ackin_tvalid, ackin_tready;
wire [127:0] str_sink_tdata, str_src_tdata;
wire [1:0] str_sink_tlast, str_sink_tvalid, str_sink_tready, str_src_tlast, str_src_tvalid, str_src_tready;
wire [31:0] in_tdata[0:1];
wire [127:0] in_tuser[0:1];
wire [1:0] in_tlast, in_tvalid, in_tready;
wire [31:0] out_tdata[0:1];
wire [127:0] out_tuser[0:1], out_tuser_pre[0:1];
wire [1:0] out_tlast, out_tvalid, out_tready;
wire [1:0] clear_tx_seqnum;
wire [15:0] src_sid[0:1], next_dst_sid[0:1];
noc_shell #(
.NOC_ID(NOC_ID),
.STR_SINK_FIFOSIZE({2{STR_SINK_FIFOSIZE[7:0]}}),
.INPUT_PORTS(2),
.OUTPUT_PORTS(2))
noc_shell (
.bus_clk(bus_clk), .bus_rst(bus_rst),
.i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
.o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
// Compute Engine Clock Domain
.clk(ce_clk), .reset(ce_rst),
// Control Sink
.set_data(), .set_addr(), .set_stb(),
.rb_stb(2'b11), .rb_data(128'd0), .rb_addr(),
// Control Source
.cmdout_tdata(cmdout_tdata), .cmdout_tlast(cmdout_tlast), .cmdout_tvalid(cmdout_tvalid), .cmdout_tready(cmdout_tready),
.ackin_tdata(ackin_tdata), .ackin_tlast(ackin_tlast), .ackin_tvalid(ackin_tvalid), .ackin_tready(ackin_tready),
// Stream Sink
.str_sink_tdata(str_sink_tdata), .str_sink_tlast(str_sink_tlast), .str_sink_tvalid(str_sink_tvalid), .str_sink_tready(str_sink_tready),
// Stream Source
.str_src_tdata(str_src_tdata), .str_src_tlast(str_src_tlast), .str_src_tvalid(str_src_tvalid), .str_src_tready(str_src_tready),
.clear_tx_seqnum(clear_tx_seqnum), .src_sid({src_sid[1],src_sid[0]}), .next_dst_sid({next_dst_sid[1],next_dst_sid[0]}),
.resp_in_dst_sid(/* Unused */), .resp_out_dst_sid(/* Unused */),
.debug(debug));
genvar i;
generate
for (i=0; i<2; i=i+1)
chdr_deframer deframer (
.clk(ce_clk), .reset(ce_rst), .clear(1'b0),
.i_tdata(str_sink_tdata[i*64+63:i*64]), .i_tlast(str_sink_tlast[i]), .i_tvalid(str_sink_tvalid[i]), .i_tready(str_sink_tready[i]),
.o_tdata(in_tdata[i]), .o_tuser(in_tuser[i]), .o_tlast(in_tlast[i]), .o_tvalid(in_tvalid[i]), .o_tready(in_tready[i]));
endgenerate
addsub inst_addsub_hls (
.ap_clk(ce_clk), .ap_rst_n(~ce_rst),
.a_TDATA(in_tdata[0]), .a_TVALID(in_tvalid[0]), .a_TREADY(in_tready[0]), .a_TLAST(in_tlast[0]),
.b_TDATA(in_tdata[1]), .b_TVALID(in_tvalid[1]), .b_TREADY(in_tready[1]), .b_TLAST(in_tlast[1]),
.add_TDATA(out_tdata[0]), .add_TVALID(out_tvalid[0]), .add_TREADY(out_tready[0]), .add_TLAST(out_tlast[0]),
.sub_TDATA(out_tdata[1]), .sub_TVALID(out_tvalid[1]), .sub_TREADY(out_tready[1]), .sub_TLAST(out_tlast[1]));
split_stream_fifo #(
.WIDTH(128), .ACTIVE_MASK(4'b0011))
tuser_splitter (
.clk(ce_clk), .reset(ce_rst), .clear(1'b0),
.i_tdata(in_tuser[0]), .i_tlast(1'b0), .i_tvalid(in_tvalid[0] & in_tlast[0]), .i_tready(),
.o0_tdata(out_tuser_pre[0]), .o0_tlast(), .o0_tvalid(), .o0_tready(out_tlast[0] & out_tready[0]),
.o1_tdata(out_tuser_pre[1]), .o1_tlast(), .o1_tvalid(), .o1_tready(out_tlast[1] & out_tready[1]),
.o2_tready(1'b1), .o3_tready(1'b1));
assign out_tuser[0] = { out_tuser_pre[0][127:96], src_sid[0], next_dst_sid[0], out_tuser_pre[0][63:0] };
assign out_tuser[1] = { out_tuser_pre[1][127:96], src_sid[1], next_dst_sid[1], out_tuser_pre[1][63:0] };
genvar j;
generate
for (j=0; j<2; j=j+1)
chdr_framer #(
.SIZE(MTU))
framer (
.clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[j]),
.i_tdata(out_tdata[j]), .i_tuser(out_tuser[j]), .i_tlast(out_tlast[j]), .i_tvalid(out_tvalid[j]), .i_tready(out_tready[j]),
.o_tdata(str_src_tdata[j*64+63:j*64]), .o_tlast(str_src_tlast[j]), .o_tvalid(str_src_tvalid[j]), .o_tready(str_src_tready[j]));
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
function integer get_baz(input integer bar);
get_baz = bar;
$fatal(2, "boom");
endfunction
module foo #(parameter BAR = 0);
localparam integer BAZ = get_baz(BAR);
endmodule
module foo2 #(parameter QUX = 0);
genvar x;
generate
for (x = 0; x < 2; x++) begin: foo2_loop
foo #(.BAR (QUX + x)) foo_in_foo2_inst();
end
endgenerate
endmodule
module t;
genvar i, j;
generate
for (i = 0; i < 2; i++) begin: genloop
foo #(.BAR (i)) foo_inst();
end
for (i = 2; i < 4; i++) begin: gen_l1
for (j = 0; j < 2; j++) begin: gen_l2
foo #(.BAR (i + j*2)) foo_inst2();
end
end
if (1 == 1) begin: cond_true
foo #(.BAR (6)) foo_inst3();
end
if (1 == 1) begin // unnamed
foo #(.BAR (7)) foo_inst4();
end
for (i = 8; i < 12; i = i + 2) begin: nested_loop
foo2 #(.QUX (i)) foo2_inst();
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e5; int ans[N], all, u, v, n, m, num, color[N], cnt[2]; vector<int> adj[N], radj[N]; bool used[N]; void output() { printf( YES n ); for (int i = 0; i < n; ++i) printf( %d%c , ans[i] + 1, n [i == n - 1]); exit(0); } void dfs(int v, int c) { color[v] = c, cnt[c]++; for (int j = 0; j < ((int)(adj[v]).size()); ++j) if (color[adj[v][j]] == -1) dfs(adj[v][j], c ^ 1); } void truecolor() { int deg = 0; for (int t = 0; t < 2; ++t) { for (int i = 0; i < n; ++i) if (color[i] == t) { ans[i] = num; ++deg; if (deg == 3) { ++num; deg = 0; } } } } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; ++i) scanf( %d%d , &u, &v), --u, --v, adj[u].push_back(v), adj[v].push_back(u); memset(color, -1, sizeof(color)); for (int i = 0; i < n; ++i) if (color[i] == -1) dfs(i, 0); if (cnt[0] % 3 > cnt[1] % 3) { for (int i = 0; i < n; ++i) color[i] ^= 1; swap(cnt[0], cnt[1]); } all = 0; for (int i = 0; i < n; ++i) if (color[i] == 1) all ^= i; num = 0; if (cnt[0] % 3 == 0) { truecolor(); output(); } for (int i = 0; i < n; ++i) if (color[i] == 0) if (((int)(adj[i]).size()) <= cnt[1] - 2) { ans[i] = 0, color[i] = 2; for (int j = 0; j < ((int)(adj[i]).size()); ++j) used[adj[i][j]] = true; int deg = 2; for (int j = 0; deg && (j < n); ++j) if ((color[j] == 1) && !used[j]) { color[j] = 2; ans[j] = 0; --deg; } ++num; truecolor(); output(); } else if (((int)(adj[i]).size()) == cnt[1] - 1) { int x = all; for (int j = 0; j < ((int)(adj[i]).size()); ++j) x ^= adj[i][j]; radj[x].push_back(i); } int res = 0; for (int i = 0; i < n; ++i) if (((int)(radj[i]).size()) >= 2) res++; if (res <= 1) { printf( NO n ); return 0; } res = 2; for (int i = 0; res && (i < n); ++i) if (((int)(radj[i]).size()) >= 2) { ans[i] = num, color[i] = 2; for (int j = 0; j < 2; ++j) ans[radj[i][j]] = num, color[radj[i][j]] = 2; --res; ++num; } truecolor(); output(); return 0; }
|
#include <bits/stdc++.h> const int N = (int)1e3 + 5; int n; int a[N]; int b[N]; int u[N]; int gcd(int a, int b) { return !b ? a : gcd(b, a % b); } int main() { int ts; scanf( %d , &ts); while (ts--) { for (int i = 0; i < N; ++i) { u[i] = 0; } scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); } int g = 0; for (int p = 1; p <= n; ++p) { int mx = -1; int ind = -1; for (int i = 0; i < n; ++i) { if (!u[i]) { if (mx < gcd(g, a[i])) { mx = gcd(g, a[i]); ind = i; } } } assert(ind != -1); u[ind] = 1; g = gcd(g, a[ind]); b[p] = a[ind]; } for (int i = 1; i <= n; ++i) { printf( %d , b[i]); } printf( n ); } }
|
/**
* Generates the current game screen contents.
*/
module game_engine (
RESET,
SYSTEM_CLOCK,
VGA_CLOCK,
PADDLE_A_POSITION,
PADDLE_B_POSITION,
PIXEL_H,
PIXEL_V,
BALL_H,
BALL_V,
PIXEL
);
input RESET;
input SYSTEM_CLOCK;
input VGA_CLOCK;
input [7:0] PADDLE_A_POSITION;
input [7:0] PADDLE_B_POSITION;
input [10:0] PIXEL_H;
input [10:0] PIXEL_V;
output [10:0] BALL_H;
output [10:0] BALL_V;
output [2:0] PIXEL; // 1 red, 1 green, 1 blue
reg [2:0] pixel;
reg [10:0] paddle_a_pos;
reg [10:0] paddle_b_pos;
reg [10:0] ball_h;
reg [10:0] ball_v;
wire [10:0] ball_h_wire;
wire [10:0] ball_v_wire;
wire border = (PIXEL_V <= 4 || PIXEL_V >= 474 || PIXEL_H <= 4 || PIXEL_H >= 774);
wire net = (PIXEL_V[4] == 1 && (PIXEL_H == 389 || PIXEL_H == 390));
wire paddle_a = (PIXEL_H >= 10 && PIXEL_H <= 20 && PIXEL_V >= paddle_a_pos && PIXEL_V <= (paddle_a_pos + 75));
wire paddle_b = (PIXEL_H >= 760 && PIXEL_H <= 770 && PIXEL_V >= paddle_b_pos && PIXEL_V <= (paddle_b_pos + 75));
wire ball = PIXEL_H >= ball_h && PIXEL_H <= (ball_h + 16) && PIXEL_V >= ball_v && PIXEL_V <= (ball_v + 16);
wire [2:0] score_rgb;
reg [7:0] score_player_one;
reg [7:0] score_player_two;
score score_1(
.clk(SYSTEM_CLOCK),
.PIXEL_H(PIXEL_H),
.PIXEL_V(PIXEL_V),
.PLAYER_ONE(score_player_one),
.PLAYER_TWO(score_player_two),
.PIXEL(score_rgb)
);
always @ (posedge VGA_CLOCK) begin
// Max incomming postion is 255
// so double to get to 510 which is a bit bigger than wanted.
paddle_a_pos <= PADDLE_A_POSITION << 1;
paddle_b_pos <= PADDLE_B_POSITION << 1;
end
// Ball
reg [16:0] ball_timer;
reg [27:0] ball_timer_delay;
reg ball_h_direction;
reg ball_v_direction;
always @ (posedge VGA_CLOCK or posedge RESET) begin
if (RESET) begin
ball_h <= 382;
ball_v <= 200;
ball_h_direction <= 0;
ball_v_direction <= 0;
ball_timer <= 0;
ball_timer_delay <= 28'd67108863;
score_player_one <= 0;
score_player_two <= 0;
end else begin
if (ball_timer_delay > 0) begin
ball_timer_delay <= ball_timer_delay -1;
end
else begin
ball_timer <= ball_timer + 1;
end
// Only move the ball when timer says so.
if (ball_timer == 17'd91071) begin
ball_timer <= 0;
// Move the ball
if (ball_h_direction) begin
ball_h <= ball_h + 1;
// Paddle B detection (right side)
if (ball_h > 755) begin
if (ball_v >= paddle_b_pos && ball_v < (paddle_b_pos + 75)) begin
// Hit the paddle
ball_h_direction <= 0;
end
else begin
// Missed the paddle - new serve
ball_h <= 382;
ball_h_direction <= 1;
ball_timer_delay <= 28'd67108863;
score_player_one <= score_player_one + 1'd1;
end
end
end
else begin
ball_h <= ball_h - 1;
// Paddle A detection (left side)
if (ball_h < 20) begin
if (ball_v >= paddle_a_pos && ball_v < (paddle_a_pos + 75)) begin
// Hit the paddle
ball_h_direction <= 1;
end
else begin
// Missed the paddle - new serve
ball_h <= 382;
ball_h_direction <= 0;
ball_timer_delay <= 28'd67108863;
score_player_two <= score_player_two + 1'd1;
end
end
end
if (ball_v_direction) begin
ball_v <= ball_v + 1;
// Bottom border collision
if (ball_v > 470) ball_v_direction <= 0;
end
else begin
ball_v <= ball_v - 1;
// Top border collision
if (ball_v < 4) ball_v_direction <= 1;
end
end
end
end
// Draw the pixel for the requested vga location.
always @ (posedge VGA_CLOCK) begin
if (paddle_a) begin
pixel <= 3'b111; // white paddle
end
else if (paddle_b) begin
pixel <= 3'b111; // white paddle
end
else if (border) begin
pixel <= 3'b100; // red border
end
else if (ball && ball_timer_delay == 0) begin
pixel <= 3'b001; // blue ball
end
else if (score_rgb) begin
pixel <= score_rgb;
end
else if (net) begin
pixel <= 3'b110; // yellow net
end
else begin
pixel <= 3'b000; // black
end
end
assign PIXEL = pixel;
assign BALL_H = ball_h;
assign BALL_V = ball_v;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int main() { ios::sync_with_stdio(false); int n; while (cin >> n) { int a, b, c, d, sum = 0, i = 0, mx = -1, my = -1, mix = N, miy = N; for (i = 0; i < n; i++) { cin >> a >> b >> c >> d; sum += abs(a - c) * abs(d - b); mx = max(mx, max(a, c)); my = max(my, max(d, b)); mix = min(mix, min(a, c)); miy = min(miy, min(d, b)); } if (((mx - mix) != (my - miy)) || (mx - mix) * (my - miy) != sum) cout << NO << endl; else cout << YES << endl; } return 0; }
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import PrimInt63 FloatClass.
(** * Definition of the interface for primitive floating-point arithmetic
This interface provides processor operators for the Binary64 format of the
IEEE standard. *)
(** ** Type definition for the co-domain of [compare] *)
Variant float_comparison : Set := FEq | FLt | FGt | FNotComparable.
Register float_comparison as kernel.ind_f_cmp.
Register float_class as kernel.ind_f_class.
(** ** The main type *)
(** [float]: primitive type for Binary64 floating-point numbers. *)
Primitive float := #float64_type.
(** ** Syntax support *)
Module Import PrimFloatNotationsInternalA.
Declare Scope float_scope.
Delimit Scope float_scope with float.
Bind Scope float_scope with float.
End PrimFloatNotationsInternalA.
Declare ML Module "float_syntax_plugin".
(** ** Floating-point operators *)
Primitive classify := #float64_classify.
Primitive abs := #float64_abs.
Primitive sqrt := #float64_sqrt.
Primitive opp := #float64_opp.
Primitive eqb := #float64_eq.
Primitive ltb := #float64_lt.
Primitive leb := #float64_le.
Primitive compare := #float64_compare.
Primitive mul := #float64_mul.
Primitive add := #float64_add.
Primitive sub := #float64_sub.
Primitive div := #float64_div.
Module Import PrimFloatNotationsInternalB.
Notation "- x" := (opp x) : float_scope.
Notation "x =? y" := (eqb x y) (at level 70, no associativity) : float_scope.
Notation "x <? y" := (ltb x y) (at level 70, no associativity) : float_scope.
Notation "x <=? y" := (leb x y) (at level 70, no associativity) : float_scope.
Notation "x ?= y" := (compare x y) (at level 70, no associativity) : float_scope.
Notation "x * y" := (mul x y) : float_scope.
Notation "x + y" := (add x y) : float_scope.
Notation "x - y" := (sub x y) : float_scope.
Notation "x / y" := (div x y) : float_scope.
End PrimFloatNotationsInternalB.
(** ** Conversions *)
(** [of_int63]: convert a primitive integer into a float value.
The value is rounded if need be. *)
Primitive of_int63 := #float64_of_int63.
(** Specification of [normfr_mantissa]:
- If the input is a float value with an absolute value inside $[0.5, 1.)$#[0.5, 1.)#;
- Then return its mantissa as a primitive integer.
The mantissa will be a 53-bit integer with its most significant bit set to 1;
- Else return zero.
The sign bit is always ignored. *)
Primitive normfr_mantissa := #float64_normfr_mantissa.
(** ** Exponent manipulation functions *)
(** [frshiftexp]: convert a float to fractional part in $[0.5, 1.)$#[0.5, 1.)#
and integer part. *)
Primitive frshiftexp := #float64_frshiftexp.
(** [ldshiftexp]: multiply a float by an integral power of 2. *)
Primitive ldshiftexp := #float64_ldshiftexp.
(** ** Predecesor/Successor functions *)
(** [next_up]: return the next float towards positive infinity. *)
Primitive next_up := #float64_next_up.
(** [next_down]: return the next float towards negative infinity. *)
Primitive next_down := #float64_next_down.
(** ** Special values (needed for pretty-printing) *)
Definition infinity := Eval compute in div (of_int63 1) (of_int63 0).
Definition neg_infinity := Eval compute in opp infinity.
Definition nan := Eval compute in div (of_int63 0) (of_int63 0).
Register infinity as num.float.infinity.
Register neg_infinity as num.float.neg_infinity.
Register nan as num.float.nan.
(** ** Other special values *)
Definition one := Eval compute in (of_int63 1).
Definition zero := Eval compute in (of_int63 0).
Definition neg_zero := Eval compute in (-zero)%float.
Definition two := Eval compute in (of_int63 2).
(** ** Predicates and helper functions *)
Definition is_nan f := negb (f =? f)%float.
Definition is_zero f := (f =? zero)%float. (* note: 0 =? -0 with floats *)
Definition is_infinity f := (abs f =? infinity)%float.
Definition is_finite (x : float) := negb (is_nan x || is_infinity x).
(** [get_sign]: return [true] for [-] sign, [false] for [+] sign. *)
Definition get_sign f :=
let f := if is_zero f then (one / f)%float else f in
(f <? zero)%float.
Module Export PrimFloatNotations.
Local Open Scope float_scope.
#[deprecated(since="8.13",note="use infix <? instead")]
Notation "x < y" := (x <? y) (at level 70, no associativity) : float_scope.
#[deprecated(since="8.13",note="use infix <=? instead")]
Notation "x <= y" := (x <=? y) (at level 70, no associativity) : float_scope.
#[deprecated(since="8.13",note="use infix =? instead")]
Notation "x == y" := (x =? y) (at level 70, no associativity) : float_scope.
Export PrimFloatNotationsInternalA.
Export PrimFloatNotationsInternalB.
End PrimFloatNotations.
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); set<string> s; s.insert( don t even ); s.insert( worse ); s.insert( terrible ); s.insert( no way ); s.insert( go die in a hole ); s.insert( are you serious ); int c = 0; while (true) { cout << c++ << endl; string t; getline(cin, t); if (t != no ) { if (s.count(t) == 0) { cout << normal << endl; return 0; } else { cout << grumpy << endl; return 0; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; char cmd[(100000 + 10)]; int vis[510][510], path[(100000 + 10)]; const int dx[] = {0, 0, 1, -1}, dy[] = {1, -1, 0, 0}; int convert(char ch) { if (ch == R ) return 0; else if (ch == L ) return 1; else if (ch == D ) return 2; else return 3; } bool Inborder(int x, int y) { if (x < 0 || x >= n || y < 0 || y >= m) return false; return true; } int main() { int x0, y0; scanf( %d%d%d%d , &n, &m, &x0, &y0); scanf( %s , cmd); memset(vis, 0, sizeof(vis)); int cnt = 0, pos = 0, len = strlen(cmd), ans = n * m; path[cnt++] = 1; ans--; int x = x0 - 1, y = y0 - 1; vis[x][y] = 1; while (pos < len - 1) { int dir = convert(cmd[pos++]); if (!Inborder(dx[dir] + x, dy[dir] + y)) { path[cnt++] = 0; continue; } x += dx[dir]; y += dy[dir]; if (vis[x][y]) { path[cnt++] = 0; } else { ans--; path[cnt++] = 1; vis[x][y] = 1; } } for (int i = 0; i < cnt; i++) { printf( %d , path[i]); } printf( %d n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBN_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DLXBN_BEHAVIORAL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
not not0 (GATE , GATE_N_delayed );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBN_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NAND3_PP_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int a[105][105], u[105], v[105]; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &a[i][j]); for (int j = 0; j < m; j++) { int cnt[105] = {}; for (int i = 0; i < n; i++) if (!u[i]) ++cnt[a[i][j]]; for (int i = 0; i < n; i++) if (!u[i] && a[i][j]) { if (v[a[i][j]]) u[i] = j + 1; else if (cnt[a[i][j]] >= 2) u[i] = v[a[i][j]] = j + 1; } } for (int i = 0; i < n; i++) printf( %d n , u[i]); }
|
module basic_checker
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(cache_pkt_width_lp)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter `BSG_INV_PARAM(mem_size_p)
)
(
input clk_i
, input reset_i
, input en_i
, input [cache_pkt_width_lp-1:0] cache_pkt_i
, input ready_o
, input v_i
, input [id_width_p-1:0] id_o
, input [data_width_p-1:0] data_o
, input v_o
, input yumi_i
);
`declare_bsg_cache_non_blocking_pkt_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
// shadow mem
logic [data_width_p-1:0] shadow_mem [mem_size_p-1:0];
logic [data_width_p-1:0] result [*];
wire [addr_width_p-1:0] cache_pkt_word_addr = cache_pkt.addr[addr_width_p-1:2];
// store logic
logic [data_width_p-1:0] store_data;
logic [data_mask_width_lp-1:0] store_mask;
always_comb begin
case (cache_pkt.opcode)
SW: begin
store_data = cache_pkt.data;
store_mask = 4'b1111;
end
SH: begin
store_data = {2{cache_pkt.data[15:0]}};
store_mask = {
{2{ cache_pkt.addr[1]}},
{2{~cache_pkt.addr[1]}}
};
end
SB: begin
store_data = {4{cache_pkt.data[7:0]}};
store_mask = {
cache_pkt.addr[1] & cache_pkt.addr[0],
cache_pkt.addr[1] & ~cache_pkt.addr[0],
~cache_pkt.addr[1] & cache_pkt.addr[0],
~cache_pkt.addr[1] & ~cache_pkt.addr[0]
};
end
SM: begin
store_data = cache_pkt.data;
store_mask = cache_pkt.mask;
end
default: begin
store_data = '0;
store_mask = '0;
end
endcase
end
// load logic
logic [data_width_p-1:0] load_data, load_data_final;
logic [7:0] byte_sel;
logic [15:0] half_sel;
assign load_data = shadow_mem[cache_pkt_word_addr];
bsg_mux #(
.els_p(4)
,.width_p(8)
) byte_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[1:0])
,.data_o(byte_sel)
);
bsg_mux #(
.els_p(2)
,.width_p(16)
) half_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[1])
,.data_o(half_sel)
);
always_comb begin
case (cache_pkt.opcode)
LW: load_data_final = load_data;
LH: load_data_final = {{16{half_sel[15]}}, half_sel};
LB: load_data_final = {{24{byte_sel[7]}}, byte_sel};
LHU: load_data_final = {{16{1'b0}}, half_sel};
LBU: load_data_final = {{24{1'b0}}, byte_sel};
default: load_data_final = '0;
endcase
end
always_ff @ (posedge clk_i) begin
if (reset_i) begin
for (integer i = 0; i < mem_size_p; i++)
shadow_mem[i] <= '0;
end
else begin
if (en_i) begin
if (v_i & ready_o) begin
case (cache_pkt.opcode)
TAGST: begin
result[cache_pkt.id] = '0;
end
ALOCK, AUNLOCK: begin
result[cache_pkt.id] = '0;
end
TAGFL, AFL, AFLINV: begin
result[cache_pkt.id] = '0;
end
SB, SH, SW, SM: begin
result[cache_pkt.id] = '0;
for (integer i = 0; i < data_mask_width_lp; i++)
if (store_mask[i])
shadow_mem[cache_pkt_word_addr][8*i+:8] <= store_data[8*i+:8];
end
LW, LH, LB, LHU, LBU: begin
result[cache_pkt.id] = load_data_final;
end
endcase
end
end
end
if (~reset_i & v_o & yumi_i & en_i) begin
$display("id=%d, data=%x", id_o, data_o);
assert(result[id_o] == data_o)
else $fatal("[BSG_FATAL] Output does not match expected result. Id= %d, Expected: %x. Actual: %x",
id_o, result[id_o], data_o);
end
end
endmodule
`BSG_ABSTRACT_MODULE(basic_checker)
|
module main;
parameter NIBBLE = 4;
reg [NIBBLE*4-1:0] array [1:0];
reg [3:0] word;
integer idx;
initial begin
for (idx = 0 ; idx < 4 ; idx = idx+1) begin
array[0][idx*NIBBLE +: 4] = +idx;
array[1][idx*NIBBLE +: 4] = -idx;
end
if (array[0] !== 16'h3210) begin
$display("FAILED -- array[0] = %h", array[0]);
$finish;
end
word = array[0][7:4];
if (word !== 4'h1) begin
$display("FAILED == array[0][7:4] = %h", word);
$finish;
end
word = array[1][7:4];
if (word !== 4'hf) begin
$display("FAILED == array[0][7:4] = %h", word);
$finish;
end
for (idx = 0 ; idx < 4 ; idx = idx+1) begin
word = array[0][idx*NIBBLE +: 4];
if (word !== idx) begin
$display("FAILED == array[0][nibble=%d] = %h", idx, word);
$finish;
end
word = array[1][idx*NIBBLE +: 4];
if (word !== - idx[3:0]) begin
$display("FAILED == array[1][nibble=%d] = %h", idx, word);
$finish;
end
end // for (idx = 0 ; idx < 4 ; idx += 1)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int m = 0, b = 0; int main() { int n; cin >> n; int Arrpi[n]; for (int j = 0; j < n; ++j) { cin >> Arrpi[j]; } int A[n]; for (int l = 0; l < n; ++l) { m = Arrpi[l] - 1; b = l + 1; A[m] = b; } for (int y = 0; y < n; ++y) { cout << A[y] << ; } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_jp_sstl_bscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_jp_sstl_bscan(in ,update_dr ,mode_ctl ,shift_dr ,clock_dr ,
bsr_so ,out ,bsr_si );
output bsr_so ;
output out ;
input in ;
input update_dr ;
input mode_ctl ;
input shift_dr ;
input clock_dr ;
input bsr_si ;
wire net033 ;
wire net035 ;
wire net042 ;
wire update_q ;
bw_u1_muxi21_2x bs_mux (
.z (net033 ),
.d0 (in ),
.d1 (update_q ),
.s (net042 ) );
bw_u1_inv_2x ctl_inv2x (
.z (net042 ),
.a (net035 ) );
bw_io_jp_bs_baseblk bs_baseblk (
.upd_q (update_q ),
.bsr_si (bsr_si ),
.update_dr (update_dr ),
.clock_dr (clock_dr ),
.shift_dr (shift_dr ),
.bsr_so (bsr_so ),
.in (in ) );
bw_u1_inv_1x ctl_inv1x (
.z (net035 ),
.a (mode_ctl ) );
bw_u1_inv_5x out_inv5x (
.z (out ),
.a (net033 ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; string T[20]; bool comp[40][1 << 20]; int res[40][1 << 20]; int pts(char c, int d) { if (c == a ) return 1 * (1 - 2 * (d % 2)); if (c == b ) return -1 * (1 - 2 * (d % 2)); return 0; } int go(int d, int bitmask) { if (bitmask == 0) { return -100; } if (comp[d][bitmask]) return res[d][bitmask]; comp[d][bitmask] = true; if (d == 2 * n - 2) { res[d][bitmask] = 0; } else if (d + 1 < n) { int best = 100; for (char x = a ; x <= z ; x++) { int nbitmask = 0; for (int j = 0; j <= d + 1; j++) { if (T[j][d + 1 - j] != x) continue; if ((1 << j) & bitmask) nbitmask |= (1 << j); if ((j != 0) && ((1 << (j - 1)) & bitmask)) nbitmask |= (1 << j); } best = min(best, pts(x, d) - go(d + 1, nbitmask)); } res[d][bitmask] = best; } else { int best = 100; for (char x = a ; x <= z ; x++) { int nbitmask = 0; for (int j = 0; j < 2 * n - 2 - d; j++) { if (T[2 - n + d + j][n - 1 - j] != x) continue; if ((1 << j) & bitmask) nbitmask |= (1 << j); if (((1 << (j + 1)) & bitmask)) nbitmask |= (1 << j); } best = min(best, pts(x, d) - go(d + 1, nbitmask)); } res[d][bitmask] = best; } return res[d][bitmask]; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> T[i]; int x = pts(T[0][0], 0) + go(0, 1); if (x > 0) { printf( FIRST n ); } else if (x == 0) { printf( DRAW n ); } else { printf( SECOND n ); } }
|
#include <bits/stdc++.h> using namespace std; vector<int> lk; void make(int num, int len) { if (len == 10) return; if (num != 0) lk.push_back(num); make(num * 10 + 4, len + 1); make(num * 10 + 7, len + 1); } double gao(int l1, int l2, int r1, int r2) { double l = max(l1, r1), r = min(l2, r2); return max(0.0, r - l + 1); } int main() { make(0, 0); sort(lk.begin(), lk.end()); int p1, p2, v1, v2, k; while (cin >> p1 >> p2 >> v1 >> v2 >> k) { int c1 = max(p1, v1), c2 = min(c2, v2); double tot = (p2 - p1 + 1.0) * (v2 - v1 + 1.0), sum = 0; int sz = lk.size(); for (int i = 0; i + k - 1 < sz; i++) { int l1, l2 = lk[i], r1 = lk[i + k - 1], r2; if (i == 0) l1 = 0; else l1 = lk[i - 1] + 1; if (i + k == sz) r2 = 1000000000; else r2 = lk[i + k] - 1; sum += gao(l1, l2, p1, p2) * gao(r1, r2, v1, v2); sum += gao(l1, l2, v1, v2) * gao(r1, r2, p1, p2); sum -= gao(c1, c2, max(l1, r1), min(l2, r2)); } printf( %.12f n , sum / tot); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> d; int countDivisors(int n) { if (d[n] != 0) return d[n]; int res = 0; for (int i = 1; i * i <= n; i++) { if (n % i == 0) { if (n / i == i) res++; else res += 2; } } d[n] = res; return res; } void solve() { int a, b, c; cin >> a >> b >> c; d = vector<int>(a * b * c + 1, 0); int ans = 0; for (auto i = (1); i < (a + 1); i++) for (auto j = (1); j < (b + 1); j++) for (auto k = (1); k < (c + 1); k++) ans += countDivisors(i * j * k); cout << ans % 1073741824 << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) solve(); return 0; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_PP_BLACKBOX_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s18 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { map<string, string> hh; map<string, string>::iterator it; int n; string a, b, c; cin >> n; while (n--) { cin >> a >> b; it = hh.find(a); if (it == hh.end()) hh[b] = a; else { c = it->second; hh.erase(it); hh[b] = c; } } cout << hh.size() << endl; for (it = hh.begin(); it != hh.end(); it++) cout << it->second << << it->first << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = (1ll << 32); const int LOGN = 14; const long long INF = (1ll << 62); long long __gcd(long long a, long long b) { if (b == 0) return a; return __gcd(b, a % b); } bool comp(pair<int, unordered_set<int> >& a, pair<int, unordered_set<int> >& b) { return a.second.size() > b.second.size(); } int main() { std ::ios_base ::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); int n, m; cin >> n >> m; vector<pair<int, unordered_set<int> > > a(n); int sz; int ct = 0; int ct_p1 = 0; for (int i = 0; i < n; ++i) { cin >> sz; ct += sz; a[i].first = i; int x; for (int j = 0; j < sz; ++j) { cin >> x; a[i].second.insert(x); } } ct_p1 = ct % n; ct /= n; sort(a.begin(), a.end(), comp); int l = 0; int r = n - 1; vector<vector<int> > ans; while (l < r) { int req_l_size = ct; int req_r_size = ct; if (l < ct_p1) req_l_size++; if (r < ct_p1) req_r_size++; vector<int> temp; for (auto it : a[l].second) { if ((int)a[l].second.size() - (int)temp.size() == req_l_size) break; if (a[r].second.size() == req_r_size) break; if (a[r].second.find(it) == a[r].second.end()) { temp.push_back(it); a[r].second.insert(it); vector<int> x; x.push_back(a[l].first); x.push_back(a[r].first); x.push_back(it); ans.push_back(x); } } for (int i = 0; i < temp.size(); ++i) a[l].second.erase(temp[i]); if (a[r].second.size() == req_r_size) r--; if (a[l].second.size() == req_l_size) l++; } cout << ans.size() << endl; for (int i = 0; i < ans.size(); ++i) cout << ans[i][0] + 1 << << ans[i][1] + 1 << << ans[i][2] << endl; return 0; }
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire exception_139931275014224;
wire exception_139931284058264;
wire exception_139931275014800;
wire exception_139931283364248;
wire exception_139931277768032;
wire exception_139931277612960;
wire exception_139931282859432;
wire exception_139931283977280;
wire exception_139931280790448;
wire exception_139931278706448;
wire exception_139931285244168;
wire exception_139931283531752;
wire exception_139931284930360;
wire exception_139931278105848;
wire exception_139931283236408;
wire exception_139931278705368;
main_0 main_0_139931275014224(
.clk(clk),
.rst(rst),
.exception(exception_139931275014224),
.input_i2c_in(input_i2c),
.input_i2c_in_stb(input_i2c_stb),
.input_i2c_in_ack(input_i2c_ack),
.output_rs232_tx(output_rs232_tx),
.output_rs232_tx_stb(output_rs232_tx_stb),
.output_rs232_tx_ack(output_rs232_tx_ack),
.output_i2c_out(output_i2c),
.output_i2c_out_stb(output_i2c_stb),
.output_i2c_out_ack(output_i2c_ack));
main_1 main_1_139931284058264(
.clk(clk),
.rst(rst),
.exception(exception_139931284058264),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_139931275014800(
.clk(clk),
.rst(rst),
.exception(exception_139931275014800),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_3 main_3_139931283364248(
.clk(clk),
.rst(rst),
.exception(exception_139931283364248),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_4 main_4_139931277768032(
.clk(clk),
.rst(rst),
.exception(exception_139931277768032),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_5 main_5_139931277612960(
.clk(clk),
.rst(rst),
.exception(exception_139931277612960),
.input_in(input_eth_rx),
.input_in_stb(input_eth_rx_stb),
.input_in_ack(input_eth_rx_ack));
main_6 main_6_139931282859432(
.clk(clk),
.rst(rst),
.exception(exception_139931282859432),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_7 main_7_139931283977280(
.clk(clk),
.rst(rst),
.exception(exception_139931283977280),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_8 main_8_139931280790448(
.clk(clk),
.rst(rst),
.exception(exception_139931280790448),
.output_out(output_eth_tx),
.output_out_stb(output_eth_tx_stb),
.output_out_ack(output_eth_tx_ack));
main_9 main_9_139931278706448(
.clk(clk),
.rst(rst),
.exception(exception_139931278706448),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
main_10 main_10_139931285244168(
.clk(clk),
.rst(rst),
.exception(exception_139931285244168),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_11 main_11_139931283531752(
.clk(clk),
.rst(rst),
.exception(exception_139931283531752),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_12 main_12_139931284930360(
.clk(clk),
.rst(rst),
.exception(exception_139931284930360),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_13 main_13_139931278105848(
.clk(clk),
.rst(rst),
.exception(exception_139931278105848),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_14 main_14_139931283236408(
.clk(clk),
.rst(rst),
.exception(exception_139931283236408),
.output_out(output_vga),
.output_out_stb(output_vga_stb),
.output_out_ack(output_vga_ack));
main_15 main_15_139931278705368(
.clk(clk),
.rst(rst),
.exception(exception_139931278705368),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931275014224 || exception_139931284058264 || exception_139931275014800 || exception_139931283364248 || exception_139931277768032 || exception_139931277612960 || exception_139931282859432 || exception_139931283977280 || exception_139931280790448 || exception_139931278706448 || exception_139931285244168 || exception_139931283531752 || exception_139931284930360 || exception_139931278105848 || exception_139931283236408 || exception_139931278705368;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; long long binpow(long long a, long long b) { if (b == 0) return 1; long long res = binpow(a, b / 2); if (b % 2) return res * res * a; else return res * res; } vector<int> adj[200006]; bool vis[200006]; bool color[200006]; bool dfs(int x) { vis[x] = 1; for (int i = 0; i < adj[x].size(); i++) { if (!vis[adj[x][i]]) { color[adj[x][i]] = !color[x]; if (!dfs(adj[x][i])) return false; } else if (color[adj[x][i]] == color[x]) { return false; } } return true; } bool check(int a, int b) { while (a != 0) { int x = a % 10; if (x == 7) return 1; a /= 10; } while (b != 0) { int xx = b % 10; if (xx == 7) return 1; b /= 10; } return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tt; cin >> tt; vector<pair<pair<int, int>, char>> vv; int ewq = 0; while (tt--) { char c; int r, l; cin >> c >> l >> r; vv.push_back({{l, r}, c}); } sort(vv.begin(), vv.end()); int F = 0; int M = 0; for (int i = 1; i <= 366; i++) { F = 0; M = 0; for (int j = 0; j < vv.size(); j++) { if (i >= vv[j].first.first && i <= vv[j].first.second) { if (vv[j].second == F ) F++; else M++; } } ewq = max(min(F, M), ewq); } cout << ewq * 2 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; void cmin(long long& x, long long y) { if (x > y) { x = y; } } int n, a[N]; long long f[N][2]; bool best[N][2]; vector<int> adj[N], answer; void dfs1(int u, int p) { long long min_diff = 0; bool go = false; for (auto v : adj[u]) { if (v != p) { go = true; dfs1(v, u); f[u][0] += f[v][0]; f[u][1] += f[v][0]; cmin(min_diff, f[v][1] - f[v][0]); } } f[u][1] += min_diff; if (!go) { f[u][0] = a[u]; } else { cmin(f[u][0], f[u][1] + a[u]); } } void dfs2(int u, int p) { if (f[u][0] == f[u][1] + a[u]) { best[u][1] |= best[u][0]; if (best[u][0]) { answer.push_back(u); } } long long sumf = 0; for (auto v : adj[u]) { if (v != p) { sumf += f[v][0]; } } vector<int> diff_nodes; for (auto v : adj[u]) { if (v != p) { if (sumf == f[u][0]) { best[v][0] |= best[u][0]; } if (sumf + f[v][1] - f[v][0] == f[u][1] && best[u][1]) { best[v][1] = true; diff_nodes.push_back(v); } else if (sumf + f[v][1] - f[v][0] + a[u] == f[u][0] && best[u][0]) { diff_nodes.push_back(v); } } } for (auto v : adj[u]) { if (v != p) { if (diff_nodes.size() > 1) { best[v][0] |= true; } else if (diff_nodes.size() == 1 && v != diff_nodes.back()) { best[v][0] |= true; } dfs2(v, u); } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } for (int i = 1; i < n; ++i) { int u, v; scanf( %d%d , &u, &v); adj[u].push_back(v); adj[v].push_back(u); } dfs1(1, 0); best[1][0] = true; dfs2(1, 0); printf( %lld %d n , f[1][0], answer.size()); sort(answer.begin(), answer.end()); for (auto v : answer) { printf( %d , v); } return puts( ), 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int a, b, cnt = 0, sum = 0, i, j, hand, flag = 0, c, n, m, k, t, res, maxy = 0, miny = 12345678910; cin >> n; string str; getline(cin, str); int len = str.size(); if (str[len - 1] == k ) { if (n == 5 || n == 6) printf( 53 n ); else printf( 52 ); } else if (str[len - 1] == h ) { if (n == 30) printf( 11 ); else if (n < 30) printf( 12 ); else printf( 7 ); } }
|
#include <bits/stdc++.h> using namespace std; const long long BIG = 1000000000000000000LL; void solve(); signed main() { ios::sync_with_stdio(false); cin.tie(0); solve(); return 0; } long long nbBoxes; long long reqSom = 0; bool cycor[1 << 15]; pair<long long, pair<long long, long long> > cymem[1 << 15]; long long dpGo[1 << 15]; long long origSom[15]; vector<long long> yolo[15]; map<long long, long long> loc; map<long long, long long> ds; vector<long long> maskOk; pair<long long, long long> finRes[15]; long long osef[15]; long long getMap(long long x) { auto it = loc.find(x); if (it == loc.end()) return -1; else return it->second; } void tester(long long dep, long long valEnvoi, long long suiv, bool act = false) { if (dep == suiv) { if (origSom[dep] == reqSom) { cycor[1LL << dep] = true; cymem[1LL << dep] = {dep, {valEnvoi, suiv}}; if (act) finRes[dep] = {dep, osef[dep]}; } return; } long long gauche = dep; long long cg = reqSom - (origSom[dep] - valEnvoi); long long mask = (1LL << gauche); if (act) finRes[dep] = {suiv, valEnvoi}; while (true) { long long prev = gauche; gauche = getMap(cg); if (gauche != -1 && act) finRes[gauche] = {prev, cg}; if (gauche == -1 || gauche == dep) break; if (mask & (1LL << gauche)) break; cg = reqSom - (origSom[gauche] - cg); mask |= (1LL << gauche); } if (gauche == dep && cg == valEnvoi) { cycor[mask] = true; cymem[mask] = {dep, {valEnvoi, suiv}}; } } void solve() { cin >> nbBoxes; for (long long i = (0); i < (nbBoxes); ++i) { long long ni; cin >> ni; for (long long i00 = (0); i00 < (ni); ++i00) { long long x; cin >> x; yolo[i].push_back(x); reqSom += x; origSom[i] += x; loc[x] = i; osef[i] = x; } } if (reqSom % nbBoxes != 0) { cout << No n ; return; } reqSom /= nbBoxes; for (long long i = (0); i < (nbBoxes); ++i) { for (long long x : yolo[i]) { tester(i, x, -1); tester(i, x, i); } } for (long long i = (0); i < ((1 << 15)); ++i) { dpGo[i] = -1; } dpGo[0] = 0; for (long long mask = 1; mask < (1 << 15); ++mask) { for (long long s = mask; s > 0; s = ((s - 1) & mask)) { if (cycor[s] && dpGo[mask ^ s] != -1) { dpGo[mask] = s; break; } } } long long cur = (1LL << nbBoxes) - 1; while (dpGo[cur] != 0) { if (dpGo[cur] == -1) { cout << No n ; return; } long long ret = dpGo[cur]; long long dep = cymem[ret].first, valEnv = cymem[ret].second.first, suiv = cymem[ret].second.second; tester(dep, valEnv, suiv, true); cur ^= ret; } cout << Yes n ; for (long long i = (0); i < (nbBoxes); ++i) cout << finRes[i].second << << finRes[i].first + 1 << n ; }
|
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 0, 1, -1, 1, -1, 1, -1}; int dy[] = {1, -1, 0, 0, -1, 1, 1, -1}; long long gcd(long long a, long long b) { return !b ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return (a / gcd(a, b)) * b; } void PLAY() { cout << fixed << setprecision(10); ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int num_cost[100005]; int mp[205][100005]; int freq_cum[100005]; int freq[100005]; int main() { PLAY(); int n; cin >> n; vector<int> v(n); set<int> st; for (int i = 0; i < n; i++) { cin >> v[i]; freq_cum[v[i]]++; freq[v[i]]++; st.insert(v[i]); } for (int i = 0; i < n; i++) { int d; cin >> d; num_cost[v[i]] += d; mp[d][v[i]]++; } vector<int> srtd(st.begin(), st.end()); sort(srtd.rbegin(), srtd.rend()); for (int i = 1; i < 100005; i++) { num_cost[i] += num_cost[i - 1]; freq_cum[i] += freq_cum[i - 1]; } for (int i = 1; i <= 200; i++) for (int j = 1; j < 100005; j++) mp[i][j] += mp[i][j - 1]; int res = INT_MAX; for (int i = 0; i < (int)srtd.size(); i++) { int num = srtd[i]; int cur_cost = num_cost[srtd[0]] - num_cost[srtd[i]]; int removed = freq_cum[srtd[0]] - freq_cum[num]; int rem = n - removed; int remove = max(0, rem - (freq[num] * 2 - 1)); for (int cost = 1; cost <= 200 && remove; cost++) { int avilable = mp[cost][num - 1] - mp[cost][0]; int cnt = min(remove, avilable); cur_cost += cnt * cost; remove -= cnt; } res = min(res, cur_cost); } cout << res << endl; return 0; }
|
//
// Copyright (c) 2001 Ed Schwartz ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Verify PR142 - Added something to print PASSED..
module testit;
reg clk;
reg [2:0] cnt;
always
begin
# 50 clk = ~clk;
end // always begin
task idle;
input [15:0] waitcnt;
begin: idletask
// begin
integer i;
for (i=0; i < waitcnt; i = i + 1)
begin
@ (posedge clk);
end // for (i=0; i < waitcnt; i = i + 1)
end
endtask // idle
initial begin
clk = 0;
cnt = 0;
$display ("One");
cnt = cnt + 1;
idle(3);
cnt = cnt + 1;
$display ("Two");
if(cnt === 2)
$display("PASSED");
else
$display("FAILED");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:45:21 02/22/2015
// Design Name:
// Module Name: AddState
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AddState(
input [1:0] idle_Allign2,
input [35:0] cout_Allign2,
input [35:0] zout_Allign2,
input [31:0] sout_Allign2,
input [1:0] modeout_Allign2,
input operationout_Allign2,
input NatLogFlagout_Allign2,
input [7:0] InsTag_Allign2,
input clock,
output reg [1:0] idle_AddState,
output reg [31:0] sout_AddState,
output reg [1:0] modeout_AddState,
output reg operationout_AddState,
output reg NatLogFlagout_AddState,
output reg [27:0] sum_AddState,
output reg [7:0] InsTag_AddState
);
parameter mode_circular =2'b01,
mode_linear =2'b00,
mode_hyperbolic=2'b11;
parameter no_idle = 2'b00,
allign_idle = 2'b01,
put_idle = 2'b10;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_Allign2[35];
assign z_exponent = zout_Allign2[34:27] - 127;
assign z_mantissa = {zout_Allign2[26:0]};
assign c_sign = cout_Allign2[35];
assign c_exponent = cout_Allign2[34:27] - 127;
assign c_mantissa = {cout_Allign2[26:0]};
always @ (posedge clock)
begin
InsTag_AddState <= InsTag_Allign2;
idle_AddState <= idle_Allign2;
modeout_AddState <= modeout_Allign2;
operationout_AddState <= operationout_Allign2;
NatLogFlagout_AddState <= NatLogFlagout_Allign2;
if (idle_Allign2 != put_idle) begin
sout_AddState[30:23] <= c_exponent;
sout_AddState[22:0] <= 0;
if (c_sign == z_sign) begin
sum_AddState <= c_mantissa + z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
if (c_mantissa >= z_mantissa) begin
sum_AddState <= c_mantissa - z_mantissa;
sout_AddState[31] <= c_sign;
end else begin
sum_AddState <= z_mantissa - c_mantissa;
sout_AddState[31] <= z_sign;
end
end
end
else begin
sout_AddState <= sout_Allign2;
sum_AddState <= 0;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine Register Block Level 15
// File : der_reg_15.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Second level register block
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module der_reg_15
(
input de_clk, // drawing engine clock input
de_rstn, // reset input
input load_15, // load L15 command parameters
input [12:0] buf_ctrl_1, // buffer control register input
input [31:0] sorg_1, // source origin register input
input [31:0] dorg_1, // destination origin register input
input [11:0] sptch_1, // source pitch register input
input [11:0] dptch_1, // destination pitch register input
input [3:0] opc_1, // opcode register
input [3:0] rop_1, // raster opcode register input
input [4:0] style_1, // drawing style register input
input nlst_1, // drawing pattern style register input
input [1:0] apat_1, // drawing area pattern mode
input [2:0] clp_1, // drawing clip control register input
input [31:0] fore_1, // foreground color register input
input [31:0] back_1, // background color register input
input [3:0] mask_1, // plane mask register input
input [23:0] de_key_1, // Key data
input [15:0] alpha_1, // Alpha Register
input [17:0] acntrl_1, // Alpha Control Register
input [1:0] bc_lvl_1,
input [31:0] xy0_1,
input [31:0] xy1_1,
input [31:0] xy2_1,
input [31:0] xy3_1,
input [31:0] xy4_1,
output reg [12:0] buf_ctrl_15, // buffer control register input
output reg [31:0] sorg_15, // source origin register input
output reg [31:0] dorg_15, // destination origin register input
output reg [11:0] sptch_15, // source pitch register input
output reg [11:0] dptch_15, // destination pitch register input
output reg [3:0] rop_15, // raster opcode register input
output reg [4:0] style_15, // drawing style register input
output reg nlst_15, // drawing pattern style register input
output reg [1:0] apat_15, // drawing area pattern mode.
output reg [2:0] clp_15, // drawing clip control register input
output reg [31:0] fore_15, // foreground color register input
output reg [31:0] back_15, // background color register input
output reg [3:0] mask_15, // plane mask register input
output reg [23:0] de_key_15, // Key data
output reg [15:0] alpha_15, // Alpha Register
output reg [17:0] acntrl_15, // Alpha Control Register
output reg [1:0] bc_lvl_15,
output reg [3:0] opc_15, // opcode register, L15
output reg [31:0] xy0_15,
output reg [31:0] xy1_15,
output reg [31:0] xy2_15,
output reg [31:0] xy3_15,
output reg [31:0] xy4_15
);
/***************************************************************************/
/* */
/* ASSIGN OUTPUTS TO REGISTERS */
/* */
/***************************************************************************/
always @(posedge de_clk or negedge de_rstn) begin
if(!de_rstn) begin
buf_ctrl_15 <= 13'b0;
sorg_15 <= 32'b0;
dorg_15 <= 32'b0;
rop_15 <= 4'b0;
style_15 <= 5'b0;
nlst_15 <= 1'b0;
apat_15 <= 2'b0;
clp_15 <= 3'b0;
bc_lvl_15 <= 2'b0;
sptch_15 <= 12'b0;
dptch_15 <= 12'b0;
fore_15 <= 32'b0;
back_15 <= 32'b0;
mask_15 <= 4'b0;
de_key_15 <= 24'b0;
alpha_15 <= 16'b0;
acntrl_15 <= 18'b0;
opc_15 <= 4'b0;
xy0_15 <= 32'h0;
xy1_15 <= 32'h0;
xy2_15 <= 32'h0;
xy3_15 <= 32'h0;
xy4_15 <= 32'h0;
end else if (load_15) begin
buf_ctrl_15 <= buf_ctrl_1;
sorg_15 <= sorg_1;
dorg_15 <= dorg_1;
rop_15 <= rop_1;
style_15 <= style_1;
nlst_15 <= nlst_1;
apat_15 <= apat_1;
clp_15 <= clp_1;
bc_lvl_15 <= bc_lvl_1;
sptch_15 <= sptch_1;
dptch_15 <= dptch_1;
fore_15 <= fore_1;
back_15 <= back_1;
mask_15 <= mask_1;
de_key_15 <= de_key_1;
alpha_15 <= alpha_1;
acntrl_15 <= acntrl_1;
opc_15 <= opc_1;
xy0_15 <= xy0_1;
xy1_15 <= xy1_1;
xy2_15 <= xy2_1;
xy3_15 <= xy3_1;
xy4_15 <= xy4_1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_SYMBOL_V
/**
* lsbuflv2hv_clkiso_hlkg: Level-shift clock buffer, low voltage to
* high voltage, isolated well
* on input buffer, inverting sleep
* mode input.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_CLKISO_HLKG_SYMBOL_V
|
module uvm;
class simple_item extends uvm_sequence_item;
rand int unsigned addr;
rand int unsigned data;
rand int unsigned delay;
constraint c1 { addr < 16'h2000; }
constraint c2 { data < 16'h1000; }
// UVM automation macros for general objects
`uvm_object_utils_begin(simple_item)
a = b;
c = d;
`uvm_field_int(addr, UVM_ALL_ON)
`uvm_field_int(data, UVM_ALL_ON)
`uvm_field_int(delay, UVM_ALL_ON)
`uvm_object_utils_end
// Constructor
function new (string name = "simple_item");
super.new(name);
endfunction : new
endclass : simple_item
class mydata extends uvm_object;
string str;
mydata subdata;
int field;
myenum e1;
int queue[$];
`uvm_object_utils(mydata)
`uvm_object_utils_begin(mydata) //requires ctor with default args
`uvm_field_string(str, UVM_DEFAULT)
`uvm_field_object(subdata, UVM_DEFAULT)
`uvm_field_int(field, UVM_DEC) //use decimal radix
`uvm_field_enum(myenum, e1, UVM_DEFAULT)
`uvm_field_queue_int(queue, UVM_DEFAULT)
`uvm_object_utils_end
`uvm_object_param_utils_begin(mydata) //requires ctor with default args
`uvm_field_string(str, UVM_DEFAULT)
`uvm_field_object(subdata, UVM_DEFAULT)
`uvm_field_int(field, UVM_DEC) //use decimal radix
`uvm_field_enum(myenum, e1, UVM_DEFAULT)
`uvm_field_queue_int(queue, UVM_DEFAULT)
`uvm_object_utils_end
endclass
class my_trans extends uvm_sequence_item;
rand bit [127:0] data [];
//---> Configuration
`uvm_object_utils_begin(my_trans)
`uvm_field_array_int ( data, UVM_ALL_ON)
`uvm_object_utils_end
function new (string name = "my_trans", uvm_sequencer_base sequencer = null, uvm_sequence parent_seq = null);
super.new(name, sequencer, parent_seq);
endfunction : new
endclass : my_trans
endmodule // uvm
module tt;
initial begin
while (1) begin
`uvm_do_with(aa, {bb == 0;})
`uvm_do(cc)
`uvm_do(cc)
end // while (1)
end // initial begin
endmodule // tt
|
#include <bits/stdc++.h> using namespace std; int INF = 1234567890; int t, T; int fa[100000], opp[100000]; int l[100000], r[100000]; int col[100000]; set<pair<int, int> > rp; set<pair<int, int> > lp; int find(int a) { if (a == -1) return -1; if (fa[a] == -1) return a; return fa[a] = find(fa[a]); } bool check(int a, int b) { if (a == -1 || b == -1) return true; if (a == b) return false; return r[a] + r[b] >= t && l[a] + l[b] <= T; } bool merge(int a, int b) { if (a == b) return true; if (a == -1 || b == -1) return true; fa[b] = a; lp.erase(make_pair(l[b], b)); rp.erase(make_pair(r[b], b)); if (l[b] > l[a]) { if (lp.find(make_pair(l[a], a)) != lp.end()) { lp.erase(make_pair(l[a], a)); lp.insert(make_pair(l[b], a)); } l[a] = l[b]; } if (r[b] < r[a]) { if (rp.find(make_pair(r[a], a)) != rp.end()) { rp.erase(make_pair(r[a], a)); rp.insert(make_pair(r[b], a)); } r[a] = r[b]; } return l[a] <= r[a]; } bool diff(int a, int b) { a = find(a); b = find(b); int aa = find(opp[a]); int bb = find(opp[b]); if (a == b) return false; if (!check(a, b)) return false; if (!check(aa, bb)) return false; if (opp[a] == -1) opp[a] = b; if (opp[b] == -1) opp[b] = a; return merge(aa, b) && merge(a, bb); } bool same(int a, int b) { a = find(a); b = find(b); int aa = find(opp[a]); int bb = find(opp[b]); if (!check(a, bb)) return false; if (!check(aa, b)) return false; if (opp[a] == -1) opp[a] = opp[b]; if (opp[b] == -1) opp[b] = opp[a]; return merge(a, b) && merge(aa, bb); } int get(int a) { if (col[a] != -1) return col[a]; if (fa[a] == -1) { col[a] = 0; if (opp[a] != -1) col[find(opp[a])] = 1; return 0; } return col[a] = get(find(a)); } int main() { while (scanf( %d%d , &t, &T) == 2) { rp.clear(); lp.clear(); int n, m; scanf( %d%d , &n, &m); bool f = true; memset(fa, -1, sizeof(fa)); memset(opp, -1, sizeof(opp)); for (int i = 0; i < n; i++) { scanf( %d%d , l + i, r + i); rp.insert(make_pair(r[i], i)); lp.insert(make_pair(l[i], i)); if (l[i] > T) f = false; } while (m--) { int a, b; scanf( %d%d , &a, &b); a--; b--; a = find(a); b = find(b); if (!diff(a, b)) f = false; } if (n == 1) { if (l[0] > T || r[0] < t) printf( IMPOSSIBLE n ); else printf( POSSIBLE n%d 0 n1 n , max(l[0], t)); continue; } for (int i = 0; i < n && f; i++) { if (find(i) != i) continue; rp.erase(rp.find(make_pair(r[i], i))); lp.erase(lp.find(make_pair(l[i], i))); while (f && !lp.empty()) { set<pair<int, int> >::iterator itr = lp.end(); itr--; int b = find(itr->second); if (b == find(opp[i])) { b = itr->second; rp.erase(make_pair(r[b], b)); lp.erase(make_pair(l[b], b)); continue; } if (r[i] < l[b]) f = diff(i, b); else break; } while (f && !lp.empty()) { set<pair<int, int> >::iterator itr = lp.end(); itr--; int b = find(itr->second); if (b == find(opp[i])) { b = itr->second; rp.erase(make_pair(r[b], b)); lp.erase(make_pair(l[b], b)); continue; } if (l[i] + l[b] > T) f = same(i, b); else break; } while (f && !lp.empty()) { set<pair<int, int> >::iterator itr = rp.begin(); int b = find(itr->second); if (b == find(opp[i])) { b = itr->second; rp.erase(make_pair(r[b], b)); lp.erase(make_pair(l[b], b)); continue; } if (r[i] + r[b] < t) f = same(i, b); else break; } if (i == find(i)) { rp.insert(make_pair(r[i], i)); lp.insert(make_pair(l[i], i)); } if (opp[i] != -1) { int j = find(opp[i]); rp.insert(make_pair(r[j], j)); lp.insert(make_pair(l[j], j)); } } if (!f) printf( IMPOSSIBLE n ); else { printf( POSSIBLE n ); memset(col, -1, sizeof(col)); int l0 = 0, r0 = T, l1 = 0, r1 = T; for (int i = 0; i < n; i++) { if (get(i)) { l1 = max(l1, l[i]); r1 = min(r1, r[i]); } else { l0 = max(l0, l[i]); r0 = min(r0, r[i]); } } int L = l0, R = l1; int ndd = t - l0 - l1; if (ndd > 0) { if (ndd + L <= r0) { L += ndd; } else { L = r0; ndd -= r0 - l0; R += ndd; } } printf( %d %d n , L, R); for (int i = 0; i < n; i++) printf( %d , col[i] + 1); printf( n ); } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A31O_PP_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; inline int read() { char c = getchar(); int x = 0; bool f = 0; for (; !isdigit(c); c = getchar()) f ^= !(c ^ 45); for (; isdigit(c); c = getchar()) x = (x << 1) + (x << 3) + (c ^ 48); if (f) x = -x; return x; } bool work() { int a = read(), b = read(); if (a > b) swap(a, b); if (a == 0) return (b == 0); if (a * 2 < b) return 0; if (a * 2 == b) return 1; int c = (abs(b - a - a)); return (a + b) % 3 == 0; } signed main() { int n = read(); while (n--) if (work()) puts( YES ); else puts( NO ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_4_V
`define SKY130_FD_SC_HD__O21BA_4_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_SYMBOL_V
`define SKY130_FD_SC_LS__NOR4BB_SYMBOL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_SYMBOL_V
|
// Copyright (c) 2016 Min Chen
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// Asymmetric port RAM
module RAM_Nx1(clkA, clkB, weA, reB, addrA, addrB, diA, doB);
parameter WIDTHA = 72;
parameter SIZEA = 512;
parameter ADDRWIDTHA = 9;
parameter WIDTHB = 18;
parameter SIZEB = 2048;
parameter ADDRWIDTHB = 11;
input clkA;
input clkB;
input weA;
input reB;
input [ADDRWIDTHA-1:0] addrA;
input [ADDRWIDTHB-1:0] addrB;
input [WIDTHA-1:0] diA;
output reg [WIDTHB-1:0] doB;
reg [WIDTHA-1:0] mux;
reg [WIDTHA-1:0] RAM [SIZEA-1:0] /* synthesis syn_ramstyle="no_rw_check" */ ;
always @(posedge clkA)
begin
if(weA)
RAM[addrA] <= diA;
end
always @(posedge clkB)
begin
mux = RAM[addrB[ADDRWIDTHB-1:1]];
if(reB)
begin
if (addrB[0])
doB <= mux[WIDTHA-1:WIDTHB];
else
doB <= mux[WIDTHB-1:0];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[105], b[105], n, k; bool f[105]; void dfs(int i) { f[i] = true; for (int k = 1; k <= n; k++) { if (f[k]) continue; if (a[i] > a[k] && a[i] < b[k]) dfs(k); else if (b[i] > a[k] && b[i] < b[k]) dfs(k); } } void setup() { cin >> k; } void work() { while (k--) { int x, y, m; cin >> m; if (m == 1) { n++; cin >> a[n] >> b[n]; } else { cin >> x >> y; memset(f, 0, sizeof(f)); dfs(x); if (f[y]) cout << YES << n ; else cout << NO << n ; } } } int main() { ios_base::sync_with_stdio(0); cin.tie(); cout.tie(); setup(); work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int r, c, ans = 0; cin >> r >> c; vector<vector<long long int> > A(r + 2, vector<long long int>(c + 2)); for (long long int i = 1; i <= r; i++) for (long long int j = 1; j <= c; j++) cin >> A[i][j]; vector<vector<long long int> > left(A), right(A), up(A), down(A); for (long long int i = 1; i <= r; i++) for (long long int j = 1; j <= c; j++) left[i][j] += left[i][j - 1]; for (long long int i = 1; i <= r; i++) for (long long int j = c; j >= 1; j--) right[i][j] += right[i][j + 1]; for (long long int j = 1; j <= c; j++) for (long long int i = 1; i <= r; i++) up[i][j] += up[i - 1][j]; for (long long int j = 1; j <= c; j++) for (long long int i = r; i >= 1; i--) down[i][j] += down[i + 1][j]; for (long long int i = 1; i <= r; i++) for (long long int j = 1; j <= c; j++) if (A[i][j] == 0) ans += (left[i][j - 1] != 0) + (right[i][j + 1] != 0) + (up[i - 1][j] != 0) + (down[i + 1][j] != 0); cout << ans; }
|
#include <bits/stdc++.h> using namespace std; long long lmin(long long a, long long b) { if (a < b) return a; return b; } long long lmax(long long a, long long b) { if (a > b) return a; return b; } int main() { long long t1, t2, x1, x2, t0; scanf( %lld %lld %lld %lld %lld , &t1, &t2, &x1, &x2, &t0); long long mint = 100000000000LL, mint2 = 10000000000000000LL; double min = 10000000000000.000; if (t2 == t0 && t1 != t0) { printf( 0 %lld n , x2); return 0; } else if (t2 == t0 && t1 == t0) { printf( %lld %lld n , x1, x2); return 0; } for (long long i = 1; i <= x1; i++) { double temp = (double)((t0 - t1) * i); temp /= (double)(t2 - t0); long long temp2 = (long long)temp; double t = ((double)t1 * (double)i + (double)t2 * (double)temp2) / (double)(i + temp2); if (temp > x2) continue; long long temp3 = temp2 * (t2 - t0) - i * (t0 - t1); if (temp3 >= 0) { if (t <= min) { min = t; mint = temp2; mint2 = i; } } else { t = ((double)t1 * (double)i + (double)t2 * (double)(temp2 + 1)) / (double)(i + temp2 + 1); if (temp2 + 1 > x2) continue; if (t <= min) { min = t; mint = temp2 + 1; mint2 = i; } } } long long i = 1; for (i = 1; mint2 * i <= x1 && mint * i <= x2; i++) ; if (mint2 * i > x1 || mint * i > x2) i--; if (i == 0) { mint2 = 0; mint = x2; i = 1; } printf( %lld %lld n , mint2 * i, mint * i); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const long long MODSQ = 1LL * MOD * MOD; int W[8]; int dp[1 << 7][1 << 7][8][2]; struct matrix { int sz; int data[1 << 7][1 << 7]; }; matrix multiply(matrix& a, matrix& b) { matrix c; c.sz = a.sz; for (int i = 0; i < c.sz; i++) for (int j = 0; j < c.sz; j++) { long long sum = 0; for (int k = 0; k < c.sz; k++) { sum += 1LL * a.data[i][k] * b.data[k][j]; if (sum >= MODSQ) sum -= MODSQ; } c.data[i][j] = sum % MOD; } return c; } matrix pow(matrix b, int e) { if (e == 1) return b; matrix ret = pow(multiply(b, b), e / 2); if (e & 1) return multiply(ret, b); return ret; } matrix transition_matrix(int sz) { matrix ret; ret.sz = 1 << sz; for (int i = 0; i < (1 << sz); i++) for (int j = 0; j < (1 << sz); j++) ret.data[i][j] = dp[i][j][sz][1]; return ret; } int main() { for (int i = 0; i < (1 << 7); i++) for (int j = 0; j < (1 << 7); j++) { dp[i][j][0][0] = 0; dp[i][j][0][1] = 1; for (int k = 0; k < 7; k++) { dp[i][j][k + 1][0] = dp[i][j][k][0] + dp[i][j][k][1]; dp[i][j][k + 1][1] = dp[i][j][k][0]; if (!(((i >> k) & 1) && ((j >> k) & 1))) dp[i][j][k + 1][1] += dp[i][j][k][1]; } } int last = 0; for (int i = 1; i <= 7; i++) { scanf( %d , W + i); if (W[i]) last = i; } matrix pre, base, tmp; int psz = -1; for (int i = 1; i <= last; i++) if (W[i]) { base.sz = 1 << i; if (psz == -1) { for (int j = 0; j < (1 << i); j++) base.data[j][0] = 0; base.data[(1 << i) - 1][0] = 1; } else { for (int j = 0; j < (1 << i); j++) { if ((j >> psz) == (1 << (i - psz)) - 1) base.data[j][0] = pre.data[j & ((1 << psz) - 1)][0]; else base.data[j][0] = 0; } } tmp = pow(transition_matrix(i), W[i]); pre = multiply(tmp, base); psz = i; } printf( %d n , pre.data[(1 << last) - 1][0]); return 0; }
|
#include <bits/stdc++.h> using namespace std; void _print(long long t) { cerr << t; } void _print(string t) { cerr << t; } void _print(char t) { cerr << t; } void _print(long double t) { cerr << t; } void _print(double t) { cerr << t; } void _print(unsigned long long t) { cerr << t; } template <class T, class V> void _print(pair<T, V> p); template <class T> void _print(vector<T> v); template <class T> void _print(set<T> v); template <class T, class V> void _print(map<T, V> v); template <class T> void _print(multiset<T> v); template <class T, class V> void _print(pair<T, V> p) { cerr << { ; _print(p.first); cerr << , ; _print(p.second); cerr << } ; } template <class T> void _print(vector<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(set<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(multiset<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T, class V> void _print(map<T, V> v) { cerr << [ ; for (auto i : v) { _print(i); cerr << ; } cerr << ] ; } const long long N = 1e6 + 5; void solve() { long long n; cin >> n; vector<vector<long long>> a; for (long long i = 0; i < n; i++) { long long x; cin >> x; vector<long long> temp(x); for (long long j = 0; j < x; j++) cin >> temp[j]; a.push_back(temp); } set<vector<long long>> vis; set<vector<long long>> banned; long long m; cin >> m; for (long long i = 0; i < m; i++) { vector<long long> temp(n); for (long long j = 0; j < n; j++) { cin >> temp[j]; temp[j]--; } banned.insert(temp); } set<pair<long long, vector<long long>>> st; long long s = 0; vector<long long> temp; for (long long i = 0; i < n; i++) { s += a[i][(long long)a[i].size() - 1]; temp.push_back((long long)a[i].size() - 1); } st.insert({s, temp}); vis.insert(temp); while (!st.empty()) { auto [val, vec] = *prev(st.end()); st.erase(prev(st.end())); if (banned.find(vec) == banned.end()) { for (auto i : vec) cout << i + 1 << ; return; } for (long long i = 0; i < n; i++) { if (vec[i] - 1 >= 0) { long long newval = val - a[i][vec[i]] + a[i][vec[i] - 1]; vector<long long> newvec = vec; newvec[i]--; if (vis.find(newvec) == vis.end()) { st.insert({newval, newvec}); vis.insert(newvec); } } } } } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { solve(); } }
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
localparam STACK_DEPTH = 7;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("call2.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 1;
reg [ MEM_ADDR:0] pc = 33;
reg [STACK_DEPTH:0] index = 0;
wire [ 63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR),
.STACK_DEPTH(STACK_DEPTH)
)
dut
(
.clk(clk),
.reset(reset),
.pc(pc),
.index(index),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("call2_tb.vcd");
$dumpvars(0, cpu_tb);
#1
reset <= 0;
if(USE_64B) begin
#45
`assert(result, 3);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#17
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 105; const long long MOD = 1e9 + 7; long long n, m, k; long long cache[N][N * N], cache2[N][N]; long long fact[N], invfact[N]; long long pow(long long a, long long b, long long m) { long long ans = 1; while (b) { if (b & 1) ans = (ans * a) % m; b /= 2; a = (a * a) % m; } return ans; } long long modinv(long long k) { return pow(k, MOD - 2, MOD); } void precompute() { fact[0] = fact[1] = 1; for (long long i = 2; i < N; i++) { fact[i] = fact[i - 1] * i; fact[i] %= MOD; } invfact[N - 1] = modinv(fact[N - 1]); for (long long i = N - 2; i >= 0; i--) { invfact[i] = invfact[i + 1] * (i + 1); invfact[i] %= MOD; } } long long nCr(long long x, long long y) { if (y > x) return 0; long long num = fact[x]; num *= invfact[y]; num %= MOD; num *= invfact[x - y]; num %= MOD; return num; } long long get(long long idx, long long cur) { long long &ans = cache2[idx][cur]; if (ans != -1) return ans; long long ways = nCr(n, cur); long long have = m / n; if (m % n >= (idx)) have++; ways = pow(ways, have, MOD); return ans = ways; } long long dp(long long idx, long long rem) { if (idx == n + 1) return (rem == 0); long long &ans = cache[idx][rem]; if (ans != -1) return ans; ans = 0; for (long long cur = 0; cur <= min(n, rem); cur++) { long long ways = get(idx, cur); ans += ways * dp(idx + 1, rem - cur); ans %= MOD; } return ans; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; precompute(); memset(cache, -1, sizeof(cache)); memset(cache2, -1, sizeof(cache2)); cin >> n >> m >> k; cout << dp(1, k); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 16, K = 225; struct HASH { size_t operator()(const pair<long long, long long> &x) const { return hash<long long>()((x.first) ^ ((x.second) << 32)); } }; int dx[4] = {0, 0, -1, 1}, dy[4] = {1, -1, 0, 0}; int n, m; int len = 0; long long pw[N]; string str[N]; unordered_map<pair<long long, long long>, int, HASH> dis; bool good(pair<long long, long long> p, int i, int j) { int cur = (i * m + j); for (int k = 0; k < len - 1 - 5; k++) if (p.first / pw[k] % K == cur) return false; for (int k = 0; k < min(len - 1, 5); k++) if (p.second / pw[k] % K == cur) return false; return true; } bool in_bound(int i, int j) { return i >= 0 && i < n && j >= 0 && j < m && str[i][j] != # ; } pair<long long, long long> getnxt(pair<long long, long long> p, int i, int j) { p.first *= K; p.first += p.second / pw[4]; p.first %= pw[max(len - 5, 0)]; p.second *= K; p.second += (i * m + j); p.second %= pw[min(len, 5)]; return p; } int main() { pw[0] = 1; for (int i = 1; i < 6; i++) pw[i] = pw[i - 1] * K; cin >> n >> m; for (int i = 0; i < n; i++) cin >> str[i]; pair<long long, long long> ori; queue<pair<long long, long long> > que; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { char c = str[i][j]; if (c >= 1 && c <= 9 ) { int x = c - 0 ; len = max(len, x); x--; if (x >= 5) ori.first += (i * m + j) * pw[x - 5]; else ori.second += (i * m + j) * pw[x]; } } } que.push(ori); dis[ori] = 0; while (!que.empty()) { pair<long long, long long> p = que.front(); que.pop(); int curdis = dis[p]; int ci = (int)(p.second % K / m), cj = (int)(p.second % K % m); for (int d = 0; d < 4; d++) { int ni = ci + dx[d], nj = cj + dy[d]; if (in_bound(ni, nj) && good(p, ni, nj)) { if (str[ni][nj] == @ ) { return cout << curdis + 1 << endl, 0; } pair<long long, long long> nxt = getnxt(p, ni, nj); if (!dis.count(nxt)) { que.push(nxt); dis[nxt] = curdis + 1; } } } } cout << -1 << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); char a[n][n]; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) a[i][j] = * ; int begin, end; begin = end = n / 2; for (int i = 0; i <= n / 2; i++) { for (int j = begin; j <= end; j++) a[i][j] = D ; begin--; end++; } begin += 2; end -= 2; for (int i = n / 2 + 1; i < n; i++) { for (int j = begin; j <= end; j++) a[i][j] = D ; begin++; end--; } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) printf( %c , a[i][j]); printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { short n; int n1, n2; bool state = false; char handle[11]; cin >> n; for (short i = 0; i < n; i++) { cin >> handle; cin >> n1; cin >> n2; if (n1 >= 2400 && n2 > n1) state = true; } if (state) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long UNDEF = -1; const long long INF = 1e18; template <typename T> inline bool chkmax(T &aa, T bb) { return aa < bb ? aa = bb, true : false; } template <typename T> inline bool chkmin(T &aa, T bb) { return aa > bb ? aa = bb, true : false; } long long cross(const pair<long long, long long> &a, const pair<long long, long long> &b, const pair<long long, long long> &c) { return (b.first - a.first) * (c.second - a.second) - (b.second - a.second) * (c.first - a.first); } vector<pair<long long, long long> > convexHullAllowStraightEdges( vector<pair<long long, long long> > points) { if (points.size() <= 1) return points; sort(points.begin(), points.end()); vector<pair<long long, long long> > h; for (auto p : points) { while (h.size() >= 2 && cross(h.end()[-2], h.back(), p) > 0) h.pop_back(); h.push_back(p); } reverse(points.begin(), points.end()); int upper = h.size(); for (auto p : points) { while (h.size() > upper && cross(h.end()[-2], h.back(), p) > 0) h.pop_back(); h.push_back(p); } h.resize(h.size() - 1 - (h[0] == h[1])); return h; } static char stdinBuffer[1024]; static char *stdinDataEnd = stdinBuffer + sizeof(stdinBuffer); static const char *stdinPos = stdinDataEnd; void readAhead(size_t amount) { size_t remaining = stdinDataEnd - stdinPos; if (remaining < amount) { memmove(stdinBuffer, stdinPos, remaining); size_t sz = fread(stdinBuffer + remaining, 1, sizeof(stdinBuffer) - remaining, stdin); stdinPos = stdinBuffer; stdinDataEnd = stdinBuffer + remaining + sz; if (stdinDataEnd != stdinBuffer + sizeof(stdinBuffer)) *stdinDataEnd = 0; } } long long readInt() { readAhead(16); long long x = 0; bool neg = false; while (*stdinPos == || *stdinPos == n ) ++stdinPos; if (*stdinPos == - ) { ++stdinPos; neg = true; } while (*stdinPos >= 0 && *stdinPos <= 9 ) { x *= 10; x += *stdinPos - 0 ; ++stdinPos; } return neg ? -x : x; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long n = readInt(), m = readInt(); long long ox = readInt(), oy = readInt(); set<pair<long long, long long> > vmin, vmax; for (long long i = 0; i < n; i++) { long long x = readInt(), y = readInt(); vmax.insert(make_pair(x, y)); } long long xhi = 0, yhi = 0; for (long long i = 0; i < m; i++) { long long x = readInt(), y = readInt(); vmin.insert(make_pair(x, y)); chkmax(xhi, x); chkmax(yhi, y); } set<pair<long long, long long> > toch; for (auto &w : vmin) toch.insert(w); for (auto &w : vmax) toch.insert(w); toch.insert(make_pair(0, 0)); toch.insert(make_pair(xhi, 0)); toch.insert(make_pair(0, yhi)); vector<pair<long long, long long> > vtoch; for (auto &w : toch) vtoch.push_back(w); vector<pair<long long, long long> > ch = convexHullAllowStraightEdges(vtoch); for (auto &w : ch) { if (vmax.find(w) != vmax.end()) { printf( Max n ); return 0; } } printf( Min n ); }
|
#include <bits/stdc++.h> using namespace std; const int INF = 2000000009; const int Max = 1000007; const double PI = acos(-1.0); long long nc2(long long n) { return (n * (n - 1)) / 2; } map<long long, long long> mp1, mp2; map<pair<long long, long long>, long long> mp3; int main() { long long i, j, k, l, temp, t, n, m, caseno = 0, ans; string str; while (cin >> n) { mp1.clear(); mp2.clear(); mp3.clear(); for (i = 0; i < n; i++) { cin >> j >> k; if (mp1.find(j) == mp1.end()) mp1[j] = 0; if (mp2.find(k) == mp2.end()) mp2[k] = 0; mp1[j]++; mp2[k]++; pair<long long, long long> ttmp = make_pair(j, k); if (mp3.find(ttmp) == mp3.end()) mp3[ttmp] = 0; mp3[ttmp]++; } map<long long, long long>::iterator it; ans = 0; for (it = mp1.begin(); it != mp1.end(); ++it) { ans += nc2(it->second); } for (it = mp2.begin(); it != mp2.end(); ++it) { ans += nc2(it->second); } map<pair<long long, long long>, long long>::iterator itr; for (itr = mp3.begin(); itr != mp3.end(); ++itr) { ans -= nc2(itr->second); } cout << ans << endl; } return 0; }
|
`include "andGate.v"
module andGateTest ();
// localize variables
wire [31:0] busADD;
wire [31:0] busA, busB;
// declare an instance of the module
andGate andGate (busADD, busA, busB);
// Running the GUI part of simulation
andGatetester tester (busADD, busA, busB);
// file for gtkwave
initial
begin
$dumpfile("andGatetest.vcd");
$dumpvars(1, andGate);
end
endmodule
module andGatetester (busADD, busA, busB);
input [31:0] busADD;
output reg [31:0] busA, busB;
parameter d = 20;
initial // Response
begin
$display("busADD \t busA \t busB \t\t\t ");
#d;
end
reg [31:0] i;
initial // Stimulus
begin
$monitor("%b \t %b \t %b \t ", busADD, busA, busB, $time);
// positive + positive
busA = 32'h01010101; busB = 32'h01010101;
#d;
busA = 32'h7FFFFFFF; busB = 32'h7FFFFFFF; // should overflow
#d;
// positive + negative
busA = 32'h01010101; busB = 32'hFFFFFFFF; // 01010101 + -1
#d;
busA = 32'h00000001; busB = 32'hF0000000;
#d;
// negative + positive
busA = 32'hFFFFFFFF; busB = 32'h01010101;
#d;
busA = 32'hF0000000; busB = 32'h00000001;
#d;
// negative + negative
busA = 32'hFFFFFFFF; busB = 32'hFFFFFFFF; // -1 + -1
#d;
busA = 32'h90000000; busB = 32'h80000000; // should overflow
#d;
#(3*d);
$stop;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000009; const int MOD = 1000000007; double probMayor(pair<int, int> x, int bid) { if (bid < x.first) { return 1.0; } if (bid > x.second) { return 0.0; } return double(x.second - bid) / (x.second - x.first + 1); } double probMenor(pair<int, int> x, int bid) { if (bid < x.first) { return 0.0; } if (bid > x.second) { return 1.0; } return double(bid - x.first) / (x.second - x.first + 1); } double go(vector<pair<int, int> > v, int idx, int bid, int cnt) { if (idx >= v.size()) { if (cnt <= 0) { return 1; } return 0; } double res = 0.0; if (bid >= v[idx].first && bid <= v[idx].second) { res += go(v, idx + 1, bid, cnt - 1) * (1.0 / (v[idx].second - v[idx].first + 1)); } res += go(v, idx + 1, bid, cnt) * probMenor(v[idx], bid); return res; } int main() { int n; cin >> n; vector<pair<int, int> > v; for (int i = 0; i < n; i++) { int l, r; cin >> l >> r; v.push_back(make_pair(l, r)); } double res = 0.0; for (int i = 0; i < n; i++) { pair<int, int> p = v[i]; v.erase(v.begin() + i); for (int j = 1; j <= 10000; j++) { res += probMayor(p, j) * j * go(v, 0, j, 1); } v.insert(v.begin() + i, p); } for (int j = 1; j <= 10000; j++) { res += j * go(v, 0, j, 2); } printf( %.10f n , res); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); cout.tie(nullptr); long long int n, m, i, j, x; cin >> n >> m; long long int a[n]; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (i = 0; i < m; i++) { cin >> x; cout << upper_bound(a, a + n, x) - a << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200010, P = 998244353; int n, k, num, ans, h[maxn], fact[maxn], inv[maxn]; int qp(int x, int y) { int z = 1; for (; y; y >>= 1, x = 1LL * x * x % P) { if (y & 1) z = 1LL * z * x % P; } return z; } int C(int x, int y) { return 1LL * fact[x] * inv[y] % P * inv[x - y] % P; } int main() { scanf( %d %d , &n, &k); for (int i = fact[0] = inv[0] = 1; i <= n; i++) { fact[i] = 1LL * i * fact[i - 1] % P; inv[i] = qp(fact[i], P - 2); } for (int i = 0; i < n; i++) { scanf( %d , &h[i]); } for (int i = 0; i < n; i++) { if (h[i] ^ h[(i + 1) % n]) num++; } for (int i = 0; i + i <= num; i++) { ans = (ans + 1LL * C(num, i) * C(num - i, i) % P * qp(k - 2, num - i - i)) % P; } ans = 1LL * qp(k, n - num) * ans % P; printf( %d n , 1LL * qp(2, P - 2) * (qp(k, n) - ans + P) % P); return 0; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module spi_core
#(
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 16
)(
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
input wire SPI_CLK,
output wire SCLK,
input wire SDO,
output reg SDI,
input wire EXT_START,
output reg SEN,
output reg SLD
);
localparam VERSION = 2;
reg [7:0] status_regs [15:0];
wire RST;
wire SOFT_RST;
assign RST = BUS_RST || SOFT_RST;
localparam DEF_BIT_OUT = 8*MEM_BYTES;
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 0;
status_regs[3] <= DEF_BIT_OUT[7:0]; //bits
status_regs[4] <= DEF_BIT_OUT[15:8]; //bits
status_regs[5] <= 4; //wait
status_regs[6] <= 0; //wait
status_regs[7] <= 0; //wait
status_regs[8] <= 0; //wait
status_regs[9] <= 1; //repeat
status_regs[10] <= 0; //repeat
status_regs[11] <= 0; //repeat
status_regs[12] <= 0; //repeat
status_regs[13] <= 0; //0:enable external start
end
else if(BUS_WR && BUS_ADD < 16)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
reg [7:0] BUS_IN_MEM;
reg [7:0] BUS_OUT_MEM;
wire START;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
wire [15:0] CONF_BIT_OUT;
assign CONF_BIT_OUT = {status_regs[4],status_regs[3]};
// TODO: not yet used
wire [7:0] CONF_CLK_DIV;
assign CONF_CLK_DIV = status_regs[2];
reg CONF_DONE;
wire [31:0] CONF_WAIT;
assign CONF_WAIT = {status_regs[8], status_regs[7], status_regs[6], status_regs[5]};
wire [31:0] CONF_REPEAT;
assign CONF_REPEAT = {status_regs[12], status_regs[11], status_regs[10], status_regs[9]};
wire CONF_EN;
assign CONF_EN = status_regs[13][0];
reg [7:0] BUS_DATA_OUT_REG;
always@(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT_REG <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT_REG <= {7'b0, CONF_DONE};
else if(BUS_ADD == 13)
BUS_DATA_OUT_REG <= {7'b0, CONF_EN};
else if(BUS_ADD == 14)
BUS_DATA_OUT_REG <= MEM_BYTES[7:0];
else if(BUS_ADD == 15)
BUS_DATA_OUT_REG <= MEM_BYTES[15:8];
else if (BUS_ADD < 16)
BUS_DATA_OUT_REG <= status_regs[BUS_ADD[3:0]];
end
end
// if one has a synchronous memory need this to give data on next clock after read
// limitation: this module still needs to be addressed
reg [ABUSWIDTH-1:0] PREV_BUS_ADD;
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
PREV_BUS_ADD <= BUS_ADD;
end
end
always @(*) begin
if(PREV_BUS_ADD < 16)
BUS_DATA_OUT = BUS_DATA_OUT_REG;
else if(PREV_BUS_ADD < 16+MEM_BYTES)
BUS_DATA_OUT = BUS_IN_MEM;
else if(PREV_BUS_ADD < 16+MEM_BYTES+MEM_BYTES)
BUS_DATA_OUT = BUS_OUT_MEM;
else
BUS_DATA_OUT = 8'hxx;
end
reg [32:0] out_bit_cnt;
wire [13:0] memout_addrb;
assign memout_addrb = out_bit_cnt;
wire [10:0] memout_addra;
assign memout_addra = (BUS_ADD-16);
reg [7:0] BUS_DATA_IN_IB;
wire [7:0] BUS_IN_MEM_IB;
wire [7:0] BUS_OUT_MEM_IB;
integer i;
always @(*) begin
for(i=0;i<8;i=i+1) begin
BUS_DATA_IN_IB[i] = BUS_DATA_IN[7-i];
BUS_IN_MEM[i] = BUS_IN_MEM_IB[7-i];
BUS_OUT_MEM[i] = BUS_OUT_MEM_IB[7-i];
end
end
wire SDI_MEM;
blk_mem_gen_8_to_1_2k memout(
.CLKA(BUS_CLK),
.CLKB(SPI_CLK),
.DOUTA(BUS_IN_MEM_IB),
.DOUTB(SDI_MEM),
.WEA(BUS_WR && BUS_ADD >=16 && BUS_ADD < 16+MEM_BYTES),
.WEB(1'b0),
.ADDRA(memout_addra),
.ADDRB(memout_addrb),
.DINA(BUS_DATA_IN_IB),
.DINB(1'b0)
);
wire [10:0] ADDRA_MIN;
assign ADDRA_MIN = (BUS_ADD-16-MEM_BYTES);
wire [13:0] ADDRB_MIN;
assign ADDRB_MIN = out_bit_cnt-1;
reg SEN_INT;
blk_mem_gen_8_to_1_2k memin(
.CLKA(BUS_CLK),
.CLKB(SPI_CLK),
.DOUTA(BUS_OUT_MEM_IB),
.DOUTB(),
.WEA(1'b0),
.WEB(SEN_INT),
.ADDRA(ADDRA_MIN),
.ADDRB(ADDRB_MIN),
.DINA(BUS_DATA_IN_IB),
.DINB(SDO)
);
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SPI_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(SPI_CLK), .pulse_out(START_SYNC));
wire EXT_START_PULSE;
reg [2:0] EXT_START_FF;
always @(posedge SPI_CLK) // first stage
begin
EXT_START_FF[0] <= EXT_START;
EXT_START_FF[1] <= EXT_START_FF[0];
EXT_START_FF[2] <= EXT_START_FF[1];
end
assign EXT_START_PULSE = !EXT_START_FF[2] & EXT_START_FF[1];
wire [32:0] STOP_BIT;
assign STOP_BIT = CONF_BIT_OUT + CONF_WAIT;
reg [31:0] REPEAT_COUNT;
wire REP_START;
assign REP_START = (out_bit_cnt == STOP_BIT && (CONF_REPEAT==0 || REPEAT_COUNT < CONF_REPEAT));
reg REP_START_DLY;
always @ (posedge SPI_CLK)
REP_START_DLY <= REP_START;
always @ (posedge SPI_CLK)
if (RST_SYNC)
SEN_INT <= 0;
else if(START_SYNC || (EXT_START_PULSE && CONF_EN) || REP_START_DLY)
SEN_INT <= 1;
else if(out_bit_cnt == CONF_BIT_OUT)
SEN_INT <= 0;
always @ (posedge SPI_CLK)
if (RST_SYNC)
out_bit_cnt <= 0;
else if(START_SYNC || (EXT_START_PULSE && CONF_EN))
out_bit_cnt <= 1;
else if(out_bit_cnt == STOP_BIT)
out_bit_cnt <= 0;
//else if(out_bit_cnt == CONF_BIT_OUT & REPEAT_COUNT == CONF_REPEAT & CONF_REPEAT!=0)
// out_bit_cnt <= 0;
else if(REP_START_DLY)
out_bit_cnt <= 1;
else if(out_bit_cnt != 0)
out_bit_cnt <= out_bit_cnt + 1;
always @ (posedge SPI_CLK)
if (RST_SYNC || START_SYNC || (EXT_START_PULSE && CONF_EN))
REPEAT_COUNT <= 1;
else if(out_bit_cnt == STOP_BIT)
REPEAT_COUNT <= REPEAT_COUNT + 1;
reg [1:0] sync_ld;
always @(posedge SPI_CLK) begin
sync_ld[0] <= SEN_INT;
sync_ld[1] <= sync_ld[0];
end
always @(posedge SPI_CLK)
SLD <= (sync_ld[1]==1 && sync_ld[0]==0);
wire DONE = out_bit_cnt == STOP_BIT && REPEAT_COUNT >= CONF_REPEAT;
wire DONE_SYNC, EXT_START_PULSE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(SPI_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
cdc_pulse_sync done_pulse_ext_start (.clk_in(SPI_CLK), .pulse_in(EXT_START_PULSE), .clk_out(BUS_CLK), .pulse_out(EXT_START_PULSE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START || (EXT_START_PULSE_SYNC && CONF_EN))
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
CG_MOD_pos icg2(.ck_in(SPI_CLK), .enable(SEN), .ck_out(SCLK));
always @(negedge SPI_CLK)
SDI <= SDI_MEM & SEN_INT;
always @(negedge SPI_CLK)
SEN <= SEN_INT;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i; vector<char> v; string s; cin >> s; n = s.size(); char c[n], ch; i = n; ch = s[n - 1]; while (i--) { if (s[i] == ch) v.push_back(s[i]); else if (s[i] > ch) { v.push_back(s[i]); ch = s[i]; } } for (i = v.size(); i > 0; i--) cout << v[i - 1]; }
|
#include <bits/stdc++.h> using namespace std; int n, m; int p[100010]; const int md = 1000000009; int an = 1; int sz[100010]; void make_set(int v) { p[v] = v; sz[v] = 1; } int find_set(int v) { if (p[v] == v) return v; return p[v] = find_set(p[v]); } void union_sets(int a, int b) { a = find_set(a); b = find_set(b); if (a != b) { if (sz[a] < sz[b]) swap(a, b); p[b] = a; sz[a] += sz[b]; } else an = (an * 2) % md; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) make_set(i); for (int i = 0; i < m; i++) { int a, b; scanf( %d %d , &a, &b); union_sets(a, b); printf( %d n , an - 1); } return 0; }
|
#include <bits/stdc++.h> int main() { char abc[105]; scanf( %s , abc); int n = strlen(abc); int i = 0; int max = 1, count = 0; while (i < n) { if (abc[i] == A || abc[i] == E || abc[i] == I || abc[i] == O || abc[i] == U || abc[i] == Y ) { if (max < count + 1) max = count + 1; count = 0; } else count++; i++; } if (max < count + 1) max = count + 1; printf( %d , max); }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Fri Sep 22 10:05:01 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[7:0],probe8[63:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[7:0],probe14[63:0],probe15[1:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [7:0]probe7;
input [63:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [0:0]probe12;
input [7:0]probe13;
input [63:0]probe14;
input [1:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [0:0]probe19;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A31OI_FUNCTIONAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31OI_FUNCTIONAL_V
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:102400000,102400000 ) using namespace std; const double PI = acos(-1.0); int f_max(int a, int b) { return a > b ? a : b; } int f_min(int a, int b) { return a < b ? a : b; } int f_abs(int a) { return a > 0 ? a : -a; } int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int n, m; int u, d, l, r; int x, y; int main() { int q, w, e; int i, j, k; int ans, len; while (~scanf( %d%d , &n, &m)) { len = 0x7fffffff; r = u = -0x7fffffff; l = d = 0x7fffffff; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d%d , &x, &y); u = f_max(u, y - x); d = f_min(d, y - x); l = f_min(l, x + y); r = f_max(r, x + y); } scanf( %d , &m); int mm; for (i = 1; i <= m; i++) { scanf( %d%d , &x, &y); mm = 0; mm = f_max(mm, u - (y - x)); mm = f_max(mm, (y - x) - d); mm = f_max(mm, r - (x + y)); mm = f_max(mm, (x + y) - l); if (mm < len) { ans = i; len = mm; } } printf( %d n%d n , len, ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k; int a[100005]; int maxans, maxnum; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); int l = 0, r = 0; int curk = k, curans = 0, curnum = 0; while (r < n) { while (r < n && curk >= (long long)curans * (a[r] - curnum)) { curk -= curans * (a[r] - curnum); curans++; curnum = a[r++]; } if (curans > maxans) { maxans = curans; maxnum = curnum; } if (l < r) { curk += curnum - a[l++]; curans--; } if (curans > maxans) { maxans = curans; maxnum = curnum; } } printf( %d %d n , maxans, maxnum); return 0; }
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: small_fifo_test.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module small_fifo_test (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [71:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [71:0] q;
output [2:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "8"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "72"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "72"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "72"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "3"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL data[71..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL q[71..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
// Retrieval info: USED_PORT: usedw 0 0 3 0 OUTPUT NODEFVAL usedw[2..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 3 0 @usedw 0 0 3 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, x1, y1, x2, y2; cin >> n >> m >> x1 >> y1 >> x2 >> y2; int dx = abs(x1 - x2) - 1; int dy = abs(y1 - y2) - 1; if (dx > 3 || dy > 3) { cout << Second << endl; } else if (dx <= 2 && dy <= 2) { cout << First << endl; } else if (dx <= 1 || dy <= 1) { cout << First << endl; } else if (dx < 3 || dy < 3) { cout << Second << endl; } else { cout << Second << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int du[maxn]; set<int> g[maxn]; int b1[maxn], b2[maxn], ans[maxn], vis[maxn]; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); set<pair<int, int> > s; for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); b1[i] = x, b2[i] = y; du[x]++, du[y]++; g[x].insert(y); g[y].insert(x); } for (int i = 1; i <= n; i++) s.insert(make_pair(du[i], i)); for (int i = m - 1; i >= 0; i--) { while (s.size() >= 1) { pair<int, int> itt = (*s.begin()); if (itt.first >= k) break; for (set<int>::iterator it = g[itt.second].begin(); it != g[itt.second].end(); it++) { int u = *it; if (vis[u] == 1) continue; s.erase(make_pair(du[u], u)); du[u]--; s.insert(make_pair(du[u], u)); g[u].erase(itt.second); } s.erase(itt); vis[itt.second] = 1; } ans[i] = s.size(); if (vis[b1[i]] == 0 && vis[b2[i]] == 0) { s.erase(make_pair(du[b1[i]], b1[i])); du[b1[i]]--; s.insert(make_pair(du[b1[i]], b1[i])); g[b1[i]].erase(b2[i]); s.erase(make_pair(du[b2[i]], b2[i])); du[b2[i]]--; s.insert(make_pair(du[b2[i]], b2[i])); g[b2[i]].erase(b1[i]); } } for (int i = 0; i < m; i++) printf( %d n , ans[i]); }
|
module xyz (/*AUTOARG*/
// Outputs
signal_f, signal_c,
// Inputs
signal_e3, signal_b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [2:0] signal_b; // To u_abc of abc.v
input signal_e3; // To u_def of def.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output signal_c; // From u_abc of abc.v
output signal_f; // From u_def of def.v
// End of automatics
/*AUTOWIRE*/
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a (signal_f), // AUTONOHOOKUP
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/
// Outputs
.signal_c (signal_c), // Templated
// Inputs
.signal_a (signal_f), // Templated AUTONOHOOKUP
.signal_b (signal_b[2:0])); // Templated
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d (signal_c), // AUTONOHOOKUP
.signal_e (signal_e), // AUTONOHOOKUP
.signal_e2 (signal_e2), // AUTONOHOOKUP
.signal_e3 ((signal_e3)),
);
*/
def u_def
(/*AUTOINST*/
// Outputs
.signal_f (signal_f), // Templated
// Inputs
.signal_d (signal_c), // Templated AUTONOHOOKUP
.signal_e (signal_e), // Templated AUTONOHOOKUP
.signal_e2 (signal_e2), // Templated AUTONOHOOKUP
.signal_e3 ((signal_e3))); // Templated
endmodule // xyz
module abc (/*AUTOARG*/
// Outputs
signal_c,
// Inputs
signal_a, signal_b
);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/
// Outputs
signal_f,
// Inputs
signal_d, signal_e, signal_e2, signal_e3
);
input [1:0] signal_d;
input [2:0] signal_e;
input [3:0] signal_e2;
input [3:0] signal_e3;
output signal_f;
endmodule // def
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2OI_4_V
`define SKY130_FD_SC_LS__A2BB2OI_4_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2bb2oi_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2OI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_TB_V
`define SKY130_FD_SC_HVL__O22AI_TB_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__o22ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hvl__o22ai dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
sys_clk,
sys_resetn,
// ddr3
ddr3_clk_p,
ddr3_clk_n,
ddr3_a,
ddr3_ba,
ddr3_cke,
ddr3_cs_n,
ddr3_odt,
ddr3_reset_n,
ddr3_we_n,
ddr3_ras_n,
ddr3_cas_n,
ddr3_dqs_p,
ddr3_dqs_n,
ddr3_dq,
ddr3_dm,
ddr3_rzq,
ddr3_ref_clk,
// ethernet
eth_ref_clk,
eth_rxd,
eth_txd,
eth_mdc,
eth_mdio,
eth_resetn,
eth_intn,
// board gpio
gpio_bd,
// lane interface
rx_ref_clk,
rx_sysref,
rx_sync,
rx_data,
tx_ref_clk,
tx_sysref,
tx_sync,
tx_data,
// gpio
trig,
adc_fdb,
adc_fda,
dac_irq,
clkd_status,
adc_pd,
dac_txen,
dac_reset,
clkd_sync,
// spi
spi_csn_clk,
spi_csn_dac,
spi_csn_adc,
spi_clk,
spi_sdio,
spi_dir);
// clock and resets
input sys_clk;
input sys_resetn;
// ddr3
output ddr3_clk_p;
output ddr3_clk_n;
output [ 14:0] ddr3_a;
output [ 2:0] ddr3_ba;
output ddr3_cke;
output ddr3_cs_n;
output ddr3_odt;
output ddr3_reset_n;
output ddr3_we_n;
output ddr3_ras_n;
output ddr3_cas_n;
inout [ 7:0] ddr3_dqs_p;
inout [ 7:0] ddr3_dqs_n;
inout [ 63:0] ddr3_dq;
output [ 7:0] ddr3_dm;
input ddr3_rzq;
input ddr3_ref_clk;
// ethernet
input eth_ref_clk;
input eth_rxd;
output eth_txd;
output eth_mdc;
inout eth_mdio;
output eth_resetn;
input eth_intn;
// board gpio
inout [ 26:0] gpio_bd;
// lane interface
input rx_ref_clk;
input rx_sysref;
output rx_sync;
input [ 3:0] rx_data;
input tx_ref_clk;
input tx_sysref;
input tx_sync;
output [ 3:0] tx_data;
// gpio
input trig;
inout adc_fdb;
inout adc_fda;
inout dac_irq;
inout [ 1:0] clkd_status;
inout adc_pd;
inout dac_txen;
inout dac_reset;
inout clkd_sync;
// spi
output spi_csn_clk;
output spi_csn_dac;
output spi_csn_adc;
output spi_clk;
inout spi_sdio;
output spi_dir;
// internal signals
wire eth_mdio_i;
wire eth_mdio_o;
wire eth_mdio_t;
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire spi_miso_s;
wire spi_mosi_s;
wire [ 7:0] spi_csn_s;
wire xcvr_pll_locked;
wire [ 3:0] xcvr_rx_ready;
wire [ 3:0] xcvr_tx_ready;
// daq2
assign spi_csn_adc = spi_csn_s[2];
assign spi_csn_dac = spi_csn_s[1];
assign spi_csn_clk = spi_csn_s[0];
daq2_spi i_daq2_spi (
.spi_csn (spi_csn_s[2:0]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi_s),
.spi_miso (spi_miso_s),
.spi_sdio (spi_sdio),
.spi_dir (spi_dir));
assign gpio_i[63:60] = xcvr_tx_ready;
assign gpio_i[59:56] = xcvr_rx_ready;
assign gpio_i[55:55] = xcvr_pll_locked;
assign gpio_i[54:44] = 11'd0;
assign gpio_i[43:43] = trig;
assign gpio_i[39:39] = 1'd0;
assign gpio_i[37:37] = 1'd0;
ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
.dio_t ({3'h0, 1'h0, 5'h1f}),
.dio_i ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
.dio_o ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
.dio_p ({ adc_pd, // 42
dac_txen, // 41
dac_reset, // 40
clkd_sync, // 38
adc_fdb, // 36
adc_fda, // 35
dac_irq, // 34
clkd_status})); // 32
// board stuff
assign eth_resetn = 1'b1;
assign eth_mdio_i = eth_mdio;
assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
assign gpio_i[31] = 1'd0;
assign gpio_i[30] = 1'd0;
assign gpio_i[29] = 1'd0;
assign gpio_i[28] = 1'd0;
assign gpio_i[27] = 1'd0;
ad_iobuf #(.DATA_WIDTH(27)) i_iobuf_bd (
.dio_t ({11'h7ff, 16'h0}),
.dio_i (gpio_o[26:0]),
.dio_o (gpio_i[26:0]),
.dio_p (gpio_bd));
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
.sys_ddr3_cntrl_mem_mem_a (ddr3_a),
.sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
.sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
.sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
.sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
.sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
.sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
.sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
.sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
.sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
.sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
.sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
.sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
.sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
.sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
.sys_ethernet_mdio_mdc (eth_mdc),
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_ethernet_ref_clk_clk (eth_ref_clk),
.sys_ethernet_sgmii_rxp_0 (eth_rxd),
.sys_ethernet_sgmii_txp_0 (eth_txd),
.sys_gpio_in_port (gpio_i[63:32]),
.sys_gpio_out_port (gpio_o[63:32]),
.sys_gpio_bd_in_port (gpio_i[31:0]),
.sys_gpio_bd_out_port (gpio_o[31:0]),
.sys_reset_reset_n (sys_resetn),
.sys_spi_MISO (spi_miso_s),
.sys_spi_MOSI (spi_mosi_s),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn_s),
.sys_xcvr_rstcntrl_pll_locked_pll_locked (xcvr_pll_locked),
.sys_xcvr_rstcntrl_rx_ready_rx_ready (xcvr_rx_ready),
.sys_xcvr_rstcntrl_tx_ready_tx_ready (xcvr_tx_ready),
.sys_xcvr_rx_ref_clk_clk (rx_ref_clk),
.sys_xcvr_rx_sync_n_export (rx_sync),
.sys_xcvr_rx_sysref_export (rx_sysref),
.sys_xcvr_rxd_rx_serial_data (rx_data),
.sys_xcvr_tx_ref_clk_clk (tx_ref_clk),
.sys_xcvr_tx_sync_n_export (tx_sync),
.sys_xcvr_tx_sysref_export (tx_sysref),
.sys_xcvr_txd_tx_serial_data (tx_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; bool check(vector<int>& v, int k, int val, int start) { vector<int> dp(v.size()); if (v[0] <= val && start == 0) { dp[0] = dp[1] = 1; } if (v[1] <= val) { dp[1] = 1; } for (int i = 2; i < v.size(); ++i) { dp[i] = dp[i - 1]; if (v[i] <= val) { dp[i] = max(dp[i], 1 + dp[i - 2]); } } int endpos = v.size() - 1; if ((start == 1 && k % 2) || (start == 0 && k % 2 == 0)) { endpos--; } if (dp[endpos] >= (k + 1 - start) / 2) { return true; } return false; } bool checkall(vector<int>& v, int k, int val) { return check(v, k, val, 0) || check(v, k, val, 1); } void solve(std::istream& in, std::ostream& out) { int n, k; in >> n >> k; vector<int> v(n); for (auto& x : v) { in >> x; } int l = 1, r = 1e9 + 1; while (r - l > 1) { int m = (r + l) / 2; if (checkall(v, k, m)) { r = m; } else { l = m; } } if (checkall(v, k, l)) { r = l; } out << r << endl; } int main() { solve(cin, cout); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211AI_4_V
`define SKY130_FD_SC_HS__O211AI_4_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o211ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o211ai_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211AI_4_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e7 + 10; const long long MOD = (long long)(1e9) + (long long)(7); const long double INF = 1e17; long long dp[505][505][12]; long long edge[505][505][4]; int main() { ios::sync_with_stdio(0); cin.tie(0); long long n; cin >> n; vector<long long> v(n); map<long long, long long> cnt; for (auto &it : v) { cin >> it; cnt[it]++; } sort(v.begin(), v.end()); reverse(v.begin(), v.end()); if (n < 4) cout << 0; else { for (int i = 0; i < n; i++) { if (cnt[v[i]] % 2 == 1) { cnt[v[i]]--; cnt[v[i] - 1]++; } } long long ans = 0; bool form = true; long long store = 0; for (long long i = 0; i < n; i++) { long long l = v[i]; while (cnt[l] >= 2) { if (form == true) { form = false; store = l; cnt[l] -= 2; } else { form = true; ans += store * l; store = 0; cnt[l] -= 2; } } } cout << ans; } }
|
#include <bits/stdc++.h> using namespace std; const long long md = 1e9 + 7; long long fe(long long e) { if (e == 0) return 1; long long ans = fe(e / 2); ans = (ans * ans) % md; if (e % 2) ans *= 2; return (ans % md); } int main() { long long x, y; cin >> x >> y; if (y % x) { cout << 0 << endl; return 0; } long long k = y / x; vector<int> pp; long long kk = k; for (long long p = 2; p < 1e5; p++) { if (kk % p == 0) { pp.push_back(p); while (kk % p == 0) kk /= p; } } if (kk > 1) pp.push_back(kk); long long ans = fe(k - 1); int mx = 1 << (int)pp.size(); for (int i = 1; i < mx; i++) { long long p = 1, sgn = 1; for (int j = 0; 1 << j <= i; j++) { if (1 << j & i) { p *= pp[j]; sgn *= -1; } } ans += sgn * fe(k / p - 1); ans %= md; while (ans < 0) ans += md; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } long long int binomialCoeff(long long int n, long long int k) { long long int C[n + 1][k + 1]; long long int i, j; for (i = 0; i <= n; i++) { for (j = 0; j <= min(i, k); j++) { if (j == 0 || j == i) C[i][j] = 1; else C[i][j] = ((C[i - 1][j - 1]) % 998244353 + (C[i - 1][j]) % 998244353) % 998244353; } } return C[n][k]; } long long int digsum(long long int a) { long long int sum = 0; while (a > 0) { sum += a % 10; a = a / 10; } return sum; } long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int fact(int a) { if (a == 1) return a; else return a * fact(a - 1); } int max3(int a, int b, int c) { return max(a, max(b, c)); } int main() { int q; cin >> q; while (q--) { int n; cin >> n; int temp; int each = 0; for (long long int i = 1; i <= n; i++) { cin >> temp; each += temp; } cout << (int)(ceil((double)(each) / (double)(n))) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const long long mod = 1e9 + 7; const long long N = 2e5 + 10; inline long long add(long long x, long long y) { x += y; if (x >= mod) x -= mod; return x; } inline long long mul(long long x, long long y) { x = (1LL * x * y) % mod; return x; } long long first[N]; long long lvl[N]; int32_t main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long n, k; cin >> n >> k; long long maxv = 0; vector<long long> v(n); for (long long i = 0; i <= n - 1; ++i) { cin >> v[i]; first[v[i]]++; maxv = max(maxv, v[i]); } long long ans = INF; for (long long i = 0; i <= maxv; ++i) { queue<long long> q; q.push(i); lvl[i] = 0; long long val = 0; long long cc = 0; while (!q.empty()) { long long x = q.front(); q.pop(); if (cc + first[x] > k) { val += (k - cc) * lvl[x]; cc = k; break; } else { cc += first[x]; val += first[x] * lvl[x]; if (i == 0) { } } if (cc >= k) break; if (2 * x <= 2e5 and x > 0) { q.push(2 * x); lvl[2 * x] = 1 + lvl[x]; } if (2 * x + 1 <= 2e5) { q.push(2 * x + 1); lvl[2 * x + 1] = 1 + lvl[x]; } } if (cc < k) val = INF; ans = min(ans, val); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct p { int s, n; }; int comp(struct p a, struct p b) { return (a.s <= b.s); } int main() { vector<long long> a, sb, s, r; long long i, j, k, n, ss, sss, rrr; cin >> n; s.resize(n + 2, 0); r.resize(n + 2, 0); sb.push_back(0); for (i = 1; i <= n; i++) { cin >> k; a.push_back(k); sb.push_back(sb.back() + k); } ss = sb.back(); if (ss % 3 != 0 || n <= 2) { cout << 0 << endl; return 0; } sss = 0; rrr = 0; for (i = 0; i < n; i++) { if (sss == ss / 3 && i != 0) s[i]++; if (rrr == ss / 3 && i != 0) r[i]++; sss += a[i]; rrr += a[n - i - 1]; s[i + 1] = s[i]; r[i + 1] = r[i]; } long long c = s[0], var = 0; for (i = 1; i < n; i++) { if (s[i] != c) { c = s[i]; var += r[n - i - 1]; } } cout << var << endl; }
|
/*******************************************************************************
* *
* Copyright (C) 2009 Altera Corporation *
* *
* Altera products are protected under numerous U.S. and foreign patents, *
* maskwork rights, copyrights and other intellectual property laws. *
* *
* This reference design file, and your use thereof, is subject to and *
* governed by the terms and conditions of the applicable Altera Reference *
* Design License Agreement (either as signed by you, agreed by you upon *
* download or as a "click-through" agreement upon installation andor found *
* at www.altera.com). By using this reference design file, you indicate your *
* acceptance of such terms and conditions between you and Altera Corporation. *
* In the event that you do not agree with such terms and conditions, you may *
* not use the reference design file and please promptly destroy any copies *
* you have made. *
* *
* This reference design file is being provided on an "as-is" basis and as an *
* accommodation and therefore all warranties, representations or guarantees *
* of any kind (whether express, implied or statutory) including, without *
* limitation, warranties of merchantability, non-infringement, or fitness for *
* a particular purpose, are specifically disclaimed. By making this refer- *
* ence design file available, Altera expressly does not recommend, suggest *
* or require that this reference design file be used in combination with any *
* other product not provided by Altera. *
* *
* Module Name: decoder File Name: decoder.v *
* *
* Module Function: This module implements a decoder. The binary *
* encoded input will be decoded to its corresponding *
* 2**N-bit one-hot output. *
* *
* Modules Used: *
* *
* Parameters and Defines Used: *
* - N : Number of bits of input data *
* - WIDTH : Width of output data *
* *
* Created by: Jim Schwalbe Created on: 08/06/2009 *
* *
* REVISION HISTORY: *
* * Revision 1.0 08/06/2009 Jim Schwalbe *
* - Initial Revision *
* *
******************************************************************************/
module decoder (
encode_in,
data_out
);
parameter WIDTH = 64;
parameter N = log2(WIDTH);
input [N-1:0] encode_in;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
//reg [N-1:0] position;
integer i;
always @(*)
begin
data_out = 0;
data_out = data_out + 2**(encode_in);
end
function integer log2;
input [32:0] depth;
integer j;
begin
log2 = 1;
for (j=0; 2**j < depth; j=j+1)
log2 = j + 1;
end
endfunction // log2
endmodule // decoder
|
#include <bits/stdc++.h> using namespace std; int n, m; int main() { cin >> n >> m; if (m / n == 2) cout << n - m % n; else if (m / n == 1) cout << m % n; else cout << 0; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, ans = 0, xs, ys, xe, ye; char q[105][105]; cin >> n >> m; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cin >> q[i][j]; if (q[i][j] == S ) { xs = i; ys = j; } if (q[i][j] == E ) { xe = i; ye = j; } } } string line; cin >> line; int x, y; for (int w = 0; w <= 3; ++w) { for (int l = 0; l <= 3; ++l) { for (int s = 0; s <= 3; ++s) { for (int r = 0; r <= 3; ++r) { if (w == l || w == s || w == r) { continue; } if (l == s || l == r) { continue; } if (s == r) { continue; } x = xs; y = ys; for (int i = 0; i < line.size(); ++i) { int p = line[i] - 0 ; if (p == w) { x++; if (x >= n) { break; } } if (p == l) { y--; if (y < 0) { break; } } if (p == s) { x--; if (x < 0) { break; } } if (p == r) { y++; if (y >= m) { break; } } if (x == xe && y == ye) { break; } if (q[x][y] == # ) { break; } } if (x == xe && y == ye) { ans++; } } } } } cout << ans << endl; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:58:39 10/16/2015
// Design Name: DFF
// Module Name: /home/steins;gate/IIIT-Delhi/ELD/Assignments/Verilog/Assignment_1/Assign1/test_DFF.v
// Project Name: Assign1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DFF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_DFF;
// Inputs
reg in_D;
reg clk;
reg reset;
// Outputs
wire out_Q;
wire out_QBar;
// Instantiate the Unit Under Test (UUT)
DFF uut (
in_D,
clk,
reset,
out_Q,
out_QBar
);
initial begin
// Initialize Inputs
in_D = 0;
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always begin
#50 in_D = ~in_D;
end
always begin
#10 clk = ~clk;
end
always begin
#251 reset = 1;
#1 reset = 0;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Ryan
//
// Create Date: 06/07/2017
// Module Name: Main Module
// Project Name: Joystick and oLED controller
// Target Devices: ICEStick
// Tool versions: iCEcube2
// Description: This module uses the Digilent PMOD JSTK2 and oLED screens to
// play around with and learn how to interface with serial communications.
// The positional data of the joystick ranges from 0 to 1023 in both the X and Y
// directions. The center LED will illuminate when a button is pressed.
// SPI mode 0 is used for communication between the PmodJSTK and the FPGA.
// SPI mode 3 is used for communication between the PMOD oLED and the FPGA.
//////////////////////////////////////////////////////////////////////////////////
// Top level entity
// ==============================================================================
// Define Module
// ==============================================================================
module Main_Control(
CLK,
RST,
// Status lights
LED,
// OLED screen
CS,
SDIN,
SCLK,
DC,
RES,
VBAT,
VDD,
// Joystick module
JSTK_SS,
JSTK_MOSI,
JSTK_MISO,
JSTK_SCK
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input CLK; // 12Mhz onboard clock
input RST; // reset command, not implemented
output [4:0] LED; // On-board LEDs
// OLED screen signals
output CS;
output SDIN;
output SCLK;
output DC;
output RES;
output VBAT;
output VDD;
// Joystick signals
input JSTK_MISO; // Master In Slave Out
output JSTK_SS; // Slave Select
output JSTK_MOSI; // Master Out Slave In
output JSTK_SCK; // Serial Clock
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
// Signal to send/receive data to/from PMOD peripherals
wire sndRec;
wire sendRec_screen;
// Data read from PmodJSTK
wire [39:0] jstkData;
// Signal carrying joystick X data
wire [9:0] XposData;
// Signal carrying joystick Y data
wire [9:0] YposData;
// Holds data to be sent to PmodJSTK
wire [39:0] sndData;
// Currently selected color for system
wire [23:0] RGBcolor;
// ===========================================================================
// Implementation
// ===========================================================================
//-----------------------------------------------
// PmodOLED Interface
//-----------------------------------------------
PmodOLEDCtrl PmodOLEDCtrl_Int(
.CLK(CLK),
.RST(RST),
.UPDATE(sendRec_screen),
.CS(CS),
.SDIN(SDIN),
.SCLK(SCLK),
.DC(DC),
.RES(RES),
.VBAT(VBAT),
.VDD(VDD),
// Position on the screen
.xpos(XposData),
.ypos(YposData)
);
//-----------------------------------------------
// PmodJSTK Interface
//-----------------------------------------------
PmodJSTK PmodJSTK_Int(
.CLK(CLK),
.RST(RST),
.sndRec(sndRec),
.DIN(sndData),
.MISO(JSTK_MISO),
.SS(JSTK_SS),
.SCLK(JSTK_SCK),
.MOSI(JSTK_MOSI),
.DOUT(jstkData)
);
//-----------------------------------------------
// Cycle colors based on joystick button
//-----------------------------------------------
RGB_color_set Select_Color(
.clk(CLK),
.button(jstkData[1:0]),
.RGBcolor(RGBcolor)
);
//-----------------------------------------------
// System update timing Generator
//-----------------------------------------------
ClkDiv_20Hz genSndRec(
.CLK(CLK),
.RST(RST),
.CLKOUT(sndRec),
.CLKOUTn(sendRec_screen)
);
//-----------------------------------------------
// Report joystick shit on on-board LEDs
//-----------------------------------------------
LED_joystick boardLEDcontroller(
.color(RGBcolor),
.button(jstkData[1:0]),
.LED(LED)
);
//-----------------------------------------------
// Assignments
//-----------------------------------------------
// Collect joystick state for position state
assign YposData = {jstkData[25:24], jstkData[39:32]};
assign XposData = {jstkData[9:8], jstkData[23:16]};
// Data to be sent to PmodJSTK, first byte is the command to control RGB on PmodJSTK
assign sndData = {8'b10000100, RGBcolor, 8'b00000000};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int intersection = n * m; int turn = 0; while (n > 1 && m > 1) { intersection -= (n + m - 1); n--; m--; turn++; } if (n == 1 && m == 1 && turn % 2 == 0) { cout << Akshat << endl; } else if (n == 1 && m == 1 && turn % 2 != 0) { cout << Malvika << endl; } else if ((n != 1 || m != 1) && turn % 2 == 0) { cout << Akshat << endl; } else { cout << Malvika << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void umax(T &a, T b) { if (a < b) a = b; } template <class T> inline void umin(T &a, T b) { if (a > b) a = b; } template <class T> inline T abs(T a) { return a > 0 ? a : -a; } template <class T> inline T gcd(T a, T b) { return __gcd(a, b); } template <class T> inline T lcm(T a, T b) { return a / gcd(a, b) * b; } long long modpow(long long a, long long n, long long temp) { long long res = 1, y = a; while (n > 0) { if (n & 1) res = (res * y) % temp; y = (y * y) % temp; n /= 2; } return res % temp; } long long ison(long long mask, long long pos) { return (mask & (1 << pos)); } long long cbit(long long n) { long long k = 0; while (n) n &= (n - 1), k++; return k; } long long nbit(long long n) { long long k = 0; while (n) n /= 2, k++; return k; } long long mod = 1e9 + 7; int sgn(long long x) { return x < 0 ? -1 : !!x; } long long xo(long long i) { if ((i & 3) == 0) return i; if ((i & 3) == 1) return 1; if ((i & 3) == 2) return i + 1; return 0; } long long a[200005]; int main() { long long n, i, j, k, l, m, ans = 0; long long pr = 0; cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; for (i = 1; i <= n; i++) { if (a[i] != pr) { ans += abs(a[i] - pr); pr = a[i]; } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; if (n == 47 || n == 74 || n == 477 || n == 477) cout << YES ; else if (n % 4 == 0 || n % 7 == 0 || n % 47 == 0) cout << YES ; else cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0), cin.tie(), cout.tie(); bool w = false; int cnt = 0; string s; cin >> s; for (int i = 0; i < s.size(); i++) { int zero = 0, one = 0; if (w && s[i] == 0 ) { cout << 1 << << 1 << endl; w = false; } else if (s[i] == 0 ) { cout << 3 << << 1 << endl; w = true; } else { cout << 4 - cnt << << 2 << endl; cnt++; if (cnt == 4) cnt = 0; } } return 0; }
|
/*
########################################################################
EPIPHANY eMesh Arbiter
########################################################################
This block takes three FIFO inputs (write, read request, read response)
and the DMA channel, arbitrates between the active channels, and forwards
the result to the transmit output pins.
Arbitration Priority:
1) read responses (highest)
2) host writes
3) read requests from host (lowest)
*/
module etx_arbiter (/*AUTOARG*/
// Outputs
txwr_wait, txrd_wait, txrr_wait, etx_access, cfg_access,
etx_packet,
// Inputs
clk, nreset, txwr_access, txwr_packet, txrd_access, txrd_packet,
txrr_access, txrr_packet, etx_wait, etx_cfg_wait
);
parameter AW = 32;
parameter PW = 2*AW+40;
parameter ID = 0;
//tx clock and reset
input clk;
input nreset;
//Write Request (from slave)
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Request (from slave)
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Read Response (from master)
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Wait signal inputs
input etx_wait;
input etx_cfg_wait;
//Outgoing transaction
output etx_access; //for IO
output cfg_access; //for RX/RX configuration
output [PW-1:0] etx_packet;
//regs
reg etx_access;
reg [PW-1:0] etx_packet;
reg cfg_access; //config access
reg [PW-1:0] cfg_packet; //config packet
//wires
wire [3:0] txrd_ctrlmode;
wire [3:0] txwr_ctrlmode;
wire access_in;
wire [PW-1:0] etx_packet_mux;
wire txrr_grant;
wire txrd_grant;
wire txwr_grant;
wire [PW-1:0] etx_mux;
wire [31:0] dstaddr_mux;
//########################################################################
//# Arbiter
//########################################################################
//TODO: change to round robin!!! (live lock hazard)
oh_arbiter #(.N(3)) arbiter (.grants({txrd_grant,
txwr_grant, //highest priority
txrr_grant
}),
.requests({txrd_access,
txwr_access,
txrr_access
})
);
oh_mux3 #(.DW(PW))
mux3(.out (etx_mux[PW-1:0]),
.in0 (txwr_packet[PW-1:0]),.sel0 (txwr_grant),
.in1 (txrd_packet[PW-1:0]),.sel1 (txrd_grant),
.in2 (txrr_packet[PW-1:0]),.sel2 (txrr_grant)
);
//######################################################################
//Pushback (stall) Signals
//######################################################################
assign etx_all_wait = (etx_wait & ~cfg_match) |
(etx_cfg_wait & cfg_match);
//Read response
assign txrr_wait = etx_all_wait;
//Write waits on pin wr wait or cfg_wait
assign txwr_wait = etx_all_wait |
txrr_access;
//Host read request (self throttling, one read at a time)
assign txrd_wait = etx_all_wait |
txrr_access |
txwr_access;
//#####################################################################
//# Pipeline stage (arbiter+mux takes time..)
//#####################################################################
assign access_in = txwr_grant |
txrd_grant |
txrr_grant;
/* assign access_in = (txwr_grant & ~txwr_wait) |
(txrd_grant & ~txrd_wait) |
(txrr_grant & ~txrr_wait);
*/
packet2emesh #(.AW(AW))
p2e (.write_in (),
.datamode_in (),
.ctrlmode_in (),
.dstaddr_in (dstaddr_mux[31:0]),
.srcaddr_in (),
.data_in (),
.packet_in (etx_mux[PW-1:0]));
assign cfg_match = (dstaddr_mux[31:20]==ID);
//access decode
always @ (posedge clk)
if (!nreset)
etx_access <= 1'b0;
else if (~etx_wait)
//for loopback, send cfg to RX (mostly for mailbox)
etx_access <= access_in & ~cfg_match;
//config access
always @ (posedge clk)
if (!nreset)
cfg_access <= 1'b0;
else if (~etx_cfg_wait)
cfg_access <= (txwr_grant | txrd_grant) & cfg_match;
//packet
always @ (posedge clk)
if (access_in & ~etx_all_wait)
etx_packet[PW-1:0] <= etx_mux[PW-1:0];
endmodule // etx_arbiter
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End:
|
#include <bits/stdc++.h> const int N = 100005; long long a[N], s[N]; long long max; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %I64d , &a[i]); } std::sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) { s[i] = s[i - 1] + a[i]; max += s[i]; } int m, k; scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d , &k); if (i) putchar( ); if (k == 1) printf( %I64d n , max - s[n]); else { long long ans = 0, t = n - 1, d = 1; while (t >= 0) { ans += s[t]; d *= k; t -= d; } printf( %I64d , ans); } } puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void smn(T &a, const T &b) { if (b < a) a = b; } template <class T> inline void smx(T &a, const T &b) { if (b > a) a = b; } template <class T> inline T gcd(T x, T y) { return y ? gcd(y, x % y) : x; } namespace std { template <class T, class U> struct hash<pair<T, U>> { inline size_t operator()(const pair<T, U> &p) const { return hash<T>()(p.first) * 701 + hash<U>()(p.second); } }; } // namespace std const double eps = 1e-8; const int key = 701; const int MN = 1000 * 1000 + 1000; string s; long long h1[MN], pw1[MN], h2[MN], pw2[MN]; const int MOD = 1000 * 1000 * 1000 + 7; long long add[MN]; int n, k; pair<long long, long long> get(int s, int e) { long long res1 = h1[e]; if (s != 0) res1 -= pw1[e - s + 1] * h1[s - 1]; long long res2 = h2[e]; if (s != 0) res2 -= pw2[e - s + 1] * h2[s - 1], res2 %= MOD; if (res2 < 0) res2 += MOD; return make_pair(res1, res2); } bool check(int l) { auto v = get(0, l - 1); int now = l; for (int i = 1; i < k; i++) { if (get(now, now + l - 1) != v) return 0; now += l; } return 1; } int fnd(int p) { int s = 1, e = n - p, res = 0; while (s <= e) { int m = (s + e) / 2; if (get(0, m - 1) == get(p, p + m - 1)) res = m, s = m + 1; else e = m - 1; } return res; } int main() { ios_base::sync_with_stdio(false); cin >> n >> k >> s; long long now = 0; for (int i = 0; i < n; i++) now = now * 701 + s[i], h1[i] = now; pw1[0] = 1; for (int i = 1; i <= n; i++) pw1[i] = 701 * pw1[i - 1]; now = 0; for (int i = 0; i < n; i++) now = (now * 701 + s[i]) % MOD, h2[i] = now; pw2[0] = 1; for (int i = 1; i <= n; i++) pw2[i] = (701 * pw2[i - 1]) % MOD; for (int i = 1; i <= n; i++) if (n / i >= k && check(i)) { int t = i * k; int b = fnd(t); smn(b, i); add[t - 1] += 1; add[t + b] += -1; } now = 0; for (int i = 0; i < n; i++) { now += add[i]; cout << (now ? 1 : 0); } cout << n ; return 0; }
|
`timescale 1ns / 1ps
`include "./MPU6050_defines.v"
module MPU6050
(
input clk,
input rst,
inout scl,
inout sda,
output reg [15:0] accel_z,
output reg valid,
output reg error
);
integer i;
localparam [4:0] INIT_REG_STATE = 0;
localparam [4:0] READ_ACCEL_Z_STATE = 4;
localparam [4:0] IDLE_STATE = 5;
localparam [4:0] ERROR_STATE = 6;
reg [4:0] state = 0;
localparam [4:0] REG_RAM_LEN = 16;
reg [7:0] REG_ADDR_RAM [0:REG_RAM_LEN-1];
reg [7:0] REG_VALUE_RAM [0:REG_RAM_LEN-1];
reg [4:0] counter = 0;
localparam [27:0] IDLE_COUNT = 28'd100000;
reg [27:0] idle_counter = 0;
reg mpu_start = 0;
reg mpu_rd_wr = 0;
reg [7:0] mpu_wr_data = 0;
wire mpu_busy;
reg mpu_prev_busy;
reg [7:0] mpu_reg_addr;
wire [7:0] mpu_rd_data;
I2CMasterTop #( .DEVICE_ADDR( 7'b1101000 ))
mpu ( .clk( clk ),
.rst( rst ),
.start( mpu_start ),
.rd_wr( mpu_rd_wr ),
.reg_addr( mpu_reg_addr ),
.wr_data( mpu_wr_data ),
.rd_data( mpu_rd_data ),
.busy( mpu_busy ),
.scl( scl ),
.sda( sda ));
initial begin
//Disabling sleep mode
for(i = 0; i < REG_RAM_LEN-1; i=i+1) begin
REG_ADDR_RAM[i] <= `MPU6050_RA_PWR_MGMT_1;
REG_VALUE_RAM[i] <= 8'h00;
end
//Set the scale to +-8G
REG_ADDR_RAM[REG_RAM_LEN-1] <= `MPU6050_RA_ACCEL_CONFIG;
REG_VALUE_RAM[REG_RAM_LEN-1] <= 8'b00011000;
end
always @ (posedge clk) begin
mpu_prev_busy <= mpu_busy;
if( rst ) begin
accel_z <= 0;
valid <= 0;
error <= 0;
mpu_start <= 0;
mpu_rd_wr <= 0;
mpu_reg_addr <= 0;
mpu_wr_data <= 0;
counter <= 0;
idle_counter <= 0;
state <= INIT_REG_STATE;
end else begin
case( state )
//Do nothing more for now; Later could restart
ERROR_STATE : begin
state <= READ_ACCEL_Z_STATE;
end
INIT_REG_STATE : begin
//If MPU is busy, then wait until available
if(mpu_busy) begin
mpu_start <= 0;
//If just started or MPU just became available, send next register data
end else if( (counter == 0) | (mpu_prev_busy & ~mpu_busy) ) begin
if ( counter == REG_RAM_LEN ) begin
counter <= 0;
state <= READ_ACCEL_Z_STATE;
end else begin
mpu_start <= 1;
mpu_rd_wr <= 0;
mpu_reg_addr <= REG_ADDR_RAM[counter];
mpu_wr_data <= REG_VALUE_RAM[counter];
counter <= counter + 1;
end
end
end
READ_ACCEL_Z_STATE : begin
//If MPU is busy, then wait until available
if(mpu_busy) begin
mpu_start <= 0;
//If just started or MPU just became available, send next register data
end else if( (counter == 0) | (mpu_prev_busy & ~mpu_busy) ) begin
case( counter )
0 :
begin
mpu_start <= 1;
mpu_rd_wr <= 1;
mpu_reg_addr <= `MPU6050_RA_ACCEL_ZOUT_H;
counter <= counter + 1;
end
1 :
begin
mpu_start <= 1;
mpu_rd_wr <= 1;
mpu_reg_addr <= `MPU6050_RA_ACCEL_ZOUT_L;
counter <= counter + 1;
accel_z <= {8'b00000000, mpu_rd_data};
end
2 :
begin
mpu_start <= 0;
counter <= 0;
accel_z <= {accel_z[7:0], mpu_rd_data};
state <= IDLE_STATE;
valid <= 1;
end
endcase
end
end
IDLE_STATE : begin
if(idle_counter >= IDLE_COUNT) begin
valid <= 0;
idle_counter <= 0;
state <= READ_ACCEL_Z_STATE;
end else begin
idle_counter <= idle_counter + 1;
end
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGRBP_SYMBOL_V
`define SKY130_FD_SC_LP__SREGRBP_SYMBOL_V
/**
* sregrbp: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sregrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{scanchain|Scan Chain}}
input ASYNC,
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGRBP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; double dp[100002]; int main() { double res = 0, prob = 0; int n; cin >> n; dp[0] = 0; for (int i = 0; i < n; i++) { double p; cin >> p; dp[i] = dp[i - 1] * p; res = res + p + dp[i] * 2.0; dp[i] += p; } printf( %.7lf n , res); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 200005; template <typename T> inline void read(T &AKNOI) { T x = 0, flag = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) flag = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } AKNOI = flag * x; } template <typename T> inline void cmin(T &x, T y) { if (x > y) x = y; } template <typename T> inline void cmax(T &x, T y) { if (x < y) x = y; } int n, cnt[MAXN], pos; int vis[MAXN], siz[MAXN], son[MAXN], tsiz, root; long long dis[MAXN]; double sum[MAXN], sq, cur, ans; struct Edge { int v, w, nxt; } e[MAXN << 1]; int first[MAXN], eCnt; inline void AddEdge(int u, int v, int w) { e[++eCnt].v = v; e[eCnt].w = w; e[eCnt].nxt = first[u]; first[u] = eCnt; } void GetRoot(int u, int fa) { siz[u] = 1; son[u] = 0; for (int i = first[u]; i; i = e[i].nxt) { int v = e[i].v; if (v == fa || vis[v]) continue; GetRoot(v, u); cmax(son[u], siz[v]); siz[u] += siz[v]; } cmax(son[u], tsiz - siz[u]); if (son[u] < son[root]) root = u; } void GetCost(int u, int fa) { sq = sqrt(dis[u]) * cnt[u]; sum[u] = sq; cur += sq * dis[u]; for (int i = first[u]; i; i = e[i].nxt) { int v = e[i].v; if (v == fa) continue; dis[v] = dis[u] + e[i].w; GetCost(v, u); sum[u] += sum[v]; } } void PointDC(int u) { vis[u] = 1; cur = dis[u] = 0; GetCost(u, 0); if (cur < ans) { ans = cur; pos = u; } for (int i = first[u]; i; i = e[i].nxt) { int v = e[i].v; if (vis[v]) continue; if (sum[u] < sum[v] * 2) { tsiz = siz[v]; root = 0; GetRoot(v, 0); PointDC(root); break; } } } void init() { read(n); for (int i = 1; i <= n; ++i) { read(cnt[i]); } for (int i = 1, u, v, w; i < n; ++i) { read(u); read(v); read(w); AddEdge(u, v, w); AddEdge(v, u, w); } } void solve() { ans = 1e30; son[0] = tsiz = n; GetRoot(1, 0); PointDC(root); printf( %d %.8lf n , pos, ans); } int main() { init(); solve(); return 0; }
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//-----------------------------------------------------------------------------
// The way that we connect things when transmitting a command to an ISO
// 15693 tag, using 100% modulation only for now.
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module hi_read_tx(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
shallow_modulation
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input shallow_modulation;
// low frequency outputs, not relevant
assign pwr_lo = 1'b0;
assign pwr_oe2 = 1'b0;
// The high-frequency stuff. For now, for testing, just bring out the carrier,
// and allow the ARM to modulate it over the SSP.
reg pwr_hi;
reg pwr_oe1;
reg pwr_oe3;
reg pwr_oe4;
always @(ck_1356megb or ssp_dout or shallow_modulation)
begin
if(shallow_modulation)
begin
pwr_hi <= ck_1356megb;
pwr_oe1 <= 1'b0;
pwr_oe3 <= 1'b0;
pwr_oe4 <= ~ssp_dout;
end
else
begin
pwr_hi <= ck_1356megb & ssp_dout;
pwr_oe1 <= 1'b0;
pwr_oe3 <= 1'b0;
pwr_oe4 <= 1'b0;
end
end
// Then just divide the 13.56 MHz clock down to produce appropriate clocks
// for the synchronous serial port.
reg [6:0] hi_div_by_128;
always @(posedge ck_1356meg)
hi_div_by_128 <= hi_div_by_128 + 1;
assign ssp_clk = hi_div_by_128[6];
reg [2:0] hi_byte_div;
always @(negedge ssp_clk)
hi_byte_div <= hi_byte_div + 1;
assign ssp_frame = (hi_byte_div == 3'b000);
// Implement a hysteresis to give out the received signal on
// ssp_din. Sample at fc.
assign adc_clk = ck_1356meg;
// ADC data appears on the rising edge, so sample it on the falling edge
reg after_hysteresis;
always @(negedge adc_clk)
begin
if(& adc_d[7:0]) after_hysteresis <= 1'b1;
else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
end
assign ssp_din = after_hysteresis;
assign dbg = ssp_din;
endmodule
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "distributed" *) module CvtColor_1_sectorocq_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 2;
parameter AWIDTH = 3;
parameter MEM_SIZE = 6;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./CvtColor_1_sectorocq_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module CvtColor_1_sectorocq(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd6;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
CvtColor_1_sectorocq_rom CvtColor_1_sectorocq_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
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