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#include <bits/stdc++.h> using namespace std; const int mod = 998244353, N = 510; int n, m, a[N], st[N][12], g[N][12], dp[N][N]; int solve(int l, int r) { if (dp[l][r]) return dp[l][r]; if (l > r) return 1; long long r1 = 0, r2 = 0; int pos, lo = log2(r - l + 1); if (st[l][lo] < st[r - (1 << lo) + 1][lo]) pos = g[l][lo]; else pos = g[r - (1 << lo) + 1][lo]; for (int i = l; i <= pos; i++) r1 += 1ll * solve(l, i - 1) * solve(i, pos - 1) % mod; for (int i = pos; i <= r; i++) r2 += 1ll * solve(pos + 1, i) * solve(i + 1, r) % mod; r1 %= mod; r2 %= mod; return dp[l][r] = 1ll * r1 * r2 % mod; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), st[i][0] = a[i], g[i][0] = i; for (int i = 1; (1 << i) <= n; i++) { for (int j = 1; j + (1 << i) - 1 <= n; j++) { int y = j + (1 << (i - 1)); if (st[j][i - 1] < st[y][i - 1]) g[j][i] = g[j][i - 1]; else g[j][i] = g[y][i - 1]; st[j][i] = min(st[j][i - 1], st[y][i - 1]); } } printf( %d n , solve(1, n)); return 0; }
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/*
*
*12bit PWM analog output module.
*Interface bit width is 16bit stereo.
*Input source require dcfifo altera megafunction.
*Clock input 196.608MHz, Output Sampling Frequency 48kHz.
*
*/
module pwm_out(
input wire clk,
input wire reset_n,
output reg fifo_rdreq,
input wire fifo_empty,
input wire [31:0] fifo_data,
output wire pwm_out_l,
output wire pwm_out_r);
reg data_rdy;
reg [11:0] pwm_timer;
reg [31:0] audiodata_32, audiodata_32_p;
always @(posedge clk, negedge reset_n)
begin
if(!reset_n)
begin
pwm_timer <= 0;
fifo_rdreq <= 0;
audiodata_32 <= 0;
audiodata_32_p <= 0;
data_rdy <= 0;
end
else
begin
pwm_timer <= pwm_timer + 1'b1;
if(pwm_timer == 12'h800 && fifo_empty == 0)
begin
fifo_rdreq <= 1'b1;
end
if(pwm_timer == 12'h801 && fifo_rdreq == 1)
begin
fifo_rdreq <= 0;
audiodata_32_p <= fifo_data;
data_rdy <= 1'b1;
end
if(pwm_timer == 12'hfff && data_rdy == 1)
begin
audiodata_32 <= audiodata_32_p;
data_rdy <= 0;
end
end
end
assign pwm_out_l = (pwm_timer <= audiodata_32[15:4]) ? 1'b1 :
(pwm_timer > audiodata_32[15:4]) ? 1'b0 : 1'bx;
assign pwm_out_r = (pwm_timer <= audiodata_32[31:20]) ? 1'b1 :
(pwm_timer > audiodata_32[31:20]) ? 1'b0 : 1'bx;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { string s; int n, a; while (cin >> s >> n) { a = s.length(); if (a % n != 0) cout << NO << endl; else { int b, c = 0; b = a / n; for (int i = 0; i < a; i += b) { for (int j = 0; j < b / 2; j++) { if (s[i + j] != s[i + b - j - 1]) { c = 1; break; } } if (c == 1) break; } if (c == 1) cout << NO << endl; else cout << YES << endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<long long> v; bitset<101> usado; long long dfs(long long nodo) { if (usado[nodo]) return 0; usado.set(nodo); return 1 + dfs(v[nodo]); } long long calcmcd(long long a, long long b) { if (a % b == 0) return b; return calcmcd(b, a % b); } int main() { ios::sync_with_stdio(false); bool puede = true; long long n, aux, resp, mcd, mcm; vector<long long> pararesp; cin >> n; v.resize(n + 1); for (long long i = 1; i <= n; i++) { cin >> v[i]; if (usado[v[i]]) puede = false; else usado.set(v[i]); } if (puede) { usado.reset(); for (long long i = 1; i <= n; i++) { while (i <= n && (usado[i] || v[i] == i)) i++; if (i <= n) { aux = dfs(i); if (aux % 2 == 0) aux /= 2; pararesp.push_back(aux); } } if (pararesp.empty()) resp = 1; else { if (pararesp.size() == 1) resp = pararesp[0]; else { mcm = pararesp[pararesp.size() - 1]; for (int i = pararesp.size() - 2; i >= 0; i--) { if (pararesp[i] > mcm) mcd = calcmcd(pararesp[i], mcm); else mcd = calcmcd(mcm, pararesp[i]); mcm = mcm * pararesp[i] / mcd; } resp = mcm; pararesp.clear(); } } cout << resp << n ; } else cout << -1 n ; v.clear(); return 0; }
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#include <bits/stdc++.h> using namespace std; bool cmp(pair<long long, long long> a, pair<long long, long long> b) { if (a.first != b.first) { return a.first < b.first; } return a.second > b.second; } const int maxn = (int)1e7; struct vt { int ed[2]; bool term; vt() { ed[0] = ed[1] = -1; term = false; } }; vt mas[maxn]; int posit = 0; int my_new() { if (posit == maxn) { throw 1; } return posit++; } void add(int t, long long x, int b, int mb) { if (b == mb) { mas[t].term = true; return; } int c = (x >> b) & 1; if (mas[t].ed[c] == -1) { mas[t].ed[c] = my_new(); } add(mas[t].ed[c], x, b - 1, mb); } void make(vector<pair<long long, long long> > &a) { sort(a.begin(), a.end(), cmp); long long rm = -1; vector<pair<long long, long long> > res; for (int i = 0; i < (int)a.size(); i++) { if (a[i].second <= rm) { continue; } else { rm = a[i].second; res.push_back(a[i]); } } a = res; } int t; void calc(long long la, long long ra, long long lb, long long rb) { add(t, la ^ lb, 59, -1); add(t, ra ^ rb, 59, -1); add(t, la ^ rb, 59, -1); add(t, ra ^ lb, 59, -1); for (int b = 59; b >= 0; b--) { long long lx = (la >> b); long long ly = (lb >> b); long long rx = (ra >> b); long long ry = (rb >> b); if (lx != rx && (lx + 1) != rx) { if ((lx & 1) == 0) { add(t, ((lx + 1) ^ ly) << b, 59, b - 1); add(t, ((lx + 1) ^ ry) << b, 59, b - 1); } if ((rx & 1) == 1) { add(t, ((rx - 1) ^ ly) << b, 59, b - 1); add(t, ((rx - 1) ^ ry) << b, 59, b - 1); } } if (ly != ry && (ly + 1) != ry) { if ((ly & 1) == 0) { add(t, (lx ^ (ly + 1)) << b, 59, b - 1); add(t, (rx ^ (ly + 1)) << b, 59, b - 1); } if (ry & 1) { add(t, (lx ^ (ry - 1)) << b, 59, b - 1); add(t, (rx ^ (ry - 1)) << b, 59, b - 1); } } if (lx != rx && (lx + 1) != rx && ly != ry && (ly + 1) != ry) { if ((lx & 1) == 0 && (ly & 1) == 0) { add(t, ((lx + 1) ^ (ly + 1)) << b, 59, b - 1); } if ((lx & 1) == 0 && (ry & 1) == 1) { add(t, ((lx + 1) ^ (ry - 1)) << b, 59, b - 1); } if ((rx & 1) == 1) { if ((ly & 1) == 0) { add(t, ((rx - 1) ^ (ly + 1)) << b, 59, b - 1); } if ((ry & 1) == 1) { add(t, ((rx - 1) ^ (ry - 1)) << b, 59, b - 1); } } } } } const int mod = 998244353; const int maxlog = 135; int st[maxlog]; int build(int t, int b, long long x) { if (mas[t].term) { int y = x % mod; y = (long long)y * st[b + 1] % mod; int ans = (long long)y * st[b + 1] % mod; ans += (long long)st[b] * (st[b + 1] - 1) % mod; ans %= mod; if (ans < 0) { ans += mod; } return ans; } int ans = 0; if (mas[t].ed[0] != -1) { ans = build(mas[t].ed[0], b - 1, x << 1); } if (mas[t].ed[1] != -1) { ans += build(mas[t].ed[1], b - 1, (x << 1) + 1); if (ans >= mod) { ans -= mod; } } return ans; } signed main() { t = my_new(); int n; cin >> n; vector<pair<long long, long long> > a(n); for (int i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; } int m; cin >> m; vector<pair<long long, long long> > b(m); for (int i = 0; i < m; i++) { cin >> b[i].first >> b[i].second; } make(a); make(b); n = (int)a.size(); m = (int)b.size(); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { calc(a[i].first, a[i].second, b[j].first, b[j].second); } } st[0] = 1; for (int i = 1; i < maxlog; i++) { st[i] = st[i - 1] * 2 % mod; } int ans = build(t, 59, 0); cout << ans << endl; }
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; template <typename T, typename TT> inline ostream &operator<<(ostream &os, const pair<T, TT> &t) { return os << t.first << << t.second; } template <typename T> inline ostream &operator<<(ostream &os, const vector<T> &t) { for (auto i : t) os << i << ; return os; } template <typename T> inline istream &operator>>(istream &is, vector<T> &v) { for (T &t : v) is >> t; return is; } template <typename T1, typename T2> inline istream &operator>>(istream &is, pair<T1, T2> &t) { is >> t.first >> t.second; return is; } const long long mod = 1e9 + 7; void solve() { int n; cin >> n; vector<int> v(n); cin >> v; int mn = *min_element(v.begin(), v.end()), c = n - count(v.begin(), v.end(), mn); if (c >= n / 2) cout << Alice << n ; else cout << Bob << n ; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); ; int T = 1; while (T--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int n; int main() { cin >> n; int ans = 0; if (n % 2 == 0) { ans = 3 * (n / 2); } else { ans = 3 * (n / 2) + 1; } cout << ans << endl; for (int i = 1; i <= n; i++) { if (!(i % 2)) cout << i << ; } for (int i = 1; i <= n; i++) { if (i % 2) cout << i << ; } for (int i = 1; i <= n; i++) { if (!(i % 2)) cout << i << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; map<string, int> m; int dis(string s1, string s2) { return (m[s2] - m[s1] + 12) % 12; } int main() { string s1, s2, s3; m[ C ] = 0; m[ C# ] = 1; m[ D ] = 2; m[ D# ] = 3; m[ E ] = 4; m[ F ] = 5; m[ F# ] = 6; m[ G ] = 7; m[ G# ] = 8; m[ A ] = 9; m[ B ] = 10; m[ H ] = 11; cin >> s1 >> s2 >> s3; if ((dis(s1, s2) == 4 && dis(s2, s3) == 3) || (dis(s1, s3) == 4 && dis(s3, s2) == 3) || (dis(s2, s1) == 4 && dis(s1, s3) == 3) || (dis(s2, s3) == 4 && dis(s3, s1) == 3) || (dis(s3, s1) == 4 && dis(s1, s2) == 3) || (dis(s3, s2) == 4 && dis(s2, s1) == 3)) cout << major n ; else if ((dis(s1, s2) == 3 && dis(s2, s3) == 4) || (dis(s1, s3) == 3 && dis(s3, s2) == 4) || (dis(s2, s1) == 3 && dis(s1, s3) == 4) || (dis(s2, s3) == 3 && dis(s3, s1) == 4) || (dis(s3, s1) == 3 && dis(s1, s2) == 4) || (dis(s3, s2) == 3 && dis(s2, s1) == 4)) cout << minor n ; else cout << strange n ; }
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#include <bits/stdc++.h> using namespace std; int n; int m; int a[1 << 7]; int min_k, max_k; bool ok(int ask) { int need = 0; for (int i = 0; i < n; i++) { if (a[i] > ask) { return false; } if (ask > a[i]) { need += ask - a[i]; } } if (need >= m) { return true; } return false; } void read(void) { cin >> n; cin >> m; for (int i = 0; i < n; i++) { cin >> a[i]; } } void solve(void) { for (int i = 0; i < n; i++) { max_k = max(max_k, a[i] + m); } for (int k = 1; k <= 10100; k++) { if (ok(k)) { min_k = k; break; } } } void print(void) { cout << min_k << << max_k << endl; } int main() { read(); solve(); print(); return 0; }
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// 4-Digit Seven Segment Display, Addressed by Digit Index, Individual Enable / Digit.
module digits(
mclk,
enable,
values,
seg,
digit
);
// Input
input wire mclk;
input wire[3:0] enable;
input wire[15:0] values;
// Output
output reg[6:0] seg = 8'b1111111;
output reg[3:0] digit = 4'b1111;
// State
reg[14:0] counter = 0;
reg clk1khz_src = 0;
reg[1:0] index;
// Interconnect
wire clk1khz;
wire[3:0] number;
// Modules
BUFG clk1khz_bufg(
.I(clk1khz_src),
.O(clk1khz)
);
// Combinational
assign number =
(index == 0) ? values[3:0] :
(index == 1) ? values[7:4] :
(index == 2) ? values[11:8] :
values[15:12];
// Process
always @ (posedge mclk) begin: khz_counter
if(counter == 24999) begin
counter <= 0;
clk1khz_src <= ~clk1khz_src;
end else begin
counter <= counter + 1;
end
end
always @ (posedge clk1khz) begin: seg_display
index <= index + 1;
case(index)
0 : digit = {3'b111, ~enable[0]};
1 : digit = {2'b11, ~enable[1], 1'b1};
2 : digit = {1'b1, ~enable[2], 2'b11};
3 : digit = {~enable[3], 3'b111};
default: digit = 4'b1111;
endcase
case(number)
'h0 : seg <= ~(7'b0111111);
'h1 : seg <= ~(7'b0000110);
'h2 : seg <= ~(7'b1011011);
'h3 : seg <= ~(7'b1001111);
'h4 : seg <= ~(7'b1100110);
'h5 : seg <= ~(7'b1101101);
'h6 : seg <= ~(7'b1111101);
'h7 : seg <= ~(7'b0000111);
'h8 : seg <= ~(7'b1111111);
'h9 : seg <= ~(7'b1101111);
'hA : seg <= ~(7'b1110111);
'hB : seg <= ~(7'b1111100);
'hC : seg <= ~(7'b0111001);
'hD : seg <= ~(7'b1011110);
'hE : seg <= ~(7'b1111001);
'hF : seg <= ~(7'b1110001);
default : seg <= ~(7'b0000000);
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int n0 = 1503, inf = 1e9; int n, s, m, k, a[n0], b[n0], p[n0], L[n0]; int dp[2][n0], mx[n0], best[n0]; int num(int pos) { for (int i = 1; i <= n; i++) { p[i] = p[i - 1] + (a[i] <= b[pos]); } memset(&dp, -0x3f, sizeof(dp)); int res = 0; for (int i = 1; i <= m; i++) { dp[(i - 1) & 1][0] = 0; mx[0] = dp[(i - 1) & 1][0]; for (int j = 1; j <= n; j++) { mx[j] = max(mx[j - 1], dp[(i - 1) & 1][j]); if (L[j] != n0) { if (best[j] != -1) dp[i & 1][j] = dp[(i - 1) & 1][best[j]] - p[best[j]] + p[j]; dp[i & 1][j] = max(dp[i & 1][j], mx[L[j] - 1] + p[j] - p[L[j] - 1]); if (i == m) res = max(res, dp[i & 1][j]); } } } return res; } int main() { ios_base::sync_with_stdio(0), cin.tie(0); cin >> n >> s >> m >> k; for (int i = 1; i <= n; i++) cin >> a[i], b[i] = a[i], L[i] = n0; sort(b + 1, b + n + 1); for (int i = 0; i < s; i++) { int l, r; cin >> l >> r; L[r] = min(L[r], l); } for (int i = 1; i <= n; i++) { best[i] = -1; for (int j = L[i]; j < i; j++) { if (best[i] == -1 || L[j] < L[best[i]]) best[i] = j; } } int l = 0, r = n + 1; while (l < r - 1) { int mid = l + r >> 1; if (num(mid) >= k) r = mid; else l = mid; } if (r == n + 1) cout << -1; else cout << b[r]; }
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#include <bits/stdc++.h> using namespace std; int32_t main() { long long t; cin >> t; while (t--) { long long n; cin >> n; cout << n / 2 << n ; } return 0; }
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#include<bits/stdc++.h> using namespace std; int main() { long long int t; cin>>t; while(t--) { long long int i,j,k,l,m,n,c1=0,c2=0,ans=0,res=0; map<long long int,long long int>mp,mp1; vector<long long int>v,v1,v2; set<long long int>st,st1; vector<pair<long long int,long long int>>vp,vp1; cin>>n; long long int arr1[n]; for(i=0;i<n;i++)cin>>arr1[i]; m=*min_element(arr1,arr1+n); for(i=0;i<n;i++) { if(arr1[i]==m)c1++; if((arr1[i]&m)!=m)c2++; } if(c1<2||c2!=0)cout<<0<<endl; else {ans=c1*(c1-1); for(i=n-2;i>=1;i--) ans=(ans*i)%1000000007; cout<<ans<<endl; } } }
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#include <bits/stdc++.h> using namespace std; typedef vector<vector<long long> > vvl; long long x, y, z, j, i, t, n, k, input, ans, flag, maxi, mini, a, b; int main() { cin >> n >> x; ans = 0; for (long long i = 1; i <= n; i++) { if (x % i == 0 && x / i <= n) ans++; } cout << ans << n ; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_PP_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_PP_V
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:36:33 04/17/2016
// Design Name:
// Module Name: control_digitos_2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module control_digitos_2
(
input [7:0] estado,
input [3:0]RG1_Unit,
input [3:0]RG2_Unit,
input [3:0]RG3_Unit,
input escribiendo,
input en_out,
input wire clk,
input wire [3:0] dig1_Unit,
input [3:0] direccion,
output reg [3:0] dig_Unit_Ho, dig_Unit_min, dig_Unit_seg, dig_Unit_mes, dig_Unit_dia, dig_Unit_an, dig_Unit_Ho_Ti, dig_Unit_min_Ti, dig_Unit_seg_Ti
);
always @(posedge clk)
if (~escribiendo)
if (en_out)
case (direccion)
4'b0000://horas
dig_Unit_Ho<=dig1_Unit;
4'b0001://minutos
dig_Unit_min<=dig1_Unit;
4'b0010://segundos
dig_Unit_seg<=dig1_Unit;
4'b0011://meses
dig_Unit_mes<=dig1_Unit;
4'b0100://dias
dig_Unit_dia<=dig1_Unit;
4'b0101://años
dig_Unit_an<=dig1_Unit;
4'b0110://Horas timer
dig_Unit_Ho_Ti<=dig1_Unit;
4'b0111://minutos timer
dig_Unit_min_Ti<=dig1_Unit;
4'b1000: //segundos timer
dig_Unit_seg_Ti<=dig1_Unit;
default:
begin
dig_Unit_Ho<=dig_Unit_Ho;
dig_Unit_min<=dig_Unit_min;
dig_Unit_seg<=dig_Unit_seg;
dig_Unit_mes<=dig_Unit_mes;
dig_Unit_an<=dig_Unit_an;
dig_Unit_dia<=dig_Unit_dia;
dig_Unit_Ho_Ti<=dig_Unit_Ho_Ti;
dig_Unit_min_Ti<=dig_Unit_min_Ti;
dig_Unit_seg_Ti<=dig_Unit_seg_Ti;
end
endcase
else
begin
dig_Unit_Ho<=dig_Unit_Ho;
dig_Unit_min<=dig_Unit_min;
dig_Unit_seg<=dig_Unit_seg;
dig_Unit_mes<=dig_Unit_mes;
dig_Unit_dia<=dig_Unit_dia;
dig_Unit_an<=dig_Unit_an;
dig_Unit_Ho_Ti<=dig_Unit_Ho_Ti;
dig_Unit_min_Ti<=dig_Unit_min_Ti;
dig_Unit_seg_Ti<=dig_Unit_seg_Ti;
end
else
case (estado)
8'h7d:
begin
if (direccion==4'b0011)
dig_Unit_mes<=RG2_Unit;
else
if (direccion==4'b0100)
dig_Unit_dia<=RG1_Unit;
else
if (direccion==4'b0101)
dig_Unit_an<=RG3_Unit;
else
begin
dig_Unit_mes<=dig_Unit_mes;
dig_Unit_dia<=dig_Unit_dia;
dig_Unit_an<=dig_Unit_an;
end
end
8'h6c:
begin
if (direccion==4'b0000)
dig_Unit_Ho<=RG3_Unit;
else
if (direccion==4'b0001)
dig_Unit_min<=RG2_Unit;
else
if (direccion==4'b0010)
dig_Unit_seg<=RG1_Unit;
else
begin
dig_Unit_Ho<=dig_Unit_Ho;
dig_Unit_min<=dig_Unit_min;
dig_Unit_seg<=dig_Unit_seg;
end
end
8'h75:
begin
if (direccion==4'b0110)
dig_Unit_Ho_Ti<=RG3_Unit;
else
if (direccion==4'b0111)
dig_Unit_min_Ti<=RG2_Unit;
else
if (direccion==4'b1000)
dig_Unit_seg_Ti<=RG1_Unit;
else
begin
dig_Unit_Ho_Ti<=dig_Unit_Ho_Ti;
dig_Unit_min_Ti<=dig_Unit_min_Ti;
dig_Unit_seg_Ti<=dig_Unit_seg_Ti;
end
end
default:
begin
dig_Unit_Ho<=dig_Unit_Ho;
dig_Unit_min<=dig_Unit_min;
dig_Unit_seg<=dig_Unit_seg;
dig_Unit_mes<=dig_Unit_mes;
dig_Unit_dia<=dig_Unit_dia;
dig_Unit_an<=dig_Unit_an;
dig_Unit_Ho_Ti<=dig_Unit_Ho_Ti;
dig_Unit_min_Ti<=dig_Unit_min_Ti;
dig_Unit_seg_Ti<=dig_Unit_seg_Ti;
end
endcase
endmodule
|
module mux_32(
add,
i_0 ,
i_1 ,
i_2 ,
i_3 ,
i_4 ,
i_5 ,
i_6 ,
i_7 ,
i_8 ,
i_9 ,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_i
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [4:0] add;
input signed [15:0] i_0 ;
input signed [15:0] i_1 ;
input signed [15:0] i_2 ;
input signed [15:0] i_3 ;
input signed [15:0] i_4 ;
input signed [15:0] i_5 ;
input signed [15:0] i_6 ;
input signed [15:0] i_7 ;
input signed [15:0] i_8 ;
input signed [15:0] i_9 ;
input signed [15:0] i_10;
input signed [15:0] i_11;
input signed [15:0] i_12;
input signed [15:0] i_13;
input signed [15:0] i_14;
input signed [15:0] i_15;
input signed [15:0] i_16;
input signed [15:0] i_17;
input signed [15:0] i_18;
input signed [15:0] i_19;
input signed [15:0] i_20;
input signed [15:0] i_21;
input signed [15:0] i_22;
input signed [15:0] i_23;
input signed [15:0] i_24;
input signed [15:0] i_25;
input signed [15:0] i_26;
input signed [15:0] i_27;
input signed [15:0] i_28;
input signed [15:0] i_29;
input signed [15:0] i_30;
input signed [15:0] i_31;
output reg signed [15:0] o_i;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
case(add)
5'd0 :o_i=i_0 ;
5'd1 :o_i=i_1 ;
5'd2 :o_i=i_2 ;
5'd3 :o_i=i_3 ;
5'd4 :o_i=i_4 ;
5'd5 :o_i=i_5 ;
5'd6 :o_i=i_6 ;
5'd7 :o_i=i_7 ;
5'd8 :o_i=i_8 ;
5'd9 :o_i=i_9 ;
5'd10:o_i=i_10;
5'd11:o_i=i_11;
5'd12:o_i=i_12;
5'd13:o_i=i_13;
5'd14:o_i=i_14;
5'd15:o_i=i_15;
5'd16:o_i=i_16;
5'd17:o_i=i_17;
5'd18:o_i=i_18;
5'd19:o_i=i_19;
5'd20:o_i=i_20;
5'd21:o_i=i_21;
5'd22:o_i=i_22;
5'd23:o_i=i_23;
5'd24:o_i=i_24;
5'd25:o_i=i_25;
5'd26:o_i=i_26;
5'd27:o_i=i_27;
5'd28:o_i=i_28;
5'd29:o_i=i_29;
5'd30:o_i=i_30;
5'd31:o_i=i_31;
endcase
endmodule
|
//CSA6:2 Compressor
//#############################################################################
//# Function: Carry Save Adder (6:2) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_csa62 #(parameter DW = 1 // data width
)
( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input
input [DW-1:0] in2,//input
input [DW-1:0] in3,//input
input [DW-1:0] in4,//input
input [DW-1:0] in5,//input
input [DW-1:0] cin0,//carry in
input [DW-1:0] cin1,//carry in
input [DW-1:0] cin2,//carry in
output [DW-1:0] s, //sum
output [DW-1:0] c, //carry
output [DW-1:0] cout0, //carry out
output [DW-1:0] cout1, //carry out
output [DW-1:0] cout2 //carry out
);
wire [DW-1:0] s_int0;
wire [DW-1:0] s_int1;
oh_csa32 #(.DW(DW)) csa32_0 (.in0(in0[DW-1:0]),
.in1(in1[DW-1:0]),
.in2(in2[DW-1:0]),
.c(cout0[DW-1:0]),
.s(s_int0[DW-1:0]));
oh_csa32 #(.DW(DW)) csa32_1 (.in0(in3[DW-1:0]),
.in1(in4[DW-1:0]),
.in2(in5[DW-1:0]),
.c(cout1[DW-1:0]),
.s(s_int1[DW-1:0]));
oh_csa42 #(.DW(DW)) csa42 (.in0(s_int0[DW-1:0]),
.in1(s_int1[DW-1:0]),
.in2(cin0[DW-1:0]),
.in3(cin1[DW-1:0]),
.cin(cin2[DW-1:0]),
.cout(cout2[DW-1:0]),
.c(c[DW-1:0]),
.s(s[DW-1:0]));
endmodule // oh_csa62
|
module top;
reg pass = 1'b1;
integer count;
reg [2:0] icount;
reg clk = 0;
real in = 0.0;
real result = -1.0;
always #10 clk = ~clk;
always #20 in = in + 1.0;
initial begin
count = 3;
result <= repeat(count) @(posedge clk) in;
if ($simtime != 0 || result != -1.0) begin
$display("Failed repeat(3) blocked at %0t, expected -1.0, got %f",
$simtime, result);
pass = 1'b0;
end
@(result);
if ($simtime != 50 || result != 0.0) begin
$display("Failed repeat(3) at %0t, expected 0.0, got %f",
$simtime, result);
pass = 1'b0;
end
#15;
count = 0;
result <= repeat(count) @(posedge clk) in;
#0; // This may not work since there is no delay.
if ($simtime != 65 || result != 3.0) begin
$display("Failed repeat(0) at %0t, expected 3.0, got %f",
$simtime, result);
pass = 1'b0;
end
#20;
count = -1;
result <= repeat(count) @(posedge clk) in;
#0; // This may not work since there is no delay.
if ($simtime != 85 || result != 4.0) begin
$display("Failed repeat(-1) at %0t, expected 4.0, got %f",
$simtime, result);
pass = 1'b0;
end
#20;
result <= @(posedge clk) 0.0;
result <= @(posedge clk) in; // This one sets the final value.
@(result);
if ($simtime != 110 || result != 5.0) begin
$display("Failed @ at %0t, expected 5.0, got %f",
$simtime, result);
pass = 1'b0;
end
icount = 3'd2;
result <= @(posedge clk) 1.0;
result <= repeat(icount) @(posedge clk) 2.0;
result <= repeat(3) @(posedge clk) 3.0;
@(result);
if ($simtime != 130 || result != 1.0) begin
$display("Failed first @ at %0t, expected 1.0, got %f",
$simtime, result);
pass = 1'b0;
end
@(result);
if ($simtime != 150 || result != 2.0) begin
$display("Failed second @ at %0t, expected 2.0, got %f",
$simtime, result);
pass = 1'b0;
end
@(result);
if ($simtime != 170 || result != 3.0) begin
$display("Failed third @ at %0t, expected 3.0, got %f",
$simtime, result);
pass = 1'b0;
end
if (pass) $display("PASSED");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: jorge Sequeira
//
// Create Date: 08/25/2016 09:12:30 AM
// Design Name:
// Module Name: Testbench_
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Prueba de un multiplicador simple combinacional
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module testbench_mult_c();
//parameter PERIOD = 10;
parameter SW=6;
reg [SW-1:0] Data_A_i;
reg [SW-1:0] Data_B_i;
wire [2*SW-1:0] Data_S_o;
multiplier_C #(.W(SW)) uut (
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(Data_S_o)
);
integer i = 1;
parameter cycles = 12;
initial begin
Data_B_i = 1;
$monitor(Data_A_i,Data_B_i,Data_S_o);
Data_A_i = 1;
#100;
$monitor(Data_A_i,Data_B_i,Data_S_o);
Data_B_i = 2;
repeat (cycles) begin
Data_A_i = i;
i = i + 1;
$monitor(Data_A_i,Data_B_i,Data_S_o);
#50;
end
end
// initial begin
// // Initialize Input
// #100;
// while (i < 50)
// begin
// $monitor(Data_A_i,Data_B_i,Data_S_o);
// Data_A_i = i;
// Data_B_i = 1;
// i = i + 1;
// #100;
// end
//// #100
//// Data_A_i = 6'd1;
//// Data_B_i = 6'd1;
//// #100
//// Data_A_i = 6'd1;
//// Data_B_i = 6'd2;
//// #100
//// Data_A_i = 6'd5;
//// Data_B_i = 6'd6;
// end
// //Add stimulus here
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int rit() { int f = 0, key = 1; char ch; do { ch = getchar(); if (ch == - ) key = -1; } while (ch < 0 || ch > 9 ); do { f = f * 10 + ch - 0 ; ch = getchar(); } while (ch >= 0 && ch <= 9 ); return f * key; } int n; int arr[2000 + 5], suf[2000 + 5], pre[2000 + 5], ans, dp[2000 + 5][2000 + 5][3]; int32_t main(void) { n = rit(); for (int i = 1; i <= (n); i++) { arr[i] = rit(); } for (int i = 1; i <= (n); i++) { pre[i] = pre[i - 1] + (arr[i] == 1); suf[n - i + 1] = suf[n - i + 2] + (arr[n - i + 1] == 2); } for (int i = 1; i <= (n); i++) for (int j = i; j <= n; ++j) { dp[i][j][1] = max(dp[i][j - 1][1], dp[i][j - 1][2]) + (arr[j] == 1); dp[i][j][2] = dp[i][j - 1][2] + (arr[j] == 2); ans = max(ans, max(dp[i][j][1], dp[i][j][2]) + pre[i - 1] + suf[j + 1]); } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[200], ans[200]; int v[1000001]; int main() { int T, n; cin >> T; while (T--) { memset(v, 0, sizeof v); scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) { for (int j = i; j <= n; j++) v[a[j] - a[i]] = 1; } memset(ans, 0, sizeof ans); ans[1] = 1; int len = 2; for (int j = 1; j <= 1e6; j++) { int tag = 1; for (int k = 1; k < len; k++) { if (v[j - ans[k]]) { tag = 0; break; } } if (tag) ans[len++] = j; if (len > n) break; } int tag = 1; for (int i = 1; i <= n; i++) if (ans[i] == 0) tag = 0; if (tag) { puts( YES ); for (int i = 1; i <= n; i++) printf( %d%c , ans[i], i == n ? n : ); } else puts( NO ); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19.02.2017 01:26:40
// Design Name:
// Module Name: seg_disp
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seg_disp(
input clk,
input[7:0] d1,
input[7:0] d2,
input[7:0] d3,
input[7:0] d4,
input dp,
output reg[6:0] seg,
output reg[3:0] an,
output dp_pin
);
wire[6:0] seg1;
wire[6:0] seg2;
wire[6:0] seg3;
wire[6:0] seg4;
reg[2:0] state = 0;
assign dp_pin = 1;
number_to_seg dd1(d1, seg1);
number_to_seg dd2(d2, seg2);
number_to_seg dd3(d3, seg3);
number_to_seg dd4(d4, seg4);
wire nd1 = (d1 == 0);
wire nd2 = (d2 == 0);
wire nd3 = (d3 == 0);
always @(posedge clk) begin
case (state)
default: state <= 0;
0: begin
seg <= seg1;
an <= nd1 ? 4'b1111 : 4'b0111;
state <= state + 1;
end
1: begin
seg <= seg2;
an <= nd1 && nd2 ? 4'b1111 : 4'b1011;
state <= state + 1;
end
2: begin
seg <= seg3;
an <= nd1 && nd2 && nd3 ? 4'b1111 : 4'b1101;
state <= state + 1;
end
3: begin
seg <= seg4;
an <= 4'b1110;
state <= 0;
end
endcase
end
endmodule
module number_to_seg(input[7:0] d, output[6:0] seg);
assign seg = (d == 0) ? 7'b1000000 :
(d == 1) ? 7'b1111001 :
(d == 2) ? 7'b0100100 :
(d == 3) ? 7'b0110000 :
(d == 4) ? 7'b0011001 :
(d == 5) ? 7'b0010010 :
(d == 6) ? 7'b0000010 :
(d == 7) ? 7'b1111000 :
(d == 8) ? 7'b0000000 :
(d == 9) ? 7'b0010000 : 7'b1000000;
endmodule
module num_to_digits(input[11:0] _num, output[3:0] _thousands, output [3:0] _hundreds, output [3:0] _tens, output [3:0] _ones);
assign _thousands = (_num % 10000) / 1000;
assign _hundreds = (_num % 1000) / 100;
assign _tens = (_num % 100) / 10;
assign _ones = _num % 10;
endmodule
module num_to_digits1(input[17:0] _num, output[3:0] _thousands, output [3:0] _hundreds, output [3:0] _tens, output [3:0] _ones);
assign _thousands = (_num % 10000) / 1000;
assign _hundreds = (_num % 1000) / 100;
assign _tens = (_num % 100) / 10;
assign _ones = _num % 10;
endmodule
|
#include <bits/stdc++.h> const int MAXN = 2e5 + 10; using namespace std; long long read() { long long x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return f * x; } int n, q; long long a[MAXN]; typedef struct node { long long maxx; long long sum; } node; node d[MAXN << 2]; void up(int x) { d[x].sum = d[x << 1].sum + d[x << 1 | 1].sum; d[x].maxx = max(d[x << 1].maxx, d[x << 1 | 1].maxx); } void built(int rt, int l, int r) { if (l == r) { d[rt].maxx = d[rt].sum = a[l]; return; } int mid = (l + r) >> 1; built(rt << 1, l, mid); built(rt << 1 | 1, mid + 1, r); up(rt); } void update(int rt, int l, int r, int t, long long vul) { if (l == r) { d[rt].maxx = d[rt].sum = vul; return; } int mid = (l + r) >> 1; if (t <= mid) update(rt << 1, l, mid, t, vul); else update(rt << 1 | 1, mid + 1, r, t, vul); up(rt); } bool flag; int pos1; void querty2(int rt, int l, int r, long long vul) { if (l == r) { pos1 = l; return; } int mid = (l + r) >> 1; if (d[rt << 1].maxx >= vul) querty2(rt << 1, l, mid, vul); else querty2(rt << 1 | 1, mid + 1, r, vul); } void querty(int rt, int l, int r, int ql, int qr, long long vul) { if (flag) return; if (ql <= l && r <= qr) { if (d[rt].maxx >= vul) { flag = 1; querty2(rt, l, r, vul); } return; } int mid = (l + r) >> 1; if (ql <= mid) querty(rt << 1, l, mid, ql, qr, vul); if (qr > mid) querty(rt << 1 | 1, mid + 1, r, ql, qr, vul); } long long ans; void querty1(int rt, int l, int r, int ql, int qr) { if (ql <= l && r <= qr) { ans += d[rt].sum; return; } int mid = (l + r) >> 1; if (ql <= mid) querty1(rt << 1, l, mid, ql, qr); if (qr > mid) querty1(rt << 1 | 1, mid + 1, r, ql, qr); } int main() { n = read(); q = read(); for (int i = 1; i <= n; i++) a[i] = read(); a[n + 1] = 1e18; int pos, ans1; long long vul, key, pre; n++; built(1, 1, n); for (int i = 1; i <= q; i++) { pos = read(); vul = read(); a[pos] = vul; update(1, 1, n, pos, vul); ans1 = -1; key = 0; if (!a[1]) { printf( 1 n ); continue; } if (a[1] == a[2]) { printf( 2 n ); continue; } key = a[1] + a[2]; pre = 3; while (1) { if (pre > n) break; flag = 0; querty(1, 1, n, pre, n, key); ans = 0; querty1(1, 1, n, 1, pos1 - 1); if (ans == a[pos1]) { ans1 = pos1; break; } key = ans + a[pos1]; pre = pos1 + 1; } printf( %d n , ans1); } return 0; }
|
module DM9000A_IF( // HOST Side
// Signals fro Avalon-MM slave port "s1"
avs_s1_writedata_iDATA,
avs_s1_readdata_oDATA,
avs_s1_address_iCMD,
avs_s1_read_n_iRD_N,
avs_s1_write_n_iWR_N,
avs_s1_chipselect_n_iCS_N,
avs_s1_reset_n_iRST_N,
avs_s1_clk_iCLK,
avs_s1_irq_oINT,
// export signal to DM9000A Chip
avs_s1_export_ENET_DATA,
avs_s1_export_ENET_CMD,
avs_s1_export_ENET_RD_N,
avs_s1_export_ENET_WR_N,
avs_s1_export_ENET_CS_N,
avs_s1_export_ENET_RST_N,
avs_s1_export_ENET_INT,
avs_s1_export_ENET_CLK
);
// HOST Side
input [15:0] avs_s1_writedata_iDATA;
input avs_s1_address_iCMD;
input avs_s1_read_n_iRD_N;
input avs_s1_write_n_iWR_N;
input avs_s1_chipselect_n_iCS_N;
input avs_s1_reset_n_iRST_N;
input avs_s1_clk_iCLK;
output [15:0] avs_s1_readdata_oDATA;
output avs_s1_irq_oINT;
// DM9000A Side
inout [15:0] avs_s1_export_ENET_DATA;
output avs_s1_export_ENET_CMD;
output avs_s1_export_ENET_RD_N;
output avs_s1_export_ENET_WR_N;
output avs_s1_export_ENET_CS_N;
output avs_s1_export_ENET_RST_N;
output avs_s1_export_ENET_CLK;
input avs_s1_export_ENET_INT;
assign avs_s1_export_ENET_DATA = avs_s1_write_n_iWR_N ? 16'hzzzz : avs_s1_writedata_iDATA;
assign avs_s1_readdata_oDATA = avs_s1_read_n_iRD_N ? 16'hzzzz : avs_s1_export_ENET_DATA;
assign avs_s1_export_ENET_RST_N = avs_s1_reset_n_iRST_N;
assign avs_s1_irq_oINT = avs_s1_export_ENET_INT;
assign avs_s1_export_ENET_CMD = avs_s1_address_iCMD;
assign avs_s1_export_ENET_CS_N = avs_s1_chipselect_n_iCS_N;
assign avs_s1_export_ENET_RD_N = avs_s1_read_n_iRD_N;
assign avs_s1_export_ENET_WR_N = avs_s1_write_n_iWR_N;
assign avs_s1_export_ENET_CLK = avs_s1_clk_iCLK;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; long long calcCards(long long x) { return x * (x + 1) + (x - 1) * x / 2; } bool P(int x) { return calcCards(x) <= n; } long long bs(long long l = 0, long long h = n) { long long m; while (l < h) { m = (l + h + 1) / 2; if (P(m)) l = m; else h = m - 1; } return l; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cout << fixed; cout << setprecision(10); int t; cin >> t; while (t--) { cin >> n; int ans = 0; while (n >= 2) { ans++; n -= calcCards(bs()); } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; inline char nc() { static char buf[1000000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; } template <typename T> inline void read(T& sum) { char ch = nc(); T tf = 0; sum = 0; while ((ch < 0 || ch > 9 ) && (ch != - )) ch = nc(); tf = ((ch == - ) && (ch = nc())); while (ch >= 0 && ch <= 9 ) sum = sum * 10 + (ch - 48), ch = nc(); (tf) && (sum = -sum); } template <typename T> inline void write(T x) { if (x == 0) { putchar( 0 ); return; } char F[200]; T tmp = x > 0 ? x : -x; if (x < 0) putchar( - ); T cnt = 0; while (tmp > 0) { F[cnt++] = tmp % 10 + 0 ; tmp /= 10; } while (cnt > 0) putchar(F[--cnt]); } template <typename T> T gcd(T a, T b) { if (!a || !b) return max(a, b); while (b ^= a ^= b ^= a %= b) ; return a; } template <typename T> T C(T m, T n) { if (n > m) return 0; if (n == 0 || m == 1 || m == n) return 1; return C(m - 1, n - 1) + C(m - 1, n); } template <typename T> void exgcd(T a, T b, T& d, T& x, T& y) { if (!b) { d = a; x = 1; y = 0; } else { exgcd(b, a % b, d, y, x); y -= x * (a / b); } } template <typename T> T niyuan(T a, T p) { T d, x, y; exgcd(a, p, d, x, y); return d == 1 ? (x + p) % p : -1; } template <typename T> T extgcd(T a, T b, T& x, T& y) { if (b) { T r = extgcd(b, a % b, y, x); y -= x * (a / b); return r; } else { x = 1; y = 0; return a; } } template <typename T> T ax_bmodM(T a, T b, T M) { T x, y, r = extgcd(a, M, x, y); if (b % r) return -1; else x = (x + M) % M * b / r; return x % (M / r); } template <typename T> inline T dmod(const string& s, T mod) { T len = s.size(); T ans = 0; for (T i = 0; i < len; i++) ans = (int)(((long long)ans * 10 + s[i] - 0 ) % mod); return ans; } template <typename T> inline T ksc(T a, T b, T mod) { T ans = 0; while (b > 0) { if (b & 1) ans = (ans + a) % mod; a = (a + a) % mod; b >>= 1; } return ans; } template <typename T> inline T ksm(T x, T n, T mod) { T ans = 1; while (n > 0) { if (n & 1) ans = ans * x % mod; x = x * x % mod; n >>= 1; } return ans; } template <typename T> inline T mod_jia(T a, T b, T mod) { return (a % mod + b % mod) % mod; } template <typename T> inline T mod_jian(T a, T b, T mod) { return (a % mod + mod - b % mod) % mod; } template <typename T> inline T mod_cheng(T a, T b, T mod) { return ((a % mod) * (b % mod)) % mod; } template <typename T> inline T mod_chu(T a, T b, T p) { b = ksm(b, p - 2, p); return a * b % p; } template <typename T> inline void rmqmin(T f[][20], T n) { for (int i = 1; i <= n; i++) cin >> f[i][0]; for (int j = 1; j <= 20; j++) for (int i = 1; i <= n; i++) if (i + (1 << j) - 1 <= n) f[i][j] = min(f[i][j - 1], f[i + (1 << (j - 1))][j - 1]); } template <typename T> inline T zymin(T f[][20], T z, T y) { int x = int(log(y - z + 1) / log(2)); return min(f[z][x], f[y - (1 << x) + 1][x]); } template <typename T> inline void rmqmax(T f[][20], T n) { for (int i = 1; i <= n; i++) cin >> f[i][0]; for (int j = 1; j <= 20; j++) for (int i = 1; i <= n; i++) if (i + (1 << j) - 1 <= n) f[i][j] = max(f[i][j - 1], f[i + (1 << (j - 1))][j - 1]); } template <typename T> inline T zymax(T f[][20], T z, T y) { int x = int(log(y - z + 1) / log(2)); return max(f[z][x], f[y - (1 << x) + 1][x]); } template <typename T> inline void stgcd(T f[][20], T n) { for (int i = 1; i <= n; i++) cin >> f[i][0], f[i + n][0] = f[i][0]; for (int j = 1; j <= 20; j++) { for (int i = 1; i + (1 << j) - 1 <= 2 * n; i++) { f[i][j] = __gcd(f[i][j - 1], f[i + (1 << (j - 1))][j - 1]); } } } template <typename T> inline T qgcd(T f[][20], T z, T y) { int x = int(log(y - z + 1) / log(2)); return __gcd(f[z][x], f[y - (1 << x) + 1][x]); } template <typename T> inline T rotatex(T x, T y, T ang, T ox = 0, T oy = 0) { return (x - ox) * cos(ang) - (y - oy) * sin(ang) + ox; } template <typename T> inline T rotatey(T x, T y, T ang, T ox = 0, T oy = 0) { return (x - ox) * sin(ang) + (y - oy) * cos(ang) + oy; } vector<int> l, y; char s[200005]; pair<int, int> p[200005]; int a[200005], ans[200005]; bool cmp(int x, int y) { return a[x] < a[y]; } void solve() { l.clear(); y.clear(); int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; p[i] = make_pair(a[i], i); } cin >> (s + 1); for (int i = 1; i <= n; ++i) { if (s[i] == 1 ) y.push_back(i); else l.push_back(i); } int xx = 0; int long long = l.size(); int yy = y.size(); sort(y.begin(), y.end(), cmp); sort(l.begin(), l.end(), cmp); for (auto& i : l) ans[i] = ++xx; for (auto& i : y) ans[i] = ++xx; for (int i = 1; i <= n; ++i) cout << ans[i] << ; cout << n ; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int _t; cin >> _t; while (_t--) solve(); return 0; }
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#include <bits/stdc++.h> const uint64_t MAX_NUM = 1000000000000000001ul; uint64_t get_iteration_simple(const int n, const uint64_t k, std::vector<uint64_t>& a) { int iterations = 0; while (true) { ++iterations; for (int i = 1; i < n; ++i) { a[i] += a[i - 1]; if (a[i] >= k) { return iterations; } } } } bool is_there_more_than_k_with_coeffs( const int n, const uint64_t k, std::vector<uint64_t>& a, std::vector<std::vector<uint64_t>>& coeffs) { for (int i = 0; i < n; ++i) { uint64_t result = 0; for (int j = 0; j <= i; ++j) { if (static_cast<double>(a[j]) * static_cast<double>(coeffs[i][j]) > MAX_NUM) { return true; } result += coeffs[i][j] * a[j]; if (result >= k) { return true; } } } return false; } std::tuple<std::vector<std::vector<uint64_t>>, bool> generate_mixed_coeffs( const int n, const uint64_t k, std::vector<std::vector<uint64_t>>& first_coeffs, std::vector<std::vector<uint64_t>>& second_coeffs) { bool is_there_overflow = false; std::vector<std::vector<uint64_t>> new_coeffs(n); for (int i = 0; i < n; ++i) { new_coeffs[i].resize(i + 1, 0); for (int j = 0; j <= i; ++j) { new_coeffs[i][j] = 0; for (int k = j; k <= i; ++k) { if (static_cast<double>(second_coeffs[i][k]) * static_cast<double>(first_coeffs[k][j]) > MAX_NUM) { is_there_overflow = true; } new_coeffs[i][j] += second_coeffs[i][k] * first_coeffs[k][j]; } } } return std::make_tuple(new_coeffs, is_there_overflow); } uint64_t get_iteration_binsearch(const int n, const uint64_t k, std::vector<uint64_t>& a) { uint64_t left = 0; uint64_t right = 1; std::vector<std::vector<std::vector<uint64_t>>> level_coeffs(100); level_coeffs[0].resize(n); std::vector<std::vector<uint64_t>> current_coeffs(n); for (int i = 0; i < n; ++i) { level_coeffs[0][i].resize(i + 1, 0); current_coeffs[i].resize(i + 1, 0); for (int j = 0; j <= i; ++j) { level_coeffs[0][i][j] = 1; current_coeffs[i][j] = (i == j ? 1 : 0); } } int diff_two_power = 0; while (true) { if (is_there_more_than_k_with_coeffs(n, k, a, level_coeffs[diff_two_power])) { break; } else { right *= 2; bool is_there_overflow; std::tie(level_coeffs[diff_two_power + 1], is_there_overflow) = generate_mixed_coeffs(n, k, level_coeffs[diff_two_power], level_coeffs[diff_two_power]); ++diff_two_power; if (is_there_overflow) { break; } } } while (right - left > 1) { uint64_t middle = left + (1ull << (diff_two_power - 1)); std::vector<std::vector<uint64_t>> middle_coeffs; bool is_there_overflow; std::tie(middle_coeffs, is_there_overflow) = generate_mixed_coeffs( n, k, current_coeffs, level_coeffs[diff_two_power - 1]); if (is_there_overflow || is_there_more_than_k_with_coeffs(n, k, a, middle_coeffs)) { right = middle; } else { left = middle; current_coeffs = std::move(middle_coeffs); } --diff_two_power; } return left + 1; } bool is_there_more_than_k(const int n, const uint64_t k, const std::vector<uint64_t>& a) { for (int i = 0; i < n; ++i) { if (a[i] >= k) { return true; } } return false; } int main() { int n; uint64_t k; std::cin >> n >> k; bool still_zero = true; std::vector<uint64_t> a(n); int new_n = 0; for (int i = 0; i < n; ++i) { uint64_t number; std::cin >> number; if (number != 0 || !still_zero) { a[new_n++] = number; } if (number != 0) { still_zero = false; } } const int simple_algo_bound = 60; uint64_t result; if (is_there_more_than_k(new_n, k, a)) { result = 0; } else if (new_n >= simple_algo_bound) { result = get_iteration_simple(new_n, k, a); } else { result = get_iteration_binsearch(new_n, k, a); } std::cout << result << std::endl; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DFSBP_BEHAVIORAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign cond0 = ( SET_B_delayed === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_BEHAVIORAL_V
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#include <bits/stdc++.h> using namespace std; struct T { int p, n; }; bool operator<(T x, T y) { return x.p < y.p; } T m[100100]; int main() { int i, n, j; for (scanf( %d , &n), i = 0; i < n; scanf( %d%d , &m[i].p, &m[i].n), i++) ; sort(m, m + n); j = m[n - 1].n; for (i = 0; i < n - 1; i++) if (m[i + 1].p - m[i].p > 40) continue; else { for (; m[i].p < m[i + 1].p; m[i].n = (m[i].n + 3) / 4, m[i].p++) ; if (m[i].n > m[i + 1].n) m[i + 1].n = m[i].n; } if (m[n - 1].n == j && j == 1) printf( %d n , m[n - 1].p + 1); else { for (; m[i].n > 1; m[i].n = (m[i].n + 3) / 4, m[i].p++) ; printf( %d n , m[i].p); } return 0; }
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// File: comm_fpga_fx2_v2.v
// Generated by MyHDL 0.9dev
// Date: Sat Jul 13 22:29:39 2013
`timescale 1ns/10ps
module comm_fpga_fx2_v2 (
clk_in,
reset_in,
fx2FifoSel_out,
fx2Data_in,
fx2Data_out,
fx2Data_sel,
fx2Read_out,
fx2GotData_in,
fx2Write_out,
fx2GotRoom_in,
fx2PktEnd_out,
chanAddr_out,
h2fData_out,
h2fValid_out,
h2fReady_in,
f2hData_in,
f2hValid_in,
f2hReady_out
);
// Original port definition
// This module bridges the "original" port mapping to the MyHDL
// version.
input clk_in;
input reset_in;
output fx2FifoSel_out;
reg fx2FifoSel_out;
input [7:0] fx2Data_in;
output [7:0] fx2Data_out;
reg [7:0] fx2Data_out;
output fx2Data_sel;
reg fx2Data_sel;
input fx2Read_out;
input fx2GotData_in;
input fx2Write_out;
input fx2GotRoom_in;
input fx2PktEnd_out;
input [6:0] chanAddr_out;
input [7:0] h2fData_out;
input h2fValid_out;
input h2fReady_in;
input [7:0] f2hData_in;
input f2hValid_in;
input f2hReady_out;
reg [6:0] g_fl_bus_chan_addr;
wire g_fx2_bus_read;
reg g_is_write;
reg [3:0] g_state;
wire [7:0] g_fl_bus_data_i;
wire g_fx2_bus_gotroom;
reg [7:0] g_fl_bus_data_o;
wire g_fl_bus_ready_i;
reg g_fl_bus_ready_o;
reg g_is_aligned;
reg [31:0] g_count;
reg [1:0] g_fifop;
reg g_fl_bus_valid_o;
wire g_fx2_bus_write;
wire g_fl_bus_valid_i;
wire g_fx2_bus_gotdata;
reg g_fx2_bus_pktend;
assign g_fl_bus_data_i = 0;
assign g_fx2_bus_gotroom = 0;
assign g_fl_bus_ready_i = 0;
assign g_fl_bus_valid_i = 0;
assign g_fx2_bus_gotdata = 0;
always @(posedge clk_in, negedge reset_in) begin: COMM_FPGA_FX2_V2_G_HDL_SM
if (reset_in == 0) begin
g_count <= 0;
g_fl_bus_chan_addr <= 0;
fx2Data_out <= 0;
fx2FifoSel_out <= 0;
g_fifop <= 3;
g_is_write <= 0;
g_fl_bus_ready_o <= 0;
fx2Data_sel <= 0;
g_fl_bus_valid_o <= 0;
g_state <= 4'b0000;
g_fx2_bus_pktend <= 0;
g_fl_bus_data_o <= 0;
g_is_aligned <= 0;
end
else begin
case (g_state)
4'b0001: begin
if (g_fx2_bus_gotdata) begin
g_count <= (fx2Data_in << 24);
g_state <= 4'b0010;
end
else begin
g_count <= 0;
end
end
4'b0010: begin
if (g_fx2_bus_gotdata) begin
g_count <= (g_count | (fx2Data_in << 16));
g_state <= 4'b0011;
end
end
4'b0011: begin
if (g_fx2_bus_gotdata) begin
g_count <= (g_count | (fx2Data_in << 8));
g_state <= 4'b0100;
end
end
4'b0100: begin
if (g_fx2_bus_gotdata) begin
g_count <= (g_count | fx2Data_in);
if (g_is_write) begin
g_state <= 4'b0101;
end
else begin
if (g_fl_bus_ready_i) begin
g_fifop <= 2;
g_state <= 4'b1001;
end
else begin
g_fifop <= 3;
g_state <= 4'b1010;
end
end
end
end
4'b0101: begin
fx2FifoSel_out <= 1;
g_fifop <= 3;
if ((g_count[9-1:0] == 0)) begin
g_is_aligned <= 1'b1;
end
else begin
g_is_aligned <= 1'b0;
end
g_state <= 4'b0110;
end
4'b0110: begin
if (g_fx2_bus_gotroom) begin
g_fl_bus_ready_o <= 1'b1;
end
if ((g_fx2_bus_gotroom && g_fl_bus_valid_i)) begin
g_fifop <= 1;
fx2Data_out <= g_fl_bus_data_i;
fx2Data_sel <= 1'b1;
g_count <= (g_count - 1);
if ((g_count == 1)) begin
if (g_is_aligned) begin
g_state <= 4'b0111;
end
else begin
g_state <= 4'b1000;
end
end
end
else begin
g_fifop <= 3;
end
end
4'b0111: begin
fx2FifoSel_out <= 1;
g_fifop <= 3;
g_state <= 4'b0000;
end
4'b1000: begin
fx2FifoSel_out <= 1;
g_fifop <= 3;
g_fx2_bus_pktend <= 1'b0;
g_state <= 4'b0000;
end
4'b1001: begin
fx2FifoSel_out <= 0;
if ((g_fx2_bus_gotdata && g_fl_bus_ready_i)) begin
if ((!g_fx2_bus_read) !== 1) begin
$display("*** AssertionError ***");
end
g_fl_bus_valid_o <= 1'b1;
g_fl_bus_data_o <= fx2Data_in;
if ((g_count <= 1)) begin
g_state <= 4'b0000;
g_count <= 0;
end
else begin
g_count <= (g_count - 1);
end
end
end
4'b1010: begin
if ((g_fx2_bus_gotdata && g_fl_bus_ready_i)) begin
g_state <= 4'b1001;
g_fifop <= 2;
end
end
default: begin
g_fifop <= 2;
g_count <= 0;
g_fl_bus_valid_o <= 1'b0;
if (g_fx2_bus_gotdata) begin
g_fl_bus_chan_addr <= fx2Data_in[7-1:0];
g_is_write <= fx2Data_in[7];
g_state <= 4'b0001;
end
end
endcase
end
end
assign g_fx2_bus_read = g_fifop[0];
assign g_fx2_bus_write = g_fifop[1];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long d[3]; cin >> d[0] >> d[1] >> d[2]; sort(d, d + 3); if (d[2] >= d[0] + d[1]) cout << d[0] + d[1] << endl; else { cout << d[2] + (d[1] + d[0] - d[2]) / 2 << endl; } } return 0; }
|
module pong16 (sys_clk,
rst_n,
dm_sel,
ramadr,
ramwe,
ramre,
dbus_in,
vid_sync_o,
vid_o,
audio_o
);
//INPUTS
input logic sys_clk;
input logic rst_n;
input wire dm_sel;
input wire ramwe;
input wire ramre;
input wire [7:0] ramadr;
input [7:0] dbus_in;
//OUTPUTS
output vid_sync_o;
output vid_o;
output audio_o;
`include "xb_adr_pack.vh"
//localparam PAD0_ADDR = 8'hE0;
//localparam PAD1_ADDR = 8'hE1;
//localparam PNGCR_ADDR = 8'hE2;
wire vid_sync;
wire vid;
reg vid_sync_o;
reg vid_o;
reg rst_clk=0;
always @(posedge sys_clk) begin
rst_clk <= ~rst_clk;
end
reg[7:0] PAD0;
reg[7:0] PAD1;
reg DEMO_MODE;
wire serv_ball;
wire game_rst;
reg[3:0] serv_ball_cnt;
reg[3:0] game_rst_cnt;
reg[1:0] ball_speed;
assign pad0_sel = (dm_sel && ramadr == PAD0_ADDR);
assign pad1_sel = (dm_sel && ramadr == PAD1_ADDR);
assign pngcr_sel = (dm_sel && ramadr == PNGCR_ADDR);
assign pad0_we = pad0_sel & ramwe;
assign pad1_we = pad1_sel & ramwe;
assign pngcr_we = pngcr_sel & ramwe;
always @(posedge sys_clk) begin
if(!rst_n) begin
PAD0 <= 100;
end else if( pad0_we) begin
PAD0 <= dbus_in ;
end
end
always @(posedge sys_clk) begin
if(!rst_n) begin
PAD1 <= 100;
end else if( pad1_we) begin
PAD1 <= dbus_in ;
end
end
//Serve the Ball
assign serv_ball = | serv_ball_cnt;
always @(posedge sys_clk) begin
if(!rst_n) begin
serv_ball_cnt <= 0;
end else begin
serv_ball_cnt <= (pngcr_we && dbus_in[1] ) ? 10 : (serv_ball_cnt != 0) ? serv_ball_cnt-1 : 0;
end
end
//Game reset
assign game_rst = | game_rst_cnt;
always @(posedge sys_clk) begin
if(!rst_n) begin
game_rst_cnt <= 0;
end else begin
game_rst_cnt <= (pngcr_we && dbus_in[0] ) ? 10 : (game_rst_cnt != 0) ? game_rst_cnt-1 : 0;
end
end
//Ball Speed PNGCR[4] sets ball speed to 2 to 1
always @(posedge sys_clk) begin
if(!rst_n) begin
ball_speed <= 2'b01;
end else if( pngcr_we) begin
ball_speed <= (dbus_in[4]==1) ? 2'b10 : 2'b01;
end
end
// DEMO MODE
always @(posedge sys_clk) begin
if(!rst_n) begin
DEMO_MODE <= 1;
end else if( pngcr_we) begin
DEMO_MODE <= dbus_in[7];
end
end
reg[23:0] cntr;
reg rst_na;
always @(posedge rst_clk) begin
if(~rst_n) begin
cntr <= 400;
end else begin
cntr <= (cntr!=0) ? cntr-1 : 0;
end
end
always @(negedge rst_clk) begin
if(~rst_n) begin
rst_na <= 1'b1;
end else begin
rst_na <= (cntr>10 && cntr <200) ? 1'b0 : 1'b1;
end
end
always @(posedge sys_clk) begin
vid_sync_o <= vid_sync;
vid_o <= vid;
end
wire[8:0] x,y;
wire vid_time;
//Video timing logic
//
vid_timer16 v_timer(.clk (sys_clk),
.rst_n (rst_na),
.vid_sync (vid_sync),
.vid_time (vid_time),
.x (x),
.y (y)
);
//Video driver
//
vid_driver v_drvr(.clk (sys_clk),
.rst_n (rst_na),
.vid_time (vid_time),
.x (x),
.y (y[8:1]),
.vid (vid),
.audio_o (audio_o),
.padl0 (PAD0),
.padl1 (PAD1),
.DEMO_MODE (DEMO_MODE),
.serv_ball (serv_ball),
.game_rst (game_rst),
.ball_speed (ball_speed)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; int n, k; bool d[1001]; long long dp[1001][2][1001]; int cnt[10001]; long long DP(int i, bool f, int j) { if (i == n) return cnt[j] == k; if (dp[i][f][j] != -1) return dp[i][f][j]; long long ret = 0; if (d[i] == 1) ret = (ret + DP(i + 1, f, j + 1)) % mod; else if (d[i] == 0 and f) ret = (ret + DP(i + 1, f, j + 1)) % mod; ret = (ret + DP(i + 1, f | (d[i] == 1), j)) % mod; return dp[i][f][j] = ret; } int main() { for (int i = 1; i <= 1000; i++) { cnt[i] = 1 + cnt[__builtin_popcount(i)]; } string s; cin >> s; n = s.size(); cin >> k; int i = 0; for (char c : s) d[i++] = c - 0 ; memset(dp, -1, sizeof dp); cout << DP(0, 0, 0) - (k == 1); }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; const int mod = 998244353; int up(int x, int y) { return x + y >= mod ? x + y - mod : x + y; } int a[1010], dp[1010][1010], pos[100010], n, k; int cal(int x) { for (int i = 0; i <= k; ++i) for (int j = 0; j <= n; ++j) dp[i][j] = 0; for (int i = 1; i <= n; ++i) dp[1][i] = 1; for (int i = 2; i <= k + 1; ++i) { for (int j = 1; j <= n; ++j) dp[i - 1][j] = up(dp[i - 1][j - 1], dp[i - 1][j]); for (int j = 1; j <= n; ++j) dp[i][j] = dp[i - 1][a[j] >= x ? pos[a[j] - x] : 0]; } return dp[k][n]; } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); sort(a + 1, a + 1 + n); for (int i = n; i >= 1; --i) pos[a[i]] = (a[i] == a[i + 1] ? pos[a[i + 1]] : i); for (int i = 1; i <= 100000; ++i) pos[i] = max(pos[i], pos[i - 1]); int ans = 0; for (int i = 1; i * (k - 1) <= 100000; ++i) ans = up(ans, cal(i)); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> static inline void amin(T &x, U y) { if (y < x) x = y; } template <typename T, typename U> static inline void amax(T &x, U y) { if (y > x) x = y; } const long long inf = (long long)1e18 + 17; const long long iinf = 1500000000; const long long dx[] = {1, 0, -1, 0}; const long long dy[] = {0, 1, 0, -1}; const long long mod = 1e9 + 7; bool test_case = 1; void solve() { string a, b; cin >> a >> b; long long next[a.size() + 10][26], n1 = a.size(); for (long long i = 0; i < 26; i++) next[n1][i] = inf; for (long long i = n1 - 1; i >= 0; i--) { for (long long j = 0; j < 26; j++) next[i][j] = next[i + 1][j]; next[i][a[i] - a ] = i; } long long n = b.size(); long long dp[n + 10][n + 10]; dp[0][0] = 0; for (long long ii = 0; ii < b.size(); ii++) { long long l1 = ii + 1, l2 = b.size() - l1; for (long long i = 0; i <= l1; i++) { for (long long j = 0; j <= l2; j++) { if (i == 0 && j == 0) continue; dp[i][j] = inf; if (j != 0) { long long op1 = dp[i][j - 1]; if (op1 != inf && ii + j < b.size()) { long long nex = b[ii + j] - a ; long long pos = next[op1][nex]; amin(dp[i][j], pos + 1); } } if (i != 0) { long long op1 = dp[i - 1][j]; if (op1 != inf) { long long nex = b[i - 1] - a ; long long pos = next[op1][nex]; amin(dp[i][j], pos + 1); } } } } if (dp[l1][l2] != inf) { cout << YES n ; return; } } cout << NO n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; if (test_case == true) cin >> t; for (long long i = 1; i <= t; i++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct point { long long x, a; } p[100]; int n; long long key[100][100]; long long k[100]; long long s[3], ans; long long v; void getb(long long ab, long long b, int cur) { if (ab < b * b) return; if (cur > n + 1) return; if (cur == n + 1) { long long a = ab / b; long long c = v / ab; long long tmp = a * c + ab + b * c; if (tmp < ans) { ans = tmp; s[0] = a, s[1] = b, s[2] = c; } return; } int t = p[cur].a - k[cur]; for (int i = t; i >= 0; i--) { getb(ab, b * key[cur][i], cur + 1); } } void dfs(long long c, int cur) { if (v / c < c * c || cur > n + 1) return; if (cur == n + 1) { long long ab = v / c; if (ab + 2 * sqrt(1.0 * v * c) <= ans) { getb(ab, 1, 1); } return; } for (int i = p[cur].a; i >= 0; i--) { k[cur] = i; dfs(c * key[cur][i], cur + 1); } } int main() { int cas; long long suma, sumb; scanf( %d , &cas); while (cas--) { scanf( %d , &n); v = 1; for (int i = 1; i <= n; i++) { cin >> p[i].x >> p[i].a; long long t = 1; key[i][0] = 1; for (int j = 1; j <= p[i].a; j++) { t *= p[i].x; key[i][j] = t; } v *= t; } ans = 2 * v + 1; s[0] = v, s[1] = s[2] = 1; dfs(1, 1); ans *= 2; cout << ans << << s[0] << << s[1] << << s[2] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; double mod(double a, double b) { long long int val = a / b; return a - val * b; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); double a, b, m, vx, vy, vz; cin >> a >> b >> m >> vx >> vy >> vz; double sx, sy, sz, t, x0, y0; t = -m / vy; sx = abs(vx * t); sz = vz * t; long long int val; if (sx > (3 * a) / 2) { sx -= (3 * a) / 2; val = sx / (a); if (val % 2 == 0) x0 = mod(sx, a); else x0 = a - mod(sx, a); } else if (sx <= a / 2) x0 = a / 2 + sx; else x0 = a - (sx - a / 2); if (vx < 0) x0 = a - x0; val = sz / (b); if (val % 2 == 0) y0 = mod(sz, b); else y0 = b - mod(sz, b); cout << fixed << setprecision(10) << x0 << << y0; }
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY RX IF
*/
module eth_phy_10g_rx_if #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* 10GBASE-R encoded interface
*/
output wire [DATA_WIDTH-1:0] encoded_rx_data,
output wire [HDR_WIDTH-1:0] encoded_rx_hdr,
/*
* SERDES interface
*/
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire [6:0] rx_error_count,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire rx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] serdes_rx_data_rev, serdes_rx_data_int;
wire [HDR_WIDTH-1:0] serdes_rx_hdr_rev, serdes_rx_hdr_int;
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_rx_data_rev[n] = serdes_rx_data[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_rx_hdr_rev[n] = serdes_rx_hdr[HDR_WIDTH-n-1];
end
end else begin
assign serdes_rx_data_rev = serdes_rx_data;
assign serdes_rx_hdr_rev = serdes_rx_hdr;
end
if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg [DATA_WIDTH-1:0] serdes_rx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_WIDTH-1:0] serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
for (n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_rx_data_pipe_reg[n] <= {DATA_WIDTH{1'b0}};
serdes_rx_hdr_pipe_reg[n] <= {HDR_WIDTH{1'b0}};
end
always @(posedge clk) begin
serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1];
serdes_rx_hdr_pipe_reg[n] <= n == 0 ? serdes_rx_hdr_rev : serdes_rx_hdr_pipe_reg[n-1];
end
end
assign serdes_rx_data_int = serdes_rx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_hdr_int = serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1];
end else begin
assign serdes_rx_data_int = serdes_rx_data_rev;
assign serdes_rx_hdr_int = serdes_rx_hdr_rev;
end
endgenerate
wire [DATA_WIDTH-1:0] descrambled_rx_data;
reg [DATA_WIDTH-1:0] encoded_rx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] encoded_rx_hdr_reg = {HDR_WIDTH{1'b0}};
reg [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
reg [30:0] prbs31_state_reg = 31'h7fffffff;
wire [30:0] prbs31_state;
wire [DATA_WIDTH+HDR_WIDTH-1:0] prbs31_data;
reg [6:0] rx_error_count_reg = 0;
reg [5:0] rx_error_count_1_reg = 0;
reg [5:0] rx_error_count_2_reg = 0;
reg [5:0] rx_error_count_1_temp = 0;
reg [5:0] rx_error_count_2_temp = 0;
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
)
descrambler_inst (
.data_in(serdes_rx_data_int),
.state_in(scrambler_state_reg),
.data_out(descrambled_rx_data),
.state_out(scrambler_state)
);
lfsr #(
.LFSR_WIDTH(31),
.LFSR_POLY(31'h10000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH+HDR_WIDTH),
.STYLE("AUTO")
)
prbs31_check_inst (
.data_in(~{serdes_rx_data_int, serdes_rx_hdr_int}),
.state_in(prbs31_state_reg),
.data_out(prbs31_data),
.state_out(prbs31_state)
);
integer i;
always @* begin
rx_error_count_1_temp = 0;
rx_error_count_2_temp = 0;
for (i = 0; i < DATA_WIDTH+HDR_WIDTH; i = i + 1) begin
if (i & 1) begin
rx_error_count_1_temp = rx_error_count_1_temp + prbs31_data[i];
end else begin
rx_error_count_2_temp = rx_error_count_2_temp + prbs31_data[i];
end
end
end
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
encoded_rx_hdr_reg <= serdes_rx_hdr_int;
if (PRBS31_ENABLE && rx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
rx_error_count_1_reg <= rx_error_count_1_temp;
rx_error_count_2_reg <= rx_error_count_2_temp;
rx_error_count_reg <= rx_error_count_1_reg + rx_error_count_2_reg;
end
end
assign encoded_rx_data = encoded_rx_data_reg;
assign encoded_rx_hdr = encoded_rx_hdr_reg;
assign rx_error_count = rx_error_count_reg;
wire serdes_rx_bitslip_int;
assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && rx_prbs31_enable);
eth_phy_10g_rx_frame_sync #(
.HDR_WIDTH(HDR_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES)
)
eth_phy_10g_rx_frame_sync_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_bitslip(serdes_rx_bitslip_int),
.rx_block_lock(rx_block_lock)
);
eth_phy_10g_rx_ber_mon #(
.HDR_WIDTH(HDR_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_ber_mon_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.rx_high_ber(rx_high_ber)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; if (n % 2 == 0) cout << 2; else cout << 1; }
|
#include <bits/stdc++.h> using namespace std; int n, m, l, r, cnt; long long ans; char s[101][10005]; int dfs(int x, int y, int d) { if (x == n - 1) return 1; if (s[x + 1][y] == . ) { l = y; r = y; ans++; cnt = 0; return dfs(x + 1, y, d); } if (s[x][y + d] == . ) { ans++; r = max(r, y + d); l = min(l, y + d); return dfs(x, y + d, d); } else if (s[x][y + d] == # ) { if (cnt > 2 * m) return 0; ans += 1; cnt++; if (d == 1) { ans += y - l; r = y; return dfs(x, l, -1); } else { ans += r - y; l = y; return dfs(x, r, 1); } } else { s[x][y + d] = . ; ans++; if (d == 1) { ans += y - l; r = y + 1; return dfs(x, l, -1); } else { ans += r - y; l = y - 1; return dfs(x, r, 1); } } } int main() { int i, j, k, t; while (~scanf( %d%d , &n, &m)) { m++; for (i = 0; i < n; i++) scanf( %s , s[i] + 1), s[i][0] = s[i][m] = # ; l = r = 1; ans = 0; j = dfs(0, 1, 1); if (j) printf( %I64d n , ans); else puts( Never ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n; inline bool check2(long long x, long long y3) { return (x * x + y3 * y3 * 3 <= n * n); } inline bool check(long long x, long long y3) { return check2(x - 2, y3) & check2(x - 1, y3 - 1) & check2(x + 1, y3 - 1) & check2(x + 2, y3) & check2(x + 1, y3 + 1) & check2(x - 1, y3 + 1); } long long calc(long long x, long long d) { long long l = 0, r = 3e6; while (l < r) { long long mid = (l + r + 1) / 2; long long y3 = d + mid * 2; if (check(x, y3)) l = mid; else r = mid - 1; } long long ret = r * 2; if (d == 0 && check(x, 0)) ret += 1; if (d == 1 && check(x, d)) ret += 2; return ret; } int main() { ios::sync_with_stdio(false); cin >> n; n *= 2; long long s = 0; int x = 3, d = 1; while (true) { long long t = calc(x, d); if (t == 0) break; s += t; x += 3, d ^= 1; } s *= 2; s += calc(0, 0); cout << s << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s, s5; cin >> s; int c = 0; string s3 = , s4 = ; s3 += s[0]; s3 += s[1]; s4 += s[3]; s4 += s[4]; int a = atoi(s3.c_str()); int b = atoi(s4.c_str()); while (1) { if (b == 59) { if (a == 23) a = 0, s3[0] = 0 , s3[1] = 0 ; else { a++; stringstream ss; ss << a; s5 = ss.str(); if (a < 10) { s3 = 0 ; s3 += s5; } else s3 = s5; } b = 0; s4[0] = 0 , s4[1] = 0 ; } else { b++; stringstream ss; ss << b; s5 = ss.str(); if (b < 10) { s4 = 0 ; s4 += s5; } else s4 = s5; } c++; if (s3[0] == s4[1] && s3[1] == s4[0] && c > 0) break; } cout << s3 << : << s4 << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__MUX4_PP_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_PP_BLACKBOX_V
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_gxb_gige_inst.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_gxb_gige_inst.v,v $
//
// $Revision: #1 $
// $Date: 2010/04/12 $
// Check in by : $Author: max $
// Author : Siew Kong NG
//
// Project : Triple Speed Ethernet - 1000 BASE-X PCS
//
// Description :
//
// Instantiation for Alt2gxb, Alt4gxb
//
// ALTERA Confidential and Proprietary
// Copyright 2007 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module altera_tse_gxb_gige_inst (
cal_blk_clk,
gxb_powerdown,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
rx_seriallpbken,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_patterndetect,
rx_rlv,
rx_syncstatus,
tx_clkout,
tx_dataout,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp
);
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter STARTING_CHANNEL_NUMBER = 0;
parameter ENABLE_ALT_RECONFIG = 0;
input cal_blk_clk;
input gxb_powerdown;
input pll_inclk;
input reconfig_clk;
input [3:0] reconfig_togxb;
input rx_analogreset;
input rx_cruclk;
input rx_datain;
input rx_digitalreset;
input rx_seriallpbken;
input tx_ctrlenable;
input [7:0] tx_datain;
input tx_digitalreset;
output [16:0] reconfig_fromgxb;
output rx_ctrldetect;
output [7:0] rx_dataout;
output rx_disperr;
output rx_errdetect;
output rx_patterndetect;
output rx_rlv;
output rx_syncstatus;
output tx_clkout;
output tx_dataout;
output rx_rmfifodatadeleted;
output rx_rmfifodatainserted;
output rx_runningdisp;
wire [16:0] reconfig_fromgxb;
wire [2:0] reconfig_togxb_alt2gxb;
wire reconfig_fromgxb_alt2gxb;
wire wire_reconfig_clk;
wire [3:0] wire_reconfig_togxb;
(* altera_attribute = "-name MESSAGE_DISABLE 10036" *)
wire [16:0] wire_reconfig_fromgxb;
generate if (ENABLE_ALT_RECONFIG == 0)
begin
assign wire_reconfig_clk = 1'b0;
assign wire_reconfig_togxb = 4'b0010;
assign reconfig_fromgxb = {17{1'b0}};
end
else
begin
assign wire_reconfig_clk = reconfig_clk;
assign wire_reconfig_togxb = reconfig_togxb;
assign reconfig_fromgxb = wire_reconfig_fromgxb;
end
endgenerate
generate if ( DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX")
begin
altera_tse_alt2gxb_gige the_altera_tse_alt2gxb_gige
(
.cal_blk_clk (cal_blk_clk),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(reconfig_togxb_alt2gxb),
.reconfig_fromgxb(reconfig_fromgxb_alt2gxb),
.rx_analogreset (rx_analogreset),
.rx_cruclk (rx_cruclk),
.rx_ctrldetect (rx_ctrldetect),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_seriallpbken (rx_seriallpbken),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp)
);
defparam
the_altera_tse_alt2gxb_gige.starting_channel_number = STARTING_CHANNEL_NUMBER,
the_altera_tse_alt2gxb_gige.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG;
assign reconfig_togxb_alt2gxb = wire_reconfig_togxb[2:0];
assign wire_reconfig_fromgxb = {{16{1'b0}}, reconfig_fromgxb_alt2gxb};
end
endgenerate
generate if ( DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "HARDCOPYIV" || DEVICE_FAMILY == "ARRIAIIGX")
begin
altera_tse_alt4gxb_gige the_altera_tse_alt4gxb_gige
(
.cal_blk_clk (cal_blk_clk),
.fixedclk(wire_reconfig_clk),
.fixedclk_fast(1'b0),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(wire_reconfig_togxb),
.reconfig_fromgxb(wire_reconfig_fromgxb),
.rx_analogreset (rx_analogreset),
.rx_cruclk (rx_cruclk),
.rx_ctrldetect (rx_ctrldetect),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_seriallpbken (rx_seriallpbken),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp)
);
defparam
the_altera_tse_alt4gxb_gige.starting_channel_number = STARTING_CHANNEL_NUMBER;
end
endgenerate
generate if ( DEVICE_FAMILY == "CYCLONEIVGX")
begin
altera_tse_altgx_civgx_gige the_altera_tse_alt_gx_civgx
(
.cal_blk_clk (cal_blk_clk),
.gxb_powerdown (gxb_powerdown),
.pll_inclk (pll_inclk),
.reconfig_clk(wire_reconfig_clk),
.reconfig_togxb(wire_reconfig_togxb),
.rx_analogreset (rx_analogreset),
.rx_ctrldetect (rx_ctrldetect),
.rx_datain (rx_datain),
.rx_dataout (rx_dataout),
.rx_digitalreset (rx_digitalreset),
.rx_disperr (rx_disperr),
.rx_errdetect (rx_errdetect),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_rlv),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_clkout),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_dataout (tx_dataout),
.tx_digitalreset (tx_digitalreset),
.reconfig_fromgxb(wire_reconfig_fromgxb[4:0]),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp)
);
defparam
the_altera_tse_alt_gx_civgx.starting_channel_number = STARTING_CHANNEL_NUMBER;
end
endgenerate
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SOC_timer_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
#include <bits/stdc++.h> using namespace std; const string YES = Yes ; const string NO = No ; string solve() { int N; cin >> N; vector<int> p(N); for (int i = 0; i < (N); ++i) { cin >> p[i]; } for (int i = 0; i < (N - 1); ++i) { if (p[i] + 1 == p[i + 1]) { continue; } if (p[i] > p[i + 1]) { continue; } return NO; } return YES; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int T; cin >> T; for (int t = 0; t < (T); ++t) { cout << solve() << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); cin.sync_with_stdio(0); cout.tie(0); string s, t, b; int n; vector<pair<char, char>> v; set<char> z; bool fine = false; char a[26]; for (int i = 0; i < 26; i++) a[i] = @ ; cin >> s >> t; for (int i = 0; i < s.length(); i++) if (a[s[i] - a ] == @ ) a[s[i] - a ] = t[i]; else if (a[s[i] - a ] != t[i]) { cout << -1; return 0; } for (int i = 0; i < 26; i++) if (a[i] != @ ) { if (((char)(i + a ) != a[a[i] - a ]) && ( @ != a[a[i] - a ])) { cout << -1; return 0; } } for (int i = 0; i < 26; i++) if ((a[i] != (char)( a + i)) && (a[i] != @ )) { fine = false; for (int j = 0; j < v.size(); j++) if ((v[j].first == a[i]) && (v[j].second == (char)( a + i))) fine = true; if (fine == false) v.push_back(make_pair((char)( a + i), a[i])); } for (int i = 0; i < v.size(); i++) z.insert(v[i].second); if (z.size() != v.size()) { cout << -1; return 0; } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) cout << v[i].first << << v[i].second << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, len, i, j, a[300009]; int main() { while (scanf( %I64d , &n) == 1) { for (i = 0; i < n; i++) { scanf( %I64d , &a[i]); } sort(a, a + n); if (n % 2 != 0) { printf( %I64d n , a[n / 2]); } else { printf( %I64d n , a[n / 2 - 1]); } } return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_64_32.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.2 Build 153 07/15/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_64_32 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [63:0] data;
input rdreq;
input wrreq;
output empty;
output [63:0] q;
wire sub_wire0;
wire [63:0] sub_wire1;
wire empty = sub_wire0;
wire [63:0] q = sub_wire1[63:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 64,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "64"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "64"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_64_32_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_2_V
`define SKY130_FD_SC_LP__O311A_2_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_2_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; int MM[500], FF[500]; int main() { ios::sync_with_stdio(0); int N; cin >> N; for (int i = 0; i < N; i++) { char g; int from, to; cin >> g >> from >> to; int *v; if (g == M ) for (int i = from; i <= to; i++) MM[i]++; else for (int i = from; i <= to; i++) FF[i]++; } int MAX = 0; for (int i = 1; i < 400; i++) MAX = max(MAX, min(MM[i], FF[i]) * 2); cout << MAX; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1010; const int INF = 100000000; string str[maxn]; int dp[maxn][maxn]; int n, m, ans; int flag[maxn][maxn]; int dir[4][2] = {0, -1, 0, 1, 1, 0, -1, 0}; char ch[5] = { D , I , M , A }; vector<pair<int, int> > q; bool Ok(int ki, int kj) { if (ki >= 0 && ki < n && kj >= 0 && kj < m) return true; return false; } int dfs(int ki, int kj, int d, int f) { int Ans = 1; for (int i = 0; i < 4; i++) { int ti = ki + dir[i][0]; int tj = kj + dir[i][1]; if (Ok(ti, tj) && str[ti][tj] == ch[d + 1 < 4 ? d + 1 : 0]) { if (flag[ti][tj] < f) { int k = flag[ti][tj]; flag[ti][tj] = f; if (dp[ti][tj] > 0) Ans = max(Ans, dp[ti][tj] + 1); else Ans = max(Ans, dfs(ti, tj, d + 1 < 4 ? d + 1 : 0, f) + 1); flag[ti][tj] = k; } else { Ans = INF; break; } } } dp[ki][kj] = Ans; return Ans; } void solve() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { cin >> str[i]; for (int j = 0; j < m; j++) { if (str[i][j] == D ) q.push_back(pair<int, int>(i, j)); } } for (int i = 0; i < q.size(); i++) { if (dp[q[i].first][q[i].second] == 0) ans = max(ans, dfs(q[i].first, q[i].second, 0, i + 1) / 4); } if (ans == 0) cout << Poor Dima! << endl; else if (ans >= 2500000) cout << Poor Inna! << endl; else cout << ans << endl; } int main() { solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int ans[30], tans[30], flot[30]; memset(flot, 0, sizeof(flot)); memset(ans, 0x3f3f3f3f, sizeof(ans)); int n, num[55], top = 0, m; string s, s1; cin >> n; cin >> s; for (int i = 0; i < n; i++) { if (s[i] == * ) num[top++] = i; else { flot[s[i] - a ] = 1; ans[s[i] - a ] = 0; } } cin >> m; for (int i = 0; i < m; i++) { int tt = 0; memset(tans, 0, sizeof(tans)); cin >> s1; for (int i = 0; i < top; i++) { if (flot[s1[num[i]] - a ] == 1) { tt = 1; break; } tans[s1[num[i]] - a ]++; } for (int i = 0; i < n; i++) { if (s[i] == * ) continue; if (s[i] != s1[i]) { tt = 1; break; } } if (tt) continue; for (int i = 0; i < 30; i++) ans[i] = min(ans[i], tans[i]); } int je = 0; for (int i = 0; i < 30; i++) if (ans[i] != 0) je++; cout << je << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<int, int> w[200000 + 20]; int a[200000 + 20][3]; vector<pair<int, pair<int, int> > > to_compress; int n; void maximize(int &a, int b) { if (a < b) a = b; } struct Fenwick_tree { int bit[1000000 + 50]; void update(int x, int v) { for (; x <= 1000000; x += x & (-x)) maximize(bit[x], v); } int get(int x) { int res = 0; for (; x > 0; x -= x & (-x)) maximize(res, bit[x]); return res; } }; Fenwick_tree LIS; int ans = 0; void compress() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d %d , &w[i].first, &w[i].second); sort(w + 1, w + 1 + n); for (int i = 1; i <= n; i++) { to_compress.push_back(pair<int, pair<int, int> >(w[i].first + w[i].second, pair<int, int>(i, 1))); to_compress.push_back(pair<int, pair<int, int> >(w[i].first - w[i].second, pair<int, int>(i, 2))); } sort(to_compress.begin(), to_compress.end()); int curr = 0; for (int i = 0; i < to_compress.size(); i++) { if (i == 0 || to_compress[i].first > to_compress[i - 1].first) curr++; a[to_compress[i].second.first][to_compress[i].second.second] = curr; } } void solve() { for (int i = 1; i <= n; i++) { int x = LIS.get(a[i][2]) + 1; maximize(ans, x); LIS.update(a[i][1], x); } printf( %d , ans); } int main() { compress(); solve(); }
|
// file: clk_gen.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______123.073_____85.928
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________250.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_gen,clk_wiz_v5_1,{component_name=clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_gen
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset
);
clk_gen_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int oo = 0x3f3f3f3f; const int MAXN = 200010; const double EPS = 1e-7; inline int read() { char c = getchar(); int x = 0, f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + (c - 0 ); c = getchar(); } return x * f; } char s[55], t[55]; int cnt[30], vis[55]; vector<int> pos[30]; vector<int> ans; int main() { int n = read(); scanf( %s , s + 1); scanf( %s , t + 1); for (int i = 1; i <= n; i++) cnt[s[i] - a ]++; for (int i = 1; i <= n; i++) pos[t[i] - a ].push_back(i); int flag = 1; for (int i = 0; i < 26; i++) if (cnt[i] != (int)((pos[i]).size())) flag = 0; if (flag) { for (int i = 1; i <= n; i++) { for (int j = i; j <= n; j++) { if (s[j] == t[i]) { for (int k = j - 1; k >= i; k--) { swap(s[k], s[k + 1]); ans.push_back(k); } break; } } } cout << (int)((ans).size()) << endl; for (int i = 0; i < (int)((ans).size()); i++) cout << ans[i] << ; } else puts( -1 ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX = 1005; map<pair<int, int>, int> mapa; int main() { int n, h, m; scanf( %d , &n); int c = 0; for (int i = 0; i < n; i++) { scanf( %d%d , &h, &m); int x = ++mapa[make_pair(h, m)]; if (x > c) c = x; } printf( %d n , c); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> knapsack(long long lim, vector<int> allItems) { vector<bool> mark; int mx = 0; for (auto it : allItems) mx += it; mx = min((long long)mx, lim); mark.assign(mx + 1, 0); mark[0] = true; for (auto it : allItems) { for (int i = (int)mx; i >= (int)it; i--) { mark[i] = max(mark[i], mark[i - it]); } } vector<int> ret; for (int i = (int)0; i <= (int)mx; i++) if (mark[i]) ret.push_back(i); return ret; } long long W; long long cnt[9]; long long max840 = 0; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> W; for (int i = (int)1; i <= (int)8; i++) cin >> cnt[i]; for (int i = (int)1; i <= (int)8; i++) { int blockSize = 840 / i; if (cnt[i] < blockSize) continue; max840 += cnt[i] / blockSize; cnt[i] %= blockSize; if (cnt[i] < blockSize) max840 -= 1, cnt[i] += blockSize; } vector<int> allItems; for (int i = (int)1; i <= (int)8; i++) { int rem = cnt[i]; for (int k = (int)0; k <= (int)60; k++) { if (rem < (1LL << k)) { allItems.push_back(rem * i); break; } else { rem -= (1LL << k); allItems.push_back((1LL << k) * i); } } } vector<int> allCreatedValue = knapsack(W, allItems); long long ans = 0; for (auto it : allCreatedValue) { long long left = W - it; left -= 1LL * min(left / 840, max840) * 840; ans = max(ans, W - left); } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { long long n; cin >> n; long long a, b, c; cin >> a >> b >> c; string s; cin >> s; long long x = 0, y = 0, z = 0; for (long long i = 0; i < n; i++) { if (s[i] == R ) { x++; } else if (s[i] == P ) { y++; } else { z++; } } long long win = 0; win = min(a, z) + min(b, x) + min(c, y); long long r = (n + 1) / 2; if (win >= r) { cout << YES << endl; char ans[n]; for (long long i = 0; i < n; i++) { if (s[i] == S && a) { ans[i] = R ; a--; z--; } else if (s[i] == R && b) { ans[i] = P ; b--; x--; } else if (s[i] == P && c) { ans[i] = S ; c--; y--; } else if (s[i] == S && b > x) { ans[i] = P ; b--; } else if (s[i] == S && c > y) { ans[i] = S ; c--; } else if (s[i] == R && a > z) { ans[i] = R ; a--; } else if (s[i] == R && c > y) { ans[i] = S ; c--; } else if (s[i] == P && a > z) { ans[i] = R ; a--; } else if (s[i] == P && b > x) { ans[i] = P ; b--; } } for (long long i = 0; i < n; i++) { cout << ans[i]; } cout << endl; } else { cout << NO << endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; return x * f; } namespace Sa { struct Node { double x, y; Node() {} Node(double x, double y) : x(x), y(y) {} Node operator-(Node a) const { return Node(x - a.x, y - a.y); } double operator*(Node a) const { return x * a.y - y * a.x; } } a[1], b[1]; double l, r, Mid, Ans, Now, x, y, Ax, T, N2; int i, j, k, n, m; inline double Getrand() { return rand() % 1000 / 1000.0; } inline double Gety(double x) { for (int i = 1; i < n; i++) if (a[i + 1].x > x) return (a[i + 1].y - a[i].y) / (a[i + 1].x - a[i].x) * (x - a[i].x) + a[i].y; } inline bool Check(Node A) { for (int i = 1; i < n; i++) if ((A - a[i]) * (A - a[i + 1]) < 0) return 0; return 1; } inline double Calc(double x) { double l = 0, r = 0, Mid; while (r - l > 1) { Mid = (l + r) / 2.0; if (Check(Node(x, Mid))) r = Mid; else l = Mid; } l -= Gety(x); if (l < Ans) Ans = l, Ax = x; return l; } inline void SA(double T) { for (; T > 0.00001; T *= 0.99) { y = x + T * (Getrand() * 2 - 1); if (y < a[1].x || y > a[n].x) continue; N2 = Calc(x) - Calc(y); if (N2 > 0 || exp(N2 / T) > Getrand()) x = y; } for (int i = 1; i <= 1000; i++) { y = Ax + T * (Getrand() * 2 - 1); if (y < a[1].x || y > a[n].x) continue; Calc(y); } } } // namespace Sa int main() { int t = read(); while (t--) { int n = read(); double T = n; if (n * n < 4 * n) { printf( N n ); continue; } double a = (T + sqrt(T * T - 4.0 * T)) / 2.0; double b = (T - sqrt(T * T - 4.0 * T)) / 2.0; printf( Y %.10f %.10f n , a, b); } }
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XORCY.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / XOR for Carry Logic with General Output
// /___/ /\ Filename : XORCY.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module XORCY (O, CI, LI);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input CI, LI;
xor X1 (O, CI, LI);
`ifdef XIL_TIMING
specify
(CI => O) = (0:0:0, 0:0:0);
(LI => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a[110][110], i, j, maxi, f, maxid[110], c = 0, poi; scanf( %d%d , &n, &m); for (i = 0; i < m; i++) { for (j = 0; j < n; j++) scanf( %d , &a[i][j]); } for (i = 0; i < m; i++) { maxi = a[i][0]; maxid[i] = 0; for (j = 0; j < n; j++) { if (maxi < a[i][j]) { maxi = a[i][j]; maxid[i] = j; } } } f = 0; sort(maxid, maxid + m); poi = maxid[0]; for (i = 1; i < m; i++) { if (maxid[i] != maxid[i - 1]) { if (f < c) { f = c; poi = maxid[i - 1]; } c = 0; } else c++; } printf( %d n , poi + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool arng(pair<long long, long long> p, pair<long long, long long> q) { if (p.first > q.first) return true; if (p.first == q.first) { return (p.second < q.second); } return false; } void solve() { long long n, m; cin >> n; long long ac[n]; pair<long long, long long> a[n]; for (long long i = 0; i < n; i++) { cin >> a[i].first; ac[i] = a[i].first; a[i].second = i; } sort(a, a + n, arng); cin >> m; while (m--) { long long k, pos; cin >> k >> pos; long long s = 0; long long posa[k]; for (long long i = 0; i < k; i++) { posa[i] = a[i].second; } sort(posa, posa + k); cout << ac[posa[pos - 1]] << endl; } return; } int32_t main() { solve(); }
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#include <bits/stdc++.h> using namespace std; int p, n, a[100100], b[100100]; bool ok(double t) { double charging = t * p; for (int i = 0; i < n; ++i) { double x = b[i] - a[i] * t; if (x >= 0) continue; else charging += x; if (charging < 0) return 0; } return 1; } int main() { cin >> n >> p; for (int i = 0; i < n; ++i) cin >> a[i] >> b[i]; double low = 0, high = 1e11, tol = 1e-7, mid; while (high - low > tol) { mid = (high + low) / 2; if (ok(mid)) low = mid; else high = mid; } if (low < 9.9e10) cout << setprecision(10) << fixed << mid; else cout << -1; }
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#include <bits/stdc++.h> using namespace std; int main() { int t, n; cin >> t; while (t--) { cin >> n; int ar[n], e = 0, o = 0; for (int i = 0; i < n; i++) cin >> ar[i]; for (int i = 0; i < n; i++) { if (ar[i] % 2 == 0) e = e + 1; else o = o + 1; } if ((e == n) || (o == n)) cout << YES << endl; else cout << NO << endl; } return 0; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_decrement (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter value = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_DECREMENT";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_decrement_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_decrement_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_decrement_psl_logic.v"
`else
`endmodule // ovl_decrement
`endif
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : VGA Top Level
// File : vga_top.v
// Author : Frank Bruno
// Created : 11-Jun-2002
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description : This file is the top level stimulus file for Borealis
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
// vga - VGA Core
// vga_hint - VGA Hist interface gasket
// vga_mint - VGA Memory Controller interface
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module vga_top
(
input sense_n, // RAMDAC Sense Pin
input mclock, // Memory controller clock
input resetn, // System Reset
input hclk, // PCI Host Clock
input crtclk, // CRT Clock
input vga_req, // VGA request
input vga_rdwr, // VGA write/read cycle
input vga_mem, // VGA memory/io cycle
input [3:0] hst_byte, // Host byte enables
input [22:0] hst_addr, // Host address (byte address)
input [31:0] hst_din, // Data from HBI to VGA_HINT
input [31:0] mem_din, // Data from MC to VGA
input mem_ack, // Memory Acknowledge
input mem_ready_n, // VGA data ready
input vga_en, // Signal to disable VGA crt and ref R
input mem_ready, // MC is ready
output [31:0] hst_dout, // Data from VGA_HINT to HBI
output [2:0] vga_stat, /* VGA status back to HBI
* [1:0]=CTL_BITS[1:0] spec
* CTL_BITS[4:2] not used here
* [2]= CTL_BITS[5] see spec */
output vga_push, // VGA push for read data
output vga_ready, // VGA Ready for next cycle
output v_clksel, // VGA frequency Selects
output [7:0] v_pd, // VGA Pixel Data
output v_blank, // VGA Blank
output v_hrtc, // VGA Hsync
output v_vrtc, // VGA Vsync
output mem_req, // Request a memory cycle
output vga_rd_wrn, // Read or write
output [17:0] vga_addr, // Address lines to memory
output [3:0] vga_we, // Write enables for each byte
output [31:0] vga_data_in // Data from VGA core to VGA_MINT
);
/* Internal VGA core signals */
wire [3:0] dummy_we; // just to stop warnings
wire [31:0] vga_hst_din; // Data from VGA_HINT to VGA core
wire [31:0] vga_hst_dout; // Data from VGA core to VGA_HINT
wire [22:0] haddr; // 23 bit address lines from Host
wire [3:0] byte_en; // Byte enable signals
wire hst_mem_io; // memory access or IO access. 1 - Mem, 0 - IO.
wire hst_rd_wr; // 1 - read, 0 - write
wire vga_sel; /* Valid address has been decoded in
* SVGA memory or IO space */
wire vga_ready_n; /* Indicates that the SVGA core has completed
* the current cycle and is ready for the
* next cycle */
wire [5:0] vga_cntrl_tmp;
assign vga_stat = { vga_cntrl_tmp[5], vga_cntrl_tmp[1:0]};
vga_hint U_HINT
(
.hclk (hclk),
.resetn (resetn),
.vga_req_0 (vga_req),
.vga_rdwr (vga_rdwr),
.vga_mem (vga_mem),
.hst_byte (hst_byte),
.hst_din (hst_din),
.hst_addr (hst_addr),
.mclock (mclock),
.vga_hst_dout (vga_hst_dout),
.vga_ready_n (vga_ready_n),
.hst_dout (hst_dout),
.vga_hst_din (vga_hst_din),
.haddr (haddr),
.vga_sel (vga_sel),
.hst_rd_wr (hst_rd_wr),
.byte_en (byte_en),
.hst_mem_io (hst_mem_io),
.vga_ready_2 (vga_ready),
.vga_push_1 (vga_push)
);
vga U_VGA
(
.t_haddr (haddr),
.t_byte_en_n (byte_en),
.t_mem_io_n (hst_mem_io),
.t_hrd_hwr_n (hst_rd_wr),
.t_hreset_n (resetn),
.t_mem_clk (mclock),
.t_svga_sel (vga_sel),
.t_crt_clk (crtclk),
.t_sense_n (sense_n),
.svga_ack (mem_ack),
.t_data_ready_n (mem_ready_n),
.m_t_mem_data_in (mem_din),
.t_hdata_in (vga_hst_din),
.vga_en (vga_en),
.mem_ready (mem_ready),
.m_t_mem_data_out (vga_data_in),
.t_hdata_out (vga_hst_dout),
.c_t_clk_sel (v_clksel),
.c_t_cblank_n (v_blank),
.c_t_hsync (v_hrtc),
.c_t_vsync (v_vrtc),
.h_t_ready_n (vga_ready_n),
.a_t_pix_data (v_pd),
.m_t_mem_addr (vga_addr),
.m_t_mwe_n ({dummy_we, vga_we}),
.m_t_svga_req (mem_req),
.g_t_ctl_bits (vga_cntrl_tmp),
.m_mrd_mwr_n (vga_rd_wrn)
);
endmodule
|
//-----------------------------------------------------------------
// USB CDC Device
// V0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module usbf_sie_tx
(
// Inputs
input clk_i
,input rst_i
,input enable_i
,input chirp_i
,input utmi_txready_i
,input tx_valid_i
,input [ 7:0] tx_pid_i
,input data_valid_i
,input data_strb_i
,input [ 7:0] data_i
,input data_last_i
// Outputs
,output [ 7:0] utmi_data_o
,output utmi_txvalid_o
,output tx_accept_o
,output data_accept_o
);
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
`include "usbf_defs.v"
localparam STATE_W = 3;
localparam STATE_TX_IDLE = 3'd0;
localparam STATE_TX_PID = 3'd1;
localparam STATE_TX_DATA = 3'd2;
localparam STATE_TX_CRC1 = 3'd3;
localparam STATE_TX_CRC2 = 3'd4;
localparam STATE_TX_DONE = 3'd5;
localparam STATE_TX_CHIRP = 3'd6;
reg [STATE_W-1:0] state_q;
reg [STATE_W-1:0] next_state_r;
//-----------------------------------------------------------------
// Wire / Regs
//-----------------------------------------------------------------
reg last_q;
//-----------------------------------------------------------------
// Request Type
//-----------------------------------------------------------------
reg data_pid_q;
reg data_zlp_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
data_pid_q <= 1'b0;
data_zlp_q <= 1'b0;
end
else if (!enable_i)
begin
data_pid_q <= 1'b0;
data_zlp_q <= 1'b0;
end
else if (tx_valid_i && tx_accept_o)
begin
case (tx_pid_i)
`PID_MDATA, `PID_DATA2, `PID_DATA0, `PID_DATA1:
begin
data_pid_q <= 1'b1;
data_zlp_q <= data_valid_i && (data_strb_i == 1'b0) && data_last_i;
end
default :
begin
data_pid_q <= 1'b0;
data_zlp_q <= 1'b0;
end
endcase
end
else if (next_state_r == STATE_TX_CRC1)
begin
data_pid_q <= 1'b0;
data_zlp_q <= 1'b0;
end
assign tx_accept_o = (state_q == STATE_TX_IDLE);
//-----------------------------------------------------------------
// Next state
//-----------------------------------------------------------------
always @ *
begin
next_state_r = state_q;
//-----------------------------------------
// State Machine
//-----------------------------------------
case (state_q)
//-----------------------------------------
// IDLE
//-----------------------------------------
STATE_TX_IDLE :
begin
if (chirp_i)
next_state_r = STATE_TX_CHIRP;
else if (tx_valid_i)
next_state_r = STATE_TX_PID;
end
//-----------------------------------------
// TX_PID
//-----------------------------------------
STATE_TX_PID :
begin
// Data accepted
if (utmi_txready_i)
begin
if (data_zlp_q)
next_state_r = STATE_TX_CRC1;
else if (data_pid_q)
next_state_r = STATE_TX_DATA;
else
next_state_r = STATE_TX_DONE;
end
end
//-----------------------------------------
// TX_DATA
//-----------------------------------------
STATE_TX_DATA :
begin
// Data accepted
if (utmi_txready_i)
begin
// Generate CRC16 at end of packet
if (data_last_i)
next_state_r = STATE_TX_CRC1;
end
end
//-----------------------------------------
// TX_CRC1 (first byte)
//-----------------------------------------
STATE_TX_CRC1 :
begin
// Data sent?
if (utmi_txready_i)
next_state_r = STATE_TX_CRC2;
end
//-----------------------------------------
// TX_CRC (second byte)
//-----------------------------------------
STATE_TX_CRC2 :
begin
// Data sent?
if (utmi_txready_i)
next_state_r = STATE_TX_DONE;
end
//-----------------------------------------
// TX_DONE
//-----------------------------------------
STATE_TX_DONE :
begin
// Data sent?
if (!utmi_txvalid_o || utmi_txready_i)
next_state_r = STATE_TX_IDLE;
end
//-----------------------------------------
// TX_CHIRP
//-----------------------------------------
STATE_TX_CHIRP :
begin
if (!chirp_i)
next_state_r = STATE_TX_IDLE;
end
default :
;
endcase
// USB reset but not chirping...
if (!enable_i && !chirp_i)
next_state_r = STATE_TX_IDLE;
end
// Update state
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
state_q <= STATE_TX_IDLE;
else
state_q <= next_state_r;
//-----------------------------------------------------------------
// Data Input
//-----------------------------------------------------------------
reg input_valid_r;
reg [7:0] input_byte_r;
reg input_last_r;
always @ *
begin
input_valid_r = data_strb_i & data_pid_q;
input_byte_r = data_i;
input_last_r = data_last_i;
end
reg data_accept_r;
always @ *
begin
if (state_q == STATE_TX_DATA)
data_accept_r = utmi_txready_i;
else if (state_q == STATE_TX_PID && data_zlp_q)
data_accept_r = utmi_txready_i;
else
data_accept_r = 1'b0;
end
assign data_accept_o = data_accept_r;
//-----------------------------------------------------------------
// CRC16: Generate CRC16 on outgoing data
//-----------------------------------------------------------------
reg [15:0] crc_sum_q;
wire [15:0] crc_out_w;
reg crc_err_q;
usbf_crc16
u_crc16
(
.crc_in_i(crc_sum_q),
.din_i(utmi_data_o),
.crc_out_o(crc_out_w)
);
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
crc_sum_q <= 16'hFFFF;
else if (state_q == STATE_TX_IDLE)
crc_sum_q <= 16'hFFFF;
else if (state_q == STATE_TX_DATA && utmi_txvalid_o && utmi_txready_i)
crc_sum_q <= crc_out_w;
//-----------------------------------------------------------------
// Output
//-----------------------------------------------------------------
reg valid_q;
reg [7:0] data_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
valid_q <= 1'b0;
data_q <= 8'b0;
last_q <= 1'b0;
end
else if (!enable_i)
begin
valid_q <= 1'b0;
data_q <= 8'b0;
last_q <= 1'b0;
end
else if (tx_valid_i && tx_accept_o)
begin
valid_q <= 1'b1;
data_q <= tx_pid_i;
last_q <= 1'b0;
end
else if (utmi_txready_i)
begin
valid_q <= 1'b0;
data_q <= 8'b0;
last_q <= 1'b0;
end
reg utmi_txvalid_r;
reg [7:0] utmi_data_r;
always @ *
begin
if (state_q == STATE_TX_CHIRP)
begin
utmi_txvalid_r = 1'b1;
utmi_data_r = 8'b0;
end
else if (state_q == STATE_TX_CRC1)
begin
utmi_txvalid_r = 1'b1;
utmi_data_r = crc_sum_q[7:0] ^ 8'hFF;
end
else if (state_q == STATE_TX_CRC2)
begin
utmi_txvalid_r = 1'b1;
utmi_data_r = crc_sum_q[15:8] ^ 8'hFF;
end
else if (state_q == STATE_TX_DATA)
begin
utmi_txvalid_r = data_valid_i;
utmi_data_r = data_i;
end
else
begin
utmi_txvalid_r = valid_q;
utmi_data_r = data_q;
end
end
assign utmi_txvalid_o = utmi_txvalid_r;
assign utmi_data_o = utmi_data_r;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3001; const int mod = 1000000007; char s[N][N]; int f[N][N]; int calc(int sr, int sc, int tr, int tc) { if (tr < sr || tc < sc) return 0; int n = tr - sr + 1, m = tc - sc + 1; f[0][0] = (s[sr][sc] != # ); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) if (i || j) { f[i][j] = 0; if (i > 0) f[i][j] += f[i - 1][j]; if (j > 0) f[i][j] += f[i][j - 1]; f[i][j] %= mod; if (s[i + sr][j + sc] == # ) f[i][j] = 0; } } return f[n - 1][m - 1]; } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %s , s[i]); int a, b, c, d; a = calc(0, 1, n - 2, m - 1); b = calc(1, 0, n - 1, m - 2); c = calc(0, 1, n - 1, m - 2); d = calc(1, 0, n - 2, m - 1); printf( %lld n , ((1LL * a * b - 1LL * c * d) % mod + mod) % mod); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_FUNCTIONAL_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_tck the_TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_sysclk the_TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <>
* 2019 Eddie Hung <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// ============================================================================
// Box containing MUXF7.[AB] + MUXF8,
// Necessary to make these an atomic unit so that
// ABC cannot optimise just one of the MUXF7 away
// and expect to save on its delay
(* abc9_box, lib_whitebox *)
module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
assign O = S1 ? (S0 ? I3 : I2)
: (S0 ? I1 : I0);
specify
(I0 => O) = 294;
(I1 => O) = 297;
(I2 => O) = 311;
(I3 => O) = 317;
(S0 => O) = 390;
(S1 => O) = 273;
endspecify
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 0x3f3f3f3f; const double eps = 1e-6; const long long mod = 998244353; inline string getstr(string &s, long long l, long long r) { string ret = ; for (long long i = l; i <= r; i++) ret.push_back(s[i]); return ret; } long long modpow(long long x, long long y, long long md = mod) { if (y == 0) return 1; long long ret = modpow(x, y >> 1, md); ret = (long long)ret * ret % md; if (y & 1) ret = (long long)ret * x % md; return ret; } string s; vector<pair<long long, long long> > g[2005]; long long value[2005]; long long LEN = 0; bool error = 0; void add_edge(long long x, long long y, long long cost) { g[x].push_back(make_pair(y, cost)); g[y].push_back(make_pair(x, cost)); } void dfs(long long x) { if (error) return; for (auto p : g[x]) { if (~value[p.first] && value[p.first] != value[x] ^ p.second) error = 1; if (error) return; if (~value[p.first]) continue; value[p.first] = value[x] ^ p.second; dfs(p.first); } } long long calc(long long len) { LEN = len; memset(value, -1, sizeof value); long long Maxa = (len) / 2; long long Maxb = ((long long)s.size() - 1) / 2; swap(Maxa, Maxb); for (long long i = 0; i <= 2002; i++) g[i].clear(); value[0] = 1; value[1001] = 1; for (long long i = 0; i < s.size(); i++) { if (s[i] == ? ) continue; long long posa = (i <= Maxa ? i : ((long long)s.size() - i - 1)); long long posb = (i <= Maxb ? i : (len - i)); if (i > len) { if (~value[posa] && value[posa] != s[i] - 0 ) return 0; value[posa] = s[i] - 0 ; continue; } add_edge(posa, posb + 1001, s[i] - 0 ); } long long ret = 1; error = 0; for (long long i = 1; i <= 2002; i++) { if (~value[i]) dfs(i); } for (long long i = 1; i <= 2002; i++) { if (((0 <= i && i <= Maxa) || (1001 <= i && i <= 1001 + Maxb)) && value[i] == -1) { value[i] = 0; (ret *= 2) %= mod; dfs(i); } if (error) return 0; } return ret; } signed main() { cin >> s; reverse(s.begin(), s.end()); long long ans = 0; for (long long len = 0; len < s.size(); len++) { (ans += calc(len)) %= mod; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> std::pair<T, U> operator+(const std::pair<T, U>& l, const std::pair<T, U>& r) { return {l.first + r.first, l.second + r.second}; } typedef void (*callback_function)(void); const long long ZERO = 0LL; const long long INF64 = 1e18; const int INF32 = 1e9; const int MOD = 1e9 + 7; const long double PI = acos(-1.0L); const long double EPS = static_cast<long double>(1e-9); long long inv(long long a, long long b) { if (a != 1) { return b - (inv(b % a, a) * b) / a; } return 1; } inline int Pow(int a, int k) { int s = 1; for (; k; k >>= 1) { k& 1 ? s = 1LL * s * a % MOD : 0; a = 1LL * a * a % MOD; } return s; } const int N = 1e6 + 7; void input() {} char a[N][20]; void solve() { int n; scanf( %d , &n); for (int i = (0); i < (n); i++) { scanf( %s , a[i]); } set<string> st; for (int i = (n - 1); i >= (0); i--) { if (!st.count(a[i])) { printf( %s n , a[i]); st.insert(a[i]); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(); { input(); solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, m, v; int main() { n = read(); m = read(); v = read(); if (m > (long long)(n - 1) * (n - 2) / 2 + 1 || m < n - 1) { printf( -1 n ); } else { for (int i = 1; i <= n; i++) { if (i != v) { printf( %d %d n , v, i); } } int s = (v == 1 ? 2 : 1); m -= (n - 1); for (int i = 1; i <= n; i++) { if (i != s && i != v) { for (int j = i + 1; j <= n; j++) { if (j != s && j != v) { if (!m--) { return 0; } printf( %d %d n , i, j); } } } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e9 + 7; const long long INF = 1LL << 60; template <class T> inline bool chmax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } template <class T> inline bool chmin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } struct UnionFind { vector<long long> par, w; UnionFind(long long n) : par(n, -1), w(n, 0) {} void init(long long n) { par.assign(n, -1); w.assign(n, 0); } long long root(long long x) { if (par[x] < 0) return x; else return par[x] = root(par[x]); } bool issame(long long x, long long y) { return root(x) == root(y); } bool merge(long long x, long long y) { x = root(x); y = root(y); if (x == y) { ++w[x]; return false; } if (par[x] > par[y]) swap(x, y); par[x] += par[y]; par[y] = x; w[x] += w[y]; ++w[x]; return true; } long long size(long long x) { return -par[root(x)]; } long long wei(long long x) { return w[root(x)]; } }; void solve() { long long n, m, q; cin >> n >> m >> q; UnionFind uf(n + m); long long cnt = n + m; for (long long i = 0; i < q; ++i) { long long r, c; cin >> r >> c; --r, --c; if (!uf.issame(r, c + n)) { uf.merge(r, c + n); --cnt; } } cout << cnt - 1 << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; using Long = long long; constexpr Long MOD = 998244353; template <typename T> using V = vector<T>; template <typename T> using Vv = V<V<T>>; using Vb = V<bool>; using Vvb = V<Vb>; using Vi = V<int>; using Vvi = V<Vi>; using Vl = V<Long>; using Vvl = V<Vl>; using Vd = V<double>; using Vvd = V<Vd>; using Vs = V<string>; template <typename First, typename Second> istream& operator>>(istream& is, pair<First, Second>& v); template <typename T> istream& operator>>(istream& is, vector<T>& v) { for (auto& x : v) { is >> x; } return is; } template <typename First, typename Second> istream& operator>>(istream& is, pair<First, Second>& v) { is >> v.first >> v.second; return is; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { for (const auto& x : v) { os << x << ; } return os; } void solve() { Vvi divisors(100001); for (int d = 1; d <= 100000; ++d) { for (int k = 1; d * k <= 100000; ++k) { divisors[d * k].push_back(d); } } int bitcount[] = {0, 1, 1, 2, 1, 2, 2, 3}; int t; cin >> t; for (int i = 0; i < t; ++i) { int num[3]; Vi* d[3]; int n[3]; for (int j = 0; j < 3; ++j) { cin >> num[j]; d[j] = &divisors[num[j]]; n[j] = d[j]->size(); } int p[3] = {}; int counts[1 << 3] = {}; while (p[0] < n[0] || p[1] < n[1] || p[2] < n[2]) { int v[3]; for (int j = 0; j < 3; ++j) { v[j] = p[j] < n[j] ? (*d[j])[p[j]] : 100001; } int m = min({v[0], v[1], v[2]}); int set = 0; for (int j = 0; j < 3; ++j) { if (v[j] == m) { set |= 1 << j; p[j]++; } } counts[set]++; } Long ans = 0; for (int x = 1; x < (1 << 3); ++x) { for (int y = x; y < (1 << 3); ++y) { for (int z = y; z < (1 << 3); ++z) { if ((x | y | z) == (1 << 3) - 1) { Long r = 0; if (x != y && y != z && x != z) { ans += (Long)counts[x] * counts[y] * counts[z]; } else if (x == y && y == z) { int c = counts[x]; r = c * (c + 1LL) * (c + 2LL) / (2 * 3); } else if (x == y) { if (bitcount[x] > 1) { int c = counts[x]; r = (c * (c + 1LL) / 2) * counts[z]; } } else if (x == z) { if (bitcount[x] > 1) { int c = counts[x]; r = (c * (c + 1LL) / 2) * counts[y]; } } else if (y == z) { if (bitcount[y] > 1) { int c = counts[y]; r = (c * (c + 1LL) / 2) * counts[x]; } } else { throw exception{}; } ans += r; } } } } cout << ans << n ; } } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cout.precision(10); cout << fixed; solve(); return 0; }
|
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
INPUTS:
None
OUTPUTS:
The same signal echoed to all other GPIOs
TEST PROCEDURE:
Apply 3.3V power to pin 1 (core / bank 1 power)
Apply 1.8V power to pin 14 (bank 2 power)
Program the device
Read pin 10.
If not 3.3V, device is missing or faulty.
Read pin 20.
If 3.3V, device is a SLG46620.
If 1.8V, device is a SLG46621.
If anything else, device is missing or faulty.
*/
module PowerRailDetector_STQFN20(dout_bank1, dout_bank2);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P10" *)
output wire dout_bank1 = 1;
(* LOC = "P20" *)
output wire dout_bank2 = 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e3 + 7; long long read() { long long res = 0, f = 1; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1, c = getchar(); while (isdigit(c)) res = (res << 1) + (res << 3) + c - 48, c = getchar(); return res * f; } long long ans; int n, m; long long f[maxn][maxn], g[maxn][maxn]; int main() { n = read(), m = read(); for (int i = 2; i <= m; i++) f[1][i] = 1; for (int i = 2; i <= n; i++) for (int j = 2; j <= m; j++) f[i][j] = (f[i - 1][j] + 2 * f[i][j - 1] - f[i][j - 2] + 1000000007) % 1000000007; for (int i = 1; i <= n; i++) for (int j = 2; j <= m; j++) g[i][j] = (g[i - 1][j] + f[i][j]) % 1000000007; for (int i = 1; i <= n; i++) for (int j = 2; j <= m; j++) (ans += f[i][j] * g[n - i + 1][j] % 1000000007 * (m - j + 1) % 1000000007) %= 1000000007; printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> void max_self(T &a, const T &b) { if (a < b) a = b; } template <class T> void min_self(T &a, const T &b) { if (a > b) a = b; } const int INF = 1e9 + 7; const double PI = acos(-1.0); const double EPS = (1e-9); int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int N, d; long long cnt = 0; cin >> N >> d; vector<int> pos(N); for (int &ele : pos) cin >> ele; for (auto itr = pos.begin(); itr != pos.end(); ++itr) { auto lim = upper_bound((pos).begin(), (pos).end(), *itr + d); int len = distance(itr, lim) - 1; cnt += (long long)len * (len - 1) / 2; } cout << cnt << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; int n, m; int a[MAXN]; int w[MAXN], h[MAXN]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &w[i], &h[i]); } long long lasth = 0; for (int i = 1; i <= m; i++) { long long int x = lasth + 1; if (a[w[i]] > x) x = a[w[i]]; printf( %I64d n , x); lasth = x + h[i] - 1; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b; cin >> a >> b; long long count = 0; while (a != b) { if (a == 0 || b == 0) break; if (a < b) { count += b / a; b = b % a; } else { count += a / b; a = a % b; } } if (a > 0 && a == b) count++; cout << count << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
// See also t_class_param.v
module t (/*AUTOARG*/);
class Cls #(parameter PBASE = 12);
bit [PBASE-1:0] member;
function bit [PBASE-1:0] get_member;
return member;
endfunction
static function int get_p;
return PBASE;
endfunction
typedef enum { E_PBASE = PBASE } enum_t;
endclass
class Wrap #(parameter P = 13);
function int get_p;
return c1.get_p();
endfunction
function new;
c1 = new;
endfunction
Cls#(PMINUS1 + 1) c1;
localparam PMINUS1 = P - 1; // Checking works when last
endclass
typedef Cls#(8) Cls8_t;
Cls c12;
Cls #(.PBASE(4)) c4;
Cls8_t c8;
Wrap #(.P(16)) w16;
initial begin
c12 = new;
c4 = new;
c8 = new;
w16 = new;
if (Cls#()::PBASE != 12) $stop;
if (Cls#(4)::PBASE != 4) $stop;
if (Cls8_t::PBASE != 8) $stop;
if (Cls#()::E_PBASE != 12) $stop;
if (Cls#(4)::E_PBASE != 4) $stop;
if (Cls8_t::E_PBASE != 8) $stop;
if (c12.PBASE != 12) $stop;
if (c4.PBASE != 4) $stop;
if (c8.PBASE != 8) $stop;
if (Cls#()::get_p() != 12) $stop;
if (Cls#(4)::get_p() != 4) $stop;
if (Cls8_t::get_p() != 8) $stop;
if (c12.get_p() != 12) $stop;
if (c4.get_p() != 4) $stop;
if (c8.get_p() != 8) $stop;
if (w16.get_p() != 16) $stop;
// verilator lint_off WIDTH
c12.member = 32'haaaaaaaa;
c4.member = 32'haaaaaaaa;
c8.member = 32'haaaaaaaa;
// verilator lint_on WIDTH
if (c12.member != 12'haaa) $stop;
if (c4.member != 4'ha) $stop;
if (c12.get_member() != 12'haaa) $stop;
if (c4.get_member() != 4'ha) $stop;
`checks($sformatf("%p", c12), "'{member:'haaa}");
`checks($sformatf("%p", c4), "'{member:'ha}");
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// This file ONLY is placed into the Public Domain, for any use,
// Author: Yu-Sheng Lin
module t (/*AUTOARG*/
// Outputs
state,
// Inputs
clk
);
input clk;
int cyc;
reg rstn;
output [4:0] state;
parameter real fst_gparam_real = 1.23;
localparam real fst_lparam_real = 4.56;
real fst_real = 1.23;
integer fst_integer;
bit fst_bit;
logic fst_logic;
int fst_int;
shortint fst_shortint;
longint fst_longint;
byte fst_byte;
parameter fst_parameter = 123;
localparam fst_lparam = 456;
supply0 fst_supply0;
supply1 fst_supply1;
tri0 fst_tri0;
tri1 fst_tri1;
tri fst_tri;
wire fst_wire;
Test test (/*AUTOINST*/
// Outputs
.state (state[4:0]),
// Inputs
.clk (clk),
.rstn (rstn));
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
rstn <= ~'1;
end
else if (cyc<10) begin
rstn <= ~'1;
end
else if (cyc<90) begin
rstn <= ~'0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input clk,
input rstn,
output logic [4:0] state
);
logic [4:0] state_w;
logic [4:0] state_array [3];
assign state = state_array[0];
always_comb begin
state_w[4] = state_array[2][0];
state_w[3] = state_array[2][4];
state_w[2] = state_array[2][3] ^ state_array[2][0];
state_w[1] = state_array[2][2];
state_w[0] = state_array[2][1];
end
always_ff @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 3; i++)
state_array[i] <= 'b1;
end
else begin
for (int i = 0; i < 2; i++)
state_array[i] <= state_array[i+1];
state_array[2] <= state_w;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, numone, numtwo, sum, tmp; char nlong; string nameone, nametwo; string read; struct node { string name; int goal, moregoal, score; int q; } wxy[100]; bool check(int t) { for (int i = 0; i < tmp; i++) if (wxy[t].name[i] != nameone[i]) return false; return true; } bool checktwo(int t) { for (int i = tmp + 1; i < sum; i++) if (wxy[t].name[i - tmp - 1] != nametwo[i - tmp - 1]) return false; return true; } bool cmpfirst(node a, node b) { if (a.score > b.score) return 1; if (a.score < b.score) return 0; if (a.moregoal > b.moregoal) return 1; if (a.moregoal < b.moregoal) return 0; if (a.goal > b.goal) return 1; return 0; } bool cmplast(node a, node b) { return a.name < b.name; } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> wxy[i].name; wxy[i].q = wxy[i].name.size(); } for (int j = 1; j <= n * (n - 1) / 2; j++) { sum = 0; tmp = 0; nameone = , nametwo = ; numone = numtwo = 0; while (1) { scanf( %c , &nlong); if (nlong == - ) break; else if ((nlong >= a && nlong <= z ) || (nlong >= A && nlong <= Z )) { nameone += nlong; sum++; } } tmp = sum; sum++; while (1) { scanf( %c , &nlong); if (nlong == ) break; else { nametwo += nlong; sum++; } } while (1) { scanf( %c , &nlong); if (nlong == : ) break; else if (nlong >= 0 && nlong <= 9 ) numone = numone * 10 + nlong - 0 ; } cin >> numtwo; int one, two; for (int i = 1; i <= n; i++) if (wxy[i].q == tmp) if (check(i)) { one = i; break; } for (int i = 1; i <= n; i++) if (wxy[i].q + tmp + 1 == sum) if (checktwo(i)) { two = i; break; } wxy[one].goal += numone; wxy[two].goal += numtwo; wxy[one].moregoal += numone - numtwo; wxy[two].moregoal += numtwo - numone; if (numone > numtwo) wxy[one].score += 3; else if (numtwo > numone) wxy[two].score += 3; else { wxy[one].score++; wxy[two].score++; } } sort(wxy + 1, wxy + n + 1, cmpfirst); sort(wxy + 1, wxy + (n) / 2 + 1, cmplast); for (int i = 1; i <= n / 2; i++) cout << wxy[i].name << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int bit[200050]; int n; int lowbit(int x) { return x & (-x); } int sum(int x) { int sum = 0; while (x > 0) { sum += bit[x]; x -= lowbit(x); } return sum; } void push(int pos, int num) { while (pos <= n) { bit[pos] += num; pos += lowbit(pos); } } int kth(int k) { int num = 0; int x = 0; for (int i = 1 << 18; i > 0; i >>= 1) { num += i; if (num >= n || x + bit[num] >= k) num -= i; else x += bit[num]; } return num + 1; } int main() { scanf( %d , &n); int a[200050]; int x; memset((bit), (0), sizeof((bit))); for (int i = 0; i < n; i++) { scanf( %d , &x); push(x + 1, 1); a[i] = x - sum(x); } memset((bit), (0), sizeof((bit))); for (int i = 0; i < n; i++) { scanf( %d , &x); push(x + 1, 1); a[i] += x - sum(x); } for (int i = n - 1; i > 0; i--) { if (a[i] >= n - i) { a[i - 1]++; a[i] -= n - i; } } if (a[0] >= n) a[0] -= n; for (int i = 0; i < n; i++) { int num = kth(a[i] + 1); printf( %d , num - 1); push(num, -1); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NOR4_PP_SYMBOL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_PP_SYMBOL_V
|
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Generated by Quartus II Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
// Created on Sun May 22 00:06:14 2016
// synthesis message_off 10175
`timescale 1ns/1ns
module key_logic_fsm (
clock,reset,k[3:0],lcd_busy,reg_busy,
run_timer,reset_timer,insert_value,clear_value);
input clock;
input reset;
input [3:0] k;
input lcd_busy;
input reg_busy;
tri0 reset;
tri0 [3:0] k;
tri0 lcd_busy;
tri0 reg_busy;
output run_timer;
output reset_timer;
output insert_value;
output clear_value;
reg run_timer;
reg reset_timer;
reg insert_value;
reg clear_value;
reg [10:0] fstate;
reg [10:0] reg_fstate;
parameter s_pre_start=0,s_run=1,s_pre_pause=2,s_pause=3,s_idle=4,s_pre_reset=5,s_reset=6,s_retrieve=7,s_save=8,s_pre_clear=9,s_clear=10;
always @(posedge clock)
begin
if (clock) begin
fstate <= reg_fstate;
end
end
always @(fstate or reset or k or lcd_busy or reg_busy)
begin
if (reset) begin
reg_fstate <= s_idle;
run_timer <= 1'b0;
reset_timer <= 1'b0;
insert_value <= 1'b0;
clear_value <= 1'b0;
end
else begin
run_timer <= 1'b0;
reset_timer <= 1'b0;
insert_value <= 1'b0;
clear_value <= 1'b0;
case (fstate)
s_pre_start: begin
if ((k[3:0] != 4'b0000))
reg_fstate <= s_pre_start;
else if ((k[3:0] == 4'b0000))
reg_fstate <= s_run;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_pre_start;
run_timer <= 1'b1;
end
s_run: begin
if ((k[3:0] == 4'b0000))
reg_fstate <= s_run;
else if ((k[3:0] == 4'b1000))
reg_fstate <= s_pre_pause;
else if ((k[3:0] == 4'b0100))
reg_fstate <= s_retrieve;
else if ((k[3:0] == 4'b0010))
reg_fstate <= s_pre_reset;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_run;
run_timer <= 1'b1;
end
s_pre_pause: begin
if ((k[3:0] != 4'b0000))
reg_fstate <= s_pre_pause;
else if ((k[3:0] == 4'b0000))
reg_fstate <= s_pause;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_pre_pause;
end
s_pause: begin
if ((k[3:0] == 4'b0000))
reg_fstate <= s_pause;
else if ((k[3:0] == 4'b1000))
reg_fstate <= s_pre_start;
else if ((k[3:0] == 4'b0010))
reg_fstate <= s_pre_reset;
else if ((k[3:0] == 4'b0001))
reg_fstate <= s_pre_clear;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_pause;
end
s_idle: begin
if ((k[3:0] == 4'b0000))
reg_fstate <= s_idle;
else if ((k[3:0] == 4'b1000))
reg_fstate <= s_pre_start;
else if ((k[3:0] == 4'b0010))
reg_fstate <= s_pre_reset;
else if ((k[3:0] == 4'b0001))
reg_fstate <= s_pre_clear;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_idle;
end
s_pre_reset: begin
if ((k[3:0] != 4'b0000))
reg_fstate <= s_pre_reset;
else if ((k[3:0] == 4'b0000))
reg_fstate <= s_reset;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_pre_reset;
end
s_reset: begin
if (reg_busy)
reg_fstate <= s_reset;
else if (~(reg_busy))
reg_fstate <= s_idle;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_reset;
reset_timer <= 1'b1;
end
s_retrieve: begin
reg_fstate <= s_save;
insert_value <= 1'b1;
end
s_save: begin
if ((lcd_busy | (k[3:0] != 4'b0000)))
reg_fstate <= s_save;
else if ((~(lcd_busy) & (k[3:0] == 4'b0000)))
reg_fstate <= s_run;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_save;
run_timer <= 1'b1;
end
s_pre_clear: begin
if ((k[3:0] != 4'b0000))
reg_fstate <= s_pre_clear;
else if ((k[3:0] == 4'b0000))
reg_fstate <= s_clear;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_pre_clear;
end
s_clear: begin
if (lcd_busy)
reg_fstate <= s_clear;
else if (~(lcd_busy))
reg_fstate <= s_pause;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_clear;
clear_value <= 1'b1;
end
default: begin
run_timer <= 1'bx;
reset_timer <= 1'bx;
insert_value <= 1'bx;
clear_value <= 1'bx;
$display ("Reach undefined state");
end
endcase
end
end
endmodule // key_logic_fsm
|
#include <bits/stdc++.h> using namespace std; const long long mx = 10000007; using pii = pair<long long, long long>; const long long mod = 1e9 + 7; const double pi = acos(-1); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long t; cin >> t; while (t--) { long long n; cin >> n; vector<pii> v; vector<long long> ev, od; set<long long> s; for (long long i = 0; i < n; i++) { s.insert(i + 1); if ((i + 1) % 2 == 0) ev.push_back(i + 1); else od.push_back(i + 1); } if (n == 2) { cout << 2 << endl; cout << 1 << << 2 << endl; continue; } sort(ev.begin(), ev.end()); sort(od.begin(), od.end()); reverse(ev.begin(), ev.end()); reverse(od.begin(), od.end()); long long d; if (n % 2 == 0) { d = ev[0]; s.erase(d); long long i = 1, j = 0; while (1) { if (d % 2 == 0) { long long a = d; long long b = ev[i]; s.erase(b); v.push_back({a, b}); d = (a + b) / 2; if (s.size() == 0) break; i++; if (i > ev.size()) break; } else { long long a = d; long long b = od[j]; s.erase(b); v.push_back({a, b}); j++; d = (a + b) / 2; if (s.size() == 0) break; if (j > od.size()) break; } if (s.size() == 0) break; } } else if (n % 2 == 1) { d = od[0]; s.erase(d); long long i = 1, j = 0; while (1) { if (d % 2 == 1) { long long a = d; long long b = od[i]; s.erase(b); v.push_back({a, b}); d = (a + b) / 2; if (s.size() == 0) break; i++; if (i > od.size()) break; } else { long long a = d; long long b = ev[j]; s.erase(b); v.push_back({a, b}); j++; d = (a + b) / 2; if (s.size() == 0) break; if (j > ev.size()) break; } if (s.size() == 0) break; } } cout << d << endl; for (long long i = 0; i < v.size(); i++) { cout << v[i].first << << v[i].second << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; pair<int, int> p[n]; for (int i = 0; i < n; i++) { cin >> p[i].first >> p[i].second; } bool check = true; for (int i = 0; i < n; i++) { if (p[i].first < p[i].second) check = false; if (i > 0) { if (p[i].first == p[i - 1].first) { if (p[i].second != p[i - 1].second) check = false; } else if (p[i].first > p[i - 1].first) { if (p[i].second < p[i - 1].second) check = false; } else check = false; if (p[i].first - p[i - 1].first < p[i].second - p[i - 1].second) check = false; } } if (check) cout << YES n ; else cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> vec(n); for (int i = 0; i < n; i++) { cin >> vec[i]; } if (n == 1) { if (vec[0] == 15) cout << DOWN << endl; else if (vec[0] == 0) cout << UP << endl; else cout << -1 << endl; } else { if (vec[n - 1] == 0 || (vec[n - 1] > vec[n - 2] && vec[n - 1] != 15)) cout << UP << endl; else cout << DOWN << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, a[1000], d; cin >> t; while (t--) { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); d = 0; for (int i = 1; i < n; i++) { if (a[i] - a[i - 1] <= 1) { d++; } } if (d) cout << 2 << endl; else cout << 1 << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVPWRVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__TAPVPWRVGND_PP_BLACKBOX_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapvpwrvgnd (
VPWR,
VGND
);
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVPWRVGND_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211OI_1_V
`define SKY130_FD_SC_HDLL__A211OI_1_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a211oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a211oi_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211OI_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int l, b, M, N; cin >> M; cin >> N; l = std::max(M, N); b = std::min(M, N); if (b >= 2) { cout << (b * (l / 2) + (b / 2) * (l % 2)); } else cout << (b * (l / 2)); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200005; set<int> ab[MAXN][2]; int N, M, Q; struct segTree { int f, t, mini, maxi; bool ans; segTree *L, *R; segTree(int _f, int _t) : f(_f), t(_t) { ans = false; mini = INT_MAX; maxi = INT_MIN; if (f != t) { L = new segTree(f, (f + t) / 2); R = new segTree((f + t) / 2 + 1, t); } } void update(int x, int v, bool flag) { if (f == t && t == x) { if (flag) maxi = v; else mini = v; ans = maxi >= mini; return; } if (x < R->f) L->update(x, v, flag); else R->update(x, v, flag); mini = min(R->mini, L->mini); maxi = max(R->maxi, L->maxi); ans = R->ans | L->ans | (R->maxi >= L->mini); } }; int main() { scanf( %d %d %d , &N, &M, &Q); segTree *tree = new segTree(0, N + 1); for (int i = 0; i < Q; i++) { int x, y; scanf( %d %d , &x, &y); x--, y--; bool flag = (x & 1); int mult = (flag ? -1 : 1); if (ab[x / 2][flag].count((y / 2) * mult)) ab[x / 2][flag].erase((y / 2) * mult); else ab[x / 2][flag].insert((y / 2) * mult); int val = INT_MAX; if (flag) val = INT_MIN; if (ab[x / 2][flag].size() > 0) val = abs(*ab[x / 2][flag].begin()); tree->update(x / 2, val, flag); puts((!tree->ans ? YES : NO )); } return 0; }
|
#include <bits/stdc++.h> using namespace std; string A; bool isPalindrome(int left, int right) { while (left < right) { if (A[left] != A[right]) return false; left++, right--; } return true; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); cin >> A; int N = A.size(); int bonus = 0; int ret = 0; if (N % 2 == 1) bonus = 1; N /= 2; while (N > 0) { if (isPalindrome(0, N - 1)) { if (N % 2 == 1) { N--; bonus = 1; } else N /= 2; } else { ret = 1 + bonus; break; } } if (ret == 0) cout << Impossible ; else cout << ret; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, k; int arr[51][51] = {0}, visit[51][51] = {0}; vector<pair<int, pair<int, int> > > v; int dfs(int a, int b, int count); void make_land(int i, int j); int main() { int i, j, sum = 0; char ch; cin >> n >> m >> k; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cin >> ch; if (ch == * ) arr[i][j]++; } } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (!visit[i][j] && !arr[i][j]) { int value = dfs(i, j, 0); if (value != -1) v.push_back(make_pair(value, make_pair(i, j))); } } } sort(v.begin(), v.end()); int check = v.size(); vector<pair<int, pair<int, int> > >::iterator it = v.begin(); for (i = 0; i < v.size() - k; i++) { sum += it->first; int a = (it->second).first; int b = (it->second).second; make_land(a, b); it++; } cout << sum << endl; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (arr[i][j] == 1) cout << * ; else cout << . ; } cout << endl; } } int dfs(int i, int j, int count) { visit[i][j] = 1; if (count != -1) count++; if (i == n - 1 || j == m - 1 || i == 0 || j == 0) count = -1; if (i <= n - 1 && j - 1 >= 0 && !visit[i][j - 1] && !arr[i][j - 1]) count = dfs(i, j - 1, count); if (i - 1 >= 0 && j <= m - 1 && !visit[i - 1][j] && !arr[i - 1][j]) count = dfs(i - 1, j, count); if (i <= n - 1 && j + 1 <= m - 1 && !visit[i][j + 1] && !arr[i][j + 1]) count = dfs(i, j + 1, count); if (i + 1 <= n - 1 && j <= m - 1 && !visit[i + 1][j] && !arr[i + 1][j]) count = dfs(i + 1, j, count); return count; } void make_land(int i, int j) { arr[i][j] = 1; if (i <= n - 1 && j - 1 >= 0 && !arr[i][j - 1]) { make_land(i, j - 1); } if (i - 1 >= 0 && j <= m - 1 && !arr[i - 1][j]) { make_land(i - 1, j); } if (i <= n - 1 && j + 1 <= m - 1 && !arr[i][j + 1]) { make_land(i, j + 1); } if (i + 1 <= n - 1 && j <= m - 1 && !arr[i + 1][j]) { make_land(i + 1, j); } }
|
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