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#include <bits/stdc++.h> struct count_seg { struct node { std::array<int, 2> c; bool flip = false; }; std::vector<node> seg; count_seg() : seg() {} explicit count_seg(int N) : seg(2 * N) {} std::array<int, 2> query_all() { return seg[1].c; } void update_node(int a) { int N = int(seg.size()) >> 1; if (a >= N) { seg[a].c[0] = 0, seg[a].c[1] = 1; } else { seg[a].c[0] = seg[2 * a].c[0] + seg[2 * a + 1].c[0]; seg[a].c[1] = seg[2 * a].c[1] + seg[2 * a + 1].c[1]; } if (seg[a].flip) std::swap(seg[a].c[0], seg[a].c[1]); } void flip_node(int a) { seg[a].flip ^= 1; std::swap(seg[a].c[0], seg[a].c[1]); } void flip_leaf_lazy(int l) { int N = int(seg.size()) >> 1; seg[N + l].flip ^= 1; } void flip_range(int l, int r) { int N = int(seg.size()) >> 1; for (int a = l + N, b = r + N; a < b; a >>= 1, b >>= 1) { if (a & 1) flip_node(a++); if (b & 1) flip_node(--b); } for (int a = l + N; a; a >>= 1) update_node(a); for (int b = r + N - 1; b; b >>= 1) update_node(b); } void update_all() { for (int i = int(seg.size()) - 1; i; --i) update_node(i); } }; struct big_seg { struct mat { std::array<std::array<std::array<int, 2>, 2>, 2> v; friend mat operator*(const mat& a, const mat& b) { mat res; for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { for (int z = 0; z < 2; z++) { res.v[i][j][z] = std::min(a.v[i][j][0] + b.v[i][j][z], a.v[i][j][1] + b.v[!i][!j][!z]); } } } return res; } int eval(std::array<int, 2> st, std::array<int, 2> en) const { int res = st[0] + v[0][0][0] + en[0]; for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { res = std::min(res, st[i] + v[i][i][i ^ j] + en[j]); } } return res; } }; struct node { mat m; std::array<bool, 2> flip = {false, false}; }; int N, M; std::vector<node> seg; big_seg() : N(0), seg() {} big_seg(int N_, int M_) : N(N_), M(M_), seg() { int S = 1; while (S < N) S *= 2; seg.resize(2 * S); } mat query_all() { return seg[1].m; } void update_node(int a) { int S = int(seg.size()) >> 1; if (a >= S) { if (a - S < N) { for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { seg[a].m.v[i][j][0] = i + j; seg[a].m.v[i][j][1] = i + j + M; } } } else { for (int i = 0; i < 2; i++) { for (int j = 0; j < 2; j++) { seg[a].m.v[i][j][0] = 0; seg[a].m.v[i][j][1] = 0 + M; } } } } else { seg[a].m = seg[2 * a].m * seg[2 * a + 1].m; } if (seg[a].flip[0]) { swap(seg[a].m.v[0], seg[a].m.v[1]); } if (seg[a].flip[1]) { swap(seg[a].m.v[0][0], seg[a].m.v[0][1]); swap(seg[a].m.v[1][0], seg[a].m.v[1][1]); } } void flip_node(int a, bool z) { seg[a].flip[z] ^= 1; if (z == 0) { swap(seg[a].m.v[0], seg[a].m.v[1]); } else if (z == 1) { swap(seg[a].m.v[0][0], seg[a].m.v[0][1]); swap(seg[a].m.v[1][0], seg[a].m.v[1][1]); } else assert(false); } void flip_leaf_lazy(int l, bool z) { int S = int(seg.size()) >> 1; seg[S + l].flip[z] ^= 1; } void flip_range(int l, int r, bool z) { int S = int(seg.size()) >> 1; for (int a = l + S, b = r + S; a < b; a >>= 1, b >>= 1) { if (a & 1) flip_node(a++, z); if (b & 1) flip_node(--b, z); } for (int a = l + S; a; a >>= 1) update_node(a); for (int b = r + S - 1; b; b >>= 1) update_node(b); } void update_all() { for (int i = int(seg.size()) - 1; i; --i) update_node(i); } }; int main() { using namespace std; ios_base::sync_with_stdio(false), cin.tie(nullptr); array<int, 2> N; int Q; cin >> N[0] >> N[1] >> Q; array<array<count_seg, 2>, 2> count_segs; array<big_seg, 2> big_segs; for (int a = 0; a < 2; a++) { big_segs[a] = big_seg(N[a], N[!a]); for (int b = 0; b < 2; b++) { count_segs[a][b] = count_seg(N[a]); string S; cin >> S; assert(int(S.size()) == N[a]); for (int i = 0; i < N[a]; i++) { if (S[i] == R ) { count_segs[a][b].flip_leaf_lazy(i); big_segs[a].flip_leaf_lazy(i, b); } } count_segs[a][b].update_all(); } big_segs[a].update_all(); } auto query = [&]() -> int { int ans = 2 * N[0] + 2 * N[1]; for (int z = 0; z < 2; z++) { int cnd = big_segs[!z].query_all().eval(count_segs[z][0].query_all(), count_segs[z][1].query_all()); ans = min(ans, cnd); } return ans; }; cout << query() << n ; for (int q = 0; q < Q; q++) { char side; int l, r; cin >> side >> l >> r; l--; bool dim, z; switch (side) { case L : dim = 0, z = 0; break; case R : dim = 0, z = 1; break; case U : dim = 1, z = 0; break; case D : dim = 1, z = 1; break; default: assert(false); } assert(0 <= l && l < r && r <= N[dim]); count_segs[dim][z].flip_range(l, r); big_segs[dim].flip_range(l, r, z); cout << query() << n ; } return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Alex Solomatnikov.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [6-1:0] foo[4-1:0];
//initial $display("%m: %p\n", foo);
//initial $display("%m: %p\n", foo[3:0]); // VCS not supported %p with slice
//logic [6-1:0] foo2[4-1:0][5:6];
//initial $display("%m: %p\n", foo2[3:0][5:6]); // This is not legal
dut #(.W(6),
.D(4)) udut(.clk(clk),
.foo(foo[4-1:0]));
endmodule
module dut
#(parameter W = 1,
parameter D = 1)
(input logic clk,
input logic [W-1:0] foo[D-1:0]);
genvar i, j;
generate
for (j = 0; j < D; j++) begin
for (i = 0; i < W; i++) begin
suba ua(.clk(clk), .foo(foo[j][i]));
end
end
endgenerate
endmodule
module suba
(input logic clk,
input logic foo);
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, d = 1; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m; while (n > d) { for (int i = 1; i < (m + 1); i++) { cout << d << << i << n ; cout << n << << m + 1 - i << n ; } n--; d++; } if (n == d) { for (int i = 0; i < (m / 2); i++) { cout << d << << 1 + i << n ; cout << d << << m - i << n ; } if (m & 1) cout << d << << (m + 1) / 2 << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int oo = 2e9; const int N = 1e6; int n; string s, x = BGR ; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> n >> s; int k = oo; string ans; do { int cnt = 0; string t = s; for (int i = 0; i < n; i++) if (t[i] != x[i % 3]) { cnt++; t[i] = x[i % 3]; } if (cnt < k) { k = cnt; ans = t; } } while (next_permutation(x.begin(), x.end())); cout << k << n << ans; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); unsigned long long int n, ans, i, j, k; cin >> n; if (n == 0) { cout << 1 << endl; return 0; } ans = 2 * n * n; ans = ans + ((n + 2) * (n + 1)) - 1; cout << ans << endl; return 0; }
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Register Interface Unit Selection Block
// /___/ /\ Filename : RIU_OR.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RIU_OR #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter real SIM_VERSION = 2.0
)(
output [15:0] RIU_RD_DATA,
output RIU_RD_VALID,
input [15:0] RIU_RD_DATA_LOW,
input [15:0] RIU_RD_DATA_UPP,
input RIU_RD_VALID_LOW,
input RIU_RD_VALID_UPP
);
// define constants
localparam MODULE_NAME = "RIU_OR";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
localparam real SIM_VERSION_REG = SIM_VERSION;
wire [63:0] SIM_VERSION_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
wire RIU_RD_VALID_out;
wire [15:0] RIU_RD_DATA_out;
wire RIU_RD_VALID_delay;
wire [15:0] RIU_RD_DATA_delay;
wire RIU_RD_VALID_LOW_in;
wire RIU_RD_VALID_UPP_in;
wire [15:0] RIU_RD_DATA_LOW_in;
wire [15:0] RIU_RD_DATA_UPP_in;
wire RIU_RD_VALID_LOW_delay;
wire RIU_RD_VALID_UPP_delay;
wire [15:0] RIU_RD_DATA_LOW_delay;
wire [15:0] RIU_RD_DATA_UPP_delay;
assign #(out_delay) RIU_RD_DATA = RIU_RD_DATA_delay;
assign #(out_delay) RIU_RD_VALID = RIU_RD_VALID_delay;
// inputs with no timing checks
assign #(in_delay) RIU_RD_DATA_LOW_delay = RIU_RD_DATA_LOW;
assign #(in_delay) RIU_RD_DATA_UPP_delay = RIU_RD_DATA_UPP;
assign #(in_delay) RIU_RD_VALID_LOW_delay = RIU_RD_VALID_LOW;
assign #(in_delay) RIU_RD_VALID_UPP_delay = RIU_RD_VALID_UPP;
assign RIU_RD_DATA_delay = RIU_RD_DATA_out;
assign RIU_RD_VALID_delay = RIU_RD_VALID_out;
assign RIU_RD_DATA_LOW_in = RIU_RD_DATA_LOW_delay;
assign RIU_RD_DATA_UPP_in = RIU_RD_DATA_UPP_delay;
assign RIU_RD_VALID_LOW_in = RIU_RD_VALID_LOW_delay;
assign RIU_RD_VALID_UPP_in = RIU_RD_VALID_UPP_delay;
assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000;
assign RIU_RD_DATA_out = RIU_RD_DATA_UPP_in | RIU_RD_DATA_LOW_in;
assign RIU_RD_VALID_out = RIU_RD_VALID_UPP_in & RIU_RD_VALID_LOW_in;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_VERSION_REG != 2.0) &&
(SIM_VERSION_REG != 1.0))) begin
$display("Error: [Unisim %s-101] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
specify
(RIU_RD_DATA_LOW *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RIU_RD_DATA_UPP *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RIU_RD_VALID_LOW => RIU_RD_VALID) = (0:0:0, 0:0:0);
(RIU_RD_VALID_UPP => RIU_RD_VALID) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//-------------------------------------------------------------------
//
// Filename : hevc_md_top.v
// Created On : 2014-04-23
// Version1.0 : 2014-05-04
// Version2.0 : 2015-03-09
// Author : Yanheng Lu
// Description : pre_intra(pre mode desision) top module
// V1.0 basic
// V2.0 for encoder
//
//-------------------------------------------------------------------
module hevc_md_top(
clk,
rstn,
md_ren_o,
md_sel_o,
md_size_o,
md_4x4_x_o,
md_4x4_y_o,
md_idx_o,
md_data_i,
md_we,
md_waddr,
md_wdata,
enable,
finish
);
//global
input clk ;
input rstn ;
// original pixels data read
output md_ren_o ;
output md_sel_o ;
output [1:0] md_size_o ;
output [3:0] md_4x4_x_o ;
output [3:0] md_4x4_y_o ;
output [4:0] md_idx_o ;
input [255:0] md_data_i ;
// mode ram
output md_we;
output [5:0] md_wdata;
output [6:0] md_waddr;
// state
output finish;
input enable;
//===============wire declaration====================================================
wire finish;
reg enable_reg;
reg enable_r;
wire [3:0] sram_raddr;
wire sram_read;
wire [31:0] sram_rdata;
wire [3:0] sram_waddr;
wire sram_write;
wire [31:0] sram_wdata;
wire [5:0] cnt;//cycle count
wire [6:0] blockcnt;//8x8 block count
wire [5:0] bestmode; //best mode for 8x8
wire [5:0] bestmode16;//best mode for 16x16
wire [5:0] bestmode32;//best mode for 32x32
//===========================================================================================
always@(posedge clk or negedge rstn)
if(!rstn)
enable_reg <= 1'b0;
else if(finish)
enable_reg <= 1'b0;
else if(enable_r && cnt[3])
enable_reg <= 1'b1;
always@(posedge clk or negedge rstn)
if(!rstn)
enable_r <= 1'b0;
else if(finish)
enable_r <= 1'b0;
else if(enable)
enable_r <= 1'b1;
md_top md_top1(
.clk (clk),
.rstn (rstn),
.enable (enable_reg),
.sram_rdata (sram_rdata),
.sram_read (sram_read),
.sram_raddr (sram_raddr),
.bestmode_o (bestmode),
.bestmode16_o (bestmode16),
.bestmode32_o (bestmode32),
.finish (finish)
);// mode decision module
md_ram md_ram1(
.clk(clk),
.wdata(sram_wdata),
.waddr(sram_waddr),
.we(sram_write),
.rd(sram_read),
.raddr(sram_raddr[3:0]),
.rdata(sram_rdata)
);// original pixels data ram
fetch8x8 u_fetch8x8(
.clk (clk),
.rstn (rstn),
.cnt (cnt),
.blockcnt (blockcnt),
.finish (finish),
.enable (enable_r||enable),
.data (sram_wdata),
.addr (sram_waddr),
.md_ren_o (md_ren_o ),
.md_sel_o (md_sel_o ),
.md_size_o (md_size_o ),
.md_4x4_x_o (md_4x4_x_o ),
.md_4x4_y_o (md_4x4_y_o ),
.md_idx_o (md_idx_o ),
.md_data_i (md_data_i ),
.control (sram_write)
);//fetch 8x8 original pixels
mode_write u_mode_write(
.clk (clk),
.rstn (rstn),
.cnt (cnt),
.blockcnt (blockcnt),
.bestmode (bestmode),
.bestmode16 (bestmode16),
.bestmode32 (bestmode32),
.finish (finish),
.md_we (md_we),
.md_waddr (md_waddr),
.md_wdata (md_wdata)
);// mode write back to mode ram
//*************************************
//
// luyanheng
//
// mode dump
//
//*************************************
/*
integer f_mode;
initial begin
f_mode = $fopen("./mode.dat","w");
end
always @(posedge clk) begin
if(md_we) begin
$fwrite(f_mode, "%0h", md_wdata);
$fwrite(f_mode, "\n");
end
end
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; char str[100005]; int cnt[250]; int main() { scanf( %s , &str); int len = strlen(str); set<char> myset; for (int i = 0; i < len; i++) { myset.insert(str[i]); cnt[str[i]]++; } if (myset.size() == 1 || myset.size() > 4) { printf( NO ); return 0; } if (myset.size() == 4) { printf( YES ); return 0; } if (myset.size() == 3) { if (len == 3) { printf( NO ); return 0; } else { printf( YES ); return 0; } } if (myset.size() == 2) { for (int i = a ; i <= z ; i++) { if (cnt[i] == 1) { printf( NO ); return 0; } } printf( YES ); } }
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#include <bits/stdc++.h> using namespace std; void test() { int t; cin >> t; while (t--) { int i = 0; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int i = 0; int n; cin >> n; map<int, int> m; for (int i = 0; i < n; i++) { int x; cin >> x; m[x]++; } int g = 0; for (auto i : m) { if (i.first != 0) g++; } cout << g; return 0; }
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#include <bits/stdc++.h> using namespace std; string s1, s2; int main() { int n, i, j; scanf( %d , &n); cin >> s1 >> s2; int ans = 0; for (i = 0; i < (n / 2); i++) { j = n - i - 1; map<char, int> mp; mp[s1[i]]++; mp[s1[j]]++; mp[s2[i]]++; mp[s2[j]]++; int len = mp.size(); if (len == 4) ans += 2; else if (len == 3) ans += 1 + (s1[i] == s1[j]); else if (len == 2) ans += (mp[s1[i]] != 2); } if ((n % 2) && (s1[n / 2] != s2[n / 2])) ans++; printf( %d , ans); return 0; }
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//
// Copyright (C) 2009-2012 Chris McClelland
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module
comm_fpga_fx2(
// FX2 interface -----------------------------------------------------------------------------
input wire fx2Clk_in, // 48MHz clock from FX2
output reg fx2FifoSel_out, // select FIFO: '0' for EP6OUT, '1' for EP8IN
inout wire[7:0] fx2Data_io, // 8-bit data to/from FX2
// When EP6OUT selected:
output wire fx2Read_out, // asserted (active-low) when reading from FX2
input wire fx2GotData_in, // asserted (active-high) when FX2 has data for us
// When EP8IN selected:
output wire fx2Write_out, // asserted (active-low) when writing to FX2
input wire fx2GotRoom_in, // asserted (active-high) when FX2 has room for more data from us
output reg fx2PktEnd_out, // asserted (active-low) when a host read needs to be committed early
// Channel read/write interface --------------------------------------------------------------
output wire[6:0] chanAddr_out, // the selected channel (0-127)
// Host >> FPGA pipe:
output wire[7:0] h2fData_out, // data lines used when the host writes to a channel
output reg h2fValid_out, // '1' means "on the next clock rising edge, please accept the data on h2fData_out"
input wire h2fReady_in, // channel logic can drive this low to say "I'm not ready for more data yet"
// Host << FPGA pipe:
input wire[7:0] f2hData_in, // data lines used when the host reads from a channel
input wire f2hValid_in, // channel logic can drive this low to say "I don't have data ready for you"
output reg f2hReady_out // '1' means "on the next clock rising edge, put your next byte of data on f2hData_in"
);
// The read/write nomenclature here refers to the FPGA reading and writing the FX2 FIFOs, and is therefore
// of the opposite sense to the host's read and write. So host reads are fulfilled in the S_WRITE state, and
// vice-versa. Apologies for the confusion.
localparam[3:0] S_IDLE = 4'h0; // wait for requst from host & register chanAddr & isWrite
localparam[3:0] S_GET_COUNT0 = 4'h1; // register most significant byte of message length
localparam[3:0] S_GET_COUNT1 = 4'h2; // register next byte of message length
localparam[3:0] S_GET_COUNT2 = 4'h3; // register next byte of message length
localparam[3:0] S_GET_COUNT3 = 4'h4; // register least significant byte of message length
localparam[3:0] S_BEGIN_WRITE = 4'h5; // switch direction of FX2 data bus
localparam[3:0] S_WRITE = 4'h6; // write data to FX2 EP8IN FIFO, one byte at a time
localparam[3:0] S_END_WRITE_ALIGNED = 4'h7; // end an aligned write (do not assert fx2PktEnd_out)
localparam[3:0] S_END_WRITE_NONALIGNED = 4'h8; // end a nonaligned write (assert fx2PktEnd_out)
localparam[3:0] S_READ = 4'h9; // read data from FX2 EP6OUT FIFO, one byte at a time
localparam[1:0] FIFO_READ = 2'b10; // assert fx2Read_out (active-low)
localparam[1:0] FIFO_WRITE = 2'b01; // assert fx2Write_out (active-low)
localparam[1:0] FIFO_NOP = 2'b11; // assert nothing
localparam OUT_FIFO = 2'b0; // EP6OUT
localparam IN_FIFO = 2'b1; // EP8IN
reg[3:0] state_next, state = S_IDLE;
reg[1:0] fifoOp = FIFO_NOP;
reg[31:0] count_next, count = 32'h0; // read/write count
reg[6:0] chanAddr_next, chanAddr = 7'h00; // channel being accessed (0-127)
reg isWrite_next, isWrite = 1'b0; // is this access is an FX2 FIFO write or a read?
reg isAligned_next, isAligned = 1'b0; // is this FX2 FIFO write block-aligned?
reg[7:0] dataOut; // data to be driven on fx2Data_io
reg driveBus; // whether or not to drive fx2Data_io
// Infer registers
always @(posedge fx2Clk_in)
begin
state <= state_next;
count <= count_next;
chanAddr <= chanAddr_next;
isWrite <= isWrite_next;
isAligned <= isAligned_next;
end
// Next state logic
always @*
begin
state_next = state;
count_next = count;
chanAddr_next = chanAddr;
isWrite_next = isWrite; // is the FPGA writing to the FX2?
isAligned_next = isAligned; // does this FIFO write end on a block (512-byte) boundary?
dataOut = 8'h00;
driveBus = 1'b0; // don't drive fx2Data_io by default
fifoOp = FIFO_READ; // read the FX2 FIFO by default
fx2PktEnd_out = 1'b1; // inactive: FPGA does not commit a short packet.
f2hReady_out = 1'b0;
h2fValid_out = 1'b0;
case ( state )
S_GET_COUNT0:
begin
fx2FifoSel_out = OUT_FIFO; // Reading from FX2
if ( fx2GotData_in == 1'b1 )
begin
// The count high word high byte will be available on the next clock.
count_next[31:24] = fx2Data_io;
state_next = S_GET_COUNT1;
end
end
S_GET_COUNT1:
begin
fx2FifoSel_out = OUT_FIFO; // Reading from FX2
if ( fx2GotData_in == 1'b1 )
begin
// The count high word low byte will be available on the next clock.
count_next[23:16] = fx2Data_io;
state_next = S_GET_COUNT2;
end
end
S_GET_COUNT2:
begin
fx2FifoSel_out = OUT_FIFO; // Reading from FX2
if ( fx2GotData_in == 1'b1 )
begin
// The count low word high byte will be available on the next clock.
count_next[15:8] = fx2Data_io;
state_next = S_GET_COUNT3;
end
end
S_GET_COUNT3:
begin
fx2FifoSel_out = OUT_FIFO; // Reading from FX2
if ( fx2GotData_in == 1'b1 )
begin
// The count low word low byte will be available on the next clock.
count_next[7:0] = fx2Data_io;
if ( isWrite == 1'b1 )
state_next = S_BEGIN_WRITE;
else
state_next = S_READ;
end
end
S_BEGIN_WRITE:
begin
fx2FifoSel_out = IN_FIFO; // Writing to FX2
fifoOp = FIFO_NOP;
if ( count[8:0] == 9'b000000000 )
isAligned_next = 1'b1;
else
isAligned_next = 1'b0;
state_next = S_WRITE;
end
S_WRITE:
begin
fx2FifoSel_out = IN_FIFO; // Writing to FX2
if ( fx2GotRoom_in == 1'b1 )
f2hReady_out = 1'b1;
if ( fx2GotRoom_in == 1'b1 && f2hValid_in == 1'b1 )
begin
fifoOp = FIFO_WRITE;
dataOut = f2hData_in;
driveBus = 1'b1;
count_next = count - 1;
if ( count == 32'h1 )
begin
if ( isAligned == 1'b1 )
state_next = S_END_WRITE_ALIGNED; // don't assert fx2PktEnd
else
state_next = S_END_WRITE_NONALIGNED; // assert fx2PktEnd to commit small packet
end
end
else
fifoOp = FIFO_NOP;
end
S_END_WRITE_ALIGNED:
begin
fx2FifoSel_out = IN_FIFO; // Writing to FX2
fifoOp = FIFO_NOP;
state_next = S_IDLE;
end
S_END_WRITE_NONALIGNED:
begin
fx2FifoSel_out = IN_FIFO; // Writing to FX2
fifoOp = FIFO_NOP;
fx2PktEnd_out = 1'b0; // Active: FPGA commits the packet early.
state_next = S_IDLE;
end
S_READ:
begin
fx2FifoSel_out = OUT_FIFO; // Reading from FX2
if ( fx2GotData_in == 1'b1 && h2fReady_in == 1'b1 )
begin
// A data byte will be available on the next clock
h2fValid_out = 1'b1;
count_next = count - 1;
if ( count == 32'h1 )
state_next = S_IDLE;
end
else
fifoOp = FIFO_NOP;
end
// S_IDLE and others
default:
begin
fx2FifoSel_out = OUT_FIFO; // Reading from FX2
if ( fx2GotData_in == 1'b1 )
begin
// The read/write flag and a seven-bit channel address will be available on
// the next clock edge.
chanAddr_next = fx2Data_io[6:0];
isWrite_next = fx2Data_io[7];
state_next = S_GET_COUNT0;
end
end
endcase
end
// Drive stateless signals
assign fx2Read_out = fifoOp[0];
assign fx2Write_out = fifoOp[1];
assign chanAddr_out = chanAddr;
assign h2fData_out = fx2Data_io;
assign fx2Data_io = driveBus ? dataOut : 8'hZZ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CONB_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CONB_FUNCTIONAL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CONB_FUNCTIONAL_V
|
// test_mis.v - Testbench for mis.bvrl
// 01-22-01 E. Brombaugh
/*
* Copyright (c) 2001 Eric Brombaugh <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* The mis'' module was generated by the synopsis module compiler
* and is typical of the modules it generates. The testbench was hand
* coded. This file was merged into a single file using the Verilog
* preprocessor.
*/
`timescale 1ns / 10 ps
module mis( y, a, b );
input [3:0] a;
input [3:0] b;
output [12:0] y;
wire dpa_zero, dpa_one;
wire [5:0] const__1_24_;
wire [7:0] C0;
wire [6:0] const__2_33_;
wire [7:0] C1;
wire [12:0] y_1_;
assign dpa_zero= 1024'h0;
assign dpa_one= 1024'h1;
assign const__1_24_=- 1024'h18;
assign const__2_33_=- 1024'h21;
/* mis.mcl:4 module mis (y, a, b); */
/* mis.mcl:5 input signed [3:0] a, b; */
/* mis.mcl:10 C0 = -24; */
assign C0= ((const__1_24_[4:0]-(const__1_24_[5]<<5)));
/* mis.mcl:11 C1 = -33; */
assign C1= ((const__2_33_[5:0]-(const__2_33_[6]<<6)));
/* mis.mcl:13 y = C0*a + C1*b; */
assign y_1_= ((C0[6:0]-(C0[7]<<7))*(a[2:0]-(a[3]<<3))+
(C1[6:0]-(C1[7]<<7))*(b[2:0]-(b[3]<<3)));
/* mis.mcl:6 output signed [12:0] y; */
assign y = y_1_[12:0];
/* mis.mcl:4 module mis (y, a, b); */
/* mis.mcl:13 y = C0*a + C1*b; */
/*User Defined Aliases */
endmodule
module test_mis;
reg [10:0] count;
reg clk;
reg [3:0] a, b;
wire [12:0] y;
mis u1(y, a, b);
initial
begin
count = 0;
clk = 0;
a = 0;
b = 0;
end
always
#10 clk = ~clk;
always @(posedge clk)
begin
a = count[3:0];
b = count[7:4];
#10
$display("%h %h %h", a, b, y);
count = count + 1;
if(count == 0)
$finish(0);
end
endmodule
|
#include <bits/stdc++.h> const int dx[4] = {1, 0, -1, 0}; const int dy[4] = {0, -1, 0, 1}; using namespace std; char str[5001]; class Point { public: int Left; int Right; int Up; int Down; }; Point f1[5001], f2[5001]; int ans1, ans2, n, m; int dfs(int p, int tot) { int tmp; if (str[p] == D ) tmp = f2[p].Down; else if (str[p] == U ) tmp = f2[p].Up; else if (str[p] == L ) tmp = f2[p].Left; else tmp = f2[p].Right; if (f2[p].Left != -1) f2[f2[p].Left].Right = f2[p].Right; if (f2[p].Right != -1) f2[f2[p].Right].Left = f2[p].Left; if (f2[p].Up != -1) f2[f2[p].Up].Down = f2[p].Down; if (f2[p].Down != -1) f2[f2[p].Down].Up = f2[p].Up; if (ans1 == tot) ans2++; if (ans1 < tot) { ans1 = tot; ans2 = 1; } if (tmp != -1) dfs(tmp, tot + 1); return 0; } int work() { scanf( %d%d , &n, &m); getchar(); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) str[i * m + j] = getchar(); getchar(); } memset(f1, -1, sizeof(f1)); memset(f2, -1, sizeof(f2)); int k; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) { int p = i * m + j; if (str[p] == . ) continue; { k = i + 1; while (str[k * m + j] == . && k < n) k++; if (k < n) { f1[p].Down = k * m + j; f1[k * m + j].Up = p; } } { k = i - 1; while (str[k * m + j] == . && k >= 0) k--; if (k >= 0) { f1[p].Up = k * m + j; f1[k * m + j].Down = p; } } { k = j - 1; while (str[i * m + k] == . && k >= 0) k--; if (k >= 0) { f1[p].Left = i * m + k; f1[i * m + k].Right = p; } } { k = j + 1; while (str[i * m + k] == . && k < m) k++; if (k < m) { f1[p].Right = i * m + k; f1[i * m + k].Left = p; } } } ans1 = ans2 = 0; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) if (str[i * m + j] != . ) { for (int k = 0; k < 5001; ++k) f2[k] = f1[k]; dfs(i * m + j, 1); } printf( %d %d n , ans1, ans2); return 0; } int main() { work(); return 0; }
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This simple write master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post writes until the length register
reaches zero. When the length register reaches zero the 'done' bit is asserted.
To use this master you must simply drive the control signals into this block,
and also write the data to the exposed write FIFO. To read from the exposed FIFO
use the 'user_write_buffer' signal to push data into the FIFO 'user_buffer_data'.
The signal 'user_buffer_full' is asserted whenever the exposed buffer is full.
You should not attempt to write data to the exposed FIFO if it is full.
*/
// altera message_off 10230
module write_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_write_base,
control_write_length,
control_go,
control_done,
// user logic inputs and outputs
user_write_buffer,
user_buffer_data,
user_buffer_full,
// master inputs and outputs
master_address,
master_write,
master_byteenable,
master_writedata,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location; // this only makes sense to enable when MAXBURSTCOUNT = 1
input [ADDRESSWIDTH-1:0] control_write_base;
input [ADDRESSWIDTH-1:0] control_write_length;
input control_go;
output wire control_done;
// user logic inputs and outputs
input user_write_buffer;
input [DATAWIDTH-1:0] user_buffer_data;
output wire user_buffer_full;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_write;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [DATAWIDTH-1:0] master_writedata;
// internal control signals
reg control_fixed_location_d1;
reg [ADDRESSWIDTH-1:0] address; // this increments for each word
reg [ADDRESSWIDTH-1:0] length;
wire increment_address; // this increments the 'address' register when write is asserted and waitrequest is de-asserted
wire read_fifo;
wire user_buffer_empty;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master word increment counter
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if (control_go == 1)
begin
address <= control_write_base;
end
else if ((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if (control_go == 1)
begin
length <= control_write_length;
end
else if (increment_address == 1)
begin
length <= length - BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign control_done = (length == 0);
assign master_write = (user_buffer_empty == 0) & (control_done == 0);
assign increment_address = (user_buffer_empty == 0) & (master_waitrequest == 0) & (control_done == 0);
assign read_fifo = increment_address;
// write data feed by user logic
scfifo the_user_to_master_fifo (
.aclr (reset),
.clock (clk),
.data (user_buffer_data),
.full (user_buffer_full),
.empty (user_buffer_empty),
.q (master_writedata),
.rdreq (read_fifo),
.wrreq (user_write_buffer)
);
defparam the_user_to_master_fifo.lpm_width = DATAWIDTH;
defparam the_user_to_master_fifo.lpm_numwords = FIFODEPTH;
defparam the_user_to_master_fifo.lpm_showahead = "ON";
defparam the_user_to_master_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_user_to_master_fifo.add_ram_output_register = "OFF";
defparam the_user_to_master_fifo.underflow_checking = "OFF";
defparam the_user_to_master_fifo.overflow_checking = "OFF";
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX = (int)1e3 + 6; int n, ax, ay, cx, cy, bx, by; int dirx8[] = {0, 0, 1, -1, 1, -1, 1, -1}; int diry8[] = {1, -1, 0, 0, 1, -1, -1, 1}; bool vis[MX][MX]; void fast() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } bool vaild(int &x, int &y) { if (x < 1 || x > n || y < 1 || y > n || vis[x][y] || x == ax || y == ay || x + y - 1 == ax + ay - 1 || x + (n - y + 1) - 1 == ax + (n - ay + 1) - 1) return false; return true; } int main() { cin >> n; cin >> ax >> ay; cin >> bx >> by; cin >> cx >> cy; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { vis[i][j] = false; } } vis[bx][by] = true; queue<pair<int, int>> q; q.push({bx, by}); while (!q.empty()) { pair<int, int> p = q.front(); q.pop(); if (p.first == cx && p.second == cy) { cout << YES ; return 0; } for (int k = 0; k < 8; k++) { int px = p.first + dirx8[k], py = p.second + diry8[k]; if (vaild(px, py)) { vis[px][py] = true; q.push({px, py}); } } } cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int stmp; const int MAXB = 100000; const int INF = 1000000001; int vis[MAXB + 1]; vector<int> arr; int k, n, maxb, t, _t; int z; inline int lis() { vector<int> L(z, INF); for (int s = 0; s < (t); ++s) { for (int i = 0; i < ((int)(arr).size()) && L.back() == INF; ++i) *lower_bound((L).begin(), (L).end(), arr[i]) = arr[i]; int c = 0; for (int i = 0; i < (((int)(arr).size())); ++i) if (arr[i] == L[s]) ++c; else arr[i - c] = arr[i]; arr.erase(arr.end() - c, arr.end()); } return find((L).begin(), (L).end(), INF) - L.begin(); } int main(int argc, char *argv[]) { stmp = scanf( %d %d %d %d , &k, &n, &maxb, &_t); for (int c = (1); c <= (k); ++c) { arr.resize(n); int rb = 0; for (int i = 0; i < (n); ++i) { stmp = scanf( %d , &arr[i]); if (vis[arr[i]] != c) ++rb; vis[arr[i]] = c; } arr.resize(unique((arr).begin(), (arr).end()) - arr.begin()); z = rb; t = min(_t, z); printf( %d n , t < z ? lis() : z); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int ans; void solve(long long n, long long l1, long long r1, long long l, long long r) { if (n == 0 || l1 > r || r1 < l) return; long long mid = (l1 + r1) >> 1; if (mid >= l && mid <= r) ans += (n % 2); solve(n / 2, l1, mid - 1, l, r); solve(n / 2, mid + 1, r1, l, r); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, l, r; cin >> n, cin >> l, cin >> r; long long tmp = n, var = 0; while (tmp > 0) { tmp /= 2; var++; } long long num = (1LL << var) - 1; solve(n, 1, num, l, r); cout << ans << endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//////////////////////////////////////////////////////////////////
// Float to fixed converts floating point numbers to 16.16 sign
//
//
module flt_fx
(
input [31:0] fp_in, // Floating point in IEEE fmt
output reg [31:0] int_out // Fixed point integer out
);
//
// 24.8, Z.
// 16.16
// 12.8 U,V
//
wire [7:0] bias_exp; /* Real exponent -127 - 128 */
wire [7:0] bias_exp2; /* Real exponent 2's comp */
wire [39:0] fixed_out2; /* 2's complement of fixed out */
wire [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [38:0] int_fixed_out;
reg [31:0] fixed_out;
assign bias_mant = {25'h0001, fp_in[22:0]};
assign bias_exp = fp_in[30:23] - 8'd127;
assign bias_exp2 = ~bias_exp + 8'h1;
// infinity or NaN - Don't do anything special, will overflow
always @* begin
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant[38:0] >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant[38:0] << bias_exp;
fixed_out = int_fixed_out[38:7] + int_fixed_out[6];
int_out = (fp_in[31]) ? ~fixed_out + 1 : fixed_out;
end
endmodule
|
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module pc_bus_to_vga
(
input wire clk_sys,
input wire rst,
// input pc_bus_vga
input wire [31:0] pc_bus_vga_address,
input wire [3:0] pc_bus_vga_byteenable,
input wire pc_bus_vga_read,
output wire [31:0] pc_bus_vga_readdata,
input wire pc_bus_vga_write,
input wire [31:0] pc_bus_vga_writedata,
output wire pc_bus_vga_waitrequest,
output wire pc_bus_vga_readdatavalid,
input wire [2:0] pc_bus_vga_burstcount,
// output vga_mem
output wire [16:0] vga_mem_address,
output wire vga_mem_read,
input wire [7:0] vga_mem_readdata,
output wire vga_mem_write,
output wire [7:0] vga_mem_writedata
);
wire [31:0] burst_converted_address;
wire burst_converted_write;
wire [31:0] burst_converted_writedata;
wire burst_converted_read;
wire [31:0] burst_converted_readdata;
wire burst_converted_readdatavalid;
wire [3:0] burst_converted_byteenable;
wire burst_converted_waitrequest;
burst_converter #(.IADDR(32), .OADDR(32))
burst_converter (
.clk_sys (clk_sys),
.rst (rst),
.addr_in (pc_bus_vga_address),
.write_in (pc_bus_vga_write),
.writedata_in (pc_bus_vga_writedata),
.read_in (pc_bus_vga_read),
.readdata_out (pc_bus_vga_readdata),
.readdatavalid_out (pc_bus_vga_readdatavalid),
.byteenable_in (pc_bus_vga_byteenable),
.burstcount_in (pc_bus_vga_burstcount),
.waitrequest_out (pc_bus_vga_waitrequest),
.addr_out (burst_converted_address),
.write_out (burst_converted_write),
.writedata_out (burst_converted_writedata),
.read_out (burst_converted_read),
.readdata_in (burst_converted_readdata),
.readdatavalid_in (burst_converted_readdatavalid),
.byteenable_out (burst_converted_byteenable),
.waitrequest_in (burst_converted_waitrequest)
);
reg vga_mem_readdatavalid;
always @(posedge clk_sys) vga_mem_readdatavalid <= vga_mem_read;
byteen_converter #(.IADDR(32), .OADDR(17))
byteen_converter (
.clk_sys (clk_sys),
.rst (rst),
.addr_in (burst_converted_address),
.write_in (burst_converted_write),
.writedata_in (burst_converted_writedata),
.read_in (burst_converted_read),
.readdata_out (burst_converted_readdata),
.readdatavalid_out (burst_converted_readdatavalid),
.byteenable_in (burst_converted_byteenable),
.waitrequest_out (burst_converted_waitrequest),
.addr_out (vga_mem_address),
.write_out (vga_mem_write),
.writedata_out (vga_mem_writedata),
.read_out (vga_mem_read),
.readdata_in (vga_mem_readdata),
.readdatavalid_in (vga_mem_readdatavalid),
.waitrequest_in (0)
);
endmodule
|
// file: ClockDivider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___108.000______0.000______50.0______221.150____300.991
// CLK_OUT2_____9.000______0.000______50.0______327.887____300.991
// CLK_OUT3____18.000______0.000______50.0______295.409____300.991
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module ClockDivider
(
// Clock in ports
input clk,
// Clock out ports
output clk_vga,
output clk_cpu,
output clk_2cpu
);
ClockDivider_clk_wiz inst
(
// Clock in ports
.clk(clk),
// Clock out ports
.clk_vga(clk_vga),
.clk_cpu(clk_cpu),
.clk_2cpu(clk_2cpu)
);
endmodule
|
`timescale 1ns / 1ns
/*
* File : Divide.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Neil Russell
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 6-Nov-2012 NJR Initial design.
*
* Description:
* A multi-cycle 32-bit divider.
*
* On any cycle that one of OP_div or OP_divu are true, the Dividend and
* Divisor will be captured and a multi-cycle divide operation initiated.
* Stall will go true on the next cycle and the first cycle of the divide
* operation completed. After some time (about 32 cycles), Stall will go
* false on the same cycle that the result becomes valid. OP_div or OP_divu
* will abort any currently running divide operation and initiate a new one.
*/
module Divide(
input clock,
input reset,
input OP_div, // True to initiate a signed divide
input OP_divu, // True to initiate an unsigned divide
input [31:0] Dividend,
input [31:0] Divisor,
output [31:0] Quotient,
output [31:0] Remainder,
output Stall, // True while calculating
//Voter Signals for Registers
input active, // True if the divider is running
input neg, // True if the result will be negative
input [31:0] result, // Begin with dividend, end with quotient
input [31:0] denom, // Divisor
input [31:0] work,
output reg vote_active, // True if the divider is running
output reg vote_neg, // True if the result will be negative
output reg [31:0] vote_result, // Begin with dividend, end with quotient
output reg [31:0] vote_denom, // Divisor
output reg [31:0] vote_work
);
reg [4:0] cycle; // Number of cycles to go
// Calculate the current digit
wire [32:0] sub = { work[30:0], result[31] } - denom;
// Send the results to our master
assign Quotient = !neg ? result : -result;
assign Remainder = work;
assign Stall = active;
// The state machine
always @(posedge clock) begin
if (reset) begin
vote_active <= 0;
vote_neg <= 0;
cycle <= 0;
vote_result <= 0;
vote_denom <= 0;
vote_work <= 0;
end
else begin
if (OP_div) begin
// Set up for a signed divide. Remember the resulting sign,
// and make the operands positive.
cycle <= 5'd31;
vote_result <= (Dividend[31] == 0) ? Dividend : -Dividend;
vote_denom <= (Divisor[31] == 0) ? Divisor : -Divisor;
vote_work <= 32'b0;
vote_neg <= Dividend[31] ^ Divisor[31];
vote_active <= 1;
end
else if (OP_divu) begin
// Set up for an unsigned divide.
cycle <= 5'd31;
vote_result <= Dividend;
vote_denom <= Divisor;
vote_work <= 32'b0;
vote_neg <= 0;
vote_active <= 1;
end
else if (active) begin
// Run an iteration of the divide.
if (sub[32] == 0) begin
vote_work <= sub[31:0];
vote_result <= {result[30:0], 1'b1};
end
else begin
vote_work <= {work[30:0], result[31]};
vote_result <= {result[30:0], 1'b0};
end
if (cycle == 0) begin
vote_active <= 0;
end
cycle <= cycle - 5'd1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_4_V
`define SKY130_FD_SC_MS__EBUFN_4_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ebufn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ebufn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; long long int a, b, c; cin >> t; while (t--) { cin >> a >> b >> c; long long int max_val = (a + c); long long int min_val = b; if (a + c <= b) { cout << 0 << endl; } else if (b + c < a) { cout << c + 1 << endl; } else { long long int ans = (max_val - min_val + 1) / 2; cout << ans << endl; } } }
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_AsyncResetRegVec(
input clock,
input reset,
input io_d,
output io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
assign io_q = reg_0_q;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = io_d;
endmodule
|
`timescale 1ns/1ns
`define CLK_PERIOD 40
module tb;
reg rst_n;
reg clk;
initial
begin
clk = 1'b0;
forever
#(`CLK_PERIOD/2) clk <= ~clk;
end
initial
begin
rst_n = 1'b0;
repeat(3) @(posedge clk);
rst_n <= 1'b1;
end
reg [3:0] pre_reqs;
reg [3:0] reqs;
reg [3:0] prev;
wire [3:0] next;
reg [3:0] ref_next;
reg [3:0] was_prev,was_reqs,was_next;
initial
begin : test_rr_arbiter
prev = 4'b0001;
reqs = 4'b0001;
repeat()
begin
@(posedge clk);
//pre_reqs = 4'd0;
//while( !pre_reqs )
pre_reqs = $random>>28;
reqs <= pre_reqs;
end
@(posedge clk);
$stop ;
end
always @(posedge clk)
begin
prev <= next;
was_prev <= prev;
was_reqs <= reqs;
was_next <= next;
#1; // allow for nonblocking assignment to take place
arbiter_predict(was_reqs,was_prev,ref_next);
if( ref_next != was_next )
begin
$display("unequal! prev=%4b, reqs=%4b: reference_next=%4b, next=%4b\n",was_prev,was_reqs,ref_next,was_next);
end
end
task arbiter_predict;
input [3:0] reqs;
input [3:0] prev;
output [3:0] next;
integer i,j,k;
begin : disable_me
if( !reqs )
begin
next = 4'd0;
end
else if( prev )
begin
i=0;
while( !prev[i] )
i=i+1;
i=(i+1)&2'b11;
while( !reqs[i] )
begin
i=(i+1)&2'b11;
end
next = 4'd1<<i;
end
else // !prev
begin
i=0;
while( !reqs[i] )
i=i+1;
next = 4'd1<<i;
end
end
endtask
rr_arbiter arbiter( .reqs(reqs),
.prev(prev),
.next(next)
);
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_light_time_in (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 5: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 5: 0] data_out;
wire [ 5: 0] out_port;
wire [ 5: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {6 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[5 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
////#include <iostream> ////#include <cstdio> ////#include <cstring> ////#include <algorithm> //// ////#define LL long long //// ////LL gcd(LL a,LL b) { //// if(b == 0) return a; //// else return gcd(b,a % b); ////} //// ////inline LL calc(LL x) { //// LL ret = 0; //// while(x) { //// ret += x % 10; //// x /= 10; //// } //// return ret; ////} //// ////int main() { //// int T; scanf( %d ,&T); //// LL n,x; //// while(T--) { //// scanf( %lld ,&n); //// x = 0; //// for(LL i=n; i; i++) { //// if(gcd(i,calc(i)) >= 2) { //// printf( %lld n ,i); //// break; //// } //// } //// } //// return 0; ////} // //#include <iostream> //#include <cstring> //#include <cstdio> //#include <algorithm> //#include <map> //#define Maxn 100005 //using namespace std; //int a[1005000]; //map<int,int> mp; //int main(int argc,char* argv[]) { // int T; scanf( %d ,&T); // // while(T--) { // mp.clear(); // int k = 524288,tmp = k; // while (tmp) { // a[tmp] = 0; // tmp >>= 1; // } // int n,w,x,ans = 0; // cin >> n >> w; // for(int i=0; i<n; i++) cin >> x,a[x]++; // while(n) { // int tmp = k,sum = w; // while(tmp) { // if(a[tmp]) { // int cnt = sum / tmp; // cnt = min(cnt,a[tmp]); // sum -= cnt * tmp; // a[tmp] -= cnt; // n -= cnt; // } // tmp >>= 1; // } // ans++; // } // cout << ans << endl; // } // return 0; //} #include <iostream> #include <cstring> #include <cstdio> #define Maxn 1005 using namespace std; int dp[Maxn][Maxn]; const int Mod = 1e9 + 7; int solve(int n,int k,int total) { if(n <= 0 || k <= 1) return 1; else { if(dp[n][k] == -1) dp[n][k] = ((solve(n - 1,k,total) % Mod + solve(total - n,k - 1,total) % Mod)) % Mod; return (dp[n][k] % Mod); } } int main(int argc,char* argv[]) { int T,n,k; scanf( %d ,&T); while(T--) { scanf( %d %d ,&n,&k); memset(dp,-1,sizeof(dp)); cout << solve(n,k,n) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int soch(int a) { if (a == 3) return 1; return soch(a - 1) * a / (a - 3); } int main() { int n, num, i, j, k, raz, dob, num1, dob1, sum = 0, flag = 0, flag1 = 0; bool graf[105][105]; bool graf1[6][6]; vector<pair<int, int>> ver; vector<int> v; vector<int> v1; vector<int> v2; cin >> k; for (i = 1; i <= 100; i++) for (j = 1; j <= 100; j++) graf[i][j] = 0; for (i = 3; i <= 100; i++) { v2.push_back(soch(i)); if (soch(i) > k) break; } num = i - 1; raz = k - soch(num); v.push_back(0); v.push_back(1); for (i = 3; i <= num; i++) v.push_back(soch(i + 1) - soch(i)); for (i = 0; i < v.size(); i++) if (v[i] > raz) { dob = i - 1; break; }; raz -= v[dob]; dob++; k = raz; if (k) { flag1 = 1; for (i = 3; i <= 100; i++) if (soch(i) > k) break; num1 = i - 1; raz = k - soch(num1); for (i = 0; i < v.size(); i++) if (v[i] > raz) { dob1 = i - 1; break; }; raz -= v[dob1]; dob1++; k = raz; } if (k == 3) { flag = 1; v1.push_back(5); for (i = 1; i <= 5; i++) for (j = 1; j <= 5; j++) if (i != j) graf1[i][j] = 1; else graf1[i][j] = 0; graf1[1][3] = graf1[3][1] = graf1[1][4] = graf1[4][1] = graf1[4][3] = graf1[3][4] = 0; } if (!flag) for (i = v2.size() - 1; k > 0; i--) while (v2[i] <= k) { k -= v2[i]; v1.push_back(i + 3); } for (i = 0; i < v1.size(); i++) sum += v1[i]; if (!flag1) num1 = dob1 = 0; n = num + num1 + sum + 1 + flag1; cout << n << endl; for (i = 1; i <= num; i++) for (j = 1; j <= num; j++) if (i != j) graf[i][j] = 1; for (j = 1; j <= dob; j++) graf[num + 1][j] = graf[j][num + 1] = 1; if (flag1) { for (i = num + 2; i <= num + num1 + 1; i++) for (j = num + 2; j <= num + num1 + 1; j++) if (i != j) graf[i][j] = 1; for (j = num + 2; j <= dob1 + num + 1; j++) graf[num + num1 + 2][j] = graf[j][num + num1 + 2] = 1; num = num + num1 + 1; } if (!flag) { raz = 2; for (k = 0; k < v1.size(); k++) { for (i = num + raz; i <= num + raz + v1[k] - 1; i++) for (j = num + raz; j <= num + raz + v1[k] - 1; j++) if (i != j) graf[i][j] = 1; raz += v1[k]; } } else { for (i = 0; i < 5; i++) for (j = 0; j < 5; j++) graf[num + 2 + i][num + 2 + j] = graf1[i + 1][j + 1]; } for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) cout << graf[i][j]; cout << endl; } return 0; }
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build Mon Apr 27 19:22:08 MDT 2015
// Date : Sun Mar 13 07:43:22 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/dcfifo_32in_32out_8kb/dcfifo_32in_32out_8kb_stub.v
// Design : dcfifo_32in_32out_8kb
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
module dcfifo_32in_32out_8kb(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, wr_data_count)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,wr_data_count[1:0]" */;
input rst;
input wr_clk;
input rd_clk;
input [31:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output empty;
output [1:0]wr_data_count;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string a; int b; cin >> b >> a; for (int i = 2; i <= b; i++) { if (b % i == 0) { reverse(a.begin(), a.begin() + i); } } cout << a; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 5; string s; long long a, b; long long v[N], pre[N], suf[N]; int32_t main() { cin >> s >> a >> b; long long n = s.size(); for (long long i = 1; i <= n; i++) v[i] = s[i - 1] - 0 ; for (long long i = 1; i <= n; i++) { pre[i] = pre[i - 1] * 10 + v[i]; pre[i] %= a; } long long curpow = 1; for (long long i = n; i >= 1; i--) { suf[i] = v[i] * curpow + suf[i + 1]; curpow *= 10; curpow %= b; suf[i] %= b; } long long check = 0, ind; for (long long i = 1; i < n; i++) { if (pre[i] == 0 && suf[i + 1] == 0 && v[i + 1] != 0) { ind = i; check = 1; } } if (check) { cout << YES << n ; for (long long i = 1; i <= ind; i++) { cout << v[i]; } cout << n ; for (long long i = ind + 1; i <= n; i++) { cout << v[i]; } } else cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); int deg[1000]; int arr[1000][1000]; int jo[1000]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int node, edge; cin >> node >> edge; for (int i = 0; i < edge; i++) { int n1, n2; cin >> n1 >> n2; arr[n1 - 1][n2 - 1] = true; arr[n2 - 1][n1 - 1] = true; deg[n1 - 1]++; deg[n2 - 1]++; } int res = 0; int i, j; while (true) { int k = 0; for (i = 0; i < node; i++) { if (deg[i] == 1) { jo[k++] = i; deg[i] = 0; } } if (k == 0) { break; } res++; for (i = 0; i < k; i++) { deg[jo[i]] = 0; for (j = 0; j < node; j++) { if (arr[jo[i]][j]) deg[j]--; } } } cout << res << n ; cerr << Time : << (float)clock() / CLOCKS_PER_SEC << s << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool comp(int a, int b) { return (a > b); } int gcd(long long int a, long long int b) { if (b == 0) return a; else return gcd(b, a % b); } int main(void) { int n, p; cin >> n >> p; int l[n], r[n], i; long long int c, cp, l1, l2; double ans = 0; for (i = 0; i < n; ++i) cin >> l[i] >> r[i]; for (i = 0; i < n; ++i) { l1 = r[i] - l[i] + 1; l2 = r[(i - 1 + n) % n] - l[(i - 1 + n) % n] + 1; c = r[i] / p - (l[i] - 1) / p; cp = r[(i - 1 + n) % n] / p - (l[(i - 1 + n) % n] - 1) / p; ans += (2000.0 * (c * l2 + cp * l1 - (c * cp))) / (l1 * l2); } printf( %.10lf , ans); return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: nine_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module nine_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../newnums2/nine_new2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/nine_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/nine_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nine_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// file: clk_166M_83M.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___166.667______0.000______50.0______211.699____237.727
// CLK_OUT2____83.333______0.000______50.0______235.626____237.727
// CLK_OUT3____83.333____180.000______50.0______235.626____237.727
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________25.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_166M_83M,clk_wiz_v3_3,{component_name=clk_166M_83M,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=3,clkin1_period=40.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module clk_166M_83M
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCM_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (40.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (6.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (12),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (12),
.CLKOUT2_PHASE (180.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (40.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkout2));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long a, b, c, d, e, first; cin >> a >> b >> c >> d >> e >> first; b = min(c, b); if (d < a && d < b) cout << d * max(e, first); else { long long p = min(a, d) * e + min(d - min(d, a), b) * first; long long q = min(b, d) * first + min(d - min(d, b), a) * e; cout << max(p, q); } }
|
#include <bits/stdc++.h> using namespace std; const long long MAGIC = 400; const long long N = 1e5 + 2; const long long inf = 1e14 + 2; long long lzval[MAGIC], lzmul[MAGIC], ar[N], add[N]; bool used[N]; vector<long long> idx[MAGIC]; struct hull { long long ptr; struct line { long long a, b, idx; long long y(long long x) { return a * x + b; } }; vector<line> hull; bool bad(line x, line y, line z) { assert(y.a != x.a); if (z.a == y.a) { return z.b > y.b; } return (1.0 * (x.b - z.b)) / (z.a - x.a) < (1.0 * (y.b - z.b)) / (z.a - y.a); } void insert(line a) { while (hull.size() > 1) { if (bad(hull[hull.size() - 2], hull[hull.size() - 1], a)) { hull.pop_back(); } else { break; } } if (hull.size() && hull.back().a == a.a) { if (hull.back().b > a.b) { return; } else { hull.pop_back(); } } hull.push_back(a); } void build(vector<long long> &wow) { hull.clear(); ptr = 0; for (long long i = 0; i < wow.size(); i++) { long long idx = wow[i]; if (used[idx]) { continue; } line tmp; tmp.a = ar[idx]; tmp.b = add[idx]; tmp.idx = idx; insert(tmp); } } pair<long long, long long> get(long long idx) { while (ptr + 1 < hull.size() && hull[ptr].y(lzmul[idx]) < hull[ptr + 1].y(lzmul[idx])) { ptr++; } return pair<long long, long long>(hull[ptr].y(lzmul[idx]) + lzval[idx], -hull[ptr].idx); } } lis[MAGIC]; long long grp(long long x) { return (x + MAGIC - 1) / MAGIC; } bool cmp(long long x, long long y) { if (ar[x] != ar[y]) { return ar[x] > ar[y]; } return add[x] > add[y]; } signed main() { ios::sync_with_stdio(0); cin.tie(0); long long n, i, j, k, l, mx, ans = 0, mxans = 0, z, q; cin >> n; for (i = 1; i <= n; i++) { cin >> ar[i]; add[i] = ar[i]; idx[grp(i)].push_back(i); } mx = grp(n); for (i = 1; i <= mx; i++) { sort(idx[i].begin(), idx[i].end(), cmp); lis[i].build(idx[i]); } for (i = 1; i <= n; i++) { pair<long long, long long> res = {-inf, -1}; for (j = 1; j <= mx; j++) { if (lis[j].hull.size()) { res = max(res, lis[j].get(j)); pair<long long, long long> kek = lis[j].get(j); } } ans += res.first; mxans = max(mxans, ans); q = j = -res.second; used[j] = true; j = grp(j); for (k = j + 1; k <= mx; k++) { lzmul[k]++; } for (k = 1; k < j; k++) { lzval[k] += ar[q]; } k = (j - 1) * MAGIC + 1, l = min(j * MAGIC, n); for (z = k; z <= l; z++) { add[z] += lzval[j] + lzmul[j] * ar[z]; if (z >= q) { add[z] += ar[z]; } else { add[z] += ar[q]; } } lzval[j] = lzmul[j] = 0; lis[j].build(idx[j]); } cout << mxans; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n1, n2, i, j, n, ma = 0, temp, c; cin >> n1 >> n2; if (n1 < n2) { cout << 2 ; } else { cout << n1; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int a[maxn], b[maxn]; int p[maxn]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } memset(p, 0, sizeof(p)); for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); p[b[i]] = i; } if (p[1]) { for (int i = 1; p[i] == p[1] + i - 1; i++) { if (p[i] == n) { int k = i + 1; for (; k <= n && p[k] <= k - i - 1; k++) ; if (k > n) { printf( %d n , n - i); return 0; } } } } int ans = 0; for (int i = 1; i <= n; i++) { ans = max(ans, p[i] - i + 1 + n); } printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__OR3_PP_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [83:4] from;
reg [83:4] to;
reg [6:0] bitn;
reg [3:0] nibblep;
reg [3:0] nibblem;
reg [7:0] cyc; initial cyc=0;
always @* begin
nibblep = from[bitn +: 4];
nibblem = from[bitn -: 4];
to = from;
to[bitn +: 4] = cyc[3:0];
to[bitn -: 4] = cyc[3:0];
end
always @ (posedge clk) begin
//$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n",$time, cyc, nibblep, nibblem, from^to);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin from<=80'h7bea9d779b67e48f67da; bitn<=7'd7; end
8'd01: begin from<=80'hefddce326b11ca5dc448; bitn<=7'd8; end
8'd02: begin from<=80'h3f99c5f34168401e210d; bitn<=7'd4; end // truncate -:
8'd03: begin from<=80'hc90635f0a7757614ce3f; bitn<=7'd79; end
8'd04: begin from<=80'hc761feca3820331370ec; bitn<=7'd83; end // truncate +:
8'd05: begin from<=80'hd6e36077bf28244f84b5; bitn<=7'd6; end // half trunc
8'd06: begin from<=80'h90118c5d3d285a1f3252; bitn<=7'd81; end // half trunc
8'd07: begin from<=80'h38305da3d46b5859fe16; bitn<=7'd67; end
8'd08: begin from<=80'h4b9ade23a8f5cc5b3111; bitn<=7'd127; end // truncate
8'd09: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
case (cyc)
8'd00: ;
8'd01: begin if ((nibblep & 4'b1111)!==4'b1011) $stop; if ((nibblem & 4'b1111)!==4'b1010) $stop; end
8'd02: begin if ((nibblep & 4'b1111)!==4'b0100) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end
8'd03: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end
8'd04: begin if ((nibblep & 4'b1111)!==4'b1001) $stop; if ((nibblem & 4'b1111)!==4'b1001) $stop; end
8'd05: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b1100) $stop; end
8'd06: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end
8'd07: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end
8'd08: begin if ((nibblep & 4'b1111)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0101) $stop; end
8'd09: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end
default: $stop;
endcase
case (cyc)
8'd00: ;
8'd01: begin if ((to^from)!==80'h0000000000000000005b) $stop; end
8'd02: begin if ((to^from)!==80'h0000000000000000006c) $stop; end
8'd03: begin if ((to^from)!==80'h0000000000000000000e) $stop; end
8'd04: begin if ((to^from)!==80'h6d000000000000000000) $stop; end
8'd05: begin if (((to^from)&~80'hf)!==80'h90000000000000000000) $stop; end // Exceed bounds, verilator may write index 0
8'd06: begin if (((to^from)&~80'hf)!==80'h00000000000000000020) $stop; end // Exceed bounds, verilator may write index 0
8'd07: begin if (((to^from)&~80'hf)!==80'h0c000000000000000000) $stop; end
8'd08: begin if ((to^from)!==80'h0004d000000000000000) $stop; end
8'd09: begin if (((to^from)&~80'hf)!==80'h00000000000000000000) $stop; end
default: $stop;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Connection Bus Top Level ////
//// ////
//// ////
//// Author: Johny Chi ////
//// ////
//// skar.Wei ////
//// Just-CJ ////
//// ////
//// ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// Copyright (C) 2014-2015 skar.Wei<> ////
//// Copyright (C) 2015 Just-CJ<> ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation;////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// Description
// 1. Up to 8 masters and 8 slaves share bus Wishbone connection
// 2. no priorty arbitor , 8 masters are processed in a round
// robin way,
// 3. if WB_USE_TRISTATE was defined, the share bus is a tristate
// bus, and use less logic resource.
// 4. wb_conbus was synthesis to XC2S100-5-PQ208 using synplify,
// Max speed >60M , and 374 SLICE if using Multiplexor bus
// or 150 SLICE if using tri-state bus.
//
//`define WB_USE_TRISTATE
`include "irq_controller_defines.v"
module irq_controller(
clk_i, rst_i,
i_gnt_arb,
intrrupt_en,
// Master 0 Interface
m0_irq_o, m0_Iack_i,
// Device 0 Interface
d0_irq_i, d0_Iack_o,
// Device 1 Interface
d1_irq_i, d1_Iack_o,
// Device 2 Interface
d2_irq_i, d2_Iack_o,
// Device 3 Interface
d3_irq_i, d3_Iack_o,
// Device 4 Interface
d4_irq_i, d4_Iack_o,
// Device 5 Interface
d5_irq_i, d5_Iack_o,
// Device 6 Interface
d6_irq_i, d6_Iack_o,
// Device 7 Interface
d7_irq_i, d7_Iack_o
);
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk_i, rst_i;
output wire [`irqNum - 1: 0]
i_gnt_arb;
input wire intrrupt_en;
// Master 0 Interface
input m0_Iack_i;
output m0_irq_o;
// Slave 0 Interface
input d0_irq_i;
output d0_Iack_o;
// Slave 1 Interface
input d1_irq_i;
output d1_Iack_o;
// Slave 2 Interface
input d2_irq_i;
output d2_Iack_o;
// Slave 3 Interface
input d3_irq_i;
output d3_Iack_o;
// Slave 4 Interface
input d4_irq_i;
output d4_Iack_o;
// Slave 5 Interface
input d5_irq_i;
output d5_Iack_o;
// Slave 6 Interface
input d6_irq_i;
output d6_Iack_o;
// Slave 7 Interface
input d7_irq_i;
output d7_Iack_o;
////////////////////////////////////////////////////////////////////
//
// Local wires
//
wire [`irqBit - 1: 0]
gnt;
reg i_bus_irq; // internal share bus, master data and control to slave
wire i_bus_ack; // internal share bus , slave control to master
////////////////////////////////////////////////////////////////////
//
// Master output Interfaces
//
// devices
assign d0_Iack_o = i_bus_ack & i_gnt_arb[0];
assign d1_Iack_o = i_bus_ack & i_gnt_arb[1];
assign d2_Iack_o = i_bus_ack & i_gnt_arb[2];
assign d3_Iack_o = i_bus_ack & i_gnt_arb[3];
// TODO: modify i_bus_s to fit number of slaves
assign i_bus_ack = { m0_Iack_i }; //s5_Iack_i | s6_Iack_i | s7_Iack_i};
////////////////////////////////
// Slave output interface
//
// slave1
assign m0_irq_o = i_bus_irq & intrrupt_en;
///////////////////////////////////////
// Master and Slave input interface
//
always @(gnt,
d0_irq_i,
d1_irq_i,
d2_irq_i,
d3_irq_i)
begin
case(gnt)
`irqBit'h0: i_bus_irq = d0_irq_i;
`irqBit'h1: i_bus_irq = d1_irq_i;
`irqBit'h2: i_bus_irq = d2_irq_i;
`irqBit'h3: i_bus_irq = d3_irq_i;
default:i_bus_irq = 0; //{m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i};
endcase
end
//
// arbitor
//
assign i_gnt_arb[0] = (gnt == `irqBit'd0);
assign i_gnt_arb[1] = (gnt == `irqBit'd1);
assign i_gnt_arb[2] = (gnt == `irqBit'd2);
assign i_gnt_arb[3] = (gnt == `irqBit'd3);
irq_arb irq_arb(
.clk(clk_i),
.rst(rst_i),
.req(
{d3_irq_i,
d2_irq_i,
d1_irq_i,
d0_irq_i}
),
.gnt(gnt)
);
endmodule
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int i = 1; while ((i * (i + 1) / 2) <= n) { if ((i * (i + 1) / 2) == n) { printf( YES ); return 0; } i++; } printf( NO ); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NOR4_BEHAVIORAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4 (
VPWR,
VGND,
Y ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; bool able[105], prime[105], left[105], flag = 0; int least = 1; string tp; bool isPrime(int i) { int to = int(sqrt(double(i) + 1.0)); if (i == 1 || i == 2 || i == 5) return 1; for (int j = 2; j <= to; j++) if (i % j == 0) return 0; return 1; } int main() { for (int i = 1; i <= 100; i++) if (isPrime(i)) prime[i] = 1; for (int i = 2; i <= 50; i++) { if (prime[i] == 0) continue; cout << i << endl; cin >> tp; if (tp[0] == y ) { if (flag == 1) { cout << composite << endl; fflush(stdout); return 0; } if (i >= 11) { cout << prime << endl; fflush(stdout); return 0; } flag = 1; cout << i * i << endl; cin >> tp; if (tp[0] == y ) { cout << composite << endl; fflush(stdout); return 0; } } } cout << prime << endl; fflush(stdout); return 0; }
|
#include <bits/stdc++.h> using namespace std; int const N = 100000; vector<pair<int, int> > g[N + 1]; vector<int> imp; long long cl[42][N + 1]; int dp[N + 1], n; pair<int, long long> pa[N + 1][17]; bool vis[N + 1]; void pl(int v = 1, int p = 0, int w = 0) { dp[v] = dp[p] + 1; vis[v] = true; pa[v][0] = make_pair(p, w); int k = 1, z; while (k < 17 && (z = pa[v][k - 1].first)) pa[v][k] = make_pair(pa[z][k - 1].first, pa[v][k - 1].second + pa[z][k - 1].second), ++k; for (int i = 0; i < (int)(g[v].size()); ++i) { int u = g[v][i].first; if (u == p) continue; if (vis[u]) imp.push_back(v), imp.push_back(u); else pl(u, v, g[v][i].second); } } long long dis(int a, int b) { if (dp[a] < dp[b]) swap(a, b); int d = dp[a] - dp[b], j = 0; long long an = 0; while (d) { if (d & 1) an += pa[a][j].second, a = pa[a][j].first; d >>= 1; ++j; } if (a == b) return an; for (int i = 16; i >= 0; --i) if (pa[a][i].first != pa[b][i].first) an += pa[a][i].second + pa[b][i].second, a = pa[a][i].first, b = pa[b][i].first; return an + pa[a][0].second + pa[b][0].second; } void bfs(int v, long long dis[]) { for (int i = 1; i < (int)(n + 1); ++i) dis[i] = 1e18; priority_queue<pair<long long, int> > q; q.push(make_pair(0, v)); dis[v] = 0; while (!q.empty()) { int v = q.top().second; long long d = -q.top().first; q.pop(); for (int i = 0; i < (int)(g[v].size()); ++i) { int u = g[v][i].first; long long nd = d + g[v][i].second; if (dis[u] > nd) { dis[u] = nd; q.push(make_pair(-nd, u)); } } } } int main() { int m; scanf( %d%d , &n, &m); for (int i = 0; i < (int)(m); ++i) { int a, b, c; scanf( %d%d%d , &a, &b, &c); g[a].push_back(make_pair(b, c)); g[b].push_back(make_pair(a, c)); } pl(); sort(imp.begin(), imp.end()); imp.resize(unique(imp.begin(), imp.end()) - imp.begin()); for (int i = 0; i < (int)(imp.size()); ++i) bfs(imp[i], cl[i]); int q; scanf( %d , &q); while (q--) { int a, b; scanf( %d%d , &a, &b); long long an = dis(a, b); for (int i = 0; i < (int)(imp.size()); ++i) for (int j = 0; j < (int)(imp.size()); ++j) an = min(an, cl[i][a] + cl[i][imp[j]] + cl[j][b]); printf( %lld n , an); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2AI_TB_V
`define SKY130_FD_SC_LP__O2BB2AI_TB_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2bb2ai.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_lp__o2bb2ai dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2AI_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; long long m, k; scanf( %d%lld%lld , &n, &m, &k); long long a[n], asum[n + 1]; asum[0] = 0; for (int((i)) = (0); ((i)) < ((n)); ++((i))) { scanf( %lld , &a[i]); asum[i + 1] = asum[i] + a[i]; } long long dp[m]; for (int((i)) = (0); ((i)) < ((m)); ++((i))) dp[i] = 1e18; long long ans = 0; for (int((i)) = (0); ((i)) < ((n)); ++((i))) { dp[i % m] = min(dp[i % m] + k, asum[i] + k); for (int((j)) = (0); ((j)) < ((m)); ++((j))) ans = max(ans, asum[i + 1] - dp[j]); } printf( %lld n , ans); }
|
//////////////////////////////////////////////////////////////////////////////////
// ScrambleEncoder for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: ScrambleEncoder
// Module Name: ScrambleEncoder
// File Name: ScrambleEncoder.v
//
// Version: v1.0.0
//
// Description: scrambler encoder
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ScrambleEncoder
#
(
parameter AddressWidth = 32 ,
parameter DataWidth = 32 ,
parameter InnerIFLengthWidth = 16 ,
parameter ThisID = 3
)
(
iClock ,
iReset ,
iSrcOpcode ,
iSrcTargetID ,
iSrcSourceID ,
iSrcAddress ,
iSrcLength ,
iSrcCmdValid ,
oSrcCmdReady ,
oDstOpcode ,
oDstTargetID ,
oDstSourceID ,
oDstAddress ,
oDstLength ,
oDstCmdValid ,
iDstCmdReady ,
oSrcReadData ,
oSrcReadValid ,
oSrcReadLast ,
iSrcReadReady ,
iDstReadData ,
iDstReadValid ,
iDstReadLast ,
oDstReadReady
);
input iClock ;
input iReset ;
input [5:0] iSrcOpcode ;
input [4:0] iSrcTargetID ;
input [4:0] iSrcSourceID ;
input [AddressWidth - 1:0] iSrcAddress ;
input [InnerIFLengthWidth - 1:0] iSrcLength ;
input iSrcCmdValid ;
output oSrcCmdReady ;
output [5:0] oDstOpcode ;
output [4:0] oDstTargetID ;
output [4:0] oDstSourceID ;
output [AddressWidth - 1:0] oDstAddress ;
output [InnerIFLengthWidth - 1:0] oDstLength ;
output oDstCmdValid ;
input iDstCmdReady ;
output [DataWidth - 1:0] oSrcReadData ;
output oSrcReadValid ;
output oSrcReadLast ;
input iSrcReadReady ;
input [DataWidth - 1:0] iDstReadData ;
input iDstReadValid ;
input iDstReadLast ;
output oDstReadReady ;
reg [5:0] rOpcode ;
reg [4:0] rTargetID ;
reg [4:0] rSourceID ;
reg [AddressWidth - 1:0] rAddress ;
reg [InnerIFLengthWidth - 1:0] rLength ;
reg rDstCValid ;
reg [DataWidth - 1:0] rRowAddress ;
parameter DispatchCmd_PageReadFromRAM = 6'b000001 ;
parameter DispatchCmd_SpareReadFromRAM = 6'b000010 ;
localparam State_Idle = 3'b000;
localparam State_BypassCmd = 3'b001;
localparam State_BypassTrf = 3'b011;
localparam State_EncTrfCmd = 3'b010;
localparam State_EncTrf = 3'b110;
reg [2:0] rCurState;
reg [2:0] rNextState;
always @ (posedge iClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
if (iSrcCmdValid && (iSrcTargetID != ThisID))
begin
if ((iSrcTargetID == 0) && ((iSrcOpcode == DispatchCmd_PageReadFromRAM) || (iSrcOpcode == DispatchCmd_SpareReadFromRAM)))
rNextState <= State_EncTrfCmd;
else
rNextState <= State_BypassCmd;
end
else
rNextState <= State_Idle;
State_BypassCmd:
if (iDstCmdReady)
begin
if (rLength == 0)
rNextState <= State_Idle;
else
rNextState <= State_BypassTrf;
end
else
rNextState <= State_BypassCmd;
State_BypassTrf:
rNextState <= (iDstReadValid && iDstReadLast && iSrcReadReady)?State_Idle:State_BypassTrf;
State_EncTrfCmd:
rNextState <= (iDstCmdReady)?State_EncTrf:State_EncTrfCmd;
State_EncTrf:
rNextState <= (iDstReadValid && iDstReadLast && iSrcReadReady)?State_Idle:State_EncTrf;
default:
rNextState <= State_Idle;
endcase
assign oSrcCmdReady = (rCurState == State_Idle);
assign oDstOpcode = rOpcode ;
assign oDstTargetID = rTargetID ;
assign oDstSourceID = rSourceID ;
assign oDstAddress = rAddress ;
assign oDstLength = rLength ;
assign oDstCmdValid = rDstCValid ;
always @ (posedge iClock)
if (iReset)
begin
rOpcode <= 6'b0;
rTargetID <= 5'b0;
rSourceID <= 5'b0;
rAddress <= {(AddressWidth){1'b0}};
rLength <= {(InnerIFLengthWidth){1'b0}};
end
else
begin
if (rCurState == State_Idle && iSrcCmdValid)
begin
rOpcode <= iSrcOpcode ;
rTargetID <= iSrcTargetID ;
rSourceID <= iSrcSourceID ;
rAddress <= iSrcAddress ;
rLength <= iSrcLength ;
end
end
always @ (*)
case (rCurState)
State_BypassCmd:
rDstCValid <= 1'b1;
State_EncTrfCmd:
rDstCValid <= 1'b1;
default:
rDstCValid <= 1'b0;
endcase
always @ (posedge iClock)
if (iReset)
rRowAddress <= {(DataWidth){1'b0}};
else
if (rCurState == State_Idle && iSrcCmdValid && (iSrcTargetID == ThisID))
rRowAddress <= iSrcAddress;
wire [DataWidth - 1:0] wLFSROut;
genvar i;
parameter IndexWidth = $clog2(DataWidth / 8);
wire [IndexWidth * (DataWidth / 8) - 1:0] wIndex;
generate
for (i = 0; i < DataWidth / 8; i = i + 1)
begin
assign wIndex[IndexWidth * (i + 1) - 1:IndexWidth * i] = {(IndexWidth){1'b1}} & i;
LFSR8
Inst_LFSR
(
.iClock (iClock ),
.iReset (iReset ),
.iSeed ({rRowAddress,
wIndex[IndexWidth * (i + 1) - 1:IndexWidth * i]}),
.iSeedEnable (rCurState == State_EncTrfCmd ),
.iShiftEnable ((rCurState == State_EncTrf) &&
iDstReadValid && iSrcReadReady ),
.oData (wLFSROut[8 * (i + 1) - 1:8 * i] )
);
end
endgenerate
assign oSrcReadValid = iDstReadValid && ((rCurState == State_EncTrf) || (rCurState == State_BypassTrf));
assign oSrcReadLast = iDstReadLast;
assign oSrcReadData = (rCurState == State_EncTrf)?(wLFSROut ^ iDstReadData):iDstReadData;
assign oDstReadReady = iSrcReadReady && ((rCurState == State_EncTrf) || (rCurState == State_BypassTrf));;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); long long i, j, x, n, m, l, r; cin >> n >> m; vector<long long> v; for (i = 0; i < n; i++) { cin >> x; v.push_back(x); } for (i = 0; i < m; i++) { cin >> l >> r >> x; long long c = 0; if (x < l || x > r) { cout << Yes n ; continue; } for (j = l - 1; j < r; j++) { if (v[j] < v[x - 1]) { c++; } } if (c == (x - l)) { cout << Yes n ; } else { cout << No n ; } } }
|
#include <bits/stdc++.h> using namespace std; const int p = 1000 * 1000 * 1000 + 7; int main() { int n, m; vector<long long> fact(1000001); fact[0] = 1; for (int i = 1; i < 1000001; i++) fact[i] = (i * fact[i - 1]) % p; cin >> n >> m; vector<pair<int, int>> v(m); for (int i = 0; i < n; i++) { int k; cin >> k; for (int j = 0; j < k; j++) { int l; cin >> l; l--; v[l].first *= p; v[l].first += i + 1; v[l].second *= 2348621; v[l].second += i + 1; } } map<pair<int, int>, int> f; for (int i = 0; i < m; i++) f[v[i]]++; long long ans = 1; for (map<pair<int, int>, int>::iterator a = f.begin(); a != f.end(); a++) ans = (fact[(*a).second] * ans) % p; cout << ans; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__AND2_BEHAVIORAL_PP_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> int a[500005][9] = {0}; int nnf[500005] = {0}; int pn[200005] = {0}; int val[200005]; int x, in; void print(int *a, int n) { int i; for (i = 0; i < n; i++) printf( %d , a[i]); printf( n ); } long long int check(int cnt, int val, int d) { if (in == -1) nnf[val] += in; long long int q = d * nnf[val], i; for (i = cnt + 1; i <= a[x][0]; i++) q += check(i, val * a[x][i], -d); if (in == 1) nnf[val] += in; return q; } int main() { a[1][0] = 1; a[1][1] = 1; int i, j; for (i = 1; i < 500001; i++) { if (a[i][0] == 1) { for (j = i; j < 500001; j += i) { a[j][0] += 1; a[j][a[j][0]] = i; } } } a[1][0] = 1; int n, q; long long int ans = 0; scanf( %d %d , &n, &q); for (i = 1; i <= n; i++) scanf( %d , &val[i]); for (i = 0; i < q; i++) { scanf( %d , &j); if (pn[j] == 1) in = -1; else in = 1; pn[j] = pn[j] ^ 1; x = val[j]; ans += check(1, 1, in); printf( %lld n , ans); } return 0; }
|
//#############################################################################
//# Purpose: A DMA ENGINE #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see below) #
//#############################################################################
module edma #( parameter AW = 32, // address width
parameter PW = 104 // packet width
)
(
// power
input vdd, // supply
input vss, // common ground
// reset, clk, config
input clk, // main core clock
input nreset, // async active low reset
output irq, // interrupt output
// datapath interface
input access_in, // streaming input access
input [PW-1:0] packet_in, // streaming input data
output wait_out, // pushback
output access_out, // output access (master/slave)
output [PW-1:0] packet_out, // output packet (with address)
input wait_in, // pushback
// config/fetch interface
input reg_access_in, // config register access
input [PW-1:0] reg_packet_in, // config register packet
output reg_wait_out, // pushback by register read
output reg_access_out,// config readback
output [PW-1:0] reg_packet_out,// config reacback packet
input reg_wait_in // pushback for readback
);
//###############
//# LOCAL WIRES
//###############
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire chainmode; // From edma_regs of edma_regs.v
wire [31:0] count; // From edma_dp of edma_dp.v
wire [31:0] count_reg; // From edma_regs of edma_regs.v
wire [4:0] ctrlmode; // From edma_regs of edma_regs.v
wire [15:0] curr_descr; // From edma_regs of edma_regs.v
wire [1:0] datamode; // From edma_regs of edma_regs.v
wire dma_en; // From edma_regs of edma_regs.v
wire [3:0] dma_state; // From edma_ctrl of edma_ctrl.v
wire [AW-1:0] dstaddr; // From edma_dp of edma_dp.v
wire [63:0] dstaddr_reg; // From edma_regs of edma_regs.v
wire fetch_access; // From edma_ctrl of edma_ctrl.v
wire [PW-1:0] fetch_packet; // From edma_ctrl of edma_ctrl.v
wire manualmode; // From edma_regs of edma_regs.v
wire master_active; // From edma_ctrl of edma_ctrl.v
wire mastermode; // From edma_regs of edma_regs.v
wire [15:0] next_descr; // From edma_regs of edma_regs.v
wire [AW-1:0] srcaddr; // From edma_dp of edma_dp.v
wire [63:0] srcaddr_reg; // From edma_regs of edma_regs.v
wire [31:0] stride_reg; // From edma_regs of edma_regs.v
wire update; // From edma_ctrl of edma_ctrl.v
wire update2d; // From edma_ctrl of edma_ctrl.v
// End of automatics
//##########################
//# DATAPATH
//##########################
edma_dp #(.AW(AW),
.PW(PW))
edma_dp(/*AUTOINST*/
// Outputs
.count (count[31:0]),
.srcaddr (srcaddr[AW-1:0]),
.dstaddr (dstaddr[AW-1:0]),
.wait_out (wait_out),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
// Inputs
.clk (clk),
.nreset (nreset),
.master_active (master_active),
.update2d (update2d),
.datamode (datamode[1:0]),
.ctrlmode (ctrlmode[4:0]),
.stride_reg (stride_reg[31:0]),
.count_reg (count_reg[31:0]),
.srcaddr_reg (srcaddr_reg[AW-1:0]),
.dstaddr_reg (dstaddr_reg[AW-1:0]),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.wait_in (wait_in));
//##########################
//# CONFIG REGISTERS
//##########################
edma_regs #(.AW(AW),
.PW(PW))
edma_regs (/*AUTOINST*/
// Outputs
.reg_wait_out (reg_wait_out),
.reg_access_out (reg_access_out),
.reg_packet_out (reg_packet_out[PW-1:0]),
.dma_en (dma_en),
.mastermode (mastermode),
.manualmode (manualmode),
.datamode (datamode[1:0]),
.ctrlmode (ctrlmode[4:0]),
.chainmode (chainmode),
.irq (irq),
.next_descr (next_descr[15:0]),
.curr_descr (curr_descr[15:0]),
.stride_reg (stride_reg[31:0]),
.count_reg (count_reg[31:0]),
.dstaddr_reg (dstaddr_reg[63:0]),
.srcaddr_reg (srcaddr_reg[63:0]),
// Inputs
.clk (clk),
.nreset (nreset),
.reg_access_in (reg_access_in),
.reg_packet_in (reg_packet_in[PW-1:0]),
.reg_wait_in (reg_wait_in),
.fetch_access (fetch_access),
.fetch_packet (fetch_packet[PW-1:0]),
.count (count[31:0]),
.dstaddr (dstaddr[AW-1:0]),
.srcaddr (srcaddr[AW-1:0]),
.dma_state (dma_state[3:0]),
.update (update));
//##########################
//# STATE MACHINE
//##########################
edma_ctrl #(.AW(AW),
.PW(PW))
edma_ctrl (/*AUTOINST*/
// Outputs
.fetch_access (fetch_access),
.fetch_packet (fetch_packet[PW-1:0]),
.dma_state (dma_state[3:0]),
.update (update),
.update2d (update2d),
.master_active (master_active),
// Inputs
.clk (clk),
.nreset (nreset),
.dma_en (dma_en),
.chainmode (chainmode),
.manualmode (manualmode),
.mastermode (mastermode),
.count (count[31:0]),
.curr_descr (curr_descr[15:0]),
.next_descr (next_descr[15:0]),
.reg_wait_in (reg_wait_in),
.access_in (access_in),
.wait_in (wait_in));
endmodule // edma
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../common/hdl")
// End:
///////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software") //
// to deal in the Software without restriction, including without limitation //
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
///////////////////////////////////////////////////////////////////////////////
|
module top(
clk,
rst_n,
sda,
speed_control,
scl,
MotorPWM,
MotorA,
MotorB,
ServoPPM,
key1,
clkOut,
uart_tx,
uart_rx,
dataLED,
newControlDataW,
accXdata,
angle_control,
testICC
);
input clk, rst_n, key1;
inout sda;
input[15:0]speed_control;
output scl, MotorPWM, MotorA, MotorB, ServoPPM, clkOut;
input uart_rx;
output uart_tx;
output reg [7:0] dataLED;
output wire newControlDataW,testICC;
output wire[15:0]accXdata;
input[15:0]angle_control;
// assign dataLED = recevData;
reg MotorA;
reg MotorB;
reg [15:0] servoDuty;
wire clk_1MHz;
ClockDIV #(.N(50)) DIV1MHz (
.clk_in(clk),
.clk_out(clk_1MHz),
.rst_n(rst_n)
);
wire clk_1KHz;
ClockDIV #(.N(50000)) DIV1kHz(
.clk_in(clk),
.clk_out(clk_1KHz),
.rst_n(rst_n)
);
assign clkOut = clk_1MHz;
reg [15:0] MotorDuty;
//DC Motor
PWM Motor1(
.clk(clk),
.rst_n(rst_n),
.pwmOut(MotorPWM),
.period(16'd5000),
.duty(MotorDuty)
);
//servo
PWM Servo(
.clk(clk_1MHz),
.rst_n(rst_n),
.pwmOut(ServoPPM),
.period(16'd20000),//period 20ms
.duty(servoDuty)//range is 500~2500, unit is us
);
I2C u1(.clk(clk),.scl(scl),.sda(sda),.rst_n(rst_n),.LED(testICC),.accXdata(accXdata));
reg sendTrigger;
wire recevNotify;
wire [7:0] recevData;
//serial port
async_receiver #(.ClkFrequency(50000000),.Baud(9600)) (.clk(clk), .RxD(uart_rx), .RxD_data_ready(recevNotify), .RxD_data(recevData));
reg [3:0] dataAssemablingState;
reg [15:0] steer, throttle;
reg newControlData;
reg controlMode;
assign newControlDataW = controlMode;
always @ (posedge recevNotify or negedge rst_n) begin
if(!rst_n) begin
dataAssemablingState <= 0;
controlMode <= 1;
end
else begin
dataLED <= recevData;
if(recevNotify) begin
case(dataAssemablingState)
4'd0:begin dataAssemablingState <= (recevData=="a")?3'd1:3'd0; end
4'd1:begin dataAssemablingState <= (recevData=="b")?3'd2:3'd0; end
4'd2:begin
if(recevData=="c") begin dataAssemablingState <= 3'd3; newControlData <= 1'b0; end
else if(recevData=="m") begin dataAssemablingState <= 4'd8; end
else dataAssemablingState <= 3'd0;
end
4'd3: begin steer[15:8] <= recevData; dataAssemablingState <= 3'd4; end
4'd4: begin steer[7:0] <= recevData; dataAssemablingState <= 3'd5; end
4'd5: begin throttle[15:8] <= recevData; dataAssemablingState <= 3'd6; end
4'd6: begin throttle[7:0] <= recevData; dataAssemablingState <= 3'd7; end
4'd7: begin newControlData <= 1'b1; dataAssemablingState <= 3'd0; end
4'd8: begin controlMode <= recevData[0]; dataAssemablingState <= 3'd0; end
default: begin dataAssemablingState <= 3'd0; end
endcase
end
end
end
always @ (posedge newControlData or posedge clk or negedge rst_n) begin
if(!rst_n) begin
servoDuty <= 16'd1500;
MotorDuty <= 0;
end
else begin
if(newControlData) begin
if(controlMode) begin
if(throttle > 512) begin
MotorA <= 1'b1;
MotorB <= 1'b0;
MotorDuty <= {(throttle[12:0] - 13'd512),3'd0};
end
else begin
MotorA <= 1'b0;
MotorB <= 1'b1;
MotorDuty <= {(13'd512 - throttle[12:0]),3'd0};
end
servoDuty <= steer + 16'd1000;
end
end
else begin
if(!controlMode) begin
MotorDuty <= speed_control;
servoDuty <= angle_control;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; while (cin >> a >> b >> c) { if (b >= c) { b = c - 1; } else { c = b + 1; } if (a >= b) { a = b - 1; cout << a + b + c << endl; } else { b = a + 1; c = a + 2; cout << a + b + c << endl; } } }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8) or oddr(x2) output module
`timescale 1ps/1ps
module ad_serdes_out (
// reset and clocks
rst,
clk,
div_clk,
// data interface
data_s0,
data_s1,
data_s2,
data_s3,
data_s4,
data_s5,
data_s6,
data_s7,
data_out_p,
data_out_n);
// parameters
parameter DEVICE_TYPE = 0;
parameter SERDES_OR_DDR_N = 1;
parameter DATA_WIDTH = 16;
localparam DEVICE_6SERIES = 1;
localparam DEVICE_7SERIES = 0;
localparam DW = DATA_WIDTH - 1;
// reset and clocks
input rst;
input clk;
input div_clk;
// data interface
input [DW:0] data_s0;
input [DW:0] data_s1;
input [DW:0] data_s2;
input [DW:0] data_s3;
input [DW:0] data_s4;
input [DW:0] data_s5;
input [DW:0] data_s6;
input [DW:0] data_s7;
output [DW:0] data_out_p;
output [DW:0] data_out_n;
// internal signals
wire [DW:0] data_out_s;
wire [DW:0] serdes_shift1_s;
wire [DW:0] serdes_shift2_s;
// instantiations
genvar l_inst;
generate
for (l_inst = 0; l_inst <= DW; l_inst = l_inst + 1) begin: g_data
if (SERDES_OR_DDR_N == 0) begin
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr (
.S (1'b0),
.CE (1'b1),
.R (rst),
.C (clk),
.D1 (data_s0[l_inst]),
.D2 (data_s1[l_inst]),
.Q (data_out_s[l_inst]));
end
if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_7SERIES)) begin
OSERDESE2 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (8),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_serdes (
.D1 (data_s0[l_inst]),
.D2 (data_s1[l_inst]),
.D3 (data_s2[l_inst]),
.D4 (data_s3[l_inst]),
.D5 (data_s4[l_inst]),
.D6 (data_s5[l_inst]),
.D7 (data_s6[l_inst]),
.D8 (data_s7[l_inst]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (clk),
.CLKDIV (div_clk),
.OQ (data_out_s[l_inst]),
.TQ (),
.OFB (),
.TFB (),
.TBYTEIN (1'b0),
.TBYTEOUT (),
.TCE (1'b0),
.RST (rst));
end
if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_6SERIES)) begin
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (8),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_serdes_m (
.D1 (data_s0[l_inst]),
.D2 (data_s1[l_inst]),
.D3 (data_s2[l_inst]),
.D4 (data_s3[l_inst]),
.D5 (data_s4[l_inst]),
.D6 (data_s5[l_inst]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (serdes_shift1_s[l_inst]),
.SHIFTIN2 (serdes_shift2_s[l_inst]),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (clk),
.CLKDIV (div_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (data_out_s[l_inst]),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (rst));
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (8),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("SLAVE"))
i_serdes_s (
.D1 (1'b0),
.D2 (1'b0),
.D3 (data_s6[l_inst]),
.D4 (data_s7[l_inst]),
.D5 (1'b0),
.D6 (1'b0),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (serdes_shift1_s[l_inst]),
.SHIFTOUT2 (serdes_shift2_s[l_inst]),
.OCE (1'b1),
.CLK (clk),
.CLKDIV (div_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (rst));
end
OBUFDS i_obuf (
.I (data_out_s[l_inst]),
.O (data_out_p[l_inst]),
.OB (data_out_n[l_inst]));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
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#include <bits/stdc++.h> using namespace std; const long long N = 112, INF = 1e18; long long t, n, m, a[N]; long long B10(string s) { reverse(s.begin(), s.end()); long long ret = 0; for (long long i = 0; i < s.size(); i++) { if (s[i] == 1 ) ret += (1ll << i); } return ret; } string B2(long long a) { string ret; for (long long i = 0; i < m; i++) { if (a & (1ll << i)) ret += 1 ; else ret += 0 ; } reverse(ret.begin(), ret.end()); return ret; } long long BS() { long long low = 0, high = (1ll << m); while (high - low > 1) { long long mid = (low + high) >> 1; long long v1 = mid - (lower_bound(a, a + n, mid) - a); long long v2 = ((1ll << m) - n - 1) / 2; if (v1 <= v2) low = mid; else high = mid; } return low; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> t; while (t--) { cin >> n >> m; for (long long i = 0; i < n; i++) { string s; cin >> s; a[i] = B10(s); } sort(a, a + n); cout << B2(BS()) << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int a[755]; long long dp[755][755]; int n, m; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) cin >> a[i]; dp[n + 1][0] = 0; for (int i = n; i >= 1; i--) { for (int j = 0; j <= n; j++) { dp[i][j] = min(dp[i + 1][j] + a[i], (long long)0); if (j > 0) dp[i][j] = max(dp[i][j], dp[i + 1][j - 1]); } } while (m--) { long long x; cin >> x; cout << lower_bound(dp[1], dp[1] + n + 1, -x) - dp[1] << endl; } return 0; }
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//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate continuous >> in assignment..dependent on always >> working
//
module main;
reg globvar;
reg [3:0] var1,var2,var3;
wire [3:0] var3a;
reg error;
assign var3a = var1 >> var2;
always @( var1 or var2)
var3 = var1 >> var2 ;
initial
begin
error =0;
for ( var1 = 4'b0; var1 != 4'hf; var1 = var1 + 1)
for ( var2 = 4'b0; var2 != 4'hf; var2 = var2 + 1)
begin
#1 ;
if(var3 != var3a)
begin
$display("FAILED continuous >> 1=%h,2=%h,3=%h,3a=%h",
var1,var2,var3,var3a);
error = 1;
end
#1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
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`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// A synchronization module for resets. Output resets are held for
// RSTDELAY+1 cycles, RSTDELAY >= 0. Reset assertion is asynchronous,
// while deassertion is synchronized to the clock.
module SyncResetA (
IN_RST,
CLK,
OUT_RST
);
parameter RSTDELAY = 1 ; // Width of reset shift reg
input CLK ;
input IN_RST ;
output OUT_RST ;
reg [RSTDELAY:0] reset_hold ;
wire [RSTDELAY+1:0] next_reset = {reset_hold, ~ `BSV_RESET_VALUE} ;
assign OUT_RST = reset_hold[RSTDELAY] ;
always @( posedge CLK or `BSV_RESET_EDGE IN_RST )
begin
if (IN_RST == `BSV_RESET_VALUE)
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY {RSTDELAY+1 {`BSV_RESET_VALUE}} ;
end
else
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:0];
end
end // always @ ( posedge CLK or `BSV_RESET_EDGE IN_RST )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
#0 ;
// initialize out of reset forcing the designer to do one
reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // SyncResetA
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; struct edge { public: int flow, cap, cost; int u, v; edge(int _u, int _v, int _flow, int _cost, int _cap) { u = _u; v = _v; flow = _flow; cost = _cost; cap = _cap; } edge() {} } E[10000]; vector<int> V[10000]; int say[100], src, dest; int phi[10000]; int B[10000], par[10000], D[10000]; bool dijkstra() { memset(B, 0, sizeof(B)); for (int i = 1; i <= dest; i++) D[i] = 1000000000; D[0] = 0; par[0] = -1; D[dest + 1] = 1000000000; for (int it = 0; it <= dest; it++) { int v = dest + 1; for (int i = 0; i <= dest; i++) if (D[i] < D[v] && (!B[i])) v = i; B[v] = 1; if (v == dest + 1) break; for (int j = 0; j < V[v].size(); j++) { int idx = V[v][j]; if (E[idx].u == v) { if (E[idx].flow < E[idx].cap) { int nv = E[idx].v; assert(D[v] + (phi[v] - phi[nv] + E[idx].cost) >= 0); if ((!B[nv]) && D[nv] > D[v] + (phi[v] - phi[nv] + E[idx].cost)) { D[nv] = D[v] + (phi[v] - phi[nv] + E[idx].cost); par[nv] = idx; } } } else { if (E[idx].flow > 0) { int nv = E[idx].u; assert(D[v] + (phi[v] - phi[nv] - E[idx].cost) >= 0); if ((!B[nv]) && D[nv] > D[v] + (phi[v] - phi[nv] - E[idx].cost)) { D[nv] = D[v] + (phi[v] - phi[nv] - E[idx].cost); par[nv] = idx; } } } } } for (int i = 0; i <= dest; i++) if (B[i]) phi[i] += D[i]; return B[dest]; } void augment() { int cur = dest, aug = 1000000000; while (par[cur] >= 0) { int idx = par[cur]; if (E[idx].v == cur) { aug = min(aug, E[idx].cap - E[idx].flow); cur = E[idx].u; } else { aug = min(aug, E[idx].flow); cur = E[idx].v; } } cur = dest; while (par[cur] >= 0) { int idx = par[cur]; if (E[idx].v == cur) { E[idx].flow += aug; cur = E[idx].u; } else { E[idx].flow -= aug; cur = E[idx].v; } } } int main() { string t, s; int n, a; cin >> t >> n; src = 0; dest = n + n * 26 + 27; int cv = n + 1, ce = 0; for (int i = 1; i <= n; i++) { cin >> s >> a; memset(say, 0, sizeof(say)); int len = s.length(); for (int j = 0; j < len; j++) say[s[j] - a ]++; for (int j = 0; j < 26; j++) { E[ce] = edge(i, cv, 0, 0, say[j]); V[i].push_back(ce); V[cv].push_back(ce); ce++; E[ce] = edge(cv, n + n * 26 + j + 1, 0, 0, 1000000000); V[cv].push_back(ce); V[n + n * 26 + j + 1].push_back(ce); ce++; cv++; } E[ce] = edge(0, i, 0, i, a); V[0].push_back(ce); V[i].push_back(ce); ce++; } memset(say, 0, sizeof(say)); int len = t.length(); for (int i = 0; i < len; i++) say[t[i] - a ]++; for (int i = 1; i <= 26; i++) { E[ce] = edge(n + n * 26 + i, dest, 0, 0, say[i - 1]); V[n + n * 26 + i].push_back(ce); V[dest].push_back(ce); ce++; } while (dijkstra()) { augment(); } int can = 1; for (int i = 0; i < V[dest].size(); i++) { int idx = V[dest][i]; if (E[idx].flow != E[idx].cap) can = 0; } if (!can) { cout << -1 << endl; return 0; } int ans = 0; for (int i = 0; i < V[0].size(); i++) { int idx = V[0][i]; ans += E[idx].cost * E[idx].flow; } cout << ans << endl; return 0; }
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/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test was inspired by PR#539. We check that the calculated bit
* select of a net in a continuous assignment gets bits in the right
* order and position. The trick here is that the bits are numbered
* from MSB to LSB.
*/
module main;
reg [0:63] target0 = 64'h0040200000000000;
reg [1:64] target1 = 64'h0040200000000000;
reg [6:0] idx;
wire mux0 = target0[idx];
wire mux1 = target1[idx+1];
initial begin
$display( "Using constant indices:" );
$display( " %b=v[ 9]", target0[ 9] );
if (target0[9] !== 1'b1) begin
$display("FAILED -- target0[9] != 1");
$finish;
end
$display( " %b=v[18]", target0[18] );
if (target0[18] !== 1'b1) begin
$display("FAILED -- target0[18] != 1");
$finish;
end
$display( " %b=v[45]", target0[45] );
if (target0[45] !== 1'b0) begin
$display("FAILED -- target0[45] != 0");
$finish;
end
$display( " %b=v[54]", target0[54] );
if (target0[54] !== 1'b0) begin
$display("FAILED -- target0[54] != 0");
$finish;
end
$display( "Using calcuated indices:" );
for (idx = 0 ; idx < 64 ; idx = idx + 1) begin
#1 $display("target0[%2d]=%b, mux0=%b", idx, target0[idx], mux0);
$display("target1[%2d]=%b, mux1=%b", idx+1, target1[idx+1], mux1);
if (target0[idx] !== mux0) begin
$display("FAILED -- target0[idx] != mux0");
$finish;
end
if (target1[idx+1] !== mux1) begin
$display("FAILED -- target1[idx+1] != mux1");
$finish;
end
end
$display("PASSED");
end
endmodule // main
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#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 100; struct node { int flag, a, b; long long sum; } t[maxn * 8]; int a[maxn], cnt[maxn * 2], js[maxn * 2]; void pushdown(int x, int l, int r) { if (t[x].flag) { int num = t[x].flag; t[2 * x].sum += num * l; t[2 * x + 1].sum += num * r; t[2 * x].flag += num; t[2 * x + 1].flag += num; t[x].flag = 0; } } int ask(int x, int l, int r, int pos) { int mid; if (l == r) { return t[x].sum; } mid = (l + r) / 2; pushdown(x, mid - l + 1, r - mid); if (pos <= mid) return ask(2 * x, l, mid, pos); else return ask(2 * x + 1, mid + 1, r, pos); } void add(int x, int l, int r, int ql, int qr, int val) { int mid; if (ql == l && qr == r) { t[x].flag += val; t[x].sum += (qr - ql + 1); return; } mid = (l + r) / 2; pushdown(x, mid - l + 1, r - mid); if (qr <= mid) { add(2 * x, l, mid, ql, qr, val); } else { if (ql > mid) add(2 * x + 1, mid + 1, r, ql, qr, val); else { add(2 * x, l, mid, ql, mid, val); add(2 * x + 1, mid + 1, r, mid + 1, qr, val); } } t[x].sum = t[2 * x].sum + t[2 * x + 1].sum; } void build(int x, int l, int r) { int mid; t[x].flag = 0; t[x].sum = 0; if (l == r) { return; } mid = (l + r) / 2; build(2 * x, l, mid); build(2 * x + 1, mid + 1, r); } int top; node s[maxn]; int cmp(node a, node b) { return a.sum < b.sum; } int main() { node e; int T, n, flag, ans, k, up; scanf( %d , &T); while (T--) { scanf( %d%d , &n, &k); for (int i = 1; i <= 2 * k; i++) { cnt[i] = 0; js[i] = 0; } build(1, 1, k * 2); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } if (n == 2) { printf( 0 n ); continue; } top = 0; if (n % 2) up = n / 2 + 1; else up = n / 2; for (int i = 1; i <= up; i++) { e.a = a[i]; e.b = a[n - i + 1]; if (e.a > e.b) swap(e.a, e.b); e.sum = e.a + e.b; s[++top] = e; js[e.sum]++; } sort(s + 1, s + top + 1, cmp); int last = 0; ans = n; for (int i = 1; i <= top; i++) { e = s[i]; if (e.sum == last) { add(1, 1, 2 * k, e.a + 1, e.b + k, 1); continue; } cnt[e.sum] += n / 2 - js[e.sum] + i - 1 - ask(1, 1, 2 * k, e.sum); add(1, 1, 2 * k, e.a + 1, e.b + k, 1); last = e.sum; } for (int i = 1; i <= top / 2; i++) { swap(s[i], s[top - i + 1]); } build(1, 1, k * 2); last = 0; ans = n; for (int i = 1; i <= top; i++) { e = s[i]; if (e.sum == last) { add(1, 1, 2 * k, e.a + 1, e.b + k, 1); continue; } cnt[e.sum] += i - 1 - ask(1, 1, 2 * k, e.sum); ans = min(ans, cnt[e.sum]); add(1, 1, 2 * k, e.a + 1, e.b + k, 1); last = e.sum; } for (int i = 1; i <= 2 * k; i++) { if (js[i]) continue; ans = min(ans, n - ask(1, 1, 2 * k, i)); } printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; pair<int, int> cnt(string s) { int bal = 0, minBal = 0; for (char c : s) { if (c == ( ) bal++; else bal--; minBal = min(minBal, bal); } return {bal, minBal}; } int k[400400]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<int> bal(n), minBal(n); for (int i = 0; i < n; i++) { string s; cin >> s; auto p = cnt(s); bal[i] = p.first; minBal[i] = p.second; if (bal[i] >= 0 && minBal[i] >= 0) k[bal[i]]++; } long long ans = 0; for (int i = 0; i < n; i++) { if (bal[i] > 0) continue; if (minBal[i] - bal[i] >= 0) ans += (long long)k[-bal[i]]; } cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> p(n / 2); for (int i = 0; i < n / 2; i++) { cin >> p[i]; } sort(p.begin(), p.end()); int sum1 = 0, sum2 = 0; for (int i = 0; i < n / 2; i++) { sum1 += abs(p[i] - i * 2 - 1); sum2 += abs(p[i] - i * 2 - 2); } cout << min(sum1, sum2) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, x, y, z, k, w, a, b, res, dist; vector<int> edge[200005], new_edge[200005]; int deg[200005], depth[200005], far[200005], far_dist[200005]; pair<int, int> dp[200005]; bool has_crit_point[200005]; void DFS(int x, int y, int pre) { if (y == 0) depth[x] = 0; else depth[x] = depth[y] + 1; int nxt_pre = pre; if (deg[x] >= 3) { has_crit_point[x] = 1; nxt_pre = x; if (pre != 0) { new_edge[pre].push_back(x); new_edge[x].push_back(pre); } } for (int i : edge[x]) if (i != y) DFS(i, x, nxt_pre), has_crit_point[x] |= has_crit_point[i]; if (!has_crit_point[x]) dp[x].first = x; for (int i : edge[x]) if (!has_crit_point[i]) { if (dp[x].first == 0 || depth[dp[i].first] >= depth[dp[x].first]) dp[x].second = dp[x].first, dp[x].first = dp[i].first; else if (dp[x].second == 0 || depth[dp[i].first] > depth[dp[x].second]) dp[x].second = dp[i].first; } } void solve(int x, int y) { for (int i : new_edge[x]) if (i != y) solve(i, x); int p = -1, q = -1, distp = 0, distq = 0; if (dp[x].second > 0) { far[x] = x; far_dist[x] = depth[dp[x].first] + depth[dp[x].second] - 2 * depth[x]; } for (int i : new_edge[x]) { int v = i; int distv = depth[dp[far[v]].first] + depth[dp[far[v]].second] - depth[far[v]] * 2; if (p == -1 || depth[far[v]] > depth[p]) q = p, distq = distp, p = far[v], distp = distv; else if (depth[far[v]] == depth[p] && distv > distp) q = p, distq = distp, p = far[v], distp = distv; else if (q == -1 || depth[far[v]] > depth[q]) distq = distv, q = far[v]; else if (depth[far[v]] == depth[q] && distv > distq) distq = distv, q = far[v]; if (depth[far[v]] > depth[far[x]]) far[x] = far[v], far_dist[x] = far_dist[v]; else if (depth[far[v]] == depth[far[x]] && far_dist[v] > far_dist[x]) far[x] = far[v], far_dist[x] = far_dist[v]; } if (dp[x].second > 0 && q == -1) q = x, distq = depth[dp[x].first] + depth[dp[x].second] - 2 * depth[x]; if (p == -1 || q == -1) return; if (depth[p] + depth[q] - 2 * depth[x] > res) { res = depth[p] + depth[q] - 2 * depth[x]; dist = distp + distq; a = p, b = q; } else if (depth[p] + depth[q] - 2 * depth[x] == res && distp + distq > dist) { dist = distp + distq; a = p, b = q; } } int main() { scanf( %d , &n); for (int i = (0); i < (n - 1); i++) scanf( %d %d , &x, &y), edge[x].push_back(y), edge[y].push_back(x), deg[x]++, deg[y]++; for (int i = (1); i <= (n); i++) if (deg[i] >= 3) x = i; DFS(x, 0, 0); a = b = -1; res = dist = 0; solve(x, 0); printf( %d %d n%d %d n , dp[a].first, dp[b].first, dp[a].second, dp[b].second); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, flag, ln, prv = -1; char in[100010][20], pr[100010][20]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %s , in[i]); ln = strlen(in[i]); flag = 0; if (ln < prv) { printf( NO n ); return 0; } else if (i == 0 || ln > prv) { for (int j = 0; j < ln; j++) { if (j == 0 && in[i][j] == ? ) pr[i][j] = 1 ; else if (in[i][j] == ? ) pr[i][j] = 0 ; else pr[i][j] = in[i][j]; } } else { for (int j = 0; j < ln; j++) { if (in[i][j] == ? ) { if (flag == 0) pr[i][j] = pr[i - 1][j]; else pr[i][j] = 0 ; } else if (in[i][j] > pr[i - 1][j]) { pr[i][j] = in[i][j]; flag = 1; } else if (in[i][j] < pr[i - 1][j] && flag == 0) { for (int x = j - 1; x >= 0; x--) { if (in[i][x] == ? && pr[i][x] < 9 ) { pr[i][x]++; for (int z = x + 1; z < j; z++) if (in[i][z] == ? ) pr[i][z] = 0 ; flag = 1; break; } } if (flag == 0) { printf( NO n ); return 0; } pr[i][j] = in[i][j]; } else pr[i][j] = in[i][j]; } if (flag == 0) { for (int j = ln - 1; j >= 0; j--) { if (in[i][j] == ? && pr[i][j] < 9 ) { pr[i][j]++; for (int z = j + 1; z < ln; z++) if (in[i][z] == ? ) pr[i][z] = 0 ; flag = 1; break; } } if (flag == 0) { printf( NO n ); return 0; } } } prv = ln; } printf( YES n ); for (int i = 0; i < n; i++) printf( %s n , pr[i]); return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( avx2 ) using namespace std; const long long MAX = -1000000000000000000; const long long MIN = 1000000000000000000; const long long inf = 1000000000; const long long KOK = 100000; const long long LOG = 30; const long long li = 500005; const long long mod = 1000000007; int n, m, b[li], a[li], k, flag, t, fa[li], si[li], vis[li], visit[li], x[li], y[li], use[li]; int cev; queue<int> q; set<pair<long long, long long> > st; string s; vector<int> v[li], vec; inline int dsu(int x) { if (x == fa[x]) return x; return fa[x] = dsu(fa[x]); } int main(void) { scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = 1; i <= k; i++) { scanf( %d %d , &x[i], &y[i]); use[x[i]]++; use[y[i]]++; v[x[i]].push_back(i); v[y[i]].push_back(i); } for (int i = 1; i <= k; i++) { if (use[x[i]] <= a[x[i]] || use[y[i]] <= a[y[i]]) q.push(i); } while (q.size()) { int node = q.front(); q.pop(); if (vis[node]) continue; vis[node] = 1; vec.push_back(node); use[x[node]]--; use[y[node]]--; int nodee = node; node = x[node]; for (int i = 0; i < (int)v[node].size(); i++) { if ((use[x[v[node][i]]] <= a[x[v[node][i]]] || use[y[v[node][i]]] <= a[y[v[node][i]]]) && vis[v[node][i]] == 0) q.push(v[node][i]); } node = y[nodee]; for (int i = 0; i < (int)v[node].size(); i++) { if ((use[x[v[node][i]]] <= a[x[v[node][i]]] || use[y[v[node][i]]] <= a[y[v[node][i]]]) && vis[v[node][i]] == 0) q.push(v[node][i]); } } if ((int)vec.size() != k) { printf( DEAD n ); return 0; } printf( ALIVE n ); reverse(vec.begin(), vec.end()); for (int i = 0; i < (int)vec.size(); i++) { printf( %d , vec[i]); } return 0; }
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#include <bits/stdc++.h> using namespace std; void file_put() { freopen( filename.in , r , stdin); freopen( filename.out , w , stdout); } long long Pow(long long x, long long k, long long _p) { long long ans = 1; for (; k; k >>= 1, x = x * x % _p) if (k & 1) (ans *= x) %= _p; return ans; } const int N = 100005, _p = 998244353; const int _M = N, _N = N; template <class V> struct FT { vector<V> aa, bb; V w[2][_M * 2 + 5], rev[_M * 2 + 5], tmp; void FFT(vector<V> &A, int m, int op) { int N = 1 << m; V w0 = Pow(3, (_p - 1) / N, _p); w[0][0] = w[1][0] = 1; for (int i = (1); i < (N); i++) w[0][i] = w[1][N - i] = (long long)w[0][i - 1] * w0 % _p; for (int i = (1); i < (N); i++) rev[i] = (rev[i >> 1] >> 1) | (i & 1) << m - 1; for (int i = (0); i < (N); i++) if (i < rev[i]) swap(A[i], A[rev[i]]); for (int i = 1; i < N; i <<= 1) for (int j = 0, t = N / (i << 1); j < N; j += i << 1) for (int k = j, l = 0; k < j + i; k++, l += t) { V x = A[k], y = (long long)w[op][l] * A[k + i] % _p; A[k] = (x + y) % _p, A[k + i] = (x - y + _p) % _p; } if (op) { tmp = Pow(N, _p - 2, _p); for (int i = (0); i < (N); i++) A[i] = 1ll * A[i] * tmp % _p; } } vector<V> multiply(vector<V> A, vector<V> B, vector<V> *C = NULL, int op = 0) { int lena = A.size(), lenb = B.size(), len = 1, L = 0; aa = A, bb = B; while (len < lena + lenb - 1) len <<= 1, ++L; aa.resize(len), bb.resize(len); if (op) reverse((bb).begin(), (bb).end()); FFT(aa, L, 0), FFT(bb, L, 0); if (!C) C = &A; (*C).resize(len); for (int i = (0); i < (len); i++) (*C)[i] = (long long)aa[i] * bb[i] % _p; FFT(*C, L, 1); if (op) reverse((*C).begin(), (*C).end()); (*C).resize(lena + lenb - 1); return *C; } }; int n, k, x, y, siz[N]; vector<int> V[N], P[N]; long long ans = 0, s = 0, fac[N], inv[N], dp[N]; FT<int> T; vector<int> solve(int l, int r, const vector<int> &a) { if (l == r) return vector<int>{1, a[l]}; int mid = l + r >> 1; return T.multiply(solve(l, mid, a), solve(mid + 1, r, a)); } void dfs(int x, int p) { siz[x] = 1; for (auto y : V[x]) { if (y == p) continue; dfs(y, x), siz[x] += siz[y], P[x].push_back(siz[y]); } if (P[x].empty()) P[x].push_back(1); else P[x] = solve(0, (int)P[x].size() - 1, P[x]); for (int i = (0); i < (min(k, (int)P[x].size() - 1) + 1); i++) dp[x] += inv[k - i] % _p * P[x][i] % _p; dp[x] %= _p, (dp[x] *= fac[k]) %= _p; } void dfs(int x, int p, long long s1, long long s2) { ans += dp[x] * (s1 - s2) % _p, ans %= _p; P[x].push_back(0); unordered_map<int, int> M; for (int i = ((int)P[x].size()) - 1; i >= (1); i--) P[x][i] += (long long)P[x][i - 1] * (n - siz[x]) % _p, P[x][i] %= _p; for (auto y : V[x]) { if (y == p || M.find(siz[y]) != M.end()) continue; long long ret = 0; vector<int> tmp = P[x]; for (int i = (0); i < ((int)tmp.size() - 1); i++) tmp[i + 1] -= (long long)tmp[i] * siz[y] % _p, tmp[i + 1] %= _p; for (int i = (0); i < (min(k, (int)tmp.size() - 1) + 1); i++) ret += tmp[i] * fac[k] % _p * inv[k - i] % _p, ret %= _p; M[siz[y]] = ret; } for (auto y : V[x]) { if (y == p) continue; dfs(y, x, (s1 + M[siz[y]]) % _p, (s2 + dp[x]) % _p); } } int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); scanf( %d%d , &n, &k); for (int i = (1); i < (n); i++) scanf( %d%d , &x, &y), V[x].push_back(y), V[y].push_back(x); fac[0] = inv[0] = inv[1] = 1; for (int i = (2); i < (N); i++) inv[i] = (_p - _p / i) * inv[_p % i] % _p; for (int i = (1); i < (N); i++) inv[i] = inv[i - 1] * inv[i] % _p, fac[i] = fac[i - 1] * i % _p; if (k == 1) { cout << (long long)n * (n - 1) / 2 % _p << endl; return 0; } dfs(1, 0), dfs(1, 0, 0, 0); for (int i = (1); i < (n + 1); i++) ans += dp[i] * s % _p, s += dp[i], ans %= _p, s %= _p; cout << (ans + _p) % _p << endl; return 0; }
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_src_cols_V_channel1_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_src_cols_V_channel1 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_src_cols_V_channel1_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_src_cols_V_channel1_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
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#include <bits/stdc++.h> using namespace std; int main(int argc, char** argv) { long long n; cin >> n; long long sum = n * (n + 1) / 2; if (sum % 2 == 1) cout << 1; else cout << 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O21BA_BEHAVIORAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_BEHAVIORAL_PP_V
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#include <bits/stdc++.h> using namespace std; int num[10]; int main(void) { int T, n; scanf( %d , &T); while (T--) { memset(num, 0, sizeof(num)); scanf( %d , &n); num[1] = n / 2; if (n & 01) { printf( 7 ); for (int i = 1; i < num[1]; ++i) printf( 1 ); } else for (int i = 0; i < num[1]; ++i) printf( 1 ); if (T) printf( n ); } }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module reads data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_in_deserializer (
// Inputs
clk,
reset,
serial_data_in,
receive_data_en,
// Bidirectionals
// Outputs
fifo_read_available,
received_data_valid,
received_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input serial_data_in;
input receive_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_read_available;
output received_data_valid;
output [DW: 0] received_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_received;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
// Internal Registers
reg receiving_data;
reg [(TDW-1):0] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_read_available <= 8'h00;
else
fifo_read_available <= {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
receiving_data <= 1'b0;
else if (all_bits_received)
receiving_data <= 1'b0;
else if (serial_data_in == 1'b0)
receiving_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_in_shift_reg <= {TDW{1'b0}};
else if (shift_data_reg_en)
data_in_shift_reg <=
{serial_data_in, data_in_shift_reg[(TDW - 1):1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign received_data_valid = ~fifo_is_empty;
// Input assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_In_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~receiving_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (),
.baud_clock_falling_edge (shift_data_reg_en),
.all_bits_transmitted (all_bits_received)
);
defparam
RS232_In_Counters.CW = CW,
RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Counters.TDW = TDW;
altera_up_sync_fifo RS232_In_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (all_bits_received & ~fifo_is_full),
.write_data (data_in_shift_reg[(DW + 1):1]),
.read_en (receive_data_en & ~fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (received_data)
);
defparam
RS232_In_FIFO.DW = DW,
RS232_In_FIFO.DATA_DEPTH = 128,
RS232_In_FIFO.AW = 6;
endmodule
|
/* Concrete parameterizations of a census transform for testing.
*
* Copyright (c) 2016, Stephen Longfield, stephenlongfield.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`include "census.v"
module census_test(
input clk,
input rst,
input wire [(32*5*5-1):0] inp,
output wire [(5*5-1):0] outp
);
census#(.WIDTH(32), .WINDOW_WIDTH(5), .WINDOW_HEIGHT(5))
ct(clk, rst, inp, outp);
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int in() { int res = 0; char c; int f = 1; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) f = -1; while (c >= 0 && c <= 9 ) res = res * 10 + c - 0 , c = getchar(); return res * f; } const int N = 100010; long long num[N], rd[N]; long long ans; pair<int, int> a[N << 1]; int main() { int n = in(), m = in(); for (int i = 1; i <= n; i++) { num[i] = 1; } for (int i = 0; i < m; i++) { a[i].first = in(); a[i].second = in(); } sort(a, a + m); for (int i = 0; i < m; i++) { int x = a[i].first, y = a[i].second; if (x > y) { num[x] = max(num[x], num[y] + 1); } else { num[y] = max(num[y], num[x] + 1); } rd[x]++; rd[y]++; } for (int i = 1; i <= n; i++) { ans = max(ans, 1LL * num[i] * rd[i]); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base ::sync_with_stdio(0); cin.tie(0); ; long long int t; cin >> t; while (t--) { string s; cin >> s; long long int a[26] = {0}; long long int cnt = 0; char c; int i = 0; while (i < s.length()) { cnt = 0; c = s[i]; while (s[i] == c && i < s.length()) { cnt++; i++; } if (cnt % 2 != 0) { a[c - a ] = 1; } } string ans = ; for (i = 0; i < 26; i++) { if (a[i] == 1) { ans += (i + a ); } } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, x; scanf( %d%d , &n, &x); if (n < 2) n = 2; int ans = ((n - 2) + x - 1) / x + 1; printf( %d n , ans); } int main() { int t; scanf( %d , &t); while (t--) solve(); return 0; }
|
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ()
//
// Copyright (c) 2004 Guy Hutchison ()
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80_reg (/*AUTOARG*/
// Outputs
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
// Inputs
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
);
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output [7:0] DOAL;
output [7:0] DOCL;
input [7:0] DIL;
output [7:0] DOBL;
output [7:0] DOCH;
output [7:0] DOAH;
input clk, CEN, WEH, WEL;
reg [7:0] RegsH [0:7];
reg [7:0] RegsL [0:7];
always @(posedge clk)
begin
if (CEN)
begin
if (WEH) RegsH[AddrA] <= DIH;
if (WEL) RegsL[AddrA] <= DIL;
end
end
assign DOAH = RegsH[AddrA];
assign DOAL = RegsL[AddrA];
assign DOBH = RegsH[AddrB];
assign DOBL = RegsL[AddrB];
assign DOCH = RegsH[AddrC];
assign DOCL = RegsL[AddrC];
// break out ram bits for waveform debug
wire [7:0] H = RegsH[2];
wire [7:0] L = RegsL[2];
// synopsys dc_script_begin
// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1 2004/05/16 17:39:57 ghutchis Exp $" -type string -quiet
// synopsys dc_script_end
endmodule
|
module functionGen_tb ();
parameter ARCH = "GENERIC";
parameter BIT_COMPRESS_PHASE = 1;
parameter BIT_COMPRESS_OUTPUT = 1;
parameter OUT_WIDTH = 8;
parameter FREQ_WIDTH = 16;
parameter INCLUDE_CLAMP = 1;
reg clk;
reg rst;
reg en;
reg [1:0] waveType;
reg [FREQ_WIDTH-1:0] freq;
reg [FREQ_WIDTH-1:0] phaseOffset;
reg signed [OUT_WIDTH-1:0] offset;
reg [OUT_WIDTH-1:0] amplitude;
wire signed [OUT_WIDTH-1:0] outSignal;
integer i;
always #1 clk = ~clk;
initial begin
clk = 1'b0;
rst = 1'b1;
en = 1'b1;
waveType = 2'd0;
freq = 'd0;
phaseOffset = 'd0;
offset = 'd0;
amplitude = 'd0;
#10
rst = 1'b0;
for (i=0; i<4; i=i+1) begin
waveType = i;
freq = 1 << (FREQ_WIDTH-12);
offset = 'd0;
amplitude = ~0;
#20000
waveType = i;
end
waveType = 'd0;
offset = {2'b01, {OUT_WIDTH-2{1'b0}}}; // 1/2 max positive offset
#20000
waveType = 'd0;
offset = {1'b0, {OUT_WIDTH-1{1'b1}}}; // max positive offset
#20000
offset = {1'b1, {OUT_WIDTH-1{1'b0}}}; // max negative offset
#20000
offset = 'd0;
#20000
$stop(2);
end
functionGen #(
.ARCH(ARCH), ///< System architecture
.BIT_COMPRESS_PHASE(BIT_COMPRESS_PHASE), ///< 1 for bit compression, 0 for truncation
.BIT_COMPRESS_OUTPUT(BIT_COMPRESS_OUTPUT), ///< 1 for bit compression, 0 for truncation
.OUT_WIDTH(OUT_WIDTH), ///< Output word width
.FREQ_WIDTH(FREQ_WIDTH), ///< Input frequency word width
.INCLUDE_CLAMP(INCLUDE_CLAMP) ///< Clamp the output to prevent wraparound
)
uut (
// Inputs
.clk(clk), ///< System clock
.rst(rst), ///< Synchronous reset, active high
.en(en), ///< Output next sample when high
.waveType(waveType), ///< [1:0] Waveform type (see top description)
.freq(freq), ///< [FREQ_WIDTH-1:0] Frequency
.phaseOffset(phaseOffset), ///< [FREQ_WIDTH-1;0] Phase offset
.offset(offset), ///< [OUT_WIDTH-1:0] Offset value
.amplitude(amplitude), ///< [OUT_WIDTH-1:0] Amplitude of waveform
// Outputs
.outSignal(outSignal) ///< [OUT_WIDTH-1:0]
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; long long int n, m, k; vector<long long int> a, b; while (t--) { cin >> n >> m; cout << n << << n * 2 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; string s; cin >> s; map<char, int> m; for (int i = 0; i < s.size(); i++) { m[s[i]]++; } char a = A ; bool flag1 = true; for (int i = 1; i < k; i++) { if (m[a] == 0) { flag1 = false; break; } a++; } bool flag = false; for (int i = 0; i < s.size(); i++) { if (a == s[i]) { flag = true; break; } } int c = 999999; if (flag == true && flag1 == true) { for (auto x : m) { if (x.second < c) { c = x.second; } } cout << c * k; } else { cout << 0 ; } }
|
#include <bits/stdc++.h> using namespace std; int a[156], T, n, k, ans, lw, que[100]; int main() { int T; cin >> T; while (T--) { cin >> k; lw = 0; for (int i = 1; i <= 7; i++) { cin >> a[i]; a[i + 7] = a[i]; lw += a[i]; } int n = k / lw; if (k % lw == 0) { int maxx = 0, ll = 0; for (int i = 1; i <= 14; i++) { if (a[i] == 0) { ll++; maxx = max(maxx, ll); } else ll = 0; } ans = n * 7 - maxx; } else { int yu = k % lw, front = 0, ll = 0, minn = 1000; queue<int> q; while (!q.empty()) q.pop(); for (int i = 1; i <= 14; i++) { if (a[i] == 0) continue; if (a[i] == 1) { ll++; q.push(i); if (ll >= yu) { front = q.front(); q.pop(); minn = min(i - front + 1, minn); } } } ans = n * 7 + minn; } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll M = 1e4 + 10; const ll G = 1e3 + 10; ll n, m, g, r; vector<ll> d; ll ansDep = -1; ll ansT = -1; bool seen[M][G]; ll ans = 1e17; void bfs() { deque<tuple<ll, ll, ll> > q; q.emplace_front(0, 0, 0); while (!q.empty()) { auto at = q.front(); q.pop_front(); ll v = get<0>(at), tempo = get<1>(at), dep = get<2>(at); if (v == m - 1) { ans = min(ans, (r + g) * dep + tempo); continue; } seen[v][tempo] = true; ll distance = d[v + 1] - d[v]; ll nt = distance + tempo; if (nt <= g and !seen[v + 1][nt % g]) { seen[v + 1][nt % g] = true; if (nt == g) { if (v + 1 != m - 1) q.emplace_back(v + 1, 0, dep + 1); else q.emplace_back(v + 1, g, dep); } else q.emplace_front(v + 1, nt, dep); } if (v > 0) { distance = d[v] - d[v - 1]; nt = distance + tempo; if (nt <= g and !seen[v - 1][nt % g]) { seen[v - 1][nt % g] = true; if (nt == g) q.emplace_back(v - 1, 0, dep + 1); else q.emplace_front(v - 1, nt, dep); } } } } int main() { ios::sync_with_stdio(false); memset(seen, false, sizeof seen); cin >> n >> m; d.resize(m); for (ll &i : d) cin >> i; sort(d.begin(), d.end()); cin >> g >> r; bfs(); if (ans == 1e17) cout << -1 n ; else cout << ans << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2_4_V
`define SKY130_FD_SC_MS__NOR2_4_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2_4_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6; int q[maxn], fin, razbeg, jump, n; pair<int, int> ans[maxn]; int sz = 0; int main() { cin >> n >> fin >> razbeg >> jump; for (int i = 0; i < n; i++) cin >> q[i]; q[n] = 0; q[n + 1] = fin; n += 2; sort(q, q + n); int i = 0, now = 0; while (i < n - 1) if (i == n - 2) { if (fin - now > 0) ans[sz] = make_pair(0, fin - now), sz++; break; } else if (q[i + 1] - 1 - now < razbeg) { cout << IMPOSSIBLE ; return 0; } else { if (q[i + 1] - 1 - now > 0) ans[sz] = make_pair(0, q[i + 1] - 1 - now), sz++; now = q[i + 1] - 1; while (1) { i++; if (q[i] + 1 - now > jump) { cout << IMPOSSIBLE ; return 0; } if (i == n - 2) { ans[sz] = make_pair(1, q[i] + 1 - now), sz++, now = q[i] + 1; break; } else if (q[i + 1] - 1 - q[i] - 1 >= razbeg) { ans[sz] = make_pair(1, q[i] + 1 - now), sz++, now = q[i] + 1; break; } } } for (int i = 0; i < sz; i++) if (ans[i].first == 0) cout << RUN << ans[i].second << n ; else cout << JUMP << ans[i].second << n ; }
|
#include <bits/stdc++.h> using namespace std; inline int max(int a, int b) { return a > b ? a : b; } map<int, int> mp; int a[200005], id; inline int read(int x) { if (mp.count(x) > 0) return mp[x]; mp[x] = ++id; return id; } int main() { int n; scanf( %d , &n); int x; for (int i = 1; i <= n; ++i) { scanf( %d , &x); ++a[read(x)]; } sort(a + 1, a + 1 + id); int ans = 0, last, now, pos; for (int i = 1; i <= n; ++i) { last = 1; now = 0; for (int k = i; k <= n; k <<= 1) { pos = lower_bound(a + last, a + id + 1, k) - a; if (pos > id) break; now += k; last = pos + 1; } ans = max(ans, now); } printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (int i = 0; i < n; i++) { if (a[i] != i + 1) { cout << i + 1; return 0; } } cout << n + 1; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_TB_V
`define SKY130_FD_SC_HVL__PROBEC_P_TB_V
/**
* probec_p: Virtual current probe point.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__probec_p.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hvl__probec_p dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBEC_P_TB_V
`define SKY130_FD_SC_HDLL__PROBEC_P_TB_V
/**
* probec_p: Virtual current probe point.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__probec_p.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__probec_p dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBEC_P_TB_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Freeze logic ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Generates all freezes and stalls inside RISC ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.2 2003/12/05 00:09:49 lampret
// No functional change.
//
// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.6 2002/07/31 02:04:35 lampret
// MAC now follows software convention (signed multiply instead of unsigned).
//
// Revision 1.5 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.4 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`define OR1200_NO_FREEZE 3'd0
`define OR1200_FREEZE_BYDC 3'd1
`define OR1200_FREEZE_BYMULTICYCLE 3'd2
`define OR1200_WAIT_LSU_TO_FINISH 3'd3
`define OR1200_WAIT_IC 3'd4
//
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
//
module or1200_freeze(
// Clock and reset
clk, rst,
// Internal i/f
multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
lsu_unstall, du_stall, mac_stall,
force_dslot_fetch, abort_ex,
genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze,
icpu_ack_i, icpu_err_i
);
//
// I/O
//
input clk;
input rst;
input [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
input flushpipe;
input extend_flush;
input lsu_stall;
input if_stall;
input lsu_unstall;
input force_dslot_fetch;
input abort_ex;
input du_stall;
input mac_stall;
output genpc_freeze;
output if_freeze;
output id_freeze;
output ex_freeze;
output wb_freeze;
input icpu_ack_i;
input icpu_err_i;
//
// Internal wires and regs
//
wire multicycle_freeze;
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt;
reg flushpipe_r;
//
// Pipeline freeze
//
// Rules how to create freeze signals:
// 1. Not overwriting pipeline stages:
// Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more
// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
//
// 2. Inserting NOPs in the middle of pipeline only if supported:
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
//assign genpc_freeze = du_stall | flushpipe_r | lsu_stall;
assign genpc_freeze = du_stall | flushpipe_r;
assign if_freeze = id_freeze | extend_flush;
//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall | mac_stall;
assign ex_freeze = wb_freeze;
//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex;
//
// registered flushpipe
//
always @(posedge clk or posedge rst)
if (rst)
flushpipe_r <= #1 1'b0;
else if (icpu_ack_i | icpu_err_i)
// else if (!if_stall)
flushpipe_r <= #1 flushpipe;
else if (!flushpipe)
flushpipe_r <= #1 1'b0;
//
// Multicycle freeze
//
assign multicycle_freeze = |multicycle_cnt;
//
// Multicycle counter
//
always @(posedge clk or posedge rst)
if (rst)
multicycle_cnt <= #1 2'b00;
else if (|multicycle_cnt)
multicycle_cnt <= #1 multicycle_cnt - 2'd1;
else if (|multicycle & !ex_freeze)
multicycle_cnt <= #1 multicycle;
endmodule
|
#include <bits/stdc++.h> using namespace std; string moves[] = { MW , LW , LM }; int sequence[25]; void listify(int k, int n) { for (int i = 0; i != n; ++i) { sequence[i] = k % 3; k /= 3; } } void solve(int n, vector<vector<int> >& V) { int n1 = n / 2; int n2 = n - n1; int k1 = pow(3, n1), k2 = pow(3, n2); vector<int> state(3); map<pair<int, int>, pair<int, int> > sums; for (int k = 0; k != k1; ++k) { listify(k, n1); state[0] = state[1] = state[2] = 0; for (int i = 0; i != n1; ++i) { state[(sequence[i] + 1) % 3] += V[i][(sequence[i] + 1) % 3]; state[(sequence[i] + 2) % 3] += V[i][(sequence[i] + 2) % 3]; } pair<int, int> p(state[1] - state[0], state[2] - state[0]); if (sums.find(p) == sums.end() || sums[p].first < state[0]) { sums[p] = make_pair(state[0], k); } } int max_equal_rel = -1000000000; pair<int, int> argmax; for (int k = 0; k != k2; ++k) { listify(k, n2); state[0] = state[1] = state[2] = 0; for (int i = 0; i != n2; ++i) { state[(sequence[i] + 1) % 3] += V[i + n1][(sequence[i] + 1) % 3]; state[(sequence[i] + 2) % 3] += V[i + n1][(sequence[i] + 2) % 3]; } pair<int, int> p(state[0] - state[1], state[0] - state[2]); if (sums.find(p) != sums.end() && sums[p].first + state[0] > max_equal_rel) { max_equal_rel = sums[p].first + state[0]; argmax = make_pair(sums[p].second, k); } } if (max_equal_rel == -1000000000) { cout << Impossible << endl; } else { listify(argmax.first, n1); for (int i = 0; i != n1; ++i) { cout << moves[sequence[i]] << endl; } listify(argmax.second, n2); for (int i = 0; i != n2; ++i) { cout << moves[sequence[i]] << endl; } } } int main() { int n; cin >> n; vector<vector<int> > V(n, vector<int>(3)); for (int i = 0; i != n; ++i) { cin >> V[i][0] >> V[i][1] >> V[i][2]; } solve(n, V); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fLL; const double EPS = 1e-8; const int MOD = 998244353; const int dy[] = {1, 0, -1, 0}, dx[] = {0, -1, 0, 1}; int mod = MOD; struct ModInt { unsigned val; ModInt() : val(0) {} ModInt(long long x) : val(x >= 0 ? x % mod : x % mod + mod) {} ModInt pow(long long exponent) { ModInt tmp = *this, res = 1; while (exponent > 0) { if (exponent & 1) res *= tmp; tmp *= tmp; exponent >>= 1; } return res; } ModInt &operator+=(const ModInt &rhs) { if ((val += rhs.val) >= mod) val -= mod; return *this; } ModInt &operator-=(const ModInt &rhs) { if ((val += mod - rhs.val) >= mod) val -= mod; return *this; } ModInt &operator*=(const ModInt &rhs) { val = (unsigned long long)val * rhs.val % mod; return *this; } ModInt &operator/=(const ModInt &rhs) { return *this *= rhs.inv(); } bool operator==(const ModInt &rhs) const { return val == rhs.val; } bool operator!=(const ModInt &rhs) const { return val != rhs.val; } bool operator<(const ModInt &rhs) const { return val < rhs.val; } bool operator<=(const ModInt &rhs) const { return val <= rhs.val; } bool operator>(const ModInt &rhs) const { return val > rhs.val; } bool operator>=(const ModInt &rhs) const { return val >= rhs.val; } ModInt operator-() const { return ModInt(-val); } ModInt operator+(const ModInt &rhs) const { return ModInt(*this) += rhs; } ModInt operator-(const ModInt &rhs) const { return ModInt(*this) -= rhs; } ModInt operator*(const ModInt &rhs) const { return ModInt(*this) *= rhs; } ModInt operator/(const ModInt &rhs) const { return ModInt(*this) /= rhs; } friend ostream &operator<<(ostream &os, const ModInt &rhs) { return os << rhs.val; } friend istream &operator>>(istream &is, ModInt &rhs) { long long x; is >> x; rhs = ModInt(x); return is; } private: ModInt inv() const { unsigned a = val, b = mod; int x = 1, y = 0; while (b) { unsigned tmp = a / b; a -= tmp * b; swap(a, b); x -= tmp * y; swap(x, y); } return ModInt(x); } }; ModInt abs(const ModInt &x) { return x.val; } struct Combinatorics { Combinatorics(int MAX = 5000000) { MAX <<= 1; fact.resize(MAX + 1); fact_inv.resize(MAX + 1); fact[0] = 1; for (int i = (1); i < (MAX + 1); ++i) fact[i] = fact[i - 1] * i; fact_inv[MAX] = ModInt(1) / fact[MAX]; for (int i = MAX; i > 0; --i) fact_inv[i - 1] = fact_inv[i] * i; } ModInt nCk(int n, int k) { if (n < 0 || n < k || k < 0) return ModInt(0); return fact[n] * fact_inv[k] * fact_inv[n - k]; } ModInt nPk(int n, int k) { if (n < 0 || n < k || k < 0) return ModInt(0); return fact[n] * fact_inv[n - k]; } ModInt nHk(int n, int k) { if (n < 0 || k < 0) return ModInt(0); return (k == 0 ? ModInt(1) : nCk(n + k - 1, k)); } private: vector<ModInt> fact, fact_inv; }; int main() { cin.tie(0); ios::sync_with_stdio(false); int n, m; cin >> n >> m; vector<int> a(n); for (int i = (0); i < (n); ++i) cin >> a[i]; vector<int> w(n); for (int i = (0); i < (n); ++i) cin >> w[i]; int dislike = 0, like = 0; for (int i = (0); i < (n); ++i) { if (a[i] == 0) dislike += w[i]; else like += w[i]; } for (int i = (0); i < (n); ++i) { vector<vector<vector<ModInt> > > dp( m + 1, vector<vector<ModInt> >(m + 1, vector<ModInt>(m + 1, 0))); dp[0][0][0] = 1; int dl = dislike, l = like; if (a[i] == 0) dl -= w[i]; else l -= w[i]; for (int x = (0); x < (m); ++x) { for (int y = (0); y < (m + 1); ++y) for (int z = (0); z < (m + 1); ++z) { int sum = like + dislike - z + (x - y - z) + (a[i] == 0 ? -y : y); if (a[i] == 0 && y > w[i]) continue; if (z > dl || y + z > x || sum <= 0) continue; dp[x + 1][y + 1][z] += dp[x][y][z] * (w[i] + (a[i] == 0 ? -y : y)) / sum; dp[x + 1][y][z + 1] += dp[x][y][z] * (dl - z) / sum; dp[x + 1][y][z] += dp[x][y][z] * (l + (x - y - z)) / sum; } } ModInt ans = 0; for (int y = (0); y < (m + 1); ++y) for (int z = (0); z < (m + 1); ++z) { if (a[i] == 0 && y > w[i]) continue; if (z > dl || y + z > m) continue; ans += dp[m][y][z] * (w[i] + (a[i] == 0 ? -y : y)); } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, a, b, c, result = 0, i, x, y, j = 0; cin >> n >> a >> b >> c; for (i = 0; i <= min(n, a / 2); i++) { x = min(c, (n - i) / 2); y = min(i + b, n); if (y - (n - x * 2) / 2 >= 0) { if (y >= n - x * 2) result += (y - (n - x * 2)) / 2 + 1; } } cout << result; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__A21O_PP_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; const int inf = 2012345678; const int N = 2e5 + 10; string s, ans, tmp; bool ch() { int i = 0; while (s[i] == tmp[i] && i < tmp.length()) ++i; return i == tmp.length(); } int main() { int n, k; cin >> n >> k >> s; ans = s, --k; int ps = 1; while (k--) { while (true) { if (ps == ans.length()) { ans += s, ps = ans.length(); break; } tmp = ans.substr(ps); if (ch()) { for (int i = tmp.length(); i < (int)(s.length()); ++i) ans += s[i]; ++ps; break; } else ++ps; } } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; struct str { int x1; int y1; int x2; int y2; }; bool compare(str &a, str &b) { if (a.x1 < b.x1) return true; else if (a.x1 == b.x1) { if (a.x2 < b.x2) return true; else if (a.x2 == b.x2) { if (a.y1 < b.y1) return true; else if (a.y1 <= b.y1) { return (a.y2 < b.y2); } } } return false; } int main() { int n; cin >> n; vector<str> v(n); for (int i = 0; i < n; i++) { cin >> v[i].x1 >> v[i].y1 >> v[i].x2 >> v[i].y2; } sort(v.begin(), v.end(), compare); int x11 = v[0].x1; int y11 = v[0].y1; int x22 = v[0].x2; int y22 = v[0].y2; int flag = 0, ind = 0, counter = 1; for (int i = 1; i < n; i++) { int x1 = max(x11, v[i].x1); int x2 = min(x22, v[i].x2); int y1 = max(y11, v[i].y1); int y2 = min(y22, v[i].y2); int x1r = x2 - x1; int y1r = y2 - y1; if ((x1r < 0 || y1r < 0) && !flag) { ind = i; } else { x11 = x1, y11 = y1, x22 = x2, y22 = y2; counter++; } } if (counter == n - 1) cout << x11 << << y11 << endl; else { x11 = v[ind].x1, y11 = v[ind].y1, x22 = v[ind].x2, y22 = v[ind].y2; for (int i = 1; i < n; i++) { int x1 = max(x11, v[i].x1); int x2 = min(x22, v[i].x2); int y1 = max(y11, v[i].y1); int y2 = min(y22, v[i].y2); int x1r = x2 - x1; int y1r = y2 - y1; if ((x1r < 0 || y1r < 0) && !flag) { ind = i; } else { x11 = x1, y11 = y1, x22 = x2, y22 = y2; counter++; } } cout << x11 << << y11 << endl; } }
|
`timescale 1 ps / 1 ps
module zynq_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output [31:0]gpio;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [31:0]gpio;
zynq_1 zynq_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.gpio(gpio));
endmodule
|
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