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#include <bits/stdc++.h> using namespace std; string solve() { int a, b, n; string number = ; cin >> a >> b >> n; bool added; added = false; a *= 10; for (int j = 1; j < 11; j++) { if (a % b == 0) { added = true; break; } a++; } if (!added) return -1 ; number = to_string(a); for (int i = 0; i < n - 1; i++) number += 0 ; return number; } int main(void) { cout << solve() << n ; }
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#include <bits/stdc++.h> using namespace std; ofstream outfile; ifstream infile; int main() { infile.open( input.txt ); outfile.open( output.txt ); long long int a, b; cin >> a >> b; if (a > b) { cout << 0 n ; return 0; } else if (b - a <= 20) { long long int digit = 1; for (long long int i = a + 1; i <= b; ++i) { digit = (digit * i) % 10; } cout << digit << n ; return 0; } cout << 0 n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, k, n2; long long dip, cert, losers; cin >> n >> k; dip = n / (2 * (k + 1)); cert = k * dip; losers = n - dip - cert; cout << dip << << cert << << losers; return 0; }
|
module \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
module \$_DFF_P_ (input D, C, output Q); SB_DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
module \$_DFFE_NN_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
module \$_DFFE_PN_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
module \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
module \$_DFF_NN0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
module \$_DFF_NN1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
module \$_DFF_PN0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
module \$_DFF_PN1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
module \$__DFFE_NN0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
module \$__DFFE_NN1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
module \$__DFFE_PN0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
module \$__DFFE_PN1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
module \$__DFFE_NP0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
module \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
module \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
`ifndef NO_SB_LUT4
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
end else
if (WIDTH == 2) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
end else
if (WIDTH == 3) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
end else
if (WIDTH == 4) begin
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* VC allocator
* Allocates new virtual-channels for newly arrived packets.
*
* "unrestricted" VC allocation (Peh/Dally style)
*
* Takes place in two stages:
*
* stage 1. ** VC Selection **
* Each waiting packet determines which VC it will request.
* (v:1 arbitration). Can support VC alloc. mask here (from
* packet header or static or dynamic..)
*
*
* stage 2. ** VC Allocation **
* Access to each output VC is arbitrated (PV x PV:1 arbiters)
*
*/
//
// ** THIS IS NOT USED ** only for hacking at present.... (*:
//
`include "types.v"
function automatic logic[15:0] NW_vc_sel_mask (input flit_t f);
begin
case (f.control.output_port)
`port5id_tile:
begin
NW_vc_sel_mask='1;
end
`port5id_north:
begin
// north next too
if (f.control.y_disp+1<0) begin
NW_vc_sel_mask=4'b0011;
end else begin
NW_vc_sel_mask=4'b1100;
end
end
`port5id_east:
begin
// east next too
if (f.control.x_disp-1>0) begin
NW_vc_sel_mask=4'b0011;
end else begin
NW_vc_sel_mask=4'b1100;
end
end
`port5id_south:
begin
// south next too
if (f.control.y_disp-1>0) begin
NW_vc_sel_mask=4'b0011;
end else begin
NW_vc_sel_mask=4'b1100;
end
end
`port5id_west:
begin
// west next too
if (f.control.x_disp+1<0) begin
NW_vc_sel_mask=4'b0011;
end else begin
NW_vc_sel_mask=4'b1100;
end
end
endcase
end
endfunction // NW_vc_sel_mask
module NW_vc_unrestricted_allocator (req, // VC request
output_port, // for which port?
//vc_mask, // which VC's are we permitted to request
req_priority, // prioritized requests? (between VC requests)
vc_status, // which VCs are free
vc_new, // newly allocated VC id.
vc_new_valid, // has new VC been allocated?
vc_allocated, // change VC status from free to allocated?
vc_requested, // which VCs were requested at each input VC?
flit, // head of each input VC buffer
vc_credits, // credits for each VC at each output port
clk, rst_n);
// `include "NW_functions.v";
//parameter type flit_priority_t = flit_pri_t;
parameter buf_len = 4;
parameter xs=4;
parameter ys=4;
parameter np=5;
parameter nv=4;
// some packets can make higher priority requests for VCs
// ** NOT YET IMPLEMENTED **
parameter dynamic_priority_vc_alloc = 0;
//
// selection policies
//
parameter vcselect_bydestinationnode = 0;
parameter vcselect_leastfullbuffer = 0;
parameter vcselect_arbstateupdate = 0; // always/never update state of VC select matrix arbiter
parameter vcselect_usepacketmask = 0; // packet determines which VCs may be requested (not with bydestinationnode!)
typedef logic unsigned [clogb2(buf_len+1)-1:0] pri_t;
//-----
input [np-1:0][nv-1:0] req;
input output_port_t output_port [np-1:0][nv-1:0];
//input [np-1:0][nv-1:0][nv-1:0] vc_mask;
input flit_priority_t req_priority [np-1:0][nv-1:0];
input [np-1:0][nv-1:0] vc_status;
output [np-1:0][nv-1:0][nv-1:0] vc_new;
output [np-1:0][nv-1:0] vc_new_valid;
output [np-1:0][nv-1:0] vc_allocated;
output [np-1:0][nv-1:0][nv-1:0] vc_requested;
input flit_t flit [np-1:0][nv-1:0];
input [np-1:0][nv-1:0][clogb2(buf_len+1)-1:0] vc_credits;
input clk, rst_n;
genvar i,j,k,l;
logic [np-1:0][nv-1:0][nv-1:0] stage1_request, stage1_grant;
logic [np-1:0][nv-1:0][nv-1:0] selected_status;
logic [np-1:0][nv-1:0][np-1:0][nv-1:0] stage2_requests, stage2_grants;
logic [np-1:0][nv-1:0][nv-1:0][np-1:0] vc_new_;
logic [np-1:0][nv-1:0][nv-1:0] vc_mask;
pri_t pri [np-1:0][nv-1:0][nv-1:0];
assign vc_requested=stage1_grant;
generate
for (i=0; i<np; i++) begin:foriports
for (j=0; j<nv; j++) begin:forvcs
//
// Determine value of 'vc_mask'
//
// What VCs may be requested?
//
// (a) all
// (b) use mask set in packet's control field
// (c) or select VC solely by destination node
//
if (vcselect_bydestinationnode || vcselect_usepacketmask) begin
if (vcselect_bydestinationnode) begin
//
// unless exiting network! - should be set as vcalloc_mask at source!!!!! TO-DO
// OR just set second stage request directly?
/*assign vc_mask[i][j] = (output_port[i][j]==`port5id_tile) ? '1 :
1'b1<<(flit[i][j].debug.xdest+xs*flit[i][j].debug.ydest);
// 1'b1<<(flit[i][j].debug.xsrc+xs*flit[i][j].debug.ysrc);
*/
end else begin
end
end else begin
// packet may request any free VC
assign vc_mask[i][j] = '1;
end
//
// Select VC status bits at output port of interest (determine which VCs are free to be allocated)
//
assign selected_status[i][j] = vc_status[oh2bin(output_port[i][j])];
//
// Requests for VC selection arbiter
//
// Narrows requests from all possible VCs that could be requested to 1
//
for (k=0; k<nv; k++) begin:forvcs2
// Request is made if
// (1) Packet requires VC
// (2) VC Mask bit is set
// (3) VC is currently free, so it can be allocated
//
assign stage1_request[i][j][k] = req[i][j] && vc_mask[i][j][k] && selected_status[i][j][k];
// VC selection priority = number of credits
if (vcselect_leastfullbuffer) begin
assign pri[i][j][k] = vc_credits[oh2bin(output_port[i][j])][k];
end
end
//
// first-stage of arbitration
//
// Arbiter state doesn't mean much here as requests on different clock cycles may be associated
// with different output ports. vcselect_arbstateupdate determines if state is always or never
// updated.
//
matrix_arb #(.size(nv), .multistage(1),
.priority_support(vcselect_leastfullbuffer)
//,
//.priority_type(pri_t)
)
stage1arb
(.request(stage1_request[i][j]),
.req_priority(pri[i][j]),
.grant(stage1_grant[i][j]),
// .success(vc_new_valid[i][j]),
.success((vcselect_arbstateupdate==1)),
.clk, .rst_n);
//
// second-stage of arbitration, determines who gets VC
//
for (k=0; k<np; k++) begin:fo
for (l=0; l<nv; l++) begin:fv
assign stage2_requests[k][l][i][j] = stage1_grant[i][j][l] && output_port[i][j][k];
end
end
//
// np*nv np*nv:1 tree arbiters
//
NW_tree_arbiter #(.multistage(0),
.size(np*nv),
.groupsize(nv),
.priority_support(dynamic_priority_vc_alloc)
//,
//.priority_type(flit_priority_t)
) vcarb
(.request(stage2_requests[i][j]),
.req_priority(req_priority),
.grant(stage2_grants[i][j]),
.clk, .rst_n);
assign vc_allocated[i][j]=|(stage2_requests[i][j]);
//
// new VC IDs
//
for (k=0; k<np; k++) begin:fo2
for (l=0; l<nv; l++) begin:fv2
// could get vc x from any one of the output ports
assign vc_new_[i][j][l][k]=stage2_grants[k][l][i][j];
end
end
for (l=0; l<nv; l++) begin:fv3
assign vc_new[i][j][l]=|vc_new_[i][j][l];
end
assign vc_new_valid[i][j]=|vc_new[i][j];
end
end
endgenerate
endmodule // NW_vc_unrestricted_allocator
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 11:44:32 02/24/2012
// Design Name:
// Module Name: ag_video
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FONT_ROM(input[10:0] adr, input cs, output[7:0] DO);
reg[7:0] mem[0:2047];
assign DO = cs?mem[adr]:8'bZ;
initial begin
`include "agathe7.v"
end
endmodule
module ag_video(input clk50,
input[7:0] vmode,
output clk_vram,
output[13:0] AB2, input[15:0] DI2,
output[4:0] vga_bus);
parameter
HGR_WHITE = 4'b1111, // RGBX
HGR_BLACK = 4'b0000,
TEXT_COLOR= 4'b1111,
TEXT_BACK = 4'b0000;
wire clk25;
assign clk_vram = ~clk25;
wire[0:15] rDI2 = DI2;
// assign AB2 = 14'b0;
clk_div#2 cd2(clk50, clk25);
wire [9:0] hpos;
wire [8:0] vpos;
wire video_on;
reg[8:0] hpos1;
reg[7:0] vpos1;
wire[1:0] VTYPE = vmode[1:0];
// for 64K+ - variant
// wire[2:0] PAGE_ADDR = {vmode[6], vmode[6]? 1'b0: vmode[5], vmode[4]};
// for 32K-variant
wire[2:0] PAGE_ADDR = {0, vmode[5], vmode[4]};
wire[1:0] SUBPAGE_ADDR = vmode[3:2];
wire VTYPE_HGR = (VTYPE == 2'b11);
wire VTYPE_MGR = (VTYPE == 2'b01);
wire VTYPE_LGR = (VTYPE == 2'b00);
wire VTYPE_TXT = (VTYPE == 2'b10);
wire VTYPE_T32 = VTYPE_TXT && !vmode[7];
wire VTYPE_T64 = VTYPE_TXT && vmode[7];
wire VTYPE_T64_INV = VTYPE_T64 && !SUBPAGE_ADDR[0];
wire[13:0] HGR_ADDR = {PAGE_ADDR[1:0], vpos1, hpos1[8:5]};
wire[3:0] HGR_BITNO = hpos1[4:1];
wire HGR_BIT = rDI2[HGR_BITNO];
wire[3:0] HGR_COLOR = HGR_BIT? HGR_WHITE: HGR_BLACK;
wire[13:0] MGR_ADDR = {PAGE_ADDR[1:0], vpos1[7:1], hpos1[8:4]};
wire[1:0] MGR_BLOCKNO = hpos1[3:2];
wire[13:0] LGR_ADDR = {PAGE_ADDR[1:0], SUBPAGE_ADDR, vpos1[7:2], hpos1[8:5]};
wire[1:0] LGR_BLOCKNO = hpos1[4:3];
wire[1:0] GR_BLOCKNO = VTYPE_MGR?MGR_BLOCKNO:
LGR_BLOCKNO;
wire[3:0] GR_COLOR = (GR_BLOCKNO == 2'b00)? {DI2[12], DI2[13], DI2[14], DI2[15]}:
(GR_BLOCKNO == 2'b01)? {DI2[8], DI2[9], DI2[10], DI2[11]}:
(GR_BLOCKNO == 2'b10)? {DI2[4], DI2[5], DI2[6], DI2[7]}:
{DI2[0], DI2[1], DI2[2], DI2[3]};
wire[13:0] TEXT_ADDR = {PAGE_ADDR[1:0], SUBPAGE_ADDR, vpos1[7:3], hpos1[8:4]};
wire h_phase = hpos1[1:0]?0:1;
reg[0:0] h_cnt = 0;
wire[0:0] h_delay = h_phase?1'd1:1'd0;
wire v_phase = vpos1[2:0]?1:0;
reg[0:0] v_cnt = 0;
wire[0:0] v_delay = v_phase?1'd1:1'd0;
wire[7:0] font_char;
wire[2:0] font_y, font_x;
wire[10:0] font_ab = {font_char, font_y};
wire[0:7] font_db;// = 8'b0;
wire font_pix = font_db[font_x];
FONT_ROM font(font_ab, 1, font_db);
integer flash_cnt = 0;
reg flash_reg = 0;
wire inverse = VTYPE_T64?VTYPE_T64_INV:!{DI2[5],DI2[3]},
flash = VTYPE_T64?font_db[7]:!{DI2[5],~DI2[3]};
wire inv_mode = inverse || (flash && flash_reg);
assign font_x = VTYPE_T64?hpos1[2:0]:hpos1[3:1];
assign font_y = vpos1[2:0];
assign font_char = (VTYPE_T64 && hpos1[3])? DI2[7:0]: DI2[15:8];
wire[3:0] T_COLOR = VTYPE_T64? TEXT_COLOR: {DI2[0], DI2[1], DI2[2], DI2[4]};
assign AB2 = VTYPE_HGR? HGR_ADDR:
VTYPE_MGR? MGR_ADDR:
VTYPE_LGR? LGR_ADDR:
TEXT_ADDR;
wire[2:0] color = VTYPE_HGR? HGR_COLOR[3:1]:
(VTYPE_MGR | VTYPE_LGR)? GR_COLOR[3:1]:
((font_pix^inv_mode)?T_COLOR[3:1]: TEXT_BACK);
reg[2:0] color_reg;
always @(posedge clk25) begin
if (!vga_bus[1]) begin
hpos1 <= 0;
h_cnt <= 1;
end else if (video_on) begin
if (!h_cnt) begin
h_cnt <= h_delay;
hpos1 <= hpos1 + 1;
end else h_cnt <= h_cnt - 1;
end
end
always @(posedge clk25) color_reg <= color;
always @(posedge video_on) begin
if (!vpos) begin
vpos1 <= 0;
v_cnt <= 1;
end else begin
if (!v_cnt) begin
v_cnt <= v_delay;
vpos1 <= vpos1 + 1;
end else v_cnt <= v_cnt - 1;
end
end
always @(posedge vga_bus[0]) begin
if (flash_cnt) flash_cnt <= flash_cnt - 1;
else begin
flash_cnt <= 11;
flash_reg <= ~flash_reg;
end
end
assign {vga_bus[4], vga_bus[3], vga_bus[2]} = video_on?color_reg:3'b000;
video_counters cnt(clk25, vga_bus[0], vga_bus[1], video_on, hpos, vpos);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_0_V
`define SKY130_FD_SC_HD__OR2_0_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2_0 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2_0 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_0_V
|
// ----------------------------
// This module impelements a counter.
//
// Note:
// - Syntax works and compiles with Verilog2LPN compiler
// - async. design follows dual rail encoding that maps
// input to output and output to internal states
//
// author: Tramy Nguyen
// ----------------------------
module counter_imp (a0, a1, b0, b1, req, ack);
input wire req;
output reg a0, a1, b0, b1, ack;
reg state0, state1;
initial begin
a0 = 1'b0;
a1 = 1'b0;
b0 = 1'b0;
b1 = 1'b0;
state0 = 1'b0;
state1 = 1'b0;
ack = 1'b0;
end
always begin
wait(req == 1'b1) #5;
// input to output
if(state1 != 1'b1 && state0 != 1'b1) begin
#5 a0 = 1'b1;
#5 b0 = 1'b1;
#5 ack = 1'b1;
end
else if(state1 != 1'b1 && state0 == 1'b1) begin
#5 a0 = 1'b1;
#5 b1 = 1'b1;
#5 ack = 1'b1;
end
else if(state1 == 1'b1 && state0 == 1'b1) begin
#5 a1 = 1'b1;
#5 b0 = 1'b1;
#5 ack = 1'b1;
end
else if(state1 == 1'b1 && state0 != 1'b1) begin
#5 a1 = 1'b1;
#5 b1 = 1'b1;
#5 ack = 1'b1;
end
// output to next state
if(a0 == 1'b1 && b0 == 1'b1 ) begin
if(state1 != 1'b1 && state0 != 1'b1) begin
state0 = 1'b1;
end
end
else if(a0 == 1'b1 && b1 == 1'b1 ) begin
if(state1 != 1'b1 && state0 == 1'b1) begin
state1 = 1'b1;
end
end
else if(a1 == 1'b1 && b0 == 1'b1) begin
if(state1 == 1'b1 && state0 == 1'b1) begin
state0 = 1'b0;
end
end
else if(a1 == 1'b1 && b1 == 1'b1) begin
if(state1 == 1'b1 && state0 != 1'b1) begin
state1 = 1'b0;
end
end
//stabilize the signals
wait((a0 == 1'b1 && b0 == 1'b1 && state1 != 1'b1 && state0 == 1'b1) ||
(a0 == 1'b1 && b1 == 1'b1 && state1 == 1'b1 && state0 == 1'b1) ||
(a1 == 1'b1 && b0 == 1'b1 && state1 == 1'b1 && state0 != 1'b1) ||
(a1 == 1'b1 && b1 == 1'b1 && state1 != 1'b1 && state0 != 1'b1)) #5;
// reset
wait(req != 1'b1) #5;
if(a0 == 1'b1) begin
#5 a0 = 1'b0;
end
if(a1 == 1'b1) begin
#5 a1 = 1'b0;
end
if(b0 == 1'b1) begin
#5 b0 = 1'b0;
end
if(b1 == 1'b1) begin
#5 b1 = 1'b0;
end
#5 ack = 1'b0;
end
endmodule
|
module RGB1_RGB2(
input clk,
input Btn_R,
input Btn_L,
output reg [2:0] RGB1 = 0,
output reg [2:0] RGB2 = 0
);
reg [1:0]state = 0;
reg [1:0]nextState = 0;
always @ (posedge clk)
begin
state <= nextState;
case(state)
0: begin
RGB1[0] <= 1;
RGB1[1] <= 0;
RGB1[2] <= 0;
RGB2[0] <= 1;
RGB2[1] <= 0;
RGB2[2] <= 0;
if (Btn_R == 1)
nextState <= 1;
if (Btn_L == 1)
nextState <= 2;
end
1: begin
RGB1[0] <= 0;
RGB1[1] <= 1;
RGB1[2] <= 0;
RGB2[0] <= 0;
RGB2[1] <= 1;
RGB2[2] <= 0;
if (Btn_R == 1)
nextState <= 2;
if (Btn_L == 1)
nextState <= 0;
end
2: begin
RGB1[0] <= 0;
RGB1[1] <= 0;
RGB1[2] <= 1;
RGB2[0] <= 0;
RGB2[1] <= 0;
RGB2[2] <= 1;
if (Btn_R == 1)
nextState <= 0;
if (Btn_L == 1)
nextState <= 1;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:40:43 05/17/2016
// Design Name:
// Module Name: MAIN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MAIN(
input clk_100,
input Step_BTN,
input rst,
//input [2:0] SW,
//output reg [7:0] LED
output [31:0] F
);
wire btnclk, ZF, OF;
wire [31:0] ALU_F;
BTN_OK BTN (
.clk(clk_100),
.BTN(Step_BTN),
.BTN_out(btnclk)
);
R_CPU CPU (
.clk(btnclk),
.rst(rst),
.ALU_F(ALU_F),
.FR_ZF(ZF),
.FR_OF(OF)
);
/*
LED_DISPLAY LEDoutput (
.OF(OF),
.ZF(ZF),
.SW(SW),
.ALU_F(ALU_F),
.LED(LED)
);
*/
assign F = ALU_F;
endmodule
module LED_DISPLAY(
input OF, ZF,
input [2:0] SW,
input [31:0] ALU_F,
output reg [7:0] LED
);
always @(*)
begin
case(SW[2:0])
3'd0: begin
LED = ALU_F[7:0];
end
3'd1: begin
LED = ALU_F[15:8];
end
3'd2: begin
LED = ALU_F[23:16];
end
3'd3: begin
LED = ALU_F[31:24];
end
3'd4: begin
LED[0] = OF;
LED[1] = ZF;
LED[7:2] = 6'd0;
end
default: begin
LED = 8'd0;
end
endcase
end
endmodule
module ALU(A, B, ZF, OF, F, ALU_OP);
input [2:0] ALU_OP;
input [31:0] A, B;
output reg [31:0] F;
output reg ZF, OF;
reg C32;
always @(*)
begin
case(ALU_OP)
3'd0:begin //and
F = A&B;
OF = 0;
end
3'd1:begin //or
F = A|B;
OF = 0;
end
3'd2:begin //xor
F = A^B;
OF = 0;
end
3'd3:begin //nor
F = ~(A|B);
OF = 0;
end
3'd4:begin //add
{C32, F} = A + B;
OF = A[31]^B[31]^F[31]^C32;
end
3'd5:begin //sub
{C32, F} = A - B;
OF = A[31]^B[31]^F[31]^C32;
end
3'd6:begin //slt
if (A<B)
begin
F = 32'd1;
end
else
begin
F = 32'd0;
end
OF = 0;
end
3'd7:begin //sll
F=B<<A;
OF=0;
end
default:begin
F=A;
OF = 0;
end
endcase
if (F == 32'd0)
begin
ZF = 1;
end
else
begin
ZF = 0;
end
end
endmodule
module register(clk, Reset, R_Addr_A, R_Addr_B, W_Addr, W_Data, Write_Reg, R_Data_A, R_Data_B
);
input clk;
input Reset;
input Write_Reg;
input [4:0] R_Addr_A, R_Addr_B, W_Addr;
input [31:0] W_Data;
output [31:0] R_Data_A;
output [31:0] R_Data_B;
reg [31:0] REGISTERS[0:31];
integer i;
assign R_Data_A = (R_Addr_A==5'b00000)? 32'h0000_0000 : REGISTERS[R_Addr_A];
assign R_Data_B = (R_Addr_B==5'b00000)? 32'h0000_0000 : REGISTERS[R_Addr_B];
always @(posedge clk or posedge Reset)
begin
if(Reset)
begin
for(i=0; i<=31; i=i+1)
begin
REGISTERS[i]<=32'h0000_0000;
end
end
else
begin
if(Write_Reg && (W_Addr != 5'b00000))
begin
REGISTERS[W_Addr]<=W_Data;
end
/*
else
begin
REGISTERS[W_Addr]<=REGISTERS[W_Addr];
end
*/
end
end
endmodule
//EXPR 7
module IF_M(
input [0:0] clka,
input [0:0] rst,
output [31:0] Inst_code
);
wire [31:0] douta;
wire [5:0] addra;
reg [31:0] PC;
wire [31:0] PC_new;
ROM_B Inst_addr (
.clka(clka), // input clka
.addra(addra), // input [5 : 0] addra
.douta(douta) // output [31 : 0] douta
);
assign PC_new = PC + 4;
assign Inst_code = douta;
assign addra = PC[7:2];
always@(posedge clka or posedge rst)
begin
if(rst)
begin
PC[31:0]<=32'd0;
end
else
begin
PC<=PC_new;
end
end
endmodule
module BTN_OK(
input clk,
input BTN,
output reg BTN_out
);
wire BTN_Down;
reg BTN1;
reg BTN2;
reg [23:0] cnt;
reg BTN_20ms_1, BTN_20ms_2;
always @(posedge clk)
begin
BTN1 <= BTN;
BTN2 <= BTN1;
end
assign BTN_Down = (~BTN2)&&BTN1;
always @(posedge clk)
begin
if(BTN_Down)
begin
cnt <= 24'b0;
BTN_out <= 1'b1;
end
else
begin
cnt<=cnt+1'b1;
end
if(cnt == 24'h1E8480)
BTN_out <= 1'b0;
end
endmodule
module R_CPU (
input clk,
input rst,
output [31:0] ALU_F,
output reg FR_ZF,FR_OF,
output wire [4:0] rs, rt, rd,
output wire [5:0] OP, func,
output wire [31:0] ALU_A, ALU_B
);
wire ZF, OF;
wire [31:0] Inst_code;
reg Write_Reg;
reg [2:0] ALU_OP;
IF_M theIF (
.clka(clk),
.rst(rst),
.Inst_code(Inst_code)
);
assign OP = Inst_code[31:26]; // 6
assign rs = Inst_code[25:21]; // 5
assign rt = Inst_code[20:16]; // 5
assign rd = Inst_code[15:11]; // 5
assign func = Inst_code[5:0]; // 6
register REGS (
.clk(~clk),
.Reset(rst),
.R_Addr_A(rs),
.R_Addr_B(rt),
.W_Addr(rd),
.W_Data(ALU_F),
.Write_Reg(Write_Reg),
.R_Data_A(ALU_A),
.R_Data_B(ALU_B)
);
ALU theALU (
.A(ALU_A),
.B(ALU_B),
.ZF(ZF),
.OF(OF),
.F(ALU_F),
.ALU_OP(ALU_OP)
);
always @(*)
begin
ALU_OP = 3'b000;
Write_Reg = 1'b0;
if(OP==6'b000000)
begin
Write_Reg = 1'b1;
case (func)
6'b100000: ALU_OP = 3'b100;
6'b100010: ALU_OP = 3'b101;
6'b100100: ALU_OP = 3'b000;
6'b100101: ALU_OP = 3'b001;
6'b100110: ALU_OP = 3'b010;
6'b100111: ALU_OP = 3'b011;
6'b101011: ALU_OP = 3'b110;
6'b000100: ALU_OP = 3'b111;
default: ALU_OP = 3'b000;
endcase
end
else
begin
ALU_OP = 3'b000;
end
end
always @(negedge clk)
begin
FR_ZF <= ZF;
FR_OF <= OF;
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test was derived from PR615.v
**/
module main();
parameter INIT_00 = 32'hffffffff;
reg [4:0] c;
initial begin
c = 0;
$display("%b",INIT_00[c]);
if (INIT_00[c] !== 1'b1) begin
$display("FAILED");
$finish;
end
c = 1;
$display("%b",INIT_00[c]);
if (INIT_00[c] !== 1'b1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; while (cin >> n) { if (n == 1) { printf( a na nb nb n ); continue; } if (n % 2 == 0) { for (int i = 0; i < 4; i++) { for (int j = 0; j < n; j++) { if (i % 4 < 2) { printf( %c , a + (i % 2 + (j % 4) / 2) % 2); } else { if (j == 0) { printf( %c , c ); } else if (j == n - 1) { printf( %c , f ); } else { printf( %c , d + (i % 2 + (j - 1) % 4 / 2) % 2); } } } printf( n ); } } else { for (int i = 0; i < 4; i++) { for (int j = 0; j < n; j++) { if (i < 2) { if (j == n - 1) { printf( %c , c ); } else { printf( %c , a + (i % 2 + (j % 4) / 2) % 2); } } else { if (j < 1) { printf( %c , d ); } else { printf( %c , f + (i % 2 + (j - 1) % 4 / 2) % 2); } } } printf( n ); } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int child[N], w[N]; long long dp[N][35][3], ans[N][2]; void pre(int n) { for (int i = 0; i < n; i++) { dp[i][0][0] = w[i]; dp[i][0][2] = w[i]; dp[i][0][1] = child[i]; } for (int j = 1; j < 35; j++) { for (int i = 0; i < n; i++) { dp[i][j][1] = dp[dp[i][j - 1][1]][j - 1][1]; dp[i][j][0] = dp[i][j - 1][0] + dp[dp[i][j - 1][1]][j - 1][0]; dp[i][j][2] = min(dp[i][j - 1][2], dp[dp[i][j - 1][1]][j - 1][2]); } } } int main() { ios::sync_with_stdio(false); cin.tie(0); int n; long long k; cin >> n >> k; for (int i = 0; i < n; i++) cin >> child[i]; for (int i = 0; i < n; i++) cin >> w[i]; pre(n); int pt; for (int i = 0; i < n; i++) { pt = i; ans[i][1] = 1000000007ULL; for (long long j = 0; (1LL << j) <= k; j++) { if ((1LL << j) & k) { ans[i][0] += dp[pt][j][0]; ans[i][1] = min(ans[i][1], dp[pt][j][2]); pt = dp[pt][j][1]; } } } for (int i = 0; i < n; i++) cout << ans[i][0] << << ans[i][1] << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S2S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLYMETAL6S2S_BEHAVIORAL_PP_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S2S_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long N = (long long)(5 * 1e5 + 10); void precision(long long a) { cout << setprecision(a) << fixed; } long long expo(long long a, long long b, long long m) { long long res = 1; while (b > 0) { if (b & 1) res = (res * a) % m; a = (a * a) % m; b = b >> 1; } return res; } long long GCD(long long A, long long B) { return (B) ? GCD(B, A % B) : A; } long long LCM(long long A, long long B) { return A * B / GCD(A, B); } long long max(long long A, long long B) { return (A >= B) ? A : B; } long long min(long long A, long long B) { return (A <= B) ? A : B; } long long ceil_div(long long a, long long b) { return a % b == 0 ? a / b : a / b + 1; } template <typename T> istream &operator>>(istream &istream, vector<T> &v) { for (auto &it : v) { cin >> it; } return istream; } bool isPrime(long long n) { if (n == 1) return false; if (n == 2) return true; for (long long i = 2; i * i <= n; i++) { if (n % i == 0) return false; } return true; } void rec(long long n) { cout << (long long)sqrt(n) + (long long)cbrt(n) - (long long)(sqrt(cbrt(n))) << n ; } void sol() { long long n; cin >> n; rec(n); } int32_t main() { ios_base::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); long long t = 1; cin >> t; while (t--) { sol(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int n, m, k; int t, x; int c[200010]; int f1[200010]; int f2[200010]; vector<int> w, a, b; vector<int> d; vector<ll> ww, aa, bb, dd; int main() { ios::sync_with_stdio(false); cin >> n >> m >> k; for (int i = 0; i < n; i++) cin >> c[i]; cin >> t; for (int i = 0; i < t; i++) { cin >> x; f1[x - 1] = 1; } cin >> t; for (int i = 0; i < t; i++) { cin >> x; f2[x - 1] = 1; } for (int i = 0; i < n; i++) { if (f1[i] && f2[i]) w.push_back(c[i]); else if (f1[i]) a.push_back(c[i]); else if (f2[i]) b.push_back(c[i]); else d.push_back(c[i]); } sort(w.begin(), w.end()); sort(a.begin(), a.end()); sort(b.begin(), b.end()); sort(d.begin(), d.end()); ww.push_back(0); aa.push_back(0); bb.push_back(0); dd.push_back(0); for (int i = 0; i < w.size(); i++) ww.push_back(ww.back() + w[i]); for (int i = 0; i < a.size(); i++) aa.push_back(aa.back() + a[i]); for (int i = 0; i < b.size(); i++) bb.push_back(bb.back() + b[i]); for (int i = 0; i < d.size(); i++) dd.push_back(dd.back() + d[i]); ll ans = 1e18 + 1; for (int i = 0; i <= w.size(); i++) { ll cost = ww[i]; int need = max(0, k - i); if (need > a.size() || need > b.size() || i + need * 2 > m) continue; cost += aa[need]; cost += bb[need]; int re = m - i - 2 * need; if (a.size() - need + b.size() - need + d.size() < re) continue; if (re > 0) { int l = 0; int r = 1e9 + 1; while (l < r) { int mid = (l + r) / 2; int cnt = 0; int h = upper_bound(a.begin(), a.end(), mid) - a.begin(); cnt += max(0, h - need); h = upper_bound(b.begin(), b.end(), mid) - b.begin(); cnt += max(0, h - need); h = upper_bound(d.begin(), d.end(), mid) - d.begin(); cnt += max(0, h); if (cnt >= re) r = mid; else l = mid + 1; } { int mid = l; int cnt = 0; int h = upper_bound(a.begin(), a.end(), mid) - a.begin(); cnt += max(0, h - need); if (h > need) cost += aa[h] - aa[need]; h = upper_bound(b.begin(), b.end(), mid) - b.begin(); cnt += max(0, h - need); if (h > need) cost += bb[h] - bb[need]; h = upper_bound(d.begin(), d.end(), mid) - d.begin(); cnt += max(0, h); cost += dd[h]; if (cnt > re) cost -= mid * (cnt - re); } } ans = min(ans, cost); } if (ans > 1e17) ans = -1; cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_BLACKBOX_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_BLACKBOX_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_BLACKBOX_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build Mon Apr 27 19:22:08 MDT 2015
// Date : Tue Mar 22 03:39:21 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/SKL/Desktop/ECE532/quadencoder/encoder_decoder_prj/project_1.srcs/sources_1/ip/dcfifo_32in_32out_16kb_rd_cnt/dcfifo_32in_32out_16kb_rd_cnt_stub.v
// Design : dcfifo_32in_32out_16kb_rd_cnt
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
module dcfifo_32in_32out_16kb_rd_cnt(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, rd_data_count)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,rd_data_count[1:0]" */;
input rst;
input wr_clk;
input rd_clk;
input [31:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output empty;
output [1:0]rd_data_count;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 , unroll-all-loops ) #pragma GCC target( sse4.2 ) using namespace std; ifstream in; ofstream out; const long long kk = 1000; const long long ml = kk * kk; const long long mod = 998244353; const long long inf = ml * ml * ml + 7; const int C = 5; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int n, nxt, root; vector<int> p, comp, sz, edges; set<pair<int, pair<int, int>>> e; vector<vector<int>> kids; bool viv = false; bool big = false; const long double PI = 3.1415926535897932384626433; inline int rev(int val, int b) { int res = 0; for (int i = 0; i < b; i++) if (val & (1 << i)) res |= (1 << (b - 1 - i)); return res; } vector<int> mul_stpd(const vector<int> &a, const vector<int> &b) { vector<long long> res(a.size() + b.size() - 1); for (int i = 0; i < b.size(); i++) { for (int j = 0; j < a.size(); j++) { res[i + j] += (long long)a[j] * b[i]; res[i + j] %= mod; } } return vector<int>(res.begin(), res.end()); } int pp(int v) { if (p[v] == v) return v; return p[v] = pp(p[v]); } bool full(int v) { if (viv) cout << at << v << with sz = << sz[v] << see << edges[v] << endl; return ((int)sz[v] - 1) * (sz[v]) == 2 * edges[v]; } void unit(int v, int u) { v = pp(v); u = pp(u); if (v == u) { edges[v]++; return; } if (full(v) && full(u)) { if (viv) cout << Fully << endl; if (sz[v] < sz[u]) swap(v, u); sz[v] += sz[u]; edges[v] += edges[u]; p[u] = v; edges[v]++; kids[nxt].push_back(comp[v]); kids[nxt].push_back(comp[u]); comp[v] = nxt++; } else { if (viv) cout << Not Fully << endl; if (sz[v] < sz[u]) swap(v, u); if (full(v) && !full(u)) swap(v, u); sz[v] += sz[u]; edges[v] += edges[u]; p[u] = v; edges[v]++; assert(comp[v] >= n); if (full(u)) kids[comp[v]].push_back(comp[u]); else { for (auto s : kids[comp[u]]) kids[comp[v]].push_back(s); } } root = comp[v]; } void work(int v, int u) { unit(v, u); } void show() { for (int i = nxt - 1; i >= 0; i--) { cout << i << : ; for (auto s : kids[i]) cout << s << ; cout << endl; } } vector<int> get(int v) { if (viv) { cout << get( << v << ) << endl; } if (v < n) { return vector<int>({0, 1}); } vector<int> lres(1, 1); for (auto s : kids[v]) { lres = mul_stpd(lres, get(s)); if (viv) { cout << tnow << v << : ; for (auto i : lres) cout << i << ; cout << endl; } } while (lres.size() < 2) lres.push_back(0); lres[1]++; if (viv) { cout << v << : ; for (auto i : lres) cout << i << ; cout << endl; } return lres; } void solve() { cin >> n; nxt = n; sz.resize(n, 1); comp.resize(n); p.resize(n); edges.resize(n, 0); for (int i = 0; i < n; i++) p[i] = i, comp[i] = i; kids.resize(2 * n); vector<pair<int, int>> use(n * (n - 1) / 2); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { int w; cin >> w; if (i < j) { use[w - 1] = {i, j}; } } } for (auto p : use) work(p.first, p.second); if (viv) show(); auto res = get(root); while (res.size() < n + 1) res.push_back(0); for (int i = 1; i <= n; i++) cout << res[i] << ; cout << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mmmm = 1111; int n; char s[mmmm]; int a[mmmm], f[mmmm]; void qwe() { a[0] = 1989; f[0] = 1; for (int i = 1; i <= 9; i++) { f[i] = f[i - 1] * 10; a[i] = a[i - 1] + f[i]; } } int main() { qwe(); while (scanf( %d , &n) != EOF) { for (int i = 1; i <= n; i++) { scanf( %s , s); int l = strlen(s) - 4; int c = 0; for (int i = 4; i < l + 4; i++) { c = c * 10 + s[i] - 0 ; } int asd = a[l - 1]; int zxc = a[l]; int t1 = asd / f[l] * f[l] + c; int t2 = zxc / f[l] * f[l] + c; if (t1 >= asd && t1 < zxc) { printf( %d n , t1); } else { printf( %d n , t2); } } } return 0; }
|
#include <bits/stdc++.h> unsigned long long int factorial(unsigned long long int n) { unsigned long long int facto; if (n == 0) return 1; return facto = n * factorial(n - 1); } int main() { long long int a, b, GCD; unsigned long long int fa, fb; scanf( %I64d %I64d , &a, &b); if (a > b) { fb = factorial(b); printf( %I64d n , fb); } else { fa = factorial(a); printf( %I64d n , fa); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int K = 26; struct Vertex { int next[K]; long long int leaf = 0; int p = -1; char pch; int link = -1; int go[K]; long long int count = -1; int leaflink = 0; Vertex(int p = -1, char ch = $ ) : p(p), pch(ch) { fill(begin(next), end(next), -1); fill(begin(go), end(go), -1); } }; vector<Vertex> t(1); void add_string(string const& s) { int v = 0; for (char ch : s) { int c = ch - a ; if (t[v].next[c] == -1) { t[v].next[c] = t.size(); t.emplace_back(v, ch); } v = t[v].next[c]; } t[v].leaf++; } int go(int v, char ch); int get_link(int v); long long int cnt(int v) { if (t[v].count == -1) { if (v == 0) t[v].count = 0; else t[v].count = cnt(get_link(v)) + t[v].leaf; } return t[v].count; } int get_link(int v) { if (t[v].link == -1) { if (v == 0 || t[v].p == 0) t[v].link = 0; else t[v].link = go(get_link(t[v].p), t[v].pch); } return t[v].link; } int go(int v, char ch) { int c = ch - a ; if (t[v].go[c] == -1) { if (t[v].next[c] != -1) t[v].go[c] = t[v].next[c]; else t[v].go[c] = v == 0 ? 0 : go(get_link(v), ch); } return t[v].go[c]; } int main() { ios::sync_with_stdio(0); cin.tie(0); string ts; cin >> ts; int n; cin >> n; vector<string> v; for (int i = 0; i < n; ++i) { string s; cin >> s; v.push_back(s); reverse(s.begin(), s.end()); add_string(s); } int m = ts.size(); vector<long long int> a = vector<long long int>(m, 0); int cs = 0; for (int i = m - 1; i > -1; --i) { get_link(cs); cs = go(cs, ts[i]); get_link(cs); a[i] = cnt(cs); } t = vector<Vertex>(1); for (int i = 0; i < n; ++i) { add_string(v[i]); } cs = 0; long long int sol = 0; for (int i = 0; i < m - 1; ++i) { get_link(cs); cs = go(cs, ts[i]); get_link(cs); sol += cnt(cs) * a[i + 1]; } cout << sol << endl; }
|
#include <bits/stdc++.h> using namespace std; const int NMax = 5e3 + 5; const int MMax = 1e3 + 5; int N, M; char input[NMax][MMax + 101]; short bit[NMax][MMax][2]; char solMin[MMax], solMax[MMax]; map<string, int> ID; struct elem { bool known; int op1, op2; char tor; } v[NMax]; int compute(int, int, int); int main() { cin.sync_with_stdio(false); cin.tie(0); cin >> N >> M; cin.getline(input[0], MMax + 100); for (int i = 1; i <= N; ++i) { cin.getline(input[i] + 1, MMax + 100); string name = ; int j = 1; while ( a <= input[i][j] && input[i][j] <= z ) { name += input[i][j++]; } ID[name] = i; } for (int i = 1; i <= N; ++i) { int j = 1; while (input[i][j] != = ) { ++j; } j += 2; if (input[i][j] == 0 || input[i][j] == 1 ) { v[i].known = true; for (int k = 1; k <= M; ++k) { bit[i][k][0] = bit[i][k][1] = input[i][j] - 0 + 1; ++j; } } else { string str; if (input[i][j] == ? ) { v[i].op1 = -1; ++j; } else { str = ; while ( a <= input[i][j] && input[i][j] <= z ) { str += input[i][j]; ++j; } v[i].op1 = ID[str]; } ++j; if (input[i][j] == A ) { v[i].tor = & ; j += 3; } else if (input[i][j] == O ) { v[i].tor = | ; j += 2; } else { v[i].tor = ^ ; j += 3; } ++j; if (input[i][j] == ? ) { v[i].op2 = -1; } else { str = ; while ( a <= input[i][j] && input[i][j] <= z ) { str += input[i][j]; ++j; } v[i].op2 = ID[str]; } } } for (int b = 1; b <= M; ++b) { int nr1By1 = 0, nr1By0 = 0; for (int i = 1; i <= N; ++i) { nr1By1 += compute(i, b, 1); nr1By0 += compute(i, b, 0); } if (nr1By1 > nr1By0) { solMax[b] = 1 ; } else { solMax[b] = 0 ; } if (nr1By1 < nr1By0) { solMin[b] = 1 ; } else { solMin[b] = 0 ; } } cout << (solMin + 1) << n << (solMax + 1); return 0; } int compute(int id, int b, int val) { if (bit[id][b][val] != 0) { return bit[id][b][val] - 1; } int f1, f2; if (v[id].op1 == -1) { f1 = val; } else { f1 = compute(v[id].op1, b, val); } if (v[id].op2 == -1) { f2 = val; } else { f2 = compute(v[id].op2, b, val); } int res; if (v[id].tor == & ) { res = f1 & f2; } else if (v[id].tor == | ) { res = f1 | f2; } else { res = f1 ^ f2; } bit[id][b][val] = res + 1; return res; }
|
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_onchip_memory2_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 9: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 1024,
the_altsyncram.numwords_a = 1024,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 10;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; string s; cin >> s; string ans = s; int k_prime = 1; for (int k = 0; k < n; k++) { string t = s; rotate(t.begin(), t.begin() + k, t.end()); if (k % 2 != n % 2) { reverse(t.begin() + n - k, t.end()); } if (t < ans) { ans = t; k_prime = k + 1; } } cout << ans << n ; cout << k_prime << n ; } }
|
#include <bits/stdc++.h> using namespace std; template <typename F, typename S> ostream &operator<<(ostream &os, const pair<F, S> &p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << { ; typename vector<T>::const_iterator it; for (it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } return os << } ; } template <typename T> ostream &operator<<(ostream &os, const set<T> &v) { os << [ ; typename set<T>::const_iterator it; for (it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename F, typename S> ostream &operator<<(ostream &os, const map<F, S> &v) { os << [ ; typename map<F, S>::const_iterator it; for (it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << it->first << = << it->second; } return os << ] ; } int n, m; string hor, ver; int give_dir(char ch) { if (ch == > || ch == v ) return 1; else return -1; } bool valid(int x, int y) { if (x < 0 || y < 0 || x >= n || y >= m) return false; return true; } void dfs(int x, int y, vector<vector<bool> > &visited) { visited[x][y] = true; int nx, ny; nx = x + give_dir(ver[y]); ny = y + give_dir(hor[x]); if (valid(nx, y) && !visited[nx][y]) dfs(nx, y, visited); if (valid(x, ny) && !visited[x][ny]) dfs(x, ny, visited); } int main() { cin >> n >> m; cin >> hor >> ver; for (int k = 0; k < (n); k++) { for (int l = 0; l < (m); l++) { vector<vector<bool> > visited(n, vector<bool>(m, false)); dfs(k, l, visited); for (int i = 0; i < (n); i++) { for (int j = 0; j < (m); j++) { if (!visited[i][j]) { cout << NO << endl; return 0; } } } } } cout << YES << endl; return 0; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_Nano_SOPC_i2c_scl (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 1;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
ColorRGB24toVGA
:Function
Covert 24bits-RGB to VGA.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module ColorRGB24toVGA(
input[23:0] rgb24,
output[15:0] vga
);
assign vga[15:11] = rgb24[23:19];
assign vga[10:5] = rgb24[15:10];
assign vga[4:0] = rgb24[7:3];
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, Andrew "bunnie" Huang
//
// See the NOTICE file distributed with this work for additional
// information regarding copyright ownership. The copyright holder
// licenses this file to you under the Apache License, Version 2.0
// (the "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// code distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module eim_debug(
input wire bclk_i,
input wire bclk_dll,
input wire adv_in,
input wire rw_in,
input wire cs1_in,
input wire [2:0] a_in,
input wire [15:0] din_in,
input wire oe_in,
input wire eim_trig_ena,
input wire eim_mon_reset,
input wire eim_mon_adv,
output wire mon_empty,
output wire mon_full,
output wire [23:0] mon_data,
input wire bclk_reset
);
wire pretrig_full;
wire pretrig_almost_full;
wire [23:0] pretrig_d;
eim_pretrigger eim_pre (
.wr_clk(bclk_i), // input wr_clk
.rd_clk(bclk_dll), // input rd_clk
.din({1'b0,oe_in,adv_in,rw_in,cs1_in,a_in[2:0],din_in[15:0]}), // input [22 : 0] din
.wr_en(1'b1), // input wr_en
.rd_en(pretrig_full | pretrig_almost_full), // input rd_en
.dout(pretrig_d[23:0]), // output [23 : 0] dout
.full(pretrig_full), // output full
.almost_full(pretrig_almost_full),
// .empty(empty), // output empty
// .underflow(underflow), // output underflow
// .rd_data_count(rd_data_count) // output [7 : 0] rd_data_count
.rst(bclk_reset) // input rst
);
wire mon_trig;
reg mon_wren;
reg mon_oneshot;
assign mon_trig = eim_trig_ena & !cs1_in; // trigger on CS1 going active
// trigger state machine: wait for trigger; then fill the FIFO; then hold until reset
always @(posedge bclk_dll) begin
if(eim_mon_reset) begin
mon_oneshot <= 1'b0;
mon_wren <= 1'b0;
end else begin
if(mon_trig && !mon_wren && !mon_oneshot) begin // init then catch trigger
mon_wren <= 1'b1;
mon_oneshot <= 1'b1; // ignore future triggers
end else if( mon_oneshot && mon_wren ) begin // next state after trigger, write until full
mon_oneshot <= 1'b1;
if(mon_full) begin
mon_wren <= 1'b0; // once full, disable mon_wren
end else begin
mon_wren <= 1'b1;
end
end else if( mon_oneshot && !mon_wren ) begin // this is the terminal state from logging
mon_oneshot <= 1'b1;
mon_wren <= 1'b0;
end else begin // we reach this case if oneshot hasn't fired yet, e.g. waiting for tigger event
mon_oneshot <= 1'b0;
mon_wren <= 1'b0;
end
end // else: !if(eim_mon_reset)
end // always @ (posedge bclk_dll)
reg eim_mon_pulse;
reg [1:0] eim_mon_adv_d;
always @(posedge bclk_dll) begin
eim_mon_adv_d[0] <= eim_mon_adv;
eim_mon_adv_d[1] <= eim_mon_adv_d[0];
eim_mon_pulse <= !eim_mon_adv_d[1] & eim_mon_adv_d[0];
end
//// TODO: add almost_full to FIFO and map mon_full to almost_full to avoid overflow-by-one
eim_monitor eim_mon (
.wr_clk(bclk_dll), // input wr_clk
.rd_clk(bclk_dll), // input rd_clk
.din(pretrig_d[23:0]), // input [21 : 0] din
.wr_en(mon_wren), // input wr_en
.rd_en(eim_mon_pulse), // input rd_en
.dout(mon_data[23:0]), // output [21 : 0] dout
.almost_full(mon_full), // output full
// .overflow(overflow), // output overflow
.empty(mon_empty), // output empty
// .rd_data_count(rd_data_count) // output [9 : 0] rd_data_count
.rst(bclk_reset | eim_mon_reset) // input rst
);
endmodule // eim_debug
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; while (n--) { string s; cin >> s; int len = s.size(); int ok = 1; for (int i = 0; i < len; i++) { if (i == len) { if (s[i - 1] != a ) s[i] = a ; else if (s[i - 1] != b ) s[i] = b ; else if (s[i - 1] != c ) s[i] = c ; } if (s[i] == ? && i != len) { if (s[i - 1] != a && s[i + 1] != a ) s[i] = a ; else if (s[i - 1] != b && s[i + 1] != b ) s[i] = b ; else if (s[i - 1] != c && s[i + 1] != c ) s[i] = c ; } } for (int i = 0; i < len - 1; i++) { if (s[i] == s[i + 1]) ok = 0; } if (!ok) cout << -1 << n ; else cout << s << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_SYMBOL_V
`define SKY130_FD_SC_MS__XNOR3_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xnor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e4 + 4; long long int a[N][20], pre[N][20], ans; struct node { node *left, *right; long long int cnt; node() { left = NULL; right = NULL; cnt = 0; } }; struct trie { node *x; }; void insert(node *t, long long int x) { for (long long int i = 31; i >= 0; i--) { if (x & (1 << i)) { if (t->right == NULL) t->right = new node(); t = t->right; t->cnt++; } else { if (t->left == NULL) t->left = new node(); t = t->left; t->cnt++; } } } void del(node *t, long long int x) { for (long long int i = 31; i >= 0; i--) { if (x & (1 << i)) { t = t->right; t->cnt--; } else { t = t->left; t->cnt--; } } } long long int query(node *t, long long int x) { long long int ret = 0; for (long long int i = 31; i >= 0; i--) { if (x & (1 << i)) { if (t->left && t->left->cnt != 0) { ret |= (1 << i); t = t->left; } else t = t->right; } else { if (t->right && t->right->cnt != 0) { ret |= (1 << i); t = t->right; } else t = t->left; } } return ret; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); trie t; t.x = new node(); long long int n; cin >> n; insert(t.x, 0); for (long long int i = 1; i <= n; i++) { char ch; cin >> ch; long long int x; cin >> x; if (ch == + ) insert(t.x, x); if (ch == - ) del(t.x, x); if (ch == ? ) cout << query(t.x, x) << endl; } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ucb_bus_out.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: ucb_bus_out (ucb bus outbound interface block)
// Description: This interface block is instantiated by the
// UCB modules and IO Bridge to transmit packets
// on the UCB bus.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which
// contains the time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module ucb_bus_out (/*AUTOARG*/
// Outputs
vld, data, outdata_buf_busy,
// Inputs
clk, rst_l, stall, outdata_buf_in, outdata_vec_in, outdata_buf_wr
);
// synopsys template
parameter UCB_BUS_WIDTH = 32;
parameter REG_WIDTH = 64; // maximum data bits that needs to
// be sent. Set to 64 or 128
// Globals
input clk;
input rst_l;
// UCB bus interface
output vld;
output [UCB_BUS_WIDTH-1:0] data;
input stall;
// Local interface
output outdata_buf_busy;
input [REG_WIDTH+63:0] outdata_buf_in;
input [(REG_WIDTH+64)/UCB_BUS_WIDTH-1:0] outdata_vec_in;
input outdata_buf_wr;
// Local signals
wire stall_d1;
wire [(REG_WIDTH+64)/UCB_BUS_WIDTH-1:0] outdata_vec;
wire [(REG_WIDTH+64)/UCB_BUS_WIDTH-1:0] outdata_vec_next;
wire [REG_WIDTH+63:0] outdata_buf;
wire [REG_WIDTH+63:0] outdata_buf_next;
wire load_outdata;
wire shift_outdata;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
/************************************************************
* UCB bus interface flops
************************************************************/
assign vld = outdata_vec[0];
assign data = outdata_buf[UCB_BUS_WIDTH-1:0];
dffrl_ns #(1) stall_d1_ff (.din(stall),
.clk(clk),
.rst_l(rst_l),
.q(stall_d1));
/************************************************************
* Outbound Data
************************************************************/
// accept new data only if there is none being processed
assign load_outdata = outdata_buf_wr & ~outdata_buf_busy;
assign outdata_buf_busy = outdata_vec[0] | stall_d1;
assign shift_outdata = outdata_vec[0] & ~stall_d1;
assign outdata_vec_next =
load_outdata ? outdata_vec_in:
shift_outdata ? outdata_vec >> 1:
outdata_vec;
dffrl_ns #((REG_WIDTH+64)/UCB_BUS_WIDTH) outdata_vec_ff (.din(outdata_vec_next),
.clk(clk),
.rst_l(rst_l),
.q(outdata_vec));
assign outdata_buf_next =
load_outdata ? outdata_buf_in:
shift_outdata ? (outdata_buf >> UCB_BUS_WIDTH):
outdata_buf;
dff_ns #(REG_WIDTH+64) outdata_buf_ff (.din(outdata_buf_next),
.clk(clk),
.q(outdata_buf));
endmodule // ucb_bus_out
|
#include <bits/stdc++.h> using namespace std; int main() { int a[200]; int t, n, x; for (int i = 0; i <= 100; i++) a[i] = 0; for (int i = 0; i <= 100; i++) for (int j = 0; j <= 100; j++) { t = 3 * i + 7 * j; if (t > 100) break; a[t] = 1; } cin >> n; for (int i = 1; i <= n; i++) { cin >> x; if (a[x] == 0) cout << NO << endl; if (a[x] == 1) cout << YES << endl; } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2015 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2015.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _no_description_
// /___/ /\ Filename : OBUFDS_DPHY.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_DPHY #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter IOSTANDARD = "DEFAULT"
)(
output O,
output OB,
input HSTX_I,
input HSTX_T,
input LPTX_I_N,
input LPTX_I_P,
input LPTX_T
);
// define constants
localparam MODULE_NAME = "OBUFDS_DPHY";
// Parameter encodings and registers
localparam IOSTANDARD_DEFAULT = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_DPHY_dr.v"
`else
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
`endif
wire IOSTANDARD_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg OB_out;
reg O_out;
wire HSTX_I_in;
wire HSTX_T_in;
wire LPTX_I_N_in;
wire LPTX_I_P_in;
wire LPTX_T_in;
reg hs_mode = 1'b1;
assign (strong1,strong0) O = (hs_mode === 1'b0) ? O_out : 1'bz;
assign (strong1, strong0) OB = (hs_mode === 1'b0) ? OB_out : 1'bz;
assign (supply1,supply0) O = (hs_mode === 1'b1) ? O_out : 1'bz;
assign (supply1,supply0) OB = (hs_mode === 1'b1) ? OB_out : 1'bz;
assign HSTX_I_in = HSTX_I;
assign HSTX_T_in = HSTX_T;
assign LPTX_I_N_in = LPTX_I_N;
assign LPTX_I_P_in = LPTX_I_P;
assign LPTX_T_in = LPTX_T;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
//Commenting out the DRC check for IOSTANDARD attribute as it is not required as per IOTST.
/* initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((IOSTANDARD_REG != "DEFAULT"))) begin
$display("Error: [Unisim %s-101] IOSTANDARD attribute is set to %s. Legal values for this attribute are DEFAULT. Instance: %m", MODULE_NAME, IOSTANDARD_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
*/
always @ (LPTX_T_in or HSTX_T_in or LPTX_I_P_in or LPTX_I_N_in or HSTX_I_in) begin
if (LPTX_T_in === 1'b0) begin
O_out <= LPTX_I_P_in;
OB_out <= LPTX_I_N_in;
hs_mode <= 1'b0;
end else if (LPTX_T_in === 1'b1 && HSTX_T_in === 1'b0) begin
O_out <= HSTX_I_in;
OB_out <= ~HSTX_I_in;
hs_mode <= 1'b1;
end else begin
O_out <= 1'bz;
OB_out <= 1'bz;
hs_mode <= 1'bx;
end
end
specify
(HSTX_I => O) = (0:0:0, 0:0:0);
(HSTX_I => OB) = (0:0:0, 0:0:0);
(HSTX_T => O) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(HSTX_T => OB) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(LPTX_I_N => OB) = (0:0:0, 0:0:0);
(LPTX_I_P => O) = (0:0:0, 0:0:0);
(LPTX_T => O) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
(LPTX_T => OB) = (0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-10; const int maxn = 1000 * 1000 * 1000 + 2; int n; int a[3][5 * 100 * 1000 + 2]; long double s, e = maxn; bool check(long double x) { long double maxr = -1000000001; for (int i = 0; i < n; i++) { if (a[2][i] > 0 && (long double)(a[1][i] + (long double)(((long double)x) * ((long double)a[2][i]))) > maxr) maxr = (long double)(a[1][i] + (long double)(((long double)x) * ((long double)a[2][i]))); if (a[2][i] < 0 && maxr != -1000000001 && maxr >= (long double)(a[1][i] + (long double)(((long double)x) * ((long double)a[2][i])))) return 1; } return 0; } long double bs(long double x, long double y) { if (y - x < eps) return x; long double min = (long double)((x + y) / (long double)2.0); if (check(min)) return bs(x, min); else return bs(min, y); } int main() { cout << fixed << setprecision(12); cin >> n; for (int i = 0; i < n; i++) cin >> a[1][i] >> a[2][i]; if (!check(1000 * 1000 * 1000 + 1.0)) { cout << -1 << .00000000000000000000 << endl; return 0; } cout << bs(s, e) << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 10/22/2016 08:49:25 PM
// Design Name:
// Module Name: multiplier
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Floating Point Multiplier
//
//////////////////////////////////////////////////////////////////////////////////
module FP_Mul #(parameter P=32, biasSP=8'd127)(
input wire clk,
input wire [P-1:0] a, //Dato entrada x
input wire [P-1:0] b, //Dato entrada y
output wire [P-1:0] p //Dato de Salida
);
wire [22:0] am, bm; //Mantisa de entrada
wire [7:0] ae,be; //exponente de salida
assign am = a[22:0];
assign bm = b[22:0];
assign ae = a[30:23];
assign be = b[30:23];
reg [22:0] pm; //Mantisa de salida
reg [7:0] pe; //Exponente salida
//Registros internos
reg [47:0] pmTemp; //Mantisa
reg [7:0] peTemp; //Exponente
reg [23:0] xm; //Redondeo/Incremento
always@*
begin
pmTemp = {1'b1,am}*{1'b1,bm}; //Multiplicación mantisas
peTemp = (ae+be)-biasSP; //Suma de exponentes y resta del valor de bias
xm = pmTemp[47] ? pmTemp[46:24] : pmTemp[45:23]; //Asignar mantisa
pe = pmTemp[47] ? peTemp+1 : peTemp; //Asignar exponente
pm = xm[22:0]; //Mantisa salida
pe = xm[23] ? pe+1 : pe; //Exponente salida
end
assign p = {(a[31]^b[31]),{pe,pm}}; //Concatenación signo+exponente+mantisa
endmodule
|
#include <bits/stdc++.h> using namespace std; using int64 = long long; struct Primal_Dual { const int INF = 1 << 30; struct edge { int to, cap, cost, rev; }; vector<vector<edge> > graph; vector<int> potential, min_cost, prevv, preve; Primal_Dual(int V) : graph(V) {} void add_edge(int from, int to, int cap, int cost) { graph[from].push_back((edge){to, cap, cost, (int)graph[to].size()}); graph[to].push_back((edge){from, 0, -cost, (int)graph[from].size() - 1}); } int min_cost_flow(int s, int t, int f) { int V = graph.size(), ret = 0; priority_queue<pair<int, int>, vector<pair<int, int> >, greater<pair<int, int> > > que; potential.assign(V, 0); preve.assign(V, -1); prevv.assign(V, -1); while (f > 0) { min_cost.assign(V, INF); que.push(pair<int, int>(0, s)); min_cost[s] = 0; while (!que.empty()) { pair<int, int> p = que.top(); que.pop(); if (min_cost[p.second] < p.first) continue; for (int i = 0; i < graph[p.second].size(); i++) { edge &e = graph[p.second][i]; int nextCost = min_cost[p.second] + e.cost + potential[p.second] - potential[e.to]; if (e.cap > 0 && min_cost[e.to] > nextCost) { min_cost[e.to] = nextCost; prevv[e.to] = p.second, preve[e.to] = i; que.push(pair<int, int>(min_cost[e.to], e.to)); } } } if (min_cost[t] == INF) return -1; for (int v = 0; v < V; v++) potential[v] += min_cost[v]; int addflow = f; for (int v = t; v != s; v = prevv[v]) { addflow = min(addflow, graph[prevv[v]][preve[v]].cap); } f -= addflow; ret += addflow * potential[t]; for (int v = t; v != s; v = prevv[v]) { edge &e = graph[prevv[v]][preve[v]]; e.cap -= addflow; graph[v][e.rev].cap += addflow; } } return ret; } }; int main() { int N, B[100]; string S; cin >> N; cin >> S; int sum[26] = {}; for (int i = 0; i < N; i++) { sum[S[i] - a ]++; } for (int i = 0; i < N; i++) { cin >> B[i]; } Primal_Dual flow(N / 2 + 28); int s = N / 2 + 26, t = N / 2 + 27; for (int i = 0; i < 26; i++) { flow.add_edge(s, N / 2 + i, sum[i], 0); } for (int i = 0; i < N / 2; i++) { flow.add_edge(i, t, 2, 0); } for (int i = 0; i < N / 2; i++) { for (int j = 0; j < 26; j++) { int ret = 0; if (S[i] - a == j) ret = max(ret, B[i]); if (S[N - i - 1] - a == j) ret = max(ret, B[N - i - 1]); flow.add_edge(N / 2 + j, i, 1, -ret); } } cout << -flow.min_cost_flow(s, t, N) << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLXBN_FUNCTIONAL_PP_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxbn (
VPWR ,
VGND ,
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hs__u_dl_p_pg `UNIT_DELAY u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_FUNCTIONAL_PP_V
|
//----------------------------------------------------------------------------
//-- Prueba de tranmision 2. Transmision continua del caracter K cuando se
//-- activa la señal DTR
//----------------------------------------------------------------------------
//-- (C) BQ. September 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//--- Modulo que envia un caracter cunado load esta a 1
module baudtx2(input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
input wire load, //-- Señal de cargar / desplazamiento
output wire tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- 1 bit start + 8 bits datos + 1 bit stop
reg [9:0] shifter;
//-- Reloj para la transmision
wire clk_baud;
//-- Registro de desplazamiento, con carga paralela
//-- Cuando DTR es 0, se carga la trama
//-- Cuando DTR es 1 se desplaza hacia la derecha, y se
//-- introducen '1's por la izquierda
always @(posedge clk_baud)
if (load == 0)
shifter <= {"K",2'b01};
else
shifter <= {shifter[0], shifter[9:1]};
//-- Sacar por tx el bit menos significativo del registros de desplazamiento
//-- Cuando estamos en modo carga (dtr == 0), se saca siempre un 1 para
//-- que la linea este siempre a un estado de reposo. De esta forma en el
//-- inicio tx esta en reposo, aunque el valor del registro de desplazamiento
//-- sea desconocido
assign tx = (load) ? shifter[0] : 1;
//-- Divisor para obtener el reloj de transmision
divider #(BAUD)
BAUD0 (
.clk_in(clk),
.clk_out(clk_baud)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000009; long long modexp_recursion(long long a, long long b, long long n) { long long t = 1; if (b == 0) return 1; if (b == 1) return a % n; t = modexp_recursion(a, b >> 1, n); t = t * t % n; if (b & 0x1) { t = t * a % n; } return t; } int main() { long long n, m, k; cin >> n >> m >> k; long long a = m / (k - 1); if (a <= n - m) cout << m << endl; else { long long ret = 0; a = n - (n - m) * k; long long b = a / k; if (b > 0) { ret = 2 * k * modexp_recursion(2, b, MOD) - 2 * k; ret = ret % MOD; } ret = (ret + (n - m) * (k - 1)) % MOD; ret = (ret + (a - a / k * k)) % MOD; cout << ret << endl; } return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; template <class T> using pq = priority_queue<T>; template <class T> using pqg = priority_queue<T, vector<T>, greater<T>>; template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char* x) { cerr << << x << ; } void __print(const string& x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V>& x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T& x) { int first = 0; cerr << { ; for (auto& i : x) cerr << (first++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } const int MOD = 998244353; const char nl = n ; const int MX = 100001; struct mi { long long v; explicit operator long long() const { return v; } mi() { v = 0; } mi(long long _v) { v = (-MOD < _v && _v < MOD) ? _v : _v % MOD; if (v < 0) v += MOD; } friend bool operator==(const mi& a, const mi& b) { return a.v == b.v; } friend bool operator!=(const mi& a, const mi& b) { return !(a == b); } friend bool operator<(const mi& a, const mi& b) { return a.v < b.v; } mi& operator+=(const mi& m) { if ((v += m.v) >= MOD) v -= MOD; return *this; } mi& operator-=(const mi& m) { if ((v -= m.v) < 0) v += MOD; return *this; } mi& operator*=(const mi& m) { v = v * m.v % MOD; return *this; } mi& operator/=(const mi& m) { return (*this) *= inv(m); } friend mi pow(mi a, long long p) { mi ans = 1; assert(p >= 0); for (; p; p /= 2, a *= a) if (p & 1) ans *= a; return ans; } friend mi inv(const mi& a) { assert(a.v != 0); return pow(a, MOD - 2); } mi operator-() const { return mi(-v); } mi& operator++() { return *this += 1; } mi& operator--() { return *this -= 1; } mi operator++(int) { mi temp; temp.v = v++; return temp; } mi operator--(int) { mi temp; temp.v = v--; return temp; } friend mi operator+(mi a, const mi& b) { return a += b; } friend mi operator-(mi a, const mi& b) { return a -= b; } friend mi operator*(mi a, const mi& b) { return a *= b; } friend mi operator/(mi a, const mi& b) { return a /= b; } friend ostream& operator<<(ostream& os, const mi& m) { os << m.v; return os; } friend istream& operator>>(istream& is, mi& m) { long long x; is >> x; m.v = x; return is; } }; void __print(mi X) { cout << X.v; } int K; mi A, H; mi vals[6]; int places[6]; map<int, map<mi, vector<int>>> get(vector<int> B) { int nm = (1 << (K - 1)) - 1; map<int, map<mi, vector<int>>> res; for (int m = 0; m < (1 << nm); m++) { int p = 0; int v = K; vector<int> cur; for (int i = 0; i < ((int)(B).size()); i++) cur.push_back(i); vector<int> place((int)(B).size()); mi value = 0; while ((int)(cur).size() > 1) { vector<int> nxt; for (int i = 0; i < ((int)(cur).size() / 2); i++) { if (m & (1 << p)) { nxt.push_back(cur[i * 2]); place[cur[i * 2 + 1]] = places[v]; value += B[cur[i * 2 + 1]] * vals[v]; } else { nxt.push_back(cur[i * 2 + 1]); place[cur[i * 2]] = places[v]; value += B[cur[i * 2]] * vals[v]; } p++; } cur = nxt; v--; } place[cur[0]] = 2; value += B[cur[0]] * vals[1]; res[B[cur[0]]][value] = (place); } return res; } void solve() { cin >> K >> A >> H; vals[0] = A; for (int i = 1; i < (6); i++) { vals[i] = pow(mi(A), (pow(mi(2), i - 1) + 1).v); } places[0] = 1; places[1] = 2; places[2] = 3; places[3] = 5; places[4] = 9; places[5] = 17; vector<int> A1, A2; for (int i = 0; i < (1 << (K - 1)); i++) { A1.push_back(i + 1); A2.push_back(i + 1 + (1 << (K - 1))); } map<int, map<mi, vector<int>>> res1 = get(A1), res2 = get(A2); for (auto& a : res1) { for (auto& b : res2) { for (auto& x : a.second) { mi cur1 = x.first + a.first * vals[0] - a.first * vals[1]; if (b.second.count(H - cur1)) { vector<int> ans1 = x.second, ans2 = b.second[H - cur1]; ans1[a.first - 1] = 1; for (auto& c : ans1) cout << c << ; for (auto& c : ans2) cout << c << ; return; } mi cur2 = x.first + b.first * vals[0] - b.first * vals[1]; if (b.second.count(H - cur2)) { vector<int> ans1 = x.second, ans2 = b.second[H - cur2]; ans2[b.first - (1 << (K - 1)) - 1] = 1; for (auto& c : ans1) cout << c << ; for (auto& c : ans2) cout << c << ; return; } } } } cout << -1 << nl; } int main() { cin.tie(0)->sync_with_stdio(0); cin.exceptions(cin.failbit); int T = 1; while (T--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 110; const int M = 1010; double f[N][M * N], sum[N * M]; int a[N], n, m, s; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , a + i); s += a[i]; } f[0][0] = 1; sum[0] = 1.0; for (int j = 1; j < s; j++) sum[j] = sum[j - 1] + f[0][j]; for (int i = 1; i <= n; i++) { for (int j = i; j < s; j++) { int l = min(m, j - i + 1); int r = max(-1, j - l - 1); double tmp = sum[j - 1] - ((r == -1) ? 0 : sum[r]); if (l < a[i]) f[i][j] = tmp / (m - 1); else f[i][j] = (tmp - f[i - 1][j - a[i]]) / (m - 1); } sum[0] = 0; for (int j = 1; j < s; j++) { sum[j] = sum[j - 1] + f[i][j]; } } double ans = 0; for (int i = n; i < s; i++) { ans += f[n][i]; } printf( %.10f n , 1 + ans * (m - 1)); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 5010; int Case, n, a[N], la[N], fn[N]; int f[N][N]; int main() { scanf( %d , &Case); while (Case--) { scanf( %d , &n); for (int i = 1; i <= n; ++i) fn[i] = 0; for (int i = 1; i <= n; ++i) { scanf( %d , a + i); if (a[i] == a[i - 1]) { --i; --n; } else { la[i] = fn[a[i]]; fn[a[i]] = i; } } for (int i = n; i; --i) { for (int j = i + 1; j <= n; ++j) { f[i][j] = f[i][j - 1]; for (int k = la[j]; k >= i; k = la[k]) { f[i][j] = max(f[i][j], f[i][k] + f[k][j - 1] + 1); } } } printf( %d n , n - 1 - f[1][n]); } return 0; }
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/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 14:30:33 2016
/////////////////////////////////////////////////////////////
module FSM_Add_Subtract ( clk, rst, rst_FSM, beg_FSM, zero_flag_i,
norm_iteration_i, add_overflow_i, round_i, load_1_o, load_2_o,
load_3_o, load_8_o, A_S_op_o, load_4_o, left_right_o, bit_shift_o,
load_5_o, load_6_o, load_7_o, ctrl_a_o, ctrl_b_o, ctrl_b_load_o,
ctrl_c_o, ctrl_d_o, rst_int, ready );
output [1:0] ctrl_b_o;
input clk, rst, rst_FSM, beg_FSM, zero_flag_i, norm_iteration_i,
add_overflow_i, round_i;
output load_1_o, load_2_o, load_3_o, load_8_o, A_S_op_o, load_4_o,
left_right_o, bit_shift_o, load_5_o, load_6_o, load_7_o, ctrl_a_o,
ctrl_b_load_o, ctrl_c_o, ctrl_d_o, rst_int, ready;
wire n1, n2, n4, ctrl_d_o, n7, n8, n9, n10, n11, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56;
wire [3:0] state_reg;
assign ctrl_a_o = ctrl_d_o;
INVX2TS U3 ( .A(rst), .Y(n1) );
DFFRX2TS \state_reg_reg[2] ( .D(n53), .CK(clk), .RN(n1), .Q(state_reg[2]),
.QN(n15) );
DFFRX2TS \state_reg_reg[3] ( .D(n55), .CK(clk), .RN(n1), .Q(state_reg[3]),
.QN(n9) );
DFFRX2TS \state_reg_reg[1] ( .D(n54), .CK(clk), .RN(n1), .Q(state_reg[1]),
.QN(n16) );
DFFRX2TS \state_reg_reg[0] ( .D(n56), .CK(clk), .RN(n1), .Q(state_reg[0]),
.QN(n17) );
NOR3BX1TS U67 ( .AN(n45), .B(n17), .C(state_reg[1]), .Y(n25) );
NOR2X1TS U68 ( .A(n16), .B(state_reg[3]), .Y(n51) );
NAND3X1TS U69 ( .A(n16), .B(n9), .C(n49), .Y(n41) );
NAND3X1TS U70 ( .A(n16), .B(n9), .C(n50), .Y(n32) );
NAND3X1TS U71 ( .A(state_reg[1]), .B(n17), .C(n45), .Y(n29) );
NAND3X1TS U72 ( .A(state_reg[1]), .B(n49), .C(state_reg[3]), .Y(n20) );
NAND2X1TS U73 ( .A(n43), .B(n27), .Y(load_5_o) );
INVX2TS U74 ( .A(n43), .Y(ctrl_c_o) );
OAI21X1TS U75 ( .A0(n32), .A1(n18), .B0(n24), .Y(n36) );
OAI21X1TS U76 ( .A0(n18), .A1(n41), .B0(n33), .Y(load_8_o) );
INVX2TS U77 ( .A(n28), .Y(ctrl_d_o) );
INVX2TS U78 ( .A(n22), .Y(n10) );
NOR3X1TS U79 ( .A(load_2_o), .B(load_1_o), .C(load_7_o), .Y(n31) );
NAND2X1TS U80 ( .A(n51), .B(n49), .Y(n43) );
NAND2X1TS U81 ( .A(n50), .B(n51), .Y(n27) );
NAND2X1TS U82 ( .A(n44), .B(n29), .Y(ctrl_b_load_o) );
NAND2X1TS U83 ( .A(n32), .B(n24), .Y(load_4_o) );
NAND3X1TS U84 ( .A(n41), .B(n42), .C(n33), .Y(load_3_o) );
INVX2TS U85 ( .A(n40), .Y(load_2_o) );
INVX2TS U86 ( .A(n41), .Y(n4) );
INVX2TS U87 ( .A(n39), .Y(rst_int) );
INVX2TS U88 ( .A(n44), .Y(load_6_o) );
INVX2TS U89 ( .A(n20), .Y(ready) );
INVX2TS U90 ( .A(n32), .Y(n8) );
INVX2TS U91 ( .A(n29), .Y(n7) );
NAND2X1TS U92 ( .A(round_i), .B(n25), .Y(n28) );
NAND4X1TS U93 ( .A(add_overflow_i), .B(n31), .C(n46), .D(n47), .Y(A_S_op_o)
);
NOR4XLTS U94 ( .A(n48), .B(ctrl_b_load_o), .C(load_5_o), .D(load_4_o), .Y(
n47) );
AOI211X1TS U95 ( .A0(n4), .A1(n18), .B0(n50), .C0(n25), .Y(n46) );
NAND3X1TS U96 ( .A(n20), .B(n39), .C(n42), .Y(n48) );
INVX2TS U97 ( .A(norm_iteration_i), .Y(n18) );
NOR2BX1TS U98 ( .AN(ctrl_b_load_o), .B(add_overflow_i), .Y(ctrl_b_o[0]) );
OA21XLTS U99 ( .A0(n36), .A1(load_8_o), .B0(add_overflow_i), .Y(bit_shift_o)
);
OAI2BB1X1TS U100 ( .A0N(load_6_o), .A1N(add_overflow_i), .B0(n29), .Y(
ctrl_b_o[1]) );
AOI211X1TS U101 ( .A0(n41), .A1(n32), .B0(n18), .C0(add_overflow_i), .Y(
left_right_o) );
AOI21X1TS U102 ( .A0(load_2_o), .A1(zero_flag_i), .B0(load_7_o), .Y(n22) );
OAI22X1TS U103 ( .A0(beg_FSM), .A1(n39), .B0(rst_FSM), .B1(n20), .Y(n26) );
NAND4BX1TS U104 ( .AN(load_5_o), .B(n33), .C(n34), .D(n35), .Y(n55) );
AOI21X1TS U105 ( .A0(n25), .A1(n19), .B0(n7), .Y(n34) );
AOI211X1TS U106 ( .A0(state_reg[3]), .A1(n26), .B0(n36), .C0(n10), .Y(n35)
);
INVX2TS U107 ( .A(round_i), .Y(n19) );
NAND4X1TS U108 ( .A(n27), .B(n28), .C(n29), .D(n30), .Y(n54) );
AOI221X1TS U109 ( .A0(n8), .A1(n18), .B0(state_reg[1]), .B1(n26), .C0(n11),
.Y(n30) );
INVX2TS U110 ( .A(n31), .Y(n11) );
AOI31X1TS U111 ( .A0(n37), .A1(n2), .A2(n38), .B0(n26), .Y(n56) );
NOR3X1TS U112 ( .A(n25), .B(rst_int), .C(n4), .Y(n38) );
AOI2BB1X1TS U113 ( .A0N(n40), .A1N(zero_flag_i), .B0(n7), .Y(n37) );
INVX2TS U114 ( .A(n36), .Y(n2) );
NOR2X1TS U115 ( .A(n15), .B(state_reg[0]), .Y(n49) );
NOR2X1TS U116 ( .A(n9), .B(state_reg[2]), .Y(n45) );
NOR2X1TS U117 ( .A(n17), .B(n15), .Y(n50) );
NOR3X1TS U118 ( .A(state_reg[2]), .B(state_reg[3]), .C(state_reg[1]), .Y(n52) );
NAND3X1TS U119 ( .A(n17), .B(n16), .C(n45), .Y(n44) );
NAND3X1TS U120 ( .A(state_reg[0]), .B(state_reg[1]), .C(n45), .Y(n33) );
NAND3X1TS U121 ( .A(n51), .B(n15), .C(state_reg[0]), .Y(n42) );
NAND2X1TS U122 ( .A(n52), .B(n17), .Y(n39) );
NAND3X1TS U123 ( .A(n17), .B(n15), .C(n51), .Y(n40) );
NAND3X1TS U124 ( .A(n49), .B(n16), .C(state_reg[3]), .Y(n24) );
AND3X2TS U125 ( .A(n50), .B(state_reg[3]), .C(n16), .Y(load_7_o) );
NAND3X1TS U126 ( .A(n21), .B(n22), .C(n23), .Y(n53) );
NOR4BX1TS U127 ( .AN(n24), .B(load_3_o), .C(load_6_o), .D(n25), .Y(n23) );
AOI22X1TS U128 ( .A0(n8), .A1(n18), .B0(state_reg[2]), .B1(n26), .Y(n21) );
AND2X2TS U129 ( .A(n52), .B(state_reg[0]), .Y(load_1_o) );
endmodule
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#include <bits/stdc++.h> using namespace std; long long a[1000006]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); long long score = 0; for (int i = 0; i < n - 1; i++) score += 1ll * (i + 2) * a[i]; score += a[n - 1] * n; cout << score << endl; return 0; }
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module reg_128x32b_3r_2w_fpga
(/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
clk, rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr1_addr, wr0_en,
wr1_en, wr0_data, wr1_data
);
input clk;
output [31:0] rd0_data;
output [31:0] rd1_data;
output [31:0] rd2_data;
input [6:0] rd0_addr;
input [6:0] rd1_addr;
input [6:0] rd2_addr;
input [6:0] wr0_addr;
input [6:0] wr1_addr;
input wr0_en;
input wr1_en;
input [31:0] wr0_data;
input [31:0] wr1_data;
wire [6:0] wr_addr;
wire [9:0] wr_addr_blk;
wire wr_en;
wire [31:0] wr_data;
wire [9:0] rd0_addr_blk;
wire [9:0] rd1_addr_blk;
wire [9:0] rd2_addr_blk;
assign rd0_addr_blk = {3'b000, rd0_addr};
assign rd1_addr_blk = {3'b000, rd1_addr};
assign rd2_addr_blk = {3'b000, rd2_addr};
assign wr_data = wr1_en ? wr1_data : wr0_data;
assign wr_addr = wr1_en ? wr1_addr : wr0_addr;
assign wr_addr_blk = {3'b000, wr_addr};
assign wr_en = wr0_en | wr1_en;
block_ram bank0(
.clka(clk), // input clka
//.rsta(rst), // input rsta
.wea(wr_en), // input [3 : 0] wea
.addra(wr_addr_blk), // input [31 : 0] addra
.dina(wr_data), // input [31 : 0] dina
.douta(), // output [31 : 0] douta
.clkb(clk), // input clkb
//.rstb(rst), // input rstb
.web(1'b0), // input [3 : 0] web
.addrb(rd0_addr_blk), // input [31 : 0] addrb
.dinb(32'd0), // input [31 : 0] dinb
.doutb(rd0_data) // output [31 : 0] doutb
);
block_ram bank1(
.clka(clk), // input clka
//.rsta(rst), // input rsta
.wea(wr_en), // input [3 : 0] wea
.addra(wr_addr_blk), // input [31 : 0] addra
.dina(wr_data), // input [31 : 0] dina
.douta(), // output [31 : 0] douta
.clkb(clk), // input clkb
//.rstb(rst), // input rstb
.web(1'b0), // input [3 : 0] web
.addrb(rd1_addr_blk), // input [31 : 0] addrb
.dinb(32'd0), // input [31 : 0] dinb
.doutb(rd1_data) // output [31 : 0] doutb
);
block_ram bank2(
.clka(clk), // input clka
//.rsta(rst), // input rsta
.wea(wr_en), // input [3 : 0] wea
.addra(wr_addr_blk), // input [31 : 0] addra
.dina(wr_data), // input [31 : 0] dina
.douta(), // output [31 : 0] douta
.clkb(clk), // input clkb
//.rstb(rst), // input rstb
.web(1'b0), // input [3 : 0] web
.addrb(rd2_addr_blk), // input [31 : 0] addrb
.dinb(32'd0), // input [31 : 0] dinb
.doutb(rd2_data) // output [31 : 0] doutb
);
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 3e4 + 7, M = 2e2 + 7; bool fl[N]; int n, k, tot, fs[N], sum[N], pos[M], f[M][N]; map<int, bool> s[N]; struct edge { int u, v; } ed[N * M]; struct node { int ch[M], num; } qt[N]; inline int read() { int num = 0; char g = getchar(); while (g < 48 || 57 < g) g = getchar(); while (47 < g && g < 58) num = (num << 1) + (num << 3) + g - 48, g = getchar(); return num; } inline int find(int u) { if (fs[u] == u) return u; return fs[u] = find(fs[u]); } inline bool equals(node a, node b) { for (int i = 1; i <= k; i++) if (a.ch[i] + 1 != b.ch[i]) return false; return true; } inline bool cmp(node a, node b) { for (int i = 1; i <= k; i++) { if (a.ch[i] < b.ch[i]) return false; if (a.ch[i] > b.ch[i]) return true; } return false; } int main() { n = read(), k = read(); for (int i = 1; i <= k; i++) for (int x = 1; x <= n; x++) f[i][x] = read(); for (int i = 1; i <= k; i++) for (int x = 1; x <= n; x++) if (!f[i][x]) pos[i] = x; for (int i = 2; i <= k; i++) { memset(sum, 0, sizeof(sum)); for (int c = 1; c <= n; c++) if (f[i][c] + f[1][c] == f[1][pos[i]]) sum[f[1][c]] = c; for (int c = 0; c <= f[1][pos[i]]; c++) if (!sum[c]) { puts( -1 ); return 0; } for (int c = 0; c < f[1][pos[i]]; c++) if (!s[sum[c]][sum[c + 1]]) s[sum[c]][sum[c + 1]] = s[sum[c + 1]][sum[c]] = 1, ed[++tot].u = sum[c], ed[tot].v = sum[c + 1]; } for (int i = 1; i <= n; i++) fs[i] = i; for (int i = 1; i <= tot; i++) { int a = ed[i].u, b = ed[i].v; fl[a] = fl[b] = 1, fs[a] = find(a), fs[b] = find(b); if (fs[a] == fs[b]) { puts( -1 ); return 0; } fs[fs[a]] = find(b); } int tp = 1; for (int x = 1; x <= n; x++) { qt[x].num = x; for (int i = 1; i <= k; i++) qt[x].ch[i] = f[i][x]; } for (int i = 1; i <= k; i++) fl[pos[i]] = 1; sort(qt + 1, qt + n + 1, cmp); for (int i = 1; i <= n; i++) { int c = qt[i].num; if (fl[c]) continue; while ((!equals(qt[tp], qt[i])) && tp <= n) tp++; if (tp > n) { puts( -1 ); return 0; } tot++, ed[tot].u = c, ed[tot].v = qt[tp].num; } for (int i = 1; i <= tot; i++) printf( %d %d n , ed[i].u, ed[i].v); return 0; }
|
`timescale 1ns/1ps
`include "../global.v"
module ExpRegisterFile_tb();
parameter HCP = 10; //half clock period
reg clk, reset;
reg writeEnableA, writeEnableB;
reg [8:0] writeValueA, writeValueB;
reg [2:0] readSelectA, readSelectB;
wire [8:0] readResultA, readResultB;
defparam DUT.REGISTER_WIDTH = 9;
RegisterFile DUT(clk, reset, writeEnableA, writeEnableB, writeValueA, writeValueB, readSelectA, readSelectB, readResultA, readResultB);
initial forever begin
#HCP clk = ~clk;
end
initial begin
clk = 0;
reset = 1;
writeEnableA = 1'b1;
writeEnableB = 1'b0;
writeValueA = 9'h0AA;
writeValueB = 9'h0EE;
readSelectA = 3'b000;
readSelectB = 3'b001;
#(2*HCP) reset = 0;
#(2*HCP) writeEnableA = 1'b0;
writeEnableB = 1'b1;
writeValueA = 9'h0EE;
writeValueB = 9'h0BB;
#(2*HCP) readSelectA = 3'b001;
readSelectB = 3'b000;
#(2*HCP) readSelectA = 3'b010;
readSelectB = 3'b011;
#(2*HCP) readSelectA = 3'b100;
readSelectB = 3'b101;
#(2*HCP) readSelectA = 3'b110;
readSelectB = 3'b111;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long nax = 100001; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(n); for (auto& x : a) { cin >> x; } if (a[0]) { cout << n + 1 << ; for (int i = 1; i <= n; ++i) { cout << i << ; } cout << n ; continue; } if (!a.back()) { for (int i = 1; i <= n + 1; ++i) { cout << i << ; } cout << n ; continue; } for (int i = 0; i < n - 1; ++i) { if (a[i] == 0 && a[i + 1] == 1) { for (int j = 1; j <= i + 1; ++j) { cout << j << ; } cout << n + 1 << ; for (int j = i + 2; j <= n; ++j) { cout << j << ; } cout << n ; break; } } } }
|
#include <bits/stdc++.h> using namespace std; int main(void) { int level[26]; for (int i = 0; i < 26; i++) cin >> level[i]; string s; cin >> s; long long ans = 0; for (char ch = a ; ch <= z ; ch++) { map<long long, long long> m; long long sum = 0; for (int i = 0; i < s.length(); i++) { sum += level[s[i] - a ]; if (s[i] == ch) ans += m[sum - level[ch - a ]], m[sum]++; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, a[102], b[102]; int main(void) { scanf( %d %d , &n, &m); for (int i = 0; i < m; ++i) scanf( %d %d , &a[i], &b[i]); for (int x = 1; x <= n; ++x) { int c = 0; for (int i = 0; i < m; ++i) if (x >= a[i] && x <= b[i]) ++c; if (c != 1) { printf( %d %d n , x, c); return 0; } } puts( OK ); return 0; }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module clips video streams on the DE boards. If the incoming image is *
* the wrong size, the circuit will discard or add pixels as necessary. *
* *
******************************************************************************/
module altera_up_video_clipper_drop (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Image's Data Width
parameter EW = 0; // Image's Empty Width
parameter IMAGE_WIDTH = 640; // Image in width in pixels
parameter IMAGE_HEIGHT = 480; // Image in height in lines
parameter WW = 9; // Image in width address width
parameter HW = 8; // Image in height address width
parameter DROP_PIXELS_AT_START = 0;
parameter DROP_PIXELS_AT_END = 0;
parameter DROP_LINES_AT_START = 0;
parameter DROP_LINES_AT_END = 0;
parameter ADD_DATA = 16'h0; // Data for added pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EW: 0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam STATE_0_WAIT_FOR_START = 2'h0,
STATE_1_RUN_CLIPPER = 2'h1,
STATE_2_ADD_MISSING_PART = 2'h2;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire increment_counters;
wire full_frame_endofpacket;
wire new_startofpacket;
wire new_endofpacket;
wire pass_inner_frame;
// Internal Registers
// State Machine Registers
reg [ 1: 0] s_video_clipper_drop;
reg [ 1: 0] ns_video_clipper_drop;
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
s_video_clipper_drop <= STATE_0_WAIT_FOR_START;
else
s_video_clipper_drop <= ns_video_clipper_drop;
end
always @(*)
begin
case (s_video_clipper_drop)
STATE_0_WAIT_FOR_START:
begin
if (stream_in_startofpacket & stream_in_valid)
ns_video_clipper_drop = STATE_1_RUN_CLIPPER;
else
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
end
STATE_1_RUN_CLIPPER:
begin
if (increment_counters & full_frame_endofpacket)
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
else if (increment_counters & stream_in_endofpacket)
ns_video_clipper_drop = STATE_2_ADD_MISSING_PART;
else
ns_video_clipper_drop = STATE_1_RUN_CLIPPER;
end
STATE_2_ADD_MISSING_PART:
begin
if (increment_counters & full_frame_endofpacket)
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
else
ns_video_clipper_drop = STATE_2_ADD_MISSING_PART;
end
default:
begin
ns_video_clipper_drop = STATE_0_WAIT_FOR_START;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
if (s_video_clipper_drop == STATE_2_ADD_MISSING_PART)
stream_out_data <= ADD_DATA;
else
stream_out_data <= stream_in_data;
stream_out_startofpacket <= new_startofpacket;
stream_out_endofpacket <= new_endofpacket;
stream_out_empty <= stream_in_empty;
if (s_video_clipper_drop == STATE_1_RUN_CLIPPER)
stream_out_valid <= pass_inner_frame & stream_in_valid;
else if (s_video_clipper_drop == STATE_2_ADD_MISSING_PART)
stream_out_valid <= pass_inner_frame;
else
stream_out_valid <= 1'b0;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready =
(s_video_clipper_drop == STATE_0_WAIT_FOR_START) ?
~(stream_in_startofpacket & stream_in_valid) :
(s_video_clipper_drop == STATE_1_RUN_CLIPPER) ?
~pass_inner_frame | stream_out_ready | ~stream_out_valid :
1'b0;
// Internal Assignments
assign increment_counters =
(s_video_clipper_drop == STATE_1_RUN_CLIPPER) ?
stream_in_valid & stream_in_ready :
(s_video_clipper_drop == STATE_2_ADD_MISSING_PART) ?
~pass_inner_frame | stream_out_ready | ~stream_out_valid :
1'b0;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_clipper_counters Clipper_Drop_Counters (
// Inputs
.clk (clk),
.reset (reset),
.increment_counters (increment_counters),
// Bi-Directional
// Outputs
.start_of_outer_frame (),
.end_of_outer_frame (full_frame_endofpacket),
.start_of_inner_frame (new_startofpacket),
.end_of_inner_frame (new_endofpacket),
.inner_frame_valid (pass_inner_frame)
);
defparam
Clipper_Drop_Counters.IMAGE_WIDTH = IMAGE_WIDTH,
Clipper_Drop_Counters.IMAGE_HEIGHT = IMAGE_HEIGHT,
Clipper_Drop_Counters.WW = WW,
Clipper_Drop_Counters.HW = HW,
Clipper_Drop_Counters.LEFT_OFFSET = DROP_PIXELS_AT_START,
Clipper_Drop_Counters.RIGHT_OFFSET = DROP_PIXELS_AT_END,
Clipper_Drop_Counters.TOP_OFFSET = DROP_LINES_AT_START,
Clipper_Drop_Counters.BOTTOM_OFFSET = DROP_LINES_AT_END;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[40005]; int main() { int i, j; int n, m, x; while (scanf( %d %d , &n, &m) != EOF) { if ((n == 1 || n == 2) && m == 1) { printf( -1 n ); continue; } if (n < (2 * m + 1)) { if (m == 1) { printf( %d n , n * m); for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { x = i + j; if (x > n) { x = x - n; } printf( %d %d n , i, x); } } } else printf( -1 n ); continue; } printf( %d n , n * m); for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { x = i + j; if (x > n) { x = x - n; } printf( %d %d n , i, x); } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int T, a, b, c, i, count = 0; cin >> T; for (i = 0; i < T; i++) { cin >> a >> b >> c; if ((a + b + c) >= 2) { count++; } } cout << count << n ; return 0; }
|
module etx_io (/*AUTOARG*/
// Outputs
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, tx_wr_wait, tx_rd_wait,
// Inputs
tx_lclk_io, tx_lclk_div4, tx_lclk90, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, tx_data_slow, tx_frame_slow
);
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 0; // 0 = parallella
// 1 = ephycard
//###########
//# reset, clocks
//##########
input tx_lclk_io; //fast ODDR
input tx_lclk_div4; //slow clock
input tx_lclk90; //fast 90deg shifted lclk
//###########
//# eLink pins
//###########
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx read pushback
//#############
//# Fabric interface
//#############
input [63:0] tx_data_slow; //data for burst or transaction
input [3:0] tx_frame_slow; //framing signal
output tx_wr_wait;
output tx_rd_wait;
//############
//# REGS
//############
reg [63:0] tx_data;
reg [3:0] tx_frame;
wire [15:0] tx_data16;
wire tx_frame16;
reg tx_wr_wait_sync;
reg tx_rd_wait_sync;
reg tx_wr_wait_reg;
reg tx_rd_wait_reg;
reg tx_wr_wait_reg2;
reg tx_rd_wait_reg2;
//############
//# WIRES
//############
wire [15:0] tx_data_mux;
wire txo_frame_ddr;
wire txo_lclk90;
wire tx_wr_wait_async;
wire tx_rd_wait_async;
wire [7:0] txo_data_ddr;
wire invert_pins;
//#########################################
//# Pins inverted for 64-core board
//#########################################
`ifdef TARGET_E64
assign invert_pins=1'b1;
`else
assign invert_pins=1'b0;
`endif
//#########################################
//# Synchronizatsion to fast domain
//#########################################
//Find the aligned edge
oh_edgealign edgealign0 (.firstedge (firstedge),
.fastclk (tx_lclk_io),
.slowclk (tx_lclk_div4)
);
//Data shift registers
always @ (posedge tx_lclk_io)
if(firstedge) //"load"
begin
tx_data[63:0] <= tx_data_slow[63:0]; //changes every 4 cycles
tx_frame[3:0] <= tx_frame_slow[3:0];
end
else //"shift"
begin
tx_data[63:0] <= {16'b0,tx_data[63:16]};
tx_frame[3:0] <= {tx_frame[2:0],1'b0};
end
assign tx_data16[15:0] = tx_data[15:0];
assign tx_frame16 = tx_frame[3];
//##############################################
//# Wait signal synchronization
//##############################################
always @ (negedge tx_lclk_io)
begin
tx_wr_wait_sync <= tx_wr_wait_async ^ invert_pins;
tx_rd_wait_sync <= tx_rd_wait_async ^ invert_pins;
end
//Looks like legacy elink puts out short wait pulses.
//Let's make sure they don't sneak through
always @ (posedge tx_lclk_div4)
begin
tx_wr_wait_reg <= tx_wr_wait_sync;
tx_wr_wait_reg2 <= tx_wr_wait_reg;
tx_rd_wait_reg <= tx_rd_wait_sync;
tx_rd_wait_reg2 <= tx_rd_wait_reg;
end
assign tx_wr_wait = tx_wr_wait_reg | tx_wr_wait_reg2;
assign tx_rd_wait = tx_rd_wait_reg | tx_rd_wait_reg2;
//############################################
//# IO DRIVER STUFF
//############################################
//DATA
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_data (
.Q (txo_data_ddr[i]),
.C (tx_lclk_io),
.CE (1'b1),
.D1 (tx_data16[i+8] ^ invert_pins),
.D2 (tx_data16[i] ^ invert_pins),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
//FRAME
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_frame (
.Q (txo_frame_ddr),
.C (tx_lclk_io),
.CE (1'b1),
.D1 (tx_frame16 ^ invert_pins),
.D2 (tx_frame16 ^ invert_pins),
.R (1'b0), //reset
.S (1'b0)
);
//LCLK
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_lclk (
.Q (txo_lclk90),
.C (tx_lclk90),
.CE (1'b1),
.D1 (1'b1 ^ invert_pins),
.D2 (1'b0 ^ invert_pins),
.R (1'b0),//should be no reason to reset clock, static input
.S (1'b0)
);
//Buffer drivers
OBUFDS obufds_data[7:0] (
.O (txo_data_p[7:0]),
.OB (txo_data_n[7:0]),
.I (txo_data_ddr[7:0])
);
OBUFDS obufds_frame ( .O (txo_frame_p),
.OB (txo_frame_n),
.I (txo_frame_ddr)
);
OBUFDS obufds_lclk ( .O (txo_lclk_p),
.OB (txo_lclk_n),
.I (txo_lclk90)
);
//Wait inputs
generate
if(ETYPE==1)
begin
assign tx_wr_wait_async = txi_wr_wait_p;
end
else if (ETYPE==0)
begin
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_wrwait
(.I (txi_wr_wait_p),
.IB (txi_wr_wait_n),
.O (tx_wr_wait_async));
end
endgenerate
//TODO: Come up with cleaner defines for this
`ifdef TODO
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rdwait
(.I (txi_rd_wait_p),
.IB (txi_rd_wait_n),
.O (tx_rd_wait_async));
`else
//On Parallella this signal comes in single-ended
assign tx_rd_wait_async = txi_rd_wait_p;
`endif
endmodule // etx_io
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1P_BEHAVIORAL_V
`define SKY130_FD_SC_LP__INPUTISO1P_BEHAVIORAL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inputiso1p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1P_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int K, P, cd; int cal(int ct, vector<pair<int, int> > vt) { int t = vt.size(), res = 0; for (int st = 1; st < (1 << t); st++) { int val = 1, sl = 0; for (int j = 0; j < t; j++) { if ((st >> j) % 2 == 1) val *= vt[j].first, sl++; } if (sl % 2 == 0) res -= ct / val; else res += ct / val; } return ct - res; } void solve() { vector<pair<int, int> > vt; int x = P; for (int i = 2; i * i <= P; i++) { if (x % i == 0) { int t = 0; while (x % i == 0) t++, x /= i; vt.push_back(pair<int, int>(i, t)); } } if (x > 1) vt.push_back(pair<int, int>(x, 1)); int t = vt.size(); int res0 = cal(cd, vt), r = 10000000, l = cd; int ans; while (1) { int mid = (l + r) / 2; int v = cal(mid, vt) - res0; if (v == K) { ans = mid; break; } if (v > K) { r = mid - 1; } else l = mid + 1; } while (1) { int ok = 1; for (int j = 0; j < vt.size(); j++) { if (ans % vt[j].first == 0) { ok = 0; break; } } if (ok) break; else ans--; } cout << ans << endl; } int main() { int T; cin >> T; for (int i = 0; i < T; i++) { cin >> cd >> P >> K; solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVER_BLACKBOX_V
/**
* busdriver: Bus driver (pmoshvt devices).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdriver (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; inline int read() { int s = 0, w = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) w |= (ch == - ), ch = getchar(); while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return w ? -s : s; } struct rr { int nt, to; } bl[100005 << 1]; int hd[100005], itot = 0; inline void adde(int x, int y) { bl[++itot] = (rr){hd[x], y}; hd[x] = itot; bl[++itot] = (rr){hd[y], x}; hd[y] = itot; return; } vector<int> to[100005]; int belong[100005], cnt = 0, sz[100005]; int dfn[100005], low[100005], num = 0, stk[100005], top = 0; int vis[100005]; void tarjan(int u, int fa) { dfn[u] = low[u] = ++num; stk[++top] = u; vis[u] = 1; for (int i = hd[u], y; i; i = bl[i].nt) if ((y = bl[i].to) != fa && vis[y] != 2) { if (!dfn[y]) { tarjan(y, u); low[u] = min(low[u], low[y]); } else low[u] = min(low[u], dfn[y]); } if (dfn[u] == low[u]) { int z; ++cnt; do { z = stk[top--]; belong[z] = cnt; sz[cnt]++; vis[z] = 2; } while (z != u); } return; } int n, m; int dist[100005], sd[100005]; int f[100005][20], LOG[100005]; inline int LCA(int x, int y) { if (sd[x] < sd[y]) swap(x, y); for (int j = LOG[sd[x]]; j >= 0; --j) if (f[x][j] && sd[f[x][j]] >= sd[y]) x = f[x][j]; if (x == y) return x; for (int j = LOG[sd[x]]; j >= 0; --j) if (f[x][j] && f[y][j] && f[x][j] != f[y][j]) x = f[x][j], y = f[y][j]; return f[x][0]; } void dfs(int u, int fa) { dist[u] = dist[fa] + (sz[u] != 1); sd[u] = sd[fa] + 1; f[u][0] = fa; for (int j = 1; j <= LOG[sd[u]]; ++j) f[u][j] = f[f[u][j - 1]][j - 1]; for (int i = 0; i < to[u].size(); ++i) if (to[u][i] != fa) dfs(to[u][i], u); return; } int bin[100005]; int main() { n = (read()), m = (read()); bin[0] = 1, bin[1] = 2; for (int i = 2; i <= n; ++i) { LOG[i] = LOG[i >> 1] + 1; bin[i] = bin[i - 1] + bin[i - 1]; if (bin[i] >= mod) bin[i] -= mod; } for (int i = 1, x, y; i <= m; ++i) x = (read()), y = (read()), adde(x, y); tarjan(1, 0); for (int i = 1; i <= n; ++i) for (int j = hd[i], y; j; j = bl[j].nt) if (belong[i] != belong[y = bl[j].to]) to[belong[i]].push_back(belong[y]); dfs(1, 0); int q = (read()), x, y; while (q--) { x = belong[(read())], y = belong[(read())]; int lca = LCA(x, y); printf( %d n , bin[dist[x] + dist[y] - dist[lca] - dist[f[lca][0]]]); } return 0; }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:42:40 06/01/2015
// Design Name:
// Module Name: scancode_to_speccy
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module scancode_to_sam (
input wire clk, // el mismo clk de ps/2
input wire rst,
input wire scan_received,
input wire [7:0] scan,
input wire extended,
input wire released,
input wire kbclean,
//------------------------
input wire [8:0] sam_row,
output wire [7:0] sam_col,
output wire user_reset,
output wire master_reset,
output wire user_nmi,
output wire [1:0] user_toggles,
//------------------------
input wire [7:0] din,
output reg [7:0] dout,
input wire cpuwrite,
input wire cpuread,
input wire rewind
);
// las teclas del SAM. Se inicializan a "no pulsadas".
reg [7:0] row[0:8];
initial begin
row[0] = 8'hFF;
row[1] = 8'hFF;
row[2] = 8'hFF;
row[3] = 8'hFF;
row[4] = 8'hFF;
row[5] = 8'hFF;
row[6] = 8'hFF;
row[7] = 8'hFF;
row[8] = 8'hFF;
end
// El gran mapa de teclado y sus registros de acceso
reg [7:0] keymap[0:16383]; // 16K x 8 bits
reg [13:0] addr = 14'h0000;
reg [13:0] cpuaddr = 14'h0000; // Dirección E/S desde la CPU. Se autoincrementa en cada acceso
initial begin
$readmemh ("keyb_es_hex.txt", keymap);
end
reg [3:0] keyrow1 = 4'h0;
reg [7:0] keycol1 = 8'h00;
reg [3:0] keyrow2 = 4'h0;
reg [7:0] keycol2 = 8'h00;
reg [2:0] keymodifiers = 3'b000;
reg [2:0] signalstate = 3'b000;
reg [1:0] togglestate = 2'b00;
reg rmaster_reset = 1'b0, ruser_reset = 1'b0, ruser_nmi = 1'b0;
reg [1:0] ruser_toggles = 2'b00;
assign master_reset = rmaster_reset;
assign user_reset = ruser_reset;
assign user_nmi = ruser_nmi;
assign user_toggles = ruser_toggles;
// Asi funciona la matriz de teclado cuando se piden semifilas
// desde la CPU.
// Un always @* hubiera quedado más claro en la descripción
// pero por algun motivo, el XST no lo ha admitido en este caso
assign sam_col = ((sam_row[0] == 1'b0)? row[0] : 8'hFF) &
((sam_row[1] == 1'b0)? row[1] : 8'hFF) &
((sam_row[2] == 1'b0)? row[2] : 8'hFF) &
((sam_row[3] == 1'b0)? row[3] : 8'hFF) &
((sam_row[4] == 1'b0)? row[4] : 8'hFF) &
((sam_row[5] == 1'b0)? row[5] : 8'hFF) &
((sam_row[6] == 1'b0)? row[6] : 8'hFF) &
((sam_row[7] == 1'b0)? row[7] : 8'hFF) &
((sam_row[8] == 1'b0)? row[8] : 8'hFF);
reg [2:0] modifiers = 3'b000;
reg [3:0] keycount = 4'b0000;
parameter
CLEANMATRIX = 4'd0,
IDLE = 4'd1,
ADDR0PUT = 4'd2,
ADDR1PUT = 4'd3,
ADDR2PUT = 4'd4,
ADDR3PUT = 4'd5,
TRANSLATE1 = 4'd6,
TRANSLATE2 = 4'd7,
TRANSLATE3 = 4'd8,
CPUTIME = 4'd9,
CPUREAD = 4'd10,
CPUWRITE = 4'd11,
CPUINCADD = 4'd12,
UPDCOUNTERS1= 4'd13,
UPDCOUNTERS2= 4'd14;
reg [3:0] state = CLEANMATRIX;
reg key_is_pending = 1'b0;
always @(posedge clk) begin
if (scan_received == 1'b1)
key_is_pending <= 1'b1;
if (rst == 1'b1 || (kbclean == 1'b1 && state == IDLE && scan_received == 1'b0))
state <= CLEANMATRIX;
else begin
case (state)
CLEANMATRIX: begin
modifiers <= 3'b000;
keycount <= 4'b0000;
row[0] <= 8'hFF;
row[1] <= 8'hFF;
row[2] <= 8'hFF;
row[3] <= 8'hFF;
row[4] <= 8'hFF;
row[5] <= 8'hFF;
row[6] <= 8'hFF;
row[7] <= 8'hFF;
row[8] <= 8'hFF;
state <= IDLE;
end
IDLE: begin
if (key_is_pending == 1'b1) begin
addr <= {modifiers, extended, scan, 2'b00}; // 1 scan tiene 8 bits + 1 bit para indicar scan extendido + 3 bits para el modificador usado
state <= ADDR0PUT;
key_is_pending <= 1'b0;
end
else if (cpuread == 1'b1 || cpuwrite == 1'b1 || rewind == 1'b1)
state <= CPUTIME;
end
ADDR0PUT: begin
{keyrow1,keycol1[7:4]} <= keymap[addr];
addr <= {modifiers, extended, scan, 2'b01};
state <= ADDR1PUT;
end
ADDR1PUT: begin
{keycol1[3:0],keyrow2} <= keymap[addr];
addr <= {modifiers, extended, scan, 2'b10};
state <= ADDR2PUT;
end
ADDR2PUT: begin
{keycol2} <= keymap[addr];
addr <= {modifiers, extended, scan, 2'b11};
state <= ADDR3PUT;
end
ADDR3PUT: begin
{signalstate,keymodifiers,togglestate} <= keymap[addr];
state <= TRANSLATE1;
end
TRANSLATE1: begin
// Actualiza las 8 semifilas del teclado con la primera tecla
if (~released) begin
if (keyrow1[3] == 1'b1)
row[8] <= row[8] & ~keycol1;
else
row[keyrow1[2:0]] <= row[keyrow1[2:0]] & ~keycol1;
end
else begin
if (keyrow1[3] == 1'b1)
row[8] <= row[8] | keycol1;
else
row[keyrow1[2:0]] <= row[keyrow1[2:0]] | keycol1;
end
state <= TRANSLATE2;
end
TRANSLATE2: begin
// Actualiza las 8 semifilas del teclado con la segunda tecla
if (~released) begin
if (keyrow2[3] == 1'b1)
row[8] <= row[8] & ~keycol2;
else
row[keyrow2[2:0]] <= row[keyrow2[2:0]] & ~keycol2;
end
else begin
if (keyrow2[3] == 1'b1)
row[8] <= row[8] | keycol2;
else
row[keyrow2[2:0]] <= row[keyrow2[2:0]] | keycol2;
end
state <= TRANSLATE3;
end
TRANSLATE3: begin
// Actualiza modificadores
if (~released)
modifiers <= modifiers | keymodifiers;
else
modifiers <= modifiers & ~keymodifiers;
// Y de la misma forma tendria que actualizar resets y los user_toogles
if (~released)
{rmaster_reset,ruser_reset,ruser_nmi} <= {rmaster_reset,ruser_reset,ruser_nmi} | signalstate;
else
{rmaster_reset,ruser_reset,ruser_nmi} <= {rmaster_reset,ruser_reset,ruser_nmi} & ~signalstate;
if (~released)
ruser_toggles <= ruser_toggles | togglestate;
else
ruser_toggles <= ruser_toggles & ~togglestate;
//state <= UPDCOUNTERS1;
state <= IDLE;
end
CPUTIME: begin
if (rewind == 1'b1) begin
cpuaddr <= 14'h0000;
state <= IDLE;
end
else if (cpuread == 1'b1) begin
addr <= cpuaddr;
state <= CPUREAD;
end
else if (cpuwrite == 1'b1) begin
addr <= cpuaddr;
state <= CPUWRITE;
end
else
state <= IDLE;
end
CPUREAD: begin // CPU wants to read from keymap
dout <= keymap[addr];
state <= CPUINCADD;
end
CPUWRITE: begin
keymap[addr] <= din;
state <= CPUINCADD;
end
CPUINCADD: begin
if (cpuread == 1'b0 && cpuwrite == 1'b0) begin
cpuaddr <= cpuaddr + 1;
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
module keyboard_pressed_status (
input wire clk,
input wire rst,
input wire scan_received,
input wire [7:0] scancode,
input wire extended,
input wire released,
output reg kbclean
);
parameter
RESETTING = 2'd0,
UPDATING = 2'd1,
SCANNING = 2'd2;
reg keybstat_ne[0:255]; // non extended keymap
reg keybstat_ex[0:255]; // extended keymap
reg [7:0] addrscan = 8'h00; // keymap bit address
reg keypressed_ne = 1'b0; // there is at least one key pressed
reg keypressed_ex = 1'b0; // there is at least one extended key pressed
reg [1:0] state = RESETTING;
integer i;
initial begin
kbclean = 1'b1;
for (i=0;i<256;i=i+1) begin
keybstat_ne[i] = 1'b0;
keybstat_ex[i] = 1'b0;
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
state <= RESETTING;
addrscan <= 8'h00;
end
else begin
case (state)
RESETTING:
begin
if (addrscan == 8'hFF) begin
addrscan <= 8'h00;
state <= SCANNING;
kbclean <= 1'b1;
end
else begin
keybstat_ne[addrscan] <= 1'b0;
keybstat_ex[addrscan] <= 1'b0;
addrscan <= addrscan + 8'd1;
end
end
UPDATING:
begin
state <= SCANNING;
addrscan <= 8'h00;
kbclean <= 1'b0;
keypressed_ne <= 1'b0;
keypressed_ex <= 1'b0;
if (extended == 1'b0)
keybstat_ne[scancode] <= ~released;
else
keybstat_ex[scancode] <= ~released;
end
SCANNING:
begin
if (scan_received == 1'b1)
state <= UPDATING;
addrscan <= addrscan + 8'd1;
if (addrscan == 8'hFF) begin
kbclean <= ~(keypressed_ne | keypressed_ex);
keypressed_ne <= 1'b0;
keypressed_ex <= 1'b0;
end
else begin
keypressed_ne <= keypressed_ne | keybstat_ne[addrscan];
keypressed_ex <= keypressed_ex | keybstat_ex[addrscan];
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, su = 0; cin >> n; vector<long long> a(n); for (long long i = 0; i < n; ++i) { cin >> a[i]; su += a[i]; } if (su % 2) { cout << NO n ; return; } long long s = 0, ind = -1; for (long long i = 0; i < n; ++i) { if (!a[i] && s % 2 == 0) { ind = i; break; } s += a[i]; } vector<long long> ans; if (ind == -1) { for (long long i = n - 2; i > 0; i -= 2) { if (a[i - 1] && a[i]) continue; ans.push_back(i); a[i] = 1; if (a[i - 1]) { ind = i - 1; a[i - 1] = a[i] = a[i + 1] = 0; break; } a[i - 1] = 1; } if (ind == -1) { cout << NO n ; return; } } for (long long i = ind - 1; i >= 0; --i) { if (a[i]) { if (a[i - 1]) { ans.push_back(i); a[i - 1] = a[i] = 0; } else { if (a[i - 2]) { ans.push_back(i - 1); a[i - 2] = a[i] = 0; } else { ans.push_back(i - 1); ans.push_back(i); a[i - 2] = 1; a[i] = 0; } } } } for (long long i = ind + 1; i < n; ++i) { if (a[i]) { if (a[i + 1]) { ans.push_back(i); a[i + 1] = a[i] = 0; } else { if (a[i + 2]) { ans.push_back(i + 1); a[i + 2] = a[i] = 0; } else { ans.push_back(i + 1); ans.push_back(i); a[i + 2] = 1; a[i] = 0; } } } } cout << YES n << ans.size() << n ; for (long long i = 0; i < ans.size(); ++i) { cout << ans[i] << ; } cout << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); long long t; cin >> t; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; void input() {} int main() { input(); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; if (n % 2 == 0) cout << -1 << n ; else { for (int i = 0; i < n; i++) cout << i << ; cout << n ; for (int i = 0; i < n; i++) cout << i << ; cout << n ; for (int i = 0; i < n; i++) cout << (2 * i) % n << ; } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1123; const int MAXK = 312345; struct S2DSum { long long x[MAXN][MAXN]; void integrate(int n, int m) { for (int j = 0; j < m; j++) { for (int i = 1; i < n; i++) { x[i][j] += x[i - 1][j]; } } for (int i = 0; i < n; i++) { for (int j = 1; j < m; j++) { x[i][j] += x[i][j - 1]; } } } void add(int a, int b, int c, int d, long long e) { x[a][b] += e; x[a][d + 1] -= e; x[c + 1][b] -= e; x[c + 1][d + 1] += e; } long long sum(int a, int b, int c, int d) { long long ans = x[c][d]; if (a) ans -= x[a - 1][d]; if (b) ans -= x[c][b - 1]; if (a and b) ans += x[a - 1][b - 1]; return ans; } }; int n, m, k; int pic[MAXN][MAXN]; S2DSum orig; S2DSum cost[26]; S2DSum dc; int a[MAXK], b[MAXK], c[MAXK], d[MAXK], e[MAXK]; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m >> k; for (int i = 0; i < n; i++) { string s; cin >> s; for (int j = 0; j < m; j++) pic[i][j] = s[j] - a ; } for (int i = 0; i < k; i++) { char ce; cin >> a[i] >> b[i] >> c[i] >> d[i] >> ce; e[i] = ce - a ; a[i]--; b[i]--; c[i]--; d[i]--; orig.add(0, 0, n - 1, m - 1, 1); orig.add(a[i], b[i], c[i], d[i], -1); for (int j = 0; j < 26; j++) { cost[j].add(a[i], b[i], c[i], d[i], abs(e[i] - j)); } } orig.integrate(n, m); orig.integrate(n, m); for (int cl = 0; cl < 26; cl++) { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { long long hm = orig.sum(i, j, i, j); cost[cl].add(i, j, i, j, abs(cl - pic[i][j]) * hm); } } cost[cl].integrate(n, m); cost[cl].integrate(n, m); } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { dc.add(i, j, i, j, cost[pic[i][j]].sum(i, j, i, j)); } } dc.integrate(n, m); dc.integrate(n, m); long long ans = numeric_limits<long long>::max(); long long ini = dc.sum(0, 0, n - 1, m - 1); for (int i = 0; i < k; i++) { long long sub = ini; sub -= dc.sum(a[i], b[i], c[i], d[i]); sub += cost[e[i]].sum(a[i], b[i], c[i], d[i]); ans = min(ans, sub); } cout << ans << endl; }
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_BNC_P_read_DT00h for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_BNC_P_read_DT00h
// Module Name: NPCG_Toggle_BNC_P_read_DT00h
// File Name: NPCG_Toggle_BNC_P_read_DT00h.v
//
// Version: v1.0.0
//
// Description: Page read transfer FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_BNC_P_read_DT00h
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iLength ,
iCMDValid ,
oCMDReady ,
oReadData ,
oReadLast ,
oReadValid ,
iReadReady ,
iWaySelect ,
iColAddress ,
iRowAddress ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CASelect ,
oPM_CAData ,
iPM_ReadData ,
iPM_ReadLast ,
iPM_ReadValid ,
oPM_ReadReady
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input [15:0] iLength ;
input iCMDValid ;
output oCMDReady ;
output [31:0] oReadData ;
output oReadLast ;
output oReadValid ;
input iReadReady ;
input [NumberOfWays - 1:0] iWaySelect ;
input [15:0] iColAddress ;
input [23:0] iRowAddress ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
input [31:0] iPM_ReadData ;
input iPM_ReadLast ;
input iPM_ReadValid ;
output oPM_ReadReady ;
reg [NumberOfWays - 1:0] rTargetWay ;
reg [15:0] rColAddress ;
reg [23:0] rRowAddress ;
wire wModuleTriggered;
reg [7:0] rPMTrigger ;
reg [2:0] rPCommandOption ;
reg [15:0] rPMLength ;
reg [15:0] rTrfLength ;
reg [7:0] rCAData ;
reg rPMCommandOrAddress ;
localparam State_Idle = 4'b0000 ;
localparam State_NPBRIssue = 4'b0001 ;
localparam State_NCmdIssue = 4'b0011 ;
localparam State_NCmdWrite0 = 4'b0010 ;
localparam State_NCmdWrite1 = 4'b0110 ;
localparam State_NCmdWrite2 = 4'b0111 ;
localparam State_NCmdWrite3 = 4'b0101 ;
localparam State_NTimer1Issue = 4'b0100 ;
localparam State_DIIssue = 4'b1100 ;
localparam State_NTimer2Issue = 4'b1101 ;
localparam State_WaitDone = 4'b1111 ;
reg [3:0] rCurState ;
reg [3:0] rNextState ;
always @ (posedge iSystemClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (wModuleTriggered)?State_NPBRIssue:State_Idle;
State_NPBRIssue:
rNextState <= (iPM_Ready)?State_NCmdIssue:State_NPBRIssue;
State_NCmdIssue:
rNextState <= (iPM_LastStep[6])? State_NCmdWrite0:State_NCmdIssue;
State_NCmdWrite0:
rNextState <= State_NCmdWrite1;
State_NCmdWrite1:
rNextState <= State_NCmdWrite2;
State_NCmdWrite2:
rNextState <= State_NCmdWrite3;
State_NCmdWrite3:
rNextState <= State_NTimer1Issue;
State_NTimer1Issue:
rNextState <= (iPM_LastStep[3])? State_DIIssue:State_NTimer1Issue;
State_DIIssue:
rNextState <= (iPM_LastStep[0])? State_NTimer2Issue:State_DIIssue;
State_NTimer2Issue:
rNextState <= (iPM_LastStep[1])? State_WaitDone:State_NTimer2Issue;
State_WaitDone:
rNextState <= (oLastStep)?State_Idle:State_WaitDone;
default:
rNextState <= State_Idle;
endcase
assign wModuleTriggered = (iCMDValid && iTargetID == 5'b00101 && iOpcode == 6'b000011);
assign oCMDReady = (rCurState == State_Idle);
always @ (posedge iSystemClock)
if (iReset)
begin
rTargetWay <= {(NumberOfWays){1'b0}};
rTrfLength <= 16'b0;
rColAddress <= 16'b0;
rRowAddress <= 24'b0;
end
else
if (wModuleTriggered && (rCurState == State_Idle))
begin
rTargetWay <= iWaySelect ;
rTrfLength <= iLength ;
rColAddress <= iColAddress ;
rRowAddress <= iRowAddress ;
end
always @ (*)
case (rCurState)
State_NPBRIssue:
rPMTrigger <= 8'b0100_0000;
State_NCmdIssue:
rPMTrigger <= 8'b0000_1000;
State_NTimer1Issue:
rPMTrigger <= 8'b0000_0001;
State_DIIssue:
rPMTrigger <= 8'b0000_0010;
State_NTimer2Issue:
rPMTrigger <= 8'b0000_0001;
default:
rPMTrigger <= 8'b0000_0000;
endcase
always @ (*)
case (rCurState)
State_NTimer1Issue:
rPCommandOption[2:0] <= 3'b001; // CE on
State_DIIssue:
rPCommandOption[2:0] <= 3'b001; // word access
State_NTimer2Issue:
rPCommandOption[2:0] <= 3'b100;
default:
rPCommandOption[2:0] <= 0;
endcase
always @ (*)
if (iReset)
rPMLength <= 0;
else
case (rCurState)
State_NCmdIssue:
rPMLength <= 16'd3;
State_NTimer1Issue:
rPMLength <= 16'd33; // 340 ns
State_DIIssue:
rPMLength <= rTrfLength;
State_NTimer2Issue:
rPMLength <= 16'd3; // 40 ns
default:
rPMLength <= 0;
endcase
always @ (*)
case (rCurState)
State_NCmdWrite0:
rPMCommandOrAddress <= 1'b0;
State_NCmdWrite1:
rPMCommandOrAddress <= 1'b1;
State_NCmdWrite2:
rPMCommandOrAddress <= 1'b1;
State_NCmdWrite3:
rPMCommandOrAddress <= 1'b0;
default:
rPMCommandOrAddress <= 1'b0;
endcase
always @ (*)
if (iReset)
rCAData <= 0;
else
case (rCurState)
State_NCmdWrite0:
rCAData <= 8'h05;
State_NCmdWrite1:
rCAData <= rColAddress[7:0];
State_NCmdWrite2:
rCAData <= rColAddress[15:8];
State_NCmdWrite3:
rCAData <= 8'hE0;
default:
rCAData <= 0;
endcase
assign oStart = wModuleTriggered;
assign oLastStep = (rCurState == State_WaitDone) & iPM_LastStep[0];
assign oReadData = iPM_ReadData;
assign oReadLast = iPM_ReadLast;
assign oReadValid = iPM_ReadValid;
assign oPM_ReadReady = iReadReady;
assign oPM_PCommand = rPMTrigger;
assign oPM_PCommandOption = rPCommandOption; // CE on of PM_Timer, Word access of PM_DI
assign oPM_TargetWay = rTargetWay;
assign oPM_NumOfData = rPMLength ;
assign oPM_CASelect = rPMCommandOrAddress;
assign oPM_CAData = rCAData;
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (win64) Build Fri Jun 26 16:35:25 MDT 2015
// Date : Sun Jun 12 16:30:48 2016
// Host : 804-066 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file
// C:/Users/Administrator/Desktop/huchao/lab4/lab4_1/lab4_1_2/lab4_1_2.sim/sim_1/synth/timing/lab4_1_2_tb_time_synth.v
// Design : lab4_1_2
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING
module fb_count
(Qc_OBUF,
Qb_OBUF,
Qa_OBUF,
Qd_OBUF,
LD_reg_inv,
Z_reg,
CP_IBUF_BUFG,
LD_reg_inv_0,
M_IBUF);
output Qc_OBUF;
output Qb_OBUF;
output Qa_OBUF;
output Qd_OBUF;
output LD_reg_inv;
output Z_reg;
input CP_IBUF_BUFG;
input LD_reg_inv_0;
input M_IBUF;
wire CP_IBUF_BUFG;
wire LD_reg_inv;
wire LD_reg_inv_0;
wire M_IBUF;
wire Qa_OBUF;
wire Qa_i_1_n_0;
wire Qb_OBUF;
wire Qb_i_1_n_0;
wire Qc_OBUF;
wire Qc_i_1_n_0;
wire Qd_OBUF;
wire Qd_i_1_n_0;
wire Z_reg;
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000080))
LD_inv_i_1
(.I0(Qb_OBUF),
.I1(Qa_OBUF),
.I2(Qd_OBUF),
.I3(Qc_OBUF),
.I4(M_IBUF),
.O(LD_reg_inv));
LUT1 #(
.INIT(2'h1))
Qa_i_1
(.I0(Qa_OBUF),
.O(Qa_i_1_n_0));
FDCE #(
.INIT(1'b0))
Qa_reg
(.C(CP_IBUF_BUFG),
.CE(1'b1),
.CLR(LD_reg_inv_0),
.D(Qa_i_1_n_0),
.Q(Qa_OBUF));
LUT3 #(
.INIT(8'h69))
Qb_i_1
(.I0(M_IBUF),
.I1(Qb_OBUF),
.I2(Qa_OBUF),
.O(Qb_i_1_n_0));
FDPE #(
.INIT(1'b1))
Qb_reg
(.C(CP_IBUF_BUFG),
.CE(1'b1),
.D(Qb_i_1_n_0),
.PRE(LD_reg_inv_0),
.Q(Qb_OBUF));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h6CC9))
Qc_i_1
(.I0(M_IBUF),
.I1(Qc_OBUF),
.I2(Qa_OBUF),
.I3(Qb_OBUF),
.O(Qc_i_1_n_0));
FDCE #(
.INIT(1'b0))
Qc_reg
(.C(CP_IBUF_BUFG),
.CE(1'b1),
.CLR(LD_reg_inv_0),
.D(Qc_i_1_n_0),
.Q(Qc_OBUF));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6CCCCCC9))
Qd_i_1
(.I0(M_IBUF),
.I1(Qd_OBUF),
.I2(Qb_OBUF),
.I3(Qa_OBUF),
.I4(Qc_OBUF),
.O(Qd_i_1_n_0));
FDCE #(
.INIT(1'b0))
Qd_reg
(.C(CP_IBUF_BUFG),
.CE(1'b1),
.CLR(LD_reg_inv_0),
.D(Qd_i_1_n_0),
.Q(Qd_OBUF));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00400080))
Z_i_1
(.I0(Qb_OBUF),
.I1(Qa_OBUF),
.I2(Qd_OBUF),
.I3(Qc_OBUF),
.I4(M_IBUF),
.O(Z_reg));
endmodule
(* NotValidForBitStream *)
module lab4_1_2
(CP,
M,
Qd,
Qc,
Qb,
Qa,
Z);
input CP;
input M;
output Qd;
output Qc;
output Qb;
output Qa;
output Z;
wire CP;
wire CP_IBUF;
wire CP_IBUF_BUFG;
wire LD_reg_inv_n_0;
wire M;
wire M_IBUF;
wire Qa;
wire Qa_OBUF;
wire Qb;
wire Qb_OBUF;
wire Qc;
wire Qc_OBUF;
wire Qd;
wire Qd_OBUF;
wire Z;
wire Z_OBUF;
wire cou1_n_4;
wire cou1_n_5;
initial begin
$sdf_annotate("lab4_1_2_tb_time_synth.sdf",,,,"tool_control");
end
BUFG CP_IBUF_BUFG_inst
(.I(CP_IBUF),
.O(CP_IBUF_BUFG));
IBUF CP_IBUF_inst
(.I(CP),
.O(CP_IBUF));
FDRE #(
.INIT(1'b0))
LD_reg_inv
(.C(CP_IBUF_BUFG),
.CE(1'b1),
.D(cou1_n_4),
.Q(LD_reg_inv_n_0),
.R(1'b0));
IBUF M_IBUF_inst
(.I(M),
.O(M_IBUF));
OBUF Qa_OBUF_inst
(.I(Qa_OBUF),
.O(Qa));
OBUF Qb_OBUF_inst
(.I(Qb_OBUF),
.O(Qb));
OBUF Qc_OBUF_inst
(.I(Qc_OBUF),
.O(Qc));
OBUF Qd_OBUF_inst
(.I(Qd_OBUF),
.O(Qd));
OBUF Z_OBUF_inst
(.I(Z_OBUF),
.O(Z));
FDRE #(
.INIT(1'b0))
Z_reg
(.C(CP_IBUF_BUFG),
.CE(1'b1),
.D(cou1_n_5),
.Q(Z_OBUF),
.R(1'b0));
fb_count cou1
(.CP_IBUF_BUFG(CP_IBUF_BUFG),
.LD_reg_inv(cou1_n_4),
.LD_reg_inv_0(LD_reg_inv_n_0),
.M_IBUF(M_IBUF),
.Qa_OBUF(Qa_OBUF),
.Qb_OBUF(Qb_OBUF),
.Qc_OBUF(Qc_OBUF),
.Qd_OBUF(Qd_OBUF),
.Z_reg(cou1_n_5));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j; cin >> n; set<int> row; set<int> col; map<int, int> row_map; map<int, int> col_map; for (i = 1; i <= n; i++) { string s; cin >> s; for (j = 1; j <= n; j++) { if (s[j - 1] == . ) { row.insert(i); col.insert(j); row_map[i] = j; col_map[j] = i; } } } if (row.size() == n) { for (i = 1; i <= n; i++) { cout << i << << row_map[i] << endl; } } else if (col.size() == n) { for (j = 1; j <= n; j++) { cout << col_map[j] << << j << endl; } } else cout << -1 << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long x, y, z; cin >> x >> y >> z; long long ans1 = x / z + y / z, ans2 = 0; x %= z; y %= z; if (x + y >= z) { ans1++; ans2 = min(z - x, z - y); } cout << ans1 << << ans2 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int h, q, v, e; string s; map<int, int> xx; inline double dfs(int x, int mx) { if (xx[x] <= mx) return mx; return 0.5 * (dfs(x << 1, max(mx, xx[x] - xx[x << 1])) + dfs(x << 1 | 1, max(mx, xx[x] - xx[x << 1 | 1]))); } int main() { scanf( %d%d , &h, &q); while (q--) { cin >> s; if (s[0] == a ) { scanf( %d%d , &v, &e); while (v) xx[v] += e, v >>= 1; } else printf( %.8lf n , dfs(1, 0)); } }
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int r, g, b; cin >> r >> g >> b; int ans = 0; ans = r / 3 + g / 3 + b / 3; if (min(r, min(g, b)) >= 1) ans = max(ans, (r - 1) / 3 + (g - 1) / 3 + (b - 1) / 3 + 1); if (min(r, min(g, b)) >= 2) ans = max(ans, (r - 2) / 3 + (g - 2) / 3 + (b - 2) / 3 + 2); cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 7; const int maxm = 2e1 + 7; int n, m; int ar[maxn]; char ch[maxn]; int main() { int k; scanf( %d%d , &n, &k); int d = (n - k) / 2; for (int i = 0; i < n; i++) { ch[i] = 0 + (i % (d + 1) == d); } printf( %s n , ch); return 0; }
|
module test_wb_ppfifo_2_mem (
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int,
//master control signal for memory arbitration
output o_mem_we,
output o_mem_stb,
output o_mem_cyc,
output [3:0] o_mem_sel,
output [31:0] o_mem_adr,
output [31:0] o_mem_dat,
input [31:0] i_mem_dat,
input i_mem_ack,
input i_mem_int
);
//Local Parameters
localparam REG_CONTROL = 32'h00000000;
localparam REG_STATUS = 32'h00000001;
localparam REG_MEM_0_BASE = 32'h00000002;
localparam REG_MEM_0_SIZE = 32'h00000003;
localparam REG_MEM_1_BASE = 32'h00000004;
localparam REG_MEM_1_SIZE = 32'h00000005;
localparam CLOCK_DIVISOR = 32'h00000006;
//Wires/Registers
reg r_enable;
reg [31:0] r_clock_divisor = 0;
reg [31:0] r_clock_count;
reg dclock;
reg r_dclock;
/*-------------------------------------
* Copy the Following into you core
*-------------------------------------*/
reg [31:0] r_memory_0_base;
reg [31:0] r_memory_0_size;
wire [31:0] w_memory_0_count;
reg r_memory_0_ready;
wire w_memory_0_empty;
wire [31:0] w_default_mem_0_base;
reg [31:0] r_memory_1_base;
reg [31:0] r_memory_1_size;
wire [31:0] w_memory_1_count;
reg r_memory_1_ready;
wire w_memory_1_empty;
wire [31:0] w_default_mem_1_base;
wire w_write_finished;
//Ping Pong FIFO Write Side
wire [23:0] w_wfifo_size;
wire [1:0] w_wfifo_ready;
reg [1:0] r_wfifo_activate;
reg r_wfifo_strobe;
reg [31:0] r_wfifo_data;
wire [23:0] w_rfifo_size;
wire w_rfifo_ready;
wire w_rfifo_activate;
wire w_rfifo_strobe;
wire [31:0] w_rfifo_data;
reg [23:0] r_wfifo_count;
//Submodules
wb_ppfifo_2_mem p2m(
.clk (clk ),
.rst (rst ),
//Control
.i_enable (r_enable ),
.i_memory_0_base (r_memory_0_base ),
.i_memory_0_size (r_memory_0_size ),
.o_memory_0_count (w_memory_0_count ),
.i_memory_0_ready (r_memory_0_ready ),
.o_memory_0_empty (w_memory_0_empty ),
.o_default_mem_0_base (w_default_mem_0_base ),
.i_memory_1_base (r_memory_1_base ),
.i_memory_1_size (r_memory_1_size ),
.o_memory_1_count (w_memory_1_count ),
.i_memory_1_ready (r_memory_1_ready ),
.o_memory_1_empty (w_memory_1_empty ),
.o_default_mem_1_base (w_default_mem_1_base ),
.o_write_finished (w_write_finished ),
//master control signal for memory arbitration
.o_mem_we (o_mem_we ),
.o_mem_stb (o_mem_stb ),
.o_mem_cyc (o_mem_cyc ),
.o_mem_sel (o_mem_sel ),
.o_mem_adr (o_mem_adr ),
.o_mem_dat (o_mem_dat ),
.i_mem_dat (i_mem_dat ),
.i_mem_ack (i_mem_ack ),
.i_mem_int (i_mem_int ),
//Ping Pong FIFO Interface (Read)
.i_ppfifo_rdy (w_rfifo_ready ),
.o_ppfifo_act (w_rfifo_activate ),
.i_ppfifo_size (w_rfifo_size ),
.o_ppfifo_stb (w_rfifo_strobe ),
.i_ppfifo_data (w_rfifo_data )
);
ppfifo #(
.DATA_WIDTH (32 ), //Size will always be 32 bits for mem
.ADDRESS_WIDTH (2 ) //Really small ping pong FIFO (only 4 items)
) ping_pong (
.reset (rst ),
//write
.write_clock (dclock ),
.write_ready (w_wfifo_ready ),
.write_activate (r_wfifo_activate ),
.write_fifo_size (w_wfifo_size ),
.write_strobe (r_wfifo_strobe ),
.write_data (r_wfifo_data ),
//read
.read_clock (clk ),
.read_strobe (w_rfifo_strobe ),
.read_ready (w_rfifo_ready ),
.read_activate (w_rfifo_activate ),
.read_count (w_rfifo_size ),
.read_data (w_rfifo_data )
);
/*-------------------------------------*/
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
r_enable <= 0;
r_clock_divisor <= 0;
/*-------------------------------------
* Copy the following into you module
-------------------------------------*/
//Default base, user can change this from the API
r_memory_0_base <= w_default_mem_0_base;
r_memory_1_base <= w_default_mem_1_base;
//Nothing in the memory initially
r_memory_0_size <= 0;
r_memory_1_size <= 0;
r_memory_0_ready <= 0;
r_memory_1_ready <= 0;
/*-------------------------------------*/
end
else begin
/*-------------------------------------
* Copy the following into you module
-------------------------------------*/
r_memory_0_ready <= 0;
r_memory_1_ready <= 0;
/*-------------------------------------*/
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting somethign
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
REG_CONTROL: begin
r_enable <= i_wbs_dat[0];
end
REG_STATUS: begin
end
/*-------------------------------------
* Copy the following into you module
-------------------------------------*/
REG_MEM_0_BASE: begin
r_memory_0_base <= i_wbs_dat;
end
REG_MEM_0_SIZE: begin
r_memory_0_size <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_0_ready <= 1;
end
end
REG_MEM_1_BASE: begin
r_memory_1_base <= i_wbs_dat;
end
REG_MEM_1_SIZE: begin
r_memory_1_size <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_1_ready <= 1;
end
end
/*-----------------------------------*/
CLOCK_DIVISOR: begin
r_clock_divisor <= i_wbs_dat;
end
default: begin
end
endcase
end
else begin
//Reading
case (i_wbs_adr)
REG_CONTROL: begin
o_wbs_dat <= {31'b0, r_enable};
end
REG_STATUS: begin
//Indicates which memory bank is empty
o_wbs_dat <= {30'h00000000, w_memory_1_empty, w_memory_0_empty};
end
/*-------------------------------------
* Copy these signals directly into your module
-------------------------------------*/
REG_MEM_0_BASE: begin
o_wbs_dat <= r_memory_0_base;
end
REG_MEM_0_SIZE: begin
o_wbs_dat <= w_memory_0_count;
end
REG_MEM_1_BASE: begin
o_wbs_dat <= r_memory_1_base;
end
REG_MEM_1_SIZE: begin
o_wbs_dat <= w_memory_1_count;
end
CLOCK_DIVISOR: begin
o_wbs_dat <= r_clock_divisor;
end
/*-----------------------------------*/
default: begin
o_wbs_dat <= 32'h00;
end
endcase
end
o_wbs_ack <= 1;
end
end
end
always @ (clk) begin
if (r_clock_divisor == 0) begin
dclock = clk;
end
else begin
if (r_clock_count == 0) begin
dclock = r_dclock;
end
end
end
always @ (posedge clk) begin
if (rst) begin
r_clock_count <= 0;
r_dclock <= 0;
end
else begin
if (r_clock_count < r_clock_divisor) begin
r_clock_count <= r_clock_count + 1;
end
else begin
r_clock_count <= 0;
r_dclock <= ~r_dclock;
end
end
end
//Fill up the Ping Pong FIFO with an incrementing number pattern
//You can use this as a starting point for your own module
always @ (posedge dclock) begin
if (rst) begin
r_wfifo_activate <= 0;
r_wfifo_strobe <= 0;
r_wfifo_data <= 0;
r_wfifo_count <= 0;
end
else begin
//Strobes
r_wfifo_strobe <= 0;
if (r_wfifo_strobe) begin
r_wfifo_data <= r_wfifo_data + 1;
end
if ((w_wfifo_ready > 0) && (r_wfifo_activate == 0)) begin
r_wfifo_count <= 0;
if (w_wfifo_ready[0]) begin
r_wfifo_activate[0] <= 1;
end
else begin
r_wfifo_activate[1] <= 1;
end
end
else if (r_wfifo_activate > 0) begin
if (r_wfifo_count < w_wfifo_size) begin
r_wfifo_count <= r_wfifo_count + 1;
r_wfifo_strobe<= 1;
end
else begin
r_wfifo_activate <= 0;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int f(int n, vector<int> &a); int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(n); for (int i = 0; i <= n - 1; i++) { cin >> a[i]; } cout << f(n, a) << n ; } return 0; } int f(int n, vector<int> &a) { sort(a.begin(), a.end()); bool flag = 0; for (int k = 1; k <= 1023; k++) { flag = 0; for (int i = 0; i <= n - 1; i++) { int x = a[i] ^ k; if (!binary_search(a.begin(), a.end(), x)) { flag = 1; break; } } if (flag == 0) { return k; } } return -1; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR2B_PP_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const double pi = acos(-1); const int M = 3e5 + 10; const int inf = 2e9 + 10; const int mod = 1e9 + 7; int n, stk[M], le[M], ri[M], f[M], cnt[M]; char s[M], s1[M]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> s + 1; int num = 0, min = 0, id = 0; for (int i = 1; i <= n; ++i) { if (s[i] == ( ) ++num; else --num; if (num < min) { min = num; id = i; } } if (num) { cout << 0 n1 1 n ; return 0; } for (int i = 1; i <= id; ++i) s1[n + i - id] = s[i]; for (int i = id + 1; i <= n; ++i) s1[i - id] = s[i]; int top = 0; num = 0; for (int i = 1; i <= n; ++i) { if (s1[i] == ( ) { stk[++top] = ++num; le[num] = i; } else { int t1 = stk[top]; ri[t1] = i; f[t1] = stk[--top]; ++cnt[stk[top]]; } } int ans = cnt[0], lans = 1, rans = 1; for (int i = 1; i <= num; ++i) { if (cnt[i] + 1 > ans && !f[i]) { ans = cnt[i] + 1; lans = le[i]; rans = ri[i]; } if (cnt[i] + 1 + cnt[0] > ans && f[i] && !f[f[i]]) { ans = cnt[i] + 1 + cnt[0]; lans = le[i]; rans = ri[i]; } } lans = (lans + id - 1) % n + 1; rans = (rans + id - 1) % n + 1; cout << ans << n << lans << << rans << n ; }
|
#include <bits/stdc++.h> using namespace std; int ans, flag, a[20][300010], n, i, x, anx[20], as[20]; void dfs(int x, int y) { if (y >= ans) return; if (x < 2) { anx[1] = 0; if (a[x][0]) { y++; anx[1] = -1; } if (a[x][2]) { y++; anx[1] = 1; } if (y < ans) { ans = y; for (int i = 1; i <= 18; i++) as[i] = anx[i]; } return; } int flag = 0; for (int i = 0; i <= 1 << x - 1; i++) a[x - 1][i] = 0; for (int i = 0; i <= 1 << x; i++) if (a[x][i]) { if (i & 1) flag = 1; a[x - 1][i >> 1] = 1; } anx[x] = flag; dfs(x - 1, y + flag); if (flag) { for (int i = 0; i <= 1 << x - 1; i++) a[x - 1][i] = 0; for (int i = 0; i <= 1 << x; i++) if (a[x][i]) a[x - 1][i + 1 >> 1] = 1; anx[x] = -flag; dfs(x - 1, y + flag); } } int main() { scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &x), a[18][x + (1 << 17)] = 1; ans = 20; dfs(18, 0); printf( %d n , ans); for (i = 18; i >= 1; i--) if (as[i]) printf( %d , as[i] * (1 << 18 - i)); }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 10; int n; int inDegree[MAXN]; long long A[MAXN], _A[MAXN], B[MAXN]; vector<int> adj[MAXN]; void build() { for (int i = 0; i < n; i++) { if (B[i] == -1) continue; adj[i].push_back(B[i]); inDegree[B[i]]++; } } vector<int> solve() { vector<int> pos, neg; queue<int> q; for (int i = 0; i < n; i++) { if (inDegree[i] == 0) { q.push(i); } } while (!q.empty()) { int i = q.front(); q.pop(); if (A[i] > 0) { pos.push_back(i); if (B[i] != -1) A[B[i]] += A[i]; } else { neg.push_back(i); } for (auto v : adj[i]) { inDegree[v]--; if (inDegree[v] == 0) q.push(v); } } reverse(neg.begin(), neg.end()); pos.insert(pos.end(), neg.begin(), neg.end()); return pos; } int main() { ; ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (int i = 0; i < n; i++) { cin >> A[i]; _A[i] = A[i]; } for (int i = 0; i < n; i++) { cin >> B[i]; if (B[i] != -1) B[i]--; } build(); long long ans = 0; vector<int> v = solve(); for (auto i : v) { ans += _A[i]; if (B[i] != -1) _A[B[i]] += _A[i]; } cout << ans << n ; for (auto i : v) cout << i + 1 << ; cout << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 100005; const int N = 200005; int from[N], to[N]; stack<pair<int, int> > G[MAX]; stack<int> res; bool visited[2 * N]; void dfs(int src, int ind = -1) { if (ind != -1) { visited[ind] = true; } while (!G[src].empty()) { int v = G[src].top().first, e = G[src].top().second; G[src].pop(); if (!visited[e]) { dfs(v, e); } } res.push(src); } int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d %d , &from[i], &to[i]); from[i]--; to[i]--; G[from[i]].push(make_pair(to[i], i)); G[to[i]].push(make_pair(from[i], i)); } int pre = -1, cnt = 0; for (int i = 0; i < n; i++) { if (G[i].size() % 2) { if (pre == -1) { pre = i; } else { G[pre].push(make_pair(i, cnt + m)); G[i].push(make_pair(pre, cnt++ + m)); pre = -1; } } } if ((cnt + m) % 2) { G[0].push(make_pair(0, cnt + m)); } dfs(0); pre = res.top(); res.pop(); printf( %d n , res.size()); while (!res.empty()) { if (res.size() % 2) { printf( %d %d n , 1 + pre, 1 + res.top()); } else { printf( %d %d n , 1 + res.top(), 1 + pre); } pre = res.top(); res.pop(); } return 0; }
|
// Must synthesize into 3 * 8x2048 brams
module vram(input clk,
input [19:0] p1_addr,
input [7:0] p1_data,
output [7:0] p1_data_out,
input p1_we,
input p1_re,
input [19:0] p2_addr,
output [7:0] p2_data);
reg [7:0] mem[0:153600-1];
assign p1_data_out = p1_re?mem[p1_addr]:0;
assign p2_data = mem[p2_addr];
always @(posedge clk)
begin
if (p1_we) begin
mem[p1_addr] <= p1_data;
end
end
endmodule
module vgatopgfxsim(input clk, // 100MHz clk
input rst,
input clsrq,
output reg clsack,
input [19:0] vmem_in_addr,
input [7:0] vmem_in_data,
input vmem_we,
input vmem_re,
output [7:0] vmem_p1_out_data,
input [19:0] vmem_out_addr,
output [7:0] vmem_out_data
);
reg clsing;
reg [19:0] clsaddr;
wire [19:0] vmem_in_addr_x;
wire [7:0] vmem_in_data_x;
wire vmem_we_x;
assign vmem_in_addr_x = clsing?clsaddr:vmem_in_addr;
assign vmem_in_data_x = clsing?0:vmem_in_data;
assign vmem_we_x = clsing|vmem_we;
wire vmem_re_x;
assign vmem_re_x = clsing?0:vmem_re;
always @(posedge clk)
if (!rst) begin
clsing <= 0;
clsack <= 0;
clsaddr <= 0;
end else begin
if (clsack) clsack <= 0;
else if (clsrq && !clsing) begin
clsing <= 1;
clsaddr <= 0;
clsack <= 0;
end else if (clsing) begin
clsaddr <= clsaddr + 1;
if (clsaddr == 153600) begin
clsack <= 1;
clsing <= 0;
end
end
end
vram vram1(.clk(clk),
.p1_addr(vmem_in_addr_x),
.p1_data(vmem_in_data_x),
.p1_we(vmem_we_x),
.p1_re(vmem_re_x),
.p1_data_out(vmem_p1_out_data),
.p2_addr(vmem_out_addr),
.p2_data(vmem_out_data)
);
endmodule
|
#include <bits/stdc++.h> constexpr const int64_t mod = 998244353; int64_t dp[1005][2005][4]; int n, k; int main(int argc, char* argv[]) { scanf( %d%d , &n, &k); std::fill(dp[1][0], dp[1][0] + 4, 1LL); for (int i = 2; i <= n; ++i) { for (int j = 0; j < k; ++j) { dp[i][j][0] = dp[i - 1][j][0]; if (j >= 1) { dp[i][j][0] += dp[i - 1][j - 1][1] + dp[i - 1][j - 1][2] + dp[i - 1][j - 1][3]; dp[i][j][0] %= mod; } dp[i][j][1] = dp[i - 1][j][0] + dp[i - 1][j][1] + dp[i - 1][j][3]; if (j >= 2) dp[i][j][1] += dp[i - 1][j - 2][2]; dp[i][j][1] %= mod; dp[i][j][2] = dp[i - 1][j][0] + dp[i - 1][j][2] + dp[i - 1][j][3]; if (j >= 2) dp[i][j][2] += dp[i - 1][j - 2][1]; dp[i][j][2] %= mod; dp[i][j][3] = dp[i - 1][j][3]; if (j >= 1) { dp[i][j][3] += dp[i - 1][j - 1][0] + dp[i - 1][j - 1][1] + dp[i - 1][j - 1][2]; dp[i][j][3] %= mod; } } } int64_t ans = dp[n][k - 1][0] + dp[n][k - 1][3]; if (k >= 2) ans += dp[n][k - 2][1] + dp[n][k - 2][2]; ans %= mod; printf( %lld n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_2_V
`define SKY130_FD_SC_LS__NOR3B_2_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor3b_2 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor3b_2 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_2_V
|
#include <bits/stdc++.h> using namespace std; int n, m; string in[1003]; int a[1003][1003]; int X[] = {-1, 0, 0, 1}; int Y[] = {0, -1, 1, 0}; bool d[1003][1003]; int getSm(int i, int j, int u, int v) { return a[u][v] - a[i - 1][v] - a[u][j - 1] + a[i - 1][j - 1]; } bool check() { for (int i = 1; i <= n; i++) { bool ok = 0; int cnt = 0; for (int j = 1; j <= m; j++) { if (in[i][j] == # ) { if (!ok) { cnt++; ok = 1; } } else { ok = 0; } } if (cnt > 1) { return 0; } if (cnt == 0) { ok = 0; for (int j = 1; j <= m; j++) { if (getSm(1, j, n, j) == 0) { ok = 1; continue; } } if (!ok) { return 0; } } } for (int j = 1; j <= m; j++) { bool ok = 0; int cnt = 0; for (int i = 1; i <= n; i++) { if (in[i][j] == # ) { if (!ok) { cnt++; ok = 1; } } else { ok = 0; } } if (cnt > 1) { return 0; } if (cnt == 0) { ok = 0; for (int i = 1; i <= n; i++) { if (getSm(i, 1, i, m) == 0) { ok = 1; continue; } } if (!ok) { return 0; } } } return 1; } bool canC(int u, int v) { return (1 <= u) && (u <= n) && (1 <= v) && (v <= m) && (in[u][v] == # ) && (d[u][v] == 0); } void DFS(int u, int v) { d[u][v] = 1; for (int k = 0; k < 4; k++) { int nu = u + X[k]; int nv = v + Y[k]; if (canC(nu, nv)) { DFS(nu, nv); } } } int main() { ios::sync_with_stdio(0); cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> in[i]; in[i].insert(0, ); for (int j = 1; j <= m; j++) a[i][j] = (in[i][j] == # ) + a[i - 1][j] + a[i][j - 1] - a[i - 1][j - 1]; } if (a[n][m] == 0) { cout << 0; return 0; } if (n == 1) { int cnt = 0; for (int j = 1; j <= m; j++) { cnt += (in[1][j] == # ); } if ((0 < cnt) && (cnt < m)) { cout << -1; return 0; } } if (m == 1) { int cnt = 0; for (int i = 1; i <= n; i++) { cnt += (in[i][1] == # ); } if ((0 < cnt) && (cnt < n)) { cout << -1; return 0; } } if (!check()) { cout << -1; return 0; } memset(d, 0, sizeof d); int res = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if ((in[i][j] == # ) && (d[i][j] == 0)) { res++; DFS(i, j); } } cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = (1 << 30) + 7; const int N = 1e5 + 7; int main() { ios::sync_with_stdio(false); int q, l, r, d, ans; cin >> q; while (q--) { cin >> l >> r >> d; ans = (r / d + 1) * d; if (d < l) ans = d; else ans = (r / d + 1) * d; cout << ans << endl; } return 0; }
|
module basic();
// -------- Variable Section ----------
// --- User Variables ----
reg signed [31:0] A [0:10] ;
reg signed [31:0] I ;
reg signed [31:0] Y ;
// --- Control Bits ----
reg clk ;
reg [63:0] cycle_count ;
reg c_bit_00000_start ;
reg c_bit_00010_dim ;
reg c_bit_00020_00_assign ;
reg c_bit_00020_01_bubble ;
reg c_bit_00030_00_assign ;
reg c_bit_00030_01_bubble ;
reg c_bit_00030_02_test_taken ;
reg c_bit_00030_02_test ;
reg c_bit_00040_00_assign ;
reg c_bit_00040_01_bubble ;
reg c_bit_00050_print ;
reg c_bit_00060_00_test_taken ;
reg c_bit_00060_00_test ;
reg c_bit_00060_01_assign ;
reg c_bit_00060_02_bubble ;
reg c_bit_00070_end ;
// -------- Initialization Section ----------
initial begin
clk =0 ;
cycle_count =0 ;
c_bit_00000_start = 1 ;
end // initial
// -------- Data Flow Section ----------
always @(posedge clk) begin // dataflow for variable A
if (c_bit_00040_00_assign == 1) begin
A[I] <= I + I ;
end
else
begin
end
end
always @(posedge clk) begin // dataflow for variable I
if (c_bit_00030_00_assign == 1) begin
I <= 1 ;
end
else
if (c_bit_00060_01_assign == 1) begin
I <= I + 1 ;
end
else
begin
I <= I ;
end
end
always @(posedge clk) begin // dataflow for variable Y
if (c_bit_00020_00_assign == 1) begin
Y <= 1 ;
end
else
begin
Y <= Y ;
end
end
// -------- I/O Section ----------
always @(posedge clk) begin
if (c_bit_00050_print == 1) begin
$display("%0s%0d%0s%0d","A:",I," is: ",A[I]);
end
end
// -------- Control Flow Section ----------
always @(posedge clk) begin // control for line 00010_dim
if ( (c_bit_00000_start == 1) ) begin
c_bit_00000_start <= 0; c_bit_00010_dim <= 1 ;
end
else begin
c_bit_00010_dim <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00020_00_assign
if ( (c_bit_00010_dim == 1) ) begin
c_bit_00020_00_assign <= 1 ;
end
else begin
c_bit_00020_00_assign <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00020_01_bubble
if ( (c_bit_00020_00_assign == 1) ) begin
c_bit_00020_01_bubble <= 1 ;
end
else begin
c_bit_00020_01_bubble <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00030_00_assign
if ( (c_bit_00020_01_bubble == 1) ) begin
c_bit_00030_00_assign <= 1 ;
end
else begin
c_bit_00030_00_assign <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00030_01_bubble
if ( (c_bit_00030_00_assign == 1) ) begin
c_bit_00030_01_bubble <= 1 ;
end
else begin
c_bit_00030_01_bubble <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00030_02_test
if ( (c_bit_00030_01_bubble == 1) ) begin
if ( (1) > 0 ) begin
if ( (I) > 10) begin
c_bit_00030_02_test_taken <= 1 ; c_bit_00030_02_test <=0 ;
end // loop exit, taken
else begin
c_bit_00030_02_test_taken <= 0; c_bit_00030_02_test <= 1;
end
end else begin
if ( (I) < 10) begin
c_bit_00030_02_test_taken <= 1 ; c_bit_00030_02_test <= 0 ;
end // loop exit, taken
else begin
c_bit_00030_02_test_taken <= 0; c_bit_00030_02_test <= 1;
end
end
end
else begin
c_bit_00030_02_test <= 0; c_bit_00030_02_test_taken <=0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00040_00_assign
if ( (c_bit_00030_02_test == 1) || (c_bit_00060_02_bubble == 1) ) begin
c_bit_00040_00_assign <= 1 ;
end
else begin
c_bit_00040_00_assign <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00040_01_bubble
if ( (c_bit_00040_00_assign == 1) ) begin
c_bit_00040_01_bubble <= 1 ;
end
else begin
c_bit_00040_01_bubble <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00050_print
if ( (c_bit_00040_01_bubble == 1) ) begin
c_bit_00050_print <= 1 ;
end
else begin
c_bit_00050_print <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00060_00_test
if ( (c_bit_00050_print == 1) ) begin
if ( (1) > 0 ) begin
if ( (I + 1) > 10) begin
c_bit_00060_00_test_taken <= 1 ; c_bit_00060_00_test <=0 ;
end // loop exit, taken
else begin
c_bit_00060_00_test_taken <= 0; c_bit_00060_00_test <= 1;
end
end else begin
if ( (I + 1) < 10) begin
c_bit_00060_00_test_taken <= 1 ; c_bit_00060_00_test <= 0 ;
end // loop exit, taken
else begin
c_bit_00060_00_test_taken <= 0; c_bit_00060_00_test <= 1;
end
end
end
else begin
c_bit_00060_00_test <= 0; c_bit_00060_00_test_taken <=0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00060_01_assign
if ( (c_bit_00060_00_test == 1) ) begin
c_bit_00060_01_assign <= 1 ;
end
else begin
c_bit_00060_01_assign <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00060_02_bubble
if ( (c_bit_00060_01_assign == 1) ) begin
c_bit_00060_02_bubble <= 1 ;
end
else begin
c_bit_00060_02_bubble <= 0 ;
end
end // end @ posedge clk
always @(posedge clk) begin // control for line 00070_end
if ( (c_bit_00070_end == 1) || (c_bit_00060_00_test_taken == 1) ) begin
c_bit_00070_end <= 1 ; $finish;
end
else begin
c_bit_00070_end <= 0 ;
end
end // end @ posedge clk
// -------- Trailer Section ----------
// cycle counter
always @(posedge clk) begin
if (cycle_count > 50000) begin $display("reached maximum cycle count of 50000");
$finish;
end
else begin
cycle_count <= cycle_count + 1 ;
end
end
// clock generator
always
#1 clk = !clk ;
endmodule // basic
|
`timescale 1ns / 1ps
module MainActivity
(
input [7:0] estado,
input [7:0]RG1_P,
input [7:0]RG2_P,
input [7:0]RG3_P,
input escribiendo,
input en_out,
input [3:0] dig0, dig1,
input [3:0] direccion,
input clk, reset, off_alarma,on_alarma,//clock signal 100M
output [7:0] COLOUR_OUT,//bit patters for colour that goes to VGA port
output HS, //Horizontal Synch signal that goes into VGA port
output VS, //Vertical Synch signal that goes into VGA port7
output [7:0] seg_Ti,
output [7:0] min_Ti,
output [7:0] hor_Ti
);
reg DOWNCOUNTER = 0;
reg [7:0] COLOUR_IN, COLOUR_IN_co, COLOUR_IN_fe, COLOUR_IN_re, COLOUR_IN_cr;
reg en_conf, en_fecha, en_reloj, en_crono;
wire [31:0] STATE1,STATE2, STATE3, STATE4;
wire TrigRefresh; //Trigger gives a pulse when displayed refreshed
wire [9:0] ADDRH; //wire for getting Horizontal pixel value
wire [8:0] ADDRV; //wire for getting vertical pixel value
// signal declaration
//reg [1:0] state_reg, state_next;
wire CLK;
wire [8:0] text_on;
wire [2:0] text_rgb;
wire [3:0] RG1_Unit;
wire [3:0] RG2_Unit;
wire [3:0] RG3_Unit;
wire [3:0] RG1_Dec;
wire [3:0] RG2_Dec;
wire [3:0] RG3_Dec;
assign RG1_Unit= RG1_P[3:0];
assign RG2_Unit= RG2_P[3:0];
assign RG3_Unit= RG3_P[3:0];
assign RG1_Dec= RG1_P[7:4];
assign RG2_Dec= RG2_P[7:4];
assign RG3_Dec= RG3_P[7:4];
clk_div clk_div (
.clk(clk),
.out_clk(CLK)
);
//Divisor a 25MHz
always @(posedge CLK)begin
DOWNCOUNTER <= ~DOWNCOUNTER; //Slow down the counter to 25MHz
end
//VGA Interface gets values of ADDRH & ADDRV and by puting COLOUR_IN, gets valid output COLOUR_OUT
VGAInterface VGA(
.CLK(DOWNCOUNTER),
.COLOUR_IN (COLOUR_IN),
.COLOUR_OUT(COLOUR_OUT),
.HS(HS),
.VS(VS),
.REFRESH(TrigRefresh),
.ADDRH(ADDRH),
.ADDRV(ADDRV),
.DOWNCOUNTER(DOWNCOUNTER)
);
VGA_text text_unit
(
.estado(estado),
.RG1_Unit(RG1_Unit),
.RG2_Unit(RG2_Unit),
.RG3_Unit(RG3_Unit),
.RG1_Dec(RG1_Dec),
.RG2_Dec(RG2_Dec),
.RG3_Dec(RG3_Dec),
.escribiendo(escribiendo),
.en_out(en_out),
.CLK(DOWNCOUNTER), .off_alarma(off_alarma), .on_alarma(on_alarma), .direccion(direccion),
.dig0_Dec(dig0), .dig1_Unit(dig1),
.pix_x(ADDRH), .pix_y(ADDRV),
.text_on(text_on),
.text_rgb(text_rgb),
.seg_Ti(seg_Ti),
.min_Ti(min_Ti),
.hor_Ti(hor_Ti)
);
//------DATO-FECHA-------------------------------------------------------------------------------------
//-------------------COLOCACION DE IMAGENES-----------------------------------------------------
//------INFORMACIÓN DE CONFIGURACIÓN------------------------------------------------------------
localparam Xc = 360;
localparam Yc = 30;
reg [7:0] COLOUR_DATA [0:configuracion2-1];
parameter configuracion2 = 16'd46872;
parameter configuracion2X = 8'd248;
parameter configuracion2Y = 8'd189;
initial
$readmemh ("Instrucciones.png.list", COLOUR_DATA);
assign STATE1 = ((ADDRH-Xc)*configuracion2Y)+ADDRV-Yc;
always @(posedge CLK) begin
if (ADDRH>=Xc && ADDRH<Xc +configuracion2X
&& ADDRV>=Yc && ADDRV<Yc+configuracion2Y)
begin
COLOUR_IN_co <= COLOUR_DATA[{STATE1}];
en_conf<=1;
end
else
begin
COLOUR_IN_co <= 8'hFF;
en_conf<=0;
end
end
//------------------------------------------------------------------------------------------------
//------TITULO-FECHA-------------------------------------------------------------------------------------
localparam Xf = 0;
localparam Yf = 45;
reg [7:0] COLOUR_DATA_f [0:fecha-1];
parameter fecha = 13'd3936;
parameter fechaX = 7'd123;
parameter fechaY = 6'd32;
initial
$readmemh ("Fecha.png.list", COLOUR_DATA_f);
assign STATE2 = ((ADDRH-Xf)*fechaY)+ADDRV-Yf;
always @(posedge CLK) begin
if (ADDRH>=Xf && ADDRH<Xf+fechaX
&& ADDRV>=Yf && ADDRV<Yf+fechaY)
begin
COLOUR_IN_fe <= COLOUR_DATA_f[{STATE2}];
en_fecha<=1;
end
else
begin
COLOUR_IN_fe <= 8'hFF;
en_fecha<=0;
end
end
//------------------------------------------------------------------------------------------------
//------TITULO-RELOJ-------------------------------------------------------------------------------------
localparam Xr = 0;
localparam Yr = 166;
reg [7:0] COLOUR_DATA_r [0:reloj-1];
parameter reloj = 13'd4446;
parameter relojX = 7'd114;
parameter relojY = 6'd39;
initial
$readmemh ("Hora.png.list", COLOUR_DATA_r);
assign STATE3 = ((ADDRH-Xr)*relojY)+ADDRV-Yr;
always @(posedge CLK) begin
if (ADDRH>=Xr && ADDRH<Xr+relojX
&& ADDRV>=Yr && ADDRV<Yr+relojY)
begin
COLOUR_IN_re <= COLOUR_DATA_r[{STATE3}];
en_reloj<=1;
end
else
begin
COLOUR_IN_re <= 8'hFF;
en_reloj<=0;
end
end
//------------------------------------------------------------------------------------------------
//------TITULO-CRONOMETRO-------------------------------------------------------------------------------------
localparam Xcr = 0;
localparam Ycr = 286;
reg [7:0] COLOUR_DATA_cr [0:cronometro-1];
parameter cronometro = 14'd9102;
parameter cronometroX = 8'd222;
parameter cronometroY = 6'd41;
initial
$readmemh ("Cronometro.png.list", COLOUR_DATA_cr);
assign STATE4 = ((ADDRH-Xcr)*cronometroY)+ADDRV-Ycr;
always @(posedge CLK) begin
if (ADDRH>=Xcr && ADDRH<Xcr+cronometroX
&& ADDRV>=Ycr && ADDRV<Ycr+cronometroY)
begin
COLOUR_IN_cr <= COLOUR_DATA_cr[{STATE4}];
en_crono<=1;
end
else
begin
COLOUR_IN_cr <= 8'hFF;
en_crono<=0;
end
end
//------------------------------------------------------------------------------------------------
wire [7:0]color;
assign color={text_rgb[2],text_rgb[2],text_rgb[1],text_rgb[1],text_rgb[1],text_rgb[0],text_rgb[0],text_rgb[0]};
//--------MUX------------------------------------------------------------------------------------
always @ (posedge DOWNCOUNTER )
begin
if (text_on[2])
COLOUR_IN<=color;
else if (text_on[4])
COLOUR_IN<=color;
else if (text_on[3])
COLOUR_IN<=color;
else if (text_on[3])
COLOUR_IN<=color;
else if (en_fecha)
COLOUR_IN<=COLOUR_IN_fe;
else if (en_reloj)
COLOUR_IN<=COLOUR_IN_re;
else if (en_crono)
COLOUR_IN<=COLOUR_IN_cr;
else if (en_conf)
begin
COLOUR_IN<=COLOUR_IN_co;
end
else
COLOUR_IN<=COLOUR_IN;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, k; string s; bool flag; void solve() { int n, k; cin >> n >> k; unordered_set<int> s; queue<int> q; vector<int> a(n); for (auto i = 0; i < n; i++) cin >> a[i]; ; for (auto i = 0; i < n; i++) { if (s.find(a[i]) == s.end()) { if (s.size() >= k) { int kk = q.front(); s.erase(kk); q.pop(); } s.insert(a[i]); q.push(a[i]); } } stack<int> st; while (!q.empty()) { int aa = q.front(); st.push(aa); q.pop(); } cout << st.size() << endl; while (!st.empty()) { int aa = st.top(); st.pop(); cout << aa << ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DLYMETAL6S2S_PP_SYMBOL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlymetal6s2s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S2S_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long a[500006]; long long dp[500006]; long long vis[500006]; vector<long long> v[500006]; long long on; long long n, d, che; void dfs(long long root, long long parent) { vis[root] = 1; dp[root] = 1; for (auto it : v[root]) { if (!vis[it]) { dfs(it, root); if (a[it] == che && it < on) { continue; } if (it != parent && che <= a[it] && a[it] <= che + d) { (dp[root] *= (1 + dp[it])) %= 1000000007; } } } } void solve() { cin >> d >> n; for (long long i = 1; i <= n; i++) cin >> a[i]; for (long long i = 0; i < n - 1; i++) { long long a, b; cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } long long ans = 0; for (long long i = 1; i <= n; i++) { on = i; for (long long j = 1; j <= n; j++) vis[j] = dp[j] = 0; che = a[i]; dfs(i, -1); (ans += dp[i]) %= 1000000007; } cout << ans << n ; } signed main() { ios_base ::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; using namespace rel_ops; using ll = int64_t; using Pii = pair<int, int>; using ull = uint64_t; using Vi = vector<int>; void run(); int main() { cin.sync_with_stdio(0); cin.tie(0); cout << fixed << setprecision(10); run(); return 0; } int uplg(int n) { return 32 - __builtin_clz(n); } int uplg(ll n) { return 64 - __builtin_clzll(n); } int cmp(double a, double b, double eps = 1e-9) { return (a > b + eps) - (a + eps < b); } char board[2001][2001]; int n, k; int dp[2001][2001]; int lex[2001][2001]; bool toRight[2001][2001]; void run() { cin >> n >> k; for (int i = (0); i < (n); i++) cin >> board[i]; for (int i = (0); i < (n); i++) for (int j = (0); j < (n); j++) { if (i == 0 && j == 0) { dp[i][j] = 0; } else { dp[i][j] = INT_MAX; } if (i > 0) { dp[i][j] = min(dp[i][j], dp[i - 1][j]); } if (j > 0) { dp[i][j] = min(dp[i][j], dp[i][j - 1]); } if (board[i][j] != a ) { dp[i][j]++; } } if (dp[n - 1][n - 1] <= k) { for (int i = (0); i < (n * 2 - 1); i++) cout << a ; cout << endl; return; } lex[n][n] = 0; Pii from{0, 0}; for (int sum = n * 2 - 1; sum >= 0; sum--) { vector<pair<Pii, int>> pairs; int best = INT_MAX; Pii bestPos = {-1, -1}; for (int i = (0); i < (n); i++) { int j = sum - i; if (j < 0 || j >= n) continue; int better = INT_MAX; if (j + 1 < n) better = min(better, lex[i][j + 1]); if (i + 1 < n) { better = min(better, lex[i + 1][j]); if (better == lex[i + 1][j]) toRight[i][j] = 1; } pairs.push_back({{board[i][j], better}, i}); if (dp[i][j] <= k) { if (better < best) { best = better; bestPos = {i, j}; } } } if (best < INT_MAX) { from = bestPos; if (toRight[bestPos.first][bestPos.second]) from.first++; else from.second++; break; } sort((pairs).begin(), (pairs).end()); Pii last = {-1, -1}; int ind = 0; for (auto& p : (pairs)) { if (p.first != last) { ind++; last = p.first; } lex[p.second][sum - p.second] = ind; } } for (int i = (0); i < (from.first + from.second); i++) cout << a ; while (from.first != n - 1 || from.second != n - 1) { cout << board[from.first][from.second]; if (toRight[from.first][from.second]) from.first++; else from.second++; } cout << board[n - 1][n - 1] << endl; }
|
#include <bits/stdc++.h> using namespace std; const int www = 9; const int Size = 10000; char buffer[Size]; int dr[] = {-1, 0, 1, 0}; int dc[] = {0, 1, 0, -1}; const int inf = 0x0fffffff; const int size = 1000; int d[size]; int solution(int nTest) { int k, a, b; scanf( %d%d%d , &k, &a, &b); scanf( %s , buffer); string s = buffer; int n = s.size(); if (n / k >= a && (n + k - 1) / k <= b) { vector<string> res; int t = n / k; int tt = (n + k - 1) / k; int r = k - (n % k); for (int i = 0; i < k - (n % k); i++) { res.push_back(s.substr(i * t, t)); } for (int i = 0; i < n % k; i++) { res.push_back(s.substr(t * r + i * tt, tt)); } for (int i = 0; i < res.size(); i++) { puts(res[i].c_str()); } return 0; } puts( No solution ); return 0; } int main() { int i = 0, n = 9999; while (i < n && solution(i)) { i++; } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> fail(string s) { int n = s.size(); vector<int> z(n); int l = 0, r = 0; for (int i = 1; i < n; ++i) { if (i <= r) z[i] = min(z[i - l], r - i + 1); while (z[i] + i < n && s[z[i] + i] == s[z[i]]) ++z[i]; if (z[i] + i - 1 > r) { l = i; r = z[i] + i - 1; } } return z; } string s; vector<int> z; vector<pair<int, int> > ans; int A[100005]; int main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); int n, m, i, j, k, x, y; cin >> s; z = fail(s); n = s.size(); z[0] = n; for (i = 0; i < n; ++i) A[z[i]]++; for (i = n - 1; i >= 0; --i) A[i] += A[i + 1]; for (i = n - 1; i >= 0; --i) { if (z[i] == (n - i)) { ans.push_back(make_pair(z[i], A[z[i]])); } } sort(ans.begin(), ans.end()); cout << ans.size() << endl; for (auto it : ans) { cout << it.first << << it.second << endl; } return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for arbiter
*/
module test_arbiter_rr;
// Parameters
localparam PORTS = 32;
localparam ARB_TYPE_ROUND_ROBIN = 1;
localparam ARB_BLOCK = 1;
localparam ARB_BLOCK_ACK = 0;
localparam ARB_LSB_HIGH_PRIORITY = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS-1:0] request = 0;
reg [PORTS-1:0] acknowledge = 0;
// Outputs
wire [PORTS-1:0] grant;
wire grant_valid;
wire [$clog2(PORTS)-1:0] grant_encoded;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
request,
acknowledge
);
$to_myhdl(
grant,
grant_valid,
grant_encoded
);
// dump file
$dumpfile("test_arbiter_rr.lxt");
$dumpvars(0, test_arbiter_rr);
end
arbiter #(
.PORTS(PORTS),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(ARB_BLOCK),
.ARB_BLOCK_ACK(ARB_BLOCK_ACK),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000 + 100; int bitRow[maxn][maxn], bitCol[maxn][maxn], n, m; bool a[maxn][maxn]; void addRow(int fi, int idx, int val) { while (idx <= 1000) { bitRow[fi][idx] += val; idx += idx & (-idx); } } void addCol(int fi, int idx, int val) { while (idx <= 1000) { bitCol[fi][idx] += val; idx += idx & (-idx); } } int getRow(int fi, int se) { if (se == 0) return 0; int ret = 0; while (se > 0) { ret += bitRow[fi][se]; se -= se & (-se); } return ret; } int getCol(int fi, int se) { if (se == 0) return 0; int ret = 0; while (se > 0) { ret += bitCol[fi][se]; se -= se & (-se); } return ret; } int getRight(int fi, int se) { int lo = se, hi = m; while (lo != hi) { int mid = (lo + hi + 1) / 2; if (getRow(fi, mid) - getRow(fi, se - 1) == mid - se + 1) lo = mid; else hi = mid - 1; } return lo; } int getLeft(int fi, int se) { int lo = 1, hi = se; while (lo != hi) { int mid = (lo + hi) / 2; if (getRow(fi, se) - getRow(fi, mid - 1) == se - mid + 1) hi = mid; else lo = mid + 1; } return lo; } int getDown(int fi, int se) { int lo = fi, hi = n; while (lo != hi) { int mid = (lo + hi + 1) / 2; if (getCol(se, mid) - getCol(se, fi - 1) == mid - fi + 1) lo = mid; else hi = mid - 1; } return lo; } int getUp(int fi, int se) { int lo = 1, hi = fi; while (lo != hi) { int mid = (lo + hi) / 2; if (getCol(se, fi) - getCol(se, mid - 1) == fi - mid + 1) hi = mid; else lo = mid + 1; } return lo; } int main() { ios_base::sync_with_stdio(false); int q; cin >> n >> m >> q; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { bool cur; cin >> cur; a[i][j] = cur; addRow(i, j, cur); addCol(j, i, cur); } while (q--) { int op, fi, se; cin >> op >> fi >> se; if (op == 1) { a[fi][se] = !a[fi][se]; if (a[fi][se] == 0) { addRow(fi, se, -1); addCol(se, fi, -1); } else { addRow(fi, se, +1); addCol(se, fi, +1); } } else { int cur = 0, left = 0, right = 10000; for (int i = fi; i >= 1; i--) { if (a[i][se] == 0) break; right = min(right, getRight(i, se)); left = max(left, getLeft(i, se)); cur = max(cur, (fi - i + 1) * (right - left + 1)); } left = 0, right = 10000; for (int i = fi; i <= n; i++) { if (a[i][se] == 0) break; right = min(right, getRight(i, se)); left = max(left, getLeft(i, se)); cur = max(cur, (i - fi + 1) * (right - left + 1)); } int up = 0, down = 10000; for (int i = se; i >= 1; i--) { if (a[fi][i] == 0) break; up = max(up, getUp(fi, i)); down = min(down, getDown(fi, i)); cur = max(cur, (se - i + 1) * (down - up + 1)); } up = 0, down = 10000; for (int i = se; i <= m; i++) { if (a[fi][i] == 0) break; up = max(up, getUp(fi, i)); down = min(down, getDown(fi, i)); cur = max(cur, (i - se + 1) * (down - up + 1)); } cout << cur << endl; } } }
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; string s; cin >> s; int cnt = 0; vector<int> v; char last = * ; for (int i = 0, to = n; i < to; i++) { if (last != s[i]) { if (cnt > 0) v.push_back(cnt); cnt = 1; last = s[i]; } else { cnt++; } } v.push_back(cnt); int ans = 0; int resto = 0; for (int i = 0, to = (int)v.size(); i < to; i++) { if (v[i] > 1) { resto -= (v[i] - 2); resto = max(resto, 0); ans++; } else { resto++; ans++; } } cout << ans - resto / 2 << n ; } int main() { ios::sync_with_stdio(0); cin.tie(NULL); int t = 1; cin >> t; while (t--) solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_SYMBOL_V
`define SKY130_FD_SC_LP__XOR2_SYMBOL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xor2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_SYMBOL_V
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#include <bits/stdc++.h> #define ll long long #define f(i, n) for (i = 0; i < n; ++i) #define all(n) n.begin(), n.end() #define P long(1e9 + 7) #define fastio ios_base::sync_with_stdio(false); cin.tie(NULL) using namespace std; ll solve(vector<vector<ll>>& dp, vector<ll>& s, int l, int r) { if (l == r) return dp[l][r] = 0; if (dp[l][r] == -1) { ll val = s[r] - s[l]; val += min(solve(dp, s, l + 1, r), solve(dp, s, l, r - 1)); return dp[l][r] = val; } return dp[l][r]; } int main() { int n, i, j, k, l, m; cin >> n; vector<ll> s(n, 0); vector<vector<ll>> dp(n, vector<ll>(n, -1)); f(i, n) cin >> s[i]; sort(all(s)); cout << solve(dp, s, 0, n - 1); }
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#include <bits/stdc++.h> using namespace std; vector<long long> lucky; void backtrack(long long x) { if (x > 1e10) return; lucky.push_back(x); backtrack(x * 10 + 4); backtrack(x * 10 + 7); } int main() { long long ans = 0; backtrack(0); sort(lucky.begin(), lucky.end()); int a, b; cin >> a >> b; for (int i = 1; i < (int)lucky.size(); i++) { int l, r, m; l = a, r = b; while (l <= r) { m = (l + r) >> 1; if (m <= lucky[i]) { ans += lucky[i] * (m - l + 1); a = m + 1; i--; break; } else { r = m - 1; } } } cout << ans << n ; return 0; }
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