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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCIN_PP_SYMBOL_V
`define SKY130_FD_SC_HD__FAHCIN_PP_SYMBOL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fahcin (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCIN_PP_SYMBOL_V
|
module jt10_test(
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
input cen, // optional clock enable, if not needed leave as 1'b1
input [7:0] din,
input [1:0] addr,
input cs_n,
input wr_n,
output [7:0] dout,
output irq_n,
// ADPCM pins
output [19:0] adpcma_addr, // real hardware has 10 pins multiplexed through RMPX pin
output [3:0] adpcma_bank,
output adpcma_roe_n, // ADPCM-A ROM output enable
input [7:0] adpcma_data, // Data from RAM
output [23:0] adpcmb_addr, // real hardware has 12 pins multiplexed through PMPX pin
output adpcmb_roe_n, // ADPCM-B ROM output enable
// combined output
output signed [15:0] snd_right,
output signed [15:0] snd_left,
output snd_sample
);
wire [7:0] psg_A;
wire [7:0] psg_B;
wire [7:0] psg_C;
wire signed [15:0] fm_snd;
wire [9:0] psg_snd;
jt10 uut (
.rst (rst ),
.clk (clk ),
.cen (cen ),
.din (din ),
.addr (addr ),
.cs_n (cs_n ),
.wr_n (wr_n ),
.dout (dout ),
.irq_n (irq_n ),
.adpcma_addr (adpcma_addr ),
.adpcma_bank (adpcma_bank ),
.adpcma_roe_n(adpcma_roe_n),
.adpcma_data (adpcma_data ),
.adpcmb_addr (adpcmb_addr ),
.adpcmb_roe_n(adpcmb_roe_n),
.psg_A (psg_A ),
.psg_B (psg_B ),
.psg_C (psg_C ),
.fm_snd (fm_snd ),
.psg_snd (psg_snd ),
.snd_right (snd_right ),
.snd_left (snd_left ),
.snd_sample (snd_sample )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31OI_1_V
`define SKY130_FD_SC_MS__A31OI_1_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a31oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a31oi_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31OI_1_V
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 26875 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4096,
w4095,
w256,
w4351,
w1024,
w5375,
w21500,
w26875;
assign w1 = i_data0;
assign w1024 = w1 << 10;
assign w21500 = w5375 << 2;
assign w256 = w1 << 8;
assign w26875 = w5375 + w21500;
assign w4095 = w4096 - w1;
assign w4096 = w1 << 12;
assign w4351 = w4095 + w256;
assign w5375 = w4351 + w1024;
assign o_data0 = w26875;
//multiplier_block area estimate = 6246.97929160441;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_BEHAVIORAL_V
`define SKY130_FD_SC_LS__INV_BEHAVIORAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_BEHAVIORAL_V
|
/*
-- ============================================================================
-- FILE NAME : if_stage.v
-- DESCRIPTION : IF¥¹¥Æ©`¥¸
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "cpu.h"
/********** ¥â¥¸¥å©`¥ë **********/
module if_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** SPM¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] spm_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire [`WordAddrBus] spm_addr, // ¥¢¥É¥ì¥¹
output wire spm_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire spm_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] spm_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] bus_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire bus_rdy_, // ¥ì¥Ç¥£
input wire bus_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
output wire bus_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
output wire [`WordAddrBus] bus_addr, // ¥¢¥É¥ì¥¹
output wire bus_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire bus_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] bus_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
input wire [`WordAddrBus] new_pc, // Ф·¤¤¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire br_taken, // ·Ö᪤γÉÁ¢
input wire [`WordAddrBus] br_addr, // ·ÖáªÏÈ¥¢¥É¥ì¥¹
output wire busy, // ¥Ó¥¸©`ÐźÅ
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output wire [`WordAddrBus] if_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
output wire [`WordDataBus] if_insn, // ÃüÁî
output wire if_en // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
);
/********** ÄÚ²¿½Ó¾AÐźŠ**********/
wire [`WordDataBus] insn; // ¥Õ¥§¥Ã¥Á¤·¤¿ÃüÁî
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
bus_if bus_if (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (stall), // ¥¹¥È©`¥ë
.flush (flush), // ¥Õ¥é¥Ã¥·¥åÐźÅ
.busy (busy), // ¥Ó¥¸©`ÐźÅ
/********** CPU¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.addr (if_pc), // ¥¢¥É¥ì¥¹
.as_ (`ENABLE_), // ¥¢¥É¥ì¥¹Óп
.rw (`READ), // Õi¤ß£¯ø¤
.wr_data (`WORD_DATA_W'h0), // ø¤Þz¤ß¥Ç©`¥¿
.rd_data (insn), // Õi¤ß³ö¤·¥Ç©`¥¿
/********** ¥¹¥¯¥é¥Ã¥Á¥Ñ¥Ã¥É¥á¥â¥ê¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.spm_rd_data (spm_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.spm_addr (spm_addr), // ¥¢¥É¥ì¥¹
.spm_as_ (spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.spm_rw (spm_rw), // Õi¤ß£¯ø¤
.spm_wr_data (spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.bus_rd_data (bus_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.bus_rdy_ (bus_rdy_), // ¥ì¥Ç¥£
.bus_grnt_ (bus_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
.bus_req_ (bus_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.bus_addr (bus_addr), // ¥¢¥É¥ì¥¹
.bus_as_ (bus_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.bus_rw (bus_rw), // Õi¤ß£¯ø¤
.bus_wr_data (bus_wr_data) // ø¤Þz¤ß¥Ç©`¥¿
);
/********** IF¥¹¥Æ©`¥¸¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
if_reg if_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Õ¥§¥Ã¥Á¥Ç©`¥¿ **********/
.insn (insn), // ¥Õ¥§¥Ã¥Á¤·¤¿ÃüÁî
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (stall), // ¥¹¥È©`¥ë
.flush (flush), // ¥Õ¥é¥Ã¥·¥å
.new_pc (new_pc), // Ф·¤¤¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.br_taken (br_taken), // ·Ö᪤γÉÁ¢
.br_addr (br_addr), // ·ÖáªÏÈ¥¢¥É¥ì¥¹
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.if_pc (if_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.if_insn (if_insn), // ÃüÁî
.if_en (if_en) // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
);
endmodule
|
#include <bits/stdc++.h> using namespace std; string s[6]; vector<string> res; void draw(vector<string> &w, int x, int y, int dx, int dy, string s) { for (int k = 0; k < s.size(); k++, x += dx, y += dy) { w[x][y] = s[k]; } return; } int main() { for (int i = 0; i < 6; i++) cin >> s[i]; sort(s, s + 6); res.clear(); do { if (s[0].size() + s[2].size() == s[1].size() + 1 && s[3].size() + s[5].size() == s[4].size() + 1) { int l[6]; for (int i = 0; i < 6; i++) l[i] = s[i].size() - 1; if (s[0][0] == s[3][0] && s[0][l[0]] == s[4][0] && s[1][0] == s[3][l[3]] && s[1][l[0]] == s[4][l[3]] && s[1][l[1]] == s[5][0] && s[2][0] == s[4][l[4]] && s[2][l[2]] == s[5][l[5]]) { int n = l[4] + 1, m = l[1] + 1; vector<string> w(n, string(m, . )); draw(w, 0, 0, 0, 1, s[0]); draw(w, l[3], 0, 0, 1, s[1]); draw(w, n - 1, l[0], 0, 1, s[2]); draw(w, 0, 0, 1, 0, s[3]); draw(w, 0, l[0], 1, 0, s[4]); draw(w, l[3], l[1], 1, 0, s[5]); if (res.size() == 0 || res > w) res = w; } } } while (next_permutation(s, s + 6)); if (res.size() == 0) cout << Impossible << endl; for (int i = 0; i < res.size(); i++) cout << res[i] << endl; }
|
`include "../network_params.h"
module mult_adder(
input clock,
input reset,
input [`MULT_ADDER_IN_BITWIDTH:0] in,
input [`MULT_ADDER_IN_BITWIDTH:0] kernal,
input [`CONV_ADD_BITWIDTH:0] bias,
output [`CONV_ADD_BITWIDTH:0] out
);
// wire declarations
wire [`CONV_PRODUCT_BITWIDTH:0] in_add_vector_wire [`MA_TREE_SIZE-1:0];
wire [`CONV_ADD_BITWIDTH:0] adder_tree_wire [((`MA_TREE_SIZE*2)-1)-1:0];
wire [(`MA_TREE_SIZE*2)-1-1:0]carry_wire ;
// assign statments
assign out = adder_tree_wire[0] + bias;
assign carry_wire [(`MA_TREE_SIZE*2)-1-1:`MA_TREE_SIZE-1] = `MA_TREE_SIZE'd0;
// connect input vector to multipliers
genvar i;
generate
//for(i = 0; i < `KERNEL_SIZE_SQ; i=i+1) begin : connect_mul
for(i = 0; i < `MA_TREE_SIZE; i=i+1) begin : connect_mul
mult_adder_mult ma_mult_inst(
.clock(clock),
.reset(reset),
.operand_a(in[`CONV_MULT_WIDTH*(i+1)-1:i*`CONV_MULT_WIDTH]),
.operand_b(kernal[`CONV_MULT_WIDTH*(i+1)-1:i*`CONV_MULT_WIDTH]),
.out(in_add_vector_wire[i])
);
end
endgenerate
// map products to adder tree wire
//genvar i;
genvar pad_count;
generate
//for(i = 0; i < `KERNEL_SIZE_SQ; i=i+1) begin : connect_in_vector
for(i = 0; i < `MA_TREE_SIZE; i=i+1) begin : connect_in_vector
// assign the lsbs here
// assign adder_tree_wire[i+`MA_TREE_SIZE-1][`CONV_PRODUCT_BITWIDTH:0] = in[(`CONV_PRODUCT_WIDTH*i)+`CONV_PRODUCT_BITWIDTH:`CONV_PRODUCT_WIDTH*i];
assign adder_tree_wire[i+`MA_TREE_SIZE-1][`CONV_PRODUCT_BITWIDTH:0] = in_add_vector_wire[i];
// loop over msb and assign sign bit here
for(pad_count=0; pad_count<`MULT_PAD_WIDTH; pad_count=pad_count+1) begin : sign_bit_extention_loop
//assign adder_tree_wire[i+`MA_TREE_SIZE-1][`CONV_PRODUCT_WIDTH+pad_count] = in[(`CONV_PRODUCT_WIDTH*i)+`CONV_PRODUCT_BITWIDTH];
assign adder_tree_wire[i+`MA_TREE_SIZE-1][`CONV_PRODUCT_WIDTH+pad_count] = in_add_vector_wire[i][`CONV_PRODUCT_BITWIDTH];
end // pad count
end
endgenerate
// connect adder tree
genvar j;
generate
//for(j= (`KERNIL_SIZE_SQ*2)-2 ; j >=1 ; j=j-2) begin : sum_products
for(j= (`MA_TREE_SIZE*2)-2 ; j >=1 ; j=j-2) begin : sum_products
mult_adder_add ma_add_inst(
.clock(clock),
.reset(reset),
.operand_a(adder_tree_wire[j-1]),
.operand_b(adder_tree_wire[j]),
.c_a(carry_wire[j-1]),
.c_b(carry_wire[j]),
.out(adder_tree_wire[(j/2)-1]),
.carry(carry_wire[(j/2)-1])
);
end // for
endgenerate
endmodule // mult_adder
module mult_adder_mult(
input clock,
input reset,
input signed [`CONV_MULT_BITWIDTH:0] operand_a,
input signed [`CONV_MULT_BITWIDTH:0] operand_b,
output [`CONV_PRODUCT_BITWIDTH:0] out
);
reg signed[`CONV_PRODUCT_BITWIDTH:0] product;
assign out = product[`CONV_PRODUCT_BITWIDTH:0];
always@(posedge clock or negedge reset) begin
if(reset == 1'b0)
product <= `CONV_PRODUCT_WIDTH'd0;
else
product <= operand_a * operand_b;
end // always
endmodule
module mult_adder_add(
input clock,
input reset,
input [`CONV_ADD_BITWIDTH:0] operand_a,
input [`CONV_ADD_BITWIDTH:0] operand_b,
input c_a, // overflow or carry indicators
input c_b,
output [`CONV_ADD_BITWIDTH:0] out,
output carry
);
reg [`CONV_ADD_BITWIDTH+1:0] sum;
assign out = sum[`CONV_ADD_BITWIDTH:0];
assign carry = sum[`CONV_ADD_BITWIDTH + 1] | c_a | c_b;
always@(posedge clock or negedge reset) begin
if(reset == 1'b0)
sum <= {1'b0,`CONV_ADD_WIDTH'd0};
else
sum <= operand_a + operand_b;
end // always
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } signed main() { std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; string s; int n, a, b; cin >> n >> a >> b >> s; for (int i = 0; i <= n / a; i++) { if ((n - i * a) % b == 0) { cout << i + (n - i * a) / b << endl; for (int j = 0; j < i * a; j++) { cout << s[j]; if ((j + 1) % a == 0) cout << endl; } for (int j = i * a, k = 0; j < n; j++, k++) { cout << s[j]; if ((k + 1) % b == 0) cout << endl; } return 0; } } cout << -1 n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 1500 + 10; int n, x, y; struct node { int xx, yy, id; bool operator<(const node &a) const { if (xx - x >= 0 && a.xx - x <= 0) return 1; if (xx - x <= 0 && a.xx - x >= 0) return 0; return (yy - y) * (long long)(a.xx - x) < (a.yy - y) * (long long)(xx - x); } } p[M]; vector<int> g[M]; int sz[M]; int ans[M]; void dfs(int o, int u) { sz[u] = 1; for (int &v : g[u]) if (v != o) { dfs(u, v); sz[u] += sz[v]; } } void dfs2(int o, int u, int l, int r) { if (sz[u] == 1) { ans[p[l].id] = u; return; } int id = l; for (int i = l + 1; i < r; ++i) { if (p[i].xx < p[id].xx) { id = i; } } swap(p[id], p[l]); ans[p[l].id] = u; x = p[l].xx, y = p[l].yy; sort(p + l + 1, p + r); int sum = l + 1; for (int &v : g[u]) if (v != o) { dfs2(u, v, sum, sum + sz[v]); sum += sz[v]; } } int main() { scanf( %d , &n); for (int i = 1, u, v; i < n; ++i) { scanf( %d%d , &u, &v); g[u].emplace_back(v); g[v].emplace_back(u); } for (int i = 0; i < n; ++i) { scanf( %d%d , &p[i].xx, &p[i].yy); p[i].id = i; } dfs(1, 1); dfs2(1, 1, 0, n); for (int i = 0; i < n; ++i) { printf( %d%c , ans[i], n [i == n - 1]); } return 0; }
|
`include "macros.vh"
////////////////////////////////////////////////////////////////////////////////////////////////////
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
// 02111-1307, USA.
//
// ©2013 - Roman Ovseitsev <>
////////////////////////////////////////////////////////////////////////////////////////////////////
//##################################################################################################
//
// Module for receiving RGB565 pixel data from OV camera.
//
//##################################################################################################
// TODO Note this module reads in raw (1 byte) data
// This is also ordering the data as follows
// MSB |15-----8|7-----0| LSB
// PIX | N+1 | N |
module RGBReader (
input pclk, // PCLK
input rst_n, // 0 - Reset.
input [7:0] din, // D0 - D7
input vsync, // VSYNC
input href, // HREF
output reg pixel_valid, // Indicates that a pixel has been received.
output reg [15:0] pixel, // RGB565 pixel.
output vstart, // first pixel of frame
output hstart, // first pixel of line
input start, // pulse
input stop, // TODO does not do anythingh
output reg [31:0] hlen,
output reg [31:0] vlen
);
reg odd;
reg frameValid;
reg href_p2;
reg vsync_p2;
reg saw_vsync;
//hlen should reset every !href
wire href_posedge;
wire href_negedge;
wire vsync_posedge;
assign href_posedge = !href_p2 && href ;
assign href_negedge = href_p2 && !href ;
assign vsync_posedge = !vsync_p2 && vsync ;
reg [31:0] pix_cnt;
`REG(pclk, pix_cnt, 32'h0,
href ? (pix_cnt+1'b1) : 0 )
`REG(pclk, hlen, 0, href_negedge ? pix_cnt : hlen)
reg [31:0] ln_cnt;
`REG(pclk, ln_cnt, 32'h0,
vsync ? 32'h0 : (href_posedge ? ln_cnt+1'b1 : ln_cnt))
`REG(pclk, vlen, 32'h0, vsync_posedge ? ln_cnt : vlen)
// Only anding with pixel_valid just in case
assign hstart = !href_p2 && href ;
assign vstart = hstart && saw_vsync ;
`REG(pclk, saw_vsync, 0,
vsync ? 1'b1 : (vstart ? 1'b0 : saw_vsync)
)
reg running;
`REG(pclk, running, 0,
start ? 1'b1 : running
)
wire [7:0] din2;
assign din2 = din;//{din[0],din[1],din[2],din[3],din[4],din[5],din[6],din[7]};
always @(posedge pclk or negedge rst_n) begin
if (rst_n == 0) begin
pixel_valid <= 0;
odd <= 0;
frameValid <= 0;
href_p2 <= 1'b0;
vsync_p2 <= 1'b0;
end
else begin
pixel_valid <= 0;
href_p2 <= href;
vsync_p2 <= vsync;
if (frameValid == 1 && vsync == 0 && href == 1) begin
if (odd==0) begin
pixel[7:0] <= din2;
end
else begin
pixel[15:8] <= din2;
pixel_valid <= 1;
end
odd <= ~odd;
// skip inital frame in case we started receiving in the middle of it
end
else if (running && frameValid == 0 && vsync == 1) begin
frameValid <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, first, last, ans, flag; cin >> n; if (n <= 2) { cout << 0 << endl; return 0; } ans = flag = 0; first = 1; last = n; for (int i = 1; i < n; i++) { ans += (first + last) % (n + 1); if (!flag) { first++; swap((first), last); } else { first--; swap((first), last); } flag = 1 - flag; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { cin.sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<int> data(n + 1); for (int i = 1; i <= n; i++) cin >> data[i]; int i = 1, j = n; while (j > i && data[j] == data[1]) j--; while (i < j && data[i + 1] == data[1]) i++; cout << max(j - 1, max(j - i, n - i - 1)) << endl; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> std::ostream &operator<<(std::ostream &out, vector<T> &v) { for (typename vector<T>::size_type i = 0; i < v.size(); ++i) out << v[i] << ; out << n ; return out; } template <typename T> std::ostream &operator<<(std::ostream &out, set<T> &s) { for (auto e : s) out << e << ; out << n ; return out; } template <typename T, typename N> std::ostream &operator<<(std::ostream &out, pair<T, N> &p) { out << ( << p.first << , << p.second << ) ; return out; } template <typename T, typename N> std::ostream &operator<<(std::ostream &out, vector<pair<T, N> > &v) { for (size_t i = 0; i < v.size(); ++i) cout << v[i]; out << n ; return out; } template <typename T> std::ostream &operator<<(std::ostream &out, vector<vector<T> > &v) { for (size_t i = 0; i < v.size(); ++i) { for (size_t j = 0; j < v[i].size(); ++j) { out << v[i][j] << ; } out << n ; } return out; } template <typename T> std::ostream &operator<<(std::ostream &out, vector<set<T> > &v) { for (size_t i = 0; i < v.size(); ++i) { out << v[i]; } out << n ; return out; } void solve() { int n; cin >> n; vector<int> a(n); int total = 0; for (int i = 0; i < n; ++i) { cin >> a[i]; total += a[i]; } int diff = 0; for (int i = n - 1; i >= 0; --i) { diff = abs(diff - a[i]); } cout << (total - diff) / 2 << << (total + diff) / 2 << n ; return; } int main() { std::ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; t = 1; while (t--) { solve(); } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 28 18:34:35 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_sync_reset_0_0 -prefix
// system_vga_sync_reset_0_0_ system_vga_sync_reset_0_0_stub.v
// Design : system_vga_sync_reset_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync_reset,Vivado 2016.4" *)
module system_vga_sync_reset_0_0(clk, rst, active, hsync, vsync, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
module microblaze (clk, reset_, led);
input clk, reset_;
output [7:0] led;
wire reset;
wire [31:0] tr_instruction;
wire tr_valid_instruction;
wire [31:0] tr_pc;
wire tr_reg_write;
wire [4:0] tr_reg_addr;
wire [14:0] tr_msr_reg;
wire [31:0] tr_new_reg_val;
wire tr_jump_taken;
wire tr_delay_slot;
wire [31:0] tr_data_addr;
wire tr_data_access;
wire tr_data_read;
wire tr_data_write;
wire [31:0] tr_data_write_val;
wire [3:0] tr_data_byte_en;
wire tr_halted;
// Top-level circuit module that instantiates the MicroBlaze CPU but otherwise
// provides no logic.
// **GOTCHA** Reset on MCS is active high, not active low!
assign reset = ~reset_;
microblaze_mcs_v1_4 mcs_0 (
.Clk(clk), // input 32Mhz clk
.Reset(reset), // input **active high** reset
.GPO1(led), // output [7:0] GPO1
// Trace bus connections: for waveform debugging, only
.Trace_Instruction(tr_instruction),
.Trace_Valid_Instr(tr_valid_instruction),
.Trace_PC(tr_pc),
.Trace_Reg_Write(tr_reg_write),
.Trace_Reg_Addr(tr_reg_addr),
.Trace_MSR_Reg(tr_msr_reg),
.Trace_New_Reg_Value(tr_new_reg_val),
.Trace_Jump_Taken(tr_jump_taken),
.Trace_Delay_Slot(tr_delay_slot),
.Trace_Data_Address(tr_data_addr),
.Trace_Data_Access(tr_data_access),
.Trace_Data_Read(tr_data_read),
.Trace_Data_Write(tr_data_write),
.Trace_Data_Write_Value(tr_data_write_val),
.Trace_Data_Byte_Enable(tr_data_byte_en),
.Trace_MB_Halted(tr_halted)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; int i = n / 2 - 1, j = n / 2; sort(arr, arr + n); int x = 0; int ans[n]; if (n % 2) ans[0] = arr[n / 2], x++, j++; for (; i >= 0 && j < n; i--, j++) { ans[x++] = arr[i]; ans[x++] = arr[j]; } for (int i = 0; i < n; i++) cout << ans[i] << ; cout << endl; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[100]; int main() { long long n, m; cin >> n >> m; int L = 0, R = n - 1; --m; long long sum = 0; for (int i = 1; i < n; ++i) { sum <<= 1; if (m & 1) sum += 1; m >>= 1; } m = sum; for (int i = 1; i <= n; m >>= 1, ++i) { if (m & 1) { a[R--] = i; } else { a[L++] = i; } } cout << a[0]; for (int i = 1; i < n; ++i) { cout << << a[i]; } cout << endl; return 0; }
|
#ifdef Prateek #include Prateek.h #else #include <bits/stdc++.h> using namespace std; #define debug(...) 42 #endif #define int ll #define all(c) begin(c),end(c) using ll = long long; const int MOD = 1e9+7, N = 1e5 + 10; struct edge{ int u, v, w; }; int32_t main(){ ios::sync_with_stdio(false); cin.tie(NULL); int L, R; cin >> L >> R; int B = L - 1; int D = R - L + 1; int k = 30; while (!(D >> k & 1)) --k; int mxN = k + 2; vector<edge> Edge; auto add = [&](int u, int v, int wt) { Edge.push_back({u, v, wt}); }; for (int i = 2; i <= mxN; ++i) { add(1, i, 1); int pw = 1; for (int j = 2; j < i; ++j) { add(j, i, pw); pw *= 2; } } cout << YES n ; if (D - (1 << k) == 0) { if (B) { mxN++; Edge.push_back({mxN - 1, mxN, B}); } cout << mxN << << Edge.size() << n ; for (auto [u, v, w] : Edge) { cout << u << << v << << w << n ; } return 0; } mxN++; --D; add(1, mxN, 1); for (int i = 0; i <= k; ++i) { if (D >> i & 1) { D -= (1 << i); add(i + 2, mxN, D + 1); } } if (B) { mxN++; Edge.push_back({mxN - 1, mxN, B}); } cout << mxN << << Edge.size() << n ; for (auto [u, v, w] : Edge) { cout << u << << v << << w << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; using u64 = unsigned long long; const int mod = 1e9 + 7, N = 2e3 + 10; char mp[N][N]; int f[N][N]; bool st[N][N]; unordered_map<char, pair<int, int>> mv = { { L , {0, -1}}, { R , {0, 1}}, { U , {-1, 0}}, { D , {1, 0}}}; int main(void) { int t; cin >> t; while (t--) { int n, m, tx, ty; cin >> n >> m; for (int i = 1; i <= n; i++) scanf( %s , &mp[i][1]); stack<pair<int, int>> q; for (int i = 0; i <= n + 1; i++) for (int j = 0; j <= m + 1; j++) f[i][j] = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { int x = i, y = j; bool ring = false; if (f[x][y] != 1) continue; do { q.push({x, y}); st[x][y] = true; tx = x + mv[mp[x][y]].first, ty = y + mv[mp[x][y]].second; x = tx, y = ty; if (x < 1 || x > n || y < 1 || y > m) break; if (st[x][y]) { ring = true; break; } if (f[x][y] != 1) { q.push({x, y}); break; } } while (true); pair<int, int> xy; int step; if (ring) { stack<pair<int, int>> rq; do { xy = q.top(); q.pop(); st[xy.first][xy.second] = false; rq.push(xy); if (xy.first == x && xy.second == y) break; } while (true); step = rq.size(); while (rq.size()) { xy = rq.top(); rq.pop(); f[xy.first][xy.second] = step; } step++; while (q.size()) { xy = q.top(); q.pop(); st[xy.first][xy.second] = false; f[xy.first][xy.second] = step++; } continue; } step = f[q.top().first][q.top().second]; while (q.size()) { xy = q.top(); q.pop(); st[xy.first][xy.second] = false; f[xy.first][xy.second] = step++; } } } int res = -1, x, y; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (res < f[i][j]) { x = i, y = j; res = f[i][j]; } } } cout << x << << y << << res << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int main() { string s; cin >> s; int cnt0, cnt1, len = s.size(); string t(len, 0 ); cnt0 = cnt1 = 0; for (int i = len - 1; i >= 0; --i) { if (s[i] == 0 ) ++cnt0; else { if (cnt0 != cnt1) t[i] = 1 ; else ++cnt0; ++cnt1; } } cout << t << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; double n; long int sum = 0; for (int i = 0; i < q; i++) { cin >> n; long long int a; for (int j = 0; j < n; j++) { cin >> a; sum += a; } cout << fixed << setprecision(0) << ceill((sum / n)) << endl; sum = 0; } }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: tlu_addern_32.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: parameterized adder macro
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module tlu_addern_32 (din, incr, sum);
// synopsys template
parameter ADDER_DATA_WIDTH = 33;
parameter INCR_DATA_WIDTH = 1;
parameter UPPER_DATA_WIDTH = ADDER_DATA_WIDTH - INCR_DATA_WIDTH;
input [ADDER_DATA_WIDTH-1:0] din;
input [INCR_DATA_WIDTH-1:0] incr;
output [ADDER_DATA_WIDTH-1:0] sum;
//
////////////////////////////////////////////////////////////////////////
// local signal declaraiont
////////////////////////////////////////////////////////////////////////
assign sum[ADDER_DATA_WIDTH-1:0] =
din[ADDER_DATA_WIDTH-1:0] + {{UPPER_DATA_WIDTH{1'b0}},incr[INCR_DATA_WIDTH-1:0]};
endmodule // tlu_addern_32
|
#include <bits/stdc++.h> using namespace std; const long long inf = 0x3f3f3f3f; const int N = 5e5 + 10; int a[8008]; int n, ans = 0; string s, ss, sss; map<string, int> mp; void str() { cin >> ss; int sum = 0; string x = ; for (int i = 0; i < ss.length(); i++) { if (ss[i] == & ) sum--; else if (ss[i] == * ) sum++; else x += ss[i]; } ans = mp[x]; if (ans > 0) ans += sum; else ans = 0; } int main() { mp[ void ] = 1; cin >> n; while (n--) { cin >> s; ans = 0; if (s == typedef ) { str(); cin >> sss; mp[sss] = ans; } else { str(); ans--; if (ans < 0) cout << errtype << endl; else { cout << void ; for (int i = 0; i < ans; i++) cout << * ; cout << endl; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; double pi = M_PI; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { long long n; cin >> n; n = n * 2; double angle = ((n - 2) * M_PI) / (2 * n); cout << fixed << setprecision(9) << tan(angle); cout << n ; } }
|
#include <bits/stdc++.h> const int inf = 2 * 1e9; const int mod = 1e9 + 7; const long long infll = (long long)1e18; const long double eps = 1e-9; const int dx[] = {1, 0, -1, 0}; const int dy[] = {0, -1, 0, 1}; const int MAXY = 1005000; using namespace std; int n, m; vector<vector<pair<int, int>>> g; vector<bool> used; vector<int> topsort; void dfs(int v, int time) { used[v] = true; for (int i = 0; i < g[v].size(); i++) { int to = g[v][i].first; int edgeTime = g[v][i].second; if (edgeTime <= time) { if (!used[to]) dfs(to, time); } } topsort.push_back(v); } bool check(int time) { used.assign(n, false); topsort.clear(); for (int i = 0; i < n; i++) { if (!used[i]) dfs(i, time); } reverse(topsort.begin(), topsort.end()); for (int i = 0; i < (n - 1); i++) { int cur = topsort[i]; int nxt = topsort[i + 1]; bool ok = false; for (int j = 0; j < g[cur].size(); j++) { if (g[cur][j].second <= time) ok = ok || g[cur][j].first == nxt; } if (!ok) return false; } return true; } void solve() { cin >> n >> m; g.resize(n); used.resize(n); for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; x--; y--; g[x].push_back(make_pair(y, i)); } if (!check(m - 1)) { cout << -1; return; } int tl = 0; int tr = m - 1; while (tr - tl > 1) { int tm = (tl + tr) / 2; if (check(tm)) tr = tm; else tl = tm; } cout << tr + 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); solve(); return 0; }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* The internal logic cell simulation library.
*
* This Verilog library contains simple simulation models for the internal
* logic cells (_NOT_, _AND_, ...) that are generated by the default technology
* mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
*
*/
module _NOT_(A, Y);
input A;
output Y;
assign Y = ~A;
endmodule
module _AND_(A, B, Y);
input A, B;
output Y;
assign Y = A & B;
endmodule
module _OR_(A, B, Y);
input A, B;
output Y;
assign Y = A | B;
endmodule
module _XOR_(A, B, Y);
input A, B;
output Y;
assign Y = A ^ B;
endmodule
module _MUX_(A, B, S, Y);
input A, B, S;
output reg Y;
always @* begin
if (S)
Y = B;
else
Y = A;
end
endmodule
module _DFF_N_(D, Q, C);
input D, C;
output reg Q;
always @(negedge C) begin
Q <= D;
end
endmodule
module _DFF_P_(D, Q, C);
input D, C;
output reg Q;
always @(posedge C) begin
Q <= D;
end
endmodule
module _DFF_NN0_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
endmodule
module _DFF_NN1_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(negedge C or negedge R) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
endmodule
module _DFF_NP0_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
endmodule
module _DFF_NP1_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(negedge C or posedge R) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module _DFF_PN0_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 0;
else
Q <= D;
end
endmodule
module _DFF_PN1_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
if (R == 0)
Q <= 1;
else
Q <= D;
end
endmodule
module _DFF_PP0_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 0;
else
Q <= D;
end
endmodule
module _DFF_PP1_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(posedge C or posedge R) begin
if (R == 1)
Q <= 1;
else
Q <= D;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 22; long long a[N]; long long dp[N][N][N]; long long DP(long long pos, long long sum, long long limit) { if (!pos) return 1; if (!limit && dp[pos][sum][limit] != -1) return dp[pos][sum][limit]; long long high = limit ? a[pos] : 9; long long ans = 0; for (long long i = 0; i <= high; i++) { if (sum == 3 && i != 0) continue; ans += DP(pos - 1, sum + (i != 0), limit && (i == high)); } if (!limit) dp[pos][sum][limit] = ans; return ans; } long long slove(long long n) { long long len = 0; while (n) { a[++len] = n % 10; n = n / 10; } return DP(len, 0, 1); } signed main() { memset(dp, -1, sizeof(dp)); long long T; cin >> T; while (T--) { long long L, R; cin >> L >> R; cout << slove(R) - slove(L - 1) << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O311A_PP_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MX = 1e5 + 5; int n; int M[9][2] = {{0, 0}, {-1, -1}, {1, 1}, {0, 1}, {1, 0}, {0, -1}, {-1, 0}, {1, -1}, {-1, 1}}; int compute(vector<int> Arr, int A0, int A1, int val) { Arr[0] = A0; Arr[1] = A1; int d = Arr[1] - Arr[0]; int ans = val; for (int i = 2; i < n; i++) { if (d + Arr[i - 1] != Arr[i]) { if (d + Arr[i - 1] != Arr[i] + 1) { if (d + Arr[i - 1] != Arr[i] - 1) { return -1; } else { Arr[i]--; ans++; } } else { Arr[i]++; ans++; } } } return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int val; cin >> n; vector<int> A; for (int i = 0; i < n; cin >> val, A.push_back(val), i++) ; int ans = -1; for (int i = 0; i < 9; i++) { int num = compute(A, A[0] + M[i][0], A[1] + M[i][1], abs(M[i][0]) + abs(M[i][1])); if (num != -1) { if (ans == -1) ans = num; else ans = min(ans, num); } } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_TB_V
`define SKY130_FD_SC_MS__SDFXBP_TB_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfxbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_TB_V
|
#include <bits/stdc++.h> using namespace std; long long modexpo(long long x, long long p) { long long res = 1; x = x % 1000000007; while (p) { if (p % 2) res = res * x; p >>= 1; x = x * x % 1000000007; res %= 1000000007; } return res; } struct compare { bool operator()(const pair<long long, long long> a, const pair<long long, long long> b) const { return a.first < b.first; } }; void __solve__(long long testCase) { long long x, y, ans = 2e18 + 7; cin >> y >> x; vector<long long> c(6); for (long long &e : c) cin >> e; for (long long i = 0; i < 3; i++) for (long long j = 0; j < 3; j++) { long long s = 0; if (i == j) { if (i == 0 && y == 0) if (x > 0) s += c[1] * x; else s += c[4] * -x; if (i == 1 && x == 0) if (y > 0) s += c[5] * y; else s += c[2] * -y; if (i == 2 && x == y) if (x > 0) s += c[0] * x; else s += c[3] * -x; if (s) ans = min(ans, s); continue; } else if (i != 2 && j != 2) { if (x > 0) s += c[1] * x; else s += c[4] * -x; if (y > 0) s += c[5] * y; else s += c[2] * -y; } else { if (j == 0 || i == 0) { if (y > 0) s += c[0] * y; else s += c[3] * -y; if (x - y > 0) s += c[1] * (x - y); else s += c[4] * -(x - y); } else { if (x > 0) s += c[0] * x; else s += c[3] * -x; if (y - x > 0) s += c[5] * (y - x); else s += c[2] * -(y - x); } } ans = min(ans, s); } cout << ans << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long testCase = 1; cin >> testCase; for (long long tc = 1; tc <= testCase; tc++) { __solve__(tc); } }
|
//////////////////////////////////////////////////////////////////////////////
/// Copyright (c) 2014, Ajit Mathew <>
/// All rights reserved.
///
// Redistribution and use in source and binary forms, with or without modification,
/// are permitted provided that the following conditions are met:
///
/// * Redistributions of source code must retain the above copyright notice,
/// this list of conditions and the following disclaimer.
/// * Redistributions in binary form must reproduce the above copyright notice,
/// this list of conditions and the following disclaimer in the documentation and/or
/// other materials provided with the distribution.
///
/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
/// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
/// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
/// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
/// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
/// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
/// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
/// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
/// POSSIBILITY OF SUCH DAMAGE.
///
///
/// * http://opensource.org/licenses/MIT
/// * http://copyfree.org/licenses/mit/license.txt
///
//////////////////////////////////////////////////////////////////////////////
module uart
#(
parameter Data_Bits = 8,
StopBits_tick = 16,
DIVISOR = 326, // divider circuit = 50M/(16*baud rate)
DVSR_BIT = 9, // # bits of divider circuit
FIFO_Add_Bit = 4
)
(
input wire clk, reset,
input wire rd_uart, wr_uart, rx,
input wire [7:0] w_data,
output wire tx_empty, rx_empty, tx,
output wire [7:0] r_data
);
wire tck, rx_done_tck, tx_done_tck;
wire tx_full, tx_fifo_not_empty;
wire [7:0] tx_fifo_out, rx_data_out;
assign clkout=clk;
//body
counter #(.M(DIVISOR), .N(DVSR_BIT)) baud_gen_unit
(.clk(clkout), .reset(reset), .q(), .max_tck(tck));
uart_rx #(.DBIT(Data_Bits), .SB_tck(StopBits_tick)) uart_rx_unit
(.clk(clkout), .reset(reset), .rx(rx), .s_tck(tck),
.rx_done_tck(rx_done_tck), .dout(rx_data_out));
fifo #(.B(Data_Bits), .W(FIFO_Add_Bit )) fifo_rx_unit
(.clk(clkout), .reset(reset), .rd(rd_uart),
.wr(rx_done_tck), .w_data(rx_data_out),
.empty(rx_empty), .full(), .r_data(r_data));
fifo #(.B(Data_Bits), .W(FIFO_Add_Bit )) fifo_tx_unit
(.clk(clkout), .reset(reset), .rd(tx_done_tck),
.wr(wr_uart), .w_data(w_data), .empty(tx_empty),
.full(tx_full), .r_data(tx_fifo_out));
uart_tx #(.DBIT(Data_Bits), .SB_tck(StopBits_tick)) uart_tx_unit
(.clk(clkout), .reset(reset), .tx_start(tx_fifo_not_empty),
.s_tck(tck), .din(tx_fifo_out),
.tx_done_tck(tx_done_tck), .tx(tx));
assign tx_fifo_not_empty = ~tx_empty;
endmodule
|
module lcd_display (
input [63:0] f1, // 1st row
input [63:0] f2, // 2nd row
input [15:0] m1, // 1st row mask
input [15:0] m2, // 2nd row mask
input clk, // 100 Mhz clock
input rst,
// Pad signals
output reg lcd_rs_,
output reg lcd_rw_,
output reg lcd_e_,
output reg [7:4] lcd_dat_
);
// Parameter definitions
parameter n = 8;
parameter k = 16;
// Register declarations
reg [k+n+1:0] cnt = 0;
reg [ 5:0] lcd;
// Net declarations
wire [127:0] f;
wire [ 31:0] m;
wire [ 4:0] i;
wire [ 3:0] c;
// Module instantiations
sel128_4 sel (
.in (f),
.sel (i),
.out (c)
);
// Continuous assignments
assign f = { f1, f2 };
assign m = { m1, m2 };
assign i = cnt[k+7:k+3];
// Behaviour
always @(posedge clk)
if (rst) cnt <= 26'hfffffff;
else begin
cnt <= cnt - 1;
casex (cnt[k+1+n:k+2])
8'hff: lcd <= 6'b000010; // function set
8'hfe: lcd <= 6'b000010;
8'hfd: lcd <= 6'b001000;
8'hfc: lcd <= 6'b000000; // display on/off control
8'hfb: lcd <= 6'b001100;
8'hfa: lcd <= 6'b000000; // display clear
8'hf9: lcd <= 6'b000001;
8'hf8: lcd <= 6'b000000; // entry mode set
8'hf7: lcd <= 6'b000110;
8'hf6: cnt[k+1+n:k+2] <= 8'b10111111;
8'b101xxxx1: lcd <= { 2'b10, m[i] ? itoa1(c) : 4'h2 };
8'b101xxxx0: lcd <= { 2'b10, m[i] ? itoa0(c) : 4'h0 };
8'b10011111: lcd <= 6'h0c;
8'b10011110: lcd <= 6'h00;
8'b10011101: cnt[k+1+n:k+2] <= 8'b01011111;
8'b010xxxx1: lcd <= { 2'b10, m[i] ? itoa1(c) : 4'h2 };
8'b010xxxx0: lcd <= { 2'b10, m[i] ? itoa0(c) : 4'h0 };
8'b00111111: lcd <= 6'h08;
8'b00111110: lcd <= 6'h00;
8'b00111101: cnt[k+1+n:k+2] <= 8'b10111111;
default: lcd <= 6'b010000;
endcase
lcd_e_ <= ^cnt[k+1:k+0] & ~lcd_rw_;
{ lcd_rs_, lcd_rw_, lcd_dat_ } <= lcd;
end
// Function definitions
function [3:0] itoa1;
input [3:0] i;
begin
if (i < 8'd10) itoa1 = 4'h3;
else itoa1 = 4'h6;
end
endfunction
function [3:0] itoa0;
input [3:0] i;
begin
if (i < 8'd10) itoa0 = i + 4'h0;
else itoa0 = i + 4'h7;
end
endfunction
endmodule
module sel128_4 (
input [127:0] in,
input [ 4:0] sel,
output reg [ 3:0] out
);
always @(in or sel)
case (sel)
5'h00: out <= in[ 3: 0];
5'h01: out <= in[ 7: 4];
5'h02: out <= in[ 11: 8];
5'h03: out <= in[ 15: 12];
5'h04: out <= in[ 19: 16];
5'h05: out <= in[ 23: 20];
5'h06: out <= in[ 27: 24];
5'h07: out <= in[ 31: 28];
5'h08: out <= in[ 35: 32];
5'h09: out <= in[ 39: 36];
5'h0a: out <= in[ 43: 40];
5'h0b: out <= in[ 47: 44];
5'h0c: out <= in[ 51: 48];
5'h0d: out <= in[ 55: 52];
5'h0e: out <= in[ 59: 56];
5'h0f: out <= in[ 63: 60];
5'h10: out <= in[ 67: 64];
5'h11: out <= in[ 71: 68];
5'h12: out <= in[ 75: 72];
5'h13: out <= in[ 79: 76];
5'h14: out <= in[ 83: 80];
5'h15: out <= in[ 87: 84];
5'h16: out <= in[ 91: 88];
5'h17: out <= in[ 95: 92];
5'h18: out <= in[ 99: 96];
5'h19: out <= in[103:100];
5'h1a: out <= in[107:104];
5'h1b: out <= in[111:108];
5'h1c: out <= in[115:112];
5'h1d: out <= in[119:116];
5'h1e: out <= in[123:120];
5'h1f: out <= in[127:124];
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double eps = 1e-9; const int inf = 2000000000; const long long infLL = 9000000000000000000; inline bool checkBit(long long n, int i) { return n & (1LL << i); } inline long long setBit(long long n, int i) { return n | (1LL << i); ; } inline long long resetBit(long long n, int i) { return n & (~(1LL << i)); } int dx[] = {0, 0, +1, -1}; int dy[] = {+1, -1, 0, 0}; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline bool isLeapYear(long long year) { return (year % 400 == 0) || (year % 4 == 0 && year % 100 != 0); } inline void normal(long long &a) { a %= 1000000007; (a < 0) && (a += 1000000007); } inline long long modMul(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); return (a * b) % 1000000007; } inline long long modAdd(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); return (a + b) % 1000000007; } inline long long modSub(long long a, long long b) { a %= 1000000007, b %= 1000000007; normal(a), normal(b); a -= b; normal(a); return a; } inline long long modPow(long long b, long long p) { long long r = 1; while (p) { if (p & 1) r = modMul(r, b); b = modMul(b, b); p >>= 1; } return r; } inline long long modInverse(long long a) { return modPow(a, 1000000007 - 2); } inline long long modDiv(long long a, long long b) { return modMul(a, modInverse(b)); } const int MX = 10100; int vis[5][5][5], l[5], r[5], curnum, n; double dp[5][5][5]; double func(int pos, int eNum, int bNum) { if (bNum > 1) return 0; if (pos == n) { if (eNum > 1 && !bNum) return 1; if (eNum && bNum) return 1; return 0; } if (vis[pos][eNum][bNum]) return dp[pos][eNum][bNum]; vis[pos][eNum][bNum] = 0; double &ret = dp[pos][eNum][bNum]; ret = 0; if (curnum >= l[pos] && curnum <= r[pos]) { double temp = (1.0 / (r[pos] - l[pos] + 1)); temp *= func(pos + 1, eNum + 1, bNum); ret += temp; } if (r[pos] > curnum) { double temp = 1; if (l[pos] <= curnum) { temp *= (double)(r[pos] - curnum) / (double)(r[pos] - l[pos] + 1); } temp *= func(pos + 1, eNum, bNum + 1); ret += temp; } if (l[pos] < curnum) { double temp = 1; if (r[pos] >= curnum) { temp *= (double)(curnum - l[pos]) / (double)(r[pos] - l[pos] + 1); } temp *= func(pos + 1, eNum, bNum); ret += temp; } return ret; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cout.unsetf(ios::floatfield); cout.precision(10); cout.setf(ios::fixed, ios::floatfield); ; cin >> n; for (int i = 0; i < n; ++i) cin >> l[i] >> r[i]; double ans = 0; for (int i = 1; i < MX; ++i) { curnum = i; ans += i * func(0, 0, 0); ; memset(vis, 0, sizeof(vis)); } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_12_V
`define SKY130_FD_SC_HDLL__BUF_12_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 12 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__buf_12 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__buf_12 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_12_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j = 0; char d; cin >> n; string s; cin >> s; char a[n][n + 1]; for (i = 0; i < n; i++) { s.copy(a[i], n - i, i), s.copy(a[i] + (n - i), i), a[i][n] = 0; d = ( 9 - a[i][0] + 1) % 10; for (j = 0; j < n; j++) a[i][j] = (((a[i][j] + d) > 9 ) ? (a[i][j] - 10) : a[i][j]) + d; } for (i = 1, j = 0; i < n; i++) j = ((strcmp(a[i], a[j]) < 0) ? i : j); puts(a[j]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n & n - 1) puts( NO ); else puts( YES ); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Edge { int x; int y; int w; }; const int N = 200 + 7; const int INF = (int)1e9; int n; int m; int d[N][N]; struct T { int f; int s; }; bool operator<(T a, T b) { return a.s - a.f < b.s - b.f; } int solve(int x, int y, int w) { vector<T> pts; for (int i = 1; i <= n; i++) { pts.push_back({d[x][i], d[y][i] + w}); } sort(pts.begin(), pts.end()); vector<int> pre(n), suf(n); pre[0] = pts[0].s; for (int i = 1; i < n; i++) { pre[i] = max(pre[i - 1], pts[i].s); } suf[n - 1] = pts[n - 1].f; for (int i = n - 2; i >= 0; i--) { suf[i] = max(suf[i + 1], pts[i].f); } vector<int> tt(n); for (int i = 0; i < n; i++) { tt[i] = (pts[i].s - pts[i].f) / 2; } int ret = INF; for (int last = -1; last < n; last++) { if (last == -1) { int m_suf = suf[last + 1]; int t = tt[last + 1]; ret = min(ret, m_suf + t); continue; } if (last == n - 1) { int m_pre = pre[last]; int t = tt[last]; ret = min(ret, m_pre - t); continue; } int t1 = tt[last]; int t2 = tt[last + 1]; int m_pre = pre[last]; int m_suf = suf[last + 1]; ret = min(ret, max(m_suf + t1, m_pre - t1)); ret = min(ret, max(m_suf + t2, m_pre - t2)); int t = (m_pre - m_suf) / 2; if (t1 <= t && t <= t2) { ret = min(ret, max(m_suf + t, m_pre - t)); } } return ret; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { d[i][j] = INF; } d[i][i] = 0; } vector<Edge> e(m); for (int i = 0; i < m; i++) { cin >> e[i].x >> e[i].y >> e[i].w; e[i].w *= 2; d[e[i].x][e[i].y] = d[e[i].y][e[i].x] = e[i].w; } for (int k = 1; k <= n; k++) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { d[i][j] = min(d[i][j], d[i][k] + d[k][j]); } } } solve(e[0].x, e[0].y, e[0].w); int ret = INF; for (auto &it : e) { ret = min(ret, solve(it.x, it.y, it.w)); } if (ret % 2 == 0) { cout << ret / 2 << .0 n ; } else { cout << ret / 2 << .5 n ; } }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T1, class T2> inline void gn(T1 &x1, T2 &x2) { gn(x1), gn(x2); } pair<int, int> edge[500010]; int w[500010]; int n, m, Q; int id[500010]; int col[1010]; int root[1010]; int rev[500010]; inline int find_root(int u) { if (root[u] == u) return u; int first = find_root(root[u]); col[u] ^= col[root[u]]; return root[u] = first; } int main() { gn(n, m); gn(Q); for (int i = 1; i <= m; i++) { gn(edge[i].first, edge[i].second); gn(w[i]); } for (int i = 1; i <= m; i++) id[i] = i; sort(id + 1, id + m + 1, [&](int u, int v) { return w[u] > w[v]; }); while (Q--) { int L, R; gn(L, R); for (int i = 1; i <= n; i++) { col[i] = 0; root[i] = i; } int ans = -1; for (int i = 1; i <= m; i++) { if (id[i] > R || id[i] < L) continue; int u = edge[id[i]].first, v = edge[id[i]].second; if (find_root(u) == find_root(v)) { if (col[u] == col[v]) { ans = w[id[i]]; break; } continue; } col[root[u]] = col[u] ^ col[v] ^ 1; root[root[u]] = root[v]; } printf( %d n , ans); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A221OI_2_V
`define SKY130_FD_SC_HDLL__A221OI_2_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a221oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a221oi_2 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A221OI_2_V
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mwram_m20k.v: Altera's M20K mixed width RAM //
// //
// Author: Ameer M.S. Abdelhadi (, ) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
// M20K Block Mixed-Width Configurations (Simple Dual-Port RAM Mode)
// --------------------------------------------------------------------------------
// | Write | 16384 | 8192 | 4096 | 4096 | 2048 | 2048 | 1024 | 1024 | 512 | 512 |
// | Read | X 1 | X 2 | X 4 | X 5 | X 8 | X 10 | X 16 | X 20 | X32 | X40 |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// |16384 X 1 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 8192 X 2 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 4096 X 4 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 4096 X 5 | | | | Yes | | Yes | | Yes | | Yes |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 2048 X 8 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 2048 X 10 | | | | Yes | | Yes | | Yes | | Yes |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 1024 X 16 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 1024 X 20 | | | | Yes | | Yes | | Yes | | Yes |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 512 X 32 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 512 X 40 | | | | Yes | | Yes | | Yes | | Yes |
// --------------------------------------------------------------------------------
`include "utils.vh"
module mwram_m20k
#( parameter WR_DW = 1 , // write width
parameter RD_DW = 32 , // read width
parameter IZERO = 1 ) // initialize to zeros
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [13-`log2f(WR_DW):0] wAddr , // write address
input [WR_DW-1 :0] wData , // write data
input [13-`log2f(RD_DW):0] rAddr , // read address
output [RD_DW-1 :0] rData ); // read data
localparam WRADDRW = 14-`log2f(WR_DW); // write address width
localparam RDADDRW = 14-`log2f(RD_DW); // read address width
// Altera's M20K mixed width RAM instantiation
altsyncram #( .address_aclr_b ("CLEAR0" ),
.address_reg_b ("CLOCK0" ),
.clock_enable_input_a ("BYPASS" ),
.clock_enable_input_b ("BYPASS" ),
.clock_enable_output_b ("BYPASS" ),
.intended_device_family ("Stratix V" ),
.lpm_type ("altsyncram" ),
.numwords_a (2**WRADDRW ),
.numwords_b (2**RDADDRW ),
.operation_mode ("DUAL_PORT" ),
.outdata_aclr_b ("CLEAR0" ),
.outdata_reg_b ("UNREGISTERED" ),
.power_up_uninitialized (IZERO ? "FALSE" : "TRUE"),
.ram_block_type ("M20K" ),
.read_during_write_mode_mixed_ports("OLD_DATA" ),
.widthad_a (WRADDRW ),
.widthad_b (RDADDRW ),
.width_a (WR_DW ),
.width_b (RD_DW ),
.width_byteena_a (1 ))
altsyncram_mw ( .aclr0 (rst ),
.address_a (wAddr ),
.clock0 (clk ),
.data_a (wData ),
.wren_a (wEnb ),
.address_b (rAddr ),
.q_b (rData ),
.aclr1 (1'b0 ),
.addressstall_a (1'b0 ),
.addressstall_b (1'b0 ),
.byteena_a (1'b1 ),
.byteena_b (1'b1 ),
.clock1 (1'b1 ),
.clocken0 (1'b1 ),
.clocken1 (1'b1 ),
.clocken2 (1'b1 ),
.clocken3 (1'b1 ),
.data_b ({RD_DW{1'b1}} ),
.eccstatus ( ),
.q_a ( ),
.rden_a (1'b1 ),
.rden_b (1'b1 ),
.wren_b (1'b0 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int p[1001000]; int main() { int a, b, k; cin >> a >> b >> k; for (int i = 2; i <= b + 20; i++) p[i] = 1; for (int i = 2; i <= b + 20; i++) if (p[i]) for (int j = i + i; j <= b + 10; j = j + i) p[j] = 0; for (int i = 1; i < b + 10; i++) p[i] = p[i] + p[i - 1]; int lo, hi, m; lo = 0; hi = b - a + 2; while (lo < hi) { int f = 1; m = (lo + hi) / 2; for (int i = a - 1; i + m <= b; i++) { if (p[i + m] - p[i] < k) { f = 0; break; } } if (f == 1) { hi = m; } else lo = m + 1; } if (lo > b - a + 1) { cout << -1 << endl; } else cout << lo << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_M_V
`define SKY130_FD_SC_LP__A31O_M_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_m (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_m (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_M_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/);
initial begin
string q[$];
string v;
int i;
int qi[$:5];
int ri[$];
q.push_front("non-empty");
i = q.size(); `checkh(i, 1);
v = $sformatf("%p", q); `checks(v, "'{\"non-empty\"} ");
q = '{};
i = q.size(); `checkh(i, 0);
q = '{"q"};
v = $sformatf("%p", q); `checks(v, "'{\"q\"} ");
q = {};
i = q.size(); `checkh(i, 0);
q = '{"q", "b", "c", "d", "e", "f"};
if (q[0] !== "q") $stop;
v = $sformatf("%p", q); `checks(v, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"} ");
q = {"q", "b", "c", "d", "e", "f"};
v = $sformatf("%p", q); `checks(v, "'{\"q\", \"b\", \"c\", \"d\", \"e\", \"f\"} ");
q.delete(1);
v = q[1]; `checks(v, "c");
v = $sformatf("%p", q); `checks(v, "'{\"q\", \"c\", \"d\", \"e\", \"f\"} ");
q.insert(0, "ins0");
q.insert(2, "ins2");
v = q[0]; `checks(v, "ins0");
v = q[2]; `checks(v, "ins2");
v = $sformatf("%p", q); `checks(v, "'{\"ins0\", \"q\", \"ins2\", \"c\", \"d\", \"e\", \"f\"} ");
// Slicing
q = '{"q", "b", "c", "d", "e", "f"};
q = q[-1:0];
v = $sformatf("%p", q); `checks(v, "'{\"q\"} ");
q = '{"q", "b", "c", "d", "e", "f"};
q = q[2:3];
v = $sformatf("%p", q); `checks(v, "'{\"c\", \"d\"} ");
q = '{"q", "b", "c", "d", "e", "f"};
q = q[3:$];
v = $sformatf("%p", q); `checks(v, "'{\"d\", \"e\", \"f\"} ");
q = q[$:$];
v = $sformatf("%p", q); `checks(v, "'{\"f\"} ");
// Similar using implied notation
q = '{"f"};
q = {q, "f1"}; // push_front
q = {q, "f2"}; // push_front
q = {"b1", q}; // push_back
q = {"b2", q}; // push_back
v = $sformatf("%p", q); `checks(v, "'{\"b2\", \"b1\", \"f\", \"f1\", \"f2\"} ");
q = {q[0], q[2:$]}; // delete element 1
v = $sformatf("%p", q); `checks(v, "'{\"b2\", \"f\", \"f1\", \"f2\"} ");
q = {"a", "b"};
q = {q, q};
v = $sformatf("%p", q); `checks(v, "'{\"a\", \"b\", \"a\", \"b\"} ");
begin
string ai[$] = '{ "Foo", "Bar" };
q = ai; // Copy
i = q.size(); `checkh(i, 2);
v = q.pop_front(); `checks(v, "Foo");
v = q.pop_front(); `checks(v, "Bar");
q = '{ "BB", "CC" }; // Note '{} not {}
v = q.pop_front(); `checks(v, "BB");
v = q.pop_front(); `checks(v, "CC");
q = { "BB", "CC" }; // Note {} not '{}
v = q.pop_front(); `checks(v, "BB");
v = q.pop_front(); `checks(v, "CC");
end
begin
qi.push_back(0);
qi.push_back(1);
qi.push_back(2);
qi.push_back(3);
qi.push_back(4);
qi.push_back(5);
// Assignment to unsized queue from sized queue
ri = qi[ 2 : 4 ];
`checkh(ri.size, 3);
ri = qi[ 4 : 2 ];
`checkh(ri.size, 0);
ri = qi[ 2 : 2 ];
`checkh(ri.size, 1);
ri = qi[ -2 : 2 ]; // 2 - 0 + 1 = 3
`checkh(ri.size, 3);
ri = qi[ 2 : 10 ]; // 5 - 2 + 1 = 4
`checkh(ri.size, 4);
// Assignment from unsized to sized
ri = '{1,2,3,4,5,6,7,8,9};
qi = ri;
`checkh(qi.size, 5);
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int i, j, k; int n; cin >> n; int x = n / 4; string s = abcd ; string ans = ; if (n % 4 == 0) for (i = 0; i < x; i++) ans += s; else { if (n % 4 == 1) { for (i = 0; i < x; i++) ans += s; ans += a ; } if (n % 4 == 2) { for (i = 0; i < x; i++) ans += s; ans += ab ; } if (n % 4 == 3) { for (i = 0; i < x; i++) ans += s; ans += abc ; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e16 + 3; const int mod = 1e9 + 7; const int lim = 2e5 + 2; int q, ni; string str; void solve() { cin >> q; while (q--) { cin >> ni >> str; if (ni > 2) { cout << YES << n ; cout << 2 << n ; cout << str[0] << ; for (int i = 1; i < ni; i++) cout << str[i]; cout << n ; } else { int f = str[0] - 0 ; int s = str[1] - 0 ; if (f < s) { cout << YES << n ; cout << 2 << n ; cout << str[0] << << str[1] << n ; } else cout << NO << n ; } } } void fastIO() { cin.sync_with_stdio(false); cin.tie(0); } void IO() { if (fopen( d: lmo.in , r ) != NULL) { freopen( d: lmo.in , r , stdin); } else if (fopen( /media/luismo/Pablo s Destruction/lmo.in , r ) != NULL) { freopen( /media/luismo/Pablo s Destruction/lmo.in , r , stdin); } } int main() { IO(); fastIO(); solve(); }
|
#include <bits/stdc++.h> using namespace std; const int N = 400005; multiset<int> S; int x, y, n, m, k; map<pair<int, int>, int> flag; struct Tree { int l, r, num, flag; } T[N * 4]; void build(int x, int l, int r) { T[x].l = l; T[x].r = r; if (l == r) { T[x].num = l - 1; return; } int mid = (l + r) / 2; build(x * 2, l, mid); build(x * 2 + 1, mid + 1, r); T[x].num = max(T[x * 2].num, T[x * 2 + 1].num); } void down(int x) { T[x * 2].num += T[x].flag; T[x * 2 + 1].num += T[x].flag; T[x * 2].flag += T[x].flag; T[x * 2 + 1].flag += T[x].flag; T[x].flag = 0; } void insert(int x, int l, int r, int z) { if (T[x].l > r || l > T[x].r) return; if (T[x].l >= l && T[x].r <= r) { T[x].num += z; T[x].flag += z; return; } down(x); insert(x * 2, l, r, z); insert(x * 2 + 1, l, r, z); T[x].num = max(T[x * 2].num, T[x * 2 + 1].num); } int find(int x, int l, int r) { if (T[x].l > r || l > T[x].r) return 0; if (T[x].l >= l && T[x].r <= r) return T[x].num; down(x); return max(find(x * 2, l, r), find(x * 2 + 1, l, r)); } int main() { scanf( %d%d%d , &n, &k, &m); build(1, 1, n + n); S.insert(n + 1); while (m--) { scanf( %d%d , &x, &y); if (flag[make_pair(x, y)]) { S.erase(S.find(y + abs(x - k))); flag[make_pair(x, y)] = 0; insert(1, 1, y + abs(x - k), -1); } else { S.insert(y + abs(x - k)); flag[make_pair(x, y)] = 1; insert(1, 1, y + abs(x - k), 1); } printf( %d n , find(1, 1, *S.rbegin()) - n); } }
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#include <bits/stdc++.h> using namespace std; void solve() { int n, m; cin >> n >> m; int arr[n], brr[m]; for (int i = 0; i < n; i++) { cin >> arr[i]; } for (int i = 0; i < m; i++) { cin >> brr[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (arr[i] == brr[j]) { cout << YES << n ; cout << 1 << << arr[i] << n ; return; } } } cout << NO << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); ; int t = 1; cin >> t; while (t--) solve(); }
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module convolution(outr,outi,a,b);
input [15:0] a, b;
output [17:0] outr, outi;
wire signed [7:0] a_rea, a_ima, b_rea, b_ima;
assign a_rea = a[15:8]; assign a_ima = a[7:0];
assign b_rea = b[15:8]; assign b_ima = b[7:0];
assign outr = a_rea*b_rea - a_ima*b_ima;
assign outi = a_rea*b_ima + a_ima*b_rea;
endmodule
module correlation(outr,outi,a,b);
input [15:0] a, b;
output signed [17:0] outr, outi;
wire signed [7:0] a_rea, a_ima, b_rea, b_ima;
assign a_rea = a[15:8]; assign a_ima = a[7:0];
assign b_rea = b[15:8]; assign b_ima = b[7:0];
assign outr = a_rea*b_rea + a_ima*b_ima;
assign outi = a_ima*b_rea - a_rea*b_ima;
endmodule
module CONVCOR(
clk,
rst_n,
in_valid,
in_a,
in_b,
in_mode,
out_valid,
out
);
//---------------------------------
// input and output declaration
//---------------------------------
input clk;
input rst_n;
input in_valid;
input [15:0] in_a;
input [15:0] in_b;
input in_mode;
output reg out_valid;
output reg [35:0] out;
//----------------------------------
// reg and wire declaration
//----------------------------------
reg signed [15:0] a0, a1, a2;
reg signed [15:0] b0, b1, b2;
reg sta;
reg [1:0] cnt;
reg [5:0] start;
reg rst;
wire signed [17:0] out11r, out21r, out22r, out31r, out32r, out33r, out41r, out42r, out51r;
wire signed [17:0] out11i, out21i, out22i, out31i, out32i, out33i, out41i, out42i, out51i;
wire signed [17:0] crrout1r, crrout2r, crrout3r, crrout1i, crrout2i, crrout3i;
//----------------------------------
//
// My design
//
//----------------------------------
convolution cnv11(out11r,out11i,a0,b0);
convolution cnv21(out21r,out21i,a0,b1);
convolution cnv22(out22r,out22i,a1,b0);
convolution cnv31(out31r,out31i,a0,b2);
convolution cnv32(out32r,out32i,a1,b1);
convolution cnv33(out33r,out33i,a2,b0);
convolution cnv41(out41r,out41i,a1,b2);
convolution cnv42(out42r,out42i,a2,b1);
convolution cnv51(out51r,out51i,a2,b2);
correlation crr1(crrout1r,crrout1i,a0,b0);
correlation crr2(crrout2r,crrout2i,a1,b1);
correlation crr3(crrout3r,crrout3i,a2,b2);
always@(negedge clk) begin
if(in_mode) sta = 1;
if(rst_n == 0 || rst) begin
out_valid = 0;
out = 0;
a0 = 0; a1 = 0; a2 = 0;
b0 = 0; b1 = 0; b2 = 0;
sta = 0;
cnt = 0;
start = 0;
rst = 0;
end
if(in_valid) begin
cnt = cnt+1;
case(cnt)
1: begin a0 = in_a; b0 = in_b; end
2: begin a1 = in_a; b1 = in_b; end
3: begin a2 = in_a; b2 = in_b; end
endcase
end
if(cnt >= 3) begin
start = start+1;
case(sta)
0: begin
case(start)
2: begin
out_valid = 1;
out[35:18] = out11r;
out[17:0] = out11i;
end
3: begin
out_valid = 1;
out[35:18] = out21r+out22r;
out[17:0] = out21i+out22i;
end
4: begin
out_valid = 1;
out[35:18] = out31r+out32r+out33r;
out[17:0] = out31i+out32i+out33i;
end
5: begin
out_valid = 1;
out[35:18] = out41r+out42r;
out[17:0] = out41i+out42i;
end
6: begin
out_valid = 1;
out[35:18] = out51r;
out[17:0] = out51i;
end
7: begin
out_valid = 0;
rst = 1;
end
endcase
end
1: begin
if(start == 2) begin
out[35:18] = crrout1r+crrout2r+crrout3r;
out[17:0] = crrout1i+crrout2i+crrout3i;
out_valid = 1;
end
if(start == 3) begin
out_valid = 0;
rst = 1;
end
end
endcase
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); function<long long(long long, long long)> power = [&](long long x, long long y) { if (y == 0) { return 1LL; } else { long long z = power(x, y / 2); return y % 2 == 0 ? (z * z) % 998244353 : ((z * z) % 998244353 * x) % 998244353; } }; auto div = [&](long long x) { return power(x, 998244353 - 2); }; long long n, m; cin >> n >> m; vector<bool> a((size_t)n); vector<long long> w((size_t)n); for (long long i = 0; i < n; i++) { long long v; cin >> v; a[i] = v == 1; } for (long long i = 0; i < n; i++) { cin >> w[i]; } long long zeros = 0, ones = 0; for (long long i = 0; i < n; i++) { if (a[i]) { ones += w[i]; } else { zeros += w[i]; } } map<tuple<bool, long long, long long, long long, long long>, long long> dp; function<long long(bool, long long, long long, long long, long long)> f = [&](bool q, long long b, long long z, long long o, long long j) { if (j >= m) { return b; } auto it = dp.find({q, b, z, o, j}); if (it != dp.end()) { return it->second; } long long r = 0; if (q) { r += b * f(q, b + 1, z, o, j + 1); r += z * f(q, b, z - 1, o, j + 1); r += o * f(q, b, z, o + 1, j + 1); } else { r += b * f(q, b - 1, z, o, j + 1); r += z * f(q, b, z - 1, o, j + 1); r += o * f(q, b, z, o + 1, j + 1); } r %= 998244353; r *= div(b + z + o); r %= 998244353; return dp[{q, b, z, o, j}] = r; }; for (long long i = 0; i < n; i++) { cout << f(a[i], w[i], a[i] ? zeros : zeros - w[i], a[i] ? ones - w[i] : ones, 0) << endl; } return 0; }
|
`default_nettype none
module TMDSify(
input clkin,
input val, hsync, vsync, inframe,
output [3:0] gpdi_dp
);
wire pixclk;
wire tmds_clk;
reg pix;
tmds_pll pll(.clkin, .clkout0(tmds_clk), .clkout1(pixclk));
always @(posedge pixclk)
pix <= val;
wire [9:0] TMDS_grn, TMDS_blu;
TMDS_mono_enc encode_grn(.clk(pixclk), .pix, .cd(2'b00) , .inframe, .tmds(TMDS_grn));
TMDS_mono_enc encode_blu(.clk(pixclk), .pix, .cd({vsync,hsync}), .inframe, .tmds(TMDS_blu));
reg [9:0] every_ten = 1;
wire should_load = every_ten[9];
always @(posedge tmds_clk)
every_ten <= {every_ten[8:0],every_ten[9]};
reg [9:0] TMDS_shift_grn = 0, TMDS_shift_blu = 0;
always @(posedge tmds_clk) begin
TMDS_shift_grn <= should_load ? TMDS_grn : TMDS_shift_grn[9:1];
TMDS_shift_blu <= should_load ? TMDS_blu : TMDS_shift_blu[9:1];
end
assign gpdi_dp[0] = TMDS_shift_blu[0];
assign gpdi_dp[1] = TMDS_shift_grn[0];
assign gpdi_dp[2] = TMDS_shift_grn[0];
assign gpdi_dp[3] = pixclk;
endmodule
module TMDS_mono_enc(
input wire clk,
input wire pix,
input [1:0] cd,
input inframe,
output reg [9:0] tmds
);
wire [9:0] word = 10'b1100000111;
wire [9:0] data = pix ? ~word : word;
wire [9:0] base = cd[1] ? 10'b0101010100 : 10'b1101010100;
wire [9:0] ctrl = cd[0] ? ~base : base;
always @(posedge clk)
tmds <= inframe ? data : ctrl;
endmodule
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#include <bits/stdc++.h> using namespace std; long long exp(long long a, long long n) { if (n == 0) return 1; long long residue = 1, result = a % 1000000007LL; while (n > 1LL) { if (n % 2LL == 1LL) residue = residue * result % 1000000007LL; result = result * result % 1000000007LL; n = n >> 1LL; } return residue * result % 1000000007LL; } void sieve(long long n, vector<bool> &isPrime) { for (int i = 0; i <= n; i++) isPrime[i] = true; isPrime[0] = isPrime[1] = false; for (long long i = 2; i * i <= n; i++) { if (!isPrime[i]) continue; for (long long j = i * i; j <= n; j += i) { isPrime[j] = false; } } } long long nc2(long long n) { return (n * (n - 1LL) / 2LL) % 1000000007LL; } bool checkPal(string s) { string t = s; reverse(s.begin(), s.end()); if (s == t) return true; else return false; } void rev(int i, int k, string &s) { int last = (i + k) / 2; for (int t = i; t <= last; t++) { swap(s[t], s[k - (t - i)]); } } int len(string &s) { return s.size(); } vector<int> KMP_preprocessing(string test1) { vector<int> preprocess; int i = 0, j = 1; preprocess.push_back(0); int len1 = len(test1); while (i < len1 and j < len1) { if (test1[i] == test1[j]) { preprocess.push_back(i + 1); i += 1; j += 1; } else { while (i != 0 and test1[i] != test1[j]) { i = preprocess[i - 1]; } if (test1[i] == test1[j]) { preprocess.push_back(i + 1); i += 1; j += 1; } else preprocess.push_back(0), j += 1; } } return preprocess; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); int n, k; vector<int> a(200001); cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; priority_queue<pair<int, pair<int, int>>, vector<pair<int, pair<int, int>>>, greater<pair<int, pair<int, int>>>> minq; int last = -1; int ans; for (int i = 0; i < n; i++) { if (a[i] <= -1) { if (last != -1) minq.push(make_pair(i - last - 1, make_pair(last + 1, i - 1))); last = i; } } if (last != -1 && minq.size() + 1 > k) { cout << -1 << endl; return 0; } k -= minq.size() + 1; while (minq.size() > 0 && (minq.top().first == 0 || minq.top().second.first == 0)) { minq.pop(); } ans = 2 * minq.size(); while (minq.size() > 0 && minq.top().first <= k) { ans -= 2; k -= minq.top().first; minq.pop(); } if (last != -1) { ans++; if (k < n - last - 1) { ans++; } } cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O2BB2AI_BEHAVIORAL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y, nand0_out, or0_out);
buf buf0 (Y , nand1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_BEHAVIORAL_V
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#include <bits/stdc++.h> const int N = 1e5 + 1; const int INF = 1e9 + 9; int n; int d[N]; std::vector<int> a[N]; int dfs(int v) { for (int u : a[v]) { d[v] += dfs(u); } if (d[v] == 0) return d[v] = 1; return d[v]; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int x; scanf( %d , &x); x--; a[x].push_back(i); } dfs(0); std::sort(d, d + n); for (int i = 0; i < n; i++) printf( %d , d[i]); }
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#include <bits/stdc++.h> using namespace std; int N, M, K, dp[505][505]; char g[505][505]; bool check(int r, int c) { int dx[] = {-1, 1, 0, 0}; int dy[] = {0, 0, -1, 1}; if (r < 0 || c < 0) return false; if (g[r][c] == 0 ) return false; for (int i = 0; i < 4; ++i) { int nextR = r + dx[i]; int nextC = c + dy[i]; if (nextR < 0 || nextC < 0) return false; if (g[nextR][nextC] == 0 ) return false; } return true; } int cntStars(int r1, int c1, int r2, int c2) { return dp[r2][c2] - dp[r1 + 1][c2] - dp[r2][c1 + 1] + dp[r1 + 1][c1 + 1]; } int main() { scanf( %d %d %d , &N, &M, &K); for (int i = 0; i < N; ++i) scanf( %s , &g[i]); for (int i = 0; i < N; ++i) { for (int j = 0; j < M; ++j) { dp[i + 1][j + 1] = dp[i][j + 1] + dp[i + 1][j] - dp[i][j] + check(i - 1, j - 1); } } long long res = 0; for (int r2 = 3; r2 <= N; ++r2) { for (int c2 = 3; c2 <= M; ++c2) { int c1 = c2 - 2; for (int r1 = 1; r1 < r2 - 1; ++r1) { while (c1 >= 1 && cntStars(r1, c1, r2, c2) < K) --c1; if (c1 >= 1 && cntStars(r1, c1, r2, c2) >= K) res += c1; } } } cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void enable_comma() {} string tostring(char c); string tostring(long long x); template <class A, class B> string tostring(pair<A, B> p); template <class A> string tostring(vector<A> v); string tostring(char c) { string s = ; s += c; return s; } string tostring(string s) { return + s + ; } string tostring(char *c) { return tostring((string)c); } string tostring(long long x) { if (x < 0) return - + tostring(-x); if (x > 9) return tostring(x / 10) + tostring(char( 0 + x % 10)); else return tostring(char( 0 + x)); } string tostring(int x) { return tostring((long long)x); } string tostring(unsigned long long x) { if (x > 9) return tostring((long long)(x / 10)) + tostring(char( 0 + x % 10)); else return tostring(char( 0 + x)); } string tostring(unsigned x) { return tostring((long long)x); } string tostring(double x) { static char res[114]; sprintf(res, %lf , x); return tostring(res); } string tostring(long double x) { return tostring((double)x); } template <class A, class B> string tostring(pair<A, B> p) { return ( + tostring(p.first) + , + tostring(p.second) + ) ; } template <class A> string tostring(vector<A> v) { string res = { ; for (int i = (0); i <= ((int)v.size() - 1); i++) { res += tostring(v[i]); res += i == (int)v.size() - 1 ? } : , ; } if (res == { ) res += } ; return res; } template <class A> string tostring(A a, int L, int R) { string res = { ; for (int i = (L); i <= (R); i++) { res += tostring(a[i]); res += i == R ? } : , ; } if (res == { ) res += } ; return res; } string tostrings() { return ; } template <typename Head, typename... Tail> string tostrings(Head H, Tail... T) { return tostring(H) + + tostrings(T...); } long long read() { long long x = 0, f = 0; char ch = getchar(); while (!isdigit(ch)) f = ch == - , ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); return f ? -x : x; } template <class T> void ckmax(T &x, const T y) { if (x < y) x = y; } template <class T> void ckmin(T &x, const T y) { if (x > y) x = y; } const int N = 500005 * 2; int n, m, q; int p[N]; pair<int, int> e[N], t[N]; int ti[N]; namespace S { int fa[N]; void init() { iota(fa, fa + N, 0); } int getf(int x) { return fa[x] == x ? x : fa[x] = getf(fa[x]); } } // namespace S int cnt; int fa[N], val[N]; vector<int> son[N]; int vis[N]; int I[N], O[N], ii[N]; int anc[N][20], dep[N]; int Time = 0; void dfs(int x, int d = 1) { vis[x] = 1; anc[x][0] = fa[x]; for (int i = (1); i <= (19); i++) anc[x][i] = anc[anc[x][i - 1]][i - 1]; dep[x] = d; I[x] = ++Time; ii[Time] = x; for (auto y : son[x]) dfs(y, d + 1); O[x] = Time; } int pmax(int x, int y) { return p[x] > p[y] ? x : y; } namespace seg { const int S = N * 4; int mx[S]; void pushup(int rt) { int ls = rt << 1, rs = ls | 1; mx[rt] = pmax(mx[ls], mx[rs]); } void build(int rt, int L, int R) { if (L == R) { mx[rt] = ii[L]; return; } int mid = (L + R) >> 1, ls = rt << 1, rs = ls | 1; build(ls, L, mid); build(rs, mid + 1, R); pushup(rt); } int query(int rt, int L, int R, int xL, int xR) { if (R < xL || L > xR) return 0; if (xL <= L && R <= xR) return mx[rt]; int mid = (L + R) >> 1, ls = rt << 1, rs = ls | 1; return pmax(query(ls, L, mid, xL, xR), query(rs, mid + 1, R, xL, xR)); } void update(int rt, int L, int R, int x) { if (L == R) { mx[rt] = 0; return; } int mid = (L + R) >> 1, ls = rt << 1, rs = ls | 1; if (x <= mid) update(ls, L, mid, x); else update(rs, mid + 1, R, x); pushup(rt); } } // namespace seg void solve() { n = read(), m = read(), q = read(); for (int i = (1); i <= (n); i++) p[i] = read(); for (int i = (1); i <= (m); i++) { int x = read(), y = read(); e[i] = make_pair(x, y); ti[i] = q + 1; } for (int i = (1); i <= (q); i++) { int tp = read(), x = read(); t[i] = make_pair(tp, x); if (tp == 2) ti[x] = i; } vector<int> id(m); iota(id.begin(), id.end(), 1); sort(id.begin(), id.end(), [&](int x, int y) { return ti[x] > ti[y]; }); cnt = n; S::init(); for (auto i : id) { int x = e[i].first, y = e[i].second; int fx = S::getf(x), fy = S::getf(y); if (fx != fy) { int f = ++cnt; fa[fx] = fa[fy] = S::fa[fx] = S::fa[fy] = f; val[f] = ti[i]; son[f] = {fx, fy}; enable_comma(); } } for (int i = (cnt); i >= (1); i--) if (!vis[i]) dfs(i); seg::build(1, 1, cnt); for (int i = (1); i <= (q); i++) { int tp = t[i].first, x = t[i].second; if (tp == 1) { for (int j = (19); j >= (0); j--) if (val[anc[x][j]] > i) x = anc[x][j]; int res = seg::query(1, 1, cnt, I[x], O[x]); printf( %d n , p[res]); p[res] = 0; seg::update(1, 1, cnt, I[res]); } else { } } } int main() { int T = 1; while (T--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; int a; int count = 0; cin >> n; for (int i = 1; i <= n; i++) { cin >> a; if (a == 1) count += 1; } if (n != 1) { if (count == (n - 1)) cout << YES << endl; else cout << NO << endl; } else { if (count == 1) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[200200], b[200200]; set<pair<long long, long long> > s; set<pair<long long, long long> >::iterator it, it2; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n, i; cin >> n; for (i = 0; i < n; i++) cin >> a[i], s.insert({a[i], i}); for (it = s.begin(); it != s.end();) { it2 = it; it2++; if (it2 == s.end()) break; if ((*it).first == (*it2).first) { s.insert({(*it).first * 2, (*it2).second}); s.erase(it2); it2 = it; it++; s.erase(it2); } else it++; } for (auto x : s) { b[x.second] = x.first; } cout << s.size() << endl; for (i = 0; i < n; i++) { if (b[i]) cout << b[i] << ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int arr[30] = {}, n, i = 0; cin >> n; while (n > 0) arr[i] = n % 2, n /= 2, i++; for (i = 29; i >= 0; i--) if (arr[i]) cout << i + 1 << ; cout << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A31O_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a31o (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; class DSU { public: vector<long long> p; DSU() {} DSU(long long n) { p.resize(n + 1); for (long long i = 1; i <= n; i++) p[i] = i; } void join(long long a, long long b) { p[find(b)] = find(a); } long long find(long long a) { return a == p[a] ? a : p[a] = find(p[a]); } bool check(long long a, long long b) { return find(a) == find(b); } }; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, m; cin >> n >> m; DSU d(n); vector<DSU> D; for (long long i = 0; i <= m; i++) D.push_back(d); for (long long i = 0; i < m; i++) { long long u, v, c; cin >> u >> v >> c; D[c].join(u, v); } long long q; cin >> q; while (q--) { long long u, v; cin >> u >> v; long long ans = 0; for (long long i = 1; i <= m; i++) if (D[i].check(u, v)) ans++; cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, x, y; cin >> n >> x >> y; if (y < n) { cout << -1 << endl; return 0; } long long a = y - n + 1; unsigned long long ans = 0; ans += n - 1 + a * a; if (ans < x) { cout << -1 << endl; return 0; } a = (y - n) + 1; cout << a << endl; for (int i = 0; i < n - 1; i++) cout << 1 << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int cycl[N], set_val[N], cycl_size[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int h, m, n; cin >> h >> m >> n; vector<int> strt; bool vis[h]; memset(vis, false, sizeof vis); int kk = 0; set<int> dmm[h + 1]; for (long long i = 0; i < m; i++) { if (vis[i]) { continue; } int ii = i; int jp = 0; while (1) { if (vis[ii]) { break; } set_val[ii] = jp; cycl[ii] = kk; dmm[kk].insert(jp); vis[ii] = true; ii += m; ii %= h; jp++; } cycl_size[kk] = jp; kk++; } map<int, int> hash; map<int, int> final; long long cnt = 0; while (n--) { char ch; cin >> ch; if (ch == + ) { int id, t; cin >> id >> t; hash[id] = t; if (dmm[cycl[t]].find(set_val[t]) != dmm[cycl[t]].end()) { final[id] = set_val[t]; dmm[cycl[t]].erase(set_val[t]); continue; } set<int>::iterator it, it1; it = dmm[cycl[t]].lower_bound(set_val[t]); int xx1; if (it == dmm[cycl[t]].end()) { it = dmm[cycl[t]].begin(); xx1 = cycl_size[cycl[t]] + *it - set_val[t]; int jj = *it; final[id] = jj; dmm[cycl[t]].erase(jj); } else { xx1 = *it - set_val[t]; int jj = *it; final[id] = jj; dmm[cycl[t]].erase(jj); } cnt += (long long)xx1; } else { int id; cin >> id; dmm[cycl[hash[id]]].insert(final[id]); } } cout << cnt << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_TB_V
`define SKY130_FD_SC_LS__A2111O_TB_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a2111o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a2111o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_bscl1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ------------------------------------------------------------------
module bw_io_dtl_bscl1(intest_oe ,intest_d ,q_dn_pad ,q25_dn_pad ,
q_up_pad );
output intest_oe ;
output intest_d ;
input q_dn_pad ;
input q25_dn_pad ;
input q_up_pad ;
wire net016 ;
wire n1 ;
bw_u1_inv_2x up_inv2x (
.z (intest_d ),
.a (net016 ) );
bw_u1_nand2_1x nand1 (
.z (n1 ),
.a (q_up_pad ),
.b (q25_dn_pad ) );
bw_u1_nand2_1x nand2 (
.z (intest_oe ),
.a (q_dn_pad ),
.b (n1 ) );
bw_u1_inv_1x up_inv1x (
.z (net016 ),
.a (q_up_pad ) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_DFF_PS_SYMBOL_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$PS (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_PS_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, p; string A; cin >> n >> p >> A; int i = n - 1; while (i >= 0 && i < n) { A[i]++; if (A[i] - 96 > p) { A[i] = 96; i--; continue; } if (i > 0 && A[i] == A[i - 1]) continue; if (i > 1 && A[i] == A[i - 2]) continue; i++; } if (i < 0) cout << NO n ; else cout << A << n ; return 0; }
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build Fri Jun 26 16:35:25 MDT 2015
// Date : Tue Nov 10 13:18:32 2015
// Host : centennial.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
// Command : write_verilog -force -mode synth_stub
// /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/new_atari/project_1/project_1.srcs/sources_1/ip/BIOS_ROM/BIOS_ROM_stub.v
// Design : BIOS_ROM
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2015.2" *)
module BIOS_ROM(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[11:0],dina[7:0],douta[7:0]" */;
input clka;
input ena;
input [0:0]wea;
input [11:0]addra;
input [7:0]dina;
output [7:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct hero { int power; int nr; }; int main() { int n, m; int board[100]; hero heroes[100]; vector<int> left, right; cin >> n >> m; for (int i = 0; i < n; ++i) heroes[i].nr = -1; int l_ind = n; int r_ind = -1; for (int si, hi, i = 0; i < m; ++i) { cin >> si >> hi; heroes[si - 1].nr = i + 1; heroes[si - 1].power = hi; if (si - 1 < l_ind) l_ind = si - 1; if (si - 1 > r_ind) r_ind = si - 1; } for (int i = 0; i < n; ++i) cin >> board[i]; int cur_pow = heroes[l_ind].power; int cur_hero = heroes[l_ind].nr; if (m == 1) { cout << l_ind + 1 << n1 << endl; return 0; } while (l_ind < n - 1 && l_ind + 1 < r_ind) { if (board[l_ind + 1] >= 0) { cur_pow += board[l_ind + 1]; if (heroes[l_ind + 1].nr != -1) { if (heroes[l_ind + 1].power > cur_pow) { left.push_back(cur_hero); cur_hero = heroes[l_ind + 1].nr; cur_pow = heroes[l_ind + 1].power; } else { left.push_back(heroes[l_ind + 1].nr); } } } else { if (cur_pow + board[l_ind + 1] >= 0) cur_pow += board[l_ind + 1]; else { break; } } ++l_ind; } left.push_back(cur_hero); cur_hero = heroes[r_ind].nr; cur_pow = heroes[r_ind].power; while (r_ind > 0 && l_ind < r_ind - 1) { if (board[r_ind - 1] >= 0) { cur_pow += board[r_ind - 1]; if (heroes[r_ind - 1].nr != -1) { if (heroes[r_ind - 1].power > cur_pow) { right.push_back(cur_hero); cur_hero = heroes[r_ind - 1].nr; cur_pow = heroes[r_ind - 1].power; } else { right.push_back(heroes[r_ind - 1].nr); } } } else { if (cur_pow + board[r_ind - 1] >= 0) cur_pow += board[r_ind - 1]; else { break; } } --r_ind; } right.push_back(cur_hero); if (abs(l_ind - r_ind) > 1) cout << -1 << endl; else { cout << l_ind + 1 << endl; for (auto it = left.end() - 1; it >= left.begin(); --it) cout << (*it) << ; for (auto it = right.end() - 1; it >= right.begin(); --it) cout << (*it) << ; cout << endl; } return 0; }
|
/*
* PS2 Mouse without FIFO buffer
* Copyright (C) 2010 Donna Polehn <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse_nofifo (
input clk,
input reset,
input [7:0] writedata, // data to send
input write, // signal to send it
output [7:0] readdata, // data read
output irq, // signal data has arrived
output command_was_sent,
output error_sending_command,
output buffer_overrun_error,
inout ps2_clk,
inout ps2_dat
);
// Unused outputs
wire start_receiving_data;
wire wait_for_incoming_data;
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse mouse (
.clk (clk),
.reset (reset),
.the_command (writedata),
.send_command (write),
.received_data (readdata),
.received_data_en (irq),
.command_was_sent (command_was_sent),
.error_communication_timed_out (error_sending_command),
.start_receiving_data (start_receiving_data),
.wait_for_incoming_data (wait_for_incoming_data),
.ps2_clk (ps2_clk),
.ps2_dat (ps2_dat)
);
// Continous assignments
assign buffer_overrun_error = error_sending_command;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_1_V
`define SKY130_FD_SC_HDLL__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_1_V
|
#include <bits/stdc++.h> using namespace std; int V = 0; struct Node { int id; long long num, sum; Node *l, *r; Node() { num = -1; sum = 0; l = r = nullptr; id = V++; } }; int N; string s; Node* build(int& n) { Node* node = new Node(); if (s[n] == ( ) { n++; node->l = build(n); n++; node->r = build(n); n++; node->sum += node->l->sum + node->r->sum + 1; } else { node->num = s[n] - 0 ; n++; } return node; } const long long INF = 1 << 25; int P, M; bool remplus; long long mi[10000][210]; long long ma[10000][210]; pair<long long, long long> f(Node* node, int rem) { if (node->num != -1) { if (rem) return {INF, INF}; return {node->num, node->num}; } int id = node->id; if (mi[id][rem] != INF) return {mi[id][rem], ma[id][rem]}; if (rem > node->sum) return {INF, INF}; pair<long long, long long> ret = {INF, -INF}; for (int i = 0; i < 2; i++) { int nrem = rem - (remplus && !i || !remplus && i); if (nrem < 0) continue; for (int j = 0; j <= nrem; j++) { auto res1 = f(node->l, j); auto res2 = f(node->r, nrem - j); if (res1.first == INF || res2.first == INF) continue; if (i == 0) { ret.first = min(ret.first, res1.first + res2.first); ret.second = max(ret.second, res1.second + res2.second); } else { ret.first = min(ret.first, res1.first - res2.second); ret.second = max(ret.second, res1.second - res2.first); } } } mi[id][rem] = ret.first; ma[id][rem] = ret.second; return ret; } int main() { cin.tie(0); ios::sync_with_stdio(false); cin >> s >> P >> M; N = s.size(); int n = 0; Node* root = build(n); fill((long long*)begin(mi), (long long*)end(mi), INF); fill((long long*)begin(ma), (long long*)end(ma), INF); remplus = P <= M; int rem = remplus ? P : M; cout << f(root, rem).second << endl; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using vi = vector<int>; using vii = vector<vector<int>>; const ll LINF = 1LL << 60; const int INF = 1 << 29; const int MOD = 1e9 + 7; int main() { int n; cin >> n; vector<pii> v(n); for (int i = 0; i < n; i++) { int x, w; cin >> x >> w; v[i] = {x + w, x - w}; } sort((v).begin(), (v).end()); int ans = 0, cur = -1e9 - 5; for (int i = 0; i < n; i++) { if (cur <= v[i].second) { cur = v[i].first; ans++; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 4, inf = 1e9 + 7; vector<int> vec[N]; vector<pair<int, int> > qry[N]; int col[N], cnt[N], frq[N]; int vis[N], siz[N], Res[N]; void dfs(int u, int p) { siz[u] = 1; for (auto v : vec[u]) { if (v == p) continue; dfs(v, u); siz[u] += siz[v]; } } void Add(int u, int p) { cnt[++frq[col[u]]]++; for (auto v : vec[u]) { if (v == p || vis[v]) continue; Add(v, u); } } void Rem(int u, int p) { cnt[frq[col[u]]--]--; for (auto v : vec[u]) { if (v == p || vis[v]) continue; Rem(v, u); } } void DFS(int u, int p, bool first) { int mx = -1, id = -1; for (auto v : vec[u]) { if (v == p) continue; if (siz[v] > mx) mx = siz[v], id = v; } for (auto v : vec[u]) { if (v == p || v == id) continue; DFS(v, u, 1); } if (id != -1) DFS(id, u, 0), vis[id] = 1; Add(u, p); for (auto x : qry[u]) Res[x.second] = cnt[x.first]; if (id != -1) vis[id] = 0; if (first) Rem(u, p); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, q; cin >> n >> q; for (int i = 1; i <= n; i++) cin >> col[i]; int m = n - 1; while (m--) { int u, v; cin >> u >> v; vec[u].push_back(v); vec[v].push_back(u); } dfs(1, 1); for (int i = 1; i <= q; i++) { int v, k; cin >> v >> k; qry[v].push_back(make_pair(k, i)); } DFS(1, 1, 0); for (int i = 1; i <= q; i++) cout << Res[i] << n ; return 0; }
|
// file: Clock50MHz_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module Clock50MHz_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk_n;
wire clk;
reg [C_W-1:0] counter;
// Instantiation of the clocking network
//--------------------------------------
Clock50MHz clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int),
// Status and control signals
.LOCKED (LOCKED));
assign clk_n = ~clk;
ODDR2 clkout_oddr
(.Q (CLK_OUT[1]),
.C0 (clk),
.C1 (clk_n),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int IN = 2e5 + 7; int sum[IN]; int main() { string str; cin >> str; int n; scanf( %d , &n); memset(sum, 0, sizeof(sum)); if (str[0] == str[1]) sum[0] = 1; else sum[0] = 0; int k = str.size(); for (int i = 1; i < k - 1; i++) { if (str[i] == str[i + 1]) { sum[i] = sum[i - 1] + 1; } else { sum[i] = sum[i - 1]; } } sum[k - 1] = sum[k - 2]; int l, r; for (int i = 0; i < n; i++) { scanf( %d%d , &l, &r); if (l != 1) printf( %d n , sum[r - 2] - sum[l - 2]); else printf( %d n , sum[r - 2]); } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`timescale 1ns / 1ps
module t_inst(/*AUTOARG*/
// Outputs
passed,
// Inputs
clk, fastclk
);
input clk;
input fastclk;
output passed; reg passed; initial passed = 0;
genvar unused;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire o_com; // From b of t_inst_b.v
wire o_seq_d1r; // From b of t_inst_b.v
// End of automatics
integer _mode; // initial _mode=0
reg na,nb,nc,nd,ne;
wire ma,mb,mc,md,me;
wire da,db,dc,dd,de;
reg [7:0] wa,wb,wc,wd,we;
wire [7:0] qa,qb,qc,qd,qe;
wire [5:0] ra;
wire [4:0] rb;
wire [29:0] rc;
wire [63:0] rd;
reg [5:0] sa;
reg [4:0] sb;
reg [29:0] sc;
reg [63:0] sd;
reg _guard1; initial _guard1=0;
wire [104:0] r_wide = {ra,rb,rc,rd};
reg _guard2; initial _guard2=0;
wire [98:0] r_wide0 = {rb,rc,rd};
reg _guard3; initial _guard3=0;
wire [93:0] r_wide1 = {rc,rd};
reg _guard4; initial _guard4=0;
wire [63:0] r_wide2 = {rd};
reg _guard5; initial _guard5=0;
wire [168:0] r_wide3 = {ra,rb,rc,rd,rd};
reg [127:0] _guard6; initial _guard6=0;
t_inst_a a (
.clk (clk),
// Outputs
.o_w5 ({ma,mb,mc,md,me}),
.o_w5_d1r ({da,db,dc,dd,de}),
.o_w40 ({qa,qb,qc,qd,qe}),
.o_w104 ({ra,rb,rc,rd}),
// Inputs
.i_w5 ({na,nb,nc,nd,ne}),
.i_w40 ({wa,wb,wc,wd,we}),
.i_w104 ({sa,sb,sc,sd})
);
reg i_seq;
reg i_com;
wire [15:14] o2_comhigh;
t_inst_b b (
.o2_com (o2_comhigh),
.i2_com ({i_com,~i_com}),
.wide_for_trace (128'h1234_5678_aaaa_bbbb_cccc_dddd),
.wide_for_trace_2 (_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd),
/*AUTOINST*/
// Outputs
.o_seq_d1r (o_seq_d1r),
.o_com (o_com),
// Inputs
.clk (clk),
.i_seq (i_seq),
.i_com (i_com));
// surefire lint_off STMINI
initial _mode = 0;
always @ (posedge fastclk) begin
if (_mode==1) begin
if (o_com !== ~i_com) $stop;
if (o2_comhigh !== {~i_com,i_com}) $stop;
end
end
always @ (posedge clk) begin
//$write("[%0t] t_inst: MODE = %0x NA=%x MA=%x DA=%x\n", $time, _mode,
// {na,nb,nc,nd,ne}, {ma,mb,mc,md,me}, {da,db,dc,dd,de});
$write("[%0t] t_inst: MODE = %0x IS=%x OS=%x\n", $time, _mode, i_seq, o_seq_d1r);
if (_mode==0) begin
$write("[%0t] t_inst: Running\n", $time);
_mode<=1;
{na,nb,nc,nd,ne} <= 5'b10110;
{wa,wb,wc,wd,we} <= {8'ha, 8'hb, 8'hc, 8'hd, 8'he};
{sa,sb,sc,sd} <= {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210};
//
i_seq <= 1'b1;
i_com <= 1'b1;
end
else if (_mode==1) begin
_mode<=2;
if ({ma,mb,mc,md,me} !== 5'b10110) $stop;
if ({qa,qb,qc,qd,qe} !== {8'ha,8'hb,8'hc,8'hd,8'he}) $stop;
if ({sa,sb,sc,sd} !== {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}) $stop;
end
else if (_mode==2) begin
_mode<=3;
if ({da,db,dc,dd,de} !== 5'b10110) $stop;
if (o_seq_d1r !== ~i_seq) $stop;
//
$write("[%0t] t_inst: Passed\n", $time);
passed <= 1'b1;
end
if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
$stop;
end
end
// surefire lint_off UDDSDN
wire _unused_ok = |{1'b1, r_wide0, r_wide1,r_wide2,r_wide3,r_wide};
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int maxn = 1e6 + 500; const long long int mod = 998244353; int dep[maxn], low[maxn], ans[maxn], dp[maxn]; int head[maxn], cnt; int n, k; struct C { int next, to; } E[maxn]; void add(int x, int y) { E[cnt].to = y; E[cnt].next = head[x]; head[x] = cnt++; } void dfs1(int u, int fa) { low[u] = 0x7f7f7f7f; dep[u] = dep[fa] + 1; if (head[u] == -1) { low[u] = dep[u]; dp[u] = 1; } else { for (int i = head[u]; i + 1; i = E[i].next) { int v = E[i].to; dfs1(v, u); low[u] = min(low[u], low[v]); if (low[v] - k <= dep[u]) dp[u] += dp[v]; } } } int dfs(int u, int fa) { if (head[u] == -1) return 1; int ans = 0; for (int i = head[u]; i + 1; i = E[i].next) { int v = E[i].to; int temp = dp[u]; if (low[v] - k <= dep[u]) temp -= dp[v]; ans = max(ans, temp + dfs(v, u)); } return ans; } int main() { int x; scanf( %d%d , &n, &k); memset(head, -1, sizeof head); for (int i = 2; i <= n; i++) { scanf( %d , &x); add(x, i); } dfs1(1, 0); printf( %d n , dfs(1, 0)); }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module des_crypt_salt_test;
// Inputs
reg [63:0] Din;
reg [63:0] K;
reg [11:0] salt;
reg CLK;
// Outputs
wire [67:0] Kout;
wire [31:0] L_out;
wire [31:0] R_out;
// Instantiate the Unit Under Test (UUT)
descrypt_salt uut (
.Din(Din),
.K(K),
.salt(salt),
.Kout(Kout),
.CLK(CLK),
.L_out(L_out),
.R_out(R_out)
);
initial begin
// Initialize Inputs
Din = 0;
K = 0;
salt = 0;
CLK = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Hash: abcdefgh Salt: AA
Din = 64'h00;
K = 64'b1100001011000100110001101100100011001010110011001100111011010000;
salt = 12'b001100001100;
#19000;
if(!(L_out === 32'h18df29dc)) $finish;
if(!(R_out === 32'hdbab5b10)) $finish;
end
initial
begin
#100;
while (1)
begin
CLK = ~CLK;
#10;
end;
end
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_eth_fcs_insert
*/
module test_axis_eth_fcs_insert;
// Parameters
parameter ENABLE_PADDING = 0;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tvalid,
s_axis_tlast,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser,
busy
);
// dump file
$dumpfile("test_axis_eth_fcs_insert.lxt");
$dumpvars(0, test_axis_eth_fcs_insert);
end
axis_eth_fcs_insert #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.busy(busy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, q, w[15]; char s[15]; int cnt[5005]; int sum[5000][105]; int tot2[15]; int main() { scanf( %d%d%d , &n, &m, &q); tot2[0] = 1; for (int i = 1; i <= 14; i++) tot2[i] = tot2[i - 1] * 2; for (int i = 1; i <= n; i++) scanf( %d , &w[i]); for (int i = 1; i <= m; i++) { scanf( %s , s); int len = strlen(s); int x = 0; for (int i = 0; i < len; i++) x = x * 2 + s[i] - 0 ; cnt[x]++; } for (int i = 0; i < tot2[n]; i++) { for (int j = 0; j < tot2[n]; j++) { int x = i ^ j; int tot = 0; for (int k = 0; k < n; k++) tot += (!((x >> k) & 1)) * w[n - k]; if (tot <= 100) sum[i][tot] += cnt[j]; } } for (int i = 0; i < tot2[n]; i++) { for (int j = 1; j <= 100; j++) { sum[i][j] += sum[i][j - 1]; } } while (q--) { int x = 0; char Q[15]; int val; scanf( %s%d , Q, &val); for (int i = 0; i < n; i++) x = x * 2 + Q[i] - 0 ; printf( %d n , sum[x][val]); } }
|
#include <bits/stdc++.h> using namespace std; using vi = vector<int>; using ii = pair<int, int>; using ld = long double; const int N = 5e5; bool flip[N], still[N]; int par[N], asdjashsgggg[N], x[N]; int find(int v, bool& b) { b = flip[v]; while (par[v] != v) { v = par[v]; b ^= flip[v]; } return v; } tuple<int, int, bool, bool> merge(int u, int v) { bool bu, bv; u = find(u, bu); v = find(v, bv); if (u == v) { if (bu == bv) throw true; else throw false; } else { int from = u, to = v; bool flipped = bu == bv, delta = 0; if (asdjashsgggg[u] == asdjashsgggg[v]) delta = 1; else if (asdjashsgggg[to] < asdjashsgggg[from]) swap(from, to); par[from] = to; flip[from] ^= flipped; asdjashsgggg[to] += delta; return {from, to, flipped, delta}; } } int main() { cin.tie(nullptr); ios_base::sync_with_stdio(false); int n, m, k; cin >> n >> m >> k; for (int i = 0; i < n; i++) { cin >> x[i]; x[i]--; } iota(par, par + n, 0); fill(still, still + k, true); vector<ii> e; while (m--) { int u, v; cin >> u >> v; u--, v--; if (x[u] == x[v] && still[x[u]]) { try { merge(u, v); } catch (bool oc) { if (oc) still[x[u]] = false; } } e.emplace_back(u, v); } int cnt = accumulate(still, still + k, 0); sort(e.begin(), e.end(), [&](ii a, ii b) { a = minmax(x[a.first], x[a.second]); b = minmax(x[b.first], x[b.second]); return a < b; }); ii pre = {-1, -1}; stack<tuple<int, int, bool, bool>> s; bool bad = false; long long ans = (long long)cnt * (cnt - 1) >> 1; for (auto [u, v] : e) { ii cur = minmax(x[u], x[v]); if (cur.first == cur.second || !still[cur.first] || !still[cur.second]) continue; if (pre < cur) { while (!s.empty()) { auto [from, to, flipped, delta] = s.top(); s.pop(); par[from] = from; flip[from] ^= flipped; asdjashsgggg[to] -= delta; } pre = cur; ans -= bad; bad = false; } if (bad) continue; try { s.push(merge(u, v)); } catch (bool oc) { if (oc) bad = true; } } ans -= bad; cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, n1, n2, c, b; cin >> n >> n1 >> n2; c = n1; b = n2; long double sum = 0, sum1 = 0; long long int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); if (n1 >= n2) { long long int i = 0; while (b > 0) { sum += a[n - i - 1]; i++; b--; } sum = sum / n2; while (c > 0) { sum1 += a[n - i - 1]; i++; c--; } sum1 = sum1 / n1; cout << fixed << setprecision(8) << sum + sum1 << endl; } else { long long int i = 0; while (c > 0) { sum += a[n - i - 1]; i++; c--; } sum = sum / n1; while (b > 0) { sum1 += a[n - i - 1]; i++; b--; } sum1 = sum1 / n2; cout << fixed << setprecision(8) << sum + sum1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> bool umin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } template <class T> bool umax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } int F[100009], arr[100009], ans[100009], imp[100009], pos[100009]; void upd(int x, int val) { for (; x; x -= x & (-x)) F[x] += val; } int tap(int x) { int res = 0; for (; x < 100009; x += x & (-x)) res += F[x]; return res; } set<int> s; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , arr + i), pos[arr[i]] = i; int all = 0; for (int i = 1; i <= n; i++) { int res = tap(arr[i]); if (!res) imp[i] = 1; else if (res == 1) { int val = *s.rbegin(); ans[pos[val]]++; } s.insert(arr[i]); upd(arr[i], +1); all += imp[i]; } int mx = -1, who; for (int i = 1; i <= n; i++) { int val = all - imp[i] + ans[i]; if (mx < val) mx = val, who = arr[i]; else if (mx == val) umin(who, arr[i]); } printf( %d n , who); return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using D = double; using uint = unsigned int; template <typename T> using pair2 = pair<T, T>; using pii = pair<int, int>; using pli = pair<ll, int>; using pll = pair<ll, ll>; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int MOD = 1000000007; inline int sum(int a, int b, int mod = MOD) { a += b; if (a >= mod) a -= mod; return a; } inline int sub(int a, int b, int mod = MOD) { a -= b; if (a < 0) a += mod; return a; } inline int mul(int a, int b, int mod = MOD) { return ((long long)a * b) % mod; } inline int powmod(int a, int b, int mod = MOD) { int tmp = a; int ans = 1; while (b) { if (b & 1) ans = mul(ans, tmp, mod); tmp = mul(tmp, tmp, mod); b >>= 1; } return ans; } inline int inv(int a, int mod = MOD) { return powmod(a, mod - 2, mod); } const int maxn = 5000006; int sm[maxn]; int ans[maxn]; int t, l, r; int main() { scanf( %d%d%d , &t, &l, &r); for (int i = 1; i < maxn; i++) sm[i] = -1; for (int i = 2; i < maxn; i++) { for (int j = i; j < maxn; j += i) if (sm[j] == -1) { sm[j] = i; } } ans[1] = 0; for (int i = 2; i < maxn; i++) { int d = sm[i]; int g = i / d; ans[i] = sum(ans[i / d], mul(g, ((ll)d * (d - 1) / 2) % MOD)); } int ml = 1; int answer = 0; for (int i = l; i <= r; i++) { answer = sum(answer, mul(ml, ans[i])); ml = mul(ml, t); } printf( %d n , answer); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2OI_1_V
`define SKY130_FD_SC_HS__A2BB2OI_1_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2OI_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/07/2015 06:38:17 PM
// Design Name:
// Module Name: m_port_ultra
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module m_port_ultra_processor_array (
input clk,
input reset_n,
input processorEnable,
input divideEnable,
input divideFinished,
input [32767:0] convexCloud,
output [4095:0] convexHull1,
output [4095:0] convexHull2,
output [4095:0] convexHull3,
output [4095:0] convexHull4,
output [4095:0] convexHull5,
output [4095:0] convexHull6,
output [4095:0] convexHull7,
output [4095:0] convexHull8,
output [8:0] convexHullSize1,
output [8:0] convexHullSize2,
output [8:0] convexHullSize3,
output [8:0] convexHullSize4,
output [8:0] convexHullSize5,
output [8:0] convexHullSize6,
output [8:0] convexHullSize7,
output [8:0] convexHullSize8,
output processorDone1,
output processorDone2,
output processorDone3,
output processorDone4,
output processorDone5,
output processorDone6,
output processorDone7,
output processorDone8
);
// Wires -- processor inputs
wire [4095:0] processorConvexCloud1;
wire [4095:0] processorConvexCloud2;
wire [4095:0] processorConvexCloud3;
wire [4095:0] processorConvexCloud4;
wire [4095:0] processorConvexCloud5;
wire [4095:0] processorConvexCloud6;
wire [4095:0] processorConvexCloud7;
wire [4095:0] processorConvexCloud8;
wire [8:0] processorConvexCloudSize1;
wire [8:0] processorConvexCloudSize2;
wire [8:0] processorConvexCloudSize3;
wire [8:0] processorConvexCloudSize4;
wire [8:0] processorConvexCloudSize5;
wire [8:0] processorConvexCloudSize6;
wire [8:0] processorConvexCloudSize7;
wire [8:0] processorConvexCloudSize8;
// Assign wires
assign processorConvexCloud1 = convexCloud[4095:0];
assign processorConvexCloud2 = convexCloud[8191:4096];
assign processorConvexCloud3 = convexCloud[12287:8192];
assign processorConvexCloud4 = convexCloud[16383:12288];
assign processorConvexCloud5 = convexCloud[20479:16384];
assign processorConvexCloud6 = convexCloud[24575:20480];
assign processorConvexCloud7 = convexCloud[28671:24576];
assign processorConvexCloud8 = convexCloud[32767:28672];
assign processorConvexCloudSize1 = 9'b100000000;
assign processorConvexCloudSize2 = 9'b100000000;
assign processorConvexCloudSize3 = 9'b100000000;
assign processorConvexCloudSize4 = 9'b100000000;
assign processorConvexCloudSize5 = 9'b100000000;
assign processorConvexCloudSize6 = 9'b100000000;
assign processorConvexCloudSize7 = 9'b100000000;
assign processorConvexCloudSize8 = 9'b100000000;
// Declare processor unit 1
m_port_ultra_quickhull quickhullProcessor1 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud1),
.convexCloudSize (processorConvexCloudSize1),
.convexPointsOutput (convexHull1),
.convexSetSizeOutput (convexHullSize1),
.processorDone (processorDone1)
);
// Declare processor unit 2
m_port_ultra_quickhull quickhullProcessor2 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud2),
.convexCloudSize (processorConvexCloudSize2),
.convexPointsOutput (convexHull2),
.convexSetSizeOutput (convexHullSize2),
.processorDone (processorDone2)
);
// Declare processor unit 3
m_port_ultra_quickhull quickhullProcessor3 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud3),
.convexCloudSize (processorConvexCloudSize3),
.convexPointsOutput (convexHull3),
.convexSetSizeOutput (convexHullSize3),
.processorDone (processorDone3)
);
// Declare processor unit 4
m_port_ultra_quickhull quickhullProcessor4 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud4),
.convexCloudSize (processorConvexCloudSize4),
.convexPointsOutput (convexHull4),
.convexSetSizeOutput (convexHullSize4),
.processorDone (processorDone4)
);
// Declare processor unit 5
m_port_ultra_quickhull quickhullProcessor5 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud5),
.convexCloudSize (processorConvexCloudSize5),
.convexPointsOutput (convexHull5),
.convexSetSizeOutput (convexHullSize5),
.processorDone (processorDone5)
);
// Declare processor unit 6
m_port_ultra_quickhull quickhullProcessor6 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud6),
.convexCloudSize (processorConvexCloudSize6),
.convexPointsOutput (convexHull6),
.convexSetSizeOutput (convexHullSize6),
.processorDone (processorDone6)
);
// Declare processor unit 7
m_port_ultra_quickhull quickhullProcessor7 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud7),
.convexCloudSize (processorConvexCloudSize7),
.convexPointsOutput (convexHull7),
.convexSetSizeOutput (convexHullSize7),
.processorDone (processorDone7)
);
// Declare processor unit 8
m_port_ultra_quickhull quickhullProcessor8 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud8),
.convexCloudSize (processorConvexCloudSize8),
.convexPointsOutput (convexHull8),
.convexSetSizeOutput (convexHullSize8),
.processorDone (processorDone8)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_SYMBOL_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long second = 0; int r, m; cin >> m >> r; long long koef = 0, koef2 = 0; for (int i = 1; i <= m; ++i) { long long lef = i - 2, rig = m - i - 1; if (lef < 0) lef = 0; if (rig < 0) rig = 0; koef2 += i != 1; koef2 += i != m; koef += lef + rig; second += 2; if (i != 1) second += 2; if (i != m) second += 2; second += (lef + 1) * lef; second += (rig + 1) * rig; } long double ans = second + (2 * koef + koef2) * sqrt(2.0); printf( %.10f n , double(ans / (1LL * m * m) * r)); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DFRTP_FUNCTIONAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRTP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; pair<int, pair<int, int> > matrix[71][71][71]; int cost[71][71][71]; vector<string> colors; int n; void initialize() { colors.clear(); for (int i = 0; i < 71; i++) { for (int j = 0; j < 71; j++) { for (int k = 0; k < 71; k++) { matrix[i][j][k] = make_pair(-1, make_pair(-1, -1)); cost[i][j][k] = 500000; } } } } int main() { scanf( %d , &n); int x, y, z; scanf( %d %d %d , &x, &y, &z); initialize(); string s; getline(cin, s); for (int i = 0; i < n; i++) { getline(cin, s); colors.push_back(s); } matrix[x][y][z] = make_pair(0, make_pair(0, 0)); queue<pair<int, pair<int, int> > > q; q.push(make_pair(x, make_pair(y, z))); cost[x][y][z] = 0; while (!q.empty()) { pair<int, pair<int, int> > elt = q.front(); q.pop(); x = elt.first; y = elt.second.first; z = elt.second.second; for (int i = 1; i <= n; i++) { if ((i == x) || (i == y) || (i == z)) continue; if (colors[x - 1][i - 1] == colors[y - 1][z - 1]) { if (cost[i][y][z] == 500000) { cost[i][y][z] = cost[x][y][z] + 1; matrix[i][y][z] = make_pair(x, (make_pair(y, z))); q.push(make_pair(i, make_pair(y, z))); } } if (colors[y - 1][i - 1] == colors[x - 1][z - 1]) { if (cost[x][i][z] == 500000) { cost[x][i][z] = cost[x][y][z] + 1; matrix[x][i][z] = make_pair(x, (make_pair(y, z))); q.push(make_pair(x, make_pair(i, z))); } } if (colors[z - 1][i - 1] == colors[y - 1][x - 1]) { if (cost[x][y][i] == 500000) { cost[x][y][i] = cost[x][y][z] + 1; matrix[x][y][i] = make_pair(x, (make_pair(y, z))); q.push(make_pair(x, make_pair(y, i))); } } } } int ans = cost[1][2][3]; x = 1; y = 2; z = 3; if (cost[1][3][2] < ans) { ans = cost[1][3][2]; x = 1; y = 3; z = 2; } if (cost[2][1][3] < ans) { ans = cost[2][1][3]; x = 2; y = 1; z = 3; } if (cost[2][3][1] < ans) { ans = cost[2][3][1]; x = 2; y = 3; z = 1; } if (cost[3][1][2] < ans) { ans = cost[3][1][2]; x = 3; y = 1; z = 2; } if (cost[3][2][1] < ans) { ans = cost[3][2][1]; x = 3; y = 2; z = 1; } if (ans == 500000) { cout << -1 << endl; } else { cout << ans << endl; pair<int, pair<int, int> > roller = make_pair(x, make_pair(y, z)); stack<pair<int, pair<int, int> > > s; s.push(roller); for (int i = 0; i < ans; i++) { roller = matrix[x][y][z]; x = roller.first; y = roller.second.first; z = roller.second.second; s.push(roller); } roller = s.top(); s.pop(); for (int i = 0; i < ans; i++) { pair<int, pair<int, int> > unroll = s.top(); s.pop(); if (roller.first != unroll.first) { cout << roller.first << << unroll.first << endl; } else if (roller.second.first != unroll.second.first) { cout << roller.second.first << << unroll.second.first << endl; } else { cout << roller.second.second << << unroll.second.second << endl; } roller = unroll; } } return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module clock_control_tb();
clock_control clock_control
(.reset(reset),
.aux_clk(aux_clk),
.clk_fpga(clk_fpga),
.clk_en(clk_en),
.clk_sel(clk_sel),
.clk_func(clk_func),
.clk_status(clk_status),
.sen(sen),
.sclk(sclk),
.sdi(sdi),
.sdo(sdo)
);
reg reset, aux_clk;
wire [1:0] clk_sel, clk_en;
initial reset = 1'b1;
initial #1000 reset = 1'b0;
initial aux_clk = 1'b0;
always #10 aux_clk = ~aux_clk;
initial $dumpfile("clock_control_tb.vcd");
initial $dumpvars(0,clock_control_tb);
initial #10000 $finish;
endmodule // clock_control_tb
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the TRDB D5M digital camera. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_d5m (
// Inputs
rom_address,
exposure,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter D5M_COLUMN_SIZE = 16'd2591;
parameter D5M_ROW_SIZE = 16'd1943;
parameter D5M_COLUMN_BIN = 16'h0000;
parameter D5M_ROW_BIN = 16'h0000;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 4: 0] rom_address;
input [15: 0] exposure;
// Bidirectionals
// Outputs
output [35: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [31: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[31:24], 1'b0,
data[23:16], 1'b0,
data[15: 8], 1'b0,
data[ 7: 0], 1'b0};
// Internal Assignments
always @(*)
begin
case (rom_address)
0 : data <= {8'hBA, 8'h00, 16'h0000};
1 : data <= {8'hBA, 8'h20, 16'hc000}; // Mirror Row and Columns
2 : data <= {8'hBA, 8'h09, exposure}; // Exposure
3 : data <= {8'hBA, 8'h05, 16'h0000}; // H_Blanking
4 : data <= {8'hBA, 8'h06, 16'h0019}; // V_Blanking
5 : data <= {8'hBA, 8'h0A, 16'h8000}; // change latch
6 : data <= {8'hBA, 8'h2B, 16'h000b}; // Green 1 Gain
7 : data <= {8'hBA, 8'h2C, 16'h000f}; // Blue Gain
8 : data <= {8'hBA, 8'h2D, 16'h000f}; // Red Gain
9 : data <= {8'hBA, 8'h2E, 16'h000b}; // Green 2 Gain
10 : data <= {8'hBA, 8'h10, 16'h0051}; // set up PLL power on
11 : data <= {8'hBA, 8'h11, 16'h1807}; // PLL_m_Factor<<8+PLL_n_Divider
12 : data <= {8'hBA, 8'h12, 16'h0002}; // PLL_p1_Divider
13 : data <= {8'hBA, 8'h10, 16'h0053}; // set USE PLL
14 : data <= {8'hBA, 8'h98, 16'h0000}; // disble calibration
`ifdef ENABLE_TEST_PATTERN
15 : data <= {8'hBA, 8'hA0, 16'h0001}; // Test pattern control
16 : data <= {8'hBA, 8'hA1, 16'h0123}; // Test green pattern value
17 : data <= {8'hBA, 8'hA2, 16'h0456}; // Test red pattern value
`else
15 : data <= {8'hBA, 8'hA0, 16'h0000}; // Test pattern control
16 : data <= {8'hBA, 8'hA1, 16'h0000}; // Test green pattern value
17 : data <= {8'hBA, 8'hA2, 16'h0FFF}; // Test red pattern value
`endif
18 : data <= {8'hBA, 8'h01, 16'h0036}; // set start row
19 : data <= {8'hBA, 8'h02, 16'h0010}; // set start column
20 : data <= {8'hBA, 8'h03, D5M_ROW_SIZE}; // set row size
21 : data <= {8'hBA, 8'h04, D5M_COLUMN_SIZE}; // set column size
22 : data <= {8'hBA, 8'h22, D5M_ROW_BIN}; // set row mode in bin mode
23 : data <= {8'hBA, 8'h23, D5M_COLUMN_BIN}; // set column mode in bin mode
24 : data <= {8'hBA, 8'h49, 16'h01A8}; // row black target
default : data <= {8'h00, 8'h00, 16'h0000};
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
`timescale 1ns / 1ps
/*
Group Members: Kevin Ingram and Warren Seto
Lab Name: Traffic Light Controller (Lab 3)
Project Name: eng312_proj3
Design Name: Traffic_Test_H_eng312_proj3.v
Design Description: Verilog Test Bench to Implement Test H (Rush Hour)
*/
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire[4:0] count1;
wire[3:0] count2;
wire[1:0] count3;
// Counter Modules
nsCounter clock1(clk, count1); // Count a total of 32 seconds
ewCounter clock2(clk, count2); // Counts a total of 16 seconds
yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 1;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, K, ma; int A[1000005]; int dp[10000005]; bool ok(int val) { int nr = 0; for (int i = 1; i <= ma; i++) { dp[i] = 0; if (val <= i) dp[i] = 1; if (i % 2) dp[i] = max(dp[i], dp[i >> 1] + dp[(i + 1) >> 1]); else dp[i] = max(dp[i], 2 * dp[i >> 1]); } for (int i = 1; i <= N; i++) { nr += dp[A[i]]; if (nr >= K) return 1; } return 0; } int main() { bool notthesamecode = 1; cin.sync_with_stdio(false); cout.sync_with_stdio(false); cin >> N >> K; for (int i = 1; i <= N; i++) { cin >> A[i]; ma = max(ma, A[i]); } int st = 0, dr = (1e7 + 10), mid; while (st < dr) { mid = (st + dr + 1) / 2; if (ok(mid)) st = mid; else dr = mid - 1; } if (!st) cout << -1; else cout << st; return 0; }
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_ic_to_avm #(
parameter integer DATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer ID_W = 1
)
(
// AVM interface
output logic avm_enable,
output logic avm_read,
output logic avm_write,
output logic [DATA_W-1:0] avm_writedata,
output logic [BURSTCOUNT_W-1:0] avm_burstcount,
output logic [ADDRESS_W-1:0] avm_address,
output logic [BYTEENA_W-1:0] avm_byteenable,
input logic avm_waitrequest,
input logic avm_readdatavalid,
input logic [DATA_W-1:0] avm_readdata,
input logic avm_writeack, // not a true Avalon signal, so ignore this
// IC interface
input logic ic_arb_request,
input logic ic_arb_enable,
input logic ic_arb_read,
input logic ic_arb_write,
input logic [DATA_W-1:0] ic_arb_writedata,
input logic [BURSTCOUNT_W-1:0] ic_arb_burstcount,
input logic [ADDRESS_W-$clog2(DATA_W / 8)-1:0] ic_arb_address,
input logic [BYTEENA_W-1:0] ic_arb_byteenable,
input logic [ID_W-1:0] ic_arb_id,
output logic ic_arb_stall,
output logic ic_wrp_ack,
output logic ic_rrp_datavalid,
output logic [DATA_W-1:0] ic_rrp_data
);
assign avm_read = ic_arb_read;
assign avm_write = ic_arb_write;
assign avm_writedata = ic_arb_writedata;
assign avm_burstcount = ic_arb_burstcount;
assign avm_address = {ic_arb_address, {$clog2(DATA_W / 8){1'b0}}};
assign avm_byteenable = ic_arb_byteenable;
assign ic_arb_stall = avm_waitrequest;
assign ic_rrp_datavalid = avm_readdatavalid;
assign ic_rrp_data = avm_readdata;
//assign ic_wrp_ack = avm_writeack;
assign ic_wrp_ack = avm_write & ~avm_waitrequest;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000001; int eu[N], ev[N]; vector<pair<int, int> > g[N]; bool vis[N]; bool be[N]; int dfn[N], low[N], vbel[N], ebel[N], dfc, ebcc; int sz[N]; int dfs_ebcc(int u, int f) { static int s[N], t; s[++t] = u; dfn[u] = low[u] = ++dfc; for (pair<int, int> p : g[u]) { int v = p.first, i = p.second; if (vis[i]) continue; vis[i] = 1; s[++t] = -i; if (!dfn[v]) { if (eu[i] != u) swap(eu[i], ev[i]); low[u] = min(low[u], dfs_ebcc(v, i)); } else { if (low[v] < low[u] && eu[i] != u) swap(eu[i], ev[i]); low[u] = min(low[u], low[v]); } } if (dfn[u] == low[u]) { for (++ebcc; s[t] != -f; --t) s[t] > 0 ? vbel[s[t]] = ebcc : ebel[-s[t]] = ebcc; if (t) --t; } return low[u]; } vector<pair<int, int> > gt[N]; void dfs_dir(int u, int f) { for (pair<int, int> p : gt[u]) { int v = p.first, i = p.second; if (v == f) continue; if (vbel[eu[i]] == u) swap(eu[i], ev[i]); dfs_dir(v, u); } } int tarjan_ebcc(int n, int m) { dfc = ebcc = 0; fill_n(vis + 1, m, 0); fill_n(ebel + 1, m, 0); fill_n(dfn + 1, n, 0); for (int u = 1; u <= n; ++u) if (!dfn[u]) dfs_ebcc(u, 0); for (int i = 1; i <= n; ++i) sz[vbel[i]]++; for (int i = 1; i <= m; ++i) { if (ebel[i]) continue; gt[vbel[eu[i]]].emplace_back(vbel[ev[i]], i); gt[vbel[ev[i]]].emplace_back(vbel[eu[i]], i); } int r = max_element(sz + 1, sz + ebcc + 1) - sz; dfs_dir(r, 0); return sz[r]; } int main(void) { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= m; ++i) { int u, v; scanf( %d%d , &u, &v); eu[i] = u; ev[i] = v; g[u].emplace_back(v, i); g[v].emplace_back(u, i); } int ans = tarjan_ebcc(n, m); printf( %d n , ans); for (int i = 1; i <= m; ++i) printf( %d %d n , eu[i], ev[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, nxt[200010], a[200010], sz[200010][31]; long long ans = 0; map<int, int> mp; inline char gc() { static char *S, *T, buf[1 << 16]; if (T == S) { T = (S = buf) + fread(buf, 1, 1 << 16, stdin); if (T == S) return EOF; } return *S++; } inline int read() { int x = 0, f = 1; char ch = gc(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = gc(); } while ( 0 <= ch && ch <= 9 ) x = x * 10 + ch - 0 , ch = gc(); return x * f; } inline int check(int l, int r) { int res = 0; for (int i = 0; i <= 30; ++i) res |= ((sz[r][i] - sz[l - 1][i]) > 0) << i; return res; } int main() { n = read(); for (int i = 1; i <= n; ++i) { a[i] = read(), nxt[i] = mp[a[i]], mp[a[i]] = i; for (int j = 0; j <= 30; ++j) { sz[i][j] = sz[i - 1][j]; if (a[i] & (1 << j)) sz[i][j]++; } } for (int i = 1; i <= n; ++i) { int l = max(nxt[i] + 1, 1), r = i, nowl = i; while (l <= r) { int mid = l + r >> 1; if (check(mid, i) == a[i]) nowl = mid, r = mid - 1; else l = mid + 1; } l = i, r = n; int nowr = i; while (l <= r) { int mid = l + r >> 1; if (check(i, mid) == a[i]) nowr = mid, l = mid + 1; else r = mid - 1; } ans += 1ll * (i - nowl + 1) * (nowr - i + 1); } printf( %I64d n , 1ll * n * (n + 1) / 2 - ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21OI_4_V
`define SKY130_FD_SC_HD__A21OI_4_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21oi_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21OI_4_V
|
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