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/* lab2_part4.v
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module lab2_part4 (SW, LEDG, LEDR, HEX1, HEX0);
input [17:0] SW;
output [8:0] LEDR, LEDG;
output [0:6] HEX1, HEX0;
assign LEDR[8:0] = SW[8:0];
wire e1, e2;
comparator C0 (SW[3:0], e1);
comparator C1 (SW[7:4], e2);
assign LEDG[8] = e1 | e2;
wire c1, c2, c3;
wire [4:0] S;
fulladder A0 (SW[0], SW[4], SW[8], S[0], c1);
fulladder A1 (SW[1], SW[5], c1, S[1], c2);
fulladder A2 (SW[2], SW[6], c2, S[2], c3);
fulladder A3 (SW[3], SW[7], c3, S[3], S[4]);
assign LEDG[4:0] = S[4:0];
wire z;
wire [3:0] A, M;
comparator9 C2 (S[4:0], z);
circuitA AA (S[3:0], A);
mux_4bit_2to1 M0 (z, S[3:0], A, M);
circuitB BB (z, HEX1);
b2d_7seg S0 (M, HEX0);
endmodule
module fulladder (a, b, ci, s, co);
input a, b, ci;
output co, s;
wire d;
assign d = a ^ b;
assign s = d ^ ci;
assign co = (b & ~d) | (d & ci);
endmodule
module b2d_7seg (X, SSD);
input [3:0] X;
output [0:6] SSD;
assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]));
assign SSD[1] = ((~X[3] & X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & X[1] & ~X[0]));
assign SSD[2] = (~X[3] & ~X[2] & X[1] & ~X[0]);
assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]));
assign SSD[4] = ~((~X[2] & ~X[0]) | (X[1] & ~X[0]));
assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]));
endmodule
module comparator (V, z);
input [3:0] V;
output z;
assign z = (V[3] & (V[2] | V[1]));
endmodule
module comparator9 (V, z);
input [4:0] V;
output z;
assign z = V[4] | ((V[3] & V[2]) | (V[3] & V[1]));
endmodule
module circuitA (V, A);
input [3:0] V;
output [3:0] A;
assign A[0] = V[0];
assign A[1] = ~V[1];
assign A[2] = (~V[3] & ~V[1]) | (V[2] & V[1]);
assign A[3] = (~V[3] & V[1]);
endmodule
module circuitB (z, SSD);
input z;
output [0:6] SSD;
assign SSD[0] = z;
assign SSD[1:2] = 2'b00;
assign SSD[3:5] = {3{z}};
assign SSD[6] = 1;
endmodule
module mux_4bit_2to1 (s, U, V, M);
// if ~s, send U
input s;
input [3:0] U, V;
output [3:0] M;
assign M = ({4{~s}} & U) | ({4{s}} & V);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, k, a[2005][2005], ans, p; int main() { cin >> n >> m >> k; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { char c; c = getchar(); while (c != . && c != * ) c = getchar(); a[i][j] = c; if (c == . ) p++; } if (k == 1) { cout << p; return 0; } int x = 0; for (int i = 1; i <= n; i++) { x = 0; for (int j = 1; j <= m; j++) { if (a[i][j] == a[i][j - 1] && a[i][j] == . ) x++; else if (a[i][j] == . ) x = 1; else { if (x >= k) ans += x - k + 1; x = 0; } } if (x >= k) ans += x - k + 1; } for (int j = 1; j <= m; j++) { x = 0; for (int i = 1; i <= n; i++) { if (a[i][j] == a[i - 1][j] && a[i][j] == . ) x++; else if (a[i][j] == . ) x = 1; else { if (x >= k) ans += x - k + 1; x = 0; } } if (x >= k) ans += x - k + 1; } cout << endl << ans; }
|
// Attention!! Кеши важны и тут
// "FPGAs are very good at streaming models,
// while GPUs are better at burst mode models."
// Choose:
// http://electronics.stackexchange.com/questions/56302/how-to-access-ram-for-use-with-an-fpga-for-high-performance-computing
// https://www.altera.com/en_US/pdfs/literature/hb/nios2/edh_ed51008.pdf - from Altera
// fixme: internal (small peaces(15k - 2M)? as cache?) external (ddr, big)
// !!! "For the money, it is hard to beat an Intel i7
// based quad-core machine with a reasonable GPU card. Just warning you, in case all you really care about is math speed."
// DDR:
// https://docs.numato.com/kb/learning-fpga-verilog-beginners-guide-part-6-ddr-sdram/
// External RAM from Altera:
// https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/external-memory/emi.pdf
//
// Overview:
// https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp_ddr2.pdf
//
// ddr3: http://airccse.org/journal/jcsit/0811csit08.pdf
//
//================= Burst ====================
// "But when all you need it a single 8-bit byte, and the next
// memory access is another 8-bit byte somewhere else in memory, you can
// never take advantage of SDRAM bursting. You will always have the
// worst case access time (about 70ns in my case, based on the SDRAM I was using.)"
// https://www.altera.com/support/support-resources/knowledge-base/solutions/rd09182009_504.html
// "Understanding Avalon MM Bursting" youtube
// https://en.wikipedia.org/wiki/Burst_mode_(computing)
//================================= Impls =======================
// http://hackaday.com/2013/10/11/sdram-controller-for-low-end-fpgas/ - see comments
// https://people.ece.cornell.edu/land/courses/eceprojectsland/STUDENTPROJ/2007to2008/dp239/Denis-MEng-Final-nocode.pdf
//
// ddr3 arbiter
// https://web.wpi.edu/Pubs/E-project/Available/E-project-031212-183607/unrestricted/FPGA_Design_for_DDR3_Memory.pdf
// "Only one address and command is sent for every 512 bits sent." - 64 байта
//
// Q: записть куском, но если в блоке не наши данные?
// A: (?) "When the arbiter_block enters its Arbiter-to-Memory execution branch,
// it first executes all buffered write commands."
// loop accel:
// http://cas.ee.ic.ac.uk/people/gac1/pubs/SamFPGA12.pdf
// "Considering only a single bank within the device, each memory address within that
//bank can be divided into three bit fields, corresponding to SDRAM
//Row, Burst, and Byte Within Burst, as shown in Fig. 2. These three
//fields can be represented as vectors in Z
//3"
//
// !! detailed Good!!
// http://codehackcreate.com/archives/444
//====================== Q ==================
// refrech cucle?
//====================================
//
// vlog *.v; vsim -t ns work.ram_tb; do waves.do
//
//=================== Ram inference ==========================
// http://quartushelp.altera.com/14.1/mergedProjects/hdl/vlog/vlog_pro_ram_inferred.htm
//
// " Altera recommends that you create RAM
// blocks in separate entities or modules that contain only the RAM logic."
//
`timescale 10ns/1ps
//`default_nettype none
//============== Memories ===============================
// form all needs - on board ddr
// fixme: 64 байта(???) за раз? DATA - x32 - биты - prefetch может быть на 64 байта
// 8 * 2 * 4 = 64 - burst(8) ddr x32
// fixme: 32 bit - addr - 4 Gb (?) biiig
//
// http://frankdenneman.nl/2015/02/19/memory-deep-dive-memory-subsystem-bandwidth/
// data: 32 bytes = lines_per_clock * (bits_per_line / 8) * burst = (2 * 16 / 2) * 4
//
// addr: 256 / 32 = 8 = 2**3
`define DDR_ADDR_WIDTH 3
`define DDR_DATA_WIDTH 32
module on_board_ddr_controller(
output reg [`DDR_DATA_WIDTH-1:0] q,
input [`DDR_DATA_WIDTH-1:0] d,
input [`DDR_ADDR_WIDTH-1:0] write_address, read_address, // !! different !!
input we, clk);
// data size, count elems
reg [`DDR_DATA_WIDTH-1:0] mem [2**`DDR_ADDR_WIDTH-1:0];
parameter MEM_INIT_FILE = "src.mif";
initial begin
if (MEM_INIT_FILE != "") begin
$readmemh(MEM_INIT_FILE, mem);
end
end
always @ (posedge clk) begin
if (we)
mem[write_address] <= d;
q <= mem[read_address]; // q doesn't get d in this clock cycle
end
endmodule
//================= on-chip ====================
// !!! диапазоны ширин и глубин зависят от чипа
// "Altera recommends that you use the Old Data Read-During-Write coding
// style for most RAM blocks as long as"
module single_clk_ram(
output reg [15:0] q,
input [15:0] d,
input [6:0] write_address, read_address, // !! different !!
input we, clk);
reg [15:0] mem [127:0]; // data size, count elems
parameter MEM_INIT_FILE = "src.mif";
initial begin
if (MEM_INIT_FILE != "") begin
$readmemh(MEM_INIT_FILE, ram);
end
end
always @ (posedge clk) begin
if (we)
mem[write_address] <= d;
q <= mem[read_address]; // q doesn't get d in this clock cycle
end
endmodule
//=====================================================
module ram_tb;
// Task0:
// read bunch -> write back this bunch
`define DELAY_SIZE 4 // fixme: -1?? сколько триггеров?
// $dump*
// http://www.referencedesigner.com/tutorials/verilog/verilog_62.php
reg clk = 0;
reg [7:0] tick;
reg [`DDR_ADDR_WIDTH-1:0] ddr_rd_addr;
reg [`DDR_ADDR_WIDTH-1:0] ddr_wr_addr;
wire [`DDR_DATA_WIDTH-1:0] ddr_q;
reg [`DDR_DATA_WIDTH-1:0] ddr_d;
wire [7:0] ddr_byte0_q; // fixme: to array !!
wire we = 0;
//=======================================================
assign ddr_byte0_q = ddr_q[7:0];
on_board_ddr_controller i0__on_board_ddr_controller (
ddr_q, ddr_d, ddr_wr_addr, ddr_rd_addr, we, clk );
always #1 clk=~clk;
initial
begin
tick = 0;
ddr_rd_addr = 0;
ddr_wr_addr = 0;
end
always @(posedge clk) begin
tick <= tick + 1;
end
always @(posedge clk) begin
ddr_rd_addr <= ddr_rd_addr + 1;
end
// //=====================================================
// // Gotchas:
// //http://www.sutherland-hdl.com/papers/2007-SNUG-SanJose_gotcha_again_presentation.pdf
// integer i;
// always @ (posedge clk) begin
// for(i = 1; i < `DELAY_SIZE; i = i+1)
// tapped_line0[i] <= tapped_line0[i-1];
// end
// integer j;
// integer tmp;
// always @(*) begin
// // for(j = 0; j < 3; j = j + 1) begin
// // tmp = tmp + tapped_line0[j];
// // end
// sum = tapped_line0[0] + tapped_line0[1] + tapped_line0[2];
// end
endmodule
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
module top (
(* CLOCK_SIGNAL = "yes", WAVEFORM = "0 5" *)
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_proxy (
.I(clk),
.O(ibuf_proxy_out)
);
IBUF ibuf_inst (
.I(ibuf_proxy_out),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int_2 = clk_int_1;
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
middle middle_inst_1 (
.clk(ibuf_out),
.out(out[2])
);
middle middle_inst_2 (
.clk(clk_int_1),
.out(out[3])
);
middle middle_inst_3 (
.clk(clk_int_2),
.out(out[4])
);
middle middle_inst_4 (
.clk(clk2),
.out(out[5])
);
assign out[1:0] = {cnt[0], in[0]};
endmodule
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.ne2.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.ne2_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 1);
`assert(result_empty, 0);
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:11:22 11/09/2016
// Design Name:
// Module Name: background_painter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module background_painter(
input wire [9:0] hpos,
input wire [8:0] vpos,
input wire [11:0] code,
// input wire [32:0] num_a,
// input wire [32:0] num_b,
input wire [32:0] resultado,
input wire [4:0] res_out_code,
output reg [2:0] res_in_row,
output reg [3:0] num_salida,
output reg [3:0] out_row,
output reg [1:0] row,
output reg [2:0] column,
output reg [7:0] rgb
);
parameter [7:0]white = 8'b11111111;
parameter [7:0]gray = 8'b10010010;
parameter [7:0]blue = 8'b00000011;
parameter [7:0]black = 8'b00000000;
reg [3:0] col;
reg [3:0] exponente;
reg [29:0] tmp;
always @(*)
begin
if (vpos >= 204 && vpos < 228) //fila 0
begin
row = 0;
out_row = {(vpos - 204) / 2}[3:0];
end
else if(vpos >= 248 && vpos < 272) //fila 1
begin
row = 1;
out_row = {(vpos - 248) / 2}[3:0];
end
else if(vpos >= 292 && vpos < 316) //fila 2
begin
row = 2;
out_row = {(vpos - 292) / 2}[3:0];
end
else
begin
row = 3;
out_row = 0;
end
if (hpos >= 220 && hpos < 244) //columna 0
begin
column = 0;
col = {(hpos - 220) / 2}[3:0];
end
else if(hpos >= 264 && hpos < 288) //columna 1
begin
column = 1;
col = {(hpos - 264) / 2}[3:0];
end
else if(hpos >= 308 && hpos < 332) //columna 2
begin
column = 2;
col = {(hpos - 308) / 2}[3:0];
end
else if(hpos >= 352 && hpos < 376) //columna 3
begin
column = 3;
col = {(hpos - 352) / 2}[3:0];
end
else if(hpos >= 396 && hpos < 420) //columna 4
begin
column = 4;
col = {(hpos - 396) / 2}[3:0];
end
else if(hpos >= 440 && hpos < 462) //columna 5
begin
column = 5;
col = {(hpos - 440) / 2}[3:0];
end
else //ninguna fila
begin
column = 6;
col = 0;
end
end
always @(*)
begin
if ((hpos >= 260 && hpos < 420) && (vpos >= 172 && vpos < 184))
begin
res_in_row = {(vpos - 172)/2}[2:0];
exponente = {(9 - ((hpos - 260)/16))}[3:0];
case (exponente)
4'b0000: tmp = 1;
4'b0001: tmp = 10;
4'b0010: tmp = 100;
4'b0011: tmp = 1000;
4'b0100: tmp = 10000;
4'b0101: tmp = 100000;
4'b0110: tmp = ;
4'b0111: tmp = 10000000;
4'b1000: tmp = 100000000;
4'b1001: tmp = ;
default: tmp = 1;
endcase
/*if(vpos >= 124 && vpos < 136)
begin
num_salida = (num_a[31:0] / tmp) % 10;
if(((hpos - 260)%16 < 10) && res_out_code[((hpos - 260)%16)/2])
rgb = black;
else
rgb = gray;
end
else if(vpos >= 148 && vpos < 160)
begin
num_salida = (num_b[31:0] / tmp) % 10;
if(((hpos - 260)%16 < 10) && res_out_code[((hpos - 260)%16)/2])
rgb = black;
else
rgb = gray;
end
else*/ //if(vpos >= 172 && vpos < 184)
//begin
num_salida = (resultado[31:0] / tmp) % 10;
if(((hpos - 260)%16 < 10) && res_out_code[((hpos - 260)%16)/2])
rgb = black;
else
rgb = gray;
/*end
else
begin
num_salida = 0;
rgb = gray;
end*/
end
else if(hpos >= 250 && hpos < 256)
begin
num_salida = 0;
res_in_row = 0;
if (/*(vpos >= 124 && vpos < 136 && num_a[32])
|| (vpos >= 148 && vpos < 160 && num_b[32])
|| */(vpos >= 176 && vpos < 178 && resultado[32]))
rgb = black;
else
rgb = gray;
end
else if((row < 2 && column < 6) || (row == 2 && column < 5))
begin
res_in_row = 0;
if(code[col])
begin
rgb = white;
end
else
begin
rgb = blue;
end
num_salida = 0;
end
else
begin
num_salida = 0;
res_in_row = 0;
rgb = gray;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const long long MAX = 1e6 + 5; bool cmp(const pair<long long, long long> &a, const pair<long long, long long> &b) { if (a.first < b.first) return true; else if (a.first == b.first) { if (b.second > a.second) return true; return false; } return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long tc = 1, i, j; while (tc--) { long long n; cin >> n; long long a, b, c, d, e, f; cin >> a >> b >> c; cin >> d >> e >> f; long long mi, ma; mi = max(0LL, max(c - f - e, max(b - d - e, a - d - f))); ma = min(a, e) + min(b, f) + min(c, d); cout << mi << << ma << n ; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:01:22 04/21/2015
// Design Name:
// Module Name: e_finder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module e_finder(
input clk,
input [63:0] boundary,
output reg [63:0] e,
output reg done
);
reg input_enable;
reg next_input_enable;
reg next_done;
reg [12:0] index;
reg [12:0] next_index;
reg [63:0] next_e;
reg has_index_changed;
reg next_has_index_changed;
reg reset_exponentiation;
reg next_reset_exponentiation;
reg is_exponentiation_already_reset;
reg next_is_exponentiation_already_reset;
wire prime_list_ready;
wire [8:0] data;
wire exponent_finder_ready;
wire [7:0] exponent;
wire [99:0] exponentiation_result;
wire exponentiation_ready;
initial begin
input_enable = 0;
next_input_enable = 0;
done = 0;
next_done = 0;
index = 1;
next_index = 1; // index starts with 1
e = 1;
next_e = 1;
has_index_changed = 0;
next_has_index_changed = 0;
reset_exponentiation = 0;
next_reset_exponentiation = 0;
is_exponentiation_already_reset = 0;
next_is_exponentiation_already_reset = 0;
end
PrimeList prime_list (
.clk(clk),
.index(index),
.ready(prime_list_ready),
.data(data)
);
exponent_finder log (
.clk(clk),
.boundary(boundary),
.input_enable(input_enable),
.base(data),
.exponent(exponent),
.ready(exponent_finder_ready)
);
BinaryExponentiation binary_exponentiation (
.clk(clk),
.base(data),
.exponent(exponent-8'd1),
.reset(reset_exponentiation),
.result(exponentiation_result),
.isDone(exponentiation_ready)
);
always @(posedge clk) begin
input_enable <= next_input_enable;
done <= next_done;
index <= next_index;
e <= next_e;
has_index_changed <= next_has_index_changed;
reset_exponentiation <= next_reset_exponentiation;
is_exponentiation_already_reset <= next_is_exponentiation_already_reset;
end
always @(*) begin
if (prime_list_ready) begin
if (done) begin
next_input_enable = 0;
next_done = 1;
next_index = index;
next_e = e;
next_has_index_changed = 0;
next_reset_exponentiation = 0;
next_is_exponentiation_already_reset = 0;
end else begin
if (exponent_finder_ready) begin // after the prime list is ready and the exponent is ready, caculate prime ^ exponent first
if (!is_exponentiation_already_reset) begin
next_reset_exponentiation = 1; // pull the reset_exponentiation pin to high to start resetting
// don't change anything else
next_input_enable = 0; // don't change the exponent finder
next_done = 0;
next_index = index;
next_e = e;
next_has_index_changed = 0;
next_is_exponentiation_already_reset = 1;
end else begin // if the exponentiation module is already reset, then wait until it's ready
next_reset_exponentiation = 0; // pull down the reset_exponentiation pin
if (exponentiation_ready == 1 && reset_exponentiation == 0) begin // if the exponentiation is ready, then go ahead and calcuates the final result. Note that reset pin should be low here
if (exponent_finder_ready && (!has_index_changed) ) begin
if (exponent-1 == 1) begin // if the exponent is 1, we don't have to use the exponentiation module. Instead, just multiply e with the base
next_e = e * data;
end else begin // otherwise, use the result from the exponentiation module
next_e = e * exponentiation_result ;
end
next_input_enable = 0;
if (data >= 5) begin
next_done = 1;
end else begin
next_done = 0;
end
next_index = index + 1;
next_has_index_changed = 1;
next_is_exponentiation_already_reset = 1;
end else begin
next_input_enable = 1;
next_done = 0;
next_index = index;
next_e = e;
next_has_index_changed = 0;
next_is_exponentiation_already_reset = 0;
end
end else begin
next_input_enable = 0; // don't change the exppnent finder
next_done = 0;
next_index = index; // keep the prime
next_e = e;
next_has_index_changed = 0;
next_is_exponentiation_already_reset = 1;
end
end
end else begin
next_is_exponentiation_already_reset = 0;
next_reset_exponentiation = 0;
next_input_enable = 1;
next_done = 0;
next_index = index;
next_e = e;
next_has_index_changed = 0;
end
end
end else begin
next_input_enable = 0;
next_done = 0;
next_index = 1;
next_e = e;
next_has_index_changed = 0;
next_is_exponentiation_already_reset = 0;
next_reset_exponentiation = 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O31AI_PP_BLACKBOX_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T sqr(const T& a) { return a * a; } template <typename T> inline int sign(const T& a) { return a < 0 ? -1 : a > 0; } void task(); int main() { ios_base::sync_with_stdio(0); task(); return 0; } int h, q; long long int l, r; vector<pair<long long, long long> > bad; vector<pair<long long, long long> > ok; void task() { cin >> h >> q; long long int start = 1; for (int i = 1; i < h; ++i) start *= 2; l = start; r = start * 2 - 1; while (q--) { long long int i; long long int _l, _r, ans; cin >> i >> _l >> _r >> ans; while (_l < start) _l *= 2; while (_r < start) _r *= 2, ++_r; if (ans) { if (_l > r || _r < l) { cout << Game cheated! ; return; } l = max(l, _l); r = min(r, _r); ok.push_back(pair<long long, long long>{_l, _r}); } else { bad.push_back(pair<long long, long long>{_l, _r}); } } bad.push_back(pair<long long, long long>{-2, -2}); bad.push_back(pair<long long, long long>{4 * start, 4 * start}); sort((bad.begin()), (bad.end())); vector<pair<long long, long long> > v; pair<long long, long long> cur = bad[0]; for (int i = 1; i < (int)bad.size(); ++i) { pair<long long, long long> x = bad[i]; if (x.first <= cur.second + 1) { cur.second = max(cur.second, x.second); } else { v.push_back(cur); cur = x; } } v.push_back(cur); bad = v; vector<pair<long long, long long> > well; long long int sum = 0; for (int i = 1; i < bad.size(); ++i) { long long int ll = max(bad[i - 1].second, l - 1); long long int rr = min(r + 1, bad[i].first); long long int len = rr - ll - 1; if (len > 0) { well.push_back(pair<long long, long long>{ll + 1, rr - 1}); sum += len; } } if (sum == 0) { cout << Game cheated! ; } else if (sum == 1) { assert(well.front().first == well.front().second); assert(well.size() == 1); cout << well.front().first; } else { cout << Data not sufficient! ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211A_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O211A_PP_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o211a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long n, m, q; long long b[100000 + 1]; long long suma; long long sums; long long sum[100000 + 1]; long long sign(long long i) { return ((i & 1) ? 1 : (-1)); } inline long long poz(long long a) { return (a > 0 ? a : (-a)); } void readFile() { scanf( %lld%lld%lld , &n, &m, &q); long long i, nr; for (i = 1; i <= n; i++) { scanf( %lld , &nr); suma += nr * sign(i); } long long sumb = 0; long long cr = 1; for (i = 1; i <= m; i++) { scanf( %lld , &b[i]); if (i > n) { sumb -= (-b[i - n]); sumb = (-sumb); } if (i <= n) cr = (-cr); sumb += cr * b[i]; if (i >= n) sum[++sums] = sumb; } } long long elem(long long i) { if (i >= 1 && i <= sums) return sum[i]; return sum[1]; } void printRez() { long long i = 0; long long pas = (1 << 16); long long caut = -suma; while (pas != 0) { if (i + pas <= sums && sum[i + pas] <= caut) i += pas; pas >>= 1; } printf( %lld n , min(min(poz(suma + elem(i)), poz(suma + elem(i + 1))), poz(suma + elem(i - 1)))); } void ansQues() { sort(sum + 1, sum + sums + 1); printRez(); while (q > 0) { q--; long long st, dr, nr; scanf( %lld%lld%lld , &st, &dr, &nr); long long mns = (dr >> 1) - ((st - 1) >> 1); long long pls = (dr - st + 1) - mns; suma += 1LL * pls * nr; suma -= 1LL * mns * nr; printRez(); } } int main() { readFile(); ansQues(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int XI = INT_MAX, NI = INT_MIN, MOD = 1e9 + 7; string s; int a[400]; int main() { cin >> s; for (int i = 0; i < 26; i++) { a[s[i]]++; } for (int i = 25; i < s.length(); i++) { bool k = 1; int cnt = 0; string second = ; for (int j = A ; j <= Z ; j++) { if (a[j] > 1) { k = 0; break; } if (a[j] == 0) { cnt++; second += (char)j; } } if (cnt != a[ ? ]) k = 0; if (k) { int y = 0; for (int x = 0; x < i - 25; x++) { if (s[x] != ? ) cout << s[x]; else cout << A ; } for (int x = i - 25; x < i + 1; x++) { if (s[x] != ? ) cout << s[x]; else { cout << second[y]; y++; } } for (int x = i + 1; x < s.length(); x++) { if (s[x] != ? ) cout << s[x]; else cout << A ; } cout << endl; return 0; } if (i + 1 == s.size()) break; a[s[i + 1]]++; a[s[i - 25]]--; } cout << -1 << endl; }
|
`include "constants.vh"
//`default_nettype none
module alloc_issue_ino #(
parameter ENTSEL = 2,
parameter ENTNUM = 4
)
(
input wire clk,
input wire reset,
input wire [1:0] reqnum,
input wire [ENTNUM-1:0] busyvec,
input wire [ENTNUM-1:0] prbusyvec_next,
input wire [ENTNUM-1:0] readyvec,
input wire prmiss,
input wire exunit_busynext,
input wire stall_DP,
input wire kill_DP,
output reg [ENTSEL-1:0] allocptr,
output wire allocatable,
output wire [ENTSEL-1:0] issueptr,
output wire issuevalid
);
wire [ENTSEL-1:0] allocptr2 = allocptr + 1;
wire [ENTSEL-1:0] b0;
wire [ENTSEL-1:0] e0;
wire [ENTSEL-1:0] b1;
wire [ENTSEL-1:0] e1;
wire notfull;
wire [ENTSEL-1:0] ne1;
wire [ENTSEL-1:0] nb0;
wire [ENTSEL-1:0] nb1;
wire notfull_next;
search_begin #(ENTSEL, ENTNUM) sb1(
.in(busyvec),
.out(b1),
.en()
);
search_end #(ENTSEL, ENTNUM) se1(
.in(busyvec),
.out(e1),
.en()
);
search_end #(ENTSEL, ENTNUM) se0(
.in(~busyvec),
.out(e0),
.en(notfull)
);
search_begin #(ENTSEL, ENTNUM) snb1(
.in(prbusyvec_next),
.out(nb1),
.en()
);
search_end #(ENTSEL, ENTNUM) sne1(
.in(prbusyvec_next),
.out(ne1),
.en()
);
search_begin #(ENTSEL, ENTNUM) snb0(
.in(~prbusyvec_next),
.out(nb0),
.en(notfull_next)
);
assign issueptr = ~notfull ? allocptr :
((b1 == 0) && (e1 == ENTNUM-1)) ? (e0+1) :
b1;
assign issuevalid = readyvec[issueptr] & ~prmiss & ~exunit_busynext;
assign allocatable = (reqnum == 2'h0) ? 1'b1 :
(reqnum == 2'h1) ? ((~busyvec[allocptr] ? 1'b1 : 1'b0)) :
((~busyvec[allocptr] && ~busyvec[allocptr2]) ? 1'b1 : 1'b0);
always @ (posedge clk) begin
if (reset) begin
allocptr <= 0;
end else if (prmiss) begin
allocptr <= ~notfull_next ? allocptr :
(((nb1 == 0) && (ne1 == ENTNUM-1)) ? nb0 : (ne1+1));
end else if (~stall_DP && ~kill_DP) begin
allocptr <= allocptr + reqnum;
end
end
endmodule // alloc_issue_ino
//`default_nettype wire
|
module dcache_top
(
// System clock, reset and stall
clk_i,
rst_i,
// to Data Memory interface
mem_data_i,
mem_ack_i,
mem_data_o,
mem_addr_o,
mem_enable_o,
mem_write_o,
// to CPU interface
p1_data_i,
p1_addr_i,
p1_MemRead_i,
p1_MemWrite_i,
p1_data_o,
p1_stall_o
);
//
// System clock, start
//
input clk_i;
input rst_i;
//
// to Data Memory interface
//
input [256-1:0] mem_data_i;
input mem_ack_i;
output [256-1:0] mem_data_o;
output [32-1:0] mem_addr_o;
output mem_enable_o;
output mem_write_o;
//
// to core interface
//
input [32-1:0] p1_data_i;
input [32-1:0] p1_addr_i;
input p1_MemRead_i;
input p1_MemWrite_i;
output [32-1:0] p1_data_o;
output p1_stall_o;
//
// to SRAM interface
//
wire [4:0] cache_sram_index;
wire cache_sram_enable;
wire [23:0] cache_sram_tag;
wire [255:0] cache_sram_data;
wire cache_sram_write;
wire [23:0] sram_cache_tag;
wire [255:0] sram_cache_data;
// cache
wire sram_valid;
wire sram_dirty;
// controller
parameter STATE_IDLE = 3'h0,
STATE_READMISS = 3'h1,
STATE_READMISSOK = 3'h2,
STATE_WRITEBACK = 3'h3,
STATE_MISS = 3'h4;
reg [2:0] state;
reg mem_enable;
reg mem_write;
reg cache_we;
wire cache_dirty;
reg write_back;
// regs & wires
wire [4:0] p1_offset;
wire [4:0] p1_index;
wire [21:0] p1_tag;
wire [255:0] r_hit_data;
wire [21:0] sram_tag;
wire hit;
reg [255:0] w_hit_data;
wire write_hit;
wire p1_req;
reg [31:0] p1_data;
// project1 interface
assign p1_req = p1_MemRead_i | p1_MemWrite_i;
assign p1_offset = p1_addr_i[4:0];
assign p1_index = p1_addr_i[9:5];
assign p1_tag = p1_addr_i[31:10];
assign p1_stall_o = ~hit & p1_req;
assign p1_data_o = p1_data;
// SRAM interface
assign sram_valid = sram_cache_tag[23];
assign sram_dirty = sram_cache_tag[22];
assign sram_tag = sram_cache_tag[21:0];
assign cache_sram_index = p1_index;
assign cache_sram_enable = p1_req;
assign cache_sram_write = cache_we | write_hit;
assign cache_sram_tag = {1'b1, cache_dirty, p1_tag};
assign cache_sram_data = (hit) ? w_hit_data : mem_data_i;
// memory interface
assign mem_enable_o = mem_enable;
assign mem_addr_o = (write_back) ? {sram_tag, p1_index, 5'b0} : {p1_tag, p1_index, 5'b0};
assign mem_data_o = sram_cache_data;
assign mem_write_o = mem_write;
assign write_hit = hit & p1_MemWrite_i;
assign cache_dirty = write_hit;
// tag comparator
assign hit = (p1_tag==sram_tag)&sram_valid;
assign r_hit_data = hit?sram_cache_data:mem_data_o;
wire [4:0] cache_addr;
assign cache_addr=p1_offset<<3;
// read data : 256-bit to 32-bit
always@(p1_offset or r_hit_data) begin
case(p1_offset)
0: p1_data <= r_hit_data[31:0];
1: p1_data <= r_hit_data[39:8];
2: p1_data <= r_hit_data[47:16];
3: p1_data <= r_hit_data[55:24];
4: p1_data <= r_hit_data[63:32];
5: p1_data <= r_hit_data[71:40];
6: p1_data <= r_hit_data[79:48];
7: p1_data <= r_hit_data[87:56];
8: p1_data <= r_hit_data[95:64];
9: p1_data <= r_hit_data[103:72];
10: p1_data <= r_hit_data[111:80];
11: p1_data <= r_hit_data[119:88];
12: p1_data <= r_hit_data[127:96];
13: p1_data <= r_hit_data[135:104];
14: p1_data <= r_hit_data[143:112];
15: p1_data <= r_hit_data[151:120];
16: p1_data <= r_hit_data[159:128];
17: p1_data <= r_hit_data[167:136];
18: p1_data <= r_hit_data[175:144];
19: p1_data <= r_hit_data[183:152];
20: p1_data <= r_hit_data[191:160];
21: p1_data <= r_hit_data[199:168];
22: p1_data <= r_hit_data[207:176];
23: p1_data <= r_hit_data[215:184];
24: p1_data <= r_hit_data[223:192];
25: p1_data <= r_hit_data[231:200];
26: p1_data <= r_hit_data[239:208];
27: p1_data <= r_hit_data[247:216];
28: p1_data <= r_hit_data[255:224];
29: p1_data <= r_hit_data[255:232];
30: p1_data <= r_hit_data[255:240];
31: p1_data <= r_hit_data[255:248];
endcase
end
// write data : 32-bit to 256-bit
always@(p1_offset or r_hit_data or p1_data_i) begin
w_hit_data <= r_hit_data;
case(p1_offset)
0: w_hit_data[31:0] <= p1_data_i;
1: w_hit_data[39:8] <= p1_data_i;
2: w_hit_data[47:16] <= p1_data_i;
3: w_hit_data[55:24] <= p1_data_i;
4: w_hit_data[63:32] <= p1_data_i;
5: w_hit_data[71:40] <= p1_data_i;
6: w_hit_data[79:48] <= p1_data_i;
7: w_hit_data[87:56] <= p1_data_i;
8: w_hit_data[95:64] <= p1_data_i;
9: w_hit_data[103:72] <= p1_data_i;
10: w_hit_data[111:80] <= p1_data_i;
11: w_hit_data[119:88] <= p1_data_i;
12: w_hit_data[127:96] <= p1_data_i;
13: w_hit_data[135:104] <= p1_data_i;
14: w_hit_data[143:112] <= p1_data_i;
15: w_hit_data[151:120] <= p1_data_i;
16: w_hit_data[159:128] <= p1_data_i;
17: w_hit_data[167:136] <= p1_data_i;
18: w_hit_data[175:144] <= p1_data_i;
19: w_hit_data[183:152] <= p1_data_i;
20: w_hit_data[191:160] <= p1_data_i;
21: w_hit_data[199:168] <= p1_data_i;
22: w_hit_data[207:176] <= p1_data_i;
23: w_hit_data[215:184] <= p1_data_i;
24: w_hit_data[223:192] <= p1_data_i;
25: w_hit_data[231:200] <= p1_data_i;
26: w_hit_data[239:208] <= p1_data_i;
27: w_hit_data[247:216] <= p1_data_i;
28: w_hit_data[255:224] <= p1_data_i;
29: w_hit_data[255:232] <= p1_data_i;
30: w_hit_data[255:240] <= p1_data_i;
31: w_hit_data[255:248] <= p1_data_i;
endcase
end
// controller
always@(posedge clk_i or negedge rst_i) begin
if(~rst_i) begin
state <= STATE_IDLE;
mem_enable <= 1'b0;
mem_write <= 1'b0;
cache_we <= 1'b0;
write_back <= 1'b0;
end
else begin
case(state)
STATE_IDLE: begin
if(p1_req && !hit) begin //wait for request
state <= STATE_MISS;
end
else begin
state <= STATE_IDLE;
end
end
STATE_MISS: begin
if(sram_dirty) begin //write back if dirty
write_back <= 1;
mem_write <= 1;
mem_enable <= 1;
state <= STATE_WRITEBACK;
end
else begin //write allocate: write miss = read miss + write hit; read miss = read miss + read hit
mem_enable <= 1;
state <= STATE_READMISS;
end
end
STATE_READMISS: begin
if(mem_ack_i) begin //wait for data memory acknowledge
mem_enable <= 0;
cache_we <= 1;
state <= STATE_READMISSOK;
end
else begin
mem_enable <= 1;
state <= STATE_READMISS;
end
end
STATE_READMISSOK: begin //wait for data memory acknowledge
cache_we <= 0;
state <= STATE_IDLE;
end
STATE_WRITEBACK: begin
if(mem_ack_i) begin //wait for data memory acknowledge
mem_write <= 0;
write_back <= 0;
state <= STATE_READMISS;
end
else begin
state <= STATE_WRITEBACK;
end
end
endcase
end
end
//
// Tag SRAM 0
//
dcache_tag_sram dcache_tag_sram
(
.clk_i(clk_i),
.addr_i(cache_sram_index),
.data_i(cache_sram_tag),
.enable_i(cache_sram_enable),
.write_i(cache_sram_write),
.data_o(sram_cache_tag)
);
//
// Data SRAM 0
//
dcache_data_sram dcache_data_sram
(
.clk_i(clk_i),
.addr_i(cache_sram_index),
.data_i(cache_sram_data),
.enable_i(cache_sram_enable),
.write_i(cache_sram_write),
.data_o(sram_cache_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int maxn = 1010; int Dp[maxn][maxn], dp[maxn][maxn], f[maxn][maxn], g[maxn][maxn]; int a[maxn][maxn]; int n, m; int main() { while (~scanf( %d%d , &n, &m)) { for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) scanf( %d , &a[i][j]); memset(Dp, 0, sizeof(Dp)); memset(dp, 0, sizeof(dp)); memset(f, 0, sizeof(f)); memset(g, 0, sizeof(g)); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) dp[i][j] = max(dp[i - 1][j], dp[i][j - 1]) + a[i][j]; for (int i = n; i >= 1; --i) for (int j = m; j >= 1; --j) Dp[i][j] = max(Dp[i + 1][j], Dp[i][j + 1]) + a[i][j]; for (int i = n; i >= 1; --i) for (int j = 1; j <= m; ++j) f[i][j] = max(f[i + 1][j], f[i][j - 1]) + a[i][j]; for (int i = 1; i <= n; ++i) for (int j = m; j >= 1; --j) g[i][j] = max(g[i - 1][j], g[i][j + 1]) + a[i][j]; int Ans = 0; for (int i = 2; i < n; ++i) for (int j = 2; j < m; ++j) Ans = max(Ans, max(dp[i - 1][j] + Dp[i + 1][j] + f[i][j - 1] + g[i][j + 1], dp[i][j - 1] + Dp[i][j + 1] + f[i + 1][j] + g[i - 1][j])); printf( %d n , Ans); } }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom_botao.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module rom_botao (
address,
clock,
q);
input [6:0] address;
input clock;
output [20:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./mif/botao.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "123"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
// Retrieval info: PRIVATE: WidthData NUMERIC "21"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./mif/botao.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "123"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "21"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 21 0 OUTPUT NODEFVAL "q[20..0]"
// Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 21 0 @q_a 0 0 21 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_botao.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_botao.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_botao.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_botao.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_botao_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_botao_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; const int N = 579; const long long P = 1000000007; int n, b[N]; long long d[N][N]; long long solve(int l, int r) { if (l == r) return 1; static bool used[N][N]; static long long ans[N][N]; if (used[l][r]) return ans[l][r]; used[l][r] = true; ++l; ++r; d[l][0] = 1; for (int i = 0; i < r - l; ++i) { if (d[l][i + 1] != -1) continue; int c = l + i; d[l][i + 1] = 0; for (int j = 0; j <= i; ++j) if (b[j + l] < b[c + 1]) (d[l][i + 1] += d[l][j] * solve(j + l, c)) %= P; } long long res = 0; for (int j = 0; j <= r - l - 1; ++j) (res += d[l][j] * solve(j + l, r - 1)) %= P; --l; --r; return ans[l][r] = res; } int main() { memset(d, -1, sizeof(d)); std::cin >> n; for (int i = 0; i < n; ++i) std::cin >> b[i]; if (b[0] == 1) std::cout << solve(0, n - 1) << n ; else std::cout << 0 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long int> prm(1000010, 1); long long int P = 1e9 + 7; long long int M = 998244353; char adjlist[1001][1001]; bool visited[1000001] = {false}; long double pi = 3.14159265358979323846264338327950; map<int, int> visit; map<int, set<int>> g; int cc = 0; vector<pair<int, int>> moves = {{1, 0}, {-1, 0}, {0, 1}, {0, -1}}; int lps[1000000]; vector<pair<int, int>> final_set; bool comp(const pair<long long int, long long int> &a, const pair<long long int, long long int> &b) { if (a.first == b.first) return a.second > b.second; return a.first < b.first; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, m, s, f; cin >> n >> m >> s >> f; bool flag = true; long long int curr = s; if (s > f) flag = false; long long int i, j; long long int t, x, y; bool mflag = false; long long int back = 0; string str = ; for (i = 0; i < m; i++) { if (i == 0) back = 0; else back = t; cin >> t >> x >> y; if (curr == f) continue; if (t - 1 != back) { while (back + 1 < t) { if (flag == false) { str.push_back( L ); curr--; } else { str.push_back( R ); curr++; } if (curr == f) break; back++; } } if (curr == f) continue; if (flag == false) { if (curr < x || curr - 1 > y) { str.push_back( L ); curr--; continue; } else { str.push_back( X ); continue; } } else { if (curr > y || curr + 1 < x) { str.push_back( R ); curr++; continue; } else { str.push_back( X ); continue; } } } if (curr != f) { if (flag == false) { for (i = curr; i > f; i--) str.push_back( L ); } else { for (i = curr; i < f; i++) str.push_back( R ); } } cout << str << n ; }
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#include <bits/stdc++.h> using namespace std; signed main() { std::ios::sync_with_stdio(false); cin.tie(NULL); long long n, k; cin >> n >> k; string s; cin >> s; s = 0 + s + 0 ; for (long long i = 0; i < s.length() - 1; i++) { if (k == 0) break; if (s[i] == 4 && s[i + 1] == 4 && s[i + 2] == 7 && i % 2) { k = k % 2; if (k) { s[i + 1] = 7 ; } k = 0; } else if (s[i] == 4 && s[i + 1] == 7 && s[i + 2] == 7 && i % 2) { k = k % 2; if (k) { s[i + 1] = 4 ; } k = 0; } else if (s[i] == 4 && s[i + 1] == 7 && i % 2) { s[i + 1] = 4 ; k--; } else if (s[i] == 4 && s[i + 1] == 7 ) { s[i] = 7 ; k--; } } cout << s.substr(1, n); return 0; }
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#include <bits/stdc++.h> using namespace std; struct InputReader { char buf[1000001]; int p; inline InputReader() { p = 1000001; } inline void Flush() { p = 0; fread(buf, 1, 1000001, stdin); } inline char C() { if (p >= 1000001) Flush(); return buf[p++]; } inline char Readnum() { char ch = C(); while (!isdigit(ch) && ch != - ) ch = C(); return ch; } inline void Readalpha(char &c) { c = C(); while (!isalpha(c)) c = C(); } int operator()() { int ans = 0, fu = 1; char ch = Readnum(); if (ch == - ) fu = -1, ch = C(); while (ch >= 0 && ch <= 9 ) { ans = ans * 10 + ch - 0 ; ch = C(); } return ans * fu; } long long Readll() { long long ans = 0LL, fu = 1LL; char ch = Readnum(); if (ch == - ) fu = -1LL, ch = C(); while (ch >= 0 && ch <= 9 ) { ans = ans * 10LL + ch - 0 ; ch = C(); } return ans * fu; } inline void Readstring(string &x) { x.clear(); char ch = C(); while (!isdigit(ch) && !isalpha(ch) && ch != # && ch != . ) ch = C(); while (isdigit(ch) || isalpha(ch) || ch == # || ch == . ) { x += ch; ch = C(); } } inline void Readchstring(char s[]) { int len = 0; char ch = C(); while (!isdigit(ch) && !isalpha(ch)) ch = C(); while (isdigit(ch) || isalpha(ch)) { s[len++] = ch; ch = C(); } s[len] = 0 ; } inline void Specialread(char &c) { c = C(); while (!isdigit(c) && !isalpha(c) && c != # && c != . && c != = && c != B ) c = C(); } } In; inline void Read(int &x) { x = In(); } inline void Read(int &x, int &y) { x = In(); y = In(); } inline void Read(int &x1, int &x2, int &x3) { x1 = In(); x2 = In(); x3 = In(); } inline void Read(int &x1, int &x2, int &x3, int &x4) { x1 = In(); x2 = In(); x3 = In(); x4 = In(); } inline void Read(long long &x) { x = In.Readll(); } inline void Read(long long &x, long long &y) { x = In.Readll(); y = In.Readll(); } inline void Read(long long &x1, long long &x2, long long &x3) { x1 = In.Readll(); x2 = In.Readll(); x3 = In.Readll(); } inline void Read(long long &x1, long long &x2, long long &x3, long long &x4) { x1 = In.Readll(); x2 = In.Readll(); x3 = In.Readll(); x4 = In.Readll(); } template <typename T> void Read(T a[], int st, int ed) { for (int(i) = (st); (i) <= (ed); ++(i)) Read(a[i]); } inline void FILEIO() {} inline void FILEIO(string pname) { freopen((pname + .in ).c_str(), r , stdin); freopen((pname + .out ).c_str(), w , stdout); } inline void FILEIO_OICONTEST(string pname) { freopen((pname + .in ).c_str(), r , stdin); freopen((pname + .out ).c_str(), w , stdout); } void Printtime() {} void END() { Printtime(); exit(0); } template <typename T> void END(T mes) { cout << mes << endl; END(); } template <typename T> void Print(T a[], int s, int t, char sp = , char ed = n ) { if (s > t) return; for (int i = s; i < t; i++) cout << a[i] << sp; cout << a[t] << ed; cout.flush(); } template <typename T> void Print(T a, int s = 0, int t = -1, char sp = , char ed = n ) { if (t == -1) t = a.size() - 1; for (int i = s; i <= t; i++) cout << a[i] << sp; cout << ed; cout.flush(); } long long Pow(long long a, long long b, long long p = (1000000007LL)) { long long ret = 1; for (; b; a = a * a % p, b >>= 1LL) if (b & 1LL) ret = ret * a % p; return ret; } long long Inv(long long a, long long p = (1000000007LL)) { return Pow(a, p - 2LL, p); } int n; long long a[524288], va[524288]; long long lowerl[524288], lowerr[524288]; long long tree[524288]; inline void Add(int pos, long long x) { assert(pos <= n + 1); for (; pos <= n; pos += ((pos) & (-pos))) { tree[pos] += x; tree[pos] = (tree[pos]) >= (1000000007LL) ? ((tree[pos]) - (1000000007LL)) : (tree[pos]); } } inline long long Sum(int pos) { long long ans = 0; for (; pos; pos -= ((pos) & (-pos))) { ans += tree[pos]; ans = (ans) >= (1000000007LL) ? ((ans) - (1000000007LL)) : (ans); } return ans; } void CalcLowerL() { memset(tree, 0, sizeof(tree)); for (int(i) = 1; (i) <= (n); ++(i)) { lowerl[i] = Sum(va[i] - 1); Add(va[i], i); } } void CalcLowerR() { memset(tree, 0, sizeof(tree)); for (int(i) = (n); (i) >= 1; --(i)) { lowerr[i] = Sum(va[i] - 1); Add(va[i], n - i + 1); } } int main() { FILEIO(); Read(n); vector<long long> d; d.clear(); for (int(i) = 1; (i) <= (n); ++(i)) { Read(a[i]); d.push_back(a[i]); } sort(d.begin(), d.end()); d.resize(unique(d.begin(), d.end()) - d.begin()); for (int(i) = 1; (i) <= (n); ++(i)) { va[i] = lower_bound(d.begin(), d.end(), a[i]) - d.begin() + 1; } CalcLowerL(); CalcLowerR(); long long ans = 0; for (int(i) = 1; (i) <= (n); ++(i)) { ans += 1LL * a[i] * i % (1000000007LL) * (n - i + 1) % (1000000007LL); ans = (ans) >= (1000000007LL) ? ((ans) - (1000000007LL)) : (ans); } for (int(i) = 1; (i) <= (n); ++(i)) { long long tans = (n - i + 1) * lowerl[i] + i * lowerr[i]; tans %= (1000000007LL); tans = tans * a[i] % (1000000007LL); ans += tans; ans = (ans) >= (1000000007LL) ? ((ans) - (1000000007LL)) : (ans); } cout << ans << endl; END(); }
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/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: True dual port ram with single clock
Copyright (C) 2013 Stefan Kristiansson <>
******************************************************************************/
module mor1kx_true_dpram_sclk
#(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32
)
(
input clk,
input [ADDR_WIDTH-1:0] addr_a,
input we_a,
input [DATA_WIDTH-1:0] din_a,
output [DATA_WIDTH-1:0] dout_a,
input [ADDR_WIDTH-1:0] addr_b,
input we_b,
input [DATA_WIDTH-1:0] din_b,
output [DATA_WIDTH-1:0] dout_b
);
reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
reg [DATA_WIDTH-1:0] rdata_a;
reg [DATA_WIDTH-1:0] rdata_b;
assign dout_a = rdata_a;
assign dout_b = rdata_b;
always @(posedge clk) begin
if (we_a) begin
mem[addr_a] <= din_a;
rdata_a <= din_a;
end else begin
rdata_a <= mem[addr_a];
end
end
always @(posedge clk) begin
if (we_b) begin
mem[addr_b] <= din_b;
rdata_b <= din_b;
end else begin
rdata_b <= mem[addr_b];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t; cin >> t; vector<int> a(7); while (t--) { long long k; cin >> k; int sum = 0; for (int i = 0; i < 7; i++) { cin >> a[i]; sum += a[i]; } long long ans = (k / sum) * 7; long long rem = k % sum; if (rem == 0) { ans -= 7; rem = sum; } int min = 7; int count = 0, count_sum = 0; for (int i = 0; i < 7; i++) { count = 0; count_sum = 0; for (int j = 0; j < 7; j++) { count++; if (a[(i + j) % 7]) { count_sum++; } if (count_sum == rem) { if (count < min) { min = count; break; } } } } cout << ans + min << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { register int x = 0, f = 1; register char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = 0; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + (ch ^ 0 ); ch = getchar(); } return f ? x : -x; } int n, m, yt, Y[200005]; struct subway { int x, y; } sbw[100005]; struct rabbit { int x, y, dis; } rbt[100005]; struct BIT { int tr[200005]; void modify(int x, int v) { for (; x <= yt; x += x & -x) tr[x] = max(tr[x], v); } int query(int x) { int ans = -1000000000; for (; x; x -= x & -x) ans = max(ans, tr[x]); return ans; } } bit; struct node { int x, y, id; } q[200005]; void work() { memset(bit.tr, -0x3f, sizeof bit.tr); yt = 0; for (int i = (1), _ed_ = (n); i <= _ed_; ++i) { Y[++yt] = rbt[i].y; } for (int i = (1), _ed_ = (m); i <= _ed_; ++i) { Y[++yt] = sbw[i].y; } sort(Y + 1, Y + yt + 1), yt = unique(Y + 1, Y + yt + 1) - Y - 1; for (int i = (1), _ed_ = (n); i <= _ed_; ++i) q[i] = (node){rbt[i].x, rbt[i].y, i}; for (int i = (1), _ed_ = (m); i <= _ed_; ++i) q[n + i] = (node){sbw[i].x, sbw[i].y, n + i}; sort(q + 1, q + n + m + 1, [&](node a, node b) { return a.x == b.x ? a.id > b.id : a.x < b.x; }); for (int i = (1), _ed_ = (n + m); i <= _ed_; ++i) { if (q[i].id > n) bit.modify(lower_bound(Y + 1, Y + yt + 1, q[i].y) - Y, q[i].x + q[i].y); else rbt[q[i].id].dis = min(rbt[q[i].id].dis, q[i].x + q[i].y - bit.query(lower_bound(Y + 1, Y + yt + 1, q[i].y) - Y)); } } int rt[100005], tcnt, tr[6000005], ls[6000005], rs[6000005]; void pushup(int p) { tr[p] = tr[ls[p]] + tr[rs[p]]; } void insert(int& x, int y, int l, int r, int pos) { x = ++tcnt; tr[x] = tr[y], ls[x] = ls[y], rs[x] = rs[y]; if (l == r) return ++tr[x], void(); int mid = (l + r) >> 1; if (pos <= mid) insert(ls[x], ls[y], l, mid, pos); else insert(rs[x], rs[y], mid + 1, r, pos); pushup(x); } int query(int x, int y, int l, int r, int L, int R) { if (L > R || x == y) return 0; if (L <= l && r <= R) return tr[x] - tr[y]; int mid = (l + r) >> 1, ans = 0; if (L <= mid) ans += query(ls[x], ls[y], l, mid, L, R); if (ans) return ans; if (mid < R) ans += query(rs[x], rs[y], mid + 1, r, L, R); return ans; } int lower(int x) { int l = 1, r = m, ans = r + 1; while (l <= r) { int mid = (l + r) >> 1; if (sbw[mid].x >= x) ans = mid, r = mid - 1; else l = mid + 1; } return ans; } int upper(int x) { int l = 1, r = m, ans = r + 1; while (l <= r) { int mid = (l + r) >> 1; if (sbw[mid].x > x) ans = mid, r = mid - 1; else l = mid + 1; } return ans - 1; } int query(int x, int y) { int l = 0, r = 1000000000, ans, L, R, D, U; while (l <= r) { int mid = (l + r) >> 1; L = lower(x - mid), R = upper(x + mid), D = lower_bound(Y + 1, Y + yt + 1, y - mid) - Y, U = upper_bound(Y + 1, Y + yt + 1, y + mid) - Y - 1; if (L <= R && query(rt[R], rt[L - 1], 1, yt, D, U)) ans = mid, r = mid - 1; else l = mid + 1; } return ans; } struct square { int x1, y1, x2, y2; square(int x1 = 0, int y1 = 0, int x2 = 0, int y2 = 0) : x1(x1), y1(y1), x2(x2), y2(y2) {} void merge(square o) { x1 = max(x1, o.x1), y1 = max(y1, o.y1); x2 = min(x2, o.x2), y2 = min(y2, o.y2); } bool valid() { if (x1 == x2 && y1 == y2 && (x1 + y1) & 1) return 0; return x1 <= x2 && y1 <= y2; } }; bool check(int tim) { int p = n; while (p && rbt[p].dis > tim) --p; square nw(-1000000000, -1000000000, 1000000000, 1000000000); for (int i = (n), _ed_ = (p + 1); i >= _ed_; --i) nw.merge( square(rbt[i].x - tim, rbt[i].y - tim, rbt[i].x + tim, rbt[i].y + tim)); int L, R, D, U; while (p && nw.valid()) { int t = tim - rbt[p].dis, x1 = nw.x1, y1 = nw.y1, x2 = nw.x2, y2 = nw.y2; if (x1 == x2) { if ((x1 + y1) & 1) ++y1; if ((x2 + y2) & 1) --y2; } else if (y1 == y2) { if ((x1 + y1) & 1) ++x1; if ((x2 + y2) & 1) --x2; } if (x1 <= x2 && y1 <= y2) { L = lower(x1 - t), R = upper(x2 + t), D = lower_bound(Y + 1, Y + yt + 1, y1 - t) - Y, U = upper_bound(Y + 1, Y + yt + 1, y2 + t) - Y - 1; if (L <= R && query(rt[R], rt[L - 1], 1, yt, D, U)) return 1; } nw.merge( square(rbt[p].x - tim, rbt[p].y - tim, rbt[p].x + tim, rbt[p].y + tim)); --p; } if (nw.valid()) return 1; return 0; } int main() { n = read(), m = read(); for (int i = (1), _ed_ = (n); i <= _ed_; ++i) rbt[i] = (rabbit){read(), read(), 1000000000}; for (int i = (1), _ed_ = (m); i <= _ed_; ++i) sbw[i] = (subway){read(), read()}; for (int i = (1), _ed_ = (n); i <= _ed_; ++i) { rbt[i].x *= -1; } for (int i = (1), _ed_ = (m); i <= _ed_; ++i) { sbw[i].x *= -1; } work(); for (int i = (1), _ed_ = (n); i <= _ed_; ++i) { rbt[i].y *= -1; } for (int i = (1), _ed_ = (m); i <= _ed_; ++i) { sbw[i].y *= -1; } work(); for (int i = (1), _ed_ = (n); i <= _ed_; ++i) { rbt[i].x *= -1; } for (int i = (1), _ed_ = (m); i <= _ed_; ++i) { sbw[i].x *= -1; } work(); for (int i = (1), _ed_ = (n); i <= _ed_; ++i) { rbt[i].y *= -1; } for (int i = (1), _ed_ = (m); i <= _ed_; ++i) { sbw[i].y *= -1; } work(); for (int i = (1), _ed_ = (n); i <= _ed_; ++i) { int x = rbt[i].x, y = rbt[i].y; rbt[i].x = x + y, rbt[i].y = x - y; } for (int i = (1), _ed_ = (m); i <= _ed_; ++i) { int x = sbw[i].x, y = sbw[i].y; sbw[i].x = x + y, sbw[i].y = x - y; } sort(sbw + 1, sbw + m + 1, [&](subway a, subway b) { return a.x == b.x ? a.y < b.y : a.x < b.x; }); yt = 0; for (int i = (1), _ed_ = (m); i <= _ed_; ++i) Y[++yt] = sbw[i].y; sort(Y + 1, Y + yt + 1), yt = unique(Y + 1, Y + yt + 1) - Y - 1; for (int i = (1), _ed_ = (m); i <= _ed_; ++i) insert(rt[i], rt[i - 1], 1, yt, lower_bound(Y + 1, Y + yt + 1, sbw[i].y) - Y); sort(rbt + 1, rbt + n + 1, [&](rabbit a, rabbit b) { return a.dis < b.dis; }); int l = 0, r = rbt[n].dis, ans; while (l <= r) { int mid = (l + r) >> 1; if (check(mid)) ans = mid, r = mid - 1; else l = mid + 1; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } int ans[200200], vst[200200], pos[200200], neg[200200]; set<int> s[200200]; priority_queue<pair<int, int> > q; int main() { int n, m, k, first; cin >> n >> m; for (int i = 1; i <= n; i++) { scanf( %d , &k); q.push(pair<int, int>(-k, i)); while (k--) { scanf( %d , &first); s[i].insert(first); if (first > 0) pos[first] = i; else neg[-first] = i; } } for (int i = 1; i <= m; i++) { if (!pos[i] || !neg[i]) { int u = pos[i] ? pos[i] : neg[i]; vst[u] = 1; ans[i] = (pos[i] == u); } } while (!q.empty()) { int u = q.top().second; q.pop(); if (vst[u]) continue; vst[u] = 1; if (s[u].empty()) { puts( NO ); return 0; } first = *s[u].begin(); if (first > 0) { ans[first] = 1; if (neg[first]) { s[neg[first]].erase(-first); q.push(pair<int, int>(-s[neg[first]].size(), neg[first])); } } else { first = -first; ans[first] = 0; if (pos[first]) { s[pos[first]].erase(first); q.push(pair<int, int>(-s[pos[first]].size(), pos[first])); } } } puts( YES ); for (int i = 1; i <= m; i++) putchar(ans[i] + 0 ); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:29:45 11/23/2014
// Design Name:
// Module Name: ssg_display
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ssg_display(
//input [3:0] sw,
input clk,
input greset,
output [7:0] sseg_cathode,
output [3:0] sseg_anode
);
wire dp;
//assign sseg_anode = 4'b1110;
assign dp = 1;
wire clkEnable_100Hz,clkEnable_25Hz;
clkEnable_gen #(.DES_CLOCK(250000)) Clock_100Hz (
.enable(clkEnable_100Hz),
.clock(clk),
.greset(greset));
clkEnable_gen #(.DES_CLOCK()) Clock_25Hz (
.enable(clkEnable_25Hz),
.clock(clk),
.greset(greset));
wire [15:0] BCDCount;
vCounter4DigitBCD BCDCounter_4Dig(.enable(clkEnable_25Hz),
.clk(clk),
.count(BCDCount),
.grst(greset)
);
reg [1:0] cnt;
initial cnt = 2'b0;
always @(posedge clk)
begin
if (clkEnable_100Hz)
cnt = cnt + 1;
else
cnt = cnt;
end
wire [3:0] hex_in;
assign sseg_anode = (cnt == 2'b00)? 4'b0111 : ( cnt==2'b01 )? 4'b1011:( cnt==2'b10 )?4'b1101 : 4'b1110;
assign hex_in = ( cnt == 0 )? BCDCount[15:12] : ( cnt == 1 )? BCDCount[11:8] : ( cnt == 2 )? BCDCount[7:4] : BCDCount[3:0];
hex_to_sseg hexToSSEG(
.hex(hex_in),
.dp(dp),
.sseg(sseg_cathode)
);
endmodule
|
module stack(DataIO, Reset, Push, Pop,
SP, Full, Empty, Err);
// declare input, output and inout ports
inout [3:0] DataIO;
input Push, Pop, Reset;
output Full, Empty, Err;
output [2:0] SP;
// Declare registers
reg Full, Empty, Err;
reg [2:0] SP;
reg [3:0] Stack [7:0];
reg [3:0] DataR;
//Continous assignment of DataIO to DataR register, with delay 0
wire [3:0] #(0) DataIO = DataR;
always @(posedge Push or posedge Pop or posedge Reset)
begin
if (Push == 1)
begin
//WHen the stack is empty
if (Empty == 1)
begin
Stack[SP] = DataIO;
Empty = 0;
if (Err == 1)
Err = 0;
end
else if (Full == 1) //When the stack is full
begin
Stack[SP] = DataIO;
Err = 1;
end
else
begin
SP = SP + 1;
Stack[SP] = DataIO;
if (SP == 3'b111)
Full = 1;
end
end
if (Pop == 1) //if SP indicates the last location but
begin // the stack is not empty
if ((SP == 3'b000) && (Empty != 1))
begin
DataR = Stack[SP];
Empty = 1;
end
else if (Empty == 1) //When the stack is empty
begin
DataR = Stack[SP];
Err = 1;
end
else
begin
DataR = Stack[SP];
if (SP != 3'b000)
SP = SP - 1;
//if the stack is full
if (Err == 1) Err = 0;
if (Full == 1) Full = 0;
end
end
if (Reset == 1)
begin
DataR = 4'bzzzz;
SP = 3'b0;
Full = 0;
Empty = 0;
Err = 0;
end
end
always @(negedge Pop)
begin
DataR = 4'bzzzz;
end
endmodule // stack
|
// Copyright (c) 2013, Simon Que
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
`timescale 1ns/1ps
`define BYTE_WIDTH 8 // Number of bits per byte.
module SPIBusTest;
// Main SPI interface.
reg main_nss, main_sck, main_mosi;
wire main_miso;
// Secondary SPI interface.
reg alt_nss, alt_sck, alt_mosi;
wire alt_miso;
// SPI memory bus interface.
wire mem_nss, mem_sck, mem_mosi;
reg mem_miso;
// Instantiate the Unit Under Test (UUT).
SPIBus spi_bus(main_nss, main_sck, main_mosi, main_miso,
alt_nss, alt_sck, alt_mosi, alt_miso,
mem_nss, mem_sck, mem_mosi, mem_miso);
integer stage; // Keeps track of test progress.
// Generate contents of |mem_miso| as the inverse of |mem_mosi|.
always @ (*)
mem_miso <= ~mem_mosi;
initial begin
main_nss = 0;
main_sck = 0;
main_mosi = 0;
alt_nss = 1;
alt_sck = 0;
alt_mosi = 0;
stage = 0;
#1 main_nss = 1;
#10
stage = 1;
// Perform some memory bus accesses.
#10
main_nss = 0;
main_spi_transmit(8'h01);
main_spi_transmit(8'h02);
main_spi_transmit(8'h04);
main_spi_transmit(8'h08);
main_nss = 1;
// Attempt a secondary SPI access, should go through.
#10
alt_nss = 0;
alt_spi_transmit(8'h11);
alt_spi_transmit(8'h22);
alt_spi_transmit(8'h44);
alt_spi_transmit(8'h88);
alt_nss = 1;
#10
stage = 2;
// Assert the main bus and the secondary bus at the same time. Neither
// should have nSS access, but the main bus should have SCK and MISO access.
#10
main_nss = 0;
alt_nss = 0;
main_spi_transmit(8'h01);
main_spi_transmit(8'h02);
main_spi_transmit(8'h04);
main_spi_transmit(8'h08);
alt_spi_transmit(8'h11);
alt_spi_transmit(8'h22);
alt_spi_transmit(8'h44);
alt_spi_transmit(8'h88);
main_nss = 1;
alt_nss = 1;
#10
stage = 3;
end
// Task to send a byte over primary SPI bus.
task main_spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
main_sck = 0;
#2
main_sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
main_mosi = data[`BYTE_WIDTH - 1 - i];
#1
main_sck = 1;
#1
main_sck = 0;
end
#2
main_sck = 0;
main_mosi = 0;
end
endtask
// Task to send a byte over secondary SPI bus.
task alt_spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
alt_sck = 0;
#2
alt_sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
alt_mosi = data[`BYTE_WIDTH - 1 - i];
#1
alt_sck = 1;
#1
alt_sck = 0;
end
#2
alt_sck = 0;
alt_mosi = 0;
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long N, M, K, L; cin >> N >> M >> K >> L; long long max = N / M; long long ans = 1; bool f1 = true, f2 = true, f3 = true; if (max < 1) f1 = !f1; if (max * M - K < L) f3 = !f3; if (f1 && f2 && f3) { ans = (L + K) / M + (bool)((L + K) % M); } if (f1 && f2 && f3) cout << ans << endl; else cout << -1 << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EDFXBP_1_V
`define SKY130_FD_SC_LP__EDFXBP_1_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for edfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__edfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__edfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__edfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__edfxbp_1 (
Q ,
Q_N,
CLK,
D ,
DE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__edfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EDFXBP_1_V
|
// Copyright 2012 by Alastair M. Robinson
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// A minimal implementation of the Akiko C2P register - 16-bit for now, worry about 32-bit
// width later.
//
// -- AMR --
//
// 2012-03-23 - initial version
module akiko
(
input clk,
input reset,
input [23:1] address_in,
input [15:0] data_in,
output [15:0] data_out,
input rd,
input sel_akiko // $B8xxxx
);
//0xb80038 - just the one register, but 32-bits wide.
reg [127:0] shifter;
reg [6:0] wrpointer;
wire sel;
// address decoding
assign sel = sel_akiko && address_in[7:1]==8'b0011_100; // 0x38
always @(posedge clk)
if (reset)
wrpointer <= 0;
else if (!rd && sel) // write to C2P reg...
begin
case(wrpointer)
0 : shifter[127:112] <= data_in[15:0];
1 : shifter[111:96] <= data_in[15:0];
2 : shifter[95:80] <= data_in[15:0];
3 : shifter[79:64] <= data_in[15:0];
4 : shifter[63:48] <= data_in[15:0];
5 : shifter[47:32] <= data_in[15:0];
6 : shifter[31:16] <= data_in[15:0];
7 : shifter[15:0] <= data_in[15:0];
endcase
wrpointer <= wrpointer + 1;
end
else if (rd && sel) // read from C2P reg
begin
shifter[127:0] <= {shifter[126:0],1'b0};
wrpointer <= 0;
end
assign data_out[15:0] = sel_akiko && rd ? {shifter[127],shifter[119],shifter[111],shifter[103],shifter[95],shifter[87],
shifter[79],shifter[71],shifter[63],shifter[55],shifter[47],shifter[39],shifter[31],
shifter[23],shifter[15],shifter[7]} : 16'b0 ;
endmodule
|
// MBT 11/9/2014
//
// Synchronous 1-port ram.
// Only one read or one write may be done per cycle.
//
// NOTE: Users of BaseJump STL should not instantiate this module directly
// they should use bsg_mem_1rw_sync.
`include "bsg_defines.v"
module bsg_mem_1rw_sync_synth
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter latch_last_read_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter verbose_p=1
)
(input clk_i
, input v_i
, input reset_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] data_i
, input [addr_width_lp-1:0] addr_i
, input w_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, v_i, data_i, addr_i, w_i};
assign data_o = '0;
end
else
begin: nz
logic [addr_width_lp-1:0] addr_r;
logic [width_p-1:0] mem [els_p-1:0];
logic read_en;
logic [width_p-1:0] data_out;
assign read_en = v_i & ~w_i;
assign data_out = mem[addr_r];
always_ff @ (posedge clk_i)
if (read_en)
addr_r <= addr_i;
else
addr_r <= 'X;
if (latch_last_read_p)
begin: llr
logic read_en_r;
bsg_dff #(
.width_p(1)
) read_en_dff (
.clk_i(clk_i)
,.data_i(read_en)
,.data_o(read_en_r)
);
bsg_dff_en_bypass #(
.width_p(width_p)
) dff_bypass (
.clk_i(clk_i)
,.en_i(read_en_r)
,.data_i(data_out)
,.data_o(data_o)
);
end
else
begin: no_llr
assign data_o = data_out;
end
always_ff @(posedge clk_i)
if (v_i & w_i)
mem[addr_i] <= data_i;
end // non_zero_width
// synopsys translate_off
initial
begin
if (verbose_p)
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
always_ff @(negedge clk_i)
if (v_i)
assert ( (v_i !== 1'b1) || (reset_i === 'X) || (reset_i === 1'b1) || (addr_i < els_p))
else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_i = %b)\n", addr_i, els_p, reset_i, v_i, clk_i);
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_synth)
|
#include <bits/stdc++.h> using namespace std; int main() { int T; scanf( %d , &T); while (T--) { int x, n, m; scanf( %d%d%d , &x, &n, &m); while (n-- && x >= 20) x = floor(1.0 * x / 2) + 10; while (m--) x -= 10; printf(x <= 0 ? YES n : NO n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 1000 * 101; const long long INF = 1e18; long long n, a[maxn]; vector<pair<char, long long> > ans1; vector<pair<long long, long long> > ans; queue<long long> bra; int main() { std::ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; a[0] = 0; a[n + 1] = 0; for (int i = 1; i <= n + 1; i++) { if (a[i] > a[i - 1]) { long long dis = a[i] - a[i - 1]; for (int j = 0; j < dis; j++) ans1.push_back({ ( , i}); } else if (a[i] < a[i - 1]) { long long dis = a[i - 1] - a[i]; for (int j = 0; j < dis; j++) ans1.push_back({ ) , i - 1}); } } for (int i = 0; i < ans1.size(); i++) { if (ans1[i].first == ( ) { bra.push(ans1[i].second); } else { long long x2 = bra.front(); ans.push_back({x2, ans1[i].second}); bra.pop(); } } cout << ans.size() << n ; for (int i = 0; i < ans.size(); i++) { cout << ans[i].first << << ans[i].second << n ; } return 0; }
|
/*
Module for converting input RAW data to RGB values.
The input data presents the 'Bayer patter' i.e. There are 4 different
components (G1-R-B-G2) that form a square: The upper row contains the
first green component (G1) and the red one; and the lower row contains
the blue component and the second green one (G2). However, the camera is
configured with the mirror mode (both rows and columns are mirrored) and
the previous pattern is inverted.
The output data has an RGB format. Thus, every pixel is formed by
merging the 4 components from the 'Bayer pattern' into the 3 colours
values. This implies that there will be a new valid pixel only a quarter
of the input clock pulses.
For merging the pixel array, it is necessary to buffer one entire row
and evaluate the pixels during the odd rows. This buffer is achieved
using a FIFO memory implemented at the FPGA memory blocks. The buffering
of the pixels left components is achieved storing on a register the
input values for using their content on the following cycle.
*/
module raw2rgb(
oRed,
oGreen,
oBlue,
oDVAL,
iX_Cont,
iY_Cont,
iDATA,
iDVAL,
iCLK,
iRST
);
input [10:0] iX_Cont;
input [10:0] iY_Cont;
input [11:0] iDATA;
input iDVAL;
input iCLK;
input iRST;
output [11:0] oRed;
output [11:0] oGreen;
output [11:0] oBlue;
output oDVAL;
// Module internal signals.
reg [11:0] mCCD_R;
reg [12:0] mCCD_G;
reg [11:0] mCCD_B;
reg mDVAL;
reg [11:0] upper_row_pixel;
reg [11:0] upper_row_pixel_delayed;
reg [11:0] lower_row_pixel;
reg [11:0] lower_row_pixel_delayed;
// FIFO memory control signals.
wire fifo_read_en;
wire fifo_write_en;
wire [11:0] fifo_data_out;
/*
The even rows are stored on a FIFO memory, that is implemented on the FPGA
memory blocks.
Thus, the FIFO is written while the even rows are being read from the camera,
and it is read when the odd rows are being read.
*/
onchip_fifo fifo(
.clock(iCLK),
.aclr(!iRST),
.rdreq(fifo_read_en),
.wrreq(fifo_write_en),
.data(iDATA),
.q(fifo_data_out)
);
assign fifo_write_en = iDVAL & !iY_Cont[0];
assign fifo_read_en = iDVAL & iY_Cont[0];
// Output signals assignment.
assign oRed = mCCD_R[11:0];
assign oGreen = mCCD_G[12:1];
assign oBlue = mCCD_B[11:0];
assign oDVAL = mDVAL;
// Core element of the module. Pixel conversion to RGB components.
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
mCCD_R <= 0;
mCCD_G <= 0;
mCCD_B <= 0;
upper_row_pixel_delayed <= 0;
upper_row_pixel <= 0;
lower_row_pixel_delayed <= 0;
lower_row_pixel <= 0;
mDVAL <= 0;
end
else
begin
/*
Each image pixel is composed by 4 components following a Bayer pattern.
Thus, this hardware module must store in 4 different registers the
values of each pixel components.
The components belonging to the upper row are stored on a FIFO memory.
Moreover, it is necessary to use a shift register for storing one pulse
the component values and having at the same moment the left (delayed)
components and the right (actual) components.
*/
upper_row_pixel_delayed <= upper_row_pixel;
upper_row_pixel <= fifo_data_out;
lower_row_pixel_delayed <= lower_row_pixel;
lower_row_pixel <= iDATA;
// There will only be a valid data when both the odd rows and columns
// are being read.
mDVAL <= {iY_Cont[0] & iX_Cont[0]} ? iDVAL : 1'b0;
/*
The camera is configured with the mirror mode. Thus, the pixel array
structure will be an inverted Bayer pattern, i.e. for a given pixel, the
position of its components will be:
- Blue component at the top left position
- Green1 component at the lower left position
- Green2 component at the top right position
- Red component at the lower right position
*/
if ({iY_Cont[0],iX_Cont[0]}==2'b11) begin
mCCD_R <= lower_row_pixel;
mCCD_G <= upper_row_pixel + lower_row_pixel_delayed;
mCCD_B <= upper_row_pixel_delayed;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 20, K = (1 << 16) + 5, M = 2005, mod = 998244353; int k, sum, a[N], b[N]; bitset<M> f[K]; inline void dfs(register int s, register int now) { if (!s) return; register int i; for (; now * k <= sum && f[s][now * k]; now *= k) for (i = s; i; i ^= i & -i) ++b[__builtin_ctz(i & -i)]; for (i = s; i; i ^= i & -i) if (now >= a[__builtin_ctz(i & -i)] && f[s ^ i & -i][now - a[__builtin_ctz(i & -i)]]) { dfs(s ^ i & -i, now - a[__builtin_ctz(i & -i)]); return; } } priority_queue<pair<int, int> > q; int main() { register int n, i, s, t; scanf( %d%d , &n, &k); for (i = 0; i ^ n; ++i) scanf( %d , &a[i]), sum += a[i]; t = (1 << n) - 1; f[0][0] = 1; for (s = 1; s <= t; ++s) { for (i = s; i; i ^= i & -i) f[s] |= f[s ^ i & -i] << a[__builtin_ctz(i & -i)]; for (i = sum / k; i >= 1; --i) if (f[s][i * k]) f[s][i] = 1; } if (!f[t][1]) puts( NO ); else { puts( YES ); dfs(t, 1); register pair<int, int> x1, x2; for (i = 0; i ^ n; ++i) q.push(make_pair(b[i], a[i])); while (q.size() > 1) { x1 = q.top(); q.pop(); x2 = q.top(); q.pop(); printf( %d %d n , x1.second, x2.second); x1.second += x2.second; while (x1.second % k == 0) x1.second /= k, --x1.first; q.push(x1); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; pair<double, double> za, zb, zc, zd; pair<double, double> a, b, c, d, e; pair<double, double> A, B, C, D; double cha(pair<double, double> a, pair<double, double> b, pair<double, double> c) { return (b.first - a.first) * (c.second - a.second) - (b.second - a.second) * (c.first - a.first); } pair<double, double> jiao(pair<double, double> a, pair<double, double> b, pair<double, double> c, pair<double, double> d) { double t1 = cha(a, c, b), t2 = cha(a, b, d), t3 = cha(c, a, d), t4 = cha(c, d, b); return make_pair((c.first * t2 + d.first * t1) / (t1 + t2), (c.second * t2 + d.second * t1) / (t1 + t2)); } void work(pair<double, double> a, pair<double, double> b, pair<double, double> &c, pair<double, double> &d) { c = make_pair((a.first + b.first) / 2, (a.second + b.second) / 2); d = make_pair(c.first + b.second - a.second, c.second + a.first - b.first); } bool get(pair<double, double> a, pair<double, double> b, pair<double, double> c) { work(a, b, za, zb), work(b, c, zc, zd); d = make_pair(b.first + zd.first - zc.first, b.second + zd.second - zc.second); d = jiao(b, d, za, zb); e = jiao(za, zb, zc, zd); A = make_pair(2 * d.first - e.first, 2 * d.second - e.second); B = make_pair(2 * b.first - A.first, 2 * b.second - A.second); C = make_pair(2 * c.first - B.first, 2 * c.second - B.second); D = make_pair(2 * a.first - A.first, 2 * a.second - A.second); return cha(A, B, C) * cha(B, C, D) - eps > 0 && cha(B, C, D) * cha(C, D, A) - eps > 0 && cha(C, D, A) * cha(D, A, B) - eps > 0; } int main() { int t; for (scanf( %d , &t); t--;) { scanf( %lf%lf%lf%lf%lf%lf , &a.first, &a.second, &b.first, &b.second, &c.first, &c.second); if (fabs(cha(a, b, c)) - eps < 0) { printf( NO n ); continue; } if (get(a, b, c) || get(a, c, b) || get(b, a, c)) { printf( YES n ); printf( %.9f %.9f , A.first, A.second); printf( %.9f %.9f , B.first, B.second); printf( %.9f %.9f , C.first, C.second); printf( %.9f %.9f n , D.first, D.second); } else printf( NO n ); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O21AI_FUNCTIONAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_FUNCTIONAL_PP_V
|
module dummy;
parameter [TSTBITS-1:0] // synopsys enum tstate_info
TIDLE = 3'b000,
TCN1 = 3'b001,
TCN2 = TCN1+1, // must be numbered consecutively
TCN3 = TCN2+1,
TCN4 = TCN3+1,
TCN5 = TCN4+1,
IOCLR = TCN5+1,
TUNU1 = 3'b111;
// state and output logic
always @ (`ifdef SIMFSM
ireset or
`endif
/*AUTOSENSE*/fooc2_qual or foocr_we or ioclrinst or tstate) begin
ioclrtmout = 1'b0;
case (tstate)
TIDLE: begin
if (foocr_we)
ntstate = TCN1;
else
ntstate = TIDLE;
end
TCN1,TCN2,TCN3,TCN4,TCN5: begin
if (ioclrinst | fooc2_qual)
ntstate = TIDLE;
else
ntstate = tstate + 1;
end
IOCLR: begin
ntstate = TIDLE;
ioclrtmout = 1'b1;
end
TUNU1: begin
ntstate = TIDLE;
`ifdef SIMFSM
if (~ireset)
$display("ERROR: entered unused state at %t",$time);
`endif
end
default: begin
ntstate = 'bx;
ioclrtmout = 1'bx;
`ifdef SIMFSM
if (~ireset)
$display("ERROR: entered unknown state at %t",$time);
`endif
end
endcase // case(tstate)
end // always @ (...
endmodule // dummy
|
#include <bits/stdc++.h> using namespace std; long long pi = 1, sum = 0, n, k, a[200100], pos[200100]; const long long inf = (long long)1e19; int main() { scanf( %I64d %I64d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %I64d , &a[i]); pos[i] = (a[i - 1] != 1 ? i - 1 : pos[i - 1]); } long long ans = 0; for (long long i = 1; i <= n; i++) { pi = sum = a[i]; ans += (k == 1); for (long long now = pos[i], pre = i;; pre = now, now = pos[now]) { long long mid = pi - sum * (long long)k; if (mid > 0 && mid % k == 0 && mid / k < pre - now) ans++; if (!now || inf / a[now] < pi) break; pi *= (long long)a[now]; sum += a[now] + pre - now - 1; ans += (pi == sum * (long long)k); } } printf( %I64d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111O_TB_V
`define SKY130_FD_SC_HD__A2111O_TB_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2111o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__a2111o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111O_TB_V
|
#include <bits/stdc++.h> using namespace std; long long l, r, k, x, y; int main() { scanf( %lld%lld%lld , &l, &r, &k), x = 1; if (k == 1 || l == r || (r - l == 1 && l % 2 && (l ^ r) >= l)) return printf( %lld n1 n%lld n , l, l), 0; for (int i = 0;; i++) { if (x > l) { y = i; break; } x *= 2; } if (x + x / 2 <= r && k >= 3) return printf( 0 n3 n%lld %lld %lld n , x - 1, x + x / 2, x + x / 2 - 1), 0; if (r - l == 1) return printf( %lld n2 n%lld %lld n , l ^ (l + 1), l, l + 1), 0; if (l % 2) l++; if (l + 3 <= r && k >= 4) return printf( 0 n4 n%lld %lld %lld %lld n , l, l + 1, l + 2, l + 3), 0; else return printf( 1 n2 n%lld %lld n , l, l + 1), 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long q, t, v, u, w; map<long long, long long> cost; cin >> q; while (q--) { cin >> t; if (t == 1) { cin >> v >> u >> w; while (v != u) { while (u > v) { cost[u] += w; u >>= 1; } while (v > u) { cost[v] += w; v >>= 1; } } } else { cin >> v >> u; long long res = 0; while (v != u) { while (u > v) { res += cost[u]; u >>= 1; } while (v > u) { res += cost[v]; v >>= 1; } } cout << res << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct order { int num; int pos; }; bool fun(order a, order b) { return (a.num < b.num); } int main() { int n, k, i, j; cin >> n >> k; vector<order> a(n); for (i = 0; i < n; i++) { cin >> a[i].num; a[i].pos = i + 1; } set<int> s; sort(a.begin(), a.end(), fun); i = 0; while (k - a[i].num >= 0 && i < n) { k -= a[i].num; s.insert(a[i].pos); i++; } cout << s.size() << endl; set<int>::iterator it; for (it = s.begin(); it != s.end(); it++) cout << *it << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 300000000; const int BLOCK = 100000; const int NUM = 3000; const int num[] = { 4784, 4194, 4003, 3920, 3831, 3791, 3726, 3667, 3669, 3591, 3642, 3612, 3532, 3554, 3507, 3500, 3517, 3449, 3496, 3432, 3462, 3406, 3394, 3376, 3378, 3445, 3362, 3368, 3371, 3305, 3369, 3386, 3336, 3320, 3302, 3273, 3356, 3286, 3307, 3284, 3327, 3291, 3247, 3251, 3306, 3241, 3278, 3231, 3271, 3248, 3239, 3184, 3227, 3204, 3235, 3210, 3216, 3191, 3211, 3222, 3193, 3206, 3234, 3157, 3149, 3191, 3188, 3193, 3225, 3192, 3182, 3138, 3152, 3135, 3106, 3167, 3211, 3130, 3141, 3137, 3125, 3129, 3135, 3122, 3125, 3160, 3154, 3168, 3106, 3117, 3076, 3149, 3118, 3135, 3063, 3171, 3091, 3103, 3099, 3075, 3087, 3126, 3071, 3086, 3114, 3074, 3101, 3069, 3091, 3080, 3080, 3101, 3067, 3111, 3079, 3117, 3093, 3089, 3103, 3073, 3040, 3054, 3122, 3079, 3021, 3024, 3098, 3068, 3057, 3013, 3014, 3077, 3020, 3073, 3038, 3027, 3039, 3044, 3061, 3012, 2998, 3043, 3054, 3066, 3018, 3025, 3037, 3035, 3015, 3010, 3004, 3014, 3018, 2931, 2994, 3015, 3025, 3032, 3075, 3031, 2990, 2994, 3030, 2994, 3050, 2997, 2973, 3008, 3017, 3034, 2998, 2962, 3052, 2980, 2996, 3025, 3000, 2994, 2973, 3022, 2961, 2981, 3039, 2964, 2968, 2941, 3016, 2992, 3014, 2978, 2983, 3006, 2970, 2968, 2999, 2936, 2985, 2983, 2950, 3034, 2953, 2964, 2930, 2950, 2965, 2996, 2968, 2960, 2962, 2952, 2972, 2933, 3012, 2982, 3002, 2904, 2965, 2963, 2974, 3012, 2915, 2921, 2947, 2908, 2934, 2998, 2925, 2951, 2971, 2936, 2986, 2949, 2951, 2958, 2936, 2930, 2957, 2895, 2926, 2934, 2899, 2971, 3011, 2951, 2937, 2925, 2916, 2968, 2931, 2927, 2944, 2913, 2902, 2936, 2912, 2925, 2955, 2939, 2936, 2912, 2935, 2905, 2928, 2956, 2968, 2923, 2953, 2902, 2938, 2928, 2928, 2902, 2886, 2942, 2873, 2980, 2886, 2911, 2920, 2922, 2968, 2876, 2924, 2904, 2952, 2885, 2910, 2924, 2901, 2928, 2887, 2887, 2961, 2911, 2882, 2896, 2897, 2874, 2941, 2958, 2898, 2926, 2916, 2933, 2873, 2969, 2886, 2907, 2938, 2845, 2855, 2898, 2883, 2900, 2902, 2887, 2889, 2877, 2905, 2879, 2901, 2891, 2867, 2867, 2869, 2906, 2888, 2893, 2870, 2921, 2878, 2910, 2914, 2864, 2879, 2898, 2841, 2919, 2943, 2856, 2817, 2837, 2899, 2823, 2901, 2878, 2824, 2888, 2880, 2906, 2855, 2854, 2907, 2902, 2862, 2859, 2918, 2890, 2835, 2847, 2898, 2844, 2923, 2857, 2884, 2917, 2840, 2875, 2831, 2880, 2907, 2916, 2859, 2861, 2831, 2841, 2871, 2854, 2898, 2849, 2905, 2896, 2903, 2868, 2835, 2845, 2853, 2926, 2874, 2849, 2832, 2876, 2859, 2885, 2887, 2853, 2913, 2828, 2842, 2820, 2900, 2805, 2866, 2860, 2877, 2834, 2852, 2923, 2817, 2850, 2840, 2884, 2796, 2860, 2885, 2826, 2842, 2842, 2843, 2799, 2817, 2871, 2909, 2841, 2853, 2791, 2809, 2854, 2815, 2832, 2818, 2866, 2800, 2872, 2877, 2865, 2774, 2846, 2881, 2890, 2847, 2805, 2869, 2789, 2850, 2828, 2844, 2850, 2846, 2827, 2821, 2783, 2882, 2855, 2823, 2845, 2853, 2821, 2840, 2792, 2822, 2788, 2859, 2846, 2819, 2805, 2890, 2830, 2846, 2881, 2755, 2890, 2829, 2813, 2862, 2820, 2835, 2828, 2871, 2810, 2840, 2826, 2778, 2865, 2835, 2837, 2809, 2800, 2840, 2826, 2836, 2807, 2829, 2834, 2822, 2843, 2815, 2806, 2861, 2805, 2786, 2842, 2792, 2813, 2841, 2840, 2817, 2827, 2795, 2816, 2780, 2799, 2796, 2897, 2789, 2820, 2738, 2852, 2791, 2818, 2863, 2787, 2765, 2826, 2773, 2820, 2823, 2817, 2784, 2812, 2770, 2814, 2856, 2793, 2778, 2781, 2822, 2779, 2809, 2850, 2793, 2835, 2765, 2790, 2760, 2869, 2785, 2801, 2769, 2866, 2861, 2767, 2812, 2767, 2790, 2765, 2841, 2805, 2816, 2811, 2808, 2894, 2762, 2769, 2810, 2756, 2848, 2802, 2760, 2762, 2776, 2802, 2837, 2832, 2802, 2813, 2785, 2757, 2828, 2785, 2791, 2765, 2781, 2835, 2755, 2835, 2779, 2784, 2802, 2765, 2765, 2800, 2756, 2746, 2808, 2797, 2802, 2800, 2830, 2795, 2793, 2772, 2783, 2822, 2839, 2768, 2826, 2800, 2797, 2776, 2769, 2727, 2790, 2774, 2821, 2716, 2761, 2788, 2755, 2812, 2854, 2782, 2796, 2789, 2746, 2762, 2767, 2807, 2770, 2774, 2784, 2805, 2744, 2805, 2772, 2761, 2768, 2844, 2807, 2778, 2792, 2812, 2842, 2775, 2773, 2728, 2792, 2757, 2783, 2777, 2831, 2752, 2829, 2711, 2844, 2745, 2803, 2774, 2780, 2752, 2791, 2809, 2749, 2806, 2771, 2777, 2801, 2768, 2725, 2786, 2728, 2779, 2792, 2809, 2820, 2767, 2745, 2771, 2768, 2815, 2729, 2783, 2791, 2766, 2807, 2753, 2769, 2811, 2743, 2764, 2783, 2807, 2713, 2813, 2769, 2777, 2820, 2728, 2741, 2748, 2765, 2791, 2760, 2745, 2781, 2788, 2755, 2741, 2739, 2746, 2767, 2767, 2808, 2735, 2778, 2787, 2766, 2695, 2826, 2731, 2794, 2743, 2777, 2765, 2769, 2780, 2801, 2754, 2789, 2751, 2768, 2691, 2752, 2778, 2740, 2795, 2771, 2750, 2779, 2710, 2718, 2741, 2764, 2799, 2749, 2788, 2741, 2785, 2768, 2735, 2761, 2728, 2759, 2777, 2809, 2775, 2738, 2771, 2786, 2776, 2731, 2760, 2702, 2774, 2749, 2760, 2765, 2724, 2747, 2798, 2763, 2766, 2758, 2767, 2749, 2717, 2700, 2758, 2733, 2747, 2734, 2766, 2764, 2765, 2728, 2757, 2705, 2792, 2683, 2754, 2773, 2739, 2720, 2747, 2781, 2726, 2769, 2756, 2734, 2698, 2765, 2732, 2771, 2769, 2752, 2724, 2721, 2765, 2766, 2733, 2806, 2754, 2717, 2729, 2773, 2737, 2774, 2734, 2757, 2797, 2772, 2680, 2716, 2745, 2736, 2758, 2746, 2748, 2776, 2777, 2723, 2669, 2760, 2689, 2758, 2748, 2750, 2718, 2809, 2824, 2664, 2749, 2717, 2774, 2775, 2713, 2685, 2758, 2725, 2767, 2724, 2710, 2719, 2785, 2782, 2755, 2715, 2762, 2700, 2695, 2778, 2724, 2706, 2752, 2740, 2747, 2702, 2700, 2739, 2716, 2792, 2717, 2765, 2704, 2700, 2783, 2750, 2743, 2771, 2747, 2744, 2710, 2765, 2729, 2760, 2638, 2781, 2735, 2739, 2725, 2708, 2779, 2769, 2706, 2729, 2717, 2718, 2690, 2762, 2688, 2692, 2720, 2759, 2756, 2727, 2739, 2683, 2736, 2710, 2697, 2731, 2724, 2806, 2707, 2693, 2649, 2741, 2725, 2700, 2751, 2724, 2765, 2710, 2749, 2752, 2714, 2760, 2747, 2754, 2670, 2699, 2730, 2717, 2736, 2731, 2699, 2677, 2697, 2714, 2789, 2778, 2702, 2705, 2677, 2701, 2761, 2749, 2699, 2781, 2755, 2697, 2699, 2733, 2710, 2769, 2736, 2699, 2701, 2727, 2757, 2706, 2747, 2669, 2727, 2700, 2722, 2754, 2726, 2714, 2734, 2735, 2687, 2730, 2669, 2725, 2745, 2688, 2729, 2722, 2737, 2691, 2722, 2728, 2683, 2699, 2772, 2725, 2659, 2731, 2676, 2769, 2683, 2680, 2721, 2697, 2737, 2704, 2708, 2709, 2735, 2721, 2714, 2721, 2663, 2718, 2695, 2745, 2691, 2684, 2749, 2713, 2707, 2723, 2704, 2712, 2669, 2763, 2668, 2701, 2737, 2719, 2696, 2749, 2769, 2676, 2723, 2729, 2683, 2746, 2688, 2735, 2624, 2698, 2700, 2729, 2684, 2704, 2676, 2692, 2779, 2710, 2719, 2744, 2724, 2705, 2699, 2697, 2697, 2727, 2685, 2734, 2674, 2712, 2714, 2699, 2716, 2680, 2709, 2679, 2696, 2732, 2704, 2712, 2661, 2702, 2735, 2695, 2663, 2726, 2645, 2758, 2735, 2696, 2755, 2696, 2668, 2744, 2717, 2695, 2622, 2708, 2712, 2711, 2715, 2747, 2700, 2745, 2701, 2684, 2720, 2688, 2749, 2726, 2652, 2759, 2665, 2714, 2716, 2700, 2764, 2701, 2644, 2677, 2656, 2727, 2658, 2743, 2695, 2723, 2693, 2705, 2698, 2657, 2731, 2674, 2698, 2705, 2761, 2728, 2717, 2743, 2722, 2699, 2698, 2633, 2686, 2703, 2750, 2680, 2662, 2714, 2716, 2656, 2696, 2685, 2655, 2694, 2652, 2671, 2653, 2668, 2713, 2685, 2697, 2685, 2642, 2782, 2694, 2664, 2675, 2710, 2689, 2736, 2651, 2702, 2698, 2673, 2705, 2632, 2732, 2707, 2682, 2684, 2726, 2622, 2688, 2670, 2657, 2680, 2711, 2694, 2654, 2722, 2697, 2681, 2730, 2674, 2673, 2666, 2701, 2717, 2717, 2692, 2681, 2698, 2710, 2670, 2626, 2674, 2696, 2719, 2689, 2699, 2690, 2674, 2727, 2675, 2688, 2687, 2677, 2688, 2640, 2709, 2627, 2691, 2664, 2714, 2664, 2724, 2675, 2733, 2680, 2641, 2684, 2706, 2717, 2611, 2696, 2662, 2693, 2712, 2636, 2651, 2719, 2685, 2673, 2689, 2708, 2729, 2677, 2678, 2735, 2693, 2703, 2661, 2710, 2680, 2686, 2656, 2732, 2674, 2674, 2713, 2699, 2670, 2640, 2689, 2709, 2646, 2717, 2646, 2705, 2690, 2677, 2660, 2660, 2664, 2721, 2676, 2689, 2675, 2697, 2709, 2616, 2671, 2714, 2675, 2653, 2661, 2717, 2742, 2662, 2656, 2688, 2716, 2658, 2701, 2675, 2681, 2678, 2725, 2649, 2679, 2656, 2641, 2720, 2708, 2735, 2734, 2665, 2643, 2719, 2659, 2670, 2718, 2679, 2676, 2742, 2578, 2697, 2638, 2646, 2626, 2720, 2656, 2628, 2697, 2719, 2666, 2710, 2658, 2678, 2715, 2704, 2688, 2683, 2702, 2658, 2630, 2700, 2665, 2684, 2711, 2646, 2670, 2707, 2655, 2673, 2690, 2613, 2737, 2674, 2584, 2703, 2695, 2667, 2643, 2651, 2645, 2710, 2661, 2671, 2699, 2691, 2720, 2641, 2677, 2670, 2659, 2695, 2709, 2646, 2677, 2631, 2709, 2585, 2655, 2687, 2638, 2653, 2637, 2667, 2635, 2686, 2732, 2672, 2695, 2658, 2631, 2658, 2643, 2629, 2693, 2671, 2705, 2686, 2665, 2707, 2629, 2577, 2650, 2669, 2590, 2681, 2662, 2688, 2649, 2647, 2705, 2684, 2653, 2705, 2636, 2693, 2726, 2693, 2684, 2680, 2639, 2727, 2724, 2652, 2609, 2662, 2643, 2669, 2656, 2619, 2598, 2707, 2612, 2648, 2696, 2710, 2609, 2703, 2671, 2698, 2657, 2664, 2699, 2642, 2671, 2706, 2635, 2615, 2669, 2659, 2671, 2639, 2707, 2627, 2709, 2687, 2657, 2649, 2654, 2690, 2657, 2680, 2672, 2671, 2681, 2701, 2645, 2652, 2704, 2605, 2653, 2655, 2684, 2647, 2678, 2649, 2669, 2639, 2646, 2654, 2694, 2672, 2663, 2667, 2676, 2652, 2670, 2650, 2653, 2671, 2662, 2678, 2697, 2616, 2647, 2687, 2675, 2678, 2603, 2630, 2639, 2687, 2683, 2618, 2646, 2652, 2661, 2667, 2639, 2652, 2670, 2611, 2641, 2669, 2623, 2690, 2642, 2670, 2625, 2704, 2671, 2628, 2643, 2655, 2632, 2650, 2668, 2629, 2641, 2667, 2615, 2617, 2664, 2636, 2658, 2655, 2646, 2633, 2628, 2703, 2639, 2693, 2641, 2604, 2596, 2601, 2666, 2623, 2663, 2670, 2633, 2641, 2687, 2627, 2609, 2669, 2642, 2706, 2688, 2670, 2701, 2618, 2679, 2643, 2645, 2637, 2628, 2658, 2649, 2602, 2682, 2654, 2660, 2614, 2679, 2584, 2662, 2711, 2637, 2617, 2640, 2652, 2730, 2665, 2639, 2663, 2658, 2651, 2670, 2666, 2645, 2655, 2599, 2608, 2677, 2652, 2698, 2651, 2620, 2617, 2634, 2659, 2678, 2590, 2653, 2667, 2648, 2535, 2634, 2616, 2632, 2686, 2653, 2650, 2596, 2645, 2672, 2691, 2602, 2667, 2659, 2648, 2588, 2695, 2645, 2641, 2673, 2653, 2634, 2603, 2717, 2621, 2725, 2641, 2626, 2588, 2653, 2646, 2635, 2639, 2621, 2625, 2611, 2657, 2662, 2673, 2648, 2648, 2649, 2663, 2634, 2623, 2645, 2631, 2678, 2642, 2628, 2692, 2710, 2639, 2667, 2661, 2612, 2611, 2695, 2629, 2616, 2652, 2671, 2597, 2648, 2621, 2587, 2639, 2644, 2632, 2679, 2610, 2602, 2632, 2647, 2682, 2559, 2641, 2671, 2658, 2697, 2604, 2614, 2647, 2604, 2650, 2646, 2646, 2636, 2610, 2706, 2584, 2628, 2629, 2673, 2640, 2632, 2628, 2644, 2636, 2631, 2626, 2708, 2594, 2651, 2628, 2703, 2671, 2641, 2672, 2683, 2635, 2597, 2638, 2646, 2583, 2677, 2662, 2624, 2648, 2644, 2618, 2607, 2583, 2660, 2623, 2671, 2630, 2665, 2643, 2641, 2621, 2603, 2666, 2628, 2604, 2665, 2652, 2638, 2644, 2624, 2638, 2632, 2644, 2631, 2622, 2627, 2694, 2621, 2681, 2641, 2660, 2658, 2572, 2626, 2654, 2635, 2636, 2625, 2640, 2648, 2620, 2558, 2675, 2651, 2618, 2629, 2651, 2668, 2619, 2646, 2662, 2613, 2605, 2621, 2645, 2628, 2599, 2649, 2657, 2616, 2613, 2654, 2640, 2605, 2670, 2652, 2635, 2604, 2691, 2610, 2617, 2614, 2647, 2652, 2668, 2660, 2647, 2621, 2604, 2629, 2623, 2649, 2630, 2706, 2579, 2672, 2618, 2629, 2657, 2641, 2614, 2652, 2697, 2659, 2630, 2645, 2610, 2622, 2607, 2623, 2645, 2600, 2634, 2599, 2583, 2645, 2587, 2671, 2646, 2613, 2604, 2649, 2635, 2599, 2693, 2620, 2667, 2622, 2545, 2597, 2604, 2640, 2635, 2593, 2605, 2656, 2627, 2587, 2623, 2633, 2631, 2654, 2618, 2605, 2624, 2623, 2631, 2670, 2639, 2629, 2648, 2645, 2655, 2615, 2635, 2625, 2669, 2625, 2647, 2603, 2584, 2608, 2612, 2620, 2658, 2653, 2637, 2584, 2617, 2641, 2602, 2630, 2617, 2668, 2619, 2626, 2671, 2618, 2635, 2663, 2576, 2557, 2642, 2603, 2650, 2646, 2688, 2567, 2614, 2627, 2614, 2674, 2616, 2562, 2615, 2640, 2691, 2630, 2635, 2638, 2614, 2620, 2625, 2621, 2681, 2622, 2607, 2588, 2649, 2553, 2606, 2592, 2568, 2565, 2591, 2665, 2600, 2595, 2623, 2640, 2596, 2578, 2617, 2571, 2625, 2611, 2602, 2605, 2640, 2629, 2633, 2666, 2626, 2668, 2613, 2665, 2619, 2558, 2603, 2629, 2635, 2676, 2599, 2623, 2619, 2632, 2611, 2613, 2627, 2634, 2583, 2631, 2627, 2640, 2649, 2618, 2640, 2565, 2616, 2620, 2627, 2623, 2648, 2597, 2629, 2630, 2587, 2588, 2621, 2645, 2620, 2580, 2596, 2648, 2584, 2606, 2572, 2656, 2548, 2598, 2602, 2584, 2610, 2628, 2630, 2570, 2623, 2592, 2653, 2630, 2635, 2654, 2635, 2555, 2592, 2598, 2584, 2638, 2697, 2592, 2614, 2606, 2566, 2610, 2685, 2664, 2686, 2616, 2547, 2628, 2632, 2562, 2638, 2607, 2588, 2679, 2650, 2604, 2637, 2614, 2562, 2613, 2620, 2632, 2657, 2626, 2654, 2589, 2640, 2577, 2635, 2566, 2606, 2645, 2569, 2610, 2630, 2616, 2670, 2630, 2565, 2646, 2601, 2626, 2629, 2592, 2598, 2551, 2627, 2661, 2621, 2654, 2576, 2643, 2614, 2591, 2583, 2618, 2596, 2586, 2585, 2590, 2664, 2601, 2587, 2629, 2608, 2635, 2576, 2620, 2625, 2530, 2660, 2628, 2634, 2562, 2598, 2640, 2621, 2636, 2628, 2596, 2609, 2543, 2619, 2562, 2625, 2591, 2584, 2619, 2585, 2615, 2639, 2587, 2592, 2605, 2573, 2563, 2662, 2659, 2607, 2673, 2641, 2578, 2607, 2596, 2664, 2614, 2625, 2557, 2613, 2617, 2555, 2603, 2594, 2615, 2681, 2632, 2633, 2644, 2561, 2636, 2581, 2631, 2611, 2595, 2572, 2635, 2632, 2620, 2615, 2641, 2593, 2590, 2675, 2620, 2589, 2600, 2623, 2609, 2606, 2624, 2561, 2594, 2631, 2622, 2623, 2577, 2581, 2603, 2574, 2639, 2616, 2620, 2640, 2642, 2627, 2587, 2637, 2612, 2603, 2621, 2599, 2606, 2639, 2645, 2617, 2633, 2618, 2596, 2596, 2592, 2600, 2616, 2581, 2590, 2606, 2598, 2646, 2576, 2545, 2591, 2636, 2556, 2604, 2636, 2635, 2599, 2575, 2527, 2616, 2607, 2610, 2572, 2589, 2643, 2545, 2650, 2608, 2615, 2585, 2627, 2536, 2603, 2587, 2612, 2643, 2597, 2654, 2544, 2610, 2605, 2558, 2618, 2553, 2616, 2604, 2688, 2559, 2577, 2581, 2642, 2619, 2550, 2609, 2642, 2613, 2616, 2544, 2599, 2675, 2639, 2594, 2547, 2645, 2595, 2618, 2602, 2551, 2637, 2667, 2596, 2600, 2590, 2515, 2615, 2577, 2635, 2647, 2605, 2590, 2568, 2592, 2657, 2672, 2627, 2578, 2544, 2563, 2560, 2609, 2593, 2617, 2660, 2562, 2638, 2567, 2575, 2599, 2599, 2593, 2636, 2649, 2665, 2569, 2608, 2638, 2585, 2626, 2563, 2547, 2525, 2543, 2581, 2597, 2595, 2608, 2572, 2570, 2555, 2581, 2648, 2624, 2545, 2632, 2578, 2625, 2564, 2578, 2629, 2569, 2579, 2576, 2568, 2637, 2630, 2598, 2566, 2595, 2598, 2625, 2614, 2621, 2578, 2531, 2608, 2580, 2594, 2595, 2611, 2568, 2640, 2577, 2612, 2635, 2571, 2602, 2606, 2588, 2624, 2567, 2611, 2638, 2590, 2604, 2549, 2585, 2550, 2576, 2601, 2619, 2600, 2604, 2541, 2600, 2590, 2599, 2578, 2553, 2573, 2606, 2610, 2599, 2637, 2594, 2587, 2571, 2644, 2591, 2621, 2633, 2570, 2563, 2578, 2592, 2601, 2644, 2581, 2595, 2577, 2598, 2586, 2658, 2609, 2596, 2578, 2595, 2587, 2594, 2578, 2663, 2561, 2584, 2609, 2576, 2622, 2624, 2583, 2614, 2583, 2551, 2651, 2613, 2579, 2588, 2544, 2591, 2601, 2582, 2641, 2540, 2623, 2542, 2584, 2560, 2632, 2564, 2631, 2621, 2618, 2631, 2558, 2556, 2615, 2587, 2561, 2664, 2597, 2603, 2597, 2599, 2524, 2594, 2593, 2606, 2552, 2564, 2520, 2597, 2599, 2555, 2526, 2599, 2628, 2572, 2602, 2503, 2642, 2538, 2596, 2598, 2623, 2578, 2635, 2568, 2525, 2635, 2589, 2562, 2594, 2618, 2617, 2581, 2673, 2595, 2572, 2616, 2616, 2590, 2605, 2597, 2577, 2579, 2587, 2561, 2512, 2621, 2566, 2574, 2584, 2601, 2571, 2575, 2611, 2579, 2573, 2604, 2519, 2590, 2620, 2570, 2532, 2579, 2558, 2615, 2538, 2613, 2631, 2623, 2585, 2571, 2596, 2593, 2602, 2591, 2578, 2604, 2565, 2600, 2518, 2591, 2576, 2585, 2570, 2596, 2570, 2601, 2597, 2567, 2556, 2561, 2626, 2613, 2635, 2627, 2563, 2540, 2566, 2585, 2555, 2590, 2597, 2547, 2579, 2545, 2645, 2584, 2537, 2548, 2599, 2578, 2506, 2602, 2605, 2552, 2587, 2594, 2621, 2607, 2585, 2665, 2548, 2564, 2577, 2567, 2567, 2600, 2615, 2574, 2607, 2582, 2636, 2556, 2621, 2605, 2585, 2560, 2534, 2645, 2589, 2559, 2602, 2592, 2557, 2601, 2583, 2603, 2588, 2559, 2557, 2566, 2583, 2545, 2610, 2664, 2557, 2633, 2632, 2579, 2561, 2573, 2560, 2531, 2582, 2625, 2598, 2546, 2595, 2580, 2608, 2603, 2611, 2602, 2612, 2550, 2559, 2586, 2620, 2578, 2593, 2597, 2548, 2523, 2576, 2549, 2597, 2585, 2576, 2598, 2607, 2582, 2582, 2600, 2582, 2642, 2580, 2620, 2575, 2572, 2585, 2590, 2561, 2551, 2569, 2567, 2579, 2628, 2589, 2607, 2670, 2572, 2547, 2571, 2615, 2593, 2617, 2612, 2560, 2588, 2563, 2533, 2568, 2614, 2581, 2531, 2573, 2616, 2597, 2598, 2556, 2562, 2583, 2545, 2651, 2578, 2528, 2611, 2613, 2626, 2587, 2587, 2583, 2607, 2572, 2614, 2555, 2598, 2565, 2530, 2584, 2514, 2575, 2550, 2613, 2543, 2600, 2559, 2584, 2566, 2555, 2630, 2571, 2532, 2594, 2576, 2637, 2525, 2525, 2588, 2594, 2644, 2581, 2547, 2601, 2621, 2561, 2580, 2582, 2606, 2529, 2541, 2537, 2561, 2567, 2559, 2521, 2590, 2595, 2622, 2597, 2584, 2592, 2540, 2587, 2544, 2535, 2554, 2568, 2569, 2530, 2610, 2603, 2621, 2591, 2525, 2556, 2564, 2589, 2597, 2596, 2557, 2548, 2533, 2579, 2538, 2577, 2524, 2554, 2618, 2604, 2598, 2570, 2577, 2580, 2604, 2582, 2608, 2563, 2589, 2533, 2610, 2622, 2566, 2523, 2623, 2517, 2561, 2610, 2569, 2542, 2625, 2566, 2561, 2577, 2596, 2565, 2534, 2620, 2601, 2516, 2568, 2553, 2598, 2562, 2595, 2560, 2544, 2614, 2525, 2592, 2595, 2599, 2584, 2531, 2591, 2545, 2525, 2575, 2561, 2529, 2613, 2555, 2559, 2525, 2600, 2555, 2574, 2554, 2571, 2518, 2596, 2583, 2646, 2518, 2611, 2521, 2589, 2558, 2544, 2589, 2647, 2557, 2524, 2557, 2520, 2556, 2586, 2625, 2539, 2619, 2554, 2598, 2580, 2569, 2554, 2478, 2581, 2583, 2580, 2559, 2573, 2543, 2564, 2551, 2585, 2562, 2568, 2558, 2612, 2543, 2631, 2578, 2565, 2570, 2556, 2554, 2569, 2610, 2571, 2527, 2584, 2553, 2596, 2603, 2537, 2492, 2529, 2567, 2641, 2560, 2573, 2555, 2591, 2527, 2580, 2586, 2526, 2556, 2574, 2510, 2574, 2552, 2555, 2608, 2551, 2643, 2599, 2567, 2564, 2588, 2557, 2556, 2541, 2577, 2578, 2606, 2524, 2557, 2603, 2543, 2562, 2617, 2547, 2598, 2578, 2532, 2463, 2549, 2566, 2583, 2589, 2604, 2588, 2545, 2569, 2540, 2573, 2540, 2637, 2546, 2537, 2577, 2596, 2608, 2601, 2611, 2585, 2546, 2571, 2520, 2516, 2543, 2603, 2584, 2601, 2557, 2567, 2597, 2577, 2555, 2515, 2547, 2550, 2524, 2530, 2600, 2570, 2615, 2543, 2556, 2552, 2583, 2552, 2564, 2557, 2570, 2599, 2573, 2547, 2605, 2551, 2559, 2594, 2544, 2595, 2533, 2541, 2538, 2574, 2568, 2585, 2553, 2570, 2539, 2551, 2570, 2516, 2531, 2553, 2575, 2600, 2642, 2566, 2516, 2547, 2562, 2541, 2616, 2557, 2544, 2528, 2567, 2564, 2525, 2635, 2538, 2576, 2541, 2591, 2596, 2582, 2476, 2567, 2543, 2511, 2537, 2530, 2511, 2570, 2599, 2531, 2544, 2620, 2530, 2558}; bool is_prime(int x) { if (x < 2) return 0; if (x == 2) return 1; for (int i = 2; i * i <= x; i++) { if (x % i == 0) return 0; } return 1; } int main() { int l, r, ans = 0; while (cin >> l >> r) { ans = 0; if (l <= 2 && r >= 2) ans++; if (l <= 2) { l = 3; } int L = l / BLOCK, R = r / BLOCK; if (L == R) { for (int i = l; i <= r; i++) { if ((i & 1) && i % 4 == 1 && is_prime(i)) { ans++; } } } else { for (int i = L + 1; i < R; i++) { ans += num[i]; } for (int i = l; i < (L + 1) * BLOCK; i++) { if ((i & 1) && i % 4 == 1 && is_prime(i)) { ans++; } } for (int i = R * BLOCK; i <= r; i++) { if ((i & 1) && i % 4 == 1 && is_prime(i)) { ans++; } } } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; inline int read() { static int r; static char c; r = 0, c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) r = r * 10 + (c - 0 ), c = getchar(); return r; } template <typename T> inline void print(T* a, int n) { for (int i = 1; i < n; ++i) cout << a[i] << ; cout << a[n] << endl; } const int INFI = 123456789; int n, a[300000 + 1], p[300000 + 1]; long long ans = 0LL; struct node { int m, mc, m2, m2c, d; } tree[300000 * 5]; inline node update(node l, node r) { static node ret; ret = l; ret.d = 0; if (r.m < ret.m) { ret.m2 = ret.m, ret.m2c = ret.mc; ret.m = r.m, ret.mc = r.mc; } else if (r.m == ret.m) { ret.mc += r.mc; } else if (r.m < ret.m2) { ret.m2 = r.m, ret.m2c = r.mc; } else if (r.m == ret.m2) { ret.m2c += r.mc; } if (r.m2 < ret.m2) { ret.m2 = r.m2, ret.m2c = r.m2c; } else if (r.m2 == ret.m2) { ret.m2c += r.m2c; } return ret; } inline void applyDelta(int x, int d) { tree[x].d += d, tree[x].m += d, tree[x].m2 += d; } inline void push(int x) { if (tree[x].d != 0) { applyDelta(((x) << 1), tree[x].d); applyDelta(((x) << 1 | 1), tree[x].d); tree[x].d = 0; } } void modify(int x, int l, int r, int s, int t, int v) { if (l == s && r == t) { applyDelta(x, v); return; } push(x); int mid = l + r >> 1; if (t <= mid) modify(((x) << 1), l, mid, s, t, v); else if (s > mid) modify(((x) << 1 | 1), mid + 1, r, s, t, v); else { modify(((x) << 1), l, mid, s, mid, v); modify(((x) << 1 | 1), mid + 1, r, mid + 1, t, v); } tree[x] = update(tree[((x) << 1)], tree[((x) << 1 | 1)]); } node query(int x, int l, int r, int s, int t) { if (l == s && r == t) return tree[x]; push(x); int mid = l + r >> 1; if (t <= mid) return query(((x) << 1), l, mid, s, t); else if (s > mid) return query(((x) << 1 | 1), mid + 1, r, s, t); return update(query(((x) << 1), l, mid, s, mid), query(((x) << 1 | 1), mid + 1, r, mid + 1, t)); } inline int query(int i) { static node cur; cur = query(1, 1, n, i, n); if (cur.m2 <= 2) return cur.mc + cur.m2c; if (cur.m <= 2) return cur.mc; return 0; } void build(int x, int l, int r) { if (l == r) { tree[x].m = 0, tree[x].m2 = INFI; tree[x].mc = 1, tree[x].m2c = 0; tree[x].d = 0; return; } int mid = l + r >> 1; build(((x) << 1), l, mid); build(((x) << 1 | 1), mid + 1, r); tree[x] = update(tree[((x) << 1)], tree[((x) << 1 | 1)]); } int main(int argc, char* argv[]) { n = read(); for (int i = 1; i <= n; ++i) a[i] = read(); for (int i = 1; i <= n; ++i) p[a[i]] = i; build(1, 1, n); for (int i = n; i > 0; --i) { int l = 0, r = 0; if (p[i] > 1 && a[p[i] - 1] > i) l = a[p[i] - 1]; if (p[i] < n && a[p[i] + 1] > i) r = a[p[i] + 1]; if (l > r) swap(l, r); if (l != 0) { modify(1, 1, n, r, n, -1); modify(1, 1, n, i, l - 1, 1); } else if (r != 0) { modify(1, 1, n, i, r - 1, 1); } else { modify(1, 1, n, i, n, 1); } ans += query(i); } cout << ans - n << endl; fclose(stdin); fclose(stdout); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_TB_V
/**
* udp_dff$P_pp$PKG$s: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_p_pp_pkg_s.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 SLEEP_B = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 KAPWR = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 KAPWR = 1'b0;
#260 SLEEP_B = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SLEEP_B = 1'b1;
#380 KAPWR = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SLEEP_B = 1'bx;
#480 KAPWR = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$P_pp$PKG$s dut (.D(D), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_TB_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx ) #pragma GCC optimize( unroll-loops ) using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; using vi = vector<int>; const ld PI = acos(-1); template <typename T, typename U> inline bool chmax(T &a, U b) { return a < b && (a = b, true); } template <typename T, typename U> inline bool chmin(T &a, U b) { return a > b && (a = b, true); } mt19937 rng(chrono::high_resolution_clock::now().time_since_epoch().count()); template <typename T, typename U> std::ostream &operator<<(std::ostream &stream, const pair<T, U> &p) { return stream << p.first << << p.second; } template <typename T1, typename U> istream &operator>>(istream &is, pair<T1, U> &p) { is >> p.first >> p.second; return is; } template <typename T> std::ostream &operator<<(std::ostream &out, const vector<T> &vec) { for (const T &x : vec) out << x << ; return out; } template <typename T> std::istream &operator>>(std::istream &in, vector<T> &vec) { for (auto &x : vec) in >> x; return in; } template <typename T> T gcd(T a, T b) { a = abs(a); b = abs(b); while (b != 0) { a = a % b; swap(a, b); } return a; } template <typename T> T lcm(T a, T b) { return a / gcd(a, b) * b; } template <typename T, typename U> T power(T a, T b, U mod) { T res = 1; while (b) { if (b & 1) { res = (res * a) % mod; } a = (a * a) % mod; b /= 2; } return res; } template <typename T> std::vector<T> powers(T base, int length) { std::vector<T> result(length); if (length > 0) { result[0] = 1; } for (int i = 1; i < length; i++) { result[i] = result[i - 1] * base; } return result; } bool miller_rabin(unsigned n) { if (n < 2) return false; for (unsigned p : {2, 3, 5, 7, 11, 13, 17, 19, 23, 29}) if (n % p == 0) return n == p; int r = __builtin_ctz(n - 1); unsigned d = (n - 1) >> r; for (unsigned a : {2, 7, 61}) { unsigned x = power(a % n, d, n); if (x <= 1 || x == n - 1) continue; for (int i = 0; i < r - 1 && x != n - 1; i++) x = unsigned(uint64_t(x) * x % n); if (x != n - 1) return false; } return true; } struct Sieve { int maxn; public: using MapType = unordered_map<long long, long long>; std::vector<long long> spf; std::vector<long long> primes; std::vector<long long> mobius; std::vector<bool> is_prime; explicit Sieve(int _n = 2e6 + 7) : maxn(_n + 1) { spf.resize(maxn, 1); is_prime.resize(maxn, true); primes.clear(); is_prime[0] = is_prime[1] = false; for (long long i = 2; i < maxn; ++i) { if (is_prime[i]) { primes.push_back(i); spf[i] = i; } for (long long j = 0; j < (int)primes.size() && (i * primes[j]) < maxn && primes[j] <= spf[i]; ++j) { is_prime[i * primes[j]] = false; spf[i * primes[j]] = primes[j]; } } } void genMobius() { mobius.resize(maxn, 0); mobius[1] = 1; for (long long i = 2; i < maxn; ++i) { if (spf[i / spf[i]] == spf[i]) { mobius[i] = 0; } else { mobius[i] = -mobius[i / spf[i]]; } } } long long nextPrime(long long x, bool strict = false) { auto it = upper_bound(primes.begin(), primes.end(), x); if (!strict and is_prime[x]) return x; next(it); return *it; } bool isPrime(long long num) { if (num < maxn) { return is_prime[num]; } for (long long div = 2; div * div <= num; ++div) { if (num % div == 0) return false; } return true; } long long numDivisors(long long val) { auto div = primeFactors(val); long long ans = 1; for (const auto &p : div) { ans *= p.second + 1; } return ans; } long long countDivisors(long long n) { if (n == 1) return 1; long long ans = 1; for (int i = 0;; i++) { if (primes[i] * primes[i] * primes[i] > n) break; int cnt = 1; while (n % primes[i] == 0) { n /= primes[i]; cnt++; } ans *= cnt; } if (is_prime[n]) ans = ans * 2; else if (is_prime[sqrt(n)] && (long long)sqrt(n) == sqrt(n)) ans = ans * 3; else if (n != 1) ans = ans * 4; return ans; } vector<pair<long long, long long>> divisorPair(long long x) { vector<pair<long long, long long>> res; for (long long i = 1; i * i <= x; i++) { if (x % i == 0) { if (x / i == i) { res.emplace_back(i, i); } else { res.emplace_back(i, x / i); } } } return res; } vector<long long> divisor(long long x) { vector<long long> res; for (long long i = 1; i * i <= x; i++) { if (x % i == 0) { res.push_back(i); if ((x / i) != i) { res.push_back(x / i); } } } return res; } set<long long> divisorSet(long long x) { set<long long> res; for (long long i = 1; i * i <= x; i++) { if (x % i == 0) { res.insert(i); res.insert(x / i); } } return res; } MapType primeFactors(long long val) { MapType fac; while (val > 1) { auto pf = spf[val]; if (pf == 1) break; long long cnt = 0; while (val % pf == 0) { cnt++; val /= pf; } fac[pf] = cnt; } return fac; } set<long long> divisorsBrute(long long val) { set<long long> res; for (long long i = 1; i * i <= val; i++) { if (val % i == 0) { if ((val / i) == i) { res.insert(i); } else { res.insert(i); res.insert(val / i); } } } return res; } }; Sieve sieve(sqrt(1e9 + 7)); class CPythagoreanTriples { public: bool ok(ll h, ll y) { return h >= 1 && y >= 1 && h <= 1e18 && y <= 1e18; } bool solveBase(ll n) { auto div = sieve.divisorPair(n); for (auto [a1, b1] : div) { for (auto [a2, b2] : div) { for (auto [a, b] : {make_pair(a1 * a2, b1 * b2), {a1 * b2, a2 * b1}}) { { ll h = (a + b) / 2; ll y = (b - a) / 2; if (n * n == h * h - y * y && ok(h, y)) { cout << h << << y << n ; return true; } } { ll y = (a + b) / 2; ll h = (b - a) / 2; if (n * n == h * h - y * y && ok(h, y)) { cout << h << << y << n ; return true; } } } } } return false; } bool solveHypot(ll n) { return false; } void solve() { ll n; cin >> n; if (solveBase(n)) { return; } else if (solveHypot(n)) { return; } else { cout << -1 << n ; } } }; int32_t main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); std::cout.tie(nullptr); CPythagoreanTriples solver; solver.solve(); return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate continuous <= in assignment.
//
module main;
reg globvar;
reg [3:0] var1;
reg error;
wire var2 = (var1 == 4'h02);
initial
begin
error = 0;
var1 = 4'h0 ;
#1 ;
if(var2 != 1'b0)
begin
$display("FAILED continuous <= logical op (1)");
error = 1;
end
#1 ;
var1 = 4'h2;
#1 ;
if(var2 != 1'b1)
begin
$display("FAILED continuos <= logical op (2)");
error = 1;
end
#1 ;
var1 = 4'h4;
#1 ;
if(var2 != 1'b0)
begin
$display("FAILED continuos <= logical op (3)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_PP_SYMBOL_V
`define SKY130_FD_SC_MS__XNOR3_PP_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xnor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_PP_SYMBOL_V
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// input clk is 24Mhz
`include "min_max_tracker.v"
module lf_edge_detect(input clk, input [7:0] adc_d, input [7:0] lf_ed_threshold,
output [7:0] max, output [7:0] min,
output [7:0] high_threshold, output [7:0] highz_threshold,
output [7:0] lowz_threshold, output [7:0] low_threshold,
output edge_state, output edge_toggle);
min_max_tracker tracker(clk, adc_d, lf_ed_threshold, min, max);
// auto-tune
assign high_threshold = (max + min) / 2 + (max - min) / 4;
assign highz_threshold = (max + min) / 2 + (max - min) / 8;
assign lowz_threshold = (max + min) / 2 - (max - min) / 8;
assign low_threshold = (max + min) / 2 - (max - min) / 4;
// heuristic to see if it makes sense to try to detect an edge
wire enabled =
(high_threshold > highz_threshold)
& (highz_threshold > lowz_threshold)
& (lowz_threshold > low_threshold)
& ((high_threshold - highz_threshold) > 8)
& ((highz_threshold - lowz_threshold) > 16)
& ((lowz_threshold - low_threshold) > 8);
// Toggle the output with hysteresis
// Set to high if the ADC value is above the threshold
// Set to low if the ADC value is below the threshold
reg is_high = 0;
reg is_low = 0;
reg is_zero = 0;
reg trigger_enabled = 1;
reg output_edge = 0;
reg output_state;
always @(posedge clk)
begin
is_high <= (adc_d >= high_threshold);
is_low <= (adc_d <= low_threshold);
is_zero <= ((adc_d > lowz_threshold) & (adc_d < highz_threshold));
end
// all edges detection
always @(posedge clk)
if (enabled) begin
// To enable detecting two consecutive peaks at the same level
// (low or high) we check whether or not we went back near 0 in-between.
// This extra check is necessary to prevent from noise artifacts
// around the threshold values.
if (trigger_enabled & (is_high | is_low)) begin
output_edge <= ~output_edge;
trigger_enabled <= 0;
end else
trigger_enabled <= trigger_enabled | is_zero;
end
// edge states
always @(posedge clk)
if (enabled) begin
if (is_high)
output_state <= 1'd1;
else if (is_low)
output_state <= 1'd0;
end
assign edge_state = output_state;
assign edge_toggle = output_edge;
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_slot_mgt
(
input pcie_user_clk,
input pcie_user_rst_n,
output hcmd_slot_rdy,
output [6:0] hcmd_slot_tag,
input hcmd_slot_alloc_en,
input hcmd_slot_free_en,
input [6:0] hcmd_slot_invalid_tag
);
localparam S_RESET_SEARCH_SLOT = 5'b00001;
localparam S_SEARCH_L1_SLOT = 5'b00010;
localparam S_SEARCH_L2_SLOT = 5'b00100;
localparam S_GNT_VAILD_SLOT = 5'b01000;
localparam S_VAILD_SLOT = 5'b10000;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [127:0] r_slot_valid;
reg [127:0] r_slot_search_mask;
reg [127:0] r_slot_valid_mask;
reg [6:0] r_slot_tag;
reg r_slot_rdy;
reg [15:0] r_slot_l1_valid;
wire [7:0] w_slot_l1_mask;
wire r_slot_l1_ok;
//wire [7:0] w_slot_l2_valid;
wire [127:0] w_slot_l2_mask;
wire w_slot_l2_ok;
reg r_slot_free_en;
reg [6:0] r_slot_invalid_tag;
reg [127:0] r_slot_invalid_mask;
wire [127:0] w_slot_invalid_mask;
assign hcmd_slot_rdy = r_slot_rdy;
assign hcmd_slot_tag = r_slot_tag;
assign w_slot_l1_mask = { r_slot_search_mask[95],
r_slot_search_mask[79],
r_slot_search_mask[63],
r_slot_search_mask[47],
r_slot_search_mask[31],
r_slot_search_mask[15],
r_slot_search_mask[127],
r_slot_search_mask[111]};
always @ (*)
begin
case(w_slot_l1_mask) // synthesis parallel_case full_case
8'b00000001: r_slot_l1_valid <= r_slot_valid[15:0];
8'b00000010: r_slot_l1_valid <= r_slot_valid[31:16];
8'b00000100: r_slot_l1_valid <= r_slot_valid[47:32];
8'b00001000: r_slot_l1_valid <= r_slot_valid[63:48];
8'b00010000: r_slot_l1_valid <= r_slot_valid[79:64];
8'b00100000: r_slot_l1_valid <= r_slot_valid[95:80];
8'b01000000: r_slot_l1_valid <= r_slot_valid[111:96];
8'b10000000: r_slot_l1_valid <= r_slot_valid[127:112];
endcase
end
assign r_slot_l1_ok = (r_slot_l1_valid != 16'hFFFF);
assign w_slot_l2_mask = {r_slot_search_mask[126:0], r_slot_search_mask[127]};
assign w_slot_l2_ok = ((r_slot_valid & w_slot_l2_mask) == 0);
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RESET_SEARCH_SLOT;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
next_state <= S_SEARCH_L1_SLOT;
end
S_SEARCH_L1_SLOT: begin
if(r_slot_l1_ok == 1)
next_state <= S_SEARCH_L2_SLOT;
else
next_state <= S_SEARCH_L1_SLOT;
end
S_SEARCH_L2_SLOT: begin
if(w_slot_l2_ok == 1)
next_state <= S_GNT_VAILD_SLOT;
else
next_state <= S_SEARCH_L2_SLOT;
end
S_GNT_VAILD_SLOT: begin
if(hcmd_slot_alloc_en == 1)
next_state <= S_VAILD_SLOT;
else
next_state <= S_GNT_VAILD_SLOT;
end
S_VAILD_SLOT: begin
next_state <= S_RESET_SEARCH_SLOT;
end
default: begin
next_state <= S_RESET_SEARCH_SLOT;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
r_slot_search_mask[127:112] <= 0;
r_slot_search_mask[111] <= 1'b1;
r_slot_search_mask[110:0] <= 0;
r_slot_tag <= 7'h6F;
end
S_SEARCH_L1_SLOT: begin
r_slot_search_mask[111] <= w_slot_l1_mask[7];
r_slot_search_mask[95] <= w_slot_l1_mask[6];
r_slot_search_mask[79] <= w_slot_l1_mask[5];
r_slot_search_mask[63] <= w_slot_l1_mask[4];
r_slot_search_mask[47] <= w_slot_l1_mask[3];
r_slot_search_mask[31] <= w_slot_l1_mask[2];
r_slot_search_mask[15] <= w_slot_l1_mask[1];
r_slot_search_mask[127] <= w_slot_l1_mask[0];
r_slot_tag <= r_slot_tag + 16;
end
S_SEARCH_L2_SLOT: begin
r_slot_search_mask <= w_slot_l2_mask;
r_slot_tag <= r_slot_tag + 1;
end
S_GNT_VAILD_SLOT: begin
end
S_VAILD_SLOT: begin
end
default: begin
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_slot_valid <= 0;
end
else begin
r_slot_valid <= (r_slot_valid | r_slot_valid_mask) & r_slot_invalid_mask;
//r_slot_valid <= (r_slot_valid | r_slot_valid_mask);
end
end
always @ (*)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_SEARCH_L1_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_SEARCH_L2_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_GNT_VAILD_SLOT: begin
r_slot_rdy <= 1;
r_slot_valid_mask <= 0;
end
S_VAILD_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= r_slot_search_mask;
end
default: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_slot_free_en <= hcmd_slot_free_en;
r_slot_invalid_tag <= hcmd_slot_invalid_tag;
if(r_slot_free_en == 1)
r_slot_invalid_mask <= w_slot_invalid_mask;
else
r_slot_invalid_mask <= {128{1'b1}};
end
genvar i;
generate
for(i = 0; i < 128; i = i + 1)
begin : INVALID_TAG
assign w_slot_invalid_mask[i] = (r_slot_invalid_tag != i);
end
endgenerate
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Clock Selection Logic
// File : clk_sel.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// crt_2_clk, crt_4_clk are generated from t_crt_clk.
// It also selects a clock between t_crt_clk, crt_2_clk and crt_4_clk
// based on {m_sr01_b3 , a_ar10_b6} bits and generates pclk.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module clk_sel
(
input h_reset_n,
input t_crt_clk,
input m_sr01_b3, /* Dot clock divided by 2.
* 1 -- 1/2 0 -- no division */
input a_ar10_b6, // Pixel double clock select
input final_sh_ld,
input pre_load, // unregistered version of final_sh_ld
input cclk_en, // Enable signal for cclk
output sel_sh_ld, // c_shift_ld pulse
output reg sel_sh_ld_pulse, // c_shift_ld pulse
output reg dclk_en, // dot clock
output reg pclk_en // pixel clock
);
reg [1:0] clk_sel_reg;
reg crt_2_clk_ff; // t_crt_clk div 2 sync. w.r.t final_sh_ld
reg [3:0] crt_4_clk_ff;
reg sel_sh_ld_pulse_store;
reg int_sh_ld_ff; // final_sh_ld delayed t_crt_clk
reg sh_ld_ctl_ff; // sh_ld gen. control signal
reg sel_sh_ld_reg;
wire sh_ld; // final_sh_ld the width of one t_crt_clk
wire dclk_by_2 = m_sr01_b3;
wire crt_2_clk_ff_din;
wire crt_4_clk_ff_din;
wire [1:0] clk_sel_ctl = { a_ar10_b6, dclk_by_2 } ;
// 00 -- crt_clock
// 01 -- crt_2_clk
// 10 -- crt_2_clk
// 11 -- crt_4_clk
// Dotclock (dclk) is either 1x or 0.5x of the crt clk
// The enable will be held high for 1x operation and toggled for 0.5x
// operation
always @(posedge t_crt_clk or negedge h_reset_n)
if (!h_reset_n) dclk_en <= 1'b0;
else if (dclk_by_2) dclk_en <= ~dclk_en;
else dclk_en <= 1'b1;
//Synchronous serializer shift pixel clock switch between 1X, 1/2X and 1/4X
// of crt_clk.
always @(posedge t_crt_clk)
if (~crt_2_clk_ff & ~crt_4_clk_ff[1]) clk_sel_reg <= clk_sel_ctl;
always @*
case (clk_sel_reg)
2'd0: pclk_en = 1'b1;
2'd1: pclk_en = crt_2_clk_ff;
2'd2: pclk_en = crt_2_clk_ff;
2'd3: pclk_en = crt_4_clk_ff[3];
endcase // case(clk_sel_reg)
// Generate sh_ld from final_sh_ld whose width is only one crt_clk.
always @( posedge t_crt_clk or negedge h_reset_n )
if(~h_reset_n)
int_sh_ld_ff <= 1'b0;
else
int_sh_ld_ff <= final_sh_ld;
// Sync. dclk_by_2 w.r.t falling edge of final_sh_ld
always @(posedge t_crt_clk or negedge h_reset_n)
if(~h_reset_n)
sh_ld_ctl_ff <= 1'b0;
else if (pre_load & ~final_sh_ld & cclk_en)
// This is equivalent to posedge of final_sh_ld (hopefully)
sh_ld_ctl_ff <= dclk_by_2;
assign sh_ld = sh_ld_ctl_ff ? (int_sh_ld_ff & final_sh_ld) : final_sh_ld;
// crt clock is divided by 2 to get crt_2_clk. crt_2_clk generation is sync.
// w.r.t sh_ld.
always @( posedge t_crt_clk or negedge h_reset_n )
if(~h_reset_n)
crt_2_clk_ff <= 1'b0;
else
crt_2_clk_ff <= ~crt_2_clk_ff;
// crt clock is divided by 4 to get crt_2_clk. crt_2_clk generation is sync.
// w.r.t sh_ld.
always @( posedge t_crt_clk or negedge h_reset_n )
if(~h_reset_n)
crt_4_clk_ff <= 3'b0;
else
begin
crt_4_clk_ff[0] <= ~|crt_4_clk_ff[2:0];
crt_4_clk_ff[1] <= crt_4_clk_ff[0];
crt_4_clk_ff[2] <= crt_4_clk_ff[1];
crt_4_clk_ff[3] <= crt_4_clk_ff[2];
end
always @( posedge t_crt_clk or negedge h_reset_n )
if(~h_reset_n) begin
sel_sh_ld_reg <= 1'b0;
sel_sh_ld_pulse <= 1'b0;
sel_sh_ld_pulse_store <= 1'b0;
end else begin
if (pclk_en) sel_sh_ld_reg <= 1'b0;
else if (final_sh_ld) sel_sh_ld_reg <= 1'b1;
if (final_sh_ld & ~sel_sh_ld_pulse_store) begin
sel_sh_ld_pulse_store <= 1'b1;
sel_sh_ld_pulse <= 1'b1;
end else begin
// This will hold the pulse signal until pclk_en has been generated
sel_sh_ld_pulse <= 1'b0;
if (~final_sh_ld) sel_sh_ld_pulse_store <= 1'b0;
end
end
assign sel_sh_ld = final_sh_ld | sel_sh_ld_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, count, area; cin >> a >> b; area = a * b; if (area < 2) cout << 0 << endl; else { while (area >= 2) { count++; area -= 2; } cout << count << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<unsigned long long> v; char x2[] = 47 ; do { v.push_back(stoi(x2)); } while (next_permutation(x2, x2 + 2)); char x4[] = 4477 ; do { v.push_back(stoi(x4)); } while (next_permutation(x4, x4 + 4)); char x6[] = 444777 ; do { v.push_back(stoi(x6)); } while (next_permutation(x6, x6 + 6)); char x8[] = 44447777 ; do { v.push_back(stoi(x8)); } while (next_permutation(x8, x8 + 8)); v.push_back(4444477777); sort(v.begin(), v.end()); string s; cin >> s; unsigned long long q = stoi(s); if (q <= v[0]) { cout << v[0]; return 0; } else for (int i = 0; i < v.size() - 1; i++) if (q == v[i + 1] || (q > v[i] && q < v[i + 1])) { cout << v[i + 1]; return 0; } cout << v[98]; return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:256000000 ) using namespace std; int main() { int n; cin >> n; if (n % 2 == 0) { puts( -1 ); } else { for (int(i) = 0; (i) < (n); (i)++) printf( %d , i); printf( n ); for (int(i) = 0; (i) < (n); (i)++) printf( %d , i); printf( n ); for (int(i) = 0; (i) < (n); (i)++) printf( %d , 2 * i % n); printf( n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$P_pp$PG$N (
Q ,
D ,
GATE ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; struct a1 { int value, freq; } arr[101]; bool compare(a1 lhs, a1 rhs) { return lhs.freq > rhs.freq; } int main() { int temp = 0, j, n, num = 0, m, i, a[101], ans = 0; scanf( %d %d , &n, &m); int b[n], c[n]; memset(a, 0, sizeof(a)); for (i = 0; i < n; i++) { scanf( %d , &temp); a[temp]++; } temp = 0; for (i = 1; i <= 100; i++) { if (a[i] != 0) { arr[num].freq = a[i]; arr[num++].value = i; } } sort(arr, arr + num, compare); for (i = 0; i < num; i++) { j = 0; while (j < arr[i].freq) { b[temp++] = arr[i].value; j++; } } for (i = arr[0].freq; i < n; i++) { c[i - arr[0].freq] = b[i]; } for (i = 0; i < arr[0].freq; i++) { c[n - arr[0].freq + i] = arr[0].value; } for (i = 0; i < n; i++) { if (b[i] != c[i]) ans++; } printf( %d n , ans); for (i = 0; i < n; i++) { printf( %d %d n , b[i], c[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, pos, lo, hi; while (cin >> n >> pos >> lo >> hi) { int cnt = 0; if (lo == 1 && hi == n) { cout << 0 << endl; continue; } int xlo = abs(pos - lo); int xhi = abs(pos - hi); if (lo - 1 >= 1 && hi + 1 <= n) { cnt += 2; if (xlo < xhi) { cnt += xlo; } else cnt += xhi; cnt += hi - lo; } else if (lo - 1 >= 1) { cnt += xlo; cnt++; } else { cnt += xhi; cnt++; } cout << cnt << endl; } return 0; }
|
#include <bits/stdc++.h> int main() { unsigned long long n; unsigned long long answer; scanf( %I64u , &n); if (n < 3) { printf( %lu , n); return 0; } if (n % 2 == 1) { answer = (n) * (n - 1) * (n - 2); } else if (n % 3 != 0) { answer = n * (n - 1) * (n - 3); } else { answer = (n - 1) * (n - 2) * (n - 3); } printf( %I64u n , answer); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4_SYMBOL_V
`define SKY130_FD_SC_HD__NAND4_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long INFF = 0x3f3f3f3f3f3f3f3fll; const long long M = 1e9 + 7; const long long maxn = 1e6 + 107; const double pi = acos(-1.0); const double eps = 0.0000000001; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } template <typename T> inline void pr2(T x, int k = 64) { long long i; for (i = 0; i < k; i++) fprintf(stderr, %d , (x >> i) & 1); putchar( ); } template <typename T> inline void add_(T &A, int B, long long MOD = M) { A += B; (A >= MOD) && (A -= MOD); } template <typename T> inline void mul_(T &A, long long B, long long MOD = M) { A = (A * B) % MOD; } template <typename T> inline void mod_(T &A, long long MOD = M) { A %= MOD; A += MOD; A %= MOD; } template <typename T> inline void max_(T &A, T B) { (A < B) && (A = B); } template <typename T> inline void min_(T &A, T B) { (A > B) && (A = B); } template <typename T> inline T abs(T a) { return a > 0 ? a : -a; } inline long long powMM(long long a, long long b, long long mod = M) { long long ret = 1; for (; b; b >>= 1ll, a = a * a % mod) if (b & 1) ret = ret * a % mod; return ret; } int startTime; void startTimer() { startTime = clock(); } void printTimer() { fprintf(stderr, /--- Time: %ld milliseconds ---/ n , clock() - startTime); } const int mod = 1e9 + 7; struct mint { long long x; mint() : x(0) {} mint(long long x) : x((x % mod + mod) % mod) {} mint &fix() { x = (x % mod + mod) % mod; return *this; } mint operator-() const { return mint(0) - *this; } mint operator~() const { return mint(1) / *this; } mint &operator+=(const mint &a) { if ((x += a.x) >= mod) x -= mod; return *this; } mint &operator-=(const mint &a) { if ((x += mod - a.x) >= mod) x -= mod; return *this; } mint &operator*=(const mint &a) { (x *= a.x) %= mod; return *this; } mint &operator/=(const mint &a) { (x *= a.pow(mod - 2).x) %= mod; return *this; } mint operator+(const mint &a) const { return mint(*this) += a; } mint operator-(const mint &a) const { return mint(*this) -= a; } mint operator*(const mint &a) const { return mint(*this) *= a; } mint operator/(const mint &a) const { return mint(*this) /= a; } mint pow(long long t) const { if (!t) return 1; mint res = pow(t / 2); res *= res; return (t & 1) ? res * x : res; } bool operator<(const mint &a) const { return x < a.x; } bool operator==(const mint &a) const { return x == a.x; } }; int bruteforce(string s) { set<string> S, T; S.insert( ); for (auto c : s) { for (auto str : S) { if (str.length() == 0) T.insert(str + c); else { if (c == 0 ) { T.insert(str); T.insert(str + 0 ); } if (c == 1 ) { T.insert(str + 1 ); *str.rbegin() = 1 ; T.insert(str); } } } S.swap(T); set<string>().swap(T); } printf( %d n , (int)T.size()); return T.size(); } mint val_kzero[maxn], to_next[maxn]; mint dp[maxn]; char str[maxn]; int main() { scanf( %s , str + 1); int n = strlen(str + 1), i; for (i = 1; i <= n; i++) if (str[i] == 1 ) break; if (i == n + 1) return 0 * printf( %d , n); int noww = i - 1; n -= noww; for (i = 1; i <= n; i++) str[i] = str[i + noww]; int count = 0; to_next[0] = mint(1); for (i = 1; i <= n; i++) { if (str[i] == 1 ) { count = 0; dp[i] = to_next[count]; to_next[0] = dp[i]; to_next[1] += dp[i]; } else { count++; dp[i] = to_next[count]; to_next[count] = mint(0); to_next[count + 1] += dp[i]; to_next[0] += dp[i]; } val_kzero[count] += dp[i]; } mint ans(0); for (i = 0; i <= count; i++) ans += val_kzero[i]; printf( %lld n , ans.x * (noww + 1) % M); }
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_if0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe (probe_input),
.source ()
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
iss_probe_inst.enable_metastability = "NO",
iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH,
iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0,
iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module writes data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_out_serializer (
// Inputs
clk,
reset,
transmit_data,
transmit_data_en,
// Bidirectionals
// Outputs
fifo_write_space,
serial_data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] transmit_data;
input transmit_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_write_space;
output reg serial_data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_transmitted;
wire read_fifo_en;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
wire [DW: 0] data_from_fifo;
// Internal Registers
reg transmitting_data;
reg [DW+1:0] data_out_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_write_space <= 8'h00;
else
fifo_write_space <= 8'h80 - {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
serial_data_out <= 1'b1;
else
serial_data_out <= data_out_shift_reg[0];
end
always @(posedge clk)
begin
if (reset)
transmitting_data <= 1'b0;
else if (all_bits_transmitted)
transmitting_data <= 1'b0;
else if (fifo_is_empty == 1'b0)
transmitting_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_out_shift_reg <= {(DW + 2){1'b1}};
else if (read_fifo_en)
data_out_shift_reg <= {data_from_fifo, 1'b0};
else if (shift_data_reg_en)
data_out_shift_reg <=
{1'b1, data_out_shift_reg[DW+1:1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign read_fifo_en =
~transmitting_data & ~fifo_is_empty & ~all_bits_transmitted;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_Out_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~transmitting_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (shift_data_reg_en),
.baud_clock_falling_edge (),
.all_bits_transmitted (all_bits_transmitted)
);
defparam
RS232_Out_Counters.CW = CW,
RS232_Out_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Counters.TDW = TDW;
altera_up_sync_fifo RS232_Out_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (transmit_data_en & ~fifo_is_full),
.write_data (transmit_data),
.read_en (read_fifo_en),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (data_from_fifo)
);
defparam
RS232_Out_FIFO.DW = DW,
RS232_Out_FIFO.DATA_DEPTH = 128,
RS232_Out_FIFO.AW = 6;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int a[m][n]; for (int i = 0; i < m; i++) for (int j = 0; j < n; j++) cin >> a[i][j]; int ans[n]; memset(ans, 0, sizeof(ans)); int k = 0; int x = 0, y = 0; int ma = INT_MIN; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { if (a[i][j] > ma) { x = j; ma = a[i][j]; } } ans[x]++; ma = INT_MIN; } ma = INT_MIN; for (int i = 0; i < n; i++) { if (ans[i] > ma) { x = i; ma = ans[i]; } } cout << x + 1 << endl; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:25:27 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_bram_ctrl,Vivado 2017.2" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid,
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arlen,
s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, bram_rst_a,
bram_clk_a, bram_en_a, bram_we_a, bram_addr_a, bram_wrdata_a, bram_rddata_a, bram_rst_b,
bram_clk_b, bram_en_b, bram_we_b, bram_addr_b, bram_wrdata_b, bram_rddata_b)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const long long INF = 1000000007; const long long INF2 = 1000000007LL * 1000000007LL; const long double EPS = 1e-9; const int SIZE = 1001000; int n, a, b; string fn[SIZE]; int val[SIZE], ans[SIZE]; int z[SIZE]; vector<int> g[SIZE]; void setVal(int v) { if (fn[v][0] == I ) { return; } for (auto& i : g[v]) setVal(i); if (fn[v][0] == A ) { val[v] = val[g[v][0]] && val[g[v][1]]; return; } if (fn[v][0] == O ) { val[v] = val[g[v][0]] || val[g[v][1]]; return; } if (fn[v][0] == X ) { val[v] = (val[g[v][0]] + val[g[v][1]]) % 2; return; } val[v] = !val[g[v][0]]; } void dfs(int v, int zn) { if (fn[v][0] == I ) { z[v] = zn; return; } if (zn == 0) { for (auto& i : g[v]) dfs(i, 0); return; } if (fn[v][0] == A ) { if (val[v] == 1) { for (auto& i : g[v]) dfs(i, 1); } else { if (!val[g[v][0]] && val[g[v][1]]) { dfs(g[v][0], 1); dfs(g[v][1], 0); } else if (val[g[v][0]] && !val[g[v][1]]) { dfs(g[v][0], 0); dfs(g[v][1], 1); } else { for (auto& i : g[v]) dfs(i, 0); } } return; } if (fn[v][0] == O ) { if (val[v] == 0) { for (auto& i : g[v]) dfs(i, 1); } else { if (val[g[v][0]] && val[g[v][1]]) { dfs(g[v][0], 0); dfs(g[v][1], 0); } else if (!val[g[v][0]] && val[g[v][1]]) { dfs(g[v][0], 0); dfs(g[v][1], 1); } else if (val[g[v][0]] && !val[g[v][1]]) { dfs(g[v][0], 1); dfs(g[v][1], 0); } } return; } for (auto& i : g[v]) dfs(i, zn); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; ++i) { cin >> fn[i]; if (fn[i] == IN ) { cin >> val[i]; } else if (fn[i] == NOT ) { cin >> a; --a; g[i].push_back(a); } else { cin >> a; --a; g[i].push_back(a); cin >> a; --a; g[i].push_back(a); } } setVal(0); dfs(0, 1); for (int i = 0; i < n; ++i) { if (fn[i][0] == I ) { if (z[i]) cout << !val[0]; else cout << val[0]; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; void PLAY() { cout << fixed << setprecision(10); ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int max(int a, int b) { if (a > b) return a; return b; } int min(int a, int b) { if (a < b) return a; return b; } long long fx4[] = {-1, 1, 0, 0}; long long fy4[] = {0, 0, -1, 1}; long long fx8[] = {-1, -1, -1, 0, 1, 1, 1, 0}; long long fy8[] = {-1, 0, 1, 1, 1, 0, -1, -1}; const double PI = 3.141592653589793; const long long N = 2e5 + 5; const long long mod = 1000000007; long long m, n; long long ar[N]; vector<long long> arr; long long dp[5005][5005]; long long func(long long l, long long r) { if (l == r) return 0; else if (l + 1 == r) return 1; long long &ans = dp[l][r]; if (ans != -1) return ans; ans = 0; long long op1 = INT_MAX; long long op2 = INT_MAX; long long op3 = INT_MAX; if (arr[l] == arr[r]) op1 = 1 + func(l + 1, r - 1); else { op2 = 1 + func(l, r - 1); op3 = 1 + func(l + 1, r); } ans = min(op1, min(op2, op3)); return ans; } int32_t main() { PLAY(); cin >> m; for (long long i = 0; i < m; i++) cin >> ar[i]; arr.push_back(ar[0]); for (long long i = 1; i < m;) { while (ar[i] == ar[i - 1]) i++; if (i < m) arr.push_back(ar[i]); i++; } memset(dp, -1, sizeof(dp)); n = arr.size(); cout << func(0, n - 1) << n ; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5; static int comp[maxn]; static int pr[maxn]; static int n; void make_set() { for (int i = 0; i < n; ++i) { pr[i] = i; comp[i] = 1; } } int find_set(int a) { if (pr[a] == a) return a; return pr[a] = find_set(pr[a]); } void union_set(int a, int b) { a = find_set(a); b = find_set(b); pr[a] = b; comp[b] += comp[a]; comp[a] = 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> n; int m; cin >> m; make_set(); for (int i = 0; i < m; ++i) { int a, b; cin >> a >> b; a--; b--; if (find_set(a) != find_set(b)) union_set(a, b); } int k; cin >> k; for (int j = 0; j < k; ++j) { int a, b; cin >> a >> b; a--; b--; if (find_set(a) == find_set(b)) { comp[find_set(a)] = 0; } } int mx = 0; for (int l = 0; l < n; ++l) { mx = max(mx, comp[l]); } cout << mx; }
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module RegisterFileTest;
wire [15:0] w_rf2mc_pc;
wire [ 7:0] w_rf2mc_a;
wire [ 7:0] w_rf2mc_x;
wire [ 7:0] w_rf2mc_y;
wire [ 7:0] w_rf2mc_s;
wire [ 7:0] w_rf2ec_a;
wire w_rf2ec_c;
wire w_rf2ec_d;
wire w_rf2ec_n;
wire w_rf2ec_v;
wire w_rf2ec_z;
reg clk;
reg rst_x;
reg [ 7:0] r_il2rf_data;
reg r_il2rf_set_pcl;
reg r_il2rf_set_pch;
reg r_mc2rf_fetched;
MC6502RegisterFile dut(
.clk (clk ),
.rst_x (rst_x ),
.il2rf_set_i (1'b0 ),
.il2rf_set_b (1'b0 ),
.il2rf_data (r_il2rf_data ),
.il2rf_set_pcl(r_il2rf_set_pcl),
.il2rf_set_pch(r_il2rf_set_pch),
.il2rf_pushed (1'b0 ),
.mc2rf_fetched(1'b1 ),
.mc2rf_pushed (1'b0 ),
.mc2rf_pull (1'b0 ),
.mc2rf_pc (16'h0000 ),
.mc2rf_set_pc (1'b0 ),
.mc2rf_psr (8'h00 ),
.mc2rf_set_psr(1'b0 ),
.rf2mc_pc (w_rf2mc_pc ),
.rf2mc_a (w_rf2mc_a ),
.rf2mc_x (w_rf2mc_x ),
.rf2mc_y (w_rf2mc_y ),
.rf2mc_s (w_rf2mc_s ),
.ec2rf_c (1'b0 ),
.ec2rf_set_c (1'b0 ),
.ec2rf_i (1'b0 ),
.ec2rf_set_i (1'b0 ),
.ec2rf_v (1'b0 ),
.ec2rf_set_v (1'b0 ),
.ec2rf_d (1'b0 ),
.ec2rf_set_d (1'b0 ),
.ec2rf_n (1'b0 ),
.ec2rf_set_n (1'b0 ),
.ec2rf_z (1'b0 ),
.ec2rf_set_z (1'b0 ),
.ec2rf_data (8'h00 ),
.ec2rf_set_a (1'b0 ),
.ec2rf_set_x (1'b0 ),
.ec2rf_set_y (1'b0 ),
.ec2rf_set_s (1'b0 ),
.ec2rf_set_pcl(1'b0 ),
.ec2rf_set_pch(1'b0 ),
.rf2ec_a (w_rf2ec_a ),
.rf2ec_c (w_rf2ec_c ),
.rf2ec_d (w_rf2ec_d ),
.rf2ec_n (w_rf2ec_n ),
.rf2ec_v (w_rf2ec_v ),
.rf2ec_z (w_rf2ec_z ));
always #1 clk = !clk;
always @ (posedge clk) begin
if (rst_x) begin
$display("pc = $%04x", w_rf2mc_pc);
end
end
initial begin
$dumpfile("RegisterFile.vcd");
$dumpvars(0, dut);
clk <= 1'b0;
rst_x <= 1'b0;
r_il2rf_data <= 8'h00;
r_il2rf_set_pcl <= 1'b0;
r_il2rf_set_pch <= 1'b0;
#2
rst_x <= 1'b1;
#2
r_il2rf_data <= 8'hef;
r_il2rf_set_pcl <= 1'b1;
#2
r_il2rf_data <= 8'hbe;
r_il2rf_set_pcl <= 1'b0;
r_il2rf_set_pch <= 1'b1;
#2
r_il2rf_set_pch <= 1'b0;
#4
$finish;
end
endmodule // RegisterFileTest
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } long long lcm(long long a, long long b) { long long g = gcd(a, b); long long ans = (a * b) / g; return ans; } vector<long long> primes; bool prime[10005]; void seive() { memset(prime, 1, sizeof(prime)); prime[0] = 0; prime[1] = 0; for (long long i = 2; i <= 10000; i++) { if (prime[i] == 1) { for (long long j = i * i; j <= 10000; j += i) prime[j] = 0; } } } long long power(long long a, long long b) { long long ans = 1; while (b > 0) { if (b % 2 == 1) ans = (ans % 1000000007 * a % 1000000007) % 1000000007; a = (a * a) % 1000000007; b = b / 2; } return ans; } template <typename T> std::string NumberToString(T Number) { std::ostringstream ss; ss << Number; return ss.str(); } long long gcdExtended(long long a, long long b, long long *x, long long *y); long long modInverse(long long b, long long m) { long long x, y; long long g = gcdExtended(b, m, &x, &y); if (g != 1) return -1; return (x % m + m) % m; } long long modDivide(long long a, long long b, long long m) { a = a % m; long long inv = modInverse(b, m); return (inv * a) % m; } long long gcdExtended(long long a, long long b, long long *x, long long *y) { if (a == 0) { *x = 0, *y = 1; return b; } long long x1, y1; long long gcd = gcdExtended(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; return gcd; } long long n; vector<long long> v[100005]; vector<long long> ans; void dfs(long long u, long long p) { if (v[u].size() == 1 and p != 0) { ans.push_back(u); return; } for (auto x : v[u]) { if (x != p) { dfs(x, u); } } } void solve() { cin >> n; long long i, j; for (i = 0; i < n - 1; i++) { long long x, y; cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } long long ct = 0, root = 1; for (long long i = 1; i <= n; i++) { if (v[i].size() > 2) { root = i; ct++; } } if (ct > 1) { cout << No ; return; } cout << Yes << n ; dfs(root, 0); cout << ans.size() << n ; for (i = 0; i < ans.size(); i++) { cout << root << << ans[i] << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); bool codechef = 0; long long t = 1; if (codechef) { cin >> t; } while (t--) { solve(); } return 0; }
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: acl_int_mult64s.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 174 10/17/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_mult64s_s5 (
enable,
clock,
dataa,
datab,
result);
parameter INPUT1_WIDTH = 64;
parameter INPUT2_WIDTH = 64;
input enable;
input clock;
input [INPUT1_WIDTH - 1 : 0] dataa;
input [INPUT2_WIDTH - 1 : 0] datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg [63:0] result;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH - 1 : 0] reg_dataa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH - 1 : 0] reg_datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH - 1 : 0] reg_dataa2;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH - 1 : 0] reg_datab2;
localparam TMP1_WIDTH = (INPUT1_WIDTH > 32)? INPUT1_WIDTH : 33;
localparam TMP2_WIDTH = (INPUT2_WIDTH > 32)? INPUT2_WIDTH : 33;
generate
if(INPUT1_WIDTH>=19 && INPUT1_WIDTH<=27 && INPUT2_WIDTH>=19 && INPUT2_WIDTH<=27)
begin
// Use a special WYSIWYG for the 27x27 multiplier mode
always@(posedge clock)
begin
if (enable)
begin
reg_dataa <= dataa;
reg_datab <= datab;
end
end
wire [53:0] mul_result;
wire [26:0] inp_a;
wire [26:0] inp_b;
assign inp_a = reg_dataa;
assign inp_b = reg_datab;
sv_mult27 the_multiplier(clock,enable,inp_a,inp_b,mul_result);
always@(*)
begin
result <= mul_result;
end
end
else if(INPUT1_WIDTH == 64 && INPUT2_WIDTH >= 32 || INPUT2_WIDTH == 64 && INPUT1_WIDTH >= 32) begin : GEN_LONG_MUL //Karatsuba algorithm
reg [63:0] temp0;
reg [TMP1_WIDTH-1:0] R_a;
reg [TMP2_WIDTH-1:0] R_b;
reg [31:0] temp1, temp2;
always@(posedge clock) begin
if(enable) begin
R_a <= dataa;
R_b <= datab;
temp0 <= R_a[31:0] * R_b[31:0];
temp1 <= R_a[31:0] * R_b[TMP2_WIDTH-1:32];
temp2 <= R_a[TMP1_WIDTH-1:32] * R_b[31:0];
result[63:32] <= temp0[63:32] + temp1 + temp2;
result[31:0] <= temp0[31:0];
end
end
end
else
begin
// Default LPM_MULT inference
always@(posedge clock)
begin
if (enable)
begin
result <= reg_dataa2 * reg_datab2;
reg_dataa <= dataa;
reg_datab <= datab;
reg_dataa2 <= reg_dataa;
reg_datab2 <= reg_datab;
end
end
end
endgenerate
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "3"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "64"
// Retrieval info: PRIVATE: WidthB NUMERIC "64"
// Retrieval info: PRIVATE: WidthP NUMERIC "128"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "128"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL "dataa[63..0]"
// Retrieval info: USED_PORT: datab 0 0 64 0 INPUT NODEFVAL "datab[63..0]"
// Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: CONNECT: @datab 0 0 64 0 datab 0 0 64 0
// Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
module asr(value1, value2, shift_hex, value_out, EN);
input [31:0] value1, value2;
input [3:0] shift_hex;
output [31:0] value_out;
input EN;
wire or_unary = |value2[31:5];
wire value2_shrink = value2[4:0];
wire [4:0] shift_amt = (value2_shrink== 32'b0) ?
( {1'b0, shift_hex} + 5'b1) : (value2_shrink + {1'b0, shift_hex});
assign value_out = (or_unary==1'b1) ? 32'b0 : (
(shift_amt == 5'b00000) ? value1[31:0] :
(shift_amt == 5'b00001) ? {{01{value1[31]}}, value1[31:01]} :
(shift_amt == 5'b00010) ? {{02{value1[31]}}, value1[31:02]} :
(shift_amt == 5'b00011) ? {{03{value1[31]}}, value1[31:03]} :
(shift_amt == 5'b00100) ? {{04{value1[31]}}, value1[31:04]} :
(shift_amt == 5'b00101) ? {{05{value1[31]}}, value1[31:05]} :
(shift_amt == 5'b00110) ? {{06{value1[31]}}, value1[31:06]} :
(shift_amt == 5'b00111) ? {{07{value1[31]}}, value1[31:07]} :
(shift_amt == 5'b01000) ? {{08{value1[31]}}, value1[31:08]} :
(shift_amt == 5'b01001) ? {{09{value1[31]}}, value1[31:09]} :
(shift_amt == 5'b01010) ? {{10{value1[31]}}, value1[31:10]} :
(shift_amt == 5'b01011) ? {{11{value1[31]}}, value1[31:11]} :
(shift_amt == 5'b01100) ? {{12{value1[31]}}, value1[31:12]} :
(shift_amt == 5'b01101) ? {{13{value1[31]}}, value1[31:13]} :
(shift_amt == 5'b01110) ? {{14{value1[31]}}, value1[31:14]} :
(shift_amt == 5'b01111) ? {{15{value1[31]}}, value1[31:15]} :
(shift_amt == 5'b10000) ? {{16{value1[31]}}, value1[31:16]} :
(shift_amt == 5'b10001) ? {{17{value1[31]}}, value1[31:17]} :
(shift_amt == 5'b10010) ? {{18{value1[31]}}, value1[31:18]} :
(shift_amt == 5'b10011) ? {{19{value1[31]}}, value1[31:19]} :
(shift_amt == 5'b10100) ? {{20{value1[31]}}, value1[31:20]} :
(shift_amt == 5'b10101) ? {{21{value1[31]}}, value1[31:21]} :
(shift_amt == 5'b10110) ? {{22{value1[31]}}, value1[31:22]} :
(shift_amt == 5'b10111) ? {{23{value1[31]}}, value1[31:23]} :
(shift_amt == 5'b11000) ? {{24{value1[31]}}, value1[31:24]} :
(shift_amt == 5'b11001) ? {{25{value1[31]}}, value1[31:25]} :
(shift_amt == 5'b11010) ? {{26{value1[31]}}, value1[31:26]} :
(shift_amt == 5'b11011) ? {{27{value1[31]}}, value1[31:27]} :
(shift_amt == 5'b11100) ? {{28{value1[31]}}, value1[31:28]} :
(shift_amt == 5'b11101) ? {{29{value1[31]}}, value1[31:29]} :
(shift_amt == 5'b11110) ? {{30{value1[31]}}, value1[31:30]} :
(shift_amt == 5'b11111) ? {{31{value1[31]}}, value1[31]} : 32'b0);
endmodule
|
`include "defines.v"
module ctrl(
input wire rst,
input wire[31:0] excepttype_i,
input wire[`RegBus] cp0_epc_i,
input wire stallreq_from_id,
//À´×ÔÖ´Ðн׶εÄÔÝÍ£ÇëÇó
input wire stallreq_from_ex,
input wire branch_from_id,
output reg[`RegBus] new_pc,
output reg flush,
output reg[5:0] stall
);
always @ (*) begin
if(rst == `RstEnable) begin
stall <= 6'b000000;
flush <= 1'b0;
new_pc <= `ZeroWord;
end else if(excepttype_i != `ZeroWord) begin
flush <= 1'b1;
stall <= 6'b000000;
case (excepttype_i)
32'h00000001: begin //interrupt
new_pc <= 32'h4;
end
32'h00000008: begin //syscall
new_pc <= 32'h4;
end
32'h0000000a: begin //inst_invalid
new_pc <= 32'h00000040;
end
32'h0000000d: begin //trap
new_pc <= 32'h4;
end
32'h0000000c: begin //break
new_pc <= 32'h4;
end
32'h0000000e: begin //eret
new_pc <= cp0_epc_i;
end
default : begin
end
endcase
end else if(stallreq_from_ex == `Stop) begin
stall <= 6'b001111;
flush <= 1'b0;
end else if(stallreq_from_id == `Stop) begin
stall <= 6'b000111;
flush <= 1'b0;
end else if(branch_from_id == `Branch) begin
stall <= 6'b000010;
flush <= 1'b0;
end else begin
stall <= 6'b000000;
flush <= 1'b0;
new_pc <= `ZeroWord;
end //if
end //always
endmodule
|
// mbt 11-10-14
//
// bsg_two_buncher
//
// see also serial_in_parallel_out
//
// this module takes an incoming stream of words.
// if the output is read every cycle, the data passes
// straight through without latency. if the output
// is not read, then one element is buffered internally
// and either one or two elements may be pulled out
// on the next cycle. this is useful for when we want to
// process two words at a time.
//
// is this what they call a gearbox?
//
// note that the interface has double ready lines
// and it is an error to assert ready_i[1] without
// asserting ready_i[0]
//
//
`include "bsg_defines.v"
module bsg_two_buncher #(parameter `BSG_INV_PARAM(width_p))
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
, output ready_o
, output [width_p*2-1:0] data_o
, output [1:0] v_o
, input [1:0] ready_i
);
logic [width_p-1:0] data_r, data_n;
logic data_v_r, data_v_n, data_en;
// synopsys translate_off
always @(posedge clk_i)
assert ( (ready_i[1] !== 1'b1) | ready_i[0])
else $error("potentially invalid ready pattern\n");
always @(posedge clk_i)
assert ( (v_o[1] !== 1'b1) | v_o[0])
else $error("invalide valid output pattern\n");
// synopsys translate_on
always_ff @(posedge clk_i)
if (reset_i)
data_v_r <= 0;
else
data_v_r <= data_v_n;
always_ff @(posedge clk_i)
if (data_en)
data_r <= data_i;
assign v_o = { data_v_r & v_i, data_v_r | v_i };
assign data_o = { data_i, data_v_r ? data_r : data_i };
// we will absorb outside data if the downstream channel is ready
// and we move forward on at least one elements
// or, if we are empty
assign ready_o = (ready_i[0] & v_i) | ~data_v_r;
// determine if we will latch data next cycle
always_comb
begin
data_v_n = data_v_r;
data_en = 1'b0;
// if we are empty
if (~data_v_r)
begin
// and there is new data that we don't forward
// we grab it
if (v_i)
begin
data_v_n = ~ready_i[0];
data_en = ~ready_i[0];
end
end
// or if we are not empty
else
begin
// if we are going to send data
if (ready_i[0])
begin
// but there is new data
// and we are not going to
// send it too
if (v_i)
begin
data_v_n = ~ready_i[1];
data_en = ~ready_i[1];
end
else
// oops, we send the new data too
data_v_n = 1'b0;
end
end
end
endmodule // bsg_two_buncher
`BSG_ABSTRACT_MODULE(bsg_two_buncher)
|
/////////////////////////////////////////////////////////////////////
// This file is part of the GOST 28147-89 CryptoCore project //
// //
// Copyright (c) 2016 Dmitry Murzinov () //
/////////////////////////////////////////////////////////////////////
module sbox_ram (
input wire CLK, // Clock
input wire CEN, // ChipEnable
input wire WEN, // Write (otherwise read)
input wire INIT, // 0 - normal mode, 1 - loading S-box
input wire [31:0] SA, // SBox Individual Addresses
input wire [3:0] CA, // Common Address for All rams
input wire [31:0] SI, // Data Input
output reg [31:0] SO // Data output
);
///////////////////////////////////////////////////
wire [3:0] AMUX [7:0]; // for address multiplexer
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin: sbox_ram
ram16x4bit
sbox_ram_u0
(.CLK(CLK ),
.CEN(CEN ),
.WEN(WEN ),
.A( AMUX[i] ),
.D( SI[i*4+3:i*4]),
.Q( SO[i*4+3:i*4])
);
assign AMUX[i] = INIT ? CA : SA[i*4+3:i*4];
end
endgenerate
endmodule
//EOF
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int nax = 1e6 + 10; vector<int> tree(4 * nax); long long i, j, x, y, k; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n, t; cin >> t; while (t--) { cin >> n; vector<long long> a; set<long long> b; for (i = 0; i < n; i++) { cin >> x; a.push_back(x); b.insert(x); } if (b.size() == 1) { cout << 1 << endl; for (i = 0; i < n; i++) cout << 1 << ; } else if (a.size() % 2 == 0) { cout << 2 << endl; for (i = 0; i < n / 2; i++) cout << 1 << << 2 << ; } else if (a.size() % 2 != 0) { vector<long long> ans; int p = 0, q = 0; ans.push_back(1); for (i = 1; i < a.size() - 1; i++) { if (a[i] == a[i - 1] && p == 0) { ans.push_back(ans[i - 1]); p = 1; } else if (q == 0) { ans.push_back(2); q = 1; } else if (q == 1) { ans.push_back(1); q = 0; } } if (p == 1) { if (q == 1) ans.push_back(1); else ans.push_back(2); } else { if (a[n - 1] == a[n - 2]) ans.push_back(ans[n - 2]); else if (a[n - 1] == a[0]) ans.push_back(ans[0]); else ans.push_back(3); } if (ans[n - 1] == 3) cout << 3 << endl; else cout << 2 << endl; for (i = 0; i < ans.size(); i++) cout << ans[i] << ; } cout << endl; } }
|
// dig
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
`include "cog.v" // cog logic and memory (8 instances)
`include "hub.v" // hub logic and memory
module dig
(
input nres, // reset input (active low)
output [7:0] cfg, // configuration output (set by clkset instruction)
input clk_cog, // cog clock input
input clk_pll, // pll simulator clock input (2x cog clock)
input [31:0] pin_in, // pin state inputs
output [31:0] pin_out, // pin state outputs
output [31:0] pin_dir, // pin direction outputs
output [7:0] cog_led // led outputs to show which cogs are active
);
parameter INVERT_COG_LEDS = 0;
// cnt
reg [31:0] cnt;
always @(posedge clk_cog)
if (nres)
cnt <= cnt + 1'b1;
// bus enable
reg ena_bus;
always @(posedge clk_cog or negedge nres)
if (!nres)
ena_bus <= 1'b0;
else
ena_bus <= !ena_bus;
// bus select
reg [7:0] bus_sel;
always @(posedge clk_cog or negedge nres)
if (!nres)
bus_sel <= 8'b0;
else if (ena_bus)
bus_sel <= {bus_sel[6:0], ~|bus_sel[6:0]};
// cogs
wire [7:0] bus_r;
wire [7:0] bus_e;
wire [7:0] bus_w;
wire [7:0] [1:0] bus_s;
wire [7:0] [15:0] bus_a;
wire [7:0] [31:0] bus_d;
wire [7:0] pll;
wire [7:0] [31:0] outx;
wire [7:0] [31:0] dirx;
genvar i;
generate
for (i=0; i<8; i++)
begin : coggen
cog cog_( .nres (nres),
.clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena_bus (ena_bus),
.ptr_w (ptr_w[i]),
.ptr_d (ptr_d),
.ena (cog_ena[i]),
.bus_sel (bus_sel[i]),
.bus_r (bus_r[i]),
.bus_e (bus_e[i]),
.bus_w (bus_w[i]),
.bus_s (bus_s[i]),
.bus_a (bus_a[i]),
.bus_d (bus_d[i]),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack[i]),
.cnt (cnt),
.pll_in (pll),
.pll_out (pll[i]),
.pin_in (pin_in),
.pin_out (outx[i]),
.pin_dir (dirx[i]) );
end
endgenerate
// hub
wire hub_bus_r = |bus_r;
wire hub_bus_e = |bus_e;
wire hub_bus_w = |bus_w;
wire [1:0] hub_bus_s = bus_s[7] | bus_s[6] | bus_s[5] | bus_s[4] | bus_s[3] | bus_s[2] | bus_s[1] | bus_s[0];
wire [15:0] hub_bus_a = bus_a[7] | bus_a[6] | bus_a[5] | bus_a[4] | bus_a[3] | bus_a[2] | bus_a[1] | bus_a[0];
wire [31:0] hub_bus_d = bus_d[7] | bus_d[6] | bus_d[5] | bus_d[4] | bus_d[3] | bus_d[2] | bus_d[1] | bus_d[0];
wire [31:0] bus_q;
wire bus_c;
wire [7:0] bus_ack;
wire [7:0] cog_ena;
wire [7:0] ptr_w;
wire [27:0] ptr_d;
hub hub_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.nres (nres),
.bus_sel (bus_sel),
.bus_r (hub_bus_r),
.bus_e (hub_bus_e),
.bus_w (hub_bus_w),
.bus_s (hub_bus_s),
.bus_a (hub_bus_a),
.bus_d (hub_bus_d),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack),
.cog_ena (cog_ena),
.ptr_w (ptr_w),
.ptr_d (ptr_d),
.cfg (cfg) );
// pins
assign pin_out = outx[7] | outx[6] | outx[5] | outx[4] | outx[3] | outx[2] | outx[1] | outx[0];
assign pin_dir = dirx[7] | dirx[6] | dirx[5] | dirx[4] | dirx[3] | dirx[2] | dirx[1] | dirx[0];
// cog leds
assign cog_led = cog_ena ^ { 8{|INVERT_COG_LEDS} };
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic 32x32 multiplier ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Generic 32x32 multiplier with pipeline stages. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_gmultp2_32x32.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.2 2002/07/31 02:04:35 lampret
// MAC now follows software convention (signed multiply instead of unsigned).
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.4 2001/12/04 05:02:35 lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.3 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.2 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
// 32x32 multiplier, no input/output registers
// Registers inside Wallace trees every 8 full adder levels,
// with first pipeline after level 4
`ifdef OR1200_GENERIC_MULTP2_32X32
`define OR1200_W 32
`define OR1200_WW 64
module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P );
input [`OR1200_W-1:0] X;
input [`OR1200_W-1:0] Y;
input CLK;
input RST;
output [`OR1200_WW-1:0] P;
reg [`OR1200_WW-1:0] p0;
reg [`OR1200_WW-1:0] p1;
integer xi;
integer yi;
//
// Conversion unsigned to signed
//
always @(X)
xi <= X;
//
// Conversion unsigned to signed
//
always @(Y)
yi <= Y;
//
// First multiply stage
//
always @(posedge CLK or posedge RST)
if (RST)
p0 <= `OR1200_WW'b0;
else
p0 <= #1 xi * yi;
//
// Second multiply stage
//
always @(posedge CLK or posedge RST)
if (RST)
p1 <= `OR1200_WW'b0;
else
p1 <= #1 p0;
assign P = p1;
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int aa[105][105]; pair<int, int> pos[105][105]; int main() { int n, m, q; scanf( %d %d %d , &n, &m, &q); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { pos[i][j] = {i, j}; aa[i][j] = INT_MAX; } } for (int l = 1; l <= q; ++l) { int a; scanf( %d , &a); if (a == 3) { int r, c, x; scanf( %d %d %d , &r, &c, &x); aa[pos[r][c].first][pos[r][c].second] = x; } else { int x; scanf( %d , &x); if (a == 1) { pair<int, int> temp = pos[x][1]; for (int i = 1; i <= m; ++i) { pos[x][i] = pos[x][i + 1]; } pos[x][m] = temp; } else { pair<int, int> temp = pos[1][x]; for (int i = 1; i <= n; ++i) { pos[i][x] = pos[i + 1][x]; } pos[n][x] = temp; } } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (aa[i][j] == INT_MAX) { printf( 1 ); } else { printf( %d , aa[i][j]); } } printf( n ); } }
|
#include <bits/stdc++.h> const int MAXN = 1e5 + 5; const long long MOD = 998244353; const int INF = 0x3f3f3f3f; const long long LL_INF = 0x3f3f3f3f3f3f3f3f; const double PI = acos(-1); const double ERR = 1e-10; const int L = 40; const int M = 30; using namespace std; long long mx = -1e18; long long mn = 1e18; int main() { ios_base::sync_with_stdio(NULL); cin.tie(NULL); cout.tie(NULL); long long a, b[MAXN], c = 0; cin >> a; if (a == 1) { cout << 0 ; return 0; } for (int i = 0; i < a; i++) { cin >> b[i]; } sort(b, b + a); for (int i = 0; i < a; i++) { c += b[a - 1] - b[i]; } cout << c; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct edge { edge(int to, int back, int orient = 0) : to(to), back(back), orient(orient) {} int to; int back; int orient; }; class Tarjan { public: vector<vector<int> > adj; vector<int> comp; int nb_cfc; private: vector<int> index; vector<int> lowlink; stack<int> s; int id; void tarjan(int i) { int j, k; index[i] = id; lowlink[i] = id; ++id; s.push(i); for (k = 0; k < (int)adj[i].size(); ++k) { j = adj[i][k]; if (index[j] == -1) tarjan(j); if (comp[j] == -1) lowlink[i] = min(lowlink[i], lowlink[j]); } if (lowlink[i] == index[i]) { do { j = s.top(); s.pop(); comp[j] = nb_cfc; } while (i != j); ++nb_cfc; } } public: void cfc() { id = 0; nb_cfc = 0; comp.clear(); index.clear(); lowlink.clear(); comp.resize(adj.size(), -1); index.resize(adj.size(), -1); lowlink.resize(adj.size(), -1); for (int i = 0; i < (int)adj.size(); ++i) { if (index[i] == -1) tarjan(i); } } }; void dfs(vector<vector<edge> > &graph, vector<bool> &mark, int x) { if (mark[x]) return; mark[x] = true; for (int i = 0; i < (graph[x].size()); ++i) { int y = graph[x][i].to; if (graph[x][i].orient == 0) { int j = graph[x][i].back; graph[x][i].orient = 1; graph[y][j].orient = -1; dfs(graph, mark, y); } } } int main(void) { int n, m; cin >> n >> m; vector<vector<edge> > graph(n); for (int i = 0; i < (m); ++i) { int x, y; cin >> x >> y; --x, --y; int u = graph[x].size(); int v = graph[y].size(); graph[x].push_back(edge(y, v)); graph[y].push_back(edge(x, u)); } vector<bool> mark(n, false); dfs(graph, mark, 0); Tarjan g; g.adj.assign(n, vector<int>()); for (int x = 0; x < (n); ++x) for (int i = 0; i < (graph[x].size()); ++i) { int y = graph[x][i].to; if (graph[x][i].orient > 0) g.adj[x].push_back(y); } g.cfc(); if (g.nb_cfc > 1) cout << 0 << endl; else { for (int i = 0; i < (n); ++i) for (int j = 0; j < (graph[i].size()); ++j) { int x = i, y = graph[i][j].to; if (y < x) continue; if (graph[i][j].orient < 0) swap(x, y); ++x, ++y; cout << x << << y << endl; } } return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 8762 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4096,
w4095,
w256,
w4351,
w32,
w4383,
w2,
w4381,
w8762;
assign w1 = i_data0;
assign w2 = w1 << 1;
assign w256 = w1 << 8;
assign w32 = w1 << 5;
assign w4095 = w4096 - w1;
assign w4096 = w1 << 12;
assign w4351 = w4095 + w256;
assign w4381 = w4383 - w2;
assign w4383 = w4351 + w32;
assign w8762 = w4381 << 1;
assign o_data0 = w8762;
//multiplier_block area estimate = 7012.05118019853;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_frame_counter.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU frame counter sub-block.
***************************************************************************************************/
module apu_frame_counter
(
input clk_in, // system clock signal
input rst_in, // reset signal
input cpu_cycle_pulse_in, // 1 clk pulse on every cpu cycle
input apu_cycle_pulse_in, // 1 clk pulse on every apu cycle
input [1:0] mode_in, // mode ([0] = IRQ inhibit, [1] = sequence mode)
input mode_wr_in, // update mode
output reg e_pulse_out, // envelope and linear counter pulse (~240 Hz)
output reg l_pulse_out, // length counter and sweep pulse (~120 Hz)
output reg f_pulse_out // frame pulse (~60Hz, should drive IRQ)
);
reg [14:0] q_apu_cycle_cnt, d_apu_cycle_cnt;
reg q_seq_mode, d_seq_mode;
reg q_irq_inhibit, d_irq_inhibit;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_apu_cycle_cnt <= 15'h0000;
q_seq_mode <= 1'b0;
q_irq_inhibit <= 1'b0;
end
else
begin
q_apu_cycle_cnt <= d_apu_cycle_cnt;
q_seq_mode <= d_seq_mode;
q_irq_inhibit <= d_irq_inhibit;
end
end
always @*
begin
d_apu_cycle_cnt = q_apu_cycle_cnt;
d_seq_mode = (mode_wr_in) ? mode_in[1] : q_seq_mode;
d_irq_inhibit = (mode_wr_in) ? mode_in[0] : q_irq_inhibit;
e_pulse_out = 1'b0;
l_pulse_out = 1'b0;
f_pulse_out = 1'b0;
if (apu_cycle_pulse_in)
begin
d_apu_cycle_cnt = q_apu_cycle_cnt + 15'h0001;
if ((q_apu_cycle_cnt == 15'h0E90) || (q_apu_cycle_cnt == 15'h2BB1))
begin
e_pulse_out = 1'b1;
end
else if (q_apu_cycle_cnt == 15'h1D20)
begin
e_pulse_out = 1'b1;
l_pulse_out = 1'b1;
end
else if (!q_seq_mode && (q_apu_cycle_cnt == 15'h3A42))
begin
e_pulse_out = 1'b1;
l_pulse_out = 1'b1;
f_pulse_out = ~q_irq_inhibit;
d_apu_cycle_cnt = 15'h0000;
end
else if ((q_apu_cycle_cnt == 15'h48d0))
begin
e_pulse_out = q_seq_mode;
l_pulse_out = q_seq_mode;
d_apu_cycle_cnt = 15'h0000;
end
end
if (cpu_cycle_pulse_in && mode_wr_in)
d_apu_cycle_cnt = 15'h48d0;
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s1_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
soc_system_cpu_s1_jtag_debug_module_tck the_soc_system_cpu_s1_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
soc_system_cpu_s1_jtag_debug_module_sysclk the_soc_system_cpu_s1_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic soc_system_cpu_s1_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam soc_system_cpu_s1_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// soc_system_cpu_s1_jtag_debug_module_phy.sld_instance_index = 0,
// soc_system_cpu_s1_jtag_debug_module_phy.sld_ir_width = 2,
// soc_system_cpu_s1_jtag_debug_module_phy.sld_mfg_id = 70,
// soc_system_cpu_s1_jtag_debug_module_phy.sld_sim_action = "",
// soc_system_cpu_s1_jtag_debug_module_phy.sld_sim_n_scan = 0,
// soc_system_cpu_s1_jtag_debug_module_phy.sld_sim_total_length = 0,
// soc_system_cpu_s1_jtag_debug_module_phy.sld_type_id = 34,
// soc_system_cpu_s1_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
// Driver for WS2812 LED strips.
// Serializes data to an LED strip.
// Copyright (c) 2013 Jared Boone, ShareBrained Technology, Inc.
//
// This file is part of the Medusa project.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
module ws2812
#(parameter LED_COUNT, parameter REVERSE)
(
input rst_i,
input clk_i,
output [8:0] address_o,
input [7:0] r_i,
input [7:0] g_i,
input [7:0] b_i,
output data_o
);
/* WS2812 data sheet:
* T0H + T0L = 350 ns + 800 ns = 1.15 us
* T1H + T1L = 700 ns + 600 ns = 1.3 us
* Treset = >50 us
*/
parameter CYCLES_0_HIGH = 21; // 0.42 us @ 50MHz
parameter CYCLES_1_HIGH = 42; // 0.84 us @ 50MHz
parameter CYCLES_BIT = 63; // 1.26 us @ 50MHz
parameter CYCLES_RESET = 2600; // 52.00 us @ 50MHz
parameter STATE_PIXEL = 0,
STATE_SYNC = 1;
reg [1:0] state;
parameter SYMBOL_0 = 0,
SYMBOL_1 = 1,
SYMBOL_RESET = 2;
wire [1:0] symbol;
reg [11:0] symbol_phase;
reg [11:0] symbol_duration;
reg [11:0] symbol_high_time;
always @(symbol) begin
case(symbol)
SYMBOL_0: symbol_high_time = CYCLES_0_HIGH;
SYMBOL_1: symbol_high_time = CYCLES_1_HIGH;
default: symbol_high_time = 0;
endcase
end
always @(symbol) begin
case(symbol)
SYMBOL_0: symbol_duration = CYCLES_BIT;
SYMBOL_1: symbol_duration = CYCLES_BIT;
default: symbol_duration = CYCLES_RESET;
endcase
end
reg symbol_out;
assign data_o = symbol_out;
wire symbol_end = (symbol_phase == (symbol_duration - 1));
always @(posedge clk_i) begin
if (rst_i) begin
symbol_phase <= 0;
symbol_out <= 0;
end
else begin
symbol_out <= (symbol_phase < symbol_high_time);
if (symbol_end)
symbol_phase <= 0;
else
symbol_phase <= symbol_phase + 1;
end
end
reg [4:0] symbol_count;
wire pixel_end = (symbol_count == 23) && symbol_end;
wire [23:0] led_data = { g_i[7:0], r_i[7:0], b_i[7:0] };
always @(posedge clk_i) begin
if (rst_i)
symbol_count <= 0;
else begin
if (symbol_end)
if (pixel_end)
symbol_count <= 0;
else
if (state == STATE_PIXEL)
symbol_count <= symbol_count + 1;
end
end
reg [8:0] pixel_count;
wire frame_end = (pixel_count == (LED_COUNT - 1)) && pixel_end;
assign symbol = (state == STATE_PIXEL) ? led_data[23 - symbol_count] : SYMBOL_RESET;
always @(posedge clk_i) begin
if (rst_i) begin
state <= STATE_SYNC;
pixel_count <= 0;
end
else begin
case(state)
STATE_PIXEL: begin
if (pixel_end) begin
if (frame_end) begin
state <= STATE_SYNC;
pixel_count <= 0;
end
else begin
state <= STATE_PIXEL;
pixel_count <= pixel_count + 1;
end
end
else begin
state <= STATE_PIXEL;
pixel_count <= pixel_count;
end
end
default: begin
if (symbol_end) begin
state <= STATE_PIXEL;
pixel_count <= 0;
end
else begin
state <= STATE_SYNC;
pixel_count <= 0;
end
end
endcase
end
end
assign address_o = REVERSE ? pixel_count : (LED_COUNT - 1 - pixel_count);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: oq_header_parser.v
// Project: NF2.1
// Description: finds the destination port in the module headers and puts it in fifo
//
///////////////////////////////////////////////////////////////////////////////
module oq_header_parser
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter OP_LUT_STAGE_NUM = 4,
parameter IOQ_STAGE_NUM = `IO_QUEUE_STAGE_NUM,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter MAX_PKT = 2048, // allow for 2K bytes
parameter PKT_BYTE_CNT_WIDTH = log2(MAX_PKT),
parameter PKT_WORD_CNT_WIDTH = log2(MAX_PKT/CTRL_WIDTH)
)
(
parsed_dst_oq,
parsed_pkt_byte_len,
parsed_pkt_word_len,
header_parser_rdy,
dst_oq_avail,
rd_dst_oq,
in_wr,
in_ctrl,
in_data,
clk,
reset
);
output [NUM_OQ_WIDTH-1:0] parsed_dst_oq;
output [PKT_BYTE_CNT_WIDTH-1:0] parsed_pkt_byte_len;
output [PKT_WORD_CNT_WIDTH-1:0] parsed_pkt_word_len;
output header_parser_rdy;
output dst_oq_avail;
input rd_dst_oq;
input in_wr;
input [CTRL_WIDTH-1:0] in_ctrl;
input [DATA_WIDTH-1:0] in_data;
input clk;
input reset;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//------------------- Internal parameters -----------------
parameter NUM_INPUT_STATES = 3;
parameter IN_WAIT_DST_PORT_LENGTH = 1;
parameter IN_WAIT_PKT_DATA = 2;
parameter IN_WAIT_EOP = 4;
//---------------------- Regs/Wires -----------------------
reg [NUM_INPUT_STATES-1:0] input_state;
reg [NUM_INPUT_STATES-1:0] input_state_next;
reg [NUM_OQ_WIDTH-1:0] dst_oq_encoded;
wire [PKT_BYTE_CNT_WIDTH-1:0]pkt_byte_len;
wire [PKT_WORD_CNT_WIDTH-1:0]pkt_word_len;
reg wr_en;
wire empty;
wire full;
//----------------------- Module --------------------------
fallthrough_small_fifo
#(
.WIDTH(NUM_OQ_WIDTH + PKT_BYTE_CNT_WIDTH + PKT_WORD_CNT_WIDTH)
)
dst_oq_fifo
(
.din ({pkt_word_len, pkt_byte_len, dst_oq_encoded}), // Data in
.wr_en (wr_en), // Write enable
.rd_en (rd_dst_oq), // Read the next word
.dout ({parsed_pkt_word_len, parsed_pkt_byte_len, parsed_dst_oq}),
.full (full),
.prog_full (),
.nearly_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------ Logic --------------------------
assign header_parser_rdy = !full;
assign dst_oq_avail = !empty;
/*********************************************************
* As data comes in, look for the dst port and queue it
*********************************************************/
always @(*) begin
wr_en = 0;
input_state_next = input_state;
case(input_state)
IN_WAIT_DST_PORT_LENGTH: begin
if(in_wr && in_ctrl==IOQ_STAGE_NUM) begin
wr_en = 1;
input_state_next = IN_WAIT_PKT_DATA;
end
end // case: IP_WAIT_DST_PORT
IN_WAIT_PKT_DATA: begin
if(in_wr && in_ctrl==0) begin
input_state_next = IN_WAIT_EOP;
end
end
IN_WAIT_EOP: begin
if(in_wr && in_ctrl != 0) begin
input_state_next = IN_WAIT_DST_PORT_LENGTH;
end
end
endcase // case(input_process_state)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
input_state <= IN_WAIT_DST_PORT_LENGTH;
end
else begin
input_state <= input_state_next;
end
// synthesis translate_off
if(in_wr && in_ctrl==0 && input_state==IN_WAIT_DST_PORT_LENGTH) begin
$display("%t %m **** ERROR: Did not find dst port", $time);
$stop;
end
// synthesis translate_on
end
/*
* get the binary form of the destination port
*/
always @(*) begin
dst_oq_encoded = 'h0;
case(in_data[`IOQ_DST_PORT_POS + NUM_OUTPUT_QUEUES - 1:`IOQ_DST_PORT_POS])
'h0: dst_oq_encoded = 'h0;
'h1: dst_oq_encoded = 'h0;
'h2: dst_oq_encoded = 'h1;
'h4: dst_oq_encoded = 'h2;
'h8: dst_oq_encoded = 'h3;
'h10: dst_oq_encoded = 'h4;
'h20: dst_oq_encoded = 'h5;
'h40: dst_oq_encoded = 'h6;
'h80: dst_oq_encoded = 'h7;
'h100: dst_oq_encoded = 'h8;
'h200: dst_oq_encoded = 'h9;
'h400: dst_oq_encoded = 'ha;
'h800: dst_oq_encoded = 'hb;
'h1000: dst_oq_encoded = 'hc;
'h2000: dst_oq_encoded = 'hd;
'h4000: dst_oq_encoded = 'he;
'h8000: dst_oq_encoded = 'hf;
endcase // case(in_data[NUM_OQ_WIDTH-1:0])
end
assign pkt_byte_len = in_data[`IOQ_BYTE_LEN_POS + PKT_BYTE_CNT_WIDTH-1:`IOQ_BYTE_LEN_POS];
assign pkt_word_len = in_data[`IOQ_WORD_LEN_POS + PKT_WORD_CNT_WIDTH-1:`IOQ_WORD_LEN_POS];
endmodule // header_parser
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title :
//
// File : alt_ddrx_bank_timer_info.v
//
// Abstract :
///////////////////////////////////////////////////////////////////////////////
module alt_ddrx_bank_timer_info #
( parameter
ACT_TO_RDWR_WIDTH = 0, // these parameters need to be set for this module to work correctly
ACT_TO_ACT_WIDTH = 0, // these parameters need to be set for this module to work correctly
ACT_TO_PCH_WIDTH = 0, // these parameters need to be set for this module to work correctly
RD_TO_PCH_WIDTH = 0, // these parameters need to be set for this module to work correctly
WR_TO_PCH_WIDTH = 0, // these parameters need to be set for this module to work correctly
RD_AP_TO_ACT_WIDTH = 0, // these parameters need to be set for this module to work correctly
WR_AP_TO_ACT_WIDTH = 0, // these parameters need to be set for this module to work correctly
PCH_TO_ACT_WIDTH = 0, // these parameters need to be set for this module to work correctly
BANK_TIMER_COUNTER_OFFSET = 3,
MEM_IF_ROW_WIDTH = 16,
CLOSE_PAGE_POLICY = 1
)
(
ctl_clk,
ctl_reset_n,
// timing information
act_to_rdwr,
act_to_act,
act_to_pch,
rd_to_pch,
wr_to_pch,
rd_ap_to_act,
wr_ap_to_act,
pch_to_act,
less_than_x2_act_to_rdwr,
// inputs
open,
close,
read,
write,
row_addr,
// outputs
current_state,
current_row,
rdwr_ready,
act_ready,
pch_ready
);
input ctl_clk;
input ctl_reset_n;
// timing information
input [ACT_TO_RDWR_WIDTH - 1 : 0] act_to_rdwr;
input [ACT_TO_ACT_WIDTH - 1 : 0] act_to_act;
input [ACT_TO_PCH_WIDTH - 1 : 0] act_to_pch;
input [RD_TO_PCH_WIDTH - 1 : 0] rd_to_pch;
input [WR_TO_PCH_WIDTH - 1 : 0] wr_to_pch;
input [RD_AP_TO_ACT_WIDTH - 1 : 0] rd_ap_to_act;
input [WR_AP_TO_ACT_WIDTH - 1 : 0] wr_ap_to_act;
input [PCH_TO_ACT_WIDTH - 1 : 0] pch_to_act;
input less_than_x2_act_to_rdwr;
// inputs
input open;
input close;
input read;
input write;
input [MEM_IF_ROW_WIDTH - 1 : 0] row_addr;
// outputs
output current_state; // 0/1 represents IDLE/ACTIVE state
output [MEM_IF_ROW_WIDTH - 1 : 0] current_row;
output rdwr_ready;
output act_ready;
output pch_ready;
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[START] Registers & Wires
------------------------------------------------------------------------------*/
localparam ACT_COUNTER_WIDTH = ACT_TO_ACT_WIDTH; // similar to act_to_act width
localparam GENERAL_COUNTER_WIDTH = 6; // 0 - 63, should be enough for all timing values
reg current_state;
reg [MEM_IF_ROW_WIDTH - 1 : 0] current_row;
reg rdwr_ready;
reg act_ready;
reg pch_ready;
reg doing_read;
reg doing_auto_precharge;
reg doing_precharge;
reg int_act_to_act_ready;
reg int_act_to_pch_ready;
reg int_rdwr_to_valid_ready;
reg [ACT_COUNTER_WIDTH - 1 : 0] act_counter;
reg [GENERAL_COUNTER_WIDTH - 1 : 0] general_counter;
/*------------------------------------------------------------------------------
[END] Registers & Wires
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
/*------------------------------------------------------------------------------
[START] General Logics
------------------------------------------------------------------------------*/
// General counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_counter <= 0;
end
else
begin
if (open)
act_counter <= BANK_TIMER_COUNTER_OFFSET;
else if (act_counter != {ACT_COUNTER_WIDTH{1'b1}})
act_counter <= act_counter + 1'b1;
end
end
// Read write counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
general_counter <= 0;
end
else
begin
if (read || write || close)
general_counter <= BANK_TIMER_COUNTER_OFFSET;
else if (general_counter != {GENERAL_COUNTER_WIDTH{1'b1}})
general_counter <= general_counter + 1'b1;
end
end
// keep track of read/write command
// '1' during read
// '0' during write
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
doing_read <= 1'b0;
else
begin
if (write)
doing_read <= 1'b0;
else if (read)
doing_read <= 1'b1;
end
end
// keep track of precharge command
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_auto_precharge <= 1'b0;
doing_precharge <= 1'b0;
end
else
begin
if (close)
begin
if (read || write)
begin
doing_auto_precharge <= 1'b1;
doing_precharge <= 1'b0;
end
else
begin
doing_auto_precharge <= 1'b0;
doing_precharge <= 1'b1;
end
end
else if (open)
begin
doing_auto_precharge <= 1'b0;
doing_precharge <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
Bank Status
------------------------------------------------------------------------------*/
// Store current state, 0 for IDLE and 1 for ACTIVE
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
current_state <= 1'b0;
end
else
begin
if (open)
current_state <= 1'b1;
else if (close)
current_state <= 1'b0;
end
end
/*------------------------------------------------------------------------------
ACT to RD/WR (tRCD)
------------------------------------------------------------------------------*/
// keep track of tRCD
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_ready <= 1'b0;
end
else
begin
if (close)
rdwr_ready <= 1'b0;
else if (open && less_than_x2_act_to_rdwr)
rdwr_ready <= 1'b1;
else if (current_state && act_counter >= act_to_rdwr) // only enable after page opened
rdwr_ready <= 1'b1;
else
rdwr_ready <= 1'b0;
end
end
/*------------------------------------------------------------------------------
ACT to ACT (tRC)
------------------------------------------------------------------------------*/
// keep track of tRC
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_act_to_act_ready <= 1'b1;
end
else
begin
if (open) // immediately de-assert act_ready after an activate is issued to a bank
int_act_to_act_ready <= 1'b0;
else if (act_counter >= act_to_act)
int_act_to_act_ready <= 1'b1;
else
int_act_to_act_ready <= 1'b0;
end
end
/*------------------------------------------------------------------------------
RD/WR(AP) to VALID
------------------------------------------------------------------------------*/
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_rdwr_to_valid_ready <= 1'b0;
end
else
begin
if (close)
int_rdwr_to_valid_ready <= 1'b0; // deassert immediately after close signal detected
else
begin
if (doing_precharge && general_counter >= pch_to_act) // PCH to ACT
int_rdwr_to_valid_ready <= 1'b1;
else if (!doing_precharge)
begin
if (!doing_read && doing_auto_precharge && general_counter >= wr_ap_to_act) // WRAP to ACT
int_rdwr_to_valid_ready <= 1'b1;
else if ( doing_read && doing_auto_precharge && general_counter >= rd_ap_to_act) // RDAP to ACT
int_rdwr_to_valid_ready <= 1'b1;
else if (!doing_read && !doing_auto_precharge && general_counter >= wr_to_pch) // WR to PCH
int_rdwr_to_valid_ready <= 1'b1;
else if ( doing_read && !doing_auto_precharge && general_counter >= rd_to_pch) // RD to PCH
int_rdwr_to_valid_ready <= 1'b1;
else
int_rdwr_to_valid_ready <= 1'b0;
end
else
int_rdwr_to_valid_ready <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
ACT to PCH (tRAS)
------------------------------------------------------------------------------*/
// keep track of tRAS
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_act_to_pch_ready <= 1'b0;
end
else
begin
if (open) // immediately de-assert pch_ready after an activate is issued to a bank
int_act_to_pch_ready <= 1'b0;
else if (act_counter >= act_to_pch)
int_act_to_pch_ready <= 1'b1;
else
int_act_to_pch_ready <= 1'b0;
end
end
/*------------------------------------------------------------------------------
ACT/PCH Ready
------------------------------------------------------------------------------*/
always @ (*)
begin
act_ready = int_act_to_act_ready & int_rdwr_to_valid_ready;
end
always @ (*)
begin
pch_ready = int_act_to_pch_ready & int_rdwr_to_valid_ready;
end
/*------------------------------------------------------------------------------
[END] General Logics
------------------------------------------------------------------------------*/
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
// OPP /*------------------------------------------------------------------------------
// OPP
// OPP [START] Open Page Policy Logics
// OPP
// OPP ------------------------------------------------------------------------------*/
// OPP generate
// OPP if (!CLOSE_PAGE_POLICY) // only enable during open page policy
// OPP begin
// OPP // Store row information
// OPP always @ (posedge ctl_clk or negedge ctl_reset_n)
// OPP begin
// OPP if (!ctl_reset_n)
// OPP begin
// OPP current_row <= 0;
// OPP end
// OPP else
// OPP begin
// OPP // update when there is an activate
// OPP if (open)
// OPP current_row <= row_addr;
// OPP end
// OPP end
// OPP end
// OPP endgenerate
// OPP /*------------------------------------------------------------------------------
// OPP
// OPP [END] Open Page Policy Logics
// OPP
// OPP ------------------------------------------------------------------------------*/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31A_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O31A_BEHAVIORAL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
// Local signals
wire B1 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31A_BEHAVIORAL_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2 * (100000) + 5; int a[MAXN], b[MAXN]; int main() { int n; cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) cin >> b[i]; int res = 0; int j = 0; for (int i = 0; i < n && j < n; ++i) { while (j < n && a[i] != b[j]) { j++; res++; } j++; } cout << res << endl; return 0; }
|
#include <bits/stdc++.h> long long mpow(long long a, long long n, long long mod) { long long ret = 1; long long b = a; while (n) { if (n & 1) ret = (ret * b) % mod; b = (b * b) % mod; n >>= 1; } return (long long)ret; } using namespace std; int n, m, s; pair<int, int> bug[(int)(1e5 + 25)]; int ANS[(int)(1e5 + 25)]; pair<pair<int, int>, int> ch[(int)(1e5 + 25)]; bool chk(int x) { priority_queue<pair<int, int> > pq; long long ans = 0; int last = m; for (int i = n; i >= 1;) { int j = i; while (j > 0 && ch[j].first.first >= bug[last].first) { pq.push(make_pair(-ch[j].first.second, ch[j].second)); j--; } i = j; if (j == 0) { break; } if (pq.empty()) { return 0; } pair<int, int> temp = pq.top(); pq.pop(); int dum = x; ans += (-temp.first); while (last > 0 && dum > 0) { ANS[bug[last].second] = temp.second; dum--; last--; } if (last <= 0) { break; } } while (last > 0) { if (pq.empty()) { return 0; } pair<int, int> temp = pq.top(); pq.pop(); int dum = x; ans += (-temp.first); while (last > 0 && dum > 0) { ANS[bug[last].second] = temp.second; dum--; last--; } } return (ans <= s); } void solve() { scanf( %d , &n); scanf( %d , &m); scanf( %d , &s); for (int i = 1; i <= m; i++) { scanf( %d , &bug[i].first); bug[i].second = i; } for (int i = 1; i <= n; i++) { scanf( %d , &ch[i].first.first); } for (int i = 1; i <= n; i++) { scanf( %d , &ch[i].first.second); ch[i].second = i; } sort(bug + 1, bug + m + 1); sort(ch + 1, ch + n + 1); int lo = 1, hi = m; while (lo < hi) { int mid = (lo + hi) >> 1; if (chk(mid)) { hi = mid; } else { lo = mid + 1; } } if (!chk(lo)) { printf( NO ); return; } printf( YES n ); for (int i = 1; i <= m; i++) { cout << ANS[i] << ; } } int main() { int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; }
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
//////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: tb_top_nto1_pll.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: June 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: Test Bench
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
//
//////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1ps
module tb_top_nto1_pll () ;
reg reset ;
reg reset2 ;
reg match ;
reg match2 ;
reg clk ;
wire refclk_n ;
reg refclk_p ;
wire clkout_p ;
wire clkout_n ;
wire clkout ;
wire [5:0] dataout_p ;
wire [5:0] dataout_n ;
wire [41:0] dummy_out ;
reg [41:0] old ;
wire [41:0] dummy_out2 ;
reg [41:0] old2 ;
wire clkout2_p ;
wire clkout2_n ;
wire [5:0] dataout2_p ;
wire [5:0] dataout2_n ;
initial refclk_p = 0 ;
initial clk = 0 ;
always #(1000) refclk_p = ~refclk_p ;
always #(4000) clk = ~clk ;
assign refclk_n = ~refclk_p ;
initial
begin
reset = 1'b1 ;
reset2 = 1'b0 ;
#150000
reset = 1'b0;
#300000
reset2 = 1'b1 ;
end
always @ (posedge refclk_p) // Check data
begin
old <= dummy_out ;
if (dummy_out[41:0] == {old[40:0], old[41]}) begin
match <= 1'b1 ;
end
else begin
match <= 1'b0 ;
end
end
always @ (posedge refclk_p) // Check data
begin
old2 <= dummy_out2 ;
if (dummy_out2[41:0] == {old2[40:0], old2[41]}) begin
match2 <= 1'b1 ;
end
else begin
match2 <= 1'b0 ;
end
end
top_nto1_pll_diff_tx diff_tx (
.refclkin_p (refclk_p),
.refclkin_n (refclk_n),
.dataout_p (dataout_p),
.dataout_n (dataout_n),
.clkout_p (clkout_p),
.clkout_n (clkout_n),
.reset (reset)) ;
top_nto1_pll_diff_rx diff_rx (
.clkin_p (clkout_p),
.clkin_n (clkout_n),
.datain_p (dataout_p),
.datain_n (dataout_n),
.reset (reset),
.dummy_out (dummy_out)) ;
top_nto1_pll_diff_rx_and_tx diff_rx_and_tx (
.clkin_p (clkout_p),
.clkin_n (clkout_n),
.datain_p (dataout_p),
.datain_n (dataout_n),
.reset (reset),
.dataout_p (dataout2_p),
.dataout_n (dataout2_n),
.clkout_p (clkout2_p),
.clkout_n (clkout2_n)) ;
top_nto1_pll_diff_rx diff_rx2 (
.clkin_p (clkout2_p),
.clkin_n (clkout2_n),
.datain_p (dataout2_p),
.datain_n (dataout2_n),
.reset (reset),
.dummy_out (dummy_out2)) ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND2B_PP_BLACKBOX_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, n1, output = 0; cin >> n; if (n % 2 == 0) cout << n / 2 - 1; else cout << n / 2; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int a, b; cin >> a >> b; a--; string l = to_string(a); string r = to_string(b); long long int ans1; if (l.length() == 1) { ans1 = a; } else { if (l[0] <= l[(l.length() - 1)]) { ans1 = (a / 10) + 9; } else { ans1 = (a / 10) + 8; } } long long int ans2; if (r.length() == 1) { ans2 = b; } else { if (r[0] <= r[(r.length() - 1)]) { ans2 = (b / 10) + 9; } else { ans2 = (b / 10) + 8; } } cout << ans2 - ans1 << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_1_V
`define SKY130_FD_SC_HD__O221AI_1_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221ai_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_1_V
|
//-----------------------------------------------------
// This is my second Verilog Design
// Design Name : first_counter
// File Name : first_counter.v
// Function : This is a 4 bit up-counter with
// Synchronous active high reset and
// with active high enable signal
//-----------------------------------------------------
module first_counter (
clock , // Clock input of the design
reset , // active high, synchronous Reset input
enable , // Active high enable signal for counter
counter_out // 4 bit vector output of the counter
); // End of port list
//-------------Input Ports-----------------------------
input clock ;
input reset ;
input enable ;
//-------------Output Ports----------------------------
output [3:0] counter_out ;
//-------------Input ports Data Type-------------------
// By rule all the input ports should be wires
wire clock ;
wire reset ;
wire enable ;
//-------------Output Ports Data Type------------------
// Output port can be a storage element (reg) or a wire
reg [3:0] counter_out ;
//------------Code Starts Here-------------------------
// Since this counter is a positive edge trigged one,
// We trigger the below block with respect to positive
// edge of the clock.
always @ (posedge clock)
begin : COUNTER // Block Name
// At every rising edge of clock we check if reset is active
// If active, we load the counter output with 4'b0000
if (reset == 1'b1) begin
counter_out <= 4'b0000;
end
// If enable is active, then we increment the counter
else if (enable == 1'b1) begin
counter_out <= counter_out + 1;
end
end // End of Block COUNTER
endmodule // End of Module counter
|
#include <bits/stdc++.h> using namespace std; int n, m, i, j, k, l, art[505][505], low[505][505], used[505][505], ans, cn, t, x, y, z, mx, mn, s, timer, vis[505][505]; char c[505][505], d[1000009], ch; void dfs(int row, int col) { timer++; used[row][col] = 1; if ((row - 1 >= 0) && (used[row - 1][col] == 0) && (timer < s) && (c[row - 1][col] == . )) { dfs(row - 1, col); } if ((col - 1 >= 0) && (used[row][col - 1] == 0) && (timer < s) && (c[row][col - 1] == . )) { dfs(row, col - 1); } if ((row + 1 < n) && (used[row + 1][col] == 0) && (timer < s) && (c[row + 1][col] == . )) { dfs(row + 1, col); } if ((col + 1 < m) && (used[row][col + 1] == 0) && (timer < s) && (c[row][col + 1] == . )) { dfs(row, col + 1); } } int main() { while (scanf( %d %d %d , &n, &m, &k) != EOF) { x = y = s = 0; timer = 1; for (i = 0; i < n; i++) { scanf( %s , c[i]); for (j = 0; j < m; j++) { if (c[i][j] == . ) { s++; x = i; y = j; } } } s -= k; memset(used, 0, sizeof(used)); timer = 0; dfs(x, y); for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if ((used[i][j] == 0) && (c[i][j] == . )) { k--; printf( X ); } else { printf( %c , c[i][j]); } } printf( n ); } } return 0; }
|
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