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#include <bits/stdc++.h> using namespace std; struct data1 { long long sum, index, position; }; bool comp(data1 a, data1 b) { return a.sum < b.sum; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); long long k; cin >> k; vector<data1> arr; long long sz = 0; for (long long i = 0; i < k; i++) { long long n; cin >> n; std::vector<long long> v(n); for (auto &x : v) cin >> x; long long sum = accumulate(v.begin(), v.end(), 0ll); for (long long j = 0; j < n; j++) { data1 d; d.sum = sum - v[j]; d.index = i; d.position = j; arr.push_back(d); sz++; } } sort(arr.begin(), arr.end(), &comp); bool flag = false; for (long long i = 0; i < sz - 1; i++) { if (arr[i].sum == arr[i + 1].sum and arr[i].index != arr[i + 1].index) { cout << YES n ; cout << arr[i].index + 1 << << arr[i].position + 1 << n ; cout << arr[i + 1].index + 1 << << arr[i + 1].position + 1 << n ; flag = true; break; } } if (flag) return 0; cout << NO n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; string s; cin >> n >> s; int ans = 15; for (int i = 0; i < n; i++) { if (s[i] == 0 ) ans &= 8; if (s[i] == 1 || s[i] == 2 || s[i] == 3 ) ans &= 7; if (s[i] == 1 || s[i] == 4 || s[i] == 7 ) ans &= 13; if (s[i] == 3 || s[i] == 6 || s[i] == 9 ) ans &= 14; if (s[i] == 7 || s[i] == 9 ) ans &= 11; } if (ans) cout << NO ; else cout << YES ; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CLKINVLP_FUNCTIONAL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_FUNCTIONAL_V
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#include <bits/stdc++.h> const int maxn = 5205; using namespace std; int n, a[maxn][maxn], m; int cnt, sum[maxn][maxn], x[maxn]; bool check(int x) { int now; for (int i = x; i <= n; i += x) { for (int j = x; j <= n; j += x) { now = sum[i][j] - sum[i - x][j] - sum[i][j - x] + sum[i - x][j - x]; if (now == 0 || now == x * x) continue; else return 0; } } return 1; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n / 4; j++) { scanf( %1x , &m); cnt = 0; while (m) { a[i][j * 4 - cnt++] = (m % 2); m >>= 1; } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { sum[i][j] = sum[i - 1][j] + sum[i][j - 1] - sum[i - 1][j - 1] + a[i][j]; } } cnt = 0; for (int i = 1; i <= n; i++) { if (n % i == 0) { x[++cnt] = i; } } for (int k = cnt; k >= 1; k--) { if (check(x[k])) { printf( %d n , x[k]); break; } } }
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#include <bits/stdc++.h> int main() { double y1, y2, yw, xb, yb, r, A, B, C; scanf( %lf%lf%lf%lf%lf%lf , &y1, &y2, &yw, &xb, &yb, &r); yw -= r; y1 += r; yb = 2 * yw - yb; A = y1 - yb; B = xb; C = -B * y1 + B * y2; if ((C / sqrt(A * A + B * B)) <= r) { printf( -1 ); return 0; } C = -B * y1; printf( %.10lf , (-C - B * yw) / A); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 51, MOD = 1e9 + 7; struct Matrix { int num[6][6]; Matrix() { memset(num, 0, sizeof(num)); } inline int* operator[](const int& x) { return num[x]; } inline const int* operator[](const int& x) const { return num[x]; } }; Matrix mat, mat2, x, x2; int f1, f2, f3, c, res; long long int n; inline long long int read() { register long long int num = 0, neg = 1; register char ch = getchar(); while (!isdigit(ch) && ch != - ) { ch = getchar(); } if (ch == - ) { neg = -1; ch = getchar(); } while (isdigit(ch)) { num = (num << 3) + (num << 1) + (ch - 0 ); ch = getchar(); } return num * neg; } inline int qpow(int base, int exponent) { int res = 1; while (exponent) { if (exponent & 1) { res = (long long int)res * base % MOD; } base = (long long int)base * base % MOD, exponent >>= 1; } return res; } inline Matrix operator*(Matrix x, Matrix y) { Matrix res; for (register int i = 1; i <= 5; i++) { for (register int j = 1; j <= 5; j++) { for (register int k = 1; k <= 5; k++) { res[i][j] = (res[i][j] + (long long int)x[i][k] * y[k][j] % (MOD - 1)) % (MOD - 1); } } } return res; } inline Matrix qpow(Matrix base, long long int exponent) { Matrix res; for (register int i = 1; i <= 5; i++) { res[i][i] = 1; } while (exponent) { if (exponent & 1) { res = res * base; } base = base * base, exponent >>= 1; } return res; } int main() { n = read(), f1 = read(), f2 = read(), f3 = read(), c = read(), res = 1; mat[1][1] = mat[2][1] = mat[3][1] = mat[1][2] = mat[2][3] = mat[4][4] = mat[5][4] = 1; mat[5][5] = x[1][5] = mat2[1][1] = 1, mat[4][1] = 2, mat[5][1] = MOD - 5, x[1][4] = 3; mat2[2][1] = mat2[3][1] = mat2[1][2] = mat2[2][3] = x2[1][3] = 1; res = qpow(c, (x * qpow(mat, n - 3))[1][1]); res = (long long int)res * qpow(f1, (x2 * qpow(mat2, n - 3))[1][1]) % MOD, x2[1][3] = 0, x2[1][2] = 1; res = (long long int)res * qpow(f2, (x2 * qpow(mat2, n - 3))[1][1]) % MOD, x2[1][2] = 0, x2[1][1] = 1; res = (long long int)res * qpow(f3, (x2 * qpow(mat2, n - 3))[1][1]) % MOD, printf( %d n , res); }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__AND2_BEHAVIORAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_BEHAVIORAL_V
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module main_pll # (parameter SPEED_MHZ = 25) (inclk0, c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
// synopsys translate_off
.fref (),
.icdrclk (),
// synopsys translate_on
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 50,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = SPEED_MHZ,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=main_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
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#include <bits/stdc++.h> int dp[51 * 10001]; int main(void) { int n, d, a, sum, i, j; while (scanf( %d%d , &n, &d) != EOF) { sum = 0; memset(dp, 0, sizeof(dp)); dp[0] = 1; for (i = 0; i < n; i++) { scanf( %d , &a); sum += a; for (j = sum; j >= a; j--) { if (dp[j - a] == 1) dp[j] = 1; } } int k = 0; int ans = 0; while (true) { i = k + d; while (dp[i] == 0 && i > k) i--; if (k == i) break; k = i; ans++; } printf( %d %d n , k, ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int t, n; cin >> t; while (t--) { cin >> n; int a[n], sum = n - 1; for (int i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } cout << sum / n << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long t, a, b, cnt, p; long long ak[101], tot; int main() { cin >> t >> a >> b; if (t == a && a == b) { if (t == 1) cout << inf ; else cout << 2 ; } else if (a == b) cout << 1 ; else { if (a == 1) { cout << 0 ; return 0; } if (t == 1) { p = 1; while (p < b) { p *= a; if (p == b) { cout << 1 ; return 0; } } } memset(ak, 0, sizeof(ak)); tot = 0; ak[tot] = b; while (ak[tot] / a) { ak[tot + 1] = ak[tot] / a; ak[tot] %= a; tot++; } cnt = 0; p = 1; for (int i = 0; i < 70; i++) { if (ak[i]) cnt = cnt + ak[i] * p; p *= t; } if (cnt == a) cout << 1 ; else cout << 0 ; } return 0; }
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/*
* Copyright (c) 1998-2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [1:0] out;
initial begin
out = 2'b0;
if (out !== 2'b0) begin
$display("FAILED to initialize: out == %b", out);
$finish;
end
out <= #5 2'b1;
if (out !== 2'b0) begin
$display("FAILED -- changed immediately: out == %b", out);
$finish;
end
#4 if (out !== 2'b0) begin
$display("FAILED -- changed too soon: out == %b", out);
$finish;
end
#2 if (out !== 2'b1) begin
$display("FAILED to change after delay: out == %b", out);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
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#include <bits/stdc++.h> using namespace std; int n, m, ans; int l[255 * 2], r[255 * 2], str[255 * 2], po[27]; char s[255][255]; int solve(int bas, int son) { int tot = 0; l[bas - 1] = bas; r[bas - 1] = bas - 1; for (int i = bas; i <= son; i++) { if (r[i - 1] < i) { l[i] = r[i] = i; } else { int sm = l[i - 1] + r[i - 1] - i; l[i] = i - min(sm - l[sm], sm - l[i - 1]); r[i] = 2 * i - l[i]; } while (r[i] + 1 <= son && l[i] - 1 >= bas && str[l[i] - 1] == str[r[i] + 1]) r[i]++, l[i]--; if (str[i] == 0) tot += (r[i] - l[i]) / 4; else tot += (r[i] - l[i] + 2) / 4; } return tot; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) scanf( %s , s[i] + 1); po[0] = 1; for (int i = 1; i < 26; i++) po[i] = 1ll * po[i - 1] * 701 % 1000000007; for (int i = 1; i <= m; i++) { int hash[255] = {0}, tot[255] = {0}; bitset<26> odd[255]; for (int j = i; j <= m; j++) { vector<pair<int, int> > v; for (int k = 1; k <= n; k++) { hash[k] = (hash[k] + po[s[k][j] - a ]) % 1000000007; tot[k] -= odd[k].test(s[k][j] - a ); odd[k][s[k][j] - a ] = !odd[k][s[k][j] - a ]; tot[k] += odd[k].test(s[k][j] - a ); v.push_back({hash[k], k}); } sort(v.begin(), v.end()); int cnt = 0; for (int k = 0; k < n; k++) { ++cnt; str[v[k].second * 2 - 1] = cnt; while (k + 1 < n && v[k].first == v[k + 1].first) { k++; str[v[k].second * 2 - 1] = cnt; } } for (int k = 1; k <= n; k++) { if (tot[k] > 1) continue; int bas = k; while (k + 1 <= n && tot[k + 1] < 2) k++; ans += solve((bas - 1) * 2, k * 2); } } } printf( %d , ans); }
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#include <bits/stdc++.h> using namespace std; using ll = long long; namespace io { const int SIZE = (1 << 21) + 1; char ibuf[SIZE], *iS, *iT, obuf[SIZE], *oS = obuf, *oT = oS + SIZE - 1; inline char getc() { return (iS == iT ? (iT = (iS = ibuf) + fread(ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS++)) : *iS++); } inline void flush() { fwrite(obuf, 1, oS - obuf, stdout); oS = obuf; } inline void putc(char x) { *oS++ = x; if (oS == oT) flush(); } template <class T> inline void read(T &x) { char ch; int f = 1; x = 0; while (isspace(ch = getc())) ; if (ch == - ) ch = getc(), f = -1; do x = x * 10 + ch - 0 ; while (isdigit(ch = getc())); x *= f; } template <class T, class... Args> inline void read(T &x, Args &...args) { read(x); read(args...); } template <class T> inline void write(T x) { static char stk[128]; int top = 0; if (x == 0) { putc( 0 ); return; } if (x < 0) putc( - ), x = -x; while (x) stk[top++] = x % 10, x /= 10; while (top) putc(stk[--top] + 0 ); } template <class T, class... Args> inline void write(T x, Args... args) { write(x); putc( ); write(args...); } inline void space() { putc( ); } inline void endl() { putc( n ); } struct _flush { ~_flush() { flush(); } } __flush; }; // namespace io using io::endl; using io::flush; using io::getc; using io::putc; using io::read; using io::space; using io::write; const int M = 1000000007; inline int add(int x, int y) { return x + y >= M ? x + y - M : x + y; } template <class... Args> inline int add(int x, int y, Args... args) { return add(add(x, y), args...); } inline int sub(int x, int y) { return x - y < 0 ? x - y + M : x - y; } inline int mul(int x, int y) { return 1LL * x * y % M; } template <class... Args> inline int mul(int x, int y, Args... args) { return mul(mul(x, y), args...); } inline void inc(int &x, int y = 1) { x += y; if (x >= M) x -= M; } inline void dec(int &x, int y = 1) { x -= y; if (x < 0) x += M; } inline int power(int x, int y) { int res = 1; for (; y; y >>= 1, x = mul(x, x)) if (y & 1) res = mul(res, x); return res; } inline int inv(int x) { return power(x, M - 2); } const int N = 4005; int _g[N * 2], *g = _g + N; int n, m; struct DP { int a[N * 2]; int *f; DP() { f = a + N; fill(f - m, f + m + 1, 0); f[0] = 1; } void update(int x) { fill(g - m, g + m + 1, 0); for (int i = -m + x; i <= m - x; ++i) g[i - x] = (g[i - x] + f[i]) % M; for (int i = -m + x; i <= m - x; ++i) g[i + x] = (g[i + x] + f[i]) % M; for (int i = -m; i <= m; ++i) f[i] = (f[i] + g[i]) % M; } void select(int x) { fill(g - m, g + m + 1, 0); for (int i = -m + x; i <= m; ++i) g[i - x] = (g[i - x] + f[i]) % M; for (int i = -m; i <= m - x; ++i) g[i + x] = (g[i + x] + f[i]) % M; for (int i = -m; i <= m; ++i) f[i] = g[i]; } void operator=(const DP &r) { for (int i = -m; i <= m; ++i) f[i] = r.f[i]; } int query(int x) { int res = 0; for (int i = 2 - x; i <= x - 2; ++i) inc(res, f[i]); return res; } }; vector<int> G[N]; int a[N]; bool vis[N]; DP f; DP stk[20]; int top = 0; int dfs(int x, int fa) { vis[x] = true; for (int v : G[x]) { if (v == fa) continue; if (v == 1) return 1; return dfs(v, x) + 1; } return 1; } int res = 0; void solve(int l, int r) { if (l == r) { inc(res, f.query(a[l])); return; } stk[top] = f; ++top; int mid = (l + r) >> 1; for (int i = l; i <= mid; ++i) f.update(a[i]); solve(mid + 1, r); f = stk[top - 1]; for (int i = mid + 1; i <= r; ++i) f.update(a[i]); solve(l, mid); --top; } void solve2(int l, int r) { if (l == r) { inc(res, add(f.f[a[l]], f.f[a[l] - 1], f.f[1 - a[l]], f.f[-a[l]])); inc(res, add(f.f[a[l]], f.f[a[l] - 1], f.f[1 - a[l]], f.f[-a[l]])); return; } stk[top] = f; ++top; int mid = (l + r) >> 1; for (int i = l; i <= mid; ++i) f.select(a[i]); solve2(mid + 1, r); f = stk[top - 1]; for (int i = mid + 1; i <= r; ++i) f.select(a[i]); solve2(l, mid); --top; } int main() { read(n, m); for (int i = 1; i <= m; ++i) { int u, v; read(u, v); G[u].push_back(v); G[v].push_back(u); } int cnt = 0; for (int v : G[1]) { if (!vis[v]) a[++cnt] = dfs(v, 1) + 1; } solve(1, cnt); res = mul(res, 2); if ((m & 1) == 0) { f = DP(); for (int i = 1; i <= cnt; ++i) f.select(a[i]); inc(res, f.f[0]); } else { f = DP(); solve2(1, cnt); } write(res), endl(); return 0; }
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#include <bits/stdc++.h> using namespace std; long long n, k, M, D, N, sol, x, mid, f, l, T; long long up(long long a, long long b) { long long tmp = a / b; if (a % b != 0) tmp = tmp + 1ll; return tmp; } long long rep(long long a) { long long tmp = n / a; tmp = up(tmp, k); return tmp; } int main() { cin >> n >> k >> M >> D; sol = rep(M) * M; for (long long p = 2ll; p <= D; p++) { f = 1ll, l = M; mid = (f + l + 1ll) / 2; T = -1; while (l > f) { mid = (f + l + 1ll) / 2; if (rep(mid) == p && rep(mid + 1ll) != p) { T = mid; break; } if (rep(mid) >= p) { f = mid; } else if (rep(mid) < p) { l = mid - 1ll; } if (l - f <= 1) { if (rep(f) == p && rep(l + 1ll) > p) { T = f; break; } if (rep(l) == p && rep(l + 1ll) > p) { T = l; break; } } } if (T != -1) { x = T; T = rep(x) * x; sol = max(sol, T); } } cout << sol; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; int dp[502][502][2], n, m; char str[502][502]; int dis; int check(int x, int y) { if (x < 0 or x >= n and y < 0 or y >= m) return 0; else return 1; } int call(int x, int y, int a, int idx) { int ham = x + y; int paisi = n - 1 - a; int baki = ham - paisi; int b = m - 1 - baki; if (check(x, y) == 0 or check(a, b) == 0) return dp[x][y][a & 1] = 0; if (str[x][y] != str[a][b]) return dp[x][y][a & 1] = 0; if (idx == 0) return dp[x][y][a & 1]; int dx = ((x - a) < 0 ? -(x - a) : (x - a)); int dy = ((y - b) < 0 ? -(y - b) : (y - b)); if (dis % 2 == 0) { if (ham + 1 > dis / 2) return dp[x][y][a & 1] = 0; if (ham + 1 == dis / 2) return dp[x][y][a & 1] = (dx + dy <= 1); } else { if (ham > dis / 2) return dp[x][y][a & 1] = 0; if (ham == dis / 2) return dp[x][y][a & 1] = (x == a and y == b); } long long ret = 0; ret += call(x + 1, y, a, 1 - idx); ret += call(x + 1, y, a - 1, 1 - idx); ret += call(x, y + 1, a, 1 - idx); ret += call(x, y + 1, a - 1, 1 - idx); return dp[x][y][a & 1] = ret % MOD; } int main() { scanf( %d %d , &n, &m); dis = n + m - 1; for (int i = 0; i < n; i++) scanf( %s , str[i]); for (int a = 0; a < n; a++) { for (int y = m - 1; y >= 0; y--) { int tempx = n - 1; int tempy = y; while (tempx >= 0 and tempy < m) { call(tempx, tempy, a, 1); tempy++; tempx--; } } for (int x = n - 2; x >= 0; x--) { int tempx = x; int tempy = 0; while (tempx >= 0 and tempy < m) { call(tempx, tempy, a, 1); tempy++; tempx--; } } } printf( %d n , dp[0][0][(n - 1) & 1]); }
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#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; using LL = long long; using PII = pair<int, int>; using PLL = pair<LL, LL>; using VI = vector<int>; using VVI = vector<VI>; const int INF = 1e9; const int MXN = 55; const int MXM = 2e4 + 5; int n, m, k; VVI init(MXN, VI(MXM, 0)); VVI a, rev_a, sum, rev_sum, Lmax, Rmax, dp, dpL, dpR; int getSum(VVI &sum, int x, int L, int R) { if (L < 1) { return sum[x][R]; } return sum[x][R] - sum[x][L - 1]; } void calc_overlapped(VVI &sum, VVI &dp, int i) { deque<PII> dq; for (int j = 1; j < (int)m - k + 2; ++j) { int num = dp[i - 1][j] - getSum(sum, i, j, j + k - 1); while (!dq.empty() && dq.front().second <= j - k) { dq.pop_front(); } while (!dq.empty() && dq.back().first + getSum(sum, i, dq.back().second, j - 1) <= num) { dq.pop_back(); } dq.push_back({num, j}); dp[i][j] = dq.front().first + getSum(sum, i, dq.front().second, j - 1) + getSum(sum, i, j, j + k - 1) + getSum(sum, i + 1, j, j + k - 1); } } int main() { cin.tie(nullptr); cout.tie(nullptr); ios_base::sync_with_stdio(false); ; cin >> n >> m >> k; a = rev_a = sum = rev_sum = Lmax = Rmax = dp = dpL = dpR = init; for (int i = 1; i < (int)n + 1; ++i) { for (int j = 1; j < (int)m + 1; ++j) { cin >> a[i][j]; sum[i][j] = sum[i][j - 1] + a[i][j]; } for (int j = 1; j < (int)m + 1; ++j) { rev_a[i][j] = a[i][m - j + 1]; rev_sum[i][j] = rev_sum[i][j - 1] + rev_a[i][j]; } } for (int i = 1; i < (int)n + 1; ++i) { for (int j = 1; j < (int)m - k + 2; ++j) { int ksum = getSum(sum, i, j, j + k - 1) + getSum(sum, i + 1, j, j + k - 1); dp[i][j] = ksum; if (j - k > 0) { dp[i][j] = max(dp[i][j], ksum + Lmax[i - 1][j - k]); } if (j + k <= m - k + 1) { dp[i][j] = max(dp[i][j], ksum + Rmax[i - 1][j + k]); } } calc_overlapped(sum, dpL, i); calc_overlapped(rev_sum, dpR, i); for (int j = 1; j < (int)m - k + 2; ++j) { dp[i][j] = max({dp[i][j], dpL[i][j], dpR[i][m - k - j + 2]}); dpL[i][j] = dpR[i][m - k - j + 2] = dp[i][j]; } for (int j = 1; j < (int)m - k + 2; ++j) { Lmax[i][j] = max(Lmax[i][j - 1], dp[i][j]); } for (int j = m - k + 1; j > (int)0; --j) { Rmax[i][j] = max(Rmax[i][j + 1], dp[i][j]); } } int ans = 0; for (int i = 1; i < (int)m - k + 2; ++i) { ans = max(ans, dp[n][i]); } cout << ans << n ; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_FUNCTIONAL_V
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_2_V
`define SKY130_FD_SC_HD__MUX2_2_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2_2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2_2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_2_V
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#include <bits/stdc++.h> using namespace std; int piles[105]; int main() { int n; cin >> n; vector<int> A(n); for (int i = 0; i < n; ++i) cin >> A[i]; sort(A.begin(), A.end()); for (int i = 0; i < n; ++i) { bool flag = false; for (int j = 0; j <= A[i]; ++j) if (piles[j]) { --piles[j]; ++piles[j + 1]; flag = true; break; } if (!flag) piles[1] += 1; } int cnt = 0; for (int i = 1; i < 105; ++i) cnt += piles[i]; cout << cnt; return 0; }
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//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_modf_s5 (
enable,
clock,
dataa,
datab,
result);
input enable;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_modf_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.b(datab),
.q(sub_wire0));
endmodule
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#include <bits/stdc++.h> using namespace std; const int maxn = 2000005; const int inf = 0x3f3f3f3f; long long a[maxn]; int q[maxn]; int main() { int n; cin >> n; long long p = 0; long long pans = 0; for (int i = (1); i < (n + 1); i++) { cin >> a[i]; pans += abs(a[i] - i); if (i < a[i]) { p++; q[a[i] - i]--; } } long long ans1 = pans, ans2 = 0; int cur = n; for (int i = (1); i < (n + 1); i++) { pans -= p; pans += n - p - 1; pans = pans - abs(a[cur] - n) + abs(a[cur] - 1); if (ans1 > pans) ans1 = pans, ans2 = i; p += q[i]; if (1 < a[cur]) { p++; q[a[cur] - 1 + i]--; } cur--; } cout << ans1 << << ans2 << endl; return 0; }
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#include<bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int,int>; #define ff first #define se second #define pb push_back #define all(x) (x).begin(),(x).end() const int mod = 1e9+7; const int inf = 1e9; const int mx = 1e6+5; #define exitYes {cout<< Yes n ; return;} #define exitNo {cout<< No n ; return;} bool can(vector<ll> a){ for(int i=1; i<a.size(); i++){ if(a[i-1] > a[i]) return false; a[i] -= a[i-1]; a[i-1] = 0; }return (a.back() == 0); } void solve(int cs){ // cout << Case << cs << : ; int n; cin >> n; vector<ll> v(n); for(auto &u:v) cin >> u; if(can(v)) exitYes if(n == 1) exitNo swap(v[0], v[1]); if(can(v)) exitYes swap(v[0],v[1]); swap(v[n-1], v[n-2]); if(can(v)) exitYes swap(v[n-1], v[n-2]); vector<ll> p(n), s(n), b = v; p[0] = b[0]; for(int i=1; i<n; i++){ if(p[i-1]==-1 || b[i-1]>b[i]) p[i]=-1; else b[i]-=b[i-1], b[i-1]=0, p[i]=b[i]; }b = v; s[n-1] = b[n-1]; for(int i=n-2; i>=0; i--){ if(s[i+1]==-1 || b[i+1]>b[i]) s[i]=-1; else b[i]-=b[i+1], b[i+1]=0, s[i]=b[i]; } for(int i=1; i+2<n; i++){ if(p[i-1] == -1 || s[i+2]==-1) continue; vector<ll> c = {p[i-1], v[i], v[i+1], s[i+2]}; swap(c[1], c[2]); if(can(c)) exitYes }exitNo } int main(){ ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int tc = 1, cs = 1; cin >> tc; while(tc--) solve(cs++); return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T> inline bool chkmin(T &x, T y) { return y < x ? x = y, 1 : 0; } template <class T> inline bool chkmax(T &x, T y) { return x < y ? x = y, 1 : 0; } inline long long Max(long long x, long long y) { return x > y ? x : y; } inline long long Min(long long x, long long y) { return x < y ? x : y; } int n, m; long long fac[1002], inv[1002]; long long dp[47][1002], ans[1002][47]; void Add(long long &x, long long y) { x += y; if (x >= 1000000007) x -= 1000000007; } long long C(int n, int m) { if (n < 0 || m > n) return 0; return fac[n] * inv[m] % 1000000007 * inv[n - m] % 1000000007; } void Init() { fac[0] = fac[1] = 1; for (int i = (2), i_end_ = (1002); i < i_end_; i++) fac[i] = fac[i - 1] * i % 1000000007; inv[0] = inv[1] = 1; for (int i = (2), i_end_ = (1002); i < i_end_; i++) inv[i] = (1000000007 - (1000000007 / i)) * inv[1000000007 % i] % 1000000007; for (int i = (2), i_end_ = (1002); i < i_end_; i++) inv[i] = inv[i] * inv[i - 1] % 1000000007; dp[0][0] = 1; for (int i = (1), i_end_ = (47); i < i_end_; i++) for (int j = (i * (i + 1) / 2), j_end_ = (1002); j < j_end_; j++) Add(dp[i][j] = dp[i][j - i], dp[i - 1][j - i]); for (int i = (1), i_end_ = (1002); i < i_end_; i++) { for (int k = (1), k_end_ = (47); k < k_end_; k++) { for (int j = (k * (k + 1) / 2), j_end_ = (i); j <= j_end_; j++) Add(ans[i][k], C(i - j + k, k) * dp[k][j] % 1000000007); ans[i][k] = ans[i][k] * fac[k] % 1000000007; } } } int main() { Init(); int cas; cin >> cas; while (cas--) { scanf( %d%d , &n, &m); printf( %I64d n , m >= 45 ? 0 : ans[n][m]); } return 0; }
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module tri_intersect_fadd_32ns_32ns_32_9_full_dsp
#(parameter
ID = 15,
NUM_STAGE = 9,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
tri_intersect_ap_fadd_7_full_dsp_32 tri_intersect_ap_fadd_7_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1505; int n, k; map<tuple<int, int, int>, bool> memo; bool query(int a, int b, int c) { if (b == a || b == c) return 1; if (a > c) swap(a, c); auto s = make_tuple(a, b, c); if (memo.count(s)) return memo[s]; cout << ? << a + 1 << << b + 1 << << c + 1 << endl; cout.flush(); string ans; cin >> ans; return memo[s] = (ans[0] == Y ); } bool alive[N], done; int GOAL; int closer(int u, int v) { for (int w = 0; w < int(n); w++) if (alive[w] && w != u && w != v && query(u, w, v)) v = w; return v; } int iter(int u) { vector<int> nodes; for (int w = 0; w < int(n); w++) if (w != u && alive[w]) nodes.push_back(w); int sz = nodes.size(); auto w = nodes[rand() % sz]; w = closer(u, w); vector<int> u_friends, w_friends; u_friends.push_back(u); w_friends.push_back(w); for (auto v : nodes) if (v != w) { if (query(u, w, v)) w_friends.push_back(v); else u_friends.push_back(u); } int ans; if (u_friends.size() > w_friends.size()) { ans = u; if (u_friends.size() == GOAL) done = 1; for (auto v : w_friends) alive[v] = 0; } else { ans = w; if (w_friends.size() == GOAL) done = 1; for (auto v : u_friends) alive[v] = 0; } return ans; } int main() { srand(time(0)); cin >> n >> k; fill_n(alive, n, 1); GOAL = 1; while (GOAL * k <= n) GOAL *= k; int u = 0; while (!done) u = iter(u); cout << ! << u + 1 << endl; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 100 * 1000 + 5; const int INF = 1000 * 1000 * 1000 + 7; const long long LINF = 1LL * INF * INF; const int MOD = INF; const double PI = acos(-1.); int main() { ios_base::sync_with_stdio(0); int n, p; cin >> n >> p; int ans = INF; for (int k = (1); k < (200); ++k) { long long tmp = n - k * p; long long x = tmp; if (tmp < 0) continue; int cnt = 0; while (tmp) { cnt += tmp % 2; tmp /= 2; } if (cnt <= k && k <= x) ans = min(ans, k); } if (ans == INF) ans = -1; cout << ans; return 0; }
|
`timescale 1ns/1ps
//Reads from accumulate buffer and writes directly to indexed location in DRAM
module dram_read #(
parameter DDR_BASE=31'h00000000,
parameter ADDRESS_WIDTH=31,
parameter TOTAL_DATA=8
) (
clk,
reset,
//External writes to dram
dram_fifo_readdata,
dram_fifo_read,
dram_fifo_empty,
//Write interface to write into DDR memory
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
user_read_buffer,
user_buffer_output_data,
user_data_available,
dram_flush, //the op_lut_process module will assert this signal, following which dram contents will be available in the fifo
num_keys
);
localparam NUM_STATES=5;
localparam STATE_IDLE=1;
localparam STATE_START_FLUSH=2;
localparam STATE_WAIT_READ=4;
localparam STATE_READ_DATA=8;
localparam STATE_WRITE_FIFO=16;
////////////Ports///////////////////
input clk;
input reset;
//Interface for external writes//
output [63:0] dram_fifo_readdata;
input dram_fifo_read;
output dram_fifo_empty;
// Write control inputs and outputs
output wire control_fixed_location;
output reg [ADDRESS_WIDTH-1:0] control_read_base;
output wire [ADDRESS_WIDTH-1:0] control_read_length;
output reg control_go;
input wire control_done;
// Write user logic inputs and outputs
output reg user_read_buffer;
input wire [255:0] user_buffer_output_data;
input wire user_data_available;
input dram_flush;
input [31:0] num_keys;
///////////Registers/////////////////////
reg [ADDRESS_WIDTH-1:0] control_read_base_next;
reg [ADDRESS_WIDTH-1:0] control_read_length_next;
reg control_go_next;
reg user_read_buffer_next;
reg [NUM_STATES-1:0] state, state_next;
reg [31:0] counter,counter_next;
reg [63:0] dram_wr_val, dram_wr_val_next;
assign control_fixed_location=1'b0;
assign control_read_length = 32;
wire dram_fifo_full;
reg dram_fifo_write, dram_fifo_write_next;
always@(*)
begin
dram_fifo_write_next = 1'b0;
control_read_base_next = control_read_base;
control_go_next = 1'b0;
user_read_buffer_next = 1'b0;
state_next = state;
counter_next = counter;
dram_wr_val_next = dram_wr_val;
case(state)
STATE_IDLE: begin
if(dram_flush) begin //if fifo is not empty, start reading first key
counter_next = 0;
state_next = STATE_START_FLUSH;
end
end
STATE_START_FLUSH: begin
control_read_base_next = DDR_BASE+(counter<<5);
control_go_next = 1'b1;
state_next = STATE_WAIT_READ;
end
STATE_WAIT_READ: begin
if(user_data_available) begin
state_next = STATE_READ_DATA;
user_read_buffer_next = 1'b1;
end
end
STATE_READ_DATA: begin
dram_wr_val_next = {user_buffer_output_data[31:0],user_buffer_output_data[63:32]}; //write 64 bits [key and value]
counter_next = counter+1;
state_next = STATE_WRITE_FIFO;
end
STATE_WRITE_FIFO: begin
if(!dram_fifo_full) begin
dram_fifo_write_next = 1'b1;
//state_next = (counter==TOTAL_DATA)?STATE_IDLE:STATE_START_FLUSH;
state_next = (counter==num_keys)?STATE_IDLE:STATE_START_FLUSH;
end
end
endcase
end
always@(posedge clk or posedge reset)
begin
if(reset) begin
state <= STATE_IDLE;
dram_fifo_write <= 1'b0;
control_read_base <= 0;
control_go <= 0;
user_read_buffer <= 1'b0;
counter <= 0;
dram_wr_val <= 0;
end
else begin
state <= state_next;
dram_fifo_write <= dram_fifo_write_next;
control_read_base <= control_read_base_next;
control_go <= control_go_next;
user_read_buffer <= user_read_buffer_next;
counter <= counter_next;
dram_wr_val <= dram_wr_val_next;
end
end
//External accumulator FIFO (receives external updates from netfpga pipeline)
txfifo #(
.DATA_WIDTH(64),
.LOCAL_FIFO_DEPTH(32)
)fifo (
.clock (clk),
.aclr (reset),
.data (dram_wr_val), //write key and value
.rdreq (dram_fifo_read),
.wrreq (dram_fifo_write),
.q (dram_fifo_readdata),
.empty (dram_fifo_empty),
.full (dram_fifo_full),
.usedw (),
.almost_full ()
);
endmodule
|
`include "defines.v"
`include "HRbridge16.v"
`timescale 1ns/1ps
/*module connectRouter_nobuffer
#(parameter addr = 4'b0000) //No. 0 connect router, port 0
(
input `control_w port_l0_i,
output `control_w port_l0_o,
input `control_w FIFO_l0_i,
output `control_w FIFO_l0_o,
input bfull_l0_i,
input clk,
input rst,
output deQ_l0_o,
output enQ_l0_o,
*/
module tb(
);
reg clk, rst;
reg `control_w port_l0, port_l1, port_g0, port_g1;
reg `control_w FIFO_l0, FIFO_l1, FIFO_g0, FIFO_g1;
reg bfull_l0, bfull_l1, bfull_g0, bfull_g1;
wire `control_w port_l0_o, port_l1_o, port_g0_o, port_g1_o;
wire `control_w FIFO_l0_o, FIFO_l1_o, FIFO_g0_o, FIFO_g1_o;
wire deQ_l0, deQ_l1, deQ_g0, deQ_g1;
wire enQ_l0, enQ_l1, enQ_g0, enQ_g1;
wire accept, push;
HRbridge16 r(
.clk(clk),
.rst(rst),
.port_l0_i(port_l0), .port_l1_i(port_l1), .port_g0_i(port_g0), .port_g1_i(port_g1),
.port_l0_o(port_l0_o), .port_l1_o(port_l1_o), .port_g0_o(port_g0_o), .port_g1_o(port_g1_o),
.FIFO_l0_i(FIFO_l0), .FIFO_l1_i(FIFO_l1), .FIFO_g0_i(FIFO_g0), .FIFO_g1_i(FIFO_g1),
.FIFO_l0_o(FIFO_l0_o), .FIFO_l1_o(FIFO_l1_o), .FIFO_g0_o(FIFO_g0_o), .FIFO_g1_o(FIFO_g1_o),
.bfull_l0_i(bfull_l0), .bfull_l1_i(bfull_l1), .bfull_g0_i(bfull_g0), .bfull_g1_i(bfull_g1),
.deQ_l0_o(deQ_l0), .deQ_l1_o(deQ_l1), .deQ_g0_o(deQ_g0), .deQ_g1_o(deQ_g1),
.enQ_l0_o(enQ_l0), .enQ_l1_o(enQ_l1), .enQ_g0_o(enQ_g0), .enQ_g1_o(enQ_g1)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
port_l0 = 144'h0; port_l1 = 144'h0; port_g0 = 144'h0; port_g1 = 144'h0;
FIFO_l0 = 144'h0; FIFO_l1 = 144'h0; FIFO_g0 = 144'h0; FIFO_g1 = 144'h0;
bfull_l0 = 0; bfull_l1 = 0; bfull_g0 = 0; bfull_g1 = 0;
port_l0 = 144'h0123456789abcdef0123456789abcdef1855;
port_g0 = 144'h0000000000000000000000000000000f1851;
port_l1 = 144'h0111111111111111111111111111111f185f;
port_g1 = 144'h0111111111111111101654541645488f1853;
bfull_l0 = 1;
bfull_g0 = 1;
bfull_l1 = 1;
bfull_g1 = 1;
FIFO_l0 = 144'h0123456789abcdef0123456789ffffff1854;
FIFO_l1 = 144'h011111111111111111111111111fffff185f;
FIFO_g0 = 144'h000000000000000000000000000fffff1850;
FIFO_g1 = 144'h011111111111111f0123456789afffff1851;
#1;
clk = 1;
#1;
clk = 0;
$display("clk = 0\n, port_l0 %04x\n, port_l1 %04x\n, port_g0 %04x\n, port_g1 %04x\n, FIFO_l0 %04x\n, FIFO_l1 %04x\n, FIFO_g0 %04x\n, FIFO_g1 %04x\n, deQ_l0 %04x\n, deQ_l1 %04x\n, deQ_g0 %04x\n, deQ_g1 %04x\n, enQ_l0 %04x\n, enQ_l1 %04x\n, enQ_g0 %04x\n, enQ_g1 %04x\n",
port_l0_o, port_l1_o, port_g0_o, port_g1_o,
FIFO_l0_o, FIFO_l1_o, FIFO_g0_o, FIFO_g1_o,
deQ_l0, deQ_l1, deQ_g0, deQ_g1,
enQ_l0, enQ_l1, enQ_g0, enQ_g1,);
#1;
clk = 1;
#1;
clk = 0;
port_l0 = 144'h0; port_l1 = 144'h0; port_g0 = 144'h0; port_g1 = 144'h0;
FIFO_l0 = 144'h0; FIFO_l1 = 144'h0; FIFO_g0 = 144'h0; FIFO_g1 = 144'h0;
bfull_l0 = 0; bfull_l1 = 0; bfull_g0 = 0; bfull_g1 = 0;
$display("clk = 0\n, port_l0 %04x\n, port_l1 %04x\n, port_g0 %04x\n, port_g1 %04x\n, FIFO_l0 %04x\n, FIFO_l1 %04x\n, FIFO_g0 %04x\n, FIFO_g1 %04x\n, deQ_l0 %04x\n, deQ_l1 %04x\n, deQ_g0 %04x\n, deQ_g1 %04x\n, enQ_l0 %04x\n, enQ_l1 %04x\n, enQ_g0 %04x\n, enQ_g1 %04x\n",
port_l0_o, port_l1_o, port_g0_o, port_g1_o,
FIFO_l0_o, FIFO_l1_o, FIFO_g0_o, FIFO_g1_o,
deQ_l0, deQ_l1, deQ_g0, deQ_g1,
enQ_l0, enQ_l1, enQ_g0, enQ_g1,);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100100; int main() { string s, ans; cin >> s; for (int i = 0; i < s.length(); i++) { if (s[i] == . ) ans += 0 ; if (s[i] == - ) { i++; if (s[i] == . ) ans += 1 ; else ans += 2 ; } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int N = 4e4 + 5; int pr[N], ps = 0; bool np[N]; bool check(int n) { if (n == 1 || n == 0) return false; for (int i = 0; pr[i] * pr[i] <= n; ++i) if (n % pr[i] == 0) return false; return true; } int main() { for (int i = 2; i < N; ++i) if (!np[i]) { pr[ps++] = i; for (int j = i + i; j < N; j += i) np[j] = 1; } int n; cin >> n; if (check(n)) { cout << 1 n << n << endl; return 0; } for (int i = 0; i < ps && pr[i] <= n; ++i) { if (check(n - pr[i])) { cout << 2 n << pr[i] << << n - pr[i] << endl; return 0; } if (pr[i] % 2 == 1 && check((n - pr[i]) / 2)) { cout << 3 n << pr[i] << << (n - pr[i]) / 2 << << (n - pr[i]) / 2 << endl; return 0; } } cout << lol nope n ; return 0; }
|
//sf_camera_controller.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "sf_camera_defines.v"
module sf_camera_controller (
input clk,
input rst,
//Physical Interface
output o_cam_rst,
output o_flash,
input i_flash_strobe,
output o_cam_in_clk,
//Configuration Registers
input i_auto_flash,
input i_manual_flash_on,
input i_enable,
input i_camera_reset,
output o_clk_locked,
//Core Controller
output o_enable_dma,
output o_enable_reader,
output o_enable_interrupt
);
//Local Parameters
//Registers/Wires
//Submodules
//20MHz Clock Genertors
sf_camera_clk_gen clk_gen(
.clk (clk ),
.rst (rst ),
.locked (o_clk_locked ),
.phy_out_clk (o_cam_in_clk )
);
//Asynchronous Logic
assign o_flash = (i_auto_flash) ? i_flash_strobe:
i_manual_flash_on;
assign o_cam_rst = i_camera_reset;
//Synchronous Logic
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 10; const long long MN = 5e2 + 10; long long n, m, a[MN], b[MN]; vector<pair<long long, char> > ans; long long lz = 0; bool fl = false; void fail() { cout << NO n ; exit(0); } long long get(long long l, long long r) { long long mx = *max_element(a + l, a + r + 1); if (a[l] == mx) { fl = true; long long ret = l; for (; a[ret] == mx; ++ret) ; return ret - 1; } long long ret = l; for (; a[ret] != mx; ++ret) ; return ret; } int32_t main() { ios_base ::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n; for (long long i = 0; i < n; ++i) cin >> a[i]; cin >> m; for (long long i = 0; i < m; ++i) cin >> b[i]; long long cur = 0; long long p = 0; long long lst = 0; for (long long i = 0; i < n; ++i) { cur += a[i]; if (cur == b[p] && p < m) { if (i == lst) { ++p, cur = 0, lst = i + 1; continue; } if (*max_element(a + lst, a + i + 1) == *min_element(a + lst, a + i + 1)) fail(); ++p; fl = false; long long ind = get(lst, i); if (fl) { for (long long j = 0; j < (i - ind); ++j) ans.push_back(make_pair(ind - lz, R )); for (long long j = ind - 1; j >= lst; --j) { ans.push_back(make_pair(ind - lz, L )); ++lz; } lz += (i - ind); } else { for (long long j = ind - 1; j >= lst; --j) { ans.push_back(make_pair(ind - lz, L )); ++lz; } for (long long j = 0; j < (i - ind); ++j) ans.push_back(make_pair(ind - lz, R )); lz += i - ind; } cur = 0; lst = i + 1; } } if (cur || p < m) fail(); cout << YES n ; for (auto v : ans) cout << v.first + 1 << << v.second << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int n, a[maxn], b[maxn], v[maxn]; unordered_map<int, int> mp; void dfs(int x, int l, int r) { if (v[x] <= r && v[x] >= l) mp[v[x]] = 1; if (a[x] != -1) { if (l < v[x]) dfs(a[x], l, min(v[x] - 1, r)); } if (b[x] != -1) { if (r > v[x]) dfs(b[x], max(l, v[x] + 1), r); } } bool f[maxn]; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> v[i] >> a[i] >> b[i]; if (a[i] != -1) f[a[i]] = 1; if (b[i] != -1) f[b[i]] = 1; } int root = 1; for (int i = 1; i <= n; i++) if (!f[i]) root = i; dfs(root, 0, 1000000000); int ret = 0; for (int i = 1; i <= n; i++) if (mp.find(v[i]) != mp.end()) ret++; cout << n - ret << endl; return 0; }
|
//device_rom_table.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
*use defparam in the instantiating module in order to set the
* number of items in the ROM
* defparam SDB_NRECS = 2;
*/
`timescale 1 ns/1 ps
`include "project_defines.v"
//`define SDB_NRECS 1
`define SDB_ROM_SIZE_OF_HEADER 16
`define SDB_ROM_SIZE_OF_DEV 16
module device_rom_table (
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int
);
//registers
parameter SDB_ROM_SIZE = `SDB_ROM_SIZE_OF_HEADER + (`SDB_NRECS * `SDB_ROM_SIZE_OF_DEV);
reg [31:0] sdb [(SDB_ROM_SIZE - 1):0];
initial begin
$readmemh(`SDB_INPUT_FILE, sdb, 0, SDB_ROM_SIZE - 1);
end
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (!o_wbs_ack && i_wbs_stb & i_wbs_cyc) begin
//master is requesting somethign
if (i_wbs_we) begin
//ROMS can't be written to
end
else begin
//read request
o_wbs_dat <= sdb[i_wbs_adr];
end
o_wbs_ack <= 1;
end
end
end
endmodule
|
/**************************************************************************
UART Transmitter Module
-Clock Rate
x4
-parameter BAUDRATE_COUNTER
Uart Baudrate Parameter (Clock / Baudrate)/4-1
BAUDRATE_COUNTER is must be greater than 4. (BAUDRATE_COUNTER >= 20'h4)
Example : Clock : 50MHz
9600bps : 13'd1301
115.2Kbps : 13'd108
-SDF Settings
Asynchronus Clock : b_bd_clock
-Make : 2013/2/21
-Update : 2013/10/13
Takahiro Ito
**************************************************************************/
`default_nettype none
module mist1032isa_uart_transmitter #(
parameter BAUDRATE_FIXED = 1'b1, //0:Use iEXTBAUD_COUNT | 1:Use Parameter BAUDRATE_COUNTER
parameter BAUDRATE_COUNTER = 20'd108 //(Clock / Baudrate) / 4 - 1
)(
//Clock
input wire iCLOCK,
input wire inRESET,
//External Baudrate Timing
input wire [19:0] iEXTBAUD_COUNT,
//Request
input wire iTX_REQ,
output wire oTX_BUSY,
input wire [7:0] iTX_DATA,
//UART
output wire oUART_TXD
);
/**************************************************************
Parameter & Wire & Register
**************************************************************/
localparam TXD_IDLE = 1'h0;
localparam TXD_WORKING = 1'h1;
localparam IF_IDLE = 2'h0;
localparam IF_START = 2'h1;
localparam IF_WORKING = 2'h2;
//Interface Latch
reg [1:0] b_if_state;
reg [7:0] b_if_data;
reg b_if_start;
//Metastable Cancel
wire dflipflop_if_start;
//Async 2 Sync
wire async2sync_if_start;
//TxD Module
reg b_txd_state;
reg [5:0] b_txd_counter;
reg b_txd_ack;
reg b_txd_end;
//Baudrate
reg [19:0] b_bd_wait_counter;
reg b_bd_clock;
/**************************************************************
Interface
**************************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_if_state <= IF_IDLE;
b_if_data <= 8'h0;
b_if_start <= 1'b0;
end
else begin
case(b_if_state)
IF_IDLE:
begin
if(iTX_REQ)begin
b_if_state <= IF_START;
b_if_data <= iTX_DATA;
b_if_start <= 1'b1;
end
end
IF_START:
begin
if(b_txd_ack)begin
b_if_state <= IF_WORKING;
b_if_start <= 1'b0;
end
end
IF_WORKING:
begin
if(b_txd_end)begin
b_if_state <= IF_IDLE;
end
end
endcase
end
end
/**************************************************************
TxD Module
**************************************************************/
function func_txd;
input [3:0] func_counter;
input [7:0] func_data;
begin
case(func_counter)
4'h0: func_txd = 1'b0;
4'h1: func_txd = func_data[0];
4'h2: func_txd = func_data[1];
4'h3: func_txd = func_data[2];
4'h4: func_txd = func_data[3];
4'h5: func_txd = func_data[4];
4'h6: func_txd = func_data[5];
4'h7: func_txd = func_data[6];
4'h8: func_txd = func_data[7];
default: func_txd = 1'b1;
endcase
end
endfunction
//Metastable Cancel
mist1032isa_uart_transmitter_double_flipflop #(1) DOUBLE_FLIPFLOP(
.iCLOCK(b_bd_clock),
.inRESET(inRESET),
//Input
.iREQ_DATA(b_if_start),
//Output
.oOUT_DATA(dflipflop_if_start)
);
//Async 2 Sync
mist1032isa_uart_transmitter_async2sync #(1) ASYNC2SYNC(
.iCLOCK(b_bd_clock),
.inRESET(inRESET),
//Ena-Signal
.iSIGNAL(dflipflop_if_start),
.oSIGNAL(async2sync_if_start)
);
//State
always@(posedge b_bd_clock or negedge inRESET)begin
if(!inRESET)begin
b_txd_state <= TXD_IDLE;
b_txd_counter <= 6'h0;
b_txd_ack <= 1'b0;
b_txd_end <= 1'b0;
end
else begin
case(b_txd_state)
TXD_IDLE:
begin
if(async2sync_if_start)begin
b_txd_state <= TXD_WORKING;
b_txd_ack <= 1'b1;
end
b_txd_counter <= 6'h0;
b_txd_end <= 1'b0;
end
TXD_WORKING:
begin
b_txd_ack <= 1'b0;
if(b_txd_counter == 6'd36)begin
b_txd_state <= TXD_IDLE;
b_txd_end <= 1'b1;
end
else begin
b_txd_counter <= b_txd_counter + 6'h1;
end
end
endcase
end
end
/**************************************************************
Baudrate Clock
**************************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_bd_wait_counter <= 20'h0;
b_bd_clock <= 1'b0;
end
else begin
if((BAUDRATE_FIXED && b_bd_wait_counter == BAUDRATE_COUNTER) || (!BAUDRATE_FIXED && b_bd_wait_counter == iEXTBAUD_COUNT))begin
b_bd_wait_counter <= 20'h0;
b_bd_clock <= 1'b1;
end
else begin
b_bd_wait_counter <= b_bd_wait_counter + 20'h1;
b_bd_clock <= 1'b0;
end
end
end
/**************************************************************
Assign
**************************************************************/
assign oUART_TXD = (b_txd_state == TXD_WORKING)? func_txd(b_txd_counter[5:2], b_if_data) : 1'b1;
assign oTX_BUSY = (b_if_state == IF_IDLE)? 1'b0 : 1'b1;
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Response Down-Sizer
// Collect MI-side responses and set the SI-side response to the most critical
// level (in descending order):
// DECERR, SLVERROR and OKAY.
// EXOKAY cannot occur for split transactions.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// wr_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 1
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
input wire [8-1:0] cmd_repeat,
output wire cmd_ready,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Repeat handling related.
reg [8-1:0] repeat_cnt_pre;
reg [8-1:0] repeat_cnt;
wire [8-1:0] next_repeat_cnt;
reg first_mi_word;
wire last_word;
// Ongoing split transaction.
wire load_bresp;
wire need_to_update_bresp;
reg [2-1:0] S_AXI_BRESP_ACC;
// Internal signals for MI-side.
wire M_AXI_BREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID_I;
reg [2-1:0] S_AXI_BRESP_I;
wire S_AXI_BVALID_I;
wire S_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// The MI-side BRESP is popped when at once for split transactions, except
// for the last cycle that behaves like a "normal" transaction.
// A "normal" BRESP is popped once the SI-side is able to use it,
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from MI-side.
assign M_AXI_BREADY_I = M_AXI_BVALID & ~mi_stalling;
assign M_AXI_BREADY = M_AXI_BREADY_I;
// Indicate when there is a BRESP available @ SI-side.
assign S_AXI_BVALID_I = M_AXI_BVALID & last_word;
// Get MI-side data.
assign pop_mi_data = M_AXI_BVALID & M_AXI_BREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = (~S_AXI_BREADY_I & last_word);
/////////////////////////////////////////////////////////////////////////////
// Handle the accumulation of BRESP.
//
// Forward the accumulated or MI-side BRESP value depending on state:
// * MI-side BRESP is forwarded untouched when it is a non split cycle.
// (MI-side BRESP value is also used when updating the accumulated for
// the last access during a split access).
// * The accumulated BRESP is for a split transaction.
//
// The accumulated BRESP register is updated for each MI-side response that
// is used.
//
/////////////////////////////////////////////////////////////////////////////
// Force load accumulated BRESPs to first value
assign load_bresp = (cmd_split & first_mi_word);
// Update if more critical.
assign need_to_update_bresp = ( M_AXI_BRESP > S_AXI_BRESP_ACC );
// Select accumultated or direct depending on setting.
always @ *
begin
if ( cmd_split ) begin
if ( load_bresp || need_to_update_bresp ) begin
S_AXI_BRESP_I = M_AXI_BRESP;
end else begin
S_AXI_BRESP_I = S_AXI_BRESP_ACC;
end
end else begin
S_AXI_BRESP_I = M_AXI_BRESP;
end
end
// Accumulate MI-side BRESP.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_BRESP_ACC <= C_RESP_OKAY;
end else begin
if ( pop_mi_data ) begin
S_AXI_BRESP_ACC <= S_AXI_BRESP_I;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Keep track of BRESP repeat counter.
//
// Last BRESP word is either:
// * The first and only word when not merging.
// * The last value when merging.
//
// The internal counter is taken from the external command interface during
// the first response when merging. The counter is updated each time a
// BRESP is popped from the MI-side interface.
//
/////////////////////////////////////////////////////////////////////////////
// Determine last BRESP cycle.
assign last_word = ( ( repeat_cnt == 8'b0 ) & ~first_mi_word ) |
~cmd_split;
// Select command reapeat or counted repeat value.
always @ *
begin
if ( first_mi_word ) begin
repeat_cnt_pre = cmd_repeat;
end else begin
repeat_cnt_pre = repeat_cnt;
end
end
// Calculate next repeat counter value.
assign next_repeat_cnt = repeat_cnt_pre - 2'b01;
// Keep track of the repeat count.
always @ (posedge ACLK) begin
if (ARESET) begin
repeat_cnt <= 8'b0;
first_mi_word <= 1'b1;
end else begin
if ( pop_mi_data ) begin
repeat_cnt <= next_repeat_cnt;
first_mi_word <= last_word;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// BID Handling
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_BID_I = cmd_id;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_BID = S_AXI_BID_I;
assign S_AXI_BRESP = S_AXI_BRESP_I;
assign S_AXI_BVALID = S_AXI_BVALID_I;
assign S_AXI_BREADY_I = S_AXI_BREADY;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300000 + 100; int p[maxn << 2]; void pushdown(int L, int R, int u) { if (L != R) { if (p[u] != -1) { p[u << 1] = p[u]; p[u << 1 | 1] = p[u]; p[u] = -1; } } } void update(int cL, int cR, int val, int L, int R, int u) { pushdown(L, R, u); if (cL <= L && R <= cR) { p[u] = val; } else { int m = (L + R) / 2; if (cR <= m) update(cL, cR, val, L, m, u << 1); else if (cL > m) update(cL, cR, val, m + 1, R, u << 1 | 1); else { update(cL, cR, val, L, m, u << 1); update(cL, cR, val, m + 1, R, u << 1 | 1); update(cL, cR, val, m + 1, R, u << 1 | 1); } } } int query(int x, int L, int R, int u) { pushdown(L, R, u); if (L == R) return p[u]; else { int m = (L + R) / 2; if (x <= m) return query(x, L, m, u << 1); else return query(x, m + 1, R, u << 1 | 1); } } vector<int> G[maxn]; int res[maxn]; int sum[maxn]; int n; void dfs(int u) { sum[u]++; int Max = 0; for (int i = 0; i < G[u].size(); ++i) { int v = G[u][i]; dfs(v); sum[u] += sum[v]; Max = max(Max, sum[v]); } update(Max, sum[u], u, 0, n, 1); res[u] = query(sum[u] / 2, 0, n, 1); } int main() { int q; scanf( %d %d , &n, &q); for (int i = 2; i <= n; ++i) { int t; scanf( %d , &t); G[t].push_back(i); } memset(p, -1, sizeof(p)); memset(sum, 0, sizeof(sum)); dfs(1); while (q--) { int t; scanf( %d , &t); printf( %d n , res[t]); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 20 + 5; const long long INF = 3e9; const char *cc = 0123456789abcdef ; int c[maxn][maxn], used[maxn]; long long dp[maxn][maxn]; char s[maxn]; long long solve(int t, int m, bool flag) { memset(dp[0], 0, sizeof(dp[0])); if (flag) { for (int i = 0; i < m; ++i) { for (int j = 0; j + used[0] <= t && j + i + 1 <= m; ++j) { dp[0][i + j] = min(INF, dp[0][i + j] + c[m - i - 1][j]); } } } else for (int i = 0; i + used[0] <= t && i <= m; ++i) dp[0][i] = c[m][i]; for (int i = 1; i < 16; ++i) { memset(dp[i], 0, sizeof(dp[i])); for (int j = 0; j <= m; ++j) { if (!dp[i - 1][j]) continue; for (int k = 0; k + used[i] <= t && k + j <= m; ++k) { dp[i][j + k] = min(INF, dp[i][j + k] + dp[i - 1][j] * c[m - j][k]); } } } return dp[15][m]; } int main() { for (int i = 0; i < maxn; ++i) { c[i][0] = c[i][i] = 1; for (int j = 1; j < i; ++j) c[i][j] = c[i - 1][j - 1] + c[i - 1][j]; } int k, t; cin >> k >> t; bool flag = true; for (int i = 0; i < 20; ++i) { long long sum = 0; for (int j = 0; j < 16; ++j) { if (used[j] >= t) continue; if (!flag || j != 0) ++used[j]; long long tmp = solve(t, 20 - i - 1, flag && j == 0); sum += tmp; if (sum >= k) { s[i] = cc[j]; k -= sum - tmp; if (j > 0) flag = false; break; } if (!flag || j != 0) --used[j]; } } s[20] = 0; int p = 0; while (s[p] == 0 ) ++p; cout << s + p << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; bool vis[30010][210][2][2][2]; int pd[30010][210][2][2][2]; int v[30010]; int n, K; int solve(int ind, int cut, int s1, int s2, int tem) { if (cut == K) return 0LL; if (ind == n) return -0x3f3f3f3f; int &ans = pd[ind][cut][s1][s2][tem]; if (vis[ind][cut][s1][s2][tem]) return ans; int p1, p2; if (s1) p1 = 1; else p1 = -1; if (s2) p2 = 1; else p2 = -1; if (cut == 0) p1 = 0LL; if (cut == K - 1) p2 = 0LL; vis[ind][cut][s1][s2][tem] = true; ans = -0x3f3f3f3f; int x = v[ind] * (p1 + p2); if (tem) { ans = max(x + solve(ind + 1, cut + 1, s2 ^ 1, 0, 0), x + solve(ind + 1, cut + 1, s2 ^ 1, 1, 0)); ans = max(ans, x + solve(ind + 1, cut, s1, s2, tem)); } else { ans = max(ans, solve(ind + 1, cut, s1, s2, 0)); ans = max(ans, x + solve(ind + 1, cut, s1, s2, 1)); ans = max(ans, x + solve(ind + 1, cut + 1, s2 ^ 1, 0, 0)); ans = max(ans, x + solve(ind + 1, cut + 1, s2 ^ 1, 1, 0)); } return ans; } int main() { scanf( %d %d , &n, &K); for (int i = 0; i < (n); ++i) scanf( %d , &v[i]); int ans = max(solve(0, 0, 0, 0, 0), solve(0, 0, 0, 1, 0)); printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int A[2], B[2], C[2]; scanf( %d %d %d %d %d %d , &A[0], &A[1], &B[0], &B[1], &C[0], &C[1]); int r1 = A[0]; int r2 = B[0]; int r3 = C[0]; int c1 = A[1]; int c2 = B[1]; int c3 = C[1]; bool check = false; int row1, row2, row3, col1, col2, col3; for (int i = 0; i < (1 << 3); i++) { A[0] = r1; B[0] = r2; C[0] = r3; A[1] = c1; B[1] = c2; C[1] = c3; if ((i & 1) == 1) { swap(A[0], A[1]); } if (((i >> 1) & 1) == 1) { swap(B[0], B[1]); } if (((i >> 2) & 1) == 1) { swap(C[0], C[1]); } if (A[0] == B[0] && B[0] == C[0] && A[0] == A[1] + B[1] + C[1]) { row1 = A[1]; row2 = B[1]; row3 = C[1]; col1 = A[0]; printf( %d n , col1); for (int i = 0; i < row1; i++) { for (int j = 0; j < col1; j++) { printf( A ); } printf( n ); } for (int i = 0; i < row2; i++) { for (int j = 0; j < col1; j++) { printf( B ); } printf( n ); } for (int i = 0; i < row3; i++) { for (int j = 0; j < col1; j++) { printf( C ); } printf( n ); } return 0; } if (A[0] == B[0] + C[0] && B[1] == C[1] && A[0] == A[1] + B[1]) { row1 = A[1]; row2 = B[1]; col1 = A[0]; col2 = B[0]; col3 = C[0]; printf( %d n , col1); for (int i = 0; i < row1; i++) { for (int j = 0; j < col1; j++) { printf( A ); } printf( n ); } for (int i = 0; i < row2; i++) { for (int j = 0; j < col2; j++) { printf( B ); } for (int j = 0; j < col3; j++) { printf( C ); } printf( n ); } return 0; } if (B[0] == A[0] + C[0] && A[1] == C[1] && B[0] == B[1] + C[1]) { row1 = B[1]; row2 = A[1]; col1 = B[0]; col2 = A[0]; col3 = C[0]; printf( %d n , col1); for (int i = 0; i < row1; i++) { for (int j = 0; j < col1; j++) { printf( B ); } printf( n ); } for (int i = 0; i < row2; i++) { for (int j = 0; j < col2; j++) { printf( A ); } for (int j = 0; j < col3; j++) { printf( C ); } printf( n ); } return 0; } if (C[0] == A[0] + B[0] && A[1] == B[1] && C[0] == A[1] + C[1]) { row1 = C[1]; row2 = A[1]; col1 = C[0]; col2 = A[0]; col3 = B[0]; printf( %d n , col1); for (int i = 0; i < row1; i++) { for (int j = 0; j < col1; j++) { printf( C ); } printf( n ); } for (int i = 0; i < row2; i++) { for (int j = 0; j < col2; j++) { printf( A ); } for (int j = 0; j < col3; j++) { printf( B ); } printf( n ); } return 0; } } if (!check) { printf( -1 ); return 0; } }
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#include <bits/stdc++.h> using namespace std; int n, k; int v[100000 + 1]; int mx, rez; pair<int, int> rz[100000 + 1]; int stkLen; int stkLen2; int stk[100000 + 1]; int stk2[100000 + 1]; int s, s2; void readFile() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> v[i]; } int cautBin(int nr, int stk[], int stkLen) { int i = 0; int pas = 1 << 16; while (pas != 0) { if (i + pas <= stkLen && abs(v[stk[i + pas]] - nr) > k) i += pas; pas >>= 1; } return stk[i] + 1; } bool verif(int st, int dr) { while (s < stkLen && stk[s] < st) s++; while (s2 < stkLen2 && stk2[s2] < st) s2++; return (abs(v[stk[s]] - v[stk2[s2]]) <= k); } void solve() { stkLen = 0; int st = 1; s = s2 = 1; for (int i = 1; i <= n; i++) { while (stkLen >= s && v[i] >= v[stk[stkLen]]) stkLen--; stk[++stkLen] = i; while (stkLen2 >= s2 && v[i] <= v[stk2[stkLen2]]) stkLen2--; stk2[++stkLen2] = i; while (st < i && verif(st, i) == 0) st++; int len = i - st + 1; if (len > mx) { mx = len; rez = 0; } if (len == mx) rz[++rez] = {st, i}; } } void printFile() { cout << mx << << rez << n ; for (int i = 1; i <= rez; i++) cout << rz[i].first << << rz[i].second << n ; } int main() { readFile(); solve(); printFile(); return 0; }
|
//`include "elink_regmap.v"
module dut(/*AUTOARG*/
// Outputs
dut_active, clkout, wait_out, access_out, packet_out,
// Inputs
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
//##########################################################################
//# INTERFACE
//##########################################################################
parameter AW = 32;
parameter ID = 12'h810;
parameter S_IDW = 12;
parameter M_IDW = 6;
parameter PW = 2*AW + 40;
parameter N = 1;
//clock,reset
input clk1;
input clk2;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
output clkout;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transaction
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
//##########################################################################
//#BODY
//##########################################################################
wire mem_rd_wait;
wire mem_wr_wait;
wire mem_access;
wire [PW-1:0] mem_packet;
/*AUTOINPUT*/
// End of automatics
/*AUTOWIRE*/
assign clkout = clk1;
assign dut_active = 1'b1;
assign wait_out = 1'b0;
emmu eemu (// Outputs
.reg_rdata (),
.emesh_access_out (access_out),
.emesh_packet_out (packet_out[PW-1:0]),
// Inputs
.nreset (nreset),
.mmu_en (1'b0),
.wr_clk (clk1),
.reg_access (1'b0),
.reg_packet ({(PW){1'b0}}),
.rd_clk (clk1),
.emesh_access_in (access_in),
.emesh_packet_in (packet_in[PW-1:0]),
.emesh_wait_in (wait_in));
endmodule
// Local Variables:
// verilog-library-directories:("." "../hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; int n, a[200010]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); int p = 2e9 + 7, ans = 0; for (int i = 1; i < n; i++) p = min(p, a[i + 1] - a[i]); for (int i = 1; i < n; i++) ans += (a[i + 1] - a[i] == p); return printf( %d %d , p, ans), 0; }
|
module CoProcessor0RF(clk, din, wEn, regNum, sel, dout, npc_out, expiaddr, ins, cop_addr, cop_data);
input clk;
input [1:0] wEn;
input [4:0] regNum;
input [2:0] sel;
input [31:0] din;
input [31:0] ins;
input [31:0] npc_out;
output [31:0] dout;
output reg [31:0] expiaddr;
input [4:0] cop_addr;
output [31:0] cop_data;
reg [31:0] coprf [0:31];
wire [5:0] op;
wire [5:0] func;
wire [4:0] mf_tc0_eret;
assign op = ins[31:26];
assign mf_tc0_eret = ins[25:21];
assign func = ins[5:0];
// op
parameter R = 6'b000000,
MTC0_MFC0_ERET = 6'b010000;
// Function code.
parameter SYSCALL = 6'b001100;
// MTC0_MFC0_ERET
parameter MTC0 = 5'b00100,
MFC0 = 5'b00000,
ERET = 5'b10000;
initial begin
coprf[12] = 32'h0000_0000;// Status
coprf[13] = 32'h0000_0000;// Cause
coprf[14] = 32'h0000_0000;// EPC
end
assign dout = coprf[regNum];
assign cop_data = coprf[cop_addr];
always @ (posedge clk) begin
if (wEn) begin
if ((op == R) && (func == SYSCALL)) begin// SYSCALL
coprf[14] <= npc_out - 4'b1000;
coprf[13][6:2] <= 5'b01000;
coprf[12][1] <= 1'b1;
expiaddr <= 32'h0000_0000;
end else if ((op == MTC0_MFC0_ERET) && (mf_tc0_eret == ERET)) begin// ERET
coprf[12][1] <= 1'b0;
expiaddr <= coprf[14][31:0];
end else begin// MTC0
coprf[regNum] <= din;
end
end
end
endmodule // CoProcessor 0 Register File;
|
/**
\file "inverters-syntax-err.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: inverters.v,v 1.3 2010/04/06 00:08:35 fang Exp $
Thanks to Ilya Ganusov for contributing this test.
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("get in0 X"); // bad command
// should fail stop
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$to_prsim("TOP.out3", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #45 $finish;
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD3_TB_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD3_TB_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkdlyinv5sd3.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__clkdlyinv5sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD3_TB_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_pps_interrupt (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg d1_data_in;
reg d2_data_in;
wire data_in;
reg edge_capture;
wire edge_capture_wr_strobe;
wire edge_detect;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask) |
({1 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture <= 0;
else if (edge_detect)
edge_capture <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in & ~d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, A, ni, ai; string si; vector<int> hero; vector<string> moves; vector<int> player; bool used[22][(int)(1 << 20)]; int dp[22][(int)(1 << 20)]; int BAD = 99999999; int memo(int a, int b) { if (used[a][b]) return dp[a][b]; if (a == A) return 0; int res = -BAD; for (int i = 0; i < A; ++i) { if ((b & (1 << i)) > 0) continue; int add = hero[i]; if (moves[a] == p ) { if (player[a] % 2 == 0) { add *= -1; if (res == -BAD) res = add + memo(a + 1, b + (1 << i)); else res = min(res, add + memo(a + 1, b + (1 << i))); } else { if (res == -BAD) res = add + memo(a + 1, b + (1 << i)); else res = max(res, add + memo(a + 1, b + (1 << i))); } } else { if (player[a] % 2 == 0) { if (res == -BAD) res = memo(a + 1, b + (1 << i)); else res = min(res, memo(a + 1, b + (1 << i))); } else { if (res == -BAD) res = memo(a + 1, b + (1 << i)); else res = max(res, memo(a + 1, b + (1 << i))); } } } used[a][b] = true; dp[a][b] = res; return dp[a][b]; } void solve() { cout << memo(0, 0) << endl; } int main() { cin >> N; for (int i = 0; i < N; ++i) { cin >> ni; hero.push_back(ni); } sort(hero.begin(), hero.end()); reverse(hero.begin(), hero.end()); cin >> A; for (int i = 0; i < A; ++i) { cin >> si; cin >> ai; moves.push_back(si); player.push_back(ai); } solve(); }
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> inline std::ostream& operator<<(std::ostream& os, const std::pair<T1, T2>& p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> inline std::ostream& operator<<(std::ostream& os, const std::vector<T>& v) { bool first = true; os << [ ; for (unsigned int i = 0; i < v.size(); i++) { if (!first) os << , ; os << v[i]; first = false; } return os << ] ; } template <typename T> inline std::ostream& operator<<(std::ostream& os, const std::set<T>& v) { bool first = true; os << [ ; for (typename std::set<T>::const_iterator ii = v.begin(); ii != v.end(); ++ii) { if (!first) os << , ; os << *ii; first = false; } return os << ] ; } template <typename T1, typename T2> inline std::ostream& operator<<(std::ostream& os, const std::map<T1, T2>& v) { bool first = true; os << [ ; for (typename std::map<T1, T2>::const_iterator ii = v.begin(); ii != v.end(); ++ii) { if (!first) os << , ; os << *ii; first = false; } return os << ] ; } struct debugger { bool first; debugger() { first = true; } template <typename T> debugger& operator,(const T& v) { if (!first) cout << , ; cout << v; first = false; return *this; } }; long long n; long long arr[10000000]; long long solve() { vector<long long> st; long long mx = 0; for (long long i = 0; i < n; i++) { while (!st.empty() && st.back() < arr[i]) st.pop_back(); st.push_back(arr[i]); if (st.size() >= 2) mx = max(mx, st[st.size() - 1] ^ st[st.size() - 2]); } return mx; } int32_t main(void) { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (long long i = 0; i < n; i++) cin >> arr[i]; long long mx = solve(); reverse(arr, arr + n); cout << max(mx, solve()); }
|
#include <bits/stdc++.h> const double eps = 1e-7, PI = 3.1415926; const int N = 2e5 + 10; using namespace std; long long n, q, m, k, x, y, a[N], mx = -1, mem[N][3], vis[N][3], mn = 1e9, sum, t; char c[N]; string s, s1, s2; map<int, int> mp; vector<int> vec; long long dp(long long i, int cur) { if (i <= 0 || i > n) return 0; if (vis[i][cur] == x) return -1e17; if (mem[i][cur] != -1) return mem[i][cur]; vis[i][cur] = x; long long p1 = 0, p2 = 0; if (cur == 0) p1 += a[i] + dp(i + a[i], cur ^ 1); else p1 += a[i] + dp(i - a[i], cur ^ 1); return mem[i][cur] = p1; } int main() { cin >> n; memset(mem, -1, sizeof mem); for (int i = 2; i <= n; i++) cin >> a[i]; for (int i = 1; i < n; i++) { a[1] = i; mem[1][0] = -1; x++; long long ans = dp(1, 0); if (ans >= 0) cout << ans << endl; else cout << -1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int digit(char c) { char digits[] = { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 }; for (int i = 0; i < 10; i++) { if (c == digits[i]) return 0; } return 1; } int main() { int t = 0; scanf( %d , &t); while (t--) { string s; cin >> s; int len = s.length(); int d = 1, c = 1, l = 1; int cd = 0, cc = 0, cl = 0; int flag = 0; for (int i = 0; i < len; i++) { if (int(s[i]) >= 48 && int(s[i]) <= 57) { d = 0; ++cd; } else if (tolower(s[i]) == s[i]) { l = 0; ++cl; } else if (toupper(s[i]) == s[i]) { c = 0; ++cc; } if ((d + c + l) == 0) { flag = 1; break; } } if (flag == 1) { cout << s << endl; continue; } if ((d + c + l) == 1) { if (d) { if (cl <= cc) { for (int i = 0; i < len; i++) { if (toupper(s[i]) == s[i]) { s[i] = 7 ; break; } } } else { for (int i = 0; i < len; i++) { if (tolower(s[i]) == s[i]) { s[i] = 7 ; break; } } } d = 0; } if (c) { if (cl <= cd) { for (int i = 0; i < len; i++) { if (int(s[i]) >= 48 && int(s[i]) <= 57) { s[i] = A ; break; } } } else { for (int i = 0; i < len; i++) { if (tolower(s[i]) == s[i] && digit(s[i])) { s[i] = toupper(s[i]); break; } } } c = 0; } if (l) { if (cc <= cd) { for (int i = 0; i < len; i++) { if (int(s[i]) >= 48 && int(s[i]) <= 57) { s[i] = a ; break; } } } else { for (int i = 0; i < len; i++) { if (toupper(s[i]) == s[i] && digit(s[i])) { s[i] = tolower(s[i]); break; } } } } l = 0; } if ((d + c + l) == 2) { if (!d) { s[0] = A ; s[1] = a ; } if (!c) { s[0] = a ; s[1] = 7 ; } if (!l) { s[0] = A ; s[1] = 7 ; } } cout << s << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SDFRTN_FUNCTIONAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_ms__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_ms__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n = 0; long long k = 0; long long wynik = 0; long long wynik2 = 0; long long wynik3 = 0; cin >> n >> k; if (k == 1) { cout << 1 ; return 0; } if (k == 2) { wynik = n * (n - 1) / 2 + 1; cout << wynik; return 0; } if (k == 3) { wynik = n * (n - 1) / 2; wynik2 = n * (n - 1) * (n - 2) / 3 + 1; cout << wynik2 + wynik; return 0; } if (k == 4) { wynik = n * (n - 1) / 2; wynik2 = n * (n - 1) * (n - 2) / 3 + 1; wynik3 = (n * (n - 1) * (n - 2) * (n - 3) / 24) * 9; cout << wynik + wynik2 + wynik3; } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2015 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire input_signal = crc[0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire output_signal; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.output_signal (output_signal),
// Inputs
.input_signal (input_signal));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, output_signal};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h765b2e12b25ec97b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input input_signal,
output output_signal
);
// bug872
// verilator lint_off UNOPTFLAT
wire some_signal[1:0][1:0];
assign some_signal[0][0] = input_signal;
assign some_signal[0][1] = some_signal[0][0];
assign some_signal[1][0] = some_signal[0][1];
assign some_signal[1][1] = some_signal[1][0];
assign output_signal = some_signal[1][1];
endmodule
|
/*
* Copyright (c) 2003 The ASIC Group (www.asicgroup.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module mult58s(input [4:0] a, input signed [7:0] b, output signed [15:0] p);
wire signed [12:0] pt;
wire signed [5:0] ta;
assign ta = a;
assign pt = b * ta;
assign p=pt;
endmodule
module test_mult;
integer a,b, prod;
wire [15:0] p;
mult58s dut(a[4:0], b[7:0], p);
initial begin
for(a = 0; a < (1<<5); a=a+1 )
for(b=-127; b<128; b=b+1)
begin
prod = a * b;
#1 if(p !== prod[15:0]) begin
$display("Error Miscompare with a=%h, b=%h expect = %0d (%h) acutal = %h",
a[4:0], b[7:0], prod, prod[15:0], p);
$finish;
end
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, k; long long num[200005], rig[200005], lef[200005]; int main() { scanf( %d%d%d , &n, &m, &k); long long tmp = 0; for (int i = 1; i <= n; ++i) { scanf( %d , &num[i]); } int t = 1; while (m--) t *= k; for (int i = 1; i <= n; ++i) { rig[i] = rig[i - 1] | num[i]; } for (int i = n; i >= 1; --i) { lef[i] = lef[i + 1] | num[i]; } for (int i = 1; i <= n; ++i) tmp = max(tmp, num[i] * t | rig[i - 1] | lef[i + 1]); printf( %I64d , tmp); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXTP_2_V
`define SKY130_FD_SC_HS__DFXTP_2_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfxtp_2 (
CLK ,
D ,
Q ,
VPWR,
VGND
);
input CLK ;
input D ;
output Q ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dfxtp base (
.CLK(CLK),
.D(D),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfxtp_2 (
CLK,
D ,
Q
);
input CLK;
input D ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfxtp base (
.CLK(CLK),
.D(D),
.Q(Q)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXTP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_4_V
`define SKY130_FD_SC_LS__A221O_4_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221o_4 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_SYMBOL_V
`define SKY130_FD_SC_HVL__DLCLKP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void dmin(T& x, T y) { y < x ? x = y : 0; } template <class T> inline void dmax(T& x, T y) { y > x ? x = y : 0; } template <class T> inline void dmin(T& x, vector<T> y) { for (auto t : y) t < x ? x = t : 0; } template <class T> inline void dmax(T& x, vector<T> y) { for (auto t : y) t > x ? x = t : 0; } const int N = 5 + 1e6; const long long INF = -2e18; int n, k; long long gk(int x, long long a[], int i, long long f) { return a[x] + (i - x) / 3 * f; } bool cmp(int x, int y, long long a[], int i, long long f) { return gk(x, a, i, f) > gk(y, a, i, f); } void opera(long long a[], int n, long long f, int k) { static long long b[N]; static long long q[3][N], left[3], right[3]; for (int i = 0; i < 3; ++i) left[i] = 1, right[i] = 0; for (int i = 0; i < n; ++i) b[i] = INF; for (int i = 0; i < n; ++i) { int t = i % 3; while (left[t] <= right[t] && q[t][left[t]] < i - 3 * k) ++left[t]; while (left[t] <= right[t] && cmp(i, q[t][right[t]], a, i, f)) --right[t]; q[t][++right[t]] = i; b[i] = gk(q[t][left[t]], a, i, f); } for (int i = 0; i < n; ++i) a[i] = b[i]; } void opera2(long long a[], int n, long long f, int k) { static long long f1[N], f2[N]; for (int i = 0; i < n; ++i) { f1[i] = f2[i] = a[i]; for (int j = 1; j < 10 && i - j >= 0; ++j) f2[i] = max(f2[i], a[i - j]); } opera(f1, n, f, 3 * k); opera(f2, n, f, 3 * (k - 1)); for (int i = 0; i < n; ++i) a[i] = max(f1[i], f2[i]); } long long a[N], b[N]; int main() { int k; scanf( %d , &k); long long f[6]; for (int i = 0; i < 6; ++i) scanf( %lld , &f[i]); a[0] = 0; n = 1; for (int i = 5; i >= 0; --i) { for (int j = 0; j < 10 * n; ++j) b[j] = INF; for (int j = 0; j < n; ++j) b[j * 10] = a[j]; n *= 10; opera2(b, n, f[i], k); for (int j = 0; j < n; ++j) a[j] = b[j]; } int q; scanf( %d , &q); while (q--) { int x; scanf( %d , &x); printf( %lld n , a[x]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[1005], b[1005], c[1005], d[1005], posa[1005], posb[1005]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int q = 1; q <= n; q++) { int x; cin >> x; a[x] = q; } for (int q = 1; q <= n; q++) { int x; cin >> x; b[x] = q; } for (int q = 1; q <= n; q++) { c[q] = d[q] = posa[q] = posb[q] = q; } vector<array<int, 4>> v; for (int q = 1; q <= n; q++) { if (c[q] == a[q] && d[q] == b[q]) continue; v.push_back({q, posb[b[q]], posa[a[q]], q}); posb[d[q]] = posb[b[q]]; posa[c[q]] = posa[a[q]]; d[posb[d[q]]] = d[q]; c[posa[c[q]]] = c[q]; } cout << ((int)((v).size())) << n ; for (int q = 0; q < ((int)((v).size())); q++) { for (int w = 0; w < 4; w++) cout << v[q][w] << ; cout << n ; } return 0; }
|
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module sdr_data_path(
CLK,
RESET_N,
DATAIN,
DM,
DQOUT,
DQM
);
//`include "Sdram_Params.h"
input CLK; // System Clock
input RESET_N; // System Reset
input [`DSIZE-1:0] DATAIN; // Data input from the host
input [`DSIZE/8-1:0] DM; // byte data masks
output [`DSIZE-1:0] DQOUT;
output [`DSIZE/8-1:0] DQM; // SDRAM data mask ouputs
reg [`DSIZE/8-1:0] DQM;
// internal
reg [`DSIZE-1:0] DIN1;
reg [`DSIZE-1:0] DIN2;
reg [`DSIZE/8-1:0] DM1;
// Allign the input and output data to the SDRAM control path
always @(posedge CLK or negedge RESET_N)
begin
if (RESET_N == 0)
begin
DIN1 <= 0;
DIN2 <= 0;
DM1 <= 0;
end
else
begin
DIN1 <= DATAIN;
DIN2 <= DIN1;
DQM <= DM;
end
end
assign DQOUT = DIN2;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int t, i, j, n, x, y; cin >> x >> y; bool c = 0; char a; for (i = 0; i < x; i++) { for (j = 0; j < y; j++) { cin >> a; if (a != W && a != B && a != G ) c = 1; } } if (c) puts( #Color ); else puts( #Black&White ); return 0; }
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lights_nios2_qsys_0_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; int sum = 0; cin >> n; int **p; p = new int *[n]; for (int i = 0; i < n; i++) { p[i] = new int[n]; for (int j = 0; j < n; j++) { cin >> p[i][j]; } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i == j || i + j == n - 1 || i == (n - 1) / 2 || j == (n - 1) / 2) { sum += p[i][j]; } } } cout << sum; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int sum = 0; sort(a, a + n); for (int i = 0; i < n; i++) { sum = sum + (a[n - 1] - a[i]); } cout << sum; }
|
#include <bits/stdc++.h> using namespace std; bool Primality(long long n) { if (n < 2) return false; if (n == 2) return true; if (n % 2 == 0) return false; for (long long i = 3; i * i <= n; i = i + 2) if (n % i == 0) return false; return true; } int main() { long long n; cin >> n; for (long long i = 1; i <= 1000; i++) { long long pr = (n * i) + 1; if (!Primality(pr)) { cout << i << n ; break; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 105; int n, m, a[maxn][maxn]; int sumr[maxn], sumc[maxn]; bool ar[maxn], ac[maxn]; int main() { ios_base::sync_with_stdio(0); cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> a[i][j]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) sumr[i] += a[i][j]; } for (int j = 0; j < m; j++) { for (int i = 0; i < n; i++) sumc[j] += a[i][j]; } while (1) { bool b = 0; for (int i = 0; i < n; i++) if (sumr[i] < 0) { b = 1; ar[i] ^= 1; for (int j = 0; j < m; j++) sumc[j] -= 2 * a[i][j], a[i][j] = -a[i][j]; sumr[i] *= -1; } for (int j = 0; j < m; j++) if (sumc[j] < 0) { b = 1; ac[j] ^= 1; for (int i = 0; i < n; i++) sumr[i] -= 2 * a[i][j], a[i][j] = -a[i][j]; sumc[j] *= -1; } if (!b) break; } vector<int> vr, vc; for (int i = 0; i < n; i++) if (ar[i]) vr.push_back(i); for (int i = 0; i < m; i++) if (ac[i]) vc.push_back(i); cout << vr.size() << ; for (int i : vr) cout << i + 1 << ; cout << n ; cout << vc.size() << ; for (int i : vc) cout << i + 1 << ; cout << n ; }
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_256x32.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_256x32 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [31:0] data;
input [7:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL rdaddress[7..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL wraddress[7..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; const int K = 65; const int inf = 1000 * 1000 * 1000; const int mod = 1000 * 1000 * 1000 + 7; int n, a[N], q; int t[4 * N][K]; void build(int v, int s, int e) { if (s == e) { for (int i = 0; i < 60; i++) { if (i % a[s] == 0) t[v][i] = 2; else t[v][i] = 1; } return; } int m = (s + e) / 2; build(2 * v, s, m); build(2 * v + 1, m + 1, e); for (int i = 0; i < 60; i++) { int x = (i + t[2 * v][i]) % 60; t[v][i] = t[2 * v][i] + t[2 * v + 1][x]; } } void update(int v, int s, int e, int pos) { if (s == e) { for (int i = 0; i < 60; i++) { if (i % a[s] == 0) t[v][i] = 2; else t[v][i] = 1; } return; } int m = (s + e) / 2; if (pos <= m) update(2 * v, s, m, pos); else update(2 * v + 1, m + 1, e, pos); for (int i = 0; i < 60; i++) { int x = (i + t[2 * v][i]) % 60; t[v][i] = t[2 * v][i] + t[2 * v + 1][x]; } } int get(int v, int s, int e, int l, int r, int st) { if (l > r) return -1; if (s == l && e == r) return t[v][st]; int m = (s + e) / 2; int answ = 0; int T = get(2 * v, s, m, l, min(r, m), st); if (T == -1) T = st; else { answ += T; T += st; } int P = get(2 * v + 1, m + 1, e, max(m + 1, l), r, T % 60); if (P != -1) answ += P; return answ; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); a[n + 1] = 1; build(1, 1, n + 1); scanf( %d , &q); while (q--) { char x; int aa, b; cin >> x; scanf( %d%d , &aa, &b); if (x == A ) { int T = get(1, 1, n + 1, aa, b - 1, 0); printf( %d n , T); } else { a[aa] = b; update(1, 1, n + 1, aa); } } return 0; }
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#include <bits/stdc++.h> using namespace std; struct str { long long num; long long id; } st[666666]; long long arr[666666]; bool cmp(str a, str b) { return a.num < b.num; } signed main() { long long n; cin >> n; for (long long i = 1; i <= n; i++) { cin >> arr[i]; } long long ans = min(arr[1], arr[n]) / (n - 1); for (long long i = 2; i < n; i++) { long long t1 = min(arr[i], arr[1]) * 1ll / (i - 1) * 1ll; long long t2 = min(arr[i], arr[n]) / (n - i) * 1ll; ans = min(ans, min(t1, t2)); } cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; unordered_map<char, int> v; int cnt = 0; int j = 0; for (int i1 = 1; i1 <= n; ++i1) { char ch; string second; cin >> ch >> second; if (ch == ! ) { if (cnt == 0) { for (int i = 0; i < second.length(); ++i) { if (v[second[i]] == 0) { v[second[i]] = 1; } } cnt++; } else { unordered_map<char, int> v1; for (int i = 0; i < second.length(); ++i) { if (v1[second[i]] == 0) { v1[second[i]] = 1; } } for (char ch1 = a ; ch1 <= z ; ++ch1) { if (v[ch1] == 1 && v1[ch1] == 1) { v[ch1] = 1; } else { v[ch1] = -1; } } } } else if (ch == . ) { if (cnt == 0) { for (int i = 0; i < second.length(); ++i) { v[second[i]] = -1; } } else { for (int i = 0; i < second.length(); ++i) { v[second[i]] = -1; } } } else { if (i1 != n) { v[second[0]] = -1; } } int sum = 0, sum1 = 0; for (char ch1 = a ; ch1 <= z ; ++ch1) { if (v[ch1] == 1) { sum += 1; } else if (v[ch1] == -1) { sum1--; } } j++; if (sum == 1 || sum1 == -25) { break; } } int totSum = 0; for (int i = j + 1; i <= n; ++i) { char ch; string second; cin >> ch >> second; if (ch == ! ) { totSum++; } else if (ch == ? && i != n) { totSum++; } } cout << totSum << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; #pragma GCC diagnostic ignored -Wmissing-declarations inline int safe_mul(const int x, const int y) __attribute__((warn_unused_result)); int const mod = 998244353; inline int safe_mul(const int x, const int y) { return x * static_cast<long long>(y) % mod; } inline void safe_add(int& x, const int y) { x += y; if (x >= mod) x -= mod; } inline int safe_pow(int x, int y) { int res = 1; for (; y > 0; y >>= 1) { if (y & 1) res = safe_mul(x, res); x = safe_mul(x, x); } return res; } const int root_pw = 1 << 21; int root; int root_1; void fft(vector<int>& a, bool invert) { int n = (int)a.size(); for (int i = 1, j = 0; i < n; ++i) { int bit = n >> 1; for (; j >= bit; bit >>= 1) j -= bit; j += bit; if (i < j) swap(a[i], a[j]); } for (int len = 2; len <= n; len <<= 1) { int wlen = invert ? root_1 : root; for (int i = len; i < root_pw; i <<= 1) wlen = safe_mul(wlen, wlen); for (int i = 0; i < n; i += len) { int w = 1; for (int j = 0; j < len / 2; ++j) { int u = a[i + j], v = safe_mul(a[i + j + len / 2], w); a[i + j] = u + v < mod ? u + v : u + v - mod; a[i + j + len / 2] = u - v >= 0 ? u - v : u - v + mod; w = safe_mul(w, wlen); } } } if (invert) { int nrev = safe_pow(n, mod - 2); for (int i = 0; i < n; ++i) a[i] = safe_mul(a[i], nrev); } } int need; vector<int> multiply(vector<int> a, vector<int> b) { size_t n = 1; while (n < max(a.size(), b.size())) n <<= 1; n <<= 1; a.resize(n, 0), b.resize(n, 0); fft(a, false), fft(b, false); for (size_t i = 0; i < n; ++i) a[i] = safe_mul(a[i], b[i]); fft(a, true); while (!a.empty() && (a.back() == 0 || a.size() > need + 1)) a.pop_back(); return a; } int solve(map<int, int> primes) { auto comp = [](const vector<int>& l, const vector<int>& r) { return l.size() < r.size(); }; multiset<vector<int>, decltype(comp)> polys(comp); for (auto pa : primes) polys.insert(vector<int>(pa.second + 1, 1)); while (polys.size() > 1) { auto vec = multiply(*polys.begin(), *next(polys.begin())); polys.erase(polys.begin()); polys.erase(polys.begin()); polys.insert(move(vec)); } return polys.begin()->operator[](need); } int main() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); for (int i = 1; i < mod; ++i) { if (safe_pow(i, root_pw) == 1 && safe_pow(i, root_pw >> 1) != 1) { root = i; root_1 = safe_pow(root, mod - 2); break; } } int n; cin >> n; need = n / 2; map<int, int> cnt; while (n--) { int p; cin >> p; ++cnt[p]; } cout << solve(cnt) << endl; }
|
`timescale 1ns / 1ps
module control( input [5:0] opcode,
input branch_eq, // result of comparison for conditional branch
output reg [1:0] if_pc_source,
output id_rt_is_source, // rt is source
output ex_imm_command,
output reg ex_alu_src_b,
output reg ex_dst_reg_sel,
output reg [1:0] ex_alu_op,
output reg mem_read,
output reg mem_write,
output reg wb_mem_to_reg,
output reg wb_reg_write );
//opcodes
localparam LW = 6'b100011,
SW = 6'b101011,
BEQ = 6'b000100,
RTYPE = 6'b0,
J = 6'd2,
JAL = 6'd3,
ADDI = 6'b001000,
ANDI = 6'b001100,
ORI = 6'b001101,
XORI = 6'b001110,
SLTI = 6'b001010;
//--------------------------------
reg memory_op;
reg r_type_op;
reg immediate_op;
reg branch_op;
reg jump_op;
assign ex_imm_command = immediate_op;
assign id_rt_is_source = (r_type_op | branch_op | opcode == SW);
always @* begin
//default values
if_pc_source = 0;
ex_alu_src_b = 0;
ex_dst_reg_sel = 0;
ex_alu_op = 0;
mem_read = 0;
mem_write = 0;
wb_mem_to_reg = 0;
wb_reg_write = 0;
memory_op = ( (opcode == LW) | (opcode == SW) );
r_type_op = ( opcode == RTYPE );
branch_op = ( opcode == BEQ );
immediate_op = ( (opcode == ADDI) | (opcode == ANDI) | (opcode == ORI) | (opcode == XORI) | (opcode == SLTI) );
jump_op = ( opcode == J);
if (memory_op) begin
ex_alu_src_b = 1'b1; // select sign_extend_offset input
ex_dst_reg_sel = 1'b0; // rt
ex_alu_op = 2'b00; // add op
wb_mem_to_reg = 1'b1; // select mem_out
if ( opcode == LW ) begin
mem_read = 1'b1;
wb_reg_write = 1'b1;
end
else
mem_write = 1'b1; // opcode == SW
end
else if (r_type_op) begin
ex_alu_src_b = 1'b0; // select B input
ex_dst_reg_sel = 1'b1; // rd
ex_alu_op = 2'b10; // operaction defined by func code
wb_mem_to_reg = 1'b0; // alu_out
wb_reg_write = 1'b1; // write result to regfile
end
else if (immediate_op) begin
ex_alu_src_b = 1'b1; // select sign_extend_offset input
ex_dst_reg_sel = 1'b0; // rt
ex_alu_op = 2'b10; // operation defined by function code
wb_mem_to_reg = 1'b0; // alu_out
wb_reg_write = 1'b1;
end
else if (branch_op) begin
if (branch_eq)
if_pc_source = 2'b01; // PC <= branch_addr
else
if_pc_source = 2'b00;
end
else if (jump_op)
if_pc_source = 2'b10; // PC <= jump_addr
else begin
//NOP
end
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Double_Range.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Double_Range
// Source Path: velocityControlHdl/Space_Vector_Modulation/Double_Range
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Double_Range
(
In1_0,
In1_1,
In1_2,
Out1_0,
Out1_1,
Out1_2
);
input signed [17:0] In1_0; // sfix18_En13
input signed [17:0] In1_1; // sfix18_En13
input signed [17:0] In1_2; // sfix18_En13
output signed [17:0] Out1_0; // sfix18_En12
output signed [17:0] Out1_1; // sfix18_En12
output signed [17:0] Out1_2; // sfix18_En12
wire signed [17:0] In1 [0:2]; // sfix18_En13 [3]
wire signed [17:0] Data_Type_Conversion_out1 [0:2]; // sfix18_En12 [3]
assign In1[0] = In1_0;
assign In1[1] = In1_1;
assign In1[2] = In1_2;
// <S40>/Data Type Conversion
assign Data_Type_Conversion_out1[0] = {In1[0][17], In1[0][17:1]};
assign Data_Type_Conversion_out1[1] = {In1[1][17], In1[1][17:1]};
assign Data_Type_Conversion_out1[2] = {In1[2][17], In1[2][17:1]};
assign Out1_0 = Data_Type_Conversion_out1[0];
assign Out1_1 = Data_Type_Conversion_out1[1];
assign Out1_2 = Data_Type_Conversion_out1[2];
endmodule // velocityControlHdl_Double_Range
|
#include <bits/stdc++.h> using namespace std; struct Node { vector<Node*> edges; bool term; vector<int> last; Node() { edges.resize(5); fill(edges.begin(), edges.end(), nullptr); term = false; } }; void add_string(Node* root, string s) { for (char c : s) { c -= a ; if (!root->edges[c]) { Node* node = new Node(); root->edges[c] = node; } root = root->edges[c]; } root->term = true; root->last.push_back(0); } void get_ans(Node* node, string s, int cnt, int& ans, int num) { if (cnt >= s.size()) { if (node->term) { for (int i = 0; i < node->last.size(); i++) { if (node->last[i] < num) { node->last[i] = num; ans++; } } } return; } char c = s[cnt]; c -= a ; if (s[cnt] != ? ) { if (node->edges[c]) { get_ans(node->edges[c], s, cnt + 1, ans, num); } } else { get_ans(node, s, cnt + 1, ans, num); for (int i = 0; i < 5; i++) { if (node->edges[i]) { get_ans(node->edges[i], s, cnt + 1, ans, num); } } } } int main() { int n, m; cin >> n >> m; Node* root = new Node(); for (int i = 0; i < n; i++) { string s; cin >> s; add_string(root, s); } for (int i = 0; i < m; i++) { string s; cin >> s; int ans = 0; get_ans(root, s, 0, ans, i + 1); cout << ans << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__EDFXBP_PP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_PP_SYMBOL_V
|
// file: TemperatureMonitor_tb.v
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//----------------------------------------------------------------------------
// System Monitor wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// System Monitor wizard. Input clock is generated in this testbench.
//----------------------------------------------------------------------------
// This testbench does not implement checking of averaging and calibration
// Bipolar signals are applied with Vn = 0
`timescale 1ps/1ps
`define wait_drdy @(negedge DRDY_TB)
module TemperatureMonitor_tb ();
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam time PER1 = 20*ONE_NS;
// Declare the input clock signals
reg DCLK_TB = 1;
wire [6:0] DADDR_TB;
wire DEN_TB;
wire DWE_TB;
wire [15:0] DI_TB;
wire [15:0] DO_TB;
wire DRDY_TB;
wire [2:0] ALM_unused;
wire FLOAT_VCCAUX_ALARM;
wire FLOAT_VCCINT_ALARM;
wire FLOAT_USER_TEMP_ALARM;
// Input clock generation
always begin
DCLK_TB = #(PER1/2) ~DCLK_TB;
end
// Start of the testbench
initial
begin
$display ("Single channel avereraging is enabled");
$display ("This TB does not verify averaging");
$display ("Please increase the simulation duration to see complete waveform") ;
//// Single Channel setup
/////////////////////////////////////////////////////////////
//// Single Channel Mode - Temperature channel selected ////
/////////////////////////////////////////////////////////////
/// Channel selected is Temp. channel
$display ("No status signals are pulled out to monitor the test status");
$display ("Simulation Stopped.");
$finish;
end
// Instantiation of the example design
//---------------------------------------------------------
TemperatureMonitor_exdes dut (
.DADDR_IN(DADDR_TB[6:0]),
.DCLK_IN(DCLK_TB),
.DEN_IN(DEN_TB),
.DI_IN(DI_TB[15:0]),
.DWE_IN(DWE_TB),
.DO_OUT(DO_TB[15:0]),
.DRDY_OUT(DRDY_TB),
.VP_IN(1'b0),
.VN_IN(1'b0)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using uint = unsigned int; struct Cup { uint cap; uint ix; uint cur; }; int main() { uint n; uint total; cin >> n >> total; vector<Cup> cups(n); for (uint i = 0, wi; i < n; ++i) { cin >> wi; cups[i] = {wi, i, 0}; } sort(cups.begin(), cups.end(), [](const Cup& left, const Cup& right) { return left.cap < right.cap; }); uint cur = 0; bool done = true; for (Cup& cup : cups) { cur = cup.cap / 2 + (cup.cap & 1); if (cur > total) { done = false; break; } cup.cur = cur; total -= cup.cur; } uint diff; for (int i = n - 1; i > -1; --i) { diff = min(total, cups[i].cap - cups[i].cur); total -= diff; cups[i].cur += diff; } if (total > 0) { done = false; } if (!done) { cout << -1 n ; } else { sort(cups.begin(), cups.end(), [](const Cup& left, const Cup& right) { return left.ix < right.ix; }); for (Cup& c : cups) { cout << c.cur << ; } cout << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long n, r; cin >> n >> r; long long int sum = 0; if (n == 1) { sum = 1; } else if (n <= r) { sum = ((n - 1) * (n)) / 2 + 1; } else { sum = (r * (r + 1)) / 2; } cout << sum << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFRTP_1_V
`define SKY130_FD_SC_HDLL__DFRTP_1_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFRTP_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 5001; long long a[N], mem[N][2], b[N]; int n, m; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; b[i] = a[i]; } sort(b, b + n); m = unique(b, b + n) - b; for (int i = n - 1; i >= 0; i--) mem[i][1 - m & 1] = abs(a[i] - b[m - 1]) + ((i + 1 < n) ? mem[i + 1][1 - m & 1] : 0ll); for (int j = m - 2; j >= 0; j--) for (int i = n - 1; i >= 0; i--) mem[i][j & 1] = min(mem[i][1 - j & 1], abs(a[i] - b[j]) + ((i + 1 < n) ? mem[i + 1][j & 1] : 0ll)); long long ans = 1ll << 50; ans = min(mem[0][0], mem[0][1]); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> const int INF = 1000000009; using namespace std; int main() { int n, i, l = 0, r = 0; string s; cin >> n >> s; s = . + s; for (i = 1; i < s.size(); i++) if (s[i] == L ) l = 1; else if (s[i] == R ) r = 1; if (r && l) cout << s.find( R ) << << s.find( L ) - 1 << n ; else if (r && !l) cout << s.find( R ) << << s.rfind( R ) + 1 << n ; else cout << s.rfind( L ) << << s.find( L ) - 1 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> c(n); for (int i = 0; i < n; ++i) { scanf( %d , &c[i]); } vector<int> ans(n + 1, 0); for (int i = 0; i < n; ++i) { vector<int> mx(n + 1, 0); int p = 0; for (int k = i; k < n; ++k) { mx[c[k]] += 1; if (mx[c[k]] > mx[p]) { p = c[k]; } else if (mx[c[k]] == mx[p]) { p = min(p, c[k]); } ans[p] += 1; } } for (int i = 1; i <= n; ++i) { printf( %d , ans[i]); } return 0; }
|
#include <bits/stdc++.h> long long vx[200010], vy[200010]; std::map<long long, long long> mp, gg; int main() { int n; long long a, b; scanf( %d%lld%lld , &n, &a, &b); long long ans = 0; for (int k = 1; k <= n; k++) { long long t; scanf( %lld%lld%lld , &t, &vx[k], &vy[k]); long long c = a * vx[k] - vy[k]; long long d = (long long)2000000000 * vx[k] + vy[k]; ans -= gg[d]; gg[d]++; ans += mp[c]; mp[c]++; } printf( %lld n , 2 * ans); }
|
module module1(clk_, rst_, bar0, bar1, foo0, foo1);
input clk_;
input rst_;
input [1:0] bar0;
input [1:0] bar1;
output [1:0] foo0;
output [1:0] foo1;
parameter poser_tied = 1'b1;
parameter poser_width_in = 0+1-0+1+1-0+1;
parameter poser_width_out = 0+1-0+1+1-0+1;
parameter poser_grid_width = 2;
parameter poser_grid_depth = 2;
parameter [poser_grid_width-1:0] cellTypes [0:poser_grid_depth-1] = '{ 2'b11,2'b11 };
wire [poser_width_in-1:0] poser_inputs;
assign poser_inputs = { bar0,bar1 };
wire [poser_width_out-1:0] poser_outputs;
assign { foo0,foo1 } = poser_outputs;
wire [poser_grid_width-1:0] poser_grid_output [0:poser_grid_depth-1];
wire poser_clk;
assign poser_clk = clk_;
wire poser_rst;
assign poser_rst = rst_;
for (genvar D = 0; D < poser_grid_depth; D++) begin
for (genvar W = 0; W < poser_grid_width; W++) begin
if (D == 0) begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_tied ,
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D][W-1],
poser_inputs[W%poser_width_in] }),
.o(poser_grid_output[D][W]));
end
end else begin
if (W == 0) begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D-1][poser_grid_depth-1] }),
.o(poser_grid_output[D][W]));
end else begin
poserCell #(.cellType(cellTypes[D][W]), .activeRst(0)) pc (.clk(poser_clk),
.rst(poser_rst),
.i(^{ poser_grid_output[D-1][W],
poser_grid_output[D][W-1] }),
.o(poser_grid_output[D][W]));
end
end
end
end
generate
if (poser_width_out == 1) begin
poserMux #(.poser_mux_width_in(poser_grid_width)) pm (.i(poser_grid_output[poser_grid_depth-1]),
.o(poser_outputs));
end
else if (poser_grid_width == poser_width_out) begin
assign poser_outputs = poser_grid_output[poser_grid_depth-1];
end
else if (poser_grid_width > poser_width_out) begin
wire [poser_grid_width-1:0] poser_grid_output_last;
assign poser_grid_output_last = poser_grid_output[poser_grid_depth-1];
poserMux #(.poser_mux_width_in((poser_grid_width - poser_width_out) + 1)) pm (.i(poser_grid_output_last[poser_grid_width-1:poser_width_out-1]),
.o(poser_outputs[poser_width_out-1]));
assign poser_outputs[poser_width_out-2:0] = poser_grid_output_last[poser_width_out-2:0];
end
endgenerate
endmodule
|
module multiplexer(q, data, select);
output q;
input [31:0] data;
input [5:0] select;
wire q;
wire [31:0] data;
wire [5:0] select;
assign q =
(select == 5'h00) ? data[0] :
(select == 5'h01) ? data[1] :
(select == 5'h02) ? data[2] :
(select == 5'h03) ? data[3] :
(select == 5'h04) ? data[4] :
(select == 5'h05) ? data[5] :
(select == 5'h06) ? data[6] :
(select == 5'h07) ? data[7] :
(select == 5'h08) ? data[8] :
(select == 5'h09) ? data[9] :
(select == 5'h0A) ? data[10] :
(select == 5'h0B) ? data[11] :
(select == 5'h0C) ? data[12] :
(select == 5'h0D) ? data[13] :
(select == 5'h0E) ? data[14] :
(select == 5'h0F) ? data[15] :
(select == 5'h10) ? data[16] :
(select == 5'h11) ? data[17] :
(select == 5'h12) ? data[18] :
(select == 5'h13) ? data[19] :
(select == 5'h14) ? data[20] :
(select == 5'h15) ? data[21] :
(select == 5'h16) ? data[22] :
(select == 5'h17) ? data[23] :
(select == 5'h18) ? data[24] :
(select == 5'h19) ? data[25] :
(select == 5'h1A) ? data[26] :
(select == 5'h1B) ? data[27] :
(select == 5'h1C) ? data[28] :
(select == 5'h1D) ? data[29] :
(select == 5'h1E) ? data[30] :
(select == 5'h1F) ? data[31] : 1'bx;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long dp[200100][2]; long long ans[200100]; int main(int argc, char const *argv[]) { int T, k; cin >> T >> k; dp[k][1] = 1; dp[1][0] = 1; for (int i = 2; i <= 100000; i++) { if (i - k <= 0) { dp[i][0] += dp[i - 1][0] + dp[i - 1][1]; dp[i][0] %= mod; } else { dp[i][0] += dp[i - 1][0] + dp[i - 1][1]; dp[i][0] %= mod; dp[i][1] += dp[i - k][0] + dp[i - k][1]; dp[i][1] %= mod; } } int a, b; for (int i = 1; i <= 100000; i++) { ans[i] = ans[i - 1] + dp[i][1] + dp[i][0]; ans[i] %= mod; } while (T--) { scanf( %d%d , &a, &b); cout << (mod + ans[b] - ans[a - 1]) % mod << endl; } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:64000000 ) using namespace std; const double eps = 1e-9; const double pi = acos(-1.0); int main() { int n, s; cin >> n >> s; int res = -1; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; if (y == 0) { if (s >= x) { res = max(res, 0); } } else { if (s > x) { res = max(res, 100 - y); } } } cout << res << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; using namespace std; typedef long long int ll; typedef unsigned long long int ull; inline void smax(int &x, int y) { x = max(x, y); } inline void smin(int &x, int y) { x = min(x, y); } ll gcd(ll a, ll b) { return ((b == 0) ? a : gcd(b, a % b)); } const double PI = acos(-1.0l); vector<long long> rev; vector<complex<double> > omega; void calc_rev(long long n, long long log_n) { rev.resize(n); omega.resize(n); for (long long i = 0; i < n; i++) { rev[i] = 0; for (long long j = 0; j < log_n; j++) { if ((i >> j) & 1) rev[i] |= 1 << (log_n - j - 1); } } } void fft(vector<complex<double> > &A, long long n, bool invert) { for (long long i = 0; i < n; i++) { if (i < rev[i]) swap(A[i], A[rev[i]]); } for (long long len = 2; len <= n; len <<= 1) { double ang = 2 * PI / len * (invert ? -1 : +1); long long half = (len >> 1); complex<double> curomega(cos(ang), sin(ang)); omega[0] = complex<double>(1, 0); for (long long i = 1; i < half; i++) omega[i] = omega[i - 1] * curomega; for (long long i = 0; i < n; i += len) { complex<double> t; long long pu = i, pv = i + half, pu_end = i + half, pw = 0; for (; pu != pu_end; pu++, pv++, pw++) { t = A[pv] * omega[pw]; A[pv] = A[pu] - t; A[pu] += t; } } } if (invert) for (long long i = 0; i < n; i++) A[i] /= n; } void multiply(long long n, vector<complex<double> > &A, vector<complex<double> > &B, vector<long long> &C) { fft(A, n, false); fft(B, n, false); for (long long i = 0; i < n; i++) A[i] *= B[i]; fft(A, n, true); for (long long i = 0; i < n; i++) { C[i] = (long long)(A[i].real() + 0.5); C[i] = min(C[i], 1LL); } } void Solve(long long n, vector<long long> &coeffA, vector<long long> &coeffB, vector<long long> &result) { vector<complex<double> > A(n), B(n); for (long long i = 0; i < n; i++) A[i] = coeffA[i]; for (long long i = 0; i < n; i++) B[i] = coeffB[i]; multiply(n, A, B, result); } void do_FFT(vector<long long> &A, vector<long long> &B, vector<long long> &result) { long long n = 1, bits = 0; while (n < 2 * A.size() || n < 2 * B.size()) n <<= 1, bits++; result.resize(n, 0); calc_rev(n, bits); vector<long long> tempA(A.begin(), A.end()); vector<long long> tempB(B.begin(), B.end()); tempA.resize(n); tempB.resize(n); Solve(n, tempA, tempB, result); } vector<ll> polpow(vector<ll> &arr, long long k) { vector<ll> sol; while (k > 0) { if (k % 2) { if (sol.size() == 0) for (__typeof(arr.size()) i = (0) - ((0) > (arr.size())); i != (arr.size()) - ((0) > (arr.size())); i += 1 - 2 * ((0) > (arr.size()))) sol.push_back(arr[i]); else do_FFT(sol, arr, sol); } do_FFT(arr, arr, arr); k = k / 2; } return sol; } int32_t main() { long long n, k; cin >> n >> k; vector<long long> v(n); for (__typeof(n) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) cin >> v[i]; vector<ll> arr(1001); for (__typeof(n) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) { arr[v[i]] = 1; } while (arr.back() == 0) { arr.pop_back(); } vector<ll> res = polpow(arr, k); for (__typeof(res.size()) i = (1) - ((1) > (res.size())); i != (res.size()) - ((1) > (res.size())); i += 1 - 2 * ((1) > (res.size()))) { if (res[i] > 0) cout << i << ; } }
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#include <bits/stdc++.h> using namespace std; vector<int> adj[100005]; struct Tree { vector<vector<int> > anc; vector<vector<int> > cost; vector<int> T, X; vector<int> depth; vector<bool> vis; int n; int root; Tree(int N = 1e5, int r = 1) { n = N + 5; root = r; anc = vector<vector<int> >(18, vector<int>(n, 0)); depth = vector<int>(n, 0); vis = vector<bool>(n, false); X = T = vector<int>(n, 0); init(root, -1); for (int d = 1; d < 18; d++) { for (int x = 0; x < n; x++) { anc[d][x] = anc[d - 1][anc[d - 1][x]]; } } } void init(int x, int pre) { static int t = 0; T[x] = t++; for (int i = 0; i < adj[x].size(); i++) { int y = adj[x][i]; if (y == pre) continue; anc[0][y] = x; depth[y] = depth[x] + 1; init(y, x); } X[x] = t++; } int LCA(int x, int y) { if (depth[x] < depth[y]) swap(x, y); for (int w = (1 << 17), d = 17; d >= 0; w /= 2, d--) { if (depth[x] - depth[y] >= w) { x = anc[d][x]; } } if (x == y) return x; for (int i = 17; i >= 0; i--) { if (anc[i][x] != anc[i][y]) { x = anc[i][x]; y = anc[i][y]; } } return anc[0][x]; } int up(int x, int k) { for (int w = (1 << 17), d = 17; d >= 0; w /= 2, d--) { if (k >= w) { x = anc[d][x]; k -= w; } } return x; } int dist(int x, int y) { int l = LCA(x, y); return depth[x] + depth[y] - 2 * depth[l]; } bool isparent(int x, int y) { return LCA(x, y) == x; } } A; vector<int> aux[100005]; vector<int> event(100005); vector<int> val(100005), resv; vector<bool> out(100005, false), tmp(100005, false); int n, m, sq, s; int ans = 0, lans = 0; vector<int> temp; vector<int> anc(100005, 0); int root = 1; vector<pair<int, int> > edge[100005]; vector<int> lazy(100005, 0); vector<pair<int, int> > ptr(100005, {0, 0}); void compress(int b) { for (auto x : temp) { aux[x].clear(); lazy[x] = 0; ptr[x] = {0, 0}; edge[x].clear(); anc[x] = 0; tmp[x] = false; } temp.clear(); temp.push_back(1); for (int i = b * sq; i < (b + 1) * sq && i < m; i++) { temp.push_back(abs(event[i])); } sort((temp).begin(), (temp).end(), [&](int x, int y) { return A.T[x] < A.T[y]; }); int ss = ((int)(temp).size()); for (int i = 1; i < ss; i++) { temp.push_back(A.LCA(temp[i - 1], temp[i])); } sort((temp).begin(), (temp).end(), [&](int x, int y) { return A.T[x] < A.T[y]; }); for (auto x : temp) tmp[x] = true; stack<int> st; root = 1; for (auto x : temp) { while (!st.empty() && A.X[st.top()] < A.T[x]) st.pop(); if (!st.empty() && st.top() != x) { aux[x].push_back(st.top()); aux[st.top()].push_back(x); anc[x] = st.top(); int l = A.anc[0][x]; map<int, int> cnt; while (l != st.top()) { if (!out[l]) cnt[val[l]]++; l = A.anc[0][l]; } for (auto itr : cnt) edge[x].push_back({itr.first, itr.second}); for (int i = 0; i < ((int)(edge[x]).size()); i++) { if (edge[x][i].first < 0) ptr[x] = {ptr[x].first + 1, ptr[x].second + edge[x][i].second}; else break; } } st.push(x); } } int currTree(int x, int pre) { int v = 0; if (out[x]) v--; for (auto y : adj[x]) { if (y == pre) continue; v += currTree(y, x); } val[x] += v; return v; } bool stat(int x, int pre) { bool down = false; if (tmp[x]) down = true; for (auto y : adj[x]) { if (y == pre) continue; down |= stat(y, x); } if (!down) { if (!out[x] && val[x] < 0) lans++; } return down; } void update(int x, int v) {} int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m; for (int i = 2; i <= n; i++) { int p; cin >> p; adj[p].push_back(i); adj[i].push_back(p); } A = Tree(); for (int i = 1; i <= n; i++) cin >> val[i]; resv = val; for (int i = 0; i < m; i++) cin >> event[i]; sq = 460; s = (m - 1) / sq + 1; for (int b = 0; b < s; b++) { compress(b); lans = 0; stat(1, 0); for (int i = b * sq; i < (b + 1) * sq && i < m; i++) { if (event[i] < 0) out[-event[i]] = false; else out[event[i]] = true; int p = abs(event[i]); int v = abs(event[i]) / event[i]; while (p != 0) { lazy[p] += v; val[p] -= v; while (ptr[p].first > 0 && edge[p][ptr[p].first - 1].first >= lazy[p]) ptr[p] = {ptr[p].first - 1, ptr[p].second - edge[p][ptr[p].first - 1].second}; while (ptr[p].first < ((int)(edge[p]).size()) && edge[p][ptr[p].first].first < lazy[p]) ptr[p] = {ptr[p].first + 1, ptr[p].second + edge[p][ptr[p].first].second}; p = anc[p]; } ans = 0; int l = -1; for (auto x : temp) { if (x == l) continue; ans += ptr[x].second; if (!out[x] && val[x] < 0) ans++; l = x; } cout << lans + ans << ; } val = resv; currTree(1, 0); } cerr << 1.0 * clock() / CLOCKS_PER_SEC << endl; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cerr.tie(nullptr); int n, i, j, tmp, tmp2; cin >> n >> tmp; for (i = 1; i < n; i++) { cin >> tmp2; if (tmp == tmp2) { for (i = i + 1; i < n; i++) { cin >> tmp2; if (tmp > tmp2) { tmp = tmp2; for (i = i + 1; i < n; i++) { cin >> tmp2; if (tmp <= tmp2) { cout << NO << endl; return 0; } tmp = tmp2; } } else if (tmp < tmp2) { cout << NO << endl; return 0; } } } else if (tmp > tmp2) { tmp = tmp2; for (i = i + 1; i < n; i++) { cin >> tmp2; if (tmp <= tmp2) { cout << NO << endl; return 0; } tmp = tmp2; } } tmp = tmp2; } cout << YES << endl; return 0; }
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///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Dispatcher State Machine
// File : dex_smdisp.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Included by dex_sm.v
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module dex_smdisp
(
input de_clk,
input de_rstn,
input d_busy,
input cmdrdy,
input pcbusy,
input line_actv_1,
input blt_actv_1,
input noop_actv_2,
output reg goline,
output reg goblt,
output reg d_cmdack,
output reg d_cmdcpyclr,
output reg load_actvn,
// For test only.
output reg [1:0] d_cs
);
/****************************************************************/
/* DEFINE PARAMETERS */
/****************************************************************/
/* define state parameters */
parameter
IDLE=2'b00,
DECODE=2'b01,
BUSY=2'b10;
/* define internal wires and make assignments */
// reg [1:0] d_cs;
reg [1:0] d_ns;
/* create the state register */
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)d_cs <= 2'b0;
else d_cs <= d_ns;
end
reg igoblt;
reg igoline;
always @(posedge de_clk) goline <= igoline;
always @(posedge de_clk) goblt <= igoblt;
always @* begin
d_cmdack=1'b0;
d_cmdcpyclr=1'b0;
load_actvn=1'b1;
igoline=1'b0;
igoblt=1'b0;
case(d_cs) /* synopsys parallel_case */
IDLE: if(!cmdrdy || pcbusy)d_ns=IDLE;
else begin
load_actvn=1'b0;
d_cmdack=1'b1;
d_ns=DECODE;
if(line_actv_1) igoline=1'b1;
if(blt_actv_1) igoblt=1'b1;
end
DECODE: d_ns=BUSY;
BUSY: begin
if((noop_actv_2) || !d_busy)
begin
d_ns=IDLE;
d_cmdcpyclr=1'b1;
end
else d_ns=BUSY;
end
default: begin
d_ns=IDLE;
d_cmdcpyclr=1'b0;
load_actvn=1'b1;
d_cmdack=1'b0;
end
endcase
end
endmodule
|
`timescale 1ns/1ns
module menc_sincos
(input c,
input [13:0] menc,
input [10:0] offset,
input [7:0] poles,
output [31:0] sin,
output [31:0] cos);
wire toggle;
r toggle_r(.c(c), .en(1'b1), .rst(1'b0), .d(~toggle), .q(toggle));
wire [10:0] sin_addr, cos_addr;
d1 #(11) sin_addr_r(.c(c), .d(menc + offset), .q(sin_addr));
d1 #(11) cos_addr_r(.c(c), .d(menc + offset + 11'd512), .q(cos_addr));
wire [10:0] table_addr = toggle ? sin_addr : cos_addr;
wire [31:0] table_q;
sine_table_11bit_float32 table_inst
(.c(c), .angle(table_addr), .sine(table_q));
r #(32) sin_r(.c(c), .en(~toggle), .rst(1'b0), .d(~(~table_q)), .q(sin));
r #(32) cos_r(.c(c), .en( toggle), .rst(1'b0), .d(~(~table_q)), .q(cos));
endmodule
////////////////////////////////////////////////////////////////
`ifdef test_menc_sincos
module menc_sincos_tb();
wire c;
sim_clk #(125) clk_125(.clk(c));
reg [10:0] offset;
reg [10:0] menc;
wire [31:0] sin, cos;
menc_sincos dut(.*);
initial begin
$dumpfile("menc_sincos.lxt");
$dumpvars();
offset = 11'h0;
menc = 11'h50;
$display("testing...");
wait(c);
wait(~c);
#1000 $finish();
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A21O_FUNCTIONAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a21o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21O_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long inv_euclid(long long a, long long m = 998244353) { long long m0 = m; long long y = 0, x = 1; if (m == 1) return 0; while (a > 1) { long long q = a / m; long long t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long max(long long a, long long b) { if (a > b) return a; return b; } long long min(long long a, long long b) { if (a < b) return a; return b; } long long ssum(long long n) { return (n * (n + 1)) / 2; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return (a * b) / (gcd(a, b)); } void solve() { long long n; cin >> n; vector<long long> v(n); for (long long i = 0; i < n; i++) cin >> v[i]; while (v.size() && v[v.size() - 1] == 0) v.pop_back(); reverse(v.begin(), v.end()); while (v.size() && v[v.size() - 1] == 0) v.pop_back(); long long ans = 0; for (auto i : v) ans += (i == 0); cout << ans << n ; } int main() { long long tttt; cin >> tttt; while (tttt--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e3 + 100, inf = 1e15; long long dis[N][N][6], clr[6][6], ans = inf; queue<pair<int, int> > q[3]; char a[N][N]; bool mark[N][N][6]; pair<int, int> k; int ki, kj, n, m, x, y; int xx[] = {0, 1, 0, -1}, yy[] = {1, 0, -1, 0}; bool is_vallid(int x, int y) { if (x >= 0 && x < n && y >= 0 && y < m) return 1; return 0; } void init() { for (int i = 0; i < 3; i++) for (int j = 0; j < 3; j++) clr[i][j] = inf; for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) for (int c = 0; c < 4; c++) dis[i][j][c] = inf; } void bfs(int b) { while (!q[b].empty()) { k = q[b].front(); ki = k.first, kj = k.second; if (a[ki][kj] - 1 != b && a[ki][kj] != # && a[ki][kj] != . ) clr[b][a[ki][kj] - 1 ] = min(dis[ki][kj][b], clr[b][a[ki][kj] - 1 ]); for (int i = 0; i < 4; i++) { x = ki + xx[i], y = kj + yy[i]; if (is_vallid(x, y) && a[x][y] != # && !mark[x][y][b]) { q[b].push({x, y}); dis[x][y][b] = dis[ki][kj][b] + 1; mark[x][y][b] = 1; } } q[b].pop(); } } int main() { init(); cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> a[i][j]; if (a[i][j] != . && a[i][j] != # ) { q[a[i][j] - 1 ].push({i, j}); mark[i][j][a[i][j] - 1 ] = 1; dis[i][j][a[i][j] - 1 ] = 0; } } for (int i = 0; i < 3; i++) bfs(i); ans = min(min(clr[0][1] + clr[0][2], clr[1][0] + clr[1][2]), clr[2][0] + clr[2][1]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) ans = min(ans, dis[i][j][0] + dis[i][j][1] + dis[i][j][2]); if (ans >= inf) { cout << -1; return 0; } cout << ans - 2; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1N_1_V
`define SKY130_FD_SC_HDLL__INPUTISO1N_1_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog wrapper for inputiso1n with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inputiso1n.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inputiso1n_1 (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__inputiso1n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inputiso1n_1 (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__inputiso1n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1N_1_V
|
#include <bits/stdc++.h> using namespace std; int n, m; int table[1000][1000]; int main() { int k = 0; scanf( %d %d %d , &n, &m, &k); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { scanf( %d , &table[i][j]); } } while (k) { char command; int x, y; scanf( %c %d %d , &command, &x, &y); if (command == g ) printf( %d n , table[x - 1][y - 1]); else if (command == c ) for (int i = 0; i < n; ++i) swap(table[i][x - 1], table[i][y - 1]); else for (int i = 0; i < m; ++i) swap(table[x - 1][i], table[y - 1][i]); k--; } return 0; }
|
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