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// file: clk_gen_83M_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module clk_gen_83M_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 3;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
clk_gen_83M clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]),
.CLK_OUT3 (clk_int[3]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk[3] = clk_int[3];
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_82x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_82x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [81:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [81:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [81:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [81:0] q = sub_wire2[81:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 82,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "82"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "82"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "82"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 82 0 INPUT NODEFVAL data[81..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 82 0 OUTPUT NODEFVAL q[81..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 82 0 data 0 0 82 0
// Retrieval info: CONNECT: q 0 0 82 0 @q 0 0 82 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, turn; cin >> n >> k; turn = n / k; if (turn % 2) cout << YES << endl; else cout << NO << endl; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Sun Jun 18 18:22:31 2017
// Host : DESKTOP-GKPSR1F running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v
// Design : clk_wiz_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, reset, locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,reset,locked,clk_in1" */;
output clk_out1;
input reset;
output locked;
input clk_in1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; long long ans = 0; for (int i = (0); i < (n); ++i) { long long t, T, x, cost; cin >> t >> T >> x >> cost; if (t >= T) { ans += cost + m * x; continue; } long long aux1 = cost; if (m > (T - t)) aux1 += m * x; long long aux2 = (long long)ceil((double)(m - (T - t)) / (T - t)) + 1; aux2 *= cost; ans += min(aux1, aux2); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000010; long long N, S; long long fa[maxn], q[maxn], d[maxn], head, tail, sz[maxn], son[maxn]; bool check(long long Mid) { long long tN = N, now = 1, p = 1, res = 0; while (tN) { res += min(p, tN) * now; if (res > S) return false; tN -= min(p, tN); p *= Mid; now++; } return true; } int main() { cin >> N >> S; long long Mn = N + N - 1; long long Mx = N * (N + 1) / 2; if (S < Mn || S > Mx) return puts( NO ), 0; long long L = 1, R = N - 1, Mid, res; while (L <= R) { Mid = (L + R) / 2; if (check(Mid)) res = Mid, R = Mid - 1; else L = Mid + 1; } puts( YES ); for (int i = 1; i <= N; i++) sz[i] = 1; long long Now = Mx, D = 2; for (int i = N;; i--) { if (Now == S) break; if (sz[D] == sz[D - 1] * res) D++; if (Now - S >= i - D) { sz[D]++; sz[i]--; Now -= (i - D); } else { sz[i]--; sz[i - (Now - S)]++; Now = S; } } head = tail = 1; q[head] = 1; d[1] = 1; long long p = 1; for (int i = 2; i <= N; i++) { if (sz[i] == 0) break; L = p + 1; R = p + sz[i]; for (int j = L; j <= R; j++) { while (d[q[head]] != i - 1 || son[q[head]] == res) { head++; } fa[j] = q[head]; son[q[head]]++; q[++tail] = j; d[j] = i; } p = R; } for (int i = 2; i <= N; i++) printf( %lld , fa[i]); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_1_V
`define SKY130_FD_SC_LS__AND4BB_1_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4bb_1 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4bb_1 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_1_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3(clk, reset, ce, a, b, s);
// ---- input/output ports list here ----
input clk;
input reset;
input ce;
input [6 - 1 : 0] a;
input [6 - 1 : 0] b;
output [6 - 1 : 0] s;
// ---- register and wire type variables list here ----
// wire for the primary inputs
wire [6 - 1 : 0] a_reg;
wire [6 - 1 : 0] b_reg;
// wires for each small adder
wire [3 - 1 : 0] a0_cb;
wire [3 - 1 : 0] b0_cb;
wire [6 - 1 : 3] a1_cb;
wire [6 - 1 : 3] b1_cb;
// registers for input register array
reg [3 - 1 : 0] a1_cb_regi1[1 - 1 : 0];
reg [3 - 1 : 0] b1_cb_regi1[1 - 1 : 0];
// wires for each full adder sum
wire [6 - 1 : 0] fas;
// wires and register for carry out bit
wire faccout_ini;
wire faccout0_co0;
wire faccout1_co1;
reg faccout0_co0_reg;
// registers for output register array
reg [3 - 1 : 0] s0_ca_rego0[0 - 0 : 0];
// wire for the temporary output
wire [6 - 1 : 0] s_tmp;
// ---- RTL code for assignment statements/always blocks/module instantiations here ----
assign a_reg = a;
assign b_reg = b;
// small adder input assigments
assign a0_cb = a_reg[3 - 1 : 0];
assign b0_cb = b_reg[3 - 1 : 0];
assign a1_cb = a_reg[6 - 1 : 3];
assign b1_cb = b_reg[6 - 1 : 3];
// input register array
always @ (posedge clk) begin
if (ce) begin
a1_cb_regi1 [0] <= a1_cb;
b1_cb_regi1 [0] <= b1_cb;
end
end
// carry out bit processing
always @ (posedge clk) begin
if (ce) begin
faccout0_co0_reg <= faccout0_co0;
end
end
// small adder generation
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder u0 (
.faa ( a0_cb ),
.fab ( b0_cb ),
.facin ( faccout_ini ),
.fas ( fas[2:0] ),
.facout ( faccout0_co0 )
);
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f u1 (
.faa ( a1_cb_regi1[0] ),
.fab ( b1_cb_regi1[0] ),
.facin ( faccout0_co0_reg ),
.fas ( fas[5 :3] ),
.facout ( faccout1_co1 )
);
assign faccout_ini = 1'b0;
// output register array
always @ (posedge clk) begin
if (ce) begin
s0_ca_rego0 [0] <= fas[3-1 : 0];
end
end
// get the s_tmp, assign it to the primary output
assign s_tmp[3-1 : 0] = s0_ca_rego0[0];
assign s_tmp[6 - 1 : 3] = fas[5 :3];
assign s = s_tmp;
endmodule
// short adder
module nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder
#(parameter
N = 3
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
// the final stage short adder
module nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f
#(parameter
N = 3
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_6ns_6ns_6_2(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.s( dout ));
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:25:26 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xbar_1/zqynq_lab_1_design_xbar_1_stub.v
// Design : zqynq_lab_1_design_xbar_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2" *)
module zqynq_lab_1_design_xbar_1(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arlen,
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arregion,
m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rlast,
m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[127:0],m_axi_awlen[31:0],m_axi_awsize[11:0],m_axi_awburst[7:0],m_axi_awlock[3:0],m_axi_awcache[15:0],m_axi_awprot[11:0],m_axi_awregion[15:0],m_axi_awqos[15:0],m_axi_awvalid[3:0],m_axi_awready[3:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast[3:0],m_axi_wvalid[3:0],m_axi_wready[3:0],m_axi_bresp[7:0],m_axi_bvalid[3:0],m_axi_bready[3:0],m_axi_araddr[127:0],m_axi_arlen[31:0],m_axi_arsize[11:0],m_axi_arburst[7:0],m_axi_arlock[3:0],m_axi_arcache[15:0],m_axi_arprot[11:0],m_axi_arregion[15:0],m_axi_arqos[15:0],m_axi_arvalid[3:0],m_axi_arready[3:0],m_axi_rdata[127:0],m_axi_rresp[7:0],m_axi_rlast[3:0],m_axi_rvalid[3:0],m_axi_rready[3:0]" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [127:0]m_axi_awaddr;
output [31:0]m_axi_awlen;
output [11:0]m_axi_awsize;
output [7:0]m_axi_awburst;
output [3:0]m_axi_awlock;
output [15:0]m_axi_awcache;
output [11:0]m_axi_awprot;
output [15:0]m_axi_awregion;
output [15:0]m_axi_awqos;
output [3:0]m_axi_awvalid;
input [3:0]m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output [3:0]m_axi_wlast;
output [3:0]m_axi_wvalid;
input [3:0]m_axi_wready;
input [7:0]m_axi_bresp;
input [3:0]m_axi_bvalid;
output [3:0]m_axi_bready;
output [127:0]m_axi_araddr;
output [31:0]m_axi_arlen;
output [11:0]m_axi_arsize;
output [7:0]m_axi_arburst;
output [3:0]m_axi_arlock;
output [15:0]m_axi_arcache;
output [11:0]m_axi_arprot;
output [15:0]m_axi_arregion;
output [15:0]m_axi_arqos;
output [3:0]m_axi_arvalid;
input [3:0]m_axi_arready;
input [127:0]m_axi_rdata;
input [7:0]m_axi_rresp;
input [3:0]m_axi_rlast;
input [3:0]m_axi_rvalid;
output [3:0]m_axi_rready;
endmodule
|
`timescale 1ns / 1ps
module mem_stage (
input clk,
input rst,
input mem_read,
input mem_write,
input [31:0] alu_result,
input [31:0] B,
input [4:0] dst_reg,
input wb_reg_write,
input wb_mem_to_reg,
input pstop_i,
output reg [4:0] MEM_WB_dst_reg,
output reg MEM_WB_reg_write,
output reg MEM_WB_mem_to_reg,
output reg [31:0] MEM_WB_mem_out,
output reg [31:0] MEM_WB_alu_out,
// Memory Interface
output d_read_en,
output d_write_en,
output [31:0] d_addr,
output [31:0] d_write_data,
input [31:0] d_data_in
);
assign d_read_en = mem_read;
assign d_write_en = mem_write;
assign d_addr = alu_result;
assign d_write_data = B;
/*
MEM/WB Pipeline register
*/
always @(posedge clk) begin
if (rst)
begin
MEM_WB_dst_reg <= 0;
MEM_WB_reg_write <= 0;
MEM_WB_mem_to_reg <= 0;
MEM_WB_mem_out <= 0;
MEM_WB_alu_out <= 0;
end
else
begin
MEM_WB_dst_reg <= dst_reg;
MEM_WB_reg_write <= wb_reg_write;
MEM_WB_mem_to_reg <= wb_mem_to_reg;
MEM_WB_mem_out <= d_data_in;
MEM_WB_alu_out <= alu_result;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 59; struct State { char c[MAX_N][MAX_N]; }; int H, W; vector<pair<int, int>> solve(State S) { vector<pair<int, int>> D; for (int t = 1; t <= 100000; t++) { bool flag = false; if (H % 2 == 0) { for (int i = 1; i <= H; i++) { for (int j = 1; j <= W; j++) { if (i % 2 == 1 && S.c[i][j] != U ) flag = true; if (i % 2 == 0 && S.c[i][j] != D ) flag = true; } } } else { for (int i = 1; i <= H; i++) { for (int j = 1; j <= W; j++) { if (j % 2 == 1 && S.c[i][j] != L ) flag = true; if (j % 2 == 0 && S.c[i][j] != R ) flag = true; } } } if (flag == false) return D; for (int i = 1; i <= H - 1; i++) { for (int j = 1; j <= W - 1; j++) { if (t % 2 == 1) { if (S.c[i][j] == U && S.c[i][j + 1] == U && S.c[i + 1][j] == D && S.c[i + 1][j + 1] == D ) { S.c[i + 0][j + 0] = L ; S.c[i + 0][j + 1] = R ; S.c[i + 1][j + 0] = L ; S.c[i + 1][j + 1] = R ; D.push_back(make_pair(i, j)); } } if (t % 2 == 0) { if (S.c[i][j] == L && S.c[i][j + 1] == R && S.c[i + 1][j] == L && S.c[i + 1][j + 1] == R ) { S.c[i + 0][j + 0] = U ; S.c[i + 0][j + 1] = U ; S.c[i + 1][j + 0] = D ; S.c[i + 1][j + 1] = D ; D.push_back(make_pair(i, j)); } } } } } return D; } int main() { cin >> H >> W; State T, U; for (int i = 1; i <= H; i++) { for (int j = 1; j <= W; j++) cin >> T.c[i][j]; } vector<pair<int, int>> D1 = solve(T); for (int i = 1; i <= H; i++) { for (int j = 1; j <= W; j++) cin >> U.c[i][j]; } vector<pair<int, int>> D2 = solve(U); vector<pair<int, int>> D3 = D1; for (int i = D2.size() - 1; i >= 0; i--) D3.push_back(D2[i]); cout << D3.size() << endl; for (int i = 0; i < D3.size(); i++) cout << D3[i].first << << D3[i].second << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, k, l, r, mid, ans; long long a[200100]; bool check(long long x) { long long p, q; double sum = 0, s; for (long long i = 1; i <= n; i++) { if (a[i] == 0) continue; s = a[i]; if (a[i] >= k) return 1; p = x - 1; q = n - i + x - 1; p = min(p, q - p); while (p) { s = s * q / p; p--; q--; if (s >= k) return 1; } sum += s; if (sum >= k) return 1; } return 0; } int main() { scanf( %I64d%I64d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %I64d , &a[i]); if (a[i] >= k) { puts( 0 ); return 0; } } l = 1; r = k; while (l <= r) { mid = (l + r) >> 1; if (check(mid)) { ans = mid; r = mid - 1; } else l = mid + 1; } printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[] = {0, 1, 2, 3, 4}; int lst[5][5]; for (int i = 0; i < 5; i++) for (int j = 0; j < 5; j++) scanf( %d , &lst[i][j]); int ANS = 0; do { int sum = lst[a[0]][a[1]] + lst[a[1]][a[0]] + lst[a[1]][a[2]] + lst[a[2]][a[1]] + 2 * (lst[a[3]][a[4]] + lst[a[4]][a[3]] + lst[a[2]][a[3]] + lst[a[3]][a[2]]); ANS = max(sum, ANS); } while (next_permutation(a, a + 5)); cout << ANS; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 15:46:53 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_1/system_ov7670_vga_0_1_stub.v
// Design : system_ov7670_vga_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_vga,Vivado 2016.4" *)
module system_ov7670_vga_0_1(pclk, data, rgb)
/* synthesis syn_black_box black_box_pad_pin="pclk,data[7:0],rgb[15:0]" */;
input pclk;
input [7:0]data;
output [15:0]rgb;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// too bad- we have to do this!
`timescale 1ns/100ps
module util_ccat (
data_0,
data_1,
data_2,
data_3,
data_4,
data_5,
data_6,
data_7,
ccat_data);
// parameters
parameter CH_DW = 1;
parameter CH_CNT = 8;
localparam CH_MCNT = 8;
// interface
input [(CH_DW-1):0] data_0;
input [(CH_DW-1):0] data_1;
input [(CH_DW-1):0] data_2;
input [(CH_DW-1):0] data_3;
input [(CH_DW-1):0] data_4;
input [(CH_DW-1):0] data_5;
input [(CH_DW-1):0] data_6;
input [(CH_DW-1):0] data_7;
output [((CH_CNT*CH_DW)-1):0] ccat_data;
// internal signals
wire [((CH_MCNT*CH_DW)-1):0] data_s;
// concatenate
assign data_s[((CH_DW*1)-1):(CH_DW*0)] = data_0;
assign data_s[((CH_DW*2)-1):(CH_DW*1)] = data_1;
assign data_s[((CH_DW*3)-1):(CH_DW*2)] = data_2;
assign data_s[((CH_DW*4)-1):(CH_DW*3)] = data_3;
assign data_s[((CH_DW*5)-1):(CH_DW*4)] = data_4;
assign data_s[((CH_DW*6)-1):(CH_DW*5)] = data_5;
assign data_s[((CH_DW*7)-1):(CH_DW*6)] = data_6;
assign data_s[((CH_DW*8)-1):(CH_DW*7)] = data_7;
assign ccat_data = data_s[((CH_CNT*CH_DW)-1):0];
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void smax(T &x, T y) { x = max((x), (y)); } template <class T> inline void smin(T &x, T y) { x = min((x), (y)); } inline void scanInt(int &x) { register char c = getchar(); x = 0; bool neg = false; while (c < 48 || c > 57) { if (c == - ) neg = true; c = getchar(); } for (; c > 47 && c < 58; c = getchar()) { x = (x << 1) + (x << 3) + c - 48; } if (neg) x *= -1; } int n, m; string origin; string s; bool place_char_start(int inx) { if (inx >= 2) { for (char i = s[inx] + 1; i < a + m; i++) if (i != s[inx - 1] && i != s[inx - 2] && i != s[inx]) { s[inx] = i; return true; } return false; } else if (inx == 1) { for (char i = s[inx] + 1; i < a + m; i++) if (i != s[inx - 1] && i != s[inx]) { s[inx] = i; return true; } return false; } else if (inx == 0) { s[0] = s[0] + 1; if (s[0] >= a + m) return false; return true; } return false; } bool place_char(int inx) { if (inx >= 2) { for (char i = a ; i < a + m; i++) if (i != s[inx - 1] && i != s[inx - 2]) { s[inx] = i; return true; } return false; } else if (inx == 1) { for (char i = a ; i < a + m; i++) if (i != s[inx - 1]) { s[inx] = i; return true; } } else if (inx == 0) { s[0] = a ; return true; } return false; } int main(int argc, const char *argv[]) { scanInt(n); scanInt(m); cin >> s; origin = s; for (int i = (int)s.size() - 1; i >= 0; i--) { s = origin; bool ok = true; ok &= place_char_start(i); for (int j = i + 1; ok && j < s.size(); j++) { if (place_char(j) == false) ok = false; } if (ok) { cout << s; return 0; } } cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { string ch; cin >> ch; long long int ans = 0; int x = 0, y = 0; set<pair<pair<int, int>, pair<int, int>>> s; pair<int, int> prev = {0, 0}; for (int i = 0; i < (int)ch.size(); i++) { if (ch[i] == N ) y++; else if (ch[i] == S ) y--; else if (ch[i] == W ) x--; else x++; bool check = false; if (s.count({prev, {x, y}}) || s.count({{x, y}, prev})) ans++; else { s.insert({prev, {x, y}}); s.insert({{x, y}, prev}); ans += 5; } prev = {x, y}; } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; char g[8][8]; int calc(int x, int y, int a, int d) { int res = 0; while (x != d) { x += a; ++res; if (g[x][y] != . ) return 2e9; } return res; } int main() { for (int i = 0; i < 8; ++i) scanf( %s , g[i]); int a = 2e9, b = 2e9; for (int i = 0; i < 8; ++i) for (int j = 0; j < 8; ++j) { if (g[i][j] == W ) a = min(a, calc(i, j, -1, 0)); if (g[i][j] == B ) b = min(b, calc(i, j, 1, 7)); } if (a <= b) puts( A ); else puts( B ); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, k; int haha[105]; int ans = 0; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , &haha[i]); if (haha[i] == 0) break; else if (i < k) ans++; else if (haha[i] == haha[k - 1]) ans++; else break; } printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; struct node { long long x, y; } s, t, dist[100005]; int dx[4] = {0, 0, -1, 1}; int dy[4] = {1, -1, 0, 0}; char wind[100005]; string mov = UDLR ; long long pos, l, r, mid; bool check(long long mid) { long long zq = mid / n, sy = mid % n; long long x = s.x + zq * dist[n].x + dist[sy].x; long long y = s.y + zq * dist[n].y + dist[sy].y; long long dis = abs(t.x - x) + abs(t.y - y); return dis <= mid; } int main() { cin >> s.x >> s.y >> t.x >> t.y; cin >> n >> wind; for (int i = 0; i < n; i++) { pos = -1; for (int j = 0; j < 4; j++) { if (wind[i] == mov[j]) pos = j; } dist[i + 1].x = dist[i].x + dx[pos]; dist[i + 1].y = dist[i].y + dy[pos]; } l = 0, r = 1e15; while (l <= r) { mid = (l + r) >> 1; if (check(mid)) { r = mid - 1; } else { l = mid + 1; } } if (l > 1e15) cout << -1 << endl; else cout << l << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; long long a, b; map<long long, bool> mp; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); for (long long i = 1; i <= 1000; i++) mp[i * i] = 1; cin >> a >> b; for (long long i = -1; i > -a; i--) { if (mp[a * a - i * i] == 0) continue; long long j = sqrt(a * a - i * i); for (long long x = 1; x < b; x++) { if (mp[b * b - x * x] == 0) continue; long long y = sqrt(b * b - x * x); if (-i * x == j * y && j != y) { cout << YES n ; cout << 0 << << 0 << endl; cout << i << << j << endl; cout << x << << y; return 0; } } } cout << NO ; return 0; }
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#include <bits/stdc++.h> using namespace std; void solve() { long long a, b; cin >> a >> b; if ((a + b) % 3 != 0) { cout << NO << endl; return; } long long mi = min(a, b); long long mx = max(a, b); long long d = mx - mi; if (mx > 2 * mi) { cout << NO << endl; } else { cout << YES << endl; } } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(NULL); long long t; cin >> t; while (t--) { solve(); } }
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// fpgaTop_ml555.v - ssiegel 2009-03-17
module fpgaTop(
input wire sys0_clkp, // sys0 Clock +
input wire sys0_clkn, // sys0 Clock -
input wire pci0_clkp, // PCIe Clock +
input wire pci0_clkn, // PCIe Clock -
input wire pci0_rstn, // PCIe Reset
output wire [7:0] pci_exp_txp, // PCIe lanes...
output wire [7:0] pci_exp_txn,
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [2:0] led, // LEDs ml555
input wire ppsExtIn, // PPS in
output wire ppsOut // PPS out
);
// Instance and connect mkFTop...
mkFTop_ml555 ftop(
.sys0_clkp (sys0_clkp),
.sys0_clkn (sys0_clkn),
.pci0_clkp (pci0_clkp),
.pci0_clkn (pci0_clkn),
.pci0_rstn (pci0_rstn),
.pcie_rxp_i (pci_exp_rxp),
.pcie_rxn_i (pci_exp_rxn),
.pcie_txp (pci_exp_txp),
.pcie_txn (pci_exp_txn),
.led (led),
.gps_ppsSyncIn_x (ppsExtIn),
.gps_ppsSyncOut (ppsOut)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> int n, a[500005], L[500005], f[500005][22], g[500005][22]; long long ans; int get(int x, int y) { if (x < 0) return 0; int k = (int)log2(y - x + 1); return L[f[x][k]] <= L[f[y + 1 - (1 << k)][k]] ? f[x][k] : f[y + 1 - (1 << k)][k]; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]), a[n + i] = a[i]; for (int i = 0; i < n + n; i++) L[i] = i - a[i], f[i][0] = i; for (int j = 0; j < 19; j++) for (int i = 0; i < n + n - (1 << j); i++) f[i][j + 1] = L[f[i][j]] <= L[f[i + (1 << j)][j]] ? f[i][j] : f[i + (1 << j)][j]; for (int i = 0; i < n + n; i++) g[i][0] = get(L[i], i); for (int j = 0; j < 19; j++) for (int i = 0; i < n + n; i++) g[i][j + 1] = g[g[i][j]][j]; for (int i = 0; i < n + n; i++) if (i >= n) { int x = i; ans += 1 + (L[i] > i - n + 1); for (int j = 19; j >= 0; j--) if (L[g[x][j]] > i - n + 1) x = g[x][j], ans += 1 << j; } printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 5005; int n, m, ans[N]; pair<int, int> p[N]; vector<pair<int, int> > g[N]; void dfs(int v, int pr = -1) { for (auto it : g[v]) { int to = it.first; if (to != pr) { p[to] = make_pair(v, it.second); dfs(to, v); } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; g[x].push_back(make_pair(y, i)); g[y].push_back(make_pair(x, i)); } cin >> m; vector<pair<int, pair<int, int> > > e; for (int i = 1; i <= m; i++) { int x, y, z; cin >> x >> y >> z; e.push_back(make_pair(z, make_pair(x, y))); } sort(e.begin(), e.end()); for (auto it : e) { int x = it.second.first, y = it.second.second, val = it.first; dfs(x); while (y != x) { ans[p[y].second] = it.first; y = p[y].first; } } for (auto it : e) { int x = it.second.first, y = it.second.second, val = it.first; dfs(x); int mn = 1e9; while (y != x) { mn = min(mn, ans[p[y].second]); y = p[y].first; } if (mn != val) { return cout << -1 , 0; } } for (int i = 1; i < n; i++) { cout << (ans[i] == 0 ? (int)1e6 : ans[i]) << ; } }
|
#include <bits/stdc++.h> class point2D { public: long long x, y; point2D() {} point2D(long long x, long long y) : x(x), y(y) {} bool operator<(const point2D &other) const { return ((y == other.y) ? (x > other.x) : (y > other.y)); } }; point2D operator-(const point2D &u, const point2D &v) { return point2D(u.x - v.x, u.y - v.y); } long long det(const point2D &u, const point2D &v) { return u.x * v.y - v.x * u.y; } long long dir(const point2D &p, const point2D &u, const point2D &v) { return det(u - p, v - p); } bool contains(int n, point2D vertex, point2D polygon[]) { int l = 1, r = n - 1, m; while (l < r) { m = (l + r) / 2; if (dir(polygon[0], polygon[m], vertex) <= 0) r = m; else l = m + 1; } if (r == 1 || dir(polygon[0], polygon[n - 1], vertex) >= 0 || dir(polygon[r], polygon[r - 1], vertex) >= 0) return 0; return 1; } int n, m; point2D polygonA[100000], vertexB; int main() { std::cin >> n; for (int i = n - 1; i >= 0; i--) { std::cin >> polygonA[i].x >> polygonA[i].y; } std::cin >> m; for (int i = 0; i < m; i++) { std::cin >> vertexB.x >> vertexB.y; if (!contains(n, vertexB, polygonA)) { std::cout << NO << std::endl; return 0; } } std::cout << YES << std::endl; return 0; }
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK keyboard
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
// Modified by: Andy Karpov <>
// Added PS2Controller with debouncer and error checking
//
// Design File: rk_kbd.v
//
module rk_kbd(
input clk,
input reset,
inout ps2_clk,
inout ps2_dat,
input[7:0] addr,
output reg[7:0] odata,
output[2:0] shift);
reg scancode_ready;
reg[9:0] scancode;
reg[2:0] shifts;
assign shift = shifts[2:0];
Keyboard kbd(
.Reset(reset), .Clock(clk),
.PS2Clock(ps2_clk), .PS2Data(ps2_dat),
.CodeReady(scancode_ready), .ScanCode(scancode)
);
reg[7:0] keymatrix[7:0]; // multi-dimensional array of key matrix
always @(addr,keymatrix) begin
odata =
(keymatrix[0] & {8{addr[0]}})|
(keymatrix[1] & {8{addr[1]}})|
(keymatrix[2] & {8{addr[2]}})|
(keymatrix[3] & {8{addr[3]}})|
(keymatrix[4] & {8{addr[4]}})|
(keymatrix[5] & {8{addr[5]}})|
(keymatrix[6] & {8{addr[6]}})|
(keymatrix[7] & {8{addr[7]}});
end
reg[2:0] c;
reg[3:0] r;
always @(*) begin
case (scancode[7:0])
8'h6C: {c,r} = 7'h00; // 7 home
8'h7D: {c,r} = 7'h10; // 9 pgup
8'h76: {c,r} = 7'h20; // esc
8'h05: {c,r} = 7'h30; // F1
8'h06: {c,r} = 7'h40; // F2
8'h04: {c,r} = 7'h50; // F3
8'h0C: {c,r} = 7'h60; // F4
8'h03: {c,r} = 7'h70; // F5
8'h0D: {c,r} = 7'h01; // tab
8'h71: {c,r} = 7'h11; // . del
8'h5A: {c,r} = 7'h21; // enter
8'h66: {c,r} = 7'h31; // bksp
8'h6B: {c,r} = 7'h41; // 4 left
8'h75: {c,r} = 7'h51; // 8 up
8'h74: {c,r} = 7'h61; // 6 right
8'h72: {c,r} = 7'h71; // 2 down
8'h45: {c,r} = 7'h02; // 0
8'h16: {c,r} = 7'h12; // 1
8'h1E: {c,r} = 7'h22; // 2
8'h26: {c,r} = 7'h32; // 3
8'h25: {c,r} = 7'h42; // 4
8'h2E: {c,r} = 7'h52; // 5
8'h36: {c,r} = 7'h62; // 6
8'h3D: {c,r} = 7'h72; // 7
8'h3E: {c,r} = 7'h03; // 8
8'h46: {c,r} = 7'h13; // 9
8'h55: {c,r} = 7'h23; // =
8'h0E: {c,r} = 7'h33; // `
8'h41: {c,r} = 7'h43; // ,
8'h4E: {c,r} = 7'h53; // -
8'h49: {c,r} = 7'h63; // .
8'h4A: {c,r} = 7'h73; // gray/ + /
8'h4C: {c,r} = 7'h04; // ;
8'h1C: {c,r} = 7'h14; // A
8'h32: {c,r} = 7'h24; // B
8'h21: {c,r} = 7'h34; // C
8'h23: {c,r} = 7'h44; // D
8'h24: {c,r} = 7'h54; // E
8'h2B: {c,r} = 7'h64; // F
8'h34: {c,r} = 7'h74; // G
8'h33: {c,r} = 7'h05; // H
8'h43: {c,r} = 7'h15; // I
8'h3B: {c,r} = 7'h25; // J
8'h42: {c,r} = 7'h35; // K
8'h4B: {c,r} = 7'h45; // L
8'h3A: {c,r} = 7'h55; // M
8'h31: {c,r} = 7'h65; // N
8'h44: {c,r} = 7'h75; // O
8'h4D: {c,r} = 7'h06; // P
8'h15: {c,r} = 7'h16; // Q
8'h2D: {c,r} = 7'h26; // R
8'h1B: {c,r} = 7'h36; // S
8'h2C: {c,r} = 7'h46; // T
8'h3C: {c,r} = 7'h56; // U
8'h2A: {c,r} = 7'h66; // V
8'h1D: {c,r} = 7'h76; // W
8'h22: {c,r} = 7'h07; // X
8'h35: {c,r} = 7'h17; // Y
8'h1A: {c,r} = 7'h27; // Z
8'h54: {c,r} = 7'h37; // [
8'h52: {c,r} = 7'h47; // '
8'h5B: {c,r} = 7'h57; // ]
8'h5D: {c,r} = 7'h67; // \!
8'h29: {c,r} = 7'h77; // space
8'h12: {c,r} = 7'h08; // lshift
8'h59: {c,r} = 7'h08; // rshift
8'h14: {c,r} = 7'h18; // rctrl + lctrl
8'h11: {c,r} = 7'h28; // lalt
/* 8'h0B: {c,r} = 7'h50; // F6
8'h83: {c,r} = 7'h70; // F7
8'h0A: {c,r} = 7'h12; // F8
8'h01: {c,r} = 7'h33; // F9
8'h07: {c,r} = 7'h56; // F12 - stop
8'h7C: {c,r} = 7'h46; // gray*
8'h7B: {c,r} = 7'h66; // gray-
8'h78: {c,r} = 7'h67; // F11 - rus
8'h73: {c,r} = 7'h28; // 5 center
8'h7A: {c,r} = 7'h48; // 3 pgdn
8'h69: {c,r} = 7'h68; // 1 end
8'h70: {c,r} = 7'h78; // 0 ins
*/ default: {c,r} = 7'h7F;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
keymatrix[0] <= 0;
keymatrix[1] <= 0;
keymatrix[2] <= 0;
keymatrix[3] <= 0;
keymatrix[4] <= 0;
keymatrix[5] <= 0;
keymatrix[6] <= 0;
keymatrix[7] <= 0;
shifts[2:0] <= 3'b0;
end else begin
if(r!=4'hF && scancode_ready) keymatrix[r][c] <= ~scancode[8];
if (scancode_ready) // extended e0
begin
case (scancode[7:0])
8'h12: shifts[0] = ~scancode[8]; // lshift
8'h59: shifts[0] = ~scancode[8]; // rshift
8'h14: shifts[1] = ~scancode[8]; // rctrl + lctrl
8'h11: shifts[2] = ~scancode[8]; // lalt
//default:
// shifts[2:0] = 3'b0;
endcase
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const int maxn = 2e6 + 5; int n, m, k; int last[30], dp[maxn]; char s[maxn]; int main() { scanf( %d%d%s , &n, &k, s + 1); m = strlen(s + 1); n += m; memset(last, -1, sizeof(last)); dp[0] = 1; for (int i = (1); i <= (n); ++i) { if (i <= m) if (~last[s[i] - a ]) dp[i] = (dp[i - 1] * 2 % INF + INF - dp[last[s[i] - a ] - 1]) % INF; else dp[i] = dp[i - 1] * 2 % INF; else { int mn = 0; for (int j = (0); j < (k); ++j) if (last[mn] > last[j]) mn = j; if (~last[mn]) dp[i] = (dp[i - 1] * 2 % INF + INF - dp[last[mn] - 1]) % INF; else dp[i] = dp[i - 1] * 2 % INF; s[i] = mn + a ; } last[s[i] - a ] = i; } printf( %d n , dp[n]); return 0; }
|
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ()
//
// Copyright (c) 2004 Guy Hutchison ()
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// Negative-edge based wrapper allows memory wait_n signal to work
// correctly without resorting to asynchronous logic.
module tv80a (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 1; // 1 => wr_n active in T3, 0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] dout;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
wire cen;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
assign cen = 1;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.dout (dout),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n)
);
reg [6:0] tstate_r = 7'h00;
reg [6:0] tstate_rr = 7'h00;
always @(negedge clk) begin
tstate_r <= tstate;
end
always @(posedge clk) begin
tstate_rr <= tstate;
end
wire mreq_read = ~iorq & ~no_read & ~write;
wire mreq_write = ~iorq & ~no_read & write;
wire iorq_read = iorq & ~no_read & ~write;
wire iorq_write = iorq & ~no_read & write;
always @* begin
mreq_n = 1;
rd_n = 1;
iorq_n = 1;
wr_n = 1;
if (mcycle[0]) begin
if (intcycle_n == 1'b1) begin
if (tstate_r[1] || tstate[2]) begin
mreq_n = 1'b0;
rd_n = 1'b0;
end
else if (rfsh_n == 1'b0 && tstate_r[3]) begin
mreq_n = 1'b0;
end
end
else begin
if (tstate[2]) begin
iorq_n = 1'b0;
end
end
end
else begin
if (mreq_read == 1'b1) begin
if (tstate_r[1] || tstate_r[2]) begin
mreq_n = 1'b0;
rd_n = 1'b0;
end
end
else if (mreq_write == 1'b1) begin
if (tstate_r[1] || tstate_r[2]) begin
mreq_n = 1'b0;
if (tstate_r[2]) begin
wr_n = 1'b0;
end
end
end
else if (iorq_read == 1'b1) begin
if (tstate_rr[1] || tstate_r[2]) begin
iorq_n = 1'b0;
rd_n = 1'b0;
end
end
else if (iorq_write == 1'b1) begin
if (tstate_rr[1] || tstate_r[2]) begin
iorq_n = 1'b0;
wr_n = 1'b0;
end
end
end
end
always @(posedge clk) begin
if (!reset_n) begin
di_reg <= #1 0;
end
else begin
if (tstate[2] && wait_n == 1'b1)
di_reg <= #1 di;
end // else: !if(!reset_n)
end // always @ (posedge clk)
endmodule // t80n
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [1:0] reg_i;
reg [1049:0] pad0;
reg [1049:0] reg_o;
reg [1049:0] spad1;
/*AUTOWIRE*/
always_comb begin
if (reg_i[1] == 1'b1)
reg_o = {986'd0, 64'hffff0000ffff0000};
else if (reg_i[0] == 1'b1)
reg_o = {64'hffff0000ffff0000, 986'd0};
else
reg_o = 1050'd0;
end
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 0) begin
reg_i <= 2'b00;
pad0 <= '1;
spad1 <= '1;
end
else if (cyc == 1) begin
reg_i <= 2'b01;
end
else if (cyc == 2) begin
if (reg_o != {64'hffff0000ffff0000, 986'd0}) $stop;
reg_i <= 2'b10;
end
else if (cyc == 99) begin
if (reg_o != {986'd0, 64'hffff0000ffff0000}) $stop;
if (pad0 != '1) $stop;
if (spad1 != '1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:15:37 04/08/2015
// Design Name: inst_decoder
// Module Name: S:/Xilinx/finalproject/inst_decoder_tb.v
// Project Name: finalproject
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: inst_decoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module processor_tb;
parameter CONTROL_WIDTH = 4; // width of the tag
parameter ADDR_WIDTH = 4; // width of the data
parameter DATA_WIDTH = 8; // width of the data
parameter LINE_WIDTH = CONTROL_WIDTH+ADDR_WIDTH+ADDR_WIDTH; // length of the input vector
parameter HALT = 1'b0;
parameter START = 1'b1;
parameter BUS_GRANTED = 1'b1;
parameter BUS_NOT_GRANTED = 1'b0;
// Inputs
reg [LINE_WIDTH-1:0]vector_in;
reg clk;
reg reset;
reg [DATA_WIDTH-1:0]data;
reg bus_grant;
// Outputs
wire bus_request;
wire status;
wire [ADDR_WIDTH-1:0]addr;
wire [DATA_WIDTH-1:0]alu_out;
// Instantiate the Unit Under Test (UUT)
processor #(CONTROL_WIDTH,ADDR_WIDTH) P1 (
.alu_out(alu_out),
.addr_out(addr),
.bus_request_out(bus_request),
.status_out(status),
.vector_in(vector_in),
.bus_grant_in(bus_grant),
.reset_in(reset),
.data_in(data),
.clk(clk)
);
initial begin
// Initialize Inputs
clk = 1;
reset = 1;
vector_in = 0;
bus_grant = 0;
// Wait 100 ns for global reset to finish
// #100;
// Add stimulus here
#2 reset = 0; vector_in = 12'b0001_0000_0101;
#2 vector_in = 12'b0010_1101_1011;
#2 vector_in = 12'b0111_1000_1111;
#4 bus_grant = BUS_GRANTED;
#2 data = 8'b01010101;
#2 data = 8'b10101010; bus_grant = BUS_NOT_GRANTED;
#2 vector_in = 12'b1010_0001_0110;
// #12 bus_grant = `BUS_GRANTED;
// #14 bus_grant = `BUS_NOT_GRANTED;
$monitor("alu_out:%d",alu_out);
#20 $finish;
end
always@(status) begin
if(status == HALT)
begin
vector_in = 12'b0010_1101_1011;
end
// else begin
// #2 reset = 0; vector_in = 12'b0001_0000_0101;
// #2 vector_in = 12'b0010_1101_1011;
// #2 vector_in = 12'b0111_1000_1111;
// #4 bus_grant = BUS_GRANTED;
// #2 data = 8'b01010101;
// #2 data = 8'b10101010; bus_grant = BUS_NOT_GRANTED;
// #2 vector_in = 12'b1010_0001_0110;
// else
end
always begin
#1 clk = ~clk; // Toggle clock every 1 ticks
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool ispos(long long x, long long y, long long n, long long m) { if (x < 0 or x >= n or y < 0 or y >= m) return false; else return true; } signed solve() { long long n, m; cin >> n >> m; string s[n]; for (long long i = 0; i < n; i++) cin >> s[i]; char a[n][m]; vector<pair<pair<long long, long long>, long long>> v; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) a[i][j] = . ; } for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { long long sz = 0; if (s[i][j] == * ) { for (long long k = 1; k <= max(n, m); k++) { if (ispos(i - k, j, n, m) and s[i - k][j] == * and ispos(i, j - k, n, m) and s[i][j - k] == * and ispos(i + k, j, n, m) and s[i + k][j] == * and ispos(i, j + k, n, m) and s[i][j + k] == * ) { sz++; } else break; } } if (sz > 0) { a[i][j] = * ; v.push_back({{i + 1, j + 1}, sz}); for (long long k = 1; k <= sz; k++) { a[i - k][j] = * ; a[i + k][j] = * ; a[i][j - k] = * ; a[i][j + k] = * ; } } } } for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { if (s[i][j] != a[i][j]) { cout << -1 << n ; return 0; } } } cout << v.size() << n ; for (long long i = 0; i < v.size(); i++) { cout << v[i].first.first << << v[i].first.second << << v[i].second << n ; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long tests = 1; while (tests--) { solve(); } }
|
#include <bits/stdc++.h> const unsigned long long maxn = 70; unsigned long long n, flg, KKK, ans; unsigned long long f[maxn], mul10[maxn], cycle[maxn], a[maxn]; struct matrix { unsigned long long len, wid; unsigned long long mt[3][3]; } pre[14][45]; inline unsigned long long min(unsigned long long a, unsigned long long b) { return a < b ? a : b; } unsigned long long modmul(unsigned long long a, unsigned long long b, unsigned long long mod) { unsigned long long res = 0; while (b) { if (b & 1) { res += a; if (res > mod) res -= mod; } a += a; if (a > mod) a -= mod; b >>= 1; } return res; } matrix mul(matrix a, matrix b, unsigned long long mod) { matrix res; res.len = a.len, res.wid = b.wid; for (unsigned long long u = 1; u <= a.len; u++) for (unsigned long long v = 1; v <= b.wid; v++) res.mt[u][v] = 0; for (unsigned long long u = 1; u <= a.len; u++) for (unsigned long long v = 1; v <= b.wid; v++) for (unsigned long long w = 1; w <= a.wid; w++) res.mt[u][v] = (res.mt[u][v] + modmul(a.mt[u][w], b.mt[w][v], mod)) % mod; return res; } unsigned long long calc(unsigned long long b, unsigned long long kk, unsigned long long mod) { matrix a, res; res.len = 1, res.wid = 2, res.mt[1][1] = 0, res.mt[1][2] = 1; for (unsigned long long i = 0; i <= 44; i++) if ((b >> i) & 1) res = mul(res, pre[kk][i], mod); return res.mt[1][1]; } void dfs(unsigned long long len, unsigned long long now) { if (now > ans) return; if (len == n + 1) { flg = 1, ans = min(ans, now); return; } for (unsigned long long i = 0; i < 10; i++) { unsigned long long k = (modmul(i, cycle[len], cycle[len + 1]) + now) % cycle[len + 1]; if (calc(k, len, mul10[len]) == a[len]) dfs(len + 1, k); } } signed main() { f[0] = 0, f[1] = 1; for (unsigned long long i = 2; i <= 60; i++) f[i] = f[i - 1] + f[i - 2]; cycle[0] = 6, mul10[0] = 1; for (unsigned long long i = 1; i <= 19; i++) cycle[i] = 10ll * cycle[i - 1], mul10[i] = 10ll * mul10[i - 1]; for (unsigned long long i = 1; i <= 13; i++) { pre[i][0].len = pre[i][0].wid = 2, pre[i][0].mt[1][1] = 0, pre[i][0].mt[1][2] = pre[i][0].mt[2][1] = pre[i][0].mt[2][2] = 1; for (unsigned long long j = 1; j <= 44; j++) pre[i][j] = mul(pre[i][j - 1], pre[i][j - 1], mul10[i]); } scanf( %llu , &KKK); n = 13, ans = 10000000000000000; for (unsigned long long i = 1; i <= n; i++) a[i] = a[i - 1] + KKK % 10 * mul10[i - 1], KKK /= 10; for (unsigned long long i = 0; i < 60; i++) if (f[i] % 10 == a[1]) dfs(1, i); if (flg == 0) puts( -1 ); else printf( %llu n , ans); return 0; }
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Test bench for basic logic elements.
`timescale 1ns/1ps
module RegLatchTest;
// Inputs
reg en, clk;
reg [3:0] data;
// Outputs
wire [3:0] rout;
wire [3:0] lout;
// Instantiate the Unit Under Test (UUT)
CC_DFlipFlop #(4) register(clk, en, data, rout);
CC_DLatch #(4) latch(en, data, lout);
initial begin
en = 0;
data = 'b0;
clk = 0;
end
always
#1 clk = ~clk;
always
#4 en = ~en;
always
#2 data = data + 1;
endmodule
module RegDelayTest;
// Inputs
reg clk;
reg reset;
reg [3:0] data;
// Outputs
wire [3:0] out1;
wire [3:0] out2;
wire [3:0] out3;
// Test different delays.
CC_Delay #(.WIDTH(4), .DELAY(1)) delay1(clk, reset, data, out1);
CC_Delay #(.WIDTH(4), .DELAY(2)) delay2(clk, reset, data, out2);
CC_Delay #(.WIDTH(4), .DELAY(3)) delay3(clk, reset, data, out3);
initial begin
clk = 0;
reset = 1;
data = 0;
#3 reset = 0;
end
always
#1 clk = ~clk;
always
#2 data = data + 1;
endmodule
module CC_BidirTest;
reg sel_in;
wire [3:0] port, in, out;
CC_Bidir #(4) bidir(sel_in, port, in, out);
reg [3:0] count_in;
reg [3:0] count_out;
initial begin
sel_in = 0;
count_in = 'b0;
count_out = 'b0;
end
always begin
#1
count_in = count_in + 1;
count_out = count_out - 1;
end
assign port = sel_in ? count_in : 'bz;
assign out = count_out;
always
#4 sel_in = ~sel_in;
endmodule
module CC_MuxRegTest;
reg clk;
reg sel;
reg en;
reg [3:0] in_a, in_b;
wire [3:0] out;
CC_MuxReg #(4) muxreg(sel, clk, en, in_a, in_b, out);
initial begin
sel = 0;
en = 0;
clk = 0;
in_a = 'b0;
in_b = 'b0;
end
always
#1 clk = ~clk;
always
#4 en = ~en;
always
#7 sel = ~sel;
always
#6 in_a = in_a + 1;
always
#10 in_b = in_b + 1;
endmodule
module CC_DecoderTest;
parameter WIDTH=4;
// Inputs
reg [WIDTH-1:0] in;
// Outputs
wire [(1 << WIDTH)-1:0] out;
CC_Decoder #(WIDTH) decoder(.in(in), .out(out));
initial
in = 0;
always
#1 in = in + 1;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; vector<long long> v; unordered_map<long long, long long> m; long long falla(long long n) { if (m.count(n)) { return m[n]; } long long ans; long long k = 0; for (int j = n - 1; j >= 1; j--) { if (n % j == 0) { ans = j; break; } if (n % (n - j + 1) == 0) { ans = n / (n - j + 1); break; } } m[ans] = ans; return ans; } int main() { long long casos; cin >> casos; long long num = pow(2, 25) - 1; for (int i = 1; i < 30; i++) { v.push_back((1 << i) - 1); } long long flag = 0; while (casos--) { long long num; long long ans1; cin >> num; if (m.count(num)) { cout << m[num] << endl; flag = 1; } if (flag == 0) { ans1 = lower_bound((v).begin(), (v).end(), num) - v.begin(); if (num == v[ans1]) { ans1 = falla(num); m[num] = ans1; cout << ans1 << endl; } else { m[num] = v[ans1]; cout << v[ans1] << endl; } } flag = 0; } }
|
`timescale 1ns / 1ps
module registers_test;
// Inputs
reg clk;
reg rst;
reg [4:0] readAddr1_i;
reg readEnable1_i;
reg [4:0] readAddr2_i;
reg readEnable2_i;
reg [4:0] writeAddr_i;
reg [31:0] writeData_i;
reg writeEnable_i;
// Outputs
wire [31:0] data1_o;
wire [31:0] data2_o;
// Instantiate the Unit Under Test (UUT)
registers uut (
.clk(clk),
.rst(rst),
.readAddr1_i(readAddr1_i),
.readEnable1_i(readEnable1_i),
.data1_o(data1_o),
.readAddr2_i(readAddr2_i),
.readEnable2_i(readEnable2_i),
.data2_o(data2_o),
.writeAddr_i(writeAddr_i),
.writeData_i(writeData_i),
.writeEnable_i(writeEnable_i)
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
readAddr1_i = 0;
readEnable1_i = 0;
readAddr2_i = 0;
readEnable2_i = 0;
writeAddr_i = 0;
writeData_i = 0;
writeEnable_i = 0;
// Wait 100 ns for global reset to finish
#100 $stop;
// Add stimulus here
end
initial begin
#7 rst = 0;
#10 readAddr1_i = 5'b00000;
readEnable1_i = 1'b1;
writeAddr_i = 5'b00001;
writeEnable_i = 1'b1;
writeData_i = 32'h12345678;
#10 readAddr1_i = 5'b00001;
readEnable1_i = 1'b1;
readAddr2_i = 5'b00001;
readEnable2_i = 1'b1;
writeEnable_i = 1'b0;
#10 readEnable1_i = 1'b0;
readEnable2_i = 1'b0;
writeAddr_i = 5'b00000;
writeEnable_i = 1'b1;
writeData_i = 32'h12345678;
#10 readEnable1_i = 1'b1;
readEnable2_i = 1'b1;
readAddr1_i = 5'b10000;
readAddr2_i = 5'b10000;
writeEnable_i = 1'b1;
writeData_i = 32'h12345678;
writeAddr_i = 5'b10000;
end
endmodule
|
//=======================================================================
// Created by :
// Filename :pc.v
// Author :(RDC)
// Created On :2014-05-08 08:49
// Last Modified :
// Update Count :2014-05-08 08:49
// Description :
//
//
//=======================================================================
module IF_stage(/*AUTOARG*/
//Inputs
clk, rst, IF_stall, IF_flush, ID_stall, IF_inst,
IF_PCnext, IF_PC,
//Outputs
ID_inst,ID_PCnext);
input clk;
input rst;
input IF_stall;
input IF_flush;
input ID_stall;
input [31:0] IF_inst;
input [31:0] IF_PCnext;
input [31:0] IF_PC;
//outputs
output reg [31:0] ID_inst;
output reg [31:0] ID_PCnext;
always @(posedge clk) begin
ID_inst <= rst ? 32'b0 : (ID_stall ? ID_inst : ((IF_stall | IF_flush) ? 32'b0 : IF_inst));
ID_PCnext <= rst ? 32'b0 : (ID_stall ? ID_PCnext : IF_PCnext);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6; const int inf = 1e9 + 100; int a[N + 100], b[N + 100]; vector<pair<int, int> > mon[N + 100]; int tree[N * 4 + 100], lazy[N * 4 + 100]; void build(int v, int tl, int tr) { if (tl == tr) { tree[v] = -b[tl + 1]; return; } int tm = (tl + tr) / 2; build(v * 2, tl, tm); build(v * 2 + 1, tm + 1, tr); tree[v] = max(tree[v * 2], tree[v * 2 + 1]); } void push(int v) { tree[v * 2] += lazy[v]; tree[v * 2 + 1] += lazy[v]; lazy[v * 2] += lazy[v]; lazy[v * 2 + 1] += lazy[v]; lazy[v] = 0; } void update(int v, int tl, int tr, int l, int r, int addend) { if (l > r) { return; } if (tl == l && tr == r) { tree[v] += addend; lazy[v] += addend; return; } push(v); int tm = (tl + tr) / 2; update(v * 2, tl, tm, l, min(r, tm), addend); update(v * 2 + 1, tm + 1, tr, max(l, tm + 1), r, addend); tree[v] = max(tree[v * 2], tree[v * 2 + 1]); } int query(int v, int tl, int tr, int l, int r) { if (l > r) { return -inf; } if (tl == l && tr == r) { return tree[v]; } push(v); int tm = (tl + tr) / 2; return max(query(v * 2, tl, tm, l, min(r, tm)), query(v * 2 + 1, tm + 1, tr, max(l, tm + 1), r)); } int main() { for (int i = 1; i <= N + 1; i++) { a[i] = b[i] = inf; } int n, m, p; scanf( %d%d%d , &n, &m, &p); for (int i = 1; i <= n; i++) { int cur, cost; scanf( %d%d , &cur, &cost); a[cur] = min(cost, a[cur]); } int mx = 0; for (int i = 1; i <= m; i++) { int cur, cost; scanf( %d%d , &cur, &cost); b[cur] = min(cost, b[cur]); mx = max(mx, cur); } for (int i = 1; i <= p; i++) { int x, y, z; scanf( %d%d%d , &x, &y, &z); mon[x].push_back(make_pair(y, z)); } for (int i = 1; i <= N; i++) { sort(mon[i].begin(), mon[i].end()); } for (int i = N; i > 0; i--) { a[i] = min(a[i], a[i + 1]); b[i] = min(b[i], b[i + 1]); } build(1, 1, N); int ans = -a[1] - b[1]; int total = 0; for (int i = 1; i <= N; i++) { if (a[i + 1] == inf) { break; } for (auto it : mon[i]) { update(1, 1, N, it.first, N, it.second); ans = max(ans, query(1, 1, N, 1, mx - 1) - a[i + 1]); } } printf( %d n , ans); }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module blk_mem_gen_0 (
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [7 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [8 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [63 : 0] doutb;
blk_mem_gen_v8_3_6 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("blk_mem_gen_0.mif"),
.C_INIT_FILE("blk_mem_gen_0.mem"),
.C_USE_DEFAULT_DATA(1),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(4000),
.C_READ_DEPTH_A(4000),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(64),
.C_READ_WIDTH_B(64),
.C_WRITE_DEPTH_B(500),
.C_READ_DEPTH_B(500),
.C_ADDRB_WIDTH(9),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 4.4085 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(enb),
.regceb(1'D0),
.web(1'B0),
.addrb(addrb),
.dinb(64'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double PI = 3.1415926535897932384626433832795; template <typename S, typename T> ostream& operator<<(ostream& out, pair<S, T> const& p) { out << ( << p.first << , << p.second << ) ; return out; } template <typename T> ostream& operator<<(ostream& out, vector<T> const& v) { int l = v.size(); for (int i = 0; i < l - 1; i++) out << v[i] << ; if (l > 0) out << v[l - 1]; return out; } void tr() { cout << endl; } template <typename S, typename... Strings> void tr(S x, const Strings&... rest) { cout << x << ; tr(rest...); } long long fast(long long a, long long b, long long MOD) { long long ret = 1; while (b) { if ((b & 1)) ret = (ret * a) % MOD; a = (a * a) % MOD; b >>= 1; } return ret; } const long long MOD = 1e6 + 3; int main() { long long n, k; cin >> n >> k; if (n <= 59 and (1ll << n) < k) { cout << 1 << << 1 << endl; return 0; } long long a, b; b = fast(2, n, MOD); b = fast(b, k - 1, MOD); a = 1; long long x = (k - 1) / MOD; long long y = (k - 1) % MOD; long long t = fast(2, n, MOD); for (int i = 1; i <= MOD; i++) { a *= (t - i + MOD) % MOD; a %= MOD; } a = fast(a, x, MOD); for (int i = 1; i <= y; i++) { a *= (t - i + MOD) % MOD; a %= MOD; } long long tot = 0, tmp = k - 1, pw = 2; while (pw <= tmp) { tot += tmp / pw; pw <<= 1; } a = a * fast(fast(2, tot, MOD), MOD - 2, MOD) % MOD; b = b * fast(fast(2, tot, MOD), MOD - 2, MOD) % MOD; a = (b - a + MOD) % MOD; cout << a << << b << endl; return 0; }
|
#include <bits/stdc++.h> bool comp(const int& a, const int& b) { return a < b ? false : true; } using namespace std; int main() { long long int k, a, b, m, n; cin >> k >> m >> n; a = max(m, n); b = min(m, n); long long int ans = 0; if (a > 0 && b > 0) { ans = a / k - (b - 1) / k; } else if (a < 0 && b < 0) { ans = abs(b) / k - (abs(a) - 1) / k; } else { ans = abs(a) / k; ans += (abs(b)) / k; ans += 1; } cout << ans; return 0; }
|
#include <bits/stdc++.h> int main() { long q; scanf( %ld , &q); while (q--) { long n; scanf( %ld , &n); long div = n / 4; if (n <= 3 || n == 5 || n == 7 || n == 11) { puts( -1 ); continue; } if (n & 1) { --div; } printf( %ld n , div); } return 0; }
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#include <bits/stdc++.h> using namespace std; namespace io { const int l = 1 << 19; char buf[l], *s, *t, c; char gc() { if (s == t) { t = (s = buf) + fread(buf, 1, l, stdin); return s == t ? EOF : *s++; } return *s++; } template <class I> void gi(I &x) { x = 0; c = gc(); while (c < 0 || c > 9 ) c = gc(); while ( 0 <= c && c <= 9 ) { x = (x << 1) + (x << 3) + (c ^ 48); c = gc(); } } }; // namespace io using io::gi; const int N = 100005; int n, q, s[N], dp[251][251][251]; int t1, t2, t3, s1[N], s2[N], s3[N]; char ss[N]; set<int> S[26]; void upd(int &a, int b) { if (a == -1 || a > b) a = b; } int main() { scanf( %d%d%s , &n, &q, ss + 1); for (int i = 1; i <= n; i++) { s[i] = ss[i] - a ; S[s[i]].insert(i); } memset(dp, -1, sizeof(dp)); dp[0][0][0] = 0; while (q--) { char A[3], C[3]; int b, c; set<int>::iterator v; scanf( %s%d , A, &b); if (A[0] == - ) { if (b == 1) --t1; if (b == 2) --t2; if (b == 3) --t3; } else { scanf( %s , C); c = C[0] - a ; if (b == 1) { s1[++t1] = c; for (int i = t1; i <= t1; i++) for (int j = 0; j <= t2; j++) for (int k = 0; k <= t3; k++) { dp[i][j][k] = -1; if (i && dp[i - 1][j][k] != -1) { v = S[s1[i]].upper_bound(dp[i - 1][j][k]); if (v != S[s1[i]].end()) upd(dp[i][j][k], *v); } if (j && dp[i][j - 1][k] != -1) { v = S[s2[j]].upper_bound(dp[i][j - 1][k]); if (v != S[s2[j]].end()) upd(dp[i][j][k], *v); } if (k && dp[i][j][k - 1] != -1) { v = S[s3[k]].upper_bound(dp[i][j][k - 1]); if (v != S[s3[k]].end()) upd(dp[i][j][k], *v); } } } if (b == 2) { s2[++t2] = c; for (int i = 0; i <= t1; i++) for (int j = t2; j <= t2; j++) for (int k = 0; k <= t3; k++) { dp[i][j][k] = -1; if (i && dp[i - 1][j][k] != -1) { v = S[s1[i]].upper_bound(dp[i - 1][j][k]); if (v != S[s1[i]].end()) upd(dp[i][j][k], *v); } if (j && dp[i][j - 1][k] != -1) { v = S[s2[j]].upper_bound(dp[i][j - 1][k]); if (v != S[s2[j]].end()) upd(dp[i][j][k], *v); } if (k && dp[i][j][k - 1] != -1) { v = S[s3[k]].upper_bound(dp[i][j][k - 1]); if (v != S[s3[k]].end()) upd(dp[i][j][k], *v); } } } if (b == 3) { s3[++t3] = c; for (int i = 0; i <= t1; i++) for (int j = 0; j <= t2; j++) for (int k = t3; k <= t3; k++) { dp[i][j][k] = -1; if (i && dp[i - 1][j][k] != -1) { v = S[s1[i]].upper_bound(dp[i - 1][j][k]); if (v != S[s1[i]].end()) upd(dp[i][j][k], *v); } if (j && dp[i][j - 1][k] != -1) { v = S[s2[j]].upper_bound(dp[i][j - 1][k]); if (v != S[s2[j]].end()) upd(dp[i][j][k], *v); } if (k && dp[i][j][k - 1] != -1) { v = S[s3[k]].upper_bound(dp[i][j][k - 1]); if (v != S[s3[k]].end()) upd(dp[i][j][k], *v); } } } } if (dp[t1][t2][t3] == -1) puts( NO ); else puts( YES ); } return 0; }
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#include <bits/stdc++.h> using namespace std; struct node { int x, y; bool operator<(const node& a) const { return x < a.x || x == a.x && y < a.y; } }; const int dr[] = {-1, 1, 0, 0, -1, -1, 1, 1}; const int dc[] = {0, 0, -1, 1, -1, 1, -1, 1}; int HH[277]; char s[401000]; int main() { int n, k; do { char _c = getchar(), _v = 1; for (n = 0; _c < 48 || _c > 57; _c = getchar()) if (_c == 45) _v = -1; for (; _c >= 48 && _c <= 57; n = (n << 1) + (n << 3) + _c - 48, _c = getchar()) ; n *= _v; } while (0); do { char _c = getchar(), _v = 1; for (k = 0; _c < 48 || _c > 57; _c = getchar()) if (_c == 45) _v = -1; for (; _c >= 48 && _c <= 57; k = (k << 1) + (k << 3) + _c - 48, _c = getchar()) ; k *= _v; } while (0); scanf( %s , s); for (int i = 0; i < n; i++) ++HH[s[i]]; if (n == k) return 0; char c; for (c = a ; c <= z ; ++c) { k -= HH[c]; if (k <= 0) { k += HH[c]; break; } HH[c] = 0; } int cnt = 0; for (int i = 0; i < n; i++) { if (HH[s[i]]) { if (s[i] != c) putchar(s[i]); else { cnt++; if (cnt > k) putchar(s[i]); } } } return 0; }
|
#include <bits/stdc++.h> const int MaxN = 1 << 20; using namespace std; int dp[MaxN + 5]; char s[30][30]; int a[30][30], cost[30][30]; int bit[30][30]; int n, m; int main() { while (~scanf( %d%d , &n, &m)) { for (int i = 0; i < n; i++) scanf( %s , s[i]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &a[i][j]); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int Max = 0, tmp = 0; bit[i][j] = 0; for (int k = 0; k < n; k++) { if (s[k][j] == s[i][j]) { Max = max(Max, a[k][j]); tmp += a[k][j]; bit[i][j] |= (1 << k); } } cost[i][j] = tmp - Max; } } for (int i = 0; i < (1 << n); i++) dp[i] = 1 << 29; dp[0] = 0; for (int i = 0; i < (1 << n); i++) { for (int j = 0; j < n; j++) { if ((i & (1 << j)) == 0) { for (int k = 0; k < m; k++) { dp[i | (1 << j)] = min(dp[i | (1 << j)], dp[i] + a[j][k]); dp[i | bit[j][k]] = min(dp[i | bit[j][k]], dp[i] + cost[j][k]); } } } } printf( %d n , dp[(1 << n) - 1]); } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by John Stevenson.
// SPDX-License-Identifier: CC0-1.0
package pkg;
typedef logic [31:0] unique_id_t;
typedef struct packed {
unique_id_t foo;
} inner_thing_t;
typedef struct packed {
inner_thing_t bar;
inner_thing_t baz;
} outer_thing_t;
endpackage
import pkg::*;
interface the_intf
#(parameter M=5);
outer_thing_t [M-1:0] things;
logic valid;
modport i (
output things,
output valid);
modport t (
input things,
input valid);
endinterface
module ThingMuxOH
#(
parameter NTHINGS = 1,
parameter M = 5 )
(
input logic [NTHINGS-1:0] select_oh,
the_intf.t things_in [NTHINGS-1:0],
the_intf.i thing_out
);
assign thing_out.valid = things_in[0].valid;
endmodule
module ThingMuxShort
#(
parameter NTHINGS = 1,
parameter M = 5 )
(
input logic [NTHINGS-1:0] select_oh,
the_intf.t things_in [NTHINGS],
the_intf.i thing_out
);
assign thing_out.valid = things_in[0].valid;
endmodule
module Thinker
#(
parameter M = 5,
parameter N = 2)
(
input logic clk,
input logic reset,
input unique_id_t uids[0:N-1],
the_intf.t thing_inp,
the_intf.i thing_out
);
the_intf #(.M(M)) curr_things [N-1:0] ();
the_intf #(.M(M)) prev_things [N-1:0] ();
the_intf #(.M(M)) s_things [N] ();
the_intf #(.M(M)) curr_thing ();
the_intf #(.M(M)) prev_thing ();
the_intf #(.M(M)) s_thing ();
logic [N-1:0] select_oh;
// 1st mux:
ThingMuxOH #(
.NTHINGS ( N ),
.M ( M ))
curr_thing_mux(
.select_oh( select_oh ),
.things_in( curr_things ),
.thing_out( curr_thing ));
// 2nd mux, comment this out and no problem:
ThingMuxOH #(
.NTHINGS ( N ),
.M ( M ))
prev_thing_mux(
.select_oh( select_oh ),
.things_in( prev_things ),
.thing_out( prev_thing ));
// 3rd mux, using short array nomenclature:
ThingMuxShort #(
.NTHINGS ( N ),
.M ( M ))
s_thing_mux(
.select_oh( select_oh ),
.things_in( s_things ),
.thing_out( s_thing ));
endmodule
module t
(
input logic clk,
input logic reset
);
localparam M = 5;
localparam N = 2;
unique_id_t uids[0:N-1];
the_intf #(.M(M)) thing_inp();
the_intf #(.M(M)) thing_out();
Thinker #(
.M ( M ),
.N ( N ))
thinker(
.clk ( clk ),
.reset ( reset ),
.uids ( uids ),
.thing_inp( thing_inp ),
.thing_out( thing_out ));
// Previously there was a problem in V3Inst if non-default parameters was used
localparam K = 2;
the_intf #(.M(K)) thing_inp2();
the_intf #(.M(K)) thing_out2();
Thinker #(
.M ( K ),
.N ( N ))
thinker2(
.clk ( clk ),
.reset ( reset ),
.uids ( uids ),
.thing_inp( thing_inp2 ),
.thing_out( thing_out2 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int used[111111]; multiset<int> g[111111]; multiset<int> vertex; vector<int> ans; void dfs(int v) { used[v] = 1; vertex.erase(v); ans.push_back(v); for (auto i = g[v].begin(); i != g[v].end(); ++i) if (!used[*i]) vertex.insert(*i); if (vertex.size()) dfs(*vertex.begin()); } int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; g[x - 1].insert(y - 1); g[y - 1].insert(x - 1); } dfs(0); for (int i = 0; i < ans.size(); i++) cout << ans[i] + 1 << ; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks.
// SPDX-License-Identifier: CC0-1.0
module top (input SEL, input[1:0] A, output W, output X, output Y, output Z);
mux mux2 (.A(A), .SEL(SEL), .Z(W));
pass mux1 (.A(A), .SEL(SEL), .Z(X));
tbuf mux0[1:0] (.A(A), .OE({SEL,!SEL}), .Z(Y));
assign Z = ( SEL) ? A[1] : 1'bz;
tbuf tbuf (.A(A[0]), .OE(!SEL), .Z(Z));
endmodule
module pass (input[1:0] A, input SEL, output Z);
tbuf tbuf1 (.A(A[1]), .OE(SEL), .Z(Z));
tbuf tbuf0 (.A(A[0]), .OE(!SEL),.Z(Z));
endmodule
module tbuf (input A, input OE, output Z);
`ifdef T_BUFIF0
bufif0 (Z, A, !OE);
`elsif T_BUFIF1
bufif1 (Z, A, OE);
`elsif T_NOTIF0
notif0 (Z, !A, !OE);
`elsif T_NOTIF1
notif1 (Z, !A, OE);
`elsif T_PMOS
pmos (Z, A, !OE);
`elsif T_NMOS
nmos (Z, A, OE);
`elsif T_COND
assign Z = (OE) ? A : 1'bz;
`else
`error "Unknown test name"
`endif
endmodule
module mux (input[1:0] A, input SEL, output Z);
assign Z = (SEL) ? A[1] : 1'bz;
assign Z = (!SEL)? A[0] : 1'bz;
assign Z = 1'bz;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, cnt = 1, point = 0; vector<int> x; cin >> n; for (int i = 0; i < n; i++) { cin >> a >> b; if (b == 0) x.push_back(a); else { cnt += (b - 1); point += a; } } sort(x.begin(), x.end()); for (int j = x.size() - 1; j >= 0 && cnt > 0; j--, cnt--) { point += x[j]; } cout << point << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long s[n]; for (long long c = 0; c < n; c++) cin >> s[c]; long long sum = 0; long long nextAllowedNum = 10000000000000 + 33; for (long long c = n - 1; c >= 0; c--) { if (nextAllowedNum <= 0) break; long long takeval = 0; takeval = s[c] <= nextAllowedNum ? s[c] : nextAllowedNum; nextAllowedNum = takeval - 1; sum += takeval; } cout << sum << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; enum { UP, DOWN, LEFT, RIGHT }; const int MaxN = 1005; const int MaxM = MaxN * MaxN; const int oo = 0x3F3F3F3F; char mp[MaxN][MaxN]; int dir[MaxM][4]; int d[MaxM][4]; int id[MaxN][MaxN], K; int R, C, s, t; struct Node { int u, dir, d; Node() {} Node(int u, int dir, int d) : u(u), dir(dir), d(d) {} }; void BFS() { deque<Node> q; Node u, v; memset(d, 0x3F, sizeof(d)); q.push_back(Node(s, RIGHT, 0)); d[s][RIGHT] = 0; while (!q.empty()) { u = q.front(); q.pop_front(); if (d[u.u][u.dir] != u.d) continue; for (int i = 0; i < 4; i++) { if (dir[u.u][i]) { v.u = dir[u.u][i]; v.dir = i; v.d = u.d + (i != u.dir); if (d[v.u][v.dir] > v.d) { d[v.u][v.dir] = v.d; if (i != u.dir) q.push_back(v); else q.push_front(v); } } } } } int main() { while (scanf( %d%d , &R, &C) == 2) { for (int i = 0; i < R; i++) { scanf( %s , mp[i]); for (int j = 0; j < C; j++) { if (mp[i][j] == # ) { id[i][j] = ++K; } else { id[i][j] = 0; } } } s = ++K; t = ++K; fill(dir[s], dir[s] + 4, 0); fill(dir[t], dir[t] + 4, 0); for (int i = 0; i < R; i++) { int last = i == 0 ? s : 0; for (int j = 0; j < C; j++) { if (mp[i][j] == # ) { if (i == 0 && dir[s][RIGHT] == 0) dir[s][RIGHT] = id[i][j]; dir[id[i][j]][LEFT] = last; last = id[i][j]; } } last = i == R - 1 ? t : 0; for (int j = C - 1; j >= 0; j--) { if (mp[i][j] == # ) { if (i == R - 1 && dir[t][LEFT] == 0) dir[t][LEFT] = id[i][j]; dir[id[i][j]][RIGHT] = last; last = id[i][j]; } } } for (int j = 0; j < C; j++) { int last = 0; for (int i = 0; i < R; i++) { if (mp[i][j] == # ) { dir[id[i][j]][UP] = last; last = id[i][j]; } } last = 0; for (int i = R - 1; i >= 0; i--) { if (mp[i][j] == # ) { dir[id[i][j]][DOWN] = last; last = id[i][j]; } } } BFS(); if (d[t][RIGHT] == oo) puts( -1 ); else printf( %d n , d[t][RIGHT]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; long long ar[100100]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> ar[i]; } sort(ar, ar + n); long long dif1 = ar[1] - ar[0], dif2 = -1; int cnt1 = 0, cnt2 = 0; if (n == 1) { cout << -1 << endl; return 0; } else if (n == 2) { if (ar[0] == ar[1]) { cout << 1 << endl << ar[0]; return 0; } else { if ((ar[0] + ar[1]) % 2 == 0) { cout << 3 << endl << ar[0] - (ar[1] - ar[0]) << << (ar[1] + ar[0]) / 2 << << ar[1] + (ar[1] - ar[0]) << endl; return 0; } else { cout << 2 << endl << ar[0] - (ar[1] - ar[0]) << << ar[1] + (ar[1] - ar[0]) << endl; return 0; } } } else { set<long long> nd; set<long long> ans; for (int i = 1; i < n; i++) { nd.insert(ar[i] - ar[i - 1]); } if (nd.size() > 2) { cout << 0 << endl; } else if (nd.size() == 1) { ans.insert(ar[0] - (ar[1] - ar[0])); ans.insert(ar[n - 1] + (ar[1] - ar[0])); cout << ans.size() << endl; for (auto it : ans) { cout << it << endl; } } else { int ls1 = -1, ls2 = -1; dif1 = *nd.begin(); dif2 = *(++nd.begin()); if (dif1 != 2 * dif2 && dif2 != 2 * dif1) { cout << 0 << endl; return 0; } for (int i = 1; i < n; i++) { if (ar[i] - ar[i - 1] == dif1) { cnt1++; ls1 = i; } else { cnt2++; ls2 = i; } } if (cnt1 == 1 && dif1 % 2 == 0 && dif1 > dif2) { cout << 1 << endl; cout << ar[ls1 - 1] + dif2 << endl; return 0; } if (cnt2 == 1 && dif2 % 2 == 0 && dif1 < dif2) { cout << 1 << endl; cout << ar[ls2 - 1] + dif1 << endl; return 0; } cout << 0 << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[122], b[122]; int main() { int n, k, t, ans = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> k >> t; a[k]++; b[t]++; } for (int i = 1; i <= 100; i++) if (a[i] > 0) ans += a[i] * b[i]; cout << ans << endl; }
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:12:35 MDT 2014
//Date : Fri Apr 10 21:05:15 2015
//Host : LIGHTNING running 64-bit major release (build 9200)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR2_addr,
DDR2_ba,
DDR2_cas_n,
DDR2_ck_n,
DDR2_ck_p,
DDR2_cke,
DDR2_cs_n,
DDR2_dm,
DDR2_dq,
DDR2_dqs_n,
DDR2_dqs_p,
DDR2_odt,
DDR2_ras_n,
DDR2_we_n,
OV7670_D,
OV7670_HREF,
OV7670_PCLK,
OV7670_PWDN,
OV7670_RESET,
OV7670_SIOC,
OV7670_SIOD,
OV7670_VSYNC,
OV7670_XCLK,
USB_Uart_rxd,
USB_Uart_txd,
ampSD,
reset,
speaker,
sys_clock,
tft_hsync,
tft_vga_b,
tft_vga_g,
tft_vga_r,
tft_vsync);
output [12:0]DDR2_addr;
output [2:0]DDR2_ba;
output DDR2_cas_n;
output [0:0]DDR2_ck_n;
output [0:0]DDR2_ck_p;
output [0:0]DDR2_cke;
output [0:0]DDR2_cs_n;
output [1:0]DDR2_dm;
inout [15:0]DDR2_dq;
inout [1:0]DDR2_dqs_n;
inout [1:0]DDR2_dqs_p;
output [0:0]DDR2_odt;
output DDR2_ras_n;
output DDR2_we_n;
input [7:0]OV7670_D;
input OV7670_HREF;
input OV7670_PCLK;
output OV7670_PWDN;
output OV7670_RESET;
output OV7670_SIOC;
inout OV7670_SIOD;
input OV7670_VSYNC;
output OV7670_XCLK;
input USB_Uart_rxd;
output USB_Uart_txd;
output ampSD;
input reset;
output speaker;
input sys_clock;
output tft_hsync;
output [3:0]tft_vga_b;
output [3:0]tft_vga_g;
output [3:0]tft_vga_r;
output tft_vsync;
wire [12:0]DDR2_addr;
wire [2:0]DDR2_ba;
wire DDR2_cas_n;
wire [0:0]DDR2_ck_n;
wire [0:0]DDR2_ck_p;
wire [0:0]DDR2_cke;
wire [0:0]DDR2_cs_n;
wire [1:0]DDR2_dm;
wire [15:0]DDR2_dq;
wire [1:0]DDR2_dqs_n;
wire [1:0]DDR2_dqs_p;
wire [0:0]DDR2_odt;
wire DDR2_ras_n;
wire DDR2_we_n;
wire [7:0]OV7670_D;
wire OV7670_HREF;
wire OV7670_PCLK;
wire OV7670_PWDN;
wire OV7670_RESET;
wire OV7670_SIOC;
wire OV7670_SIOD;
wire OV7670_VSYNC;
wire OV7670_XCLK;
wire USB_Uart_rxd;
wire USB_Uart_txd;
wire ampSD;
wire reset;
wire speaker;
wire sys_clock;
wire tft_hsync;
wire [3:0]tft_vga_b;
wire [3:0]tft_vga_g;
wire [3:0]tft_vga_r;
wire tft_vsync;
design_1 design_1_i
(.DDR2_addr(DDR2_addr),
.DDR2_ba(DDR2_ba),
.DDR2_cas_n(DDR2_cas_n),
.DDR2_ck_n(DDR2_ck_n),
.DDR2_ck_p(DDR2_ck_p),
.DDR2_cke(DDR2_cke),
.DDR2_cs_n(DDR2_cs_n),
.DDR2_dm(DDR2_dm),
.DDR2_dq(DDR2_dq),
.DDR2_dqs_n(DDR2_dqs_n),
.DDR2_dqs_p(DDR2_dqs_p),
.DDR2_odt(DDR2_odt),
.DDR2_ras_n(DDR2_ras_n),
.DDR2_we_n(DDR2_we_n),
.OV7670_D(OV7670_D),
.OV7670_HREF(OV7670_HREF),
.OV7670_PCLK(OV7670_PCLK),
.OV7670_PWDN(OV7670_PWDN),
.OV7670_RESET(OV7670_RESET),
.OV7670_SIOC(OV7670_SIOC),
.OV7670_SIOD(OV7670_SIOD),
.OV7670_VSYNC(OV7670_VSYNC),
.OV7670_XCLK(OV7670_XCLK),
.USB_Uart_rxd(USB_Uart_rxd),
.USB_Uart_txd(USB_Uart_txd),
.ampSD(ampSD),
.reset(reset),
.speaker(speaker),
.sys_clock(sys_clock),
.tft_hsync(tft_hsync),
.tft_vga_b(tft_vga_b),
.tft_vga_g(tft_vga_g),
.tft_vga_r(tft_vga_r),
.tft_vsync(tft_vsync));
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of array querying functions.
//
// This code instantiates a module that calls the various array querying
// functions.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// SPDX-License-Identifier: CC0-1.0
// Contributed 2012 by Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire a = clk;
wire b = 1'b0;
reg c;
array_test array_test_i (/*AUTOINST*/
// Inputs
.clk (clk));
endmodule
// Check the array sizing functions work correctly.
module array_test
#( parameter
LEFT = 5,
RIGHT = 55)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off LITENDIAN
reg [7:0] a [LEFT:RIGHT];
// verilator lint_on LITENDIAN
typedef reg [7:0] r_t;
integer l;
integer r;
integer s;
always @(posedge clk) begin
l = $left (a);
r = $right (a);
s = $size (a);
`ifdef TEST_VERBOSE
$write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s);
`endif
if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop;
if ($left(r_t)!=7 || $right(r_t)!=0 || $size(r_t)!=8 || $bits(r_t) !=8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool cmax(T &x, T y) { return x < y ? x = y, 1 : 0; } template <typename T> inline bool cmin(T &x, T y) { return y < x ? x = y, 1 : 0; } const int _ = 2e5 + 55, __ = 5e5 + 55; int N; long long a[_], b[_]; char ans[__]; int n, cnt; bool check() { for (int i(1), I(N); i <= I; ++i) if (b[i] <= 0) return 0; return 1; } bool up() { for (int i(1), I(N - 1); i <= I; ++i) if (b[i + 1] <= b[i]) return 0; return 1; } bool down() { for (int i(1), I(N - 1); i <= I; ++i) if (b[i] <= b[i + 1]) return 0; return 1; } int main() { ios::sync_with_stdio(0), cin.tie(0); cin >> N; for (int i(1), I(N); i <= I; ++i) cin >> a[i]; for (int i(1), I(N); i <= I; ++i) cin >> b[i]; if (N == 1) return printf(a[1] == b[1] ? SMALL n0 n : IMPOSSIBLE n ), 0; if (N == 2) { long long x(b[1]), y(b[2]), s(0); while (x && y) { if (y == a[1]) swap(x, y); if (x == a[1] && y >= a[2] && (y - a[2]) % x == 0) { s += (y - a[2]) / x, y = a[2]; break; } if (y == a[2]) swap(x, y); if (x == a[2] && y >= a[1] && (y - a[1]) % x == 0) { s += (y - a[1]) / x, y = a[1], swap(x, y); break; } if (x > y) swap(x, y); s += y / x, y %= x; } if (x != a[1] || y != a[2]) return printf( IMPOSSIBLE n ), 0; else if (s > 2e5) return printf( BIG n%lld n , s), 0; } while (check()) { int flg = 1; for (int i(1), I(N); i <= I; ++i) if (a[i] != b[i]) { flg = 0; break; } if (!flg) { flg = 2; for (int i(1), I(N); i <= I; ++i) if (a[i] != b[N - i + 1]) { flg = 0; break; } } if (flg) { if (flg == 2 && cnt <= 2e5) ans[++n] = R ; if (cnt <= 2e5) { printf( SMALL n%d n , n); for (int i(n), I(1); i >= I; --i) putchar(ans[i]); putchar( n ); } else printf( BIG n%d n , cnt); return 0; } else if (up()) { ++cnt; if (cnt <= 2e5) ans[++n] = P ; for (int i(N), I(2); i >= I; --i) b[i] -= b[i - 1]; } else if (down()) { ++cnt; if (cnt <= 2e5) ans[++n] = R , ans[++n] = P ; reverse(b + 1, b + N + 1); for (int i(N), I(2); i >= I; --i) b[i] -= b[i - 1]; } else break; } printf( IMPOSSIBLE n ); return 0; }
|
//`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:26:25 12/09/2014
// Design Name: cpu
// Module Name: /home/administrator/Documents/Xilinx/RiscCpu/test_cpu.v
// Project Name: RiscCpu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cpu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
/*module test_cpu;
// Inputs
reg clk;
reg reset;
// Outputs
wire halt;
wire rd;
wire wr;
wire [12:0] addr;
// Bidirs
wire [7:0] data;
// Instantiate the Unit Under Test (UUT)
cpu uut (
.clk(clk),
.reset(reset),
.halt(halt),
.rd(rd),
.wr(wr),
.addr(addr),
.data(data)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
*/
`timescale 1ns / 100ps
`define PERIOD 100 // matches clk_gen.v
module cputop;
reg reset_req,clock;
integer test;
reg [(3*8):0] mnemonic; //array that holds 3 8-bit ASCII characters
reg [12:0] PC_addr,IR_addr;
wire [7:0] data;
wire [12:0] addr;
wire rd,wr,halt,ram_sel,rom_sel;
//------------------------ cpu ?????????ROM?RAM?????--------------------------------------
cpu t_cpu (.clk(clock),.reset(reset_req),.halt(halt),.rd(rd),
.wr(wr),.addr(addr),.data(data));
ram t_ram (.addr(addr[9:0]),.read(rd),.write(wr),.ena(ram_sel),.data(data));
rom t_rom (.addr(addr),.read(rd),.ena(rom_sel),.data(data));
addr_decode t_addr_decode (.addr(addr),.ram_sel(ram_sel),.rom_sel(rom_sel));
//--------------------cpu ?????????ROM?RAM???????----------------------------------
initial
begin
clock=1;
//display time in nanoseconds
$timeformat ( -9, 1, " ns", 12);
display_debug_message;
sys_reset;
test1;
$stop;
test2;
$stop;
test3;
$stop;
end
task display_debug_message;
begin
$display("\n**************************************************");
$display("* THE FOLLOWING DEBUG TASK ARE AVAILABLE: *");
$display("* \"test1; \" to load the 1st diagnostic progran. *");
$display("* \"test2; \" to load the 2nd diagnostic program. *");
$display("* \"test3; \" to load the Fibonacci program. *");
$display("*****************************************************\n");
end
endtask
task test1;
begin
test = 0;
disable MONITOR;
$readmemb ("test1.pro", t_rom.memory);
$display("rom loaded successfully!");
$readmemb("test1.dat",t_ram.ram);
$display("ram loaded successfully!");
#1 test = 1;
#14800 ;
sys_reset;
end
endtask
task test2;
begin
test = 0;
disable MONITOR;
$readmemb("test2.pro",t_rom.memory);
$display("rom loaded successfully!");
$readmemb("test2.dat",t_ram.ram);
$display("ram loaded successfully!");
#1 test = 2;
#11600;
sys_reset;
end
endtask
task test3;
begin
test = 0;
disable MONITOR;
$readmemb("test3.pro",t_rom.memory);
$display("rom loaded successfully!");
$readmemb("test3.dat",t_ram.ram);
$display("ram loaded successfully!");
#1 test = 3;
#94000;
sys_reset;
end
endtask
task sys_reset;
begin
reset_req = 0;
#(`PERIOD*0.7) reset_req = 1;
#(1.5*`PERIOD) reset_req = 0;
end
endtask
always @(test)
begin: MONITOR
case (test)
1: begin //display results when running test 1
$display("\n*** RUNNING CPUtest1 - The Basic CPU Diagnostic Program ***");
$display("\n TIME PC INSTR ADDR DATA ");
$display(" ---------- ---- ----- ----- ----- ");
while (test == 1)
@(t_cpu.m_adr.pc_addr)//fixed
if ((t_cpu.m_adr.pc_addr%2 == 1)&&(t_cpu.m_adr.fetch == 1))//fixed
begin
# 60 PC_addr <=t_cpu.m_adr.pc_addr -1 ;
IR_addr <=t_cpu.m_adr.ir_addr;
# 340 $strobe("%t %h %s %h %h", $time, PC_addr,
mnemonic, IR_addr,data );
//HERE DATA HAS BEEN CHANGED T-CPU-M-REGISTER.DATA
end
end
2: begin
$display("\n*** RUNNING CPUtest2 - The Advanced CPU Diagnostic Program ***");
$display("\n TIME PC INSTR ADDR DATA ");
$display(" ---------- --- ----- ----- ---- ");
while (test == 2)
@(t_cpu.m_adr.pc_addr)
if ((t_cpu.m_adr.pc_addr%2 == 1)
&& (t_cpu.m_adr.fetch == 1))
begin
# 60 PC_addr <= t_cpu.m_adr.pc_addr - 1 ;
IR_addr <= t_cpu.m_adr.ir_addr;
# 340 $strobe("%t %h %s %h %h", $time, PC_addr,
mnemonic, IR_addr, data );
end
end
3: begin
$display("\n*** RUNNING CPUtest3 - An Executable Program ***");
$display("*** This program should calculate the fibonacci ***");
$display("\n TIME FIBONACCI NUMBER");
$display( " --------- -----------------");
while (test == 3)
begin
wait ( t_cpu.m_alu.opcode == 3'h1) // display Fib. No. at end of program loop
$strobe("%t %d", $time,t_ram.ram[10'h2]);
wait ( t_cpu.m_alu.opcode != 3'h1);
end
end
endcase
end
//-------------------------------------------------------------------------
always @(posedge halt) //STOP when HALT instruction decoded
begin
#500
$display("\n*********************************************");
$display( "** A HALT INSTRUCTION WAS PROCESSED !!! **");
$display( "*********************************************\n");
end
always #(`PERIOD/2) clock=~clock;
always @(t_cpu.m_alu.opcode)
//get an ASCII mnemonic for each opcode
case(t_cpu.m_alu.opcode)
3'b000 : mnemonic ="HLT";
3'h1 : mnemonic = "SKZ";
3'h2 : mnemonic = "ADD";
3'h3 : mnemonic = "AND";
3'h4 : mnemonic = "XOR";
3'h5 : mnemonic = "LDA";
3'h6 : mnemonic = "STO";
3'h7 : mnemonic = "JMP";
default : mnemonic = "???";
endcase
endmodule
//------------------------------------------- cputop.v ????? -----------------------------------------------------
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_top.v,v 1.10 2003/09/01 10:34:38 rherveille Exp $
//
// $Date: 2003/09/01 10:34:38 $
// $Revision: 1.10 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_top.v,v $
// Revision 1.10 2003/09/01 10:34:38 rherveille
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
// Revision 1.9 2003/01/09 16:44:45 rherveille
// Fixed a bug in the Command Register declaration.
//
// Revision 1.8 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.7 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.6 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.5 2001/11/10 10:52:55 rherveille
// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b0; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis full_case parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis full_case parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (~rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 1'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t, n, m, a, b, c, q, k, d, x; cin >> n >> m; vector<vector<int>> mat(n + 1, vector<int>(m + 1)), ans(n + 1, vector<int>(m + 1)); char ch; for (int i = 1; i < n + 1; i++) { for (int j = 1; j < m + 1; j++) { cin >> ch; mat[i][j] = ch - 0 ; ans[i][j] = ans[i - 1][j] + ans[i][j - 1] - ans[i - 1][j - 1] + mat[i][j]; } } a = 0; for (int i = 1; i < n + 1; i++) { for (int j = 1; j < m + 1; j++) { for (int i_ = i; i_ < n + 1; i_++) { for (int j_ = j; j_ < m + 1; j_++) { if (ans[i_][j_] - ans[i - 1][j_] - ans[i_][j - 1] + ans[i - 1][j - 1] == 0) { a = max(a, 2 * (i_ - i + 1 + j_ - j + 1)); } } } } } cout << a << n ; return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc3_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc3_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 600; int mat[2000][2000]; int quad[20][20]; int cont[20][20]; int main() { int n, m; scanf( %d%d , &n, &m); int foi = 0; int result = -1; for (int i = 0; i < m; i++) { int x, y; for (int h = 0; h < 5; h++) { for (int k = 0; k < 5; k++) { quad[h][k] = 0; cont[h][k] = 0; } } scanf( %d%d , &x, &y); x--; y--; mat[x][y]++; int maiorX = max(x - 2, 0); int menorX = min(x + 2, n - 1) + 1; int maiorY = max(y - 2, 0); int menorY = min(y + 2, n - 1) + 1; for (int h = maiorX; h < menorX; h++) { for (int k = maiorY; k < menorY; k++) { if (mat[h][k]) { cont[h - maiorX][k - maiorY]++; if (h - maiorX - 1 >= 0) { cont[h - maiorX][k - maiorY] += cont[h - maiorX - 1][k - maiorY]; } } } } int pode = 0; for (int h = 0; h < 5; h++) { int soma = 0; for (int k = 0; k < 5; k++) { if (cont[h][k] >= 3) { soma++; if (soma >= 3) { pode = 1; } } else { soma = 0; } } } if (foi == 0 && pode) { result = i + 1; foi = 1; } } printf( %d n , result); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4.1,sse4.2,avx,avx2,popcnt,tune=native ) using namespace std; template <typename Tp> inline void read(Tp &x) { static char c; static bool neg; x = 0, c = getchar(), neg = false; for (; !isdigit(c); c = getchar()) { if (c == - ) { neg = true; } } for (; isdigit(c); c = getchar()) { x = x * 10 + c - 0 ; } if (neg) { x = -x; } } const int N = 100000 + 5; int n, w, q; int a[N], b[N]; int mn[N], mx[N], ans[N]; inline void checkMax(int &x, const int &y) { if (x < y) { x = y; } } inline void checkMin(int &x, const int &y) { if (x > y) { x = y; } } int main() { read(n), read(w), read(q); for (int i = 0; i < n; ++i) { read(a[i]); } for (int i = 0, x; i < q; ++i) { read(x); b[i] = w - x; } fill(mn, mn + q, a[0]); fill(mx, mx + q, a[0]); for (int j = 1; j < n; ++j) { for (int i = 0; i < q; ++i) { checkMax(mx[i], a[j]); checkMin(mn[i], a[j]); if (mx[i] - mn[i] > b[i]) { ++ans[i]; mn[i] = mx[i] = a[j]; } } } for (int i = 0; i < q; ++i) { printf( %d n , ans[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma warning(disable : 4996) #pragma comment(linker, /STACK:336777216 ) const int sqrtn = 300; const int inf = 987654321; const int sz = 1e5 + 5; const int mod = 1e9 + 7; int n, vis[sz]; string str; int main() { scanf( %d , &n); cin >> str; int ret = 0, x = 0, y = 0, last = 0; if (str[0] == U ) { y++; last = 1; } else x++, last = 0; for (int i = 1; i < n; i++) { if (str[i] == U ) y++; else x++; if (vis[i - 1]) { if (y > x && last == 0) { ret++, last = 1; } else if (x > y && last == 1) { ret++, last = 0; } } if (y == x) vis[i] = 1; } printf( %d , ret); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__SDFRTN_FUNCTIONAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 30, Mod = 1e9 + 7; const long long SQ = 330; int main() { ios::sync_with_stdio(0), cin.tie(0); long long a, b; cin >> a >> b; long long ans = 0; while (a > 0 && b > 0) { if (a <= b) a++, b -= 2; else b++, a -= 2; if (a < 0 || b < 0) ans--; ans++; } cout << ans; return (0); }
|
#include <bits/stdc++.h> using namespace std; long long n, m, a, b, res; int main() { cin >> n >> m; for (a = 0; a <= 1000; a++) { for (b = 0; b <= 1000; b++) { if (a * a + b == n && a + b * b == m) { res++; } } } cout << res; }
|
module mandlebrot_factory(
input clk,
input [ADDR_WIDTH - 1 : 0]raddr,
output [DATA_WIDTH - 1 : 0] q
);
// Plot between
// (-2, 2)Re, (1,-1)Im
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 9;
// parameter PIPE_WIDTH = 2 * DATA_WIDTH + 5;
// parameter PIPE_WIDTH = 2 * DATA_WIDTH + 3;
parameter PIPE_WIDTH = 2 * DATA_WIDTH + 7;
// localparam MAX_N_IT = 1 << DATA_WIDTH;
localparam MAX_N_IT = 5; // remove to be max data width
reg we = 0;
reg [DATA_WIDTH - 1 : 0] iteration_pipe[PIPE_WIDTH - 1 : 0];
reg [ADDR_WIDTH - 1 : 0] ctr = 0;
reg [ADDR_WIDTH - 1 : 0] waddr_pipe[PIPE_WIDTH - 1 : 0];
wire escaped;
wire en;
always @(posedge clk)
begin
if ( ~en || escaped || (iteration_pipe[PIPE_WIDTH - 1] > MAX_N_IT) )
begin
ctr <= ctr + 1;
end
end
always @(posedge clk)
begin
if ( escaped || (iteration_pipe[PIPE_WIDTH - 2] > (MAX_N_IT - 1)) )
begin
we <= 1;
iteration_pipe[0] <= 0;
end
else
begin
we <= 0;
iteration_pipe[0] <= en ? iteration_pipe[PIPE_WIDTH - 2] + 1 : 0;
end
end // always @ (posedge clk)
always @(posedge clk)
begin
if ( ~en || escaped || (iteration_pipe[PIPE_WIDTH - 2] > MAX_N_IT - 1) )
begin
waddr_pipe[0] <= ctr;
end
else
begin
waddr_pipe[0] <= waddr_pipe[PIPE_WIDTH - 2];
end
end
genvar i;
generate
for (i = 1; i < PIPE_WIDTH; i = i + 1)
begin
always @(posedge clk)
begin
waddr_pipe[i] <= waddr_pipe[i - 1];
if (i == PIPE_WIDTH - 1)
begin
iteration_pipe[i] <= escaped ? iteration_pipe[i - 1] : iteration_pipe[i - 1] + 1;
end
else
begin
iteration_pipe[i] <= iteration_pipe[i - 1];
end
end
end
endgenerate
wire [DATA_WIDTH - 1 : 0] d;
wire [ADDR_WIDTH - 1 : 0] waddr;
assign d = iteration_pipe[PIPE_WIDTH - 1];
assign waddr = waddr_pipe[PIPE_WIDTH - 1];
dram_512x8#(
) memory (
.w_clk(clk),
.r_clk(clk),
.we(we),
.waddr(waddr),
.d(d),
.re(1'b1),
.raddr(raddr),
.q(q)
);
reg [ADDR_WIDTH - 1 : 0] re_i, re_c;
wire [ADDR_WIDTH - 1 : 0] re_o;
reg [ADDR_WIDTH - 1 : 0] im_i, im_c;
wire [ADDR_WIDTH - 1 : 0] im_o;
reg valid_i;
always @(*)
begin
if (~en ||~escaped)
begin
re_i <= 0;
im_i <= 0;
re_c <= waddr_pipe[0];
im_c <= waddr_pipe[0];
end
else
begin
re_i <= re_o;
im_i <= im_o;
re_c <= waddr_pipe[0];
im_c <= waddr_pipe[0];
end
end // always @ (*)
always @(posedge clk)
begin
valid_i <= 1'b1;
end
mandlebrot#(
.WIDTH(ADDR_WIDTH)
) mandle(
.clk(clk),
.re_i(re_i),
.im_i(im_i),
.re_c(re_c),
.im_c(im_c),
.re_o(re_o),
.im_o(im_o),
.escaped(escaped),
.valid_i(valid_i),
.valid_o(en)
);
integer k;
initial
begin
$dumpfile("./build/iverilog/mandlebrot.vcd");
for (k = 0; k < PIPE_WIDTH; k = k + 1)
begin
$dumpvars(0, iteration_pipe[k]);
$dumpvars(0, waddr_pipe[k]);
end
end
endmodule
|
//#############################################################################
//# Function: Dual data rate input buffer (2 cycle delay) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_iddr #(parameter DW = 1 // width of data inputs
)
(
input clk, // clock
input ce0, // 1st cycle enable
input ce1, // 2nd cycle enable
input [DW/2-1:0] din, // data input sampled on both edges of clock
output reg [DW-1:0] dout // iddr aligned
);
//regs("sl"=stable low, "sh"=stable high)
reg [DW/2-1:0] din_sl;
reg [DW/2-1:0] din_sh;
reg ce0_negedge;
//########################
// Pipeline valid for negedge
//########################
always @ (negedge clk)
ce0_negedge <= ce0;
//########################
// Dual edge sampling
//########################
always @ (posedge clk)
if(ce0)
din_sl[DW/2-1:0] <= din[DW/2-1:0];
always @ (negedge clk)
if(ce0_negedge)
din_sh[DW/2-1:0] <= din[DW/2-1:0];
//########################
// Aign pipeline
//########################
always @ (posedge clk)
if(ce1)
dout[DW-1:0] <= {din_sh[DW/2-1:0],
din_sl[DW/2-1:0]};
endmodule // oh_iddr
|
#include <bits/stdc++.h> using namespace std; long long n, m; long long ar[1000001], dp[1001][1001]; long long calc(long long idx, long long rem) { if (rem == 0 && idx != 0) return 1; if (idx >= n) return 0; long long &b = dp[idx][rem]; if (b != -1) return b; else b = 0; b |= calc(idx + 1, (rem + ar[idx]) % m); b |= calc(idx + 1, rem); return b; } void solve() { cin >> n >> m; for (long long i = 0; i < (n); ++i) { cin >> ar[i]; ar[i] %= m; if (ar[i] == 0) { cout << YES n ; return; } } if (n >= m) { cout << YES n ; return; } else { for (long long i = 0; i < (1001); ++i) for (long long j = 0; j < (1001); ++j) dp[i][j] = -1; if (calc(0, m)) { cout << YES n ; } else cout << NO n ; } } int32_t main() { ios::sync_with_stdio(0), cin.tie(NULL), cout.tie(NULL); long long t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int t, n, m, ans; vector<vector<int>> gh, used; int dx[8] = {1, 1, 1, 0, 0, -1, -1, -1}; int dy[8] = {1, 0, -1, 1, -1, 1, 0, -1}; bool onseg(double x1, double y1, double x2, double y2, double x, double y) { double d1 = sqrt((x - x1) * (x - x1) + (y - y1) * (y - y1)); double d2 = sqrt((x - x2) * (x - x2) + (y - y2) * (y - y2)); double d3 = sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)); return abs(d3 - d2 - d1) < 1e-9; } void bfs(int y, int x) { if (gh[y][x] == 0) return; if (used[y][x]) return; used[y][x] = true; vector<pair<int, int>> todo, temp, bunch; int cx, cy, nx, ny; todo.push_back({y, x}); bunch.push_back({y, x}); while (true) { if (todo.empty()) break; for (int i = 0; i < todo.size(); i++) { cy = todo[i].first, cx = todo[i].second; for (int j = 0; j < 8; j++) { ny = cy + dy[j]; nx = cx + dx[j]; if (ny >= 0 && ny < n && nx >= 0 && nx < m) { if (used[ny][nx] == 0) { temp.push_back({ny, nx}); bunch.push_back({ny, nx}); used[ny][nx] = 1; } } } } todo = temp; temp.clear(); } if (bunch.size() % 4) return; int len = bunch.size() / 4; int topx, topy, btx, bty; topx = bunch[0].second, topy = bunch[0].first; btx = topx + len, bty = topy + len; bool sq = true; for (int j = 1; j < bunch.size(); j++) { int nx = bunch[j].second, ny = bunch[j].first; if (!onseg(topx, topy, btx, topy, nx, ny) && !onseg(topx, topy, topx, bty, nx, ny) && !onseg(btx, bty, btx, topy, nx, ny) && !onseg(btx, bty, topx, bty, nx, ny)) { sq = false; break; } } if (sq) { ans++; return; } sq = true; topx = bunch[0].second, topy = bunch[0].first; btx = topx, bty = topy + 2 * len; for (int j = 1; j < bunch.size(); j++) { int nx = bunch[j].second, ny = bunch[j].first; if (!onseg(topx, topy, topx - len, topy + len, nx, ny) && !onseg(topx, topy, topx + len, topy + len, nx, ny) && !onseg(btx, bty, topx - len, topy + len, nx, ny) && !onseg(btx, bty, topx + len, topy + len, nx, ny)) { sq = false; break; } } if (sq) { ans++; } } void solve() { cin >> n >> m; gh = used = vector<vector<int>>(n, vector<int>(m)); ans = 0; char ch; int val; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> ch; val = ch - 0 ; if (val == 0) used[i][j] = 1; gh[i][j] = val; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) if (used[i][j] == 0) bfs(i, j); } cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> t; while (t--) solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111OI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A2111OI_PP_BLACKBOX_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const long long INF = 1000000000; template <class T> T read(T &x) { char c; int flag = 1; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) flag *= -1; x = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) x = x * 10 + c - 0 ; x *= flag; return x; } int dep[100005]; int fa[100005]; vector<int> adj[100005]; void dfs(int x, int f) { for (int i : adj[x]) { if (i == f) continue; fa[i] = x; dep[i] = dep[x] + 1; dfs(i, x); } } int main() { ios::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; for (int i = 1; i < n; ++i) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(1, -1); int root = 1; for (int i = 1; i <= n; ++i) if (dep[root] < dep[i]) root = i; memset(dep, 0, sizeof dep); ; dfs(root, -1); int tar = root; for (int i = 1; i <= n; ++i) if (dep[tar] < dep[i]) tar = i; vector<int> v; while (tar != root) { v.push_back(tar); tar = fa[tar]; } v.push_back(root); if (v.size() != (k << 1) + 1) return cout << No << endl, 0; memset(dep, 0, sizeof dep); ; root = v[k]; dfs(root, -1); for (int i = 1; i <= n; ++i) { if (dep[i] == k) continue; int sz = adj[i].size() - 1 + (root == i); if (sz < 3) return cout << No << endl, 0; } cout << Yes << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int ts; cin >> ts; while (ts--) { long long n, i, vis[500] = {0}, a; cin >> n; for (i = 1; i <= 2 * n; i++) { cin >> a; if (vis[a] == 0) { cout << a << ; } vis[a] = 1; } cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int nums[n]; for (int i = 0; i < n; i++) { cin >> nums[i]; } if ((nums[0] % 2 == 0)) { cout << No ; return 0; } if ((nums[n - 1] % 2 == 0)) { cout << No ; return 0; } if ((n % 2) == 0) { cout << No ; return 0; } cout << Yes ; return 0; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct fastIO { fastIO() { ios_base::sync_with_stdio(0); } }; const int MAXN = 1e6 * 2; long long n, a[MAXN], x, ans = MAXN, b; int main() { fastIO(); cin >> n; for (long long i = 0; i < n; i++) cin >> a[i]; for (x = 0; x < n; x++) { b = 0; for (long long i = 0; i < n; i++) { b += (abs(x - i) + i + x) * a[i] * 2; } if (0) cerr << ans << endl; ans = min(ans, b); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int mod = 1000000007; int gcd(int a, int b) { if (b == 0) return a; else return gcd(b, a % b); } int prime(long long int n) { long long int i; for (i = 2; i <= sqrt(n); i++) { if (n % i == 0) return 0; } return 1; } long long int ans[1000000], c = 0; void get_num(long long int n) { long long int i; for (i = 2; i <= sqrt(n); i++) { if (n % i == 0) { if (prime(i)) ans[c++] = i; if (prime(n / i)) { if (n / i != i) ans[c++] = i; } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int n; cin >> n; get_num(n); if (c == 0) cout << n; else if (c == 1) cout << ans[0]; else cout << 1; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFRTP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_SYMBOL_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module priority_enc
(input [31:0] in,
output reg [31:0] out);
always @*
casex(in)
32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 31;
32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 30;
32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 29;
32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 28;
32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 27;
32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 26;
32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 25;
32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 24;
32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 23;
32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 22;
32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 21;
32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 20;
32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : out <= 19;
32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : out <= 18;
32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : out <= 17;
32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : out <= 16;
32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : out <= 15;
32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : out <= 14;
32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : out <= 13;
32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : out <= 12;
32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : out <= 11;
32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : out <= 10;
32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : out <= 9;
32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : out <= 8;
32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : out <= 7;
32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : out <= 6;
32'b0000_0000_0000_0000_0000_0000_001x_xxxx : out <= 5;
32'b0000_0000_0000_0000_0000_0000_0001_xxxx : out <= 4;
32'b0000_0000_0000_0000_0000_0000_0000_1xxx : out <= 3;
32'b0000_0000_0000_0000_0000_0000_0000_01xx : out <= 2;
32'b0000_0000_0000_0000_0000_0000_0000_001x : out <= 1;
32'b0000_0000_0000_0000_0000_0000_0000_0001 : out <= 0;
32'b0000_0000_0000_0000_0000_0000_0000_0000 : out <= 32'hFFFF_FFFF;
default : out <= 32'hFFFF_FFFF;
endcase // casex (in)
endmodule // priority_enc
|
#include <bits/stdc++.h> using namespace std; struct ww { long long x, y; } c[400][400]; int i, j, k, n, m, ma, ren, C, kuai; int cov[400], zhi[400]; long long b[400][400], s[400][400]; vector<int> a[100010]; inline void gao(int x) { int i, n = kuai - 1, g[400], r = 0; long long jum[400]; for (i = 0; i <= n; i++) b[x][i] += cov[x]; cov[x] = 0; s[x][0] = b[x][0]; for (i = 1; i <= n; i++) s[x][i] = s[x][i - 1] + b[x][i]; for (i = 0; i <= n; i++) { long long A = s[x][i], F = 0; for (; r; r--) { int wei = g[r]; long long B = s[x][wei]; int cha = i - wei; if (A >= B) continue; long long ci = (B - A) / cha + ((B - A) % cha > 0); if (jum[r] >= ci) continue; else { F = ci; break; } } g[++r] = i, jum[r] = F; } jum[r + 1] = 100010; for (i = 1; i <= r; i++) c[x][i] = (ww){g[i], jum[i + 1]}; zhi[x] = 1; } inline void jian(int x) { int A = x / kuai, B = x % kuai; b[A][B] -= x; gao(A); } inline void jia(int x) { if (x < 0) return; int A = x / kuai, B = x % kuai, i; for (i = 0; i <= A - 1; i++) { cov[i]++; if (c[i][zhi[i]].y == cov[i]) zhi[i]++; } for (i = 0; i <= B; i++) b[A][i]++; gao(A); } inline long long suan(int x) { ww A = c[x][zhi[x]]; return s[x][A.x] + 1ll * cov[x] * (A.x + 1); } inline ww cal() { int i, id; long long ma, sum; ma = -1, sum = 0; for (i = 0; i <= 400 - 1; i++) { long long re = sum + suan(i); if (re > ma) ma = re, id = i * kuai + c[i][zhi[i]].x; sum += s[i][kuai - 1] + 1ll * cov[i] * kuai; } return (ww){ma, id}; } int main() { kuai = 300; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) { int x, y; scanf( %d%d , &x, &y); a[y].push_back(x - 1); ma = max(ma, y); } for (i = 0; i <= 400 - 1; i++) gao(i); ren = n; for (C = 0; C <= ma + 1; C++) { ww re = cal(); printf( %I64d %I64d n , 1ll * ren * C * m + re.x, re.y + 1); for (j = 0; j < a[C].size(); j++) { int A = a[C][j]; ren--; jia(A); jian(A + 1); } } return 0; }
|
// Atari XL/XE SD cartridge
// Copyright (C) 2013 Piotr Wiszowaty
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
`timescale 1ns / 1ps
module main(
input cart_fi2,
output cart_fi2_copy,
input fi2,
input cart_s4,
input cart_s5,
input cart_rw,
input cart_cctl,
output reg cart_rd4 = 1,
output reg cart_rd5 = 1,
input [12:0] cart_addr,
inout [7:0] cart_data,
output ram_oe,
output ram_we,
output [14:0] ram_addr,
inout [7:0] ram_data,
input clk,
inout [7:0] uc_data,
output reg uc_ack = 0,
input uc_read,
input uc_write,
input set_addr_lo,
input set_addr_hi,
input strobe_addr,
output aux0,
input aux1,
input cart_write_enable,
/*input aux3,*/
/*input aux4,*/
/*input aux5,*/
output dbg0,
output dbg1);
wire cart_select;
wire cart_ram_select;
wire cart_d5_select;
wire cart_d5ef_select;
wire fi2_falling;
wire fi2_rising;
reg state_cart_write = 0;
reg state_cart_read = 0;
reg state_uc_write = 0;
reg state_uc_read = 0;
reg [1:0] phase = 2'b01;
reg [1:0] fi2_r = 2'b00;
reg s4_r = 1;
reg s5_r = 1;
reg rw_r = 1;
reg cctl_r = 1;
reg rd4_r = 1;
reg rd5_r = 1;
reg [7:0] cart_out_data_latch;
reg [14:0] uc_addr = 0;
reg [7:0] uc_out_data_latch = 0;
reg [13:0] read_address = 0;
assign cart_fi2_copy = cart_fi2 ^ aux1;
assign fi2_falling = fi2_r[1] & ~fi2_r[0];
assign fi2_rising = ~fi2_r[1] & fi2_r[0];
assign cart_ram_select = s4_r ^ s5_r;
assign cart_d5_select = ~cctl_r & (cart_addr[7:3] == 5'b11101); // D5E8-D5EF
//assign cart_d5ef_select = ~cctl_r & (cart_addr[7:0] == 8'b11101111); // D5EF
assign cart_d5ef_select = cart_d5_select & cart_addr[2:0] == 3'b111;
assign cart_select = cart_ram_select | cart_d5_select;
assign cart_data = (cart_select & cart_rw & cart_fi2) ? cart_out_data_latch : 8'hzz;
assign ram_addr = (state_cart_read & cart_d5ef_select) ? {1'b1, read_address} :
(state_cart_write | state_cart_read) ? {cctl_r, s4_r, cart_addr} :
uc_addr;
assign ram_data = state_cart_write ? cart_data :
state_uc_write ? uc_data :
8'hzz;
assign uc_data = uc_read ? uc_out_data_latch : 8'hzz;
always @(posedge strobe_addr) begin
if (set_addr_lo)
uc_addr[7:0] <= uc_data;
else if (set_addr_hi)
uc_addr[14:8] <= uc_data[6:0];
else
uc_addr <= uc_addr + 1;
end
always @(posedge fi2) begin
s4_r <= cart_s4;
s5_r <= cart_s5;
rw_r <= cart_rw;
cctl_r <= cart_cctl;
end
always @(posedge clk) begin
fi2_r <= {fi2_r[0], fi2};
if (state_cart_write | state_cart_read | state_uc_write | state_uc_read)
case (phase)
2'b01: phase <= 2'b11;
2'b11: phase <= 2'b10;
2'b10: phase <= 2'b00;
2'b00: phase <= 2'b01;
endcase
case ({state_cart_write, state_cart_read, state_uc_write, state_uc_read})
// idle
4'b0000:
if (fi2_rising & ~rw_r & (cart_d5_select | (cart_ram_select & cart_write_enable)))
state_cart_write <= 1;
else if (fi2_rising & rw_r & cart_select)
state_cart_read <= 1;
else if (fi2_falling & uc_write & ~uc_ack)
state_uc_write <= 1;
else if (fi2_falling & uc_read & ~uc_ack)
state_uc_read <= 1;
// cart write
4'b1000:
if (phase == 2'b00)
state_cart_write <= 0;
// cart read
4'b0100:
if (phase == 2'b00)
state_cart_read <= 0;
// uc write
4'b0010:
if (phase == 2'b00)
state_uc_write <= 0;
// uc read
4'b0001:
if (phase == 2'b00)
state_uc_read <= 0;
endcase
if (state_cart_read & phase == 2'b10)
cart_out_data_latch <= ram_data;
if (cart_d5_select & state_cart_write & phase[1] & cart_addr[2:0] == 3'b111)
{rd5_r, rd4_r} <= cart_data[7:6];
if (state_uc_read & phase == 2'b10)
uc_out_data_latch <= ram_data;
if ((state_uc_write | state_uc_read) & phase == 2'b00)
uc_ack <= 1;
else if (~uc_write & ~uc_read)
uc_ack <= 0;
if (fi2_rising & ~cart_select)
{cart_rd5, cart_rd4} <= {rd5_r, rd4_r};
if (state_cart_read & cart_d5ef_select & phase == 2'b00)
read_address <= read_address + 1;
else if (state_cart_write & cart_d5ef_select & phase == 2'b00)
read_address <= {cart_data[4:0], 9'b0};
end
assign ram_oe = ~(state_cart_read | state_uc_read);
assign ram_we = ~((state_cart_write | state_uc_write) & phase[1]);
assign dbg0 = state_uc_read;
assign dbg1 = ram_oe;
assign aux0 = 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct road { int x, next; double dis; } r[305 * 305 * 2]; int N, M; int st[305], w; int vis[305]; double P[305]; double l1 = -1, r1 = 0, mid; double dis[305]; void add(int x, int y, double dis) { r[++w].x = y, r[w].next = st[x]; r[w].dis = dis; st[x] = w; } bool work(int x) { int i, j, tmp; if (vis[x]) return true; vis[x] = 1; for (i = st[x]; i; i = r[i].next) { tmp = r[i].x; if (dis[tmp] > dis[x] + r[i].dis - mid) { dis[tmp] = dis[x] + r[i].dis - mid; if (work(tmp)) return true; } } vis[x] = 0; return false; } int main() { int i, j; int fr, to; scanf( %d , &N); for (i = 0; i <= N; i++) scanf( %lf , &P[i]); M = N * 3; for (i = 0; i <= M; i++) for (j = N, fr = i; j >= -N; j -= 2) { to = fr + j; if (to > M || to < 0) continue; add(fr, to, -P[(N - j) / 2]); } for (i = 1; i <= 21; i++) { mid = (l1 + r1) / 2; for (j = 1; j <= 20; j++) { memset(dis, 63, sizeof(dis)); memset(vis, 0, sizeof(vis)); fr = rand() % M + 1, dis[fr] = 0; if (work(fr)) break; } if (j <= 9) r1 = mid; else l1 = mid; } printf( %.8lf n , -mid); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTN_1_V
`define SKY130_FD_SC_HS__SDFRTN_1_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog wrapper for sdfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtn_1 (
RESET_B,
CLK_N ,
D ,
Q ,
SCD ,
SCE ,
VPWR ,
VGND
);
input RESET_B;
input CLK_N ;
input D ;
output Q ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfrtn base (
.RESET_B(RESET_B),
.CLK_N(CLK_N),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtn_1 (
RESET_B,
CLK_N ,
D ,
Q ,
SCD ,
SCE
);
input RESET_B;
input CLK_N ;
input D ;
output Q ;
input SCD ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfrtn base (
.RESET_B(RESET_B),
.CLK_N(CLK_N),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTN_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_p0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_p0(/*AUTOARG*/
// Outputs
pcx_spc0_grant_bufp0_pa, spc0_pcx_req_bufp0_pq,
spc0_pcx_atom_bufp0_pq, spc1_pcx_req_bufp0_pq,
spc1_pcx_atom_bufp0_pq,
// Inputs
spc0_pcx_req_bufpt_pq_l, spc0_pcx_atom_bufpt_pq_l,
spc1_pcx_req_bufpt_pq_l, spc1_pcx_atom_bufpt_pq_l,
pcx_spc0_grant_bufp1_pa_l
);
output [4:0] pcx_spc0_grant_bufp0_pa;
output [4:0] spc0_pcx_req_bufp0_pq;
output spc0_pcx_atom_bufp0_pq;
output [4:0] spc1_pcx_req_bufp0_pq;
output spc1_pcx_atom_bufp0_pq;
input [4:0] spc0_pcx_req_bufpt_pq_l;
input spc0_pcx_atom_bufpt_pq_l;
input [4:0] spc1_pcx_req_bufpt_pq_l;
input spc1_pcx_atom_bufpt_pq_l;
input [4:0] pcx_spc0_grant_bufp1_pa_l;
assign spc0_pcx_req_bufp0_pq[4:0] = ~spc0_pcx_req_bufpt_pq_l[4:0];
assign spc0_pcx_atom_bufp0_pq = ~spc0_pcx_atom_bufpt_pq_l;
assign pcx_spc0_grant_bufp0_pa = ~pcx_spc0_grant_bufp1_pa_l;
assign spc1_pcx_req_bufp0_pq[4:0] = ~spc1_pcx_req_bufpt_pq_l[4:0];
assign spc1_pcx_atom_bufp0_pq = ~spc1_pcx_atom_bufpt_pq_l;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A2BB2O_PP_BLACKBOX_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long double pi = acos(-1); const long long int mod = 1000000007; const double epsilon = 1e-9; template <class T> ostream &operator<<(ostream &out, vector<T> &A) { for (auto x : A) out << x << ; return out; } template <class T> ostream &operator<<(ostream &out, set<T> &A) { for (auto x : A) out << x << ; return out; } template <class T> ostream &operator<<(ostream &out, unordered_set<T> &A) { for (auto x : A) out << x << ; return out; } template <class T1, class T2> T1 powr(T1 a, T2 b) { T1 res = 1; for (long long int i = 1; i < b + 1; i++) res = res * a; return res; } long long int binpow(long long int a, long long int b) { a = a % mod; long long int res = 1; while (b > 0) { if (b & 1) res = (res * a) % mod; a = (a * a) % mod; b >>= 1; } return (res + mod) % mod; } const long long int N = 10000025; long long int prime[10000000]; void SieveOfEratosthenes() { for (long long int i = 0; i < N; i++) prime[i] = 1; prime[0] = 0; prime[1] = 0; for (long long int p = 2; p * p <= 10000000; p++) { if (prime[p] == 1) { for (long long int i = p * p; i <= 10000000; i += p) prime[i] = 0; } } } int32_t main() { std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int t; cin >> t; while (t--) { long long int n; cin >> n; long long int sum = 0, cnt = 0; for (long long int i = 1; i < 100000; i++) { long long int x = pow(2, i) - 1; if (n - (x * (x + 1)) / 2 >= 0) { n -= (x * (x + 1) / 2); cnt++; } else { break; } } cout << cnt << n ; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A2BB2OI_FUNCTIONAL_PP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> int g[102][102]; int main() { int n, t, sum = 0; scanf( %d , &n); t = n / 2; for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) scanf( %d , &g[i][j]); for (int i = 0; i < n; ++i) sum += g[i][i] + g[i][n - i - 1] + g[t][i] + g[i][t]; sum -= 3 * g[t][t]; printf( %d n , sum); }
|
#include <bits/stdc++.h> using namespace std; int n, a[300010], s[300010], x[2]; long long p; int main() { int i, j; long long k; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %lld , &k); for (j = 0; j <= 60; j++) if (k & (1ll << j)) a[i]++; s[i] = s[i - 1] + a[i]; } x[0] = 1; for (i = 1; i <= n; i++) { p += x[s[i] & 1]; x[s[i] & 1]++; for (j = i, k = 0; j > 0 && i - j <= 80; j--) { k = max(k, (long long)a[j]); if (!(s[i] - s[j - 1] & 1) && k * 2 > s[i] - s[j - 1]) p--; } } cout << p << n ; return 0; }
|
#include <bits/stdc++.h> int main() { const double eps = 1e-6; double x[3], y[3]; for (int i = 0; i < 3; ++i) scanf( %lf%lf , &x[i], &y[i]); x[1] -= x[0]; x[2] -= x[0]; y[1] -= y[0]; y[2] -= y[0]; x[0] = y[0] = 0; double cx = (y[2] * (x[1] * x[1] + y[1] * y[1]) - y[1] * (x[2] * x[2] + y[2] * y[2])) / (x[1] * y[2] - x[2] * y[1]) / 2; double cy = (x[2] * (x[1] * x[1] + y[1] * y[1]) - x[1] * (x[2] * x[2] + y[2] * y[2])) / (x[2] * y[1] - x[1] * y[2]) / 2; double dx[3], dy[3]; for (int i = 0; i < 3; ++i) dx[i] = x[i] - cx, dy[i] = y[i] - cy; double sin_t1 = (dx[0] * dy[1] - dx[1] * dy[0]) / (dx[0] * dx[0] + dy[0] * dy[0]); double cos_t1 = (dx[0] * dx[1] + dy[0] * dy[1]) / (dx[0] * dx[0] + dy[0] * dy[0]); double sin_t2 = (dx[0] * dy[2] - dx[2] * dy[0]) / (dx[0] * dx[0] + dy[0] * dy[0]); double cos_t2 = (dx[0] * dx[2] + dy[0] * dy[2]) / (dx[0] * dx[0] + dy[0] * dy[0]); for (int n = 3; n <= 100; ++n) { for (int i = 1; i < n; ++i) { if (fabs(sin_t1 - sin(2 * M_PI / n * i)) > eps || fabs(cos_t1 - cos(2 * M_PI / n * i)) > eps) continue; for (int j = 1; j < n; ++j) { if (fabs(sin_t2 - sin(2 * M_PI / n * j)) > eps || fabs(cos_t2 - cos(2 * M_PI / n * j)) > eps) continue; printf( %.9f n , (dx[0] * dx[0] + dy[0] * dy[0]) * sin(2 * M_PI / n) * n / 2); return 0; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int a, b, c; cin >> a >> b >> c; if (b >= a && c >= a) cout << YES n ; else cout << NO n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 00:48:00 01/25/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #3 Project
// Module Name: Key_Synchronizer_Module
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Key input signal synchronizer to align asynchronous key
// press signals to the system clock. Also, provides a
// key lockout so only one key press will be generated per
// lockout delay period.
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module Key_Synchronizer_Module
#(
parameter CLK_RATE_HZ = 50000000, // Hz
parameter KEY_LOCK_DELAY = 800000000 // nS
)
(
// Input Signals
input KEY,
// Output Signals
output reg KEY_EVENT,
// System Signals
input CLK
);
// Include Standard Functions header file (needed for bit_index())
`include "StdFunctions.vh"
//
// Synchronize Key Input to System Clock
//
wire key_sync;
CDC_Input_Synchronizer
#(
.SYNC_REG_LEN( 2 )
)
key_synchronizer
(
// Input Signal
.ASYNC_IN( ~KEY ),
// Output Signal
.SYNC_OUT( key_sync ),
// System Signals
.CLK( CLK )
);
//
// Key Lockout Counter
//
localparam KEY_LOCK_DELAY_TICKS = (1.0 * KEY_LOCK_DELAY) / (.0 / CLK_RATE_HZ);
localparam KEY_LOCK_WIDTH = bit_index(KEY_LOCK_DELAY_TICKS);
localparam [KEY_LOCK_WIDTH:0] KEY_LOCK_LOADVAL = {1'b1, {(KEY_LOCK_WIDTH-1){1'b0}}, 1'b1} - KEY_LOCK_DELAY_TICKS;
wire key_lock_out;
reg [KEY_LOCK_WIDTH:0] key_lock_counter_reg;
assign key_lock_out = ~key_lock_counter_reg[KEY_LOCK_WIDTH];
initial
begin
// Startout with the key enabled
key_lock_counter_reg <= { 1'b1, {KEY_LOCK_WIDTH{1'b0}} };
end
// !! LAB 3: Impement Key Lockout Counter Here !!
always@(posedge CLK)
begin
if((key_lock_out == 0) && (key_sync == 0))
key_lock_counter_reg <= key_lock_counter_reg;
else if((key_lock_out == 0) && (key_sync == 1))
key_lock_counter_reg <= KEY_LOCK_LOADVAL;
else if((key_lock_out == 1) && (key_sync == 0))
key_lock_counter_reg <= key_lock_counter_reg + 1'b1;
else
key_lock_counter_reg <= key_lock_counter_reg + 1'b1;
end
//
// Key Event Register
//
// !! LAB 3: Add KEY_EVENT Register Implementation Here !!
always@(posedge CLK)
begin
KEY_EVENT <= key_sync & ~key_lock_out;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, g; cin >> n >> g; vector<long long> v, ans; map<long long, long long> m; map<long long, long long>::iterator it; for (int i = 0; i < n; i++) { long long a; cin >> a; m[a]++; } for (it = m.begin(); it != m.end(); ++it) { v.push_back(it->second); } long long s1 = 0; for (int i = 0; i < v.size() - 1; i++) { long long s = 0; for (int j = i + 1; j < v.size(); j++) { s += v[j]; } s1 += s * v[i]; } cout << s1 << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DFBBP_BEHAVIORAL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBP_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211OI_TB_V
`define SKY130_FD_SC_HDLL__A211OI_TB_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a211oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hdll__a211oi dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211OI_TB_V
|
module EX_MEM(
input Clk,
input stall,
input flush,
input [31:0]Branch_addr_EX,
input [5:0]op_EX,
input [2:0]Condition_EX,
input Branch_EX,
input MemWrite_EX,
input RegWrite_EX,
input MemRead_EX,
input [31:0]MemData_EX,
input [31:0]WBData_EX,
input Less_EX,
input Zero_EX,
input Overflow_EX,
input [4:0]Rd_EX,
output reg [31:0]Branch_addr_MEM,
output reg [5:0]op_MEM,
output reg [2:0]Condition_MEM,
output reg Branch_MEM,
output reg MemWrite_MEM,
output reg RegWrite_MEM,
output reg MemRead_MEM,
output reg [31:0]MemData_MEM,
output reg [31:0]WBData_MEM,
output reg Less_MEM,
output reg Zero_MEM,
output reg Overflow_MEM,
output reg [4:0]Rd_MEM
);
initial
begin
Branch_addr_MEM=32'b0;
op_MEM=6'b0;
Condition_MEM=3'b0;
Branch_MEM=0;
MemWrite_MEM=0;
RegWrite_MEM=0;
MemRead_MEM=0;
MemData_MEM=2'b0;
WBData_MEM=32'b0;
Less_MEM=0;
Zero_MEM=0;
Overflow_MEM=0;
Rd_MEM=5'b0;
end
always @(negedge Clk)begin
if(flush)begin//冲刷，防止出错
op_MEM <= 0;
Condition_MEM <= 0;
Branch_MEM <= 0;
MemWrite_MEM <= 0;
RegWrite_MEM <= 0;
MemRead_MEM <= 0;
MemData_MEM <= 0;
WBData_MEM <= 0;
Less_MEM <= 0;
Zero_MEM <= 0;
Overflow_MEM <= 0;
Rd_MEM <= 0;
end
else if(!stall)begin//如果不是保持就继续向下传递流水
Branch_addr_MEM <= Branch_addr_EX;
op_MEM <= op_EX;
Condition_MEM <= Condition_EX;
Branch_MEM <= Branch_EX;
MemWrite_MEM <= MemWrite_EX;
RegWrite_MEM <= RegWrite_EX;
MemRead_MEM <= MemRead_EX;
MemData_MEM <= MemData_EX;
WBData_MEM <= WBData_EX;
Less_MEM <= Less_EX;
Zero_MEM <= Zero_EX;
Overflow_MEM <= Overflow_EX;
Rd_MEM <= Rd_EX;
end
// 否则就是保持，也即什么赋值也不需要做继续保持
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; long long ans = 0; for (int i = (0); i < (n); ++i) { long long t, T, x, cost; cin >> t >> T >> x >> cost; if (t >= T) { ans += cost + m * x; continue; } long long aux1 = cost; if (m > (T - t)) aux1 += m * x; long long aux2 = (long long)ceil((double)(m - (T - t)) / (T - t)) + 1; aux2 *= cost; ans += min(aux1, aux2); } cout << ans << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
module some_module (
input [3:0] i_clks
);
logic [ 1 : 0 ] some_state;
logic [1:0] some_other_state;
logic the_clk;
assign the_clk = i_clks[3];
always @(posedge the_clk) begin
case (some_state)
2'b11:
if (some_other_state == 0)
some_state <= 2'b00;
default:
$display ("This is a display statement");
endcase
if (the_clk)
some_other_state <= 0;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
`define BROKEN
module t1(
input [3:0] i_clks,
input i_clk0,
input i_clk1
);
some_module
some_module
(
.i_clks (i_clks)
);
endmodule
module ident(
input i_ident,
output o_ident
);
assign o_ident = i_ident;
endmodule
module t2(
input [2:0] i_clks,
input i_clk0,
input i_clk1,
input i_clk2,
input i_data
);
logic [3:0] the_clks;
logic data_q;
logic ident_clk1;
always @(posedge i_clk0) begin
data_q <= i_data;
end
ident
ident
(
.i_ident (i_clk1),
.o_ident (ident_clk1)
);
t1 t1
(
.i_clks ({ident_clk1, i_clk2, ident_clk1, i_clk0}),
.i_clk0 (i_clk0),
.i_clk1 (i_clk1)
);
endmodule
module t(
/*AUTOARG*/
// Inputs
clk /*verilator clocker*/ /*verilator public_flat*/,
input clk0 /*verilator clocker*/,
input clk1 /*verilator clocker*/,
input clk2 /*verilator clocker*/,
input data_in
);
input clk;
logic [2:0] clks;
assign clks = {1'b0, clk1, clk0};
t2
t2
(
.i_clks (clks),
.i_clk0 (clk0),
.i_clk1 (clk),
.i_clk2 (clk2),
.i_data (data_in)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k, a, b, ans; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> k >> a >> b; if (k == 1) { cout << (n - 1) * a; return 0; } while (n > 1) { if (n % k != 0 && n < k) { ans += (n - 1) * a; n = 1; } else if (n % k != 0) { ans += (n % k) * a; n -= (n % k); } else { long long temp, temp2, val; val = n / k; temp = (n - val) * a; ans += min(temp, b); n = val; } } cout << ans; return 0; }
|
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