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#include <bits/stdc++.h> using namespace std; const int N = (int)5e5 + 9; vector<int> T[N]; bool use[2 * N]; int p; int l[N], r[N]; void dfs(int u, int par) { if (par == -1) { l[u] = 1; r[u] = T[u].size() + 2; use[1] = true; use[T[u].size() + 2] = true; p = T[u].size() + 3; vector<pair<int, int> > srt; int fl = 2; for (auto x : T[u]) { if (x == par) continue; dfs(x, u); srt.push_back(make_pair(r[x], x)); } sort(srt.begin(), srt.end()); reverse(srt.begin(), srt.end()); for (int i = 0; i < srt.size(); i++) { l[srt[i].second] = fl++; } return; } vector<int> rr; for (auto x : T[u]) { if (x == par) { continue; } while (use[p]) p++; use[p] = true; rr.push_back(p); } while (use[p]) p++; r[u] = p; use[p] = true; vector<pair<int, int> > srt; for (int i = 0; i < T[u].size(); i++) { if (T[u][i] == par) continue; dfs(T[u][i], u); srt.push_back(make_pair(r[T[u][i]], T[u][i])); } sort(srt.begin(), srt.end()); reverse(srt.begin(), srt.end()); for (int i = 0; i < srt.size(); i++) { l[srt[i].second] = rr[i]; } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int n; cin >> n; int x, y; for (int i = 1; i < n; i++) { cin >> x >> y; T[x].push_back(y); T[y].push_back(x); } dfs(1, -1); for (int i = 1; i <= n; i++) cout << l[i] << << r[i] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Z = (int)2e5 + 111; const int inf = (int)1e9 + 111; const long long llinf = (long long)1e18 + 5; const int MOD = (int)1e9 + 7; vector<long long> pref[4 * Z]; vector<int> t[4 * Z]; int a[Z]; void build(int v, int vl, int vr) { if (vl == vr) { t[v].push_back(a[vl]); pref[v].push_back(a[vl]); return; } int vm = (vl + vr) / 2; build(2 * v, vl, vm); build(2 * v + 1, vm + 1, vr); merge((t[2 * v]).begin(), (t[2 * v]).end(), (t[2 * v + 1]).begin(), (t[2 * v + 1]).end(), back_inserter(t[v])); pref[v].resize((int)t[v].size()); pref[v][0] = t[v][0]; for (int i = 1; i < (int)t[v].size(); ++i) { pref[v][i] = pref[v][i - 1] + t[v][i]; } } pair<long long, long long> query(int v, int vl, int vr, int l, int r, int val1, int val2) { if (vl > r || vr < l) return make_pair(0, 0); if (l <= vl && r >= vr) { long long cnt = upper_bound((t[v]).begin(), (t[v]).end(), val2) - lower_bound((t[v]).begin(), (t[v]).end(), val1); int posL = lower_bound((t[v]).begin(), (t[v]).end(), val1) - t[v].begin(); int posR = upper_bound((t[v]).begin(), (t[v]).end(), val2) - t[v].begin(); posR--; long long sum; if (posR == -1) sum = 0; else sum = pref[v][posR] - (posL == 0 ? 0 : pref[v][posL - 1]); return make_pair(sum, cnt); } int vm = (vl + vr) / 2; pair<long long, long long> ql = query(2 * v, vl, vm, l, r, val1, val2); pair<long long, long long> qr = query(2 * v + 1, vm + 1, vr, l, r, val1, val2); return make_pair(ql.first + qr.first, ql.second + qr.second); } int main() { srand(time(0)); ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; } build(1, 1, n); long double ans = 0; for (int i = 1; i <= n; ++i) { pair<long long, long long> l; if (a[i] - 2 >= 1) l = query(1, 1, n, i + 1, n, 1, a[i] - 2); else l = make_pair(0, 0); pair<long long, long long> r = query(1, 1, n, i + 1, n, a[i] + 2, inf); ans += l.first + r.first - (l.second + r.second) * a[i]; } cout << fixed << setprecision(0) << ans; return 0; }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
* Copyright (C) 2007 Das Labor
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart_transceiver(
input sys_rst,
input sys_clk,
input uart_rx,
output reg uart_tx,
input [15:0] divisor,
output reg [7:0] rx_data,
output reg rx_done,
input [7:0] tx_data,
input tx_wr,
output reg tx_done
);
//-----------------------------------------------------------------
// enable16 generator
//-----------------------------------------------------------------
reg [15:0] enable16_counter;
wire enable16;
assign enable16 = (enable16_counter == 16'd0);
always @(posedge sys_clk) begin
if(sys_rst)
enable16_counter <= divisor - 16'b1;
else begin
enable16_counter <= enable16_counter - 16'd1;
if(enable16)
enable16_counter <= divisor - 16'b1;
end
end
//-----------------------------------------------------------------
// Synchronize uart_rx
//-----------------------------------------------------------------
reg uart_rx1;
reg uart_rx2;
always @(posedge sys_clk) begin
uart_rx1 <= uart_rx;
uart_rx2 <= uart_rx1;
end
//-----------------------------------------------------------------
// UART RX Logic
//-----------------------------------------------------------------
reg rx_busy;
reg [3:0] rx_count16;
reg [3:0] rx_bitcount;
reg [7:0] rx_reg;
always @(posedge sys_clk) begin
if(sys_rst) begin
rx_done <= 1'b0;
rx_busy <= 1'b0;
rx_count16 <= 4'd0;
rx_bitcount <= 4'd0;
end else begin
rx_done <= 1'b0;
if(enable16) begin
if(~rx_busy) begin // look for start bit
if(~uart_rx2) begin // start bit found
rx_busy <= 1'b1;
rx_count16 <= 4'd7;
rx_bitcount <= 4'd0;
end
end else begin
rx_count16 <= rx_count16 + 4'd1;
if(rx_count16 == 4'd0) begin // sample
rx_bitcount <= rx_bitcount + 4'd1;
if(rx_bitcount == 4'd0) begin // verify startbit
if(uart_rx2)
rx_busy <= 1'b0;
end else if(rx_bitcount == 4'd9) begin
rx_busy <= 1'b0;
if(uart_rx2) begin // stop bit ok
rx_data <= rx_reg;
rx_done <= 1'b1;
end // ignore RX error
end else
rx_reg <= {uart_rx2, rx_reg[7:1]};
end
end
end
end
end
//-----------------------------------------------------------------
// UART TX Logic
//-----------------------------------------------------------------
reg tx_busy;
reg [3:0] tx_bitcount;
reg [3:0] tx_count16;
reg [7:0] tx_reg;
always @(posedge sys_clk) begin
if(sys_rst) begin
tx_done <= 1'b0;
tx_busy <= 1'b0;
uart_tx <= 1'b1;
end else begin
tx_done <= 1'b0;
if(tx_wr) begin
tx_reg <= tx_data;
tx_bitcount <= 4'd0;
tx_count16 <= 4'd1;
tx_busy <= 1'b1;
uart_tx <= 1'b0;
`ifdef SIMULATION
$display("UART: %c", tx_data);
`endif
end else if(enable16 && tx_busy) begin
tx_count16 <= tx_count16 + 4'd1;
if(tx_count16 == 4'd0) begin
tx_bitcount <= tx_bitcount + 4'd1;
if(tx_bitcount == 4'd8) begin
uart_tx <= 1'b1;
end else if(tx_bitcount == 4'd9) begin
uart_tx <= 1'b1;
tx_busy <= 1'b0;
tx_done <= 1'b1;
end else begin
uart_tx <= tx_reg[0];
tx_reg <= {1'b0, tx_reg[7:1]};
end
end
end
end
end
endmodule
|
// megafunction wizard: %LPM_ABS%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_abs
// ============================================================
// File Name: ABS.v
// Megafunction Name(s):
// lpm_abs
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ABS (
data,
result);
input [29:0] data;
output [29:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: OptionalOverflowOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "30"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ABS"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
// Retrieval info: USED_PORT: data 0 0 30 0 INPUT NODEFVAL data[29..0]
// Retrieval info: USED_PORT: result 0 0 30 0 OUTPUT NODEFVAL result[29..0]
// Retrieval info: CONNECT: @data 0 0 30 0 data 0 0 30 0
// Retrieval info: CONNECT: result 0 0 30 0 @result 0 0 30 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ABS_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; vector<int> cr1[27]; vector<int> cr2[27]; int s1[27]; int s2[27]; struct node { int x; int y; }; int main() { int n; cin >> n; char c; for (int i = 0; i < n; i++) { cin >> c; if (c == ? ) { s1[26]++; cr1[26].push_back(i); } else { s1[c - a ]++; cr1[c - a ].push_back(i); } } for (int i = 0; i < n; i++) { cin >> c; if (c == ? ) { s2[26]++; cr2[26].push_back(i); } else { s2[c - a ]++; cr2[c - a ].push_back(i); } } int cnt = 0; vector<node> nd; for (int i = 0; i < 26; i++) { int x = s1[i] - 1; int y = s2[i] - 1; while (x >= 0 && y >= 0) { node n1; n1.x = cr1[i][x]; n1.y = cr2[i][y]; nd.push_back(n1); cnt++; x--; y--; } if (x >= 0 && y < 0) { node n1; while (x >= 0 && s2[26] > 0) { n1.x = cr1[i][x]; n1.y = cr2[26][s2[26] - 1]; nd.push_back(n1); cnt++; s2[26]--; x--; } } else if (x < 0 && y >= 0) { node n1; while (y >= 0 && s1[26] > 0) { n1.x = cr1[26][s1[26] - 1]; n1.y = cr2[i][y]; nd.push_back(n1); cnt++; s1[26]--; y--; } } } while (s1[26] > 0 && s2[26] > 0) { node n1; n1.x = cr1[26][s1[26] - 1]; n1.y = cr2[26][s2[26] - 1]; nd.push_back(n1); cnt++; s1[26]--; s2[26]--; } cout << cnt << endl; for (int i = 0; i < nd.size(); i++) cout << nd[i].x + 1 << << nd[i].y + 1 << endl; }
|
#include <bits/stdc++.h> using namespace std; string CHECK(long long n) { long long t, temp = n, zero = 0, ans = 0, flag = 0; while (temp != 0) { t = temp % 10; if (t == 0 && flag == 0) zero++; else { flag = 1; ans *= 10; ans += t; } temp /= 10; } if (zero != 0) { while (zero != 0) { ans *= 10; zero--; } } if (n == ans) return YES ; else return NO ; } int main() { long long n; cin >> n; cout << CHECK(n) << endl; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp_macb_l.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of PCX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp_macb_l(/*AUTOARG*/
// Outputs
data_out_px_l, scan_out, shiftenable_buf,
// Inputs
arb_pcxdp_qsel1_pa, arb_pcxdp_qsel0_pa, arb_pcxdp_grant_pa,
arb_pcxdp_shift_px, arb_pcxdp_q0_hold_pa, src_pcx_data_pa,
data_prev_px_l, rclk, scan_in, shiftenable
);
output [129:0] data_out_px_l; // pcx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_pcxdp_qsel1_pa; // queue write sel
input arb_pcxdp_qsel0_pa; // queue write sel
input arb_pcxdp_grant_pa;//grant signal
input arb_pcxdp_shift_px;//grant signal
input arb_pcxdp_q0_hold_pa;//grant signal
input [129:0] src_pcx_data_pa; // spache to pcx data
input [129:0] data_prev_px_l;
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_px;
wire [129:0] q0_datain_pa;
wire [129:0] q1_dataout, q0_dataout;
wire [129:0] data_px_l;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_pcxdp_q0_hold_pa),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_pcxdp_qsel1_pa),
.tmb_l(se_l));
// Latch and drive grant signal
// Generate write selects
dff_s #(1) dff_pcx_grin_r(
.din (arb_pcxdp_grant_pa),
.q (grant_px),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(130) dff_pcx_datain_q1(
.din (src_pcx_data_pa[129:0]),
.q (q1_dataout[129:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
/*
mux2ds #(`PCX_WIDTH) mx2ds_pcx_datain_q0(
.dout (q0_datain_pa[`PCX_WIDTH-1:0]),
.in0 (q1_dataout[`PCX_WIDTH-1:0]),
.in1 (src_pcx_data_pa[`PCX_WIDTH-1:0]),
.sel0 (arb_pcxdp_shift_px),
.sel1 (arb_pcxdp_qsel0_pa));
*/
assign q0_datain_pa[129:0] =
(arb_pcxdp_qsel0_pa ? src_pcx_data_pa[129:0] : 130'd0) |
(arb_pcxdp_shift_px ? q1_dataout[129:0] : 130'd0) ;
dff_s #(130) dff_pcx_datain_q0(
.din (q0_datain_pa[129:0]),
.q (q0_dataout[129:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_px_l[129:0] = ~(grant_px ? q0_dataout[129:0]:130'd0);
assign data_out_px_l[129:0] = data_px_l[129:0] & data_prev_px_l[129:0];
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int f[10]; for (int i = 0; i < 10; i++) { f[i] = 0; } for (int i = 0; i < 6; i++) { int tem; cin >> tem; f[tem]++; } int leg; int flag = 0; for (int i = 0; i < 10; i++) { if (f[i] >= 4) { flag = 1; f[i] = f[i] - 4; break; } } if (flag == 0) { cout << Alien n ; return 0; } int h = 0, b = 0; for (int i = 0; i < 10; i++) { if (f[i] != 0) { h = i; f[i] = f[i] - 1; } } for (int i = 0; i < 10; i++) { if (f[i] != 0) { b = i; } } if (h == b) { cout << Elephant n ; } else { cout << Bear n ; } return 0; }
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 02:34:31 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_rst_ps7_0_100M_0/zybo_zynq_design_rst_ps7_0_100M_0_stub.v
// Design : zybo_zynq_design_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2018.2" *)
module zybo_zynq_design_rst_ps7_0_100M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, ar[11][100005]; int rev[11][100005]; long long mx(int start) { int val = ar[0][start]; for (int tmp = 0; tmp < n; ++tmp) { for (int row = 1; row < m; ++row) { int col = rev[row][val]; if (col + tmp >= n) { return tmp; } int curVal = ar[row][col + tmp]; int val2 = ar[0][start + tmp]; if (curVal != val2) { return tmp; } } } return n; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; ++i) { for (int j = 0; j < n; ++j) { scanf( %d , ar[i] + j); rev[i][ar[i][j]] = j; } } long long ans = 0; for (int i = 0; i < n;) { long long mxi = mx(i); ans += (mxi * (mxi + 1) / 2ll); i += mxi; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Max = 50; int row[Max][Max] = {0}, dp[Max][Max][Max][Max] = {0}, a[Max][Max]; int main() { int n, m, q; cin >> n >> m >> q; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %1d , &a[i][j]); row[i][j] = row[i][j - 1] + 1; if (a[i][j] == 1) row[i][j] = 0; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { for (int k = i; k <= n; k++) { for (int l = j; l <= m; l++) { dp[i][j][k][l] = dp[i][j][k - 1][l] + dp[i][j][k][l - 1] - dp[i][j][k - 1][l - 1]; int r = l - j + 1; for (int z = k; z >= i; z--) { r = min(r, row[z][l]); dp[i][j][k][l] += r; } } } } } while (q--) { int a, b, c, d; scanf( %d%d%d%d , &a, &b, &c, &d); cout << dp[a][b][c][d] << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:23:05 04/19/2017
// Design Name:
// Module Name: decrypt
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decrypt(
message,
DESkey,
decrypted,
done,
clk,
reset,
enable,
ack
);
input [7:0][7:0] message;
input [7:0][7:0] DESkey;
output [7:0][7:0] decrypted;
input clk, reset, enable, ack;
output done;
reg [63:0] msg, key, result;
reg [5:0] state;
reg [55:0] k;
reg [63:0] ip;
integer pc1[55:0] = {57, 49, 41, 33, 25, 17, 9, 1,
58, 50, 42, 34, 26, 18, 10, 2,
59, 51, 43, 35, 27, 19, 11, 3,
60, 52, 44, 36, 63, 55, 47, 39,
31, 23, 15, 7, 62, 54, 46, 38,
30, 22, 14, 6, 61, 53, 45, 37,
29, 21, 13, 5, 28, 20, 12, 4};
integer mp[63:0] = {58, 50, 42, 34, 26, 18, 10, 2,
60, 52, 44, 36, 28, 20, 12, 4,
62, 54, 46, 38, 30, 22, 14, 6,
64, 56, 48, 40, 32, 24, 16, 8,
57, 49, 41, 33, 25, 17, 9, 1,
59, 51, 43, 35, 27, 19, 11, 3,
61, 53, 45, 37, 29, 21, 13, 5,
63, 55, 47, 39, 31, 23, 15, 7};
localparam
INITIAL = 6'b0000001,
FIRSTPERMUTATION_MESSAGE_KEY = 6'b0000010,
LOADSHIFTARRAYS = 6'b0000100,
CREATEALLKEYS = 6'b0001000,
CREATEALLMESSAGEPERMUTATIONS = 6'b0010000,
ENCRYPT = 6'b0100000,
DONE = 7'b1000000;
always @ (posedge clk, posedge reset)
begin
if(reset)
begin
state <= INITIAL;
msg <= 8'hX;
key <= 8'hX;
result <= 8'hX;
end
else
begin
case (state)
INITIAL:
begin
//state
state <= FIRSTPERMUTATION_MESSAGE_KEY;
//rtl
msg <= message;
key <= DESkey;
result <= 0;
end
FIRSTPERMUTATION_MESSAGE_KEY:
begin
integer i;
//state
state <= LOADSHIFTARRAYS;
//rtl
for(i = 0; i < 56; i = i + 1)
begin
integer index;
index = pc1[i];
k[i] <= key[index];
end
/*for(int i = 0; i < 64; i = i + 1)
begin
integer index;
index = mp[i] - 1;
ip[i] <= key[index];
end*/
end
LOADSHIFTARRAYS:
begin
end
CREATEALLKEYS:
begin
end
CREATEALLMESSAGEPERMUTATIONS:
begin
end
ENCRYPT:
begin
end
DONE:
begin
end
endcase
end
end
assign encrypted = result;
assign done = (state == DONE);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int ans = -1; int n, dol, cent, s, i; cin >> n >> s; for (i = 0; i < n; i++) { cin >> dol >> cent; if (s > dol && cent != 0 && 100 - cent > ans) ans = 100 - cent; if (s >= dol && cent == 0 && ans == -1) ans = 0; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; cin >> n >> m; long long a = n, b = m; while (1) { if (a <= 0 || b <= 0) break; if (a >= 2 * b) { a %= 2 * b; continue; } if (b >= 2 * a) { b %= 2 * a; continue; } break; } cout << a << << b << endl; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9680_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [55:0] adc_data;
input adc_or;
// channel interface
output [63:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad9680_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*14+13:n*14]),
.valid_out (),
.data_out (adc_dfmt_data[n*16+15:n*16]),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//---------------------------------------------------------------------------
//-- (c) 2016 Alexey Spirkov
//-- I am happy for anyone to use this for non-commercial use.
//-- If my verilog/vhdl/c files are used commercially or otherwise sold,
//-- please contact me for explicit permission at me _at_ alsp.net.
//-- This applies for source and binary form and derived works.
//
//-- Audio and infoframe packet generation mechanizms based on Charlie Cole 2015
//-- design of HDMI output for Neo Geo MVS
module hdmidataencoder
#(parameter FREQ=27000000, FS=48000, CTS=27000, N=6144)
(
input i_pixclk,
input i_hSync,
input i_vSync,
input i_blank,
input i_audio_enable,
input [15:0] i_audioL,
input [15:0] i_audioR,
output [3:0] o_d0,
output [3:0] o_d1,
output [3:0] o_d2,
output o_data
);
`define AUDIO_TIMER_ADDITION FS/1000
`define AUDIO_TIMER_LIMIT FREQ/1000
localparam [191:0] channelStatus = (FS == 48000)?192'hc202004004:(FS == 44100)?192'hc200004004:192'hc203004004;
localparam [55:0] audioRegenPacket = {N[7:0], N[15:8], 8'h00, CTS[7:0], CTS[15:8], 16'h0000};
reg [23:0] audioPacketHeader;
reg [55:0] audioSubPacket[3:0];
reg [7:0] channelStatusIdx;
reg [16:0] audioTimer;
reg [16:0] ctsTimer;
reg [1:0] samplesHead;
reg [3:0] dataChannel0;
reg [3:0] dataChannel1;
reg [3:0] dataChannel2;
reg [23:0] packetHeader;
reg [55:0] subpacket[3:0];
reg [7:0] bchHdr;
reg [7:0] bchCode [3:0];
reg [4:0] dataOffset;
reg tercData;
reg [25:0] audioRAvgSum;
reg [25:0] audioLAvgSum;
reg [15:0] audioRAvg;
reg [15:0] audioLAvg;
reg [10:0] audioAvgCnt;
reg [15:0] counterX;
reg firstHSyncChange;
reg oddLine;
reg prevHSync;
reg prevBlank;
reg allowGeneration;
initial
begin
audioPacketHeader<=0;
audioSubPacket[0]<=0;
audioSubPacket[1]<=0;
audioSubPacket[2]<=0;
audioSubPacket[3]<=0;
channelStatusIdx<=0;
audioTimer<=0;
samplesHead<=0;
ctsTimer = 0;
dataChannel0<=0;
dataChannel1<=0;
dataChannel2<=0;
packetHeader<=0;
subpacket[0]<=0;
subpacket[1]<=0;
subpacket[2]<=0;
subpacket[3]<=0;
bchHdr<=0;
bchCode[0]<=0;
bchCode[1]<=0;
bchCode[2]<=0;
bchCode[3]<=0;
dataOffset<=0;
tercData<=0;
oddLine<=0;
counterX<=0;
prevHSync = 0;
prevBlank = 0;
firstHSyncChange = 0;
allowGeneration = 0;
audioRAvg = 0;
audioLAvg = 0;
audioRAvgSum = 0;
audioLAvgSum = 0;
audioAvgCnt = 1;
end
function [7:0] ECCcode; // Cycles the error code generator
input [7:0] code;
input bita;
input passthroughData;
begin
ECCcode = (code<<1) ^ (((code[7]^bita) && passthroughData)?(1+(1<<6)+(1<<7)):0);
end
endfunction
task ECCu;
output outbit;
inout [7:0] code;
input bita;
input passthroughData;
begin
outbit <= passthroughData?bita:code[7];
code <= ECCcode(code, bita, passthroughData);
end
endtask
task ECC2u;
output outbita;
output outbitb;
inout [7:0] code;
input bita;
input bitb;
input passthroughData;
begin
outbita <= passthroughData?bita:code[7];
outbitb <= passthroughData?bitb:(code[6]^(((code[7]^bita) && passthroughData)?1'b1:1'b0));
code <= ECCcode(ECCcode(code, bita, passthroughData), bitb, passthroughData);
end
endtask
task SendPacket;
inout [32:0] pckHeader;
inout [55:0] pckData0;
inout [55:0] pckData1;
inout [55:0] pckData2;
inout [55:0] pckData3;
input firstPacket;
begin
dataChannel0[0]<=i_hSync;
dataChannel0[1]<=i_vSync;
dataChannel0[3]<=(!firstPacket || dataOffset)?1'b1:1'b0;
ECCu(dataChannel0[2], bchHdr, pckHeader[0], dataOffset<24?1'b1:1'b0);
ECC2u(dataChannel1[0], dataChannel2[0], bchCode[0], pckData0[0], pckData0[1], dataOffset<28?1'b1:1'b0);
ECC2u(dataChannel1[1], dataChannel2[1], bchCode[1], pckData1[0], pckData1[1], dataOffset<28?1'b1:1'b0);
ECC2u(dataChannel1[2], dataChannel2[2], bchCode[2], pckData2[0], pckData2[1], dataOffset<28?1'b1:1'b0);
ECC2u(dataChannel1[3], dataChannel2[3], bchCode[3], pckData3[0], pckData3[1], dataOffset<28?1'b1:1'b0);
pckHeader<=pckHeader[23:1];
pckData0<=pckData0[55:2];
pckData1<=pckData1[55:2];
pckData2<=pckData2[55:2];
pckData3<=pckData3[55:2];
dataOffset<=dataOffset+5'b1;
end
endtask
task InfoGen;
inout [16:0] _timer;
begin
if (_timer >= CTS) begin
packetHeader<=24'h000001; // audio clock regeneration packet
subpacket[0]<=audioRegenPacket;
subpacket[1]<=audioRegenPacket;
subpacket[2]<=audioRegenPacket;
subpacket[3]<=audioRegenPacket;
_timer <= _timer - CTS + 1;
end else begin
if (!oddLine) begin
packetHeader<=24'h0D0282; // infoframe AVI packet
// Byte0: Checksum (256-(S%256))%256
// Byte1: 10 = 0(Y1:Y0<=0 RGB)(A0=1 active format valid)(B1:B0=00 No bar info)(S1:S0=00 No scan info)
// Byte2: 19 = (C1:C0=0 No colorimetry)(M1:M0=1 4:3)(R3:R0=9 4:3 center)
// Byte3: 00 = 0(SC1:SC0=0 No scaling)
// Byte4: 00 = 0(VIC6:VIC0=0 custom resolution)
// Byte5: 00 = 0(PR5:PR0=0 No repeation)
subpacket[0]<=56'h00000000191046;
subpacket[1]<=56'h00000000000000;
end else begin
packetHeader<=24'h0A0184; // infoframe audio packet
// Byte0: Checksum (256-(S%256))%256
// Byte1: 11 = (CT3:0=1 PCM)0(CC2:0=1 2ch)
// Byte2: 00 = 000(SF2:0=0 As stream)(SS1:0=0 As stream)
// Byte3: 00 = LPCM doesn't use this
// Byte4-5: 00 Multichannel only (>2ch)
subpacket[0]<=56'h00000000001160;
subpacket[1]<=56'h00000000000000;
end
subpacket[2]<=56'h00000000000000;
subpacket[3]<=56'h00000000000000;
end
end
endtask
task AproximateAudio;
begin
audioLAvgSum <= audioLAvgSum + i_audioL;
audioRAvgSum <= audioRAvgSum + i_audioR;
audioLAvg <= audioLAvgSum/audioAvgCnt;
audioRAvg <= audioRAvgSum/audioAvgCnt;
audioAvgCnt <= audioAvgCnt + 1;
end
endtask
task AudioGen;
begin
// Buffer up an audio sample
// Don't add to the audio output if we're currently sending that packet though
if (!( allowGeneration && counterX >= 32 && counterX < 64)) begin
if (audioTimer>=`AUDIO_TIMER_LIMIT) begin
audioTimer<=audioTimer-`AUDIO_TIMER_LIMIT+`AUDIO_TIMER_ADDITION;
audioPacketHeader<=audioPacketHeader|24'h000002|((channelStatusIdx==0?24'h100100:24'h000100)<<samplesHead);
audioSubPacket[samplesHead]<=((audioLAvg<<8)|(audioRAvg<<32)
|((^audioLAvg)?56'h08000000000000:56'h0) // parity bit for left channel
|((^audioRAvg)?56'h80000000000000:56'h0)) // parity bit for right channel
^(channelStatus[channelStatusIdx]?56'hCC000000000000:56'h0); // And channel status bit and adjust parity
if (channelStatusIdx<191)
channelStatusIdx<=channelStatusIdx+8'd1;
else
channelStatusIdx<=0;
samplesHead<=samplesHead+2'd1;
audioLAvgSum <= 0;
audioRAvgSum <= 0;
audioAvgCnt <= 1;
end else begin
audioTimer<=audioTimer+`AUDIO_TIMER_ADDITION;
AproximateAudio();
end
end else begin
audioTimer<=audioTimer+`AUDIO_TIMER_ADDITION;
AproximateAudio();
samplesHead<=0;
end
end
endtask
task SendPackets;
inout dataEnable;
begin
if (counterX<32) begin
// Send first data packet (Infoframe or audio clock regen)
dataEnable<=1;
SendPacket(packetHeader, subpacket[0], subpacket[1], subpacket[2], subpacket[3], 1);
end else if (counterX<64) begin
// Send second data packet (audio data)
SendPacket(audioPacketHeader, audioSubPacket[0], audioSubPacket[1], audioSubPacket[2], audioSubPacket[3], 0);
end else begin
dataEnable<=0;
end
end
endtask
always @(posedge i_pixclk)
begin
AudioGen();
// Send 2 packets each line
if(allowGeneration & i_audio_enable) begin
SendPackets(tercData);
end else begin
tercData<=0;
end
ctsTimer <= ctsTimer + 1;
if((prevBlank == 0) && (i_blank == 1))
firstHSyncChange <= 1;
if((prevBlank == 1) && (i_blank == 0))
allowGeneration <= 0;
if(prevHSync != i_hSync) begin
if(firstHSyncChange) begin
InfoGen(ctsTimer);
oddLine <= ! oddLine;
counterX <= 0;
allowGeneration <= 1;
end else begin
counterX <= counterX + 1;
end
firstHSyncChange <= !firstHSyncChange;
end else
counterX <= counterX + 1;
prevBlank <= i_blank;
prevHSync <= i_hSync;
end
assign o_d0 = dataChannel0;
assign o_d1 = dataChannel1;
assign o_d2 = dataChannel2;
assign o_data = tercData;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_16_V
`define SKY130_FD_SC_HD__BUFBUF_16_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__bufbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_16_V
|
#include <bits/stdc++.h> using namespace std; int n, h; pair<int, int> arr[100010]; int res[100010]; int ptr = -1; int cnt, bits; int main() { cin >> n >> h; for (int i = 0; i < n; i++) { scanf( %d , &arr[i].first); arr[i].second = i; res[i] = 1; } sort(arr, arr + n); int ans = arr[n - 1].first + arr[n - 2].first - arr[0].first - arr[1].first; for (int i = n - 2; i >= 0; i--) { int mx = arr[i].first + arr[n - 1].first + h; if (i < n - 2) mx = max(mx, arr[n - 1].first + arr[n - 2].first); int init = min(7, i); int col[7]; if (i <= 6) { col[i] = 2; for (int j = i + 1; j < min(n, 7); j++) col[j] = 1; } for (int j = 0; j < (1 << init); j++) { for (int k = 0; k < init; k++) { col[k] = ((j & (1 << k)) ? 1 : 2); } int mn = 1000000000; for (int k = 0; k < min(n, 7); k++) { for (int l = k + 1; l < min(n, 7); l++) { int val = arr[k].first + arr[l].first; if (col[k] != col[l]) val += h; mn = min(mn, val); } } int dif = mx - mn; if (dif < ans) { ans = dif; ptr = i; cnt = init; bits = j; } } } if (ptr != -1) { for (int i = 0; i < cnt; i++) { res[arr[i].second] = ((bits & (1 << i)) ? 1 : 2); } res[arr[ptr].second] = 2; for (int i = ptr + 1; i < n; i++) res[arr[i].second] = 1; } cout << ans << endl; for (int i = 0; i < n; i++) { if (i) printf( ); printf( %d , res[i]); } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 123, INF = 1e9, mod = 1e9 + 7, N = 2e5 + 123; struct btr { map<int, long long> dp; set<pair<long long, int> > st; long long mn, add; }; vector<int> g[maxn]; int n, m; btr a[maxn]; void Merge(btr &a, btr &b) { if (a.dp.size() < b.dp.size()) swap(a, b); long long x = a.add, y = b.add; a.add += b.mn + y; b.add += a.mn + x; for (auto x : b.dp) { int v = x.first; long long c = x.second + b.add - a.add; if (!a.dp.count(v) || a.dp[v] > c) { a.st.erase({a.dp[v], v}); a.dp[v] = c; a.st.insert({a.dp[v], v}); } } if (!a.st.empty()) a.mn = a.st.begin()->first; } void dfs(int v, int p) { if (!a[v].st.empty()) a[v].mn = a[v].st.begin()->first; btr tmp; bool flag = 0; for (auto to : g[v]) { if (to == p) continue; dfs(to, v); if (!flag) swap(tmp, a[to]); else Merge(tmp, a[to]); flag = 1; a[to].dp.clear(); a[to].st.clear(); } if (flag) { for (auto x : a[v].dp) { int u = x.first; long long c = x.second + tmp.mn; if (!tmp.dp.count(u) || tmp.dp[u] > c) { tmp.st.erase({tmp.dp[u], u}); tmp.dp[u] = c; tmp.st.insert({tmp.dp[u], u}); } } swap(a[v], tmp); } if (v != 1 && a[v].dp.count(v)) { a[v].st.erase({a[v].dp[v], v}); a[v].dp.erase(v); if (!a[v].st.empty()) a[v].mn = a[v].st.begin()->first; } if (a[v].st.empty()) { cerr << v << endl; printf( -1 ); exit(0); } } int main() { scanf( %d%d , &n, &m); if (n == 1) { printf( 0 ); exit(0); } for (int i = 1; i < n; i++) { int v, u; scanf( %d%d , &v, &u); g[v].push_back(u); g[u].push_back(v); } for (int i = 0; i < m; i++) { int u, v, c; scanf( %d%d%d , &v, &u, &c); if (!a[v].dp.count(u) || a[v].dp[u] > c) { a[v].st.erase({a[v].dp[u], u}); a[v].dp[u] = c; a[v].st.insert({a[v].dp[u], u}); } } dfs(1, 1); printf( %lld , 0ll + a[1].mn + a[1].add); }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:33:06 03/03/2016
// Design Name: data_memory
// Module Name: G:/ceshi/lab4.2/test_for_datamem.v
// Project Name: lab4.2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: data_memory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_datamem;
// Inputs
reg clock_in;
reg [31:0] address;
reg [31:0] writeData;
reg memWrite;
reg memRead;
// Outputs
wire [31:0] readData;
// Instantiate the Unit Under Test (UUT)
data_memory uut (
.clock_in(clock_in),
.address(address),
.writeData(writeData),
.memWrite(memWrite),
.memRead(memRead),
.readData(readData)
);
always #100 clock_in = ~clock_in;
initial begin
// Initialize Inputs
clock_in = 0;
address = 0;
writeData = 0;
memWrite = 0;
memRead = 0;
// Wait 100 ns for global reset to finish
#185;
memWrite = 1'b1;
address = 32'b00000000000000000000000000001111;
writeData = 32'b11111111111111110000000000000000;
#250;
memRead = 1'b1;
memWrite = 1'b0;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DIODE_SYMBOL_V
`define SKY130_FD_SC_LS__DIODE_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__diode (
//# {{power|Power}}
input DIODE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DIODE_SYMBOL_V
|
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altrea Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//`define I2C_VIDEO
module speaker_i2c_av_config ( // Host Side
clk_i,
rst_i,
// I2C Side
i2c_sclk,
i2c_sdat );
// Host Side
input clk_i;
input rst_i;
// I2C Side
output i2c_sclk;
inout i2c_sdat;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
// Clock Setting
parameter CLK_Freq = 25000000; // 25 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
`ifdef I2C_VIDEO
parameter LUT_SIZE = 50;
`else
parameter LUT_SIZE = 10;
`endif
// Audio Data Index
parameter SET_LIN_L = 0;
parameter SET_LIN_R = 1;
parameter SET_HEAD_L = 2;
parameter SET_HEAD_R = 3;
parameter A_PATH_CTRL = 4;
parameter D_PATH_CTRL = 5;
parameter POWER_ON = 6;
parameter SET_FORMAT = 7;
parameter SAMPLE_CTRL = 8;
parameter SET_ACTIVE = 9;
`ifdef I2C_VIDEO
// Video Data Index
parameter SET_VIDEO = 10;
`endif
///////////////////// I2C Control Clock ////////////////////////
always@(posedge clk_i)
begin
if(rst_i)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+16'h1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
speaker_i2c_controller i2c_controller ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(i2c_sclk), // I2C CLOCK
.I2C_SDAT(i2c_sdat), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(rst_i),
.W_R (1'b0)
);
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK)
begin
if(rst_i)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mSetup_ST)
0: begin
`ifdef I2C_VIDEO
if(LUT_INDEX>=SET_VIDEO)
mI2C_DATA <= {8'h40,LUT_DATA};
else
`endif
mI2C_DATA <= {8'h34,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+6'h1;
mSetup_ST <= 0;
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
// Audio Config Data
SET_LIN_L : LUT_DATA <= 16'h001A;
SET_LIN_R : LUT_DATA <= 16'h021A;
SET_HEAD_L : LUT_DATA <= 16'h047B;
SET_HEAD_R : LUT_DATA <= 16'h067B;
A_PATH_CTRL : LUT_DATA <= 16'h08F8;
D_PATH_CTRL : LUT_DATA <= 16'h0A06;
POWER_ON : LUT_DATA <= 16'h0C00;
SET_FORMAT : LUT_DATA <= 16'h0E42;
SAMPLE_CTRL : LUT_DATA <= 16'h107C;
SET_ACTIVE : LUT_DATA <= 16'h1201;
`ifdef I2C_VIDEO
// Video Config Data
SET_VIDEO+0 : LUT_DATA <= 16'h1500;
SET_VIDEO+1 : LUT_DATA <= 16'h1741;
SET_VIDEO+2 : LUT_DATA <= 16'h3a16;
SET_VIDEO+3 : LUT_DATA <= 16'h5004;
SET_VIDEO+4 : LUT_DATA <= 16'hc305;
SET_VIDEO+5 : LUT_DATA <= 16'hc480;
SET_VIDEO+6 : LUT_DATA <= 16'h0e80;
SET_VIDEO+7 : LUT_DATA <= 16'h5020;
SET_VIDEO+8 : LUT_DATA <= 16'h5218;
SET_VIDEO+9 : LUT_DATA <= 16'h58ed;
SET_VIDEO+10: LUT_DATA <= 16'h77c5;
SET_VIDEO+11: LUT_DATA <= 16'h7c93;
SET_VIDEO+12: LUT_DATA <= 16'h7d00;
SET_VIDEO+13: LUT_DATA <= 16'hd048;
SET_VIDEO+14: LUT_DATA <= 16'hd5a0;
SET_VIDEO+15: LUT_DATA <= 16'hd7ea;
SET_VIDEO+16: LUT_DATA <= 16'he43e;
SET_VIDEO+17: LUT_DATA <= 16'hea0f;
SET_VIDEO+18: LUT_DATA <= 16'h3112;
SET_VIDEO+19: LUT_DATA <= 16'h3281;
SET_VIDEO+20: LUT_DATA <= 16'h3384;
SET_VIDEO+21: LUT_DATA <= 16'h37A0;
SET_VIDEO+22: LUT_DATA <= 16'he580;
SET_VIDEO+23: LUT_DATA <= 16'he603;
SET_VIDEO+24: LUT_DATA <= 16'he785;
SET_VIDEO+25: LUT_DATA <= 16'h5000;
SET_VIDEO+26: LUT_DATA <= 16'h5100;
SET_VIDEO+27: LUT_DATA <= 16'h0050;
SET_VIDEO+28: LUT_DATA <= 16'h1000;
SET_VIDEO+29: LUT_DATA <= 16'h0402;
SET_VIDEO+30: LUT_DATA <= 16'h0b00;
SET_VIDEO+31: LUT_DATA <= 16'h0a20;
SET_VIDEO+32: LUT_DATA <= 16'h1100;
SET_VIDEO+33: LUT_DATA <= 16'h2b00;
SET_VIDEO+34: LUT_DATA <= 16'h2c8c;
SET_VIDEO+35: LUT_DATA <= 16'h2df2;
SET_VIDEO+36: LUT_DATA <= 16'h2eee;
SET_VIDEO+37: LUT_DATA <= 16'h2ff4;
SET_VIDEO+38: LUT_DATA <= 16'h30d2;
SET_VIDEO+39: LUT_DATA <= 16'h0e05;
`endif
default: LUT_DATA <= 16'h0000;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule
|
module buffer_copier(
input wire clk,
input wire vblank,
output reg front_vram_wr_low,
output reg back_vram_rd_low,
output reg copy_in_progress,
input wire [7:0] copy_enable,
inout wire [7:0] front_vram_data,
inout wire [7:0] back_vram_data,
output wire [12:0] front_vram_addr,
output wire [12:0] back_vram_addr
);
reg [12:0] counter;
assign front_vram_data = copy_in_progress ? back_vram_data : 8'bzzzzzzzz;
always @(posedge clk)
begin
if (vblank == 0) begin
back_vram_rd_low <= 1'bz;
front_vram_wr_low <= 1;
copy_in_progress <= 0;
counter <= 0;
end
else if (copy_enable && counter <= 4800) begin
back_vram_rd_low <= 0;
front_vram_wr_low <= 0;
copy_in_progress <= 1;
counter <= counter + 1;
end
else begin
copy_in_progress <= 0;
back_vram_rd_low <= 1'bz;
front_vram_wr_low <= 1;
counter <= 0;
end
end
assign back_vram_addr = copy_in_progress ? counter : 13'bzzzzzzzzzzzzz;
assign front_vram_addr = copy_in_progress ? counter : 13'bzzzzzzzzzzzzz;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLRTN_PP_SYMBOL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int first[maxn]; int n; int main() { int num, i; while (scanf( %d , &n) != EOF) { memset(first, 0, sizeof(first)); for (i = 1; i <= n; i++) { scanf( %d , &num); if (i <= n / 2) { if (num - (i - 1) > 0) first[num - (i - 1)]++; } else { if (num - (n - i) > 0) first[num - (n - i)]++; } } int Max = 0; for (i = 1; i < maxn; i++) if (first[i] > Max) Max = first[i]; printf( %d n , n - Max); } return 0; }
|
module bluetooth_TB;
reg rx=1;
wire avail;
reg clk_in;
wire clk_div;
reg reset=0;
wire [7:0] dout;
reg enable=0;
wire busy;
wire done;
wire tx;
bluetooth bt(.rx(rx),.clk_in(clk_in),.reset(reset),.dout(dout),.avail(avail),.clk_div(clk_div),.enable(enable),.busy(busy),.done(done),.tx(tx));
reg [3:0] bitpos = 0;
reg [3:0] counter = 0;
reg [19:0]count=0;
reg [7:0] data = 8'b0;
always #1 clk_in = ~clk_in;
initial begin
clk_in=0;
reset=0;
end
always @(posedge clk_in)begin
count<=count+1;
if(count<=150000)
data<=8'b10101010;
else
data<=8'b11110000;
end
always @(posedge clk_div)begin
counter <= counter+1;
if (counter >=4)begin
if(bitpos<=7)begin
rx<=data[bitpos];
bitpos<=bitpos+1;
end
else begin
rx<=1;
if (avail)begin
counter<=0;
bitpos<=0;
enable<=1;
end
end
end
else if (counter<3)
rx=1;
if(counter<1)
enable<=0;
else if (counter==3)
rx=0;
end
initial begin: TEST_CASE
$dumpfile("bluetooth_TB.vcd");
$dumpvars(0, bluetooth_TB);
$display("FIN de la simulacion");
# $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DFXTP_PP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; map<pair<long long, long long>, long long> O; map<pair<long long, long long>, long long>::iterator oit; map<long long, long long> X, Y; map<long long, long long>::iterator it; int main() { int n; cin >> n; for (int i = 0; i < n; ++i) { double x, y; cin >> x >> y; O[make_pair(x, y)]++; X[x]++; Y[y]++; } long long cnt = 0; for (it = X.begin(); it != X.end(); ++it) if (it->second > 1) cnt += (it->second - 1) * (it->second) / 2; for (it = Y.begin(); it != Y.end(); ++it) if (it->second > 1) cnt += (it->second - 1) * (it->second) / 2; for (oit = O.begin(); oit != O.end(); ++oit) if (oit->second > 1) cnt -= (oit->second - 1) * (oit->second) / 2; cout << cnt << endl; return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file cx4_pgmrom.v when simulating
// the core, cx4_pgmrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module cx4_pgmrom(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> a; vector<pair<pair<int, int>, int> > b; vector<int> k; vector<int> ans; signed main() { ios_base::sync_with_stdio(0); int n, m; cin >> n; a.resize(n); b.resize(n); ans.resize(n); for (int i = 0; i < n; i++) { cin >> b[i].first.first >> b[i].second; } cin >> m; b.resize(n + m); k.resize(m); for (int i = 0; i < n; i++) { b[i].first.second = i + m; } for (int i = n; i < m + n; i++) { cin >> b[i].first.first >> b[i].second >> k[i - n]; b[i].first.second = i - n; } sort(b.begin(), b.end()); set<pair<int, int> > d; bool poss = true; for (int i = 0; i < n + m; i++) { if (b[i].first.second < m) d.insert(make_pair(b[i].second, b[i].first.second)); else { set<pair<int, int> >::iterator it = d.upper_bound(make_pair(b[i].second - 1, m)); if (it == d.end()) { poss = false; continue; } k[it->second]--; ans[b[i].first.second - m] = it->second + 1; if (k[it->second] == 0) d.erase(it); } } if (poss) { cout << YES << endl; for (int i = 0; i < n; i++) { cout << ans[i] << ; } cout << endl; } else cout << NO << endl; return 0; }
|
// -*- Mode: Verilog -*-
// Filename : cpu.v
// Description : Complete Picoblaze Design
// Author : Philip Tracton
// Created On : Thu May 21 22:33:37 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 21 22:33:37 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
module cpu (/*AUTOARG*/
// Outputs
port_id, out_port, write_strobe, read_strobe, interrupt_ack,
// Inputs
clk, in_port, interrupt, kcpsm6_sleep, cpu_reset
) ;
input clk;
input [7:0] in_port;
output [7:0] port_id;
output [7:0] out_port;
output write_strobe;
output read_strobe;
input interrupt; //See note above
output interrupt_ack;
input kcpsm6_sleep;
input cpu_reset;
/*AUTOWIRE*/
/*AUTOREG*/
//
// Signals for connection of KCPSM6 and Program Memory.
//
wire [11:0] address;
wire [17:0] instruction;
wire [7:0] out_port;
wire [7:0] port_id;
wire bram_enable;
wire k_write_strobe;
wire kcpsm6_reset; //See note above
wire interrupt_ack;
wire read_strobe;
wire write_strobe;
//
// Some additional signals are required if your system also needs to reset KCPSM6.
//
//
// When interrupt is to be used then the recommended circuit included below requires
// the following signal to represent the request made from your system.
//
wire int_request;
kcpsm6 #(
.interrupt_vector (12'h3FF),
.scratch_pad_memory_size(64),
.hwbuild (8'h00))
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
//
// If your design also needs to be able to reset KCPSM6 the arrangement below should be
// used to 'OR' your signal with 'rdl' from the program memory.
//
basic_rom
program_rom ( //Name to match your PSM file
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
assign kcpsm6_reset = cpu_reset;
endmodule // cpu
|
`include "serialClock.v"
module finiteStateMachine(clk, sclkPosEdge, instr, cs, dc, delayEn, parallelData);
input clk, sclkPosEdge;
input[9:0] instr;
output reg cs, dc, delayEn;
output[7:0] parallelData;
wire[1:0] code;
assign code = instr[9:8]; // our makeshift opcodes
assign parallelData = instr[7:0]; // what goes to the shift register
//states: write data, write command, delay
always @( * ) begin
if (code == 2'b00) begin // write data
$display("writing data");
cs = 0;
dc = 1; // data is high
delayEn = 0;
end
if (code == 2'b01) begin // write command
$display("writing command");
cs = 0;
dc = 0; // command is low
delayEn = 0;
end
if (code == 2'b10) begin // delay
$display("beginning delay");
cs = 1;
delayEn = 1;
end
end
endmodule
module testStateMachine;
reg clk;
reg[9:0] instr;
wire cs, dc, delayEn, sclk, sclkPosEdge, sclkNegEdge;
wire[7:0] parallelData;
serialClock #(2) sc(clk, sclk, sclkPosEdge, sclkNegEdge);
finiteStateMachine fsm(clk, sclkPosEdge, instr, cs, dc, delayEn, parallelData);
initial clk = 0;
always #5 clk=!clk;
initial begin
instr = 10'b0010101010;
#600
instr = 10'b0100110011;
#600
instr = 10'b1010110110;
#600
instr = 10'b0010101010;
end
endmodule
|
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_PIPELINE=1 LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=64 LPM_WIDTHN=64 clken clock denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:07:21:01:49:21:SJ cbx_stratixii 2016:07:21:01:48:16:SJ cbx_util_mgl 2016:07:21:01:48:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mg32n
(
clken,
clock,
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input clken;
input clock;
input [63:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [63:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [63:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.clken(clken),
.clock(clock),
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_pipeline = 1,
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 64,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mg32n
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int tc; cin >> tc; while (tc--) { long long l, r; cin >> l >> r; long long i = 1; while ((l | i) <= r) { l |= i; i <<= 1; } cout << l << n ; } }
|
#include <bits/stdc++.h> using namespace std; string a, b; bool func(string s, long n) { if (s.size() % n) return false; for (long i = 0; i < s.size(); i++) if (s[i] != a[i % n]) return 0; return 1; } int main() { cin >> a >> b; long ans = 0, i = 1; string p = a, q = b; long minx = min(a.size(), b.size()); while (i <= minx) { ans += (func(p, i) && func(q, i)); i++; } cout << ans; }
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) FILE *in = stdin, *out = stdout; using namespace std; #pragma comment(linker, /stack:36777216 ) int n; char a[300005]; int D[300005]; void input() { fscanf(in, %d , &n); fscanf(in, %s , &a[1]); } bool isSame(int x) { if (x & 1) return false; for (int i = (1); i <= (x / 2); i++) { if (a[i] != a[i + x / 2]) return false; } return true; } void pro() { int ans = n; for (int i = (1); i <= (n); i++) { if (isSame(i)) ans = min(ans, i / 2 + 1 + (n - i)); } fprintf(out, %d , ans); } int main() { input(); pro(); return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// RxfifoBI.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
//`include "timescale.v"
`include "wishBoneBus_h.v"
module RxfifoBI (
address,
writeEn,
strobe_i,
busClk,
usbClk,
rstSyncToBusClk,
fifoSelect,
fifoDataIn,
busDataIn,
busDataOut,
fifoREn,
forceEmptySyncToUsbClk,
forceEmptySyncToBusClk,
numElementsInFifo
);
input [2:0] address;
input writeEn;
input strobe_i;
input busClk;
input usbClk;
input rstSyncToBusClk;
input [7:0] fifoDataIn;
input [7:0] busDataIn;
output [7:0] busDataOut;
output fifoREn;
output forceEmptySyncToUsbClk;
output forceEmptySyncToBusClk;
input [15:0] numElementsInFifo;
input fifoSelect;
wire [2:0] address;
wire writeEn;
wire strobe_i;
wire busClk;
wire usbClk;
wire rstSyncToBusClk;
wire [7:0] fifoDataIn;
wire [7:0] busDataIn;
reg [7:0] busDataOut;
reg fifoREn;
wire forceEmptySyncToUsbClk;
wire forceEmptySyncToBusClk;
wire [15:0] numElementsInFifo;
wire fifoSelect;
reg forceEmptyReg;
reg forceEmpty;
reg forceEmptyToggle;
reg [2:0] forceEmptyToggleSyncToUsbClk;
//sync write
always @(posedge busClk)
begin
if (writeEn == 1'b1 && fifoSelect == 1'b1 &&
address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1)
forceEmpty <= 1'b1;
else
forceEmpty <= 1'b0;
end
//detect rising edge of 'forceEmpty', and generate toggle signal
always @(posedge busClk) begin
if (rstSyncToBusClk == 1'b1) begin
forceEmptyReg <= 1'b0;
forceEmptyToggle <= 1'b0;
end
else begin
if (forceEmpty == 1'b1)
forceEmptyReg <= 1'b1;
else
forceEmptyReg <= 1'b0;
if (forceEmpty == 1'b1 && forceEmptyReg == 1'b0)
forceEmptyToggle <= ~forceEmptyToggle;
end
end
assign forceEmptySyncToBusClk = (forceEmpty == 1'b1 && forceEmptyReg == 1'b0) ? 1'b1 : 1'b0;
// double sync across clock domains to generate 'forceEmptySyncToUsbClk'
always @(posedge usbClk) begin
forceEmptyToggleSyncToUsbClk <= {forceEmptyToggleSyncToUsbClk[1:0], forceEmptyToggle};
end
assign forceEmptySyncToUsbClk = forceEmptyToggleSyncToUsbClk[2] ^ forceEmptyToggleSyncToUsbClk[1];
// async read mux
always @(address or fifoDataIn or numElementsInFifo)
begin
case (address)
`FIFO_DATA_REG : busDataOut <= fifoDataIn;
`FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8];
`FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0];
default: busDataOut <= 8'h00;
endcase
end
//generate fifo read strobe
always @(address or writeEn or strobe_i or fifoSelect) begin
if (address == `FIFO_DATA_REG && writeEn == 1'b0 &&
strobe_i == 1'b1 && fifoSelect == 1'b1)
fifoREn <= 1'b1;
else
fifoREn <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void rc(char &a) { a = 0; register int x = getchar_unlocked(); while (x < a || x > z ) { if (x == n ) { a = 0 ; return; } x = getchar_unlocked(); } a = x; } const int maxn = 100100; int key; int main() { ios_base::sync_with_stdio(0); string ans = ; char cur; while (true) { rc(cur); if (cur == 0 ) break; if (cur == a ) { if (key == 0) ans += a ; else if (key == 1) { ans += a ; key = 2; } else { ans += a ; } } else { if (key == 1) ans += (cur - 1); else if (key == 0) { ans += (cur - 1); key = 1; } else { ans += cur; } } } if (key == 0) { ans = ans.substr(0, ans.size() - 1) + z ; cout << ans << n ; return 0; } cout << ans << n ; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module logicblock_counter(clock, resetn, i_start, i_size,
o_dataout, o_dataout_valid, i_dataout_stall, i_counter_reset);
parameter DATA_WIDTH = 32;
input clock, resetn;
input i_start;
input [DATA_WIDTH-1:0] i_size;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_dataout_stall;
input i_counter_reset;
reg [DATA_WIDTH-1:0] counter;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
counter <= 32'h00000000;
end
else
begin
if (i_counter_reset)
begin
counter <= {DATA_WIDTH{1'b0}};
end
else if (i_start && ~i_dataout_stall && counter < i_size)
begin
counter <= counter + 1;
end
end
end
assign o_dataout = counter;
assign o_dataout_valid = i_start && !i_counter_reset && (counter < i_size);
endmodule
|
module adv3224 (
// avalon-bus
input clk,
input reset,
input avs_slave_write,
input avs_slave_read,
input [7:0]avs_slave_writedata,
output [7:0]avs_slave_readdata,
input [2:0]avs_slave_address,
// adv3224
output cps_reset_n,
output cps_ce_n,
output cps_update_n,
output cps_clk,
output cps_datain
);
//
// parameters
//
parameter divider = 5;
//
// regs / wires
//
reg [8:0]clk_counter;
reg div_clk;
reg clk_en;
reg [39:0]shift_buffer;
reg shift_busy;
reg [5:0]shift_counter;
reg [4:0]outputs[0:7];
//
// ip
//
assign cps_reset_n = !reset;
assign cps_ce_n = 0;
assign avs_slave_readdata = shift_busy;
assign cps_clk = clk_en ? div_clk : 1;
assign cps_update_n = (!clk_en && shift_busy) ? !div_clk : 1;
assign cps_datain = shift_buffer[39];
always @(posedge clk or posedge reset)
begin
if(reset)
begin
clk_counter <= 1;
div_clk <= 1;
clk_en <= 0;
shift_busy <= 0;
shift_counter <= 0;
outputs[0] <= 5'b00000;
outputs[1] <= 5'b00000;
outputs[2] <= 5'b00000;
outputs[3] <= 5'b00000;
outputs[4] <= 5'b00000;
outputs[5] <= 5'b00000;
outputs[6] <= 5'b00000;
outputs[7] <= 5'b00000;
end
else
begin // posedge clk
if(shift_busy)
begin
if(clk_counter == (divider/2))
begin
clk_counter <= 1;
div_clk <= !div_clk;
if(!div_clk)
begin
if(!clk_en)
begin
shift_busy <= 0;
end
else
begin
if(shift_counter == 39)
begin
clk_en <= 0;
end
else
begin
shift_counter <= shift_counter + 1;
shift_buffer <= shift_buffer << 1;
end
end
end
end
else
begin
clk_counter = clk_counter + 1;
end
end
else
begin
clk_counter <= 1;
shift_counter <= 0;
div_clk <= 1;
if(avs_slave_write)
begin
if(avs_slave_writedata[7])
begin
shift_buffer <= {outputs[7], outputs[6], outputs[5], outputs[4], outputs[3], outputs[2], outputs[1], outputs[0]};
shift_busy <= 1;
clk_en <= 1;
end
else
begin
outputs[avs_slave_address] <= {!avs_slave_writedata[4], avs_slave_writedata[3:0]};
end
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S6S_TB_V
`define SKY130_FD_SC_MS__DLYMETAL6S6S_TB_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlymetal6s6s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__dlymetal6s6s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S6S_TB_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: COCO3GEN.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module COCO3GEN (
address,
clock,
q);
input [10:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "2048"
// Retrieval info: PRIVATE: MIFfilename STRING "coco3gen.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "coco3gen.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COCO3GEN_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; struct node { int left, right; int time[60]; node(int left = 0, int right = 0) : left(left), right(right) {} } arb[4 * 100000 + 5]; inline void unite(node &a, node b, node &c) { for (int i = 0; i < 60; i++) a.time[i] = b.time[i] + c.time[(i + b.time[i]) % 60]; } int a[100000 + 5]; void build(int left, int right, int pos) { arb[pos].left = left, arb[pos].right = right; if (left == right) { for (int i = 0; i < 60; i++) if (i % a[left]) arb[pos].time[i] = 1; else arb[pos].time[i] = 2; return; } int mijl = (left + right) >> 1; build(left, mijl, pos << 1); build(mijl + 1, right, (pos << 1) + 1); unite(arb[pos], arb[pos << 1], arb[(pos << 1) + 1]); } void update(int up_pos, int val, int pos) { if (arb[pos].left == arb[pos].right) { for (int i = 0; i < 60; i++) if (i % val) arb[pos].time[i] = 1; else arb[pos].time[i] = 2; return; } int mijl = (arb[pos].left + arb[pos].right) >> 1; if (up_pos <= mijl) update(up_pos, val, pos << 1); else update(up_pos, val, (pos << 1) + 1); unite(arb[pos], arb[pos << 1], arb[(pos << 1) + 1]); } int ans; void query(int x, int y, int pos) { if (arb[pos].left == x && arb[pos].right == y) { ans += arb[pos].time[ans % 60]; return; } int mijl = (arb[pos].left + arb[pos].right) >> 1; if (y <= mijl) query(x, y, pos << 1); else if (x > mijl) query(x, y, (pos << 1) + 1); else { query(x, mijl, pos << 1); query(mijl + 1, y, (pos << 1) + 1); } } int main() { ios_base::sync_with_stdio(false); int n = 0; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; build(1, n, 1); int q = 0; cin >> q; char type; int x, y; while (q--) { cin >> type >> x >> y; if (type == A ) { y--; ans = 0; query(x, y, 1); cout << ans << n ; } else update(x, y, 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, i, j, k, l, m, t; int a[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int main() { cin >> m >> t; a[m] -= 7 - t + 1; if (a[m] % 7 == 0) { cout << a[m] / 7 + 1; } else { cout << a[m] / 7 + 2; } }
|
/*
Usage: 3 slices, 13 regs, 8 LUTs, 4 LUTRAMs, for 16-deep 8-bit FIFO
*/
module Fifo #(
parameter WIDTH = 8, ///< Width of data word
parameter LOG2_DEPTH = 4 ///< log2(depth of FIFO). Must be an integer
)
(
// Inputs
input clk, ///< System clock
input rst, ///< Reset FIFO pointer
input write, ///< Write strobe (1 clk)
input read, ///< Read strobe (1 clk)
input [WIDTH-1:0] dataIn, ///< Data to write
// Outputs
output wire [WIDTH-1:0] dataOut, ///< Data from FIFO
output reg dataPresent, ///< Data is present in FIFO
output wire halfFull, ///< FIFO is half full
output wire full ///< FIFO is full
);
reg [WIDTH-1:0] memory[2**LOG2_DEPTH-1:0];
reg [LOG2_DEPTH-1:0] pointer;
wire zero;
integer i;
// Zero out internal memory
initial begin
pointer = 'd0;
dataPresent = 1'b0;
for (i=0; i<(2**LOG2_DEPTH); i=i+1) begin
memory[i] = 'd0;
end
end
// Shift register for FIFO
always @(posedge clk) begin
if (write) begin
memory[0] <= dataIn;
for (i=1; i<(2**LOG2_DEPTH); i=i+1) begin
memory[i] <= memory[i-1];
end
end
end
assign dataOut = memory[pointer];
// Pointer for FIFO
always @(posedge clk) begin
if (rst) begin
pointer <= 'd0;
dataPresent <= 1'b0;
end
else begin
dataPresent <= write
| (dataPresent & ~zero)
| (dataPresent & zero & ~read);
case ({read, write})
2'b00 : pointer <= pointer;
2'b01 : pointer <= (!full && dataPresent) ? pointer + 2'd1 : pointer;
2'b10 : pointer <= (!zero) ? pointer - 2'd1 : pointer;
2'b11 : pointer <= pointer;
endcase
end
end
assign zero = ~|pointer;
assign halfFull = pointer[LOG2_DEPTH-1];
assign full = &pointer;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long dp[2][300000]; long long dfs(int previous,bool previousMax,int N, vector<vector<int> > & adj, vector<pair<long long,long long> > &vals) { if(dp[previousMax][N]!=-1) return dp[previousMax][N]; long long res1 = 0; long long res2 = 0; if(previous != -1) { res1 = abs((previousMax?vals[previous].second:vals[previous].first)-vals[N].first); res2 = abs((previousMax?vals[previous].second:vals[previous].first)-vals[N].second); } for(auto &z:adj[N]) { if(z != previous) { res1 += dfs(N,false,z,adj,vals); res2 += dfs(N,true,z,adj,vals); } } dp[previousMax][N] = max(res1,res2); return max(res1,res2); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int T; cin>>T; while(T--) { int N; cin>>N; vector<pair<long long int,long long int> > vals(N); for(int c=0;c<N;c++) cin>>vals[c].first>>vals[c].second; vector<vector<int> > adj(N); for(int c=0;c<2;c++) for(int c2=0;c2<N;c2++) dp[c][c2] = -1; for(int c=1;c<N;c++) { int f,t; cin>>f>>t; f--; t--; adj[f].push_back(t); adj[t].push_back(f); } cout<<max(dfs(-1,false,0,adj,vals),dfs(-1,false,0,adj,vals))<< n ; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 09:32:00 01/19/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #1 Demo
// Module Name: TF_EECS301_Lab1_TopLevel
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Test Bench Simulation for EECS301_Lab1_TopLevel
//
//
// Dependencies: EECS301_Lab1_TopLevel.v
//
//////////////////////////////////////////////////////////////////////////////////
module TF_EECS301_Lab1_TopLevel();
//
// Signal Declarations
//
// Signals must be declared before they are used so either
// declare everything at the top of the file or
// group the declarations with the code where they are first used.
//
reg CLOCK_50;
reg [3:0] KEY;
wire [9:0] LEDR;
wire [6:0] HEX0;
wire [6:0] HEX1;
wire [6:0] HEX2;
wire [6:0] HEX3;
wire [6:0] HEX4;
wire [6:0] HEX5;
//
// System Clock Emulation
//
// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal.
// The CLK_HALF_PER calculation converts Hz into ns for the clock period then
// divides by 2 so the signal is toggled twice per cycle.
//
localparam CLK_RATE_HZ = 50000000; // 50 MHz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * .0) / 2.0; // ns
initial
begin
CLOCK_50 = 1'b0;
forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
end
//
// Unit Under Test: EECS301_Lab1_TopLevel
//
// This is the instantiation of the module being tested.
// Input signals
// CLOCK_50 1-bit 50MHz Clock
// KEY 4-bit Push Button Inputs (Active-Low)
// Output signals
// LEDR 10-bit Status LED Controls
// HEX0 7-bit Seven-Segment LED Controls (Active-Low)
// HEX1 7-bit Seven-Segment LED Controls (Active-Low)
// HEX2 7-bit Seven-Segment LED Controls (Active-Low)
// HEX3 7-bit Seven-Segment LED Controls (Active-Low)
// HEX4 7-bit Seven-Segment LED Controls (Active-Low)
// HEX5 7-bit Seven-Segment LED Controls (Active-Low)
EECS301_Lab1_TopLevel uut
(
// Clock Signals
.CLOCK_50( CLOCK_50 ),
// LED Signals
.LEDR( LEDR ),
// HEX LED Display Signals (Active-Low)
.HEX0( HEX0 ), // HEX LED Disp 0
.HEX1( HEX1 ), // HEX LED Disp 1
.HEX2( HEX2 ), // HEX LED Disp 2
.HEX3( HEX3 ), // HEX LED Disp 3
.HEX4( HEX4 ), // HEX LED Disp 4
.HEX5( HEX5 ), // HEX LED Disp 5
// Key Button Signals (Active-Low)
.KEY( KEY )
);
//
// Expected Key Value Computation
//
wire [3:0] exp_key_value;
wire [3:0] exp_key0_value = ~KEY[0] ? 4'h1 : 4'h0; // KEY[0] = 1
wire [3:0] exp_key1_value = ~KEY[1] ? 4'h2 : 4'h0; // KEY[1] = 2
wire [3:0] exp_key2_value = ~KEY[2] ? 4'h3 : 4'h0; // KEY[3] = 3
wire [3:0] exp_key3_value = ~KEY[3] ? 4'h4 : 4'h0; // KEY[4] = 4
assign exp_key_value = exp_key3_value + exp_key2_value + exp_key1_value + exp_key0_value;
//
// Expected LED Output Computation
//
// The expected LED output value is determined from the computed
// key value.
reg [9:0] exp_ledr_value;
always @*
begin
case (exp_key_value)
4'h0 : exp_ledr_value <= 10'b0000000000;
4'h1 : exp_ledr_value <= 10'b0000000001;
4'h2 : exp_ledr_value <= 10'b0000000011;
4'h3 : exp_ledr_value <= 10'b0000000111;
4'h4 : exp_ledr_value <= 10'b0000001111;
4'h5 : exp_ledr_value <= 10'b0000011111;
4'h6 : exp_ledr_value <= 10'b0000111111;
4'h7 : exp_ledr_value <= 10'b0001111111;
4'h8 : exp_ledr_value <= 10'b0011111111;
4'h9 : exp_ledr_value <= 10'b0111111111;
4'hA : exp_ledr_value <= 10'b1111111111;
default : exp_ledr_value <= 10'bxxxxxxxxxx; // Invalid Key Value
endcase
end
//
// Test Stimulus
//
// This process provides the main testing routine for the simulation.
// Note the use of blocking assignments for sequential process execution.
//
integer i;
reg [3:0] test_key_reg;
reg test_pass_fail;
initial
begin
// Initialize Signals
KEY = 4'hF; // The 4'hF value sets each of the four KEY bits high (off)
test_pass_fail = 1'b1;
test_key_reg = 4'h0;
// Delay for system to stabilize (in lieu of a Reset)
#1000; // Delay 1000 ns
/////////////////////////////////////////////////////
//
// Start Testing
//
//
// Simulate single button presses
//
// Each of the four Keys are individually pressed for 1000ns.
// The LEDR output is verified 100ns after the key press starts.
// There is 1000ns between Key Press tests.
//
// The $display function prints messages to the terminal message log
$display("Single Button Press Tests");
// Press Key 1
KEY[0] = 1'b0; // Press Key (KEY is indexed so only bit 0 is changed)
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0; // This uses the ternary if-then-else operation
if (test_pass_fail)
$display(" KEY[0] Press Passed. Key Value = %d", exp_key_value);
else
$display(" KEY[0] Press FAILED!!! Expected [%010b] != Actual [%010b]", exp_ledr_value, LEDR);
#900;
KEY[0] = 1'b1; // Release Key
#1000;
// Press Key 2
KEY[1] = 1'b0; // Press Key
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0;
if (test_pass_fail)
$display(" KEY[1] Press Passed. Key Value = %d", exp_key_value);
else
$display(" KEY[1] Press FAILED!!! Expected [%010b] != Actual [%010b]", exp_ledr_value, LEDR);
#900;
KEY[1] = 1'b1; // Release Key
#1000;
// Press Key 3
KEY[2] = 1'b0; // Press Key
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0;
if (test_pass_fail)
$display(" KEY[2] Press Passed. Key Value = %d", exp_key_value);
else
$display(" KEY[2] Press FAILED!!! Expected [%010b] != Actual [%010b]", exp_ledr_value, LEDR);
#900;
KEY[2] = 1'b1; // Release Key
#1000;
// Press Key 4
KEY[3] = 1'b0; // Press Key
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0;
if (test_pass_fail)
$display(" KEY[3] Press Passed. Key Value = %d", exp_key_value);
else
$display(" KEY[3] Press FAILED!!! Expected [%010b] != Actual [%010b]", exp_ledr_value, LEDR);
#900;
KEY[3] = 1'b1; // Release Key
#2000;
//
// Run thorough all KEY input combinations
//
// The same test routine is used in a loop to test every possible key
// press combination for full coverage verification.
$display("Full Coverage Key Press Tests");
test_key_reg = 4'h0;
for (i=0; i < 16; i=i+1)
begin
// Assign the test pattern to the KEY input
KEY = ~test_key_reg; // KEY is active-low so invert the test pattern
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0;
if (test_pass_fail)
$display(" KEY Pattern [%04b] Press Passed. Key Value = %d", test_key_reg, exp_key_value);
else
$display(" KEY Pattern [%04b] Press FAILED!!! Expected [%010b] != Actual [%010b]", test_key_reg, exp_ledr_value, LEDR);
#900;
KEY = 4'hF; // Release All Keys
#1000;
// Next Test Key Pattern
test_key_reg = test_key_reg + 1'b1;
end
KEY = 4'hF; // Release All Keys
//
// Add another Key Test Pattern here...
KEY = 4'h5; // Press Key (KEY is indexed so only bit 0 is changed)
#100;
test_pass_fail = exp_ledr_value == LEDR ? 1'b1 : 1'b0; // This uses the ternary if-then-else operation
if (test_pass_fail)
$display(" KEY[0] and KEY[2] Press Passed. Key Value = %d", exp_key_value);
else
$display(" KEY[0] and KEY[2] Press FAILED!!! Expected [%010b] != Actual [%010b]", exp_ledr_value, LEDR);
#900;
KEY = 4'hF; // Release Key
//
#2000;
$finish;
end
endmodule
|
`timescale 1 ns / 1 ps
module BoardInit_AXI_v1_0 #
(
// Users to add parameters here
parameter integer im_bits_width = 9,
parameter integer color_width = 8,
parameter integer window_width = 8,
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S00_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S00_AXI_ADDR_WIDTH = 7
)
(
// Users to add ports here
input wire rst_n,
input wire pll_locked,
output wire rst_all_n,
output wire th_mode,
output wire[color_width - 1 : 0] th1,
output wire[color_width - 1 : 0] th2,
output wire[23 : 0] ct_scale,
output wire signed[color_width : 0] lm_gain,
output wire[3 : 0] rank,
output wire ed_mode,
output wire[window_width * window_width - 1 : 0] ed_template,
output wire[window_width * window_width - 1 : 0] mt_template,
output wire[im_bits_width - 1 : 0] crop_top,crop_bottom,crop_left,crop_right,
output wire[1 : 0] mirror_mode,
output wire signed[im_bits_width : 0] offset_x, offset_y,
output wire [23 : 0] scale_x, scale_y,
output wire signed[24 : 0] sh_u, sh_v,
output wire[8 : 0] angle,
output wire[31 : 0] sels,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
BoardInit_AXI_v1_0_S00_AXI # (
.im_bits_width(im_bits_width),
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) BoardInit_AXI_v1_0_S00_AXI_inst (
.rst_n(rst_n),
.pll_locked(pll_locked),
.rst_all_n(rst_all_n),
.th_mode(th_mode),
.th1(th1),
.th2(th2),
.lm_gain(lm_gain),
.ct_scale(ct_scale),
.rank(rank),
.ed_mode(ed_mode),
.ed_template(ed_template),
.mt_template(mt_template),
.crop_top(crop_top),
.crop_bottom(crop_bottom),
.crop_left(crop_left),
.crop_right(crop_right),
.mirror_mode(mirror_mode),
.offset_x(offset_x),
.offset_y(offset_y),
.scale_x(scale_x),
.scale_y(scale_y),
.sh_u(sh_u),
.sh_v(sh_v),
.angle(angle),
.sels(sels),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const int dx[] = {1, 0, -1, 0, -1, -1, 1, 1}; const int dy[] = {0, 1, 0, -1, -1, 1, -1, 1}; const int OO = INT_MAX; long long tolong(string s) { stringstream ss; ss << s; long long n; ss >> n; return n; } string toString(long long s) { stringstream ss; ss << s; string n; ss >> n; return n; } int main() { string x; cin >> x; long long n = tolong(x); if (x == toString(n)) { if (n >= -128 && n <= 127) { cout << byte ; } else if (n >= -32768 && n <= 32767) { cout << short ; } else if (n >= -2147483648 && n <= 2147483647) { cout << int ; } else { cout << long ; } } else { cout << BigInteger ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y; cin >> n >> x >> y; if ((x == n / 2 || x == n / 2 + 1) && (y == n / 2 || y == n / 2 + 1)) cout << NO << endl; else cout << YES << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_SYMBOL_V
`define SKY130_FD_SC_HD__PROBEC_P_SYMBOL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__probec_p (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply0 VGND;
supply0 VNB ;
supply1 VPB ;
supply1 VPWR;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_2_V
`define SKY130_FD_SC_LS__BUF_2_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__buf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_2_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; map<string, long long> mp; const long long N = 8; long long a[N][N]; long long ans1 = (long long)1e18 + 5, ans2 = 0; vector<long long> vv(3); vector<long long> ini = {0, 1, 2, 3, 4, 5, 6}; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; mp[ Anka ] = 0, mp[ Chapay ] = 1, mp[ Cleo ] = 2, mp[ Troll ] = 3, mp[ Dracul ] = 4, mp[ Snowy ] = 5, mp[ Hexadecimal ] = 6; cin >> n; string x, cc1, y; for (long long i = 0; i < n; i++) { cin >> x >> cc1 >> y; a[mp[x]][mp[y]] = 1; } cin >> vv[0] >> vv[1] >> vv[2]; do { for (long long i = 1; i < 5; i++) { for (long long j = i + 1; j < 6; j++) { vector<vector<long long> > aa(3); for (long long k = 0; k < i; k++) aa[0].push_back(ini[k]); for (long long k = i; k < j; k++) aa[1].push_back(ini[k]); for (long long k = j; k < 7; k++) aa[2].push_back(ini[k]); vector<vector<long long> > cur1 = aa; long long lik = 0; for (long long ii = 0; ii < 3; ii++) { for (long long jj = 0; jj < (long long)cur1[ii].size(); jj++) { for (long long k = jj + 1; k < (long long)cur1[ii].size(); k++) { if (a[cur1[ii][jj]][cur1[ii][k]]) { lik++; } if (a[cur1[ii][k]][cur1[ii][jj]]) lik++; } } } vector<long long> cur = {0, 1, 2}; vector<long long> arr(3, 0); do { arr[0] = (vv[cur[0]] / (long long)aa[0].size()); arr[1] = (vv[cur[1]] / (long long)aa[1].size()); arr[2] = (vv[cur[2]] / (long long)aa[2].size()); long long ans = 0; for (long long ii = 0; ii < 3; ii++) { for (long long jj = ii + 1; jj < 3; jj++) { ans = max(ans, abs(arr[ii] - arr[jj])); } } if (ans <= ans1) { if (ans == ans1) { if (lik > ans2) { ans2 = lik; } } else { ans1 = ans; ans2 = lik; } } } while (next_permutation((cur).begin(), (cur).end())); } } } while (next_permutation((ini).begin(), (ini).end())); cout << ans1 << << ans2 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; for (int k = 0; k < n - 1; k++) { if (s[k] > s[k + 1]) { cout << YES << endl; cout << k + 1 << << k + 2; return 0; } } cout << NO ; return 0; }
|
#include <bits/stdc++.h> #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; inline int read() { int f = 1, x = 0; char ch; do { ch = getchar(); if (ch == - ) f = -1LL; } while (ch < 0 || ch > 9 ); do { x = x * 10 + ch - 0 ; ch = getchar(); } while (ch >= 0 && ch <= 9 ); return f * x; } template <class T> inline void chmax(T &a, T b) { if (a < b) a = b; } template <class T> inline void chmin(T &a, T b) { if (a > b) a = b; } inline void swap(int &a, int &b) { int c = a; a = b; b = c; } using namespace std; const int N = 4e5 + 10; set<int> seg[N << 2]; int mx[N << 2], mn[N << 2]; struct node { int x1, y1, x2, y2; } a[N]; inline void show(node a) { printf( %d %d %d %d n , a.x1, a.y1, a.x2, a.y2); } vector<int> ins[N], era[N]; int n, px[N << 1], py[N << 1], totx, toty, lenx, leny, ok[N]; inline void upd(int cur) { int mxp; if (seg[cur].size()) { mxp = *(--seg[cur].end()); } else { mxp = -1; } int mxt = max(mx[cur << 1], mx[cur << 1 | 1]); int mnt = min(mn[cur << 1], mn[cur << 1 | 1]); if (mxp > mxt) { if (ok[mxp] || mxp < mnt) { mx[cur] = -1; } else { mx[cur] = mxp; } } else { mx[cur] = mxt; } mn[cur] = max(mxp, mnt); } inline void cover(int cur, int L, int R, int l, int r, int id, int fl) { if (l > r) return; if (l <= L && r >= R) { if (fl == 1) { seg[cur].insert(id); } else if (fl == -1) { seg[cur].erase(id); } upd(cur); return; } int mid = (L + R) >> 1; if (l <= mid) cover(cur << 1, L, mid, l, r, id, fl); if (r > mid) cover(cur << 1 | 1, mid + 1, R, l, r, id, fl); upd(cur); } inline void norx(int &x) { x = (int)(lower_bound(px + 1, px + lenx + 1, x) - px); } inline void nory(int &x) { x = (int)(lower_bound(py + 1, py + leny + 1, x) - py); } int main() { memset(mx, -1, sizeof(mx)); n = read(); for (int i = (1); i <= (n); ++i) a[i].x1 = read(), a[i].y1 = read(), a[i].x2 = read(), a[i].y2 = read(); for (int i = (1); i <= (n); ++i) { px[++totx] = a[i].x1; px[++totx] = a[i].x2; py[++toty] = a[i].y1; py[++toty] = a[i].y2; } sort(px + 1, px + totx + 1); sort(py + 1, py + toty + 1); lenx = (int)(unique(px + 1, px + totx + 1) - px - 1); leny = (int)(unique(py + 1, py + toty + 1) - py - 1); for (int i = (1); i <= (n); ++i) { norx(a[i].x1); norx(a[i].x2); nory(a[i].y1); nory(a[i].y2); } for (int i = (1); i <= (n); ++i) { ins[a[i].x1].push_back(i); era[a[i].x2].push_back(i); } for (int t = (1); t <= (lenx); ++t) { for (auto cur : ins[t]) { cover(1, 1, leny, a[cur].y1, a[cur].y2 - 1, cur, 1); } for (auto cur : era[t]) { cover(1, 1, leny, a[cur].y1, a[cur].y2 - 1, cur, -1); } while (~mx[1]) { ok[mx[1]] = 1; cover(1, 1, leny, a[mx[1]].y1, a[mx[1]].y2 - 1, mx[1], 0); } } int ans = 1; for (int i = (1); i <= (n); ++i) if (ok[i]) ++ans; printf( %d n , ans); return 0; }
|
`timescale 1ns / 1ps
/*
-- Module Name: DES Sbox 4
-- Description: Sbox 4 del algoritmo DES
-- Dependencies: -- none
-- Parameters: -- none
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 05 de Junio 2015
*/
module des_sbox4
(
// -- inputs --------------------------------------------------------- >>>>>
input wire [0:5] right_xor_key_segment_din,
// -- outputs -------------------------------------------------------- >>>>>
output reg [0:3] sbox_dout
);
always @(*)
case ({right_xor_key_segment_din[0], right_xor_key_segment_din[5]})
2'b00:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd7;
4'd1: sbox_dout = 4'd13;
4'd2: sbox_dout = 4'd14;
4'd3: sbox_dout = 4'd3;
4'd4: sbox_dout = 4'd0;
4'd5: sbox_dout = 4'd6;
4'd6: sbox_dout = 4'd9;
4'd7: sbox_dout = 4'd10;
4'd8: sbox_dout = 4'd1;
4'd9: sbox_dout = 4'd2;
4'd10: sbox_dout = 4'd8;
4'd11: sbox_dout = 4'd5;
4'd12: sbox_dout = 4'd11;
4'd13: sbox_dout = 4'd12;
4'd14: sbox_dout = 4'd4;
4'd15: sbox_dout = 4'd15;
endcase
2'b01:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd13;
4'd1: sbox_dout = 4'd8;
4'd2: sbox_dout = 4'd11;
4'd3: sbox_dout = 4'd5;
4'd4: sbox_dout = 4'd6;
4'd5: sbox_dout = 4'd15;
4'd6: sbox_dout = 4'd0;
4'd7: sbox_dout = 4'd3;
4'd8: sbox_dout = 4'd4;
4'd9: sbox_dout = 4'd7;
4'd10: sbox_dout = 4'd2;
4'd11: sbox_dout = 4'd12;
4'd12: sbox_dout = 4'd1;
4'd13: sbox_dout = 4'd10;
4'd14: sbox_dout = 4'd14;
4'd15: sbox_dout = 4'd9;
endcase
2'b10:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd10;
4'd1: sbox_dout = 4'd6;
4'd2: sbox_dout = 4'd9;
4'd3: sbox_dout = 4'd0;
4'd4: sbox_dout = 4'd12;
4'd5: sbox_dout = 4'd11;
4'd6: sbox_dout = 4'd7;
4'd7: sbox_dout = 4'd13;
4'd8: sbox_dout = 4'd15;
4'd9: sbox_dout = 4'd1;
4'd10: sbox_dout = 4'd3;
4'd11: sbox_dout = 4'd14;
4'd12: sbox_dout = 4'd5;
4'd13: sbox_dout = 4'd2;
4'd14: sbox_dout = 4'd8;
4'd15: sbox_dout = 4'd4;
endcase
2'b11:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd3;
4'd1: sbox_dout = 4'd15;
4'd2: sbox_dout = 4'd0;
4'd3: sbox_dout = 4'd6;
4'd4: sbox_dout = 4'd10;
4'd5: sbox_dout = 4'd1;
4'd6: sbox_dout = 4'd13;
4'd7: sbox_dout = 4'd8;
4'd8: sbox_dout = 4'd9;
4'd9: sbox_dout = 4'd4;
4'd10: sbox_dout = 4'd5;
4'd11: sbox_dout = 4'd11;
4'd12: sbox_dout = 4'd12;
4'd13: sbox_dout = 4'd7;
4'd14: sbox_dout = 4'd2;
4'd15: sbox_dout = 4'd14;
endcase
endcase // right_xor_key_segment_din[0], right_xor_key_segment_din[5]
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
des_sbox4 sbox4
(
// -- inputs ------------------------------------------------- >>>>>
.right_xor_key_segment_din (right_xor_key_segment),
// -- outputs ------------------------------------------------ >>>>>
sbox_dout (sbox_dout)
);
*/
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 50; const int mod = 1e9 + 7; const int inf = 0x3f3f3f3f; long long n, k; long long a[maxn]; int vis[maxn]; long long ans = 0; bool Overflow(long long x, long long y) { if (x > LLONG_MAX / y) return false; else return true; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); memset(vis, 0, sizeof(vis)); memset(a, 0, sizeof(a)); cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; } vis[n + 1] = -1; for (int i = n; i >= 1; i--) { if (a[i] > 1) vis[i] = i; else vis[i] = vis[i + 1]; } long long p = 1; long long s = 0; for (int i = 1; i <= n; i++) { int j = i; p = a[i]; s = a[i]; if (p == s * k) ans++; while (1) { int z = vis[j + 1]; if (z == -1) z = n + 1; int ones = z - j - 1; if (p % k == 0 && p / k - s >= 1 && p / k - s <= ones) { ans++; } if (z == n + 1) break; if (Overflow(p, a[z])) { p = p * a[z]; j = z; s = s + a[z] + ones; if (p == s * k) ans++; } else break; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 505, mod = 1e9 + 7; long long c[N][N], s[N][N], p[N], inv[N]; long long l, r; long long k, ans; long long add(long long a, long long b) { return a + b >= mod ? a + b - mod : a + b; } long long dec(long long a, long long b) { return a - b < 0 ? a - b + mod : a - b; } long long ksm(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = 1ll * ans * a % mod; a = 1ll * a * a % mod; b >>= 1; } return ans; } struct node { long long a, b; node() {} node(long long aa, long long bb) { a = aa, b = bb; } inline node operator+(const node& x) const { return node(add(a, x.a), add(b, x.b)); } inline node operator+(const long long& x) const { return node(add(a, x), b); } inline node operator-(const node& x) const { return node(dec(a, x.a), dec(b, x.b)); } inline node operator-(const long long& x) const { return node(dec(a, x), b); } inline node operator*(const node& x) const { node ans; ans.a = (a * x.a + b * x.b * 5) % mod; ans.b = (a * x.b + b * x.a) % mod; return ans; } inline node operator*(const long long& x) const { return node(a * x % mod, b * x % mod); } friend inline node operator/(const node& x, const node& y) { node ans, z = y; if (z.b != 0) z.b = mod - z.b; ans = x * z; return ans * ksm(dec(y.a * y.a % mod, y.b * y.b * 5 % mod), mod - 2); } }; node ksm(node a, long long b) { node ans = node(1, 0); while (b) { if (b & 1) ans = ans * a; a = a * a; b >>= 1; } return ans; } node sum(node a, long long b) { return (ksm(a, b + 1) - a) / (a - 1); } node query(node x, long long l, long long r) { if (x.a == 1 && x.b == 0) return x * (r - l + 1); return sum(x, r) - sum(x, l - 1); } signed main() { scanf( %d%lld%lld , &k, &l, &r); l += 2, r += 2; p[0] = p[1] = inv[1] = 1; for (long long i = 2; i <= max(k, 5ll); i++) { p[i] = p[i - 1] * i % mod; inv[i] = (mod - mod / i) * inv[mod % i] % mod; } c[0][0] = c[1][0] = c[1][1] = s[0][0] = s[1][1] = 1; for (long long i = 2; i <= k; i++) { c[i][0] = 1, s[i][0] = 0; for (long long j = 1; j <= i; j++) c[i][j] = add(c[i - 1][j], c[i - 1][j - 1]), s[i][j] = dec(s[i - 1][j - 1], (i - 1) * s[i - 1][j] % mod); } node a = node(0, inv[5]), b = node(0, mod - inv[5]); node x = node(inv[2], inv[2]), y = node(inv[2], mod - inv[2]); for (long long i = 0; i <= k; i++) { node sum = node(0, 0); for (long long j = 0; j <= i; j++) { node ss = ksm(a, j) * ksm(b, i - j) * query(ksm(x, j) * ksm(y, i - j), l, r) * c[i][j]; sum = sum + ss; } sum = sum * s[k][i]; ans = add(ans, sum.a); } ans = ans * ksm(p[k], mod - 2) % mod; printf( %lld , ans); }
|
`include "divider.v"
`include "sim.v"
`define TESTS 5
module test;
reg[`WIDTH-1:0] a, b;
reg[`WIDTH-1:0] result, corr_result;
wire[`WIDTH-1:0] out, remainder;
reg start = 1'b0;
reg next_reg = 1'b0;
wire clk, reset, ready, next;
assign next = next_reg;
integer t;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
#10 start = 1'b1;
a = $random % 10;
b = $random % 10;
t = 0;
end
always @(posedge ready) begin
$display("Result = %d, exp = %d", out, corr_result);
start <= 1'b0;
#10 next_reg<= 1'b1;
end
always @(posedge next) begin
a <= $random % 10000;
b <= $random % 10;
#10 next_reg <= 1'b0;
#1 corr_result <= a/b;
#1 start <= 1'b1;
t = t+1;
if (t >= `TESTS-1)
#10 $finish;
end
divider div(
.start(start),
.clk(clk),
.dividend(b),
.divisor(a),
.quotient(out),
.remainder(remainder),
.ready(ready));
sim my_sim(.clk(clk), .reset(reset));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 2000; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; for (int i = 1; i <= n; i++) { long long l, r; cin >> l >> r; int ans = 0; long long mn = r; long long cur = 0; int cnt = 0; for (int i = 60; i >= 0; i--) { long long tmp = r; if (r & (1ll << i)) { if (cur + (1ll << i) - 1 >= l) { if (ans < cnt + i) { mn = cur + (1ll << i) - 1; ans = cnt + i; } } cnt++; cur += (1ll << i); } } if (cnt > ans) { ans = cnt; mn = r; } cout << mn << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; int pre[N]; int find(int x) { if (!pre[x]) return x; return pre[x] = find(pre[x]); } int d[510][510]; struct point { int x, y, z; void read() { scanf( %d%d%d , &x, &y, &z); } } a[N]; int type[N]; int main() { int n, m, r, x, y; scanf( %d%d%d , &n, &m, &r); int t = 0; for (int i = 1; i <= r; i++) { scanf( %d , &x); while (x--) type[++t] = i; } for (int i = 1; i <= m; i++) { a[i].read(); if (a[i].z == 0) { x = find(a[i].x); y = find(a[i].y); if (x != y) pre[x] = y; } } for (int i = 2; i <= n; i++) if (type[i] == type[i - 1] && find(i) != find(i - 1)) { cout << No << endl; return 0; } memset(d, -1, sizeof(d)); for (int i = 1; i <= m; i++) { x = type[a[i].x], y = type[a[i].y]; if (d[x][y] == -1) d[y][x] = d[x][y] = a[i].z; else d[y][x] = d[x][y] = min(d[x][y], a[i].z); } for (int i = 1; i <= r; i++) d[i][i] = 0; for (int k = 1; k <= r; k++) for (int i = 1; i <= r; i++) for (int j = 1; j <= r; j++) if (d[i][k] != -1 && d[k][j] != -1) if (d[i][j] == -1) d[i][j] = d[i][k] + d[k][j]; else d[i][j] = min(d[i][j], d[i][k] + d[k][j]); cout << Yes << endl; for (int i = 1; i <= r; i++) { for (int j = 1; j <= r; j++) { printf( %d , d[i][j]); } printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } const int N = 3e5 + 5; long long a[N]; int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string s; cin >> s; string open = ([{< ; string close = )]}> ; map<char, char> closeMp; for (int i = 0; i < 4; i++) closeMp[close[i]] = open[i]; stack<char> st; int ans = 0; for (auto i : s) { if (closeMp.count(i) == 0) { st.push(i); } else { if (st.empty()) return cout << Impossible , 0; else { if (st.top() != closeMp[i]) ans++; st.pop(); } } } if (st.empty()) cout << ans; else cout << Impossible ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int arr[300005]; map<int, int> mp; vector<int> opt; int main() { int n, lst = 0; cin >> n; for (int i = 1; i <= n; i++) { scanf( %d , &arr[i]); if (mp[arr[i]] && mp[arr[i]] > lst) { mp[arr[i]] = 0; opt.push_back(++lst); opt.push_back(i); lst = i; } else { mp[arr[i]] = i; } } int l = opt.size(); if (l / 2 == 0) { printf( -1 n ); return 0; } printf( %d n , l / 2); opt[l - 1] = n; for (int i = 0; i < l; i++) { printf( %d , opt[i++]); printf( %d n , opt[i]); } return 0; }
|
module tx_DS_char(
input TxReset,
input TxClk,
input valid_i,
input [7:0] dat_i,
input lchar_i,
output Tx0,
output Tx1,
output ready_o
);
reg ready;
reg [3:0] chrLen;
reg [1:0] icpLen;
reg [7:0] shreg;
reg lcharFlag;
reg parity;
reg Tx0, Tx1;
wire isReady = (ready && (chrLen == 4'd0) && (icpLen == 2'd2));
wire isSendingParity = (~ready && (icpLen == 2'd2));
wire isSendingLChar = (~ready && (icpLen == 2'd1));
wire isSendingBits = (~ready && (icpLen == 2'd0) && (chrLen > 0));
assign ready_o = isReady & ~valid_i;
always @(posedge TxClk) begin
ready <= ready;
chrLen <= chrLen;
icpLen <= icpLen;
parity <= parity;
Tx1 <= Tx1;
Tx0 <= Tx0;
shreg <= shreg;
if(TxReset) begin // S1
ready <= 1;
chrLen <= 0;
icpLen <= 2'd2;
parity <= 0;
Tx1 <= 0;
Tx0 <= 0;
shreg <= 8'd0;
end
else begin
if(isReady) begin
Tx0 <= 0;
Tx1 <= 0;
end
if(valid_i && isReady) begin // S2, S3
ready <= 0;
shreg <= dat_i;
lcharFlag <= lchar_i;
if(lchar_i) begin // S3
chrLen <= 4'd2;
end
else begin // S2
chrLen <= 4'd8;
end
end
if(isSendingParity) begin // S4
Tx1 <= ~lcharFlag ^ parity;
Tx0 <= lcharFlag ^ parity;
icpLen <= 2'd1;
end
if(isSendingLChar) begin // S5
Tx1 <= lcharFlag;
Tx0 <= ~lcharFlag;
icpLen <= 2'd0;
parity <= 0;
end
if(isSendingBits) begin // S6, S7
Tx1 <= shreg[0];
Tx0 <= ~shreg[0];
parity <= parity ^ shreg[0];
shreg <= (shreg >> 1);
chrLen <= chrLen - 1;
if(chrLen == 4'd1) begin // S7
ready <= 1;
icpLen <= 2'd2;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> odd, even; int main() { int cnt1 = 0, cnt2 = 0, tem = -1; int n, k, p, x; scanf( %d%d%d , &n, &k, &p); for (int i = 0; i < n; i++) { scanf( %d , &x); if (x % 2 == 0) { cnt2++; even.push_back(x); } else { if (cnt1 >= k - p) { if (tem == -1) tem = x; else { even.push_back(tem); even.push_back(x); cnt2++; tem = -1; } } else { cnt1++; odd.push_back(x); } } } if (cnt1 < k - p || cnt2 < p || tem != -1) printf( NO n ); else { printf( YES n ); if (p == 0) { for (int i = 0; i < k - p - 1; i++) printf( %d %d n , 1, odd[i]); printf( %d , n - (k - p - 1)); for (int i = 0; i < even.size(); i++) printf( %d , even[i]); printf( %d n , odd[k - p - 1]); return 0; } for (int i = 0; i < k - p; i++) printf( %d %d n , 1, odd[i]); int tem2 = 0, cur = 0; while (tem2 < p - 1) { if (even[cur] % 2 == 0) { printf( %d %d n , 1, even[cur]); cur++; } else { printf( %d %d %d n , 2, even[cur], even[cur + 1]); cur++; cur++; } tem2++; } if (even.size() > cur) printf( %d , even.size() - cur); for (int i = cur; i < even.size(); i++) printf( %d , even[i]); } return 0; }
|
`default_nettype none
module core_if #(
parameter CORE_ID = 32'h0
)(
/****************************************
System
****************************************/
input wire iCLOCK,
input wire inRESET,
/****************************************
Core
****************************************/
//oCORE_FLASH,
output wire oFREE_TLB_FLUSH,
/****************************************
GCI Controll
****************************************/
//Interrupt Controll
output wire oIO_IRQ_CONFIG_TABLE_REQ,
output wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID,
output wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL,
/****************************************
Instruction Memory
****************************************/
//Req
output wire oINST_REQ,
input wire iINST_LOCK,
output wire [1:0] oINST_MMUMOD,
output wire [31:0] oINST_PDT,
output wire [31:0] oINST_ADDR,
//RAM -> This
input wire iINST_VALID,
output wire oINST_BUSY,
input wire iINST_PAGEFAULT,
input wire iINST_QUEUE_FLUSH,
input wire [63:0] iINST_DATA,
input wire [27:0] iINST_MMU_FLAGS,
/****************************************
Data Memory
****************************************/
//Req
output wire oDATA_REQ,
input wire iDATA_LOCK,
output wire [1:0] oDATA_ORDER,
output wire [3:0] oDATA_MASK,
output wire oDATA_RW, //0=Write 1=Read
output wire [13:0] oDATA_TID,
output wire [1:0] oDATA_MMUMOD,
output wire [31:0] oDATA_PDT,
output wire [31:0] oDATA_ADDR,
//This -> Data RAM
output wire [31:0] oDATA_DATA,
//Data RAM -> This
input wire iDATA_VALID,
input wire iDATA_PAGEFAULT,
input wire [63:0] iDATA_DATA,
input wire [27:0] iDATA_MMU_FLAGS,
/****************************************
IO
****************************************/
//Req
output wire oIO_REQ,
input wire iIO_BUSY,
output wire [1:0] oIO_ORDER,
output wire oIO_RW, //0=Write 1=Read
output wire [31:0] oIO_ADDR,
//Write
output wire [31:0] oIO_DATA,
//Rec
input wire iIO_VALID,
input wire [31:0] iIO_DATA,
/****************************************
Interrupt
****************************************/
input wire iINTERRUPT_VALID,
output wire oINTERRUPT_ACK,
input wire [5:0] iINTERRUPT_NUM,
/****************************************
System Infomation
****************************************/
input wire iSYSINFO_IOSR_VALID,
input wire [31:0] iSYSINFO_IOSR
);
/************************************************************************************
Core - Main Pipeline
************************************************************************************/
core_pipeline #(CORE_ID) CORE_PIPELINE(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Core
.oFREE_TLB_FLUSH(oFREE_TLB_FLUSH),
//GCI Interrupt Controll
//Interrupt Control
.oIO_IRQ_CONFIG_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIO_IRQ_CONFIG_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
//Instruction Memory Request
.oINST_REQ(oINST_REQ),
.iINST_LOCK(iINST_LOCK),
.oINST_MMUMOD(oINST_MMUMOD),
.oINST_PDT(oINST_PDT),
.oINST_ADDR(oINST_ADDR),
.iINST_VALID(iINST_VALID),
.oINST_BUSY(oINST_BUSY),
.iINST_PAGEFAULT(iINST_PAGEFAULT),
.iINST_QUEUE_FLUSH(iINST_QUEUE_FLUSH),
.iINST_DATA(iINST_DATA),
.iINST_MMU_FLAGS(iINST_MMU_FLAGS),
/****************************************
Data Memory
****************************************/
//Req
.oDATA_REQ(oDATA_REQ),
.iDATA_LOCK(iDATA_LOCK),
.oDATA_ORDER(oDATA_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oDATA_MASK(oDATA_MASK),
.oDATA_RW(oDATA_RW), //1=Write 0=Read
.oDATA_TID(oDATA_TID),
.oDATA_MMUMOD(oDATA_MMUMOD),
.oDATA_PDT(oDATA_PDT),
.oDATA_ADDR(oDATA_ADDR),
//This -> Data RAM
.oDATA_DATA(oDATA_DATA),
//Data RAM -> This
.iDATA_VALID(iDATA_VALID),
.iDATA_PAGEFAULT(iDATA_PAGEFAULT),
.iDATA_DATA(iDATA_DATA),
.iDATA_MMU_FLAGS(iDATA_MMU_FLAGS),
/****************************************
IO
****************************************/
//Req
.oIO_REQ(oIO_REQ),
.iIO_BUSY(iIO_BUSY),
.oIO_ORDER(oIO_ORDER), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oIO_RW(oIO_RW), //0=Write 1=Read
.oIO_ADDR(oIO_ADDR),
//Write
.oIO_DATA(oIO_DATA),
//Rec
.iIO_VALID(iIO_VALID),
.iIO_DATA(iIO_DATA),
//Interrupt
.iINTERRUPT_VALID(iINTERRUPT_VALID),
.oINTERRUPT_ACK(oINTERRUPT_ACK),
.iINTERRUPT_NUM(iINTERRUPT_NUM),
.iSYSINFO_IOSR_VALID(iSYSINFO_IOSR_VALID),
.iSYSINFO_IOSR(iSYSINFO_IOSR)
);
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int INF = 1791791791; const long long INFLL = 1791791791791791791ll; template <int input_buf_size, int output_buf_size> class FastIO { char cbuf[input_buf_size + 1]; int icur = 0; inline bool go_to_next_token() { while (cbuf[icur] == || cbuf[icur] == n ) icur++; while (cbuf[icur] == 0) { icur = 0; if (fgets(cbuf, sizeof(cbuf), stdin) != cbuf) return false; while (cbuf[icur] == || cbuf[icur] == n ) icur++; } return true; } public: string readString() { assert(go_to_next_token()); string ans; while (cbuf[icur] != && cbuf[icur] != n && cbuf[icur] != 0) ans.push_back(cbuf[icur++]); ans.shrink_to_fit(); return ans; } template <class int_type> int_type readInt() { assert(go_to_next_token()); int_type x = 0; bool m = cbuf[icur] == - ; if (m) icur++; while ( 0 <= cbuf[icur] && cbuf[icur] <= 9 ) { x *= 10; x += (cbuf[icur] - 0 ); icur++; } if (m) x = -x; return x; } bool seekEof() { return !go_to_next_token(); } private: char obuf[output_buf_size + 1]; int ocur = 0; inline void write_string(const char* str, size_t sz = 0) { if (sz == 0) sz = strlen(str); if (ocur + sz > output_buf_size) { fputs(obuf, stdout); fputs(str, stdout); ocur = 0; obuf[0] = 0; return; } strcpy(obuf + ocur, str); ocur += sz; obuf[ocur] = 0; } public: template <class int_type> void writeInt(int_type x, bool sp = true) { char buf[20]; int c = 0; if (x < 0) { buf[c++] = - ; x = -x; } int s = c; if (x == 0) { buf[c++] = 0 ; } while (x > 0) { buf[c++] = (x % 10) + 0 ; x /= 10; } for (int i = 0; 2 * i < c - s; i++) { swap(buf[s + i], buf[c - 1 - i]); } buf[c] = 0; write_string(buf, c); if (sp) write_string( , 1); } void writeString(string s, bool space = true) { write_string(s.c_str(), s.size()); if (space) write_string( , 1); } void writeEndl() { write_string( n , 1); } void flush() { fputs(obuf, stdout); ocur = 0; obuf[0] = 0; } private: bool lflush; public: FastIO(bool local_flush) { obuf[0] = 0; lflush = local_flush; } ~FastIO() { fputs(obuf, stdout); } }; FastIO<10000000, 10000000> IO(true); const int maxn = 3179; vector<int> graph[maxn]; int dist[maxn][maxn]; vector<int> mdff[maxn]; vector<int> mdfs[maxn]; int main() { int n = IO.readInt<int>(); int m = IO.readInt<int>(); for (int i = 0; i < ((int)(m)); ++i) { int u = IO.readInt<int>() - 1; int v = IO.readInt<int>() - 1; graph[u].push_back(v); } for (int start = 0; start < ((int)(n)); ++start) { fill(dist[start], dist[start] + n, -1); dist[start][start] = 0; queue<int> q; q.push(start); while (!q.empty()) { int a = q.front(); q.pop(); for (int v : graph[a]) { if (dist[start][v] == -1) { dist[start][v] = dist[start][a] + 1; q.push(v); } } } } for (int i = 0; i < ((int)(n)); ++i) { for (int j = 0; j < ((int)(n)); ++j) if (j != i) { mdfs[i].push_back(j); mdff[i].push_back(j); } sort((mdfs[i]).begin(), (mdfs[i]).end(), [&](const int& a, const int& b) -> bool { return dist[i][a] > dist[i][b]; }); sort((mdff[i]).begin(), (mdff[i]).end(), [&](const int& a, const int& b) -> bool { return dist[a][i] > dist[b][i]; }); } int a, b, c, d; int ans = -1; for (int m1 = 0; m1 < ((int)(n)); ++m1) { for (int m2 = 0; m2 < ((int)(n)); ++m2) { if (m1 != m2) { for (int i = 0; i < ((int)(3)); ++i) { for (int j = 0; j < ((int)(3)); ++j) { int l = mdff[m1][i]; int r = mdfs[m2][j]; if (m1 == r || m2 == l || l == r) continue; if (dist[l][m1] == -1 || dist[m1][m2] == -1 || dist[m2][r] == -1) continue; if (dist[l][m1] + dist[m1][m2] + dist[m2][r] > ans) { ans = dist[l][m1] + dist[m1][m2] + dist[m2][r]; a = l; b = m1; c = m2; d = r; } } } } } } cerr << ans << endl; IO.writeInt(a + 1); IO.writeInt(b + 1); IO.writeInt(c + 1); IO.writeInt(d + 1); IO.writeEndl(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 500010; const int LOG = 20; const long long INF = (1ll << 60); int n; int a[N]; vector<int> adj[N]; int par[LOG][N]; void dfs(int u, int p) { par[0][u] = p; for (int i = 1; i < LOG; i++) { par[i][u] = par[i - 1][par[i - 1][u]]; } for (int v : adj[u]) { if (v != p) dfs(v, u); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; int root = -1; for (int i = 1; i <= n; i++) { cin >> a[i]; if (root == -1 || a[root] > a[i]) root = i; } for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(root, 0); long long res = 0; for (int i = 1; i <= n; i++) { if (i == root) continue; long long foo = INF; for (int j = 0; j < LOG; j++) { int u = par[j][i]; if (u == 0) u = root; foo = min(foo, 1ll * a[u] * (j + 1)); if (u == root) break; } res += foo; res += a[i]; } cout << res << endl; return 0; }
|
`default_nettype none
`timescale 1ns/1ns
module tb_membusif();
wire clk, reset;
clock clock(clk, reset);
// avalon
reg a_write = 0;
reg a_read = 0;
reg [31:0] a_writedata = 0;
reg [1:0] a_address;
wire [31:0] a_readdata;
wire a_waitrequest;
// membus
wire b_rq_cyc;
wire b_rd_rq;
wire b_wr_rq;
wire [21:35] b_ma;
wire [18:21] b_sel;
wire b_fmc_select;
wire [0:35] b_mb_write;
wire b_wr_rs;
wire [0:35] b_mb_read = b_mb_read_0 | b_mb_read_1;
wire b_addr_ack = b_addr_ack_0 | b_addr_ack_1;
wire b_rd_rs = b_rd_rs_0 | b_rd_rs_1;
membusif membusif0(
.clk(clk),
.reset(reset),
.s_address(a_address),
.s_write(a_write),
.s_read(a_read),
.s_writedata(a_writedata),
.s_readdata(a_readdata),
.s_waitrequest(a_waitrequest),
.m_rq_cyc(b_rq_cyc),
.m_rd_rq(b_rd_rq),
.m_wr_rq(b_wr_rq),
.m_ma(b_ma),
.m_sel(b_sel),
.m_fmc_select(b_fmc_select),
.m_mb_write(b_mb_write),
.m_wr_rs(b_wr_rs),
.m_mb_read(b_mb_read),
.m_addr_ack(b_addr_ack),
.m_rd_rs(b_rd_rs));
wire [0:35] b_mb_read_0;
wire b_addr_ack_0;
wire b_rd_rs_0;
core161c cmem(
.clk(clk),
.reset(~reset),
.power(1'b1),
.sw_single_step(1'b0),
.sw_restart(1'b0),
.membus_rq_cyc_p0(b_rq_cyc),
.membus_rd_rq_p0(b_rd_rq),
.membus_wr_rq_p0(b_wr_rq),
.membus_ma_p0(b_ma),
.membus_sel_p0(b_sel),
.membus_fmc_select_p0(b_fmc_select),
.membus_mb_in_p0(b_mb_write),
.membus_wr_rs_p0(b_wr_rs),
.membus_mb_out_p0(b_mb_read_0),
.membus_addr_ack_p0(b_addr_ack_0),
.membus_rd_rs_p0(b_rd_rs_0),
.membus_wr_rs_p1(1'b0),
.membus_rq_cyc_p1(1'b0),
.membus_rd_rq_p1(1'b0),
.membus_wr_rq_p1(1'b0),
.membus_ma_p1(15'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_mb_in_p1(36'b0),
.membus_wr_rs_p2(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_rd_rq_p2(1'b0),
.membus_wr_rq_p2(1'b0),
.membus_ma_p2(15'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_mb_in_p2(36'b0),
.membus_wr_rs_p3(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_rd_rq_p3(1'b0),
.membus_wr_rq_p3(1'b0),
.membus_ma_p3(15'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0),
.membus_mb_in_p3(36'b0)
);
wire [0:35] b_mb_read_1;
wire b_addr_ack_1;
wire b_rd_rs_1;
fast162 fmem(
.clk(clk),
.reset(~reset),
.power(1'b1),
.sw_single_step(1'b0),
.sw_restart(1'b0),
.membus_rq_cyc_p0(b_rq_cyc),
.membus_rd_rq_p0(b_rd_rq),
.membus_wr_rq_p0(b_wr_rq),
.membus_ma_p0(b_ma),
.membus_sel_p0(b_sel),
.membus_fmc_select_p0(b_fmc_select),
.membus_mb_in_p0(b_mb_write),
.membus_wr_rs_p0(b_wr_rs),
.membus_mb_out_p0(b_mb_read_1),
.membus_addr_ack_p0(b_addr_ack_1),
.membus_rd_rs_p0(b_rd_rs_1),
.membus_wr_rs_p1(1'b0),
.membus_rq_cyc_p1(1'b0),
.membus_rd_rq_p1(1'b0),
.membus_wr_rq_p1(1'b0),
.membus_ma_p1(15'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_mb_in_p1(36'b0),
.membus_wr_rs_p2(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_rd_rq_p2(1'b0),
.membus_wr_rq_p2(1'b0),
.membus_ma_p2(15'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_mb_in_p2(36'b0),
.membus_wr_rs_p3(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_rd_rq_p3(1'b0),
.membus_wr_rq_p3(1'b0),
.membus_ma_p3(15'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0),
.membus_mb_in_p3(36'b0)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars();
cmem.core[4] = 123;
cmem.core[5] = 321;
cmem.core['o123] = 36'o112233445566;
fmem.ff[3] = 36'o777777666666;
#5;
#200;
// write address
@(posedge clk);
a_address <= 0;
a_write <= 1;
a_writedata <= 32'o0000123;
@(negedge a_write);
@(posedge clk);
a_address <= 2;
a_read <= 1;
@(negedge a_read);
@(posedge clk);
a_address <= 1;
a_read <= 1;
@(negedge a_read);
// write address
@(posedge clk);
a_address <= 0;
a_write <= 1;
a_writedata <= 32'o0000124;
@(negedge a_write);
@(posedge clk);
a_address <= 2;
a_read <= 1;
@(negedge a_read);
@(posedge clk);
a_address <= 1;
a_read <= 1;
@(negedge a_read);
/*
// write low word
@(posedge clk);
a_address <= 1;
a_write <= 1;
a_writedata <= 32'o111222;
@(negedge a_write);
// write high word
@(posedge clk);
a_address <= 2;
a_write <= 1;
a_writedata <= 32'o333444;
@(negedge a_write);
*/
end
initial begin
#40000;
$finish;
end
always @(posedge clk) begin
if(~a_waitrequest & a_write)
a_write <= 0;
if(~a_waitrequest & a_read)
a_read <= 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> g[100005]; int n, fa[100005], p[100005], size[100005], tsize[100005], q, d[100005]; long long ans = 0, sum[100005]; void dfs(int x, int f) { p[x] = f, fa[x] = x, size[x] = tsize[x] = 1, d[x] = d[f] + 1, ans += 1ll * (n - 2) * (n - 1); for (int y : g[x]) { if (y == f) continue; dfs(y, x), tsize[x] += tsize[y], sum[x] += 1ll * tsize[y] * (tsize[y] - 1); } ans -= 1ll * (n - tsize[x]) * (n - tsize[x] - 1) + sum[x]; } int gf(int x) { return x == fa[x] ? x : fa[x] = gf(fa[x]); } void Add(int x, long long dlt) { ans += dlt * size[x] * (1ll * (n - size[x]) * (n - size[x] - 1) - sum[x] - 1ll * (n - tsize[x]) * (n - tsize[x] - 1)); ans += dlt * size[x] * (size[x] - 1) * (n - size[x]) * 2; ans += dlt * size[x] * (size[x] - 1) * (size[x] - 2); } void Merge(int x, int y) { x = gf(x), y = gf(y); if (x == y) return; Add(x, -1), Add(y, -1), fa[x] = y, size[y] += size[x], sum[y] += sum[x] - 1ll * (tsize[x] - 1) * tsize[x], Add(y, 1); } int main() { cin >> n; for (int i = 1, x, y; i < n; i++) cin >> x >> y, g[x].push_back(y), g[y].push_back(x); dfs(1, 0), cout << ans << n , cin >> q; while (q--) { int x, y; cin >> x >> y, x = gf(x), y = gf(y); while (x ^ y) { if (d[gf(p[x])] < d[gf(p[y])]) swap(x, y); Merge(x, p[x]), x = gf(p[x]), y = gf(y); } cout << ans << n ; } return 0; }
|
//=======================================================
// ECE3400 Fall 2017
// Lab 3: Template top-level module
//
// Top-level skeleton from Terasic
// Modified by Claire Chen for ECE3400 Fall 2017
//=======================================================
`define ONE_SEC 25000000
module DE0_NANO(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
GPIO_0_D,
GPIO_0_IN,
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
GPIO_1_D,
GPIO_1_IN,
);
//=======================================================
// PARAMETER declarations
//=======================================================
localparam ONE_SEC = 25000000; // one second in 25MHz clock cycles
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//output [7:0] q; //DAC
/////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [33:0] GPIO_0_D;
input [1:0] GPIO_0_IN;
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO_1_D;
input [1:0] GPIO_1_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg CLOCK_25;
wire reset; // active high reset signal
reg address; // sin table stuff
wire [9:0] PIXEL_COORD_X; // current x-coord from VGA driver
wire [9:0] PIXEL_COORD_Y; // current y-coord from VGA driver
wire [7:0] PIXEL_COLOR; // input 8-bit pixel color for current coords
reg [24:0] led_counter; // timer to keep track of when to toggle LED
reg led_state; // 1 is on, 0 is off
reg [7:0] q; //DAC
// Module outputs coordinates of next pixel to be written onto screen
VGA_DRIVER driver(
.RESET(reset),
.CLOCK(CLOCK_25),
.PIXEL_COLOR_IN(PIXEL_COLOR),
.PIXEL_X(PIXEL_COORD_X),
.PIXEL_Y(PIXEL_COORD_Y),
.PIXEL_COLOR_OUT({GPIO_0_D[9],GPIO_0_D[11],GPIO_0_D[13],GPIO_0_D[15],GPIO_0_D[17],GPIO_0_D[19],GPIO_0_D[21],GPIO_0_D[23]}),
.H_SYNC_NEG(GPIO_0_D[7]),
.V_SYNC_NEG(GPIO_0_D[5])
);
assign reset = ~KEY[0]; // reset when KEY0 is pressed
assign PIXEL_COLOR = 8'b000_111_00; // Green
assign LED[0] = led_state;
assign GPIO_0_D[7:0] = q[7:0];
reg [7:0] sin[0:15];
//PUT the sintable in rom!
initial
begin
$readmemb("sinetable.txt", sin);
end
//=======================================================
// Structural coding
//=======================================================
// Generate 25MHz clock for VGA, FPGA has 50 MHz clock
always @ (posedge CLOCK_50) begin
CLOCK_25 <= ~CLOCK_25;
end // always @ (posedge CLOCK_50)
// Simple state machine to toggle LED0 every one second
always @ (posedge CLOCK_25) begin
if (reset) begin
led_state <= 1'b0;
led_counter <= 25'b0;
end
if (led_counter == ONE_SEC) begin
led_state <= ~led_state;
led_counter <= 25'b0;
end
else begin
led_state <= led_state;
led_counter <= led_counter + 25'b1;
end // always @ (posedge CLOCK_25)
end
// Read from requested address of ROM
always @ (posedge CLOCK_25)
begin
q <= sin[address];
address = address+1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_2_V
`define SKY130_FD_SC_LP__A21OI_2_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21oi_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 300005; const int MD = 1000000007; int n, a[N]; long long s[N], k; int ft[N]; long long all[N]; int gt(int first) { int res = 0; for (int i = first; i >= 0; i &= i + 1, --i) res += ft[i]; return res; } void upd(int first, int v) { for (int i = first; i < N; i |= i + 1) ft[i] += v; } long long chk(long long first) { memset(ft, 0, sizeof ft); for (int _tmp = (n), i = (0); i <= _tmp; ++i) all[i] = s[i]; sort(all, all + n + 1); upd(lower_bound(all, all + n + 1, s[0]) - all, +1); long long res = 0; for (int _tmp = (n), i = (1); i <= _tmp; ++i) { res += gt(upper_bound(all, all + n + 1, s[i] - first) - all - 1); upd(lower_bound(all, all + n + 1, s[i]) - all, +1); } return res; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (int _tmp = (n), i = (1); i <= _tmp; ++i) { cin >> a[i]; s[i] = a[i] + s[i - 1]; } long long l = -1e14, r = 1e14, rs = 0; while (l <= r) { long long m = (l + r) / 2; if (chk(m) >= k) { l = m + 1; rs = m; } else { r = m - 1; } } cout << rs << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S2S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLYMETAL6S2S_FUNCTIONAL_PP_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlymetal6s2s (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S2S_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int i, j, k, l, n, m, s; int a[1000], b[1000]; int main() { cin >> n >> m; for (i = 1; i <= n; i++) { cin >> l; a[l]++; } for (i = 1; i <= 110; i++) { s = 0; for (j = i; j <= i + m; j++) s = s + a[j]; k = max(k, s); } cout << n - k; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 2 == 1) { cout << (n - 1) / 2 << endl; } else { long long x = 1; while (2 * x <= n) { x *= 2; } cout << (n - x) / 2 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; inline int add(int a, int b) { if ((a += b) >= mod) a -= mod; return a; } inline int dec(int a, int b) { if ((a -= b) < 0) a += mod; return a; } inline void _add(int& a, int b) { if ((a += b) >= mod) a -= mod; } inline void _dec(int& a, int b) { if ((a -= b) < 0) a += mod; } inline int mult(int a, int b) { long long t = 1ll * a * b; if (t >= mod) t %= mod; return t; } const int L = 16; char s[510]; int n, nodecnt = 0, f[170][65536], f2[170][65536]; void fwt_or(int* A, int flag) { if (flag == 1) for (int i = 1; i < 65536; i <<= 1) for (int j = 0; j < 65536; j += (i << 1)) for (int k = 0; k < i; k++) _add(A[i + j + k], A[j + k]); else for (int i = 1; i < 65536; i <<= 1) for (int j = 0; j < 65536; j += (i << 1)) for (int k = 0; k < i; k++) _dec(A[i + j + k], A[j + k]); } void fwt_and(int* A, int flag) { if (flag == 1) for (int i = 1; i < 65536; i <<= 1) for (int j = 0; j < 65536; j += (i << 1)) for (int k = 0; k < i; k++) _add(A[j + k], A[i + j + k]); else for (int i = 1; i < 65536; i <<= 1) for (int j = 0; j < 65536; j += (i << 1)) for (int k = 0; k < i; k++) _dec(A[j + k], A[i + j + k]); } int dfs(int l, int r) { int p = ++nodecnt; if (l == r) { if (s[l] == ? ) { for (int t = 0; t < 4; t++) { int S = 0; for (int i = 0; i < 16; i++) if ((i >> t) & 1) S |= (1 << i); f[p][S]++; f[p][65535 ^ S]++; } } else { if (s[l] >= A && s[l] <= D ) { int t = s[l] - A , S = 0; for (int i = 0; i < 16; i++) if ((i >> t) & 1) S |= (1 << i); f[p][S] = 1; } else { int t = s[l] - a , S = 0; for (int i = 0; i < 16; i++) if ((i >> t) & 1) S |= (1 << i); f[p][65535 ^ S] = 1; } } memcpy(f2[p], f[p], sizeof(f[p])); return p; } int cnt = 0, pos = 0; for (int i = l; i <= r; i++) { if (s[i] == ( ) cnt++; else if (s[i] == ) ) cnt--; if (!cnt) { pos = i + 1; break; } } int lc = dfs(l + 1, pos - 2), rc = dfs(pos + 2, r - 1); if (s[pos] != | ) { fwt_and(f[lc], 1); fwt_and(f[rc], 1); for (int i = 0; i < 65536; i++) f[p][i] = mult(f[lc][i], f[rc][i]); fwt_and(f[p], -1); } if (s[pos] != & ) { fwt_or(f2[lc], 1); fwt_or(f2[rc], 1); for (int i = 0; i < 65536; i++) f2[p][i] = mult(f2[lc][i], f2[rc][i]); fwt_or(f2[p], -1); } for (int i = 0; i < 65536; i++) _add(f[p][i], f2[p][i]); memcpy(f2[p], f[p], sizeof(f[p])); return p; } int m, fs[16]; int main() { scanf( %s , s + 1); n = strlen(s + 1); dfs(1, n); scanf( %d , &m); memset(fs, 255, sizeof(fs)); for (int i = 1, a, b, c, d, e; i <= m; i++) { scanf( %d%d%d%d%d , &a, &b, &c, &d, &e); fs[a | (b << 1) | (c << 2) | (d << 3)] = e; } int ans = 0; for (int i = 0; i < 65536; i++) { bool s = 1; for (int j = 0; j < 16; j++) s &= (fs[j] == -1 || fs[j] == ((i >> j) & 1)); if (s) ans = add(ans, f[1][i]); } printf( %d n , ans); return 0; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
reg sampling_event_prev;
reg r_reset_n;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_sampling_event;
wire valid_test_expr;
wire valid_sampling_event_prev;
assign valid_sampling_event = ~(sampling_event^sampling_event);
assign valid_test_expr = ~(test_expr^test_expr);
assign valid_sampling_event_prev = ~(sampling_event_prev ^
sampling_event_prev);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
`ifdef OVL_SYNTHESIS
`else
initial begin
r_reset_n = 1'b0;
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
r_reset_n <= `OVL_RESET_SIGNAL;
// Capture Sampling Event @Clock for rising edge detections
sampling_event_prev <= sampling_event;
if ((edge_type == `OVL_NOEDGE) && (!test_expr))
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is FALSE irrespective of sampling event");
else if ((edge_type == `OVL_POSEDGE) && (!sampling_event_prev) &&
(sampling_event) && (!test_expr) && r_reset_n)
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is FALSE on posedge of sampling event");
else if ((edge_type == `OVL_NEGEDGE) && (sampling_event_prev) &&
(!sampling_event) && (!test_expr) && r_reset_n)
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is FALSE on negedge of sampling event");
else if ((edge_type == `OVL_ANYEDGE) &&
(sampling_event_prev != sampling_event) && (!test_expr) &&
r_reset_n)
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is FALSE on any edge of sampling event");
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
//x/z checking for test_expr
if ( (edge_type == `OVL_NOEDGE) ||
((edge_type == `OVL_POSEDGE) && (!sampling_event_prev) &&
(sampling_event) && r_reset_n) ||
((edge_type == `OVL_NEGEDGE) && (sampling_event_prev) &&
(!sampling_event) && r_reset_n) ||
((edge_type == `OVL_ANYEDGE) &&
(sampling_event_prev != sampling_event) && r_reset_n) )
begin
if ( valid_test_expr == 1'b1 )
begin
//Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
//x/z checking for sampling_event
if ( r_reset_n && (edge_type != `OVL_NOEDGE) )
begin
if ( valid_sampling_event == 1'b1 )
begin
if ( valid_sampling_event_prev == 1'b1 )
begin
//Do nothing
end
else if ( ( (edge_type == `OVL_POSEDGE) &&
(sampling_event == 1'b1) ) ||
( (edge_type == `OVL_NEGEDGE) &&
(sampling_event == 1'b0) ) ||
( (edge_type == `OVL_ANYEDGE) ) )
begin
ovl_error_t(`OVL_FIRE_XCHECK,"sampling_event contains X or Z");
end
end
else if ( ( (edge_type == `OVL_POSEDGE) && (!sampling_event_prev) )||
( (edge_type == `OVL_NEGEDGE) && (sampling_event_prev) ) ||
( (edge_type == `OVL_ANYEDGE) ) )
begin
ovl_error_t(`OVL_FIRE_XCHECK,"sampling_event contains X or Z");
end
else if ( valid_sampling_event_prev == 1'b1 )
begin
//Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"sampling_event contains X or Z");
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
else begin
r_reset_n <= 1'b0;
`ifdef OVL_INIT_REG
sampling_event_prev <= 1'b0;
`endif
end
end
`endif // OVL_ASSERT_ON
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<pair<pair<int, int>, pair<int, int> > > ans; bool invert; void print(vector<vector<string> > &mat) { for (auto vs : mat) { for (string s : vs) { printf( |%6s| , s.c_str()); } cout << endl; } } void move(int si, int sj, int ti, int tj) { assert(si != ti || sj != tj); if (si != ti && sj != tj) { move(si, sj, si, tj); move(si, tj, ti, tj); } else ans.push_back({{si + 1, sj + 1}, {ti + 1, tj + 1}}); } void clean(vector<vector<string> > &mat, int i, int j) { if (invert) reverse(mat[i][j].begin(), mat[i][j].end()); for (char c : mat[i][j]) { if (c == 1 ) { move(i, j, 0, 1); mat[0][1].push_back(c); } if (c == 0 ) { move(i, j, 0, 0); mat[0][0].push_back(c); } } mat[i][j].clear(); } void simulate(vector<vector<string> > mat) { printf( npart 1: n ); print(mat); int cnt = 0; int n = ans.size(); assert(!ans.empty()); for (auto p : ans) { int si = p.first.first - 1; int sj = p.first.second - 1; int ti = p.second.first - 1; int tj = p.second.second - 1; assert(!mat[si][sj].empty()); char c = mat[si][sj].back(); mat[si][sj].pop_back(); string aux; aux.push_back(c); mat[ti][tj] = aux + mat[ti][tj]; cnt++; printf( step %d: n , cnt); print(mat); if (2 * cnt == n) printf( npart 2 n ); } } void go(vector<vector<string> > &mat) { string z0, z1, o0, o1; if (invert) { reverse(mat[0][0].begin(), mat[0][0].end()); reverse(mat[0][1].begin(), mat[0][1].end()); } for (char c : mat[0][0]) { if (c == 0 ) z0.push_back(c), move(0, 0, 1, 0); else o0.push_back(c), move(0, 0, 0, 1); } for (char c : mat[0][1]) { if (c == 0 ) z1.push_back(c), move(0, 1, 0, 0); else o1.push_back(c), move(0, 1, 1, 1); } if (invert) { mat[1][0] = z0 + mat[1][0]; mat[1][1] = o1 + mat[1][1]; } else { mat[1][0] = mat[1][0] + z0; mat[1][1] = mat[1][1] + o1; } mat[0][0] = z1; mat[0][1] = o0; for (int i = 0; (i) < int(n); (i)++) { if (i == 0) continue; string aux; if (invert) reverse(mat[i][0].begin(), mat[i][0].end()); for (char c : mat[i][0]) { if (c == 0 ) { move(i, 0, 0, 0); mat[0][0].push_back(c); } else { aux.push_back(c); move(i, 0, i, 1); } } if (invert) mat[i][1] = aux + mat[i][1]; else mat[i][1] = mat[i][1] + aux; mat[i][0].clear(); } for (int i = 0; (i) < int(n); (i)++) for (int j = 0; (j) < int(m); (j)++) { if (j == 0) continue; if (i == 0 && j == 1) continue; clean(mat, i, j); } } vector<vector<string> > from, to; int main() { while (cin >> n >> m) { from.resize(n); for (int i = 0; (i) < int(n); (i)++) { from[i].resize(m); for (int j = 0; (j) < int(m); (j)++) cin >> from[i][j]; } to.resize(n); for (int i = 0; (i) < int(n); (i)++) { to[i].resize(m); for (int j = 0; (j) < int(m); (j)++) cin >> to[i][j]; } vector<vector<string> > aux = from; invert = true; ans.clear(); go(from); auto p1 = ans; invert = false; ans.clear(); go(to); auto p2 = ans; for (auto &pp : p2) swap(pp.first, pp.second); reverse(p2.begin(), p2.end()); ans = p1; ans.insert(ans.end(), p2.begin(), p2.end()); printf( %d n , int(ans.size())); for (auto pp : ans) { printf( %d %d %d %d n , pp.first.first, pp.first.second, pp.second.first, pp.second.second); } } return 0; }
|
// megafunction wizard: %ALTSYNCRAM%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: altera_ram.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 178 04/27/2006 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_ram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [10:0] rdaddress;
input [10:0] wraddress;
input wren;
output [7:0] q;
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_b ({8{1'b1}}),
.q_a (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL rdaddress[10..0]
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL wraddress[10..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_wave*.jpg FALSE
|
#include<bits/stdc++.h> #include<algorithm> using namespace std; #define ll long long #define ld long double #define rep(i,a,b) for(ll i=a;i<b;i++) #define repb(i,a,b) for(ll i=a;i>=b;i--) #define err() cout<< ================================== <<endl; #define errA(A) for(auto i:A) cout<<i<< ;cout<<endl; #define err1(a) cout<<#a<< <<a<<endl #define err2(a,b) cout<<#a<< <<a<< <<#b<< <<b<<endl #define err3(a,b,c) cout<<#a<< <<a<< <<#b<< <<b<< <<#c<< <<c<<endl #define err4(a,b,c,d) cout<<#a<< <<a<< <<#b<< <<b<< <<#c<< <<c<< <<#d<< <<d<<endl #define pb push_back #define all(A) A.begin(),A.end() #define allr(A) A.rbegin(),A.rend() #define ft first #define sd second #define pll pair<ll,ll> #define V vector<ll> #define S set<ll> #define VV vector<V> #define Vpll vector<pll> #define VVpll vector<Vpll> #define endl n const ll logN = 20; const ll N=100005; const ll M = 1000000007; const ll M2=998244353 ; const ll INF = 1e12; #define PI 3.14159265 #define fast ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL) ll pow1(ll a,ll b){ ll res=1; while(b>0){ if(b&1){ res=(res*a)%M; } a=(a*a)%M; b>>=1; } return res%M; } map<ll,ll>mp; V a; ll n; void recur(ll depth,ll ind1=0, ll ind2=n-1 ) { if(ind1>ind2)return; ll mx_ind; ll mx=LLONG_MIN; rep(i,ind1,ind2+1) { if(a[i]>mx) { mx=a[i]; mx_ind=i; } } mp[mx_ind]=depth; recur(depth+1,ind1,mx_ind-1); recur(depth+1,mx_ind+1,ind2); return; } int main() { fast; #ifndef ONLINE_JUDGE freopen( ../input.txt , r , stdin); freopen( ../output.txt , w , stdout); #endif ll T=1; cin>>T; while(T--) { cin>>n; a=V(n); rep(i,0,n)cin>>a[i]; recur(0); for(auto it:mp) cout<<it.sd<< ; cout<<endl; mp.clear(); } }
|
/**
* bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma.v
*
* If a read and write are issued to the same address the new value is read back.
*
*/
`include "bsg_defines.v"
module bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter data_width_in_bytes_lp=(width_p>>3)
, parameter write_mask_width_lp=data_width_in_bytes_lp
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter byte_offset_width_lp=$clog2(data_width_in_bytes_lp)
, parameter init_mem_p=0
)
(
input clk_i
, input reset_i
// ctrl interface
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input [write_mask_width_lp-1:0] w_mask_i
// read channel
, output logic [width_p-1:0] data_o
);
import "DPI-C" context function
chandle bsg_mem_dma_init(longint unsigned id,
longint unsigned channel_addr_width_fp,
longint unsigned data_width_fp,
longint unsigned mem_els_fp,
longint unsigned init_mem_fp);
import "DPI-C" context function
void bsg_mem_dma_exit(longint unsigned id);
import "DPI-C" context function
byte unsigned bsg_mem_dma_get(chandle handle, longint unsigned addr);
import "DPI-C" context function
void bsg_mem_dma_set(chandle handle, longint unsigned addr, byte val);
chandle memory;
initial begin
memory
= bsg_mem_dma_init(id_p, addr_width_lp, width_p, els_p, init_mem_p);
end
final begin
bsg_mem_dma_exit(id_p);
end
////////////////
// read logic //
////////////////
logic [addr_width_lp+byte_offset_width_lp-1:0] read_byte_addr;
assign read_byte_addr = { r_addr_i, {(byte_offset_width_lp){1'b0}} };
logic [width_p-1:0] data_r;
always_ff @(negedge clk_i) begin
if (r_v_i) begin
for (integer byte_id = 0; byte_id < data_width_in_bytes_lp; byte_id++) begin
data_r[byte_id*8+:8] <= bsg_mem_dma_get(memory, read_byte_addr+byte_id);
end
end
end
// most client code expects outputs to change at the positive edge
always_ff @(posedge clk_i) begin
data_o <= data_r;
end
/////////////////
// write logic //
/////////////////
logic [addr_width_lp+byte_offset_width_lp-1:0] write_byte_addr;
assign write_byte_addr = { w_addr_i, {(byte_offset_width_lp){1'b0}} };
logic [width_p-1:0] mem_data_li;
logic write_valid;
assign write_valid = ~reset_i & w_v_i;
assign mem_data_li = w_data_i;
always_ff @(posedge clk_i) begin
for (integer byte_id = 0; byte_id < data_width_in_bytes_lp; byte_id++) begin
if (write_valid & w_mask_i[byte_id])
bsg_mem_dma_set(memory, write_byte_addr+byte_id, mem_data_li[byte_id*8+:8]);
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma)
|
#include <bits/stdc++.h> using namespace std; long long int ar[500009], br[500009], cr[500009], tr[500009]; long long int fx[] = {-1, 1, 0, 0}; long long int fy[] = {0, 0, 1, -1}; map<long long int, long long int> mp; vector<long long int> v; string s; struct evan { long long int l, r, pos; } st[500009]; bool com(evan i1, evan i2) { return (i1.r < i2.r); } int main() { long long int a, b, c, d, e, i, j, k, x, y, z, f, g, h, n, m; cin >> a; while (a--) { cin >> b; c = b / 4; j = (b * 4) - b; b -= c; for (i = 1; i < b; i++) { cout << 9 ; } if (j % 4) cout << 8 ; else { cout << 9 ; } for (i = 1; i <= c; i++) { cout << 8 ; } cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; unsigned long long bt[maxn]; unsigned long long d[maxn]; map<unsigned long long, int> has; pair<int, int> edg[maxn]; int f[maxn]; int id[maxn]; int lab[maxn]; vector<int> e[maxn]; int vis[maxn]; int getf(int x) { if (x == f[x]) return x; else return f[x] = getf(f[x]); } void dfs(int x, int y, int de) { int i; lab[x] = de; vis[x] = 1; for (i = 0; i < (int)e[x].size(); i++) { if (e[x][i] == y) continue; dfs(e[x][i], x, de + 1); } } int main() { int i, j, n, m; cin >> n >> m; int x, y; bt[0] = 1; for (int i = 1; i <= n; i++) { bt[i] = 3 * bt[i - 1]; d[i] = bt[i]; } for (i = 0; i < m; i++) { scanf( %d%d , &x, &y); edg[i] = make_pair(x, y); d[x] += bt[y], d[y] += bt[x]; } j = 1; for (i = 1; i <= n; i++) { if (!has[d[i]]) has[d[i]] = j++; id[i] = has[d[i]]; f[i] = i; } for (i = 0; i < m; i++) { x = id[edg[i].first], y = id[edg[i].second]; if (x == y) continue; for (j = 0; j < (int)e[x].size(); j++) { if (e[x][j] == y) break; } if (j >= 2) { printf( NO n ); return 0; } if (j == (int)e[x].size()) e[x].push_back(y); else continue; for (j = 0; j < (int)e[y].size(); j++) { if (e[y][j] == x) break; } if (j >= 2) { printf( NO n ); return 0; } if (j == (int)e[y].size()) e[y].push_back(x); else continue; if (getf(x) == getf(y)) { printf( NO n ); return 0; } else f[getf(y)] = f[getf(x)]; } int cnt = 0; for (i = 1; i <= n; i++) { if (vis[id[i]] == 0 && (int)e[id[i]].size() < 2) { vis[id[i]] = 1; dfs(id[i], -1, 1); } } printf( YES n ); for (i = 1; i <= n; i++) printf(i == n ? %d n : %d , lab[id[i]]); }
|
#include <bits/stdc++.h> using namespace std; long long v[3], l, ans, minusVal; long long accSum(long long limit) { return (limit + 1LL) * (limit + 2LL) / 2LL; } long long invalidCase(long long a, long long b, long long c) { long long ret = 0LL; for (long long i = 0LL; i <= l; i++) { long long val = min(c - a - b + i, l - i); if (val >= 0LL) ret += accSum(val); } return ret; } int main() { scanf( %lld %lld %lld %lld , &v[0], &v[1], &v[2], &l); ans = (l + 1LL) * (l + 2LL) * (l + 3LL) / 6LL; ans -= invalidCase(v[2], v[1], v[0]); ans -= invalidCase(v[0], v[2], v[1]); ans -= invalidCase(v[0], v[1], v[2]); printf( %lld n , ans); return 0; }
|
module peripheral_audio(clk , rst , d_in , cs , addr, d_out, mclk, ledres, micLRSel,micData,full,empty );
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
output [15:0]d_out;
output ledres;
output mclk;
output micLRSel;
input micData;
output full;
output empty;
//------------------------------------ regs and wires-------------------------------
reg [2:0] s; //selector mux_4 and demux_4
//------------------------------------ regs and wires-------------------------------
microfono tx(.reset(rst), .clk(clk), .micLRSel(micLRSel),.empty(empty) .mclk(mclk),.micData(micData),.ledres(ledres),.empty(empty));
always @(*) begin//----address_decoder------------------
case (addr)
4'h0:begin s = (cs && wr) ? 3'b001 : 3'b000 ;end //enable
4'h2:begin s = (cs && rd) ? 3'b010 : 3'b000 ;end //full
4'h4:begin s = (cs && rd) ? 3'b100 : 3'b000 ;end //empty
default:begin s=3'b000 ; end
endcase
end//-----------------address_decoder--------------------
always @(negedge clk) begin//-------------------- escritura de registros
d_in= (s[0]) ? enable : d_in; // data enable
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
3'b010: d_out[0]= full;
3'b100: d_out[7:0]= empty;
default: d_out=0;
endcase
end//----------------------------------------------mux_4
//(addr != 4'h4): se hace para evitar escrituras fantasm
endmodule
|
// nios_system_nios2_qsys_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2016.05.03.15:20:15
`timescale 1 ps / 1 ps
module nios_system_nios2_qsys_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [18:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [18:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
nios_system_nios2_qsys_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int fir = 0; char s[1100000]; int check() { for (int i = 0; s[i]; i++) { if (s[i] == ) continue; if (s[i] == # ) return 1; else return 0; } return 0; } int main() { while (gets(s)) { if (check()) { if (fir) putchar( n ); puts(s); fir = 0; } else { for (int i = 0; s[i]; i++) { if (s[i] == ) continue; putchar(s[i]); } fir = 1; } } if (fir) putchar( n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A31O_PP_SYMBOL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a31o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_PP_SYMBOL_V
|
module logic_analyzer # (
parameter CAPTURE_WIDTH = 32,
parameter CAPTURE_DEPTH = 10
) (
input clk,
input rst,
input i_cap_clk,
input i_cap_ext_trig,
input [31:0] i_cap_data,
input [31:0] i_trigger,
input [31:0] i_trigger_mask,
input [31:0] i_trigger_after,
input [31:0] i_trigger_edge,
input [31:0] i_both_edges,
input [31:0] i_repeat_count,
input i_force_stb,
input i_enable,
input i_restart,
output reg [31:0] o_capture_start,
output reg o_finished = 0,
output [31:0] o_capture_size,
input [31:0] i_bram_addr,
output [CAPTURE_WIDTH - 1:0] o_bram_data
);
//Local Parameter
localparam CAPTURE_SIZE = (1 << CAPTURE_DEPTH);
localparam IDLE = 0;
localparam SETUP = 1;
localparam CONT_READ = 2;
localparam CAPTURE = 3;
localparam FINISHED = 4;
//Registers/Wires
reg [3:0] state;
reg [CAPTURE_DEPTH - 1: 0] r_in_pointer;
reg [CAPTURE_DEPTH - 1: 0] r_out_pointer;
reg [CAPTURE_DEPTH - 1: 0] r_start;
wire [CAPTURE_DEPTH - 1: 0] w_last;
wire w_full;
reg r_cap_wr_stb;
reg r_start_stb;
reg r_pos_start_stb;
reg r_neg_start_stb;
reg [31:0] r_repeat_count;
reg [31:0] r_prev_cap;
wire [31:0] w_cap_pos_edge;
wire [31:0] w_cap_neg_edge;
wire [31:0] w_cap_sig_start;
wire w_cap_start;
wire [31:0] w_inv_cap_data;
wire [31:0] w_inv_cap_prev_data;
//Submodules
dpb #(
.DATA_WIDTH (CAPTURE_WIDTH ),
.ADDR_WIDTH (CAPTURE_DEPTH )
) local_buffer (
.clka (i_cap_clk ),
.wea (r_cap_wr_stb ),
.addra (r_in_pointer ),
.dina (r_prev_cap ),
.clkb (clk ),
.web (1'b0 ),
.addrb (i_bram_addr[CAPTURE_DEPTH - 1:0] ),
.dinb (32'h0 ),
.doutb (o_bram_data )
);
//Asynchronous Logic
assign o_capture_size = CAPTURE_SIZE;
assign w_last = r_start + ((CAPTURE_SIZE - 1) - i_trigger_after);
assign w_full = r_in_pointer == w_last;
assign w_cap_start = (w_cap_sig_start == 32'hFFFFFFFF);
assign w_inv_cap_data = ~i_cap_data;
assign w_inv_cap_prev_data = ~r_prev_cap;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : la
assign w_cap_pos_edge[i] = i_cap_data[i] & ~r_prev_cap[i];
assign w_cap_neg_edge[i] = ~i_cap_data[i] & r_prev_cap[i];
assign w_cap_sig_start[i] =
(~i_trigger_mask[i]) ? 1 : //If the mask is 0 then this is true
i_trigger_edge[i] ? //Look For Edge
(i_both_edges[i] & (w_cap_pos_edge[i] | w_cap_neg_edge[i])) | //Both Edges
(i_trigger[i] & w_cap_pos_edge[i]) | (~i_trigger[i] & w_cap_neg_edge[i]) : //Pos/Neg Edge
(i_trigger[i] & i_cap_data[i]) | (~i_trigger[i] & ~i_cap_data[i]);//Not edge but level and data
end
endgenerate
//Synchronous Logic
always @ (posedge i_cap_clk) begin
r_cap_wr_stb <= 0;
if (rst) begin
r_in_pointer <= 0;
r_start <= 0;
o_capture_start <= 0;
r_repeat_count <= 0;
r_prev_cap <= 32'h0;
state <= IDLE;
o_finished <= 0;
end
else begin
r_prev_cap <= i_cap_data;
case (state)
IDLE: begin
o_capture_start <= 0;
r_in_pointer <= 0;
r_repeat_count <= 0;
r_start <= 0;
if (i_enable) begin
if ((i_trigger_after > 0) || (i_repeat_count > 0)) begin
//Special Case, need to continue reading data, we have a history
state <= CONT_READ;
end
else if(w_cap_start || i_cap_ext_trig) begin
r_cap_wr_stb <= 1;
state <= CAPTURE;
end
end
if (i_force_stb) begin
state <= CAPTURE;
end
end
CONT_READ: begin
r_cap_wr_stb <= 1;
r_start <= r_start + 1;
r_in_pointer <= r_start + 1;
if (w_cap_start) begin
if (r_repeat_count < i_repeat_count) begin
r_repeat_count <= r_repeat_count + 1;
end
else begin
state <= CAPTURE;
end
end
end
CAPTURE: begin
if (w_full) begin
state <= FINISHED;
if (r_start < i_trigger_after) begin
//Wrap around case
o_capture_start <= (CAPTURE_SIZE - 1) + r_start - i_trigger_after;
end
else begin
o_capture_start <= r_start - i_trigger_after;
end
end
else begin
r_cap_wr_stb <= 1;
r_in_pointer <= r_in_pointer + 1;
end
end
FINISHED: begin
o_finished <= 1;
if (!i_enable) begin
o_finished <= 0;
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_vdivops(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input signed [17:0] cx,
input signed [17:0] cy,
input signed [17:0] dx,
input signed [17:0] dy,
input signed [11:0] drx,
input signed [11:0] dry,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [17:0] ax_f,
output reg signed [17:0] ay_f,
output reg signed [17:0] bx_f,
output reg signed [17:0] by_f,
output reg diff_cx_positive,
output reg [16:0] diff_cx,
output reg diff_cy_positive,
output reg [16:0] diff_cy,
output reg diff_dx_positive,
output reg [16:0] diff_dx,
output reg diff_dy_positive,
output reg [16:0] diff_dy,
output reg signed [11:0] drx_f,
output reg signed [11:0] dry_f
);
always @(posedge sys_clk) begin
if(sys_rst)
pipe_stb_o <= 1'b0;
else begin
if(pipe_ack_i)
pipe_stb_o <= 1'b0;
if(pipe_stb_i & pipe_ack_o) begin
pipe_stb_o <= 1'b1;
if(cx > ax) begin
diff_cx_positive <= 1'b1;
diff_cx <= cx - ax;
end else begin
diff_cx_positive <= 1'b0;
diff_cx <= ax - cx;
end
if(cy > ay) begin
diff_cy_positive <= 1'b1;
diff_cy <= cy - ay;
end else begin
diff_cy_positive <= 1'b0;
diff_cy <= ay - cy;
end
if(dx > bx) begin
diff_dx_positive <= 1'b1;
diff_dx <= dx - bx;
end else begin
diff_dx_positive <= 1'b0;
diff_dx <= bx - dx;
end
if(dy > by) begin
diff_dy_positive <= 1'b1;
diff_dy <= dy - by;
end else begin
diff_dy_positive <= 1'b0;
diff_dy <= by - dy;
end
ax_f <= ax;
ay_f <= ay;
bx_f <= bx;
by_f <= by;
drx_f <= drx;
dry_f <= dry;
end
end
end
assign pipe_ack_o = ~pipe_stb_o | pipe_ack_i;
assign busy = pipe_stb_o;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-9; const long long MOD = 1e9 + 7; const int N = 2e6 + 10; const long double pi = 3.1415926535897932384650288; int n, m; string s, t; bool ok(int i, int j, int d) { if (j == m) return 1; if (i == n) return 0; if (i < 0) return 0; if (s[i] != t[j]) return 0; if (d) { return ok(i - 1, j + 1, d); } return ok(i + 1, j + 1, d) || ok(i - 1, j + 1, 1); } void solve() { cin >> s >> t; n = s.size(); m = t.size(); for (int i = 0; i < n; i++) { if (ok(i, 0, 0)) { puts( Yes ); return; } } puts( No ); } int main() { int t = 1; scanf( %d , &t); while (t--) { solve(); } }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:15:12 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_1_stub.v
// Design : bram_1024_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[9:0],dina[19:0],douta[19:0]" */;
input clka;
input ena;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a; cin >> a; string s; cin >> s; int x = 0; for (int i = 0; i < a - 1; i++) { if (s[i] > s[i + 1]) { cout << YES << endl; cout << i + 1 << << i + 2; return 0; } } cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; double p, f[220][220]; int x, k; int main() { scanf( %d%d%lf , &x, &k, &p); p /= 100; for (int i = 0; i <= k; i++) for (int j = x + i; j % 2 == 0; j /= 2) f[0][i]++; for (int i = 0; i < k; i++) { for (int j = 0; j <= k; j++) { if (j) f[i + 1][j - 1] += (1 - p) * f[i][j]; if (j * 2 <= k) f[i + 1][j * 2] += p * (f[i][j] + 1); } } printf( %.10lf n , f[k][0]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, A[200010], L[200010], R[200010], ans = 1; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &A[i]); L[i] = R[i] = 1; } for (int i = 2; i <= n; i++) { if (A[i - 1] < A[i]) L[i] = L[i - 1] + 1; ans = max(ans, L[i]); } for (int i = n - 1; i >= 1; i--) { if (A[i] < A[i + 1]) R[i] = R[i + 1] + 1; ans = max(ans, R[i]); } for (int i = 1; i <= n - 2; i++) { if (A[i] < A[i + 2]) ans = max(ans, L[i] + R[i + 2]); } printf( %d , ans); return 0; }
|
#include<bits/stdc++.h> #define rep(i,a,b) for(int i=(a);i<(b);++i) #define per(i,a,b) for(int i=(b)-1;i>=(a);--i) #define ll long long #define lb(x) ((x)&-(x)) #define pii pair<int,int> #define vi vector<int> #define pb push_back #define fi first #define se second #define de(x) cout<<#x<< x <<endl #define LCAFA rep(i,1,20)rep(j,1,n+1)fa[j][i]=fa[fa[j][i-1]][i-1] #define all(x) x.begin(),x.end() #define ls(x) x<<1 #define rs(x) x<<1|1 #define pr(x) {for(auto v:x)cout<<v<< ;cout<<#x<<endl;} using namespace std; const int N=3e4+9; const ll mod=998244353; const ll Inf=1e18; /* inline int add(int a,const int &b){ a+=b; if(a>=mod)a-=mod; return a; } inline int sub(int a,const int &b){ a-=b; if(a<0)a+=mod; return a; } inline int mul(const int &a,const int &b){return 1ll*a*b%mod;} int jie[N],inv[N]; ll quick(ll a,ll b){ ll res=1; while(b){ if(b&1)res=res*a%mod; a=a*a%mod; b>>=1; } return res; } inline int C(int m,int n){ if(n>m||m<0||n<0)return 0; return mul(mul(jie[m],inv[n]),inv[m-n]); } void pre(){ inv[0]=inv[1]=1,jie[0]=1; rep(i,2,N)inv[i]=-1ll*mod/i*inv[mod%i]%mod+mod; rep(i,1,N)inv[i]=mul(inv[i],inv[i-1]),jie[i]=mul(jie[i-1],i); } */ ll dp[N][5]; int p[N]; vi s[N]; ll L[N][5][16],R[N][5][16]; int main(){ //pre(); int T; scanf( %d ,&T); while(T--){ int n,c,q; scanf( %d%d%d ,&n,&c,&q); rep(i,0,n)scanf( %d ,&p[i]); rep(i,0,c+1)dp[n][i]=1; per(i,0,n){ rep(j,0,c+1){ dp[i][j]=0; rep(k,0,j+1){ if(i+k<n)dp[i][j]+=dp[i+k+1][j-k]; } } } rep(i,0,n){ s[i].clear(); rep(j,0,c+1){ if(i+j<n)s[i].pb(j); } sort(all(s[i]),[&](int a,int b){return p[i+a]<p[i+b];}); } int lim=0; while((1<<lim)<n)++lim; rep(i,0,n)rep(j,0,c+1)rep(k,0,lim+1)L[i][j][k]=R[i][j][k]=0; per(i,0,n){ rep(j,0,c+1){ if(i+j>=n)break; ll sum=0; for(auto v:s[i]){ if(v>j)continue; if(v==0)break; sum+=dp[i+v+1][j-v]; } L[i][j][0]=sum; R[i][j][0]=sum+dp[i+1][j]; rep(k,1,lim+1){ if(i+(1<<k)<=n){ L[i][j][k]=L[i][j][k-1]+L[i+(1<<k-1)][j][k-1]; R[i][j][k]=L[i][j][k-1]+R[i+(1<<k-1)][j][k-1]; } } } } while(q--){ int pos; ll id; scanf( %d%lld ,&pos,&id); if(id>dp[0][c]){ puts( -1 ); continue; } --pos; --id; int i=0,ans=p[pos],r=c; // cout<<ans<< ans n ; int cnt=0; while(i<n){ ++cnt; if(cnt>6)return 0; for(int j=lim;j>=0;--j){ if(i+(1<<j)<=n&&L[i][r][j]<=id&&id<R[i][r][j]){ id-=L[i][r][j]; i+=1<<j; } } if(i==n)break; // cout<<cnt<< <<i<< <<r<< <<id<< i n ; for(auto v:s[i]){ if(v>r)continue; if(id>=dp[i+v+1][r-v]){ id-=dp[i+v+1][r-v]; } else{ // cout<<v<< v n ; int i1=i+v; r-=v; if(i<=pos&&pos<=i1){ ans=p[i+i1-pos]; } i=i1+1; break; } } } printf( %d n ,ans); } } } /* 1 3 1 1 1 2 3 2 1 1 6 4 1 6 5 4 3 1 2 3 14 1 20 4 1 16 5 15 14 13 3 17 18 2 20 19 6 4 1 12 8 11 10 9 7 8 1100 */
|
#include <bits/stdc++.h> using namespace std; long long sq(long long k) { return k * k; } long long knan(long long k, long long n) { if (n == 1) return k; else if (n == 0) return 1; else { if (n % 2 == 0) return sq(knan(k, n / 2)) % 1000000007; else return (k * knan(k, n - 1)) % 1000000007; } } int main() { string s; int p[4], n; for (int i = 0; i < 4; i++) p[i] = 0; cin >> n; cin >> s; for (int i = 0; i < s.length(); i++) { if (s[i] == A ) p[0]++; if (s[i] == T ) p[1]++; if (s[i] == C ) p[2]++; if (s[i] == G ) p[3]++; } int max(0), brmax(0); for (int i = 0; i < 4; i++) if (p[i] > max) max = p[i]; for (int i = 0; i < 4; i++) if (p[i] == max) brmax++; cout << knan(brmax, n) % 1000000007 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; vector<char> v; int main() { ios_base::sync_with_stdio(false); getline(cin, s); int cnt = 0; bool mark; for (int i = 0; i < s.size(); i++) { if (s[i] == ) cnt++; else { v.push_back(s[i]); if (s[i] != ) mark = true; } if (mark == true && (i == s.size() - 1 || (s[i] == && s[i + 1] != )) && ((cnt != 1 || s[i] == ) && cnt != 2)) { mark = false; string t = ; for (int i = 0; i < v.size(); i++) if (v[i] != ) t += v[i]; v.clear(); cout << < << t << > << endl; } if (cnt == 2) { cnt = 0; string t = ; for (int i = 0; i < v.size(); i++) t += v[i]; v.clear(); mark = false; cout << < << t << > << endl; } if (cnt == 1 && s[i] == ) v.clear(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; inline long long quick(long long mul, long long b) { long long c = 1; while (b) { if (b & 1) { c = c * mul % mod; } mul = mul * mul % mod; b /= 2; } return c; } int main() { long long n, m; cin >> n >> m; cout << (quick(2 * n + 2, m) * (n - m + 1) % mod) * quick(n + 1, mod - 2) % mod; return 0; }
|
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