text
stringlengths 59
71.4k
|
|---|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_TB_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_TB_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busdrivernovlpsleep.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg SLEEP;
reg VPWR;
reg VGND;
reg KAPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
SLEEP = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 SLEEP = 1'b0;
#80 TE_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 KAPWR = 1'b1;
#220 SLEEP = 1'b1;
#240 TE_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 KAPWR = 1'b0;
#380 SLEEP = 1'b0;
#400 TE_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 TE_B = 1'b1;
#600 SLEEP = 1'b1;
#620 KAPWR = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 TE_B = 1'bx;
#760 SLEEP = 1'bx;
#780 KAPWR = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_lp__busdrivernovlpsleep dut (.A(A), .TE_B(TE_B), .SLEEP(SLEEP), .VPWR(VPWR), .VGND(VGND), .KAPWR(KAPWR), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_TB_V
|
#define _USE_MATH_DEFINES #include <bits/stdc++.h> using namespace std; //template #define rep(i,a,b) for(int i=(int)(a);i<(int)(b);i++) #define ALL(v) (v).begin(),(v).end() using ll=long long int; const int inf = 0x3fffffff; const ll INF = 0x1fffffffffffffff; const double eps=1e-12; template<typename T>inline bool chmax(T& a,T b){if(a<b){a=b;return 1;}return 0;} template<typename T>inline bool chmin(T& a,T b){if(a>b){a=b;return 1;}return 0;} //end void solve(int _rot){ // printf( Case #%d: ,_rot); int n; cin>>n; string s[3]; rep(i,0,3)cin>>s[i]; rep(_,0,3){ string S=s[_],T=s[(_+1)%3]; string res; int S0=0,T0=0; rep(i,0,n*2)if(S[i]== 0 )S0++; rep(i,0,n*2)if(T[i]== 0 )T0++; if((S0>n) and (T0<n))continue; if((S0<n) and (T0>n))continue; char mx; if(S0>=n and T0>=n)mx= 0 ; if(S0<=n and T0<=n)mx= 1 ; int i1=0,i2=0; for(;;){ int c1=0,c2=0; while(i1<n*2 and S[i1]!=mx){ i1++; c1++; } while(i2<n*2 and T[i2]!=mx){ i2++; c2++; } res+=string(max(c1,c2),mx^ 0 ^ 1 ); res+=mx; i1=min(i1+1,n*2); i2=min(i2+1,n*2); if(i1==n*2 and i2==n*2)break; } while(res.size()>n*3)res.pop_back(); while(res.size()<n*3)res+= 0 ; cout<<res<< n ; return; } } int main(){ int t; scanf( %d ,&t); rep(rot,0,t)solve(rot+1); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/23/2015 05:17:53 PM
// Design Name:
// Module Name: testcase_basic
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "packet_type.vh"
`include "system.vh"
module testcase_basic();
localparam X_LOCAL = 2;
localparam Y_LOCAL = 2;
localparam xpos_packets = 7600;
localparam ypos_packets = 8600;
localparam xneg_packets = 9600;
localparam yneg_packets = 10600;
reg xpos = 1'b0;
reg ypos = 1'b0;
reg xneg = 1'b0;
reg yneg = 1'b0;
reg pe = 1'b0;
harness harness();
// -- x+
always
harness.xpos_in_channel.receive_credit();
// -- y+
always
harness.ypos_in_channel.receive_credit();
// -- x-
always
harness.xneg_in_channel.receive_credit();
// -- y-
always
harness.yneg_in_channel.receive_credit();
packet_generator
#(
.port(`X_POS),
.pe_percent(3),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
xpos_gen();
initial
begin: xpos_injector
integer index;
@(negedge harness.reset);
for (index = 0; index < xpos_packets; index = index + 1)
begin
@(posedge harness.clk)
#(harness.Thold)
xpos_gen.random_packet(index);
harness.xpos_in_channel.send_packet(xpos_gen.packet);
end
xpos = 1'b1;
end
packet_generator
#(
.port(`X_NEG),
.pe_percent(5),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
xneg_gen();
initial
begin: xneg_injector
integer index;
@(negedge harness.reset);
for (index = 0; index < xneg_packets; index = index + 1)
begin
@(posedge harness.clk)
#(harness.Thold)
xneg_gen.random_packet(index);
harness.xneg_in_channel.send_packet(xneg_gen.packet);
end
xneg = 1'b1;
end
packet_generator
#(
.port(`Y_POS),
.pe_percent(4),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
ypos_gen();
initial
begin: ypos_injector
integer index;
@(negedge harness.reset);
for (index = 0; index < ypos_packets; index = index + 1)
begin
@(posedge harness.clk)
#(harness.Thold)
ypos_gen.random_packet(index);
harness.ypos_in_channel.send_packet(ypos_gen.packet);
end
ypos = 1'b1;
end
packet_generator
#(
.port(`Y_NEG),
.pe_percent(8),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
yneg_gen();
initial
begin: yneg_injector
integer index;
@(negedge harness.reset);
//harness.yneg_in_channel.send_packet({"DAT4", "DAT3", "DAT2", "DAT1", {2'b10, 3'd2, 3'd4, "Y--"}});
for (index = 0; index < yneg_packets; index = index + 1)
begin
@(posedge harness.clk)
#(harness.Thold)
yneg_gen.random_packet(index);
harness.yneg_in_channel.send_packet(yneg_gen.packet);
end
yneg = 1'b1;
end
initial
begin : ciclo_principal
integer total_envio;
integer total_recepcion;
harness.sync_reset();
//repeat(120)
// @(negedge harness.clk);
@(xpos & ypos & xneg & yneg)
repeat(100)
@(negedge harness.clk);
total_envio = harness.xpos_in_channel.packet_count +
harness.xneg_in_channel.packet_count +
harness.ypos_in_channel.packet_count +
harness.yneg_in_channel.packet_count;
total_recepcion = harness.xpos_out_channel.packet_count +
harness.xneg_out_channel.packet_count +
harness.ypos_out_channel.packet_count +
harness.yneg_out_channel.packet_count;
$display("",);
$display("",);
$display("",);
$display("|| -- PAQUETES ENVIADOS ---------------- >>>>>",);
$display("",);
$display("Paquetes enviados por x+: ", harness.xpos_in_channel.packet_count);
$display("Paquetes enviados por x-: ", harness.xneg_in_channel.packet_count);
$display("Paquetes enviados por y+: ", harness.ypos_in_channel.packet_count);
$display("Paquetes enviados por y-: ", harness.yneg_in_channel.packet_count);
$display("",);
$display("Total de paquetes enviados'testcase': ", total_envio);
$display("",);
$display("|| -- PAQUETES RECIBIDOS --------------- >>>>>",);
$display("",);
$display("Paquetes recibidos por x+: ", harness.xpos_out_channel.packet_count);
$display("Paquetes recibidos por x-: ", harness.xneg_out_channel.packet_count);
$display("Paquetes recibidos por y+: ", harness.ypos_out_channel.packet_count);
$display("Paquetes recibidos por y-: ", harness.yneg_out_channel.packet_count);
$display("",);
$display("Total de paquetes recibidos'testcase': ", total_recepcion);
$display("",);
$display("|| -- TOTALES -------------------------- >>>>>",);
$display("",);
$display("",);
if(total_envio == total_recepcion)
$display("prueba satisfactoria",);
else
$display("prueba no satisfactoria",);
$display("",);
$display("",);
$display("",);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211A_1_V
`define SKY130_FD_SC_MS__O211A_1_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211a_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211A_1_V
|
#include <bits/stdc++.h> using namespace std; int N, M, P, Q; int A[101], B[101]; int w[202][202]; bool V[202]; vector<int> path; bool dfs(int n) { path.push_back(n); V[n] = 1; if (n == N + N + 1) return 1; for (int i = 0; i <= N + N + 1; i++) if (!V[i] && w[n][i]) { if (dfs(i)) return 1; } path.pop_back(); return 0; } int main() { ios_base::sync_with_stdio(false); cin >> N >> M; for (int i = 1; i <= N; i++) cin >> A[i], w[0][i] = A[i], P += A[i]; for (int i = 1; i <= N; i++) cin >> B[i], w[N + i][N + N + 1] = B[i], Q += B[i]; for (int i = 1; i <= N; i++) w[i][N + i] = 1e9; for (int i = 1; i <= M; i++) { int a, b; cin >> a >> b; w[a][N + b] = 1e9; w[b][N + a] = 1e9; } int ans = 0; while (dfs(0)) { int flow = 2e9; for (int i = 1; i < ((int)(path).size()); i++) flow = min(flow, w[path[i - 1]][path[i]]); for (int i = 1; i < ((int)(path).size()); i++) { w[path[i - 1]][path[i]] -= flow; w[path[i]][path[i - 1]] += flow; } ans += flow; path.clear(); for (int i = 0; i <= N + N + 1; i++) V[i] = 0; } if (P != Q || ans != P) { puts( NO ); return 0; } puts( YES ); for (int i = 1; i <= N; i++, puts( )) for (int j = 1; j <= N; j++) { printf( %d , w[N + j][i]); } }
|
// Copyright (c) 2000-2011 Bluespec, Inc.
// Copyright (c) 2013 Jonathan Woodruff
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29754 $
// $Date: 2012-10-22 13:58:07 +0000 (Mon, 22 Oct 2012) $
// Modified by Jonathan Woodruff 19/7/2013:
// Removed reference to CLKB
// Removed writing to interface A
// Removed reading from interface B
// (To allow inferring by Quartus)
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Dual-Ported BRAM (WRITE FIRST)
module BRAM2Load(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter FILENAME = "";
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
parameter BINARY = 0;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R2;
// synopsys translate_off
initial
begin : init_block
`ifdef BSV_NO_INITIAL_BLOCKS
`else
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
end
// synopsys translate_on
initial
begin : init_rom_block
if (BINARY)
$readmemb(FILENAME, RAM, 0, MEMSIZE-1);
else
$readmemh(FILENAME, RAM, 0, MEMSIZE-1);
end
always @(posedge CLKA) begin
if (ENA) begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end
always @(posedge CLKA) begin
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
end
end
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end
// Output drivers
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
endmodule // BRAM2Load
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: FIFO_DETECTION_TIME.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module FIFO_DETECTION_TIME (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [13:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [13:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "8"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "14"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "14"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "14"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "3"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 14 0 INPUT NODEFVAL "data[13..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 14 0 OUTPUT NODEFVAL "q[13..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 14 0 data 0 0 14 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 14 0 @q 0 0 14 0
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_TIME.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_TIME.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_TIME.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_TIME.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_TIME_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_TIME_bb.v TRUE
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_pcie_brams_7x.v
// Version : 3.0
// Description : pcie bram wrapper
// arrange and connect brams
// implement address decoding, datapath muxing and pipeline stages
//
// banks of brams are used for 1,2,4,8,18 brams
// brams are stacked for other values of NUM_BRAMS
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_pcie_brams_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
// the number of BRAMs to use
// supported values are:
// 1,2,4,8,18
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1,
parameter TCQ = 1 // synthesis warning removed: parameter declaration becomes local
)
(
input user_clk_i,
input reset_i,
input wen,
input [12:0] waddr,
input [71:0] wdata,
input ren,
input rce,
input [12:0] raddr,
output [71:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :
(NUM_BRAMS == 2) ? 36 :
(NUM_BRAMS == 4) ? 18 :
(NUM_BRAMS == 8) ? 9 :
4
);
// parameter TCQ = 1;
wire wen_int;
wire [12:0] waddr_int;
wire [71:0] wdata_int;
wire ren_int;
wire [12:0] raddr_int;
wire [71:0] rdata_int;
//synthesis translate_off
initial
begin
$display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
$time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);
case (NUM_BRAMS)
1,2,4,8,18:;
default:
begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_q;
reg [12:0] waddr_q;
reg [71:0] wdata_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
wen_q <= #TCQ 1'b0;
waddr_q <= #TCQ 13'b0;
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
// wdata_q <= #TCQ 72'b0;
end
else
begin
wen_q <= #TCQ wen;
waddr_q <= #TCQ waddr;
wdata_q <= #TCQ wdata;
end
end
assign wen_int = wen_q;
assign waddr_int = waddr_q;
assign wdata_int = wdata_q;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_q;
reg [12:0] raddr_q;
always @(posedge user_clk_i) begin
if (reset_i)
begin
ren_q <= #TCQ 1'b0;
raddr_q <= #TCQ 13'b0;
end
else
begin
ren_q <= #TCQ ren;
raddr_q <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_q;
assign raddr_int = raddr_q;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [71:0] rdata_q;
always @(posedge user_clk_i) begin
// Disable Reset on Data Path @ BRAM i/f as I/O come from PCIe HB.
//if (reset_i)
//begin
// rdata_q <= #TCQ 72'b0;
//end
//else
//begin
rdata_q <= #TCQ rdata_int;
//end // else: !if(reset_i)
end
assign rdata = rdata_q;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
genvar ii;
for (ii = 0; ii < NUM_BRAMS; ii = ii + 1) begin : brams
pcie_7x_0_core_top_pcie_bram_7x #(
.LINK_CAP_MAX_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.IMPL_TARGET (IMPL_TARGET),
.DOB_REG (DOB_REG),
.WIDTH (WIDTH)
)
ram (
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.wen_i(wen_int),
.waddr_i(waddr_int),
.wdata_i(wdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.ren_i(ren_int),
.raddr_i(raddr_int),
.rdata_o(rdata_int[(((ii + 1) * WIDTH) - 1): (ii * WIDTH)]),
.rce_i(rce)
);
end
endgenerate
endmodule // pcie_brams_7x
|
#include <bits/stdc++.h> using namespace std; int n, m, a[110], s[110][110]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); for (int j = 1; j <= a[i]; j++) s[i][j % m + 1]++; } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) for (int k = 1; k <= m; k++) if (abs(s[i][k] - s[j][k]) > 1) { printf( NO n ); return 0; } printf( YES n ); for (int i = 1; i <= n; i++) { for (int j = 1; j <= a[i]; j++) printf( %d , j % m + 1); printf( n ); } return 0; }
|
/**
* A module for helping the processor handle loads
* and stores to and from main memory.
*
* @author Robert Fotino, 2016
*/
`include "definitions.vh"
module data_cache
(
input clk,
input boot_done,
// Interface for using the cache
input wr_en,
input [`ADDR_BITS-1:0] wr_addr,
input [`WORD_BITS-1:0] wr_data,
output wr_done,
input rd_en,
input [`ADDR_BITS-1:0] rd_addr,
output reg [`WORD_BITS-1:0] rd_data,
output rd_done,
// Signals for communicating with main memory
output reg mem_cmd_en,
output reg [2:0] mem_cmd_instr,
output reg [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_byte_addr,
input mem_cmd_empty,
input mem_cmd_full,
output reg mem_wr_en,
output reg [3:0] mem_wr_mask,
output reg [31:0] mem_wr_data,
input mem_wr_full,
input mem_wr_empty,
input [6:0] mem_wr_count,
input mem_wr_underrun,
input mem_wr_error,
output reg mem_rd_en,
input [31:0] mem_rd_data,
input mem_rd_full,
input mem_rd_empty,
input [6:0] mem_rd_count,
input mem_rd_overflow,
input mem_rd_error
);
initial begin
rd_data = 0;
mem_cmd_en = 0;
mem_wr_en = 0;
mem_rd_en = 0;
end
// State machine for accessing the RAM
localparam [2:0] STATE_PRE_BOOT = 0;
localparam [2:0] STATE_IDLE = 1;
localparam [2:0] STATE_WR_CMD = 2;
localparam [2:0] STATE_WR_WAIT = 3;
localparam [2:0] STATE_RD_WAIT = 4;
localparam [2:0] STATE_RD_EN = 5;
reg [2:0] state = 0;
wire mostly_done =
(STATE_IDLE == state) && !wr_en && !rd_en && !mem_cmd_full;
assign wr_done = mostly_done && !mem_wr_full;
assign rd_done = mostly_done && !mem_rd_full;
always @ (posedge clk) begin
mem_cmd_en <= 0;
mem_wr_en <= 0;
mem_rd_en <= 0;
case (state)
STATE_PRE_BOOT: begin
if (boot_done) begin
state <= STATE_IDLE;
end
end
STATE_IDLE: begin
if (wr_en) begin
// Set up command signals and write the data to the write FIFO
mem_cmd_instr <= 3'b000;
mem_cmd_bl <= 6'b000000;
mem_cmd_byte_addr <= { `MAIN_MEM_PREFIX, wr_addr };
mem_wr_en <= 1;
// We write only the upper or lower 16 bits
mem_wr_mask <= wr_addr[1] ? 4'b1100 : 4'b0011;
mem_wr_data <= {2{wr_data}};
state <= STATE_WR_CMD;
end else if (rd_en) begin
// Send the read command
mem_cmd_en <= 1;
mem_cmd_instr <= 3'b001;
mem_cmd_bl <= 6'b000000;
mem_cmd_byte_addr <= { `MAIN_MEM_PREFIX, rd_addr };
state <= STATE_RD_WAIT;
end
end
STATE_WR_CMD: begin
mem_cmd_en <= 1;
state <= STATE_IDLE;
end
STATE_RD_WAIT: begin
if (!mem_rd_empty) begin
mem_rd_en <= 1;
state <= STATE_RD_EN;
end
end
STATE_RD_EN: begin
// Only grab the upper or lower half, depending on the second
// to last address bit
rd_data <= mem_cmd_byte_addr[1] ?
mem_rd_data[15:0] :
mem_rd_data[31:16];
state <= STATE_IDLE;
end
endcase
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
parameter bitwidth = 16;
parameter zwidth = 16;
parameter shift = 1;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi,yi;
input [zwidth-1:0] zi;
input [zwidth-1:0] constant;
output [bitwidth-1:0] xo,yo;
output [zwidth-1:0] zo;
wire z_is_pos = ~zi[zwidth-1];
reg [bitwidth-1:0] xo,yo;
reg [zwidth-1:0] zo;
always @(posedge clock)
if(reset)
begin
xo <= #1 0;
yo <= #1 0;
zo <= #1 0;
end
else if(enable)
begin
xo <= #1 z_is_pos ?
xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
yo <= #1 z_is_pos ?
yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
zo <= #1 z_is_pos ?
zi - constant :
zi + constant;
end
endmodule
|
module MMCME2_ADV # (
parameter BANDWIDTH = "OPTIMIZED",
parameter real CLKFBOUT_MULT_F = 5.000,
parameter real CLKFBOUT_PHASE = 0.000,
parameter CLKFBOUT_USE_FINE_PS = "FALSE",
parameter real CLKIN1_PERIOD = 10.000,
parameter real CLKIN2_PERIOD = 0.000,
parameter real CLKOUT0_DIVIDE_F = 1.000,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter CLKOUT0_USE_FINE_PS = "FALSE",
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter CLKOUT1_USE_FINE_PS = "FALSE",
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter CLKOUT2_USE_FINE_PS = "FALSE",
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter CLKOUT3_USE_FINE_PS = "FALSE",
parameter CLKOUT4_CASCADE = "FALSE",
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter CLKOUT4_USE_FINE_PS = "FALSE",
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter CLKOUT5_USE_FINE_PS = "FALSE",
parameter integer CLKOUT6_DIVIDE = 1,
parameter real CLKOUT6_DUTY_CYCLE = 0.500,
parameter real CLKOUT6_PHASE = 0.000,
parameter CLKOUT6_USE_FINE_PS = "FALSE",
parameter COMPENSATION = "ZHOLD",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
parameter [0:0] IS_PSEN_INVERTED = 1'b0,
parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter real REF_JITTER2 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter integer SS_MOD_PERIOD = 10000,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT, //feedback clock to connect to CLKFBIN
output CLKFBOUTB, //inverted feedback clock output
output CLKFBSTOPPED, //indicates that FB clock as stoppped
output CLKINSTOPPED, //indicates that input clock has stopped
output CLKOUT0, //clock output
output CLKOUT0B, //inverted clock output
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output LOCKED, //indicates PLL is locked
output PSDONE, //phase shift done
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL, //selects between two input clocks,1=primary
output DRDY, //dynamic reconfig ready
input [6:0] DADDR, //Address port for dynamic reconfig
input DCLK, //clock port for dynamic reconfig
input DEN, //enable for dynamic reconfig
input [15:0] DI, //data for dynamic reconfig
input DWE, //dynamic reconfig write enable
output [15:0] DO, //readback data for dyanmic reconfig
input PSCLK, //phase shift clock
input PSEN, //phase shift enable
input PSINCDEC, //phase shift decrement/increment
input PWRDWN, //global power down pin
input RST //async global reset
);
//#LOCAL DERIVED PARAMETERS
localparam VCO_PERIOD = (CLKIN1_PERIOD * DIVCLK_DIVIDE) / CLKFBOUT_MULT_F;
localparam CLK0_DELAY = VCO_PERIOD * CLKOUT0_DIVIDE_F * (CLKOUT0_PHASE/360);
localparam CLK1_DELAY = VCO_PERIOD * CLKOUT1_DIVIDE * (CLKOUT1_PHASE/360);
localparam CLK2_DELAY = VCO_PERIOD * CLKOUT2_DIVIDE * (CLKOUT2_PHASE/360);
localparam CLK3_DELAY = VCO_PERIOD * CLKOUT3_DIVIDE * (CLKOUT3_PHASE/360);
localparam CLK4_DELAY = VCO_PERIOD * CLKOUT4_DIVIDE * (CLKOUT4_PHASE/360);
localparam CLK5_DELAY = VCO_PERIOD * CLKOUT5_DIVIDE * (CLKOUT5_PHASE/360);
localparam CLK6_DELAY = VCO_PERIOD * CLKOUT6_DIVIDE * (CLKOUT6_PHASE/360);
localparam phases = CLKFBOUT_MULT_F / DIVCLK_DIVIDE;
//########################################################################
//# CLOCK MULTIPLIER
//########################################################################
//
integer j;
reg [2*phases-1:0] delay;
always @ (CLKIN1)
begin
for(j=0; j<(2*phases); j=j+1)
delay[j] <= #(CLKIN1_PERIOD*j/(2*phases)) CLKIN1;
end
reg [(phases)-1:0] clk_comb;
always @ (delay)
begin
for(j=0; j<(phases); j=j+1)
clk_comb[j] <= delay[2*j] & ~delay[2*j+1];
end
reg vco_clk;
integer k;
always @*
begin
vco_clk = 1'b0;
for(k=0; k<(phases); k=k+1)
vco_clk = vco_clk | clk_comb[k];
end
//##############
//#DIVIDERS
//##############
wire [3:0] DIVCFG[6:0];
wire [6:0] CLKOUT_DIV;
assign DIVCFG[0] = $clog2(CLKOUT0_DIVIDE_F);
assign DIVCFG[1] = $clog2(CLKOUT1_DIVIDE);
assign DIVCFG[2] = $clog2(CLKOUT2_DIVIDE);
assign DIVCFG[3] = $clog2(CLKOUT3_DIVIDE);
assign DIVCFG[4] = $clog2(CLKOUT4_DIVIDE);
assign DIVCFG[5] = $clog2(CLKOUT5_DIVIDE);
assign DIVCFG[6] = $clog2(CLKOUT6_DIVIDE);
//ugly POR reset
reg POR;
initial
begin
POR=1'b1;
#1
POR=1'b0;
end
//BUG! This only supports divide by 2,4,8, etc for now
//TODO: This clearly won't work, need general purpose clock divider
//divide by 2-N (3,5,6,7 and all the other ugly numbers)
genvar i;
generate for(i=0; i<7; i=i+1)
begin : gen_clkdiv
clock_divider clkdiv (/*AUTOINST*/
// Outputs
.clkout (CLKOUT_DIV[i]),
// Inputs
.clkin (vco_clk),
.divcfg (DIVCFG[i]),
.reset (RST | POR));
end
endgenerate
//##############
//#PHASE DELAY
//##############
reg CLKOUT0;
reg CLKOUT1;
reg CLKOUT2;
reg CLKOUT3;
reg CLKOUT4;
reg CLKOUT5;
reg CLKOUT6;
always @ (CLKOUT_DIV)
begin
CLKOUT0 <= #(CLK0_DELAY) CLKOUT_DIV[0];
CLKOUT1 <= #(CLK1_DELAY) CLKOUT_DIV[1];
CLKOUT2 <= #(CLK2_DELAY) CLKOUT_DIV[2];
CLKOUT3 <= #(CLK3_DELAY) CLKOUT_DIV[3];
CLKOUT4 <= #(CLK4_DELAY) CLKOUT_DIV[4];
CLKOUT5 <= #(CLK5_DELAY) CLKOUT_DIV[5];
CLKOUT6 <= #(CLK6_DELAY) CLKOUT_DIV[6];
end
//##############
//#DUMMY DRIVES
//##############
assign CLKFBOUT=CLKIN1;
//###########################
//#SANITY CHECK LOCK COUNTER
//############################
parameter LCW=4;
reg [LCW-1:0] lock_counter;
wire reset = POR | RST;
always @ (posedge CLKIN1 or posedge reset)
if(reset)
lock_counter[LCW-1:0] <= {(LCW){1'b1}};
else if(~LOCKED)
lock_counter[LCW-1:0] <= lock_counter[LCW-1:0] - 1'b1;
assign LOCKED = ~(|lock_counter[LCW-1:0]);
endmodule // MMCME2_ADV
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_dp_macb_r.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_dp_macb_r(/*AUTOARG*/
// Outputs
data_out_cx_l, scan_out, shiftenable_buf,
// Inputs
arb_cpxdp_qsel1_ca, arb_cpxdp_qsel0_ca, arb_cpxdp_grant_ca,
arb_cpxdp_shift_cx, arb_cpxdp_q0_hold_ca, src_cpx_data_ca,
data_prev_cx_l, rclk, scan_in, shiftenable
);
output [149:0] data_out_cx_l; // cpx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_cpxdp_qsel1_ca; // queue write sel
input arb_cpxdp_qsel0_ca; // queue write sel
input arb_cpxdp_grant_ca;//grant signal
input arb_cpxdp_shift_cx;//grant signal
input arb_cpxdp_q0_hold_ca;//grant signal
input [149:0] src_cpx_data_ca; // scache to cpx data
input [149:0] data_prev_cx_l;
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_cx;
wire [149:0] q0_datain_ca;
wire [149:0] q1_dataout, q0_dataout;
wire [149:0] data_cx_l;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
/*
always @ (clk or arb_cpxdp_qsel1_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq1 = arb_cpxdp_qsel1_ca ;
end // always @ (clk or arb_cpxdp_qsel1_ca or tmb)
assign clkq1 = clkenq1 & clk;
always @ (clk or arb_cpxdp_q0_hold_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq0 = !arb_cpxdp_q0_hold_ca ;
end // always @ (clk or arb_cpxdp_q0_hold_ca or tmb)
assign clkq0 = clkenq0 & clk;
*/
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_cpxdp_q0_hold_ca),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_cpxdp_qsel1_ca),
.tmb_l(se_l));
dff_s #(1) dff_cpx_grin_r(
.din (arb_cpxdp_grant_ca),
.q (grant_cx),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(150) dff_cpx_datain_q1(
.din (src_cpx_data_ca[149:0]),
.q (q1_dataout[149:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
assign q0_datain_ca[149:0] =
(arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
(arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
dff_s #(150) dff_cpx_datain_q0(
.din (q0_datain_ca[149:0]),
.q (q0_dataout[149:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_cx_l[149:0] = ~(grant_cx ? q0_dataout[149:0] : 150'd0);
assign data_out_cx_l[149:0] = data_prev_cx_l[149:0] & data_cx_l[149:0];
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
// Code start here
//
endmodule
|
#include <bits/stdc++.h> using namespace std; long double PI = acosl(-1); bool compare_int(int a, int b) { return (a > b); } bool compare_string(string a, string b) { return a.size() < b.size(); } bool compare_pair(const pair<int, int> &a, const pair<int, int> &b) { if (a.second == b.second) return a.first < b.first; else return (a.second > b.second); } bool cmp(pair<string, int> x, pair<string, int> y) { return (x.second < y.second); } void NA() { printf( NO n ); exit(0); } void YA() { printf( YES n ); exit(0); } const int N = 300005; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, x, y, q; cin >> n; int sz = sqrt(n); long long int a[n + 1], tmp[n + 1]; for (int i = 0; i < n; i++) cin >> a[i]; cin >> q; vector<long long int> res(q); vector<pair<int, pair<int, int> > > v; for (int i = 0; i < q; i++) { cin >> x >> y; v.push_back({y, {x, i}}); } sort(v.begin(), v.end()); int pre = -1; for (int i = 0; i < q; i++) { x = v[i].second.first - 1; y = v[i].first; int id = v[i].second.second; if (y >= sz) { for (int i = x; i < n; i += y) res[id] += a[i]; } else { if (pre != y) { memset(tmp, 0, sizeof tmp); for (int i = n - 1; i >= 0; i--) { tmp[i] += a[i]; if (i + y < n) tmp[i] += tmp[i + y]; } pre = y; } res[id] = tmp[x]; } } for (int i = 0; i < q; i++) { cout << res[i] << endl; } }
|
module ovm;
class simple_item extends ovm_sequence_item;
rand int unsigned addr;
rand int unsigned data;
rand int unsigned delay;
constraint c1 { addr < 16'h2000; }
constraint c2 { data < 16'h1000; }
// OVM automation macros for general objects
`ovm_object_utils_begin(simple_item)
a = b;
c = d;
`ovm_field_int(addr, OVM_ALL_ON)
`ovm_field_int(data, OVM_ALL_ON)
`ovm_field_int(delay, OVM_ALL_ON)
`ovm_object_utils_end
// Constructor
function new (string name = "simple_item");
super.new(name);
endfunction : new
endclass : simple_item
class mydata extends ovm_object;
string str;
mydata subdata;
int field;
myenum e1;
int queue[$];
`ovm_object_utils(mydata)
`ovm_object_utils_begin(mydata) //requires ctor with default args
`ovm_field_string(str, OVM_DEFAULT)
`ovm_field_object(subdata, OVM_DEFAULT)
`ovm_field_int(field, OVM_DEC) //use decimal radix
`ovm_field_enum(myenum, e1, OVM_DEFAULT)
`ovm_field_queue_int(queue, OVM_DEFAULT)
`ovm_object_utils_end
`ovm_object_param_utils_begin(mydata) //requires ctor with default args
`ovm_field_string(str, OVM_DEFAULT)
`ovm_field_object(subdata, OVM_DEFAULT)
`ovm_field_int(field, OVM_DEC) //use decimal radix
`ovm_field_enum(myenum, e1, OVM_DEFAULT)
`ovm_field_queue_int(queue, OVM_DEFAULT)
`ovm_object_utils_end
endclass
class my_trans extends ovm_sequence_item;
rand bit [127:0] data [];
//---> Configuration
`ovm_object_utils_begin(my_trans)
`ovm_field_array_int ( data, OVM_ALL_ON)
`ovm_object_utils_end
function new (string name = "my_trans", ovm_sequencer_base sequencer = null, ovm_sequence parent_seq = null);
super.new(name, sequencer, parent_seq);
endfunction : new
endclass : my_trans
endmodule // ovm
module tt;
initial begin
while (1) begin
`ovm_do_with(aa, {bb == 0;})
`ovm_do(cc)
`ovm_do(cc)
end // while (1)
end // initial begin
endmodule // tt
|
#include <bits/stdc++.h> using namespace std; using namespace std; const long long mod = 1e9 + 7; const int inf = 1e9; string s; long long expMod(long long base, long long ex, long long mod) { if (ex == 0) return 1; long long temp = expMod(base, ex / 2, mod); temp = (temp * temp) % mod; if (ex % 2) temp = (temp * base) % mod; return temp; } long long solve(string x) { long long n = x.size(); if (n == 1) { if (x[0] == 1 ) return 1; else return 0; } string temp = x.substr(1); long long sz = temp.size(); long long ret = 0; if (x[0] == 0 ) { ret = (1LL * 2 * solve(temp)) % mod; } else { ret = (expMod(2, 2 * sz, mod) + 2 * solve(temp)) % mod; } return ret; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> s; cout << solve(s) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int n, x, y, b[N], cnt[N], a[N]; bool vis[N]; bool cmp(int i, int j) { return make_pair(cnt[b[i]], b[i]) > make_pair(cnt[b[j]], b[j]); } int main() { ios::sync_with_stdio(0); cin.tie(0); int T; cin >> T; while (T--) { cin >> n >> x >> y; for (int i = 1; i <= n + 1; i++) cnt[i] = 0; for (int i = 1; i <= n; i++) cin >> b[i], ++cnt[b[i]], vis[i] = 0; int oth = 0; for (int i = 1; i <= n + 1; i++) if (!cnt[i]) { oth = i; break; } int l = 0, r = n; while (l < r) { int mid = (l + r) >> 1, sum = 0; for (int i = 1; i <= n + 1; i++) sum += max(0, cnt[i] - mid); if (sum <= x) r = mid; else l = mid + 1; } if (2 * (n - x - l) < y - x) { cout << NO n ; continue; } cout << YES n ; int sum = x; for (int i = 1; i <= n; i++) if (cnt[b[i]] > l) --cnt[b[i]], a[i] = b[i], vis[i] = 1, --sum; for (int i = 1; i <= n && sum; i++) if (!vis[i]) --cnt[b[i]], a[i] = b[i], vis[i] = 1, --sum; vector<int> id; for (int i = 1; i <= n; i++) if (!vis[i]) id.push_back(i); sort(id.begin(), id.end(), cmp); vector<int> seq; for (int i = 0; i < int(id.size()); i++) if (i == 0 || b[id[i]] != b[id[i - 1]]) seq.push_back(b[id[i]]); if (!seq.empty()) { seq.push_back(seq[0]); seq.erase(seq.begin()); } for (int i = 0, p = 0; i < int(seq.size()); i++) for (int j = 1; j <= cnt[seq[i]]; j++) a[id[p++]] = seq[i]; sum = n - x; for (int i = 1; i <= n; i++) if (!vis[i] && a[i] == b[i]) a[i] = oth, --sum; for (int i = 1; i <= n && sum > y - x; i++) if (!vis[i] && a[i] != oth) a[i] = oth, --sum; for (int i = 1; i <= n; i++) cout << a[i] << ; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; long long arr[200010], tot = 0; int main(void) { cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i]; if (i > 0) tot += abs(arr[i] - arr[i - 1]); else tot += abs(arr[i]); } cout << tot; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, k; cin >> n >> k; string s; cin >> s; string ans; for (long long i = 0; i < k; i++) { ans.push_back(s[i]); } for (long long i = k; i < n; i++) { ans.push_back(ans[i - k]); } cout << n << endl; if (ans >= s) { cout << ans << endl; } else { long long i = k - 1; while (i >= 0 && ans[i] == 9 ) { ans[i] = 0 ; for (long long j = i; j < n; j += k) { ans[j] = 0 ; } i--; } for (; i < n; i += k) { ans[i]++; } cout << ans << endl; } }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF_DCIEN.v
// \ \ / \ Timestamp : Wed Dec 8 17:04:24 PST 2010
// \___\/\___\
//
// Revision:
// 12/08/10 - Initial version.
// 03/28/11 - CR 603466 fix
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUF_DCIEN (O, IO, DCITERMDISABLE, I, IBUFDISABLE, T);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
inout IO;
input DCITERMDISABLE;
input I;
input IBUFDISABLE;
input T;
wire ts;
wire T_OR_IBUFDISABLE;
wire out_val;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
and a1 (disable_out, DCITERMDISABLE, IBUFDISABLE);
// buf B1 (O, IO);
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUF_DCIEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE")) begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on IOBUF_DCIEN instance %m is set to %s. Legal values for this attribute are 7SERIES or ULTRASCALE.",SIM_DEVICE);
$finish;
end
end // initial begin
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
end
"ULTRASCALE" : begin
assign out_val = 1'b0;
end
endcase
endgenerate
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign T_OR_IBUFDISABLE = ~T || IBUFDISABLE;
assign O = (T_OR_IBUFDISABLE == 1'b1) ? out_val : (T_OR_IBUFDISABLE == 1'b0) ? IO : 1'bx;
end
"FALSE" : begin
assign O = IO;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(DCITERMDISABLE => IO) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:46:41 12/12/2016
// Design Name:
// Module Name: vga_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_test(
input wire clk, clr,
output wire hsync, vsync,
output reg [3:0] red, green, blue
);
// signal declaration
wire clk25m;
wire video_on;
wire btn_pos;
wire back_pos;
wire [9:0] pixel_x, pixel_y;
wire [9:0] back_x, back_y, btn_x, btn_y;
wire [17:0] back_addr;
wire [14:0] btn_addr;
wire [11:0] back_data, btn_data;
// instantiate vga_sync circuit
clkdiv div_unit ( .clk(clk), .clr(clr), .clk25m(clk25m) );
vga_sync sync_unit (
.clk(clk25m), .clr(clr), .hsync(hsync), .vsync(vsync), .video_on(video_on), .pixel_x(pixel_x), .pixel_y(pixel_y)
);
// instantiate bmp's pixel data
background P1 (.clka(clk), .addra(back_addr), .douta(back_data));
startBtn P2 (.clka(clk), .addra(btn_addr), .douta(btn_data));
// render the test bmp
assign back_x = pixel_x;
assign back_y = pixel_y - 60;
assign back_addr = back_y * 640 + back_x;
assign btn_x = pixel_x - 350;
assign btn_y = pixel_y - 340;
assign btn_addr = btn_y * 300 + btn_x;
assign btn_pos = (pixel_x >= 350) && (pixel_x < 650) && (pixel_y >= 340) && (pixel_y < 420);
assign back_pos = (pixel_y >=60) && (pixel_y < 420);
//===========================================================================
// Layer 0: background
// Layer 1: static objects
// Layer 2: moving objects
always @*
begin
if(video_on)
begin
if (btn_pos)
begin
if (btn_data == 12'hfff)
begin
if (back_pos)
begin
red <= back_data[ 3: 0];
green <= back_data[ 7: 4];
blue <= back_data[11: 8];
end
else
begin
red <= 4'b0;
green <= 4'b1000;
blue <= 4'b1111;
end
end
else
begin
red <= btn_data[ 3: 0];
green <= btn_data[ 7: 4];
blue <= btn_data[11: 8];
end
end
else
begin
if (back_pos)
begin
red <= back_data[ 3: 0];
green <= back_data[ 7: 4];
blue <= back_data[11: 8];
end
else
begin
red <= 4'b0;
green <= 4'b1000;
blue <= 4'b1111;
end
end
end
else
begin
red <= 4'b0;
green <= 4'b0;
blue <= 4'b0;
end
end
/* pure color display for debug
clkdiv div_unit ( .clk(clk), .clr(clr), .clk25m(clk25m) );
vga_sync test_unit(.clk(clk25m), .clr(clr), .hsync(hsync), .vsync(vsync), .video_on(video_on), .pixel_x(), .pixel_y());
always @*
begin
red <= 4'b0;
blue <= 4'b0;
green <= 4'b0;
if (video_on == 1)
begin
red <= 4'b0;
green <= 4'b1000;
blue <= 4'b1111;
end
end
*/
endmodule
|
module Counter32_RV1 (
input Reset_n_i,
input Clk_i,
input Preset_i,
input Enable_i,
input[31:0] PresetVal_i,
output Zero_o
);
wire ResetSig_s;
wire Direction_s;
wire [15:0] DH_s;
wire [15:0] DL_s;
wire Overflow_s;
assign ResetSig_s = 1'b0;
assign Direction_s = 1'b1;
Counter32 ThisCounter (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.ResetSig_i (ResetSig_s),
.Preset_i (Preset_i),
.Enable_i (Enable_i),
.Direction_i (Direction_s),
.PresetValH_i(PresetVal_i[31:16]),
.PresetValL_i(PresetVal_i[15:0]),
.DH_o (DH_s),
.DL_o (DL_s),
.Overflow_o (Overflow_s),
.Zero_o (Zero_o)
);
endmodule
module Counter32_RV1_Timer (
input Reset_n_i,
input Clk_i,
input Preset_i,
input Enable_i,
input[31:0] PresetVal_i,
output Zero_o
);
reg [31:0] Value;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Value <= 'd0;
end
else
begin
if (Preset_i) begin
Value <= PresetVal_i;
end else if (Enable_i)
begin
Value <= Value - 1'b1;
end
end
end
assign Zero_o = (Value == 0 ? 1'b1 : 1'b0);
endmodule
|
module ghrd_10as066n2_pr_region_controller_0 (
input wire avl_csr_read, // avl_csr.read
input wire avl_csr_write, // .write
input wire [1:0] avl_csr_address, // .address
input wire [31:0] avl_csr_writedata, // .writedata
output wire [31:0] avl_csr_readdata, // .readdata
output wire bridge_freeze0_freeze, // bridge_freeze0.freeze
input wire bridge_freeze0_illegal_request, // .illegal_request
output wire bridge_freeze1_freeze, // bridge_freeze1.freeze
input wire bridge_freeze1_illegal_request, // .illegal_request
input wire clock_clk, // clock.clk
output wire pr_handshake_start_req, // pr_handshake.start_req
input wire pr_handshake_start_ack, // .start_ack
output wire pr_handshake_stop_req, // .stop_req
input wire pr_handshake_stop_ack, // .stop_ack
input wire reset_reset, // reset.reset
output wire reset_source_reset // reset_source.reset
);
endmodule
|
`include "defines.v"
module connectRouter_nobuffer
#(parameter addr = 4'b0000) //No. 0 connect router, port 0
(
input `control_w port_in,
input `control_w inj,
input bfull,
input clk,
input rst,
output `control_w port_out,
output accept,
output `control_w eject,
output push
);
wire `control_w port_0;
assign port_0 = (rst) ? `control_n'd0 : port_in;
wire bfull;
wire productive;
wire push;
wire pop;
wire `control_w bout;
wire [2:0] bsize;
/************* STAGE 1 *************/
reg `control_w port_r_0, port_r_1;
wire `control_w port_1, port_2;
always @(posedge clk) begin
port_r_0 <= port_0;
end
assign productive = (port_r_0[`dest_f] < 4 || port_r_0[`dest_f] > 11)? 0 : 1;
assign push = productive && ~bfull;
assign eject = port_r_0;
assign port_1 = push ? 0 : port_r_0;
assign accept = (~port_1[`valid_f] & inj[`valid_f]);
assign port_2 = accept ? inj : port_1;
/*********** STAGE 2 ***************/
always @ (posedge clk) begin
port_r_1 <= port_2;
end
assign port_out = port_r_1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n1, n2, k1, k2; cin >> n1 >> n2 >> k1 >> k2; if (n1 > n2) { cout << First << endl; return 0; } if (n2 > n1) { cout << Second << endl; return 0; } if (k1 < k2) { cout << Second << endl; return 0; } if (k2 < k1) { cout << Second << endl; return 0; } if (n1 == n2 && k1 == k2) { cout << Second << endl; return 0; } return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { long long a[4]; for (long long i = 0; i < 4; i++) cin >> a[i]; sort(a, a + 4); if ((a[3] + a[0] == a[2] + a[1]) || (a[3] == a[0] + a[1] + a[2])) cout << YES << endl; else cout << NO << endl; return 0; }
|
// megafunction wizard: %LPM_RAM_DP+%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_128_32x32_be.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 148 04/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dpram_128_32x32_be (
data,
wren,
wraddress,
rdaddress,
byteena_a,
wrclock,
rdclock,
q);
input [127:0] data;
input wren;
input [3:0] wraddress;
input [5:0] rdaddress;
input [15:0] byteena_a;
input wrclock;
input rdclock;
output [31:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "16"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0]
// Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL rdaddress[5..0]
// Retrieval info: USED_PORT: byteena_a 0 0 16 0 INPUT VCC byteena_a[15..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: CONNECT: @data_a 0 0 128 0 data 0 0 128 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
// Retrieval info: CONNECT: @byteena_a 0 0 16 0 byteena_a 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be_bb.v TRUE
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_register
*/
module test_axis_register_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter REG_TYPE = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_register_64.lxt");
$dumpvars(0, test_axis_register_64);
end
axis_register #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.REG_TYPE(REG_TYPE)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:39:19 05/12/2015
// Design Name: data_memory
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_data_memory.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: data_memory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_data_memory;
// Inputs
reg clock;
reg mem_write;
reg [11:0] address;
reg [15:0] data_in;
// Outputs
wire [15:0] data_out;
// Instantiate the Unit Under Test (UUT)
data_memory uut (
.clock(clock),
.mem_write(mem_write),
.address(address),
.data_in(data_in),
.data_out(data_out)
);
initial begin
// Initialize Inputs
clock = 0;
mem_write = 0;
address = 0;
data_in = 0;
// Wait 100 ns for global reset to finish
//#100;
#1;
address = 12'h001;
#2;
address = 12'h002;
#2;
address = 12'h003;
end
always #1 clock = !clock;
endmodule
|
//Iamskk// #include <iostream> #include <iosfwd> #include <iomanip> #include <cstdio> #include <cstring> #include <cstdlib> #include <ctime> #include <cmath> #include <cassert> #include <cctype> #include <climits> #include <vector> #include <bitset> #include <set> #include <queue> #include <stack> #include <map> #include <deque> #include <string> #include <list> #include <iterator> #include <sstream> #include <complex> #include <fstream> #include <functional> #include <numeric> #include <utility> #include <algorithm> #include <assert.h> #include <unordered_map> using namespace std; #define IOS ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); #define endl n #define yes cout<< YES <<endl #define no cout<< NO <<endl #define pb push_back #define all(c) (c).begin(),(c).end() #define rall(c) (c).rbegin(),(c).rend() #define ai(arr,n) for(int i=0;i<n;i++)cin>>arr[i]; #define ao(arr) for(auto asdfasdfasdf:arr) cout<<asdfasdfasdf<< ; #define mi(arr,m,n) for(int i=0;i<m;i++){ for(int j=0;j<n;j++) cin>>arr[i][j];} #define mo(arr,m,n) for(int i=0;i<m;i++){ for(int j=0;j<n;j++) cout<<arr[i][j]<< ; cout<<endl;} #define countsetbits(x) __builtin_popcount(x) #define ll long long #define debug cout<< I AM EXECUTING <<endl #define testcases int asdf; cin>>asdf; while(asdf--) #define vi vector<int> #define vll vector<long long int> #define vppo(prs) for(auto x:prs){cout<<x.first<< <<x.second<<endl;} #define For(__,hajmola,adfdf) for(int __ = hajmola; __<adfdf;__++) #define formax 1e18 #define formin -1e18 string sconvert(ll int n) { stringstream ss; ss<<n; string str = ss.str(); return str; } bool sortbysec(const pair<int,int> &a, const pair<int,int> &b) { return (a.second > b.second); } template<typename T> void imax(T &x,T y){ x = max(x,y); } template<typename T> void imin(T &x,T y){ x = min(x,y); } const int nax = 2e3+1; ll int dp[nax][nax]; vector<ll int> krr; ll int answer = 0; ll int solve(int left,int right){ if(dp[left][right]!=-1){ return dp[left][right]; } if(left>=right){ return 0; } ll int value = krr[right]-krr[left]; return dp[left][right]=value + min(solve(left+1,right),solve(left,right-1)); } void single() { memset(dp,-1,sizeof(dp)); int n; cin>>n; vector<ll int> arr(n); ai(arr,n); sort(all(arr)); krr = arr; answer = solve(0,n-1); cout<<answer<<endl; // answer = *max_element(all(arr))-*min_element(all(arr)); return; } void multiple() { testcases { single(); } } int main() { IOS; // freopen( input.txt , r ,stdin); //freopen( output.txt , w ,stdout); single(); }
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="pointer_basic,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.552000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=33,HLS_SYN_LUT=39,HLS_VERSION=2018_2}" *)
module pointer_basic (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
d_i,
d_o,
d_o_ap_vld
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [31:0] d_i;
output [31:0] d_o;
output d_o_ap_vld;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg d_o_ap_vld;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg [31:0] acc;
wire [31:0] acc_assign_fu_31_p2;
reg [0:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 1'd1;
#0 acc = 32'd0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
acc <= acc_assign_fu_31_p2;
end
end
always @ (*) begin
if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
d_o_ap_vld = 1'b1;
end else begin
d_o_ap_vld = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign acc_assign_fu_31_p2 = (acc + d_i);
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign d_o = (acc + d_i);
endmodule //pointer_basic
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1024000000,1024000000 ) using namespace std; const int maxn = 510005; int n, m; vector<int> g[maxn]; char s[maxn]; vector<int> dep[maxn]; vector<int> op[maxn]; int id[maxn][2]; int deep[maxn]; int mx[maxn]; int dfs_clock = 1; void dfs(int u, int d) { deep[u] = mx[u] = d; id[u][0] = dfs_clock++; dep[d].push_back(1 << (s[u] - a )); op[d].push_back(id[u][0]); for (int i = 0; i < g[u].size(); i++) { dfs(g[u][i], d + 1); mx[u] = max(mx[u], mx[g[u][i]]); } id[u][1] = dfs_clock++; } int main() { int p; scanf( %d%d , &n, &m); for (int i = 2; i <= n; i++) { scanf( %d , &p); g[p].push_back(i); } scanf( %s , s + 1); dfs(1, 1); for (int i = 1; i <= n; i++) { for (int j = 1; j < dep[i].size(); j++) { dep[i][j] ^= dep[i][j - 1]; } } int u, h; for (int i = 0; i < m; i++) { scanf( %d%d , &u, &h); if (h <= deep[u] || h > mx[u]) { printf( Yes n ); } else { int i = upper_bound(op[h].begin(), op[h].end(), id[u][0]) - op[h].begin(); int j = upper_bound(op[h].begin(), op[h].end(), id[u][1]) - op[h].begin() - 1; int a; if (i - 1 >= 0) a = dep[h][j] ^ dep[h][i - 1]; else a = dep[h][j]; int num = 0; for (int i = 0; i < 26; i++) { if (a & (1 << i)) num++; } if (num <= 1) printf( Yes n ); else printf( No n ); } } return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_NIOS_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
SoC_NIOS_jtag_debug_module_tck the_SoC_NIOS_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
SoC_NIOS_jtag_debug_module_sysclk the_SoC_NIOS_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic SoC_NIOS_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam SoC_NIOS_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// SoC_NIOS_jtag_debug_module_phy.sld_instance_index = 0,
// SoC_NIOS_jtag_debug_module_phy.sld_ir_width = 2,
// SoC_NIOS_jtag_debug_module_phy.sld_mfg_id = 70,
// SoC_NIOS_jtag_debug_module_phy.sld_sim_action = "",
// SoC_NIOS_jtag_debug_module_phy.sld_sim_n_scan = 0,
// SoC_NIOS_jtag_debug_module_phy.sld_sim_total_length = 0,
// SoC_NIOS_jtag_debug_module_phy.sld_type_id = 34,
// SoC_NIOS_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
`timescale 1ns / 1ps
module data_path(
//---------------channel data input-----------------------------------------
input [15:0] din16,
//---------------channel data output-----------------------------------------
output [31:0] dout32,
//---------------Register-----------------------------------------------------
input [31:0] control_reg,
output [63:0] freq_reg,
output [63:0] total_size,
//--------------Globe signal----------------------------------------------------
input data_path_rst,
input clk_50m,
input clk_pcie,
input adc_clk,
//---------------Control-----------------------------------------------------
input ddr3_fifo_full,
output fifo_empty,
output fifo_full,
output total_size_mannul_reset,
output fifo_rd_en
);
localparam BUFR_DIVIDE = 2;
BUFR #(
.BUFR_DIVIDE(BUFR_DIVIDE), // "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
.SIM_DEVICE("7SERIES") // Specify target device, "VIRTEX4" or "VIRTEX5"
) BUFR_clkdiv (
.O(clk_bufr), // Clock buffer output
.CE(1'b1), // Clock enable input
.CLR(1'b0), // Clock buffer reset input
.I(clk_pcie) // Clock buffer input
);
assign fifo_rd_en = control_reg[4] ? counter_fifo_rd_en : fifo16to32_rd_en;
assign fifo_empty = control_reg[4] ? counter_fifo_empty : fifo16to32_empty;
assign fifo_full = control_reg[4] ? counter_fifo_full : fifo16to32_full;
//--------------ÄÚ²¿¼Ä´æÆ÷-----------------------------------------------------------------------
wire [63:0] freq_det_q_d,freq_det_q_c;
reg [63:0] total_size_reg1;
reg [63:0] total_size_reg2;
wire [31:0] fifo16to32_dout;//16to32´®²¢×ª»»Êý¾ÝÊä³ö
wire [31:0] counter_data;//¼ÆÊýÆ÷Êý¾Ý
wire [31:0] counter_fifo_dout;//¼ÆÊýÆ÷Êý¾Ý»º³åÊä³ö
//--------------½»Ö¯½»»»---------------------------------------------
assign dout32 = control_reg[4] ? counter_fifo_dout :
(control_reg[5] ? fifo16to32_dout :
{fifo16to32_dout[7:0],fifo16to32_dout[15:8],
fifo16to32_dout[23:16],fifo16to32_dout[31:24]});
//--------------8 to 32---------------------------------------------------
wire rec_en = control_reg[1] ? 1'b0 : control_reg[0];
assign fifo16to32_rd_en = !fifo16to32_empty & !ddr3_fifo_full;
fifo8to32 fifo16to32_ch (
.rst(data_path_rst),
.wr_clk(adc_clk),
.rd_clk(clk_pcie),
.din(din16),
.wr_en(rec_en),
.rd_en(fifo16to32_rd_en),
.dout(fifo16to32_dout),
.full(fifo16to32_full),
.empty(fifo16to32_empty)
);
//------------------------µÝÔö²âÊÔ¼ÆÊýÆ÷----------------------------------------------
wire counter_ce = control_reg[7] & control_reg[4] & rec_en;
assign counter_fifo_rd_en = !counter_fifo_empty & !ddr3_fifo_full;
COUNTER_LOAD_MACRO #(
.COUNT_BY(48'h000000000001),
.DEVICE("7SERIES"),
.WIDTH_DATA(32)
) counter32_ch (
.Q(counter_data),
.CLK(clk_bufr),
.CE(counter_ce & (~data_path_rst)),
.DIRECTION(1'b1),
.LOAD(control_reg[18]),
.LOAD_DATA(counter_load_data),
.RST(data_path_rst)
);
counter_fifo counter_fifo_ch (
.rst(data_path_rst),
.wr_clk(clk_bufr),
.rd_clk(clk_pcie),
.din(counter_data),
.wr_en(counter_ce & (~data_path_rst)),
.rd_en(counter_fifo_rd_en),
.dout(counter_fifo_dout),
.full(counter_fifo_full),
.empty(counter_fifo_empty)
);
//------------------------Êý¾Ýͳ¼Æ----------------------------------------------
assign total_size_mannul_reset = control_reg[17];
assign total_size = control_reg[4] ? total_size_reg2 : total_size_reg1;
always @(posedge c_div or posedge data_path_rst)begin
if(data_path_rst)begin
total_size_reg1 <= 64'b0;
end
else if(!rec_en | total_size_mannul_reset)begin
total_size_reg1 <= 64'b0;
end
else begin
total_size_reg1 <= total_size_reg1 + 64'd8;
end
end
always @(posedge clk_bufr or posedge data_path_rst)begin
if(data_path_rst)begin
total_size_reg2 <= 64'b0;
end
else if(!counter_ce | total_size_mannul_reset)begin
total_size_reg2 <= 64'b0;
end
else begin
total_size_reg2 <= total_size_reg2 + 64'd32;
end
end
//------------------------ƵÂʼì²â----------------------------------------------
assign freq_reg = control_reg[4] ? (freq_det_q_c<<3) : (freq_det_q_d<<3);
Freq_Count_Top freq_det_d (
.sys_clk_50m(clk_50m),
.ch_c(c_div),
.freq_reg(freq_det_q_d),
.sys_rst_n(~data_path_rst)
);
Freq_Count_Top freq_det_c (
.sys_clk_50m(clk_50m),
.ch_c(clk_bufr),
.freq_reg(freq_det_q_c),
.sys_rst_n(~data_path_rst)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, a[102400], i, j, o = 0, l = 0, ma, k = 0; cin >> n; for (i = 0; i < n; i++) cin >> a[i]; for (i = 1; i < n; i++) { if (a[i] + k < a[i - 1]) { o += a[i - 1] - (a[i] + k); k += a[i - 1] - (a[i] + k); a[i] = a[i - 1]; } else { if (a[i] < a[i - 1]) { k = a[i - 1] - a[i]; a[i] = a[i - 1]; } else k = 0; } } cout << o << endl; }
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ()
//
// Brief Description:
// DVB interleaver.
//
//------------------------------------------------------------------------------
`ifndef _ZL_INTERLEAVER_V_
`define _ZL_INTERLEAVER_V_
`include "zl_fifo_sc.v"
`include "zl_sdp_ram.v"
module zl_interleaver
(
input clk,
input rst_n,
//
input data_in_req,
output data_in_ack,
input [7:0] data_in,
//
output data_out_req,
input data_out_ack,
output [7:0] data_out
);
localparam Ptr_width = 8; // max fifo size = 17x11=187
localparam N_ptrs = 12;
localparam N_ptrs_width = 4;
localparam Packet_len = 204;
localparam Packet_len_width = 8;
localparam Sync_byte = 8'h47;
reg [Packet_len_width-1:0] packet_byte_count;
reg [Ptr_width-1:0] rd_ptr [0:N_ptrs-1];
reg [Ptr_width-1:0] wr_ptr [0:N_ptrs-1];
reg [N_ptrs_width-1:0] ptr_select;
wire data_fifo_out_req;
wire token_fifo_out_req;
wire token_fifo_in_req;
wire token_fifo_in_ack;
wire data_fifo_in_req;
wire [7:0] data_fifo_in;
reg data_in_ack_d1;
reg data_in_ack_d2;
reg [7:0] data_in_d1;
reg [7:0] data_in_d2;
wire [(N_ptrs_width+Ptr_width)-1:0] mem_rd_addr;
wire [(N_ptrs_width+Ptr_width)-1:0] mem_wr_addr;
wire [7:0] mem_rd_data;
wire [7:0] mem_rd_data_fixed;
wire mem_wr_en;
wire rd_wr_conflict;
reg rd_wr_conflict_d1;
reg rd_wr_conflict_d2;
zl_fifo_sc #
(
.Data_width(8),
.Addr_width(2)
)
data_fifo
(
.clk(clk),
.rst_n(rst_n),
//
.in_req(data_fifo_in_req),
.in_ack(),
.in_data(data_fifo_in),
//
.out_req(data_fifo_out_req),
.out_ack(data_out_ack),
.out_data(data_out),
//
.full(),
.empty(),
.used()
);
zl_fifo_sc #
(
.Data_width(1),
.Addr_width(2)
)
token_fifo
(
.clk(clk),
.rst_n(rst_n),
//
.in_req(token_fifo_in_req),
.in_ack(token_fifo_in_ack),
.in_data(1'b0),
//
.out_req(token_fifo_out_req),
.out_ack(data_out_ack),
.out_data(),
//
.full(),
.empty(),
.used()
);
zl_sdp_ram #
(
.Write_data_width(8),
.Write_addr_width(N_ptrs_width+Ptr_width),
.Read_data_width(8),
.Read_addr_width(N_ptrs_width+Ptr_width)
)
interleave_mem
(
.clk_wr(clk),
.clk_rd(clk),
//
.wr_addr(mem_wr_addr),
.wr_data(data_in),
.wr_en(mem_wr_en),
//
.rd_addr(mem_rd_addr),
.rd_data(mem_rd_data)
);
// delayed copies of signals to align with BRAM read latency
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
data_in_ack_d1 <= 1'b0;
data_in_ack_d2 <= 1'b0;
//
data_in_d1 <= 8'b0;
data_in_d2 <= 8'b0;
//
rd_wr_conflict_d1 <= 1'b0;
rd_wr_conflict_d2 <= 1'b0;
end
else begin
data_in_ack_d1 <= data_in_ack;
data_in_ack_d2 <= data_in_ack_d1;
//
data_in_d1 <= data_in;
data_in_d2 <= data_in_d1;
//
rd_wr_conflict_d1 <= rd_wr_conflict;
rd_wr_conflict_d2 <= rd_wr_conflict_d1;
end
end
// addressing into the memory
assign mem_wr_addr = {ptr_select, wr_ptr[ptr_select]};
assign mem_rd_addr = {ptr_select, rd_ptr[ptr_select]};
assign mem_wr_en = data_in_ack;
// if we read the same location we are writing, we want to new value
// this logic bypasses the memory in this case
assign rd_wr_conflict = mem_wr_en && (mem_wr_addr == mem_rd_addr);
assign mem_rd_data_fixed = (rd_wr_conflict_d2 ? data_in_d2 : mem_rd_data);
// two output of the same depth - a data fifo and a token fifo
// the token fifo gets a "token" placed in it when new data_in
// is accepted, and is responsible for providing backpressure.
assign data_out_req = token_fifo_out_req && data_fifo_out_req;
assign token_fifo_in_req = data_in_req;
assign data_in_ack = token_fifo_in_ack;
// the data fifo gets data placed in it 2 cycles after the token
// fifo (BRAM read latency).
assign data_fifo_in_req = data_in_ack_d2;
assign data_fifo_in = mem_rd_data_fixed;
// keep track of the pointers - rd and wr pointers are kept a fixed
// distance apart to create the necessary delay in the arm of the
// interleaver. Note that the size of the ring buffer (256) is the same
// in all cases - what matters is the delta between pointers, not the buffer
// size (as long as it is larger than the desired delay).
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ptr_select <= {N_ptrs_width{1'b0}};
rd_ptr[0] <= {Ptr_width{1'b0}};
rd_ptr[1] <= {Ptr_width{1'b0}};
rd_ptr[2] <= {Ptr_width{1'b0}};
rd_ptr[3] <= {Ptr_width{1'b0}};
rd_ptr[4] <= {Ptr_width{1'b0}};
rd_ptr[5] <= {Ptr_width{1'b0}};
rd_ptr[6] <= {Ptr_width{1'b0}};
rd_ptr[7] <= {Ptr_width{1'b0}};
rd_ptr[8] <= {Ptr_width{1'b0}};
rd_ptr[9] <= {Ptr_width{1'b0}};
rd_ptr[10] <= {Ptr_width{1'b0}};
rd_ptr[11] <= {Ptr_width{1'b0}};
wr_ptr[0] <= 0;
wr_ptr[1] <= 17;
wr_ptr[2] <= 17*2;
wr_ptr[3] <= 17*3;
wr_ptr[4] <= 17*4;
wr_ptr[5] <= 17*5;
wr_ptr[6] <= 17*6;
wr_ptr[7] <= 17*7;
wr_ptr[8] <= 17*8;
wr_ptr[9] <= 17*9;
wr_ptr[10] <= 17*10;
wr_ptr[11] <= 17*11;
packet_byte_count <= {Packet_len_width{1'b0}};
end
else if(data_in_ack) begin
if(packet_byte_count == 0 &&
!(data_in == Sync_byte || data_in == ~Sync_byte)) begin
// if we get off sync (datastream got messed up)
// then wait here and make sure the next sync byte
// ends up in the 0th arm of the interleaver
ptr_select <= {N_ptrs_width{1'b0}};
end
else begin
if(packet_byte_count == Packet_len-1) begin
packet_byte_count <= {Packet_len_width{1'b0}};
end
else begin
packet_byte_count <= packet_byte_count + 1'b1;
end
//
if(ptr_select == N_ptrs-1) begin
ptr_select <= {N_ptrs_width{1'b0}};
end
else begin
ptr_select <= ptr_select + 1'b1;
end
//
rd_ptr[ptr_select] <= rd_ptr[ptr_select] + 1'b1;
wr_ptr[ptr_select] <= wr_ptr[ptr_select] + 1'b1;
end
end
end
endmodule // zl_interleaver
`endif // _ZL_INTERLEAVER_V_
|
#include <bits/stdc++.h> using namespace std; const int MAXL = 40000; pair<int, int> p[MAXL]; int Init() { for (int i = 0; i * i < MAXL; i++) { for (int j = i; j * j + i * i < MAXL; j++) { int now = i * i + j * j; p[now].first = i; p[now].second = j; } } return 0; } inline bool cmp(pair<int, int> a, pair<int, int> b) { return a.first * a.first + a.second * a.second > b.first * b.first + b.second * b.second; } inline bool cmp2(pair<int, int> a, pair<int, int> b) { return atan2(a.second, a.first) < atan2(b.second, b.first) - (1e-8); } int L(int a, int b) { return a * a + b * b; } int n; int Solve() { vector<pair<int, int> > e; int sum = 0; scanf( %d , &n); for (int i = 0; i < MAXL && e.size() <= n; i++) { if (p[i].first == 0 && p[i].second == 0) continue; sum ^= p[i].first ^ p[i].second; e.push_back(p[i]); } reverse(e.begin(), e.end()); for (vector<pair<int, int> >::iterator it = e.begin(); it != e.end(); it++) { if (((sum ^ it->first ^ it->second) & 1) == 0) { e.erase(it); break; } } sort(e.begin(), e.end(), cmp); int ix = 0, iy = 0; for (vector<pair<int, int> >::iterator it = e.begin(); it != e.end(); it++) { int fx = 1, fy = 1; int xx = it->first, yy = it->second; if (ix > 0) fx = -1; if (iy > 0) fy = -1; if (L(fx * xx + ix, fy * yy + iy) < L(fx * yy + ix, fy * xx + iy)) *it = make_pair(fx * xx, fy * yy); else *it = make_pair(fx * yy, fy * xx); ix = it->first + ix; iy = it->second + iy; } sort(e.begin(), e.end(), cmp2); puts( YES ); for (vector<pair<int, int> >::iterator it = e.begin(); it != e.end(); it++) { printf( %d %d n , ix, iy); ix += it->first; iy += it->second; } return 0; } int main() { Init(); Solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long read() { long long x = 0, F = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) F = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + c - 0 ; c = getchar(); } return x * F; } int add(int a, int b) { return (a + b >= 51123987) ? a + b - 51123987 : a + b; } int dec(int a, int b) { return (a - b < 0) ? a - b + 51123987 : a - b; } int mul(long long a, int b) { return 1LL * a * b % 51123987; } int ans, Tk, n, L[2000000 + 5], R[2000000 + 5], ecnt, head[2000000 + 5]; char s[2000000 + 5]; struct edge { int to, nxt, c; } e[2000000 + 5]; void add(int u, int v, int c) { e[++ecnt] = (edge){v, head[u], c}; head[u] = ecnt; } struct Palindromic_Tree { int dep[2000000 + 5], fa[2000000 + 5], len[2000000 + 5]; int lst, tot; void init() { memset(head, 0, sizeof(head)); ecnt = 0; memset(fa, 0, sizeof(fa)), memset(len, 0, sizeof(len)), memset(dep, 0, sizeof(dep)); tot = 0, lst = 0; len[++tot] = -1; fa[0] = fa[1] = 1; } int get_id(int x, int c) { for (int i = head[x]; i; i = e[i].nxt) if (e[i].c == c) return e[i].to; return 0; } void Insert(int c, int L) { int p = lst; while (s[L - len[p] - 1] != s[L]) p = fa[p]; if (!get_id(p, c)) { int np = ++tot, k = fa[p]; len[np] = len[p] + 2; while (s[L - len[k] - 1] != s[L]) k = fa[k]; fa[np] = get_id(k, c); dep[np] = dep[fa[np]] + 1; add(p, np, c); } lst = get_id(p, c); } } T; int main() { n = read(); scanf( %s , s + 1); T.init(); for (int i = 1; i <= n; i++) { T.Insert(s[i] - a , i); L[i] = T.dep[T.lst]; ans = add(ans, L[i]); } ans = mul(1LL * ans * (ans - 1) / 2, 1); T.init(); reverse(s + 1, s + n + 1); for (int i = n; i >= 1; i--) { T.Insert(s[n - i + 1] - a , n - i + 1); R[i] = T.dep[T.lst]; R[i] = add(R[i], R[i + 1]); } for (int i = 1; i < n; i++) ans = dec(ans, mul(L[i], R[i + 1])); printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; int main() { int count[26] = {0}, c = 0, i; string str; getline(cin, str); for (i = 1; i <= str.length() - 1; i++) { if (str[i] == } || str[i] == , ) count[str[i - 1] - a ]++; } for (i = 0; i <= 25; i++) if (count[i] > 0) c++; printf( %d n , c); }
|
#include <bits/stdc++.h> using namespace std; vector<int> all; vector<int> zu; vector<int> de; int main() { string x; cin >> x; int y = x.size() / 2; cout << x; for (size_t i = 0; i < y; i++) { swap(x[i], x[x.size() - i - 1]); } cout << x << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void amin(T &x, U y) { if (y < x) x = y; } template <typename T, typename U> inline void amax(T &x, U y) { if (x < y) x = y; } int main() { int n, p, k, ai; cin >> n >> k >> p; vector<int> ods; vector<int> evns; for (int i = 0; i < n; i++) { cin >> ai; if (ai % 2 == 0) evns.push_back(ai); else ods.push_back(ai); } int rem = k - p; vector<vector<int> > ans; for (int i = 0; i < p; i++) { if (evns.size()) { vector<int> tmp; tmp.push_back(evns.back()); ans.push_back(tmp); evns.pop_back(); } else if (ods.size() >= 2) { vector<int> tmp; tmp.push_back(ods.back()); ods.pop_back(); tmp.push_back(ods.back()); ods.pop_back(); ans.push_back(tmp); } else { cout << NO ; return 0; } } for (int i = 0; i < rem; i++) { if (ods.size()) { vector<int> tmp; tmp.push_back(ods.back()); ans.push_back(tmp); ods.pop_back(); } else { cout << NO ; return 0; } } if (ods.size() % 2 == 1) { cout << NO ; return 0; } if (k == 1) { cout << YES << endl; int m = ans[0].size() + ods.size() + evns.size(); cout << m << ; for (int j = 0; j < ans[0].size(); j++) cout << ans[0][j] << ; for (int j = 0; j < ods.size(); j++) cout << ods[j] << ; for (int j = 0; j < evns.size(); j++) cout << evns[j] << ; return 0; } cout << YES << endl; for (int i = 0; i < ans.size(); i++) { if (ods.size()) { int m = ans[i].size() + ods.size(); cout << m << ; for (int j = 0; j < ans[i].size(); j++) cout << ans[i][j] << ; for (int j = 0; j < ods.size(); j++) cout << ods[j] << ; ods.clear(); cout << endl; } else if (evns.size()) { int m = ans[i].size() + evns.size(); cout << m << ; for (int j = 0; j < ans[i].size(); j++) cout << ans[i][j] << ; for (int j = 0; j < evns.size(); j++) cout << evns[j] << ; evns.clear(); cout << endl; } else { cout << ans[i].size() << ; for (int j = 0; j < ans[i].size(); j++) cout << ans[i][j] << ; cout << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int x[2001], y[2001]; int p[2001], mn[2001]; int k[2001], c[2001]; bool used[2001][2001]; unsigned long long dst[2001][2001]; unsigned long long dist(int i, int j) { return (unsigned long long)(k[i] + k[j]) * (unsigned long long)(abs(x[i] - x[j]) + abs(y[i] - y[j])); } void init() { for (int i = 0; i < n; i++) { p[i] = i; mn[i] = c[i]; } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { dst[i][j] = dist(i, j); dst[j][i] = dst[i][j]; } } } struct vertex { unsigned long long len; int x, y; vertex(){}; vertex(unsigned long long _len, int _x, int _y) { len = _len; x = _x; y = _y; } bool operator<(vertex b) { return len < b.len; } }; bool operator<(const vertex& a, const vertex& b) { return a.len < b.len; } multiset<vertex> s; int get_anc(int x) { if (x == p[x]) return x; return p[x] = get_anc(p[x]); } void unite(int x, int y) { x = get_anc(x); y = get_anc(y); if (x == y) return; if (x < y) swap(x, y); p[x] = y; mn[y] = min(mn[x], mn[y]); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i]; } for (int i = 0; i < n; i++) cin >> c[i]; for (int i = 0; i < n; i++) cin >> k[i]; init(); for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { s.insert(vertex(dst[i][j], i, j)); } } unsigned long long ans = 0; int conn = 0; while (!s.empty()) { vertex cur = *s.begin(); s.erase(s.begin()); unsigned long long curlen = cur.len; int curx = cur.x, cury = cur.y; if (get_anc(curx) == get_anc(cury)) continue; if (curlen + min(mn[get_anc(curx)], mn[get_anc(cury)]) > mn[get_anc(curx)] + mn[get_anc(cury)]) continue; unite(curx, cury); ans += curlen; used[curx][cury] = used[cury][curx] = 1; conn++; } vector<int> way; for (int i = 0; i < n; i++) { int x = get_anc(i); if (c[i] == mn[x]) { ans += c[i]; mn[i] = -1; way.push_back(i + 1); } } cout << ans << endl; cout << way.size() << endl; for (int i = 0; i < way.size(); i++) cout << way[i] << ; cout << endl; cout << conn << endl; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (used[i][j]) cout << i + 1 << << j + 1 << endl; } } return 0; }
|
//-----------------------------------------------------------------
// FPGA Audio Project SoC IP
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email:
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module sram4
(
clk_i,
address_i,
data_i,
data_o,
wr_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] SRAM_ADDR_WIDTH = 14;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input [31:0] address_i /*verilator public*/;
input [31:0] data_i /*verilator public*/;
output [31:0] data_o /*verilator public*/;
input [3:0] wr_i /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
wire [31:0] address;
wire [31:0] data_o;
//-----------------------------------------------------------------
// Implementation
//-----------------------------------------------------------------
assign address = {2'b00, address_i[31:2]};
generate
begin : sram_gen
genvar i;
for (i=0;i<4;i=i+1)
begin :sram_loop
sram
#(
.WIDTH(8),
.SIZE(SRAM_ADDR_WIDTH)
)
u1_bram
(
.clk_i(clk_i),
.dat_o(data_o[(((i + 1) * 8) - 1):(i * 8)]),
.dat_i(data_i[(((i + 1) * 8) - 1):(i * 8)]),
.adr_i(address[(SRAM_ADDR_WIDTH - 1):0]),
.wr_i(wr_i[i])
);
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16000000 ) using namespace std; const int inf = 0x3f3f3f3f; const long long inf2 = 0x3f3f3f3f3f3f3f3f; const double eps = 1e-6; const int mod = 1000000007; namespace fastio { char in[100000]; int itr = 0, llen = 0; char get() { if (itr == llen) llen = fread(in, 1, 100000, stdin), itr = 0; if (llen == 0) return EOF; return in[itr++]; } char out[100000]; int itr2 = 0; void put(char c) { out[itr2++] = c; if (itr2 == 100000) { fwrite(out, 1, 100000, stdout); itr2 = 0; } } int clear() { fwrite(out, 1, itr2, stdout); itr2 = 0; return 0; } int getint() { int r = 0; bool ng = 0; char c; c = get(); while (c != - && (c < 0 || c > 9 )) c = get(); if (c == - ) ng = 1, c = get(); while (c >= 0 && c <= 9 ) r = r * 10 + c - 0 , c = get(); return ng ? inf : r; } string getstr() { string ret = ; char ch = get(); while (ch == || ch == n ) ch = get(); while (ch != && ch != n ) ret.push_back(ch), ch = get(); return ret; } void putstr(string s) { for (int i = 0; i < s.size(); i++) put(s[i]); } void putint(int x) { if (x == 0) { put( 0 ); return; } char c[20]; int pos = 0; while (x) { c[pos++] = 0 + x % 10; x /= 10; } for (int i = pos - 1; i >= 0; i--) put(c[i]); } void getarr(int arrname[], int size) { for (int i = 0; i < size; i++) arrname[i] = getint(); } } // namespace fastio using namespace fastio; int n, m; bool used[111111 * 5]; vector<int> g[111111 * 5]; int deg[111111 * 5]; vector<pair<int, int> > edges; vector<int> ans; void dfs(int x, int par) { used[x] = true; ans.push_back(x); for (auto p : g[x]) { deg[p]--; if (deg[p] == 0) dfs(p, x); } } int main() { n = getint(); m = getint(); vector<vector<int> > vec(n, vector<int>(m)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) vec[i][j] = getint(); int pre = m; for (int i = 0; i < n; i++) { bool buff = (i == 0); vector<pair<int, int> > V; for (int j = 0; j < m; j++) V.push_back(make_pair(vec[i][j], j)); sort(V.begin(), V.end()); while (V.back().first == inf) V.pop_back(); if (!V.size()) continue; int pos = 0; set<int> Set; Set.clear(); for (int ii = 0; ii < V.size(); ii++) { Set.insert(V[ii].first); } bool first = true; for (set<int>::iterator itr = Set.begin(); itr != Set.end(); itr++) { int p = *itr; set<int>::iterator itr2 = itr; itr2++; bool last = itr2 == Set.end(); for (int &t = pos; t < V.size() && V[t].first == p; t++) { if (!first) g[pre].push_back(V[t].second), deg[V[t].second]++, cerr << V[t].second << endl; if (Set.size() != 1 && !last) g[V[t].second].push_back(pre + 1), deg[pre + 1]++, cerr << pre << endl; } if (Set.size() != 1) pre++; first = false; } } cerr << Start top sort: n ; for (int i = 0; i < pre; i++) if (!used[i] && !deg[i]) dfs(i, -1); vector<int> ans2; ans2.clear(); for (int i = 0; i < ans.size(); i++) if (ans[i] < m) ans2.push_back(ans[i]); if (ans2.size() < m) { puts( -1 ); return 0; } else { for (int i = 0; i < ans2.size(); i++) putint(ans2[i] + 1), put( ); return clear(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); string s; cin >> s; char x = a ; int y; set<int> arr[26]; for (int i = 0; i < s.length(); i++) { y = s[i] - x; arr[y].insert(i); } int q; cin >> q; int n, ans = 0; for (int i = 0; i < q; i++) { cin >> n; if (n == 1) { int pos; char c; cin >> pos >> c; y = s[pos - 1] - x; arr[y].erase(pos - 1); s[pos - 1] = c; y = c - x; arr[y].insert(pos - 1); } if (n == 2) { int l, r; cin >> l >> r; l--; r--; for (int i = 0; i < 26; i++) { auto it = arr[i].lower_bound(l); if (it == arr[i].end()) continue; else if (*it <= r) ans++; } cout << ans << endl; ans = 0; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool SR(int &_x) { return scanf( %d , &_x) == 1; } bool SR(long long &_x) { return scanf( %lld , &_x) == 1; } bool SR(double &_x) { return scanf( %lf , &_x) == 1; } bool SR(char *_s) { return scanf( %s , _s) == 1; } bool RI() { return true; } template <typename I, typename... T> bool RI(I &_x, T &..._tail) { return SR(_x) && RI(_tail...); } void SP(const int _x) { printf( %d , _x); } void SP(const long long _x) { printf( %lld , _x); } void SP(const double _x) { printf( %.16lf , _x); } void SP(const char *s) { printf( %s , s); } void PL() { puts( ); } template <typename I, typename... T> void PL(const I _x, const T... _tail) { SP(_x); if (sizeof...(_tail)) putchar( ); PL(_tail...); } const int maxn = 5e5 + 5; int n, x[maxn], y[maxn]; void read() { RI(n); for (int i = (1); i <= int(n); i++) { int a, b; RI(x[i], y[i], a, b); } } int c[maxn]; void build() { for (int i = (1); i <= int(n); i++) { c[i] = 1 + (x[i] & 1) * 2 + (y[i] & 1); } } void sol() { PL( YES ); for (int i = (1); i <= int(n); i++) PL(c[i]); } int main() { read(); build(); sol(); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool isAscending(const vector<int64_t>& vec) { for (int i = 1; i < vec.size(); ++i) { if (vec[i - 1] >= vec[i]) { return false; } } return true; } bool Requal(const vector<int64_t>& av, const vector<int64_t>& bv) { for (int i = 0; i < av.size(); ++i) { if (av[i] != bv[bv.size() - i - 1]) { return false; } } return true; } bool Equal(const vector<int64_t>& av, const vector<int64_t>& bv) { for (int i = 0; i < av.size(); ++i) { if (av[i] != bv[i]) { return false; } } return true; } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); int len; cin >> len; vector<int64_t> av(len), bv(len); for (auto&& e : av) { cin >> e; } for (auto&& e : bv) { cin >> e; } if (len == 1) { if (av[0] == bv[0]) { cout << SMALL << endl; cout << 0 << endl; cout << endl; } else { cout << IMPOSSIBLE << endl; } return 0; } if (len == 2) { int64_t total = 0; vector<pair<char, int64_t>> buf; string res; if (av[0] > av[1]) { swap(av[0], av[1]); res += R ; } while (1) { if (bv[0] > bv[1]) { swap(bv[0], bv[1]); buf.push_back({ R , 1}); } if (bv[0] == av[0]) { if (bv[1] >= av[1] && ((bv[1] - av[1]) % bv[0]) == 0) { buf.push_back({ P , (bv[1] - av[1]) / bv[0]}); total += (bv[1] - av[1]) / bv[0]; } else { total = -1; } break; } if (bv[0] == bv[1]) { total = -1; break; } buf.push_back({ P , bv[1] / bv[0]}); bv[1] = bv[1] % bv[0]; total += buf.back().second; if (bv[1] == 0) { bv[1] = bv[0]; total--; buf.back().second--; } } if (total < 0) { cout << IMPOSSIBLE << endl; return 0; } if (total > 200000) { cout << BIG << endl; cout << total << endl; } else { cout << SMALL << endl; for (auto it = buf.rbegin(); it != buf.rend(); ++it) { for (int i = 0; i < it->second; ++i) { res += it->first; } } cout << res.size() << endl; cout << res << endl; } return 0; } int64_t total = 0; string res; while (1) { if (Equal(av, bv)) { break; } if (Requal(av, bv)) { res += R ; break; } if (bv[0] > bv[1]) { reverse(begin(bv), end(bv)); res += R ; } if (isAscending(bv) and bv[0] > 0) { for (int i = len; i-- > 1;) { bv[i] -= bv[i - 1]; } res += P ; ++total; } else { res = ; break; } } if (res == ) { cout << IMPOSSIBLE << endl; } else if (total > 200000) { cout << BIG << endl; cout << total << endl; } else { cout << SMALL << endl; reverse(begin(res), end(res)); cout << res.size() << endl; cout << res << endl; } return 0; }
|
#include <bits/stdc++.h> template <typename Tp> void in(Tp &x) { char ch = getchar(), f = 1; x = 0; while (ch != - && (ch < 0 || ch > 9 )) ch = getchar(); if (ch == - ) f = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); x *= f; } template <typename Tp> bool chkmax(Tp &x, Tp y) { return x >= y ? 0 : (x = y, 1); } template <typename Tp> bool chkmin(Tp &x, Tp y) { return x <= y ? 0 : (x = y, 1); } template <typename Tp> Tp Max(const Tp &x, const Tp &y) { return x > y ? x : y; } template <typename Tp> Tp Min(const Tp &x, const Tp &y) { return x < y ? x : y; } const int MAXN = 400010; int n; int s[MAXN], g[MAXN]; int head[MAXN], nxt[MAXN << 1], data[MAXN << 1], flow[MAXN << 1], cnt; void add(int x, int y, int z) { nxt[cnt] = head[x]; data[cnt] = y; flow[cnt] = z; head[x] = cnt++; } using std::queue; queue<int> q; bool instack[MAXN]; long long dis[MAXN]; void spfa() { memset(dis, 0x3f, sizeof dis); dis[0] = 0; instack[0] = true; q.push(0); while (!q.empty()) { int now = q.front(); q.pop(); instack[now] = false; for (int i = head[now]; i != -1; i = nxt[i]) { if (dis[data[i]] > dis[now] + flow[i]) { dis[data[i]] = dis[now] + flow[i]; if (!instack[data[i]]) { q.push(data[i]); instack[data[i]] = true; } } } } long long ans1 = 0; for (int i = (1), i_END_ = (n); i <= i_END_; ++i) { ans1 += dis[i]; if (dis[i] < 0) { puts( -1 ); return; } } printf( %I64d n , ans1); for (int i = (1), i_END_ = (n); i <= i_END_; ++i) printf( %I64d , dis[i] + s[i]); putchar(10); } int main() { in(n); for (int i = (1), i_END_ = (n); i <= i_END_; ++i) in(s[i]), in(g[i]); memset(head, -1, sizeof head); for (int i = (1), i_END_ = (n); i <= i_END_; ++i) add(0, i, g[i]); for (int i = (1), i_END_ = (n - 1); i <= i_END_; ++i) { int t = s[i] - s[i + 1]; add(i, i + 1, 1 + t); add(i + 1, i, 1 - t); } spfa(); return 0; }
|
#include <bits/stdc++.h> namespace imzzy { class fastin { private: int _ch, _f; public: inline fastin &operator>>(char &c) { c = getchar(); return *this; } template <typename _Tp> inline fastin &operator>>(_Tp &_x) { _x = 0; while (!isdigit(_ch)) _f |= (_ch == 45), _ch = getchar(); while (isdigit(_ch)) _x = (_x << 1) + (_x << 3) + (_ch ^ 48), _ch = getchar(); _f && (_x = -_x, _f = 0); return *this; } fastin() { _ch = _f = 0; } } fin; } // namespace imzzy using namespace imzzy; const int maxn = 1004, maxm = 500004; int nxt[maxn], pre[maxn], p[5]; bool g1[maxn][maxn], g2[maxn][maxn]; std::vector<std::pair<std::pair<int, int>, std::pair<int, int> > > ans1, ans2; inline std::pair<std::pair<int, int>, std::pair<int, int> > rev( int u, int v, int n, bool g[maxn][maxn]) { int indx = 0; for (register int i = 1; i <= n; ++i) if (g[u][i] && g[v][i]) p[++indx] = i; g[u][v] = g[v][u] = 0, g[p[1]][p[2]] = g[p[2]][p[1]] = 1; return std::make_pair(std::make_pair(u, v), std::make_pair(p[1], p[2])); } inline void work( int n, bool g[maxn][maxn], std::vector<std::pair<std::pair<int, int>, std::pair<int, int> > > &res) { for (register int i = 2; i <= n; ++i) { for (register int j = n; j > 1; --j) { if (j == i || j == pre[i] || j == nxt[i]) continue; if (g[i][j]) res.push_back(rev(i, j, n, g)); } } } signed main() { int n, u, v; fin >> n; for (register int i = 1; i <= n; ++i) pre[i] = i - 1, nxt[i] = i + 1; pre[1] = n, nxt[n] = 1; for (register int i = 1; i <= n; ++i) g1[i][pre[i]] = g1[i][nxt[i]] = g2[i][pre[i]] = g2[i][nxt[i]] = 1; for (register int i = 1; i <= n - 3; ++i) fin >> u >> v, g1[u][v] = g1[v][u] = 1; for (register int i = 1; i <= n - 3; ++i) fin >> u >> v, g2[u][v] = g2[v][u] = 1; work(n, g1, ans1), work(n, g2, ans2); std::cout << ans1.size() + ans2.size() << n ; for (register int i = 0; i < ans1.size(); ++i) std::cout << ans1[i].first.first << << ans1[i].first.second << n ; for (register int i = ans2.size() - 1; i >= 0; --i) std::cout << ans2[i].second.first << << ans2[i].second.second << n ; return 0; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression evaluates to a value outside the range specified by parameters min and max");
end
end
end
assign fire_2state_1 = ((test_expr < min) || (test_expr > max));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
// REVISIT: update only if SANITY on?
prev_test_expr <= test_expr; // deliberately not reset
end
wire fire_cover_1, fire_cover_2, fire_cover_3;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("test_expr_at_min covered"); // corner
end
if (fire_cover_3) begin
ovl_cover_t("test_expr_at_max covered"); // corner
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == min));
assign fire_cover_3 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == max));
`endif // OVL_COVER_ON
|
#include <bits/stdc++.h> using namespace std; int n, m, i, x, y, res; vector<int> g[200200], o[200200]; bool u[3][200200], w[200200], ok = true; char r[200200]; void dfs(int i, int z) { u[z][i] = true; w[i] = true; for (int j = 0; j < g[i].size(); j++) { int k = g[i][j]; if (w[k]) ok = false; if (!u[z][k]) dfs(k, z); } w[i] = false; } void ofs(int i, int z) { u[z][i] = true; for (int j = 0; j < o[i].size(); j++) { int k = o[i][j]; if (!u[z][k]) ofs(k, z); } } int main() { scanf( %d%d , &n, &m); for (i = 0; i < m; i++) { scanf( %d%d , &x, &y); g[x].push_back(y); o[y].push_back(x); } for (i = 1; ok && i <= n; i++) if (!u[0][i]) dfs(i, 0); if (!ok) { puts( -1 ); return 0; } memset(u, 0, sizeof(u)); for (i = 1; i <= n; i++) if (!u[0][i] && !u[1][i] && !u[2][i]) { dfs(i, 0); ofs(i, 0); r[i - 1] = A ; res++; } else { r[i - 1] = E ; if (!u[1][i]) dfs(i, 1); if (!u[2][i]) ofs(i, 2); } printf( %d n , res); puts(r); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, k; cin >> n >> k; int ans = n; for (int i = 1; i * i <= n; i++) if (n % i == 0) { if (i <= k) ans = min(ans, n / i); if (n / i <= k) ans = min(ans, i); } cout << ans << endl; } }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) const int inf = 0x3f3f3f3f; const long double PI = acos(-1); using namespace std; const int N = 1e5 + 10; int t, n, ans; char s[N]; int solve() { for (char c = a ; c <= z ; c++) { int temp = 0, i = 0, j = n - 1; while (i < j) { if (s[i] != s[j]) { if (s[i] == c) { i++, temp++; } else if (s[j] == c) { j--, temp++; } else { temp = n + 1; break; } } else { i++, j--; } } ans = min(ans, temp); } if (ans == n + 1) return -1; else return ans; } int main() { ios::sync_with_stdio(false), cin.tie(0); cin >> t; while (t--) { cin >> n; for (int i = 0; i < n; i++) cin >> s[i]; ans = inf; cout << solve() << endl; } }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file BRAM_larg.v when simulating
// the core, BRAM_larg. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module BRAM_larg(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
input clka;
input [0 : 0] wea;
input [11 : 0] addra;
input [31 : 0] dina;
input clkb;
input [11 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a[102][102]; int b, c, i, j, n, m; cin >> n >> m; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) cin >> a[i][j]; b = n; while (b % 2 == 0 && b / 2 != 0) { c = 0; for (i = 1; i <= b / 2; i++) for (j = 1; j <= m; j++) if (a[i][j] != a[b - i + 1][j]) c = 1; if (c == 1) break; b = b / 2; } printf( %d n , b); return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, M; vector<vector<char>> v; bool Mastervis[50][50]; bool vis[50][50]; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; bool isCyc(int r, int c, int pr, int pc) { if (vis[r][c]) return true; vis[r][c] = true; Mastervis[r][c] = true; int nr, nc; for (int k = 0; k < 4; k++) { nr = r + dy[k]; nc = c + dx[k]; if (nr >= 0 && nr < N && nc >= 0 && nc < M && !(nr == pr && nc == pc)) { if (v[r][c] == v[nr][nc]) { if (isCyc(nr, nc, r, c)) return true; } } } return false; } int main() { string s; cin >> N >> M; v.resize(N); memset(Mastervis, false, 50 * 50 * sizeof(bool)); for (int i = 0; i < N; i++) { cin >> s; for (int j = 0; j < M; j++) { v[i].push_back(s[j]); } } for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { if (!Mastervis[i][j]) { memset(vis, false, 50 * 50 * sizeof(bool)); if (isCyc(i, j, -2, -2)) { cout << Yes ; return 0; } } } } cout << No ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int fun(string x) { if (x.size() > 7) return 1000005; int n = 0; for (int i = 0; i < x.size(); i++) { n *= 10; n += (x[i] - 0 ); } return n; } bool f(string s) { if (s.size() > 1 && s[0] == 0 || s.size() > 7) return false; else return true; } int main() { string s; cin >> s; int n = s.size(); int a1, a2, a3, mx = 0; bool d = false; for (int i = 1; i < s.size() - 1; i++) { for (int j = i + 1; j < s.size(); j++) { if (f(s.substr(0, i)) && f(s.substr(i, j - i)) && f(s.substr(j, s.size() - j))) { if (fun(s.substr(0, i)) <= 1000000 && fun(s.substr(i, j - i)) <= 1000000 && fun(s.substr(j, s.size() - j)) <= 1000000) { a1 = fun(s.substr(0, i)); a2 = fun(s.substr(i, j - i)); a3 = fun(s.substr(j, s.size() - j)); mx = max((a1 + a2 + a3), mx); d = true; } } } } if (d) cout << mx << n ; else cout << -1 n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__XOR3_PP_BLACKBOX_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long double Fictive = 5e18; struct str { long long k, b; long double eval(long double x) { return x * (long double)k + b; } }; vector<str> vec; inline long double get_x(str fi, str se) { return (long double)(fi.b - se.b) / (long double)(se.k - fi.k); } inline bool to_erase(str l1, str l2, str l3) { long double x = get_x(l1, l3); return (l2.eval(x) >= l3.eval(x)); } inline void add_line(str l) { while (vec.size() >= 2 && to_erase(vec[vec.size() - 2], vec.back(), l)) vec.pop_back(); vec.push_back(l); } inline long long get(long long x) { int l = 0, r = vec.size() - 1; while (l < r) { int mid = (l + r) >> 1; if (vec[mid].eval(x) >= vec[mid + 1].eval(x)) l = mid + 1; else r = mid; } return vec[l].eval(x); } int n, a[100100], b[100100]; long long dp[100100]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= n; i++) { cin >> b[i]; } dp[1] = 0; add_line({b[1], 0}); for (int i = 2; i <= n; i++) { dp[i] = 1e15; dp[i] = get(a[i]); add_line({b[i], dp[i]}); } cout << dp[n]; }
|
#include <bits/stdc++.h> using namespace std; const int D = 505; const int N = 5005; pair<int, int> pre[D][N]; int ans[D][N]; void solve() { memset(pre, -1, sizeof(pre)); memset(ans, -1, sizeof(ans)); int d, s; cin >> d >> s; queue<pair<int, int> > que; que.push(pair<int, int>(0, 0)); vector<int> vec; while (!que.empty()) { pair<int, int> u = que.front(); que.pop(); if (u.first == 0 && u.second == s) { pair<int, int> cur = u; while (!(cur.first == 0 && cur.second == 0)) { vec.push_back(ans[cur.first][cur.second]); cur = pre[cur.first][cur.second]; } break; } for (int i = 0; i <= 9; i++) { pair<int, int> v = pair<int, int>((u.first * 10 + i) % d, u.second + i); if (v.second <= s && ans[v.first][v.second] == -1) { ans[v.first][v.second] = i; pre[v.first][v.second] = u; que.push(v); } } } if (!vec.size()) printf( -1 n ); else { reverse(vec.begin(), vec.end()); for (auto i : vec) putchar(i + 0 ); printf( n ); } } int main() { solve(); return 0; }
|
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module dlog_video(
//////////// CLOCK //////////
OSC_50_B3B,
OSC_50_B4A,
OSC_50_B5B,
OSC_50_B8A,
//////////// Si5338 //////////
SI5338_SCL,
SI5338_SDA,
//////////// Temperature //////////
TEMP_CS_n,
TEMP_DIN,
TEMP_DOUT,
TEMP_SCLK,
//////////// VGA //////////
VGA_B,
VGA_BLANK_n,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_n,
VGA_VS
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input OSC_50_B3B;
input OSC_50_B4A;
input OSC_50_B5B;
input OSC_50_B8A;
//////////// Si5338 //////////
output SI5338_SCL;
inout SI5338_SDA;
//////////// Temperature //////////
output TEMP_CS_n;
output TEMP_DIN;
input TEMP_DOUT;
output TEMP_SCLK;
//////////// VGA //////////
output [7:0] VGA_B;
output VGA_BLANK_n;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_n;
output VGA_VS;
//=======================================================
// REG/WIRE declarations
//=======================================================
assign SI5338_SCL = 0;
assign TEMP_CS_n = 1;
assign TEMP_DIN = 0;
assign TEMP_SCLK = 0;
assign SI5338_SDA = 1'bz;
//=======================================================
// Structural coding
//=======================================================
reg [7:0] ResetCnt = 0;
reg ResetN = 0;
always@(posedge OSC_50_B3B)
begin
if(ResetCnt != 8'd10) begin
ResetN <= 0;
ResetCnt <= ResetCnt + 8'd1;
end else
ResetN <= 1;
end
dv_main u0 (
OSC_50_B3B, ResetN,
VGA_CLK, VGA_HS, VGA_VS, VGA_SYNC_n, VGA_BLANK_n,
VGA_R, VGA_G, VGA_B
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ebc_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:29 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ebc_e.v,v 1.1 2004/04/06 10:50:26 wig Exp $
// $Date: 2004/04/06 10:50:26 $
// $Log: inst_ebc_e.v,v $
// Revision 1.1 2004/04/06 10:50:26 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ebc_e
//
// No `defines in this module
module inst_ebc_e
//
// Generated module inst_ebc
//
(
nreset,
nreset_s
);
// Generated Module Inputs:
input nreset;
input nreset_s;
// Generated Wires:
wire nreset;
wire nreset_s;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ebc_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3_SYMBOL_V
`define SKY130_FD_SC_MS__OR3_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3_SYMBOL_V
|
#include <bits/stdc++.h> const long long int MOD = 1e9 + 7; using namespace std; constexpr int mul(int a, int b) { return 1LL * a * b % MOD; } template <typename... T> constexpr int mul(int a, int b, T... t) { return mul(mul(a, b), t...); } template <class T> inline T Min(const T &a, const T &b) { return a < b ? a : b; } template <class T> inline T Max(const T &a, const T &b) { return a < b ? b : a; } inline void inc(int &x, int &v, int &mod) { x += v; if (x >= mod) x -= mod; } inline void dec(int &x, int &v, int &mod) { x -= v; if (x < 0) x += mod; } inline int read() { char ch = getchar(); int x = 0, f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } inline long long int readl() { char ch = getchar(); long long int x = 0, f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int T[200010 << 2][9], MIN[200010 << 2][9], minsum[200010 << 2][9]; int a[200010]; int res1, res2; void pushup(int now, int k) { T[now][k] = T[now << 1][k] + T[now << 1 | 1][k]; MIN[now][k] = Min(MIN[now << 1][k], MIN[now << 1 | 1][k]); minsum[now][k] = Min(minsum[now << 1][k], minsum[now << 1 | 1][k]); if (T[now << 1][k] != 0 && T[now << 1 | 1][k] != 0) minsum[now][k] = Min(minsum[now][k], MIN[now << 1][k] + MIN[now << 1 | 1][k]); } void build(int l, int r, int now, int k) { if (l == r) { int tmp = a[l]; for (int i = 0; i < k; i++) { tmp /= 10; } minsum[now][k] = MIN[now][k] = 2e9; if (tmp % 10 != 0) { MIN[now][k] = a[l]; T[now][k] = 1; } else T[now][k] = 0; return; } int mid = (l + r) >> 1; build(l, mid, now << 1, k); build(mid + 1, r, now << 1 | 1, k); pushup(now, k); } int query(int L, int R, int l, int r, int now, int k) { if (L <= l && r <= R) { return T[now][k]; } int mid = (l + r) >> 1; int ans = 0; if (L <= mid) ans += query(L, R, l, mid, now << 1, k); if (mid < R) ans += query(L, R, mid + 1, r, now << 1 | 1, k); return ans; } int query2(int L, int R, int l, int r, int now, int k) { if (L <= l && r <= R) { if (MIN[now][k] < res1) { res2 = res1; res1 = MIN[now][k]; } else if (MIN[now][k] < res2) { res2 = MIN[now][k]; } return minsum[now][k]; } int mid = (l + r) >> 1; int ans1 = 2e9, ans2 = 2e9; if (L <= mid) ans1 = query2(L, R, l, mid, now << 1, k); if (mid < R) ans2 = query2(L, R, mid + 1, r, now << 1 | 1, k); return Min(ans1, ans2); } void update(int pos, int C, int l, int r, int now, int k) { if (l == r) { int tmp = C; for (int i = 0; i < k; i++) tmp /= 10; minsum[now][k] = MIN[now][k] = 2e9; if (tmp % 10 != 0) { MIN[now][k] = C; T[now][k] = 1; } else T[now][k] = 0; return; } int mid = (l + r) >> 1; if (pos <= mid) update(pos, C, l, mid, now << 1, k); else update(pos, C, mid + 1, r, now << 1 | 1, k); pushup(now, k); } int main() { int n = read(), q = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 0; i < 9; i++) { build(1, n, 1, i); } while (q--) { int op = read(), a = read(), b = read(); if (op == 1) { for (int i = 0; i < 9; i++) update(a, b, 1, n, 1, i); } else { bool tag = true; int sum = 2e9; for (int i = 0; i < 9; i++) { int cnt = query(a, b, 1, n, 1, i); if (cnt > 1) { res1 = res2 = 1e9; sum = Min(Min((res1 + res2), sum), query2(a, b, 1, n, 1, i)); tag = false; } } if (tag) { printf( -1 n ); } else { printf( %d n , sum); } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_TB_V
`define SKY130_FD_SC_LP__SDFXBP_TB_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfxbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_TB_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long int; int ara[200005], dist[200005], ans[200005]; vector<int> even, odd, ad[200005]; bool vis[200005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, i, j; cin >> n; for (i = 1; i <= n; i++) { cin >> ara[i]; if (ara[i] & 1) odd.push_back(i); else even.push_back(i); if (i - ara[i] >= 1) ad[i - ara[i]].push_back(i); if (i + ara[i] <= n) ad[i + ara[i]].push_back(i); } memset(dist, -1, sizeof dist); queue<int> q; for (i = 0; i < (int)even.size(); i++) { q.push(even[i]); dist[even[i]] = 0; vis[even[i]] = true; } while (!q.empty()) { int u = q.front(); q.pop(); for (i = 0; i < (int)ad[u].size(); i++) { int v = ad[u][i]; if (!vis[v]) { vis[v] = true; q.push(v); dist[v] = dist[u] + 1; if (ara[v] & 1) ans[v] = dist[v]; } } } memset(vis, false, sizeof vis); memset(dist, -1, sizeof dist); for (i = 0; i < (int)odd.size(); i++) { q.push(odd[i]); dist[odd[i]] = 0; vis[odd[i]] = true; } while (!q.empty()) { int u = q.front(); q.pop(); for (i = 0; i < (int)ad[u].size(); i++) { int v = ad[u][i]; if (!vis[v]) { vis[v] = true; q.push(v); dist[v] = dist[u] + 1; if (ara[v] % 2 == 0) ans[v] = dist[v]; } } } for (i = 1; i <= n; i++) { if (!ans[i]) ans[i] = -1; cout << ans[i] << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int him(long long int a, long long int n) { long long int ans = 1; while (n) { if (n % 2 != 0) { ans = ((ans) * (a)); } a = ((a) * (a)); n = n / 2; } return ans; } int main() { long long int t; cin >> t; while (t--) { long long int n; cin >> n; if (n == 1 || n == 2) cout << 0 << endl; else cout << n - 2 << endl; } }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using vvi = vector<vi>; using vll = vector<ll>; using vvll = vector<vll>; using vb = vector<bool>; using vd = vector<double>; using vs = vector<string>; using pii = pair<int, int>; using pll = pair<ll, ll>; using pdd = pair<double, double>; using vpii = vector<pii>; using vvpii = vector<vpii>; using vpll = vector<pll>; using vvpll = vector<vpll>; using vpdd = vector<pdd>; using vvpdd = vector<vpdd>; template <typename T> void ckmin(T& a, const T& b) { a = min(a, b); } template <typename T> void ckmax(T& a, const T& b) { a = max(a, b); } mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); namespace __input { template <class T1, class T2> void re(pair<T1, T2>& p); template <class T> void re(vector<T>& a); template <class T, size_t SZ> void re(array<T, SZ>& a); template <class T> void re(T& x) { cin >> x; } void re(double& x) { string t; re(t); x = stod(t); } template <class Arg, class... Args> void re(Arg& first, Args&... rest) { re(first); re(rest...); } template <class T1, class T2> void re(pair<T1, T2>& p) { re(p.first, p.second); } template <class T> void re(vector<T>& a) { for (int i = 0; i < (int((a).size())); i++) re(a[i]); } template <class T, size_t SZ> void re(array<T, SZ>& a) { for (int i = 0; i < (SZ); i++) re(a[i]); } } // namespace __input using namespace __input; namespace __output { template <class T1, class T2> void pr(const pair<T1, T2>& x); template <class T, size_t SZ> void pr(const array<T, SZ>& x); template <class T> void pr(const vector<T>& x); template <class T> void pr(const deque<T>& x); template <class T> void pr(const set<T>& x); template <class T1, class T2> void pr(const map<T1, T2>& x); template <class T> void pr(const T& x) { cout << x; } template <class Arg, class... Args> void pr(const Arg& first, const Args&... rest) { pr(first); pr(rest...); } template <class T1, class T2> void pr(const pair<T1, T2>& x) { pr( { , x.first, , , x.second, } ); } template <class T, bool pretty = true> void prContain(const T& x) { if (pretty) pr( { ); bool fst = 1; for (const auto& a : x) pr(!fst ? pretty ? , : : , a), fst = 0; if (pretty) pr( } ); } template <class T> void pc(const T& x) { prContain<T, false>(x); pr( n ); } template <class T, size_t SZ> void pr(const array<T, SZ>& x) { prContain(x); } template <class T> void pr(const vector<T>& x) { prContain(x); } template <class T> void pr(const deque<T>& x) { prContain(x); } template <class T> void pr(const set<T>& x) { prContain(x); } template <class T1, class T2> void pr(const map<T1, T2>& x) { prContain(x); } void ps() { pr( n ); } template <class Arg> void ps(const Arg& first) { pr(first); ps(); } template <class Arg, class... Args> void ps(const Arg& first, const Args&... rest) { pr(first, ); ps(rest...); } } // namespace __output using namespace __output; namespace __numeric { template <typename T> typename enable_if<is_integral<T>::value, T>::type floor(T n, T d) { assert(d != 0); if (d < 0) tie(n, d) = make_pair(-n, -d); return n / d - ((n < 0) && (n % d)); } template <typename T> typename enable_if<is_integral<T>::value, T>::type ceil(T n, T d) { assert(d != 0); if (d < 0) tie(n, d) = make_pair(-n, -d); return n / d + ((n > 0) && (n % d)); } }; // namespace __numeric using namespace __numeric; namespace __algorithm { template <typename T> void dedup(vector<T>& v) { sort((v).begin(), (v).end()); v.erase(unique((v).begin(), (v).end()), v.end()); } template <typename T> typename vector<T>::iterator find(vector<T>& v, const T& x) { auto it = lower_bound((v).begin(), (v).end(), x); return it != v.end() && *it == x ? it : v.end(); } template <typename T> size_t index(vector<T>& v, const T& x) { auto it = find(v, x); assert(it != v.end() && *it == x); return it - v.begin(); } template <typename C, typename T, typename OP> vector<T> prefixes(const C& v, T id, OP op) { vector<T> r(int((v).size()) + 1, id); for (int i = 0; i < (int((v).size())); i++) r[i + 1] = op(r[i], v[i]); return r; } template <typename C, typename T, typename OP> vector<T> suffixes(const C& v, T id, OP op) { vector<T> r(int((v).size()) + 1, id); for (int i = (int((v).size())) - 1; i >= 0; i--) r[i] = op(v[i], r[i + 1]); return r; } } // namespace __algorithm using namespace __algorithm; #pragma GCC diagnostic push #pragma GCC diagnostic ignored -Wunused-parameter struct monostate { friend istream& operator>>(istream& is, const monostate& ms) { return is; } friend ostream& operator<<(ostream& os, const monostate& ms) { return os; } friend monostate operator+(const monostate& a, const monostate& b) { return a; } } ms; #pragma GCC diagnostic pop namespace __io { void setIn(string second) { freopen(second.c_str(), r , stdin); } void setOut(string second) { freopen(second.c_str(), w , stdout); } void setIO(string second = ) { ios_base::sync_with_stdio(0); cin.tie(0); cout << fixed << setprecision(15); if (int((second).size())) { setIn(second + .in ), setOut(second + .out ); } } } // namespace __io using namespace __io; struct union_find { struct node { int par, rnk, size; node(int id = 0) : par(id), rnk(0), size(1) {} }; vector<node> uf; union_find(int N = 0) : uf(N) { for (int i = 0; i < N; i++) uf[i] = node(i); } int rep(int i) { if (i != uf[i].par) uf[i].par = rep(uf[i].par); return uf[i].par; } bool unio(int a, int b) { a = rep(a), b = rep(b); if (a == b) return false; if (uf[a].rnk < uf[b].rnk) swap(a, b); uf[b].par = a; uf[a].size += uf[b].size; if (uf[a].rnk == uf[b].rnk) uf[a].rnk++; return true; } node& operator[](int i) { return uf[rep(i)]; } friend void pr(const union_find& u) { pr( { ); bool first = 1; for (int i = 0; i < int((u.uf).size()); i++) if (u.uf[i].par == i) { if (!first) pr( , ); else first = 0; pr( [ , i, | rank= , u.uf[i].rnk, size= , u.uf[i].size, ] ); } pr( } ); } }; const int MAXB = 18; const int MAXV = 1 << MAXB; int ct[MAXV]; int main() { setIO(); int N; re(N); for (int i = 0; i < (N); i++) { int v; re(v); ct[v]++; } ll ans = 0; for (int v = 0; v < (MAXV); v++) { ans -= ll(v) * ct[v]; } union_find uf(MAXV + 1); for (int sum = (MAXV)-1; sum >= 0; sum--) { for (int v1 = sum, v2 = 0; v1 > v2; v1 = (v1 - 1) & sum, v2 = sum ^ v1) { if (ct[v1] && ct[v2]) { if (uf.unio(v1, v2)) { ans += ll(ct[v1] + ct[v2] - 1) * sum; ct[v1] = 1; ct[v2] = 1; } } } if (ct[sum] && uf.unio(MAXV, sum)) ans += ll(ct[sum]) * sum; } ps(ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, ms, type[5005], dp[5005]; int main() { scanf( %d %d , &n, &ms); for (int i = 1; i <= n; i++) { double x; scanf( %d %lf , type + i, &x); } for (int i = 1; i <= n; i++) { int j = type[i]; for (int k = j; k >= 1; k--) { dp[j] = max(dp[j], 1 + dp[k]); } } int ans = 0; for (int i = 1; i <= n; i++) { ans = max(ans, dp[i]); } printf( %d n , n - ans); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [2:0] in;
wire a,y,y_fixed;
wire b = in[0];
wire en = in[1];
pullup(a);
ChildA childa ( .A(a), .B(b), .en(en), .Y(y),.Yfix(y_fixed) );
initial in=0;
// Test loop
always @ (posedge clk) begin
in <= in + 1;
$display ( "a %d b %d en %d y %d yfix: %d)" , a, b, en, y, y_fixed);
if (en) begin
// driving b
// a should be b
// y and yfix should also be b
if (a!=b || y != b || y_fixed != b) begin
$display ( "Expected a %d y %b yfix %b" , a, y, y_fixed);
$stop;
end
end else begin
// not driving b
// a should be 1 (pullup)
// y and yfix shold be 1
if (a!=1 || y != 1 || y_fixed != 1) begin
$display( "Expected a,y,yfix == 1");
$stop;
end
end
if (in==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module ChildA(inout A, input B, input en, output Y, output Yfix);
// workaround
wire a_in = A;
ChildB childB(.A(A), .Y(Y));
assign A = en ? B : 1'bz;
ChildB childBfix(.A(a_in),.Y(Yfix));
endmodule
module ChildB(input A, output Y);
assign Y = A;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Universidad De Costa Rica
// Engineer: Joshua Torres M (A76478)
//
// Create Date: 15:27:21 09/06/2015
// Design Name:
// Module Name: ram
// Project Name: Diseno de una Cola/Pila sincronicas
// Description:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ram (dat_i, dat_o, adr_wr_i, adr_rd_i, we_i, rde_i, clk );
//Parameters
parameter dat_width = 32;
parameter adr_width = 11;
parameter mem_size = 2048;
//Inputs, Ouputs
input [dat_width-1:0] dat_i;
input [adr_width-1:0] adr_rd_i;
input [adr_width-1:0] adr_wr_i;
input we_i;
input rde_i;
input clk;
output reg [dat_width-1:0] dat_o;
//Internal circuitry
reg [dat_width-1:0] ram [0:mem_size - 1];
always @ (posedge clk) begin
if (we_i)
ram[adr_wr_i] <= dat_i;
end
always @ (posedge clk) begin
if (rde_i)
dat_o <= ram[adr_rd_i];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const int INF = 1e9; const long long IINF = 1e18; const int dx[4] = {1, 0, -1, 0}; const int dy[4] = {0, 1, 0, -1}; const char dir[4] = { D , R , U , L }; template <typename T> istream &operator>>(istream &is, vector<T> &v) { for (T &x : v) is >> x; return is; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { for (int i = 0; i < v.size(); ++i) { os << v[i] << (i + 1 == v.size() ? n : ); } return os; } template <typename T, typename U> ostream &operator<<(ostream &os, const pair<T, U> &p) { cout << ( << p.first << , << p.second << ) ; return os; } template <class T> inline bool chmin(T &a, T b) { if (a > b) { a = b; return true; } return false; } template <class T> inline bool chmax(T &a, T b) { if (a < b) { a = b; return true; } return false; } void solve(long long n) { long long m = n; vector<int> convert; while (3 <= m) { convert.emplace_back(m % 3); m /= 3; } convert.emplace_back(m); convert.emplace_back(0); int d = convert.size(), most; for (most = d - 1; most >= 0; --most) { if (convert[most] == 2) break; } if (most < 0) { cout << n << n ; return; } for (int i = 0; i < most; ++i) convert[i] = 0; for (int i = most; i < d; ++i) { if (convert[i] == 2) convert[i] = 0, convert[i + 1] += 1; else if (convert[i] == 3) convert[i] = 0, convert[i + 1] + -1; } long long po = 1, ans = 0; for (int i = 0; i < d; ++i) { ans += po * convert[i]; po *= 3; } cout << ans << n ; } int main() { cin.tie(0); ios::sync_with_stdio(false); int t; cin >> t; for (; t--;) { long long n; cin >> n; solve(n); } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 20:36:12
// Design Name:
// Module Name: D_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module D_behavior_tb(
);
reg D, Clk;
wire Qa, Qb, Qc;
D_behavior DUT (.D(D), .Clk(Clk), .Qa(Qa), .Qb(Qb), .Qc(Qc));
initial begin
#180 $finish;
end
initial begin
Clk = 0; D = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 D = 1;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; D = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 D = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; D = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
#20;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function int mon_check();
`endif
import "DPI-C" function void dpi_print(input string somestring);
`ifdef VERILATOR_COMMENTS
`define PUBLIC_FLAT_RD /*verilator public_flat_rd*/
`define PUBLIC_FLAT_RW /*verilator public_flat_rw @(posedge clk)*/
`else
`define PUBLIC_FLAT_RD
`define PUBLIC_FLAT_RW
`endif
interface intf #(parameter int param `PUBLIC_FLAT_RD = 7);
localparam int lparam `PUBLIC_FLAT_RD = param + 1;
logic [7:0] bytesig `PUBLIC_FLAT_RD;
endinterface
module t (/*AUTOARG*/
// Inputs
input clk `PUBLIC_FLAT_RD,
// test ports
input [15:0] testin `PUBLIC_FLAT_RD,
output [23:0] testout `PUBLIC_FLAT_RW
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
reg onebit `PUBLIC_FLAT_RW;
reg [2:1] twoone `PUBLIC_FLAT_RW;
reg onetwo [1:2] `PUBLIC_FLAT_RW;
reg [2:1] fourthreetwoone[4:3] `PUBLIC_FLAT_RW;
reg [1:0] [1:0] twobytwo `PUBLIC_FLAT_RW;
int theint `PUBLIC_FLAT_RW;
integer status;
`ifdef IVERILOG
// stop icarus optimizing signals away
wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3] | twobytwo;
`endif
wire subin `PUBLIC_FLAT_RD;
wire subout `PUBLIC_FLAT_RD;
sub sub(.*);
// Test loop
initial begin
dpi_print("foo");
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef IVERILOG
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_get.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : t
module sub #(
parameter int subparam `PUBLIC_FLAT_RD = 2
) (
input subin `PUBLIC_FLAT_RD,
output subout `PUBLIC_FLAT_RD
);
intf the_intf();
endmodule : sub
|
#include <bits/stdc++.h> using namespace std; int brute(int s, int x) { int ans = 0; for (int i = 1; i <= s; ++i) for (int j = 1; j <= s; ++j) if (i + j == s && (i ^ j) == x) ++ans; return ans; } long long ways0(long long s, long long x) { if (s == x) return 2; return 0; } long long solve(long long s, long long x) { long long dp[60][2] = {}; if (s % 2 != x % 2) { return 0; } if (x & (1LL << 0)) { dp[0][0] = 2; } else { dp[0][0] = 1; dp[0][1] = 1; } for (int i = 1; i < 60; ++i) { if (x & (1LL << i)) { if (s & (1LL << i)) { dp[i][0] += 2 * dp[i - 1][0]; } else { dp[i][1] += 2 * dp[i - 1][1]; } } else { if (s & (1LL << i)) { dp[i][0] += dp[i - 1][1]; dp[i][1] += dp[i - 1][1]; } else { dp[i][0] += dp[i - 1][0]; dp[i][1] += dp[i - 1][0]; } } } return dp[59][0] - ways0(s, x); } int main() { long long s, x; cin >> s >> x; cout << solve(s, x) << n ; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; #define pb push_back #define endl n #define F first #define S second #define pp pop_back ll mod = 1e9+7; ll dp[200200][2]; ll st[200200]; ll n; ll rec(ll level,int curr){ if(st[level]==1||st[level]==0){ if(curr!=st[level])return 0; } if(level==n-1){ return 1; } if(dp[level][curr]!=-1)return dp[level][curr]; return dp[level][curr] = 1+rec(level+1,1-curr); } int main() { ios_base::sync_with_stdio(0);cin.tie(0);cout.tie(0); ll t;cin>>t; while(t--){ memset(dp,-1,sizeof(dp));memset(st,-1,sizeof(st)); string s;cin>>s; n = (ll)s.size(); for(ll i=0;i<n;i++){ if(s[i]== 1 ||s[i]== 0 ){st[i]=s[i]- 0 ;} else{ st[i]=3; } } ll ans = 0; for(int i=0;i<n;i++){ ans+=max(rec(i,1),rec(i,0)); } cout<<ans<<endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { unsigned long long n, i, j, sum, k, temp; scanf( %llu , &n); unsigned long long a[n]; for (i = 0; i < n; i++) { scanf( %llu , &a[i]); } sum = 0; sort(a, a + n); k = n / 2; for (i = 0; i < k; i++) { temp = (a[i] + a[n - 1 - i]); sum += (temp * temp); } printf( %llu n , sum); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLXTN_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLXTN_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlxtn (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLXTN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 50; int n, p, first[N], second[N]; double tmin = 1e9; pair<double, int> d[N]; bool ok(double x) { double tp = x * p; for (int i = 0; i < n; ++i) { tp -= max(first[i] * x - second[i], 0.0); } return tp >= 0; } int main() { cin.sync_with_stdio(0); cin >> n >> p; for (int i = 0; i < n; ++i) cin >> first[i] >> second[i]; double lo = 0, hi = 1e20, mid; if (ok(hi)) { printf( -1 ); } else { for (int i = 0; i < 1000; ++i) { mid = (lo + hi) / 2; if (ok(mid)) lo = mid; else hi = mid; } printf( %.6f , mid); } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:34:40 05/17/2015
// Design Name: Main
// Module Name: C:/Users/dagosttv.ROSE-HULMAN/Documents/School/ECE/ECE398/CAN-Bus-Controller-/Main_test.v
// Project Name: CAN_Controller
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Main_test;
// Inputs
assign CAN_RX = CAN_TX;
reg RESET;
reg CLOCK_SIGNAL_IN;
reg send_data;
reg [7:0] transmit_data;
// Outputs
wire CAN_TX;
// Instantiate the Unit Under Test (UUT)
Main uut (
.CAN_TX(CAN_TX),
.CAN_RX(CAN_RX),
.RESET(RESET),
.CLOCK_SIGNAL_IN(CLOCK_SIGNAL_IN),
.send_data(send_data),
.transmit_data(transmit_data)
);
initial begin
// Initialize Inputs
RESET = 1;
CLOCK_SIGNAL_IN = 0;
send_data = 0;
transmit_data = 8'b11100011;
// Wait 100 ns for global reset to finish
#100;
#100 RESET = 0;
#1000 send_data = 1;
#100000 $stop;
// Add stimulus here
end
always #10 CLOCK_SIGNAL_IN = ~CLOCK_SIGNAL_IN;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, i; string s; int main() { char c; cin >> s; i = 0; while (s[i] < 80) { n *= 10; n += s[i] - 48; i++; } c = s[i]; if (n % 4 == 1) m = (n + 1) / 2; if (n % 4 == 2) m = (n + 2) / 2; if (n % 4 == 3) m = (n - 1) / 2; if (n % 4 == 0) m = n / 2; m--; m *= 6; m += n - 1; if (n % 4 == 0) m -= 2; if (n % 4 == 3) m -= 2; if (c == f ) m++; if (c == e ) m += 2; if (c == d ) m += 3; if (c == a ) m += 4; if (c == b ) m += 5; if (c == c ) m += 6; cout << m; }
|
#include <bits/stdc++.h> using namespace std; using db = long double; using pll = pair<long long, long long>; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t, i, x, j, y, z, k, n; long long tt; cin >> tt; for (long long _tt = 0; _tt < tt; _tt++) { cin >> n; z = 0; while (n != 1) { if (n % 6 == 0) n /= 6; else if ((n * 2) % 6 == 0) n *= 2; else { z = -1; break; } z++; } cout << z << n ; } }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:28:52 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xlconcat_0_0_sim_netlist.v
// Design : zqynq_lab_1_design_xlconcat_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_xlconcat_0_0,xlconcat_v2_1_1_xlconcat,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(In0,
In1,
dout);
input [0:0]In0;
input [0:0]In1;
output [1:0]dout;
wire [0:0]In0;
wire [0:0]In1;
assign dout[1] = In1;
assign dout[0] = In0;
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> char a[1111]; int main() { int i, j, k, l, s, flag; while (~scanf( %s , a + 2)) { a[0] = a[1] = 0 ; s = 0; l = strlen(a); flag = 0; for (i = 0; i < l - 2; i++) { if (flag) break; for (j = i + 1; j < l - 1; j++) { if (flag) break; for (k = j + 1; k < l; k++) { s = (a[i] - 0 ) * 100 + (a[j] - 0 ) * 10 + a[k] - 0 ; if (s % 8 == 0) { flag = 1; break; } } } } if (flag) printf( YES n%d n , s); else printf( NO n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, len1, len2, ans; string s; int main() { cin >> n; getline(cin, s), getline(cin, s); while (len1 < s.size()) { len2 = len1 + n - 1; while (len2 > len1) if (s[len2] == . || s[len2] == ? || s[len2] == ! ) { len1 = len2 + 2; break; } else len2--; if (len2 == len1) return puts( Impossible ), 0; ans++; } cout << ans << endl; }
|
(*******************************************************************)
(* Copyright 2010 Alexandre Pilkiewicz *)
(* < > *)
(* This program is free software. It comes without any warranty, *)
(* to the extent permitted by applicable law. You can redistribute *)
(* it and/or modify it under the terms of the WTFPL, Version 2, as *)
(* published by Sam Hocevar. See http://sam.zoy.org/wtfpl/COPYING *)
(* for more details. *)
(*******************************************************************)
(* this small example suppose that you have included insert-cases.el
in your .emacs. If you have not, you can of course run the file,
but reproducing it might be a bit painful ! *)
Add Rec LoadPath "../theories" as Case_Tactics.
Add ML Path "../src".
Require Import Case_Tactics.
(* the (S* )Case tactics, by Aaron Bohannon
http://www.cis.upenn.edu/~bcpierce/sf/Basics.html#lab27
*)
(* The Case tactic allows you to add "comments" in your code, telling
which subcase you are dealing with*)
Goal (True -> 1 = 1 -> False) -> False.
Proof.
intro H.
apply H.
Case "True".
(* Notice that the hypothesis have been modified *)
constructor.
Case "1 = 1".
reflexivity.
Qed.
(* But it is more powerful than simple comments. If you try to enter a
new case before finishing the current one, it fails. So imagine
that the goal changes slightly *)
Inductive pack := Pack: True -> pack.
Goal (pack -> 1 = 1 -> False) -> False.
Proof.
intro H.
apply H.
Case "True".
constructor.
(* The subgoal has not been eliminated. Try to un-comment the next line *)
(*Case "1 = 1".*)
(* It fails with "Tactic failure: because we are working on a
different case."*)
constructor.
Case "1 = 1".
reflexivity.
Qed.
(* This helps a lot with maintainability: you know precisely which
sub-goal fails *)
(* Inductive types *)
(* when working with inductive types, it is recommended to write a
tactic that automatically apply the proper (S* )Case tactic to each
subgoal when performing a destruction or induction
http://www.cis.upenn.edu/~bcpierce/sf/Rel.html#lab260
*)
Inductive pack2 (A:Prop) : Prop :=
|Pack1: (A /\ True)-> pack2 A
|Pack2: A -> pack2 A.
Tactic Notation "pack2_cases" tactic(first) tactic(c) :=
first;
[ c "Pack1" | c "Pack2"].
Goal forall A, pack2 A -> A.
Proof.
intros A PACK2.
pack2_cases (destruct PACK2) Case.
(* notice that Case := "Pack1" is already in the hypothesis. If you
are lazy, are using emacs and have added the insert_case.el in
your .emacs, just press C-c C-a C-q or C-c C-a C-z to copy it
directly *)
Case "Pack1".
destruct H. assumption.
Case "Pack2".
assumption.
Qed.
(* But this can quickly become tedious, especially if you are working
with big inductive (like this one
http://compcert.inria.fr/doc/html/Op.html#operation )
Here comes the goal of this contribution: automatically build such tactic.
*)
Goal forall n, n = n + 0.
Proof.
(* don't miss the ' at the end of induction' *)
induction' n; simpl.
(* Notice this is already in the goal *)
Case "O".
reflexivity.
(* and this too *)
Case "S".
f_equal. assumption.
Qed.
(*when you use an intro pattern, it is used to build nicer names for subgoals *)
Goal forall A B (f: A -> B) l, length l = length (List.map f l).
Proof.
intros A B f l.
induction' l as [| a l'].
Case "nil".
reflexivity.
Case "cons a l'".
simpl. f_equal. assumption.
Qed.
(* it also works with destruct' and case' *)
Goal forall n, n = 0 \/ n <> 0.
Proof.
destruct' n as [|n'].
Case "O".
left; reflexivity.
Case "S n'".
right. intro H. inversion H.
Qed.
Require Import List.
Goal forall l: list nat, l = nil \/ l = hd 0 l :: tl l.
Proof.
case' l as [|n l'] _eqn.
Case "nil".
left. reflexivity.
Case "cons n l'".
right. simpl. reflexivity.
Qed.
(* the library only defines induction', destruct' and case', because
those are the only one I use. But you can of course do the
same. The only tactic related to inductive that I do not know how
to deal with is the inversion tactic since it does not produce the
same number of goal. There is in fact a inversion' tactics, but it
fails every time some subgoals are automatically eliminated *)
(* the primed tactics don't always use the name of the
constructor. There are two special cases for or (\/) and sumbool
({}+{}) where the content of the hypothesis is put in the tag *)
Lemma nat_eq_dec : forall (n m: nat), {n = m} + {n <> m}.
Proof.
decide equality.
Qed.
Notation "x == y" := (nat_eq_dec x y) (at level 70, no associativity).
Tactic Notation "dest" constr(a) "==" constr(b) :=
(* the tactic cannot just return the string, it has to be stored in
some hypothesis *)
destruct' (a == b).
Tactic Notation "dest" "==" :=
match goal with
| H : context[?a == ?b] |- _ =>
dest a == b
| |- context[?a == ?b] =>
dest a == b
end.
Goal forall foo,
(if foo == 42 then
False
else
False
) -> False.
Proof.
intro. dest ==.
(* note that the notation for 42 is used *)
Case "foo = 42".
auto.
Case "foo <> 42".
auto.
Qed.
Goal forall foo bar baz,
(if foo == bar then
if bar == baz then
False
else
(foo <> baz -> False)
else
if bar == baz then
(foo <> baz -> False)
else
False
) -> False.
Proof.
intros foo bar baz H. repeat (dest ==); try assumption.
(* here the C-c C-a C-q command can be pretty handy *)
Case "foo = bar"; SCase "bar <> baz".
apply H. subst. assumption.
Case "foo <> bar"; SCase "bar = baz".
apply H. subst. assumption.
Qed.
(* it also works with bindings and when lemma needs to be reducesed *)
Definition true_imp_true:= forall (TRUE_in:True), True.
Lemma useless: forall (n:nat) (EQ:n = n) (TRUE_out:True), true_imp_true.
Proof. red. auto. Qed.
(* Other example *)
Axiom classicT : forall P:Prop, {P} + {~P}.
Notation "'_If' X 'then' Y 'else' Z" := (if classicT X then Y else Z) (at level 100).
Ltac case_if :=
match goal with
| |- _If ?P then _ else _ =>
destruct' (classicT P)
end.
Goal forall a: nat, _If a = 0 then 0 = a else 0 <> a.
Proof.
intro.
case_if.
Case "a = 0".
auto.
Case "a <> 0".
auto.
Qed.
(* another tactic defined in the ml library is the "string of foo in
H" tactic. It builds a coq string from any term, and put it in
H. The wraper string_of is easier to use, even if it is written in
CPS style *)
Ltac Case_Goal :=
match goal with
| |- ?G =>
string_of G (fun strG =>
fst_Case_tac strG)
end.
Goal (True /\ 1 = 1).
Proof.
split; Case_Goal.
Case "True".
constructor.
Case "1 = 1".
reflexivity.
Qed.
(* one might have noticed that notations were used with the string_of
tactic, but not with the induction' tactic.*)
(* to make the 'ed tactics use notation (this works only for
constructors without arguments for now), use *)
Set Notations With Case.
Goal forall n:nat, n >= 0.
Proof.
induction' n as [|n'].
Case "0". (* notice the 0 *)
auto.
Case "S n'".
auto.
Qed.
(* to get a string without notations, use string_of_without *)
Ltac Case_Goal' :=
match goal with
| |- ?G =>
string_of_without G (fun strG =>
fst_Case_tac strG)
end.
Goal (1 <= 2 /\ 1 <> 2).
Proof.
split; Case_Goal'.
Case "le (S O) (S (S O))".
constructor. constructor.
Case "not (eq (S O) (S (S O)))".
congruence.
Qed.
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_c
//
// Generated
// by: wig
// on: Thu Jun 29 16:41:09 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro ../../configuration.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_c.v,v 1.1 2006/07/04 09:54:10 wig Exp $
// $Date: 2006/07/04 09:54:10 $
// $Log: ent_c.v,v $
// Revision 1.1 2006/07/04 09:54:10 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_c
//
// No user `defines in this module
// Generated include statements
`include "include.h" // some include test
`define some_var somevalue
`include "include2.h"
module ent_c
//
// Generated Module inst_c
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_14;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_ca
ent_ca inst_ca (
.sig_14(sig_14) // Create connection for inst_c
);
// End of Generated Instance Port Map for inst_ca
// Generated Instance Port Map for inst_cb
ent_cb inst_cb (
.sig_14(sig_14) // Create connection for inst_c
);
// End of Generated Instance Port Map for inst_cb
endmodule
//
// End of Generated Module rtl of ent_c
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; long long read() { char ch = getchar(); long long x = 0, ff = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) ff = -ff; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x * ff; } void write(long long aa) { if (aa < 0) putchar( - ), aa = -aa; if (aa > 9) write(aa / 10); putchar(aa % 10 + 0 ); return; } long long n; long long a[200005]; long long tt[800005], tts[800005], lz[800005]; void up(long long rt) { tt[rt] = min(tt[rt << 1], tt[rt << 1 | 1]); if (tt[rt << 1] >= tt[rt << 1 | 1]) tts[rt] = tts[rt << 1 | 1]; else tts[rt] = tts[rt << 1]; return; } void bt(long long rt, long long ll, long long rr) { if (ll == rr) { tt[rt] = read(), tts[rt] = ll; return; } long long mid = (ll + rr) >> 1; bt(rt << 1, ll, mid); bt(rt << 1 | 1, mid + 1, rr); up(rt); return; } void push(long long rt) { if (!lz[rt]) return; tt[rt << 1] += lz[rt]; tt[rt << 1 | 1] += lz[rt]; lz[rt << 1] += lz[rt]; lz[rt << 1 | 1] += lz[rt]; lz[rt] = 0; return; } void update(long long rt, long long ll, long long rr, long long L, long long R, long long kk) { if (ll == L && rr == R) { tt[rt] += kk; lz[rt] += kk; return; } long long mid = (ll + rr) >> 1; push(rt); if (R <= mid) update(rt << 1, ll, mid, L, R, kk); else if (L > mid) update(rt << 1 | 1, mid + 1, rr, L, R, kk); else update(rt << 1, ll, mid, L, mid, kk), update(rt << 1 | 1, mid + 1, rr, mid + 1, R, kk); up(rt); return; } int main() { n = read(); bt(1, 1, n); for (long long i = 1; i <= n; ++i) { long long now = tts[1]; a[now] = i; update(1, 1, n, now, now, n * n); if (now < n) update(1, 1, n, now + 1, n, -i); } for (long long i = 1; i <= n; ++i, putchar( )) write(a[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int oo = 1000111000; int n, k, a[30300], f[222][30300][2], ans[222][30300]; int main() { int x; cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> x; a[i] = a[i - 1] + x; } for (int i = 0; i <= k; i++) for (int j = 0; j <= n; j++) f[i][j][0] = f[i][j][1] = -oo; for (int i = 1; i <= k; i++) for (int j = 1; j <= n; j++) { ans[i][j] = ans[i][j - 1]; f[i][j][0] = f[i][j - 1][0]; f[i][j][1] = f[i][j - 1][1]; for (int jj = 0; jj < j; jj++) { int sum = a[j] - a[jj]; int best = max(f[i - 1][jj][1] + sum, f[i - 1][jj][0] - sum); if (i == 1) best = 0; ans[i][j] = max(ans[i][j], best); f[i][j][0] = max(f[i][j][0], best + sum); f[i][j][1] = max(f[i][j][1], best - sum); } } cout << ans[k][n] << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, one, two[2], tmp, num, a[N]; bool flag, f[N]; int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } int main() { n = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= n; i++) { if (f[i]) continue; f[i] = true; if (a[i] == i) { one = i; continue; } if (a[a[i]] == i) { two[0] = i; two[1] = a[i]; f[a[i]] = true; continue; } tmp = a[i]; num = 1; while (!f[tmp]) { f[tmp] = true; num++; tmp = a[tmp]; } if (num & 1) flag = true; } if (one) { printf( YES n ); for (int i = 1; i <= n; i++) if (i != one) printf( %d %d n , one, i); return 0; } if (flag || !two[0]) { printf( NO ); return 0; } printf( YES n%d %d n , two[0], two[1]); memset(f, 0, sizeof(f)); for (int i = 1; i <= n; i++) { if (f[i] || i == two[0] || i == two[1]) continue; tmp = i; num = 0; while (!f[tmp]) { printf( %d %d n , two[num & 1], a[tmp]); num++; f[tmp] = true; tmp = a[tmp]; } } return 0; }
|
//hardware top level module
module sm_top
(
input clkIn,
input rst_n,
input [ 3:0 ] clkDevide,
input clkEnable,
output clk,
input [ 4:0 ] regAddr,
output [31:0 ] regData
);
//metastability input filters
wire [ 3:0 ] devide;
wire enable;
wire [ 4:0 ] addr;
sm_debouncer #(.SIZE(4)) f0(clkIn, clkDevide, devide);
sm_debouncer #(.SIZE(1)) f1(clkIn, clkEnable, enable);
sm_debouncer #(.SIZE(5)) f2(clkIn, regAddr, addr );
//cores
//clock devider
sm_clk_divider sm_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( devide ),
.enable ( enable ),
.clkOut ( clk )
);
//instruction memory
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom reset_rom(imAddr, imData);
sm_cpu sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( addr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData )
);
endmodule
//metastability input debouncer module
module sm_debouncer
#(
parameter SIZE = 1
)
(
input clk,
input [ SIZE - 1 : 0] d,
output reg [ SIZE - 1 : 0] q
);
reg [ SIZE - 1 : 0] data;
always @ (posedge clk) begin
data <= d;
q <= data;
end
endmodule
//tunable clock devider
module sm_clk_divider
#(
parameter shift = 16,
bypass = 0
)
(
input clkIn,
input rst_n,
input [ 3:0 ] devide,
input enable,
output clkOut
);
wire [31:0] cntr;
wire [31:0] cntrNext = cntr + 1;
sm_register_we r_cntr(clkIn, rst_n, enable, cntrNext, cntr);
assign clkOut = bypass ? clkIn
: cntr[shift + devide];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
`define STRINGIFY(x) `"x`"
module t (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input in; // inputs don't get flagged as undriven
output out; // outputs don't get flagged as unused
sub sub ();
// Check we don't warn about unused UDP signals
udp_mux2 udpsub (out, in, in, in);
// Check ignoreds mark as used
reg sysused;
initial $bboxed(sysused);
// Check file IO. The fopen is the "driver" all else a usage.
integer infile;
integer outfile;
initial begin
outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "w");
$fwrite(outfile, "1\n");
$fclose(outfile);
infile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/open.log"}, "r");
if ($fgetc(infile) != "1") begin end
end
wire _unused_ok;
endmodule
module sub;
wire pub /*verilator public*/; // Ignore publics
localparam THREE = 3;
endmodule
primitive udp_mux2 (q, a, b, s);
output q;
input a, b, s;
table
//a b s : out
1 ? 0 : 1 ;
0 ? 0 : 0 ;
? 1 1 : 1 ;
? 0 1 : 0 ;
0 0 x : 0 ;
1 1 x : 1 ;
endtable
endprimitive
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100 + 10, maxm = 10000 + 10; long long n, m, drt = 1, x = 1, y = 1, ans = 0, dis = 0, o = 0; char mat[maxn][maxm]; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) { mat[i][0] = # ; mat[i][m + 1] = # ; for (int j = 1; j <= m; j++) { cin >> mat[i][j]; } } while (x != n) { if (mat[x][y + drt] == # && o == 2) { break; } if (mat[x + 1][y] == . ) { x++; dis = 0; o = 0; } else if (mat[x][y + drt] == # ) { drt *= (-1); y += (drt * dis); ans += dis; o++; } else if (mat[x][y + drt] == + ) { mat[x][y + drt] = . ; drt *= (-1); y += (drt * dis); ans += dis; o = 0; } else { y += drt; dis++; o = 0; } ans++; } if (o == 2) { cout << Never << endl; } else cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 7; const int maxm = 1e5 + 7; struct Que { int l, r, rt, id; }; struct Data { int sum; int id; bool operator<(const Data& a) const { return (sum == a.sum) ? (id < a.id) : (sum > a.sum); } }; struct Edge { int to, last; } E[maxm]; vector<Que> Q[maxm]; struct Node { Data val; int lch, rch; } rne[maxm * 20]; int fail[maxm]; int ch[maxm][26]; int len[maxm]; int n, m; Data ans[maxn]; char s[maxn]; char t[maxn]; int rt[maxm]; int head[maxm]; int f[20][maxm]; int pos[maxn]; int Len[maxn]; int LL[maxn]; int last; int root; int cnt; int tot; int qvq; void Pushup(int u) { if (!rne[u].lch && !rne[u].rch) return; if (rne[u].lch && !rne[u].rch) rne[u].val = rne[rne[u].lch].val; else if (rne[u].rch && !rne[u].lch) rne[u].val = rne[rne[u].rch].val; else rne[u].val = min(rne[rne[u].lch].val, rne[rne[u].rch].val); } void Modify(int& u, int l, int r, int x) { if (!u) u = ++qvq; if (l == r) { rne[u].val.sum++; rne[u].val.id = l; return; } int mid = l + r >> 1; if (x <= mid) Modify(rne[u].lch, l, mid, x); else Modify(rne[u].rch, mid + 1, r, x); Pushup(u); } void Extend(int x, int id) { int p = last, np = ++tot; last = np; len[np] = len[p] + 1; while (p && !ch[p][x]) ch[p][x] = np, p = fail[p]; if (!p) fail[np] = root; else { int q = ch[p][x]; if (len[q] == len[p] + 1) fail[np] = q; else { int nq = ++tot; fail[nq] = fail[q]; len[nq] = len[p] + 1; memcpy(ch[nq], ch[q], sizeof ch[q]); fail[np] = fail[q] = nq; while (p && ch[p][x] == q) ch[p][x] = nq, p = fail[p]; } } Modify(rt[np], 1, m, id); } int Merge(int x, int y, int l, int r) { if (!x || !y) return x + y; if (l == r) { int re = ++qvq; rne[re].val.sum = rne[x].val.sum + rne[y].val.sum; rne[re].val.id = l; return re; } int mid = l + r >> 1; int re = ++qvq; rne[re].lch = Merge(rne[x].lch, rne[y].lch, l, mid); rne[re].rch = Merge(rne[x].rch, rne[y].rch, mid + 1, r); Pushup(re); return re; } Data Query(int u, int l, int r, int L, int R) { if (l >= L && r <= R) return rne[u].val; int mid = l + r >> 1; Data re = (Data){-1, m + 1}; if (L <= mid) re = min(re, Query(rne[u].lch, l, mid, L, R)); if (R > mid) re = min(re, Query(rne[u].rch, mid + 1, r, L, R)); return re; } void Dfs(int x, int p) { for (int i = head[x], y; y = E[i].to, i; i = E[i].last) { Dfs(y, x); rt[x] = Merge(rt[x], rt[y], 1, m); } for (Que cur : Q[x]) { ans[cur.id] = Query(rt[x], 1, m, cur.l, cur.r); } } void Adde(int x, int y) { E[++cnt] = (Edge){y, head[x]}; head[x] = cnt; } int Read(char c = 0, int re = 0) { while (!isdigit(c = getchar())) ; re = c - 0 ; while (isdigit(c = getchar())) re = ((re << 2) + re << 1) + c - 0 ; return re; } int main() { scanf( %s , s + 1); n = strlen(s + 1); scanf( %d , &m); last = tot = root = 1; for (int i = 1; i <= m; ++i) { scanf( %s , t + 1); int len = strlen(t + 1); last = 1; for (int j = 1; j <= len; ++j) Extend(t[j] - a , i); } for (int i = 1; i <= tot; ++i) f[0][i] = fail[i]; for (int i = 0; i < 19; ++i) for (int x = 1; x <= tot; ++x) f[i + 1][x] = f[i][f[i][x]]; int x = 1, tmp = 0; for (int i = 1; i <= n; ++i) { int d = s[i] - a ; if (ch[x][d]) tmp++, x = ch[x][d]; else { while (x && !ch[x][d]) x = fail[x]; if (x) tmp = len[x] + 1, x = ch[x][d]; else x = 1, tmp = 0; } pos[i] = x; Len[i] = tmp; } for (int i = 1; i <= tot; ++i) if (fail[i]) Adde(fail[i], i); int q = Read(); for (int i = 1; i <= q; ++i) { int l = Read(), r = Read(), pl = Read(), pr = Read(); LL[i] = l; if (Len[pr] < pr - pl + 1) { ans[i] = (Data){0, l}; continue; } int rt = pos[pr]; int LEN = pr - pl + 1; for (int i = 19; ~i; --i) { if (len[f[i][rt]] >= LEN) rt = f[i][rt]; } Q[rt].push_back((Que){l, r, rt, i}); } Dfs(1, 0); for (int i = 1; i <= q; ++i) { if (!ans[i].sum) ans[i].id = LL[i]; printf( %d %d n , ans[i].id, ans[i].sum); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; struct Node { int pos, val, sit; } a[305]; bool cmp(Node x, Node y) { if (x.val == y.val) { return x.pos > y.pos; } return x.val < y.val; } bool cmp2(Node x, Node y) { return x.pos < y.pos; } int main() { int T; std::cin >> T; while (T--) { cin >> n >> m; for (int i = 1; i <= m; i++) { scanf( %d , &a[i].val); a[i].pos = i; } sort(a + 1, a + 1 + m, cmp); for (int i = 1; i <= m; i++) { a[i].sit = i; } sort(a + 1, a + 1 + m, cmp2); int ans = 0; for (int i = 2; i <= m; i++) { for (int j = i - 1; j >= 1; j--) { if (a[j].sit < a[i].sit) ans++; } } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; int n; int neg = 0; string s[N + 5]; inline long long pars(int x) { long long ret = 0LL; for (int i = 0; i < s[x].size(); i++) { if (s[x][i] == - ) continue; if (s[x][i] == . ) break; ret *= 10; ret += s[x][i] - 0 ; } if (s[x][0] == - ) ret *= -1; return ret; } bool bisa(int x) { for (int i = s[x].size() - 1; i >= 0; i--) { if (s[x][i] == . ) break; if (s[x][i] != 0 ) return 1; } return 0; } int main() { cin >> n; long long ct = 0LL; for (int i = 1; i <= n; i++) { cin >> s[i]; if (s[i][0] == - ) neg++; ct += pars(i); } for (int i = 1; i <= n; i++) { long long tmp = pars(i); if (bisa(i)) { if (ct > 0) { if (s[i][0] == - ) { tmp--; ct--; } } else if (ct < 0) { if (s[i][0] != - ) { tmp++; ct++; } } } cout << tmp << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; long long ans = 0; priority_queue<int, vector<int>, greater<int>> pq; while (n--) { int x; cin >> x; if (pq.size() && x > pq.top()) { ans += x - pq.top(); pq.pop(); pq.push(x); } pq.push(x); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b); int main() { long long t, w, b; cin >> t >> w >> b; long long tie = 0; long long total = t; bool overflow = false; long long gcdValue = gcd(w, b); if (LLONG_MAX / double(w) < double(b) / gcdValue) overflow = true; long long lcm = b / gcdValue * w; tie += min(w, b) * (t / lcm); if (t % lcm < min(w, b)) tie += t % lcm; else tie += min(w, b) - 1; if (overflow == true) { if (t < min(w, b)) { tie = 1; total = 1; } else tie = min(w, b) - 1; } long long gcdans = gcd(tie, total); tie /= gcdans; total /= gcdans; cout << tie << / << total << endl; ; return 0; } long long gcd(long long a, long long b) { if (a % b == 0) return b; if (b % a == 0) return a; return gcd(max(a, b) % min(a, b), min(a, b)); }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_contrast_strecud_DSP48_1(
input [8 - 1:0] in0,
input [20 - 1:0] in1,
input [29 - 1:0] in2,
output [29 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $unsigned(in1);
assign b = $unsigned(in0);
assign c = $unsigned(in2);
assign m = a * b;
assign p = m + c;
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module hls_contrast_strecud(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
hls_contrast_strecud_DSP48_1 hls_contrast_strecud_DSP48_1_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
`timescale 1ns / 1ps
module bridge(
// FURCULA BUS
input f_signed_i,
input [1:0] f_siz_i,
input [2:0] f_adr_i,
input [63:0] f_dat_i,
output [63:0] f_dat_o,
// WISHBONE BUS
output [7:0] wb_sel_o,
output [63:0] wb_dat_o,
input [63:0] wb_dat_i
);
// Wishbone SEL_O signal generation.
wire size_byte = (f_siz_i == 2'b00);
wire size_hword = (f_siz_i == 2'b01);
wire size_word = (f_siz_i == 2'b10);
wire size_dword = (f_siz_i == 2'b11);
wire ab7 = f_adr_i[2:0] == 3'b111;
wire ab6 = f_adr_i[2:0] == 3'b110;
wire ab5 = f_adr_i[2:0] == 3'b101;
wire ab4 = f_adr_i[2:0] == 3'b100;
wire ab3 = f_adr_i[2:0] == 3'b011;
wire ab2 = f_adr_i[2:0] == 3'b010;
wire ab1 = f_adr_i[2:0] == 3'b001;
wire ab0 = f_adr_i[2:0] == 3'b000;
wire ah3 = f_adr_i[2:1] == 2'b11;
wire ah2 = f_adr_i[2:1] == 2'b10;
wire ah1 = f_adr_i[2:1] == 2'b01;
wire ah0 = f_adr_i[2:1] == 2'b00;
wire aw1 = f_adr_i[2] == 1'b1;
wire aw0 = f_adr_i[2] == 1'b0;
wire den = size_dword;
wire wen1 = size_word & aw1;
wire wen0 = size_word & aw0;
wire hen3 = size_hword & ah3;
wire hen2 = size_hword & ah2;
wire hen1 = size_hword & ah1;
wire hen0 = size_hword & ah0;
wire ben7 = size_byte & ab7;
wire ben6 = size_byte & ab6;
wire ben5 = size_byte & ab5;
wire ben4 = size_byte & ab4;
wire ben3 = size_byte & ab3;
wire ben2 = size_byte & ab2;
wire ben1 = size_byte & ab1;
wire ben0 = size_byte & ab0;
wire sel7 = den | wen1 | hen3 | ben7;
wire sel6 = den | wen1 | hen3 | ben6;
wire sel5 = den | wen1 | hen2 | ben5;
wire sel4 = den | wen1 | hen2 | ben4;
wire sel3 = den | wen0 | hen1 | ben3;
wire sel2 = den | wen0 | hen1 | ben2;
wire sel1 = den | wen0 | hen0 | ben1;
wire sel0 = den | wen0 | hen0 | ben0;
assign wb_sel_o = {sel7, sel6, sel5, sel4, sel3, sel2, sel1, sel0};
// Furcula-to-Wishbone Data Routing
wire [7:0] od7 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[31:24] : 0) |
(size_dword ? f_dat_i[63:56] : 0);
wire [7:0] od6 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[23:16] : 0) |
(size_dword ? f_dat_i[55:48] : 0);
wire [7:0] od5 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[15:8] : 0) |
(size_dword ? f_dat_i[47:40] : 0);
wire [7:0] od4 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[7:0] : 0) |
(size_dword ? f_dat_i[39:32] : 0);
wire [7:0] od3 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[31:24] : 0) |
(size_dword ? f_dat_i[31:24] : 0);
wire [7:0] od2 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[23:16] : 0) |
(size_dword ? f_dat_i[23:16] : 0);
wire [7:0] od1 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[15:8] : 0) |
(size_dword ? f_dat_i[15:8] : 0);
wire [7:0] od0 = f_dat_i[7:0];
assign wb_dat_o = {od7, od6, od5, od4, od3, od2, od1, od0};
// Wishbone to Furcula Data Routing
wire [31:0] id2 =
(wen1 ? wb_dat_i[63:32] : 0) |
(wen0 ? wb_dat_i[31:0] : 0);
wire [15:0] id1 =
(hen3 ? wb_dat_i[63:48] : 0) |
(hen2 ? wb_dat_i[47:32] : 0) |
(hen1 ? wb_dat_i[31:16] : 0) |
(hen0 ? wb_dat_i[15:0] : 0);
wire [7:0] id0 =
(ben7 ? wb_dat_i[63:56] : 0) |
(ben6 ? wb_dat_i[55:48] : 0) |
(ben5 ? wb_dat_i[47:40] : 0) |
(ben4 ? wb_dat_i[39:32] : 0) |
(ben3 ? wb_dat_i[31:24] : 0) |
(ben2 ? wb_dat_i[23:16] : 0) |
(ben1 ? wb_dat_i[15:8] : 0) |
(ben0 ? wb_dat_i[7:0] : 0);
wire [63:32] id2s = (f_signed_i ? {32{id2[31]}} : 32'd0);
wire [63:16] id1s = (f_signed_i ? {48{id1[15]}} : 48'd0);
wire [63:8] id0s = (f_signed_i ? {56{id0[7]}} : 56'd0);
assign f_dat_o =
(size_dword ? wb_dat_i : 0) |
(size_word ? {id2s, id2} : 0) |
(size_hword ? {id1s, id1} : 0) |
(size_byte ? {id0s, id0} : 0);
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.