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/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 14:29:56 2016
/////////////////////////////////////////////////////////////
module FSM_Add_Subtract ( clk, rst, rst_FSM, beg_FSM, zero_flag_i,
norm_iteration_i, add_overflow_i, round_i, load_1_o, load_2_o,
load_3_o, load_8_o, A_S_op_o, load_4_o, left_right_o, bit_shift_o,
load_5_o, load_6_o, load_7_o, ctrl_a_o, ctrl_b_o, ctrl_b_load_o,
ctrl_c_o, ctrl_d_o, rst_int, ready );
output [1:0] ctrl_b_o;
input clk, rst, rst_FSM, beg_FSM, zero_flag_i, norm_iteration_i,
add_overflow_i, round_i;
output load_1_o, load_2_o, load_3_o, load_8_o, A_S_op_o, load_4_o,
left_right_o, bit_shift_o, load_5_o, load_6_o, load_7_o, ctrl_a_o,
ctrl_b_load_o, ctrl_c_o, ctrl_d_o, rst_int, ready;
wire n1, n2, n4, ctrl_d_o, n7, n8, n9, n10, n11, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56;
wire [3:0] state_reg;
assign ctrl_a_o = ctrl_d_o;
INVX2TS U3 ( .A(rst), .Y(n1) );
DFFRX2TS \state_reg_reg[2] ( .D(n53), .CK(clk), .RN(n1), .Q(state_reg[2]),
.QN(n15) );
DFFRX2TS \state_reg_reg[3] ( .D(n55), .CK(clk), .RN(n1), .Q(state_reg[3]),
.QN(n9) );
DFFRX2TS \state_reg_reg[1] ( .D(n54), .CK(clk), .RN(n1), .Q(state_reg[1]),
.QN(n16) );
DFFRX2TS \state_reg_reg[0] ( .D(n56), .CK(clk), .RN(n1), .Q(state_reg[0]),
.QN(n17) );
NOR3BX1TS U67 ( .AN(n45), .B(n17), .C(state_reg[1]), .Y(n25) );
NOR2X1TS U68 ( .A(n16), .B(state_reg[3]), .Y(n51) );
NAND3X1TS U69 ( .A(n16), .B(n9), .C(n49), .Y(n41) );
NAND3X1TS U70 ( .A(n16), .B(n9), .C(n50), .Y(n32) );
NAND3X1TS U71 ( .A(state_reg[1]), .B(n17), .C(n45), .Y(n29) );
NAND3X1TS U72 ( .A(state_reg[1]), .B(n49), .C(state_reg[3]), .Y(n20) );
NAND2X1TS U73 ( .A(n43), .B(n27), .Y(load_5_o) );
INVX2TS U74 ( .A(n43), .Y(ctrl_c_o) );
OAI21X1TS U75 ( .A0(n32), .A1(n18), .B0(n24), .Y(n36) );
OAI21X1TS U76 ( .A0(n18), .A1(n41), .B0(n33), .Y(load_8_o) );
INVX2TS U77 ( .A(n28), .Y(ctrl_d_o) );
INVX2TS U78 ( .A(n22), .Y(n10) );
NOR3X1TS U79 ( .A(load_2_o), .B(load_1_o), .C(load_7_o), .Y(n31) );
NAND2X1TS U80 ( .A(n51), .B(n49), .Y(n43) );
NAND2X1TS U81 ( .A(n50), .B(n51), .Y(n27) );
NAND2X1TS U82 ( .A(n44), .B(n29), .Y(ctrl_b_load_o) );
NAND2X1TS U83 ( .A(n32), .B(n24), .Y(load_4_o) );
NAND3X1TS U84 ( .A(n41), .B(n42), .C(n33), .Y(load_3_o) );
INVX2TS U85 ( .A(n40), .Y(load_2_o) );
INVX2TS U86 ( .A(n41), .Y(n4) );
INVX2TS U87 ( .A(n39), .Y(rst_int) );
INVX2TS U88 ( .A(n44), .Y(load_6_o) );
INVX2TS U89 ( .A(n20), .Y(ready) );
INVX2TS U90 ( .A(n32), .Y(n8) );
INVX2TS U91 ( .A(n29), .Y(n7) );
NAND2X1TS U92 ( .A(round_i), .B(n25), .Y(n28) );
NAND4X1TS U93 ( .A(add_overflow_i), .B(n31), .C(n46), .D(n47), .Y(A_S_op_o)
);
NOR4XLTS U94 ( .A(n48), .B(ctrl_b_load_o), .C(load_5_o), .D(load_4_o), .Y(
n47) );
AOI211X1TS U95 ( .A0(n4), .A1(n18), .B0(n50), .C0(n25), .Y(n46) );
NAND3X1TS U96 ( .A(n20), .B(n39), .C(n42), .Y(n48) );
INVX2TS U97 ( .A(norm_iteration_i), .Y(n18) );
NOR2BX1TS U98 ( .AN(ctrl_b_load_o), .B(add_overflow_i), .Y(ctrl_b_o[0]) );
OA21XLTS U99 ( .A0(n36), .A1(load_8_o), .B0(add_overflow_i), .Y(bit_shift_o)
);
OAI2BB1X1TS U100 ( .A0N(load_6_o), .A1N(add_overflow_i), .B0(n29), .Y(
ctrl_b_o[1]) );
AOI211X1TS U101 ( .A0(n41), .A1(n32), .B0(n18), .C0(add_overflow_i), .Y(
left_right_o) );
AOI21X1TS U102 ( .A0(load_2_o), .A1(zero_flag_i), .B0(load_7_o), .Y(n22) );
OAI22X1TS U103 ( .A0(beg_FSM), .A1(n39), .B0(rst_FSM), .B1(n20), .Y(n26) );
NAND4BX1TS U104 ( .AN(load_5_o), .B(n33), .C(n34), .D(n35), .Y(n55) );
AOI21X1TS U105 ( .A0(n25), .A1(n19), .B0(n7), .Y(n34) );
AOI211X1TS U106 ( .A0(state_reg[3]), .A1(n26), .B0(n36), .C0(n10), .Y(n35)
);
INVX2TS U107 ( .A(round_i), .Y(n19) );
NAND4X1TS U108 ( .A(n27), .B(n28), .C(n29), .D(n30), .Y(n54) );
AOI221X1TS U109 ( .A0(n8), .A1(n18), .B0(state_reg[1]), .B1(n26), .C0(n11),
.Y(n30) );
INVX2TS U110 ( .A(n31), .Y(n11) );
AOI31X1TS U111 ( .A0(n37), .A1(n2), .A2(n38), .B0(n26), .Y(n56) );
NOR3X1TS U112 ( .A(n25), .B(rst_int), .C(n4), .Y(n38) );
AOI2BB1X1TS U113 ( .A0N(n40), .A1N(zero_flag_i), .B0(n7), .Y(n37) );
INVX2TS U114 ( .A(n36), .Y(n2) );
NOR2X1TS U115 ( .A(n15), .B(state_reg[0]), .Y(n49) );
NOR2X1TS U116 ( .A(n9), .B(state_reg[2]), .Y(n45) );
NOR2X1TS U117 ( .A(n17), .B(n15), .Y(n50) );
NOR3X1TS U118 ( .A(state_reg[2]), .B(state_reg[3]), .C(state_reg[1]), .Y(n52) );
NAND3X1TS U119 ( .A(n17), .B(n16), .C(n45), .Y(n44) );
NAND3X1TS U120 ( .A(state_reg[0]), .B(state_reg[1]), .C(n45), .Y(n33) );
NAND3X1TS U121 ( .A(n51), .B(n15), .C(state_reg[0]), .Y(n42) );
NAND2X1TS U122 ( .A(n52), .B(n17), .Y(n39) );
NAND3X1TS U123 ( .A(n17), .B(n15), .C(n51), .Y(n40) );
NAND3X1TS U124 ( .A(n49), .B(n16), .C(state_reg[3]), .Y(n24) );
AND3X2TS U125 ( .A(n50), .B(state_reg[3]), .C(n16), .Y(load_7_o) );
NAND3X1TS U126 ( .A(n21), .B(n22), .C(n23), .Y(n53) );
NOR4BX1TS U127 ( .AN(n24), .B(load_3_o), .C(load_6_o), .D(n25), .Y(n23) );
AOI22X1TS U128 ( .A0(n8), .A1(n18), .B0(state_reg[2]), .B1(n26), .Y(n21) );
AND2X2TS U129 ( .A(n52), .B(state_reg[0]), .Y(load_1_o) );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 10; pair<long long, long long> p[maxn]; long long ans[maxn]; int main() { int n, num = 0, cnt = 0; long long l, r; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lld%lld , &l, &r); p[++num].first = l; p[num].second = 1; p[++num].first = r + 1; p[num].second = -1; } sort(p + 1, p + 1 + num); for (int i = 1; i <= num; i++) { ans[cnt] += p[i].first - p[i - 1].first; cnt += p[i].second; } for (int i = 1; i <= n; i++) printf( %lld%c , ans[i], i == n ? n : ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_BLACKBOX_V
`define SKY130_FD_SC_LS__DLYMETAL6S2S_BLACKBOX_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlymetal6s2s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S2S_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m; int lace[110][110]; int main() { int x, y, i, j; while (cin >> n >> m) { memset(lace, 0, sizeof(lace)); for (i = 1; i <= m; i++) { cin >> x >> y; lace[x][y] = lace[y][x] = 1; } int xx, ans = 0; while (1) { int g[110], num = 0; for (i = 1; i <= n; i++) { xx = 0; for (j = 1; j <= n; j++) if (lace[i][j]) xx++; if (xx == 1) g[++num] = i; } for (j = 1; j <= num; j++) { for (i = 1; i <= n; i++) lace[g[j]][i] = lace[i][g[j]] = 0; } if (!num) break; ans++; } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[100100], ans; int arr[100100], cnt[100100]; bool visited[100100]; int n, m; void dfs(int v) { for (vector<int>::iterator it = adj[v].begin(); it != adj[v].end(); it++) { cnt[*it]++; if (cnt[*it] == arr[*it]) { cnt[*it]++; ans.push_back(*it); dfs(*it); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> m; int x, y; for (int i = 1; i <= m; i++) { cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } for (int i = 1; i <= n; i++) cin >> arr[i]; for (int i = 1; i <= n; i++) { if (cnt[i] == arr[i]) { visited[i] = true; cnt[i]++; ans.push_back(i); dfs(i); } } cout << ans.size() << n ; vector<int>::iterator it; for (it = ans.begin(); it != ans.end(); it++) cout << *it << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[200001]; int main() { long long t, m = 0, i, n, k, ans; ; scanf( %lld%lld , &n, &k); for (i = 0; i < n; i++) scanf( %lld , &a[i]); sort(a, a + n); for (i = (n + 1) / 2; i < n; i++) { t = m; m += (a[i] - a[i - 1]) * (i - (n - 1) / 2); if (m > k) { ans = a[i - 1] + (k - t) / (i - (n - 1) / 2); break; } } if (i == n) ans = (k - m) / (n - (n - 1) / 2) + a[n - 1]; printf( %lld n , ans); }
|
#include <bits/stdc++.h> using namespace std; void frepn() { freopen( .in , r , stdin); freopen( .out , w , stdout); } const int N = 50500; const long long INF = (1e17) + 777; const int mod = (1e9) + 7; int n, a[N], k, t; int ans, ans2, ans3, ans4; int main() { ios_base::sync_with_stdio(0); ; cin >> n >> k >> t; ans = k * t; for (int i = 1; i <= n; i++) { cin >> a[i]; ans4 += a[i]; } sort(a + 1, a + 1 + n); for (int i = n - k; i <= n; i++) { ans2 += a[i]; } for (int i = 1; i <= n - k; i++) { ans3 += a[i]; } if (ans2 < ans) cout << ans4; else cout << ans3 + ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 10; const long long inf = 1e18; long long n, m, Q, E[N][3], l[N], r[N], op[N]; long long hd[N], ht = 1, tf[N], id[N]; long long cnt = 0; struct edge { long long v, w, n; } e[N * 2]; void addedge(long long u, long long v, long long w) { e[++ht] = (edge){v, w, hd[u]}; hd[u] = ht; } long long diss[N], dist[N]; priority_queue<pair<long long, long long> > q; pair<long long, long long> qtmp; void Dijkstra(long long S, long long T, bool typed, long long typef, long long u = 0) { memset((typed ? dist : diss), 0x3f, sizeof((typed ? dist : diss))); (typed ? dist : diss)[S] = 0; q.push(make_pair(0, S)); while (!q.empty()) { qtmp = q.top(); q.pop(); if (qtmp.first != -(typed ? dist : diss)[u = qtmp.second]) continue; for (long long i = hd[u], v; i; i = e[i].n) { v = e[i].v; if ((typed ? dist : diss)[v] > (typed ? dist : diss)[u] + e[i].w) { tf[v] = i >> 1; (typed ? dist : diss)[v] = (typed ? dist : diss)[u] + e[i].w; if (typef == 1 && !op[v]) l[v] = l[u]; if (typef == 2 && !op[v]) r[v] = r[u]; q.push(make_pair(-(typed ? dist : diss)[v], v)); } } } } long long t[N << 3]; void build(long long k, long long l, long long r) { t[k] = inf; if (l == r) return; long long mid = (l + r) >> 1; build(k << 1, l, mid); build(k << 1 | 1, mid + 1, r); } void modify(long long k, long long l, long long r, long long L, long long R, long long x) { if (R < l || r < L) return; if (L <= l && r <= R) { t[k] = min(t[k], x); return; } long long mid = (l + r) >> 1; modify(k << 1, l, mid, L, R, x); modify(k << 1 | 1, mid + 1, r, L, R, x); } long long query(long long k, long long l, long long r, long long x) { if (l == r) return t[k]; long long mid = (l + r) >> 1; if (x <= mid) return min(t[k], query(k << 1, l, mid, x)); else return min(t[k], query(k << 1 | 1, mid + 1, r, x)); } signed main() { scanf( %lld%lld%lld , &n, &m, &Q); memset(id, -1, sizeof(id)); for (long long i = 1; i <= m; i++) { scanf( %lld%lld%lld , &E[i][0], &E[i][1], &E[i][2]); addedge(E[i][0], E[i][1], E[i][2]); addedge(E[i][1], E[i][0], E[i][2]); id[i] = -1; } Dijkstra(n, 1, 1, 0); op[1] = 1, l[1] = r[1] = 0; for (long long i = 1, x = 1, tmp; x != n; i++) { id[tmp = tf[x]] = i, ++cnt; op[x ^= E[tmp][0] ^ E[tmp][1]] = 1; l[x] = r[x] = i; } Dijkstra(1, n, 0, 1); Dijkstra(n, 1, 1, 2); build(1, 1, cnt); for (long long i = 1; i <= m; i++) if (!~id[i]) { modify(1, 1, cnt, l[E[i][0]] + 1, r[E[i][1]], diss[E[i][0]] + E[i][2] + dist[E[i][1]]); modify(1, 1, cnt, l[E[i][1]] + 1, r[E[i][0]], diss[E[i][1]] + E[i][2] + dist[E[i][0]]); } long long ans, tmpw; for (long long i = 1, tmp; i <= Q; i++) { scanf( %lld%lld , &tmp, &tmpw); ans = diss[n]; if (id[tmp] != -1) { ans -= E[tmp][2] - tmpw; if (tmpw > E[tmp][2]) ans = min(ans, query(1, 1, cnt, id[tmp])); } else { if (tmpw < E[tmp][2]) { ans = min(ans, diss[E[tmp][0]] + tmpw + dist[E[tmp][1]]); ans = min(ans, diss[E[tmp][1]] + tmpw + dist[E[tmp][0]]); } } printf( %lld n , ans); } return 0; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_2_r_0 (
In0,
In1,
In2,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
input wire [0 : 0] In2;
output wire [2 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(3),
.NUM_PORTS(3)
) inst (
.In0(In0),
.In1(In1),
.In2(In2),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int sz = 105; long long int r[sz], a[sz][sz], b[sz][sz], ans[sz][sz], m; void multiply(long long int a[][sz], long long int b[][sz]) { for (int i = 0; i < m; i++) { for (int j = 0; j < m; j++) { ans[i][j] = 0; for (int k = 0; k < m; k++) { ans[i][j] += a[i][k] * b[k][j] % 1000000007; ans[i][j] %= 1000000007; } } } for (int i = 0; i < m; i++) { for (int j = 0; j < m; j++) { a[i][j] = ans[i][j]; } } } void power(long long int a[][sz], long long int n) { if (n <= 1) { return; } power(a, n / 2); multiply(a, a); if (n % 2 == 1) { multiply(a, b); } } int main() { long long int n; cin >> n >> m; r[0] = 1; for (int i = 1; i <= m; i++) { r[i] = r[i - 1]; if (i - m >= 0) { r[i] += r[i - m]; } r[i] %= 1000000007; } for (int i = 1; i < m; i++) { a[i][i - 1] = b[i][i - 1] = 1; } a[0][m - 1] = b[0][m - 1] = 1; a[m - 1][m - 1] = b[m - 1][m - 1] = 1; power(a, n); long long int res = 0; for (int k = 0; k < m; k++) { res += r[k] * a[k][0] % 1000000007; res %= 1000000007; } cout << res << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFRBP_PP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRBP_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLXBN_FUNCTIONAL_PP_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlxbn (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
not not0 (GATE , GATE_N );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> const double pi = 3.141592653589793238462643383279; using namespace std; long long GCD(long long a, long long b) { if (b == 0) return a; return GCD(b, a % b); } int arr[1000010]; int rev[1000010]; int main() { cin.tie(0); ios::sync_with_stdio(false); cout << fixed << setprecision(10); int n; cin >> n; string s; cin >> s; if (s[0] == ) && s[s.size() - 1] == ( ) { cout << 0 << endl; return 0; } else if (s[0] == ) ) { arr[0]++; arr[1] += arr[0]; bool f = true; for (int i = 1; i < s.size(); i++) { if (s[i] == ( ) arr[i]++; else arr[i]--; arr[i + 1] += arr[i]; if (arr[i] < 0) f = false; } if (f && arr[s.size() - 1] == 0) cout << 1 << endl; else cout << 0 << endl; return 0; } else if (s[s.size() - 1] == ( ) { bool f = true; for (int i = 0; i < s.size() - 1; i++) { if (s[i] == ( ) arr[i]++; else arr[i]--; arr[i + 1] += arr[i]; if (arr[i] < 0) f = false; } arr[s.size() - 1]--; if (f && arr[s.size() - 1] == 0) cout << 1 << endl; else cout << 0 << endl; return 0; } for (int i = 0; i < s.size(); i++) { if (s[i] == ( ) { arr[i]++; } else { arr[i]--; } arr[i + 1] += arr[i]; } for (int i = s.size() - 1; i >= 0; i--) { if (s[i] == ( ) { rev[i]++; } else { rev[i]--; } rev[i] += rev[i + 1]; } if (arr[s.size() - 1] == 2) { int ans = 0; for (int i = 0; i < s.size(); i++) { if (arr[i] < 0) { cout << 0 << endl; return 0; } } for (int i = s.size() - 1; i >= 0; i--) { if (arr[i] <= 1) break; if (s[i] == ( ) ans++; } cout << ans << endl; } else if (arr[s.size() - 1] == -2) { int ans = 0; for (int i = 0; i < s.size(); i++) { if (arr[i] <= -3) { cout << 0 << endl; return 0; } } for (int i = 0; i < s.size(); i++) { if (s[i] == ) ) { ans++; if (arr[i] < 0) { break; } } } cout << ans << endl; } else { cout << 0 << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_BLACKBOX_V
`define SKY130_FD_SC_LS__XNOR2_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_V
`define SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module spi
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 2
)
(
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire SPI_CLK,
output wire SCLK,
input wire SDO,
output wire SDI,
input wire EXT_START,
output wire SEN,
output wire SLD
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH)) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
spi_core #(
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_BYTES)
) i_spi_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SPI_CLK(SPI_CLK),
.SCLK(SCLK),
.SDO(SDO),
.SDI(SDI),
.EXT_START(EXT_START),
.SEN(SEN),
.SLD(SLD)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 1234567; const long long MOD = 998244353; void solve() { long long n, m, i, j = 0, k, l = 0, ok = 0, o = 0, p, ans = 0, x, y, a[30]; string s; cin >> n >> k >> s; for (long long i = 0; i < k / 2; i++) { map<char, long long> mg; for (j = 0; j < n; j += k) { mg[s[i + j]]++; mg[s[j + k - i - 1]]++; } l = 0; for (auto it : mg) l = max(l, it.second); ans += l; } if (k % 2) { map<char, long long> mg; for (j = 0; j < n; j += k) { mg[s[j + k / 2]]++; } l = 0; for (auto it : mg) l = max(l, it.second); ans += l; } cout << (n - ans) << endl; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 10000000; int main() { int n; cin >> n; string a; cin >> a; for (int j = 1; j <= 25; j++) for (int i = 0; i + 4 * j < a.size(); i++) { if (a[i] == * && a[i + j] == * && a[i + 2 * j] == * && a[i + 3 * j] == * && a[i + 4 * j] == * ) { cout << yes ; return 0; } } cout << no ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__EBUFN_FUNCTIONAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFBUF_16_V
`define SKY130_FD_SC_MS__BUFBUF_16_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__bufbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFBUF_16_V
|
//======================================================================
//
// siphash.v
// ---------
// Top level wrapper for the Verilog 2001 implementation of SipHash.
// This wrapper provides a 32-bit memory like interface.
//
//
// Copyright (c) 2012, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module siphash(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] addr,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// API and Symbolic names.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_COMPRESS_BIT = 1;
localparam CTRL_FINALIZE_BIT = 2;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_CONFIG = 8'h0a;
localparam CONFIG_LONG_BIT = 0;
localparam ADDR_PARAM = 8'h0b;
localparam SIPHASH_START_C = 0;
localparam SIPHASH_SIZE_C = 4;
localparam SIPHASH_DEFAULT_C = 4'h2;
localparam SIPHASH_START_D = 4;
localparam SIPHASH_SIZE_D = 4;
localparam SIPHASH_DEFAULT_D = 4'h4;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY1 = 8'h11;
localparam ADDR_KEY2 = 8'h12;
localparam ADDR_KEY3 = 8'h13;
localparam ADDR_MI0 = 8'h18;
localparam ADDR_MI1 = 8'h19;
localparam ADDR_WORD0 = 8'h20;
localparam ADDR_WORD1 = 8'h21;
localparam ADDR_WORD2 = 8'h22;
localparam ADDR_WORD3 = 8'h23;
localparam CORE_NAME0 = 32'h73697068; // "siph"
localparam CORE_NAME1 = 32'h61736820; // "ash "
localparam CORE_VERSION = 32'h322e3030; // "2.00"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [2 : 0] ctrl_reg;
reg [2 : 0] ctrl_new;
reg long_reg;
reg long_we;
reg [7 : 0] param_reg;
reg param_we;
reg [31 : 0] key_reg[0 : 3];
reg key_we;
reg [31 : 0] mi0_reg;
reg mi0_we;
reg [31 : 0] mi1_reg;
reg mi1_we;
reg [31 : 0] word0_reg;
reg [31 : 0] word1_reg;
reg [31 : 0] word2_reg;
reg [31 : 0] word3_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
wire core_initalize;
wire core_compress;
wire core_finalize;
wire [3 : 0] core_c;
wire [3 : 0] core_d;
wire [127 : 0] core_key;
wire [63 : 0] core_mi;
wire core_ready;
wire [127 : 0] core_siphash_word;
wire core_siphash_word_valid;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign core_initalize = ctrl_reg[CTRL_INIT_BIT];
assign core_compress = ctrl_reg[CTRL_COMPRESS_BIT];
assign core_finalize = ctrl_reg[CTRL_FINALIZE_BIT];
assign core_c = param_reg[(SIPHASH_START_C + SIPHASH_SIZE_C - 1) :
SIPHASH_START_C];
assign core_d = param_reg[(SIPHASH_START_D + SIPHASH_SIZE_D - 1) :
SIPHASH_START_D];
assign core_key = {key_reg[3], key_reg[2], key_reg[1], key_reg[0]};
assign core_mi = {mi1_reg, mi0_reg};
//----------------------------------------------------------------
// Core instance.
//----------------------------------------------------------------
siphash_core core(
.clk(clk),
.reset_n(reset_n),
.initalize(core_initalize),
.compress(core_compress),
.finalize(core_finalize),
.long(long_reg),
.compression_rounds(core_c),
.final_rounds(core_d),
.key(core_key),
.mi(core_mi),
.ready(core_ready),
.siphash_word(core_siphash_word),
.siphash_word_valid(core_siphash_word_valid)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with
// synchronous active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 4 ; i = i + 1)
key_reg[i] <= 32'h0;
ctrl_reg <= 3'h0;
long_reg <= 1'b0;
param_reg <= {SIPHASH_DEFAULT_D, SIPHASH_DEFAULT_C};
mi0_reg <= 32'h0;
mi1_reg <= 32'h0;
word0_reg <= 32'h0;
word1_reg <= 32'h0;
word2_reg <= 32'h0;
word3_reg <= 32'h0;
end
else
begin
ctrl_reg <= ctrl_new;
if (long_we)
long_reg <= write_data[CONFIG_LONG_BIT];
if (param_we)
param_reg <= write_data[7 : 0];
if (key_we)
key_reg[addr[1 : 0]] <= write_data;
if (mi0_we)
mi0_reg <= write_data;
if (mi1_we)
mi1_reg <= write_data;
// We sample the siphash word when valid is set.
if (core_siphash_word_valid)
begin
word0_reg <= core_siphash_word[31 : 0];
word1_reg <= core_siphash_word[63 : 32];
word2_reg <= core_siphash_word[95 : 64];
word3_reg <= core_siphash_word[127 : 96];
end
end
end // reg_update
//----------------------------------------------------------------
// api
//----------------------------------------------------------------
always @*
begin : api
tmp_read_data = 32'h0;
ctrl_new = 3'h0;
long_we = 1'b0;
param_we = 1'b0;
key_we = 1'b0;
mi0_we = 1'b0;
mi1_we = 1'b0;
if (cs)
begin
if (we)
begin
case (addr)
ADDR_CTRL: ctrl_new = write_data[2 : 0];
ADDR_CONFIG: long_we = 1'b1;
ADDR_PARAM: param_we = 1'b1;
ADDR_MI0: mi0_we = 1'b1;
ADDR_MI1: mi1_we = 1'b1;
default:
begin
end
endcase // case (addr)
if ((addr >= ADDR_KEY0) && (addr <= ADDR_KEY3))
key_we = 1'h1;
end
else
begin
case (addr)
ADDR_NAME0: tmp_read_data = CORE_NAME0;
ADDR_NAME1: tmp_read_data = CORE_NAME1;
ADDR_VERSION: tmp_read_data = CORE_VERSION;
ADDR_STATUS: tmp_read_data = {30'h0, core_siphash_word_valid, core_ready};
ADDR_PARAM: tmp_read_data = {24'h0, param_reg};
ADDR_WORD0: tmp_read_data = word0_reg;
ADDR_WORD1: tmp_read_data = word1_reg;
ADDR_WORD2: tmp_read_data = word2_reg;
ADDR_WORD3: tmp_read_data = word3_reg;
default:
begin
end
endcase // case (addr)
end
end
end
endmodule // siphash
//======================================================================
// EOF siphash.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_TB_V
`define SKY130_FD_SC_LS__DLYMETAL6S6S_TB_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlymetal6s6s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__dlymetal6s6s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S6S_TB_V
|
#include <bits/stdc++.h> using namespace std; const int M = 110; const int inf = 1000000000; int main() { int n, m, g[M][M] = {0}; double f[M][M] = {0.0}; cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { g[i][j] = inf; f[i][j] = 0; } g[i][i] = 0; } while (m--) { int u, v; cin >> u >> v; g[u][v] = 1, f[u][v] = 1; g[v][u] = 1, f[v][u] = 1; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { for (int k = 1; k <= n; k++) { if (g[j][k] > g[j][i] + g[i][k]) { g[j][k] = g[j][i] + g[i][k]; f[j][k] = f[j][i] * f[i][k]; } else { if (g[j][k] == g[j][i] + g[i][k]) { f[j][k] += f[j][i] * f[i][k]; } } } } } double ans = 1.0; for (int i = 2; i < n; i++) if (g[1][n] == g[1][i] + g[i][n]) ans = max(ans, (((double)2.0 * (f[1][i] * f[i][n])) / f[1][n])); printf( %.20lf n , ans); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 11:46:02 10/17/2016
// Module Name: ID_EX
// Project Name: MIPS
// Description: ID/EX module for the DECODE stage.
//
// Dependencies: None
//
////////////////////////////////////////////////////////////////////////////////
module ID_EX(
input clk,
input [1:0] ctlwb_out,
input [2:0] ctlm_out,
input [3:0] ctlex_out,
input [31:0] npc, readdat1, readdat2, signext_out,
input [4:0] instr_2016, instr_1511,
output reg [1:0] wb_ctlout,
output reg [2:0] m_ctlout,
output reg [3:0] ex_ctlout,
output reg [31:0] npcout, rdata1out, rdata2out, s_extendout,
output reg [4:0] instrout_2016, instrout_1511,
// Forwarding
// ---------------------------
input [4:0] instr_2521,
output reg [4:0] instrout_2521
// ---------------------------
);
// Inititalize
initial
begin
wb_ctlout <= 0;
m_ctlout <= 0;
ex_ctlout <= 0;
npcout <= 0;
rdata1out <= 0;
rdata2out <= 0;
s_extendout <= 0;
instrout_2016 <= 0;
instrout_1511 <= 0;
// Forwarding
instrout_2521 <= 0;
end
// Update
always @ (posedge clk)
begin
wb_ctlout <= ctlwb_out;
m_ctlout <= ctlm_out;
ex_ctlout <= ctlex_out;
npcout <= npc;
rdata1out <= readdat1;
rdata2out <= readdat2;
s_extendout <= signext_out;
instrout_2016 <= instr_2016;
instrout_1511 <= instr_1511;
// Forwarding
instrout_2521 <= instr_2521;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI{3.1415926535897932384626433832795}; const int MOD{static_cast<int>(1e9 + 7)}; const double EPS{1e-9}; template <typename T> T ModAdd(const T &a, const T &b, const int &mod = MOD) { return ((a) % mod + (a) % mod) % mod; } template <typename T> T ModSub(const T &a, const T &b, const int &mod = MOD) { return ((((a % mod) - (b % mod)) % mod) + mod) % mod; } template <typename T> T ModMul(const T &a, const T &b, const int &mod = MOD) { return ((a % mod) * (b % mod)) % mod; } template <typename T> bool AdditionLimitFlow(const T &a, const T &x) { T MAXIMUM_INT{a}, MINIMUM_INT{a}; switch (sizeof(a)) { case 8: MAXIMUM_INT = LLONG_MAX; MINIMUM_INT = LLONG_MIN; break; case 4: MAXIMUM_INT = INT_MAX; MINIMUM_INT = INT_MIN; break; default: cerr << PARAMETER SHOULD BE EITHER int OR long long !! << endl; assert(0); break; } bool overflow{false}, underflow{false}; if ((x > 0) && (a > MAXIMUM_INT - x)) overflow = true; if ((x < 0) && (a < MINIMUM_INT - x)) underflow = true; if (overflow) { cerr << OVERFLOW: [ << a << , << x << ] << endl; return overflow; } if (underflow) { cerr << UNDERFLOW: [ << a << , << x << ] << endl; return underflow; } return false; } template <typename T> bool SubstractionLimitFlow(const T &a, const T &x) { T MAXIMUM_INT{}, MINIMUM_INT{}; switch (sizeof(a)) { case 8: MAXIMUM_INT = LLONG_MAX; MINIMUM_INT = LLONG_MIN; break; case 4: MAXIMUM_INT = INT_MAX; MINIMUM_INT = INT_MIN; break; default: cerr << PARAMETER SHOULD BE EITHER int OR long long !! << endl; assert(0); break; } bool overflow{false}, underflow{false}; if ((x < 0) && (a > MAXIMUM_INT + x)) overflow = true; if ((x > 0) && (a < MINIMUM_INT + x)) underflow = true; if (overflow) { cerr << OVERFLOW: [ << a << , << x << ] << endl; return overflow; } if (underflow) { cerr << UNDERFLOW: [ << a << , << x << ] << endl; return underflow; } return false; } template <typename T> bool MultiplicationLimitFlow(const T &a, const T &x) { T MAXIMUM_INT{}, MINIMUM_INT{}; switch (sizeof(a)) { case 8: MAXIMUM_INT = LLONG_MAX; MINIMUM_INT = LLONG_MIN; break; case 4: MAXIMUM_INT = INT_MAX; MINIMUM_INT = INT_MIN; break; default: cerr << PARAMETER SHOULD BE EITHER int OR long long !! << endl; assert(0); break; } bool overflow{false}, underflow{false}; if ((a == -1) && (x == MINIMUM_INT)) overflow = true; if ((x == -1) && (a == MINIMUM_INT)) overflow = true; if (a > MAXIMUM_INT / x) overflow = true; if (a < MINIMUM_INT / x) underflow = true; if (overflow) { cerr << OVERFLOW: [ << a << , << x << ] << endl; return overflow; } if (underflow) { cerr << UNDERFLOW: [ << a << , << x << ] << endl; return underflow; } return false; } template <typename T, size_t N> istream &operator>>(istream &is, array<T, N> &ARR) { for (T &a : ARR) is >> a; return is; } template <typename T, size_t N> ostream &operator<<(ostream &os, array<T, N> &ARR) { for (T const &a : ARR) os << a << ; return os; } template <typename T> istream &operator>>(istream &is, vector<T> &VEC) { for (T &v : VEC) is >> v; return is; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &VEC) { for (T const &v : VEC) os << v << ; return os; } template <typename T> istream &operator>>(istream &is, deque<T> &DEQ) { for (T &d : DEQ) is >> d; return is; } template <typename T> ostream &operator<<(ostream &os, const deque<T> &DEQ) { for (const T &d : DEQ) os << d << ; return os; } template <typename T> istream &operator>>(istream &is, list<T> &LIS) { for (T &l : LIS) is >> l; return is; } template <typename T> ostream &operator<<(ostream &os, const list<T> &LIS) { for (T const &l : LIS) os << l << ; return os; } template <typename T> ostream &operator<<(ostream &os, const set<T> &ST) { for (auto const &s : ST) os << s << ; return os; } template <typename T> ostream &operator<<(ostream &os, const unordered_set<T> &U_ST) { for (T const &us : U_ST) os << us << ; return os; } template <typename T1, typename T2> istream &operator>>(istream &is, pair<T1, T2> &PR) { is >> PR.first >> PR.second; return is; } template <typename T1, typename T2> ostream &operator<<(ostream &os, const pair<T1, T2> &PR) { os << [ << PR.first << : << PR.second << ] ; return os; } template <typename T1, typename T2> ostream &operator<<(ostream &os, const map<T1, T2> &MP) { os << [ ; for (pair<T1, T2> const &m : MP) os << m << ; os << ] ; return os; } template <typename T1, typename T2> ostream &operator<<(ostream &os, const unordered_map<T1, T2> &U_MP) { os << [ ; for (pair<T1, T2> const &um : U_MP) os << um << ; os << ] ; return os; } template <typename T> ostream &operator<<(ostream &os, stack<T> STACK) { while (!STACK.empty()) { os << STACK.top() << ; STACK.pop(); } return os; } template <typename T> ostream &operator<<(ostream &os, queue<T> QUEUE) { while (!QUEUE.empty()) { os << QUEUE.front() << ; QUEUE.pop(); } return os; } template <typename T, size_t R, size_t C> ostream &operator<<(ostream &os, array<array<T, C>, R> &MAT) { for (array<T, C> &ROW : MAT) os << ROW << endl; return os; } template <typename T> ostream &operator<<(ostream &os, vector<vector<T>> &MAT) { for (vector<T> &ROW : MAT) os << ROW << endl; return os; } template <typename T> T max(const T &A, const T &B, const T &C) { T mx{A}; (mx < B) && (mx = B); (mx < C) && (mx = C); return mx; } template <typename T> T min(const T &A, const T &B, const T &C) { T mn{A}; (mn > B) && (mn = B); (mn > C) && (mn = C); return mn; } template <typename T> int cntDigits(const T &N) { return (static_cast<int>(log10(N)) + 1); } template <typename T> bool isPowOfTwo(const T &N) { return (N && (!(N & (N - 1)))); } template <typename T> bool dblEqual(const T &a, const T &b) { return abs(a - b) < EPS; } void TEST_CASES() { int n{}; cin >> n; vector<int> arr(n); cin >> arr; int mn{*min_element(arr.begin(), arr.end())}; if (mn == 1) cout << 1 << endl; else { bool alldivisible{true}; for (int i{}; i < n; ++i) { if (arr.at(i) % mn) { alldivisible = false; break; } } if (alldivisible) cout << mn << endl; else cout << -1 << endl; } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cerr.setf(std::ios::boolalpha); cout << std::fixed; cout << std::setprecision(6); unsigned TT{1}; while (TT--) { TEST_CASES(); } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Dual 74HC595 interface (16 bit) for the YL-3
// Original Engineer: Jon Carrier (https://gist.github.com/jjcarrier/)
// Re-written: EllisGL
//
// Dependencies: CLK=50MHz. Slower clocks should also work. If a faster CLK is
// used, the parameters below may need adjusting
//
////////////////////////////////////////////////////////////////////////////////
/**
* Control Signals
* CLK <=50 Mhz cloc
* DATA_IN 16 bit data input - Position (MSB = Right to Left posision so 1000_0000 is the most right element),Character (inverted GFEDCBA 1 = off 0 = on)
* EN_IN Data is valid, output data
* RDY Ready to accept data input
*
* Output pins
* RCLK = RCK
* SRCLK = SCK
* SER_OUT = DIO
*/
module YL3_Shift_Register(
input CLK,
input [15:0] DATA_IN,
input EN_IN,
output RDY,
output RCLK,
output SRCLK,
output SER_OUT
);
// Registers and initial settings
reg [16:0] shift = 0;
reg RCLK = 0;
reg SRCLK = 0;
reg RDY = 1;
//==============================================================================
//--------------------------------PARAMETERS------------------------------------
//==============================================================================
//If we assume CLK=50MHz, then T=20nS
//If VCC=5V, SRCLK at worst case is capable of 5MHz and at best 29MHz
//Lets assume SRCLK=10MHz, T_SCLK=100nS
//See page 7 of the SN74HC595 datasheet for the parameters below
//------------------------------NUMBER OF BITS----------------------------------
parameter N = 3; //This parameter is used on several registers/parameters below
//---------------------PULSE DURATION PARAMETER (PAGE7)-------------------------
//This parameter is used to specify in how many clock cycles of CLK must
//occur prior to setting or unsetting SRCLK/RCLK HI or LO
parameter [N-1:0] pulse_duration = 6; //safety time > 100ns, >=6 CLK cycles
//---------------------SETUP TIME PARAMETER (PAGE7)-----------------------------
//This parameter is used to control how much time is required to setup the
//SER_OUT signal prior to setting SRCLK HI.
//Note there is no required hold duration, once the signal is written to SER,
//and SRCLK has gone HI, the next signal can be immediately setup
parameter [N-1:0] setup_time = 7; //Safety time > 125ns, >=7 CLK cycles
//==============================================================================
//----------------------------ASSIGN THE SER_OUT--------------------------------
//==============================================================================
//The SER_OUT port can be thought of as a wire to the MSB of an 16-bit shift reg
wire SER_OUT;
assign SER_OUT = shift[16]; //shift data out using MSBF
//==============================================================================
//--------------------------CREATE THE SRCLK SIGNAL-----------------------------
//==============================================================================
//Create the SRCLK signal that will be used to clock-in the serial data
reg [N-1:0] clk_cnt = 0;
reg [1:0] SRCLK_state = 0;
reg SRCLK_toggle = 0; //Instructs the process to toggle SRCLK for a period of time
always @(posedge CLK)
begin
case(SRCLK_state)
0:
begin //Wait for SRCLK_toggle=1
if(SRCLK_toggle == 1)
begin
SRCLK_state <= SRCLK_state + 1;
SRCLK <= 0; //Make sure SRCLK is low
clk_cnt <= 0;
end
end
1:
begin //Wait for the defined setup time, prior to setting SRCLK HI
if(clk_cnt == setup_time - 1)
begin
SRCLK <= 1;
clk_cnt <= 0;
SRCLK_state <= SRCLK_state + 1;
end
else
begin
clk_cnt <= clk_cnt + 1;
end
end
2:
begin //Wait for the defined pulse duration, prior to setting SRCLK LO
if(clk_cnt == pulse_duration - 1)
begin
SRCLK <= 0;
clk_cnt <= 0;
SRCLK_state <= SRCLK_state + 1;
end
else
begin
clk_cnt <= clk_cnt + 1;
end
end
3:
begin //Wait for SRCLK_toggle=0
if(SRCLK_toggle == 0)
begin
SRCLK_state<=0;
end
end
endcase
end
//==============================================================================
//--------------------------CREATE THE RCLK SIGNAL------------------------------
//==============================================================================
//Create the RCLK signal that will be used to clock-out the parallel data
reg [N-1:0] clk_cnt2 = 0;
reg [1:0] RCLK_state = 0;
reg RCLK_toggle = 0; //Instructs the process to toggle RCLK for a period of time
always @(posedge CLK)
begin
case(RCLK_state)
0:
begin //Wait for RCLK_toggle=1
if(RCLK_toggle == 1)
begin
RCLK_state <= RCLK_state + 1;
RCLK <= 0; //Make sure RCLK is low
clk_cnt2 <= 0;
end
end
1:
begin //Wait for the defined setup time, prior to setting RCLK HI
if(clk_cnt2 == setup_time - 1)
begin
RCLK <= 1;
clk_cnt2 <= 0;
RCLK_state <= RCLK_state + 1;
end
else
begin
clk_cnt2 <= clk_cnt2 + 1;
end
end
2:
begin //Wait for the defined pulse duration, prior to setting SRCLK LO
if(clk_cnt2 == pulse_duration - 1)
begin
RCLK <= 0;
clk_cnt2 <= 0;
RCLK_state <= RCLK_state + 1;
end
else
begin
clk_cnt2 <= clk_cnt2 + 1;
end
end
3:
begin //Wait for RCLK_toggle=0
if(RCLK_toggle==0)
begin
RCLK_state <= 0;
end
end
endcase
end
//==============================================================================
//-------------------CREATE THE FUNCTIONAL SWITCHING LOGIC----------------------
//==============================================================================
reg [1:0] state = 0; //Statemachine variable
reg [1:0] substate = 0;
reg [3:0] cnt = 0;
reg init_done = 0;
always @(posedge CLK)
begin
case(state)
0:
begin //-----------------------------Populate the FPGA's shift register
if(EN_IN==1)
begin //Only start the statemachine when input is enabled
shift[15:0] <= DATA_IN;
cnt <= 0;
state <= state + 1;
RDY <= 0;
SRCLK_toggle <= 0;
RCLK_toggle <= 0;
substate <= 0;
end
else
begin
RDY <= 1;
cnt <= 0;
SRCLK_toggle <= 0;
RCLK_toggle <= 0;
state <= 0;
substate <= 0;
end
end
1:
begin //-----------------------------------------Push the bits out MSBF
case(substate)
0:
begin //PUSH DATA ON SER
shift[16:1] <= shift[15:0];
shift[0] <= 0;
substate <= substate + 1;
end
1:
begin //PULSE SRCLK
SRCLK_toggle <= 1;
substate <= substate + 1;
end
2:
begin //TURN OFF THE TOGGLE BIT
if(SRCLK == 1)
begin
SRCLK_toggle <= 0;
substate <= substate + 1;
end
end
3:
begin //WHEN SRCLK GOES LOW, CHECK & UPDATE cnt
if(SRCLK == 0)
begin
if(cnt == 15)
begin
//All bits have been shifted
state <= state + 1;
cnt <= 0;
end
else
begin
//We have more bits to shift
cnt <= cnt + 1;
end
substate <= 0;
end
end
endcase
end
2:
begin //--------------------------Update & Activate the parallel output
//First Pulse RCLK
//Then indicate init_done
case(substate)
0:
begin //PULSE RCLK
RCLK_toggle <= 1;
substate <= substate + 1;
end
1:
begin //TURN OFF THE TOGGLE BIT
if(RCLK == 1)
begin
RCLK_toggle <= 0;
substate <= substate + 1;
end
end
2:
begin //WHEN RCLK GOES LOW, CHECK & UPDATE cnt
if(RCLK == 0)
begin
state <= 0;
substate <= 0;
init_done <= 1;
RDY <= 1;
end
end
endcase
end
default:
begin
state <= 0;
substate <= 0;
init_done <= 0;
RDY <= 1;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__XOR2_BEHAVIORAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xor2 (
VPWR,
VGND,
X ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
// Local signals
wire xor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR2_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NOR2B_FUNCTIONAL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor2b (
Y ,
A ,
B_N
);
// Module ports
output Y ;
input A ;
input B_N;
// Local signals
wire not0_out ;
wire and0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y, not0_out, B_N );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const long long M = 1000000007; const double pi = 3.141592653589793238463; bool vow(char ch) { return ch == a || ch == e || ch == i || ch == o || ch == u ; } bool isPrime(long long n) { for (long long i = 2; i * i <= n; i++) if (n % i == 0) return false; return true; } long long fast_exp(long long x, long long n) { long long ans = 1; while (n) { if (n & 1) { ans *= x; ans %= M; } n = n >> 1; x = (x * x) % M; } return ans; } long long inverse(long long x) { return fast_exp(x, M - 2); } long long comb(long long n, long long r) { if (r == 0) return 1; else { long long ans = n % M; ans *= comb(n - 1, r - 1) % M; ans %= M; ans *= inverse(r) % M; ans %= M; return ans; } } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); ; long long n, m, k; cin >> n >> m >> k; cout << (comb(n - 1, 2 * k) % M * comb(m - 1, 2 * k) % M) % M; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double eps = 1e-6; template <class T> T gcd(T a, T b) { if (!b) return a; return gcd(b, a % b); } const int maxn = 1e6 + 10; int n, m; int phi[maxn]; int a[maxn]; int get(int x) { int res = x; for (long long i = 2; i * i <= x; i++) { if (x % i == 0) { res = res / i * (i - 1); while (x % i == 0) x /= i; } } if (x > 1) res = res / x * (x - 1); return res; } int qpow(int b, int n, int mod) { int res = 1; while (n) { if (n & 1) res = 1LL * res * b >= mod ? 1LL * res * b % mod + mod : res * b; b = 1LL * b * b >= mod ? 1LL * b * b % mod + mod : b * b; n >>= 1; } return res; } int solve(int l, int r, int k) { if (phi[k] == 1) return 1; if (l == r) { if (a[l] < phi[k]) return a[l]; else return a[l] % phi[k] + phi[k]; } else return qpow(a[l], solve(l + 1, r, k + 1), phi[k]); } int main() { scanf( %d , &n); scanf( %d , &phi[0]); while (phi[m] != 1) { phi[m + 1] = get(phi[m]); m++; } for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } int q; scanf( %d , &q); for (int i = 0; i < q; i++) { int l, r; scanf( %d , &l); scanf( %d , &r); int ans = solve(l, r, 0) % phi[0]; printf( %d n , ans); } return 0; }
|
/*
-- ============================================================================
-- FILE NAME : uart_rx.v
-- DESCRIPTION : UARTÊÜÐť⥸¥å©`¥ë
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "uart.h"
/********** ¥â¥¸¥å©`¥ë **********/
module uart_rx (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ÖÆÓùÐźŠ**********/
output wire rx_busy, // ÊÜÐÅÖХե饰
output reg rx_end, // ÊÜÐÅÍêÁËÐźÅ
output reg [`ByteDataBus] rx_data, // ÊÜÐťǩ`¥¿
/********** UARTÊÜÐÅÐźŠ**********/
input wire rx // UARTÊÜÐÅÐźÅ
);
/********** ÄÚ²¿¥ì¥¸¥¹¥¿ **********/
reg [`UartStateBus] state; // ¥¹¥Æ©`¥È
reg [`UartDivCntBus] div_cnt; // ·ÖÖÜ¥«¥¦¥ó¥¿
reg [`UartBitCntBus] bit_cnt; // ¥Ó¥Ã¥È¥«¥¦¥ó¥¿
/********** ÊÜÐÅÖХե饰¤ÎÉú³É **********/
assign rx_busy = (state != `UART_STATE_IDLE) ? `ENABLE : `DISABLE;
/********** ÊÜÐÅÕÀí **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ·ÇͬÆڥꥻ¥Ã¥È */
rx_end <= #1 `DISABLE;
rx_data <= #1 `BYTE_DATA_W'h0;
state <= #1 `UART_STATE_IDLE;
div_cnt <= #1 `UART_DIV_RATE / 2;
bit_cnt <= #1 `UART_BIT_CNT_W'h0;
end else begin
/* ÊÜÐÅ¥¹¥Æ©`¥È */
case (state)
`UART_STATE_IDLE : begin // ¥¢¥¤¥É¥ë×´B
if (rx == `UART_START_BIT) begin // ÊÜÐÅé_ʼ
state <= #1 `UART_STATE_RX;
end
rx_end <= #1 `DISABLE;
end
`UART_STATE_RX : begin // ÊÜÐÅÖÐ
/* ¥¯¥í¥Ã¥¯·ÖÖܤˤè¤ë¥Ü©`¥ì©`¥ÈÕ{Õû */
if (div_cnt == {`UART_DIV_CNT_W{1'b0}}) begin // ºÁË
/* ´Î¥Ç©`¥¿¤ÎÊÜÐÅ */
case (bit_cnt)
`UART_BIT_CNT_STOP : begin // ¥¹¥È¥Ã¥×¥Ó¥Ã¥È¤ÎÊÜÐÅ
state <= #1 `UART_STATE_IDLE;
bit_cnt <= #1 `UART_BIT_CNT_START;
div_cnt <= #1 `UART_DIV_RATE / 2;
/* ¥Õ¥ì©`¥ß¥ó¥°¥¨¥é©`¤Î¥Á¥§¥Ã¥¯ */
if (rx == `UART_STOP_BIT) begin
rx_end <= #1 `ENABLE;
end
end
default : begin // ¥Ç©`¥¿¤ÎÊÜÐÅ
rx_data <= #1 {rx, rx_data[`BYTE_MSB:`LSB+1]};
bit_cnt <= #1 bit_cnt + 1'b1;
div_cnt <= #1 `UART_DIV_RATE;
end
endcase
end else begin // ¥«¥¦¥ó¥È¥À¥¦¥ó
div_cnt <= #1 div_cnt - 1'b1;
end
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVN_BLACKBOX_V
`define SKY130_FD_SC_HS__EINVN_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__einvn (
A ,
TE_B,
Z
);
input A ;
input TE_B;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int INF = (int)1e9; const int N = 155; int old[N][N * N]; int now[N][N * N]; int q[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); int n, k, s; cin >> n >> k >> s; for (int i = 0; i < n; i++) cin >> q[i]; for (int i = 0; i < N; i++) for (int j = 0; j < N * N / 2; j++) old[i][j] = INF; old[0][0] = 0; for (int pos = 0; pos < n; pos++) { for (int i = 0; i < N; i++) for (int j = 0; j < N * N / 2; j++) now[i][j] = INF; for (int taken = 0; taken <= k; taken++) { for (int swaps = 0; swaps <= N * N / 2; swaps++) { now[taken][swaps] = min(now[taken][swaps], old[taken][swaps]); if (taken <= pos) now[taken + 1][swaps + pos - taken] = min( now[taken + 1][swaps + pos - taken], old[taken][swaps] + q[pos]); } } for (int i = 0; i < N; i++) for (int j = 0; j < N * N / 2; j++) old[i][j] = now[i][j]; } int res = INF; for (int swaps = 0; swaps <= min(N * N / 2 - 1, s); swaps++) res = min(res, now[k][swaps]); cout << res << endl; return 0; }
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
module loacal_sw(
input clk,
input reset,
output reg [31:0] data_out,
input [64:0] command,
input command_wr,
output reg ale,
output reg cs_n,
output reg rd_wr,
output reg [31:0] data,
input ack_n_um,
input [31:0] rdata_um
);
reg command_rd;
reg [64:0] command_q_r;
wire [64:0] command_q;
wire command_wr_empty;
reg [7:0] count;
reg [2:0] current_state;
localparam
idle_s = 'd1,
ale_s = 'd2,
cs_s = 'd3,
wait_ack_s = 'd4,
wait_addr_s = 'd5,
wait_addr_s1 = 'd6;
always @(posedge clk or negedge reset)
if(!reset) begin
ale <= 1'b0;
cs_n <= 1'b1;
rd_wr <= 1'b1;
data <= 32'b0;
command_rd <= 1'b0;
command_q_r <= 65'b0;
data_out <= 32'b0;
count <= 8'b0;
current_state <= idle_s;
end
else begin
case(current_state)
idle_s: begin
ale <= 1'b0;
cs_n <= 1'b1;
rd_wr <= 1'b1;
count <= 8'b0;
command_rd <= 1'b0;
if(command_wr_empty == 1'b1) begin
current_state <= idle_s;
end
else begin
command_rd <= 1'b1;
command_q_r <= command_q;
data <= command_q[63:32];
rd_wr <= command_q[64]; //0:wr 1:read
current_state <= ale_s;
end
end
ale_s : begin
ale <= 1'b1;
command_rd <= 1'b0;
current_state <= cs_s;
end
cs_s: begin
ale <= 1'b0;
//cs_n <= 1'b0;
//data <= command_q_r[31:0];
current_state <= wait_addr_s;
end
wait_addr_s:begin
current_state <= wait_addr_s1;
end
wait_addr_s1: begin
data <= command_q_r[31:0];
cs_n <= 1'b0;
current_state <= wait_ack_s;
end
wait_ack_s: begin
if(ack_n_um == 1'b0) begin
cs_n <= 1'b0;
data_out <= rdata_um;
current_state <= idle_s;
end
else begin
count <= count + 1'b1;
if(count[7:4] == 4'b1111) begin
current_state <= idle_s;
end
else begin
current_state <= wait_ack_s;
end
end
end
endcase
end
fifo_65_256 command_fifo(//crc check result fifo;
.aclr(!reset),
.clock(clk),
.data(command),
.rdreq(command_rd),
.wrreq(command_wr),
.empty(command_wr_empty),
.q(command_q)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, k; cin >> n >> k; string s; cin >> s; vector<long long> l_r, r_l; long long count = k + 1; for (long long i = 0; i < n; i++) { if (s[i] == 1 ) { count = 0; l_r.push_back(0); } else if (s[i] == 0 ) { count++; if (count > k) l_r.push_back(1); else l_r.push_back(0); } } count = k + 1; for (long long i = n - 1; i >= 0; i--) { if (s[i] == 1 ) { count = 0; r_l.push_back(0); } else if (s[i] == 0 ) { count++; if (count > k) r_l.push_back(1); else r_l.push_back(0); } } reverse(r_l.begin(), r_l.end()); long long i = 0, ans = 0; while (i < n) { if (l_r[i] && r_l[i]) { ans++; i += k; } i++; } cout << ans << n ; return; } int main() { long long t; cin >> t; for (long long i = 0; i < t; i++) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, a[300010][27]; int val[300010], cost[610]; int fail[300010]; string st[610]; char s[300010], p[300010]; int main() { int T, op, len, slen, i, j, k, x; long long ans; for (scanf( %d , &T); T; --T) { scanf( %d %s , &op, s); len = strlen(s); if (op <= 2) { if (len <= 500) { for (i = 0, j = 0; i < len; ++i) { if (!a[j][x = s[i] - a ]) a[j][x] = ++m; j = a[j][x]; } val[j] += op == 1 ? 1 : -1; } else { st[++n] = s; cost[n] = op == 1 ? 1 : -1; } } else { ans = 0; for (i = 0; i < len; ++i) for (k = i, j = 0; k < len; ++k) { if (!a[j][x = s[k] - a ]) break; j = a[j][x]; ans += val[j]; } for (i = 1; i <= n; ++i) { if ((slen = st[i].length()) > len) continue; fail[0] = fail[1] = 0; for (j = 1; j < slen; ++j) { for (k = fail[j]; k && st[i][k] != st[i][j]; k = fail[k]) ; fail[j + 1] = st[i][k] == st[i][j] ? k + 1 : 0; } for (j = 0, k = 0; j < len; ++j) { while (k && st[i][k] != s[j]) k = fail[k]; if (st[i][k] == s[j]) ++k; if (k == slen) { ans += cost[i]; k = fail[k]; } } } cout << ans << endl; } } return 0; }
|
/*
File: ewrapper_io_rx_slow.v
This file is part of the Parallella Project .
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
`include "fpga_constants.v"
module ewrapper_io_rx_slow (/*AUTOARG*/
// Outputs
CLK_DIV_OUT, DATA_IN_TO_DEVICE,
// Inputs
CLK_IN_P, CLK_IN_N, CLK_RESET, IO_RESET, DATA_IN_FROM_PINS_P,
DATA_IN_FROM_PINS_N, BITSLIP
);
//###########
//# INPUTS
//###########
input CLK_IN_P; // Differential clock from IOB
input CLK_IN_N;
input CLK_RESET;
input IO_RESET;
input [8:0] DATA_IN_FROM_PINS_P;
input [8:0] DATA_IN_FROM_PINS_N;
input BITSLIP;
//#############
//# OUTPUTS
//#############
output CLK_DIV_OUT; // Slow clock output
output [71:0] DATA_IN_TO_DEVICE;
//############
//# REGS
//############
reg [3:0] clk_edge;
reg rx_pedge_first;
reg [8:0] clk_even_reg;
reg [8:0] clk_odd_reg;
reg [8:0] clk0_even;
reg [8:0] clk1_even;
reg [8:0] clk2_even;
reg [8:0] clk3_even;
reg [8:0] clk0_odd;
reg [8:0] clk1_odd;
reg [8:0] clk2_odd;
reg [8:0] clk3_odd;
reg [71:0] rx_out_sync_pos;
reg rx_outclock_del_45;
reg rx_outclock_del_135;
reg [71:0] rx_out;
//############
//# WIRES
//############
wire reset;
wire rx_outclock;
wire rxi_lclk;
wire [71:0] rx_out_int;
wire [8:0] rx_in_t;
wire [8:0] rx_in;
wire [8:0] clk_even;
wire [8:0] clk_odd;
wire [8:0] iddr_q1;
wire [8:0] iddr_q2;
// Inversions for E16/E64 migration
`ifdef TARGET_E16
assign rx_in = rx_in_t;
assign clk_even = iddr_q1;
assign clk_odd = iddr_q2;
`define CLKEDGE_DDR "SAME_EDGE_PIPELINED"
`elsif TARGET_E64
assign rx_in = ~rx_in_t;
assign clk_even = iddr_q2;
assign clk_odd = iddr_q1;
`define CLKEDGE_DDR "SAME_EDGE"
`endif
/*AUTOINPUT*/
/*AUTOWIRE*/
assign reset = IO_RESET;
assign DATA_IN_TO_DEVICE[71:0] = rx_out[71:0];
assign CLK_DIV_OUT = rx_outclock;
//################################
//# Input Buffers Instantiation
//################################
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (`IOSTD_ELINK))
ibufds_inst[0:8]
(.I (DATA_IN_FROM_PINS_P),
.IB (DATA_IN_FROM_PINS_N),
.O (rx_in_t));
//#####################
//# Clock Buffers
//#####################
IBUFGDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (`IOSTD_ELINK))
ibufds_clk_inst
(.I (CLK_IN_P),
.IB (CLK_IN_N),
.O (rxi_lclk));
// BUFR generates the slow clock
BUFR
#(.SIM_DEVICE("7SERIES"),
.BUFR_DIVIDE("4"))
clkout_buf_inst
(.O (rx_outclock),
.CE(1'b1),
.CLR(CLK_RESET),
.I (rxi_lclk));
//#################################
//# De-serialization Cycle Counter
//#################################
always @ (posedge rxi_lclk) begin
if(rx_pedge_first)
clk_edge <= 4'b1000;
else
clk_edge <= {clk_edge[2:0], clk_edge[3]};
end
//################################################################
//# Posedge Detection of the Slow Clock in the Fast Clock Domain
//################################################################
always @ (negedge rxi_lclk) begin
rx_outclock_del_45 <= rx_outclock;
rx_outclock_del_135 <= rx_outclock_del_45;
rx_pedge_first <= ~rx_outclock_del_45 & ~rx_outclock_del_135;
end
//#############################
//# De-serialization Output
//#############################
// Synchronizing the clocks (fast to slow)
always @ (posedge rxi_lclk or posedge reset)
if(reset)
rx_out_sync_pos <= 72'd0;
else
rx_out_sync_pos <= rx_out_int;
always @ (posedge rx_outclock or posedge reset)
if(reset)
rx_out <= 72'd0;
else
rx_out <= rx_out_sync_pos;
//#############################
//# IDDR instantiation
//#############################
IDDR #(
.DDR_CLK_EDGE (`CLKEDGE_DDR),
.SRTYPE ("ASYNC"))
iddr_inst[0:8] (
.Q1 (iddr_q1),
.Q2 (iddr_q2),
.C (rxi_lclk),
.CE (1'b1),
.D (rx_in),
.R (1'b0),
.S (1'b0));
//#############################
//# De-serialization Registers
//#############################
always @ (posedge rxi_lclk or posedge reset) begin
if(reset) begin
clk_even_reg <= 9'd0;
clk_odd_reg <= 9'd0;
clk0_even <= 9'd0;
clk0_odd <= 9'd0;
clk1_even <= 9'd0;
clk1_odd <= 9'd0;
clk2_even <= 9'd0;
clk2_odd <= 9'd0;
clk3_even <= 9'd0;
clk3_odd <= 9'd0;
end else begin
clk_even_reg <= clk_even;
clk_odd_reg <= clk_odd;
if(clk_edge[0]) begin
clk0_even <= clk_even_reg;
clk0_odd <= clk_odd_reg;
end
if(clk_edge[1]) begin
clk1_even <= clk_even_reg;
clk1_odd <= clk_odd_reg;
end
if(clk_edge[2]) begin
clk2_even <= clk_even_reg;
clk2_odd <= clk_odd_reg;
end
if(clk_edge[3]) begin
clk3_even <= clk_even_reg;
clk3_odd <= clk_odd_reg;
end
end // else: !if(reset)
end // always @ (posedge rxi_lclk or posedge reset)
//#####################################
//# De-serialization Data Construction
//#####################################
assign rx_out_int[71:64]={clk0_even[8],clk0_odd[8],clk1_even[8],clk1_odd[8],
clk2_even[8],clk2_odd[8],clk3_even[8],clk3_odd[8]};
assign rx_out_int[63:56]={clk0_even[7],clk0_odd[7],clk1_even[7],clk1_odd[7],
clk2_even[7],clk2_odd[7],clk3_even[7],clk3_odd[7]};
assign rx_out_int[55:48]={clk0_even[6],clk0_odd[6],clk1_even[6],clk1_odd[6],
clk2_even[6],clk2_odd[6],clk3_even[6],clk3_odd[6]};
assign rx_out_int[47:40]={clk0_even[5],clk0_odd[5],clk1_even[5],clk1_odd[5],
clk2_even[5],clk2_odd[5],clk3_even[5],clk3_odd[5]};
assign rx_out_int[39:32]={clk0_even[4],clk0_odd[4],clk1_even[4],clk1_odd[4],
clk2_even[4],clk2_odd[4],clk3_even[4],clk3_odd[4]};
assign rx_out_int[31:24]={clk0_even[3],clk0_odd[3],clk1_even[3],clk1_odd[3],
clk2_even[3],clk2_odd[3],clk3_even[3],clk3_odd[3]};
assign rx_out_int[23:16]={clk0_even[2],clk0_odd[2],clk1_even[2],clk1_odd[2],
clk2_even[2],clk2_odd[2],clk3_even[2],clk3_odd[2]};
assign rx_out_int[15:8] ={clk0_even[1],clk0_odd[1],clk1_even[1],clk1_odd[1],
clk2_even[1],clk2_odd[1],clk3_even[1],clk3_odd[1]};
assign rx_out_int[7:0] ={clk0_even[0],clk0_odd[0],clk1_even[0],clk1_odd[0],
clk2_even[0],clk2_odd[0],clk3_even[0],clk3_odd[0]};
endmodule // dv_io_rx
|
// -*- Mode: Verilog -*-
// Filename : basic.v
// Description : Basic Picoblaze Example Project
// Author : Philip Tracton
// Created On : Thu May 21 22:30:44 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 21 22:30:44 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
module basic (/*AUTOARG*/
// Inouts
SWITCHES, LEDS,
// Inputs
CLK_IN, RESET_IN
) ;
input CLK_IN;
input RESET_IN;
inout [7:0] SWITCHES;
inout [7:0] LEDS;
//
// Wires and Registers
//
wire [7:0] in_port;
wire [7:0] LEDS;
wire [7:0] port_id;
wire [7:0] out_port;
wire [7:0] gpio_switches_data_out;
wire [7:0] gpio_leds_data_out;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire CLK_OUT; // From syscon of system_controller.v
wire RESET_OUT; // From syscon of system_controller.v
// End of automatics
/*AUTOREG*/
//
// System Controller
//
system_controller syscon(/*AUTOINST*/
// Outputs
.CLK_OUT (CLK_OUT),
.RESET_OUT (RESET_OUT),
// Inputs
.CLK_IN (CLK_IN),
.RESET_IN (RESET_IN));
// assign CLK_OUT = CLK_IN;
// assign RESET_OUT = RESET_IN;
//
// Picoblaze CPU
//
cpu Picoblaze(
// Outputs
.port_id (port_id[7:0]),
.out_port (out_port[7:0]),
.write_strobe (write_strobe),
.read_strobe (read_strobe),
.interrupt_ack (interrupt_ack),
// Inputs
.clk (CLK_OUT),
.in_port (in_port[7:0]),
.interrupt (interrupt),
.kcpsm6_sleep (kcpsm6_sleep),
.cpu_reset (RESET_OUT));
assign in_port = gpio_leds_data_out | gpio_switches_data_out;
assign interrupt = gpio_switches_interrupt;
assign kcpsm6_sleep = 0;
//
// LED GPIO
//
pb_gpio gpio_leds(
// Outputs
.data_out(gpio_leds_data_out),
.interrupt(gpio_leds_interrupt),
// Inouts
.gpio(LEDS),
// Inputs
.clk(CLK_OUT),
.reset(RESET_OUT),
.port_id(port_id),
.data_in(out_port),
.read_strobe(read_strobe),
.write_strobe(write_strobe));
//
// Switches GPIO
//
pb_gpio #(.GPIO_BASE_ADDRESS(8))
gpio_switches(
// Outputs
.data_out(gpio_switches_data_out),
.interrupt(gpio_switches_interrupt),
// Inouts
.gpio(SWITCHES),
// Inputs
.clk(CLK_OUT),
.reset(RESET_OUT),
.port_id(port_id),
.data_in(out_port),
.read_strobe(read_strobe),
.write_strobe(write_strobe));
endmodule // basic
|
// Computer_System_mm_interconnect_0_avalon_st_adapter_001.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Computer_System_mm_interconnect_0_avalon_st_adapter_001 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
Computer_System_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// csc = c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
`timescale 1ns/100ps
module ad_csc_1 #(
parameter DELAY_DATA_WIDTH = 16) (
// data
input clk,
input [DW:0] sync,
input [23:0] data,
// constants
input [16:0] C1,
input [16:0] C2,
input [16:0] C3,
input [24:0] C4,
// sync is delay matched
output [DW:0] csc_sync_1,
output [ 7:0] csc_data_1);
localparam DW = DELAY_DATA_WIDTH - 1;
// internal wires
wire [24:0] data_1_m_s;
wire [24:0] data_2_m_s;
wire [24:0] data_3_m_s;
wire [DW:0] sync_3_m_s;
// c1*R
ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c1 (
.clk (clk),
.data_a (C1),
.data_b (data[23:16]),
.data_p (data_1_m_s),
.ddata_in (1'd0),
.ddata_out ());
// c2*G
ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c2 (
.clk (clk),
.data_a (C2),
.data_b (data[15:8]),
.data_p (data_2_m_s),
.ddata_in (1'd0),
.ddata_out ());
// c3*B
ad_csc_1_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_c3 (
.clk (clk),
.data_a (C3),
.data_b (data[7:0]),
.data_p (data_3_m_s),
.ddata_in (sync),
.ddata_out (sync_3_m_s));
// sum + c4
ad_csc_1_add #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_add_c4 (
.clk (clk),
.data_1 (data_1_m_s),
.data_2 (data_2_m_s),
.data_3 (data_3_m_s),
.data_4 (C4),
.data_p (csc_data_1),
.ddata_in (sync_3_m_s),
.ddata_out (csc_sync_1));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int n, x, fr, x0, L, R, len, l[4000], f[4000]; string s1[4000], s2[4000], ss, p, p1; int main() { ios::sync_with_stdio(0); cin >> n; for (int i = (1); i <= (n); i++) { cin >> s1[i]; l[i] = s1[i].length() - 1; } for (int i = (1); i <= (n); i++) cin >> s2[i]; for (int i = (1); i <= (n); i++) if (s1[i] != s2[i]) { if (fr) { for (int j = (0); j <= (l[i]); j++) if (s1[i][j] != s2[i][j]) { x = j; break; } for (int j = (0); j <= (L); j++) if (x - j < 0 || s1[i][x - j] != s1[fr][x0 - j] || s2[i][x - j] != s2[fr][x0 - j]) { L = j - 1; break; } for (int j = (0); j <= (R); j++) if (x + j > l[i] || s1[i][x + j] != s1[fr][x0 + j] || s2[i][x + j] != s2[fr][x0 + j]) { R = j - 1; break; } } else { fr = i; for (int j = (0); j <= (l[i]); j++) if (s1[i][j] != s2[i][j]) { x0 = j; break; } L = x0; R = l[i] - x0; } } if (L == -1) { cout << NO n ; return 0; } for (int i = (x0 - L); i <= (x0 + R); i++) p = p + s1[fr][i], p1 = p1 + s2[fr][i]; len = p.length() - 1; f[0] = -1; for (int i = (1); i <= (len); i++) { for (x = f[i - 1]; ~x; x = f[x]) if (p[i - 1] == p[x]) break; f[i] = x + 1; } for (int i = (1); i <= (n); i++) { x = 0; for (int j = (0); j <= (l[i]); j++) { while (~x && p[x] != s1[i][j]) x = f[x]; x++; if (x > len) { ss = s1[i]; for (int k = (0); k <= (len); k++) ss[j - len + k] = p1[k]; if (ss != s2[i]) { cout << NO n ; return 0; } break; } } if (x <= len && s1[i] != s2[i]) { cout << NO n ; return 0; } } cout << YES n << p << n << p1 << n ; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); long long n, m, k; cin >> n >> m >> k; long long l = 1, r = 1e9 + 1; while (r - l > 1) { long long mid = (l + r) / 2; long long ans = mid; if (k >= mid) ans += ((mid - 1) * mid) / 2; if (k > mid) ans += k - mid; if (k < mid) ans += (((mid - 1) + (k - mid)) * ((mid - 1) - (k - mid) + 1)) / 2; long long t = n - k + 1; if (t >= mid) ans += ((mid - 1) * mid) / 2; if (t > mid) ans += t - mid; if (t < mid) ans += (((mid - 1) + (t - mid)) * ((mid - 1) - (t - mid) + 1)) / 2; if (ans > m) r = mid; else l = mid; } cout << l << endl; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream frame joiner
*/
module axis_frame_join #
(
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Prepend data with tag
parameter TAG_ENABLE = 1,
// Tag field width
parameter TAG_WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_COUNT-1:0] s_axis_tvalid,
output wire [S_COUNT-1:0] s_axis_tready,
input wire [S_COUNT-1:0] s_axis_tlast,
input wire [S_COUNT-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Configuration
*/
input wire [TAG_WIDTH-1:0] tag,
/*
* Status signals
*/
output wire busy
);
parameter CL_S_COUNT = $clog2(S_COUNT);
parameter TAG_WORD_WIDTH = (TAG_WIDTH + DATA_WIDTH - 1) / DATA_WIDTH;
parameter CL_TAG_WORD_WIDTH = $clog2(TAG_WORD_WIDTH);
// state register
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_WRITE_TAG = 2'd1,
STATE_TRANSFER = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
reg [CL_TAG_WORD_WIDTH-1:0] frame_ptr_reg = {CL_TAG_WORD_WIDTH{1'b0}}, frame_ptr_next;
reg [CL_S_COUNT-1:0] port_sel_reg = {CL_S_COUNT{1'b0}}, port_sel_next;
reg busy_reg = 1'b0, busy_next;
reg output_tuser_reg = 1'b0, output_tuser_next;
reg [S_COUNT-1:0] s_axis_tready_reg = {S_COUNT{1'b0}}, s_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign busy = busy_reg;
wire [DATA_WIDTH-1:0] input_tdata = s_axis_tdata[port_sel_reg*DATA_WIDTH +: DATA_WIDTH];
wire input_tvalid = s_axis_tvalid[port_sel_reg];
wire input_tlast = s_axis_tlast[port_sel_reg];
wire input_tuser = s_axis_tuser[port_sel_reg];
always @* begin
state_next = STATE_IDLE;
frame_ptr_next = frame_ptr_reg;
port_sel_next = port_sel_reg;
s_axis_tready_next = {S_COUNT{1'b0}};
m_axis_tdata_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
output_tuser_next = output_tuser_reg;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = {CL_TAG_WORD_WIDTH{1'b0}};
port_sel_next = {CL_S_COUNT{1'b0}};
output_tuser_next = 1'b0;
if (TAG_ENABLE) begin
// next cycle if started will send tag, so do not enable input
s_axis_tready_next = 1'b0;
end else begin
// next cycle if started will send data, so enable input
s_axis_tready_next = m_axis_tready_int_early;
end
if (s_axis_tvalid) begin
// input 0 valid; start transferring data
if (TAG_ENABLE) begin
// tag enabled, so transmit it
if (m_axis_tready_int_reg) begin
// output is ready, so short-circuit first tag word
frame_ptr_next = 1;
m_axis_tdata_int = tag;
m_axis_tvalid_int = 1'b1;
end
state_next = STATE_WRITE_TAG;
end else begin
// tag disabled, so transmit data
if (m_axis_tready_int_reg) begin
// output is ready, so short-circuit first data word
m_axis_tdata_int = s_axis_tdata;
m_axis_tvalid_int = 1'b1;
end
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_TAG: begin
// write tag data
if (m_axis_tready_int_reg) begin
// output ready, so send tag word
state_next = STATE_WRITE_TAG;
frame_ptr_next = frame_ptr_reg + 1;
m_axis_tvalid_int = 1'b1;
m_axis_tdata_int = tag >> frame_ptr_reg*DATA_WIDTH;
if (frame_ptr_reg == TAG_WORD_WIDTH-1) begin
s_axis_tready_next = m_axis_tready_int_early << 0;
state_next = STATE_TRANSFER;
end
end else begin
state_next = STATE_WRITE_TAG;
end
end
STATE_TRANSFER: begin
// transfer input data
// set ready for current input
s_axis_tready_next = m_axis_tready_int_early << port_sel_reg;
if (input_tvalid && m_axis_tready_int_reg) begin
// output ready, transfer byte
state_next = STATE_TRANSFER;
m_axis_tdata_int = input_tdata;
m_axis_tvalid_int = input_tvalid;
if (input_tlast) begin
// last flag received, switch to next port
port_sel_next = port_sel_reg + 1;
// save tuser - assert tuser out if ANY tuser asserts received
output_tuser_next = output_tuser_next | input_tuser;
// disable input
s_axis_tready_next = {S_COUNT{1'b0}};
if (S_COUNT == 1 || port_sel_reg == S_COUNT-1) begin
// last port - send tlast and tuser and revert to idle
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = output_tuser_next;
state_next = STATE_IDLE;
end else begin
// otherwise, disable enable next port
s_axis_tready_next = m_axis_tready_int_early << port_sel_next;
end
end
end else begin
state_next = STATE_TRANSFER;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= {CL_TAG_WORD_WIDTH{1'b0}};
port_sel_reg <= {CL_S_COUNT{1'b0}};
s_axis_tready_reg <= {S_COUNT{1'b0}};
output_tuser_reg <= 1'b0;
busy_reg <= 1'b0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
port_sel_reg <= port_sel_next;
s_axis_tready_reg <= s_axis_tready_next;
output_tuser_reg <= output_tuser_next;
busy_reg <= state_next != STATE_IDLE;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t, n, ar[100010]; long long int xr[50010], yr[50010], mr[50010]; while (cin >> t) { for (int i = 0; i < t; i++) { cin >> n; xr[i] = 0; yr[i] = 0; mr[i] = 0; for (int j = 0; j < n; j++) { cin >> ar[j]; if (ar[j] % 3 == 1) xr[i]++; if (ar[j] % 3 == 2) yr[i]++; if (ar[j] % 3 == 0 && ar[j] != 0) mr[i]++; } } for (int i = 0; i < t; i++) { if (xr[i] >= yr[i]) cout << yr[i] + mr[i] + (xr[i] - yr[i] - (xr[i] - yr[i]) % 3) / 3 << endl; else cout << mr[i] + xr[i] + (yr[i] - xr[i] - (yr[i] - xr[i]) % 3) / 3 << endl; } } }
|
`timescale 1ns / 1ps
module mac_test();
reg reset;
reg [31:0] data_in;
reg data_in_clock;
reg data_in_enable;
reg data_in_start;
reg data_in_end;
reg tx_clock;
reg carrier_sense;
reg collision;
wire tx_enable;
wire [7:0] tx_data;
reg [31:0] packet [0:380];
integer i;
mac U_mac (
.reset(reset),
// IN PORT
.data_in(data_in),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
.data_in_start(data_in_start),
.data_in_end(data_in_end),
.tx_clock(tx_clock),
.carrier_sense(carrier_sense),
.collision(collision),
.tx_enable(tx_enable),
.tx_data(tx_data)
);
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,mac_test,U_mac,U_mac.U_tx_sm,U_mac.U_tx_sm.U_crc);
end
initial
begin
$monitor("TX ENABLE: %b, TX DATA: %x", tx_enable, tx_data);
reset = 1;
data_in = 0;
data_in_clock = 0;
data_in_enable = 0;
tx_clock = 0;
data_in_start = 0;
$readmemh("tx.hex", packet);
#15 reset = 0;
// Send a packet
push(packet[0], 1, 0);
for(i = 1; i < 14; i = i + 1)
begin
push(packet[i], 0, 0);
end
push(packet[14], 0, 1);
#120 $finish;
end
always
#20 data_in_clock = ~data_in_clock;
always
#1 tx_clock = ~tx_clock;
task push;
input[31:0] data;
input data_start;
input data_end;
begin
data_in = data;
data_in_enable = 1;
data_in_start = data_start;
data_in_end = data_end;
@(posedge data_in_clock);
#1 data_in_enable = 0;
data_in_start = 0;
data_in_end = 0;
$display("Pushed: %x Start: %b End: %b",data, data_start, data_end );
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2I_BLACKBOX_V
`define SKY130_FD_SC_MS__MUX2I_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux2i (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2I_BLACKBOX_V
|
`timescale 1ns/10ps
`define CLK_PERIOD 4.0
module PATTERN(
output reg clk,
output reg [2:0] circle1,
output reg [2:0] circle2,
output reg [4:0] in,
output reg in_valid,
output reg rst_n,
input [5:0] out,
input out_valid
);
reg [4:0] pixel1 [0:7];
reg [4:0] pixel2 [0:7];
parameter CLK = `CLK_PERIOD;
parameter PATTERN_NUM = 10;
integer latency, total_latency;
integer pattern_num;
integer round;
integer i,j;
integer op;
integer ans[0:7];
integer unsort[0:7];
integer swap;
integer cir1, cir2;
initial begin
total_latency = 0;
end
initial begin
clk = 0;
forever #CLK clk = ~clk;
end
initial begin
in <= 'dx;
in_valid <= 'bx;
rst_n <= 1'b1;
#16;
rst_n <= 1'b0;
#8;
rst_n <= 1'b1;
check_out_rst;
check_out_valid_rst;
in_valid <= 'b0;
#16
@(negedge clk);
for(pattern_num=0;pattern_num<PATTERN_NUM;pattern_num=pattern_num+1) begin
check_out_valid_rst;
if(pattern_num === 0) begin
cir1 = 0;
cir2 = 0;
pixel1[0] = 31; pixel1[1] = 31; pixel1[2] = 31; pixel1[3] = 31; pixel1[4] = 31; pixel1[5] = 31; pixel1[6] = 31; pixel1[7] = 31;
pixel2[0] = 31; pixel2[1] = 31; pixel2[2] = 31; pixel2[3] = 31; pixel2[4] = 31; pixel2[5] = 31; pixel2[6] = 31; pixel2[7] = 31;
end else if(pattern_num === 2) begin
cir1 = 0;
cir2 = 0;
pixel1[0] = 0; pixel1[1] = 1; pixel1[2] = 2; pixel1[3] = 3; pixel1[4] = 4; pixel1[5] = 5; pixel1[6] = 6; pixel1[7] = 7;
pixel2[0] = 0; pixel2[1] = 1; pixel2[2] = 2; pixel2[3] = 3; pixel2[4] = 4; pixel2[5] = 5; pixel2[6] = 6; pixel2[7] = 7;
end else begin
cir1 = {$random()}%8;
cir2 = {$random()}%8;
for(i=0;i<8;i=i+1) begin
pixel1[i] = $random()%32;
pixel2[i] = $random()%32;
end
end
for(i=0;i<8;i=i+1) begin
if(i == 0) begin circle1 <= cir1; circle2 <= cir2; end
else begin circle1 <= 1'bx; circle2 <= 1'bx; end
in_valid <= 1'b1;
in <= pixel1[i];
check_out_valid_rst;
@(negedge clk);
end
for(i=0;i<8;i=i+1) begin
in_valid <= 1'b1;
in <= pixel2[i];
check_out_valid_rst;
@(negedge clk);
end
operate;
in <= 'dx;
in_valid = 1'b0;
wait_out;
for(i=0;i<8;i=i+1) begin
if(out !== ans[i]) begin
$display("");
$display("=================================================");
$display(" Failed!! PATTERN %4d is wrong! ", pattern_num+1);
$display(" ans is %d your ans is %d ", ans[i],out);
$display("=================================================");
$display("");
repeat(8)@(negedge clk);
$finish;
end
@(negedge clk);
end
$display("");
$display(" Pass pattern %3d ", pattern_num+1);
check_out_valid_rst;
@(negedge clk);
end
@(negedge clk);
$display ("--------------------------------------------------------------------");
$display (" Congratulations ! ");
$display (" You have passed all patterns ! ");
$display (" Your total latency is %6d ! ", total_latency);
$display ("--------------------------------------------------------------------");
@(negedge clk);
$finish;
end
task check_out_valid_rst;
begin
if(out_valid !== 1'b0) begin
$display("");
$display("========================================");
$display(" 'out_valid' should be reset !!!!! ");
$display("========================================");
$display("");
@(negedge clk);
$finish;
end
end
endtask
task check_out_rst;
begin
if(out !== 1'b0) begin
$display("");
$display("========================================");
$display(" 'out' should be reset !!!!! ");
$display("========================================");
$display("");
@(negedge clk);
$finish;
end
end
endtask
task wait_out;
begin
latency = 0;
while(!(out_valid === 1'b1)) begin
if(latency > 100) begin
$display("");
$display("========================================");
$display(" Latency too mord !!!! ");
$display("========================================");
$display("");
@(negedge clk);
$finish;
end
latency = latency + 1;
total_latency = total_latency + 1;
@(negedge clk);
end
end
endtask
task operate;
begin
op = cir1 - cir2;
for(i=0;i<8;i=i+1) begin
while(i+op<0) op=op+8;
while(i+op>7) op=op-8;
ans[i] = pixel1[i] + pixel2[i+op];
unsort[i] = pixel1[i] + pixel2[i+op];
end
for(i=0;i<8;i=i+1) begin
for(j=0;j<7;j=j+1) begin
if(ans[j]>ans[j+1]) begin
swap = ans[j];
ans[j] = ans[j+1];
ans[j+1] = swap;
end
end
end
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 17; int n, m, x, y, z, inf; int bin[N], d[N][N], du[N], f[1 << N], q[N]; int main() { for (register int i = 1; i <= 16; ++i) bin[i] = 1 << (i - 1); int sum = 0; scanf( %d , &n); scanf( %d , &m); memset(d, 60, sizeof(d)); inf = d[0][0]; for (register int i = 1; i <= m; ++i) { scanf( %d%d%d , &x, &y, &z); sum += z; du[x]++; du[y]++; d[x][y] = d[y][x] = min(d[x][y], z); } for (register int k = 1; k <= n; ++k) for (register int i = 1; i <= n; ++i) for (register int j = 1; j <= n; ++j) d[i][j] = min(d[i][j], d[i][k] + d[k][j]); for (register int i = 2; i <= n; ++i) if (du[i] && d[1][i] == inf) { puts( -1 ); return 0; } int tot = 0; for (register int i = 1; i <= n; ++i) if (du[i] & 1) q[++tot] = i; int max_statue = bin[tot + 1] - 1; memset(f, 60, sizeof(f)); f[0] = 0; for (register int p = 0; p < max_statue; ++p) { for (register int i = 1; i <= tot; ++i) if (!(bin[i] & p)) { for (register int j = i + 1; j <= tot; ++j) if (!(bin[j] & p)) f[p | bin[i] | bin[j]] = min(f[p | bin[i] | bin[j]], f[p] + d[q[i]][q[j]]); break; } } sum += f[max_statue]; printf( %d n , sum); return 0; }
|
// ======================================================================
// CBC-DES encryption/decryption
// algorithm according to FIPS 46-3 specification
// Copyright (C) 2013 Torsten Meissner
//-----------------------------------------------------------------------
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write:the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
// ======================================================================
`timescale 1ns/1ps
module cbcdes
(
input reset_i, // async reset
input clk_i, // clock
input start_i, // start cbc
input mode_i, // des-mode: 0 = encrypt, 1 = decrypt
input [0:63] key_i, // key input
input [0:63] iv_i, // iv input
input [0:63] data_i, // data input
input valid_i, // input key/data valid flag
output reg ready_o, // ready to encrypt/decrypt
output reg [0:63] data_o, // data output
output valid_o // output data valid flag
);
reg mode;
wire des_mode;
reg start;
reg [0:63] key;
wire [0:63] des_key;
reg [0:63] iv;
reg [0:63] datain;
reg [0:63] datain_d;
reg [0:63] des_datain;
wire validin;
wire [0:63] des_dataout;
reg reset;
reg [0:63] dataout;
assign des_key = (start_i) ? key_i : key;
assign des_mode = (start_i) ? mode_i : mode;
assign validin = valid_i & ready_o;
always @(*) begin
if (~mode_i && start_i) begin
des_datain = iv_i ^ data_i;
end
else if (~mode && ~start_i) begin
des_datain = dataout ^ data_i;
end
else begin
des_datain = data_i;
end
end
always @(*) begin
if (mode && start) begin
data_o = iv ^ des_dataout;
end
else if (mode && ~start) begin
data_o = datain_d ^ des_dataout;
end
else begin
data_o = des_dataout;
end
end
// input register
always @(posedge clk_i, negedge reset_i) begin
if (~reset_i) begin
reset <= 0;
mode <= 0;
start <= 0;
key <= 0;
iv <= 0;
datain <= 0;
datain_d <= 0;
end
else begin
reset <= reset_i;
if (valid_i && ready_o) begin
start <= start_i;
datain <= data_i;
datain_d <= datain;
end
else if (valid_i && ready_o && start_i) begin
mode <= mode_i;
key <= key_i;
iv <= iv_i;
end
end
end
// output register
always @(posedge clk_i, negedge reset_i) begin
if (~reset_i) begin
ready_o <= 0;
dataout <= 0;
end
else begin
if (valid_i && ready_o) begin
ready_o <= 0;
end
else if (valid_o || (reset_i && ~reset)) begin
ready_o <= 1;
dataout <= des_dataout;
end
end
end
// des instance
des i_des (
.reset_i(reset),
.clk_i(clk_i),
.mode_i(des_mode),
.key_i(des_key),
.data_i(des_datain),
.valid_i(validin),
.data_o(des_dataout),
.valid_o(valid_o)
);
endmodule
|
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
module e_transmit(/*AUTOARG*/
// Outputs
esaxi_emrq_full, esaxi_emrq_prog_full, esaxi_emwr_full,
esaxi_emwr_prog_full, emaxi_emrr_full, emaxi_emrr_prog_full,
tx_lclk_p, tx_lclk_n, tx_frame_p, tx_frame_n, tx_data_p, tx_data_n,
// Inputs
reset, txlclk_out, txlclk_p, txlclk_s, s_axi_aclk, m_axi_aclk,
ecfg_dataout, ecfg_tx_clkdiv, ecfg_tx_enable, ecfg_tx_gpio_mode,
esaxi_emrq_wr_en, esaxi_emrq_wr_data, esaxi_emwr_wr_en,
esaxi_emwr_wr_data, emaxi_emrr_wr_en, emaxi_emrr_wr_data,
tx_wr_wait_p, tx_wr_wait_n, tx_rd_wait_p, tx_rd_wait_n
);
//Clocks and reset
input reset;
input txlclk_out; //lclk output
input txlclk_p; //slow speed parallel clock for serializer
input txlclk_s; //high speed serdes clock
input s_axi_aclk; //clock for slave read request and write fifos
input m_axi_aclk; //clock for master read response fifo
//Configuration signals
input [10:0] ecfg_dataout; //data for gpio mode
input [3:0] ecfg_tx_clkdiv; //transmit clock divider
input ecfg_tx_enable; //transmit output buffer enable
input ecfg_tx_gpio_mode;
//Read requests (from axi slave)
input esaxi_emrq_wr_en;
input [102:0] esaxi_emrq_wr_data;
output esaxi_emrq_full;
output esaxi_emrq_prog_full;
//Write requests (from axi slave)
input esaxi_emwr_wr_en;
input [102:0] esaxi_emwr_wr_data;
output esaxi_emwr_full;
output esaxi_emwr_prog_full;
//Read responses (from axi master)
input emaxi_emrr_wr_en;
input [102:0] emaxi_emrr_wr_data;
output emaxi_emrr_full;
output emaxi_emrr_prog_full;
//Transmit signals for IO
output tx_lclk_p; //link clock output (up to 500MHz)
output tx_lclk_n;
output tx_frame_p; //transaction frame signal
output tx_frame_n;
output [7:0] tx_data_p; //transmit data (dual data rate)
output [7:0] tx_data_n;
input tx_wr_wait_p; //incoming pushback on write transactions
input tx_wr_wait_n;
input tx_rd_wait_p; //incoming pushback on read transactions
input tx_rd_wait_n;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/************************************************************/
/*FIFOs */
/************************************************************/
/*fifo_103x16 AUTO_TEMPLATE (
// Outputs
.dout (em@"(substring vl-cell-name 2 4)"_rd_data[102:0]),
.prog_full (e@"(substring vl-cell-name 0 1)"axi_em@"(substring vl-cell-name 2 4)"_prog_full),
.empty (em@"(substring vl-cell-name 2 4)"_empty),
.full (e@"(substring vl-cell-name 0 1)"axi_em@"(substring vl-cell-name 2 4)"_full),
//Inputs
.din (e@"(substring vl-cell-name 0 1)"axi_em@"(substring vl-cell-name 2 4)"_wr_data[103:0]),
.wr_clk (@"(substring vl-cell-name 0 1)"_axi_aclk),
.wr_en (e@"(substring vl-cell-name 0 1)"axi_em@"(substring vl-cell-name 2 4)"_wr_en),
.rd_clk (txlclk_p),
.rd_en (em@"(substring vl-cell-name 2 4)"_rd_en),
.rst (reset),
);
*/
//Read request fifo (from slave)
fifo_103x16 s_rq_fifo(/*AUTOINST*/
// Outputs
.dout (emrq_rd_data[102:0]), // Templated
.empty (emrq_empty), // Templated
.full (esaxi_emrq_full), // Templated
.prog_full (esaxi_emrq_prog_full), // Templated
// Inputs
.din (esaxi_emrq_wr_data[103:0]), // Templated
.rd_clk (txlclk_p), // Templated
.rd_en (emrq_rd_en), // Templated
.rst (reset), // Templated
.wr_clk (s_axi_aclk), // Templated
.wr_en (esaxi_emrq_wr_en)); // Templated
//Write fifo (from slave)
fifo_103x16 s_wr_fifo(/*AUTOINST*/
// Outputs
.dout (emwr_rd_data[102:0]), // Templated
.empty (emwr_empty), // Templated
.full (esaxi_emwr_full), // Templated
.prog_full (esaxi_emwr_prog_full), // Templated
// Inputs
.din (esaxi_emwr_wr_data[103:0]), // Templated
.rd_clk (txlclk_p), // Templated
.rd_en (emwr_rd_en), // Templated
.rst (reset), // Templated
.wr_clk (s_axi_aclk), // Templated
.wr_en (esaxi_emwr_wr_en)); // Templated
//Read response fifo (from master)
fifo_103x16 m_rr_fifo(/*AUTOINST*/
// Outputs
.dout (emrr_rd_data[102:0]), // Templated
.empty (emrr_empty), // Templated
.full (emaxi_emrr_full), // Templated
.prog_full (emaxi_emrr_prog_full), // Templated
// Inputs
.din (emaxi_emrr_wr_data[103:0]), // Templated
.rd_clk (txlclk_p), // Templated
.rd_en (emrr_rd_en), // Templated
.rst (reset), // Templated
.wr_clk (m_axi_aclk), // Templated
.wr_en (emaxi_emrr_wr_en)); // Templated
/************************************************************/
/*ELINK TRANSMIT ARBITER */
/*-arbiter between write (slave), read request (slave), */
/* and read response channel (master) */
/********************1****************************************/
e_tx_arbiter e_tx_arbiter (.clk (txlclk_p),
/*AUTOINST*/
// Outputs
.emwr_rd_en (emwr_rd_en),
.emrq_rd_en (emrq_rd_en),
.emrr_rd_en (emrr_rd_en),
.e_tx_access (e_tx_access),
.e_tx_write (e_tx_write),
.e_tx_datamode (e_tx_datamode[1:0]),
.e_tx_ctrlmode (e_tx_ctrlmode[3:0]),
.e_tx_dstaddr (e_tx_dstaddr[31:0]),
.e_tx_srcaddr (e_tx_srcaddr[31:0]),
.e_tx_data (e_tx_data[31:0]),
// Inputs
.reset (reset),
.emwr_rd_data (emwr_rd_data[102:0]),
.emwr_empty (emwr_empty),
.emrq_rd_data (emrq_rd_data[102:0]),
.emrq_empty (emrq_empty),
.emrr_rd_data (emrr_rd_data[102:0]),
.emrr_empty (emrr_empty),
.e_tx_rd_wait (e_tx_rd_wait),
.e_tx_wr_wait (e_tx_wr_wait),
.e_tx_ack (e_tx_ack));
/************************************************************/
/*ELINK PROTOCOL LOGIC */
/*-translates the 104 bit emesh transaction to elink packeet*/
/************************************************************/
e_tx_protocol e_tx_protocol (/*AUTOINST*/
// Outputs
.e_tx_rd_wait (e_tx_rd_wait),
.e_tx_wr_wait (e_tx_wr_wait),
.e_tx_ack (e_tx_ack),
.txframe_p (txframe_p[7:0]),
.txdata_p (txdata_p[63:0]),
// Inputs
.reset (reset),
.e_tx_access (e_tx_access),
.e_tx_write (e_tx_write),
.e_tx_datamode (e_tx_datamode[1:0]),
.e_tx_ctrlmode (e_tx_ctrlmode[3:0]),
.e_tx_dstaddr (e_tx_dstaddr[31:0]),
.e_tx_srcaddr (e_tx_srcaddr[31:0]),
.e_tx_data (e_tx_data[31:0]),
.txlclk_p (txlclk_p),
.tx_rd_wait (tx_rd_wait),
.tx_wr_wait (tx_wr_wait));
/***********************************************************/
/*ELINK TRANSMIT I/O LOGIC */
/*-parallel data and frame as input */
/*-serializes data for I/O */
/***********************************************************/
e_tx_io e_tx_io (.ioreset (reset),
/*AUTOINST*/
// Outputs
.tx_lclk_p (tx_lclk_p),
.tx_lclk_n (tx_lclk_n),
.tx_frame_p (tx_frame_p),
.tx_frame_n (tx_frame_n),
.tx_data_p (tx_data_p[7:0]),
.tx_data_n (tx_data_n[7:0]),
.tx_wr_wait (tx_wr_wait),
.tx_rd_wait (tx_rd_wait),
// Inputs
.reset (reset),
.tx_wr_wait_p (tx_wr_wait_p),
.tx_wr_wait_n (tx_wr_wait_n),
.tx_rd_wait_p (tx_rd_wait_p),
.tx_rd_wait_n (tx_rd_wait_n),
.txlclk_p (txlclk_p),
.txlclk_s (txlclk_s),
.txlclk_out (txlclk_out),
.txframe_p (txframe_p[7:0]),
.txdata_p (txdata_p[63:0]),
.ecfg_tx_enable (ecfg_tx_enable),
.ecfg_tx_gpio_mode (ecfg_tx_gpio_mode),
.ecfg_tx_clkdiv (ecfg_tx_clkdiv[3:0]),
.ecfg_dataout (ecfg_dataout[10:0]));
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../stubs/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; int t; char a[30]; int main() { cin >> t; while (t--) { string s; cin >> s; int len = s.size(), id = 0; for (int i = 0; i < len; i++) { int temp = 1; while (s[i + 1] == s[i]) { i++; temp++; } if (temp % 2 == 0) continue; int flag = 0; for (int j = 0; j < id; j++) { if (a[j] == s[i]) { flag = 1; break; } } if (!flag) a[id++] = s[i]; } if (!id) cout << endl; else { sort(a, a + id); for (int i = 0; i < id; i++) cout << a[i]; cout << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[2005]; vector<long long> Z; vector<long long> F; int main() { long long n, i, S = 0; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; S += a[i]; } sort(a, a + n); reverse(a, a + n); for (i = 0; i < n; i++) { if (a[i] % 2 == 0) Z.push_back(a[i]); else F.push_back(a[i]); } i = 0; long long j = 0, k = 1, sum1 = 0, sum2 = 0; while (1) { if (k == 0) { if (i >= Z.size()) break; sum1 += Z[i]; i++; k = 1; } else { if (j >= F.size()) break; sum1 += F[j]; j++; k = 0; } } i = 0, j = 0, k = 0; while (1) { if (k == 0) { if (i >= Z.size()) break; sum2 += Z[i]; i++; k = 1; } else { if (j >= F.size()) break; sum2 += F[j]; j++; k = 0; } } long long maxi = max(sum1, sum2); cout << S - maxi; return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom16x2048.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom16x2048 (
address,
clken,
clock,
q);
input [10:0] address;
input clken;
input clock;
output [15:0] q;
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({16{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef OPENMSP430_SIMULATION
altsyncram_component.init_file = "./pmem.mif",
`else
altsyncram_component.init_file = "../../software/memledtest/memledtest.mif",
`endif
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=ROM",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.ram_block_type = "M4K",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "ROM"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../software/memledtest/memledtest.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../software/memledtest/memledtest.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=ROM"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom16x2048_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Mar 28 05:22:50 2017
// Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/sidxb/FPGA/ee2020/ee2020.runs/dds_compiler_0_synth_1/dds_compiler_0_stub.v
// Design : dds_compiler_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0_13,Vivado 2016.4" *)
module dds_compiler_0(aclk, s_axis_phase_tvalid,
s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [23:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: Reset_Delay
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2,oRST_3,oRST_4);
input iCLK;
input iRST;
output reg oRST_0;
output reg oRST_1;
output reg oRST_2;
output reg oRST_3;
output reg oRST_4;
reg [31:0] Cont;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
Cont <= 0;
oRST_0 <= 0;
oRST_1 <= 0;
oRST_2 <= 0;
oRST_3 <= 0;
oRST_4 <= 0;
end
else
begin
if(Cont!=32'h01FFFFFF)
Cont <= Cont+1;
if(Cont>=32'h001FFFFF)
oRST_0 <= 1;
if(Cont>=32'h002FFFFF)
oRST_1 <= 1;
if(Cont>=32'h011FFFFF)
oRST_2 <= 1;
if(Cont>=32'h016FFFFF)
oRST_3 <= 1;
if(Cont>=32'h01FFFFFF)
oRST_4 <= 1;
end
end
endmodule
|
module mult_wrap (
input ck,
input [31:0] i_a, i_b,
input [3:0] i_htId,
input i_vld,
output [63:0] o_res,
output [3:0] o_htId,
output o_vld
);
// Wires & Registers
wire [63:0] c_t6_res;
wire [3:0] c_t1_htId;
wire c_t1_vld;
reg [3:0] r_t2_htId, r_t3_htId, r_t4_htId, r_t5_htId, r_t6_htId;
reg r_t2_vld, r_t3_vld, r_t4_vld, r_t5_vld, r_t6_vld;
// The following example uses a fixed-length pipeline,
// but could be used with any length or a variable length pipeline.
always @(posedge ck) begin
r_t2_htId <= c_t1_htId;
r_t2_vld <= c_t1_vld;
r_t3_htId <= r_t2_htId;
r_t3_vld <= r_t2_vld;
r_t4_htId <= r_t3_htId;
r_t4_vld <= r_t3_vld;
r_t5_htId <= r_t4_htId;
r_t5_vld <= r_t4_vld;
r_t6_htId <= r_t5_htId;
r_t6_vld <= r_t5_vld;
end
// Black box instantiation
multiplier multiplier (.clk(ck), .a(i_a), .b(i_b), .p(c_t6_res));
// Inputs
assign c_t1_htId = i_htId;
assign c_t1_vld = i_vld;
// Outputs
assign o_res = c_t6_res;
assign o_htId = r_t6_htId;
assign o_vld = r_t6_vld;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_TB_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_TB_V
/**
* udp_dlatch$PR_pp$PKG$s: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dlatch_pr_pp_pkg_s.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 RESET = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 RESET = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 RESET = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 RESET = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 RESET = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__udp_dlatch$PR_pp$PKG$s dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PKG_S_TB_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_8_axi_basic_top.v
// Version : 1.7
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_8_axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_8_axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_8_axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> solve(vector<int> a) { int n = (int)a.size(); vector<int> dp(n + 1, 1e9); dp[0] = -1e9; vector<int> ret(n); for (int i = 0; i < n; i++) { int x = (int)(upper_bound(dp.begin(), dp.end(), a[i]) - dp.begin()); ret[i] = x; dp[x] = a[i]; } return ret; } int main() { int n, m; cin >> m >> n; vector<int> a(n); vector<int> delta(n + 1); for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; x--; delta[x]++; delta[y]--; } int temp = 0; for (int i = 0; i < n; i++) { temp += delta[i]; a[i] = temp; } auto l = solve(a); reverse(a.begin(), a.end()); auto r = solve(a); reverse(r.begin(), r.end()); int ans = 0; for (int i = 0; i < n; i++) { ans = max(ans, l[i] + r[i] - 1); } cout << ans; return 0; }
|
// -*- Mode: Verilog -*-
// Filename : cpu.v
// Description : Complete Picoblaze Design
// Author : Philip Tracton
// Created On : Thu May 21 22:33:37 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 21 22:33:37 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
module cpu (/*AUTOARG*/
// Outputs
port_id, out_port, write_strobe, read_strobe, interrupt_ack,
// Inputs
clk, in_port, interrupt, kcpsm6_sleep, cpu_reset
) ;
input clk;
input [7:0] in_port;
output [7:0] port_id;
output [7:0] out_port;
output write_strobe;
output read_strobe;
input interrupt; //See note above
output interrupt_ack;
input kcpsm6_sleep;
input cpu_reset;
/*AUTOWIRE*/
/*AUTOREG*/
//
// Signals for connection of KCPSM6 and Program Memory.
//
wire [11:0] address;
wire [17:0] instruction;
wire [7:0] out_port;
wire [7:0] port_id;
wire bram_enable;
wire k_write_strobe;
wire kcpsm6_reset; //See note above
wire interrupt_ack;
wire read_strobe;
wire write_strobe;
//
// Some additional signals are required if your system also needs to reset KCPSM6.
//
//
// When interrupt is to be used then the recommended circuit included below requires
// the following signal to represent the request made from your system.
//
wire int_request;
kcpsm6 #(
.interrupt_vector (12'h3FF),
.scratch_pad_memory_size(64),
.hwbuild (8'h00))
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
//
// If your design also needs to be able to reset KCPSM6 the arrangement below should be
// used to 'OR' your signal with 'rdl' from the program memory.
//
timers_rom
program_rom ( //Name to match your PSM file
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
assign kcpsm6_reset = cpu_reset;
endmodule // cpu
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_0_V
`define SKY130_FD_SC_LP__A22OI_0_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_0 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_0 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_0_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21AI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O21AI_BEHAVIORAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21AI_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int toint(char a) { return (a - 0 ); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tst; cin >> tst; while (tst--) { string a, s; cin >> a >> s; long long int num = stoll(a); long long int sum = stoll(s); if (s.length() < a.length()) { cout << -1 n ; } else if (a.length() == s.length()) { bool no = false; for (int i = s.length() - 1; i >= 0; i--) { if ((toint(s[i]) - toint(a[i])) < 0) { cout << -1 n ; no = true; break; } } if (!no) { cout << stoll(s) - stoll(a) << n ; } } else if (a.length() < s.length()) { int lastdigit; int lastsub; string ans; bool no = 0; int strlen = s.length(); while (strlen > 0) { lastsub = num % 10; if (sum % 10 - num % 10 < 0) { lastdigit = (sum % 10) + ((sum % 100) - (sum % 10)); sum /= 100; num /= 10; strlen -= 2; } else { lastdigit = sum % 10; sum /= 10; num /= 10; strlen--; } if (lastdigit - lastsub >= 0 && lastdigit - lastsub <= 9) { if (strlen != 0) { ans = to_string(lastdigit - lastsub) + ans; } else { if (lastdigit - lastsub != 0) { ans = to_string(lastdigit - lastsub) + ans; } } } else { cout << -1 n ; no = true; break; } } if (!no) { cout << ans << n ; } } } return 0; }
|
#include <iostream> #include <bits/stdc++.h> #include <stdio.h> #include <cstdlib> #include<algorithm> #include<string.h> #include<map> #include<math.h> using namespace std; int main() { int t; cin>>t; while(t--) { int n,k; cin>>n>>k;int count =0; vector <int> v,a(n);int max=n; if(k>(n-1)/2) { cout<< -1 <<endl; continue; } for(int i=1;i<n;i+=2) { if(count==k) break; a[i]=max; max--; count++; } for(int i=0;i<n;i++) { if(a[i]!=0) continue; a[i]=max; max--; } for(int i=0;i<n;i++) { cout<<a[i]<< ; } cout<<endl; } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Johan Bjork.
// SPDX-License-Identifier: CC0-1.0
parameter N = 4;
interface a_if #(parameter PARAM = 0) ();
logic long_name;
modport source (output long_name);
modport sink (input long_name);
endinterface
module intf_source
(
input logic [N-1:0] intf_input,
a_if.source i_intf_source[N-1:0]
);
generate
for (genvar i=0; i < N;i++) begin
assign i_intf_source[i].long_name = intf_input[i];
end
endgenerate
endmodule
module intf_sink
(
output [N-1:0] a_out,
a_if.sink i_intf_sink[N-1:0]
);
generate
for (genvar i=0; i < N;i++) begin
assign a_out[i] = i_intf_sink[i].long_name;
end
endgenerate
endmodule
module t
(
clk
);
input clk;
logic [N-1:0] a_in;
logic [N-1:0] a_out;
logic [N-1:0] ack_out;
// verilator lint_off LITENDIAN
a_if #(.PARAM(1)) tl_intf [N] ();
// verilator lint_on LITENDIAN
intf_source source(a_in, tl_intf);
intf_sink sink(a_out, tl_intf);
initial a_in = '0;
always @(posedge clk) begin
a_in <= a_in + { {N-1 {1'b0}}, 1'b1 };
ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 };
if (ack_out != a_out) begin
$stop;
end
if (& a_in) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// "and_tree_plusarg.v"
// This variant demonstrates using a plusarg to pass in the name of
// a HAC object file.
// @vcs-flags@ -P pli.tab -sverilog
// @haco@ and_tree.haco-c
// @plusargs@ +PRSIM_OBJ=and_tree.haco-c
`timescale 1ps / 1ps
// `include "standard.v"
`include "standard.v-wrap"
//-----------------------------------------------------------------------------
module _timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg a, b, c, d;
wire z;
initial
begin
string prs_obj;
if (!$value$plusargs("PRSIM_OBJ=%s", prs_obj)) begin
prs_obj = "Missing +PRSIM_OBJ=objfile argument.";
end
$prsim(prs_obj);
$prsim_cmd("echo $start of simulation");
$prsim_cmd("watchall");
$to_prsim("TOP.a", "a");
$to_prsim("TOP.b", "b");
$to_prsim("TOP.c", "c");
$to_prsim("TOP.d", "d");
$from_prsim("z", "TOP.z");
end
// these could be automatically generated
// by finding all globally unique instances of processes
// along with their hierarchical names
// e.g. from hacobjdump of .haco-c file
HAC_AND2 and_0();
defparam and_0.prsim_name="mytree.and_0";
HAC_AND2 and_1();
defparam and_1.prsim_name="mytree.and_1";
HAC_AND2 and_2();
defparam and_2.prsim_name="mytree.and_2";
initial
begin
#10 a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
d <= 1'b0;
#100 a <= 1'b1;
b <= 1'b1;
c <= 1'b1;
d <= 1'b1;
#100 a <= 1'b0;
#100 d <= 1'b0;
#100 a <= 1'b1;
#100 d <= 1'b1;
#50 $finish;
end
endmodule
|
`timescale 1ns / 1ps
module tx_sm_tb ();
`include "dut.v"
integer i;
initial
begin
//$dumpfile("test.vcd");
//$dumpvars(0,tx_sm_tb,U_tx_sm);
end
initial
begin
#15 reset = 0;
// Will initially wait IFG before making any transmissions
// Set fifo_count to 1 and check IFG delay before tx_enable is asserted
// Clock flips every 5ns -> 10ns period
// tx_enable_monitor will take care of these checks
fifo_count = 1;
#110
expected_tx_enable = 1;
// MAC should then start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Followed by the frame data we supply
// 10 Bytes
fork
// Data Start
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
// Data End
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
// Followed by padding
// 50 bytes
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
// Followed by CRC
// 4 bytes
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
// Wait IFG and send the same packet again
#120
// Assert Carrier Sense - Should have no effect in Full Duplex
carrier_sense = 1;
expected_tx_enable = 1;
// MAC should start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Followed by the frame data we supply
// 10 Bytes
fork
// Data Start
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
// Data End
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
// Followed by padding
// 50 bytes
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
// Followed by CRC
// 4 bytes
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
// Wait IFG and send the same packet again
#120
expected_tx_enable = 1;
// MAC should start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Assert a collision - Should have no effect in Full Duplex
collision = 1;
// Followed by the frame data we supply
// 10 Bytes
fork
// Data Start
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
// Data End
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
// Followed by padding
// 50 bytes
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
// Followed by CRC
// 4 bytes
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-10; const double PI = acos(-1.0); int dp[51][51][51]; int dfs(int n, int m, int k) { if (dp[n][m][k] >= 0) return dp[n][m][k]; if (k == 0 || n * m == k) return dp[n][m][k] = 0; dp[n][m][k] = 1e9; for (int j = 0; j <= k; ++j) { for (int i = 1; i < n; ++i) dp[n][m][k] = min(dp[n][m][k], dfs(n - i, m, k - j) + dfs(i, m, j) + m * m); for (int i = 1; i < m; ++i) dp[n][m][k] = min(dp[n][m][k], dfs(n, m - i, k - j) + dfs(n, i, j) + n * n); } return dp[n][m][k]; } int main() { cin.tie(0); ios_base::sync_with_stdio(false); fill((int*)dp, (int*)dp + 51 * 51 * 51, -1); int T; cin >> T; while (T--) { int n, m, k; cin >> n >> m >> k; cout << dfs(n, m, k) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 8e6 + 7, mod = 998244353, root = 3; long long x[N], n, m, i, j, ma, mb, inv, res, b[N], ans[N], L, R[N]; long long pow_mod(long long x, long long n) { long long res = 1; while (n) { if (n & 1) res = 1LL * x * res % mod; x = 1LL * x * x % mod; n >>= 1; } return res; } void ntt(long long* x, long long type) { for (long long i = 0; i < n; ++i) if (i < R[i]) swap(x[i], x[R[i]]); for (long long i = 1; i < n; i <<= 1) { long long wn = pow_mod(root, type == 1 ? (mod - 1) / (i << 1) : (mod - 1 - (mod - 1) / (i << 1))); for (long long p = i << 1, j = 0; j < n; j += p) { long long w = 1; for (long long k = 0; k < i; ++k, w = 1LL * wn * w % mod) { long long l = x[j + k], r = 1LL * x[j + k + i] * w % mod; x[j + k] = (l + r) % mod; x[j + k + i] = (l - r + mod) % mod; } } } } void fpow(long long sz) { ntt(ans, 1); ntt(x, 1); while (sz) { if (sz & 1) { for (long long i = 0; i < n; i++) ans[i] = 1ll * ans[i] * x[i] % mod; } for (long long i = 0; i < n; i++) x[i] = 1ll * x[i] * x[i] % mod; sz >>= 1; } ntt(ans, -1); } int32_t main() { ans[0] = 1; long long sz, k, tx; cin >> sz >> k; for (long long i = 1; i <= k; i++) { scanf( %d , &tx); x[tx] = 1; } for (m = 200000 * 9 + 7, n = 1; n <= m; n <<= 1) L++; for (i = 0; i < n; ++i) R[i] = (R[i >> 1] >> 1) | ((i & 1) << L - 1); fpow(sz / 2); long long cnt = 0; inv = pow_mod(n, mod - 2); for (long long i = 0; i < n; i++) cnt = (cnt + (ans[i] % mod * inv % mod) * (ans[i] % mod * inv % mod) % mod) % mod; cout << cnt << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_FUNCTIONAL_V
|
module SensorFSM (
input Reset_n_i,
input Clk_i,
input In0_i,
input In1_i,
input In2_i,
input In3_i,
input In4_i,
input In5_i,
input In6_i,
input In7_i,
input In8_i,
input In9_i,
output Out0_o,
output Out1_o,
output Out2_o,
output Out3_o,
output Out4_o,
output Out5_o,
output Out6_o,
output Out7_o,
output Out8_o,
output Out9_o,
input CfgMode_i,
input CfgClk_i,
input CfgShift_i,
input CfgDataIn_i,
output CfgDataOut_o
);
wire [9:0] Input_s;
wire [9:0] Output_s;
wire ScanEnable_s;
wire ScanClk_s;
wire ScanDataIn_s;
wire ScanDataOut_s;
TRFSM #(
.InputWidth(10),
.OutputWidth(10),
.StateWidth(5),
.UseResetRow(0),
.NumRows0(5),
.NumRows1(5),
.NumRows2(5),
.NumRows3(5),
.NumRows4(5),
.NumRows5(0),
.NumRows6(0),
.NumRows7(0),
.NumRows8(0),
.NumRows9(0)
) TRFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Input_i(Input_s),
.Output_o(Output_s),
.CfgMode_i(CfgMode_i),
.CfgClk_i(CfgClk_i),
.CfgShift_i(CfgShift_i),
.CfgDataIn_i(CfgDataIn_i),
.CfgDataOut_o(CfgDataOut_o),
.ScanEnable_i(ScanEnable_s),
.ScanClk_i(ScanClk_s),
.ScanDataIn_i(ScanDataIn_s),
.ScanDataOut_o(ScanDataOut_s)
);
assign Input_s = { In9_i, In8_i, In7_i, In6_i, In5_i, In4_i, In3_i, In2_i, In1_i, In0_i };
assign Out0_o = Output_s[0];
assign Out1_o = Output_s[1];
assign Out2_o = Output_s[2];
assign Out3_o = Output_s[3];
assign Out4_o = Output_s[4];
assign Out5_o = Output_s[5];
assign Out6_o = Output_s[6];
assign Out7_o = Output_s[7];
assign Out8_o = Output_s[8];
assign Out9_o = Output_s[9];
assign ScanEnable_s = 1'b0;
assign ScanClk_s = 1'b0;
assign ScanDataIn_s = 1'b0;
endmodule
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// TODO: NMI and IRQ handling is not correct. It should push PC and PSR to
// stack, and follow timing constraint. It must be realized by collaboration
// with the core sequencer.
module MC6502InterruptLogic(
clk,
rst_x,
i_irq_x,
i_nmi_x,
// MemoryController interfaces.
mc2il_data,
mc2il_brk,
il2mc_addr,
il2mc_read,
il2mc_write,
il2mc_data,
// RegisterFile interfaces.
rf2il_s,
rf2il_psr,
rf2il_pc,
il2rf_set_i,
il2rf_set_b,
il2rf_data,
il2rf_set_pcl,
il2rf_set_pch,
il2rf_pushed);
input clk;
input rst_x;
input i_irq_x;
input i_nmi_x;
input [ 7:0] mc2il_data;
input mc2il_brk;
output [15:0] il2mc_addr;
output il2mc_read;
output il2mc_write;
output [ 7:0] il2mc_data;
input [ 7:0] rf2il_s;
input [ 7:0] rf2il_psr;
input [15:0] rf2il_pc;
output il2rf_set_i;
output il2rf_set_b;
output [ 7:0] il2rf_data;
output il2rf_set_pcl;
output il2rf_set_pch;
output il2rf_pushed;
reg [ 1:0] r_res_state;
reg [ 1:0] r_int_state;
reg [ 1:0] r_vector;
wire w_read_pcl;
wire w_read_pch;
localparam VECTOR_NMI = 2'b01;
localparam VECTOR_RES = 2'b10;
localparam VECTOR_IRQ = 2'b11;
localparam VECTOR_BRK = 2'b11;
localparam S_RES_IDLE = 2'b00;
localparam S_RES_LOAD_PCL = 2'b01;
localparam S_RES_LOAD_PCH = 2'b11;
localparam S_INT_IDLE = 2'b00;
localparam S_INT_PUSH_PCL = 2'b01;
localparam S_INT_PUSH_PSR = 2'b10;
assign il2mc_addr = il2mc_write ? { 8'h01, rf2il_s } :
{ 12'hfff, 1'b1, r_vector, w_read_pch };
assign il2mc_read = w_read_pcl | w_read_pch;
assign il2mc_write = mc2il_brk | (r_int_state == S_INT_PUSH_PCL) |
(r_int_state == S_INT_PUSH_PSR);
assign il2mc_data = mc2il_brk ? rf2il_pc[15:8] :
(r_int_state == S_INT_PUSH_PCL) ? rf2il_pc[7:0] :
(r_int_state == S_INT_PUSH_PSR) ? rf2il_psr :
8'hxx;
assign il2rf_set_i = (r_int_state == S_INT_PUSH_PSR) | !i_irq_x | !i_nmi_x;
assign il2rf_set_b = r_int_state == S_INT_PUSH_PSR;
assign il2rf_data = mc2il_data;
assign il2rf_set_pcl = w_read_pcl;
assign il2rf_set_pch = w_read_pch;
assign il2rf_pushed = il2mc_write;
assign w_read_pcl = r_res_state == S_RES_LOAD_PCL;
assign w_read_pch = r_res_state == S_RES_LOAD_PCH;
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_res_state <= S_RES_LOAD_PCL;
r_vector <= VECTOR_RES;
end else begin
case (r_res_state)
S_RES_IDLE: begin
if (!i_irq_x | (r_int_state == S_INT_PUSH_PSR)) begin
r_res_state <= S_RES_LOAD_PCL;
r_vector <= VECTOR_IRQ;
end else if (!i_nmi_x) begin
r_res_state <= S_RES_LOAD_PCL;
r_vector <= VECTOR_NMI;
end
end
S_RES_LOAD_PCL: begin
r_res_state <= S_RES_LOAD_PCH;
end
S_RES_LOAD_PCH: begin
r_res_state <= S_RES_IDLE;
end
endcase // r_res_state
end
end // always @ (posedge clk or negedge rst_x)
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_int_state <= S_INT_IDLE;
end else begin
case (r_int_state)
S_INT_IDLE: begin
if (mc2il_brk) begin
r_int_state <= S_INT_PUSH_PCL;
end
end
S_INT_PUSH_PCL: begin
r_int_state <= S_INT_PUSH_PSR;
end
S_INT_PUSH_PSR: begin
r_int_state <= S_INT_IDLE;
end
endcase // r_int_state
end
end // always @ (posedge clk or negedge rst_x)
endmodule // MC6502InterruptLogic
|
#include <bits/stdc++.h> using namespace std; int main() { string x, y; cin >> x >> y; const auto n = int(x.size()); auto ok = true; for (auto i = 0; i < n; i++) ok &= y[i] <= x[i]; if (ok) cout << y << endl; else cout << -1 << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s; string c; cin >> n >> c; s = n; string r = ; while (n > 0) { if (n % 2 == 0) { string y = ; y += c[s - n]; y += r; r = y; } else { r += c[s - n]; } n--; } cout << r; return 0; }
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module uarttx(
input rst,
input clk,
input tx_start,
input [7 : 0] tx_byte,
output tx, output tx_ready);
localparam STATE_IDLE = 0;
localparam STATE_START_BYTE = 1;
localparam STATE_BYTE_1 = 2;
localparam STATE_BYTE_2 = 3;
localparam STATE_BYTE_3 = 4;
localparam STATE_BYTE_4 = 5;
localparam STATE_BYTE_5 = 6;
localparam STATE_BYTE_6 = 7;
localparam STATE_BYTE_7 = 8;
localparam STATE_BYTE_8 = 9;
localparam STATE_STOP_BYTE1 = 10;
localparam STATE_STOP_BYTE2 = 11;
localparam STATE_FINISH = 12;
localparam STATE_WIDTH = $clog2(STATE_FINISH);
parameter CLK_SPEED = 12000000; //Hz
`ifdef IVERILOG_SIM
parameter BAUD_RATE = CLK_SPEED / 2;
`else
parameter BAUD_RATE = 19200;
`endif
localparam BAUD_COUNT = CLK_SPEED / BAUD_RATE;
localparam BAUD_REG_SIZE = $clog2(BAUD_COUNT);
reg [BAUD_REG_SIZE-1 : 0] baud_counter;
reg [STATE_WIDTH-1 : 0] tx_state;
reg tx_val;
reg [7 : 0] value;
assign tx_ready = (tx_state != STATE_IDLE) || (tx_start) ? 0 : 1;
assign tx = (tx_state == STATE_IDLE) ? 1 : tx_val;
always @(posedge clk) begin
if (rst) begin
tx_state <= 0;
tx_val <= 0;
baud_counter <= 0;
value <= 0;
end else begin
if (baud_counter == BAUD_COUNT) begin
baud_counter <= 0;
end else if (tx_state != STATE_IDLE) begin
baud_counter <= baud_counter + 1;
end
case (tx_state)
STATE_IDLE: begin
if (tx_start) begin
tx_state <= STATE_START_BYTE;
tx_val <= 1;
value <= tx_byte;
end
end
STATE_START_BYTE: begin
if (baud_counter == 0) begin
tx_val <= 0;
tx_state <= STATE_BYTE_1;
end
end
STATE_BYTE_1: begin
if (baud_counter == 0) begin
tx_val <= value[0];
tx_state <= STATE_BYTE_2;
end
end
STATE_BYTE_2: begin
if (baud_counter == 0) begin
tx_val <= value[1];
tx_state <= STATE_BYTE_3;
end
end
STATE_BYTE_3: begin
if (baud_counter == 0) begin
tx_val <= value[2];
tx_state <= STATE_BYTE_4;
end
end
STATE_BYTE_4: begin
if (baud_counter == 0) begin
tx_val <= value[3];
tx_state <= STATE_BYTE_5;
end
end
STATE_BYTE_5: begin
if (baud_counter == 0) begin
tx_val <= value[4];
tx_state <= STATE_BYTE_6;
end
end
STATE_BYTE_6: begin
if (baud_counter == 0) begin
tx_val <= value[5];
tx_state <= STATE_BYTE_7;
end
end
STATE_BYTE_7: begin
if (baud_counter == 0) begin
tx_val <= value[6];
tx_state <= STATE_BYTE_8;
end
end
STATE_BYTE_8: begin
if (baud_counter == 0) begin
tx_val <= value[7];
tx_state <= STATE_STOP_BYTE1;
end
end
STATE_STOP_BYTE1: begin
if (baud_counter == 0) begin
tx_val <= 1;
tx_state <= STATE_STOP_BYTE2;
end
end
STATE_STOP_BYTE2: begin
if (baud_counter == 0) begin
tx_val <= 1;
tx_state <= STATE_FINISH;
end
end
STATE_FINISH : begin
tx_state <= STATE_IDLE;
end
default: begin
tx_state <= STATE_IDLE;
end
endcase
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t_embed1_wrap (/*AUTOARG*/
// Outputs
bit_out, vec_out, wide_out, did_init_out,
// Inputs
clk, bit_in, vec_in, wide_in, is_ref
);
/*AUTOINOUTMODULE("t_embed1_child")*/
// Beginning of automatic in/out/inouts (from specific module)
output bit_out;
output [30:0] vec_out;
output [123:0] wide_out;
output did_init_out;
input clk;
input bit_in;
input [30:0] vec_in;
input [123:0] wide_in;
input is_ref;
// End of automatics
`ifdef verilator
// Import $t_embed_child__initial etc as a DPI function
`endif
//TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this
import "DPI-C" context function void t_embed_child_initial();
import "DPI-C" context function void t_embed_child_final();
import "DPI-C" context function void t_embed_child_eval();
import "DPI-C" context function void t_embed_child_io_eval
(
//TODO we support bit, but not logic
input bit clk,
input bit bit_in,
input bit [30:0] vec_in,
input bit [123:0] wide_in,
input bit is_ref,
output bit bit_out,
output bit [30:0] vec_out,
output bit [123:0] wide_out,
output bit did_init_out);
initial begin
// Load all values
t_embed_child_initial();
end
// Only if system verilog, and if a "final" block in the code
final begin
t_embed_child_final();
end
bit _temp_bit_out;
bit _temp_did_init_out;
bit [30:0] _temp_vec_out;
bit [123:0] _temp_wide_out;
always @* begin
t_embed_child_io_eval(
clk,
bit_in,
vec_in,
wide_in,
is_ref,
_temp_bit_out,
_temp_vec_out,
_temp_wide_out,
_temp_did_init_out
);
// TODO might eliminate these temporaries
bit_out = _temp_bit_out;
did_init_out = _temp_did_init_out;
end
// Send all variables every cycle,
// or have a sensitivity routine for each?
// How to make sure we call eval at end of variable changes?
// #0 (though not verilator compatible!)
// TODO for now, we know what changes when
always @ (posedge clk) begin
vec_out <= _temp_vec_out;
wide_out <= _temp_wide_out;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct point { point() : x(0), y(0){}; point(long long x, long long y) : x(x), y(y){}; long long x; long long y; }; point operator+(point a, point b) { return point(a.x + b.x, a.y + b.y); } point operator-(point a, point b) { return point(a.x - b.x, a.y - b.y); } long long dotProduct(point a, point b) { return a.x * b.x + a.y * b.y; } long long crossProduct(point a, point b) { return a.x * b.y - a.y * b.x; } int f(point a, point b) { if ((double)a.x / a.y > (double)b.x / b.y) return 1; return -1; } int main() { int n; cin >> n; vector<long long> a(n), b(n); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; vector<long long> dp(n); dp[0] = 0; vector<point> hull(n); hull[0] = point(b[0], dp[0]); int k = 1; for (int i = 1; i < n; i++) { int l = 0, r = k; point q(a[i], 1); while (r - l > 2) { int m1 = (r + 2 * l) / 3; int m2 = (2 * r + l) / 3; long long u = dotProduct(q, hull[m1]); long long v = dotProduct(q, hull[m2]); if (u < v) r = m2; else l = m1; } if (l + 1 < r && dotProduct(q, hull[l]) > dotProduct(q, hull[l + 1])) l++; dp[i] = a[i] * hull[l].x + hull[l].y; point p(b[i], dp[i]); while (k > 1 && f(hull[k - 1] - hull[k - 2], p - hull[k - 1]) > 0) k--; hull[k++] = p; } cout << dp[n - 1] << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d, i, j, x, y = 0, w, z = 0, e; cin >> a >> b >> c >> d; if (d % c != 0) { cout << 0; return 0; } w = d / c; if (c == d) { if (c >= a && c <= b) cout << 1; else cout << 0; return 0; } for (i = 1; i <= sqrt(w); i++) { if (w % i == 0) { x = w / i; e = 0; for (j = 2; j <= i; j++) { if (i % j == 0 && x % j == 0) { e = 1; break; } } if (e == 0) { if (i * c >= a && i * c <= b && x * c >= a && x * c <= b) y++; } } } cout << y * 2; return 0; }
|
module audio_player(CLK, PB_PLY, VOL, PB_RST, LEDS, SEGA, SEGD, P,
i2c_rst, i2c_scl, i2c_sda, i2c_vcc, i2c_gnd, i2c_beat,
MemOe, MemWr, FlashRp, FlashCS, RamCS, ADDR,
EppAstb, EppDstb, EppWr, FlashStSts, RamWait, EppWait,
RamAdv, RamClk, RamCre, RamCS, RamLB, RamUB, EppDB, MemDB
);
input CLK; // 100MHz clock input
// I/O
// Switches
input [3:0] VOL; // 4-bit volume
// Push buttons
input PB_RST;
input PB_PLY; // Play command input from push-button
//i2c stuff
input i2c_rst; //i2c reset
inout i2c_scl; //serial clock line
inout i2c_sda; //serial data line
output i2c_vcc; //constant 1
output i2c_gnd; //constant 0
output wire i2c_beat; //beat detection
// 7-Seg Display
output [3:0] SEGA; // Display-select (common anode) output
output [7:0] SEGD; // Display-pattern output
// LEDs
output [7:0] LEDS; // LEDs to display what is being retrieved from memory.
output P; // Square wave output
// Ram Access
inout [15:0] MemDB;
output [23:1] ADDR; // 23-bit address sent to flash memory
input EppAstb;
input EppDstb;
input EppWr;
input FlashStSts;
input RamWait;
output EppWait;
output FlashCS;
output FlashRp;
output MemOe;
output MemWr;
output RamAdv;
output RamClk;
output RamCre;
output RamCS;
output RamLB;
output RamUB;
inout [7:0] EppDB;
wire [1:0] MODE;
wire [3:0] NOTE;
wire [5:0] TONE;
wire [15:0] DATA;
wire DONE;
wire END_SONG;
wire EN;
parameter
NORMAL = 2'b00,
STACCATO = 2'b01,
SLURRED = 2'b10,
BPM_COMM = 2'b11;
reg PLAY;
reg [7:0] DEFAULT_BPM;
reg LATCH_PB_PLY;
// I2C Stuff
wire signed [15:0] accel_z; //Raw data coming out of the i2c bus (not always valid)
reg [15:0] accel_out; //Captured data from accel_z when the valid bit goes high. Should always be valid
wire valid; //After a successful read from the z-register this will be high
//BPM calculation stuff
wire [7:0] BPM; //Current BPM of playback
wire clk_slow; //100kHz clock for BPM calculation and stuff
initial begin
DEFAULT_BPM <= 8'd80;
PLAY <= 0;
LATCH_PB_PLY <= 0;
end
always @(posedge CLK) begin
// Toggle only on rising edge/ falling edge
if (PB_PLY && ~LATCH_PB_PLY)
PLAY <= ~PLAY;
LATCH_PB_PLY <= PB_PLY;
end
//Capture the i2c z-accveleration output when it's valid
always @ (posedge valid) begin
accel_out <= accel_z;
end
// Update BPM with the falling edge of DONE to allow for all the bits to be loaded from RAM
always @ (negedge DONE) begin
if (PLAY && (DATA[15:14] == BPM_COMM))
DEFAULT_BPM <= DATA[7:0];
end
// Grabbing everything out of the DATA register
assign MODE = (DATA[15:14] == BPM_COMM) ? NORMAL : DATA[15:14];
assign NOTE = (DATA[15:14] == BPM_COMM) ? 4'b0 : DATA[3:0];
assign TONE = DATA[13:8];
assign END_SONG = PLAY && (DATA[15:14] == BPM_COMM) && (DATA[7:0] == 0);
// assign LEDS = DATA[15:8]; //High Bytes (BPM Command/ Tone)
//assign LEDS = DATA[7:0]; //Low Bytes (BPM/ Duration)
assign LEDS[7:0] = {4'h0, VOL[3:0]};
// Power for the Gyro
assign i2c_gnd = 0;
assign i2c_vcc = 1;
MPU6050 mpu (
.clk(CLK),
.rst(i2c_rst),
.scl(i2c_scl),
.sda(i2c_sda),
.accel_z(accel_z),
.valid(valid),
.error(error)
);
//double_thermometer LED_display (
// .accel(accel_out),
// .out(LEDS)
// );
beatmaker bm (
.clk(CLK),
.accel(accel_out),
.beat(i2c_beat)
);
clk_divider clkdiv (
.clkin(CLK),
.clkout(clk_slow)
);
bpmcalculator bpmcalc (
.clk(clk_slow),
.beat(i2c_beat),
.default_bpm(DEFAULT_BPM),
.bpm_out(BPM)
);
memory_controller memory_ctrl_blk (.clk(CLK), .EppAstb(EppAstb), .EppDstb(EppDstb), .EppWr(EppWr), .FlashStSts(FlashStSts),
.RamWait(RamWait), .EppWait(EppWait), .FlashCS(FlashCS), .FlashRp(FlashRp), .MemAdr(ADDR), .MemOe(MemOe),
.MemWr(MemWr), .RamAdv(RamAdv), .RamClk(RamClk), .RamCre(RamCre), .RamCS(RamCS), .RamLB(RamLB), .RamUB(RamUB),
.MemDB(MemDB), .EppDB(EppDB), .BTN(DONE & PLAY), .dataOut(DATA), .Reset(PB_RST ));
timing_controller timing_ctrl_blk (CLK, BPM, MODE, NOTE, PLAY, EN, DONE);
display disp_blk (CLK, BPM, PLAY, SEGA, SEGD);
tone tone_blk (CLK, TONE, EN & PLAY ,VOL[3:0], P);
endmodule
|
#include <bits/stdc++.h> char s[300010], p; int main() { int n, m, sum = 0, k, i; scanf( %d%d , &n, &m); scanf( %s , s); for (i = 1; i < n; i++) if (s[i] == . && s[i - 1] == . ) sum++; while (m--) { scanf( %d %c , &k, &p); if (p != . && s[k - 1] == . ) { if (s[k - 2] == . ) sum--; if (s[k] == . ) sum--; } else if (p == . && s[k - 1] != . ) { if (s[k - 2] == . ) sum++; if (s[k] == . ) sum++; } s[k - 1] = p; printf( %d n , sum); } return 0; }
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_babasu_TX_CLK_DIV (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 6: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 6: 0] data_out;
wire [ 6: 0] out_port;
wire [ 6: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {7 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 3;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[6 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, s, i, a[1003], res, x; int main() { cin >> n >> x; for (i = 1; i <= n; i++) { cin >> a[i]; s += a[i]; } if (s <= 0) s *= (-1); res = s / x; if (s % x > 0) res++; cout << res; return 0; }
|
#include <bits/stdc++.h> #pragma GCC target( sse4,avx ) const int p = 1000000007; int mul32(int x, int y) { return int(int64_t(x) * y % p); } int add32(int x, int y) { int res = x + y; if (res >= p) res -= p; return res; } int sub32(int x, int y) { int res = x - y; if (res < 0) res += p; return res; } void run(std::istream &in, std::ostream &out) { int n; in >> n; std::vector<int> xs(n); for (int i = 0; i < n; i++) { in >> xs[i]; } std::sort(xs.begin(), xs.end()); std::vector<int> pow2(n + 1); pow2[0] = 1; for (int i = 1; i <= n; i++) { pow2[i] = (pow2[i - 1] * 2) % p; } int res = 0; for (int i = 0; i < n; i++) { res = add32(res, mul32(xs[i], pow2[i])); res = sub32(res, mul32(xs[i], pow2[n - i - 1])); } out << res << std::endl; } int main() { std::cin.sync_with_stdio(false); std::cin.tie(nullptr); run(std::cin, std::cout); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_2_V
`define SKY130_FD_SC_MS__A2BB2O_2_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_2_V
|
module test();
wire [1:0] n0 = 2'bzx;
wire [1:0] n1 = 2'b0x;
wire [1:0] n2 = 2'b1x;
wire [1:0] n3 = 2'bxx;
wire [1:0] n4 = 2'bxx;
wand [1:0] n5 = 2'bxx;
wor [1:0] n6 = 2'bxx;
assign n4 = 2'b0x;
assign n4 = 2'b0x;
assign n4 = 2'b1x;
assign n4 = 2'b1x;
assign n4 = 2'b1x;
assign n5 = 2'b0x;
assign n5 = 2'b0x;
assign n5 = 2'b0x;
assign n5 = 2'b1x;
assign n5 = 2'b1x;
assign n6 = 2'b0x;
assign n6 = 2'b1x;
assign n6 = 2'b1x;
assign n6 = 2'bxx;
assign n6 = 2'bxx;
reg [15:0] multi;
reg [15:0] forced;
reg [15:0] countD;
reg [15:0] count0;
reg [15:0] count1;
reg [15:0] countX;
reg failed = 0;
task check_results;
input integer expected_multi;
input integer expected_forced;
input integer expected_countD;
input integer expected_count0;
input integer expected_count1;
input integer expected_countX;
begin
$write("multi = %0d ", multi);
if (multi !== expected_multi) failed = 1;
if (expected_forced != -1) begin
$write("forced = %0d ", forced);
if (forced !== expected_forced) failed = 1;
end
if (expected_countD != -1) begin
$write("countD = %0d ", countD);
if (countD !== expected_countD) failed = 1;
end
if (expected_count0 != -1) begin
$write("count0 = %0d ", count0);
if (count0 !== expected_count0) failed = 1;
end
if (expected_count1 != -1) begin
$write("count1 = %0d ", count1);
if (count1 !== expected_count1) failed = 1;
end
if (expected_countX != -1) begin
$write("countX = %0d ", countX);
if (countX !== expected_countX) failed = 1;
end
$write("\n");
end
endtask
initial begin
#0; // wait for initial values to propagate
// test undriven net
multi = $countdrivers(n0[1]);
check_results(0, -1, -1, -1, -1, -1);
multi = $countdrivers(n0[1], forced);
check_results(0, 0, -1, -1, -1, -1);
multi = $countdrivers(n0[1], forced, countD);
check_results(0, 0, 0, -1, -1, -1);
multi = $countdrivers(n0[1], forced, countD, count0);
check_results(0, 0, 0, 0, -1, -1);
multi = $countdrivers(n0[1], forced, countD, count0, count1);
check_results(0, 0, 0, 0, 0, -1);
multi = $countdrivers(n0[1], forced, countD, count0, count1, countX);
check_results(0, 0, 0, 0, 0, 0);
force n0 = 2'bxx;
multi = $countdrivers(n0[1], forced, countD, count0, count1, countX);
check_results(0, 1, 0, 0, 0, 0);
// test net driven to 0
multi = $countdrivers(n1[1]);
check_results(0, -1, -1, -1, -1, -1);
multi = $countdrivers(n1[1], forced);
check_results(0, 0, -1, -1, -1, -1);
multi = $countdrivers(n1[1], forced, countD);
check_results(0, 0, 1, -1, -1, -1);
multi = $countdrivers(n1[1], forced, countD, count0);
check_results(0, 0, 1, 1, -1, -1);
multi = $countdrivers(n1[1], forced, countD, count0, count1);
check_results(0, 0, 1, 1, 0, -1);
multi = $countdrivers(n1[1], forced, countD, count0, count1, countX);
check_results(0, 0, 1, 1, 0, 0);
force n1 = 2'bxx;
multi = $countdrivers(n1[1], forced, countD, count0, count1, countX);
check_results(0, 1, 1, 1, 0, 0);
// test net driven to 1
multi = $countdrivers(n2[1]);
check_results(0, -1, -1, -1, -1, -1);
multi = $countdrivers(n2[1], forced);
check_results(0, 0, -1, -1, -1, -1);
multi = $countdrivers(n2[1], forced, countD);
check_results(0, 0, 1, -1, -1, -1);
multi = $countdrivers(n2[1], forced, countD, count0);
check_results(0, 0, 1, 0, -1, -1);
multi = $countdrivers(n2[1], forced, countD, count0, count1);
check_results(0, 0, 1, 0, 1, -1);
multi = $countdrivers(n2[1], forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 1, 0);
force n2 = 2'bxx;
multi = $countdrivers(n2[1], forced, countD, count0, count1, countX);
check_results(0, 1, 1, 0, 1, 0);
// test net driven to X
multi = $countdrivers(n3[1]);
check_results(0, -1, -1, -1, -1, -1);
multi = $countdrivers(n3[1], forced);
check_results(0, 0, -1, -1, -1, -1);
multi = $countdrivers(n3[1], forced, countD);
check_results(0, 0, 1, -1, -1, -1);
multi = $countdrivers(n3[1], forced, countD, count0);
check_results(0, 0, 1, 0, -1, -1);
multi = $countdrivers(n3[1], forced, countD, count0, count1);
check_results(0, 0, 1, 0, 0, -1);
multi = $countdrivers(n3[1], forced, countD, count0, count1, countX);
check_results(0, 0, 1, 0, 0, 1);
force n3 = 2'bxx;
multi = $countdrivers(n3[1], forced, countD, count0, count1, countX);
check_results(0, 1, 1, 0, 0, 1);
// test multi-driven net
multi = $countdrivers(n4[1]);
check_results(1, -1, -1, -1, -1, -1);
multi = $countdrivers(n4[1], forced);
check_results(1, 0, -1, -1, -1, -1);
multi = $countdrivers(n4[1], forced, countD);
check_results(1, 0, 6, -1, -1, -1);
multi = $countdrivers(n4[1], forced, countD, count0);
check_results(1, 0, 6, 2, -1, -1);
multi = $countdrivers(n4[1], forced, countD, count0, count1);
check_results(1, 0, 6, 2, 3, -1);
multi = $countdrivers(n4[1], forced, countD, count0, count1, countX);
check_results(1, 0, 6, 2, 3, 1);
force n4 = 2'bxx;
multi = $countdrivers(n4[1], forced, countD, count0, count1, countX);
check_results(1, 1, 6, 2, 3, 1);
// test wire and
multi = $countdrivers(n5[1]);
check_results(1, -1, -1, -1, -1, -1);
multi = $countdrivers(n5[1], forced);
check_results(1, 0, -1, -1, -1, -1);
multi = $countdrivers(n5[1], forced, countD);
check_results(1, 0, 6, -1, -1, -1);
multi = $countdrivers(n5[1], forced, countD, count0);
check_results(1, 0, 6, 3, -1, -1);
multi = $countdrivers(n5[1], forced, countD, count0, count1);
check_results(1, 0, 6, 3, 2, -1);
multi = $countdrivers(n5[1], forced, countD, count0, count1, countX);
check_results(1, 0, 6, 3, 2, 1);
force n5 = 2'bxx;
multi = $countdrivers(n5[1], forced, countD, count0, count1, countX);
check_results(1, 1, 6, 3, 2, 1);
// test wire or
multi = $countdrivers(n6[1]);
check_results(1, -1, -1, -1, -1, -1);
multi = $countdrivers(n6[1], forced);
check_results(1, 0, -1, -1, -1, -1);
multi = $countdrivers(n6[1], forced, countD);
check_results(1, 0, 6, -1, -1, -1);
multi = $countdrivers(n6[1], forced, countD, count0);
check_results(1, 0, 6, 1, -1, -1);
multi = $countdrivers(n6[1], forced, countD, count0, count1);
check_results(1, 0, 6, 1, 2, -1);
multi = $countdrivers(n6[1], forced, countD, count0, count1, countX);
check_results(1, 0, 6, 1, 2, 3);
force n6 = 2'bxx;
multi = $countdrivers(n6[1], forced, countD, count0, count1, countX);
check_results(1, 1, 6, 1, 2, 3);
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_2_V
`define SKY130_FD_SC_MS__BUF_2_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__buf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_2_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module SDPRAM_16A9024X32B4512 (
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [15 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [12 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [31 : 0] doutb;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("SDPRAM_16A9024X32B4512.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_WIDTH_A(16),
.C_READ_WIDTH_A(16),
.C_WRITE_DEPTH_A(9024),
.C_READ_DEPTH_A(9024),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_B(32),
.C_READ_WIDTH_B(32),
.C_WRITE_DEPTH_B(4512),
.C_READ_DEPTH_B(4512),
.C_ADDRB_WIDTH(13),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(1),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("4"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 8.9942449999999994 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(enb),
.regceb(1'D0),
.web(1'B0),
.addrb(addrb),
.dinb(32'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(16'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
module EmitOneCH
(
input Transmit_CLK, //100M
input RX_Gate, //Transmit Enable
input [7:0] EmitDelay, //7th bit for Transmit Enable, 6:0 for Delay
input [5:0] Emit_Width, //Emit pulse width
output reg TXP,
output reg TXN
);
reg [6:0] Emit_Counter;
reg [6:0] Delay_Counter;
always @(posedge Transmit_CLK or negedge RX_Gate)
begin
if(~RX_Gate)
begin
Emit_Counter <= 7'd0;
Delay_Counter <= 8'd0;
TXP <= 1'b1;
TXN <= 1'b1;
end
else
begin
if(Delay_Counter < EmitDelay[6:0] ) begin
Delay_Counter <= Delay_Counter + 1'b1;
TXP <= 1'b1;
TXN <= 1'b1;
end
else begin
if(~EmitDelay[7]) begin //enble Emit
if(Emit_Counter <Emit_Width)begin // Positive Pulse
TXP <= 1'b1;
TXN <= 1'b0;
Emit_Counter <= Emit_Counter + 1'b1;
end
else if(Emit_Counter <{Emit_Width,1'b0})begin // Negetive Pulse
TXP <= 1'b0;
TXN <= 1'b1;
Emit_Counter <= Emit_Counter + 1'b1;
end
/*
else if(Emit_Counter <({Emit_Width,1'b0}+Emit_Width))begin // Positive Pulse
TXP <= 1'b1;
TXN <= 1'b0;
Emit_Counter <= Emit_Counter + 1'b1;
end
else if(Emit_Counter <{Emit_Width,2'b0})begin // Negetive Pulse
TXP <= 1'b0;
TXN <= 1'b1;
Emit_Counter <= Emit_Counter + 1'b1;
end
*/
else if(Emit_Counter <({Emit_Width,2'b0}+Emit_Width))begin //Return to Zero (RTZ)
TXP <= 1'b0;
TXN <= 1'b0;
Emit_Counter <= Emit_Counter + 1'b1;
end
else begin
TXP <= 1'b1;
TXN <= 1'b1;
end
end
else begin //disable Emit
TXP <= 1'b1;
TXN <= 1'b1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n; cin >> n; for (long long i = 1; i <= n; i++) { cout << 1 << ; } cout << endl; } }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module i2c #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 1
)(
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire I2C_CLK,
inout wire I2C_SDA,
inout wire I2C_SCL
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
i2c_core
#(
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_BYTES)
)
i_i2c_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.I2C_CLK(I2C_CLK),
.I2C_SDA(I2C_SDA),
.I2C_SCL(I2C_SCL)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int X, Y; int n; int cnt; bool used[1000][1000]; bool edge[1000][1000][4]; const int DX[] = {1, 0, -1, 0}, DY[] = {0, 1, 0, -1}; vector<int> ans; void dfs(int x, int y) { if (x < 0 || x >= X || y < 0 || y >= Y || used[x][y]) return; used[x][y] = true; cnt++; for (int i = 0; i < 4; i++) { if (!edge[x][y][i]) { dfs(x + DX[i], y + DY[i]); } } } int main() { scanf( %d%d%d , &X, &Y, &n); for (int i = 1; i <= n; i++) { int x1, y1, x2, y2; scanf( %d%d%d%d , &x1, &y1, &x2, &y2); if (x1 == x2) { for (int j = y1; j < y2; j++) { edge[x1 - 1][j][0] = true; edge[x1][j][2] = true; } } else if (y1 == y2) { for (int j = x1; j < x2; j++) { edge[j][y1 - 1][1] = true; edge[j][y1][3] = true; } } } for (int i = 0; i < X; i++) for (int j = 0; j < Y; j++) if (!used[i][j]) { cnt = 0; dfs(i, j); ans.push_back(cnt); } sort(ans.begin(), ans.end()); for (int i = 0; i < ans.size(); i++) printf( %d , ans[i]); puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int A[maxn], MAX = 0; int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> A[i]; sort(A, A + n); int ans = 0; for (int i = 0; i < n; i++) if (ans * A[i] + ans <= i) ans++; cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool flag = 0; void sss(int &n, int &k) { if (flag == 0) n = n + k; else if (flag == 1) n = n - k; } void print(int &now, int k) { k += 48; if (k > now) { while (k != now) { printf( + ); now++; } } else if (k < now) { while (k != now) { printf( - ); now--; } } printf( . ); } int main() { int i, k = 0, n = 0; char c; while ((c = getchar()) != EOF) { if (c >= 0 && c <= 9 ) n = n * 10 + c - 0 ; else if (c == + ) { sss(k, n); n = 0; flag = 0; } else if (c == - ) { sss(k, n); n = 0; flag = 1; } } sss(k, n); n = 0; int p = k, j; while (p) { p /= 10; n++; } if (k == 0) n = 1; int now = 0; for (i = n; i >= 1; i--) { p = k; for (j = 1; j <= i - 1; j++) p /= 10; p %= 10; print(now, p); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long i, j, t, a, b, m, n, c, d, y, x, k, s; t = 1; while (t--) { string s1, s2; cin >> s1 >> s2; if (s1 == s2) cout << s1; else cout << 1; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBN_BLACKBOX_V
`define SKY130_FD_SC_HS__SDFBBN_BLACKBOX_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBN_BLACKBOX_V
|
/*
** -----------------------------------------------------------------------------**
** extjtag.v
**
** GPIO control
**
** Copyright (C) 2007 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
/*
Control programming of external FPGA on the sensor/sensor multiplexor board
Mulptiplex status signals into a single line
bits:
31:20 - not used
19:16 - 0xb..0xf - no changes
- 0xa - select xfpgadone
- 0x9 - select xfpgatdo
- 0x8 - select senspgmin (default)
- 0x0..0x7 - no changes
15:10 - not used
9: 8 - 3 - set xpgmen,
- 2 - reset xpgmen,
- 0, 1 - no changes to xpgmen
7: 6 - 3 - set xfpgaprog,
- 2 - reset xfpgaprog,
- 0, 1 - no changes to xfpgaprog
5: 4 - 3 - set xfpgatck,
- 2 - reset xfpgatck,
- 0, 1 - no changes to xfpgatck
3: 2 - 3 - set xfpgatms,
- 2 - reset xfpgatms,
- 0, 1 - no changes to xfpgatms
1: 0 - 3 - set xfpgatdi,
- 2 - reset xfpgatdi,
- 0, 1 - no changes to xfpgatdi
*/
module extjtag (sclk, // @negedge
pre_wen, // 1 cycle ahead of write data
di, // [31:0] data in (only some bits are used)
xpgmen, // enable programming mode for an external FPGA
xfpgaprog, // PROG_B to be sent to an external FPGA
xfpgatck, // TCK to be sent to an external FPGA
xfpgatms, // TMS to be sent to an external FPGA
xfpgatdi, // TDI to be sent to an external FPGA
senspgmin, // state of the SENSPGM I/O pin (read)
xfpgadone, // state of the MRST pin ("DONE" pin on an external FPGA)
xfpgatdo, // TDO read from an external FPGA
state); // multiplexed state (one of 3 inputs)
input sclk;
input pre_wen;
input [31:0] di;
output xpgmen; // enable programming mode for an external FPGA
output xfpgaprog; // PROG_B to be sent to an external FPGA
output xfpgatck; // TCK to be sent to an external FPGA
output xfpgatms; // TMS to be sent to an external FPGA
output xfpgatdi;
input senspgmin;
input xfpgadone;
input xfpgatdo; // TDO read from an external FPGA
output state;
// reg wen;
wire wen= pre_wen;
wire [1:0] mux; // select source for state, initilaized to
wire xpgmen;
wire xfpgaprog;
wire xfpgatck;
wire xfpgatms;
wire xfpgatdi;
wire state=mux[1]?(mux[0]?1'b0:xfpgadone):(mux[0]?xfpgatdo:senspgmin);
/*
always @ (negedge sclk) begin
wen <= pre_wen;
end
*/
FDE_1 i_mux_0 (.C(sclk), .CE(wen & di[19]), .D(di[16]), .Q(mux[0]));
FDE_1 i_mux_1 (.C(sclk), .CE(wen & di[19]), .D(di[17]), .Q(mux[1]));
FDE_1 i_xpgmen (.C(sclk), .CE(wen & di[9]), .D(di[8]), .Q(xpgmen));
FDE_1 i_xfpgaprog (.C(sclk), .CE(wen & di[7]), .D(di[6]), .Q(xfpgaprog));
FDE_1 i_xfpgatck (.C(sclk), .CE(wen & di[5]), .D(di[4]), .Q(xfpgatck));
FDE_1 i_xfpgatms (.C(sclk), .CE(wen & di[3]), .D(di[2]), .Q(xfpgatms));
FDE_1 i_xfpgatdi (.C(sclk), .CE(wen & di[1]), .D(di[0]), .Q(xfpgatdi));
endmodule
|
#include <bits/stdc++.h> int main() { char a[110], b[110]; scanf( %s , a); getchar(); scanf( %s , b); int len = strlen(a); for (int i = 0; i < len; i++) { if (a[i] < b[i]) { printf( -1 ); return 0; } } for (int i = 0; i < len; i++) { if (a[i] == b[i]) printf( z ); else printf( %c , b[i]); } return 0; }
|
module Sec5_SM(
input DigitalLDir,
input DigitalRDir,
input clk_i,
input reset_n,
output reg [3:0] outputs
// output reg Len,
// output reg Ldir,
// output reg Ren,
// output reg Rdir
);
reg [2:0] state;
reg [2:0] state_next;
parameter S0 = 3'b000; //Moving forward
parameter S1 = 3'b001; //Moving backward (right bumper)
parameter S2 = 3'b010; //Moving backward (right bumper)
parameter S3 = 3'b011; //Spinning left (right bumper)
parameter S4 = 3'b100; //Moving backward (left bumper)
parameter S5 = 3'b101; //Moving backward (left bumper)
parameter S6 = 3'b110; //Spinning right (left bumper)
//Async reset
always @ (posedge clk_i, negedge reset_n)
begin
if(!reset_n)
state <= S0;
else
state <= state_next;
end
//Next state logic
always @ (*)
begin
case(state)
S0:
begin
if( !DigitalLDir ) state_next <= S4;
else if( !DigitalRDir ) state_next <= S1;
else state_next <= S0;
end
S1: state_next = S2;
S2: state_next = S3;
S3: state_next = S0;
S4: state_next = S5;
S5: state_next = S6;
S6: state_next = S0;
default: state_next = S0;
endcase
end
//Output status logic
always @ (*)
begin
case (state)
S0:
begin
outputs = 4'b0101;
// Len <= 0; Ldir <= 1; Ren <= 0; Rdir <= 1;
end
S1:
begin
outputs = 4'b0000;
// Len <= 0; Ldir <= 0; Ren <= 0; Rdir <= 0;
end
S2:
begin
outputs = 4'b0000;
// Len <= 0; Ldir <= 1; Ren <= 0; Rdir <= 0;
end
S3:
begin
outputs = 4'b0100;
// Len <= 0; Ldir <= 1; Ren <= 0; Rdir <= 0;
end
S4:
begin
outputs = 4'b0000;
// Len <= 0; Ldir <= 0; Ren <= 0; Rdir <= 0;
end
S5:
begin
outputs = 4'b0000;
// Len <= 0; Ldir <= 0; Ren <= 0; Rdir <= 1;
end
S6:
begin
outputs = 4'b0001;
// Len <= 0; Ldir <= 0; Ren <= 0; Rdir <= 1;
end
default:
begin
outputs = 4'b0101;
end
endcase
end
endmodule
/*
module mux2(
input d0,
input d1,
input s,
output y);
assign y = (s) ? d1 : d0;
endmodule
module inv (input A,
output Z);
assign Z = ~A;
endmodule
*/
|
/**
* bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma.v
*
*/
`include "bsg_defines.v"
module bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter data_width_in_bytes_lp=(width_p>>3)
, parameter write_mask_width_lp=data_width_in_bytes_lp
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_in_bytes_lp)
, parameter init_mem_p=0
)
(
input clk_i
, input reset_i
// ctrl interface
, input v_i
, input w_i
, input [addr_width_lp-1:0] addr_i
, input [width_p-1:0] data_i
, input [write_mask_width_lp-1:0] w_mask_i
// read channel
, output logic [width_p-1:0] data_o
);
bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma
#(.width_p(width_p)
,.els_p(els_p)
,.id_p(id_p)
,.init_mem_p(init_mem_p))
mem
(.clk_i(clk_i)
,.reset_i(reset_i)
,.r_v_i(v_i & ~w_i)
,.r_addr_i(addr_i)
,.w_v_i(v_i & w_i)
,.w_addr_i(addr_i)
,.w_data_i(data_i)
,.w_mask_i(w_mask_i)
,.data_o(data_o));
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma)
|
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