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// Part of NeoGS project
//
// Z80 clock switch and nothing more. config_n=coldres_n.
//
// (c) 2008-2010 NedoPC
module GS_cpld(
output wire config_n, // ACEX1K config pins
input wire status_n, //
input wire conf_done, //
output wire cs, //
input wire init_done, //
input wire clk24in, // 24mhz in
input wire clk20in, // 20mhz in
input wire clksel0, // clock select 0 (1=divide by 2, 0=no divide)
input wire clksel1, // clock select 1 (1=clk20in, 0=clk24in)
output wire clkout, // clock out
input wire clkin, // input of clkout signal, buffered, same as for Z80
input wire coldres_n, // resets
output wire warmres_n,
input wire iorq_n, // Z80 control signals
input wire mreq_n,
input wire rd_n,
input wire wr_n,
inout wire [ 7:0] d, // Z80 data bus
input wire a6, // some Z80 addresses
input wire a7,
input wire a10,
input wire a11,
input wire a12,
input wire a13,
input wire a14,
input wire a15,
output wire mema14,
output wire mema15,
output wire mema19,
inout wire romcs_n,
inout wire memoe_n,
inout wire memwe_n,
input wire in_ramcs0_n,
input wire in_ramcs1_n,
input wire in_ramcs2_n,
input wire in_ramcs3_n,
output wire out_ramcs0_n,
output wire out_ramcs1_n,
output wire ra6, // some buffered memory addresses
output wire ra7,
output wire ra10,
output wire ra11,
output wire ra12,
output wire ra13,
inout wire [ 7:0] rd // memory data bus
);
// clock selector
clocker clk( .clk1(clk24in),
.clk2(clk20in),
.clksel(clksel1),
.divsel(clksel0),
.clkout(clkout)
);
// memory control pins when running without configured FPGA
assign mema14 = 1'bZ;
assign mema15 = 1'bZ;
assign mema19 = 1'bZ;
assign romcs_n = 1'bZ;
assign memoe_n = 1'bZ;
assign memwe_n = 1'bZ;
assign cs = 1'b0;
assign out_ramcs0_n = 1'b1;
assign out_ramcs1_n = 1'b1;
assign rd = 8'bZZZZ_ZZZZ;
assign warmres_n = 1'bZ;
assign d = 8'bZZZZ_ZZZZ;
assign {ra6,ra7,ra10,ra11,ra12,ra13} = 6'd0;
// reset FPGA at cold reset
assign config_n = coldres_n;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, val[200100], m; set<pair<int, int> > s[200100]; struct opt { int tp, x, y; } q[200100]; inline void read(int &x) { x = 0; register char c = getchar(); while (c > 9 || c < 0 ) c = getchar(); while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); } inline void print(int x) { if (x <= 9) putchar( 0 + x); else print(x / 10), putchar( 0 + x % 10); } void ins(int x, pair<int, int> k) { while (x) s[x].insert(k), x -= x & -x; } void del(int x, pair<int, int> k) { while (x) s[x].erase(k), x -= x & -x; } pair<int, int> ask(int x, pair<int, int> k) { pair<int, int> res = make_pair(0x3f3f3f3f, 0x3f3f3f3f); while (x <= m) res = min(res, *s[x].lower_bound(k)), x += x & -x; return res; } int main() { read(n); for (register int i = 1; i <= n; i++) { char str[10]; scanf( %s , str), read(q[i].x), read(q[i].y); if (str[0] == a ) q[i].tp = 1; if (str[0] == r ) q[i].tp = 2; if (str[0] == f ) q[i].tp = 3, q[i].x++, q[i].y++; val[++m] = q[i].y; } sort(val + 1, val + m + 1), m = unique(val + 1, val + m + 1) - val + 1; for (int i = 1; i <= m; i++) s[i].insert(make_pair(0x3f3f3f3f, 0x3f3f3f3f)); for (register int i = 1; i <= n; i++) { if (q[i].tp == 1) ins(lower_bound(val + 1, val + m, q[i].y) - val, make_pair(q[i].x, q[i].y)); if (q[i].tp == 2) del(lower_bound(val + 1, val + m, q[i].y) - val, make_pair(q[i].x, q[i].y)); if (q[i].tp == 3) { register pair<int, int> tmp = ask(lower_bound(val + 1, val + m, q[i].y) - val, make_pair(q[i].x, q[i].y)); if (tmp == make_pair(0x3f3f3f3f, 0x3f3f3f3f)) putchar( - ), putchar( 1 ), putchar( n ); else print(tmp.first), putchar( ), print(tmp.second), putchar( n ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; char s[2000011]; int h1[2000011], h2[2000011], p1[2000011], p2[2000011], mod1 = 998244353, mod2 = 1000000007; int geth1(int L, int R) { return (h1[R] - h1[L - 1] * 1ll * p1[R - L + 1] % mod1 + mod1) % mod1; } int geth2(int L, int R) { return (h2[R] - h2[L - 1] * 1ll * p2[R - L + 1] % mod2 + mod2) % mod2; } int ans[2000011]; int main() { scanf( %d%s , &n, s + 1); h1[0] = h2[0] = 0; for (int i = 1; i <= n; i++) h1[i] = (h1[i - 1] * 27ll + s[i] - a + 1) % mod1, h2[i] = (h2[i - 1] * 27ll + s[i] - a + 1) % mod2; p1[0] = p2[0] = 1; for (int i = 1; i <= n; i++) p1[i] = p1[i - 1] * 27ll % mod1, p2[i] = p2[i - 1] * 27ll % mod2; for (int i = 0; i <= (n + 1) >> 1; i++) ans[i] = -1; for (int i = 1; i <= n >> 1; i++) { int L = 0, R = i, p = n - i + 1; while (L < R) { int mid = (L + R + 1) >> 1, a = i - mid + 1, b = i + mid - 1, c = p - mid + 1, d = p + mid - 1; if (geth1(a, b) == geth1(c, d) && geth2(a, b) == geth2(c, d)) L = mid; else R = mid - 1; } ans[i - L + 1] = max(ans[i - L + 1], 2 * L - 1); } for (int i = 1; i <= (n + 1) >> 1; i++) { ans[i] = max(ans[i], ans[i - 1] - 2); printf( %d , ans[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int X = 1e5 + 9; const long long inf = (1ll << 60); int n, sum, a[109], b[109], c[109]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; b[a[i]]++; } for (int i = 0; i < n; i++) { cin >> a[i]; c[a[i]]++; } for (int i = 1; i <= 5; i++) { if ((b[i] + c[i]) % 2 == 1) { puts( -1 ); return 0; } } for (int i = 1; i <= 5; i++) { sum += (abs(c[i] - b[i]) / 2); } cout << sum / 2 << endl; }
|
#include <bits/stdc++.h> using namespace std; vector<int> arr; int n, k; long long sum[5500]; double mx = -1e9; int main() { cin >> n >> k; for (int x, i = 1; i <= n; i++) { cin >> x; arr.push_back(x); sum[i] = sum[i - 1] + x; } for (int i = 1; i <= n; i++) { for (int j = i + k - 1; j <= n; j++) { mx = max(mx, (sum[j] - sum[i - 1]) / (double(j - i + 1))); } } printf( %0.15lf , mx); }
|
module vexriscv_wrapper (
input clk,
output rst_out,
// PORTA
inout[7:0] porta,
// PORTB
inout[7:0] portb,
// SDCARD
input sdcard_sck,
input sdcard_mosi,
output sdcard_miso,
// UART related
input rxd,
output reg txd,
// EXTRAM i/f
output wire[15:0] extram_a,
input wire[31:0] extram_d_in,
output wire[31:0] extram_d_out,
output wire extram_cs,
output wire extram_oe,
output wire[3:0] extram_wstrb,
// IRQ
input wire ext_irq3
);
parameter CLK_FREQUENCY = 50000000;
parameter AVR109_BAUD_RATE = 19200;
parameter mem_init = "";
parameter mem_size = 1;
// -------------------------------
// Reset generator
wire nrst;
assign rst_out = ~nrst;
rst_gen rst_gen_inst(.clk(clk), .nrst(nrst));
// -------------------------------
// AVR109
wire prog_mode;
wire intercept_mode;
wire [15:0] prog_addr;
wire [15:0] prog_data;
wire prog_low;
wire prog_high;
wire txd_core;
wire txd_avr109;
avr109 #(.CLK_FREQUENCY(CLK_FREQUENCY), .BAUD_RATE(AVR109_BAUD_RATE))
avr109_inst(.rst(~nrst), .clk(clk),
.rxd(rxd), .txd(txd_avr109), .intercept_mode(intercept_mode),
.prog_mode(prog_mode), .prog_addr(prog_addr),
.prog_data(prog_data),
.prog_data_in(prog_addr[0]? ram_read[31:16] : ram_read[15:0]),
.prog_low(prog_low), .prog_high(prog_high));
always @(posedge clk)
txd <= (nrst ? (intercept_mode ? txd_avr109 : txd_core ) : 1'b1);
// -------------------------------
// VexRiscv Core
wire iBus_cmd_valid;
wire iBus_cmd_ready;
wire [31:0] iBus_cmd_payload_pc;
wire iBus_rsp_valid;
wire iBus_rsp_payload_error;
wire [31:0] iBus_rsp_payload_inst;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [1:0] dBus_cmd_payload_size;
wire dBus_rsp_ready;
wire dBus_rsp_error;
wire [31:0] dBus_rsp_data;
VexRiscv cpu(.iBus_cmd_valid(iBus_cmd_valid),
.iBus_cmd_ready(iBus_cmd_ready),
.iBus_cmd_payload_pc(iBus_cmd_payload_pc),
.iBus_rsp_valid(iBus_rsp_valid),
.iBus_rsp_payload_error(iBus_rsp_payload_error),
.iBus_rsp_payload_inst(iBus_rsp_payload_inst),
.timerInterrupt(timer0_comp_irq),
.externalInterrupt(ext_irq3),
.softwareInterrupt(1'b0),
.dBus_cmd_valid(dBus_cmd_valid),
.dBus_cmd_ready(dBus_cmd_ready),
.dBus_cmd_payload_wr(dBus_cmd_payload_wr),
.dBus_cmd_payload_address(dBus_cmd_payload_address),
.dBus_cmd_payload_data(dBus_cmd_payload_data),
.dBus_cmd_payload_size(dBus_cmd_payload_size),
.dBus_rsp_ready(dBus_rsp_ready),
.dBus_rsp_error(dBus_rsp_error),
.dBus_rsp_data(dBus_rsp_data),
.clk(clk), .reset(rst_out | prog_mode));
// -------------------------------
// Memory/IO Interface
reg [31:0] ram[0:(mem_size*256)-1];
reg [31:0] ram_read;
wire dbus_ram_access;
// assign dbus_ram_access = dBus_cmd_payload_address < mem_size * 1024;
assign dbus_ram_access = dBus_cmd_payload_address[31] == 1'b0;
generate
if (mem_init == "") begin : no_initdata
;
end else begin : yes_initdata
initial $readmemh(mem_init, ram);
end
endgenerate
always @(posedge clk)
if (prog_mode) begin
ram_read <= ram[prog_addr >> 1];
end else if (!rst_out) begin
if (dBus_cmd_valid && !dBus_cmd_payload_wr && dbus_ram_access)
ram_read <= ram[dBus_cmd_payload_address[15:2]];
else if (ibus_stalled)
ram_read <= ram[ibus_stall_pc];
else if (iBus_cmd_valid)
ram_read <= ram[iBus_cmd_payload_pc[15:2]];
end
/* iBus */
reg ibus_valid;
reg ibus_ready;
reg ibus_stalled;
reg [15:2] ibus_stall_pc;
assign iBus_cmd_ready = ibus_ready;
assign iBus_rsp_valid = ibus_valid;
assign iBus_rsp_payload_error = 1'b0;
assign iBus_rsp_payload_inst = ram_read;
always @(posedge clk)
if (prog_mode || rst_out) begin
ibus_valid <= 1'b0;
ibus_ready <= 1'b0;
ibus_stalled <= 1'b0;
end else if (dBus_cmd_valid && !dBus_cmd_payload_wr && dbus_ram_access) begin
if (iBus_cmd_valid && ibus_ready) begin
// Stall until dBus read complete
ibus_valid <= 1'b0;
ibus_ready <= 1'b0;
ibus_stalled <= 1'b1;
ibus_stall_pc <= iBus_cmd_payload_pc[15:2];
end
end else if (ibus_stalled) begin
// Clear stall
ibus_valid <= 1'b1;
ibus_ready <= 1'b1;
ibus_stalled <= 1'b0;
end else if(iBus_cmd_valid && ibus_ready) begin
// Can read without stall
ibus_valid <= 1'b1;
ibus_ready <= 1'b1;
end else begin
ibus_valid <= 1'b0;
ibus_ready <= 1'b1;
end
/* dBus */
reg dbus_ready;
reg [31:0] reg_read;
reg dbus_regspace;
wire dbus_reg_access;
wire valid_internal_reg, valid_external_reg;
wire [3:0] write_mask;
assign dbus_reg_access = !dbus_ram_access;
assign write_mask = (dBus_cmd_payload_size == 2'b00 ?
4'b0001 << dBus_cmd_payload_address[1:0] :
(dBus_cmd_payload_size == 2'b01 ?
(dBus_cmd_payload_address[1]? 4'b1100 : 4'b0011) :
4'b1111));
assign valid_internal_reg = &dBus_cmd_payload_address[31:8];
assign valid_external_reg = &dBus_cmd_payload_address[31:17] &&
dBus_cmd_payload_address[16:13] == 4'b0111;
assign dBus_cmd_ready = 1'b1;
assign dBus_rsp_ready = dbus_ready;
assign dBus_rsp_error = 1'b0;
assign dBus_rsp_data = (dbus_regspace? reg_read : ram_read);
assign extram_a = dBus_cmd_payload_address[15:0];
assign extram_d_out = dBus_cmd_payload_data;
assign extram_cs = dbus_reg_access && valid_external_reg;
assign extram_oe = dBus_cmd_valid && !dBus_cmd_payload_wr;
assign extram_wstrb = (dBus_cmd_valid && dBus_cmd_payload_wr? write_mask : 4'b0000);
always @(posedge clk) begin
if (prog_mode) begin
dbus_ready <= 1'b0;
if (prog_high) begin
if (prog_addr[0])
ram[prog_addr >> 1][31:24] <= prog_data;
else
ram[prog_addr >> 1][15:8] <= prog_data;
end else if (prog_low) begin
if (prog_addr[0])
ram[prog_addr >> 1][23:16] <= prog_data;
else
ram[prog_addr >> 1][7:0] <= prog_data;
end
end else if (rst_out || !dBus_cmd_valid)
dbus_ready <= 1'b0;
else begin
dbus_ready <= 1'b1;
if (dbus_ram_access) begin
dbus_regspace <= 1'b0;
if (dBus_cmd_payload_wr) begin
if (write_mask[0]) ram[dBus_cmd_payload_address[15:2]][7:0] <= dBus_cmd_payload_data[7:0];
if (write_mask[1]) ram[dBus_cmd_payload_address[15:2]][15:8] <= dBus_cmd_payload_data[15:8];
if (write_mask[2]) ram[dBus_cmd_payload_address[15:2]][23:16] <= dBus_cmd_payload_data[23:16];
if (write_mask[3]) ram[dBus_cmd_payload_address[15:2]][31:24] <= dBus_cmd_payload_data[31:24];
end
end else if (dbus_reg_access) begin
dbus_regspace <= 1'b1;
if (!dBus_cmd_payload_wr) begin
if (valid_internal_reg)
reg_read <= periph_rdata;
else if (valid_external_reg)
reg_read <= extram_d_in;
else
reg_read <= 0;
end
end
end // else: !if(rst_out || !dBus_cmd_valid)
end // always @ (posedge clk)
// -------------
// Periherals
wire [31:0] periph_rdata;
wire timer0_comp_irq;
peripherals peripherals_inst(.clk(clk),
.nrst(nrst),
.data_out(periph_rdata),
.data_in(dBus_cmd_payload_data),
.addr(dBus_cmd_payload_address[7:2]),
.cs(dbus_reg_access && valid_internal_reg),
.oe(dBus_cmd_valid && !dBus_cmd_payload_wr),
.wstrb(dBus_cmd_valid && dBus_cmd_payload_wr?
write_mask : 4'b0000),
.porta(porta), .portb(portb),
.sdcard_sck(sdcard_sck),
.sdcard_mosi(sdcard_mosi),
.sdcard_miso(sdcard_miso),
.rxd(intercept_mode | rxd), .txd(txd_core),
.timer0_comp_irq(timer0_comp_irq)
);
endmodule // vexriscv_wrapper
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_LP_V
`define SKY130_FD_SC_LP__O32A_LP_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_lp (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_lp (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_1_V
`define SKY130_FD_SC_HD__MUX2I_1_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_1 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_1 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_1_V
|
#include <bits/stdc++.h> int main() { int n, m; scanf( %d%d , &n, &m); int min_row = n, max_row = 0, min_col = m, max_col = 0; char S[105][105]; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %c , &S[i][j]); if (S[i][j] == * ) { min_row = std::min(min_row, i), max_row = std::max(max_row, i), min_col = std::min(min_col, j), max_col = std::max(max_col, j); } } } for (int i = min_row; i <= max_row; i++, putchar( n )) { for (int j = min_col; j <= max_col; j++) { printf( %c , S[i][j]); } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor3b (
Y ,
A ,
B ,
C_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, C_N, nor0_out );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_BEHAVIORAL_V
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: March, 9th 2017
*/
`timescale 1ns / 1ps
/*
input sampling rate must be the same as clk frequency
interpolate input signal accordingly to get the
right sampling rate.
Refer to sigmadelta.ods to see how the internal width (int_w)
was determined.
*/
module jt12_dac2 #(parameter width=12)
(
input clk,
input rst,
input signed [width-1:0] din,
output reg dout
);
localparam int_w = width+5;
reg [int_w-1:0] y, error, error_1, error_2;
wire [width-1:0] undin = { ~din[width-1], din[width-2:0] };
always @(*) begin
y = undin + { error_1, 1'b0} - error_2;
dout = ~y[int_w-1];
error = y - {dout, {width{1'b0}}};
end
always @(posedge clk)
if( rst ) begin
error_1 <= {int_w{1'b0}};
error_2 <= {int_w{1'b0}};
end else begin
error_1 <= error;
error_2 <= error_1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = INT32_MAX; const int NMAX = 10007; int main() { cin.tie(0); cin.sync_with_stdio(0); cout.precision(30); string z[2]; cin >> z[0] >> z[1]; int n; cin >> n; cout << z[1] << << z[0] << endl; for (int i = 0; i < n; i++) { string k, next; cin >> k >> next; if (k == z[1]) z[1] = next; else z[0] = next; cout << z[1] << << z[0] << endl; } return 0; };
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_adapter
*/
module test_wb_adapter_8_32;
// Parameters
parameter ADDR_WIDTH = 32;
parameter WBM_DATA_WIDTH = 8;
parameter WBM_SELECT_WIDTH = 1;
parameter WBS_DATA_WIDTH = 32;
parameter WBS_SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [WBM_DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [WBM_SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [WBS_DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [WBM_DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [WBS_DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [WBS_SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
wbm_adr_i,
wbm_dat_i,
wbm_we_i,
wbm_sel_i,
wbm_stb_i,
wbm_cyc_i,
wbs_dat_i,
wbs_ack_i,
wbs_err_i,
wbs_rty_i
);
$to_myhdl(
wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbm_rty_o,
wbs_adr_o,
wbs_dat_o,
wbs_we_o,
wbs_sel_o,
wbs_stb_o,
wbs_cyc_o
);
// dump file
$dumpfile("test_wb_adapter_8_32.lxt");
$dumpvars(0, test_wb_adapter_8_32);
end
wb_adapter #(
.ADDR_WIDTH(ADDR_WIDTH),
.WBM_DATA_WIDTH(WBM_DATA_WIDTH),
.WBM_SELECT_WIDTH(WBM_SELECT_WIDTH),
.WBS_DATA_WIDTH(WBS_DATA_WIDTH),
.WBS_SELECT_WIDTH(WBS_SELECT_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const int M = 1000010; const int MAX = M; struct BIT { int bit[MAX + 1], N; BIT() {} BIT(int N) : N(N) { memset(bit, 0, sizeof(bit)); } int sum(int i) { i++; int ret = 0; while (i) { ret += bit[i]; i -= i & -i; } return ret; } int sum(int i, int j) { return sum(j - 1) - sum(i - 1); } void add(int i, int x) { i++; while (i <= N) { bit[i] += x; i += i & -i; } } int find(int i) { int lb = -1, ub = N, mid; while (ub - lb > 1) { mid = (lb + ub) / 2; if (sum(mid) >= i) ub = mid; else lb = mid; } return ub; } }; int n, m, a[M], seq[M], k[M]; int len, ns, ms; BIT b; void solve() { if (!len) { puts( Poor stack! ); return; } b = BIT(ns); for (int i = (int)(0); i < (int)(ns); i++) b.add(i, 1); for (int i = (int)(0); i < (int)(ms); i++) { for (int j = k[i] - 1; j >= 0; --j) { int pos = b.find(a[j]); b.add(pos, -1); } } for (int i = (int)(0); i < (int)(ns); i++) if (b.sum(i, i + 1)) printf( %d , seq[i]); puts( ); } void input() { scanf( %d%d , &n, &m); for (int i = (int)(0); i < (int)(m); i++) scanf( %d , a + i); for (int i = (int)(0); i < (int)(n); i++) { scanf( %d , seq + ns); if (seq[ns] < 0) { if (a[0] > len) continue; k[ms] = lower_bound(a, a + m, len + 1) - a; len -= k[ms++]; } else ++len, ++ns; } } int main() { input(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a; long long k; cin >> n >> k; vector<int> arr(n), c(n); for (int i = 0; i < n; i++) { cin >> arr[i]; } cin >> a; for (int i = 0; i < n; i++) { cin >> c[i]; } set<int> m; long long ans = 0; for (int i = 0; i < n; i++) { m.insert(c[i]); while (k < arr[i]) { if (m.empty()) { cout << -1; return 0; } ans += *(m.begin()); k += a; m.erase(m.begin()); } } cout << ans; }
|
#include <bits/stdc++.h> int p[100100]; void solve(int n, int m) { int i, j, k, x, s = 0, l = 0, r = n; for (i = 0; i < 100100; i++) p[i] = 0; for (i = 0; i <= n; i++) p[i] = i; for (k = 0; k < m; k++) { scanf( %d , &x); if (x == 1) { scanf( %d , &x); if (s == 0) { if (2 * x <= r - l) { for (i = l + x; i <= l + 2 * x; i++) p[i] = p[i] - p[2 * l + 2 * x - i]; l += x; } else { for (i = l + x; i >= 2 * l + 2 * x - r; i--) p[i] = p[i] + n - p[2 * l + 2 * x - i]; r -= r - l - x; s = 1; } } else { if (2 * x <= r - l) { x = r - l - x; for (i = l + x; i >= 2 * l + 2 * x - r; i--) p[i] = p[i] + n - p[2 * l + 2 * x - i]; r -= r - l - x; } else { x = r - l - x; for (i = l + x; i <= l + 2 * x; i++) p[i] = p[i] - p[2 * l + 2 * x - i]; l += x; s = 0; } } } else { scanf( %d%d , &i, &j); if (s == 0) { printf( %d n , p[j + l] - p[i + l]); } else { printf( %d n , p[r - i] - p[r - j]); } } } } int main() { #pragma comment(linker, /STACK:134217728 ) int n, m; while (scanf( %d%d , &n, &m) != EOF) { solve(n, m); printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m1, m2; long long C[4005][4005], f[4005], ret; long long MOD = 1000000009; int main() { for (int i = 0; i <= 4000; i++) { C[i][0] = C[i][i] = 1; for (int j = 1; j <= i; j++) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % MOD; } f[0] = 1; for (int i = (1); i <= (4000); i++) f[i] = (f[i - 1] * i) % MOD; ret = 0; scanf( %d%d%d , &n, &m1, &m2); for (int i = (1); i <= (m1); i++) for (int j = (1); j <= (m2); j++) if (i + j < n && n - j <= m1) { ret += C[m2 - 1][j - 1] * f[m2] % MOD * C[m1 - 1][n - j - 1] % MOD * f[m1] % MOD; ret %= MOD; } printf( %d n , (int)ret); return 0; }
|
//==========================================
// Function : Code Gray counter.
// Coder : Alex Claros F.
// Date : 15/May/2005.
//=======================================
`timescale 1ns/1ps
module graycounter
#(parameter COUNTER_WIDTH = 2)
(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire rst, //Count reset.
input wire Clk);
/////////Internal connections & variables///////
reg [COUNTER_WIDTH-1:0] BinaryCount;
/////////Code///////////////////////
always @ (posedge Clk)
if (rst) begin
BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'.
end
else if (Enable_in) begin
BinaryCount <= BinaryCount + 1;
GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma GCC optimize(3) #pragma GCC optimize( Ofast ) #pragma GCC optimize( inline ) #pragma GCC optimize( -fgcse ) #pragma GCC optimize( -fgcse-lm ) #pragma GCC optimize( -fipa-sra ) #pragma GCC optimize( -ftree-pre ) #pragma GCC optimize( -ftree-vrp ) #pragma GCC optimize( -fpeephole2 ) #pragma GCC optimize( -ffast-math ) #pragma GCC optimize( -fsched-spec ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( -falign-jumps ) #pragma GCC optimize( -falign-loops ) #pragma GCC optimize( -falign-labels ) #pragma GCC optimize( -fdevirtualize ) #pragma GCC optimize( -fcaller-saves ) #pragma GCC optimize( -fcrossjumping ) #pragma GCC optimize( -fthread-jumps ) #pragma GCC optimize( -funroll-loops ) #pragma GCC optimize( -fwhole-program ) #pragma GCC optimize( -freorder-blocks ) #pragma GCC optimize( -fschedule-insns ) #pragma GCC optimize( inline-functions ) #pragma GCC optimize( -ftree-tail-merge ) #pragma GCC optimize( -fschedule-insns2 ) #pragma GCC optimize( -fstrict-aliasing ) #pragma GCC optimize( -fstrict-overflow ) #pragma GCC optimize( -falign-functions ) #pragma GCC optimize( -fcse-skip-blocks ) #pragma GCC optimize( -fcse-follow-jumps ) #pragma GCC optimize( -fsched-interblock ) #pragma GCC optimize( -fpartial-inlining ) #pragma GCC optimize( no-stack-protector ) #pragma GCC optimize( -freorder-functions ) #pragma GCC optimize( -findirect-inlining ) #pragma GCC optimize( -fhoist-adjacent-loads ) #pragma GCC optimize( -frerun-cse-after-loop ) #pragma GCC optimize( inline-small-functions ) #pragma GCC optimize( -finline-small-functions ) #pragma GCC optimize( -ftree-switch-conversion ) #pragma GCC optimize( -foptimize-sibling-calls ) #pragma GCC optimize( -fexpensive-optimizations ) #pragma GCC optimize( -funsafe-loop-optimizations ) #pragma GCC optimize( inline-functions-called-once ) #pragma GCC optimize( -fdelete-null-pointer-checks ) using namespace std; const long long maxn = 1005; const long long maxm = 1000005; const long long dd = 998244353; long long n, m; long long a[maxm], sav[maxm], dp[maxn][maxn], col[maxn][maxn], L[maxn], R[maxn]; vector<long long> t[maxn]; struct nod { long long val, pos; } uni[maxm]; inline bool cmp(nod x, nod y) { return x.val < y.val; } inline long long read() { long long ret = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -f; ch = getchar(); } while (isdigit(ch)) { ret = ret * 10 + ch - 0 ; ch = getchar(); } return ret * f; } void scan() { m = read(); n = read(); for (long long k = 1; k <= n; k++) { uni[k].val = read(); uni[k].pos = k; } } void prework() { long long lst = 0; sort(uni + 1, uni + n + 1, cmp); for (long long k = 1; k <= n; k++) { if (uni[k].val != uni[k - 1].val) lst++; sav[uni[k].pos] = lst; } m = lst; long long now = 0; for (long long k = 1; k <= n; k++) if (sav[k] != a[now]) a[++now] = sav[k]; n = now; for (long long k = 1; k <= n; k++) t[a[k]].push_back(k); for (long long k = 1; k <= m; k++) L[k] = t[k][0], R[k] = t[k][t[k].size() - 1]; for (long long k = 1; k <= m; k++) for (long long j = k + 1; j <= m; j++) if ((L[j] <= R[k] && R[k] < R[j]) || (R[j] >= L[k] && L[k] > L[j])) { puts( 0 ); exit(0); } for (long long k = 1; k <= n; k++) { long long now = k; for (long long j = k; j <= n; j++) col[k][j] = a[j] > a[now] ? now : now = j; } } void solve() { for (long long k = 0; k <= n + 1; k++) for (long long j = 0; j <= k; j++) dp[k][j] = 1; dp[0][1] = dp[1][1]; for (long long k = 2; k <= n; k++) { for (long long l = 1; l + k - 1 <= n; l++) { long long r = l + k - 1; long long x = col[l][r], siz = t[a[x]].size(); long long ll = L[a[x]], rr = R[a[x]]; long long ans1 = 0, ans2 = 0, ans3 = 1; for (long long k = l - 1; k < ll; k++) ans1 = (ans1 + dp[l][k] * dp[k + 1][ll - 1]) % dd; for (long long k = r + 1; k > rr; k--) ans2 = (ans2 + dp[k][r] * dp[rr + 1][k - 1]) % dd; dp[l][r] = ans1 * ans2 % dd; for (long long k = 0; k < siz - 1; k++) ans3 = ans3 * dp[t[a[x]][k] + 1][t[a[x]][k + 1] - 1] % dd; dp[l][r] = dp[l][r] * ans3 % dd; } } printf( %lld n , dp[1][n]); } signed main() { scan(); prework(); solve(); return 0; }
|
// File: memory_array.v
// Generated by MyHDL 0.10
// Date: Mon Aug 27 20:10:17 2018
`timescale 1ns/10ps
module memory_array (
data_in,
fifo_we,
wptr,
rptr,
data_out,
clk,
clear
);
// Input:
// data_in(8bit): data to be writen
// fifo_we(bool): write enable
// wptr(5bit): write memory address pointer
// rptr(5bit): read memory address pointer
// clk(bool): clock
// clear(bool): signal to clear clear memeory to 0
// Ouput:
// data_out(8bit): data to be read out based on`rptr`
input [7:0] data_in;
input fifo_we;
input [4:0] wptr;
input [4:0] rptr;
output [7:0] data_out;
wire [7:0] data_out;
input clk;
input clear;
reg [7:0] data_out_i [0:16-1];
initial begin: INITIALIZE_DATA_OUT_I
integer i;
for(i=0; i<16; i=i+1) begin
data_out_i[i] = 0;
end
end
always @(posedge clk) begin: MEMORY_ARRAY_UPTAKE
if (fifo_we) begin
data_out_i[wptr[4-1:0]] <= data_in;
end
end
assign data_out = data_out_i[rptr[4-1:0]];
always @(negedge clear) begin: MEMORY_ARRAY_CLEARMEM
integer i;
for (i=0; i<16; i=i+1) begin
data_out_i[i] <= 0;
end
end
endmodule
|
// Wrapper for aeMB core:
// Drive wb_cyc_o (just tied to wb_stb_o for now)
// Make input reset active high (like the signal name makes it sound....)
// No longer needed
// Make it big-endian like the standard MicroBlaze
module aeMB_core_BE
#(parameter ISIZ=32, parameter DSIZ=32,
parameter MUL=0, parameter BSF=0)
(input sys_clk_i,
input sys_rst_i,
// Instruction port
output [ISIZ-1:0] if_adr,
input [31:0] if_dat,
// Data port
output dwb_we_o,
output dwb_stb_o,
output [DSIZ-1:0] dwb_adr_o,
output [31:0] dwb_dat_o,
input [31:0] dwb_dat_i,
input dwb_ack_i,
output [3:0] dwb_sel_o,
output dwb_cyc_o,
input sys_int_i,
input sys_exc_i);
wire [ISIZ-1:0] iwb_adr_o;
wire [31:0] iwb_dat_i;
wire iwb_ack_i;
wire iwb_stb_o;
assign dwb_cyc_o = dwb_stb_o;
assign iwb_ack_i = 1'b1;
assign if_adr = iwb_adr_o[ISIZ-1:0];
assign iwb_dat_i = if_dat;
// Note some "wishbone" instruction fetch signals pruned on external interface
// but not propogated change deep into aeMB.
aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF))
aeMB_edk32 (.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i),
// Instruction Port
.iwb_stb_o(iwb_stb_o),
.iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
.iwb_ack_i(iwb_ack_i),
.iwb_dat_i(iwb_dat_i),
// Data port
.dwb_wre_o(dwb_we_o),
.dwb_stb_o(dwb_stb_o),
.dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
.dwb_ack_i(dwb_ack_i),
.dwb_sel_o(dwb_sel_o),
.dwb_dat_i(dwb_dat_i),
.dwb_dat_o(dwb_dat_o),
.fsl_wre_o(),
.fsl_tag_o(),
.fsl_stb_o(),
.fsl_dat_o(),
.fsl_adr_o(),
.fsl_dat_i(32'b0),
.fsl_ack_i(1'b0),
.sys_int_i(sys_int_i) );
assign iwb_adr_o[1:0] = 2'b0;
assign dwb_adr_o[1:0] = 2'b0;
endmodule // aeMB_core_BE
|
module basic_ShieldCtrl(
//Avalon System control signal.
input rsi_MRST_reset, // reset_n from MCU GPIO
input csi_MCLK_clk,
//Avalon-MM Control.
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
//Over current interrupt.
output ins_OC_irq,
input coe_A_OCN,
output coe_A_PWREN,
output coe_A_HOE,
output coe_A_LOE,
input coe_B_OCN,
output coe_B_PWREN,
output coe_B_HOE,
output coe_B_LOE
);
reg rMODA_PWREN = 1;
reg rMODA_HOE = 0;
reg rMODA_LOE = 0;
reg rMODB_PWREN = 1;
reg rMODB_HOE = 0;
reg rMODB_LOE = 0;
assign avs_ctrl_readdata = {6'b0, ~rMODB_PWREN, ~rMODA_PWREN, 6'b0, rMODB_HOE, rMODA_HOE, 6'b0, rMODB_LOE, rMODA_LOE, 6'b0, ~coe_B_OCN, ~coe_A_OCN};
assign avs_ctrl_waitrequest = 1'b0;
assign ins_OC_irq = ~(coe_A_OCN & coe_B_OCN);
assign coe_A_PWREN = rMODA_PWREN;
assign coe_A_HOE = rMODA_HOE;
assign coe_A_LOE = rMODA_LOE;
assign coe_B_PWREN = rMODB_PWREN;
assign coe_B_HOE = rMODB_HOE;
assign coe_B_LOE = rMODB_LOE;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
rMODA_PWREN <= 1;
rMODA_HOE <= 0;
rMODA_LOE <= 0;
rMODB_PWREN <= 1;
rMODB_HOE <= 0;
rMODB_LOE <= 0;
end
else begin
if(avs_ctrl_write) begin
if(avs_ctrl_byteenable[3]) begin rMODB_PWREN <= ~avs_ctrl_writedata[25]; rMODA_PWREN <= ~avs_ctrl_writedata[24]; end
if(avs_ctrl_byteenable[2]) begin rMODB_HOE <= avs_ctrl_writedata[17]; rMODA_HOE <= avs_ctrl_writedata[16]; end
if(avs_ctrl_byteenable[1]) begin rMODB_LOE <= avs_ctrl_writedata[9]; rMODA_LOE <= avs_ctrl_writedata[8]; end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5010; const int mod = 998244353; long long d[N][N]; long long p[N]; long long inv[N]; long long _inv[N]; long long f[N]; void init(int n) { d[0][0] = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= i; j++) { d[i][j] = (d[i - 1][j - 1] * (i - j + 1) % mod + d[i - 1][j] * j % mod) % mod; } } p[0] = p[1] = inv[0] = inv[1] = _inv[0] = _inv[1] = 1; for (int i = 2; i <= n; i++) { p[i] = p[i - 1] * i % mod; inv[i] = (mod - mod / i) * inv[mod % i] % mod; _inv[i] = _inv[i - 1] * inv[i] % mod; } } int ans[N]; int main() { int n; cin >> n; init(n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { ans[i] = (ans[i] + d[j][i] * _inv[j] % mod) % mod; } for (int i = 1; i <= n; i++) ans[i] = ans[i] * p[n] % mod; for (int i = 1; i <= n; i++) cout << ans[i] << ; }
|
`define ADDER_WIDTH 096
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sync_dpram_32W_256D.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sync_dpram_32W_256D (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_dpram_32W_256D.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_dpram_32W_256D.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_dpram_32W_256D.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_dpram_32W_256D.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_dpram_32W_256D_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_dpram_32W_256D_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`include "bsg_nonsynth_dramsim3.svh"
`define dram_pkg bsg_dramsim3_hbm2_8gb_x128_pkg
module testbench();
bit clk;
bit reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(1000)
) cg0 (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(10)
) rg0 (
.clk_i(clk)
,.async_reset_o(reset)
);
import `dram_pkg::*;
// trace replay
localparam write_data_width_lp = 32; // we only write 32-bit data to save space.
localparam payload_width_p = `dram_pkg::channel_addr_width_p + 1 + write_data_width_lp;
localparam rom_addr_width_p = 20;
typedef struct packed {
logic write_not_read;
logic [`dram_pkg::channel_addr_width_p-1:0] ch_addr;
logic [write_data_width_lp-1:0] data;
} trace_s;
trace_s tr_data_lo;
logic tr_v_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [payload_width_p+4-1:0] rom_data;
logic tr_done_lo;
bsg_trace_replay #(
.payload_width_p(payload_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr0 (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(tr_done_lo)
,.error_o()
);
bsg_nonsynth_test_rom #(
.filename_p("trace.tr")
,.data_width_p(payload_width_p+4)
,.addr_width_p(rom_addr_width_p)
) trom0 (
.addr_i(rom_addr)
,.data_o(rom_data)
);
// dramsim3
//
logic [num_channels_p-1:0] dramsim3_v_li;
logic [num_channels_p-1:0][channel_addr_width_p-1:0] dramsim3_ch_addr_li;
logic [num_channels_p-1:0] dramsim3_yumi_lo;
logic [num_channels_p-1:0] dramsim3_write_not_read_li;
logic [num_channels_p-1:0] dramsim3_data_v_li;
logic [num_channels_p-1:0] dramsim3_data_yumi_lo;
logic [num_channels_p-1:0][data_width_p-1:0] dramsim3_data_li;
logic [num_channels_p-1:0] dramsim3_data_v_lo;
logic [num_channels_p-1:0][data_width_p-1:0] dramsim3_data_lo;
logic [num_channels_p-1:0][channel_addr_width_p-1:0] dramsim3_read_done_ch_addr_lo;
logic [num_channels_p-1:0] dramsim3_write_done_lo;
bsg_nonsynth_dramsim3 #(
.channel_addr_width_p(`dram_pkg::channel_addr_width_p)
,.data_width_p(`dram_pkg::data_width_p)
,.num_channels_p(`dram_pkg::num_channels_p)
,.num_columns_p(`dram_pkg::num_columns_p)
,.num_rows_p(`dram_pkg::num_rows_p)
,.num_ba_p(`dram_pkg::num_ba_p)
,.num_bg_p(`dram_pkg::num_bg_p)
,.num_ranks_p(`dram_pkg::num_ranks_p)
,.size_in_bits_p(`dram_pkg::size_in_bits_p)
,.address_mapping_p(`dram_pkg::address_mapping_p)
,.config_p(`dram_pkg::config_p)
,.masked_p(0)
,.debug_p(1)
,.init_mem_p(1)
) DUT (
.clk_i(clk)
,.reset_i(reset)
,.v_i(dramsim3_v_li)
,.write_not_read_i(dramsim3_write_not_read_li)
,.ch_addr_i(dramsim3_ch_addr_li)
,.yumi_o(dramsim3_yumi_lo)
,.data_v_i(dramsim3_data_v_li)
,.data_i(dramsim3_data_li)
,.mask_i('0)
,.data_yumi_o(dramsim3_data_yumi_lo)
,.data_v_o(dramsim3_data_v_lo)
,.data_o(dramsim3_data_lo)
,.read_done_ch_addr_o(dramsim3_read_done_ch_addr_lo)
,.write_done_o(dramsim3_write_done_lo)
,.write_done_ch_addr_o()
);
assign dramsim3_v_li[0] = tr_v_lo;
assign dramsim3_write_not_read_li[0] = tr_data_lo.write_not_read;
assign dramsim3_ch_addr_li[0] = tr_data_lo.ch_addr;
assign tr_yumi_li = dramsim3_yumi_lo[0];
assign dramsim3_data_v_li[0] = tr_v_lo & tr_data_lo.write_not_read;
assign dramsim3_data_li[0] = {{(`dram_pkg::data_width_p-write_data_width_lp){1'b0}}, tr_data_lo.data};
for (genvar i = 1; i < `dram_pkg::num_channels_p; i++) begin
assign dramsim3_v_li[i] = 1'b0;
assign dramsim3_ch_addr_li[i] = '0;
assign dramsim3_write_not_read_li[i] = 1'b0;
assign dramsim3_data_v_li[i] = 1'b0;
assign dramsim3_data_li[i] = '0;
end
// request tracker
integer sent_r;
integer recv_r;
always_ff @ (posedge clk) begin
if (reset) begin
sent_r <= 0;
recv_r <= 0;
end
else begin
if (tr_v_lo & tr_yumi_li) sent_r <= sent_r + 1;
recv_r <= recv_r + dramsim3_data_v_lo[0] + dramsim3_write_done_lo[0];
end
end
initial begin
wait(tr_done_lo & (sent_r == recv_r));
#30000;
$display("[BSG_FINISH] test successful.");
$finish();
end
// consistency checker
// num_cols_p = columns_per_row * num_banks * ba_per_bg * num_rows
localparam num_cols_p = 64*4*4*(2**15);
logic [31:0] shadow_mem [num_cols_p-1:0];
logic [`dram_pkg::channel_addr_width_p-5-1:0] col_addr;
logic [`dram_pkg::channel_addr_width_p-5-1:0] read_done_col_addr;
assign col_addr = dramsim3_ch_addr_li[0][`dram_pkg::channel_addr_width_p-1:5];
assign read_done_col_addr = dramsim3_read_done_ch_addr_lo[0][`dram_pkg::channel_addr_width_p-1:5];
always_ff @ (posedge clk) begin
if (reset) begin
for (integer i = 0; i < num_cols_p; i++)
shadow_mem[i] = '0;
end
else begin
// input record
if (dramsim3_v_li[0] & dramsim3_yumi_lo[0]) begin
if (dramsim3_write_not_read_li[0]) begin
shadow_mem[col_addr] <= dramsim3_data_li[0][0+:32];
$display("[BSG_DEBUG] t=%t writing 0x%08x to 0x%08x\n", $time, dramsim3_data_li[0][0+:32], dramsim3_ch_addr_li[0]);
end
end
// output checker
if (dramsim3_data_v_lo[0]) begin
$display("[BSG_DEBUG] t=%t read 0x%08x from 0x%08x\n",$time, dramsim3_data_lo[0][0+:32], dramsim3_read_done_ch_addr_lo[0]);
assert(shadow_mem[read_done_col_addr] == dramsim3_data_lo[0][0+:32])
//$display("[BSG_INFO] output matched. Id=%d, Expected=%x, Actual=%x", recv_id, result[recv_id], dramsim3_data_lo[0][0+:32]);
else $fatal("[BSG_FATAL] output does not match expected result for 0x%x. Expected=%x, Actual=%x",
dramsim3_read_done_ch_addr_lo[0], shadow_mem[read_done_col_addr], dramsim3_data_lo[0][0+:32]);
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, kezd[200002], veg[200002], pos[200002], inv[200002], x, csa, csb; vector<pair<pair<int, int>, int> > sz; vector<int> v; priority_queue<pair<int, int> > q; void p() { for (int i = 1; i <= n; i++) inv[pos[i]] = i; for (int i = 1; i <= n; i++) cout << inv[i] << ; cout << n ; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { int a, b; cin >> a >> b, kezd[i] = a, veg[i] = b; sz.push_back({{a, b}, i}); } sort(sz.begin(), sz.end()); for (int i = 1; i <= n; i++) { while (x < n && sz[x].first.first == i) q.push({-sz[x].first.second, sz[x].second}), x++; pos[i] = q.top().second, q.pop(); } for (int i = 1; i <= n; i++) { while (v.size() > 0 && veg[pos[v.back()]] < i) { v.pop_back(); } int a = kezd[pos[i]], b = veg[pos[i]]; if (v.size() > 0 && a <= v.back()) { csa = i, csb = v.back(); } while (v.size() > 0 && b >= veg[pos[v.back()]]) v.pop_back(); v.push_back(i); } if (!csa) { cout << YES << n ; p(); } else { cout << NO << n ; p(); swap(pos[csa], pos[csb]); p(); } return 0; }
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_gen_clock.v
*
* Date : 2012-11
*
* Description : Module that generates FCLK clocks and internal clock for Zynq BFM.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_gen_clock(
ps_clk,
sw_clk,
fclk_clk3,
fclk_clk2,
fclk_clk1,
fclk_clk0
);
input ps_clk;
output sw_clk;
output fclk_clk3;
output fclk_clk2;
output fclk_clk1;
output fclk_clk0;
parameter freq_clk3 = 50;
parameter freq_clk2 = 50;
parameter freq_clk1 = 50;
parameter freq_clk0 = 50;
reg clk0 = 1'b0;
reg clk1 = 1'b0;
reg clk2 = 1'b0;
reg clk3 = 1'b0;
reg sw_clk = 1'b0;
assign fclk_clk0 = clk0;
assign fclk_clk1 = clk1;
assign fclk_clk2 = clk2;
assign fclk_clk3 = clk3;
real clk3_p = (1000.00/freq_clk3)/2;
real clk2_p = (1000.00/freq_clk2)/2;
real clk1_p = (1000.00/freq_clk1)/2;
real clk0_p = (1000.00/freq_clk0)/2;
always #(clk3_p) clk3 = !clk3;
always #(clk2_p) clk2 = !clk2;
always #(clk1_p) clk1 = !clk1;
always #(clk0_p) clk0 = !clk0;
always #(0.5) sw_clk = !sw_clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.1415926535897932384626433; int MOD = 0; int pl(int v1, int v2) { int res = v1 + v2; if (res < 0) res += MOD; else if (res >= MOD) res -= MOD; return res; } int mul(const int v1, const int v2) { return (int)((1LL * v1 * v2) % MOD); } const int N = 250007; vector<int> fac(N); void initFac() { fac[1] = 1; for (int i = 2; i < N; i++) { fac[i] = mul(fac[i - 1], i); } } void solve() { int n; cin >> n; ; cin >> MOD; if (n == 1) { cout << 1 << endl; return; } initFac(); int ans = mul(fac[n], n); ans = pl(ans, fac[n]); for (int len = 2; len < n; len++) { int lans = n - len + 1; lans = mul(lans, fac[len]); lans = mul(lans, n - len + 1); lans = mul(lans, fac[n - len]); ans = pl(ans, lans); } cout << ans << endl; } int main() { cin.tie(nullptr); std::ios::sync_with_stdio(false); solve(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_MUX_4TO2_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_MUX_4TO2_BLACKBOX_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_mux_4to2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_MUX_4TO2_BLACKBOX_V
|
`timescale 1ns / 1ps
`include "../src/axis_blender.v"
module test_axis_blender(
);
parameter integer C_CHN_WIDTH = 8;
parameter integer C_S0_CHN_NUM = 1;
parameter integer C_S1_CHN_NUM = 3;
parameter integer C_ALPHA_WIDTH = 8;
parameter integer C_S1_ENABLE = 1;
parameter integer C_IN_NEED_WIDTH = 0;
parameter integer C_OUT_NEED_WIDTH = 0; /// must be (C_IN_NEED_WIDTH - 1), min val is 0
parameter integer C_M_WIDTH = 24; /// must be max(C_S0_CHN_NUM, C_S1_CHN_NUM) * C_CHN_WIDTH
parameter integer C_TEST = 0;
reg clk;
reg resetn;
localparam integer C_MAX_STREAM_NUM = 2;
localparam integer C_IMG_BITS = 12;
reg [C_MAX_STREAM_NUM-1:0] s_random ;
reg [C_IMG_BITS-1:0] s_width;
reg [C_IMG_BITS-1:0] s_height;
reg s_valid [C_MAX_STREAM_NUM-1:0];
wire [C_M_WIDTH + C_ALPHA_WIDTH-1:0] s_data [C_MAX_STREAM_NUM-1:0];
wire [C_IN_NEED_WIDTH:0] s_user [C_MAX_STREAM_NUM-1:0];
wire s_last [C_MAX_STREAM_NUM-1:0];
wire s_ready [C_MAX_STREAM_NUM-1:0];
reg s_enable [C_MAX_STREAM_NUM-1:0];
reg m_random ;
reg m_enprint;
wire m_valid ;
wire [C_M_WIDTH-1:0] m_data ;
wire [C_OUT_NEED_WIDTH:0]m_user ;
wire m_last ;
reg m_ready ;
axis_blender # (
.C_CHN_WIDTH (C_CHN_WIDTH ),
.C_S0_CHN_NUM (C_S0_CHN_NUM ),
.C_S1_CHN_NUM (C_S1_CHN_NUM ),
.C_ALPHA_WIDTH (C_ALPHA_WIDTH ),
.C_S1_ENABLE (C_S1_ENABLE ),
.C_IN_NEED_WIDTH (C_IN_NEED_WIDTH ),
.C_OUT_NEED_WIDTH (C_OUT_NEED_WIDTH),
.C_M_WIDTH (C_M_WIDTH ),
.C_TEST (C_TEST )
) uut (
.clk(clk),
.resetn(resetn),
.s0_axis_tvalid(s_valid [0]),
.s0_axis_tdata (s_data [0][C_S0_CHN_NUM*C_CHN_WIDTH-1:0]),
.s0_axis_tuser (s_user [0]),
.s0_axis_tlast (s_last [0]),
.s0_axis_tready(s_ready [0]),
.s1_enable (s_enable [0]),
.s1_axis_tvalid(s_valid [1]),
.s1_axis_tdata (s_data [1]),
.s1_axis_tuser (s_user [1][0]),
.s1_axis_tlast (s_last [1]),
.s1_axis_tready(s_ready [1]),
.m_axis_tvalid(m_valid ),
.m_axis_tdata (m_data ),
.m_axis_tuser (m_user ),
.m_axis_tlast (m_last ),
.m_axis_tready(m_ready )
);
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
initial begin
s_enable[0] <= 1;
s_enable[1] <= 1;
s_random <= 2'b11;
m_random <= 1'b1;
m_enprint <= 1'b1;
s_width <= 3;
s_height <= 5;
end
generate
genvar i;
genvar j;
for (i = 0; i < 2; i = i + 1) begin: single_input
reg [C_IMG_BITS-1:0] s_ridx;
reg [C_IMG_BITS-1:0] s_cidx;
reg en_input;
always @ (posedge clk) begin
if (resetn == 1'b0) en_input <= 1'b0;
else en_input <= (s_random[i] ? {$random}%2 : 1);
end
always @ (posedge clk) begin
if (resetn == 1'b0)
s_valid[i] <= 1'b0;
else if (~s_valid[i]) begin
if (en_input)
s_valid[i] <= 1'b1;
end
else begin
if (s_ready[i])
s_valid[i] <= en_input;
end
end
assign s_data[i] = (s_ridx * 16 + s_cidx) + (255 << 24);
assign s_user[i] = (s_ridx == 0 && s_cidx == 0);
assign s_last[i] = (s_cidx == s_width - 1);
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s_ridx <= 0;
s_cidx <= 0;
end
else if (s_valid[i] && s_ready[i]) begin
if (s_cidx != s_width - 1) begin
s_cidx <= s_cidx + 1;
s_ridx <= s_ridx;
end
else if (s_ridx != s_height - 1) begin
s_cidx <= 0;
s_ridx <= s_ridx + 1;
end
else begin
s_cidx <= 0;
s_ridx <= 0;
end
end
end
end
endgenerate
generate
reg [C_IMG_BITS-1:0] m_ridx;
reg [C_IMG_BITS-1:0] m_cidx;
reg en_output;
always @ (posedge clk) begin
if (resetn == 1'b0) en_output <= 1'b0;
else en_output <= (m_random ? {$random}%2 : 1);
end
always @(posedge clk) begin
if (resetn == 1'b0)
m_ready <= 1'b0;
else if (~m_ready)
m_ready <= en_output;
else begin
if (m_valid)
m_ready <= en_output;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
m_ridx = 0;
m_cidx = 0;
end
else if (m_ready && m_valid) begin
if (m_user[0]) begin
m_ridx = 0;
m_cidx = 0;
end
else if (m_last) begin
m_cidx = 0;
m_ridx = m_ridx + 1;
end
else begin
m_cidx = m_cidx + 1;
m_ridx = m_ridx;
end
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
end
else if (m_ready && m_valid && m_enprint) begin
if (m_user[0])
$write("out new frame: \n");
$write("%h ", m_data);
if (m_last)
$write("\n");
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
`define SIMULATION
module peripheral_bt_TB;
reg clk;
reg rst;
reg reset;
reg start;
reg [15:0]d_in;
reg cs;
reg [1:0]addr;
reg rd;
reg wr;
wire [15:0]d_out;
peripheral_bt uut (.clk(clk) , .rst(reset) , .d_in(d_in) , .cs(cs) , .addr(addr) , .rd(rd) , .wr(wr), .d_out(d_out) );
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
reg [20:0] i;
event reset_trigger;
reg d;
initial begin // Initialize Inputs
clk = 0; reset = 1; start = 0; d_in = 16'd0035; addr = 16'h0000; cs=1; rd=0; wr=1;
end
initial begin // Process for clk
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin // Reset the system, Start the image capture process
forever begin
@ (reset_trigger);
@ (posedge clk);
start = 0;
@ (posedge clk);
start = 1;
for(i=0; i<2; i=i+1) begin
@ (posedge clk);
end
start = 0;
#4 reset=0;
// stimulus here
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'h0001; //envio 1
addr = 16'h0000;
cs=1; rd=0; wr=1;
addr = 16'h0002;
cs=1; rd=1; wr=0;
for(i=0; i<40000; i=i+1) begin
@ (posedge clk);
end
d_in = 16'h0002; //envio 1
addr = 16'h0000;
cs=1; rd=0; wr=1;
end
end
initial begin: TEST_CASE
$dumpfile("peripheral_bt_TB.vcd");
$dumpvars(-1, uut);
#10 -> reset_trigger;
#((PERIOD*DUTY_CYCLE)*200000) $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return (b != 0 ? gcd(b, a % b) : a); } int lcm(int a, int b) { return (a / gcd(a, b) * b); } int R[] = {1, -1, 0, 0, 1, -1, -1, 1}; int C[] = {0, 0, 1, -1, 1, -1, 1, -1}; int KR[] = {-2, -2, -1, 1, 2, 2, -1, 1}; int KC[] = {1, -1, 2, 2, 1, -1, -2, -2}; struct P { double x, y; P(double x = 0.0, double y = 0.0) { this->x = x; this->y = y; } }; P mkv(P ae, P be) { return P(be.x - ae.x, be.y - ae.y); } double dtp(P ae, P be) { return (ae.x * be.x + ae.y * be.y); } double crp(P ae, P be) { return (ae.x * be.y - ae.y * be.x); } double val(P ae) { return sqrt(dtp(ae, ae)); } P vresize(P ae, double llen) { double v = val(ae); return P(ae.x * llen / v, ae.y * llen / v); } double ART(P ae, P be) { return crp(ae, be) / 2.0; } P rot(P ae, double ang) { return P(ae.x * cos(ang) - ae.y * sin(ang), ae.y * cos(ang) + ae.x * sin(ang)); } int main() { int a, b, c, d, h, m, n, p, x, y, i, j, k, l, q, r, t, cnt, sm, tmp; scanf( %d %d %d %d , &a, &b, &c, &d); sm = max((3.0 * a) / 10.0, a - (a * c / 250.0)); cnt = max((3.0 * b) / 10.0, b - (b * d / 250.0)); if (sm > cnt) printf( Misha n ); else if (cnt > sm) printf( Vasya n ); else printf( Tie n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); double a[20] = {0}; int i = 0; for (i = 0; i < 16; i++) cin >> a[i]; double x1 = a[0], x2 = a[2], x3 = a[4], x4 = a[6]; double y1 = a[1], y2 = a[3], y3 = a[5], y4 = a[7]; double maxx = max(x1, (max(x2, max(x3, x4)))); double minx = min(x1, (min(x2, min(x3, x4)))); double maxy = max(y1, (max(y2, max(y3, y4)))); double miny = min(y1, (min(y2, min(y3, y4)))); double centre2x = (a[8] + a[12]) / 2.00; double centre2y = (a[9] + a[13]) / 2.00; if (minx <= centre2x && centre2x <= maxx && miny <= centre2y && centre2y <= maxy) { cout << YES << n ; return 0; } if (minx <= a[8] && a[8] <= maxx && miny <= a[9] && a[9] <= maxy) { cout << YES << n ; return 0; } if (minx <= a[10] && a[10] <= maxx && miny <= a[11] && a[11] <= maxy) { cout << YES << n ; return 0; } if (minx <= a[12] && a[12] <= maxx && miny <= a[13] && a[13] <= maxy) { cout << YES << n ; return 0; } if (minx <= a[14] && a[14] <= maxx && miny <= a[15] && a[15] <= maxy) { cout << YES << n ; return 0; } for (i = 0; i < 16; i += 2) { double x = (a[i] + a[i + 1]) / sqrt(2); double y = (a[i] - a[i + 1]) / sqrt(2); a[i] = x; a[i + 1] = y; } x1 = a[0 + 8], x2 = a[2 + 8], x3 = a[4 + 8], x4 = a[6 + 8]; y1 = a[1 + 8], y2 = a[3 + 8], y3 = a[5 + 8], y4 = a[7 + 8]; maxx = max(x1, (max(x2, max(x3, x4)))); minx = min(x1, (min(x2, min(x3, x4)))); maxy = max(y1, (max(y2, max(y3, y4)))); miny = min(y1, (min(y2, min(y3, y4)))); centre2x = (a[8 - 8] + a[12 - 8]) / 2.00; centre2y = (a[9 - 8] + a[13 - 8]) / 2.00; if (minx <= centre2x && centre2x <= maxx && miny <= centre2y && centre2y <= maxy) { cout << YES << n ; return 0; } if (minx <= a[8 - 8] && a[8 - 8] <= maxx && miny <= a[9 - 8] && a[9 - 8] <= maxy) { cout << YES << n ; return 0; } if (minx <= a[10 - 8] && a[10 - 8] <= maxx && miny <= a[11 - 8] && a[11 - 8] <= maxy) { cout << YES << n ; return 0; } if (minx <= a[12 - 8] && a[12 - 8] <= maxx && miny <= a[13 - 8] && a[13 - 8] <= maxy) { cout << YES << n ; return 0; } if (minx <= a[14 - 8] && a[14 - 8] <= maxx && miny <= a[15 - 8] && a[15 - 8] <= maxy) { cout << YES << n ; return 0; } cout << NO << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; typedef struct st { int a; string b; } st; bool func(st x, st y) { if (x.a == y.a) return x.b > y.b; else return x.a > y.a; } int main() { string a; cin >> a; int sum1 = 0; for (int i = 0; i < a.size(); i++) sum1 += a[i] - 48; if (a.size() == 1) { cout << a; return 0; } vector<st> v(1); v[0].a = sum1; v[0].b = a; for (int i = a.size() - 2; i >= 0; i--) { string s; for (int j = 0; j <= i; j++) s += a[j]; s[s.size() - 1]--; for (int j = i + 1; j < a.size(); j++) { char f = 48 + 9; s += f; } int sum2 = 0; for (int j = 0; j < s.size(); j++) sum2 += s[j] - 48; st x; x.a = sum2; x.b = s; v.push_back(x); } sort(v.begin(), v.end(), func); if (v[0].b[0] != 0 ) cout << v[0].b; else for (int i = 1; i < v[0].b.size(); i++) cout << v[0].b[i]; return 0; }
|
#include <bits/stdc++.h> using namespace std; static const double EPS = 1e-10; template <typename T, typename S> vector<T>& operator<<(vector<T>& a, S b) { a.push_back(b); return a; } template <typename T> void operator>>(vector<T>& a, int b) { while (b--) if (!a.empty()) a.pop_back(); } bool isprime(int n) { if (n < 2) return false; for (int i = 2; i * i <= n; i++) if (n % i == 0) return false; return true; } long long b_pow(long long x, long long n) { return n ? b_pow(x * x, n / 2) * (n % 2 ? x : 1) : 1ll; } string itos(int n) { stringstream ss; ss << n; return ss.str(); } vector<int> pos[10]; int main() { ios_base::sync_with_stdio(false); string s; int n, m; cin >> n >> m; cin >> s; int e[10] = {0}; for (int i = 0; (int)i < (int)s.size(); i++) { e[s[i] - 0 ]++; pos[s[i] - 0 ].push_back(i); } string ans; vector<int> can; int mi = INT_MAX; pair<int, string> W = make_pair(INT_MAX, ~ ); for (int X = 0; X < 10; X++) { if (e[X] < m) { string mur = s; int sum = 0; int t = m - e[X]; for (int i = 1; i <= 9; i++) { int x = X - i; int y = X + i; if (y <= 9) { int j = 0; while (j < pos[y].size() && t) { mur[pos[y][j]] = X + 0 ; sum += i; t--; j++; } } if (x >= 0) { int j = pos[x].size() - 1; while (j >= 0 && t) { mur[pos[x][j]] = X + 0 ; sum += i; t--; j--; } } } W = min(W, make_pair(sum, mur)); } else if (e[X] >= m) { cout << 0 << endl; cout << s << endl; return 0; } } cout << W.first << endl; cout << W.second << endl; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: counter.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple up-counter. The maximum value is the largest expected
// value. The counter will not pass the SAT_VALUE. If the SAT_VALUE > MAX_VALUE,
// the counter will roll over and never stop. On RST_IN, the counter
// synchronously resets to the RST_VALUE
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module counter
#(parameter C_MAX_VALUE = 10,
parameter C_SAT_VALUE = 10,
parameter C_RST_VALUE = 0)
(
input CLK,
input RST_IN,
input ENABLE,
output [clog2s(C_MAX_VALUE+1)-1:0] VALUE
);
`include "functions.vh"
wire wEnable;
reg [clog2s(C_MAX_VALUE+1)-1:0] wCtrValue;
reg [clog2s(C_MAX_VALUE+1)-1:0] rCtrValue;
/* verilator lint_off WIDTH */
assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue);
/* verilator lint_on WIDTH */
assign VALUE = rCtrValue;
always @(posedge CLK) begin
if(RST_IN) begin
rCtrValue <= C_RST_VALUE;
end else if(wEnable) begin
rCtrValue <= rCtrValue + 1;
end
end
endmodule
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : if_reg.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/if_reg.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.29 - lichangbeiju - Change the xx_ to xx_n.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
//File Include : system header file
`include "../sys_include.h"
`include "isa.h"
`include "cpu.h"
module if_reg (
input wire clk ,//clock
input wire reset ,//async reset
input wire [`WordDataBus] insn ,//read inst
input wire stall ,//delay
input wire flush ,//refresh
input wire [`WordAddrBus] new_pc ,//new program count
input wire br_taken,//branch taken
input wire [`WordAddrBus] br_addr ,//branch dest address
output reg [`WordAddrBus] if_pc ,//program count
output reg [`WordDataBus] if_insn ,//inst
output reg if_en //pipeline data valid flag
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.2 the internal reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 3.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the pipeline register
//------------------------------------------------------------------------------------------------
always @(posedge clk or `RESET_EDGE reset) begin : PIPELINE_REG
//asynchronous reset
if (reset == `RESET_ENABLE) begin
if_pc <= #1 `RESET_VECTOR;
if_insn <= #1 `ISA_NOP;
if_en <= #1 `DISABLE;
end else begin
//update the pipeline reg
if (stall == `DISABLE) begin
if (flush == `ENABLE) begin //refresh the pipeline and pc
if_pc <= #1 new_pc;
if_insn <= #1 `ISA_NOP;
if_en <= #1 `DISABLE;
end else if (br_taken == `ENABLE) begin //branch taken and pc = br_addr
if_pc <= #1 br_addr;
if_insn <= #1 insn;
if_en <= #1 `ENABLE;
end else begin
if_pc <= #1 if_pc + 1'd1; //pc = next address[+1]
if_insn <= #1 insn;
if_en <= #1 `ENABLE;
end
end
end
end
//************************************************************************************************
// 4.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the clk generate module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
// Copyright (c) 2015 CERN
// @author Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// boolean values test.
module vhdl_boolean_test;
vhdl_boolean dut();
initial begin
if(dut.true_val != \true ) begin
$display("FAILED true 1");
$finish();
end
if(!dut.true_val) begin
$display("FAILED true 2");
$finish();
end
if(dut.false_val != \false ) begin
$display("FAILED false 1");
$finish();
end
if(dut.false_val) begin
$display("FAILED false 2");
$finish();
end
if(!dut.and1) begin
$display("FAILED and1");
$finish();
end
if(dut.and2) begin
$display("FAILED and2");
$finish();
end
if(dut.and3) begin
$display("FAILED and3");
$finish();
end
if(!dut.or1) begin
$display("FAILED or1");
$finish();
end
if(dut.or2) begin
$display("FAILED or2");
$finish();
end
if(dut.or3) begin
$display("FAILED or3");
$finish();
end
if(!dut.not1) begin
$display("FAILED not1");
$finish();
end
if(dut.not2) begin
$display("FAILED not2");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math ) const int maxn = 1e6 + 50; int seg[4 * maxn], ans[maxn], last_pos[maxn], next_pos[maxn]; int n, m; vector<int> v, get_val, partial_xor; vector<pair<pair<int, int>, int> > ques; void update(int val, int l, int r = n) { for (l += n, r += n; l < r; l >>= 1, r >>= 1) { if (l & 1) seg[l++] ^= val; if (r & 1) seg[--r] ^= val; } } int get_xor(int idx) { int res = 0; for (idx += n; idx; idx >>= 1) res ^= seg[idx]; return res; } void sweep(int pos) { int val = get_val[v[pos]]; int nxt = next_pos[pos]; update(val, pos, nxt); } void input() { cin >> n; for (int i = 0; i < n; i++) { int b; cin >> b; if (i == 0) partial_xor.push_back(b); else partial_xor.push_back(partial_xor[i - 1] ^ b); get_val.push_back(b); v.push_back(b); last_pos[i] = n; } cin >> m; for (int i = 0; i < m; i++) { int l, r; cin >> l >> r; l--, r--; ques.push_back({{l, r}, i}); } } void map_it() { sort(get_val.begin(), get_val.end()); vector<int>::iterator ip; ip = std::unique(get_val.begin(), get_val.end()); get_val.resize(std::distance(get_val.begin(), ip)); for (int i = v.size() - 1; i > -1; i--) { v[i] = lower_bound(get_val.begin(), get_val.end(), v[i]) - get_val.begin(); next_pos[i] = last_pos[v[i]]; last_pos[v[i]] = i; } for (int i = 0; i < get_val.size(); i++) update(get_val[i], last_pos[i]); } void answer_ques(int i) { pair<int, int> p = ques[i].first; ans[ques[i].second] = get_xor(p.second) ^ partial_xor[p.first] ^ partial_xor[p.second] ^ get_val[v[p.first]]; } void calc() { int go_pos = 0; int i = 0; sort(ques.begin(), ques.end()); while (go_pos < ques.size()) { while (go_pos < ques.size() and i == ques[go_pos].first.first) answer_ques(go_pos++); if (go_pos == ques.size()) break; while (i < ques[go_pos].first.first) sweep(i++); } } void ansing() { for (int i = 0; i < m; i++) cout << ans[i] << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); input(); map_it(); calc(); ansing(); }
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; bool replace(std::string& str, const std::string& from, const std::string& to) { size_t start_pos = str.find(from); if (start_pos == std::string::npos) return false; str.replace(start_pos, from.length(), to); return true; } inline int c(string& b) { int w = 0; for (auto& c : b) w = w * 10 + c - 0 ; return w; } struct segtree { vector<int> t; vector<int> a; int o = 0, iv = -2e9, ee; int _func(int v, int vv) { return max(v, vv); } int func(int v1, int v2) { return _func(t[v1], t[v2]); } void build(vector<int>& v, int y = -2e9) { int x = 1; iv = y; while (x < v.size()) x <<= 1; x *= 2; t.resize(x); ee = x; o = x >> 1; while (v.size() < o) v.push_back(y); for (int i = 0; i < o; i++) t[i + o] = v[i]; for (int i = o - 1; i > 0; i--) t[i] = func(i * 2, i * 2 + 1); a.resize(x); } void push(int v) { if (a[v]) { int v1 = v * 2; int v2 = v * 2 + 1; t[v] += a[v]; if (v1 < ee) { if (v1 > o) t[v1] += a[v]; else a[v1] += a[v]; } if (v2 < ee) { if (v2 > o) t[v2] += a[v]; else a[v2] += a[v]; } a[v] = 0; } } void _add(int v, int l, int r, int vl, int vr, int w) { if (vl > vr) return; if (l > vr || r < vl) return; if (vl == vr && l <= vl && vr <= r) { t[v] += w; return; } if (l <= vl && vr <= r) { a[v] += w; return; } push(v); int m = (vl + vr) >> 1; _add(v << 1, l, r, vl, m, w); _add(1 + (v << 1), l, r, m + 1, vr, w); if (vl != vr) t[v] = _func(t[v << 1] + a[v << 1], t[v * 2 + 1] + a[v * 2 + 1]); } void add(int l, int r, int v) { _add(1, l, r, 0, o - 1, v); } int q(int v, int l, int r, int vl, int vr) { if (vl > vr) return iv; if (l > vr || r < vl) return iv; push(v); if (vl != vr) t[v] = _func(t[v * 2] + a[v * 2], t[v * 2 + 1] + a[v * 2 + 1]); if (l <= vl && vr <= r) return a[v] + t[v]; int m = (vl + vr) / 2; return _func(q(v * 2, l, r, vl, m), q(v * 2 + 1, l, r, m + 1, vr)); } int query(int l, int r) { return q(1, l, r, 0, o - 1); } }; int32_t main(int32_t argc, char** argv) { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m, p; cin >> n >> m >> p; vector<pair<int, int>> a(n), b(m); vector<pair<int, pair<int, int>>> y(p); for (auto& e : a) cin >> e.first >> e.second; for (auto& e : b) cin >> e.first >> e.second; for (auto& e : y) cin >> e.first >> e.second.first >> e.second.second; sort(a.begin(), a.end()); sort(b.begin(), b.end()); sort(y.begin(), y.end()); vector<int> s(m); for (int i = 0; i < m; i++) s[i] = -b[i].second; int i1 = 0; segtree t; t.build(s, -2e9); int r = -2e9; for (int i = 0; i < n; i++) { while (i1 < y.size() && y[i1].first < a[i].first) { pair<int, int> a = {y[i1].second.first + 1, -2e9}; auto e = upper_bound(b.begin(), b.end(), a); int mx = (e - b.begin()); if (mx < m) { t.add(mx, m - 1, y[i1].second.second); } i1++; } r = max(r, t.query(0, m - 1) - a[i].second); } cout << r; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, RGB to CrYCb conversion
// The multiplication coefficients are in 1.4.12 format
// The addition coefficients are in 1.12.12 format
// Cr = (+112.439/256)*R + (-094.154/256)*G + (-018.285/256)*B + 128;
// Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16;
// Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128;
`timescale 1ns/100ps
module ad_csc_RGB2CrYCb #(
parameter DELAY_DATA_WIDTH = 16) (
// R-G-B inputs
input clk,
input [DW:0] RGB_sync,
input [23:0] RGB_data,
// Cr-Y-Cb outputs
output [DW:0] CrYCb_sync,
output [23:0] CrYCb_data);
localparam DW = DELAY_DATA_WIDTH - 1;
// Cr (red-diff)
ad_csc_1 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_csc_1_Cr (
.clk (clk),
.sync (RGB_sync),
.data (RGB_data),
.C1 (17'h00707),
.C2 (17'h105e2),
.C3 (17'h10124),
.C4 (25'h0080000),
.csc_sync_1 (CrYCb_sync),
.csc_data_1 (CrYCb_data[23:16]));
// Y (luma)
ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_Y (
.clk (clk),
.sync (1'd0),
.data (RGB_data),
.C1 (17'h0041b),
.C2 (17'h00810),
.C3 (17'h00191),
.C4 (25'h0010000),
.csc_sync_1 (),
.csc_data_1 (CrYCb_data[15:8]));
// Cb (blue-diff)
ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_Cb (
.clk (clk),
.sync (1'd0),
.data (RGB_data),
.C1 (17'h1025f),
.C2 (17'h104a7),
.C3 (17'h00707),
.C4 (25'h0080000),
.csc_sync_1 (),
.csc_data_1 (CrYCb_data[7:0]));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file BINARYZACJA.v when simulating
// the core, BINARYZACJA. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module BINARYZACJA(
a,
clk,
qspo
);
input [7 : 0] a;
input clk;
output [7 : 0] qspo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(8),
.C_DEFAULT_DATA("0"),
.C_DEPTH(256),
.C_FAMILY("spartan6"),
.C_HAS_CLK(1),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(1),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(0),
.C_HAS_SPRA(0),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("BINARYZACJA.mif"),
.C_MEM_TYPE(0),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(8)
)
inst (
.A(a),
.CLK(clk),
.QSPO(qspo),
.D(),
.DPRA(),
.SPRA(),
.WE(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.SPO(),
.DPO(),
.QDPO()
);
// synthesis translate_on
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_chip
//
// Generated
// by: wig
// on: Tue Apr 25 19:40:28 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_chip.v,v 1.1 2006/07/10 07:30:08 wig Exp $
// $Date: 2006/07/10 07:30:08 $
// $Log: avfb_chip.v,v $
// Revision 1.1 2006/07/10 07:30:08 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_chip
//
// No user `defines in this module
module avfb_chip
//
// Generated module dut
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_avfb_top
avfb_top i_avfb_top (
);
// End of Generated Instance Port Map for i_avfb_top
endmodule
//
// End of Generated Module rtl of avfb_chip
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR3_BLACKBOX_V
`define SKY130_FD_SC_HS__XNOR3_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long _pow(long long a, long long b, long long m) { if (b == 0) return 1; long long t = _pow(a, b / 2, m); t = (t * t) % m; if (b & 1) return (t * a) % m; else return t; } int main(int argc, char *argv[]) { int n; cin >> n; vector<string> v; int cnt = 0; bool zero = false; string ex = 1 ; for (int i = 0; i < n; i++) { string x; cin >> x; v.push_back(x); bool f = true; if (x[0] == 0 and x.size() == 1) zero = true; else if (x[0] == 1 ) { int cn = 0; int j; for (j = 1; j < x.size(); j++) if (x[j] != 0 ) { ex = x; break; } else cn++; if (j == x.size()) cnt += cn; } else ex = x; } if (zero) cout << 0 << endl; else { cout << ex; for (int i = 0; i < cnt; i++) cout << 0; cout << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:10:27 04/07/2016
// Design Name:
// Module Name: forwardUnit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module forwardUnit(
input [4:0] rs,
input [4:0] rt,
input MEM_WB_regWrite,
input [4:0] MEM_WB_rd,
input EX_MEM_regWrite,
input [4:0] EX_MEM_rd,
output reg [1:0] forwardA,
output reg [1:0] forwardB,
input rst
);
//forwardA
always @(*) begin
if(rst) begin
forwardA = 'b00;
forwardB = 'b00;
end
else
begin
if(MEM_WB_regWrite & MEM_WB_rd != 0 & MEM_WB_rd == rs) forwardA = 'b01;
else if(EX_MEM_regWrite & EX_MEM_rd != 0 & EX_MEM_rd == rs) forwardA = 'b10;
else forwardA = 'b00;
if(MEM_WB_regWrite & MEM_WB_rd != 0 & MEM_WB_rd == rt) forwardB = 'b01;
else if(EX_MEM_regWrite & EX_MEM_rd != 0 & EX_MEM_rd == rt) forwardB = 'b10;
else forwardB = 'b00;
end
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3,inline,unroll-loops ) using namespace std; int f[4020][4020][2][2]; inline int Mod(int x) { return x + ((x >> 31) & 1000000007); } inline void Modadd(int &x, int y) { x = Mod(x + y - 1000000007); return; } int Modular(string &a, int b) { string c; int i; long long t; c = string(a.size(), 0 ); for (i = t = 0; i < (signed)a.size(); i++) { t = t * 10 + a[i] - 48; c[i] = t / b + 48; t %= b; } for (i = 0; i < (signed)c.size() && c[i] == 0 ; i++) ; a = c.substr(i); return (int)t; } int main(void) { int p, k; string a; vector<int> b; int i, j, o; int w[6]; cin >> p >> k >> a; while (!a.empty()) b.push_back(Modular(a, p)); reverse(b.begin(), b.end()); f[0][0][1][0] = 1; for (i = 0; i < (signed)b.size(); i++) { w[0] = (long long)p * (p + 1) / 2 % 1000000007; w[1] = (long long)p * (p - 1) / 2 % 1000000007; w[2] = (long long)b[i] * (b[i] + 1) / 2 % 1000000007; w[3] = (long long)b[i] * (b[i] - 1) / 2 % 1000000007; w[4] = (long long)b[i] * (p + p - b[i] - 1) / 2 % 1000000007; w[5] = (long long)b[i] * (p + p - b[i] + 1) / 2 % 1000000007; for (j = 0; j <= i + 1; j++) { Modadd(f[i + 1][j][0][0], (long long)f[i][j][0][0] * w[0] % 1000000007); Modadd(f[i + 1][j][0][0], (long long)f[i][j][1][0] * w[2] % 1000000007); Modadd(f[i + 1][j][0][1], (long long)f[i][j][0][0] * w[1] % 1000000007); Modadd(f[i + 1][j][0][1], (long long)f[i][j][1][0] * w[3] % 1000000007); Modadd(f[i + 1][j][1][0], (long long)f[i][j][1][0] * (b[i] + 1) % 1000000007); Modadd(f[i + 1][j][1][1], (long long)f[i][j][1][0] * b[i] % 1000000007); Modadd(f[i + 1][j + 1][0][0], (long long)f[i][j][0][1] * w[1] % 1000000007); Modadd(f[i + 1][j + 1][0][0], (long long)f[i][j][1][1] * w[4] % 1000000007); Modadd(f[i + 1][j + 1][0][1], (long long)f[i][j][0][1] * w[0] % 1000000007); Modadd(f[i + 1][j + 1][0][1], (long long)f[i][j][1][1] * w[5] % 1000000007); Modadd(f[i + 1][j + 1][1][0], (long long)f[i][j][1][1] * (p - b[i] - 1) % 1000000007); Modadd(f[i + 1][j + 1][1][1], (long long)f[i][j][1][1] * (p - b[i]) % 1000000007); } } for (i = k, o = 0; i <= (signed)b.size(); i++) Modadd(o, Mod(f[b.size()][i][0][0] + f[b.size()][i][1][0] - 1000000007)); cout << o << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct fenwick_tree_1D { long long n, log_n; vector<long long> tree; fenwick_tree_1D(long long _n) : n(_n), log_n((long long)(log2(_n) + 1.0L)), tree(_n + 5) {} void update(long long x, long long v) { while (x <= n) { tree[x] += v; x += x & (-x); } } long long prefix_sum(long long x) { long long r = 0; while (x) { r += tree[x]; x -= x & (-x); } return r; } long long range_sum(long long l, long long r) { return prefix_sum(r) - prefix_sum(l - 1); } }; const long long bs = 300; fenwick_tree_1D bit(100005); long long a[100005], nxt[100005], last[100005] = {0}, dl[2 * bs + 5], id[100005], dc = 0, result[100005] = {0}; set<long long> s[100005]; long long qc; struct query { long long t, l, r, qno; } q[bs + 5]; long long q2c; struct query2 { long long l, r, qno; } q2[bs + 5]; vector<long long> ans; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); long long n, m; cin >> n >> m; for (long long i = 1; i <= n; i++) { cin >> a[i]; s[a[i]].insert(i); } for (long long h = 0; h < m; h += bs) { qc = min(bs, m - h); for (long long j = 0; j < qc; j++) { cin >> q[j].t >> q[j].l >> q[j].r; q[j].qno = h + j; if (q[j].t == 1) { if (!id[a[q[j].l]]) dl[dc] = a[q[j].l], id[a[q[j].l]] = 1, dc++; if (!id[q[j].r]) dl[dc] = q[j].r, id[q[j].r] = 1, dc++; } else q2[q2c].l = q[j].l, q2[q2c].r = q[j].r, q2[q2c].qno = q[j].qno, ans.push_back(q[j].qno), q2c++; } for (long long i = n; i >= 1; i--) { if (id[a[i]]) { nxt[i] = 0; continue; } nxt[i] = last[a[i]]; if (nxt[i]) bit.update(nxt[i], nxt[i] - i); last[a[i]] = i; } sort(q2, q2 + q2c, [](const query2 &l, const query2 &r) { return l.l < r.l; }); long long pos = 1; for (long long i = 0; i < q2c; i++) { while (pos < q2[i].l) { if (id[a[pos]] || !nxt[pos]) { pos++; continue; } bit.update(nxt[pos], pos - nxt[pos]); pos++; } result[q2[i].qno] = bit.prefix_sum(q2[i].r); } for (long long i = 0; i < qc; i++) { if (q[i].t == 1) { s[a[q[i].l]].erase(q[i].l); a[q[i].l] = q[i].r; s[a[q[i].l]].insert(q[i].l); } else { for (long long j = 0; j < dc; j++) { auto it1 = s[dl[j]].lower_bound(q[i].l); auto it2 = s[dl[j]].upper_bound(q[i].r); if (it1 != s[dl[j]].end() && it2 != s[dl[j]].begin()) { it2--; if (*it2 > *it1) result[q[i].qno] += *it2 - *it1; } } } } for (long long i = 0; i < dc; i++) id[dl[i]] = 0; dc = 0; q2c = 0; for (long long i = 1; i <= n; i++) bit.tree[i] = 0, last[i] = 0; } for (auto &k : ans) cout << result[k] << n ; }
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#include <bits/stdc++.h> using std::abs; using std::bitset; using std::cerr; using std::cin; using std::copy; using std::cout; using std::deque; using std::endl; using std::fill; using std::fixed; using std::greater; using std::iota; using std::istream; using std::lower_bound; using std::make_pair; using std::make_tuple; using std::map; using std::max; using std::max_element; using std::min; using std::min_element; using std::multiset; using std::next_permutation; using std::nth_element; using std::ostream; using std::pair; using std::priority_queue; using std::queue; using std::reverse; using std::rotate; using std::set; using std::sort; using std::string; using std::swap; using std::tie; using std::tuple; using std::unique; using std::unordered_map; using std::unordered_set; using std::upper_bound; using std::vector; long long rnd(long long x, long long y) { static auto gen = std::bind(std::uniform_int_distribution<long long>(), std::mt19937(960172)); return gen() % (y - x + 1) + x; } long long gcd(long long a, long long b) { while (b > 0) { long long t = a % b; a = b; b = t; } return a; } template <typename T> T sqr(T const& a) { return a * a; } int const INF = 100 + (int)1e9; long long const INFL = 100 + (long long)1e18; long double const PI = 3.1415926535897932384626433832795028; int const N = 211; int const A = 26; int next[N][A]; int link[N]; int go[N][A]; int prev[N]; int back[N]; int leaf[N]; int sz; int getNode(int pr, int edge) { std::fill(next[sz], next[sz] + A, -1); link[sz] = -1; std::fill(go[sz], go[sz] + A, -1); prev[sz] = pr; back[sz] = edge; leaf[sz] = 0; return sz++; } int getGo(int, int); int getLink(int v) { if (link[v] == -1) { if (v == 0 || prev[v] == 0) { link[v] = 0; } else { link[v] = getGo(getLink(prev[v]), back[v]); } } return link[v]; } int getGo(int v, int x) { if (go[v][x] == -1) { if (next[v][x] != -1) { go[v][x] = next[v][x]; } else if (v == 0) { go[v][x] = v; } else { go[v][x] = getGo(getLink(v), x); } } return go[v][x]; } void mul(long long a[N][N], long long b[N][N], long long c[N][N]) { static long long t[N][N]; for (int i = 0; i < N; ++i) { for (int j = 0; j < N; ++j) { long long cur = -INFL; for (int k = 0; k < N; ++k) { cur = max(cur, a[i][k] + b[k][j]); } t[i][j] = cur; } } for (int i = 0; i < N; ++i) { for (int j = 0; j < N; ++j) { c[i][j] = t[i][j]; } } } int a[N]; void solve() { int n; long long L; scanf( %d %lld , &n, &L); for (int i = 0; i < n; ++i) { scanf( %d , a + i); } static char buf[N]; gets(buf); getNode(0, 0); for (int i = 0; i < n; ++i) { gets(buf); int v = 0; for (int j = 0; buf[j]; ++j) { int x = buf[j] - a ; if (next[v][x] == -1) { next[v][x] = getNode(v, x); } v = next[v][x]; } leaf[v] += a[i]; } { vector<int> q = {0}; for (int head = 0; head < (int)q.size(); ++head) { int v = q[head]; leaf[v] += leaf[getLink(v)]; for (int x = 0; x < A; ++x) { int to = next[v][x]; if (to >= 0) { q.push_back(to); } } } } static long long mat[N][N]; for (int i = 0; i < N; ++i) { fill(mat[i], mat[i] + N, -INFL); } for (int from = 0; from < sz; ++from) { for (int x = 0; x < A; ++x) { int to = getGo(from, x); if (mat[to][from] == -INFL) { mat[to][from] = 0; } mat[to][from] += leaf[to]; } } static long long dp[N]; fill(dp, dp + N, -INFL); dp[0] = 0; for (long long l = L; l > 0; l /= 2) { if (l % 2 == 1) { static long long dp1[N]; for (int v = 0; v < N; ++v) { long long cur = -INFL; for (int u = 0; u < N; ++u) { cur = max(cur, dp[u] + mat[v][u]); } dp1[v] = cur; } for (int i = 0; i < N; ++i) { dp[i] = dp1[i]; } } mul(mat, mat, mat); } cout << *max_element(dp, dp + N) << endl; } int main() { cout.precision(15); cout << fixed; cerr.precision(6); cerr << fixed; solve(); }
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Control_Velocity.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Control_Velocity
// Source Path: velocityControlHdl/Control_Velocity
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Control_Velocity
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
velocity_command,
velocity_measured,
param_velocity_p_gain,
param_velocity_i_gain,
q_command
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [17:0] velocity_command; // sfix18_En8
input signed [17:0] velocity_measured; // sfix18_En8
input signed [17:0] param_velocity_p_gain; // sfix18_En16
input signed [17:0] param_velocity_i_gain; // sfix18_En15
output signed [17:0] q_command; // sfix18_En15
wire signed [18:0] Error_Sum_sub_cast; // sfix19_En8
wire signed [18:0] Error_Sum_sub_cast_1; // sfix19_En8
wire signed [18:0] Error_Sum_sub_temp; // sfix19_En8
wire signed [17:0] velocity_error; // sfix18_En7
// Velocity Controller
//
// The controller regulates motor velocity using rotor velocity feedback compared to a commanded velocity.
// The output of the controller is the quadrature-winding current command which is directly proportional to the electromagnetic torque of the motor.
// Since the motor being controlled is a Permanent Magnet Synchronous Machine, the rotor flux linkage is fixed (determined by the magnets),
// hence the commanded direct-winding current is always zero.
// <S2>/Error Sum
assign Error_Sum_sub_cast = velocity_command;
assign Error_Sum_sub_cast_1 = velocity_measured;
assign Error_Sum_sub_temp = Error_Sum_sub_cast - Error_Sum_sub_cast_1;
assign velocity_error = Error_Sum_sub_temp[18:1];
// <S2>/Rotor_Velocity_Control
velocityControlHdl_Rotor_Velocity_Control u_Rotor_Velocity_Control (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(Reset_1),
.Err(velocity_error), // sfix18_En7
.param_velocity_p_gain(param_velocity_p_gain), // sfix18_En16
.param_velocity_i_gain(param_velocity_i_gain), // sfix18_En15
.Out(q_command) // sfix18_En15
);
endmodule // velocityControlHdl_Control_Velocity
|
module acl_iface_system (
config_clk_clk,
reset_n,
kernel_clk_clk,
kernel_clk_snoop_clk,
kernel_mem0_waitrequest,
kernel_mem0_readdata,
kernel_mem0_readdatavalid,
kernel_mem0_burstcount,
kernel_mem0_writedata,
kernel_mem0_address,
kernel_mem0_write,
kernel_mem0_read,
kernel_mem0_byteenable,
kernel_mem0_debugaccess,
kernel_reset_reset_n,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
peripheral_hps_io_emac1_inst_TX_CLK,
peripheral_hps_io_emac1_inst_TXD0,
peripheral_hps_io_emac1_inst_TXD1,
peripheral_hps_io_emac1_inst_TXD2,
peripheral_hps_io_emac1_inst_TXD3,
peripheral_hps_io_emac1_inst_RXD0,
peripheral_hps_io_emac1_inst_MDIO,
peripheral_hps_io_emac1_inst_MDC,
peripheral_hps_io_emac1_inst_RX_CTL,
peripheral_hps_io_emac1_inst_TX_CTL,
peripheral_hps_io_emac1_inst_RX_CLK,
peripheral_hps_io_emac1_inst_RXD1,
peripheral_hps_io_emac1_inst_RXD2,
peripheral_hps_io_emac1_inst_RXD3,
peripheral_hps_io_sdio_inst_CMD,
peripheral_hps_io_sdio_inst_D0,
peripheral_hps_io_sdio_inst_D1,
peripheral_hps_io_sdio_inst_CLK,
peripheral_hps_io_sdio_inst_D2,
peripheral_hps_io_sdio_inst_D3,
peripheral_hps_io_usb1_inst_D0,
peripheral_hps_io_usb1_inst_D1,
peripheral_hps_io_usb1_inst_D2,
peripheral_hps_io_usb1_inst_D3,
peripheral_hps_io_usb1_inst_D4,
peripheral_hps_io_usb1_inst_D5,
peripheral_hps_io_usb1_inst_D6,
peripheral_hps_io_usb1_inst_D7,
peripheral_hps_io_usb1_inst_CLK,
peripheral_hps_io_usb1_inst_STP,
peripheral_hps_io_usb1_inst_DIR,
peripheral_hps_io_usb1_inst_NXT,
peripheral_hps_io_uart0_inst_RX,
peripheral_hps_io_uart0_inst_TX,
peripheral_hps_io_i2c1_inst_SDA,
peripheral_hps_io_i2c1_inst_SCL,
peripheral_hps_io_gpio_inst_GPIO53);
input config_clk_clk;
input reset_n;
output kernel_clk_clk;
output kernel_clk_snoop_clk;
output kernel_mem0_waitrequest;
output [255:0] kernel_mem0_readdata;
output kernel_mem0_readdatavalid;
input [4:0] kernel_mem0_burstcount;
input [255:0] kernel_mem0_writedata;
input [24:0] kernel_mem0_address;
input kernel_mem0_write;
input kernel_mem0_read;
input [31:0] kernel_mem0_byteenable;
input kernel_mem0_debugaccess;
output kernel_reset_reset_n;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
output peripheral_hps_io_emac1_inst_TX_CLK;
output peripheral_hps_io_emac1_inst_TXD0;
output peripheral_hps_io_emac1_inst_TXD1;
output peripheral_hps_io_emac1_inst_TXD2;
output peripheral_hps_io_emac1_inst_TXD3;
input peripheral_hps_io_emac1_inst_RXD0;
inout peripheral_hps_io_emac1_inst_MDIO;
output peripheral_hps_io_emac1_inst_MDC;
input peripheral_hps_io_emac1_inst_RX_CTL;
output peripheral_hps_io_emac1_inst_TX_CTL;
input peripheral_hps_io_emac1_inst_RX_CLK;
input peripheral_hps_io_emac1_inst_RXD1;
input peripheral_hps_io_emac1_inst_RXD2;
input peripheral_hps_io_emac1_inst_RXD3;
inout peripheral_hps_io_sdio_inst_CMD;
inout peripheral_hps_io_sdio_inst_D0;
inout peripheral_hps_io_sdio_inst_D1;
output peripheral_hps_io_sdio_inst_CLK;
inout peripheral_hps_io_sdio_inst_D2;
inout peripheral_hps_io_sdio_inst_D3;
inout peripheral_hps_io_usb1_inst_D0;
inout peripheral_hps_io_usb1_inst_D1;
inout peripheral_hps_io_usb1_inst_D2;
inout peripheral_hps_io_usb1_inst_D3;
inout peripheral_hps_io_usb1_inst_D4;
inout peripheral_hps_io_usb1_inst_D5;
inout peripheral_hps_io_usb1_inst_D6;
inout peripheral_hps_io_usb1_inst_D7;
input peripheral_hps_io_usb1_inst_CLK;
output peripheral_hps_io_usb1_inst_STP;
input peripheral_hps_io_usb1_inst_DIR;
input peripheral_hps_io_usb1_inst_NXT;
input peripheral_hps_io_uart0_inst_RX;
output peripheral_hps_io_uart0_inst_TX;
inout peripheral_hps_io_i2c1_inst_SDA;
inout peripheral_hps_io_i2c1_inst_SCL;
inout peripheral_hps_io_gpio_inst_GPIO53;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PR_PP_PKG_SN_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_PR_PP_PKG_SN_BLACKBOX_V
/**
* udp_dff$PR_pp$PKG$sN: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$PR_pp$PKG$sN (
Q ,
D ,
CLK ,
RESET ,
SLEEP_B ,
NOTIFIER,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK ;
input RESET ;
input SLEEP_B ;
input NOTIFIER;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PR_PP_PKG_SN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long oo = 1000000000000000000; long long sum, ans = 0, mx = 0, mn = 1000000000, num, pos; vector<int> v[100001]; long long int a[100001], mxx[100001]; map<int, int> mp[100001]; void unin(int x, int y) { if (mp[x].size() < mp[y].size()) { mp[x].swap(mp[y]); mxx[x] = mxx[y]; a[x] = a[y]; } for (map<int, int>::iterator it = mp[y].begin(); it != mp[y].end(); it++) { mp[x][(it)->first] += (it)->second; if (mp[x][it->first] == mxx[x]) { a[x] += it->first; } else if (mp[x][it->first] > mxx[x]) { mxx[x] = mp[x][it->first]; a[x] = it->first; } } } void dfs(int u, int pr = -1) { for (int i = 0; i < v[u].size(); i++) { int to = v[u][i]; if (to == pr) continue; dfs(to, u); unin(u, to); } } int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> num; mp[i][num]++; mxx[i] = 1; a[i] = num; } int x, y; for (int i = 1; i < n; i++) { cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } dfs(1); for (int i = 1; i <= n; i++) { num = 0; cout << a[i] << ; sum = 0; } }
|
`timescale 1ns/1ps
/***************************************************************************
Name:
Date: 7/11/2016
Founction: Send out capture value
Note:
****************************************************************************/
module captuer_tx(
clk,rst_n,tx_start,capture_ready,periodcounter,tx_data,counter,led_input
);
input clk;
input rst_n;
input capture_ready;
input [31:0] counter;
input led_input;
input[31:0] periodcounter;
output tx_start;
output [7:0] tx_data;
reg tx_start;
reg[7:0] tx_data;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n)begin
tx_start <= 1'b1;
tx_data <= 'hzz;
end
else if(capture_ready)begin
tx_start <= 1'b0;
tx_data <= (periodcounter >= 'd100000000) ? "S"
:((periodcounter < 'd100000000) && (periodcounter >= 'd10000000)) ? "F"
:((periodcounter < 'd10000000) && (periodcounter >= 'd5000000)) ? "H"
:(periodcounter < 'd5000000) ? "E" : 'hzz;
end
else if(counter > 'd300000000)begin
tx_start <= 1'b0;
tx_data <= led_input ? "M" : "L";
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n, m; cin >> n >> m; vector<vector<char>> arr(n + 2, vector<char>(m + 2)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> arr[i][j]; } } for (int i = 0; i < n + 2; i++) { arr[i][0] = arr[i][m + 1] = . ; } for (int i = 0; i < m + 2; i++) { arr[0][i] = arr[n + 1][i] = . ; } n += 2, m += 2; int l = 0, r = n + m + 1; vector<vector<int>> dist(n, vector<int>(m)); queue<pair<int, int>> q; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (arr[i][j] == . ) { q.emplace(i, j); dist[i][j] = 0; } else { dist[i][j] = INF; } } } while (!q.empty()) { int i = q.front().first, j = q.front().second; q.pop(); vector<pair<int, int>> t = {{1, 0}, {1, 1}, {0, 1}, {-1, 1}, {-1, 0}, {-1, -1}, {0, -1}, {1, -1}}; for (auto &add : t) { int ni = i + add.first, nj = j + add.second; if (ni >= 0 && ni < n && nj >= 0 && nj < m && dist[ni][nj] == INF) { dist[ni][nj] = dist[i][j] + 1; q.emplace(ni, nj); } } } while (r - l > 1) { int t = (l + r) / 2; vector<vector<int>> dist_start(n, vector<int>(m)); deque<pair<int, int>> q; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (arr[i][j] == X && dist[i][j] > t) { q.emplace_back(i, j); dist_start[i][j] = 0; } else { dist_start[i][j] = INF; } } } while (!q.empty()) { int i = q.front().first, j = q.front().second; q.pop_front(); vector<pair<int, int>> t = {{1, 0}, {1, 1}, {0, 1}, {-1, 1}, {-1, 0}, {-1, -1}, {0, -1}, {1, -1}}; for (auto &add : t) { int ni = i + add.first, nj = j + add.second; if (ni >= 0 && ni < n && nj >= 0 && nj < m && dist_start[ni][nj] == INF) { dist_start[ni][nj] = dist_start[i][j] + 1; q.emplace_back(ni, nj); } } } bool flag = true; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (arr[i][j] == X && dist_start[i][j] > t) { flag = false; } } } if (flag) { l = t; } else { r = t; } } cout << l << n ; for (int i = 1; i < n - 1; i++) { for (int j = 1; j < m - 1; j++) { if (arr[i][j] == X && dist[i][j] > l) { cout << X ; } else { cout << . ; } } cout << n ; } return 0; }
|
module Mod_Teste_Template(
input CLOCK_27,
input CLOCK_50,
input [3:0] KEY,
input [17:0] SW,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
output [8:0] LEDG,
output [17:0] LEDR,
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0, // GPIO Connection 0
inout [35:0] GPIO_1
);
assign GPIO_1 = 36'hzzzzzzzzz;
assign GPIO_0 = 36'hzzzzzzzzz;
// LCD
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
Output_LiquidCyrstalDisplay_TestModule LCD0 (
// Host Side
.iCLK ( CLOCK_50 ),
.iRST_N ( KEY[0] ),
// Data to display
.d0(ADDR_bus), // 4 dígitos canto superior esquerdo
.d1(DATA_bus), // 4 dígitos superior meio
.d2(INSTR_bus), // 4 dígitos canto superior direito
.d3(CNTRL_bus), // 4 dígitos canto inferior esquerdo
.d4(PC), // 4 dígitos inferior meio
.d5(D_bus), // 4 dígitos canto inferior direito
// LCD Side
.LCD_DATA( LCD_DATA ),
.LCD_RW( LCD_RW ),
.LCD_EN( LCD_EN ),
.LCD_RS( LCD_RS )
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter INSTR_WIDTH = WORD_WIDTH;
wire RST = KEY[0], CLK = KEY[3];
// Program Counter
reg [WORD_WIDTH-1:0] PC;
always@(posedge CLK)
begin
if(RST == 0) //SE O RESET FOI ATIVADO
PC <= 0;//ZERA O PC
else if((PL)&&(JB)) //JUMP INCONDICIONAL
PC <= ADDR_bus;//RECEBE O VALOR DE BUS_A QUE DIZ A NOVA POSIÇÃO PRA ONDE VAI PULAR
else if((PL)&&(!JB)&&(BC)&&(N)) //(JUMP) BRANCH ON NEGATIVE
PC <= PC + {{10{INSTR_bus[8]}}, INSTR_bus[8:6], INSTR_bus[2:0]};//AQUI VÊMOS O EXTEND, OU SEJA,
else if((PL)&&(!JB)&&(!BC)&&(Z)) //(JUMP) BRANCH ON ZERO SOMA O PC COM UM NOVO VALOR PRA ELE APONTAR
PC <= PC + {{10{INSTR_bus[8]}}, INSTR_bus[8:6], INSTR_bus[2:0]};
else //CASO PADRÃO DO PC
PC <= PC + 1'b1;
end
// Instruction Memory
reg [INSTR_WIDTH-1:0] INSTR_bus;
always@(PC)
begin
case(PC)
//16'h0000: INSTR_out = 16'b000_0000_000_000_000; //
16'h0000: INSTR_bus = 16'b100_1100_000_000_011; // LDI R0 <- 3
16'h0001: INSTR_bus = 16'b100_1100_001_000_111; // LDI R1 <- 7
16'h0002: INSTR_bus = 16'b000_0000_010_000_XXX; // MOVA R2 <- R0
16'h0003: INSTR_bus = 16'b000_1100_011_XXX_001; // MOVB R3 <- R1
16'h0004: INSTR_bus = 16'b000_0010_100_000_001; // ADD R4 <- R0;R1
16'h0005: INSTR_bus = 16'b000_0101_101_011_100; // SUB R5 <- R3;R4
16'h0006: INSTR_bus = 16'b110_0000_000_101_011; // BRZ R5;3
16'h0007: INSTR_bus = 16'b110_0001_000_101_011; // BRN R5;3
16'h000A: INSTR_bus = 16'b111_0000_110_000_001; // JMP R0;
endcase
end
// Instruction Decoder
wire [3*DR_WIDTH-1+11:0] CNTRL_bus;
wire PL = CNTRL_bus[2];
wire JB = CNTRL_bus[1];
wire BC = CNTRL_bus[0];
wire [OPCODE_WIDTH-1:0] OPCODE = INSTR_bus[15:9];
assign CNTRL_bus[0] = INSTR_bus[9];
assign CNTRL_bus[1] = INSTR_bus[13];
assign CNTRL_bus[2] = INSTR_bus[15]&INSTR_bus[14];
assign CNTRL_bus[3] = ~INSTR_bus[15]&INSTR_bus[14];
assign CNTRL_bus[4] = ~INSTR_bus[14];
assign CNTRL_bus[5] = INSTR_bus[13];
assign CNTRL_bus[9:6] = {INSTR_bus[12:10],~CNTRL_bus[2]&INSTR_bus[9]};
assign CNTRL_bus[10] = INSTR_bus[15];
assign CNTRL_bus[13:11] = INSTR_bus[2:0];
assign CNTRL_bus[16:14] = INSTR_bus[5:3];
assign CNTRL_bus[19:17] = INSTR_bus[8:6];
// Register file
reg [WORD_WIDTH-1:0] ADDR_bus;
reg [WORD_WIDTH-1:0] B_data;
wire RW = CNTRL_bus[4];
wire [SA_WIDTH-1:0] DA = CNTRL_bus[19:17];
wire [SA_WIDTH-1:0] AA = CNTRL_bus[16:14];
wire [SA_WIDTH-1:0] BA = CNTRL_bus[13:11];
reg [WORD_WIDTH-1:0] SYNC_RAM0 [2**DR_WIDTH-1:0];
reg [WORD_WIDTH-1:0] SYNC_RAM1 [2**DR_WIDTH-1:0];
always@(posedge CLK) begin
if(RW) begin
SYNC_RAM0[DA] <= D_bus;
SYNC_RAM1[DA] <= D_bus;
end
end
always@(*) begin
ADDR_bus <= SYNC_RAM0[AA];
B_data <= SYNC_RAM1[BA];
end
/*
reg [WORD_WIDTH-1:0] REGS[7:0];
always@(posedge CLK)
if(RW)
case(DA)
3'b 000 : REGS[0] <= D_bus;
3'b 001 : REGS[1] <= D_bus;
3'b 010 : REGS[2] <= D_bus;
3'b 011 : REGS[3] <= D_bus;
3'b 100 : REGS[4] <= D_bus;
3'b 101 : REGS[5] <= D_bus;
3'b 110 : REGS[6] <= D_bus;
3'b 111 : REGS[7] <= D_bus;
endcase
always@(AA, BA, REGS)
begin
case(AA)
3'b 000 : ADDR_bus <= REGS[0];
3'b 001 : ADDR_bus <= REGS[1];
3'b 010 : ADDR_bus <= REGS[2];
3'b 011 : ADDR_bus <= REGS[3];
3'b 100 : ADDR_bus <= REGS[4];
3'b 101 : ADDR_bus <= REGS[5];
3'b 110 : ADDR_bus <= REGS[6];
3'b 111 : ADDR_bus <= REGS[7];
endcase
case(BA)
3'b 000 : B_data <= REGS[0];
3'b 001 : B_data <= REGS[1];
3'b 010 : B_data <= REGS[2];
3'b 011 : B_data <= REGS[3];
3'b 100 : B_data <= REGS[4];
3'b 101 : B_data <= REGS[5];
3'b 110 : B_data <= REGS[6];
3'b 111 : B_data <= REGS[7];
endcase
end
*/
// B Muxer
reg [WORD_WIDTH-1:0] DATA_bus;
wire MB = CNTRL_bus[10];
always@(MB, B_data, INSTR_bus)
case(MB)
1'b0: DATA_bus <= B_data;
1'b1: DATA_bus <= INSTR_bus[2:0];
endcase
// Arithmetic Logic Unit
parameter FS_WIDTH = 4;
reg [WORD_WIDTH-1:0] F;
wire [WORD_WIDTH-2:0] V_temp;
wire [FS_WIDTH-1:0] FS = CNTRL_bus[9:6];
wire V, N, Z;
reg C;
assign V_temp = ADDR_bus[WORD_WIDTH-2:0]+DATA_bus[WORD_WIDTH-2:0];
assign V = V_temp[WORD_WIDTH-2:0];
assign N = F[WORD_WIDTH-1];
assign Z = (!F)?1'b1:1'b0;
always@(*)
case(FS)
4'b0000: {C, F} = ADDR_bus; // Move A
4'b0001: {C, F} = ADDR_bus+1; // Increment
4'b0010: {C, F} = ADDR_bus+DATA_bus; // Add
4'b0011: {C, F} = ADDR_bus+DATA_bus+1; //
4'b0100: {C, F} = ADDR_bus+(~DATA_bus); //
4'b0101: {C, F} = ADDR_bus+(~DATA_bus)+1; // Subtraction
4'b0110: {C, F} = ADDR_bus-1; // Decrement
4'b0111: {C, F} = ADDR_bus; // Move A
4'b1000: {C, F} = ADDR_bus&DATA_bus; // Bitwize and
4'b1001: {C, F} = ADDR_bus|DATA_bus; // Bitwize or
4'b1010: {C, F} = ADDR_bus^DATA_bus; // Bitwize xor
4'b1011: {C, F} = (~ADDR_bus); // Bitwize Invert
4'b1100: {C, F} = DATA_bus; // Move B
4'b1101: {C, F} = (DATA_bus>>1); // Shift Right B
4'b1110: {C, F} = (DATA_bus<<1); // Shift Left B
4'b1111: {C, F} = (~DATA_bus); // Ivert B
endcase
// Data Memory
reg [WORD_WIDTH-1:0] DMEM [2**DR_WIDTH-1:0];
reg [WORD_WIDTH-1:0] DMEM_out;
wire MW = CNTRL_bus[3];
always@(ADDR_bus, DATA_bus, MW) begin
if(MW)
DMEM[ADDR_bus] <= DATA_bus;
end
always@(*)
DMEM_out <= DMEM[ADDR_bus];
// D Muxer
reg [WORD_WIDTH-1:0] D_bus;
wire MD = CNTRL_bus[5];
always@(F, DMEM_out, MD)
case(MD)
1'b0: D_bus = F;
1'b1: D_bus = DMEM_out;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; long long a, b, w, x; int main() { while (scanf( %d , &n) != EOF) { cin >> a >> b; for (int i = 1; i <= n; i++) { scanf( %I64d , &w); x = w * a / b; x = x * b; printf( %I64d%c , (w * a - x) / a, n [i == n]); } } return 0; }
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts resamples the chroma components of a video in *
* stream, whos colour space is YCrCb. *
* *
******************************************************************************/
module Raster_Laser_Projector_Video_In_video_chroma_resampler_0 (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 15; // Incoming frame's data width
parameter ODW = 23; // Outcoming frame's data width
parameter IEW = 0; // Incoming frame's empty width
parameter OEW = 1; // Outcoming frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [ODW:0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [OEW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IDW:0] data;
reg startofpacket;
reg endofpacket;
reg [IEW:0] empty;
reg valid;
reg [ 7: 0] saved_CrCb;
reg cur_is_Cr_or_Cb;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
saved_CrCb <= 8'h00;
else if (stream_in_ready & stream_in_startofpacket)
saved_CrCb <= 8'h00;
else if (transfer_data & valid)
saved_CrCb <= data[15: 8];
end
always @(posedge clk)
begin
if (reset)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready & stream_in_startofpacket)
cur_is_Cr_or_Cb <= 1'b0;
else if (stream_in_ready)
cur_is_Cr_or_Cb <= cur_is_Cr_or_Cb ^ 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data =
~stream_out_valid | (stream_out_ready & stream_out_valid);
assign converted_data[23:16] = (cur_is_Cr_or_Cb) ? data[15: 8] : saved_CrCb;
assign converted_data[15: 8] = (cur_is_Cr_or_Cb) ? saved_CrCb : data[15: 8];
assign converted_data[ 7: 0] = data[ 7: 0];
assign converted_startofpacket = startofpacket;
assign converted_endofpacket = endofpacket;
assign converted_empty = empty;
assign converted_valid = valid;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; int d[10010][8]; int d1[8]; int p[3][10010]; int n; vector<int> var; int MD = 1000000007; int mod(long long a) { if (a % MD < 0) return a % MD + MD; else return a % MD; } void put(int i, int prof) { if (prof == 0) { d[i + 1][7] = mod(d[i + 1][7] + d[i][0]); d[i + 1][1] = mod(d[i + 1][1] + d[i][0]); d[i + 1][4] = mod(d[i + 1][4] + d[i][0]); } else if (prof == 1) { d[i + 1][0] = mod(d[i + 1][0] + d[i][1]); d[i + 1][6] = mod(d[i + 1][6] + d[i][1]); } else if (prof == 2) { d[i + 1][5] = mod(d[i + 1][5] + d[i][2]); } else if (prof == 3) { d[i + 1][4] = mod(d[i + 1][4] + d[i][3]); } else if (prof == 4) { d[i + 1][0] = mod(d[i + 1][0] + d[i][4]); d[i + 1][3] = mod(d[i + 1][3] + d[i][4]); } else if (prof == 5) { d[i + 1][2] = mod(d[i + 1][2] + d[i][5]); } else if (prof == 6) { d[i + 1][1] = mod(d[i + 1][1] + d[i][6]); } else if (prof == 7) { d[i + 1][0] = mod(d[i + 1][0] + d[i][7]); } } int dyn() { memset(d, 0, sizeof(d)); d[0][0] = 1; for (int i = 0; i < n; i++) { int prof = p[0][i] + p[1][i] * 2 + p[2][i] * 4; if (prof != 0) { memset(d1, 0, sizeof(d1)); for (int j = 0; j < 8; j++) { if ((j & prof) != 0) d[i][j] = 0; d1[j | prof] = mod(d1[j | prof] + d[i][j]); } for (int j = 0; j < 8; j++) { d[i][j] = d1[j]; } } for (int j = 0; j < 8; j++) { if (d[i][j] != 0) put(i, j); } } return d[n][0]; } bool bit(int v, int i) { return (v >> i) & 1; } int incl() { int ans = 0; int sz = var.size() / 4; int powsz = 1 << sz; for (int v = 1; v < powsz; v++) { int sgn = -1; int cnt = 0; for (int i = 0; i < sz; i++) { if (bit(v, i)) { p[var[i * 4]][var[i * 4 + 1]] = 1; p[var[i * 4 + 2]][var[i * 4 + 3]] = 1; sgn *= -1; cnt++; } } ans = mod(ans + sgn * dyn()); for (int i = 0; i < sz; i++) { if (bit(v, i)) { p[var[i * 4]][var[i * 4 + 1]] = 0; p[var[i * 4 + 2]][var[i * 4 + 3]] = 0; } } } return ans; } int main() { cin >> n; int inpi, inpj; char c; for (int j = 0; j < 3; j++) { for (int i = 0; i < n; i++) { cin >> c; if (c == . ) p[j][i] = 0; if (c == X ) p[j][i] = 1; if (c == O ) { p[j][i] = 1; inpi = j; inpj = i; } } } if (inpi == 1) { if (inpj > 1 && p[inpi][inpj - 2] != 1) { var.push_back(inpi); var.push_back(inpj - 1); var.push_back(inpi); var.push_back(inpj - 2); } if (inpj < n - 2 && p[inpi][inpj + 2] != 1) { var.push_back(inpi); var.push_back(inpj + 1); var.push_back(inpi); var.push_back(inpj + 2); } cout << incl(); } else { int opp = 2 - inpi; if (inpj > 1 && p[inpi][inpj - 2] != 1) { var.push_back(inpi); var.push_back(inpj - 1); var.push_back(inpi); var.push_back(inpj - 2); } if (inpj < n - 2 && p[inpi][inpj + 2] != 1) { var.push_back(inpi); var.push_back(inpj + 1); var.push_back(inpi); var.push_back(inpj + 2); } if (p[opp][inpj] != 1) { var.push_back(1); var.push_back(inpj); var.push_back(opp); var.push_back(inpj); } cout << incl(); } return 0; }
|
// ECE 429
module memory(clock, address, data_in, access_size, rw, enable, busy, data_out);
parameter data_width = 32;
parameter address_width = 32;
parameter depth = ;
// -1 for 0 based indexed
parameter bytes_in_word = 4-1;
parameter bits_in_bytes = 8-1;
parameter BYTE = 8;
parameter start_addr = 32'h80020000;
// Input Ports
input clock;
input [address_width-1:0] address;
input [data_width-1:0] data_in;
input [1:0] access_size;
input rw;
input enable;
// Output Ports
//FIXME: change to output port.
output reg busy;
output reg [data_width-1:0] data_out;
// Create a 1MB deep memory of 8-bits (1 byte) width
reg [7:0] mem[0:depth]; // should be [7:0] since its byte addressible memory
reg [7:0] data;
reg [7:0] byte[3:0];
reg [31:0] global_cur_addr;
reg [31:0] global_cur_addr_write;
reg [31:0] global_cur_addr_read;
integer cyc_ctr = 0;
integer cyc_ctr_write = 0;
integer i = 0;
integer words_written = 0;
integer words_read = 0;
integer write_total_words = 0;
integer read_total_words = 0;
integer fd;
integer status_read, status_write;
reg [31:0] fd_in;
reg [31:0] str;
always @(posedge clock, data_in, rw)
begin : WRITE
// rw = 1
if ((!rw && enable)) begin
// busy is to be asserted in case of burst transactions.
if(write_total_words > 1) begin
busy = 1;
end
// this will give busy an initial value.
// Note: This would also be set for burst transactions (which is fine).
else begin
busy = 0;
end
// 00: 1 word
if (access_size == 2'b0_0 ) begin
mem[address-start_addr+3] <= data_in[7:0];
mem[address-start_addr+2] <= data_in[15:8];
mem[address-start_addr+1] <= data_in[23:16];
mem[address-start_addr] <= data_in[31:24];
end
// 01: 4 words
else if (access_size == 2'b0_1) begin
write_total_words = 4;
// skip over the already written bytes
global_cur_addr_write = address-start_addr;
if (words_written < 4) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_written = 0;
end
end
// 10: 8 words
else if (access_size == 2'b1_0) begin
write_total_words = 8;
global_cur_addr_write = address-start_addr;
if (words_written < 8) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
else begin
words_written = 0;
end
end
// 11: 16 words
else if (access_size == 2'b1_1) begin
write_total_words = 16;
global_cur_addr_write = address-start_addr;
if (words_written < 16) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
else begin
words_written = 0;
end
end
end
end
/*
00: 1 word (4-bytes)
01: 4 words (16-bytes)
10: 8 words (32-bytes)
11: 16 words (64-bytes)
*/
always @(posedge clock, address, rw)
begin : READ
if ((rw && enable)) begin
// busy is to be asserted in case of burst transactions.
if(read_total_words > 1) begin
busy = 1;
end
// this will give busy an initial value.
// Note: This would also be set for burst transactions (which is fine).
else begin
busy = 0;
end
// 00: 1 word
if (access_size == 2'b0_0 ) begin
// read 4 bytes at max in 1 clock cycle.
//assign data_out = {mem[address-start_addr], mem[address-start_addr+1], mem[address-start_addr+2], mem[address-start_addr+3]};
data_out[7:0] <= mem[address-start_addr+3];
data_out[15:8] <= mem[address-start_addr+2];
data_out[23:16] <= mem[address-start_addr+1];
data_out[31:24] <= mem[address-start_addr];
end
// 01: 4 words
else if (access_size == 2'b0_1) begin
read_total_words = 4;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 4) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
end
// 10: 8 words
else if (access_size == 2'b1_0) begin
read_total_words = 8;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 8) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
// 11: 16 words
end else if (access_size == 2'b1_1) begin
read_total_words = 16;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 16) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
end
end
end
endmodule
|
`timescale 1ns/10ps
module system_pll_0(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("100.000000 MHz"),
.phase_shift1("8250 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int m, n; string bs[50]; long long component[1000]; long long combo[1001][1001]; long long pseudopart[1001]; bool visited[1000]; int main() { cin >> m >> n; for (int i = 0; i < n; i++) cin >> bs[i]; for (int i = 0; i < m; i++) for (int j = 0; j < n; j++) { component[i] *= 2LL; component[i] += (long long)((int)bs[j][i] - (int) 0 ); } combo[0][0] = 1; for (int i = 1; i < 1001; i++) for (int j = 0; j <= i; j++) { if (j == 0 || j == i) combo[i][j] = 1; else combo[i][j] = combo[i - 1][j] + combo[i - 1][j - 1]; combo[i][j] %= 1000000007; } pseudopart[0] = 1; pseudopart[1] = 1; for (int i = 2; i <= m; i++) { for (int j = 0; j < i; j++) { pseudopart[i] += combo[i - 1][j] * pseudopart[i - 1 - j]; pseudopart[i] %= 1000000007; } } long long ans = 1; for (int i = 0; i < m; i++) { if (visited[i]) continue; long long temp = 0; for (int j = 0; j < m; j++) if (component[j] == component[i]) { visited[j] = true; temp++; } ans *= pseudopart[temp]; ans %= 1000000007; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { string Scale, left, right, rest_elements; int Slash; cin >> Scale; Slash = Scale.find( | ); left = Scale.substr(0, Slash); right = Scale.substr(Slash + 1, Scale.size()); cin >> rest_elements; for (auto i : rest_elements) if (left.size() <= right.size()) left += i; else right += i; cout << (left.size() == right.size() ? left + | + right : Impossible ) << endl; return 0; }
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 18220 $
// $Date: 2009-10-27 15:19:11 +0000 (Tue, 27 Oct 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module RevertReg(CLK, Q_OUT, D_IN, EN);
parameter width = 1;
parameter init = { width {1'b0} } ;
input CLK;
input EN;
input [width - 1 : 0] D_IN;
output [width - 1 : 0] Q_OUT;
assign Q_OUT = init;
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_green_leds (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; namespace Base { const int inf = 0x3f3f3f3f, INF = 0x7fffffff; const long long infll = 0x3f3f3f3f3f3f3f3fll, INFll = 0x7fffffffffffffffll; template <typename T> void read(T &x) { x = 0; int fh = 1; double num = 1.0; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) fh = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } if (ch == . ) { ch = getchar(); while (isdigit(ch)) { num /= 10; x = x + num * (ch - 0 ); ch = getchar(); } } x = x * fh; } template <typename T> void chmax(T &x, T y) { x = x < y ? y : x; } template <typename T> void chmin(T &x, T y) { x = x > y ? y : x; } } // namespace Base using namespace Base; const int N = 100010; int n, a[N], q[N], use[N], pre[N], prel[N], prem[N], prer[N], num, l[N], m[N], r[N]; void force(int *a, int n, int id) { int tmp = 0; for (int i = 1; i <= n; i++) tmp = tmp + (a[i] << (i - 1)); int pl = 1, pr = 1; q[1] = 0; use[0] = true; while (pl <= pr) { int x = q[pl++]; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) { int k = j + (j - i); if (k > n) continue; int nxt = x ^ (1 << (i - 1)) ^ (1 << (j - 1)) ^ (1 << (k - 1)); if (use[nxt] == false) { q[++pr] = nxt; use[nxt] = true; pre[nxt] = x; prel[nxt] = i; prem[nxt] = j, prer[nxt] = k; } } } if (use[tmp] == false) { printf( NO n ); exit(0); } printf( YES n ); while (tmp != 0) { num++; l[num] = prel[tmp] + id, m[num] = prem[tmp] + id, r[num] = prer[tmp] + id; tmp = pre[tmp]; } printf( %d n , num); for (int i = 1; i <= num; i++) printf( %d %d %d n , l[i], m[i], r[i]); } void doit(int nl, int nm, int nr) { num++; l[num] = nl, m[num] = nm, r[num] = nr; a[nl] ^= 1, a[nm] ^= 1, a[nr] ^= 1; } int main() { read(n); for (int i = 1; i <= n; i++) read(a[i]); int pl = 1, pr = n; while (pr - pl + 1 > 12) { if (a[pl] == 0) { pl++; continue; } if (a[pr] == 0) { pr--; continue; } if (a[pl] + a[pl + 1] + a[pl + 2] == 3) { doit(pl, pl + 1, pl + 2); continue; } if (a[pr] + a[pr - 1] + a[pr - 2] == 3) { doit(pr - 2, pr - 1, pr); continue; } if ((pr - pl) % 2 == 0) { doit(pl, (pl + pr) / 2, pr); continue; } if (a[pl] != a[pl + 1] && a[pl] == a[pl + 2]) { doit(pl, pl + 2, pl + 4); continue; } if (a[pr] != a[pr - 1] && a[pr] == a[pr - 2]) { doit(pr - 4, pr - 2, pr); continue; } doit(pl, (pl + pr - 1) / 2, pr - 1); } if (n <= 12) force(a, n, 0); else force(a + pl - 1, 12, pl - 1); return 0; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:frequency_analyzer_manager:1.0
// IP Revision: 1
(* X_CORE_INFO = "frequency_analyzer_manager,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_frequency_analyzer_manager_1_0,frequency_analyzer_manager,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_frequency_analyzer_manager_1_0,frequency_analyzer_manager,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=frequency_analyzer_manager,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S00_AXI_DATA_WIDTH=32,C_S00_AXI_ADDR_WIDTH=4}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_frequency_analyzer_manager_1_0 (
data,
pixel_clock,
start,
stop,
clear,
irq,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready
);
input wire [7 : 0] data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 pixel_clock CLK" *)
input wire pixel_clock;
input wire start;
input wire stop;
input wire clear;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 irq INTERRUPT" *)
output wire irq;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
input wire s00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [3 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [3 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
frequency_analyzer_manager #(
.C_S00_AXI_DATA_WIDTH(32),
.C_S00_AXI_ADDR_WIDTH(4)
) inst (
.data(data),
.pixel_clock(pixel_clock),
.start(start),
.stop(stop),
.clear(clear),
.irq(irq),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : CPU Write SM
// File : cpu_wr.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// The function of this module is to take the hostdata
// from the graphic module as g_graph_data[31:0] and is
// latched into a 32 x 8 deep fifo before shifting out
// on to the memory data bus m_t_mem_data [31:0].
//
// The address & the planes to the memory is also latched
// into the fifo along with the data and is shifted out
// to the memory to write that particular data.
//
// A cpu write statemachine (cpu_wr_sm) is instansiated
// in this module. The cpu-write state machine generates
// cpu-write request (cpu_wr_req) to the arbitration
// module to obtain cpu write cycle. The state machine
// also generates svga_req to the memory block and once
// the acknowledge is obtained the data is put on the
// memory bus along with the corresponding address and
// the write-enables.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module cpu_wr
(
input cpu_rd_gnt,
input hreset_n,
input cpu_wr_gnt,
input crt_req,
input svga_ack,
input mem_clk,
input g_memwr,
input [19:0] val_mrdwr_addr,
input [7:0] fin_plane_sel,
input [31:0] g_graph_data_out,
output cpu_wr_req,
output cpu_wr_svga_req,
output [7:0] cpuwr_mwe_n,
output [22:3] cpuwr_mem_addr,
output m_cpu_ff_full,
output cpu_mem_wr,
output enwr_cpu_ad_da_pl,
output [31:0] cpuwr_mem_data_out,
output cpu_arb_wr
);
reg [2:0] cntrd_out;
reg [2:0] cntwr_out;
reg [2:0] ffstat_out;
reg [22:3] int_wrmem_add;
wire [59:0] cpu_fifo_data_out;
// reg [59:0] fifo_store[7:0];
reg [7:0] int_m_t_mwe_n;
reg [31:0] int1_m_t_mem_data;
wire [2:0] next_read;
wire [31:0] cpuwr_data_out;
wire [7:0] plane_sel;
wire [22:3] cpuwr_add_out;
wire [59:0] cpu_fifo_wr_in;
wire [22:3] cpuwr_conv22;
wire cpu_fifo_read;
wire ff_wr_pend;
wire int_cpu_fifo_rd;
wire cpu_ff_empty;
wire cpu_ff_full_by1;
wire g_memwr_cwr;
wire [3:0] nc4_0;
assign g_memwr_cwr = g_memwr & ~cpu_rd_gnt;
assign cpuwr_mem_addr = cpuwr_add_out[20:3];
assign cpuwr_mwe_n = ~plane_sel;
assign cpuwr_mem_data_out = cpu_fifo_data_out[31:0];
//
// muxing address data for high and low data
//
assign cpuwr_conv22 = {1'b0, cpuwr_add_out[21:3]};
//
// Instantiating a 60 x 8 FIFO
//
assign cpu_fifo_wr_in[59:0] = {fin_plane_sel[7:0], val_mrdwr_addr[19:0],
g_graph_data_out[31:0]};
assign cpuwr_data_out[31:0] = cpu_fifo_data_out[31:0];
assign cpuwr_add_out[22:3] = cpu_fifo_data_out[51:32];
assign plane_sel[7:0] = cpu_fifo_data_out[59:52];
ram_64x32_2p u_cpu_fifo_data
(
.clock (mem_clk),
.wren (g_memwr_cwr),
.wraddress ({2'b00, cntwr_out}),
.rdaddress ({2'b00, next_read}),
.data ({4'b0000, cpu_fifo_wr_in}),
.q ({nc4_0, cpu_fifo_data_out})
);
//
// In the following always statements all the variables are not included
// because of the timing of the counters.
//
assign next_read = cntrd_out + 3'b001;
always @ (posedge mem_clk or negedge hreset_n )
if (~hreset_n) cntrd_out <= 3'b111;
else if (cpu_fifo_read) cntrd_out <= next_read[2:0];
always @ (posedge mem_clk or negedge hreset_n )
if (~hreset_n) cntwr_out <= 3'b0;
else if (g_memwr_cwr) cntwr_out <= cntwr_out + 1;
always @ (posedge mem_clk or negedge hreset_n )
if (~hreset_n) ffstat_out <= 3'b0;
else if (g_memwr_cwr & ~cpu_fifo_read) ffstat_out <= ffstat_out + 1'b1;
else if (cpu_fifo_read & ~g_memwr_cwr) ffstat_out <= ffstat_out - 1'b1;
assign cpu_ff_empty = ~|ffstat_out;
assign ff_wr_pend = ~cpu_ff_empty;
assign m_cpu_ff_full = &ffstat_out;
assign cpu_ff_full_by1 = (ffstat_out == 3'h6);
//
// Instantiating CPUWR STATE MACHINE
//
sm_cpuwr CPUWR_SM
(
.ff_wr_pend (ff_wr_pend),
.hreset_n (hreset_n),
.cpu_wr_gnt (cpu_wr_gnt),
.crt_req (crt_req),
.svga_ack (svga_ack),
.mem_clk (mem_clk),
.cpu_wr_req (cpu_wr_req),
.cpu_wr_svga_req (cpu_wr_svga_req),
.enwr_cpu_ad_da_pl (enwr_cpu_ad_da_pl),
.cpu_fifo_read (cpu_fifo_read),
.int_cpu_fifo_rd (int_cpu_fifo_rd),
.cpu_mem_wr (cpu_mem_wr),
.cpu_arb_wr (cpu_arb_wr)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; set<int> S[100001]; int main() { scanf( %d , &n); set<int> s; int x, k; for (int i = 0; i < n; ++i) { scanf( %d%d , &x, &k); if (x && S[k].find(x - 1) == S[k].end()) { puts( NO ); return 0; } S[k].insert(x); } puts( YES ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A311OI_PP_BLACKBOX_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SDFRBP_FUNCTIONAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_pg/sky130_fd_sc_hs__u_df_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrbp (
VPWR ,
VGND ,
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_r_pg `UNIT_DELAY u_df_p_r_pg0 (buf_Q , mux_out, CLK, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRBP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; struct Number { array<int, 4> powers = {{0, 0, 0, 0}}; Number() {} Number(int a) { if (a != -1) powers[a]++; } long double log_value() const { if (powers[0] > 0) return -INFINITY; return powers[2] * log(2L) + powers[3] * log(3L); } int mod() const { long long result = 1; for (int i = 0; i < 4; i++) for (int j = 0; j < powers[i]; j++) result = (result * i) % (int)(1e9 + 7); return result; } bool is_zero() const { return powers[0] > 0; } }; bool operator<(const Number& a, const Number& b) { return a.log_value() < b.log_value(); } Number operator*(const Number& a, const Number& b) { Number result; for (int i = 0; i < 4; i++) result.powers[i] = a.powers[i] + b.powers[i]; return result; } Number operator/(const Number& a, const Number& b) { Number result; for (int i = 0; i < 4; i++) result.powers[i] = a.powers[i] - b.powers[i]; return result; } template <typename T> using Matrix = vector<vector<T>>; template <typename T> Matrix<T> matrix(int R, int C, T x = T()) { return Matrix<T>(R, vector<T>(C, x)); } struct RangeProduct { int N; Matrix<int> grid; Matrix<Number> hprod; Matrix<Number> vprod; bool valid(int r, int c) { return 0 <= r && r < N && 0 <= c && c < N; } RangeProduct(int N, Matrix<int> grid) : N(N), grid(grid) { hprod = matrix<Number>(N + 1, N + 1); vprod = matrix<Number>(N + 1, N + 1); for (int r = 0; r < N; r++) for (int c = 0; c < N; c++) { hprod[r][c + 1] = hprod[r][c] * grid[r][c]; vprod[r + 1][c] = vprod[r][c] * grid[r][c]; } } Number hquery(int r, int c, int radius) { int c1 = c - radius, c2 = c + radius; if (!valid(r, c1) || !valid(r, c2)) return 0; return hprod[r][c2 + 1] / hprod[r][c1]; } Number vquery(int r, int c, int radius) { int r1 = r - radius, r2 = r + radius; if (!valid(r1, c) || !valid(r2, c)) return 0; return vprod[r2 + 1][c] / vprod[r1][c]; } Number cross(int r, int c, int radius) { return hquery(r, c, radius) * vquery(r, c, radius) / grid[r][c]; } Number max_cross(int r, int c) { int a = 0, b = N; while (a < b) { int mid = (a + b + 1) / 2; if (cross(r, c, mid).is_zero()) b = mid - 1; else a = mid; } return cross(r, c, a); } }; Number solve(int N, Matrix<int> grid) { RangeProduct rp(N, grid); Number result(0); for (int r = 0; r < N; r++) for (int c = 0; c < N; c++) result = max(result, rp.max_cross(r, c)); return result; } Matrix<int> rotate(int N, const Matrix<int>& grid, int shift) { auto ngrid = matrix<int>(N, N); for (int r = 0; r < N; r++) for (int c = 0; c < N; c++) if ((r + c) % 2 == shift) ngrid[(r + c) / 2][(r - c + N) / 2] = grid[r][c]; return ngrid; } int main() { int N; cin >> N; auto grid = matrix<int>(N, N); for (int i = 0; i < N; i++) { string s; cin >> s; for (int j = 0; j < N; j++) grid[i][j] = s[j] - 0 ; } auto rgrid0 = rotate(N, grid, 0); auto rgrid1 = rotate(N, grid, 1); Number answer = max({solve(N, grid), solve(N, rgrid0), solve(N, rgrid1)}); cout << answer.mod() << endl; }
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, x, y, c1 = 0, c2 = 0, m; cin >> n; for (int i = 0; i < n; i++) { cin >> x >> y; if (x > 0) c1++; else c2++; } m = min(c1, c2); if (m <= 1) cout << YES << endl; else cout << NO << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 10, maxk = 1e6 + 10; int n, k, A[maxn], cnt[maxk], sum[maxk]; int32_t main() { scanf( %d%d , &n, &k); for (int i = int(0); i < int(n); i++) { scanf( %d , A + i); cnt[A[i]]++; } sort(A, A + n); for (int i = int(1); i < int(maxk); i++) { sum[i] = sum[i - 1] + cnt[i - 1]; } int g, c = n, ans = 0; for (g = 1; g < maxk; g++) { c = 0; for (int j = g; j < maxk; j += g) { c += sum[min(maxk - 1, j + min(k + 1, g))] - sum[j]; } if (c >= n) ans = g; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int store[20][1 << 20]; struct trie { int k; struct Node { Node* ch[2]; Node() { ch[0] = ch[1] = NULL; } }; Node* root; trie(int k) : k(k) { root = new Node(); } void insert(int x) { Node* cur = root; for (int i = k - 1; i >= 0; i--) { int side = x >> i & 1; if (!cur->ch[side]) cur->ch[side] = new Node(); cur = cur->ch[side]; } } void eval() { vector<int> ret(1 << k); for (int i = 0; i <= k; i++) fill(store[i], store[i] + (1 << k), 1 << 30); function<vector<pair<int, int> >(Node*, int)> dfs = [&](Node* node, int h) { if (!node) return vector<pair<int, int> >(); if (h == 0) { vector<pair<int, int> > ret = {{0, 0}}; return ret; } vector<pair<int, int> > A = dfs(node->ch[0], h - 1), B = dfs(node->ch[1], h - 1); vector<pair<int, int> > ret(1 << h); for (int x = 0; x < (1 << h); x++) { int add = 1 << (h - 1); int rem = x & (add - 1); if (x >> (h - 1) & 1) { ret[x].first = node->ch[1] ? B[rem].first : A[rem].first + add; ret[x].second = node->ch[0] ? A[rem].second + add : B[rem].second; } else { ret[x].first = node->ch[0] ? A[rem].first : B[rem].first + add; ret[x].second = node->ch[1] ? B[rem].second + add : A[rem].second; } if (!A.empty() && !B.empty()) { if (x >> (h - 1) & 1) store[h][x] = min(store[h][x], A[rem].first + add - B[rem].second); else store[h][x] = min(store[h][x], B[rem].first + add - A[rem].second); } assert(max(ret[x].first, ret[x].second) < (1 << h) && min(ret[x].first, ret[x].second) >= 0); } return ret; }; dfs(root, k); } }; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; trie T(k); for (int i = 0; i < n; i++) { int x; cin >> x; T.insert(x); } T.eval(); for (int x = 0; x < (1 << k); x++) { int ans = 1 << 30; for (int h = k; h; h--) { ans = min(ans, store[h][x & ((1 << h) - 1)]); } cout << ans << ; } cout << n ; }
|
#include <bits/stdc++.h> using namespace std; int a, b, c; int f[2001 * 2001]; int _GCD[2001][2001]; int GCD(int a, int b) { if (_GCD[a][b]) return _GCD[a][b]; if (!b) return a; return _GCD[a][b] = GCD(b, a % b); } int phi(int x) { if (x & 1) return -1; return 1; } int main() { cin >> a >> b >> c; for (int j = (1); j <= (b); j++) for (int k = (1); k <= (c); k++) if (GCD(j, k) == 1) f[j * k] += (b / j) * (c / k); for (int x = (1); x <= (b * c); x++) for (int y = 2 * x; y <= b * c; y += x) f[x] += f[y]; int ans = 0; for (int i = (1); i <= (a); i++) { vector<int> L; int x, y; for (x = i, y = 2; y * y <= x; y++) if (x % y == 0) { L.push_back(y); while (x % y == 0) x /= y; } if (x != 1) L.push_back(x); for (int s = (0); s <= ((1 << int((L).size())) - 1); s++) { int x = 1, cnt = 0; for (int j = (0); j <= (int((L).size()) - 1); j++) if ((s >> j) & 1) cnt++, x *= L[j]; ans += phi(cnt) * f[x] * (a / i); } } cout << (ans % (1 << 30) + (1 << 30)) % (1 << 30); return 0; }
|
`timescale 1ns / 1ps
`include "collaterals.v"
module io
(
input wire Clock,
input wire Reset,
input wire [5:0] iP, //Pressed button
output wire [5:0] oP, //[5:4] most be triggered before [3:0]
output wire oIE //Enable interruption $FFFF
);
wire [5:0] wiPlast;
wire [5:0] woPlast;
wire [5:0] wXnorAresult;
wire [5:0] wXnorBresult;
wire [5:0] wXnorCresult;
wire [5:0] wMuxAresult;
wire [5:0] wMuxBresult;
reg [5:0] rP;
assign oP = rP;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 6 ) FFD_oP
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(oP),
.Q(woPlast)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 6 ) FFD2_iP
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(iP),
.Q(wiPlast)
);
XNOR # ( 6 ) XOR1
(
.inA(iP),
.inB(woPlast),
.out(wXnorAresult)
);
XNOR # ( 6 ) XNOR2
(
.inA(iP),
.inB(wiPlast),
.out(wXnorBresult)
);
MUX2 # ( 6 ) MUX1
(
.select(&iP),
.inA(wXnorAresult),
.inB(iP),
.out(wMuxAresult)
);
// assign wMuxBresult = (woPlast == iP) ? iP : wMuxAresult;
MUX2 # ( 6 ) MUX2
(
.select(&wXnorAresult),
.inA(wMuxAresult),
.inB(iP),
.out(wMuxBresult)
);
// assign oIE = (&oP == 0) ? 1 : 0;
MUX2 # ( 1 ) MUX3
(
.select(&oP),
.inA(1),
.inB(0),
.out(oIE)
);
always @ ( * )
begin
case (wMuxBresult)
// one button is pressed. Or two buttons pressed with diferrent ending and type. Ex. Left + Start. Or juest A.
6'b101110, 6'b101101, 6'b101011, 6'b100111, 6'b011110, 6'b011101, 6'b011011, 6'b010111:
begin
`ifdef JOYPAD_TOGGLE_PRESSED_KEY
rP <= wMuxBresult;
`else
if (&wXnorBresult == 0)
rP <= wMuxBresult;
else
rP <= woPlast;
`endif
end
// two buttons pressed with the same ending. Ex A + Right (10 1110 + 01 1110)
6'b011111,6'b101111:
begin
`ifdef JOYPAD_TOGGLE_PRESSED_KEY
rP <= wMuxBresult;
`else
if (&wXnorBresult == 0)
rP <= {wMuxBresult[5:4],woPlast[3:0]};
else
rP <= woPlast;
`endif
end
// two buttons pressed with the same type. Ex. Up + Down. A + B
6'b111110,6'b111101,6'b111011,6'b110111:
begin
`ifdef JOYPAD_TOGGLE_PRESSED_KEY
rP <= wMuxBresult;
`else
if (&wXnorBresult == 0)
rP <= {woPlast[5:4],wMuxBresult[3:0]};
else
rP <= woPlast;
`endif
end
default:
begin
$display("Default %dns",$time);
rP <= 6'b111111;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 501; const long long DIM = 3e5 + 1; int in, n, t, a[DIM]; int main() { ios_base::sync_with_stdio; cin.tie(0); cout.tie(0); in = scanf( %d , &t); while (t--) { in = scanf( %d , &n); set<int> s; for (int i = 1; i <= n; i++) { in = scanf( %d , &a[i]); s.insert(a[i]); } if (s.size() == 1) printf( -1 n ); else { auto it = s.end(); it--; for (int i = 1; i <= n; i++) { if (a[i] == *it && ((i > 1 && a[i - 1] != *it) || (i < n && a[i + 1] != *it))) { printf( %d n , i); break; } } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100007; int n, m; long long h[maxn], p[maxn]; bool check(long long time) { int x = 1, old_x; for (int i = 1, _c = n; i <= _c; i++) { if (x > m) return 1; if (p[x] <= h[i]) { if (h[i] - p[x] > time) return 0; old_x = x; while (x <= m && h[i] >= p[x]) x++; if (old_x != x) { while (x <= m && p[x] - p[old_x] + min(p[x] - h[i], h[i] - p[old_x]) <= time) x++; } } else { while (x <= m && p[x] - h[i] <= time) x++; } } return (x > m); } int main() { scanf( %d%d , &n, &m); for (int i = 1, _c = n; i <= _c; i++) scanf( %I64d , &h[i]); for (int i = 1, _c = m; i <= _c; i++) scanf( %I64d , &p[i]); long long l, r, mid, res; r = res = 20000000000ll; l = 0; while (l <= r) { mid = (l + r) / 2; if (check(mid)) { res = mid; r = mid - 1; } else l = mid + 1; } cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> num; int n; cin >> n; int k = -1, tmp; while (n > 0) { tmp = n % 10; num.push_back(tmp); if (tmp > k) k = tmp; n /= 10; } cout << k << endl; bool flag = true; bool main = true; while (true) { flag = false; main = false; for (int i = num.size() - 1; i > -1; i--) { if (num[i] > 0) { cout << 1; flag = true; main = true; num[i]--; } else if ((num[i] == 0) && (main)) cout << 0; } if (flag == false) break; cout << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, max = 0; cin >> n; int arr[n]; long long ans = 0; for (int i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] > max) { max = arr[i]; } } for (int i = 0; i < n; i++) { ans += max - arr[i]; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int xa, ya, xb, yb, n; cin >> xa >> ya >> xb >> yb >> n; vector<int> X(n), Y(n), R(n); for (int i = 0; i < n; ++i) cin >> X[i] >> Y[i] >> R[i]; if (xa > xb) swap(xa, xb); if (ya > yb) swap(ya, yb); int ans = 0; for (int i = xa; i <= xb; i++) { bool flag = false; for (int j = 0; j < n; ++j) { int d = (X[j] - i) * (X[j] - i) + (Y[j] - ya) * (Y[j] - ya); if (d <= R[j] * R[j]) flag = true; } ans += !flag; flag = false; for (int j = 0; j < n; ++j) { int d = (X[j] - i) * (X[j] - i) + (Y[j] - yb) * (Y[j] - yb); if (d <= R[j] * R[j]) flag = true; } ans += !flag; } for (int i = ya + 1; i < yb; ++i) { bool flag = false; for (int j = 0; j < n; ++j) { int d = (X[j] - xa) * (X[j] - xa) + (Y[j] - i) * (Y[j] - i); if (d <= R[j] * R[j]) flag = true; } ans += !flag; flag = false; for (int j = 0; j < n; ++j) { int d = (X[j] - xb) * (X[j] - xb) + (Y[j] - i) * (Y[j] - i); if (d <= R[j] * R[j]) flag = true; } ans += !flag; } cout << ans << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__OR4B_BEHAVIORAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
// Local signals
wire DN not0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_BEHAVIORAL_V
|
#include <bits/stdc++.h> const int MAXN = 50 + 10; bool row[MAXN]; bool column[MAXN]; int main() { int n, x, y; std::cin >> n; for (int i = 0; i <= n * n; i++) { std::cin >> x >> y; if (row[x - 1] == false && column[y - 1] == false) { row[x - 1] = true; column[y - 1] = true; std::cout << i + 1 << ; } } return 0; }
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: write_data_path.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This is top level of write path .
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module write_data_path #(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter ADDR_WIDTH = 32,
parameter START_ADDR = 32'h00000000,
parameter BL_WIDTH = 6,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter EYE_TEST = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
output cmd_rdy_o,
input cmd_valid_i,
input cmd_validB_i,
input cmd_validC_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input mode_load_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
// input [5:0] port_data_counts_i,// connect to data port fifo counts
input data_rdy_i,
output data_valid_o,
output last_word_wr_o,
output [DWIDTH-1:0] data_o,
output [(DWIDTH/8) - 1:0] data_mask_o,
output data_wr_end_o
);
wire data_valid;
reg cmd_rdy;
assign data_valid_o = data_valid;// & data_rdy_i;
wr_data_gen #(
.TCQ (TCQ),
.FAMILY (FAMILY),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_BURST_LEN (MEM_BURST_LEN),
.BL_WIDTH (BL_WIDTH),
.START_ADDR (START_ADDR),
.nCK_PER_CLK (nCK_PER_CLK),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
wr_data_gen(
.clk_i (clk_i ),
.rst_i (rst_i[9:5]),
.prbs_fseed_i (prbs_fseed_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done_i),
.data_mode_i (data_mode_i ),
.cmd_rdy_o (cmd_rdy_o ),
.cmd_valid_i (cmd_valid_i ),
.cmd_validB_i (cmd_validB_i ),
.cmd_validC_i (cmd_validC_i ),
.last_word_o (last_word_wr_o ),
// .port_data_counts_i (port_data_counts_i),
// .m_addr_i (m_addr_i ),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (addr_i ),
.bl_i (bl_i ),
.data_rdy_i (data_rdy_i ),
.data_valid_o ( data_valid ),
.data_o (data_o ),
.data_wr_end_o (data_wr_end_o),
.data_mask_o (data_mask_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int TOUR = 1 << 18, MOD = 1e9 + 7; int Add(int a, int b) { a += b; if (a >= MOD) a -= MOD; return a; } int Sub(int a, int b) { a -= b; if (a < 0) a += MOD; return a; } int Mul(int a, int b) { return (int)(((long long)a * b) % MOD); } int Inverz(int x) { int ret = 1; for (int e = MOD - 2; e; e /= 2, x = Mul(x, x)) if (e & 1) ret = Mul(ret, x); return ret; } int Div(int a, int b) { return Mul(a, Inverz(b)); } struct node { int sum, mul, prop; }; struct tour { node t[2 * TOUR]; tour() { for (int i = 0; i < 2 * TOUR; i++) { t[i].sum = 0; t[i].mul = t[i].prop = 1; } } void propagiraj(int x) { for (int i = 2 * x; i <= 2 * x + 1; i++) { t[i].sum = Mul(t[i].sum, t[x].prop); t[i].mul = Mul(t[i].mul, t[x].prop); t[i].prop = Mul(t[i].prop, t[x].prop); } t[x].prop = 1; } void stavi_sum(int pos, int lo, int hi, int ind, int val) { if (lo >= ind + 1 || hi <= ind) return; if (lo == ind && hi == ind + 1) { t[pos].sum = Mul(t[pos].mul, val); return; } propagiraj(pos); stavi_sum(2 * pos + 0, lo, (lo + hi) / 2, ind, val); stavi_sum(2 * pos + 1, (lo + hi) / 2, hi, ind, val); t[pos].sum = Add(t[2 * pos].sum, t[2 * pos + 1].sum); } void stavi_sum(int pos, int val) { stavi_sum(1, 0, TOUR, pos, val); } void stavi_mul(int pos, int lo, int hi, int begin, int end, int val) { if (lo >= end || hi <= begin) return; if (lo >= begin && hi <= end) { t[pos].sum = Mul(t[pos].sum, val); t[pos].mul = Mul(t[pos].mul, val); t[pos].prop = Mul(t[pos].prop, val); return; } propagiraj(pos); stavi_mul(2 * pos + 0, lo, (lo + hi) / 2, begin, end, val); stavi_mul(2 * pos + 1, (lo + hi) / 2, hi, begin, end, val); t[pos].sum = Add(t[2 * pos].sum, t[2 * pos + 1].sum); } void stavi_mul(int begin, int end, int val) { stavi_mul(1, 0, TOUR, begin, end, val); } int query_sum(int pos, int lo, int hi, int begin, int end) { if (lo >= end || hi <= begin) return 0; if (lo >= begin && hi <= end) return t[pos].sum; propagiraj(pos); return Add(query_sum(2 * pos + 0, lo, (lo + hi) / 2, begin, end), query_sum(2 * pos + 1, (lo + hi) / 2, hi, begin, end)); } int query_sum(int begin, int end) { return query_sum(1, 0, TOUR, begin, end); } int query_mul(int pos, int lo, int hi, int ind) { if (lo >= ind + 1 || hi <= ind) return 0; if (lo == ind && hi == ind + 1) return t[pos].mul; propagiraj(pos); return Add(query_mul(2 * pos + 0, lo, (lo + hi) / 2, ind), query_mul(2 * pos + 1, (lo + hi) / 2, hi, ind)); } int query_mul(int ind) { return query_mul(1, 0, TOUR, ind); } } T; vector<int> V[TOUR]; pair<int, int> ev[TOUR]; int disc[TOUR], fin[TOUR], vr = 1; int pocval[TOUR], par[TOUR]; int brdjec[TOUR]; void Dfs(int node) { disc[node] = vr++; for (int i = 0; i < (int)V[node].size(); i++) Dfs(V[node][i]); fin[node] = vr; } void Dodaj(int node) { int p = par[node]; T.stavi_mul(disc[p], fin[p], Mul(Inverz(brdjec[p]), brdjec[p] + 1)); T.stavi_sum(disc[node], pocval[node]); brdjec[p]++; } int Query(int node) { int ret = T.query_sum(disc[node], fin[node]); if (node) ret = Div(ret, T.query_mul(disc[par[node]])); return ret; } int main() { int brq, brcv = 1; scanf( %d%d , &pocval[0], &brq); for (int i = 0; i < brq; i++) { int st; scanf( %d , &st); if (st == 2) { int tmp; scanf( %d , &tmp); tmp--; ev[i] = pair<int, int>(st, tmp); } else { scanf( %d%d , &par[brcv], &pocval[brcv]); par[brcv]--; V[par[brcv]].push_back(brcv); ev[i] = pair<int, int>(st, brcv++); } } Dfs(0); T.stavi_sum(disc[0], pocval[0]); for (int i = 0; i < brcv; i++) brdjec[i] = 1; for (int i = 0; i < brq; i++) { if (ev[i].first == 1) Dodaj(ev[i].second); else printf( %d n , Query(ev[i].second)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int v[1000005]; long long int l[1000005]; long long int r[1000005]; int main(void) { int n, m; int sum; scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d , &v[i]); } l[0] = 0; sum = 0; for (int i = 1; i < n; i++) { sum++; int trip = (sum + m - 1) / m; l[i] = l[i - 1] + 1LL * trip * (v[i] - v[i - 1]); } r[n - 1] = 0; sum = 0; for (int i = n - 2; i >= 0; i--) { sum++; int trip = (sum + m - 1) / m; r[i] = r[i + 1] + 1LL * trip * (v[i + 1] - v[i]); } long long int res = l[0] + r[0]; for (int i = 0; i < n; i++) { res = min(res, l[i] + r[i]); } printf( %lld n , 2 * res); return 0; }
|
/*
* Copyright (c) 2003 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
real x, y;
initial begin
$monitor("%t: x=%f, y=%f", $time, x, y);
#1 x = 1.0;
#1 y = 2.0;
#1 x = 1.5;
#1 y = 5.1;
#1 $finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int a[210000]; long long dp[210000][2]; const long long INF = 1LL << 60; int N; void init() { for (int i = 0; i < 210000; i++) for (int j = 0; j < 2; j++) dp[i][j] = INF; } long long solve(int x, bool t) { if (x <= 0 || x > N) return 0; if (x == 1) return -1; if (dp[x][t] == -INF) return dp[x][t] = -1; if (dp[x][t] != INF) return dp[x][t]; dp[x][t] = -INF; int i2 = x; if (t) i2 += a[x]; else i2 -= a[x]; long long r = solve(i2, !t); long long res; if (r == -1) res = -1; else res = a[x] + r; return dp[x][t] = res; } int main() { cin >> N; for (int i = 0; i < N - 1; i++) cin >> a[i + 2]; init(); for (int i = 1; i < N; i++) { long long r = solve(1 + i, 0); if (r != -1) r += i; cout << r << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SDFSTP_BEHAVIORAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_SYMBOL_V
`define SKY130_FD_SC_LP__O41A_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o41a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_SYMBOL_V
|
//wb_hs_demo.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:wb_hs_demo
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/11/13
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
module wb_hs_demo #(
parameter BUFFER_WIDTH = 10
)(
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int,
//output o_wbs_int
//Write Side
input i_write_enable,
input [63:0] i_write_addr,
input i_write_addr_inc,
input i_write_addr_dec,
output o_write_finished,
input [23:0] i_write_count,
input i_write_flush,
output [1:0] o_write_ready,
input [1:0] i_write_activate,
output [23:0] o_write_size,
input i_write_strobe,
input [31:0] i_write_data,
//Read Side
input i_read_enable,
input [63:0] i_read_addr,
input i_read_addr_inc,
input i_read_addr_dec,
output o_read_busy,
output o_read_error,
input [23:0] i_read_count,
input i_read_flush,
output o_read_ready,
input i_read_activate,
output [23:0] o_read_size,
output [31:0] o_read_data,
input i_read_strobe
);
//Local Parameters
localparam SLEEP_COUNT = 4;
//Local Registers/Wires
wire w_bram_wea;
reg [BUFFER_WIDTH - 1:0] r_bram_addr;
reg [31:0] r_bram_din;
wire [31:0] w_bram_dout;
reg [3:0] ram_sleep;
//Submodules
hs_demo #(
.BUFFER_WIDTH (BUFFER_WIDTH ),
.FIFO_WIDTH (7 )
) demo (
.clk (clk ),
.rst (rst ),
.o_idle (hs_demo_idle ),
//DEMO CODE START
.i_bram_wea (w_bram_wea ),
.i_bram_addr (r_bram_addr ),
.i_bram_din (r_bram_din ),
.o_bram_dout (w_bram_dout ),
//DEMO CODE END
//Write Side
.i_write_enable (i_write_enable ),
.i_write_addr (i_write_addr ),
.i_write_addr_inc (i_write_addr_inc ),
.i_write_addr_dec (i_write_addr_dec ),
.o_write_finished (o_write_finished ),
.i_write_count (i_write_count ),
.i_write_flush (i_write_flush ),
.o_write_ready (o_write_ready ),
.i_write_activate (i_write_activate ),
.o_write_size (o_write_size ),
.i_write_strobe (i_write_strobe ),
.i_write_data (i_write_data ),
//Read Side
.i_read_enable (i_read_enable ),
.i_read_addr (i_read_addr ),
.i_read_addr_inc (i_read_addr_inc ),
.i_read_addr_dec (i_read_addr_dec ),
.o_read_busy (o_read_busy ),
.o_read_error (o_read_error ),
.i_read_count (i_read_count ),
.i_read_flush (i_read_flush ),
.o_read_ready (o_read_ready ),
.i_read_activate (i_read_activate ),
.o_read_size (o_read_size ),
.o_read_data (o_read_data ),
.i_read_strobe (i_read_strobe )
);
//Asynchronous Logic
assign w_bram_wea = i_wbs_we;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
//Ram Specific
ram_sleep <= 0;
r_bram_addr <= 0;
r_bram_din <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
ram_sleep <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
r_bram_addr <= i_wbs_adr[BUFFER_WIDTH - 1:0];
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
r_bram_din <= i_wbs_dat;
end
else begin
//read request
o_wbs_dat <= w_bram_dout;
end
if (ram_sleep < SLEEP_COUNT) begin
ram_sleep <= ram_sleep + 1;
end
else begin
o_wbs_ack <= 1;
end
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDLCLKP_2_V
`define SKY130_FD_SC_HDLL__SDLCLKP_2_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdlclkp_2 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdlclkp_2 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDLCLKP_2_V
|
module test_bench(clk, rst);
input clk;
input rst;
wire [31:0] wire_39069600;
wire wire_39069600_stb;
wire wire_39069600_ack;
wire [31:0] wire_39795024;
wire wire_39795024_stb;
wire wire_39795024_ack;
wire [31:0] wire_39795168;
wire wire_39795168_stb;
wire wire_39795168_ack;
file_reader_a file_reader_a_39796104(
.clk(clk),
.rst(rst),
.output_z(wire_39069600),
.output_z_stb(wire_39069600_stb),
.output_z_ack(wire_39069600_ack));
file_reader_b file_reader_b_39759816(
.clk(clk),
.rst(rst),
.output_z(wire_39795024),
.output_z_stb(wire_39795024_stb),
.output_z_ack(wire_39795024_ack));
file_writer file_writer_39028208(
.clk(clk),
.rst(rst),
.input_a(wire_39795168),
.input_a_stb(wire_39795168_stb),
.input_a_ack(wire_39795168_ack));
multiplier multiplier_39759952(
.clk(clk),
.rst(rst),
.input_a(wire_39069600),
.input_a_stb(wire_39069600_stb),
.input_a_ack(wire_39069600_ack),
.input_b(wire_39795024),
.input_b_stb(wire_39795024_stb),
.input_b_ack(wire_39795024_ack),
.output_z(wire_39795168),
.output_z_stb(wire_39795168_stb),
.output_z_ack(wire_39795168_ack));
endmodule
|
// **************************************************************************
// $Header: /var/lib/cvs/dncvs/FPGA/dini/misc/resync.v,v 1.7 2015/04/07 22:03:42 bpoladian Exp $
// **************************************************************************
// $Log: resync.v,v $
// Revision 1.7 2015/04/07 22:03:42 bpoladian
// Only stop simulation on first warning.
//
// Revision 1.6 2015/04/06 23:58:10 bpoladian
// Resync reset to read clock domain.
//
// Revision 1.5 2013/05/20 17:39:36 claudiug
// added ALLOW_FAST_WRITE_PULSE parameter, disabled by default. Should not change old behavior.
//
// Revision 1.4 2013/03/07 23:10:37 bpoladian
// Fixed typo.
//
// Revision 1.3 2013/03/07 23:07:10 bpoladian
// Added simulation error about asserting wr_pulse too often.
//
// Revision 1.2 2010/11/17 20:41:05 bpoladian
// Syntax fix.
//
// Revision 1.1 2010/11/17 20:03:42 bpoladian
// Initial revision.
//
//
// Description:
// Transfers a group of signals from one clock domain into another.
// The transfer operation is triggered by a "wr_pulse", and data is
// valid on the other side when "rd_pulse" goes active.
// **************************************************************************
`ifdef INCL_RESYNC
`else
`define INCL_RESYNC
module resync #(
parameter DATA_SIZE = 32,
parameter ALLOW_FAST_WRITE_PULSE = 0
)(
input rst,
input wr_clk,
input wr_pulse,
input [DATA_SIZE-1:0] wr_data,
input rd_clk,
output reg rd_pulse,
output reg [DATA_SIZE-1:0] rd_data
);
// **********************************************************************
// REG AND WIRE DECLARATIONS
// **********************************************************************
reg [DATA_SIZE-1:0] data_wrclk;
reg toggle_wr;
reg toggle_return_wr_meta;
reg toggle_return_wr0;
reg toggle_rd_meta;
reg toggle_rd0;
reg toggle_rd1;
// **********************************************************************
// WRITE CLOCK DOMAIN DATA CAPTURE
// **********************************************************************
// synthesis translate_off
reg stop_once;
initial begin
stop_once = 0;
end
// synthesis translate_on
always @(posedge wr_clk or posedge rst) begin
if (rst) begin
toggle_wr <= 1'b0;
toggle_return_wr_meta <= 1'b0;
toggle_return_wr0 <= 1'b0;
data_wrclk[DATA_SIZE-1:0] <= 'h0;
end else begin
toggle_wr <= ALLOW_FAST_WRITE_PULSE ? toggle_wr ^ (wr_pulse & (toggle_wr ^ ~toggle_return_wr0)) : toggle_wr ^ wr_pulse;
toggle_return_wr_meta <= toggle_rd0;
toggle_return_wr0 <= toggle_return_wr_meta;
if (wr_pulse) begin
data_wrclk[DATA_SIZE-1:0] <= wr_data[DATA_SIZE-1:0];
end
// synthesis translate_off
if(wr_pulse & (ALLOW_FAST_WRITE_PULSE ? (toggle_wr ^ ~toggle_return_wr0) : 1'b1) & (toggle_wr ^ toggle_rd1)) begin
$display("%t: %m: ERROR: wr_pulse too early to guarantee safe clock domain crossing!", $realtime);
if(!stop_once) begin
stop_once = 1;
$stop;
end
end
// synthesis translate_on
end
end
// **********************************************************************
// READ CLOCK DOMAIN DATA TRANSFER
// **********************************************************************
wire rd_rst;
reset_resync i_reset_resync (
.rst_in (rst),
.clk_in (wr_clk),
.clk_out (rd_clk),
.rst_out (rd_rst)
);
always @(posedge rd_clk or posedge rd_rst) begin
if (rd_rst) begin
toggle_rd_meta <= 1'b0;
toggle_rd0 <= 1'b0;
toggle_rd1 <= 1'b0;
rd_pulse <= 1'b0;
rd_data <= {DATA_SIZE{1'b0}};
end else begin
toggle_rd_meta <= toggle_wr;
toggle_rd0 <= toggle_rd_meta;
toggle_rd1 <= toggle_rd0;
rd_pulse <= toggle_rd0 ^ toggle_rd1;
if (toggle_rd0 ^ toggle_rd1) begin
rd_data[DATA_SIZE-1:0] <= data_wrclk[DATA_SIZE-1:0];
end
end
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; template <typename T> std::ostream& operator<<(std::ostream& str, const std::vector<T>& v) { str << [ ; for (auto n : v) str << n << , ; str << ] ; return str; } template <typename K, typename V> std::ostream& operator<<(std::ostream& str, const std::unordered_map<K, V>& m) { str << [ ; for (auto n : m) str << n.first << => << n.second << , ; str << ] ; return str; } void gen(int i, string c, vector<string>& r) { if (i == 0) { r.push_back(c); return; } gen(i - 1, c + 4 , r); gen(i - 1, c + 7 , r); } int main() { cin.sync_with_stdio(false); cout.sync_with_stdio(false); int input; cin >> input; std::vector<string> all_n; for (int i = 1; i <= 10; i++) { gen(i - 1, 4 , all_n); gen(i - 1, 7 , all_n); } stringstream ss; ss << input; string inp_string = ss.str(); for (int i = 0; i < all_n.size(); i++) { if (all_n[i] == inp_string) { cout << i + 1 << endl; return 0; } } cout << all_n << : << all_n << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5; int xp, yp, xc, yc; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> xp >> yp >> xc >> yc; vector<pair<int, int>> store; while (xc != 0 || yc != 0) { store.push_back({xc, yc}); xc--; yc--; xc = max(0, xc); yc = max(0, yc); } store.push_back({xc, yc}); for (int i = 0; i < store.size(); i++) { pair<int, int> h = store[i]; int z = max(0, xp - h.first) + max(0, yp - h.second); if (z <= i) { cout << Polycarp ; return 0; } } cout << Vasiliy ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_PP_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_LP_V
`define SKY130_FD_SC_LP__LSBUFISO1P_LP_V
/**
* lsbufiso1p: ????.
*
* Verilog wrapper for lsbufiso1p with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__lsbufiso1p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__lsbufiso1p_lp (
X ,
A ,
SLEEP ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
sky130_fd_sc_lp__lsbufiso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP),
.DESTPWR(DESTPWR),
.VPWR(VPWR),
.VGND(VGND),
.DESTVPB(DESTVPB),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__lsbufiso1p_lp (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__lsbufiso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_LP_V
|
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