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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, x; cin >> n >> x; vector<int> v[n + 1]; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } bool vstd[n + 1]; int dst1[n + 1]; int dst2[n + 1]; memset(vstd, false, sizeof vstd); memset(dst1, 0x7f, sizeof dst1); memset(dst2, 0x7f, sizeof dst2); queue<int> q; q.push(1); dst1[1] = 0; while (q.size()) { int node = q.front(); q.pop(); if (vstd[node]) continue; vstd[node] = true; for (auto u : v[node]) { dst1[u] = min(dst1[u], dst1[node] + 1); q.push(u); } } q.push(x); dst2[x] = 0; memset(vstd, false, sizeof vstd); while (q.size()) { int node = q.front(); q.pop(); if (vstd[node]) continue; vstd[node] = true; for (auto u : v[node]) { dst2[u] = min(dst2[u], dst2[node] + 1); q.push(u); } } int ans = 0; for (int i = 1; i <= n; i++) { if (dst1[i] > dst2[i]) { ans = max(ans, max(2 * dst1[i], 2 * dst2[i])); } } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const int N = 1e5 + 7, M = 1e7, OO = 0x3f3f3f3f; map<int, int> dp; int solve(int num) { if (num == 0) { return 0; } if (dp[num]) { return dp[num]; } vector<int> v; int temp = num; while (temp) { v.push_back(temp % 10); temp /= 10; } int ret = -OO; for (int i = 0; i < v.size(); ++i) { ret = max(ret, v[i]); } return dp[num] = 1 + solve(num - ret); } int main() { dp.clear(); int num; cin >> num; cout << solve(num); return 0; }
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#include <bits/stdc++.h> using namespace std; struct _ { ios_base::Init i; _() { cin.sync_with_stdio(0); cin.tie(0); } } _; struct House { int height; int initial_position; }; int main() { int n; cin >> n; vector<House> houses; for (int i = 0; i < n; i++) { int x; cin >> x; House h{x, i}; houses.push_back(h); } stable_sort(houses.begin(), houses.end(), [&](House h1, House h2) { return h1.height < h2.height; }); int up_to = 0; int number_of_blocks = 0; for (int i = 0; i < n; i++) { int initial_position = houses[i].initial_position; up_to = max(up_to, initial_position); if (up_to == i) { up_to++; number_of_blocks++; } } cout << number_of_blocks << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int r1, r2, c1, c2, d1, d2; int main() { scanf( %d%d%d%d%d%d , &r1, &r2, &c1, &c2, &d1, &d2); for (int i = 1; i <= 9; ++i) for (int j = 1; j <= 9; ++j) for (int ii = 1; ii <= 9; ++ii) for (int jj = 1; jj <= 9; ++jj) { if (i != j && i != ii && i != jj && j != ii && j != jj && ii != jj) if (i + j == r1 && jj + ii == r2 && i + ii == c1 && j + jj == c2 && i + jj == d1 && j + ii == d2) { printf( %d %d n%d %d , i, j, ii, jj); return 0; } } printf( -1 ); return 0; }
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#include <bits/stdc++.h> using namespace std; long long q1 = 1000000007, q2 = 100003; long long p1 = 1299827, p2 = 41; bool v[100009]; long long sp[100009]; void sieve() { for (long long i = 2; i < 100009; i += 2) sp[i] = 2; for (long long i = 3; i < 100009; i += 2) { if (!v[i]) { sp[i] = i; for (long long j = i; (j * i) < 100009; j += 2) { if (!v[j * i]) v[j * i] = true, sp[j * i] = i; } } } } set<long long> factorize(long long k) { set<long long> ans; while (k > 1) { ans.insert(sp[k]); k /= sp[k]; } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<long long> used(100009, -1); for (int i = 0; i < n; i++) { long long x, y; cin >> x >> y; long long ans = 0; for (long long j = 1; j * j <= x; j++) { if (x % j == 0) { if (used[j] == -1 || i - used[j] > y) { ans++; } used[j] = i; if (x / j != j && used[x / j] == -1 || i - used[x / j] > y) { ans++; } used[x / j] = i; } } if (used[x] == -1 || i - used[x] > y) { ans++; } used[x] = i; cout << ans << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, ans, q; int main() { cin >> n; int i = 1; while (q < n) { if (i % 2) q++, ans++; else if (q < n - 1) q += 2, ans++; else break; i++; } cout << ans << endl; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311OI_BLACKBOX_V
`define SKY130_FD_SC_MS__A311OI_BLACKBOX_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a311oi (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 310; int can[maxn][maxn]; int p[maxn]; int main() { ios ::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) cin >> p[i]; char k; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { cin >> k; can[i][j] = k - 0 ; } for (int i = 1; i <= n; i++) can[i][i] = 1; for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (can[i][k] && can[k][j]) can[i][j] = 1; for (int i = 1; i < n; i++) for (int j = i + 1; j <= n; j++) if (p[i] > p[j] && can[i][j]) swap(p[i], p[j]); for (int i = 1; i <= n; i++) cout << p[i] << ; cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_LP_V
`define SKY130_FD_SC_LP__DFXTP_LP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_lp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_lp (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_LP_V
|
#include <bits/stdc++.h> const int N = 100001; int i, n, m, g[N], v[N], b[N], res[N], c[N], a; int main() { scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) scanf( %d , &g[i]); for (i = 1; i <= m; i++) scanf( %d , &v[i]); for (i = 1; i <= m; i++) scanf( %d , &b[i]); for (i = 1; i <= m; i++) { for (a = (v[i] + res[i - 1] - 1) % n + 1; b[i] > c[a]; a = g[a]) { if (c[a] == 0) res[i]++; c[a] = b[i]; b[i]--; } printf( %d n , res[i]); } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__ISO0N_BEHAVIORAL_PP_V
/**
* iso0n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__iso0n (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_sleepb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, KAGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_sleepb, SLEEP_B, VPWR, KAGND );
and and0 (X , pwrgood_pp0_out_A, pwrgood_pp1_out_sleepb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long int powOfPositive(long long int n) { long long int pos = floor(log2(n)); return pos; } int main() { long long int t; cin >> t; while (t--) { long long int n; cin >> n; vector<long long int> arr(n); for (long long int i = 0; i < n; i++) { cin >> arr[i]; } vector<long long int> dp(30, 0); long long int ans = 0; for (long long int i = 0; i < n; i++) { if (arr[i] == 1) { dp[0]++; continue; } long long int x = powOfPositive(arr[i]); dp[x]++; } for (long long int i = 0; i < 30; i++) { if (dp[i] > 0) { ans += ((dp[i]) * (dp[i] - 1)) / 2; } } cout << ans << endl; } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
// parameters for array sizes
localparam WA = 4;
localparam WB = 6;
localparam WC = 8;
// 2D packed arrays
logic [WA+1:2] [WB+1:2] [WC+1:2] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [2:WA+1] [2:WB+1] [2:WC+1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
logic [1:0] array_unpk [3:2][1:0];
integer cnt = 0;
integer slc = 0; // slice type
integer dim = 0; // dimension
integer wdt = 0; // width
initial begin
`checkh($dimensions (array_unpk), 3);
`ifndef VCS
`checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009
`endif
`checkh($bits (array_unpk), 2*2*2);
`checkh($low (array_unpk), 2);
`checkh($high (array_unpk), 3);
`checkh($left (array_unpk), 3);
`checkh($right(array_unpk), 2);
`checkh($increment(array_unpk), 1);
`checkh($size (array_unpk), 2);
end
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin
$write("*-* All Finished *-*\n");
$finish;
end
integer slc_next;
// calculation of dimention sizes
always @ (posedge clk) begin
// slicing type counter
case (cnt[3:2])
2'd0 : begin slc_next = 0; end // full array
2'd1 : begin slc_next = 1; end // single array element
2'd2 : begin slc_next = 2; end // half array
default: begin slc_next = 0; end
endcase
slc <= slc_next;
// dimension counter
case (cnt[1:0])
2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end
2'd1 : begin dim <= 2; wdt <= WB; end
2'd2 : begin dim <= 3; wdt <= WC; end
default: begin dim <= 0; wdt <= 0; end
endcase
end
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt);
`endif
if (cnt[30:4]==1) begin
// big endian
if (slc==0) begin
// full array
`checkh($dimensions (array_bg), 3);
`checkh($bits (array_bg), WA*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_bg, dim), wdt+1);
`checkh($right (array_bg, dim), 2 );
`checkh($low (array_bg, dim), 2 );
`checkh($high (array_bg, dim), wdt+1);
`checkh($increment (array_bg, dim), 1 );
`checkh($size (array_bg, dim), wdt );
end
end else if (slc==1) begin
// single array element
`checkh($dimensions (array_bg[2]), 2);
`checkh($bits (array_bg[2]), WB*WC);
if ((dim>=2)&&(dim<=3)) begin
`checkh($left (array_bg[2], dim-1), wdt+1);
`checkh($right (array_bg[2], dim-1), 2 );
`checkh($low (array_bg[2], dim-1), 2 );
`checkh($high (array_bg[2], dim-1), wdt+1);
`checkh($increment (array_bg[2], dim-1), 1 );
`checkh($size (array_bg[2], dim-1), wdt );
end
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
end else if (slc==2) begin
// half array
`checkh($dimensions (array_bg[WA/2+1:2]), 3);
`checkh($bits (array_bg[WA/2+1:2]), WA/2*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_bg[WA/2+1:2], dim), wdt+1);
`checkh($right (array_bg[WA/2+1:2], dim), 2 );
`checkh($low (array_bg[WA/2+1:2], dim), 2 );
`checkh($high (array_bg[WA/2+1:2], dim), wdt+1);
`checkh($increment (array_bg[WA/2+1:2], dim), 1 );
`checkh($size (array_bg[WA/2+1:2], dim), wdt);
end
`endif
end
end else if (cnt[30:4]==2) begin
// little endian
if (slc==0) begin
// full array
`checkh($dimensions (array_lt), 3);
`checkh($bits (array_lt), WA*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_lt, dim), 2 );
`checkh($right (array_lt, dim), wdt+1);
`checkh($low (array_lt, dim), 2 );
`checkh($high (array_lt, dim), wdt+1);
`checkh($increment (array_lt, dim), -1 );
`checkh($size (array_lt, dim), wdt );
end
end else if (slc==1) begin
// single array element
`checkh($dimensions (array_lt[2]), 2);
`checkh($bits (array_lt[2]), WB*WC);
if ((dim>=2)&&(dim<=3)) begin
`checkh($left (array_lt[2], dim-1), 2 );
`checkh($right (array_lt[2], dim-1), wdt+1);
`checkh($low (array_lt[2], dim-1), 2 );
`checkh($high (array_lt[2], dim-1), wdt+1);
`checkh($increment (array_lt[2], dim-1), -1 );
`checkh($size (array_lt[2], dim-1), wdt );
end
`ifndef VERILATOR // Unsupported slices don't maintain size correctly
end else if (slc==2) begin
// half array
`checkh($dimensions (array_lt[2:WA/2+1]), 3);
`checkh($bits (array_lt[2:WA/2+1]), WA/2*WB*WC);
if ((dim>=1)&&(dim<=3)) begin
`checkh($left (array_lt[2:WA/2+1], dim), 2 );
`checkh($right (array_lt[2:WA/2+1], dim), wdt+1);
`checkh($low (array_lt[2:WA/2+1], dim), 2 );
`checkh($high (array_lt[2:WA/2+1], dim), wdt+1);
`checkh($increment (array_lt[2:WA/2+1], dim), -1 );
`checkh($size (array_lt[2:WA/2+1], dim), wdt );
end
`endif
end
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Drawing Engine Top Level Miscelaneos module
// File : de_top_misc.v
// Author : Frank Bruno
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module contains functionality which used to be instantiated at the
// top level
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module de_top_misc
(// inputs
input de_clk,
input sys_locked,
input hb_clk,
input hb_rstn,
input [1:0] ps_2,
input pc_mc_rdy,
input busy_hb,
input mw_de_fip,
input [4:0] dr_style_2,
input dx_blt_actv_2,
input load_actvn,
input line_actv_2,
input wb_clip_ind,
input clip,
input deb,
input cmd_trig_comb,
input line_actv_1,
input blt_actv_1,
input [23:0] de_key_2,
input cmdcpyclr,
input pc_empty,
input pal_busy,
output reg mw_fip,
output ca_busy,
output ps8_2,
output ps16_2,
output ps565_2,
output ps32_2,
output de_pad8_2,
output [1:0] stpl_2,
output reg de_rstn,
output reg de_clint_tog,
output reg dx_clp,
output reg dx_deb,
output [31:0] kcol_2,
output de_trnsp_2,
output reg de_ddint_tog,
output [3:0] probe_misc
);
wire wb_clip_rstn;
wire clip_ddd;
reg mw_fip_dd, de_busy_sync;
reg ca_busyi;
reg tmp_rstn;
reg clip_disab;
reg wb_clip;
reg clip_d, clip_dd;
reg deb_clr_hold;
reg deb_clr_q0,deb_clr_q1,deb_clr_q2;
reg deb_last;
reg de_clint;
reg pal_clr_q0;
reg pal_clr_q1;
reg pal_clr_q2;
reg pal_clr;
assign probe_misc = {ca_busyi, busy_hb, de_busy_sync, pc_mc_rdy};
// Syncronizers.
always @ (posedge de_clk) begin
de_busy_sync <= busy_hb;
mw_fip_dd <= mw_de_fip;
mw_fip <= mw_fip_dd;
end
always @ (posedge de_clk or negedge de_rstn) begin
if(!de_rstn) ca_busyi <= 1'b0;
else ca_busyi <= ~pc_empty | ((busy_hb & de_busy_sync) |
(~pc_mc_rdy & ca_busyi));
end
assign ca_busy = (ca_busyi | busy_hb);
// create the pixel size bits
assign ps8_2 = (ps_2==2'b00);
assign ps16_2 = (ps_2==2'b01) | (ps_2==2'b11);
assign ps565_2 = (ps_2==2'b11);
assign ps32_2 = (ps_2==2'b10);
// 8 bit padding for linear
assign de_pad8_2 = dr_style_2[3] & dr_style_2[2];
// transparent enable bit
assign de_trnsp_2 = (dr_style_2[1] & ~dr_style_2[0] & ~(dx_blt_actv_2)) |
(dr_style_2[1] & ~dr_style_2[0] &
(dr_style_2[3] | dr_style_2[2]));
// stipple packed enable bit
assign stpl_2[1] = dr_style_2[3] & ~line_actv_2;
// stipple planar enable bit
assign stpl_2[0] = ~dr_style_2[3] & dr_style_2[2] & ~line_actv_2;
// syncronize the drawing engine reset.
always @ (posedge de_clk) begin
tmp_rstn <= (sys_locked & hb_rstn);
de_rstn <= tmp_rstn;
end //
//
always @ (posedge de_clk or negedge de_rstn) begin
if (!de_rstn) clip_disab <= 1'b0;
else if (!load_actvn) clip_disab <= 1'b0;
else if (clip_ddd) clip_disab <= 1'b1;
end //
// grab the wb clip pulse.
always @ (posedge de_clk or negedge de_rstn) begin
if (!de_rstn) wb_clip <= 1'b0;
else if (clip_ddd) wb_clip <= 1'b0; // checkme ???? ~
else if (wb_clip_ind) wb_clip <= 1'b1;
end //
always @ (posedge de_clk) begin
clip_d <= ((clip & line_actv_2) | wb_clip);
clip_dd <= clip_d;
de_clint <= (clip_ddd & ~clip_disab);
end //
always @ (posedge de_clk or negedge de_rstn) begin
if(!de_rstn) de_clint_tog <= 1'b0;
else if(de_clint) de_clint_tog <= ~de_clint_tog;
end //
assign clip_ddd = clip_d & ~clip_dd;
always @ (posedge de_clk or negedge de_rstn) begin
if(!de_rstn) de_ddint_tog <= 1'b0;
else if(cmdcpyclr) de_ddint_tog <= ~de_ddint_tog;
end //
always @ (posedge de_clk or negedge de_rstn) begin
if (!de_rstn) dx_clp <= 1'b0;
else if (!load_actvn) dx_clp <= 1'b0;
else if (de_clint) dx_clp <= 1'b1;
end //
// Detect DEB going away
always @(posedge de_clk or negedge hb_rstn) begin
if (!hb_rstn) begin
deb_last <= 1'b0;
deb_clr_hold <= 1'b0;
end else begin
deb_last <= deb;
deb_clr_hold <= (deb_last & ~deb) ^ deb_clr_hold; // Selectable inverter
end
end
always @ (posedge hb_clk) begin
pal_clr_q0 <= pal_busy;
pal_clr_q1 <= pal_clr_q0;
pal_clr_q2 <= pal_clr_q1;
pal_clr <= (pal_clr_q2 & ~pal_clr_q1);
end //
always @ (posedge hb_clk) begin
deb_clr_q0 <= deb_clr_hold;
deb_clr_q1 <= deb_clr_q0;
deb_clr_q2 <= deb_clr_q1;
end //
wire busy_and_not_noop;
assign busy_and_not_noop = (busy_hb && (line_actv_1 || blt_actv_1));
always @(posedge hb_clk or negedge hb_rstn) begin
if (!hb_rstn) dx_deb <= 1'b0;
// else if (cmd_trig_comb && (line_actv_1 || blt_actv_1)) dx_deb <= 1'b1;
else if (cmd_trig_comb) dx_deb <= 1'b1;
else if ((deb_clr_q2 ^ deb_clr_q1) && !busy_and_not_noop) dx_deb <= 1'b0;
else if (pal_clr) dx_deb <= 1'b0;
end //
assign kcol_2 = (ps8_2) ?
{de_key_2[7:0],de_key_2[7:0],de_key_2[7:0],de_key_2[7:0]} :
(ps16_2) ? {de_key_2[15:0],de_key_2[15:0]} : {8'h0,de_key_2};
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { if (b == 0) return a; else return gcd(b, a % b); } bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); std::cout.precision(12); int t; cin >> t; while (t--) { bool f = 0; int n, m; cin >> n >> m; char a[n][m]; char ans[n][m]; vector<pair<int, int>> v[26]; int ma = -1; int r, c; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { cin >> a[i][j]; ans[i][j] = . ; if (a[i][j] >= 97 && a[i][j] <= z ) { v[a[i][j] - a ].push_back({i + 1, j + 1}); if (a[i][j] - a > ma) { ma = a[i][j] - a ; r = i + 1; c = j + 1; } } } } vector<pair<int, int>> start[ma + 1], end[ma + 1]; for (long long int i = 0; i < ma + 1; i++) { if (v[i].size() == 0) { start[i].push_back({r, c}); end[i].push_back({r, c}); } else if (v[i].size() == 1) { ans[v[i][0].first - 1][v[i][0].second - 1] = a + i; start[i].push_back({v[i][0].first, v[i][0].second}); end[i].push_back({v[i][0].first, v[i][0].second}); } else { if (v[i][1].first == v[i][0].first) { int mi = m + 6, m = 0; for (int j = 0; j < v[i].size(); j++) { if (v[i][j].first != v[i][0].first) { f = 1; break; } mi = min(mi, v[i][j].second); m = max(m, v[i][j].second); } if (f == 1) break; for (int j = mi - 1; j < m; j++) { ans[v[i][0].first - 1][j] = a + i; } start[i].push_back({v[i][0].first, mi}); end[i].push_back({v[i][0].first, m}); } else if (v[i][1].second == v[i][0].second) { int mi = n + 6, m = 0; for (int j = 0; j < v[i].size(); j++) { if (v[i][j].second != v[i][0].second) { f = 1; break; } mi = min(mi, v[i][j].first); m = max(m, v[i][j].first); } if (f == 1) break; for (int j = mi - 1; j < m; j++) { ans[j][v[i][0].second - 1] = a + i; } start[i].push_back({mi, v[i][0].second}); end[i].push_back({m, v[i][0].second}); } else { f = 1; break; } } } for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { if (a[i][j] != ans[i][j]) { f = 1; break; } } if (f == 1) break; } if (f == 0) { cout << YES n ; cout << ma + 1 << endl; for (long long int i = 0; i < ma + 1; i++) cout << start[i][0].first << << start[i][0].second << << end[i][0].first << << end[i][0].second << endl; } else { cout << NO n ; } } }
|
/*
* Check that errors are caught.
*/
timeunit 100us;
timeprecision 1us;
// Repeated declarations must match the initial declarations.
timeunit 1ms;
timeprecision 1ns;
// A local time unit is OK, but a repeat must match.
module check_tu_d_e;
timeunit 10us;
timeunit 1us;
endmodule
// A local time precision is OK, but a repeat must match.
module check_tp_d_e;
timeprecision 10us;
timeprecision 1us;
endmodule
// A repeat time unit is only allowed if an initial one is given.
module check_tu_m_e;
integer foo;
timeunit 10us;
endmodule
// A repeat time precision is only allowed if an initial one is given.
module check_tp_m_e;
integer foo;
timeprecision 10us;
endmodule
// A local time unit is OK and a repeat is OK, but this is not a prec decl.
module check_tup_d_e;
timeunit 10us;
timeunit 10us;
timeprecision 1us;
endmodule
// A local time prec is OK and a repeat is OK, but this is not a unit decl.
module check_tpu_d_e;
timeprecision 1us;
timeprecision 1us;
timeunit 10us;
endmodule
/* Check some invalid values */
// Only a power of 10 is allowed.
timeunit 200s;
timeprecision 200s;
// Too many zeros (only allow 0 - 2).
timeunit 1000s;
timeprecision 1000s;
// This actually trips as an invalid scale of '2s'.
timeunit 12s;
timeprecision 12s;
// This needs to be checked. The base time_literal supports this, but
// for now timeunit/precision code does not.
timeunit 1_0s;
timeprecision 1_0s;
|
#include <bits/stdc++.h> using namespace std; long long d1[] = {0, 2, 3, 1}; long long fn1(long long start, long long pos, long long len) { long long zzz = len / 4; if (len == 1) return start; for (long long i = 0; i < 4; i++) { long long l = i * zzz; long long r = l + (zzz - 1); if (l <= pos && pos <= r) return fn1(start + d1[i] * zzz, pos - l, zzz); } return -1; } long long d2[] = {0, 3, 1, 2}; long long fn2(long long start, long long pos, long long len) { long long zzz = len / 4; if (len == 1) return start; for (long long i = 0; i < 4; i++) { long long l = i * zzz; long long r = l + (zzz - 1); if (l <= pos && pos <= r) return fn2(start + d2[i] * zzz, pos - l, zzz); } return -1; } long long solve() { long long n; cin >> n; n--; long long row = n / 3; long long col = n % 3; if (col == 0) { long long pos = row; long long temp = 1; long long start = 1; while (true) { if (pos - temp >= 0) { pos -= temp; temp *= 4; start *= 4; continue; } break; } cout << start + pos << n ; } if (col == 1) { long long pos = row; long long temp = 1; long long start = 2; while (true) { if (pos - temp >= 0) { pos -= temp; temp *= 4; start *= 4; continue; } break; } cout << fn1(start, pos, temp) << n ; } if (col == 2) { long long pos = row; long long temp = 1; long long start = 3; while (true) { if (pos - temp >= 0) { pos -= temp; temp *= 4; start *= 4; continue; } break; } cout << fn2(start, pos, temp) << n ; } return 0; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); ; long long t = 1; cin >> t; while (t-- != 0) { long long stat = solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int long long a[200005], b[200005]; vector<int> v; int main() { int n, t; scanf( %d , &t); while (t--) { scanf( %d , &n); int long long neg = 0, ans = 0; for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); } for (int i = n - 1; i >= 0; i--) { neg += a[i]; if (a[i] > 0) { if (neg > 0) { ans += neg; neg = 0; } } } printf( %lld n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; string winner; int score; int calc(int Suc, int Fal, int A, int B, int C, int D, int E) { int ret = A + B + C + D + E; ret += Suc * 100; ret -= Fal * 50; return ret; } int main() { int n; while (cin >> n) { score = -100000000; for (int i = 1; i <= n; i++) { string name; int Suc, Fal, A, B, C, D, E; cin >> name >> Suc >> Fal >> A >> B >> C >> D >> E; int s = calc(Suc, Fal, A, B, C, D, E); if (s > score) winner = name, score = s; } cout << winner << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long mnr = 1e9, mxl = -1e9; for (long long i = 0; i < n; i++) { long long l, r; cin >> l >> r; mnr = min(mnr, r); mxl = max(mxl, l); } cout << (n == 1 ? 0 : max(mxl - mnr, 0ll)) << n ; } }
|
#include <bits/stdc++.h> using namespace std; int n, a[5050][5050], b[5050][5050] = {0}; int q, l, r; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[0][i]; b[0][i] = a[0][i]; } for (int l = 1; l < n; l++) { for (int i = 0; i < n - l; i++) { a[l][i] = a[l - 1][i] ^ a[l - 1][i + 1]; b[l][i] = max(b[l - 1][i], b[l - 1][i + 1]); b[l][i] = max(b[l][i], a[l][i]); } } cin >> q; for (int i = 0; i < q; i++) { cin >> l >> r; cout << b[r - l][l - 1] << endl; } return 0; }
|
/*
File: pulse2pulse.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module pulse2pulse(/*AUTOARG*/
// Outputs
out,
// Inputs
inclk, outclk, in, reset
);
//clocks
input inclk;
input outclk;
input in;
output out;
//reset
input reset;
wire intoggle;
wire insync;
//pulse to toggle
pulse2toggle pulse2toggle(
// Outputs
.out (intoggle),
// Inputs
.clk (inclk),
.in (in),
.reset (reset));
//metastability synchronizer
synchronizer #(1) synchronizer(
// Outputs
.out (insync),
// Inputs
.in (intoggle),
.clk (outclk),
.reset (reset));
//toogle to pulse
toggle2pulse toggle2pulse(
// Outputs
.out (out),
// Inputs
.clk (outclk),
.in (insync),
.reset (reset));
endmodule // pulse2pulse
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311AI_TB_V
`define SKY130_FD_SC_LP__O311AI_TB_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__o311ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311AI_TB_V
|
#include <bits/stdc++.h> using namespace std; struct Dish { int ind; int cost; int cnt; }; int n; bool dishComp(Dish a, Dish b) { if (a.cost == b.cost) { return a.ind < b.ind; } return a.cost < b.cost; } int main() { int m, a, c; cin >> n >> m; vector<Dish> dishes; for (int i = 0; i < n; i++) { cin >> a; Dish dish; dish.ind = i + 1; dish.cnt = a; dishes.push_back(dish); } int has[n + 1]; for (int i = 0; i < n; i++) { cin >> c; dishes[i].cost = c; } sort(dishes.begin(), dishes.end(), dishComp); for (int i = 0; i < n; i++) { has[dishes[i].ind] = i; } int t, d, btindex, cnti; long long int sm; int saveIndex = 0; for (int i = 0; i < m; i++) { cin >> t >> d; btindex = has[t]; if (dishes[btindex].cnt >= d) { sm = (long long int)dishes[btindex].cost * d; dishes[btindex].cnt = dishes[btindex].cnt - d; } else { sm = (long long int)dishes[btindex].cost * dishes[btindex].cnt; d = d - dishes[btindex].cnt; dishes[btindex].cnt = 0; cnti = 0; while (saveIndex < n) { if (dishes[saveIndex].cnt < d) { d = d - dishes[saveIndex].cnt; sm = sm + (long long int)dishes[saveIndex].cost * dishes[saveIndex].cnt; dishes[saveIndex].cnt = 0; } else { sm = sm + (long long int)dishes[saveIndex].cost * d; dishes[saveIndex].cnt = dishes[saveIndex].cnt - d; cnti = 1; break; } saveIndex++; } if (cnti == 0) sm = 0; } cout << sm << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int a[100100]; int dig[11]; int ans[11]; int main() { int sum = 0; bool pos = false; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; dig[a[i]]++; sum += a[i]; } if (dig[0] == 0) { cout << -1; return 0; } if (sum % 3 == 0) pos = true; if (sum % 3 == 1) { if (dig[1] > 0) { dig[1] -= 1; pos = true; } else if (dig[4] > 0) { pos = true; dig[4] -= 1; } else if (dig[7] > 0) { dig[7] -= 1; pos = true; } else { int a = 10, ai, aj; for (int i = 0; i <= 9; i++) for (int j = 0; j <= 9; j++) if (i != j) { if ((i + j) % 3 == 1 && dig[i] > 0 && dig[j] > 0 && max(i, j) < a) { a = max(i, j); ai = i; aj = j; pos = true; } } else { if ((i + j) % 3 == 1 && dig[i] > 1 && max(i, j) < a) { a = max(i, j); ai = i; aj = j; pos = true; } } dig[ai] -= 1; dig[aj] -= 1; } } else if (sum % 3 == 2) { if (dig[2] > 0) { dig[2] -= 1; pos = true; } else if (dig[5] > 0) { dig[5] -= 1; pos = true; } else if (dig[8] > 0) { dig[8] -= 1; pos = true; } else { int a = 10, ai, aj; for (int i = 0; i <= 9; i++) for (int j = 0; j <= 9; j++) if (i != j) { if ((i + j) % 3 == 2 && dig[i] > 0 && dig[j] > 0 && max(i, j) < a) { a = max(i, j); ai = i; aj = j; pos = true; } } else { if ((i + j) % 3 == 2 && dig[i] > 1 && max(i, j) < a) { a = max(i, j); ai = i; aj = j; pos = true; } } dig[ai] -= 1; dig[aj] -= 1; } } if (pos) { bool shown = false; for (int i = 9; i > 0; i--) for (int j = 0; j < dig[i]; j++) { cout << i; shown = true; } if (shown) for (int j = 0; j < dig[0]; j++) cout << 0; else cout << 0; } else cout << 0; }
|
#include <bits/stdc++.h> using namespace std; int n, s, e; int x[5013]; int a[5013], b[5013], c[5013], d[5013]; long long dp[5013][5013]; int main() { scanf( %d%d%d , &n, &s, &e); for (int i = 1; i <= n; i++) scanf( %d , &x[i]); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) scanf( %d , &b[i]); for (int i = 1; i <= n; i++) scanf( %d , &c[i]); for (int i = 1; i <= n; i++) scanf( %d , &d[i]); memset(dp, 0x7F, sizeof dp); dp[0][0] = 0; for (int i = 1; i <= n; i++) { int diff = 0; if (s < i && e >= i) diff = 1; if (e < i && s >= i) diff = -1; for (int j = 0; j <= n; j++) { int k = j - diff; if (k < 0) continue; if (i == s) { if (k) dp[i][j] = min(dp[i][j], dp[i - 1][j] + c[i] + x[i]); dp[i][j + 1] = min(dp[i][j + 1], dp[i - 1][j] + d[i] - x[i]); } else if (i == e) { if (j) dp[i][j - 1] = min(dp[i][j - 1], dp[i - 1][j] + a[i] + x[i]); dp[i][j] = min(dp[i][j], dp[i - 1][j] + b[i] - x[i]); } else { if (j && k) dp[i][j - 1] = min(dp[i][j - 1], dp[i - 1][j] + c[i] + a[i] + 2 * x[i]); if (k) dp[i][j] = min(dp[i][j], dp[i - 1][j] + c[i] + b[i]); if (j) dp[i][j] = min(dp[i][j], dp[i - 1][j] + d[i] + a[i]); dp[i][j + 1] = min(dp[i][j + 1], dp[i - 1][j] + d[i] + b[i] - 2 * x[i]); } } if (i == n) continue; diff = 0; if (s <= i && e > i) diff = 1; if (e <= i && s > i) diff = -1; for (int j = 0; j <= n; j++) { int k = j - diff; if (j <= 0 && k <= 0) dp[i][j] = 1e18; } } printf( %lld n , dp[n][0]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4_1_V
`define SKY130_FD_SC_HDLL__AND4_1_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4_1_V
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
module BRAM #(parameter AWIDTH = 9,
parameter DWIDTH = 32)
(clk,
rce,
ra,
rq,
wce,
wa,
wd);
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
reg [DWIDTH-1:0] memory[0:AWIDTH-1];
always @(posedge clk) begin
if (rce)
rq <= memory[ra];
if (wce)
memory[wa] <= wd;
end
integer i;
initial
begin
for(i = 0; i < AWIDTH-1; i = i + 1)
memory[i] = 0;
end
endmodule
module BRAM_32x512(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 9;
parameter DWIDTH = 32;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_32x512 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
module BRAM_16x1024(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 10;
parameter DWIDTH = 16;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_16x1024 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
module BRAM_8x2048(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 11;
parameter DWIDTH = 8;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_8x2048 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
module BRAM_4x4096(
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 12;
parameter DWIDTH = 4;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
BRAM_4x4096 ( .clk(clk),
.rce(rce),
.ra(ra),
.rq(rq),
.wce(wce),
.wa(wa),
.wd(wd));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR3_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__XNOR3_PP_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xnor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 9; const int N = 4040; int n, w, b; long long fac[N], f[N][N], inv[N]; long long qpow(long long x, long long p) { long long res = 1ll; while (p) { if (p & 1) { res = (res * x) % mod; } x = (x * x) % mod; p >>= 1; } return res; } long long INV(long long k) { return qpow(k, mod - 2); } long long calc(int x, int y) { return fac[x] * inv[y] % mod * inv[x - y] % mod; } void init() { fac[0] = 1ll; inv[0] = 1ll; for (int i = 1; i < N; i++) { fac[i] = (fac[i - 1] * 1ll * i) % mod; inv[i] = INV(fac[i]); } } int main() { scanf( %d%d%d , &n, &w, &b); init(); for (int i = 1; i <= n; i++) { for (int j = i; j < N; j++) { f[i][j] = (fac[j] * calc(j - 1, i - 1)) % mod; } } long long ans = 0; for (int i = 1; i < n - 1; i++) { ans = (ans + f[n - i][w] * f[i][b] % mod * (1ll * n - 1ll * i - 1ll) % mod) % mod; } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_BLACKBOX_V
`define SKY130_FD_SC_LS__FILL_DIODE_BLACKBOX_V
/**
* fill_diode: Fill diode.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fill_diode ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int p, first, cnts, cntw, S, W; int solve(long long picked) { int cap1 = p, cap2 = first, cnt1 = cnts, cnt2 = cntw; long long temp = picked; cap1 -= (picked * S); cnt1 -= picked; if (cap1 >= W) { temp += min(cap1 / W, cnt2); cnt2 -= min(cap1 / W, cnt2); } if (S <= W) { temp += min(cap2 / S, cnt1); cap2 -= (min(cap2 / S, cnt1) * S); temp += min(cap2 / W, cnt2); } else { temp += min(cap2 / W, cnt2); cap2 -= (min(cap2 / W, cnt2) * W); temp += min(cap2 / S, cnt1); } return temp; } int main() { int t; scanf( %d , &t); while (t--) { scanf( %d %d , &p, &first); scanf( %d %d , &cnts, &cntw); scanf( %d %d , &S, &W); long long ans = 0, temp; for (int pickedS = 0; pickedS <= min(cnts, p / S); pickedS++) { temp = solve(pickedS); ans = max(ans, temp); } printf( %lld n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog wrapper for lpflow_clkinvkapwr with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_clkinvkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_16 (
Y ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output Y ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:00:56 03/26/2015
// Design Name:
// Module Name: summator
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
acc wymaga 21 bitow do poprawnego dzialania.
Zakres liczby 13 bitowej typu z8c4u to - (matlab)
A wic w najgorszym przypadku (256 * min/max) = (-65536 65520)
potrzebne jest 21 bitow do reprezentacji. Zakres to wtedy -65536 65536.
Wymagana latencja - 0
*/
module summator(
input [12:0] A,
input clk,
input ce,
input rst,
output [20:0] Y
);
reg [20:0] sum = 21'b0;
wire [20:0] new_sum;
reg [20:0 ] tmp = 21'b0;
always @(posedge clk)
begin
if(rst) sum = 21'b0;
else
begin
sum = new_sum;
if(ce) tmp = {{A[12]}, {8{A[12]}}, {A[11:0]}};
else tmp = 0;
end
end
add adder (
.a(sum), // input [20 : 0] a
.b(tmp), // input [20 : 0] b
//.clk(clk), // input clk
.s(new_sum) // output [20 : 0] s
);
assign Y = sum;
endmodule
|
// The cordic algorithm
// This will be a pipelined design that processes
// one angle rotation per clock cycle. There is
// one rotation per input bit.
// Rotation angle must be between -pi/2 to pi/2
// Angle is stated in I3Q13 as it must accomodate +- 1.57...
// Output is approx 1.64 times larger than reality due to
// the scale factor, which is sum(1 / sqrt(1 + 2^-i)^2) over
// i in 0->Width. It's 1.6467602581210652 to more exact
module cordic(
clk,
xI, // Input X value
yI, // Input Y Value
angle, // Rotation angle in radians
xO,
yO
);
// Bitness of all relevant buses
parameter WIDTH = 16;
parameter ANGLE_WIDTH = 32;
parameter ATAN_INITIAL_FILE = "../mems/atan16_32.hex";
// Inputs
/* verilator lint_off UNUSED */
input clk;
input signed[WIDTH-1:0] xI, yI;
input signed[ANGLE_WIDTH-1:0] angle;
/* verilator lint_on UNUSED */
// Outputs
output signed[WIDTH-1:0] xO, yO;
// Pipeline
reg signed[WIDTH-1:0] x_pl[WIDTH:0]; // X pipeline stages
reg signed[WIDTH-1:0] y_pl[WIDTH:0]; // Y pipeline stages
reg signed[ANGLE_WIDTH-1:0] a_pl[WIDTH:0]; // Angle pipeline stages
// atan_lut[i] is the result of atan(x) w/ x = 2^-i in radians
reg[ANGLE_WIDTH-1:0] atan_lut[WIDTH-1:0];
initial begin
$readmemh(ATAN_INITIAL_FILE, atan_lut);
end
// Result depends on angle > 0 for +/-
// xO = xI -/+ (yI >> i)
// yO = yI +/- (xI >> i)
wire[1:0] quadrant;
assign quadrant = angle[31:30];
integer i;
always @(posedge clk) begin
// Preprocess angle before entering pipeline.
case (quadrant)
2'b00, // Tangent is fine in this quadrants, no reflection
2'b11: begin
x_pl[0] <= xI;
y_pl[0] <= yI;
a_pl[0] <= angle;
end
2'b01: begin
x_pl[0] <= -yI;
y_pl[0] <= xI;
a_pl[0] <= {2'b00, angle[29:0]};
end
2'b10: begin
x_pl[0] <= yI;
y_pl[0] <= -xI;
a_pl[0] <= {2'b11, angle[29:0]};
end
endcase
// Generate pipeline stages. Might need to break this up if it synths to something awful.
// Will probably need an alway @(*) block if so to hold the combinational parts.
for(i = 0; i < WIDTH; i = i + 1) begin
x_pl[i+1] <= (a_pl[i] > 0) ? x_pl[i] - (y_pl[i] >>> i) : x_pl[i] + (y_pl[i] >>> i);
y_pl[i+1] <= (a_pl[i] > 0) ? y_pl[i] + (x_pl[i] >>> i) : y_pl[i] - (x_pl[i] >>> i);
a_pl[i+1] <= (a_pl[i] > 0) ? a_pl[i] - atan_lut[i] : a_pl[i] + atan_lut[i];
end
end
// Set the output. That sure looks like it means x[0] doesn't it? But it's xO...utput.
assign xO = x_pl[WIDTH-1];
assign yO = y_pl[WIDTH-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxn = 100010; int x0[maxn], x1[maxn], d[maxn], c[maxn]; int main() { int n, m, y0, y1; cin >> n >> m >> y0 >> y1; for (int i = 0; i < n; ++i) { cin >> x0[i]; } memset(d, -1, sizeof(d)); for (int i = 0; i < m; ++i) { cin >> x1[i]; } int p = 0, k = 0, last = -1; for (int i = 0; i < n; ++i) { while (p < m && abs(x0[i] - x1[p]) > abs(x0[i] - x1[p + 1])) ++p; if (last < p || abs(x0[i - 1] - x1[p]) == abs(x0[i] - x1[p])) ++k, last = p; else if (p < m && abs(x0[i] - x1[p]) == abs(x0[i] - x1[p + 1])) ++k, last = ++p; else last = p; } cout << n - k << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math ) using namespace std; const int N = 2e5 + 100, sq = 1002, nsq = 200; int cnt[nsq][N], b[nsq][N / 2]; int a[N]; map<int, int> mp, nmp; vector<pair<int, pair<int, int> > > q; void add(int id, int val) { while (id < nsq) { cnt[id][val]++; b[id][cnt[id][val]]++; id++; } } void rem(int id, int val) { while (id < nsq) { b[id][cnt[id][val]]--; cnt[id][val]--; id++; } } int get1(int id) { int val = a[id]; int pid = id / sq; int ans = cnt[pid][val]; int x = pid * sq; for (int i = x; i <= id; i++) { if (a[i] == val) ans++; } return ans; } int get2(int id) { int val = a[id]; int pid = id / sq; int w = cnt[pid][val]; int x = pid * sq; for (int i = x; i <= id; i++) { if (a[i] == val) w++; } int ans = b[pid][w]; for (int i = x; i <= id; i++) { cnt[pid][a[i]]++; if (cnt[pid][a[i]] == w) ans++; } for (int i = x; i <= id; i++) { cnt[pid][a[i]]--; } return ans; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; vector<int> mol; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; mol.push_back(a[i]); } int q1; cin >> q1; for (int i = 0; i < q1; i++) { int t, u, v; cin >> t >> u >> v; if (t == 1) mol.push_back(u); q.push_back({t, {u, v - 1}}); } sort(mol.begin(), mol.end()); mol.resize(unique(mol.begin(), mol.end()) - mol.begin()); for (int i = 0; i < mol.size(); i++) { mp[mol[i]] = i + 1; nmp[i + 1] = mol[i]; } for (int i = 0; i < n; i++) a[i] = mp[a[i]]; for (int i = 0; i < q1; i++) if (q[i].first == 1) q[i].second.first = mp[q[i].second.first]; int id = 0; while (id < n) { for (int i = 0; i < id; i++) { cnt[id / sq][a[i]]++; } for (int i = 0; i < N; i++) { b[id / sq][cnt[id / sq][i]]++; } for (int i = N - 1; i; i--) { b[id / sq][i] += b[id / sq][i + 1]; } id += sq; } for (int i = 0; i < q1; i++) { if (q[i].first == 1) { int v = q[i].second.first, p = q[i].second.second; int z = a[p]; add(p / sq + 1, v); rem(p / sq + 1, a[p]); a[p] = v; } else { int x = q[i].second.first, y = q[i].second.second; if (x == 1) cout << nmp[a[y]] << n ; else if (x % 2 == 0) { int ans = get1(y); cout << ans << n ; } else { int ans = get2(y); cout << ans << n ; } } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j; cin >> n; vector<pair<int, int>> v; for (i = 0; i < n; i++) { int x, y; cin >> x >> y; v.push_back(make_pair(x, y)); } int ans = 0; int total = 0; bool u, d, l, r; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (v[i].first > v[j].first && v[i].second == v[j].second) d = true; if (v[i].first < v[j].first && v[i].second == v[j].second) u = true; if (v[i].second > v[j].second && v[i].first == v[j].first) l = true; if (v[i].second < v[j].second && v[i].first == v[j].first) r = true; } if (d && u && l && r) total++; d = false; u = false; l = false; r = false; } cout << total; }
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return a * (b / gcd(a, b)); } const int N = 100005; void solve() { long long n; cin >> n; long long ans = 1; for (long long i = 2; i <= n; i++) { ans = ans + 4 * (i - 1); } cout << ans; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) { solve(); } cerr << nTime elapsed: << 1000 * clock() / CLOCKS_PER_SEC << ms n ; return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - always block with @(value) and (posedge OR negedge)
//
// D: New test used to validate always @(value), and
// D: always @(val1 or val2), and always @(posedge val1 or negedge val2)
// D: statements.
//
//
module main ();
reg working;
reg reset;
reg clock ;
reg test_var;
initial // Used to generate timing of events
begin
clock = 0;
reset = 0;
// Nothing sent yet...
#5 ;
$display("time=%d, c=%b, r=%b, reg=%b",$time,clock,reset,test_var);
reset = 1; // 5 ns
#5 ;
$display("time=%d, c=%b, r=%b, reg=%b",$time,clock,reset,test_var);
reset = 0; // 10ns
#5 ;
$display("time=%d, c=%b, r=%b, reg=%b",$time,clock,reset,test_var);
clock = 1; // 15 ns
#5 ;
$display("time=%d, c=%b, r=%b, reg=%b",$time,clock,reset,test_var);
clock = 0; // 20 ns
#5 ; // 25 ns
$display("time=%d, c=%b, r=%b, reg=%b",$time,clock,reset,test_var);
end
//
// This is the statement being verified...
//
// This LOOKS like a race between the posedge and the reset value
// but is a standard method for reseting f/f's.
//
always @(posedge clock or posedge reset)
if(reset)
test_var = 0;
else
test_var = ~test_var;
initial // This is the validation block
begin
# 3; // 3 ns Check always @(val)
if(test_var != 1'bx)
begin
$display("FAILED - initial condition of reg variable not x\n");
$finish ;
end
# 5; // 8 ns Check posedge of always @(posedge val or negedge)
if(test_var == 1'bx)
begin
$display("FAILED - Reset didn't reset var \n");
$finish ;
end
if(test_var == 1'b1)
begin
$display("FAILED - Reset set it to 1?? \n");
$finish ;
end
# 5; // 12 ns
if(test_var == 1'bx)
begin
$display("FAILED - Reset didn't reset var \n");
$finish ;
end
if(test_var == 1'b1)
begin
$display("FAILED - Reset set it to 1?? \n");
$finish ;
end
# 5; // 17 ns - have received the clock by now
if(test_var == 1'bx)
begin
$display("FAILED - The clock caused an x??\n");
$finish ;
end
if(test_var == 1'b0)
begin
$display("FAILED - The clock didn't have any effect?? \n");
$finish ;
end
# 30;
$display("PASSED\n");
$finish;
end
endmodule
|
`define ADDER_WIDTH 008
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1 << 20; const long long MOD = 2305843009255636993, RT = 5; struct CD { double r, i; CD(double r = 0, double i = 0) : r(r), i(i) {} double real() const { return r; } void operator/=(const int c) { r /= c, i /= c; } }; CD operator*(const CD& a, const CD& b) { return CD(a.r * b.r - a.i * b.i, a.r * b.i + a.i * b.r); } CD operator+(const CD& a, const CD& b) { return CD(a.r + b.r, a.i + b.i); } CD operator-(const CD& a, const CD& b) { return CD(a.r - b.r, a.i - b.i); } const double pi = acos(-1.0); CD cp1[MAXN + 9], cp2[MAXN + 9]; int R[MAXN + 9]; void dft(CD* a, int n, bool inv) { for (int i = 0, ThxDem = n; i < ThxDem; ++i) if (R[i] < i) swap(a[R[i]], a[i]); for (int m = 2; m <= n; m *= 2) { double z = 2 * pi / m * (inv ? -1 : 1); CD wi = CD(cos(z), sin(z)); for (int j = 0; j < n; j += m) { CD w(1); for (int k = j, k2 = j + m / 2; k2 < j + m; k++, k2++) { CD u = a[k]; CD v = a[k2] * w; a[k] = u + v; a[k2] = u - v; w = w * wi; } } } if (inv) for (int i = 0, ThxDem = n; i < ThxDem; ++i) a[i] /= n; } vector<long long> multiply(vector<long long>& p1, vector<long long>& p2) { int n = p1.size() + p2.size() + 1; int m = 1, cnt = 0; while (m <= n) m += m, cnt++; for (int i = 0, ThxDem = m; i < ThxDem; ++i) { R[i] = 0; for (int j = 0, ThxDem = cnt; j < ThxDem; ++j) R[i] = (R[i] << 1) | ((i >> j) & 1); } for (int i = 0, ThxDem = m; i < ThxDem; ++i) cp1[i] = 0, cp2[i] = 0; for (int i = 0, ThxDem = p1.size(); i < ThxDem; ++i) cp1[i] = p1[i]; for (int i = 0, ThxDem = p2.size(); i < ThxDem; ++i) cp2[i] = p2[i]; dft(cp1, m, false); dft(cp2, m, false); for (int i = 0, ThxDem = m; i < ThxDem; ++i) cp1[i] = cp1[i] * cp2[i]; dft(cp1, m, true); vector<long long> res; n -= 2; for (int i = 0, ThxDem = n; i < ThxDem; ++i) res.push_back((long long)floor(cp1[i].real() + 0.5)); return res; } int spf[MAXN]; vector<int> ds; vector<pair<int, int> > prs; void gen(int x, int pos) { if (pos == int(prs.size())) ds.push_back(x); else { for (int i = 0, ThxDem = prs[pos].second + 1; i < ThxDem; ++i) { if (i || prs[pos].first != 2) gen(x, pos + 1); x *= prs[pos].first; } } } vector<int> dis[MAXN]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); for (int i = 2, ThxDem = MAXN; i < ThxDem; ++i) if (!spf[i]) for (int j = i; j < MAXN; j += i) if (!spf[j]) spf[j] = i; for (int i = 2, ThxDem = MAXN; i < ThxDem; ++i) if (i % 2 == 0) { prs.clear(); ds.clear(); int x = i; while (x > 1) { int now = spf[x], pw = 0; while (x % now == 0) x /= now, pw++; prs.push_back({now, pw}); } gen(1, 0); sort(ds.begin(), ds.end()); reverse(ds.begin(), ds.end()); dis[i] = ds; } int n, x, y; cin >> n >> x >> y; n++; vector<int> a(n); int off = x + 1; vector<long long> neg(2 * (x + 1)), pos(2 * (x + 1)); for (int i = 0, ThxDem = n; i < ThxDem; ++i) { cin >> a[i]; neg[x + 1 - a[i]] = 1; pos[off + a[i]] = 1; } auto ws = multiply(neg, pos); int q; cin >> q; vector<int> ans(q, -1); for (int j = 0, ThxDem = q; j < ThxDem; ++j) { int v; cin >> v; for (auto tt : dis[v]) { int len = tt - 2 * y; if (len <= 0 || len % 2) continue; len /= 2; if (2 * off + len < int(ws.size()) && ws[2 * off + len] > 0) { ans[j] = tt; break; } } } for (auto x : ans) cout << x << ; cout << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DFSTP_BEHAVIORAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_BEHAVIORAL_PP_V
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [7:0] testr;
wire [7:0] testw = {-5'd1, -3'sd1};
initial begin
#1 testr = {-5'd1, -3'sd1};
if (testr !== 8'b11111_111) begin
$display("FAILED -- testr=%b", testr);
$finish;
end
if (testw !== 8'b11111_111) begin
$display("FAILED -- testw=%b", testw);
$finish;
end
$display("testr=%b", testr);
$display("testw=%b", testw);
$display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; struct numer { int rost; int num_of; numer() : rost(0), num_of(0) {} numer(int _rost, int _num_of) : rost(_rost), num_of(_num_of) {} }; int maxim(int a, int b) { return a > b ? a : b; } int comp(const void *a, const void *b) { int *A = (int *)a, *B = (int *)b; return *A < *B ? -1 : *A > *B ? 1 : 0; } void push(stack<int> &S, numer &chel) { for (int i = 0; i < chel.num_of; i++) S.push(chel.rost); } int balance(int *Rost, int num, int *&ring, bool else_good = false, bool good = false) { qsort(Rost, num, sizeof(int), comp); vector<numer> people; numer temp(Rost[0], 1); stack<int> Stack; for (int i = 1; i < num; i++) { if (Rost[i] == Rost[i - 1]) temp.num_of++; else { people.push_back(temp); temp = numer(Rost[i], 1); } } people.push_back(temp); int kol = people.size(), min = 0, curr = 0, tmp = 0, tmp1, *p = 0; if (else_good == false) { for (int i = 1; i <= kol; i++) { curr += people[i - 1].num_of; if (i == kol) { tmp1 = balance(Rost + min, curr - min, p, true, false); if (tmp1 > tmp) { ring = p; tmp = tmp1; } continue; } if (people[i].rost - people[i - 1].rost >= 2) { tmp1 = balance(Rost + min, curr - min, p, true, false); if (tmp1 > tmp) { ring = p; tmp = tmp1; } min = curr; } } } if (tmp == 0) { int new_curr = people[0].num_of, new_min = 0; if (good == false) { for (int i = 1; i < kol; i++) { new_curr += people[i].num_of; if (people[i].num_of == 1 || i == kol - 1) { tmp1 = balance(Rost + new_min, new_curr - new_min, p, true, true); if (tmp1 > tmp) { ring = p; tmp = tmp1; } new_min = new_curr - people[i].num_of; } } if (kol == 1) { tmp = tmp1 = new_curr; ring = new int[tmp]; for (int j = 0; j < tmp; j++) ring[j] = people[0].rost; } } else { for (int i = 0; i < kol; i++) { Stack.push(people[i].rost); people[i].num_of--; } for (int i = kol - 1; i >= 0; i--) push(Stack, people[i]); tmp = Stack.size(); ring = new int[tmp]; for (int i = 0; i < tmp; i++) { ring[i] = Stack.top(); Stack.pop(); } } } return tmp; } int main() { int n; cin >> n; int *A = new int[n], *B = 0; for (int i = 0; i < n; i++) cin >> A[i]; int k = balance(A, n, B); cout << k << endl; for (int i = 0; i < k; i++) cout << B[i] << ; delete[] A; delete[] B; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; vector<long long> arr(n); for (int i = 0; i < n; i++) { cin >> arr[i]; } long long c = 0; for (int i = 0; i < n; i++) { c += arr[i] - 1; if (c % 2 == 0) cout << 2 << n ; else cout << 1 << n ; } } int main() { ios_base::sync_with_stdio(false), cin.tie(nullptr); long long T; T = 1; for (int t = 0; t < T; t++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int M[16]; int R[16]; int N; int main() { cin >> N; for (int i = 0; i < N; i++) { cin >> M[i]; } for (int i = 0; i < N; i++) { cin >> R[i]; } int ans = 0; for (int i = 0; i < 720720; i++) { bool checker = false; for (int j = 0; j < N; j++) { if (i % M[j] == R[j]) checker = true; } if (checker) ans++; } cout << ans / 720720.0 << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s, s2; cin >> s; cin >> s2; vector<char> v, t; for (int i = 0; i < s.length(); i++) { v.push_back(s[i]); } vector<char>::iterator it; int i = 0; for (it = v.end() - 1; it >= v.begin(); it--) { t.push_back(*it); } int cnt = 0, n = s.length(); for (int i = 0; i < n; i++) { if (t[i] == s2[i]) cnt++; } if (cnt == n) cout << YES ; else cout << NO ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_4_V
`define SKY130_FD_SC_LP__A22OI_4_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_4_V
|
#include <bits/stdc++.h> using namespace std; int n; char a[22][22], b[22][22], c[22][22]; bool chk() { for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (a[i][j] != b[i][j]) return false; return true; } void flip() { for (int i = 0; i < n; i++) for (int j = 0; j < n - j - 1; j++) swap(a[i][j], a[i][n - j - 1]); } void rotate() { for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) c[j][n - i - 1] = a[i][j]; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) a[i][j] = c[i][j]; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %s , a[i]); for (int i = 0; i < n; i++) scanf( %s , b[i]); bool f = false; for (int i = 0; i < 2 && !f; i++) { for (int j = 0; j < 4 && !f; j++) { if (chk()) f = true; rotate(); } flip(); } puts(f ? Yes : No ); return 0; }
|
/*
* Modified to add "endtask : <name>" syntax. This modification tests
* the SystemVerilog extension to the syntax. -- Stephen Williams
*/
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: task_scope.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $
// $Log: task_scope.v,v $
// Revision 1.1 2001/06/19 13:52:13 ka6s
// Added 4 tests from Stephan Boettcher
//
// Test for task scope lookup in VVP
module test;
wire w;
jobs j(w);
task ini;
begin
j.set(1'bz);
end
endtask : ini
initial
begin
ini;
#1;
j.set(1'b1);
#1;
if (w===1)
$display("PASSED");
else
$display("FAILED");
end
endmodule // test
module jobs (out);
output out;
reg out;
task set;
input val;
begin
#1 out = val;
end
endtask : set
endmodule // jobs
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__DIODE_PP_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__diode (
//# {{power|Power}}
input DIODE,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_PP_SYMBOL_V
|
#include <bits/stdc++.h> const int maxn = 1000 + 10; const int maxm = 4e5 + 10; const int inf_max = 0x3f3f3f; using namespace std; int a, b, c; int main() { int t; cin >> t; while (t--) { cin >> a >> b >> c; string ans = ; if (a) ans += 0 ; for (int i = 1; i <= a; ++i) ans += 0 ; if (c) { ans += 1 ; if (a) b--; } for (int i = 1; i <= c; ++i) ans += 1 ; int len = ans.size(); if (len == 0 && b) ans += 0 ; len = ans.size(); if (ans[len - 1] == 0 ) { while (b >= 2) ans += 10 , b -= 2; if (b) ans += 1 ; } else { if (b) ans += 0 , b--; while (b >= 2) ans += 10 , b -= 2; if (b) ans += 1 ; } cout << ans << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:13:00 10/17/2016
// Design Name:
// Module Name: num_3
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module num_3(
input [2:0] in_row,
output reg [4:0] out_code
);
parameter [4:0] d_0 = 5'b01110; // XXX
parameter [4:0] d_1 = 5'b10001; // X X
parameter [4:0] d_2 = 5'b01000; // X
parameter [4:0] d_3 = 5'b10000; // X
always @ *
begin
case (in_row)
3'b000:
out_code = d_0;
3'b001:
out_code = d_1;
3'b010:
out_code = d_2;
3'b011:
out_code = d_3;
3'b100:
out_code = d_1;
3'b101:
out_code = d_0;
default:
out_code = 5'b0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long base = 7; const long long maxn = 1e6 + 9; const long long inf = 1e9 + 7; set<long long> W, H; multiset<long long> l1, l2; long long w, h, n, a; long long x, y; char c; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> w >> h >> n; W.insert(0); W.insert(w); l1.insert(w); H.insert(0); H.insert(h); l2.insert(h); long long maxx; while (n--) { cin >> c >> a; if (c == V ) { W.insert(a); x = *prev(W.find(a)); y = *next(W.find(a)); auto it = l1.find(y - x); l1.erase(it); l1.insert(y - a); l1.insert(a - x); } else { H.insert(a); x = *prev(H.find(a)); y = *next(H.find(a)); auto it = l2.find(y - x); l2.erase(it); l2.insert(y - a); l2.insert(a - x); } long long p = *prev(l1.end()); long long q = *prev(l2.end()); cout << p * q << n ; } }
|
#include <bits/stdc++.h> using namespace std; const long long OO = (long long)1e15; const double EPS = 1e-11; vector<vector<pair<long long, int> > > adj; vector<vector<long long> > ar; vector<vector<long long> > dep; long long nxt(int node, long long time) { int idx = lower_bound(ar[node].begin(), ar[node].end(), time) - ar[node].begin(); if (idx >= (int)ar[node].size() || ar[node][idx] != time) return 0; return dep[node][idx] - time; } long long dij(int src, int d, int len) { priority_queue<pair<long long, int>, vector<pair<long long, int> >, greater<pair<long long, int> > > q; long long cst = nxt(src, 0); q.push(make_pair((cst), (src))); vector<long long> dest(len, OO); dest[src] = q.top().first; while (!q.empty()) { int n = q.top().second; long long c = q.top().first; q.pop(); if (c != dest[n]) continue; if (n == d) return c; for (int i = 0; i < (int)adj[n].size(); ++i) { int tn = adj[n][i].second; long long tc = adj[n][i].first; long long nc = c + tc + ((tn == d) ? 0 : nxt(tn, c + tc)); if (nc < dest[tn]) { dest[tn] = nc; q.push(make_pair((dest[tn]), (tn))); } } } return -1; } int main() { int n, m, a, b, k; cin >> n >> m; adj.clear(); adj.resize(n); long long c; for (int i = 0; i < m; ++i) { cin >> a >> b >> c; a--, b--; adj[a].push_back(make_pair((c), (b))); swap(a, b); adj[a].push_back(make_pair((c), (b))); } ar.clear(); dep.clear(); ar.resize(n); dep.resize(n); for (int i = 0; i < n; ++i) { cin >> k; if (k == 0) continue; ar[i].resize(k); dep[i].resize(k); for (int j = 0; j < k; ++j) { cin >> ar[i][j]; } dep[i][k - 1] = ar[i][k - 1] + 1; for (int j = k - 2; j >= 0; --j) { if (ar[i][j] + 1 != ar[i][j + 1]) dep[i][j] = ar[i][j] + 1; else dep[i][j] = dep[i][j + 1]; } } cout << dij(0, n - 1, n) << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_4_V
`define SKY130_FD_SC_LP__O211AI_4_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211ai_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
/**
* lpflow_inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, SLEEP_B );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long MOD; inline void modulas(long long a) { MOD = a; } inline void normal(long long &a) { a %= MOD; (a < 0) && (a += MOD); } inline long long modMul(long long a, long long b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a * b) % MOD; } inline long long modAdd(long long a, long long b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a + b) % MOD; } inline long long modSub(long long a, long long b) { a %= MOD, b %= MOD; normal(a), normal(b); a -= b; normal(a); return a; } inline long long modPow(long long b, long long p) { long long r = 1; while (p) { if (p & 1) r = modMul(r, b); b = modMul(b, b); p >>= 1; } return r; } inline long long modInverse(long long a) { return modPow(a, MOD - 2); } inline long long modDiv(long long a, long long b) { return modMul(a, modInverse(b)); } vector<bool> isPrime(10000010, true); inline void seivePrime(long long L, long long R) { long long lim = sqrt(R); for (long long i = 2; i <= lim; ++i) { for (long long j = max(i * i, (L + i - 1) / i * i); j <= R; j += i) isPrime[j - L] = false; } if (L == 1) isPrime[0] = false; } inline long long chckPrime(long long L, long long prme) { return isPrime[prme - L]; } inline long long cntPrime(long long L, long long R) { return count(isPrime.begin(), isPrime.begin() + R - L + 1, true); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t = 1; cin >> t; while (t--) { int n; cin >> n; int ar[n]; for (int i = 0; i < n; i++) cin >> ar[i]; int s = 0, sum = 0; for (int i = 0; i < n; i++) { if (ar[i] == 0) { ar[i] = 1; s++; } sum += ar[i]; } if (sum == 0) { sort(ar, ar + n); if (ar[n - 1] > 0) cout << s + 1 << n ; else if (ar[0] == -1) cout << s + 2 << n ; else cout << s + 1 << n ; } else cout << s << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int vocala(char c) { if (c == a || c == A || c == e || c == E || c == i || c == I || c == o || c == O || c == u || c == U ) return 1; if (c == y || c == Y ) return 1; return 0; } int isprime(long long n) { if (n <= 1) return 0; for (long long i = 2; i * i <= n; ++i) if (n % i == 0) return 0; return 1; } int isfibo(long long n) { long long a = 5 * n * n + 4; long long b = a - 8; if (sqrt(a) == int(sqrt(a)) || sqrt(b) == int(sqrt(b))) return 1; return 0; } int gcd(long long a, long long b) { long long r; while (b) { r = a % b; a = b; b = r; } return a; } ifstream in( input.txt ); ofstream out( output.txt ); long long const nrmax = 1e18; long long v[100005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> v[i]; } long long cnt = 3e9; sort(v + 1, v + n + 1); cnt = min(cnt, v[n] - v[2]); cnt = min(cnt, v[n - 1] - v[1]); cout << cnt << n ; in.close(); out.close(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_BLACKBOX_V
`define SKY130_FD_SC_HD__NOR4B_BLACKBOX_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_BLACKBOX_V
|
module BarrelShifter(
inputA, Bse,
control,
outputBS,
N, Zero, C//Flags
);
input [31:0] inputA, Bse;
input [3:0] control;
output reg N, Zero, C;
output reg [31:0] outputBS;
reg [31:0] aux1, aux3;
reg aux2;
wire zer;
assign zer = (outputBS == 0);
always @ ( * ) begin
N=0; Zero=0; C=0; //Flag cleaning
outputBS=0; //Output cleaning
aux1=0; aux2=0; aux3=0; //Auxiliar cleaning
case (control)
1:begin //Saída=B<<1
{aux2,outputBS}=Bse<<1;
C=aux2;
Zero=zer;
N=outputBS[31];
end
2:begin //ASR
aux2=inputA[31];
if (Bse<31) begin
aux3=inputA>>Bse;
aux1 = (aux2)? 32'hffffffff : 32'h0;
aux1=aux1<<32-Bse;
outputBS= aux3|aux1;
// aux1=inputA<<32-Bse;
C=|inputA;
Zero=zer;
N=aux2;
end else begin
C=|inputA;
outputBS = (aux2) ? 32'hffffffff : 32'h0;
Zero=!aux2;
N=aux2;
end
end
3:begin //LSL
if (Bse<32) begin
// {aux1,outputBS}=inputA<<Bse;
outputBS=inputA<<Bse;
aux1=inputA>>32-Bse;
C=|aux1;
Zero=zer;
N=outputBS[31];
end else begin
C=|inputA;
outputBS=0;
Zero=1;
N=0;
end
end
4:begin //LSR
if (Bse<32) begin
outputBS=inputA>>Bse;
aux1=inputA<<32-Bse;
C=|aux1;
Zero=zer;
N=outputBS[31];
end else begin
C=|inputA;
outputBS=0;
Zero=1;
N=0;
end
end
5:begin //ROR
outputBS=inputA>>Bse%32;
aux1=inputA<<32-(Bse % 32);
outputBS=outputBS | aux1;
C=aux1[31];
Zero=zer;
N=outputBS[31];
end
6:begin //REV
outputBS[31:24]=inputA[7:0];
outputBS[23:16]=inputA[15:8];
outputBS[15:8]=inputA[23:16];
outputBS[7:0]=inputA[31:24];
end
7:begin //REV16
outputBS[31:24]=inputA[23:16];
outputBS[23:16]=inputA[31:24];
outputBS[15:8]=inputA[7:0];
outputBS[7:0]=inputA[15:8];
end
8:begin //REVSH
outputBS[31:16]=(inputA[7]) ? 16'hFFFF :16'h0;
outputBS[15:8]=inputA[7:0];
outputBS[7:0]=inputA[15:8];
end
default:begin
outputBS=Bse;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T, class U> T &ctmax(T &x, const U &y) { return x = max<T>(x, y); } template <class T, class U> T &ctmin(T &x, const U &y) { return x = min<T>(x, y); } int main() { cin.tie(0)->sync_with_stdio(0); cin.exceptions(ios::badbit | ios::failbit); int n, c1, c2; cin >> n >> c1 >> c2; vector<int> a(n); for (auto i = 0; i < n; ++i) { cin >> a[i]; } long long res = numeric_limits<long long>::max(); vector<int> primes; auto get_primes = [&](int x) { for (auto p = 2; p * p <= x; ++p) { if (x % p == 0) { primes.push_back(p); while (x % p == 0) { x /= p; } } } if (x >= 2) { primes.push_back(x); } }; get_primes(a.front() - 1), get_primes(a.front()), get_primes(a.front() + 1); get_primes(a.back() - 1), get_primes(a.back()), get_primes(a.back() + 1); sort(primes.begin(), primes.end()); primes.erase(unique(primes.begin(), primes.end()), primes.end()); for (auto p : primes) { array<long long, 3> dp{}; for (auto x : a) { array<long long, 3> dp_next{}; dp_next.fill(numeric_limits<long long>::max() / 2); if (x % p == 0) { ctmin(dp_next[0], dp[0]); ctmin(dp_next[2], min(dp[1], dp[2])); } ctmin(dp_next[1], min(dp[0], dp[1]) + c1); if ((x + 1) % p == 0 || (x - 1) % p == 0) { ctmin(dp_next[0], dp[0] + c2); ctmin(dp_next[2], min(dp[1], dp[2]) + c2); } swap(dp, dp_next); } ctmin(res, *min_element(dp.begin(), dp.end())); } cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[100] = {0, 4, 4, 4, 4, 4, 4, 4, 4, 4, 15, 4}; int n; int main() { scanf( %d , &n); if (n <= 10) puts( 0 ); else printf( %d n , a[n - 10]); }
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module debounce (
clk,
reset_n,
data_in,
data_out
);
parameter WIDTH = 32; // set to be the width of the bus being debounced
parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce
parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state
parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT))
input wire clk;
input wire reset_n;
input wire [WIDTH-1:0] data_in;
output wire [WIDTH-1:0] data_out;
reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1];
wire counter_reset [0:WIDTH-1];
wire counter_enable [0:WIDTH-1];
// need one counter per input to debounce
genvar i;
generate for (i = 0; i < WIDTH; i = i+1)
begin: debounce_counter_loop
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
counter[i] <= 0;
end
else
begin
if (counter_reset[i] == 1) // resetting the counter needs to win
begin
counter[i] <= 0;
end
else if (counter_enable[i] == 1)
begin
counter[i] <= counter[i] + 1'b1;
end
end
end
if (POLARITY == "HIGH")
begin
assign counter_reset[i] = (data_in[i] == 0);
assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0;
end
else
begin
assign counter_reset[i] = (data_in[i] == 1);
assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1;
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; bool isPrime(int x) { if (x == 1) return false; for (long long i = 2; i <= sqrt(x); i += 1) if (x % i == 0) return false; return true; } void print(int a[], int n) { for (long long i = 0; i < n; i += 1) cout << a[i] << ; } void iarr(int *a, int n) { for (long long i = 0; i < n; i += 1) cin >> a[i]; } long long power(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) res = ((res % 1000000007) * (a % 1000000007)) % 1000000007; a = ((a % 1000000007) * (a % 1000000007)) % 1000000007; b >>= 1; } return res; } long long numFactors(long long x) { long long cnt = 0; for (long long i = 1; i <= sqrt(x); i += 1) { if (x % i == 0) { if (x / i == i) cnt += 1; else cnt += 2; } } return cnt; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout << fixed; cout.precision(10); ; int n; cin >> n; int a[n]; iarr(a, n); long long cnt = 0; while (true) { int ind = -1, mx = a[0]; for (long long i = 1; i < n; i += 1) { if (a[i] >= mx) { ind = i; mx = a[i]; } } if (ind != -1) { a[ind]--; a[0]++; cnt++; } else if (ind == -1) { break; } } cout << cnt; return 0; }
|
#include <bits/stdc++.h> int cmp(const void *a, const void *b) { return *(int *)a - *(int *)b; } int main() { int a[55], b[55], m, i, j, map[55], n, x, y, s; while (~scanf( %d , &m)) { for (i = 0; i < m - 1; i++) { scanf( %d , &a[i]); } for (i = 0; i < m - 1; i++) { scanf( %d , &b[i]); } j = 0; for (i = 0; i < m; i++) { scanf( %d , &s); for (x = i; x < m - 1; x++) { s += b[x]; } for (y = 0; y < i; y++) { s += a[y]; } map[j++] = s; } qsort(map, j, sizeof(map[0]), cmp); printf( %d n , map[0] + map[1]); } }
|
#include <bits/stdc++.h> using namespace std; long long powr(long long exp) { if (exp == 1) return 2; if (exp % 2 == 0) { long long ret = (powr(exp / 2)) % 1000000007; ret = (ret * ret) % 1000000007; return ret; } long long ret = powr(exp / 2) % 1000000007; ret = (ret * ret * 2) % 1000000007; return ret; } int main() { string s; cin >> s; long long mul = 1; string s1 = ; for (int i = 0; i < s.size(); i++) { if (s[i] == a || s[i] == b ) s1 += s[i]; } s1 += b ; long long st = 1; for (int i = 0; i < s1.size(); i++) { if (s1[i] == b ) { mul = ((mul) * (st % 1000000007)) % 1000000007; st = 1; } else if (s1[i] == a ) { st++; } } mul = (mul - 1); if (mul < 0) mul += 1000000007; cout << mul; }
|
#include <bits/stdc++.h> using namespace std; int main() { int e, f; cin >> e >> f; cout << e + f << endl; return 0; }
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#include<bits/stdc++.h> using namespace std; #define task sol #define lb lower_bound #define ub upper_bound #define fi first #define se second #define pb push_back #define mp make_pair #define zs(v) ((int)(v).size()) #define BIT(x, i) (((x) >> (i)) & 1) #define CNTBIT __builtin_popcountll #define ALL(v) (v).begin(),(v).end() #define endl n typedef long double ld; typedef long long ll; typedef pair<int, int> pii; const ll base=331; const int dx[8]={0,-1,0,1,1,-1,-1,1}; const int dy[8]={-1,0,1,0,-1,-1,1,1}; int c[55][55]; int mod; ll dp[55][55*55]; ll fact[55]; int f[4005]; int n; void gogo() { cin>>n>>mod; dp[0][0]=1; for (int i=1;i<=n;++i) { for (int num=0;num<=n*n;++num) { for (int k=1;k<=i;++k) if (num+i-k<=n*n) (dp[i][num+i-k]+=dp[i-1][num])%=mod; } } for (int i=0;i<=n;++i) { c[i][0]=1; for (int j=1;j<=i;++j) c[i][j]=(c[i-1][j]+c[i-1][j-1])%mod; } fact[0]=1; for (int i=1;i<=n;++i) fact[i]=fact[i-1]*i%mod; int ans=0; for (int i=0;i<n;++i) { ll val=c[n][i]*fact[i]%mod; int len=n-i-1; int m=len*(len-1)/2; for (int i=0;i<=m;++i) f[i]=0; for (int inv1=0;inv1<=m;++inv1) { for (int inv2=0;inv2<=inv1;++inv2) { (f[inv1-inv2]+=dp[len][inv1]*dp[len][inv2]%mod)%=mod; } } for (int i=1;i<=m;++i) (f[i]+=f[i-1])%=mod; int value=0; for (int x=1;x<=len+1;++x) { for (int y=x+1;y<=len+1;++y) { assert(y-x>=0); if (m>y-x) (value+=(f[m]-f[y-x]+mod)%mod)%=mod; } } // cout<<value<<endl; ans=(ans+val*value%mod)%mod; } cout<<ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); if (fopen(task .inp , r )) { freopen(task .inp , r , stdin); freopen(task .out , w , stdout); } gogo(); }
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#include <bits/stdc++.h> using namespace std; void make_uni(vector<int> &v) { sort(v.begin(), v.end()); v.resize(unique(v.begin(), v.end()) - v.begin()); } int get(vector<int> &v, int d) { return lower_bound(v.begin(), v.end(), d) - v.begin(); } int getu(vector<int> &v, int d) { return upper_bound(v.begin(), v.end(), d) - v.begin(); } int n, k; vector<tuple<int, int, int> > que; int main() { scanf( %d %d , &n, &k); vector<int> c1; for (int i = 0, a, b, c; i < n; ++i) { scanf( %d %d %d , &a, &b, &c); c1.emplace_back(c); que.emplace_back(a, b, c); } make_uni(c1); vector<vector<int> > c2(c1.size()); for (int i = 0, a, b, c; i < n; ++i) { tie(a, b, c) = que[i]; c2[get(c1, c)].emplace_back(a + b); } for (int i = 0; i < c2.size(); ++i) make_uni(c2[i]); vector<vector<vector<int> > > c3(c2.size()); for (int i = 0; i < c3.size(); ++i) c3[i].resize(c2[i].size()); for (int i = 0, a, b, c; i < n; ++i) { tie(a, b, c) = que[i]; int k1 = get(c1, c); int k2 = get(c2[k1], a + b); for (int i = k2 + 1; i; i -= i & -i) c3[k1][i - 1].emplace_back(a); } for (int i = 0; i < c3.size(); ++i) for (int j = 0; j < c3[i].size(); ++j) make_uni(c3[i][j]); vector<vector<vector<int> > > t(c3.size()); for (int i = 0; i < c3.size(); ++i) { t[i].resize(c3[i].size()); for (int j = 0; j < t[i].size(); ++j) t[i][j].resize(c3[i][j].size()); } sort(que.begin(), que.end(), [&](const tuple<int, int, int> &a, const tuple<int, int, int> &b) { return get<0>(a) < get<0>(b); }); long long sum = 0; for (auto &x : que) { int a, b, c; tie(a, b, c) = x; for (int l = get(c1, c - k), r = getu(c1, c + k); l != r; ++l) for (int i = get(c2[l], a) + 1; i <= c2[l].size(); i += i & -i) for (int j = get(c3[l][i - 1], a - b) + 1; j <= c3[l][i - 1].size(); j += j & -j) sum += t[l][i - 1][j - 1]; int p = get(c1, c); for (int i = get(c2[p], a + b) + 1; i; i -= i & -i) for (int j = get(c3[p][i - 1], a) + 1; j; j -= j & -j) t[p][i - 1][j - 1]++; } printf( %lld n , sum); }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NOR4_PP_SYMBOL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_PP_SYMBOL_V
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_TB_V
`define SKY130_FD_SC_LP__O32A_TB_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__o32a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_TB_V
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, m; cin >> n >> m; long long vmax = n - (m - 1); long long kmax = vmax * (vmax - 1) / 2; long long vmin = n / m; long long vmin_add = n - vmin * m; long long kmin = (m - vmin_add) * vmin * (vmin - 1) / 2 + vmin_add * (vmin + 1) * vmin / 2; cout << kmin << << kmax; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1005; bool vis[N]; vector<int> temp; int n, t, num; int ans[N], L[N], R[N]; void pr() { return; for (int i = 0; i < n; i++) printf( %d , ans[i]); puts( ); puts( ); } void pr2() { return; printf( %d n , temp.size()); for (int i = 0; i < temp.size(); i++) printf( %d , temp[i]); puts( ); puts( ); } void check() { for (int i = 0; i < n; i++) { int c = 0; for (int j = 0; j < i; j++) c += (ans[j] > ans[i]); if (c != L[i]) { printf( NO ); exit(0); } c = 0; for (int j = i; j < n; j++) c += (ans[j] > ans[i]); if (c != R[i]) { printf( NO ); exit(0); } } } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &L[i]); for (int i = 0; i < n; i++) scanf( %d , &R[i]); if (L[0] != 0 || R[n - 1] != 0) { printf( NO ); return 0; } num = 0; pr(); while (num < n) { temp.clear(); for (int i = 0; i < n; i++) { if (L[i] + R[i] == num) { temp.push_back(i); vis[i] = 1; } } if (temp.empty()) { printf( NO ); return 0; } pr2(); for (int i = 0; i < temp.size(); i++) { int x = temp[i]; ans[x] = n - num; } pr(); num += temp.size(); } check(); puts( YES ); for (int i = 0; i < n; i++) printf( %d , ans[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, s[111]; int f[20][1 << 20]; int bitc[1 << 20]; int act[22]; int who[22]; int picks[22]; inline void upd_max(int i, int j, int val) { if (f[i][j] > 1000000000) f[i][j] = val; else f[i][j] = max(f[i][j], val); } inline void upd_min(int i, int j, int val) { if (f[i][j] > 1000000000) f[i][j] = val; else f[i][j] = min(f[i][j], val); } int solve(int step, int ban) { if (step == n) return 0; if (f[step][ban] < 1000000000) return f[step][ban]; int pick, left; for (pick = 0, left = picks[step];; ++pick) { if (!(ban & (1 << pick))) --left; if (left == -1) break; } if (act[step] == 1) { if (who[step] == 1) { upd_max(step, ban, solve(step + 1, ban) + s[pick]); } else { upd_min(step, ban, solve(step + 1, ban) - s[pick]); } } else { for (; pick < n; ++pick) { if (!(ban & (1 << pick))) { if (who[step] == 1) { upd_max(step, ban, solve(step + 1, ban | (1 << pick))); } else { upd_min(step, ban, solve(step + 1, ban | (1 << pick))); } } } } return f[step][ban]; } int main() { cin >> n; for (int i = 0; i < n; ++i) cin >> s[i]; sort(s, s + n); reverse(s, s + n); cin >> m; if (n > m) n = m; for (int i = 0; i < m; ++i) { char ch; cin >> ch; if (ch == p ) act[i] = 1; else act[i] = 0; cin >> who[i]; if (i) picks[i] = picks[i - 1] + act[i - 1]; } memset(f, 63, sizeof(f)); bitc[0] = 0; for (int i = 1; i < (1 << n); ++i) { bitc[i] = bitc[i / 2] + i % 2; } cout << solve(0, 0) << endl; }
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#include <bits/stdc++.h> #pragma GCC target( sse4,avx ) const int inf = 100000; int rec(size_t gl, std::vector<int>& odd, std::vector<bool>& flags, std::vector<std::vector<int>>& graph) { if (gl == odd.size()) { return 0; } if (flags[gl]) { return rec(gl + 1, odd, flags, graph); } int res = 1000000000; for (size_t i = gl + 1; i < odd.size(); i++) { if (!flags[i]) { flags[i] = true; res = std::min(res, graph[odd[gl]][odd[i]] + rec(gl + 1, odd, flags, graph)); flags[i] = false; } } return res; } void run(std::istream& in, std::ostream& out) { int n, m; in >> n >> m; std::vector<std::vector<int>> graph(n, std::vector<int>(n, inf)); for (int i = 0; i < n; i++) graph[i][i] = 0; std::vector<int> degs(n); int64_t sum = 0; for (int i = 0; i < m; i++) { int x, y, w; in >> x >> y >> w; x--; y--; degs[x]++; degs[y]++; sum += w; graph[x][y] = std::min(graph[x][y], w); graph[y][x] = std::min(graph[y][x], w); } for (size_t i = 0; i < n; i++) { for (size_t j = 0; j < n; j++) { for (size_t k = 0; k < n; k++) { if (graph[j][k] > graph[j][i] + graph[i][k]) { graph[j][k] = graph[j][i] + graph[i][k]; } } } } for (size_t i = 0; i < n; i++) { if (graph[0][i] == inf && degs[i] != 0) { out << -1 << std::endl; return; } } std::vector<int> odd; for (size_t i = 0; i < n; i++) { if ((degs[i] % 2) != 0) { odd.push_back(i); } } std::vector<bool> flags(odd.size()); sum += rec(0, odd, flags, graph); out << sum << std::endl; } int main() { std::cin.sync_with_stdio(false); std::cin.tie(nullptr); run(std::cin, std::cout); return 0; }
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// test_psi2c.v
`timescale 1 ns / 1 ps
module test_psi2c;
// avalon clock interface
reg clk = 0;
reg reset = 1;
// avalon mm slave
reg [2:0]address = 3'bxxx;
reg read = 0;
wire [31:0]readdata;
reg write = 0;
reg [31:0]writedata = 32'hxxxx_xxxx;
// conduit
reg sync = 0;
wire phase;
wire send;
wire sda;
wire rda = sda;
localparam s = 31'h0000_0800; // i2c start
localparam p = 31'h0000_0400; // i2c stop
task Write(input [2:0]a, input [31:0]d);
begin
@(posedge clk) #1;
address = a;
writedata = d;
write = 1;
@(posedge clk) #1;
address = 3'bxxx;
writedata = 32'hxxxx_xxxx;
write = 0;
end
endtask
task Read(input [2:0]a);
begin
@(posedge clk) #1;
address = a;
read = 1;
@(posedge clk) #1;
address = 3'bxxx;
read = 0;
end
endtask
always #10 clk = !clk;
always @(posedge clk) sync = !sync;
assign phase = !sync;
initial
begin
#60 reset = 0;
#200 Write(0, 0);
Write(1, s + 'h2aa);
Write(1, 'h2aa);
Write(1, p + 'h2aa);
Write(0, 1);
#200 Read(0);
#1150 Read(0);
Write(3, 'h55);
Write(2, 'hca);
Write(4, 'h35);
Write(0, 1);
#1400 $stop(2);
end
psi2c DUT
(
.csi_clock_clk(clk),
.csi_clock_reset(reset),
.avs_ctrl_address(address),
.avs_ctrl_read(read),
.avs_ctrl_readdata(readdata),
.avs_ctrl_write(write),
.avs_ctrl_writedata(writedata),
.sync(sync),
.phase(phase),
.send(send),
.sda(sda),
.rda(rda)
);
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, a, b, t; string str; cin >> n >> a >> b >> t >> str; str += str; long long len = 1, l = n, r, remain = t - 1 - (str[n] == w ) * b, ans = 1; if (remain < 0) { cout << 0 n ; return 0; } while (len < n) { long long require = 2 * a + 1 + (str[l - 1] == w ) * b; if (remain < require) { break; } else { l--; len++; remain -= require; } } for (r = n + 1; r < str.size(); r++) { remain -= a + 1 + (str[r] == w ) * b; while (r - l + 1 > n || (l < n && remain < 0)) { remain += 2 * a + 1 + (str[l] == w ) * b; l++; } if (l >= n && remain < 0) break; ans = max(ans, r - l + 1); } len = 1, l = r = n, remain = t - 1 - (str[n] == w ) * b; while (len < n) { long long require = 2 * a + 1 + (str[r + 1] == w ) * b; if (remain < require) { break; } else { r++; len++; remain -= require; } } for (l = n - 1; l > 0; l--) { remain -= a + 1 + (str[l] == w ) * b; while (r - l + 1 > n || (r > n && remain < 0)) { remain += 2 * a + 1 + (str[r] == w ) * b; r--; } if (r <= n && remain < 0) break; ans = max(ans, r - l + 1); } cout << ans << n ; }
|
#include <bits/stdc++.h> namespace IO { inline char gc() { static const int Rlen = 1 << 22 | 1; static char buf[Rlen], *p1, *p2; return (p1 == p2) && (p2 = (p1 = buf) + fread(buf, 1, Rlen, stdin), p1 == p2) ? EOF : *p1++; } template <typename T> T get_integer() { char c; bool f = false; while (!isdigit(c = gc())) f = c == - ; T x = c ^ 48; while (isdigit(c = gc())) x = ((x + (x << 2)) << 1) + (c ^ 48); return f ? -x : x; } inline int gi() { return get_integer<int>(); } } // namespace IO using namespace IO; using std::cerr; using std::cout; using pii = std::pair<int, int>; const int N = 1.5e5 + 7; int n, m, k; long long ans; std::vector<int> G[N]; std::vector<pii> Q[N]; int fa[N], in[N], out[N]; int sz[N], son[N], top[N]; int d[N], ps[N], dfc; void dfs1(int u, int p) { fa[u] = p, d[u] = d[p] + 1; for (int v : G[u]) if (v != p) { dfs1(v, u); sz[u] += sz[v]; if (sz[v] > sz[son[u]]) son[u] = v; } ++sz[u]; } void dfs2(int u, int tp) { top[u] = tp; ps[in[u] = ++dfc] = u; if (son[u]) dfs2(son[u], tp); for (int v : G[u]) if (v != fa[u] && v != son[u]) dfs2(v, v); out[u] = dfc; } int LCA(int u, int v) { while (top[u] != top[v]) d[top[u]] < d[top[v]] ? v = fa[top[v]] : u = fa[top[u]]; return d[u] < d[v] ? u : v; } int jump(int u, int k) { while (k > d[u] - d[top[u]]) { k -= d[u] - d[top[u]] + 1; u = fa[top[u]]; } return ps[in[u] - k]; } namespace SGT { const int N = ::N * 40; int lc[N], rc[N], sm[N], ct; void ins(int &u, int l, int r, int p) { if (!u) u = ++ct; ++sm[u]; if (l == r) return; int m = (l + r) >> 1; p <= m ? ins(lc[u], l, m, p) : ins(rc[u], m + 1, r, p); } int qy(int u, int l, int r, int ql, int qr) { if ((ql <= l && r <= qr) || !u) return sm[u]; int m = (l + r) >> 1; if (qr <= m) return qy(lc[u], l, m, ql, qr); if (m < ql) return qy(rc[u], m + 1, r, ql, qr); return qy(lc[u], l, m, ql, qr) + qy(rc[u], m + 1, r, ql, qr); } void merge(int &u, int v) { if (!u || !v) { u |= v; return; } merge(lc[u], lc[v]); merge(rc[u], rc[v]); sm[u] += sm[v]; } void ins(int &u, int p) { ins(u, 1, n, p); } int qy(int u, int l, int r) { return qy(u, 1, n, l, r); } void clear() { while (ct) lc[ct] = rc[ct] = sm[ct] = 0, --ct; } } // namespace SGT namespace BIT { int tr[N]; void add(int l, int r) { for (int register p = l; p <= n; p += p & -p) ++tr[p]; for (int register p = r + 1; p <= n; p += p & -p) --tr[p]; } int qy(int p) { int r = 0; for (; p; p &= p - 1) r += tr[p]; return r; } } // namespace BIT int rt[N]; std::vector<int> q[N]; void solve_q(int u, int Rt) { rt[u] = 0; int od = std::max(0, k - d[u] + d[Rt]); for (int v : q[u]) { if (d[v] >= od + d[Rt]) { int p = jump(v, d[v] - d[Rt] - od); ans += SGT::qy(rt[u], in[p], out[p]); } SGT::ins(rt[u], in[v]); } for (int w : G[u]) if (Rt != u || w != son[u]) { solve_q(w, Rt); if (q[w].size() > q[u].size()) q[u].swap(q[w]), std::swap(rt[u], rt[w]); for (int v : q[w]) { if (d[v] >= od + d[Rt]) { int p = jump(v, d[v] - d[Rt] - od); ans += SGT::qy(rt[u], in[p], out[p]); } q[u].push_back(v); } q[w].clear(); SGT::merge(rt[u], rt[w]); } } void solve(int u) { for (int v : G[u]) solve(v); for (auto &t : Q[u]) ans += BIT::qy(in[t.second]); for (auto &t : Q[u]) if (d[t.second] >= d[u] + k) { int p = jump(t.second, d[t.second] - d[u] - k); BIT::add(in[p], out[p]); } for (auto &t : Q[u]) ans += BIT::qy(in[t.first]); for (auto &t : Q[u]) if (d[t.first] >= d[u] + k) { int p = jump(t.first, d[t.first] - d[u] - k); BIT::add(in[p], out[p]); } for (auto &t : Q[u]) q[t.first].push_back(t.second); solve_q(u, u); q[u].clear(); SGT::clear(); } void Main() { n = gi(), m = gi(), k = gi(); for (int register i = 1; i < n; ++i) { int u = gi(), v = gi(); G[u].push_back(v); G[v].push_back(u); } dfs1(1, 0); dfs2(1, 1); for (int register i = 2; i <= n; ++i) G[i].erase(std::find(G[i].begin(), G[i].end(), fa[i])); for (int register i = 1; i <= m; ++i) { int u = gi(), v = gi(); if (in[u] > in[v]) std::swap(u, v); if (in[v] > out[u]) std::swap(u, v); Q[LCA(u, v)].push_back({u, v}); } solve(1); cout << ans << n ; } inline void file() {} signed main() { file(); Main(); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool solve(long long n, long long k) { int r = n % k; long long turn = n / k; if (turn % 2 == 1) { return false; } return true; } int main() { long long n, k; cin >> n >> k; if (!solve(n, k)) cout << YES << endl; else cout << NO << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVPWRVGND_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__TAPVPWRVGND_FUNCTIONAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvpwrvgnd (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVPWRVGND_FUNCTIONAL_PP_V
|
// --------------------------------------------------------------------
// Module: Sound.v
// Description: Sound module. This is NOT a sound blaster emulator.
// This module produces simple sounds by implementing a simple interface,
// The user simply writes a byte of data to the left and/or right channels.
// Then poll the status register which will raise a flag when ready for the
// next byte of data. Alternatively, it can generate an interupt to request
// the next byte.
//
// Sound uses 16 I/O addresses 0x0nn0 to 0x0nnF, nn can be anything
//
// I/O Address Description
// ----------- ------------------
// 0x0210 Left Channel
// 0x0211 Right Channel
// 0x0212 High byte of timing increment
// 0x0213 Low byte of timing increment
// 0x0215 Control, 0x01 to enable interupt, 0x00 for polled mode
// 0x0217 Status, 0x80 when ready for next data, else 0x00
//
// --------------------------------------------------------------------
module pcm_dac (
input clk, // Main Clock
input [15:0] dac_L, // Left DAC
input [15:0] dac_R, // Right DAC
input wren_L, // Write data to Left DAC
input wren_R, // Write data to Right DAC
output audio_L, // Left PCM audio output
output audio_R // Right PCM audio output
);
// --------------------------------------------------------------------
// Pulse the DAC data into the DAC registers
// --------------------------------------------------------------------
always @(posedge wren_L) begin
dsp_audio_l <= {~dac_L[15], dac_L[14:0]};
end
always @(posedge wren_R) begin
dsp_audio_r <= {~dac_R[15], dac_R[14:0]};
end
// --------------------------------------------------------------------
// DAC CLock Generation Section:
// We need to divide down the clock for PCM, clk = 50Mhz
// then 50,000,000 / 256 = 195,312.5Hz which is ~2X highest CODEC rate (96Khz)
// 0 = 2 => 25,000,000.00 Hz
// 1 = 4 => 12,500,000.00 Hz
// 2 = 8 => 6,250,000.00 Hz
// 3 = 16 => 3,125,000.00 Hz
// 4 = 32 => 1,562,500.00 Hz
// 5 = 64 => 781,250.00 Hz
// 6 = 128 => 390,625.00 Hz
// 7 = 256 => 195,312.50 Hz
// 8 = 512 => 97,656.25 Hz
// --------------------------------------------------------------------
wire dac_clk = clkdiv[4];
reg [8:0] clkdiv;
always @(posedge clk) clkdiv <= clkdiv + 9'd1;
// --------------------------------------------------------------------
// Audio Generation Section
// --------------------------------------------------------------------
reg [15:0] dsp_audio_l;
reg [15:0] dsp_audio_r;
dac16 left (.clk(dac_clk),.DAC_in(dsp_audio_l),.audio_out(audio_L));
dac16 right(.clk(dac_clk),.DAC_in(dsp_audio_r),.audio_out(audio_R));
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Module: DAC16.v
// Description: 16 bit pcm DAC
// --------------------------------------------------------------------
module dac16(
input clk,
input [15:0] DAC_in,
output audio_out
);
reg [16:0] DAC_Register;
always @(posedge clk) DAC_Register <= DAC_Register[15:0] + DAC_in;
assign audio_out = DAC_Register[16];
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; struct Tree { int ch[10]; int len; int fail; } T[100010]; int tot; void insert(char* str, int len) { int now = 0; for (int i = 0; i < len; i++) { if (!T[now].ch[str[i] - 0 ]) { T[now].ch[str[i] - 0 ] = ++tot; T[tot].len = i + 1; } now = T[now].ch[str[i] - 0 ]; } return; } queue<int> q; void bfs() { for (int i = 0; i < 10; i++) if (T[0].ch[i]) { q.push(T[0].ch[i]); T[T[0].ch[i]].fail = 0; } while (!q.empty()) { int u = q.front(); q.pop(); for (int i = 0; i < 10; i++) if (T[u].ch[i]) { T[T[u].ch[i]].fail = T[T[u].fail].ch[i]; q.push(T[u].ch[i]); } else T[u].ch[i] = T[T[u].fail].ch[i]; } return; } int d, D; int dp[61][60010][2][2]; void add(int& x, int y) { x += y; if (x >= 1000000007) x -= 1000000007; return; } int solve(int* a) { memset(dp, 0, sizeof(dp)); dp[d][0][0][0] = 1; for (int i = d; i >= 1; i--) for (int j = 0; j <= tot; j++) for (int k = 0; k < 2; k++) { for (int l = 0; l <= a[i]; l++) { int v = T[j].ch[l]; int tk = k || (T[v].len >= D); int o = (l < a[i]); add(dp[i - 1][v][tk][o], dp[i][j][k][0]); } for (int l = 0; l <= 9; l++) { int v = T[j].ch[l]; int tk = k || (T[v].len >= D); add(dp[i - 1][v][tk][1], dp[i][j][k][1]); } } int ans = 0; for (int i = 0; i <= tot; i++) { add(ans, dp[0][i][1][0]); add(ans, dp[0][i][1][1]); } return ans; } char x[61], y[61], str[1010]; int tmp[61]; int main() { scanf( %s , str); scanf( %s , x + 1); scanf( %s , y + 1); int len = strlen(str); d = strlen(x + 1); D = d / 2; for (int i = 0; i + D <= len; i++) insert(str + i, D); bfs(); for (int i = 1; i <= d; i++) tmp[i] = x[d - i + 1] - 0 ; tmp[1]--; for (int i = 1; i <= d; i++) if (tmp[i] < 0) { tmp[i + 1]--; tmp[i] += 10; } int ans1 = solve(tmp); for (int i = 1; i <= d; i++) tmp[i] = y[d - i + 1] - 0 ; int ans2 = solve(tmp); printf( %d n , (ans2 - ans1 + 1000000007) % 1000000007); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVER_BEHAVIORAL_PP_V
/**
* busdriver: Bus driver (pmoshvt devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busdriver (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int n, k; vector<char> s; int main() { cin >> n >> k; if (k > n) { cout << -1; cin >> n; return 0; } if (k == 1 && n > 1) { cout << -1; cin >> n; return 0; } for (int i = 0; i < n; i++) { if (i % 2 == 0) { s.push_back( a ); } else { s.push_back( b ); } } int x = 98 + k - 2; for (int i = n - 1; i >= n - k + 2; i--) { s[i] = (char)x; x--; } for (int i = 0; i < n; i++) { cout << s[i]; } cin >> n; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGRBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SREGRBP_PP_SYMBOL_V
/**
* sregrbp: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sregrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{scanchain|Scan Chain}}
input ASYNC,
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGRBP_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//-----------------------------------------------
// Company: agh
//-----------------------------------------------
module i_mem
(
input [7:0]address,
output [31:0]data
);
//-----------------------------------------------
//instruction memory
wire [31:0]program[255:0];
//assign program[0]=32'h0036e00c; // movi R0, 12
//assign program[1]=32'h0036e10d; // movi R1, 13
//assign program[2]=32'h00101000; // add R0, R0, R1
//assign program[3]=32'h0010e10e; // addi R1, R0, 14
//assign program[4]=32'h00001000; // and R0, R0, R1
//assign program[5]=32'h0000e10b; // andi R1, R0, 11
//assign program[6]=32'h0136e700; // jmpi 0
//assign program[7]=32'h00360000; // nop
assign program[0]=32'h0036e000; // movi R0, 0
assign program[1]=32'h0036e104; // movi R1, 4
assign program[2]=32'h0010e001; // addi R0, R0, 1
assign program[3]=32'h00001200; // and R2, R0, R1
assign program[4]=32'h0332e702; // jz R2, 2
assign program[5]=32'h0036e301; // movi R3, 1
//-----------------------------------------------
assign data=program[address];
//-----------------------------------------------
endmodule
//-----------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_2_V
`define SKY130_FD_SC_MS__SDFXBP_2_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog wrapper for sdfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfxbp_2 (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:08:20 05/21/2015
// Design Name:
// Module Name: sobel
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sobel #(
parameter [9:0] H_SIZE = 83 // domylny rozmiar obrazu to szeroko = 64 piksele
)(
input clk,
input ce,
input rst,
input [7:0] in_image,
input in_de,
input in_vsync,
input in_hsync,
output [7:0] out_sobel,
output out_de,
output out_vsync,
output out_hsync
);
wire [10:0] delay_line11;
reg [10:0] delay_line12 [2:0];
wire [10:0] delay_line21;
reg [10:0] delay_line22 [2:0];
wire [10:0] delay_line31;
reg [10:0] delay_line32 [2:0];
reg signed [11:0] sum_linesX[2:0];
reg signed [11:0] sum_finalX;
reg signed [11:0] sum_linesY[2:0];
reg signed [11:0] sum_finalY;
assign delay_line11 = {in_image, in_de, in_hsync, in_vsync};
//pojedyncze opoznienia dla piksela
genvar i;
generate
always @(posedge clk)
begin
delay_line12[0] <= delay_line11;
delay_line22[0] <= delay_line21;
delay_line32[0] <= delay_line31;
delay_line12[1] <= delay_line12[0];
delay_line22[1] <= delay_line22[0];
delay_line32[1] <= delay_line32[0];
delay_line12[2] <= delay_line12[1];
delay_line22[2] <= delay_line22[1];
delay_line32[2] <= delay_line32[1];
end
endgenerate;
wire [9:0] dummy;//zbdne dane
delayLinieBRAM_WP long_delay1
(
.clk(clk),
.rst(1'b0),
.ce(1'b1),
.din({5'b0, delay_line12[2]}),
.dout({dummy[4:0], delay_line21}),
.h_size(H_SIZE - 3)
);
delayLinieBRAM_WP long_delay2
(
.clk(clk),
.rst(1'b0),
.ce(1'b1),
.din({5'b0, delay_line22[2]}),
.dout({dummy[9:5], delay_line31}),
.h_size(H_SIZE - 3)
);
always @(posedge clk)
begin
//wyznaczanie sum
//if(context_valid) begin
//sobel Y
//-A - 2B - C
sum_linesY[0] <= - {4'b0, delay_line12[0][10:3]} - {3'b0, delay_line12[1][10:3], 1'b0} - {4'b0,delay_line12[2][10:3]};
//0
sum_linesY[1] <= 12'b0;
//A + 2B + C
sum_linesY[2] <= {4'b0, delay_line32[0][10:3]} + {3'b0, delay_line32[1][10:3], 1'b0} + {4'b0,delay_line32[2][10:3]};
sum_finalY <= sum_linesY[0] + sum_linesY[1] + sum_linesY[2];
//sobel X
//-A + 0 + C
sum_linesX[0] <= - {4'b0, delay_line12[0][10:3]} + {4'b0,delay_line12[2][10:3]};
//-2A + 0 +2C
sum_linesX[1] <= - {3'b0, delay_line22[0][10:3], 1'b0} + {3'b0,delay_line22[2][10:3], 1'b0};
////-A + 0 + C
sum_linesX[2] <= -{4'b0, delay_line32[0][10:3]} + {4'b0,delay_line32[2][10:3]};
sum_finalX <= sum_linesX[0] + sum_linesX[1] + sum_linesX[2];
if(sum_finalY < 12'b0) sum_finalY <= -sum_finalY;
if(sum_finalX < 12'b0) sum_finalX <= -sum_finalX;
//end
end
wire context_valid;
assign context_valid = delay_line12[0][1] & delay_line12[1][1] & delay_line12[2][1] &
delay_line22[0][1] & delay_line22[1][1] & delay_line22[2][1] &
delay_line32[0][1] & delay_line32[1][1] & delay_line32[2][1];
wire [2:0] d_dhv;
delay #
(
.N(3),
.DELAY(4)
)
dhv
(
.d(delay_line22[2][2:0]),
.ce(1'b1),
.clk(clk),
.q({d_dhv})
);
assign out_de = d_dhv[2];
assign out_hsync = d_dhv[1];
assign out_vsync = d_dhv[0];
reg signed[11:0] sobel_latch = 0;
always @(posedge clk)
begin
/*if(context_valid)*/ sobel_latch <= sum_finalX + sum_finalY;
end;
assign out_sobel = sobel_latch[10:3];
endmodule
|
#include <bits/stdc++.h> using namespace std; int mult(int a, int b) { long long res = ((long long)a * b) % 1000000007; return res; } int binaryPow(int n, int p) { int acc = 1; while (p) { if (p & 1) acc = mult(acc, n); n = mult(n, n); p /= 2; } return acc; } int modularInv(int n) { return binaryPow(n, 1000000007 - 2); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int k, pa, pb; cin >> k >> pa >> pb; int pd = modularInv(pa + pb); int dp[k + 1][k + 1]; for (int i = k; i >= 1; i--) { for (int j = k; j >= 0; j--) { if (i + j < k) { dp[i][j] = mult( (mult(pa, dp[i + 1][j]) + mult(pb, dp[i][i + j])) % 1000000007, pd); } else { dp[i][j] = (i + j + mult(pa, modularInv(pb))) % 1000000007; } } } cout << dp[1][0] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int i, n, k; double jumlah, x[101], y[101]; int main() { scanf( %d %d , &n, &k); for (i = 1; i <= n; ++i) { scanf( %lf %lf , &x[i], &y[i]); } for (i = 1; i < n; ++i) { jumlah += sqrt(((x[i] - x[i + 1]) * (x[i] - x[i + 1])) + ((y[i] - y[i + 1]) * (y[i] - y[i + 1]))); } jumlah = ((jumlah / 50) * k); printf( %.9lf n , jumlah); }
|
//SAGAR SINGH // #pragma GCC optimize( Ofast ) // #pragma GCC target( avx,avx2,fma ) // #pragma GCC optimization( unroll-loops ) #include<bits/stdc++.h> using namespace std; #define fastio ios_base::sync_with_stdio;cin.tie(NULL);cout.tie(0); #define ll long long #define ld long double #define rep(i,a,b) for(ll i=a;i<b;i++) //rep(i,0,n) #define repr(i,a,b) for(ll i=a;i>=b;i--)//repr(i,n-1,0) #define repit(it,a) for(auto it=(a).begin();it!=(a).end();it++)//repr(i,n,0) #define vll vector<long long> #define vpl vector<pair<ll,ll> > #define sll set<long long> #define msll multiset<long long> #define mll map<ll,ll> #define mmll multimap<ll,ll> #define all(x) x.begin(),x.end() #define rall(x) x.rbegin(),x.rend() #define get(x) getline(cin,x) #define in(v) for(auto &x:v) cin>>x; #define out(v) for(auto x:v) {cout<<x<< ;} cout<< n ; #define str string #define pb push_back #define ins insert #define lb lower_bound #define ub upper_bound #define ff first #define ss second /*--- bit-stuff ----*/ #define setbits(a) ( __builtin_popcountll(a)) #define right(a) (__builtin_ctzll(a)) #define left(a) (__builtin_clzll(a)) #define parity(a) (__builtin_parityll(a)) #define TRACE #ifdef TRACE #define trace(...) __f(#__VA_ARGS__, __VA_ARGS__) template <typename Arg1> void __f(const char* name, Arg1&& arg1){ cout << name << : << arg1 << endl; //use cerr if u want to display at the bottom } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args){ const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1<< | ;__f(comma+1, args...); } #else #define trace(...) #endif const ll mod = 1e9+7; const ll N = 1e5+1; const ll INF = 1e18; const ll NINF = -1e18; void solve(){ ll n;cin>>n; vll v(n);in(v); str s; rep(i,0,n) s.pb( 0 ); ll cur=0; ll i=n-1; while(i>=0){ cur=max({cur,v[i],(ll)0}); if(cur>0) s[i]= 1 ; else s[i]= 0 ; i--; cur--; } out(s); } int main(){ ios_base::sync_with_stdio; cin.tie(NULL);cout.tie(0); ll t=1; cin>>t; while(t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; double A[1010], B[1010]; double p[1010][1010]; double dis(int u) { return (B[u] + 1) / (1 - A[u]); } int mark[1010]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { scanf( %lf , &p[i][j]); p[i][j] /= 100; } for (int i = 1; i <= n - 1; i++) A[i] = 1; A[n] = 0, B[n] = -1; for (int k = 1; k <= n; k++) { int u = -1; for (int i = 1; i <= n; i++) { if ((u == -1 || dis(i) < dis(u) && !mark[i])) u = i; } mark[u] = 1; for (int v = 1; v <= n; v++) { if (mark[v]) continue; B[v] += A[v] * p[v][u] * dis(u); A[v] *= (1 - p[v][u]); } } printf( %.10f n , dis(1)); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, p, dp[2][110][110][110], ans; const int mod = 1e9 + 7; int main() { scanf( %d%d%d , &n, &m, &p); for (int i = 1; i <= n; i++) dp[0][i][i][1] = 1; for (int i = 0; i < m - 1; i++) { memset(dp[!(i & 1)], 0, sizeof(dp[!(i & 1)])); for (int j = 1; j <= n; j++) for (int k = 1; k <= j; k++) for (int s = 1; s <= p; s++) if (dp[i & 1][j][k][s]) { int ns = s; for (int k2 = k; k2 <= n - j; k2++) { if (k2 > k) ns *= (k2 - 1), ns /= (k2 - k); if (ns > p) break; (dp[!(i & 1)][j + k2][k2 - k][ns] += dp[i & 1][j][k][s]) %= mod; } } for (int j = 1; j <= n; j++) for (int s = 1; s <= p; s++) (ans += 1ll * (m - i - 1) * dp[!(i & 1)][j][0][s] % mod) %= mod; } return printf( %d , ans), 0; }
|
#include <bits/stdc++.h> using namespace std; long long A[200005]; long long fast_pow(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) res = (res * a) % 1000000007; a = (a * a) % 1000000007; b >>= 1; } return res; } int main() { long long div = 1, num = 1; int n; cin >> n; for (int i = 0; i < n; i++) { cin >> A[i]; num = (num * A[i]) % 1000000007; } sort(A, A + n); int idx = 0; bool chk = true; while (idx < n) { long long p = A[idx]; long long cnt = 0; while (idx < n && p == A[idx]) { idx++; cnt++; } div = (div * (cnt + 1LL)) % (2LL * (1000000007 - 1)); chk = (chk && (cnt % 2 == 0)); } div = (div % ((1000000007 - 1) * 2LL)) / 2; long long ans = fast_pow(num, div); if (chk) { idx = 0; while (idx < n) { long long p = A[idx]; long long cnt = 0; while (idx < n && p == A[idx]) { idx++; cnt++; } ans = (ans * fast_pow(p, cnt / 2)) % 1000000007; } } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_TB_V
`define SKY130_FD_SC_HDLL__CONB_TB_V
/**
* conb: Constant value, low, high outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__conb.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire HI;
wire LO;
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hdll__conb dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .HI(HI), .LO(LO));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_TB_V
|
#include <bits/stdc++.h> using namespace std; int fastio() { ios_base::sync_with_stdio(false); cout << fixed << setprecision(10); cin.tie(nullptr); return 0; } int __fastio = fastio(); void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } void solve() { int n, m; cin >> n >> m; vector<int> res(n + 1); set<int> alive; for (int i = 1; i <= n; i++) alive.insert(i); vector<tuple<int, int, int>> events; for (int i = 0; i < m; i++) { int l, r, x; cin >> l >> r >> x; events.emplace_back(l, r, x); } for (auto [l, r, x] : events) { auto lb = alive.lower_bound(l); vector<int> killed; while (lb != alive.end() && *lb <= r) { killed.push_back(*lb); ++lb; } for (auto &k : killed) { if (k != x) { res[k] = x; alive.erase(k); } } } for (int i = 1; i <= n; i++) cout << res[i] << ; } int main() { int t = 1; while (t--) { solve(); } }
|
/*
* This program is derived from iverilog issue # .
*/
`timescale 1ns/1ns
module verilog_test ();
reg [24:0] APAD;
wire [24:0] AIN;
initial begin
// $dumpfile("dumpfile.vcd");
// $dumpvars;
APAD=25'h1ffffff;
#21 if (AIN !== APAD) begin
$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
$finish;
end
#79
APAD=25'h1555555;
#19 if (AIN !== 25'h1ffffff) begin
$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
$finish;
end
#2 if (AIN !== 25'h1555555) begin
$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
$finish;
end
#79
APAD=25'h0aaaaaa;
#19 if (AIN !== 25'h1555555) begin
$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
$finish;
end
#2 if (AIN !== 25'h0aaaaaa) begin
$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
$finish;
end
#79
APAD=25'h1555555;
#19 if (AIN !== 25'h0aaaaaa) begin
$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
$finish;
end
#2 if (AIN !== 25'h1555555) begin
$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
$finish;
end
#79
APAD=25'h0aaaaaa;
#19 if (AIN !== 25'h1555555) begin
$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
$finish;
end
#2 if (AIN !== 25'h0aaaaaa) begin
$display("FAILED -- APAD=%b, AIN=%b, time=%0t", APAD, AIN, $time);
$finish;
end
$display("PASSED");
end
assign #20 AIN= APAD;
endmodule
|
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