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// Author: Vinay Khilwani // Language: C++ // @vok8: Codeforces, AtCoder, LeetCode, HackerEarth, TopCoder, Google, FB, CSES, Spoj, GitHub // @vok_8: CodeChef, GFG // @vok8_khilwani: HackerRank // Never Stop Trying. // Trying to be Better than Myself. // while(true) // { // if(AC) // { // break; // } // else if(Contest Over) // { // Try. // Check out Editorial. // Understand. // Find out your Mistake. // Learn the topic (if new). // Solve Problems on that topic (if new). // Upsolve that problem. // break; // } // else // { // Try. // Use Pen-Paper. // Find errors, edge cases, etc. // continue; // } // } // Optimizations #pragma GCC optimize( O2 ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( avx2 ) #pragma GCC optimize( Os ) // Libraries #include <bits/stdc++.h> using namespace std; // #include <ext/pb_ds/assoc_container.hpp> // #include <ext/pb_ds/tree_policy.hpp> // using namespace __gnu_pbds; // Debugging #define dbg(a) cerr<<a<< n ; #define debug_a(a) for(auto x:a) {cerr<<x<< ;} cerr<< n ; #define debug_b(a) for(auto x:a) {cerr<< [ <<x.first<< , <<x.second<< ] << n ;} cerr<< n ; #define debug_c(a) for(auto x:a) {debug_a(x)} cerr<< n ; #define debug_d(a) for(auto x:a) {debug_b(x)} cerr<< n ; #define debug_e(a) cerr<< [ <<a.first<< , <<a.second<< ] << n ; // Defines #define fast ios_base::sync_with_stdio(false); cout.tie(NULL); cin.tie(NULL); #define loop(i,a,n) for(ll i=a; i<n; i++) #define rloop(i,a,n) for(int i=a; i>=n; i--) #define fr(i,a,n,b) for(int i=a; i<n; i+=b) #define rfr(i,a,n,b) for(int i=a; i>=n; i-=b) #define IN cin>> #define OUT cout<< #define nl n #define sz(a) int(a.size()) #define all(a) (a).begin(),(a).end() #define each(a,b) for(auto &a:b) #define pb push_back #define set_bits(a) __builtin_popcountll(a) #define ar array #define write(a) for(auto x:a) {OUT x<< ;} OUT endl; #define read(a) for(auto &x:a) {IN x;} // #define oset tree<int,null_type,less<int>,rb_tree_tag,tree_order_statistics_node_update> using ll=long long int; using ld=long double; using pll=pair<ll,ll>; using pii=pair<int,int>; using vll=vector<ll>; using vi=vector<int>; const ll mod=(ll)(1e9)+7LL; const ll M=998244353LL; const int dx[4]={1,0,-1,0}; const int dy[4]={0,1,0,-1}; const ld pi=acos(-1); // General Functions ll gcd(ll a, ll b) { return (b?gcd(b,a%b):a); } ll P(ll B, ll power, ll modulo) //Fast Power { ll ans=1LL; while(power>0LL) { if(power%2LL==1LL) { ans=(ans*B)%modulo; } B=(B*B)%modulo; power/=2LL; } return ans; } bool isPrime(ll n) { if(n<=1LL) { return false; } if(n<=3LL) { return true; } if(n%2==0LL || n%3==0LL) { return false; } for(ll i=5LL; (i*i)<=n; i+=6LL) { if(n%i==0LL || n%(i+2LL)==0LL) { return false; } } return true; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); ll get_rand(ll l, ll r) { uniform_int_distribution<ll> uid(l,r); return uid(rng); } void vok() { fast #ifndef ONLINE_JUDGE freopen( input.txt , r ,stdin); freopen( output.txt , w ,stdout); freopen( error.txt , w ,stderr); #endif } // Global Variables const int mxN=int(1e5)+100; vector<bool> cycle; ll sizee=0; vector<bool> vis; // Solver Function(s) void dfs_cycle(int u, int p, int color[], int mark[], int par[], int& cyclenumber, vi graph[]) { // already (completely) visited vertex. if (color[u] == 2) { return; } // seen vertex, but was not completely visited -> cycle detected. // backtrack based on parents to find the complete cycle. if (color[u] == 1) { cyclenumber++; int cur = p; mark[cur] = cyclenumber; // backtrack the vertex which are // in the current cycle thats found while (cur != u) { cur = par[cur]; mark[cur] = cyclenumber; } return; } par[u] = p; // partially visited. color[u] = 1; // simple dfs on graph for (int v : graph[u]) { // if it has not been visited previously if (v == par[u]) { continue; } dfs_cycle(v, u, color, mark, par, cyclenumber, graph); } // completely visited. color[u] = 2; } void dfs(int u, vi g[]) { sizee++; vis[u]=true; each(x,g[u]) { if(!vis[x] && !cycle[x]) { dfs(x,g); } } } void solve() { int n; IN n; vi g[n+1]; loop(i,0,n) { int u,v; IN u>>v; g[u].pb(v); g[v].pb(u); } if(n==3) { OUT 6<<nl; return; } int color[n+1]; int par[n+1]; int mark[n+1]; loop(i,0,n+1) { color[i]=par[i]=mark[i]=0; } int cyclenumber = 0; int edges = n; dfs_cycle(1, 0, color, mark, par, cyclenumber, g); vis=vector<bool>(n+1,false); vll vv; cycle=vis; ll sz_cycle=0; loop(i,1,n+1) { if(mark[i]) { cycle[i]=true; sz_cycle++; } } ll ans=(ll)(sz_cycle)*(ll)(sz_cycle-1); loop(i,1,n+1) { if(cycle[i]) { sizee=0; dfs(i,g); ll add=sizee*(sizee-1)/2; // OUT i<< <<sizee<<nl; if(sizee>1) { vv.pb(sizee-1); ans+=((sizee-1)*(ll)(sz_cycle-1)*2); } ans+=add; // OUT ans<<nl; // ans+=((sizee-1)*(ll)(sz(cycle)-1)*2); // OUT ans<<nl; } } ll sum=0; ll sq=0; each(x,vv) { sum+=x; sq+=(x*x); } sum*=sum; ll temp=sum-sq; ans+=temp; OUT ans<<nl; } // Main Function int main() { vok(); int t=1; IN t; while(t--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; bool As; char c; int n, m, k; inline void read(int& a) { a = 0; do c = getchar(); while (c < 0 || c > 9 ); while (c <= 9 && c >= 0 ) a = (a << 3) + (a << 1) + c - 0 , c = getchar(); } int Min[1211]; double A[11][11]; bool Has[11][11]; const double eps = 1e-7; int Matrix(int n) { int o = 1; double res = 1; if (n < 0) return 0; for (int i = 0; i < n; i++) { int j = -1; for (int t = i; t < n; t++) if (((A[t][i]) > 0 ? (A[t][i]) : -(A[t][i])) > eps) { j = t; break; } if (j ^ i) o ^= 1; if (j == -1) return 0; for (int t = 0; t < n; t++) swap(A[j][t], A[i][t]); for (int j = i + 1; j < n; j++) if (((A[j][i]) > 0 ? (A[j][i]) : -(A[j][i])) > eps) { double U = A[j][i] / A[i][i]; for (int k = 0; k < n; k++) A[j][k] -= U * A[i][k]; } res *= A[i][i]; } if (o) return res + 0.1; else return -res + 0.1; } int Build(int S) { vector<int> Q; Q.clear(); memset(A, 0, sizeof(A)); while (S) Q.push_back(Min[S]), S ^= 1 << Min[S]; for (int i = 0; i < Q.size(); i++) for (int j = 0; j < i; j++) if (Has[Q[i]][Q[j]]) A[i][j]--, A[j][i]--, A[j][j]++, A[i][i]++; return Q.size() - 1; } int Cnt[2002]; int Pow(int a, int x) { int res = 1; for (x; x; x >>= 1, a = a * a) if (x & 1) res = res * a; return res; } int F[2002]; int G[2002]; int main() { Min[0] = -1; for (int i = 1; i < 1024; i++) Cnt[i] = (i & 1) ? Cnt[i >> 1] + 1 : Cnt[i >> 1], Min[i] = (i & 1) ? 0 : (Min[i >> 1] + 1); read(n), read(m), read(k); while (m--) { int a, b; read(a), read(b); a--, b--; Has[b][a] = Has[a][b] = true; } int t = 1 << n; t--; for (int i = 1; i <= t; i++) { int W = 1; for (int j = 0; j < n; j++) if ((1 << j) & i) { int f = 0; for (int k = 0; k < n; k++) if (!(i & (1 << k))) if (Has[j][k]) f++; W *= f; } int df; G[i] = F[i] = W * (df = Matrix(Build(t ^ i))); } int Ans = 0; for (int i = t; ~i; i--) { if (Cnt[i] == k) Ans += G[i]; int j = (i - 1) & i; while (j) { G[j] += (Cnt[j ^ i] & 1 ? -1 : 1) * F[i]; j = i & (j - 1); } } cout << Ans << endl; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFXTP_SYMBOL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, CrYCb to RGB conversion
// The multiplication coefficients are in 1.4.12 format
// The addition coefficients are in 1.12.12 format
// R = (+408.583/256)*Cr + (+298.082/256)*Y + ( 000.000/256)*Cb + (-222.921);
// G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576);
// B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836);
module ad_csc_CrYCb2RGB (
// Cr-Y-Cb inputs
clk,
CrYCb_sync,
CrYCb_data,
// R-G-B outputs
RGB_sync,
RGB_data);
// parameters
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// Cr-Y-Cb inputs
input clk;
input [DW:0] CrYCb_sync;
input [23:0] CrYCb_data;
// R-G-B outputs
output [DW:0] RGB_sync;
output [23:0] RGB_data;
// red
ad_csc_1 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_csc_1_R (
.clk (clk),
.sync (CrYCb_sync),
.data (CrYCb_data),
.C1 (17'h01989),
.C2 (17'h012a1),
.C3 (17'h00000),
.C4 (25'h10deebc),
.csc_sync_1 (RGB_sync),
.csc_data_1 (RGB_data[23:16]));
// green
ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_G (
.clk (clk),
.sync (1'd0),
.data (CrYCb_data),
.C1 (17'h10d01),
.C2 (17'h012a1),
.C3 (17'h10644),
.C4 (25'h0087937),
.csc_sync_1 (),
.csc_data_1 (RGB_data[15:8]));
// blue
ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_B (
.clk (clk),
.sync (1'd0),
.data (CrYCb_data),
.C1 (17'h00000),
.C2 (17'h012a1),
.C3 (17'h02046),
.C4 (25'h1114d60),
.csc_sync_1 (),
.csc_data_1 (RGB_data[7:0]));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ====================================================================
// Bashkiria-2M FPGA REPLICA
//
// Copyright (C) 2010 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Bashkiria-2M home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580vv55.v
//
// Parallel interface k580vv55 design file of Bashkiria-2M replica.
//
// Warning: This realization is not fully operational.
module k580vv55
(
input reset,
input clk_sys,
input [1:0] addr,
input we_n,
input [7:0] idata,
output reg[7:0] odata,
input [7:0] ipa,
output [7:0] opa,
input [7:0] ipb,
output [7:0] opb,
input [7:0] ipc,
output [7:0] opc
);
reg [7:0] mode;
reg [7:0] opa_r;
reg [7:0] opb_r;
reg [7:0] opc_r;
assign opa = mode[4] ? 8'hFF : opa_r;
assign opb = mode[1] ? 8'hFF : opb_r;
assign opc ={mode[3] ? 4'hF : opc_r[7:4], mode[0] ? 4'hF : opc_r[3:0]};
always @* begin
case(addr)
0: odata = mode[4] ? ipa : opa_r;
1: odata = mode[1] ? ipb : opb_r;
2: odata ={mode[3] ? ipc[7:4] : opc_r[7:4], mode[0] ? ipc[3:0] : opc_r[3:0]};
3: odata = 0;
endcase
end
always @(posedge clk_sys, posedge reset) begin
reg old_we;
if (reset) begin
{opa_r,opb_r,opc_r,mode} <= {8'h00,8'h00,8'h00,8'hFF};
end else begin
old_we <= we_n;
if(old_we & ~we_n) begin
case(addr)
0: opa_r <= idata;
1: opb_r <= idata;
2: opc_r <= idata;
default: begin
if (~idata[7]) opc_r[idata[3:1]] <= idata[0];
else {opa_r,opb_r,opc_r,mode} <= {8'h00,8'h00,8'h00,idata};
end
endcase
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; vector<int> d(n); for (int(i) = 0; (i) < (n); (i)++) { cin >> d[i]; } sort((d).begin(), (d).end()); if (d[b] != d[b - 1]) { cout << d[b] - d[b - 1] << endl; } else { cout << 0 << endl; } return 0; }
|
/* -------------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*
* *** NOT FOR SYNTHESIS ***
*
* Traffic Sink
*
* Collects incoming packets and produces statistics.
*
* - check flit id's are sequential
*
*/
//`include "parameters.v"
`timescale 1 ps/ 1 ps
`include "types.v"
`include "LAG_functions.v"
`include "parameters.v"
module LAG_traffic_sink (flit_in, cntrl_out, rec_count, stats, clk, rst_n);
parameter xdim = 4;
parameter ydim = 4;
parameter xpos = 0;
parameter ypos = 0;
parameter warmup_packets = 100;
parameter measurement_packets = 1000;
parameter router_num_pls_on_exit = 1;
input flit_t [router_num_pls_on_exit-1:0] flit_in;
output chan_cntrl_t cntrl_out;
output sim_stats_t stats;
input clk, rst_n;
output integer rec_count;
logic [7:0] expected_flit_id [router_num_pls_on_exit-1:0]; //in test version our packets is only 255 flit length
logic [15:0] expected_packet_id[router_num_pls_on_exit-1:0];
logic [15:0] arrived_packet_id[router_num_pls_on_exit-1:0];
logic [31:0] head_injection_time [router_num_pls_on_exit-1:0];
logic [31:0] latency, sys_time;
logic [31:0] crc_computed [router_num_pls_on_exit-1:0];
logic [31:0] crc_received [router_num_pls_on_exit-1:0];
integer j, i;
integer error_count;
genvar ch;
for (ch=0; ch<router_num_pls; ch++) begin:flow_control
always@(posedge clk) begin
if (!rst_n) begin
cntrl_out.credits[ch] <= 0;
end else begin
if (flit_in[ch].control.valid) begin
if (ch < router_num_pls_on_exit) begin
cntrl_out.credits[ch] <= 1;
end else begin
$display ("%m: Error: Flit Channel ID is out-of-range for exit from network!");
$display ("Channel ID = %1d (router_num_pls_on_exit=%1d)", ch, router_num_pls_on_exit);
$finish;
end
end else begin
cntrl_out.credits[ch] <= 0;
end
end
end
end
always@(posedge clk) begin
if (!rst_n) begin
rec_count=0;
stats.total_latency=0;
stats.total_hops=0;
stats.max_hops=0;
stats.min_hops=MAXINT;
stats.max_latency=0;
stats.min_latency=MAXINT;
stats.measure_start=-1;
stats.measure_end=-1;
stats.flit_count=0;
error_count = 0;
for (j=0; j<router_num_pls_on_exit; j++) begin
expected_flit_id[j]=1;
expected_packet_id[j]=1;
head_injection_time[j]='0;
crc_computed[i] = '0;
crc_received[i] = '0;
end
for (j=0; j<=100; j++) begin
stats.lat_freq[j]=0;
end
sys_time = 0;
end else begin // if (!rst_n)
#3000 sys_time++;
for (i=0; i<router_num_pls_on_exit; i++) begin
if (flit_in[i].control.valid) begin
//
// check flits for each packet are received in order
//
if(~flit_in[i].control.head && expected_flit_id[i] != flit_in[i].data[7:0]) begin
error_count++;
$display("%m Error: flit out of sequence.");
$display("-- Flit ID = %1d, Expected = %1d", flit_in[i].data[7:0], expected_flit_id[i]);
end
/*$display($time, " ----> Flit %d is received in x[%1d]y[%1d], ch=%1d", flit_in[i].data[7:0], xpos, ypos, i);
$display("****************************************************************************"); */
if(expected_flit_id[i] > 1 && expected_flit_id[i] < 9) crc_computed[i] = crc32(flit_in[i].data, crc_computed[i]);
if(expected_flit_id[i] == 1) begin
if(~flit_in[i].control.head) begin
error_count++;
$display("%m Error: flit out of sequence. Expected 1st flit");
end
head_injection_time[i] = '0;
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 2) begin
arrived_packet_id[i][7:0] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 3) begin
arrived_packet_id[i][15:8] = flit_in[i].data[15:8];
if ((arrived_packet_id[i] > warmup_packets) && (stats.measure_start==-1)) stats.measure_start = sys_time - 2;
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 4) begin
if(xpos != flit_in[i].data[11:8] && ypos != flit_in[i].data[15:12] )begin
error_count++;
$display("Packet arrived at wrong destination");
end
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 5) begin
head_injection_time[i][7:0] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 6) begin
head_injection_time[i][15:8] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 7) begin
head_injection_time[i][23:16] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 8) begin
head_injection_time[i][31:24] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 9) begin
crc_received[i][7:0] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 10) begin
crc_received[i][15:8] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 11) begin
crc_received[i][23:16] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 12) begin //last (tail) flit
crc_received[i][31:24] = flit_in[i].data[15:8];
if (crc_received[i] != crc_computed[i]) begin
error_count++;
$display("%m Error: checksum do not match");
$display("--------> crc_computed = %h, crc_received = %h", crc_computed[i], crc_received[i]);
$finish;
end else begin
/*$display($time, " ---------> Packet is received in x[%1d]y[%1d], ch=%1d", xpos, ypos, i);
$display("****************************************************************************"); */
end
crc_computed[i] = '0;
crc_received[i] = '0;
expected_flit_id[i] = 1;
expected_packet_id[i]++;
//----------> count statistics
if ((arrived_packet_id[i] > warmup_packets) &&
(arrived_packet_id[i] <= warmup_packets + measurement_packets)) begin
rec_count++;
// time last measurement packet was received
stats.measure_end = sys_time;
//
// gather latency stats.
//
latency = sys_time - head_injection_time[i];
stats.total_latency = stats.total_latency + latency;
stats.min_latency = min (stats.min_latency, latency);
stats.max_latency = max (stats.max_latency, latency);
//
// display progress estimate
//
if (rec_count%(measurement_packets/100)==0)
$display ("%1d: %m: %1.2f%% complete (this packet's latency was %1d)", sys_time,
$itor(rec_count*100)/$itor(measurement_packets),
latency);
//
// bin latencies
//
stats.lat_freq[min(latency, 100)]++;
end
end
if(error_count) begin
$display("At least %1d errors occured during simulation", error_count);
$finish;
end
// count all flits received in measurement period
if (arrived_packet_id[i] <= warmup_packets + measurement_packets)
if (stats.measure_start!=-1) stats.flit_count++;
end // if flit valid
end //for
end //if(!rst_n)
end //always
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module halfband_ideal (
input clock,
input reset,
input enable,
input strobe_in,
input wire signed [17:0] data_in,
output reg strobe_out,
output reg signed [17:0] data_out
) ;
parameter decim = 1 ;
parameter rate = 2 ;
reg signed [40:0] temp ;
reg signed [17:0] delay[30:0] ;
reg signed [17:0] coeffs[30:0] ;
reg [7:0] count ;
integer i ;
initial begin
for( i = 0 ; i < 31 ; i = i + 1 ) begin
coeffs[i] = 18'd0 ;
end
coeffs[0] = -1390 ;
coeffs[2] = 1604 ;
coeffs[4] = -1896 ;
coeffs[6] = 2317 ;
coeffs[8] = -2979 ;
coeffs[10] = 4172 ;
coeffs[12] = -6953 ;
coeffs[14] = 20860 ;
coeffs[15] = 32768 ;
coeffs[16] = 20860 ;
coeffs[18] = -6953 ;
coeffs[20] = 4172 ;
coeffs[22] = -2979 ;
coeffs[24] = 2317 ;
coeffs[26] = -1896 ;
coeffs[28] = 1604 ;
coeffs[30] = -1390 ;
end
always @(posedge clock) begin
if( reset ) begin
count <= 0 ;
for( i = 0 ; i < 31 ; i = i + 1 ) begin
delay[i] <= 18'd0 ;
end
temp <= 41'd0 ;
data_out <= 18'd0 ;
strobe_out <= 1'b0 ;
end else if( enable ) begin
if( (decim && (count == rate-1)) || !decim )
strobe_out <= strobe_in ;
else
strobe_out <= 1'b0 ;
if( strobe_in ) begin
// Increment decimation count
count <= count + 1 ;
// Shift the input
for( i = 30 ; i > 0 ; i = i - 1 ) begin
delay[i] = delay[i-1] ;
end
delay[0] = data_in ;
// clear the temp reg
temp = 18'd0 ;
if( (decim && (count == rate-1)) || !decim ) begin
count <= 0 ;
for( i = 0 ; i < 31 ; i = i + 1 ) begin
// Multiply Accumulate
temp = temp + delay[i]*coeffs[i] ;
end
// Assign data output
data_out <= temp >>> 15 ;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; struct state { int l, r, v, d; } node[N]; int n, m, cnt, bit[2][N * 2]; vector<int> g[N]; void add(int x, int val, int *b) { while (x <= n * 2) { b[x] += val; x += (x & (-x)); } } int get(int x, int *b) { int ans = 0; while (x > 0) { ans += b[x]; x -= (x & (-x)); } return ans; } void dfs(int c, int fa, int d) { node[c].l = cnt++; node[c].d = d; for (int i = 0; i < g[c].size(); i++) { if (g[c][i] == fa) continue; dfs(g[c][i], c, 1 - d); } node[c].r = cnt++; } void init() { cnt = 1; scanf( %d%d , &n, &m); memset(bit, 0, sizeof(bit)); for (int i = 1; i <= n; i++) scanf( %d , &node[i].v); int a, b; for (int i = 1; i < n; i++) { scanf( %d%d , &a, &b); g[a].push_back(b); g[b].push_back(a); } dfs(1, -1, 0); } void solve() { int o, a, b; for (int i = 0; i < m; i++) { scanf( %d , &o); if (o == 1) { scanf( %d%d , &a, &b); add(node[a].l, b, bit[node[a].d]); add(node[a].r + 1, -b, bit[node[a].d]); } else { scanf( %d , &a); printf( %d n , node[a].v + get(node[a].l, bit[node[a].d]) - get(node[a].l, bit[1 - node[a].d])); } } } int main() { init(); solve(); return 0; }
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_phy_dm_iob.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module places the data mask signals into the IOBs.
//Reference:
//Revision History:
// Rev 1.1 - To fix timing issues with Synplicity 9.6.1, syn_preserve
// attribute added for the instance u_dm_ce. PK. 11/11/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_dm_iob
(
input clk90,
input dm_ce,
input mask_data_rise,
input mask_data_fall,
output ddr_dm
);
wire dm_out;
wire dm_ce_r;
FDRSE_1 u_dm_ce
(
.Q (dm_ce_r),
.C (clk90),
.CE (1'b1),
.D (dm_ce),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve=1 */;
ODDR #
(
.SRTYPE("SYNC"),
.DDR_CLK_EDGE("SAME_EDGE")
)
u_oddr_dm
(
.Q (dm_out),
.C (clk90),
.CE (dm_ce_r),
.D1 (mask_data_rise),
.D2 (mask_data_fall),
.R (1'b0),
.S (1'b0)
);
OBUF u_obuf_dm
(
.I (dm_out),
.O (ddr_dm)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:58:24 11/03/2014
// Design Name:
// Module Name: temp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module temp(
clock,
a,
//enable,
store000,
store001,
store010,
store100,
store101,
store110
);
parameter NUM_BITS = 5;
//--------------------------------------------
input clock;
input [NUM_BITS-1:0] a;
//--------------------------------------------
wire [NUM_BITS-1:0] a;
wire clock;
//--------------------------------------------
reg [2:0] remain = NUM_BITS-1;
reg [3:0] bits = NUM_BITS;
reg [2:0] shift = 3'b000;
reg [NUM_BITS-1:0] b;
reg [4:0] r1;
//--------------------------------------------
output reg [3:0] store000; //= 4'h0;
output reg [3:0] store001; //= 4'h0;
output reg [3:0] store010; //= 4'h0;
output reg [3:0] store100; //= 4'h0;
output reg [3:0] store101;//= 4'h0;
output reg [3:0] store110;
reg count =1'b0;
parameter [4:0] VAL1 = 5'h10;
parameter [4:0] VAL2 = 5'h12;
parameter [4:0] VAL3 = 5'h18;
parameter [4:0] VAL4 = 5'h1B;
parameter [2:0] exp1 = 3'b000;
parameter [2:0] exp2 = 3'b011;
parameter [2:0] exp3 = 3'b001;
parameter [2:0] exp4 = 3'b100;
always@(posedge clock)
begin
if(count == 1'b0)
begin
b <=a;
remain <= NUM_BITS-1;
count<=1'b1;
end
else
begin
if((b >= VAL1) && (remain >= exp1)&&((b < VAL2)||(remain<exp2)))
begin
r1[2:0] <= remain - exp1;
r1[4:3] <= 2'b00;
b <= b - VAL1;
end
else if((b >= VAL2) && (remain >= exp2)&&(b < VAL3))
begin
r1[2:0] <= remain - exp2;
r1[4:3] <= 2'b10;
b <= b - VAL2;
end
else if((b >= VAL3) && (remain >= exp3)&&(b < VAL4))
begin
r1[2:0] <= remain - exp3;
r1[4:3] <= 2'b01;
b <= b - VAL3;
end
else if((b >= VAL4) && (remain >= exp4)&&(b< 6'b100000))
begin
r1[2:0] <= remain - exp4;
r1[4:3] <= 2'b11;
b <= b - VAL4;
end
else
begin
if(b[4] == 1'b1)
begin
shift <= 3'b000;
remain <= remain - shift;
b <= (b<<shift);
end
else if(b[3] == 1'b1)
begin
shift <= 3'b001;
remain <= remain - shift;
b <= (b<<shift);
end
else if(b[2] == 1'b1)
begin
shift <= 3'b010;
remain <= remain - shift;
b <= (b<<shift);
end
else if(b[1] == 1'b1)
begin
shift <= 3'b011;
remain <= remain - shift;
b <= (b<<shift);
end
else if(b[0] == 1'b1)
begin
shift <= 3'b100;
remain <= remain - shift;
b <= (b<<shift);
end
else
begin
shift <= 3'b110;
remain <= remain - shift;
b <= (b<<shift);
end
end
end
end
always@(posedge clock)
begin
/* if(r1 == 5'b00000)
begin
store000[0] = 1'b1;
end
else if(r1 == 5'b00001)
begin
store000[1] = 1'b1;
end
else if(r1 == 5'b01000)
begin
store000[2] = 1'b1;
end
else if(r1 == 5'b01001)
begin
store000[3] = 1'b1;
end
else if(r1 == 5'b00010)
begin
store001[0] = 1'b1;
end
else if(r1 == 5'b00011)
begin
store001[1] = 1'b1;
end
else if(r1 == 5'b01010)
begin
store001[2] = 1'b1;
end
else if(r1 == 5'b01011)
begin
store001[3] = 1'b1;
end
else if(r1 == 5'b00100)
begin
store010[0] = 1'b1;
end
else if(r1 == 5'b01100)
begin
store010[2] = 1'b1;
end
else if(r1 == 5'b10000)
begin
store100[0] = 1'b1;
end
else if(r1 == 5'b10001)
begin
store100[1] = 1'b1;
end
else if(r1 == 5'b11000)
begin
store100[2] = 1'b1;
end
else
begin
store000[3:0] = 4'b0000;
store001[3:0] = 4'b0000;
store010[3:0] = 4'b0000;
store100[3:0] = 4'b0000;
store101[3:0] = 4'b0000;
store110[3:0] = 4'b0000;
end*/
case(r1)
5'b00000 : store000[0] <= 1'b1; // First 0 in store000 is for the first box and then the numbers 00 represent the position of the box
5'b00001 : store000[1] <= 1'b1;
5'b01000 : store000[2] <= 1'b1;
5'b01001 : store000[3] <= 1'b1;
5'b00010 : store001[0] <= 1'b1;
5'b00011 : store001[1] <= 1'b1;
5'b01010 : store001[2] <= 1'b1;
5'b01011 : store001[3] <= 1'b1;
5'b00100 : store010[0] <= 1'b1;
5'b01100 : store010[2] <= 1'b1;
5'b10000 : store100[0] <= 1'b1;
5'b10001 : store100[1] <= 1'b1;
5'b11000 : store100[2] <= 1'b1;
5'b11001 : store100[3] <= 1'b1;
5'b10010 : store101[0] <= 1'b1;
5'b10011 : store101[1] <= 1'b1;
5'b11010 : store101[2] <= 1'b1;
5'b11011 : store101[3] <= 1'b1;
5'b10100 : store110[0] <= 1'b1;
5'b11100 : store110[2] <= 1'b1;
default : begin
store000[3:0] <= 4'b0000;
store001[3:0] <= 4'b0000;
store010[3:0] <= 4'b0000;
store100[3:0] <= 4'b0000;
store101[3:0] <= 4'b0000;
store110[3:0] <= 4'b0000;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> const int oo = 0x7fffffff; const long long OO = 0x7fffffffffffffff; using namespace std; const int NX = 50; typedef bitset<NX * NX * NX * NX> dp_t; int n; array<bitset<NX>, NX> board1, board2, done; dp_t dp1, dp2; int ask(int x1, int y1, int x2, int y2) { cout << ? << (1 + x1) << << (1 + y1) << << (1 + x2) << << (1 + y2) << endl; int r; cin >> r; if (r == -1) exit(0); return r; } void ask_n_set(int x1, int y1, int x2, int y2, bool forward = true) { int r = ask(x1, y1, x2, y2) ^ 1; if (forward) { board1[x2][y2] = r ^ board1[x1][y1]; board2[x2][y2] = r ^ board2[x1][y1]; done[x2][y2] = 1; } else { board1[x1][y1] = r ^ board1[x2][y2]; board2[x1][y1] = r ^ board2[x2][y2]; done[x1][y1] = 1; } } void print(const array<bitset<NX>, NX>& B) { cout << ! n ; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) cout << B[i][j]; cout << n ; } cout << endl; } void solve(const array<bitset<NX>, NX>& B, dp_t& dp) { for (int x1 = 0; x1 < n; ++x1) for (int y1 = 0; y1 < n; ++y1) for (int x2 = 0; x2 < n; ++x2) for (int y2 = 0; y2 < n; ++y2) if ((abs(x1 - x2) + abs(y1 - y2)) <= 2) dp[(y2 + NX * (x2 + NX * (y1 + NX * x1)))] = B[x1][y1] == B[x2][y2]; for (int x1 = 0; x1 < n; ++x1) for (int y1 = 0; y1 < n; ++y1) for (int x2 = x1 - 1; x2 >= 0; --x2) for (int y2 = y1 - 1; y2 >= 0; --y2) dp[(y2 + NX * (x2 + NX * (y1 + NX * x1)))] = 0; for (int len = 3; len < (2 * n); ++len) for (int x1 = 0; x1 < n; ++x1) for (int y1 = 0; y1 < n; ++y1) for (int x2 = x1; x2 < n; ++x2) if ((abs(x1 - x2) + abs(y1 - y1)) <= len) { int d = len - (x2 - x1); int y2 = y1 + d; if (y2 >= n) continue; if (x1 == x2) { dp[(y2 + NX * (x2 + NX * (y1 + NX * x1)))] = B[x1][y1] == B[x2][y2] and dp[(y2 - 1 + NX * (x2 + NX * (y1 + 1 + NX * x1)))]; } else if (y1 == y2) { dp[(y2 + NX * (x2 + NX * (y1 + NX * x1)))] = B[x1][y1] == B[x2][y2] and dp[(y2 + NX * (x2 - 1 + NX * (y1 + NX * x1 + 1)))]; } else { dp[(y2 + NX * (x2 + NX * (y1 + NX * x1)))] = B[x1][y1] == B[x2][y2] and (dp[(y2 + NX * (x2 - 1 + NX * (y1 + NX * x1 + 1)))] or dp[(y2 - 1 + NX * (x2 + NX * (y1 + NX * x1 + 1)))] or dp[(y2 + NX * (x2 - 1 + NX * (y1 + 1 + NX * x1)))] or dp[(y2 - 1 + NX * (x2 + NX * (y1 + 1 + NX * x1)))]); } } } int main() { cin >> n; for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) done[i][j] = 0; board2[0][0] = board1[0][0] = 1; board2[n - 1][n - 1] = board1[n - 1][n - 1] = 0; done[0][0] = done[n - 1][n - 1] = 1; board1[0][1] = 1; board2[0][1] = 0; done[0][1] = 1; ask_n_set(0, 1, 2, 1); ask_n_set(1, 0, 2, 1, false); for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) if (not done[i][j]) { int x, y; if (i - 2 >= 0) { x = i - 2; y = j; } else if (j - 2 >= 0) { x = i; y = j - 2; } else { x = i - 1; y = j - 1; } ask_n_set(x, y, i, j); } solve(board1, dp1); solve(board2, dp2); for (int x1 = 0; x1 < n; ++x1) for (int x2 = x1; x2 < n; ++x2) for (int y1 = 0; y1 < n; ++y1) for (int y2 = y1; y2 < n; ++y2) if (2 <= y2 - y1 + x2 - x1) { int r1 = dp1[(y2 + NX * (x2 + NX * (y1 + NX * x1)))], r2 = dp2[(y2 + NX * (x2 + NX * (y1 + NX * x1)))]; if (r1 == r2) continue; int r = ask(x1, y1, x2, y2); if (r1 == r) print(board1); else print(board2); return 0; } print(board1); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_2_V
`define SKY130_FD_SC_HD__DFXBP_2_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfxbp_2 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_2_V
|
#include <bits/stdc++.h> using namespace std; int t1, n, i, j, a[202], f[202][404]; int main() { scanf( %d , &t1); while (t1--) { scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); memset(f, 44, sizeof(f)); for (j = 0; j <= n * 2; j++) f[0][j] = 0; for (i = 1; i <= n; i++) for (j = 1; j <= n * 2; j++) { f[i][j] = min(f[i][j - 1], f[i - 1][j - 1] + abs(a[i] - j)); } printf( %d n , f[n][n * 2]); } }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 9; const long long INF = 1e18; const int MAXN = 1e6 + 10; const int MAXM = 1e4 + 500; const int N = 2000 + 15; const double EPS = 1e-9; int dx[] = {1, 0, 0, -1}; int dy[] = {0, 1, -1, 0}; double len(complex<long long> a) { return sqrt(a.real() * a.real() + a.imag() * a.imag()); } long long sq(complex<long long> a) { return a.real() * a.real() + a.imag() * a.imag(); } complex<long long> perp(complex<long long> p) { return {-p.imag(), p.real()}; } long long dotProduct(complex<long long> a, complex<long long> b) { return (conj(a) * b).real(); } long long crossProduct(complex<long long> a, complex<long long> b) { return (conj(a) * b).imag(); } long long orient(complex<long long> a, complex<long long> b, complex<long long> c) { return crossProduct(b - a, c - a); } bool inDisk(complex<long long> a, complex<long long> b, complex<long long> p) { return dotProduct(a - p, b - p) <= 0; } bool onSegment(complex<long long> a, complex<long long> b, complex<long long> p) { return orient(a, b, p) == 0 && inDisk(a, b, p); }; struct cmpX { bool operator()(complex<long long> a, complex<long long> b) { return make_pair(a.real(), a.imag()) < make_pair(b.real(), b.imag()); } }; struct line { complex<long long> v; long long c; line(complex<long long> v, long long c) : v(v), c(c) {} line(long long a, long long b, long long c) : v({b, -a}), c(c) {} line(complex<long long> p, complex<long long> q) : v(q - p), c(crossProduct(v, p)) {} long long side(complex<long long> p) { return crossProduct(v, p) - c; } double dist(complex<long long> p) { return abs(side(p)) / len(v); } line perpThrough(complex<long long> p) { return {p, p + perp(v)}; } bool cmpProj(complex<long long> p, complex<long long> q) { return dotProduct(v, p) < dotProduct(v, q); } line translate(complex<long long> t) { return {v, c + crossProduct(v, t)}; } complex<long long> proj(complex<long long> p) { return p - perp(v) * side(p) / sq(v); } }; double segPoint(complex<long long> a, complex<long long> b, complex<long long> p) { if (a != b) { line l(a, b); if (l.cmpProj(a, p) && l.cmpProj(p, b)) return l.dist(p); } return min(abs(p - a), abs(p - b)); } bool inAngle(complex<long long> a, complex<long long> b, complex<long long> c, complex<long long> p) { if (orient(a, b, c) < 0) swap(b, c); return orient(a, b, p) >= 0 && orient(a, c, p) <= 0; } bool isInsidePol(vector<complex<long long> > &a, complex<long long> b) { int n = a.size(); int pos = 0, neg = 0; for (int i = 0; i < n - 1; i++) { if (onSegment(a[i], a[(i + 1) % n], b)) return false; line l(a[i], a[i + 1]); if (l.side(b) > 0) pos++; else neg++; } line l(a[n - 1], a[0]); if (l.side(b) > 0) pos++; else neg++; return ((!pos && neg == n) || (!neg && pos == n)); } long long i, j, k; long long n, m, t; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); string w; cin >> w; stack<int> kek; kek.push(0); for (auto e : w) { e == kek.top() ? kek.pop() : kek.push(e); } cout << (kek.top() ? No : Yes ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e9 + 7; long long read() { long long x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return f * x; } long long n, m, _x, _y, f[300005][2], a[300005], b[300005]; int main() { n = read(); m = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= n; i++) b[i] = read(); for (int i = 1; i <= n; i++) { _x = a[i]; _y = b[i]; for (int j = 0; j <= 1; j++) { long long x = _x, y = _y, t = 1, cnt, s; cnt = min(x, y); x -= cnt; y -= cnt; x -= m - f[i - 1][j]; x -= (cnt - 1) * (m - 1); if (x > 0) { if (x > m - 1) s = inf; else s = 1 + x; } else s = 1; y -= cnt * (m - 1); if (y > 0) s = inf; f[i][j] = s; x = _x; y = _y; x--; cnt = min(x, y); x -= cnt; y -= cnt; y -= m - f[i - 1][j ^ 1]; x -= cnt * (m - 1); if (x > 0) { if (x > m - 1) s = inf; else s = x + 1; } else s = 1; y -= cnt * (m - 1); if (y > 0) s = inf; f[i][j] = min(f[i][j], s); swap(_x, _y); } } if (f[n][0] < inf || f[n][1] < inf) puts( YES ); else puts( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; char n[1000 + 2]; char m[1000 + 2]; int color_n[30]; int color_m[30]; int main() { while (scanf( %s , n) != EOF) { scanf( %s , m); memset(color_n, 0, sizeof(color_n)); memset(color_m, 0, sizeof(color_m)); for (int i = 0; i < strlen(n); i++) color_n[n[i] - a ]++; for (int j = 0; j < strlen(m); j++) color_m[m[j] - a ]++; int ans = 0; int flag = 1; for (int i = 0; i < 30; i++) { ans += min(color_n[i], color_m[i]); if (color_m[i] && color_n[i] == 0) flag = 0; } if (ans == 0 || flag == 0) printf( -1 n ); else printf( %d n , ans); } return 0; }
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice/Mark_Extract_Bits/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function
(
u,
y
);
input [35:0] u; // ufix36
output [17:0] y; // ufix18
//MATLAB Function 'Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position/Mod_2pi_Scale_And_Bit_Slice/Mark_Extract_Bits/MATLAB Function': '<S13>:1'
// Non-tunable mask parameter
//'<S13>:1:8'
//'<S13>:1:10'
assign y = u[17:0];
//'<S13>:1:14'
endmodule // controllerHdl_MATLAB_Function
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2014 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Extraction to Ocaml : use of basic Ocaml types *)
Extract Inductive bool => bool [ true false ].
Extract Inductive option => option [ Some None ].
Extract Inductive unit => unit [ "()" ].
Extract Inductive list => list [ "[]" "( :: )" ].
Extract Inductive prod => "( * )" [ "" ].
(** NB: The "" above is a hack, but produce nicer code than "(,)" *)
(** Mapping sumbool to bool and sumor to option is not always nicer,
but it helps when realizing stuff like [lt_eq_lt_dec] *)
Extract Inductive sumbool => bool [ true false ].
Extract Inductive sumor => option [ Some None ].
(** Restore lazyness of andb, orb.
NB: without these Extract Constant, andb/orb would be inlined
by extraction in order to have lazyness, producing inelegant
(if ... then ... else false) and (if ... then true else ...).
*)
Extract Inlined Constant andb => "(&&)".
Extract Inlined Constant orb => "(||)".
|
#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)1e9 + 7; const int N = 105; const int M = 5005; long long dp[N][M]; int x[N]; int y[N]; long long c[M][N]; int sum[N]; int rSum[N]; int h[N]; int main() { int n, i, j, k, l; long long ans = 0; scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &x[i]); } for (i = 1; i <= n; i++) { scanf( %d , &y[i]); } for (i = 0; i < M; i++) { c[i][0] = 1; if (i <= 100) { c[i][i] = 1; } for (j = 1; j < min(i, N); j++) { c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % MOD; } } for (i = 1; i <= n; i++) { sum[i] = sum[i - 1] + x[i]; } for (i = n; i >= 1; i--) { rSum[i] = rSum[i + 1] + y[i] - x[i]; } for (i = 1; i <= n; i++) { h[i] = x[i] + min(sum[i - 1], rSum[i]); } for (j = x[n]; j <= y[n]; j++) { dp[n][j] = 1; } for (i = n - 1; i >= 1; i--) { for (j = x[i]; j <= h[i]; j++) { for (k = 0; k <= min(y[i], j); k++) { dp[i][j] = (dp[i][j] + c[j][k] * dp[i + 1][x[i + 1] + j - k]) % MOD; } } } ans = dp[1][x[1]]; int num = sum[n]; for (i = 1; i <= n; i++) { ans = (ans * c[num][x[i]]) % MOD; num -= x[i]; } printf( %d n , (int)ans); }
|
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
fritz
writeback phase
*/
module cpu_wb(mem_c_rfw, mem_c_wbsource, mem_alu_r, mem_dmem_in, mem_rf_waddr,
mem_jalra, rfw, wdata, rf_waddr);
input mem_c_rfw;
input [1:0] mem_c_wbsource;
input [31:0] mem_alu_r;
input [31:0] mem_dmem_in;
input [4:0] mem_rf_waddr;
input [31:0] mem_jalra;
output rfw;
output [31:0] wdata;
output [4:0] rf_waddr;
assign rfw = mem_c_rfw;
assign wdata =
(mem_c_wbsource == 2'b00) ? mem_alu_r :
(mem_c_wbsource == 2'b01) ? mem_dmem_in :
(mem_c_wbsource == 2'b10) ? mem_jalra :
32'd0;
assign rf_waddr = mem_rf_waddr;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_20_V
`define SKY130_FD_SC_LP__BUSDRIVER2_20_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog wrapper for busdriver2 with size of 20 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busdriver2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdriver2_20 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__busdriver2 base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdriver2_20 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__busdriver2 base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_20_V
|
#include <bits/stdc++.h> using namespace std; const int maxl = 1000 * 100 + 5; int n, k; string s; int dis[30][maxl]; int main() { cin >> n >> k >> s; memset(dis, -1, sizeof dis); for (int i = 0; i < 27; i++) { queue<int> q; for (int j = 0; j < k; j++) if (s[j] == (char)(i + a )) { q.push(j); dis[i][j] = 0; } while (!q.empty()) { int index = q.front(); q.pop(); if (index != 0) if (dis[i][index - 1] == -1) { dis[i][index - 1] = dis[i][index] + 1; q.push(index - 1); } if (index != maxl - 1) if (dis[i][index + 1] == -1) { dis[i][index + 1] = dis[i][index] + 1; q.push(index + 1); } } } for (int j = 0; j < n; j++) { string tmp; cin >> tmp; long long int ans = 0; for (int i = 0; i < tmp.size(); i++) ans += (dis[tmp[i] - a ][i] == -1 ? tmp.size() : dis[tmp[i] - a ][i]); cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 12 + 1, M = 1 << N | 5; bool dp1[M][N + N], dp2[M][N + N]; int n, k, mx[M], c[N + N]; int main() { cin >> n; dp1[0][1] = true; for (int i = 0; i < n; i++) { cin >> c[i]; if (c[i] < 2) n--, k++, i--; } if (n > k) return cout << NO , 0; for (int i = 1; i <= k; i++) { dp1[0][i] = true; dp2[0][i] = (i > 1); } for (int i = 0; i < n; i++) dp1[1 << i][c[i] - 1] = (c[i] > 2); for (int i = 1; i < 1 << n; i++) { int &u = mx[i] = __builtin_ctz(i); if (i ^ i & -i && c[u] < c[mx[i ^ i & -i]]) u = mx[i ^ i & -i]; for (int j = 1; j <= k; j++) for (int x = i; x; --x &= i) for (int y = 0; y <= j; y++) { if (~x >> u & 1 && c[u] == __builtin_popcount(i) + j) dp1[i][j] |= dp1[x][y] && (dp1[i ^ x ^ 1 << u][j - y] || dp2[i ^ x ^ 1 << u][j - y]); dp2[i][j] |= dp1[x][y] && (dp1[i ^ x][j - y] || dp2[i ^ x][j - y]); } } cout << (dp1[(1 << n) - 1][k] ? YES : NO ); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:01:50 03/29/2015
// Design Name:
// Module Name: aluparam_behav
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu_behav
( output [15:0] Y,
output [15:0] flags,
input [15:0] A,
input [15:0] B,
input [3:0] sel
);
reg [15:0] outreg;
reg [15:0] flagreg;
reg carry;
reg overflow;
always @(A, B, sel) begin
flagreg = 0;
carry = 0;
overflow = 0;
case(sel)
4'b0011: begin // XOR
outreg = A ^ B;
end
4'b0001: begin // AND
outreg = A & B;
end
4'b0010: begin // OR
outreg = A | B;
end
4'b0101: begin // ADD
{carry, outreg} = A + B;
overflow = (($signed(A) >= 0 && $signed(B) >= 0 && $signed(outreg) < 0) || ($signed(A) < 0 && $signed(B) < 0 && $signed(outreg) >= 0)) ? 1'b1 : 1'b0;
end
4'b1001,
4'b1011: begin // SUB or CMP
{carry, outreg} = A + ~B + 1'b1;
overflow = (($signed(A) >= 0 && $signed(B) < 0 && $signed(outreg) < 0) || ($signed(A) < 0 && $signed(B) >= 0 && $signed(outreg) >= 0)) ? 1'b1 : 1'b0;
end
4'b1101: begin // MOV
outreg = B;
end
4'b1111: begin // Load Upper
outreg = { B[7:0], {(8){1'b0}} };
end
default: begin
outreg = A; // Do nothing
flagreg = 0;
end
endcase
flagreg[0] = carry; // Carry set by ADD and SUB only.
flagreg[2] = (A < B) && (sel == 4'b1011); // Low Flag set by CMP only.
flagreg[5] = overflow; // Overflow set by ADD and SUB only.
flagreg[6] = (outreg == 16'b0) && (sel == 4'b1011); // Zero Flag set by CMP only.
flagreg[7] = outreg[15] && (sel == 4'b1011); // Negative (Sign) Flag set by CMP only.
if(sel == 4'b1011) begin
outreg = A;
end
end
assign Y = outreg;
assign flags = flagreg;
endmodule
|
//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
//Date : Sun Sep 22 03:30:11 2019
//Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
//Command : generate_target gcd_block_design_wrapper.bd
//Design : gcd_block_design_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module gcd_block_design_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
gcd_block_design gcd_block_design_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
//An ALU module for the integer pipeline.
//List of ops accepted:
//0: NOP
//1: ADD
//2: ADDC
//3: SUB
//4: SUBC
//5: BSL
//6: BSR
//7: AND
//8: OR
//9: INV
//10: XOR
module ALU(
OP,
FLGIN,
A,
B,
flgOut,
out,
shouldWriteBack
);
input [3:0] OP;
input [7:0] FLGIN;
input [15:0] A;
input [15:0] B;
output [7:0] flgOut;
output [15:0] out;
output shouldWriteBack;
wire [15:0] nopWire;
wire [16:0] addWire;
wire [16:0] addcWire;
wire [15:0] subWire;
wire [15:0] subcWire;
wire [15:0] bslWire;
wire [15:0] bsrWire;
wire [15:0] andWire;
wire [15:0] orWire;
wire [15:0] invWire;
wire [15:0] xorWire;
wire [15:0] outputMuxWire[15:0];
//Assign the wires to their respective actions:
assign nopWire=0;
assign addWire=A+B;
assign addcWire=A+B+FLGIN[1];
assign subWire=A-B;
assign subcWire=A-B-FLGIN[1];
assign bslWire=A<<B;
assign bsrWire=A>>B;
assign andWire=A&B;
assign orWire=A|B;
assign invWire=~A;
assign xorWire=A^B;
assign outputMuxWire[0]=nopWire;
assign outputMuxWire[1]=addWire[15:0];
assign outputMuxWire[2]=addcWire[15:0];
assign outputMuxWire[3]=subWire;
assign outputMuxWire[4]=subcWire;
assign outputMuxWire[5]=bslWire;
assign outputMuxWire[6]=bsrWire;
assign outputMuxWire[7]=andWire;
assign outputMuxWire[8]=orWire;
assign outputMuxWire[9]=invWire;
assign outputMuxWire[10]=xorWire;
assign outputMuxWire[11]=nopWire;
assign outputMuxWire[12]=nopWire;
assign outputMuxWire[13]=nopWire;
assign outputMuxWire[14]=nopWire;
assign outputMuxWire[15]=nopWire;
//Set normal computation outputs.
assign out=outputMuxWire[OP];
assign shouldWriteBack=OP>0&&OP<11; //Enables NOPs.
//Now construct flags: (zero, carry, overflow, negative)
wire zero, carry, overflow, negative;
wire zeroMuxWire[10:0];
assign zeroMuxWire[0]=nopWire==0;
assign zeroMuxWire[1]=addWire==0;
assign zeroMuxWire[2]=addcWire==0;
assign zeroMuxWire[3]=subWire==0;
assign zeroMuxWire[4]=subcWire==0;
assign zeroMuxWire[5]=bslWire==0;
assign zeroMuxWire[6]=bsrWire==0;
assign zeroMuxWire[7]=andWire==0;
assign zeroMuxWire[8]=orWire==0;
assign zeroMuxWire[9]=invWire==0;
assign zeroMuxWire[10]=xorWire==0;
assign zero=zeroMuxWire[OP];
assign carry=addWire[16]&&(OP==1)||addcWire[16]&&(OP==2);
//I'll figure out overflow later on:
assign overflow=0;
//Negative:
assign negative=subWire<0&&(OP==3)||subcWire<0&&(OP==4);
//Condense all of the flags:
assign flgOut[0]=zero;
assign flgOut[1]=carry;
assign flgOut[2]=overflow;
assign flgOut[3]=negative;
assign flgOut[7:4]=0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, k; cin >> n >> k; if (k == 1) { long long int ans = n * (n - 1) / 2; cout << ans << << ans << endl; } else { long long int ans = (n - k + 1) * (n - k) / 2; long long int x = n / k; long long int y = n % k; long long int ans2 = x * (x - 1) / 2; long long int ans3 = (x + 1) * x / 2; cout << ans3 * y + ans2 * (k - y) << << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long tc, n, x, cnt1, cnt2, i, max_; scanf( %lld , &tc); while (tc--) { scanf( %lld , &n); vector<long long> v; vector<long long> v1; for (i = 0; i < n; i++) { scanf( %lld , &x); v.push_back(x); } sort(v.begin(), v.end()); cnt1 = 0; v1.push_back(0); for (i = 0; i < n; i++) { cnt1++; if (cnt1 >= v[i]) v1.push_back(i + 1); } max_ = *max_element(v1.begin(), v1.end()); printf( %lld n , max_ + 1); } }
|
#include <bits/stdc++.h> using namespace std; inline long long getint() { long long _x = 0, _tmp = 1; char _tc = getchar(); while ((_tc < 0 || _tc > 9 ) && _tc != - ) _tc = getchar(); if (_tc == - ) _tc = getchar(), _tmp = -1; while (_tc >= 0 && _tc <= 9 ) _x *= 10, _x += (_tc - 0 ), _tc = getchar(); return _x * _tmp; } long long mypow(long long _a, long long _x, long long _mod) { if (_x == 0) return 1ll; long long _tmp = mypow(_a, _x / 2, _mod); _tmp = (_tmp * _tmp) % _mod; if (_x & 1) _tmp = (_tmp * _a) % _mod; return _tmp; } inline long long add(long long _x, long long _y, long long _mod = 1000000007ll) { long long _ = _x + _y; if (_ >= _mod) _ -= _mod; return _; } inline long long sub(long long _x, long long _y, long long _mod = 1000000007ll) { long long _ = _x - _y; if (_ < 0) _ += _mod; return _; } inline long long mul(long long _x, long long _y, long long _mod = 1000000007ll) { long long _ = _x * _y; if (_ >= _mod) _ %= _mod; return _; } inline bool equal(double _x, double _y) { return _x > _y - 1e-9 && _x < _y + 1e-9; } int __ = 1, _cs; int n, k; vector<int> v; void build() {} void init() { n = getint(); k = getint(); for (int i = 1; i <= n; i++) v.push_back(getint()); sort((v).begin(), (v).end()); v.resize(unique((v).begin(), (v).end()) - v.begin()); } int dp[1001 * 1001]; void solve() { for (int i = 1; i <= (v.back() - v[0]) * k; i++) { dp[i] = 1001 * 1001; for (size_t j = 1; j < v.size(); j++) if (v[j] - v[0] > i) break; else dp[i] = min(dp[i], dp[i - v[j] + v[0]] + 1); } for (int i = 0; i <= (v.back() - v[0]) * k; i++) if (dp[i] <= k) printf( %d , i + v[0] * k); puts( ); } int main() { build(); while (__--) { init(); solve(); } }
|
#include <bits/stdc++.h> using namespace std; int n, m; struct pos { long long x, y; bool operator<(const pos &p) const { if (x != p.x) return x < p.x; return y < p.y; } } A[200005], stk[200005]; bool check(pos a, pos b, pos c) { return (c.y - a.y) * (b.x - c.x) <= (b.y - c.y) * (c.x - a.x); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { long long x, y; scanf( %lld%lld , &x, &y); y -= x * x, A[i] = (pos){x, y}; } sort(A + 1, A + n + 1); int cnt = 0; for (int i = 1; i <= n; i++) { if (i != n && A[i].x == A[i + 1].x) continue; while (cnt > 1 && check(stk[cnt - 1], A[i], stk[cnt])) cnt--; stk[++cnt] = A[i]; } printf( %d n , cnt - 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100000; const double eps = 1e-15; int n; double p[N + 9], q[N + 9]; void into() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %lf , &p[i]); for (int i = 1; i <= n; ++i) scanf( %lf , &q[i]); } double a[N + 9], b[N + 9]; double Get_root(double a, double b, double c) { return fabs(a) <= eps ? -c / b : (sqrt(max(b * b - 4 * a * c, 0.0)) - b) / (2 * a); } void Get_ans() { for (int i = 1; i <= n; ++i) { double x = p[i] + a[i - 1] * b[i - 1]; double y = p[i] + q[i] + a[i - 1] + b[i - 1]; b[i] = Get_root(1, -y, x); a[i] = y - b[i]; } for (int i = n; i >= 1; --i) a[i] -= a[i - 1], b[i] -= b[i - 1]; } void work() { Get_ans(); } void outo() { for (int i = 1; i <= n; ++i) printf( %.10lf , a[i]); puts( ); for (int i = 1; i <= n; ++i) printf( %.10lf , b[i]); puts( ); } int main() { int T = 1; for (; T--;) { into(); work(); outo(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool isprime[2000005]; void setprime() { for (long long i = 0; i < 2000005; i++) isprime[i] = true; isprime[0] = false; isprime[1] = false; for (long long i = 2; i < 2000005; i++) { for (long long j = 2; i * j < 2000005; j++) isprime[i * j] = false; } } long long choose(long long n, long long k) { if (k == 0) return 1; return (n * choose(n - 1, k - 1)) / k; } long long gcd(long long a, long long b) { if (!a) return b; return gcd(b % a, a); } long long n, m, temp; pair<long long, long long> p[100005]; bool start[100005]; vector<pair<pair<long long, long long>, long long> > ans; long long min1 = LONG_LONG_MAX; long long end1; void dfs(long long x) { if (p[x].first != 0) { min1 = min(min1, p[x].second); dfs(p[x].first); } else { end1 = x; return; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; for (long long i = 0; i < m; i++) { long long u, v, w; cin >> u >> v >> w; p[u] = make_pair(v, w); start[v] = 1; } for (long long i = 1; i < n + 1; i++) { if (!start[i]) { min1 = LONG_LONG_MAX; end1 = -1; dfs(i); if (min1 != LONG_LONG_MAX) ans.push_back(make_pair(make_pair(i, end1), min1)); } } sort(ans.begin(), ans.end()); cout << ans.size() << endl; for (long long i = 0; i < ans.size(); i++) { cout << ans[i].first.first << << ans[i].first.second << << ans[i].second << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_1_V
`define SKY130_FD_SC_LS__EBUFN_1_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_1 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_1_V
|
#include <bits/stdc++.h> using namespace std; long long n, a[100100], tmp, Ans, Odd, Even; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] & 1) Odd++; else Even++; } tmp = min(Odd, Even); Ans += tmp; Odd -= tmp; Ans += Odd / 3; cout << Ans << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; long long modexp(long long base, long long exp) { if (exp == 1) return base; else if (exp == 0) return 1; else { if (exp % 2 == 0) { long long base1 = pow(modexp(base, exp / 2), 2); if (base1 >= 1000000007) return base1 % 1000000007; else return base1; } else { long long ans = (base * pow(modexp(base, (exp - 1) / 2), 2)); if (ans >= 1000000007) return ans % 1000000007; else return ans; } } } long long gcd(long long a, long long b) { if (!a) return b; return gcd(b % a, a); } map<int, int> d; set<int> s; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; int a[n]; for (long long i = 0; i < n; ++i) cin >> a[i]; for (long long i = 0; i < n; ++i) d[a[i]]++; long long ans = 0; for (long long i = 0; i < n; ++i) { d[a[i]]--; if (!d[a[i]]) { d.erase(a[i]); } if (s.find(a[i]) == s.end()) { ans += d.size(); s.insert(a[i]); } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100010; int F[MAXN] = {0}; int main() { int N, x, y; cin >> N; for (int I = 1; I <= N; I++) { cin >> x >> y; int ans = 0; for (int i = 1; i <= sqrt(x) + 1; i++) { if (x % i) continue; if (F[i] + y < I) ans++; F[i] = I; int j = x / i; if (j == i) continue; if (F[j] + y < I) ans++; F[j] = I; } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; int t,n; int a[100010]; int main(){ cin>>t; while(t--){ cin>>n; for(int i=0;i<n;++i)cin>>a[i]; sort(a,a+n); long long ans=a[n-1],sum=0; for(int i=0;i<n;++i){ sum+=a[i]; ans+=sum-1ll*a[i]*(i+1); } cout<<ans<< n ; } }
|
#include <bits/stdc++.h> using namespace std; bool Check(int X1, int Y1, int X2, int Y2, int a, int b) { bool answ = false; if (X1 <= a && X2 <= a && Y1 <= b && Y2 <= b) if (!(X1 + X2 > a) || !(Y1 + Y2 > b)) answ = true; if (Y1 <= a && X2 <= a && X1 <= b && Y2 <= b) if (!(Y1 + X2 > a) || !(X1 + Y2 > b)) answ = true; if (X1 <= a && Y2 <= a && Y1 <= b && X2 <= b) if (!(X1 + Y2 > a) || !(Y1 + X2 > b)) answ = true; if (Y1 <= a && Y2 <= a && X1 <= b && X2 <= b) if (!(Y1 + Y2 > a) || !(X1 + X2 > b)) answ = true; return answ; } int main() { int n, a, b; cin >> n >> a >> b; char XY[n][2]; for (int i = 0; i < n; i++) { int Xi, Yi; cin >> Xi >> Yi; XY[i][0] = Xi; XY[i][1] = Yi; } int maxS = 0; for (int i = 0; i < n - 1; i++) { int X1 = XY[i][0]; int Y1 = XY[i][1]; for (int j = i + 1; j < n; j++) { int X2 = XY[j][0]; int Y2 = XY[j][1]; if (Check(X1, Y1, X2, Y2, a, b) == true) { maxS = max(maxS, X1 * Y1 + X2 * Y2); } } } cout << maxS; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string p, z; cin >> p; cin >> z; for (int i = 0; i < p.length(); i++) { if (p[i] >= A && p[i] <= Z ) p[i] = tolower(p[i]); } for (int i = 0; i < z.length(); i++) { if (z[i] >= A && z[i] <= Z ) z[i] = tolower(z[i]); } cout << p.compare(z); return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s1_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEV",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEV",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[3][55], b[55]; int sum(int row, int f, int e) { int res = 0; for (int i = f; i <= e; ++i) res += a[row][i]; return res; } int main() { cin >> n; for (int x = 1; x <= 2; ++x) for (int i = 1; i < n; ++i) cin >> a[x][i]; for (int i = 1; i <= n; ++i) cin >> b[i]; int ans = (1 << 30); for (int i = 1; i < n; ++i) for (int j = i + 1; j <= n; ++j) ans = min(ans, sum(1, 1, i - 1) + sum(2, i, n - 1) + b[i] + sum(1, 1, j - 1) + sum(2, j, n - 1) + b[j]); cout << ans; }
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
module resetter(
clk,
rst_in1_n,
rst_in2_n,
rst_out_n );
parameter RST_CNT_SIZE = 3;
input clk;
input rst_in1_n; // input of external asynchronous reset 1
input rst_in2_n; // input of external asynchronous reset 2
output reg rst_out_n; // output of end-synchronized reset (beginning is asynchronous to clock)
reg [RST_CNT_SIZE:0] rst_cnt; // one bit more for counter stopping
reg rst1_n,rst2_n;
wire resets_n;
assign resets_n = rst_in1_n & rst_in2_n;
always @(posedge clk, negedge resets_n)
if( !resets_n ) // external asynchronous reset
begin
rst_cnt <= 0;
rst1_n <= 1'b0;
rst2_n <= 1'b0; // sync in reset end
rst_out_n <= 1'b0; // this zeroing also happens after FPGA configuration, so also power-up reset happens
end
else // clocking
begin
rst1_n <= 1'b1;
rst2_n <= rst1_n;
if( rst2_n && !rst_cnt[RST_CNT_SIZE] )
begin
rst_cnt <= rst_cnt + 1;
end
rst_out_n <= rst_cnt[RST_CNT_SIZE];
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_alu_carry_out (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 37; const long long INF = 1LL << 61; int n, u, r; long long sum; int a[MAX_N], b[MAX_N], k[MAX_N], p[MAX_N]; void dfs(int dep, bool f) { if ((u - dep) % 2 == 0) { long long s = 0; for (int i = 1; i <= n; ++i) { s += (long long)a[i] * k[i]; } sum = max(sum, s); } if (dep == u) return; int t[MAX_N] = {0}; for (int i = 1; i <= n; ++i) { t[i] = a[i]; } if (!f) { for (int i = 1; i <= n; ++i) { a[i] = t[i] ^ b[i]; } dfs(dep + 1, true); } for (int i = 1; i <= n; ++i) { a[i] = t[p[i]] + r; } dfs(dep + 1, false); for (int i = 1; i <= n; ++i) { a[i] = t[i]; } } int main() { scanf( %d%d%d , &n, &u, &r); for (int i = 1; i <= n; ++i) { scanf( %d , a + i); } for (int i = 1; i <= n; ++i) { scanf( %d , b + i); } for (int i = 1; i <= n; ++i) { scanf( %d , k + i); } for (int i = 1; i <= n; ++i) { scanf( %d , p + i); } sum = -INF; dfs(0, 0); printf( %I64d n , sum); return 0; }
|
#include <bits/stdc++.h> const int Inf = (int)(1e9); const int K = 1000 + 1; const int N = 60 + 1; int w[N][N][N]; int n, m, r; int ans[K][N][N]; void prepare() { for (int i = 0; i < K; ++i) for (int j = 0; j < N; ++j) for (int k = 0; k < N; ++k) ans[i][j][k] = Inf; for (int i = 0; i < m; ++i) { for (int k = 0; k < n; ++k) for (int ii = 0; ii < n; ++ii) for (int jj = 0; jj < n; ++jj) w[i][ii][jj] = std::min(w[i][ii][jj], w[i][ii][k] + w[i][k][jj]); for (int ii = 0; ii < n; ++ii) for (int jj = 0; jj < n; ++jj) ans[0][ii][jj] = std::min(ans[0][ii][jj], w[i][ii][jj]); } for (int i = 1; i < K; ++i) { for (int ii = 0; ii < n; ++ii) for (int jj = 0; jj < n; ++jj) ans[i][ii][jj] = ans[i - 1][ii][jj]; for (int k = 0; k < n; ++k) for (int ii = 0; ii < n; ++ii) for (int jj = 0; jj < n; ++jj) ans[i][ii][jj] = std::min(ans[i][ii][jj], ans[i - 1][ii][k] + ans[0][k][jj]); } } int main() { scanf( %d%d%d , &n, &m, &r); for (int i = 0; i < m; ++i) for (int j = 0; j < n; ++j) for (int k = 0; k < n; ++k) scanf( %d , &w[i][j][k]); prepare(); int si, ti, ki; while (r-- > 0) { scanf( %d%d%d , &si, &ti, &ki); --si; --ti; printf( %d n , ans[ki][si][ti]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long int n; cin >> n; vector<long long int> s(2 * n); for (int i = 0; i < 2 * n; i++) cin >> s[i]; sort(s.begin(), s.end()); if (s[0] == s[2 * n - 1]) { cout << -1 << n ; return; } for (int i = 0; i < 2 * n; i++) cout << s[i] << ; cout << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); long long int t; t = 1; while (t--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_TB_V
`define SKY130_FD_SC_HD__O22A_TB_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o22a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__o22a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_TB_V
|
#include <bits/stdc++.h> using namespace std; int dp[100][100]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; if (n == 1 || n == 2) { cout << -1; return 0; } int m = INT_MAX; int mi = -1; int a[n]; int m2 = INT_MIN; int mi2 = -1; for (int i = 0; i < n; i++) { cin >> a[i]; if (m > a[i]) { m = a[i]; mi = i; } if (m == a[i] && i != 0 && i != n - 1) { mi = i; } if (m2 < a[i]) { m2 = a[i]; mi2 = i; } if (m2 == a[i] && i != 0 && i != n - 1) { mi2 = i; } } if (mi != mi2) { int t = a[mi2]; a[mi2] = a[mi]; a[mi] = t; int flag = 0; for (int i = 0; i < n - 1; i++) { if (a[i] >= a[i + 1]) { } else { flag = 1; } } if (flag) { int flag2 = 0; for (int i = 0; i < n - 1; i++) { if (a[i] <= a[i + 1]) { } else { flag2 = 1; } } if (flag2) { cout << mi + 1 << << mi2 + 1; return 0; } } } cout << -1; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
/**
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
* keep-alive power rail.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_0_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx2;
wire unxunused_resetxx3;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx2 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; double a[200005], b[200005]; double l = -10001, r = 10001; const double eps = 2e-12; double solve(double x) { for (int i = 1; i <= n; ++i) b[i] = a[i] - x; double res = 0, tmp = 0; for (int i = 1; i <= n; ++i) { if (tmp < 0) tmp = 0; tmp += b[i]; res = max(res, tmp); } tmp = 0; for (int i = 1; i <= n; ++i) { if (tmp < 0) tmp = 0; tmp -= b[i]; res = max(res, tmp); } return res; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %lf , &a[i]); } while (r > eps + l) { double ll = (2 * l + r) / 3, rr = (l + 2 * r) / 3; double lll = solve(ll); double rrr = solve(rr); if (lll < rrr) r = rr; else l = ll; } cout << fixed << setprecision(12) << solve((l + r) / 2) << endl; }
|
/** try <3 **/ #include<bits/stdc++.h> using namespace std; #define task sol #define lb lower_bound #define ub upper_bound #define fi first #define se second #define pb push_back #define mp make_pair #define zs(v) ((int)(v).size()) #define BIT(x, i) (((x) >> (i)) & 1) #define CNTBIT __builtin_popcountll #define ALL(v) (v).begin(),(v).end() #define endl n typedef long double ld; typedef long long ll; typedef pair<int,int> pii; void gogo() { int x; cin>>x; ll s=0, ans=0; for(int i=1;i<=x;++i) { s+=i; ans=i; if(s>=x) break; } if(!(s==x||s>x+1)) ++ans; cout<<ans<< n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); if(fopen(task .inp , r )) { freopen(task .inp , r ,stdin); freopen(task .out , w ,stdout); } int t; cin>>t; while(t--) gogo(); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct rect { int x1, y1, x2, y2; }; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; vector<rect> v(n); int minx = 1000000000; int miny = 1000000000; for (int i = 0; i < n; ++i) { cin >> v[i].x1 >> v[i].y1 >> v[i].x2 >> v[i].y2; minx = min(minx, v[i].x1); miny = min(miny, v[i].y1); } cout << YES << endl; for (int i = 0; i < n; ++i) { int x = (v[i].x1 - minx) % 2; int y = (v[i].y1 - miny) % 2; if (x == 0 && y == 0) { cout << 1; } else if (x == 1 && y == 0) { cout << 2; } else if (x == 0 && y == 1) { cout << 3; } else { cout << 4; } cout << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NOR2_FUNCTIONAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 105, maxm = 5005; const double eps = 1e-9; int N, M, m, X[maxm], Y[maxm], Z[maxm]; double f[maxn][maxn], p[maxn]; int main() { scanf( %d%d , &N, &M); for (int i = 1; i <= M; i++) { scanf( %d%d%d , &X[i], &Y[i], &Z[i]); if (X[i] > 1 && X[i] < N) f[X[i]][X[i]]++, f[X[i]][Y[i]]--; if (Y[i] > 1 && Y[i] < N) f[Y[i]][Y[i]]++, f[Y[i]][X[i]]--; } f[1][N + 1] = 1, f[1][1] = 1; f[N][N + 1] = 0, f[N][N] = 1; for (int i = 1; i <= N; i++) { if (abs(f[i][i]) < eps) for (int j = i + 1; j <= N; j++) if (abs(f[j][i]) > eps) { for (int k = i; k <= N + 1; k++) f[i][k] += f[j][k]; break; } for (int j = i + 1; j <= N; j++) if (abs(f[j][i]) > eps) { double r(f[j][i] / f[i][i]); for (int k = i; k <= N + 1; k++) f[j][k] -= f[i][k] * r; } } for (int i = N; i; i--) if (abs(f[i][i]) > eps) { p[i] = f[i][N + 1]; for (int j = i + 1; j <= N; j++) p[i] -= f[i][j] * p[j]; p[i] /= f[i][i]; } double rate(1.0 / 0), ans(0); for (int i = 1; i <= M; i++) rate = min(rate, Z[i] / abs(p[X[i]] - p[Y[i]])); for (int i = 1; i <= M; i++) { if (X[i] == 1) ans += p[1] - p[Y[i]]; if (Y[i] == 1) ans += p[1] - p[X[i]]; } printf( %.7f n , isfinite(rate) ? ans * rate : 0); for (int i = 1; i <= M; i++) printf( %.7f n , isfinite(rate) ? (p[X[i]] - p[Y[i]]) * rate : 0); return 0; }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
addressstall_a, addressstall_b);
parameter clock_enable_input_b = "ALTERNATE";
parameter clock_enable_input_a = "ALTERNATE";
parameter clock_enable_output_b = "NORMAL";
parameter clock_enable_output_a = "NORMAL";
parameter wrcontrol_aclr_a = "NONE";
parameter indata_aclr_a = "NONE";
parameter address_aclr_a = "NONE";
parameter outdata_aclr_a = "NONE";
parameter outdata_reg_a = "UNREGISTERED";
parameter operation_mode = "SINGLE_PORT";
parameter intended_device_family = "MAX 10 FPGA";
parameter outdata_reg_b = "UNREGISTERED";
parameter lpm_type = "altsyncram";
parameter init_type = "unused";
parameter ram_block_type = "AUTO";
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
parameter power_up_uninitialized = "FALSE";
parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ";
parameter width_byteena_a = 1;
parameter numwords_b = 0;
parameter numwords_a = 0;
parameter widthad_b = 1;
parameter width_b = 1;
parameter widthad_a = 1;
parameter width_a = 1;
// Port A declarations
output [35:0] q_a;
input [35:0] data_a;
input [7:0] address_a;
input wren_a;
input rden_a;
// Port B declarations
output [35:0] q_b;
input [35:0] data_b;
input [7:0] address_b;
input wren_b;
input rden_b;
// Control signals
input clock0, clock1;
input clocken0, clocken1, clocken2, clocken3;
input aclr0, aclr1;
input addressstall_a;
input addressstall_b;
// TODO: Implement the correct simulation model
endmodule // altsyncram
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module daala_4x4_transpose_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXIS
parameter integer C_S00_AXIS_TDATA_WIDTH = 256,
// Parameters of Axi Master Bus Interface M00_AXIS
parameter integer C_M00_AXIS_TDATA_WIDTH = 256
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
input wire axis_clk,
input wire axis_aresetn,
// Ports of Axi Slave Bus Interface S00_AXIS
output wire s00_axis_tready,
input wire [C_S00_AXIS_TDATA_WIDTH-1 : 0] s00_axis_tdata,
input wire s00_axis_tlast,
input wire s00_axis_tvalid,
// Ports of Axi Master Bus Interface M00_AXIS
output wire m00_axis_tvalid,
output wire [C_M00_AXIS_TDATA_WIDTH-1 : 0] m00_axis_tdata,
output wire m00_axis_tlast,
input wire m00_axis_tready
);
// Add user logic here
assign s00_axis_tready = m00_axis_tready;
assign m00_axis_tlast = s00_axis_tlast;
assign m00_axis_tvalid = s00_axis_tvalid;
assign m00_axis_tdata[( 0+1)*16-1: 0*16] = s00_axis_tdata[( 0+1)*16-1: 0*16];
assign m00_axis_tdata[( 1+1)*16-1: 1*16] = s00_axis_tdata[( 4+1)*16-1: 4*16];
assign m00_axis_tdata[( 2+1)*16-1: 2*16] = s00_axis_tdata[( 8+1)*16-1: 8*16];
assign m00_axis_tdata[( 3+1)*16-1: 3*16] = s00_axis_tdata[(12+1)*16-1:12*16];
assign m00_axis_tdata[( 4+1)*16-1: 4*16] = s00_axis_tdata[( 1+1)*16-1: 1*16];
assign m00_axis_tdata[( 5+1)*16-1: 5*16] = s00_axis_tdata[( 5+1)*16-1: 5*16];
assign m00_axis_tdata[( 6+1)*16-1: 6*16] = s00_axis_tdata[( 9+1)*16-1: 9*16];
assign m00_axis_tdata[( 7+1)*16-1: 7*16] = s00_axis_tdata[(13+1)*16-1:13*16];
assign m00_axis_tdata[( 8+1)*16-1: 8*16] = s00_axis_tdata[( 2+1)*16-1: 2*16];
assign m00_axis_tdata[( 9+1)*16-1: 9*16] = s00_axis_tdata[( 6+1)*16-1: 6*16];
assign m00_axis_tdata[(10+1)*16-1:10*16] = s00_axis_tdata[(10+1)*16-1:10*16];
assign m00_axis_tdata[(11+1)*16-1:11*16] = s00_axis_tdata[(14+1)*16-1:14*16];
assign m00_axis_tdata[(12+1)*16-1:12*16] = s00_axis_tdata[( 3+1)*16-1: 3*16];
assign m00_axis_tdata[(13+1)*16-1:13*16] = s00_axis_tdata[( 7+1)*16-1: 7*16];
assign m00_axis_tdata[(14+1)*16-1:14*16] = s00_axis_tdata[(11+1)*16-1:11*16];
assign m00_axis_tdata[(15+1)*16-1:15*16] = s00_axis_tdata[(15+1)*16-1:15*16];
// User logic ends
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, a[N], b[N], posa[N], posb[N], dif[N], ans, ord[N], t1; multiset<int> rig, lef; int abss(const int i) { return i < 0 ? -i : i; } bool cmp(int i, int j) { return dif[i] < dif[j]; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); posa[a[i]] = i; } for (int i = 1; i <= n; ++i) { scanf( %d , &b[i]); posb[b[i]] = i; } ans = n; for (int i = 1; i <= n; ++i) { ans = min(ans, abss(posa[i] - posb[i])); dif[i] = posb[i] - posa[i]; if (dif[i] > 0) { rig.insert(dif[i]); } else { lef.insert(-dif[i]); } ord[i] = i; } sort(ord + 1, ord + 1 + n, cmp); t1 = 1; printf( %d n , ans); for (int i = 2; i <= n; ++i) { lef.erase(lef.find(posa[b[i - 1]] - i + 1)); rig.insert(n - posa[b[i - 1]] + i - 1); while (rig.size() > 0 && *rig.begin() - i + 1 == 0) { rig.erase(rig.find(*rig.begin())); lef.insert((int)(-i + 1)); } ans = min(*lef.begin() + i - 1, rig.size() > 0 ? *rig.begin() - i + 1 : n + 1); printf( %d n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, a[93], b[93]; scanf( %d , &n); int ans = 0; a[0] = 0; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); b[i - 1] = a[i] - a[i - 1]; } b[n] = 90 - a[n]; for (int i = 0; i <= n; i++) { if (b[i] > 15) { ans = a[i] + 15; break; } } if (!ans) ans = 90; printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; char str[100005]; char notValid[15] = { B , C , D , E , F , G , J , K , L , N , P , Q , R , S , Z }; bool valid(char c) { static int i; for (i = 0; i < 15; ++i) if (c == notValid[i]) return false; return true; } bool check(char *s) { int i; int len = strlen(s); int lend2 = len / 2; for (i = 0; i < lend2; ++i) { if (!valid(s[i]) || !valid(s[len - i - 1]) || (s[i] != s[len - i - 1])) return false; } if (len & 1) return valid(s[lend2]); return true; } int main(void) { int i; while (scanf( %s , str) == 1) { printf( %s n , check(str) ? YES : NO ); } return 0; }
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#include <bits/stdc++.h> using namespace std; using namespace chrono; void _print(long long t) { cerr << t; } void _print(int t) { cerr << t; } void _print(string t) { cerr << t; } void _print(char t) { cerr << t; } void _print(long double t) { cerr << t; } void _print(double t) { cerr << t; } void _print(unsigned long long t) { cerr << t; } template <class T, class V> void _print(T a[], V sz); template <class T, class V> void _print(pair<T, V> p); template <class T> void _print(vector<T> v); template <class T> void _print(set<T> v); template <class T, class V> void _print(map<T, V> v); template <class T> void _print(multiset<T> v); template <class T, class V> void _print(pair<T, V> p) { cerr << { ; _print(p.first); cerr << , ; _print(p.second); cerr << } ; } template <class T, class V> void _print(T a[], V sz) { for (V i = 0; i < sz; i++) { _print(a[i]); cerr << ; } cerr << n ; } template <class T> void _print(vector<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; cerr << n ; } template <class T> void _print(set<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; cerr << n ; } template <class T> void _print(multiset<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T, class V> void _print(map<T, V> v) { cerr << [ ; for (auto i : v) { _print(i); cerr << ; } cerr << ] ; } long long mod = LONG_MAX; long long add(long long a, long long b) { return ((a % mod) + (b % mod)) % mod; } long long mul(long long a, long long b) { return ((a % mod) * (b % mod)) % mod; } long long sub(long long a, long long b) { return ((a % mod) - (b % mod) + mod) % mod; } long long max(long long a, long long b) { return (a > b) ? a : b; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(int a, int b) { return (a / gcd(a, b)) * b; } long long fe(long long base, long long exp) { long long ans = 1; while (exp) { if (exp & 1) ans = mul(ans, base); base = mul(base, base); exp >>= 1; } return ans; } long long fact(long long n) { long long res = 1; for (int i = 1; i <= n; i++) { res = res * 1ll * i % mod; } return res; } long long modin(long long a) { return fe(a, mod - 2); } long long nCr(long long a, long long b) { if (a < b) return 0; return mul(fact(a), mul(modin(fact(b)), modin(fact(a - b)))); } void solve() { long long n; cin >> n; vector<long long> eve, odd; for (int i = 1; i < 2 * n + 1; i++) { long long x; cin >> x; if (x % 2) odd.push_back(i); else eve.push_back(i); } for (int i = 0; i < n - 1; i++) { if (eve.size() > 1) { cout << eve[eve.size() - 1] << ; eve.pop_back(); cout << eve[eve.size() - 1] << n ; eve.pop_back(); } else { cout << odd[odd.size() - 1] << ; odd.pop_back(); cout << odd[odd.size() - 1] << n ; odd.pop_back(); } } } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); ; int t = 1; cin >> t; while (t--) { solve(); } cerr << time taken : << (float)clock() / CLOCKS_PER_SEC << secs << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> using min_pq = priority_queue<T, vector<T>, greater<T>>; template <typename T> using max_pq = priority_queue<T>; const int inf = 2e9 + 5; const long long l_inf = 2e18 + 5; const int mod_v = 1e9 + 7; const int max_n = 1e5 + 5; const int dx[4] = {-1, 0, 1, 0}; const int dy[4] = {0, 1, 0, -1}; template <typename T> T gcd(T a, T b) { while (b) { T temp = a % b; a = b; b = temp; } return a; } template <typename T> tuple<T, T, T> egcd(T a, T b) { T x1 = 1, x2 = 0, y1 = 0, y2 = 1; while (b) { T q = a / b, r = a % b; T new_x = x1 - q * x2, new_y = y1 - q * y2; x1 = x2, y1 = y2, x2 = new_x, y2 = new_y; a = b, b = r; } return make_tuple(a, x1, y1); } inline long long lcm(long long a, long long b) { return a * b / gcd(a, b); } template <typename T> inline T mod(T a, T b = mod_v) { return (a % b + b) % b; } template <typename T> inline T mod_inv(T a, T b = mod_v) { return mod(get<1>(egcd(a, b)), b); } template <typename T> inline T sum(T a, T b, T m = mod_v) { return mod(mod(a, m) + mod(b, m), m); } template <typename T> inline T difference(T a, T b, T m = mod_v) { return mod(mod(a, m) - mod(b, m), m); } inline long long product(long long a, long long b, long long m = mod_v) { return mod(mod(a, m) * mod(b, m), m); } inline long long quotient(long long a, long long b, long long m = mod_v) { return mod(mod(a, m) * mod_inv(b, m), m); } template <typename T, typename T2> ostream &operator<<(ostream &s, const pair<T, T2> &p) { return s << p.first << << p.second << ; } template <typename T, typename T2> istream &operator>>(istream &s, pair<T, T2> &p) { return s >> p.first >> p.second; } template <typename T> ostream &operator<<(ostream &s, const vector<T> &v) { for (auto it : v) s << it << ; return s; } template <typename T> istream &operator>>(istream &s, vector<T> &v) { for (auto it = (v).begin(), it_ = (v).end(); it != it_; ++it) s >> *it; return s; } template <typename T> void read_range(T beg, T end) { while (beg != end) cin >> *beg++; } template <typename T> void print_range(T beg, T end) { while (beg != end) cout << *beg++ << ; } struct reader { template <typename T> reader &operator,(T &v) { cin >> v; return *this; } } rdr; struct debugger { template <typename T> debugger &operator,(const T &v) { cerr << v << , ; return *this; } } dbg; int cnt[300]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; rdr, n; ; string s; rdr, s; ; if (n > 26) { cout << -1; return 0; } int ans = 0; for (char ch : s) { if (cnt[ch] != 0) ++ans; ++cnt[ch]; } cout << ans; return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) using namespace std; const long long MOD = 1000000007; const long long mod = 1000000007; const int Nmax = 2000006; long long gcd(long long a, long long b) { if (a == 0) { return b; } return gcd(b % a, a); } int lcm(int a, int b) { return (a * b) / gcd(a, b); } bool isPrime(long long n) { for (int i = 2; i <= sqrt(n); i++) if (n % i == 0) return 0; return 1; } void binaryRepresentation(int x) { for (int i = 31; i >= 0; i--) { if (x & (1 << i)) cout << 1 ; else cout << 0 ; } } long long combination(long long n, long long r) { if (r == n || r == 0) { return 1LL; } return combination(n - 1, r - 1) + combination(n - 1, r); } bool isPowerOfTwo(long long n) { if (n == 0) return false; return (ceil(log2(n)) == floor(log2(n))); } long long power(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = (ans * a) % MOD; b /= 2; a = (a * a) % MOD; } return ans % MOD; } long long inverse(long long i) { if (i == 1) return 1; return (MOD - ((MOD / i) * inverse(MOD % i)) % MOD + MOD) % MOD; } bool cmp(const pair<long long, long long> &a, const pair<long long, long long> &b) { if (a.first == b.first) return a.second < b.second; return a.first < b.first; } string toString(long long a) { ostringstream temp; temp << a; return temp.str(); } int main() { long long n, k; cin >> n >> k; long long ct = 1; if (k == 1) { cout << n; return 0; } while (ct <= n) { ct = ct * 2; } cout << ct - 1; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CONB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__CONB_FUNCTIONAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_ms__udp_pwrgood_pp_p.v"
`include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_ms__udp_pwrgood_pp_g.v"
`celldefine
module sky130_fd_sc_ms__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_ms__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_ms__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CONB_FUNCTIONAL_PP_V
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cout.tie(0); cin.tie(0); cout.precision(10); bool vozr = 1, ub = 1, same; int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; if (i != 0 && a[i] > a[i - 1]) ub = 0; if (i != 0 && a[i] < a[i - 1]) vozr = 0; } if (n <= 2 || (vozr && ub)) { cout << -1 << n ; return 0; } if (vozr) { same = 1; for (int i = 2; i < n - 1; i++) { if (a[i] != a[i - 1]) same = 0; } if (same) { if (a[n - 2] == a[n - 1]) cout << 1 << << n - 1 << n ; else cout << n - 1 << << n << n ; } else cout << 1 << << n << n ; } else if (ub) { same = 1; for (int i = 2; i < n - 1; i++) { if (a[i] != a[i - 1]) same = 0; } if (same) { if (a[n - 2] == a[n - 1]) cout << 1 << << 2 << n ; else cout << n - 1 << << n << n ; } else cout << 1 << << n << n ; } else { if (n == 3) { if (a[0] == a[2]) cout << -1 << n ; else cout << 1 << << 3 << n ; } else { int minn = 1100000000, maxx = -1, id1, id2; for (int i = 0; i < n; i++) { if (a[i] < minn) { minn = a[i]; id1 = i; } if (a[i] >= maxx) { maxx = a[i]; id2 = i; } } if (id1 == 0) { if (id2 == n - 1) cout << 1 << << n << n ; else { if (id2 == 1) cout << 2 << << 3 << n ; else cout << 2 << << id2 + 1 << n ; } } else { if (id1 == 1) cout << 2 << << 3 << n ; else cout << 2 << << id1 + 1 << n ; } } } return 0; }
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#include <bits/stdc++.h> using namespace std; void solve() { long long int n, k; cin >> n >> k; string s; cin >> s; string ans = ; long long int reqd = k / 2, op = 0, cl = 0; for (auto x : s) { if (op < reqd) { if (x == ( ) { ans.push_back(x); op++; } } if (cl < reqd) { if (x == ) ) { ans.push_back(x); cl++; } } if (op == reqd and cl == reqd) { break; } } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); solve(); }
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#include <bits/stdc++.h> using namespace std; int a[1111111]; int main() { ios_base::sync_with_stdio(false); int n; long long ts, tf, t; cin >> ts >> tf >> t; cin >> n; long long ansV = ts, ans = 0; long long total = ts; for (int i = 0; i <= n; i++) { long long x; if (i == n) { x = tf - t + 1; } else { cin >> x; } if (x - 1 >= total) { if (total + t <= tf) { ansV = 0; ans = total; } } else { if (total + t <= tf) { if (total - (x - 1) < ansV) { ansV = total - (x - 1); ans = x - 1; } } } total = max(total, x) + t; } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int a[110], b[110], cnt, n; map<int, int> mp; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { int num; scanf( %d , &num); if (!mp[num]) { mp[num]++; b[cnt++] = num; } } sort(b, b + cnt); if (cnt == 1) printf( 0 ); else if (cnt == 2) { if (abs(b[1] - b[0]) % 2) printf( %d , abs(b[1] - b[0])); else printf( %d , abs(b[1] - b[0]) / 2); } else if (cnt == 3 && ((b[1] - b[0]) == (b[2] - b[1]))) printf( %d , b[1] - b[0]); else printf( -1 ); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 10; const long long mod = 1e9 + 7; long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + c - 0 , c = getchar(); return x * f; } double ans; struct BIT { long long tr[N]; long long Bmax; long long lb(long long x) { return (-x) & x; } void init(long long n) { Bmax = n; for (long long i = 0; i <= n; i++) tr[i] = 0; } long long query(long long x) { if (x <= 0) return 0; long long res = 0; while (x) { res += tr[x]; x -= lb(x); } return res; } void update(long long x, long long w) { if (x <= 0) return; while (x <= Bmax) { tr[x] += w; x += lb(x); } } } t1, t2; int a[N]; int main() { long long n = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (long long i = 1; i <= n; i++) { ans += (double)1.00 * i * (i - 1) / 4.00 * (n - i + 1); } t1.init(n); t2.init(n); for (long long i = 1; i <= n; i++) { long long o1 = t1.query(n) - t1.query(a[i]); long long o2 = t2.query(n) - t2.query(a[i]); t1.update(a[i], 1); t2.update(a[i], i); ans += (double)(1.00 * n * (n + 1) * o1 * 0.5 - 1.00 * (n - i + 1) * o2); } printf( %.10lf , ans / (1.00 * n * (n + 1) / 2)); }
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#include <bits/stdc++.h> int setBit(int N, int pos) { return N = N | (1 << pos); } int resetBit(int N, int pos) { return N = N & ~(1 << pos); } bool checkBit(int N, int pos) { return (bool)(N & (1 << pos)); } using namespace std; const int maxn = 100000; int n, m, cost[maxn + 5], okayRoad[maxn + 5], par[maxn + 5]; vector<int> graph[maxn + 5], flag[maxn + 5]; map<pair<int, int>, int> mapp, out; map<pair<int, int>, int>::iterator it; void bfs() { queue<int> q; int i, u, v; memset(cost, 63, sizeof(cost)); ; cost[1] = 0; par[1] = 1; q.push(1); while (!q.empty()) { u = q.front(); q.pop(); int siz = (int)graph[u].size(); for (i = 0; i < siz; i++) { v = graph[u][i]; if (cost[u] + 1 < cost[v]) { cost[v] = cost[u] + 1; okayRoad[v] = okayRoad[u] + flag[u][i]; par[v] = u; q.push(v); } else if (cost[u] + 1 == cost[v] && okayRoad[u] + flag[u][i] > okayRoad[v]) { okayRoad[v] = okayRoad[u] + flag[u][i]; par[v] = u; q.push(v); } } } } void giveOutput() { int u, v = n; vector<int> path; path.push_back(n); while (v != par[v]) { v = par[v]; path.push_back(v); } int i, j, siz = (int)path.size(); for (i = 1; i < siz; i++) { u = path[i - 1]; v = path[i]; if (u > v) swap(u, v); if (mapp[pair<int, int>(u, v)] == 0) out[pair<int, int>(u, v)] = 1; mapp[pair<int, int>(u, v)] = -1; } for (__typeof((mapp).begin()) it = (mapp).begin(); it != (mapp).end(); it++) { if (it->second == 1) out[it->first] = 0; } printf( %d n , (int)out.size()); for (__typeof((out).begin()) it = (out).begin(); it != (out).end(); it++) { cout << it->first.first << << it->first.second << << it->second << n ; } } int main() { int i, u, v, w; scanf( %d %d , &n, &m); for (i = 0; i < m; i++) { scanf( %d %d %d , &u, &v, &w); if (u > v) swap(u, v); graph[u].push_back(v); graph[v].push_back(u); flag[u].push_back(w); flag[v].push_back(w); mapp[pair<int, int>(u, v)] = w; } bfs(); giveOutput(); return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_3_rows_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_3_rows_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_3_rows_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_3_rows_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long fastPrime(long long n) { if (n == 2) return true; if (n % 2 == 0) return false; for (long long i = 3; i * i <= n; i++) { if (n % i == 0) return false; } return true; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, val; cin >> n; for (long long i = 0; i < n; i++) { cin >> val; long long sr = sqrt(val); if (val != 1 && fastPrime(sr) && sr * sr == val) cout << YES n ; else cout << NO n ; } return 0; }
|
// DESCRIPTION: Verilator: Simple static elaboration case
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
typedef struct packed {
logic [ 31 : 0 ] _five;
} five_t;
typedef enum {
LOW_FIVE = 32'hdeadbeef,
HIGH_FIVE
} five_style_t;
function five_t gimme_five ();
automatic five_t result;
result._five = 5;
return result;
endfunction
function five_style_t gimme_high_five ();
automatic five_style_t result;
result = HIGH_FIVE;
return result;
endfunction
localparam five_t FIVE = gimme_five();
localparam five_style_t THE_HIGH_FIVE = gimme_high_five();
initial begin
if (FIVE._five != 5) begin
$display("%%Error: Got 0b%b instead of 5", FIVE._five);
$stop;
end
if (THE_HIGH_FIVE != HIGH_FIVE) begin
$display("%%Error: Got 0b%b instead of HIGH_FIVE", THE_HIGH_FIVE);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBN_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDFBBN_PP_BLACKBOX_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBN_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = -1; const int INF = 1.01e9; const int MOD = 1e9 + 7; long long rev(long long a, long long m) { if (a == 0) return 0; return ((1 - rev(m % a, a) * m) / a + m) % m; } int main() { int n, k; scanf( %d%d , &n, &k); vector<long long> fact(n + 1); fact[0] = 1; for (int i = 1; i <= n; i++) { fact[i] = (fact[i - 1] * i) % MOD; } vector<long long> rfact(n + 1); rfact[n] = rev(fact[n], MOD); assert(fact[n] * rfact[n] % MOD == 1); for (int i = n - 1; i >= 0; i--) { rfact[i] = (rfact[i + 1] * (i + 1)) % MOD; } auto getC = [&](int nn, int kk) { assert(0 <= kk && kk <= nn); return fact[nn] * rfact[kk] % MOD * rfact[nn - kk] % MOD; }; vector<long long> f(n + 1); vector<long long> g(n + 1); vector<long long> prefG(n + 1); f[1] = 1; g[1] = 1; prefG[1] = 1; for (int i = 2; i <= n; i++) { long long tmp = prefG[i - 1]; if (i - k - 1 >= 1) { tmp = (tmp - prefG[i - k - 1] + MOD) % MOD; } tmp = (tmp * fact[i - 2]) % MOD; f[i] = tmp; g[i] = f[i] * rfact[i - 1] % MOD; prefG[i] = (prefG[i - 1] + g[i]) % MOD; } long long answer = 0; for (int i = 1; i <= n; i++) { answer = (answer + getC(n - 1, i - 1) * f[i] % MOD * fact[n - i]) % MOD; } cout << (fact[n] - answer + MOD) % MOD << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) bool iseven(long long int n) { if ((n & 1) == 0) return true; return false; } void print(long long int t) { cout << t; } void print(int t) { cout << t; } void print(string t) { cout << t; } void print(char t) { cout << t; } void print(double t) { cout << t; } void print(long double t) { cout << t; } template <class T, class V> void print(pair<T, V> p); template <class T> void print(vector<T> v); template <class T> void print(set<T> v); template <class T, class V> void print(map<T, V> v); template <class T> void print(multiset<T> v); template <class T, class V> void print(pair<T, V> p) { cout << { ; print(p.first); cout << , ; print(p.second); cout << } ; } template <class T> void print(vector<T> v) { cout << [ ; for (T i : v) { print(i); cout << ; } cout << ] ; } template <class T> void print(set<T> v) { cout << [ ; for (T i : v) { print(i); cout << ; } cout << ] ; } template <class T> void print(multiset<T> v) { cout << [ ; for (T i : v) { print(i); cout << ; } cout << ] ; } template <class T, class V> void print(map<T, V> v) { cout << [ ; for (auto i : v) { print(i); cout << ; } cout << ] ; } void solve() { long long int n; cin >> n; string s; cin >> s; string original = s; string ans = ; for (long long int i = 0; i < n; ++i) { ans += 9 ; } for (long long int i = 0; i < n; ++i) { s = original; long long int toincrease = 10 - (s[i] - 0 ); for (auto &ch : s) { long long int temp = (ch - 0 + toincrease) % 10; ch = 0 + temp; } string tempans = ; tempans += s[i]; long long int ptr = (i + 1) % n; while (ptr != i) { tempans += s[ptr]; ptr = (ptr + 1) % n; } ans = min(ans, tempans); } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo32_clk_crossing_with_usage.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo32_clk_crossing_with_usage (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdusedw,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output [12:0] rdusedw;
output [12:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [12:0] sub_wire1;
wire [12:0] sub_wire2;
wire [31:0] q = sub_wire0[31:0];
wire [12:0] rdusedw = sub_wire1[12:0];
wire [12:0] wrusedw = sub_wire2[12:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdusedw (sub_wire1),
.wrusedw (sub_wire2),
.eccstatus (),
.rdempty (),
.rdfull (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.add_usedw_msb_bit = "ON",
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 13,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 13 0 OUTPUT NODEFVAL "rdusedw[12..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 13 0 OUTPUT NODEFVAL "wrusedw[12..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdusedw 0 0 13 0 @rdusedw 0 0 13 0
// Retrieval info: CONNECT: wrusedw 0 0 13 0 @wrusedw 0 0 13 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_clk_crossing_with_usage.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_clk_crossing_with_usage.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_clk_crossing_with_usage.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_clk_crossing_with_usage.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_clk_crossing_with_usage_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_clk_crossing_with_usage_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module mojo_com #(
parameter ADDR_SPACE = 64 //addr is last 6 bits
)(
input clk,
input rst,
//SPI connections
input ss,
input sck,
input mosi,
output miso,
//Interface, doesn't guarantee atomicity
output [8*ADDR_SPACE-1:0] rx_arr,
output rx_busy,
output new_rx,
input [8*ADDR_SPACE-1:0] tx_arr,
output tx_busy
);
parameter ADDR_BITS = $clog2(ADDR_SPACE);
//SPI addressing setup
wire [ADDR_BITS-1:0] reg_addr;
wire [7:0] write_value, read_value;
wire write, new_req, in_transaction;
spi_addressing spi_interface(
.clk(clk),
.rst(rst),
//SPI pins
.spi_ss(ss),
.spi_sck(sck),
.spi_mosi(mosi),
.spi_miso(miso),
//Interface
.reg_addr(reg_addr),
.write(write),
.new_req(new_req),
.write_value(write_value),
.read_value(read_value),
.in_transaction(in_transaction)
);
mojo_com_logic #(.ADDR_SPACE(ADDR_SPACE)) com_logic (
.clk(clk),
.rst(rst),
//SPI addressing interface
.reg_addr(reg_addr),
.write(write),
.new_req(new_req),
.write_value(write_value),
.read_value(read_value),
.in_transaction(in_transaction),
//Interface
.rx_arr(rx_arr),
.rx_busy(rx_busy),
.new_rx(new_rx),
.tx_arr(tx_arr),
.tx_busy(tx_busy)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR3_1_V
`define SKY130_FD_SC_LP__XOR3_1_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR3_1_V
|
#include <bits/stdc++.h> using namespace std; long long n, k, res, ans[1010101]; queue<long long> q; stack<long long> st; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; for (long long i = 1; i <= n; ++i) { st.push(i); q.push(i); k -= i; res += i; } if (k < 0) { cout << -1; return 0; } while (!st.empty() && !q.empty()) { long long vt1 = st.top(), vt2 = q.front(); if (vt2 > vt1) break; if (k < vt1 - vt2) { st.pop(); ans[vt1] = vt1; } else { ans[vt1] = vt2; ans[vt2] = vt1; k -= vt1 - vt2; res += vt1 - vt2; st.pop(); q.pop(); } } cout << res << n ; for (long long i = 1; i <= n; ++i) cout << ans[i] << ; cout << n ; for (long long i = 1; i <= n; ++i) cout << i << ; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; long long int a[n], sum = 0, fg = 0, cnt = 0, ind = 1, ans = 0; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { if (a[i] <= ind) { ind++; continue; } ans = ans + a[i] - ind; ind = a[i] + 1; } cout << ans; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void input() {} void solve() { long long int n, m; cin >> n >> m; long long int a[n][m]; long long int flag = 1, temp = 0; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { char ch; cin >> ch; if (ch == A ) { a[i][j] = 1; } else { a[i][j] = 0; } if (a[i][j]) { flag = 0; } temp += a[i][j]; } } if (temp == n * m) { cout << 0 ; return; } if (flag) { cout << MORTAL ; return; } for (long long int i = 0; i < 1; i++) { long long int cnt1 = 0, cnt2 = 0; for (long long int j = 0; j < m; j++) { if (a[0][j]) { cnt1++; } if (a[n - 1][j]) { cnt2++; } } if (cnt1 == m || cnt2 == m) { cout << 1 ; return; } } for (long long int j = 0; j < 1; j++) { long long int cnt1 = 0, cnt2 = 0; for (long long int i = 0; i < n; i++) { if (a[i][0]) { cnt1++; } if (a[i][m - 1]) { cnt2++; } } if (cnt1 == n || cnt2 == n) { cout << 1 ; return; } } for (long long int i = 1; i < n - 1; i++) { long long int cnt = 0; for (long long int j = 0; j < m; j++) { if (a[i][j]) { cnt++; } } if (cnt == m) { cout << 2 ; return; } } for (long long int j = 1; j < m - 1; j++) { long long int cnt = 0; for (long long int i = 0; i < n; i++) { if (a[i][j]) { cnt++; } } if (cnt == n) { cout << 2 ; return; } } if (a[0][m - 1] || a[0][0] || a[n - 1][0] || a[n - 1][m - 1]) { cout << 2 ; return; } long long int cnt = 0; for (long long int i = 0; i < n; i++) { cnt += a[i][0]; cnt += a[i][m - 1]; } for (long long int i = 0; i < m; i++) { cnt += a[0][i]; cnt += a[n - 1][i]; } if (cnt) { cout << 3 ; } else { cout << 4 ; } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); input(); int t = 1, i = 1; cin >> t; while (t--) { solve(); cout << n ; } }
|
#include <bits/stdc++.h> int main() { int a, i; char b, c, x; scanf( %d , &a); scanf( %c , &b); for (i = 1; i <= a - 2; i++) scanf( %c , &x); scanf( %c , &c); if (b == S && c == F ) printf( YES ); else printf( NO ); }
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; int main() { int num, dig; scanf( %d%d , &num, &dig); vector<int> a, b; for (int i = 0; i < num / dig; i++) { int z; scanf( %d , &z); a.push_back(z); } for (int i = 0; i < num / dig; i++) { int z; scanf( %d , &z); b.push_back(z); } int t = 1; for (int i = 0; i < dig - 1; i++) t *= 10; long long ret = 1; for (int i = 0; i < num / dig; i++) { long long r = 0; for (int j = 0; j < 10; j++) { if (j != b[i]) { r += (t * (j + 1) + a[i] - 1) / a[i]; r -= (t * j + a[i] - 1) / a[i]; } } ret *= r; ret %= mod; } printf( %I64d n , ret); }
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=25 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=altpll_myfirstfpga" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 16.0 cbx_altclkbuf 2016:04:27:18:05:34:SJ cbx_altiobuf_bidir 2016:04:27:18:05:34:SJ cbx_altiobuf_in 2016:04:27:18:05:34:SJ cbx_altiobuf_out 2016:04:27:18:05:34:SJ cbx_altpll 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
//CBXI_INSTANCE_NAME="DE0_myfirstfpga_altpll_myfirstfpga_dac_pll_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altpll_myfirstfpga_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 25,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //altpll_myfirstfpga_altpll
//VALID FILE
|
`timescale 1ps / 1ps
module main;
reg clk = 0;
always #300 clk = !clk;
reg A,B,C;
integer ret;
integer tvec_file;
reg Aval,Bval,Cval,Gval;
integer delay=0;
reg [3:0] gg="0000";
initial begin
$sdf_annotate("mydesign.sdf",DUT,,,"MAXIMUM");
$dumpfile("test.vcd");
$dumpvars(0,main);
tvec_file = $fopen("../test_circuit.tvec", "r");
if (tvec_file == 0) begin
$display("data_file handle was NULL");
$finish;
end
end
always @(posedge clk) begin
gg = {gg[2:0], gg[3]};
ret = $fscanf(tvec_file, "%b,%b,%b,%b\n", Aval,Bval,Cval,Gval);
if (!$feof(tvec_file)) begin
A = Aval;
B = Bval;
C = Cval;
gg[0] = Gval;
end
else
begin
if (delay==4) begin
$display("SoE: %d",sum_of_errors);
$finish;
end
else begin
gg[0] = Gval;
delay = delay + 1;
end
end
end
wire G;
test_circuit DUT (.clk(clk),
.A(A),
.B(B),
.C(C),
.G(G));
//initial
// $monitor("At time %t: A=%b,B=%b,C=%b,G=%b",$time,A,B,C,G);
integer sum_of_errors=0;
always @(posedge clk) begin
if (G != gg[3]) begin
if (delay != 4) begin
//$display("ERROR At time %t: A=%b,B=%b,C=%b,G=%b,gg=%b",$time,A,B,C,G,gg);
sum_of_errors = sum_of_errors + 1;
end
end
end
always @(posedge clk) begin
//$display("At time %t: A=%b,B=%b,C=%b,G=%b,gg=%b,Gval=%b",$time,A,B,C,G,gg,Gval);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 4e5 + 10; int n, a[M], b[M], ans, cnt; int f(int x, int i) { return n - (x >> i) - (lower_bound(b, b + n, (1 << (i + 1)) - x) - b); } int32_t main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , a + i); for (int i = 0; i < 28; i++) { for (int j = 0; j < n; j++) b[j] = (a[j] & ((1 << (i + 1)) - 1)); sort(b, b + n); cnt = 0; for (int j = 0; j < n; j++) cnt += f(b[j], i); ans += (((cnt >> 1) & 1) << (i + 1)); } if (n % 2 == 0) for (int i = 0; i < n; i++) ans ^= a[i]; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; void *wmem; char memarr[10485760]; template <class T> inline void walloc1d(T **arr, int x, void **mem = &wmem) { static int skip[16] = {0, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1}; (*mem) = (void *)(((char *)(*mem)) + skip[((unsigned long long)(*mem)) & 15]); (*arr) = (T *)(*mem); (*mem) = ((*arr) + x); } inline void rd(int &x) { int k; int m = 0; x = 0; for (;;) { k = getchar(); if (k == - ) { m = 1; break; } if ( 0 <= k && k <= 9 ) { x = k - 0 ; break; } } for (;;) { k = getchar(); if (k < 0 || k > 9 ) { break; } x = x * 10 + k - 0 ; } if (m) { x = -x; } } inline void wt_L(char a) { putchar(a); } inline void wt_L(int x) { int s = 0; int m = 0; char f[10]; if (x < 0) { m = 1; x = -x; } while (x) { f[s++] = x % 10; x /= 10; } if (!s) { f[s++] = 0; } if (m) { putchar( - ); } while (s--) { putchar(f[s] + 0 ); } } struct unionFind { int *d; int N; int M; inline void malloc(const int n) { d = (int *)std::malloc(n * sizeof(int)); M = n; } inline void free(void) { std::free(d); } inline void walloc(const int n, void **mem = &wmem) { walloc1d(&d, n, mem); M = n; } inline void init(const int n) { int i; N = n; for (i = (0); i < (n); i++) { d[i] = -1; } } inline void init(void) { init(M); } inline int get(int a) { int t = a; int k; while (d[t] >= 0) { t = d[t]; } while (d[a] >= 0) { k = d[a]; d[a] = t; a = k; } return a; } inline int connect(int a, int b) { if (d[a] >= 0) { a = get(a); } if (d[b] >= 0) { b = get(b); } if (a == b) { return 0; } if (d[a] < d[b]) { d[a] += d[b]; d[b] = a; } else { d[b] += d[a]; d[a] = b; } return 1; } inline int operator()(int a) { return get(a); } inline int operator()(int a, int b) { return connect(a, b); } inline int &operator[](const int a) { return d[a]; } inline int size(int a) { a = get(a); return -d[a]; } inline int sizeList(int res[]) { int i; int sz = 0; for (i = (0); i < (N); i++) { if (d[i] < 0) { res[sz++] = -d[i]; } } return sz; } }; int N; int M; int Q; int X; int Y; int C; int res[2000000 + 2]; int mp[300][300]; vector<int> tmm[2000000 + 1]; vector<int> type[2000000 + 1]; vector<int> place[2000000 + 1]; int main() { wmem = memarr; int i; int j; int k; int c; int t; int x; int y; int nx; int ny; int d; int dx[4] = {-1, 1, 0, 0}; int dy[4] = {0, 0, -1, 1}; unionFind uf; rd(N); rd(M); rd(Q); for (i = (0); i < (N * M); i++) { tmm[0].push_back(0); type[0].push_back(1); place[0].push_back(i); } for (i = (0); i < (Q); i++) { rd(X); X += (-1); rd(Y); Y += (-1); rd(C); if (mp[X][Y] == C) { continue; } k = mp[X][Y]; tmm[k].push_back(i + 1); type[k].push_back(-1); place[k].push_back(X * M + Y); k = mp[X][Y] = C; tmm[k].push_back(i + 1); type[k].push_back(1); place[k].push_back(X * M + Y); } for (i = (0); i < (N * M); i++) { k = mp[i / M][i % M]; tmm[k].push_back(Q + 1); type[k].push_back(-1); place[k].push_back(i); } uf.walloc(N * M); for (k = (0); k < (2000000 + 1); k++) { if (tmm[k].size()) { for (i = (0); i < (N); i++) { for (j = (0); j < (M); j++) { mp[i][j] = 0; } } uf.init(N * M); t = c = 0; for (i = (0); i < (tmm[k].size()); i++) { if (tmm[k][i] != t) { res[t] += c; t = tmm[k][i]; res[t] -= c; } if (type[k][i] == -1) { break; } x = place[k][i] / M; y = place[k][i] % M; mp[x][y] = 1; c++; for (d = (0); d < (4); d++) { nx = x + dx[d]; ny = y + dy[d]; if (nx < 0 || ny < 0 || nx >= N || ny >= M) { continue; } if (mp[nx][ny] == 1) { c -= uf(x * M + y, nx * M + ny); } } } for (i = (0); i < (N); i++) { for (j = (0); j < (M); j++) { mp[i][j] = 0; } } uf.init(N * M); t = Q + 1; c = 0; for (i = (tmm[k].size()) - 1; i >= (0); i--) { if (type[k][i] == 1) { break; } if (tmm[k][i] != t) { res[t] -= c; t = tmm[k][i]; res[t] += c; } x = place[k][i] / M; y = place[k][i] % M; mp[x][y] = 1; c++; for (d = (0); d < (4); d++) { nx = x + dx[d]; ny = y + dy[d]; if (nx < 0 || ny < 0 || nx >= N || ny >= M) { continue; } if (mp[nx][ny] == 1) { c -= uf(x * M + y, nx * M + ny); } } } } } for (i = (1); i < (Q + 1); i++) { res[i] += res[i - 1]; wt_L(res[i]); wt_L( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int tt = 0; tt < int(t); tt++) { int a, b, c, r; cin >> a >> b >> c >> r; int L = max(min(a, b), c - r); int R = min(max(a, b), c + r); cout << max(a, b) - min(a, b) - max(0, R - L) << endl; } }
|
/*
-------------------------------------------------------------------------------
This file is part of the hardware description for the Propeller 1 Design
for Pipistrello LX45.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
// Andy Silverman 20140902 Added support for 100Mhz input clock as on the Digilent
// Nexys4 (Artix7-based board.)
//
// Copyright 2014 Saanlima Electronics
//
// Magnus Karlsson 20140820 Moved reg and wire declarations to top of file
// Added PLL or DCM selection option
// Added dtr or inp_resn selection option
//
// Magnus Karlsson 20140818 Wrote top level verilog module from scratch based
// on top.tdf and tim.tdf in the Parallax release.
//`define use_pll 1 // comment out for DCM mode
`define use_dtr 1 // comment out for inp_resn instead of dtr
`define Nexys4 1 // comment out for 50Mhz input clock, otherwise 100Mhz input is assumed.
module top
(
input clock_50, // clock input
`ifdef use_dtr
input dtr, // serial port DTR input
`else
input inp_resn, // reset input (active low)
`endif
inout [31:0] pin, // i/o pins
output [7:0] ledg, // cog leds
output tx_led, // tx monitor LED
output rx_led, // rx monitor LED
output p16_led, // monitor LED for pin 16
output p17_led // monitor LED for pin 17
);
//
// reg and wire declarations
//
reg nres;
wire [7:0] cfg;
wire [31:0] pin_in, pin_out, pin_dir;
wire clkfb, clock_160, clk;
reg [31:0] reset_cnt;
reg reset_to;
wire res;
reg [7:0] cfgx;
reg [12:0] divide;
wire clk_pll;
wire clk_cog;
//
// Clock generation
//
`ifdef use_pll
//
// PLL (50 MHz -> 160 MHz)
//
PLL_BASE # (
`ifdef Nexys4 //Nexys4 input clock = 100Mhz, not 50.
.CLKIN_PERIOD(10),
.CLKFBOUT_MULT(8),
`else
.CLKIN_PERIOD(20),
.CLKFBOUT_MULT(16),
`endif
.CLKOUT0_DIVIDE(5),
.COMPENSATION("INTERNAL")
) PLL (
.CLKFBOUT(clkfb),
.CLKOUT0(clock_160),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.LOCKED(),
.CLKFBIN(clkfb),
.CLKIN(clock_50),
.RST(1'b0)
);
`else
//
// DCM (50 MHz -> 160 MHz)
//
DCM_SP DCM_SP_(
.CLKIN(clock_50),
.CLKFB(clkfb),
.RST(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PSCLK(1'b0),
.DSSEN(1'b0),
.CLK0(clkfb),
.CLK90(),
.CLK180(),
.CLK270(),
.CLKDV(),
.CLK2X(),
.CLK2X180(),
.CLKFX(clock_160),
.CLKFX180(),
.STATUS(),
.LOCKED(),
.PSDONE());
defparam DCM_SP_.CLKIN_DIVIDE_BY_2 = "FALSE";
defparam DCM_SP_.CLK_FEEDBACK = "1X";
defparam DCM_SP_.CLKFX_DIVIDE = 5;
`ifdef Nexys4
defparam DCM_SP_.CLKFX_MULTIPLY = 8;
defparam DCM_SP_.CLKIN_PERIOD = 10;
`else
defparam DCM_SP_.CLKFX_MULTIPLY = 16;
defparam DCM_SP_.CLKIN_PERIOD = 20;
`endif
`endif
BUFG BUFG_clk(.I(clock_160), .O(clk));
assign clk_pll = ((cfgx[6:5] == 2'b11) && (cfgx[2:0] == 3'b111)) ? clock_160 : divide[11];
assign clk_cog = divide[12];
`ifdef use_dtr
//
// Emulate RC filter on Prop Plug by generating a long reset pulse
// everytime DTR goes high
//
always @ (posedge clk or negedge dtr)
if (!dtr) begin
reset_cnt <= 32'd0;
reset_to <= 1'b0;
end else begin
reset_cnt <= reset_to ? reset_cnt : reset_cnt + 1;
reset_to <= (reset_cnt == 32'h4c4b40) ? 1'b1 : reset_to; //50ms delay value lowered to handle Nexys 4's 100Mhz input clk.
end
wire inp_resn = ~(dtr & ~reset_to);
`endif
//
// Clock control (from tim.tdf)
//
assign res = ~inp_resn;
always @ (posedge clk)
cfgx <= cfg;
always @ (posedge clk)
divide <= divide +
{ (cfgx[6:5] == 2'b11 && cfgx[2:0] == 3'b111) || res,
cfgx[6:5] == 2'b11 && cfgx[2:0] == 3'b110 && !res,
cfgx[6:5] == 2'b11 && cfgx[2:0] == 3'b101 && !res,
((cfgx[6:5] == 2'b11 && cfgx[2:0] == 3'b100) || cfgx[2:0] == 3'b000) && !res,
((cfgx[6:5] == 2'b11 && cfgx[2:0] == 3'b011) || (cfgx[5] == 1'b1 && cfgx[2:0] == 3'b010)) && !res,
7'b0,
cfgx[2:0] == 3'b001 && !res
};
//
// Propeller 1 core module
//
always @ (posedge clk_cog)
nres <= inp_resn & !cfgx[7];
dig core ( .nres (nres),
.cfg (cfg),
.clk_cog (clk_cog),
.clk_pll (clk_pll),
.pin_in (pin_in),
.pin_out (pin_out),
.pin_dir (pin_dir),
.cog_led (ledg) );
//
// Bidir I/O buffers
//
genvar i;
generate
for (i=0; i<32; i=i+1)
begin : iogen
IOBUF io_ (.IO(pin[i]), .O(pin_in[i]), .I(pin_out[i]), .T(~pin_dir[i]));
end
endgenerate
//
// Monitor LEDs
//
//assign tx_led = pin_in[30];
//assign rx_led = pin_in[31];
//assign p16_led = pin_in[16];
//assign p17_led = pin_in[17];
endmodule
|
#include <bits/stdc++.h> using namespace std; namespace io { void _(int &k) { char c; int e = 1; k = 0; while ((c = getchar()) > 9 || c < 0 ) if (c == - ) e = -1; k = c - 0 ; while ((c = getchar()) <= 9 && c >= 0 ) { k *= 10; k += c - 0 ; } k *= e; } void _(long long &k) { char c; int e = 1; k = 0; while ((c = getchar()) > 9 || c < 0 ) if (c == - ) e = -1; k = c - 0 ; while ((c = getchar()) <= 9 && c >= 0 ) { k *= 10; k += c - 0 ; } k *= e; } void _(char &c) { while ((c = getchar()) == || c == n ) ; } void _(double &c) { scanf( %lf , &c); } void _(char *s) { char c; while ((c = getchar()) != EOF && c != && c != 10) *s++ = c; } template <class t1, class t2> void _(t1 &a, t2 &b) { _(a); _(b); } template <class t1, class t2, class t3> void _(t1 &a, t2 &b, t3 &c) { _(a); _(b); _(c); } template <class t1, class t2, class t3, class t4> void _(t1 &a, t2 &b, t3 &c, t4 &d) { _(a); _(b); _(c); _(d); } template <class t1, class t2, class t3, class t4, class t5> void _(t1 &a, t2 &b, t3 &c, t4 &d, t5 &e) { _(a); _(b); _(c); _(d); _(e); } void _p(double k) { printf( %.6lf , k); } void _p(char *c) { for (; *c; putchar(*c++)) ; } void _p(const char *c) { for (; *c; putchar(*c++)) ; } void _p(char c) { putchar(c); } template <class T> void _p0(T k) { if (k >= 10) _p0(k / 10); putchar(k % 10 + 0 ); } template <class T> void _p(T k) { if (k < 0) { putchar( - ); _p0(-k); } else _p0(k); } template <class T> void __p(T k) { _p(k); putchar( ); } template <class T> void _pn(T k) { _p(k); putchar( n ); } template <class t1, class t2> void _p(t1 a, t2 b) { __p(a); _pn(b); } template <class t1, class t2, class t3> void _p(t1 a, t2 b, t3 c) { __p(a); __p(b); _pn(c); } template <class t1, class t2, class t3, class t4> void _p(t1 a, t2 b, t3 c, t4 d) { __p(a); __p(b); __p(c); _pn(d); } template <class T> void op(T *a, int n) { int i; n--; for (i = 1; i <= n; i++) __p(a[i]); _pn(a[n + 1]); } int gi() { int first; _(first); return first; } long long gll() { long long first; _(first); return first; } } // namespace io int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } void fcl() { fclose(stdin); fclose(stdout); } void fop(const char *s) { char c[256], d[256]; memset(c, 0, sizeof(c)); memset(d, 0, sizeof(d)); strcpy(c, s); strcpy(d, s); freopen(strcat(c, .in ), r , stdin); freopen(strcat(d, .out ), w , stdout); } int eq(double a, double b) { return a + 0.00000000001 >= b && b + 0.00000000001 >= a; } template <class T> void _ma(T &a, T b) { if (a < b) a = b; } template <class T> void _mi(T &a, T b) { if (a > b) a = b; } const int N = 1234567, EE = 100000000, GG = 1000000000, ima = 2147483647; using namespace io; int n, m, a[N], f[N], an, T; char s[555][555]; int main() { int i, j, a1, a2; _(n); for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) _(s[i][j]); for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) an += s[i][j] == X && s[i + 1][j + 1] == X && s[i + 1][j - 1] == X && s[i - 1][j + 1] == X && s[i - 1][j - 1] == X ; _pn(an); }
|
#include <bits/stdc++.h> using namespace std; char s[10]; int main() { scanf( %s , s); int res = 1; for (int i = 1; i < 7; i++) { if (s[i] == 1 ) res += 10, i++; else res += s[i] - 0 ; } printf( %d n , res); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_BLACKBOX_V
`define SKY130_FD_SC_HS__XOR3_BLACKBOX_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_BLACKBOX_V
|
`timescale 1ns / 1ps
`define NULL 0
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/22/2015 02:49:20 PM
// Design Name:
// Module Name: pcap_wrapper_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pcap_wrapper_tb #(
parameter pcap_filename = "/home/jf.zazo/Desktop/FPGA/detectpro_isa/driver/user/Trazas/2flujos_crc"
)(
);
reg clk;
reg rst_n;
reg [127 : 0] pcap_tdata;
reg pcap_tvalid;
wire pcap_tready;
reg pcap_finished;
integer file = 0;
integer dump_file = 0;
always
#5 clk = !clk;
initial begin
clk = 0;
rst_n = 0;
pcap_finished = 0;
pcap_tvalid = 0;
pcap_tdata = 0;
#20;
rst_n = 1;
#15
//open file
if (pcap_filename == "none") begin
$display("Memory filename parameter not set");
$finish;
end
file = $fopen(pcap_filename, "rb");
if (file == `NULL) begin
$display("can't read memory input %s", pcap_filename);
$finish;
end
$display("MEMORY: %m reading from %s", pcap_filename);
while(!$feof(file)) begin
#1
pcap_tvalid = 1;
if(pcap_tready) begin
pcap_tdata[0*8+:8] <= $fgetc(file);
pcap_tdata[1*8+:8] <= $fgetc(file);
pcap_tdata[2*8+:8] <= $fgetc(file);
pcap_tdata[3*8+:8] <= $fgetc(file);
pcap_tdata[4*8+:8] <= $fgetc(file);
pcap_tdata[5*8+:8] <= $fgetc(file);
pcap_tdata[6*8+:8] <= $fgetc(file);
pcap_tdata[7*8+:8] <= $fgetc(file);
pcap_tdata[8*8+:8] <= $fgetc(file);
pcap_tdata[9*8+:8] <= $fgetc(file);
pcap_tdata[10*8+:8] <= $fgetc(file);
pcap_tdata[11*8+:8] <= $fgetc(file);
pcap_tdata[12*8+:8] <= $fgetc(file);
pcap_tdata[13*8+:8] <= $fgetc(file);
pcap_tdata[14*8+:8] <= $fgetc(file);
pcap_tdata[15*8+:8] <= $fgetc(file);
end
#9
pcap_tvalid = 1;
// @(posedge pcap_tready)
end
#15
pcap_finished = 1'b1;
end
initial begin
@(posedge pcap_finished)
#1000
$fclose(dump_file);
$fclose(file);
$finish;
end
pcap2hwgen pcap2hwgen_i (
.CLK(clk),
.RST_N(rst_n),
.PCAP_TVALID(pcap_tvalid),
.PCAP_TREADY(pcap_tready),
.PCAP_TDATA(pcap_tdata),
.HWGEN_TVALID(),
.HWGEN_TREADY(1'b1),
.HWGEN_TDATA()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2000000 + 7; const int M = 26; const int mod = 999983; const int inf = 1e9 + 7; const double pi = acos(-1); const int maxn = N * 2; const double PI = acos(-1); int n, m; int a[N]; int dp[22][N]; string s; void solve() { cin >> n >> m; for (int i = (0); i < (n); i++) { cin >> s; for (int j = (0); j < (m); j++) { int u = s[j] - 0 ; a[j] = (a[j] << 1) | u; } } for (int i = (0); i < (m); i++) { dp[0][a[i]]++; } for (int k = (1); k < (n + 1); k++) { for (int mask = (0); mask < (1 << n); mask++) { if (k >= 2) dp[k][mask] = (k - 2 - n) * dp[k - 2][mask]; for (int p = (0); p < (n); p++) dp[k][mask] += dp[k - 1][mask ^ (1 << p)]; dp[k][mask] /= k; } } int ans = inf; for (int mask = (0); mask < (1 << n); mask++) { int cur = 0; for (int k = (0); k < (n + 1); k++) cur += min(k, n - k) * dp[k][mask]; ans = min(ans, cur); } cout << ans; } int main() { int T = 1; for (int i = (1); i < (T + 1); i++) { solve(); } }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:40:24 05/08/2015
// Design Name: IR_fetch
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_fetch.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: IR_fetch
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_fetch;
// Inputs
reg clock;
reg PC_source;
reg [11:0] PC_offset;
reg [11:0] ISR_adr;
reg branch_ISR;
reg stall_d;
reg stall_f;
reg flush_d;
// Outputs
wire [15:0] IR;
wire [11:0] PC;
// Instantiate the Unit Under Test (UUT)
IR_fetch uut (
.clock(clock),
.PC_source(PC_source),
.PC_offset(PC_offset),
.ISR_adr(ISR_adr),
.branch_ISR(branch_ISR),
.stall_d(stall_d),
.stall_f(stall_f),
.flush_d(flush_d),
.IR(IR),
.PC(PC)
);
initial begin
// Initialize Inputs
clock = 0;
PC_source = 0;
PC_offset = 0;
ISR_adr = 0;
branch_ISR = 0;
stall_f = 0;
stall_d = 0;
flush_d = 0;
// Wait 100 ns for global reset to finish
//#100;
#10;
#400;
flush_d = 1;
#20;
flush_d = 0;
end
always #10 clock = !clock;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_BLACKBOX_V
`define SKY130_FD_SC_HS__O32A_BLACKBOX_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o32a (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long mx = 2e6 + 10; int posx[] = {1, -1, 0, 0}; int posy[] = {0, 0, 1, -1}; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1, n, k, m, a, b, c, d, h; cin >> t; while (t--) { cin >> h >> c >> k; if (h + c >= 2 * k) { cout << 2 << endl; continue; } long long x = (c - k) / (h + c - (2 * k)); long long y = x + 1; long double xx = ((h * x) + (c * (x - 1))) / ((1.0) * 2 * x - 1); long double yy = ((h * y) + (c * (y - 1))) / ((1.0) * 2 * y - 1); if (abs(xx - k) <= abs(yy - k)) cout << 2 * x - 1 << endl; else cout << 2 * y - 1 << endl; } return 0; }
|
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