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#include <bits/stdc++.h> using namespace std; inline int in() { int32_t x; scanf( %d , &x); return x; } inline long long lin() { long long x; scanf( %lld , &x); return x; } const int maxn = 2e5 + 10; const int mod = 1e9 + 7; const long long infll = 1e18; const int inf = 1e9; int lcp[40][40]; string s[maxn]; int32_t main() { int n = in(), k = in(); for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { int where = 0; while (where < s[i].size() && where < s[j].size() && s[i][where] == s[j][where]) where++; lcp[i][j] = where; } } int res = 0; for (int mask = 0; mask < (1 << n); mask++) { if (__builtin_popcount(mask) - k) continue; vector<int> Ids; for (int i = 0; i < n; i++) if (mask >> i & 1) Ids.push_back(i); int tot = 0; for (int i = 0; i < Ids.size(); i++) for (int j = i + 1; j < Ids.size(); j++) tot += lcp[Ids[i]][Ids[j]]; res = max(res, tot); } cout << res << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long int N = 1e6 + 3; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int t; cin >> t; while (t--) { long long int n, m; cin >> n; long long int a[n + 1]; long long int i = 0; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); long long int flag = 0; for (i = 1; i < n; i++) { if (abs(a[i] - a[i - 1]) > 1) { flag = 1; break; } } if (flag == 1) cout << NO << endl; else cout << YES << endl; } }
|
#include <bits/stdc++.h> const int long long N = 10e8 + 7; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; int arr[n]; vector<int> odd, even; for (int i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] % 2 == 0) even.push_back(arr[i]); else odd.push_back(arr[i]); } int p = int(odd.size()), q = even.size(); if (p % 2 == 0 && q % 2 == 0) { cout << YES << n ; continue; } bool flag = 0; for (int i = 0; i < p; i++) { for (int j = 0; j < q; j++) { if (int(abs(even[j] - odd[i])) == 1) flag = 1; } if (flag) break; } if (flag) cout << YES << n ; else cout << NO << n ; } }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using vvi = vector<vi>; using pii = pair<int, int>; constexpr auto MOD = 1000000007LL; constexpr auto LINF = (1LL << 60); constexpr auto INF = 2147483647LL; constexpr auto PI = 3.1415926535897932384626433; constexpr auto EPS = 1E-9; template <typename T1, typename T2> ostream &operator<<(ostream &out, const pair<T1, T2> p) { out << p.first << << p.second; return out; } template <typename T1, typename T2> istream &operator>>(istream &in, pair<T1, T2> &p) { in >> p.first >> p.second; return in; } template <typename T> istream &operator>>(istream &in, vector<T> &v) { for (auto &x : v) in >> x; return in; } template <typename T> ostream &operator<<(ostream &out, vector<T> v) { for (int i = 0; i < v.size(); i++) out << v[i] << (i + 1 == v.size() ? n : ); out.flush(); return out; } int n, k, a[2][300010]; int tail[2], nxttail[2]; int main() { ios_base::sync_with_stdio(false); cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[0][i]; for (int i = 0; i < n; i++) cin >> a[1][i]; if (k == 1) { int tail = 3; for (int i = 0; i < n; i++) { if (abs(a[0][i] - a[1][i]) > 1) { cout << NO << endl; return 0; } if (a[0][i] > a[1][i]) { if ((tail & 2) == 0) { cout << NO << endl; return 0; } tail = 1; } else if (a[1][i] > a[0][i]) { if ((tail & 1) == 0) { cout << NO << endl; return 0; } tail = 2; } else ; } cout << YES << endl; return 0; } for (int i = 0; i < n; i++) { nxttail[0] = nxttail[1] = INF; for (int t = 0; t < 2; t++) { if (tail[t] > k) continue; if (a[t][i] >= a[t ^ 1][i]) { int groups = 1 + (a[t][i] - (k - tail[t]) + k - 1) / k; if (a[t ^ 1][i] < groups - 1) continue; else if (a[t ^ 1][i] == groups - 1) { nxttail[t] = min(nxttail[t], (a[t][i] - (k - tail[t]) - 1) % k + 1); } else if (a[t ^ 1][i] > groups - 1) { nxttail[t ^ 1] = nxttail[t] = 1; } } else { int groups = (a[t ^ 1][i] + k - 1) / k; if (a[t][i] < groups - 1) continue; else if (a[t][i] == groups - 1) { nxttail[t ^ 1] = min(nxttail[t ^ 1], (a[t ^ 1][i] - 1) % k + 1); } else if (a[t][i] > groups - 1) { nxttail[t] = nxttail[t ^ 1] = 1; } } } tail[0] = nxttail[0]; tail[1] = nxttail[1]; } cout << (min(tail[0], tail[1]) <= k ? YES : NO ) << endl; return 0; }
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2016/02/08 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR3_BLACKBOX_V
`define SKY130_FD_SC_HDLL__XNOR3_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int P = 998244353; int add(int a, int b) { if ((a += b) >= P) a -= P; return a < 0 ? a + P : a; } int mul(int a, int b) { return 1ll * a * b % P; } int kpow(int a, int b) { int r = 1; for (; b; b >>= 1, a = mul(a, a)) { if (b & 1) r = mul(r, a); } return r; } const int N = 3e5 + 7; int f[N][2][2], n, u, v, pre[N], suf[N]; vector<int> g[N]; void dfs(int u, int fa) { int p = -1; for (int i = (0); i < ((int)g[u].size()); i++) if (g[u][i] == fa) { p = i; break; } if (p >= 0) g[u].erase(g[u].begin() + p); f[u][0][0] = 1; f[u][1][0] = 1; for (auto v : g[u]) { dfs(v, u); f[u][0][0] = mul(f[u][0][0], add(f[v][0][0], f[v][1][1])); f[u][1][0] = mul(f[u][1][0], add(f[v][0][0], mul(f[v][1][1], 2))); pre[v] = suf[v] = add(f[v][0][0], mul(f[v][1][1], 2)); } f[u][1][0] = add(f[u][1][0], -f[u][0][0]); for (int i = (1); i < ((int)g[u].size()); i++) pre[g[u][i]] = mul(pre[g[u][i]], pre[g[u][i - 1]]); for (int i = ((int)g[u].size() - 1) - 1; i >= (0); i--) suf[g[u][i]] = mul(suf[g[u][i]], suf[g[u][i + 1]]); for (int i = (0); i < ((int)g[u].size()); i++) { int v = g[u][i], t = add(f[v][1][0], f[v][0][0]); if (i) t = mul(t, pre[g[u][i - 1]]); if (i + 1 < (int)g[u].size()) t = mul(t, suf[g[u][i + 1]]); f[u][1][1] = add(f[u][1][1], t); } } int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); cin >> n; for (int i = (1); i < (n); i++) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } dfs(1, 0); cout << add(f[1][0][0], f[1][1][1]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A2BB2OI_FUNCTIONAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2OI_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long long n, m, ans, u, v, start; string opz; int vis[2][200005]; vector<int> grafo[2][200005]; void dfs(int nodo, int mode) { vis[mode][nodo] = 1; for (auto i : grafo[mode][nodo]) { if (vis[mode][i] == 1) { cout << -1 n ; exit(0); } if (vis[mode][i] == 0) { dfs(i, mode); } } vis[mode][nodo] = 2; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; opz.resize(n); for (int i = 0; i < m; i++) { cin >> u >> v; grafo[0][u].push_back(v); grafo[1][v].push_back(u); } for (int i = 1; i <= n; i++) { if (vis[0][i] == 0 && vis[1][i] == 0) { opz[i - 1] = A ; ans++; } else { opz[i - 1] = E ; } if (vis[0][i] == false) dfs(i, 0); if (vis[1][i] == false) dfs(i, 1); } cout << ans << n << opz << n ; return 0; }
|
`timescale 1ns/1ns
module mii_mgmt
#(parameter CLK_MHZ=0,
parameter MDC_KHZ=2500)
(input clk,
input [0:4] phyad,
input [0:4] addr,
input [15:0] wdata,
output [15:0] rdata,
input req,
input we,
output ack,
output mdc,
inout mdio);
// IEEE 802.3-2008 section 22.2.2.11 says mdc must have
// a period > 400ns, so we need to divide the user clock
//`include "clog2.inc"
localparam MDC_DIV_WIDTH = 8; //`clog2(CLK_MHZ*1000/MDC_KHZ);
// generate mdc
wire [MDC_DIV_WIDTH-1:0] div_cnt;
wire [MDC_DIV_WIDTH-1:0] div_cnt_p1 = div_cnt + 1'b1;
r #(MDC_DIV_WIDTH) div_reg
(.c(clk), .d(div_cnt_p1), .rst(1'b0), .en(1'b1), .q(div_cnt));
assign mdc = div_cnt[MDC_DIV_WIDTH-1];
wire mdc_re = ~mdc & &div_cnt[MDC_DIV_WIDTH-2:0]; // high one clk before rising edge
wire mdc_fe = &div_cnt; // high one clk before falling edge
// state machine
localparam SW = 4;
localparam ST_IDLE = 4'd0;
localparam ST_PREAMBLE = 4'd1;
localparam ST_START = 4'd2;
localparam ST_OP1 = 4'd3;
localparam ST_OP2 = 4'd4;
localparam ST_PHYAD = 4'd5;
localparam ST_REGAD = 4'd6;
localparam ST_RD_TA = 4'd7;
localparam ST_RD_RECV = 4'd8;
localparam ST_WR_TA = 4'd9;
localparam ST_WR_SEND = 4'd10;
// ctrl[0] = mdio output
// ctrl[1] = mdio output enable
// ctrl[2] = receiving: 1 = use mdc_re, 0 = use mdc_fe
// ctrl[3] = clear count
// ctrl[SW+4-1:4] = next state
reg [SW+4-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+4-1:4];
wire step = ctrl[2] ? mdc_re : mdc_fe;
r #(SW) state_reg
(.c(clk), .d(next_state), .rst(1'b0), .en(step), .q(state));
// counter
wire [3:0] count;
wire [3:0] count_p1 = count + 1'b1;
r #(4) count_reg
(.c(clk), .d(count_p1), .rst(ctrl[3] & step), .en(step), .q(count));
// want to send bit 15 first, so swap wdata
wire [0:15] wdata_swap = wdata;
always @* begin
case(state)
ST_IDLE: // nxt_state clr_cnt rcving, mdo_oe, mdo
if (req) ctrl = {ST_PREAMBLE, 1'b1, 1'b0, 1'b0, 1'b0};
else ctrl = {ST_IDLE, 1'b1, 1'b0, 1'b0, 1'b0};
ST_PREAMBLE:
if (&count) ctrl = {ST_START, 1'b1, 1'b0, 1'b1, 1'b1};
else ctrl = {ST_PREAMBLE, 1'b0, 1'b0, 1'b1, 1'b1};
ST_START:
if (~count[0]) ctrl = {ST_START, 1'b0, 1'b0, 1'b1, 1'b0};
else ctrl = {ST_OP1, 1'b1, 1'b0, 1'b1, 1'b1};
ST_OP1: ctrl = {ST_OP2, 1'b1, 1'b0, 1'b1, ~we};
ST_OP2: ctrl = {ST_PHYAD, 1'b1, 1'b0, 1'b1, we};
ST_PHYAD:
if (count[2]) ctrl = {ST_REGAD, 1'b1, 1'b0, 1'b1, phyad[count[2:0]]};
else ctrl = {ST_PHYAD, 1'b0, 1'b0, 1'b1, phyad[count[2:0]]};
ST_REGAD:
if (count[2])
if (we) ctrl = {ST_WR_TA, 1'b1, 1'b0, 1'b1, addr[count[2:0]]};
else ctrl = {ST_RD_TA, 1'b1, 1'b0, 1'b1, addr[count[2:0]]};
else ctrl = {ST_REGAD, 1'b0, 1'b0, 1'b1, addr[count[2:0]]};
ST_RD_TA:
if (~count[0]) ctrl = {ST_RD_TA, 1'b0, 1'b1, 1'b0, 1'b0};
else ctrl = {ST_RD_RECV, 1'b1, 1'b1, 1'b0, 1'b0};
ST_RD_RECV:
if (&count) ctrl = {ST_IDLE, 1'b1, 1'b1, 1'b0, 1'b0};
else ctrl = {ST_RD_RECV, 1'b0, 1'b1, 1'b0, 1'b0};
ST_WR_TA:
if (~count[0]) ctrl = {ST_WR_TA, 1'b0, 1'b0, 1'b1, 1'b1};
else ctrl = {ST_WR_SEND, 1'b1, 1'b0, 1'b1, 1'b0};
ST_WR_SEND:
if (&count) ctrl = {ST_IDLE, 1'b1, 1'b0, 1'b1, wdata_swap[count[3:0]]};
else ctrl = {ST_WR_SEND, 1'b0, 1'b0, 1'b1, wdata_swap[count[3:0]]};
default: ctrl = {ST_IDLE, 1'b1, 1'b0, 1'b0, 1'b0};
endcase
end
wire [15:0] next_rdata = {rdata[14:0], mdio};
wire latch_mdio = (state == ST_RD_RECV) & mdc_re;
r #(16) rdata_reg
(.c(clk), .d(next_rdata), .rst(1'b0), .en(latch_mdio), .q(rdata));
// only want to ack for one user clk cycle
wire done = (state == ST_IDLE);
wire ackd;
r #(1) ackd_reg
(.c(clk), .d(done), .rst(1'b0), .en(1'b1), .q(ackd));
assign ack = done & ~ackd;
assign mdio = ctrl[1] ? ctrl[0] : 1'bz;
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
module
recF16ToUi32 (
input [(`floatControlWidth - 1):0] control,
input [16:0] in,
input [2:0] roundingMode,
output [31:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(5, 11, 32)
recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);
endmodule
module
recF16ToUi64 (
input [(`floatControlWidth - 1):0] control,
input [16:0] in,
input [2:0] roundingMode,
output [63:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(5, 11, 64)
recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);
endmodule
module
recF16ToI32 (
input [(`floatControlWidth - 1):0] control,
input [16:0] in,
input [2:0] roundingMode,
output [31:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(5, 11, 32)
recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);
endmodule
module
recF16ToI64 (
input [(`floatControlWidth - 1):0] control,
input [16:0] in,
input [2:0] roundingMode,
output [63:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(5, 11, 64)
recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);
endmodule
module
recF32ToUi32 (
input [(`floatControlWidth - 1):0] control,
input [32:0] in,
input [2:0] roundingMode,
output [31:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(8, 24, 32)
recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);
endmodule
module
recF32ToUi64 (
input [(`floatControlWidth - 1):0] control,
input [32:0] in,
input [2:0] roundingMode,
output [63:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(8, 24, 64)
recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);
endmodule
module
recF32ToI32 (
input [(`floatControlWidth - 1):0] control,
input [32:0] in,
input [2:0] roundingMode,
output [31:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(8, 24, 32)
recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);
endmodule
module
recF32ToI64 (
input [(`floatControlWidth - 1):0] control,
input [32:0] in,
input [2:0] roundingMode,
output [63:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(8, 24, 64)
recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);
endmodule
module
recF64ToUi32 (
input [(`floatControlWidth - 1):0] control,
input [64:0] in,
input [2:0] roundingMode,
output [31:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(11, 53, 32)
recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);
endmodule
module
recF64ToUi64 (
input [(`floatControlWidth - 1):0] control,
input [64:0] in,
input [2:0] roundingMode,
output [63:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(11, 53, 64)
recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);
endmodule
module
recF64ToI32 (
input [(`floatControlWidth - 1):0] control,
input [64:0] in,
input [2:0] roundingMode,
output [31:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(11, 53, 32)
recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);
endmodule
module
recF64ToI64 (
input [(`floatControlWidth - 1):0] control,
input [64:0] in,
input [2:0] roundingMode,
output [63:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(11, 53, 64)
recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);
endmodule
module
recF128ToUi32 (
input [(`floatControlWidth - 1):0] control,
input [128:0] in,
input [2:0] roundingMode,
output [31:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(15, 113, 32)
recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);
endmodule
module
recF128ToUi64 (
input [(`floatControlWidth - 1):0] control,
input [128:0] in,
input [2:0] roundingMode,
output [63:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(15, 113, 64)
recFNToIN(control, in, roundingMode, 0, out, exceptionFlags);
endmodule
module
recF128ToI32 (
input [(`floatControlWidth - 1):0] control,
input [128:0] in,
input [2:0] roundingMode,
output [31:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(15, 113, 32)
recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);
endmodule
module
recF128ToI64 (
input [(`floatControlWidth - 1):0] control,
input [128:0] in,
input [2:0] roundingMode,
output [63:0] out,
output [2:0] exceptionFlags
);
recFNToIN#(15, 113, 64)
recFNToIN(control, in, roundingMode, 1, out, exceptionFlags);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double esp = 1e-8; const int msz = 100000; const int mod = 2015; struct Child { int v, d; long long p; }; Child c[4444]; bool vis[4444]; queue<int> q; int n; void cut(int id) { long long v = c[id].v + 1; long long d = 0; for (int i = id + 1; i <= n; ++i) { if (vis[i]) continue; if (v > 0) v--; c[i].p -= (d + v); if (c[i].p < 0) { vis[i] = 1; d += c[i].d; } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d %d %lld , &c[i].v, &c[i].d, &c[i].p); } memset(vis, 0, sizeof(vis)); for (int i = 1; i <= n; ++i) { if (vis[i]) continue; cut(i); q.push(i); } int sz = q.size(); printf( %d n , sz); while (sz--) { printf( %d , q.front()); q.pop(); if (sz) putchar( ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline bool read(T &x) { int c = getchar(); int sgn = 1; while (~c && c< 0 | c> 9 ) { if (c == - ) sgn = -1; c = getchar(); } for (x = 0; ~c && 0 <= c && c <= 9 ; c = getchar()) x = x * 10 + c - 0 ; x *= sgn; return ~c; } const long long N = 200005; const long long MOD = 1e9 + 7; long long cnt[N]; long long ara[N]; int main() { long long n = ({ long long a; read(a); a; }); long long mx = 0; long long val; for (int i = 1; i <= n; i++) { ara[i] = ({ long long a; read(a); a; }); ++cnt[ara[i]]; if (cnt[ara[i]] > mx) { mx = cnt[ara[i]]; val = ara[i]; } } if (mx == n) puts( 0 ); else { cout << n - mx << endl; for (int i = 1; i <= n; i++) { if (ara[i] == val) { for (long long j = i - 1; j >= 1; --j) { if (ara[j] != val) { if (ara[j] > val) { cout << 2 << << j << << j + 1 << endl; } else { cout << 1 << << j << << j + 1 << endl; } ara[j] = val; } else break; } for (long long j = i + 1; j <= n; ++j) { if (ara[j] != val) { if (ara[j] > val) { cout << 2 << << j << << j - 1 << endl; } else { cout << 1 << << j << << j - 1 << endl; } ara[j] = val; } else break; } } } } }
|
// bug981
module a(
parameter AUM=80;
parameter BUM=70;
parameter VUM=1;
parameter V2=2;
input my_data_z;
input my_data_v[VUM];
input my_data_vv[VUM][V2];
input [AUM-1:0] my_data_av[VUM];
input [AUM-1:0][BUM-1:0] my_data_ab;
input [AUM-1:0][BUM-1:0] my_data_abv[VUM];
input [XUM-1:0][YUM-1:0] my_data_xyz[ZUM];
input PARAMS0__t params0 [1:0];
input PARAMS1__t params1 [1:0];
);
endmodule
module top (/*AUTOARG*/
// Inputs
TEST1_params1, TEST1_params0, TEST1_my_data_z, TEST1_my_data_xyz, TEST1_my_data_vv,
TEST1_my_data_v, TEST1_my_data_av, TEST1_my_data_abv, TEST1_my_data_ab, TEST0_params1,
TEST0_params0, TEST0_my_data_z, TEST0_my_data_xyz, TEST0_my_data_vv, TEST0_my_data_v,
TEST0_my_data_av, TEST0_my_data_abv, TEST0_my_data_ab
)
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [TEST0_AUM-1:0] [TEST0_BUM-1:0] TEST0_my_data_ab;// To a_0 of a.v
input [TEST0_AUM-1:0] [TEST0_BUM-1:0] TEST0_my_data_abv [TEST0_VUM];// To a_0 of a.v
input [TEST0_AUM-1:0] TEST0_my_data_av [TEST0_VUM];// To a_0 of a.v
input TEST0_my_data_v [VUM]; // To a_0 of a.v
input TEST0_my_data_vv [VUM][V2];// To a_0 of a.v
input [XUM-1:0] [YUM-1:0] TEST0_my_data_xyz [ZUM];// To a_0 of a.v
input TEST0_my_data_z; // To a_0 of a.v
input PARAMS0__t TEST0_params0 [1:0]; // To a_0 of a.v
input PARAMS1__t TEST0_params1 [1:0]; // To a_0 of a.v
input [TEST1_AUM-1:0] [TEST1_BUM-1:0] TEST1_my_data_ab;// To a_1 of a.v
input [TEST1_AUM-1:0] [TEST1_BUM-1:0] TEST1_my_data_abv [TEST1_VUM];// To a_1 of a.v
input [TEST1_AUM-1:0] TEST1_my_data_av [TEST1_VUM];// To a_1 of a.v
input TEST1_my_data_v [VUM]; // To a_1 of a.v
input TEST1_my_data_vv [VUM][V2];// To a_1 of a.v
input [XUM-1:0] [YUM-1:0] TEST1_my_data_xyz [ZUM];// To a_1 of a.v
input TEST1_my_data_z; // To a_1 of a.v
input PARAMS0__t TEST1_params0 [1:0]; // To a_1 of a.v
input PARAMS1__t TEST1_params1 [1:0]; // To a_1 of a.v
// End of automatics
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/*
a AUTO_TEMPLATE
(
.\(.*\) (TEST@_\1[][]),
);
*/
a #(/*AUTOINSTPARAM*/
// Parameters
.AUM (TEST0_AUM), // Templated
.BUM (TEST0_BUM), // Templated
.VUM (TEST0_VUM), // Templated
.V2 (TEST0_V2)) // Templated
a_0 (/*AUTOINST*/
// Inputs
.my_data_z (TEST0_my_data_z), // Templated
.my_data_v (TEST0_my_data_v/*.[VUM]*/), // Templated
.my_data_vv (TEST0_my_data_vv/*.[VUM][V2]*/), // Templated
.my_data_av (TEST0_my_data_av/*[TEST0_AUM-1:0].[TEST0_VUM]*/), // Templated
.my_data_ab (TEST0_my_data_ab/*[TEST0_AUM-1:0][TEST0_BUM-1:0]*/), // Templated
.my_data_abv (TEST0_my_data_abv/*[TEST0_AUM-1:0][TEST0_BUM-1:0].[TEST0_VUM]*/), // Templated
.my_data_xyz (TEST0_my_data_xyz/*[XUM-1:0][YUM-1:0].[ZUM]*/), // Templated
.params0 (TEST0_params0/*.[1:0]*/), // Templated
.params1 (TEST0_params1/*.[1:0]*/)); // Templated
a #(/*AUTOINSTPARAM*/
// Parameters
.AUM (TEST1_AUM), // Templated
.BUM (TEST1_BUM), // Templated
.VUM (TEST1_VUM), // Templated
.V2 (TEST1_V2)) // Templated
a_1 (/*AUTOINST*/
// Inputs
.my_data_z (TEST1_my_data_z), // Templated
.my_data_v (TEST1_my_data_v/*.[VUM]*/), // Templated
.my_data_vv (TEST1_my_data_vv/*.[VUM][V2]*/), // Templated
.my_data_av (TEST1_my_data_av/*[TEST1_AUM-1:0].[TEST1_VUM]*/), // Templated
.my_data_ab (TEST1_my_data_ab/*[TEST1_AUM-1:0][TEST1_BUM-1:0]*/), // Templated
.my_data_abv (TEST1_my_data_abv/*[TEST1_AUM-1:0][TEST1_BUM-1:0].[TEST1_VUM]*/), // Templated
.my_data_xyz (TEST1_my_data_xyz/*[XUM-1:0][YUM-1:0].[ZUM]*/), // Templated
.params0 (TEST1_params0/*.[1:0]*/), // Templated
.params1 (TEST1_params1/*.[1:0]*/)); // Templated
endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// verilog-typedef-regexp: "_t$"
// End:
|
// Issue-Execute Pipeline Register
module ex_pipe_reg
(
input wire clk,
input wire reset,
input wire clr,
input wire valid_ex_pipe_reg_i,
input wire[5:0] op_ex_pipe_reg_i,
input wire jump_ex_pipe_reg_i,
input wire branch_ex_pipe_reg_i,
input wire reg_wr_ex_pipe_reg_i,
input wire mem_to_reg_ex_pipe_reg_i,
input wire mem_wr_ex_pipe_reg_i,
input wire[5:0] alu_op_ex_pipe_reg_i,
input wire[2:0] alu_src_ex_pipe_reg_i,
input wire reg_dst_ex_pipe_reg_i,
input wire[4:0] rt_ex_pipe_reg_i,
input wire[4:0] rs_ex_pipe_reg_i,
input wire[4:0] rd_ex_pipe_reg_i,
input wire[31:0] r_data_p1_ex_pipe_reg_i,
input wire[31:0] r_data_p2_ex_pipe_reg_i,
input wire[31:0] brn_eq_pc_ex_pipe_reg_i,
input wire[31:0] sign_imm_ex_pipe_reg_i,
input wire[4:0] shamt_ex_pipe_reg_i,
input wire brn_pred_ex_pipe_reg_i,
input wire[31:0] curr_pc_ex_pipe_reg_i,
input wire[31:0] next_pred_pc_ex_pipe_reg_i,
input wire[31:0] next_seq_pc_ex_pipe_reg_i,
input wire is_lw_ex_pipe_reg_i,
input wire use_link_reg_ex_pipe_reg_i,
output wire valid_ex_pipe_reg_o,
output wire[5:0] op_ex_pipe_reg_o,
output wire jump_ex_pipe_reg_o,
output wire branch_ex_pipe_reg_o,
output wire reg_wr_ex_pipe_reg_o,
output wire mem_to_reg_ex_pipe_reg_o,
output wire mem_wr_ex_pipe_reg_o,
output wire[5:0] alu_op_ex_pipe_reg_o,
output wire[2:0] alu_src_ex_pipe_reg_o,
output wire reg_dst_ex_pipe_reg_o,
output wire[4:0] rt_ex_pipe_reg_o,
output wire[4:0] rs_ex_pipe_reg_o,
output wire[4:0] rd_ex_pipe_reg_o,
output wire[31:0] r_data_p1_ex_pipe_reg_o,
output wire[31:0] r_data_p2_ex_pipe_reg_o,
output wire[31:0] brn_eq_pc_ex_pipe_reg_o,
output wire[31:0] sign_imm_ex_pipe_reg_o,
output wire[4:0] shamt_ex_pipe_reg_o,
output wire brn_pred_ex_pipe_reg_o,
output wire[31:0] curr_pc_ex_pipe_reg_o,
output wire[31:0] next_pred_pc_ex_pipe_reg_o,
output wire[31:0] next_seq_pc_ex_pipe_reg_o,
output wire is_lw_ex_pipe_reg_o,
output wire use_link_reg_ex_pipe_reg_o
);
reg valid_ex_pipe_reg;
reg[5:0] op_ex_pipe_reg;
reg jump_ex_pipe_reg;
reg branch_ex_pipe_reg;
reg reg_wr_ex_pipe_reg;
reg mem_to_reg_ex_pipe_reg;
reg mem_wr_ex_pipe_reg;
reg[5:0] alu_op_ex_pipe_reg;
reg[2:0] alu_src_ex_pipe_reg;
reg reg_dst_ex_pipe_reg;
reg[4:0] rt_ex_pipe_reg;
reg[4:0] rs_ex_pipe_reg;
reg[4:0] rd_ex_pipe_reg;
reg[31:0] r_data_p1_ex_pipe_reg;
reg[31:0] r_data_p2_ex_pipe_reg;
reg[31:0] brn_eq_pc_ex_pipe_reg;
reg[31:0] sign_imm_ex_pipe_reg;
reg[5:0] shamt_ex_pipe_reg;
reg brn_pred_ex_pipe_reg;
reg[31:0] curr_pc_ex_pipe_reg;
reg[31:0] next_pred_pc_ex_pipe_reg;
reg[31:0] next_seq_pc_ex_pipe_reg;
reg is_lw_ex_pipe_reg;
reg use_link_reg_ex_pipe_reg;
assign valid_ex_pipe_reg_o = valid_ex_pipe_reg;
assign op_ex_pipe_reg_o = op_ex_pipe_reg;
assign branch_ex_pipe_reg_o = branch_ex_pipe_reg;
assign jump_ex_pipe_reg_o = jump_ex_pipe_reg;
assign reg_wr_ex_pipe_reg_o = reg_wr_ex_pipe_reg;
assign mem_to_reg_ex_pipe_reg_o = mem_to_reg_ex_pipe_reg;
assign mem_wr_ex_pipe_reg_o = mem_wr_ex_pipe_reg;
assign alu_op_ex_pipe_reg_o = alu_op_ex_pipe_reg;
assign alu_src_ex_pipe_reg_o = alu_src_ex_pipe_reg;
assign reg_dst_ex_pipe_reg_o = reg_dst_ex_pipe_reg;
assign rt_ex_pipe_reg_o = rt_ex_pipe_reg;
assign rs_ex_pipe_reg_o = rs_ex_pipe_reg;
assign rd_ex_pipe_reg_o = rd_ex_pipe_reg;
assign r_data_p1_ex_pipe_reg_o = r_data_p1_ex_pipe_reg;
assign r_data_p2_ex_pipe_reg_o = r_data_p2_ex_pipe_reg;
assign brn_eq_pc_ex_pipe_reg_o = brn_eq_pc_ex_pipe_reg;
assign sign_imm_ex_pipe_reg_o = sign_imm_ex_pipe_reg;
assign shamt_ex_pipe_reg_o = shamt_ex_pipe_reg;
assign brn_pred_ex_pipe_reg_o = brn_pred_ex_pipe_reg;
assign curr_pc_ex_pipe_reg_o = curr_pc_ex_pipe_reg;
assign next_pred_pc_ex_pipe_reg_o = next_pred_pc_ex_pipe_reg;
assign next_seq_pc_ex_pipe_reg_o = next_seq_pc_ex_pipe_reg;
assign is_lw_ex_pipe_reg_o = is_lw_ex_pipe_reg;
assign use_link_reg_ex_pipe_reg_o = use_link_reg_ex_pipe_reg;
always @(posedge clk or posedge reset)
if (reset | clr)
begin
valid_ex_pipe_reg <= 0;
op_ex_pipe_reg <= 0;
branch_ex_pipe_reg <= 0;
jump_ex_pipe_reg <= 0;
reg_wr_ex_pipe_reg <= 0;
mem_to_reg_ex_pipe_reg <= 0;
mem_wr_ex_pipe_reg <= 0;
alu_op_ex_pipe_reg <= 0;
alu_src_ex_pipe_reg <= 0;
reg_dst_ex_pipe_reg <= 0;
rt_ex_pipe_reg <= 0;
rs_ex_pipe_reg <= 0;
rd_ex_pipe_reg <= 0;
r_data_p1_ex_pipe_reg <= 0;
r_data_p2_ex_pipe_reg <= 0;
brn_eq_pc_ex_pipe_reg <= 0;
sign_imm_ex_pipe_reg <= 0;
shamt_ex_pipe_reg <= 0;
brn_pred_ex_pipe_reg <= 0;
curr_pc_ex_pipe_reg <= 0;
next_pred_pc_ex_pipe_reg <= 0;
next_seq_pc_ex_pipe_reg <= 0;
is_lw_ex_pipe_reg <= 0;
use_link_reg_ex_pipe_reg <= 0;
end
else
begin
valid_ex_pipe_reg <= valid_ex_pipe_reg_i;
op_ex_pipe_reg <= op_ex_pipe_reg_i;
branch_ex_pipe_reg <= branch_ex_pipe_reg_i;
jump_ex_pipe_reg <= jump_ex_pipe_reg_i;
reg_wr_ex_pipe_reg <= reg_wr_ex_pipe_reg_i;
mem_to_reg_ex_pipe_reg <= mem_to_reg_ex_pipe_reg_i;
mem_wr_ex_pipe_reg <= mem_wr_ex_pipe_reg_i;
alu_op_ex_pipe_reg <= alu_op_ex_pipe_reg_i;
alu_src_ex_pipe_reg <= alu_src_ex_pipe_reg_i;
reg_dst_ex_pipe_reg <= reg_dst_ex_pipe_reg_i;
rt_ex_pipe_reg <= rt_ex_pipe_reg_i;
rs_ex_pipe_reg <= rs_ex_pipe_reg_i;
rd_ex_pipe_reg <= rd_ex_pipe_reg_i;
r_data_p1_ex_pipe_reg <= r_data_p1_ex_pipe_reg_i;
r_data_p2_ex_pipe_reg <= r_data_p2_ex_pipe_reg_i;
brn_eq_pc_ex_pipe_reg <= brn_eq_pc_ex_pipe_reg_i;
sign_imm_ex_pipe_reg <= sign_imm_ex_pipe_reg_i;
shamt_ex_pipe_reg <= shamt_ex_pipe_reg_i;
brn_pred_ex_pipe_reg <= brn_pred_ex_pipe_reg_i;
curr_pc_ex_pipe_reg <= curr_pc_ex_pipe_reg_i;
next_pred_pc_ex_pipe_reg <= next_pred_pc_ex_pipe_reg_i;
next_seq_pc_ex_pipe_reg <= next_seq_pc_ex_pipe_reg_i;
is_lw_ex_pipe_reg <= is_lw_ex_pipe_reg_i;
use_link_reg_ex_pipe_reg <= use_link_reg_ex_pipe_reg_i;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(chrono::high_resolution_clock::now().time_since_epoch().count()); const long long inf = 1e15 + 7; bool check(long long n) { return __builtin_popcount(n + 1) == 1; } vector<long long> res; bool solve(long long n, long long k, long long par) { if (n == 11 && k == 3) { res[10] = par; res[9] = 10; res[8] = 9; res[7] = 9; return solve(7, 2, 10); } if (k <= 1) { if ((!check(n) && k == 0) || (check(n) && k == 1)) return false; res[0] = par; for (long long i = 1; i < n; i++) res[i] = (i - 1) / 2; return true; } if (k == 2 && check(n - 2)) { res[n - 1] = par; res[n - 2] = n - 1; res[n - 3] = n - 2; res[n - 4] = n - 2; return solve(n - 4, k - 1, n - 1); } res[n - 1] = par; res[n - 2] = n - 1; return solve(n - 2, k - 1, n - 1); } signed main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); long long n, k; cin >> n >> k; if (n == 1 && k == 0) { cout << YES << endl << 0; return 0; } if (n % 2 == 0 || (n - 3) / 2 < k || (k == 0 && !check(n)) || (k == 1 && check(n)) || (k == 2 && n == 9)) { cout << NO ; return 0; } res.resize(n); bool temp = solve(n, k, -1); if (!temp) cout << Bad << endl; cout << YES << endl; for (long long i : res) cout << i + 1 << ; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); int t; cin >> t; for (int tc=1; tc<=t; tc++) { int n, x; cin >> n >> x; vector<int> v(n); for (int i=0; i<n; i++) { cin >> v[i]; } vector<int> ans; int sum = 0; bool ok = true; for (int i=0; i<n; i++) { int val = v[i]; if (sum + val == x) { if (i == n-1) { ok = false; break; } swap(v[i], v[n-1]); val = v[i]; } ans.push_back(val); sum += val; } if (!ok) { cout << NO n ; continue; } cout << YES n ; for (int i=0; i<n; i++) { cout << ans[i] << n [i+1==n]; } } }
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; void solve() { int a, b, k; cin >> a >> b >> k; vector<int> A(k); vector<int> B(k); vector<int> cA(a + 1); vector<int> cB(b + 1); ll ans = 0; for (int i = 0; i < k; i++) { cin >> A[i]; cA[A[i]]++; } for (int i = 0; i < k; i++) { cin >> B[i]; cB[B[i]]++; } for (int i = 0; i < k; i++) { ans += k - cA[A[i]] - cB[B[i]] + 1; } cout << ans / 2 << n ; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; while(t--) solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_PP_SYMBOL_V
`define SKY130_FD_SC_HD__TAPVPWRVGND_PP_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvpwrvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long dp[100000 + 25]; struct node { int iz, der; long long tiempo; node() {} node(long long t, int i, int d) { tiempo = t; iz = i; der = d; } }; struct otro { int proct, pos; long long tiemp; otro() {} otro(int ps, long long time, int timprt) { pos = ps; tiemp = time; proct = timprt; } bool operator<(const otro& algo) const { return algo.tiemp < tiemp; } }; vector<node> v; int n, m, ini, fin; int valoreleg; char eleg; char ch[500000]; map<long long, int> mp; void f() { long long tiemp = 1; int c = 0; int pos = ini; while (true) { if (v[mp[tiemp]].iz <= pos && v[mp[tiemp]].der >= pos) { ch[c++] = X ; tiemp++; continue; } pos += valoreleg; ch[c] = eleg; if (v[mp[tiemp]].iz <= pos && v[mp[tiemp]].der >= pos) { pos -= valoreleg; ch[c] = X ; } c++; tiemp++; if (pos == fin) { for (int a = 0; a < c; a++) cout << ch[a]; cout << endl; return; } } } int main() { cin >> n >> m >> ini >> fin; int li, ri; long long tim; v.push_back(node(0, 0, 0)); for (int a = 0; a < m; a++) { cin >> tim >> li >> ri; mp[tim] = a + 1; v.push_back(node(tim, li, ri)); } if (ini < fin) { valoreleg = 1; eleg = R ; } else { valoreleg = -1; eleg = L ; } f(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S2S_1_V
`define SKY130_FD_SC_HS__DLYMETAL6S2S_1_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog wrapper for dlymetal6s2s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlymetal6s2s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlymetal6s2s_1 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dlymetal6s2s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlymetal6s2s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlymetal6s2s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S2S_1_V
|
#include <bits/stdc++.h> using namespace std; bitset<20> a; vector<int> w; int sol = 0; void verific(int &l, int &r, int &x) { int sum = 0, i, minim = INT_MAX, maxim = INT_MIN; for (i = 0; i < w.size(); ++i) { if (a[i]) { sum += w[i]; minim = min(minim, w[i]); maxim = max(maxim, w[i]); } } if (sum >= l and sum <= r and maxim - minim >= x) ++sol; } int main() { int n, i, val, l, r, x; cin >> n >> l >> r >> x; for (i = 1; i <= n; ++i) { cin >> val; w.push_back(val); } for (i = 1; i <= 1 << n; ++i) { a = i; if (i & (i - 1) == 0) continue; verific(l, r, x); } cout << sol; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NAND3_FUNCTIONAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int row[] = {0, 1, 0, -1, -1, -1, 1, 1}; int col[] = {1, 0, -1, 0, 1, -1, -1, 1}; const long long N = 2e5 + 10; const long long M = 1e18 + 7; const long long H = 1e9 + 7; const long long base = 131; long long logx(long long a, long long bs) { return log(a) / log(bs); } long long Max(long long a, long long b) { if (a > b) return a; return b; } long long Min(long long a, long long b) { if (a > b) return b; return a; } long long big_mul(long long a, long long b, long long m) { long long x = 0, y = a % m; while (b > 0) { if (b & 1) x = (x + y) % m; y = (2 * y) % m; b >>= 1; } return x % m; } long long big_mod(long long a, long long b, long long m) { long long x = 1, y = a % m; while (b > 0) { if (b & 1) x = (x * y) % m; y = (y * y) % m; b >>= 1; } return x % m; } long long Big_mod(long long a, long long b, long long m) { long long x = 1, y = a % m; while (b > 0) { if (b & 1) x = big_mul(x, y, m); y = big_mul(y, y, m); b >>= 1; } return x % m; } long long mod_inverse(long long a, long long m) { return big_mod(a, m - 2, m); } long long GCD(long long a, long long b) { if (!a) return b; return GCD(b % a, a); } double l, r; vector<double> vec1; vector<double> vec2; double fnct(double total, double value) { return total / value; } bool possible(double x, double m) { double total = m + x; double need = fnct(total, vec1[0]); if (need > x) return false; x -= need; total = m + x; for (int i = 1; i < vec1.size(); i++) { need = fnct(total, vec2[i]); if (need > x) return false; x -= need; total = m + x; need = fnct(total, vec1[i]); if (need > x) return false; x -= need; total = m + x; } need = fnct(total, vec2[0]); if (need > x) return false; return true; } void bs(double m) { l = 0; r = (double)H; int cnt = 0; while (cnt++ <= 100) { double mid = (l + r) / 2.0; if (possible(mid, m) == true) r = mid; else l = mid; } if (l == H || r == H) cout << -1 << endl; else printf( %0.10lf n , l); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int n; cin >> n; double m; cin >> m; for (int i = 0; i < n; i++) { double a; cin >> a; vec1.push_back(a); } for (int i = 0; i < n; i++) { double a; cin >> a; vec2.push_back(a); } bs(m); return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 24232 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w1024,
w1023,
w2,
w1021,
w32,
w1055,
w4084,
w3029,
w24232;
assign w1 = i_data0;
assign w1021 = w1023 - w2;
assign w1023 = w1024 - w1;
assign w1024 = w1 << 10;
assign w1055 = w1023 + w32;
assign w2 = w1 << 1;
assign w24232 = w3029 << 3;
assign w3029 = w4084 - w1055;
assign w32 = w1 << 5;
assign w4084 = w1021 << 2;
assign o_data0 = w24232;
//multiplier_block area estimate = 6872.34229935442;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXTP_BEHAVIORAL_V
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module LIST (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [7 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [7 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [7 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [7 : 0] doutb;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("LIST.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(256),
.C_READ_DEPTH_A(256),
.C_ADDRA_WIDTH(8),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(256),
.C_READ_DEPTH_B(256),
.C_ADDRB_WIDTH(8),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("0"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.68455 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(addrb),
.dinb(8'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_bscl2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_dtl_bscl2(scan_mode ,mode_ctl ,out_type ,rst_val_dn ,
bscan_oe ,sel_data_n ,q25_dn_mux_l ,down_25 ,rst_io_l ,ps_select ,
q_dn_mux_l ,up_open ,bscan_d ,hiz_l ,q_up_mux ,ps_data ,rst_val_up
);
output sel_data_n ;
output q25_dn_mux_l ;
output q_dn_mux_l ;
output q_up_mux ;
input scan_mode ;
input mode_ctl ;
input out_type ;
input rst_val_dn ;
input bscan_oe ;
input down_25 ;
input rst_io_l ;
input ps_select ;
input up_open ;
input bscan_d ;
input hiz_l ;
input ps_data ;
input rst_val_up ;
supply1 vdd ;
wire net186 ;
wire net106 ;
wire net188 ;
wire q_up_log2 ;
wire uo_n ;
wire net191 ;
wire net194 ;
wire net197 ;
wire net118 ;
wire n1 ;
wire n2 ;
wire bsoe ;
wire rmd ;
wire q_dn_log2 ;
wire bsoe_n ;
wire rmd25 ;
wire net136 ;
wire q25_dn_log2 ;
wire rmu ;
wire a1b ;
wire bsd_n ;
wire net149 ;
wire rin_n ;
wire net153 ;
wire net157 ;
wire n1b ;
wire net163 ;
wire net166 ;
wire bsd ;
wire hiz ;
wire net178 ;
wire hz_n ;
wire net182 ;
bw_u1_inv_8x I63 (
.z (sel_data_n ),
.a (net118 ) );
bw_u1_inv_1x inv1x_rst (
.z (rin_n ),
.a (rst_io_l ) );
bw_u1_inv_3x I64 (
.z (net118 ),
.a (net163 ) );
bw_u1_nor2_1x I66 (
.z (net194 ),
.a (rin_n ),
.b (mode_ctl ) );
bw_u1_nor2_1x I67 (
.z (net197 ),
.a (ps_select ),
.b (scan_mode ) );
bw_u1_muxi21_1x rst_mux_dn (
.z (net149 ),
.d0 (q_dn_log2 ),
.d1 (rst_val_dn ),
.s (net191 ) );
bw_u1_inv_4x inv2x_bmc (
.z (net188 ),
.a (net136 ) );
bw_u1_inv_2x oe_inv2x (
.z (bsoe_n ),
.a (bscan_oe ) );
bw_u1_inv_2x boe_inv2x (
.z (bsoe ),
.a (bsoe_n ) );
bw_u1_inv_1x hiz_inv1x (
.z (hiz ),
.a (hiz_l ) );
bw_u1_nor2_2x nor2_rst (
.z (net191 ),
.a (mode_ctl ),
.b (rst_io_l ) );
bw_u1_inv_8x inv8x_1 (
.z (q_up_mux ),
.a (net178 ) );
bw_u1_inv_8x inv8x_2 (
.z (q_dn_mux_l ),
.a (net186 ) );
bw_u1_inv_8x inv8x_3 (
.z (q25_dn_mux_l ),
.a (net182 ) );
bw_u1_nand2_1x nand2_bmc (
.z (net163 ),
.a (net194 ),
.b (net197 ) );
bw_u1_muxi21_2x scn_mx_up (
.z (net178 ),
.d0 (rmu ),
.d1 (a1b ),
.s (net188 ) );
bw_u1_muxi21_2x scn_mx_dn25 (
.z (net182 ),
.d0 (rmd25 ),
.d1 (vdd ),
.s (net188 ) );
bw_u1_inv_1x pd_inv1x (
.z (net106 ),
.a (ps_data ) );
bw_u1_inv_1x open_inv1x (
.z (uo_n ),
.a (up_open ) );
bw_u1_inv_3x hiz_inv3x (
.z (hz_n ),
.a (hiz ) );
bw_u1_inv_1x inv1x_1 (
.z (rmu ),
.a (net153 ) );
bw_u1_inv_1x inv1x_2 (
.z (rmd ),
.a (net149 ) );
bw_u1_inv_1x inv1x_3 (
.z (rmd25 ),
.a (net157 ) );
bw_u1_nand2_1x nand2_pd (
.z (n1b ),
.a (out_type ),
.b (net106 ) );
bw_u1_inv_1x bs_inv1x (
.z (bsd ),
.a (bsd_n ) );
bw_u1_muxi21_2x scn_mx_dn (
.z (net186 ),
.d0 (rmd ),
.d1 (n1b ),
.s (net188 ) );
bw_u1_inv_1x qup_inv1x (
.z (a1b ),
.a (net166 ) );
bw_u1_muxi21_1x rst_mux_up (
.z (net153 ),
.d0 (q_up_log2 ),
.d1 (rst_val_up ),
.s (net191 ) );
bw_u1_nand2_2x nand2_1 (
.z (q_up_log2 ),
.a (n1 ),
.b (n2 ) );
bw_u1_nand3_1x nand3_1 (
.z (n1 ),
.a (hz_n ),
.b (bsoe ),
.c (bsd ) );
bw_u1_nand2_1x nand2_4 (
.z (net166 ),
.a (ps_data ),
.b (out_type ) );
bw_u1_nand2_2x nand2_sm (
.z (net136 ),
.a (ps_select ),
.b (scan_mode ) );
bw_u1_nand3_1x nand3_2 (
.z (n2 ),
.a (hz_n ),
.b (bsoe_n ),
.c (uo_n ) );
bw_u1_nand4_2x nand4_1 (
.z (q25_dn_log2 ),
.a (hz_n ),
.b (bsoe ),
.c (bsd_n ),
.d (down_25 ) );
bw_u1_nand3_2x nand3_3 (
.z (q_dn_log2 ),
.a (hz_n ),
.b (bsoe ),
.c (bsd_n ) );
bw_u1_muxi21_1x rst_mux_dn25 (
.z (net157 ),
.d0 (q25_dn_log2 ),
.d1 (rst_val_dn ),
.s (net191 ) );
bw_u1_inv_3x bs_inv3x (
.z (bsd_n ),
.a (bscan_d ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, s = 0, s2 = 0; cin >> n; char a[n]; cin >> a; for (i = 0; i < n; i++) { if (a[i] == 0 ) s++; else s2++; } if (s2 > 0) cout << 1 ; while (s--) cout << 0 ; return 0; }
|
// DESCRIPTION: Verilator: System Verilog test of a complete CPU
//
// This code instantiates and runs a simple CPU written in System Verilog.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// **************************************************************************
// Regs and Wires
// **************************************************************************
reg rst;
integer rst_count;
integer clk_count;
testbench testbench_i (/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// **************************************************************************
// Reset Generation
// **************************************************************************
initial begin
rst = 1'b1;
rst_count = 0;
end
always @( posedge clk ) begin
if (rst_count < 2) begin
rst_count++;
end
else begin
rst = 1'b0;
end
end
// **************************************************************************
// Drive simulation for 500 clock cycles
// **************************************************************************
initial begin
`ifdef TEST_VERBOSE
$display( "[testbench] - Start of simulation ----------------------- " );
`endif
clk_count = 0;
end
always @( posedge clk ) begin
if (90 == clk_count) begin
$finish ();
end
else begin
clk_count++;
end
end
final begin
`ifdef TEST_VERBOSE
$display( "[testbench] - End of simulation ------------------------- " );
`endif
$write("*-* All Finished *-*\n");
end
endmodule
module testbench (/*AUTOARG*/
// Inputs
clk, rst
);
input clk;
input rst;
// **************************************************************************
// Local parameters
// **************************************************************************
localparam
NUMPADS = $size( pinout );
// **************************************************************************
// Regs and Wires
// **************************************************************************
// **** Pinout ****
`ifdef VERILATOR // see t_tri_array
wire [NUMPADS:1] pad; // GPIO Pads (PORT{A,...,R}).
`else
wire pad [1:NUMPADS]; // GPIO Pads (PORT{A,...,R}).
`endif
// **************************************************************************
// Regs and Wires, Automatics
// **************************************************************************
/*AUTOWIRE*/
// **************************************************************************
// Includes (Testbench extensions)
// **************************************************************************
// N/A
// **************************************************************************
// Chip Instance
// **************************************************************************
chip
i_chip
(
/*AUTOINST*/
// Inouts
.pad (pad[NUMPADS:1]),
// Inputs
.clk (clk),
.rst (rst));
endmodule // test
// Local Variables:
// verilog-library-directories:("." "t_sv_cpu_code")
// End:
|
// +----------------------------------------------------------------------------
// GNU General Public License
// -----------------------------------------------------------------------------
// This file is part of uDLX (micro-DeLuX) soft IP-core.
//
// uDLX is free soft IP-core: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// uDLX soft core is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with uDLX. If not, see <http://www.gnu.org/licenses/>.
// +----------------------------------------------------------------------------
// PROJECT: uDLX core Processor
// ------------------------------------------------------------------------------
// FILE NAME : instruction_decode.v
// -----------------------------------------------------------------------------
// KEYWORDS : dlx, decoder, instruction
// -----------------------------------------------------------------------------
// PURPOSE : Top level module of Instruction Decode stage
// -----------------------------------------------------------------------------
module instruction_decode
#(
parameter PC_WIDTH = 20,
parameter DATA_WIDTH = 32,
parameter INSTRUCTION_WIDTH = 32,
parameter REG_ADDR_WIDTH = 5,
parameter OPCODE_WIDTH = 6,
parameter FUNCTION_WIDTH = 6,
parameter IMEDIATE_WIDTH = 16,
parameter PC_OFFSET_WIDTH = 26
)
(
input clk,
input rst_n,
input en,
input [INSTRUCTION_WIDTH-1:0] instruction_in,
// input [PC_WIDTH-1:0] new_pc_in,
input [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_in,
input [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_in,
input [DATA_WIDTH-1:0] reg_a_wr_data_in,
input [DATA_WIDTH-1:0] reg_b_wr_data_in,
input reg_a_wr_en_in,
input reg_b_wr_en_in,
// input wb_write_enable_in,
// input [DATA_WIDTH-1:0] wb_write_data_in,
// input [REG_ADDR_WIDTH-1:0] wb_reg_wr_addr_in,
input select_new_pc_in,
input id_ex_mem_data_rd_en_in,
input [REG_ADDR_WIDTH-1:0] id_ex_reg_wr_addr_in,
// output alu_src_out,
output [REG_ADDR_WIDTH-1:0] reg_rd_addr1_out,
output [REG_ADDR_WIDTH-1:0] reg_rd_addr2_out,
// output [INSTRUCTION_WIDTH-1:0] instruction_out,
output [OPCODE_WIDTH-1:0] opcode_out,
output [FUNCTION_WIDTH-1:0] inst_function_out, //added, will exist when the function is zero
output mem_data_rd_en_out,
output mem_data_wr_en_out,
output write_back_mux_sel_out,
output [REG_ADDR_WIDTH-1:0] reg_a_wr_addr_out,
output [REG_ADDR_WIDTH-1:0] reg_b_wr_addr_out,
output reg_a_wr_en_out,
output reg_b_wr_en_out,
output [DATA_WIDTH-1:0] constant_out,
output imm_inst_out,
output [DATA_WIDTH-1:0] data_alu_a_out,
output [DATA_WIDTH-1:0] data_alu_b_out,
// output [PC_WIDTH-1:0] new_pc_out,
output [PC_OFFSET_WIDTH-1:0] pc_offset_out,
output branch_inst_out,
output branch_use_r_out,
output jump_inst_out,
output jump_use_r_out,
output rd_inst_ena_out,
output stall_out,
output general_flush_out,
output decode_flush_out
);
// -----------------------------------------------------------------------------
// Internal
// -----------------------------------------------------------------------------
// Wires
// wire [DATA_WIDTH-1:0] data_alu_a;
// wire [DATA_WIDTH-1:0] data_alu_b;
// wire [OPCODE_WIDTH-1:0] opcode;
// wire [FUNCTION_WIDTH-1:0] inst_function;
wire [REG_ADDR_WIDTH-1:0] reg_rd_addr1;
wire [REG_ADDR_WIDTH-1:0] reg_rd_addr2;
wire reg_rd_en1;
wire reg_rd_en2;
// wire [REG_ADDR_WIDTH-1:0] reg_wr_addr;
// wire reg_wr_en;
wire [IMEDIATE_WIDTH-1:0] immediate;
// wire imm_inst;
// wire [DATA_WIDTH-1:0] constant;
// wire [PC_OFFSET_WIDTH-1:0] pc_offset;
// wire mem_data_wr_en;
// wire write_back_mux_sel;
// wire branch_inst;
// wire jump_inst;
// wire jump_use_r;
// Ranges dependem das instruções a serem definidas
// -----------------------------------------------------------------------------
// Instruction decoder unit
// -----------------------------------------------------------------------------
instruction_decoder
#(
.INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
.OPCODE_WIDTH(OPCODE_WIDTH),
.FUNCTION_WIDTH(FUNCTION_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.IMEDIATE_WIDTH(IMEDIATE_WIDTH),
.PC_OFFSET_WIDTH(PC_OFFSET_WIDTH)
)
instruction_decoder_u0
(
.instruction_in(instruction_in),
.opcode(opcode_out),
.inst_function(inst_function_out),
.reg_rd_addr1_out(reg_rd_addr1),
.reg_rd_addr2_out(reg_rd_addr2),
.reg_rd_en1_out(reg_rd_en1),
.reg_rd_en2_out(reg_rd_en2),
.reg_a_wr_addr_out(reg_a_wr_addr_out),
.reg_b_wr_addr_out(reg_b_wr_addr_out),
.reg_a_wr_en_out(reg_a_wr_en_out),
.reg_b_wr_en_out(reg_b_wr_en_out),
.immediate_out(immediate),
.imm_inst_out(imm_inst_out),
.pc_offset(pc_offset_out),
.mem_data_wr_en_out(mem_data_wr_en_out),
.mem_data_rd_en_out(mem_data_rd_en_out),
.write_back_mux_sel_out(write_back_mux_sel_out),
.branch_inst_out(branch_inst_out),
.branch_use_r_out(branch_use_r_out),
.jump_inst_out(jump_inst_out),
.jump_use_r_out(jump_use_r_out)
);
assign reg_rd_addr1_out = reg_rd_addr1;
assign reg_rd_addr2_out = reg_rd_addr2;
// -----------------------------------------------------------------------------
// Register File
// -----------------------------------------------------------------------------
register_bank
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDRESS_WIDTH(REG_ADDR_WIDTH)
)
register_bank_u0
(
.clk(clk),
.rst_n(rst_n),
.en(en),
.rd_reg1_addr(reg_rd_addr1),
.rd_reg2_addr(reg_rd_addr2),
// .write_address(wb_reg_wr_addr_in),
// .write_enable(wb_write_enable_in),
// .write_data(wb_write_data_in),
.reg_a_wr_addr(reg_a_wr_addr_in),
.reg_b_wr_addr(reg_b_wr_addr_in),
.reg_a_wr_data(reg_a_wr_data_in),
.reg_b_wr_data(reg_b_wr_data_in),
.reg_a_wr_en(reg_a_wr_en_in),
.reg_b_wr_en(reg_b_wr_en_in),
.rd_reg1_data_out(data_alu_a_out),
.rd_reg2_data_out(data_alu_b_out)
);
// -----------------------------------------------------------------------------
// General core control Signals
// -----------------------------------------------------------------------------
control
#(
.REG_ADDR_WIDTH(REG_ADDR_WIDTH)
)
control_u0
(
.id_ex_mem_data_rd_en(id_ex_mem_data_rd_en_in),
.id_ex_reg_wr_addr(id_ex_reg_wr_addr_in),
.if_id_rd_reg_a_en(reg_rd_en1),
.if_id_rd_reg_b_en(reg_rd_en2),
.if_id_rd_reg_a_addr(reg_rd_addr1),
.if_id_rd_reg_b_addr(reg_rd_addr2),
.select_new_pc(select_new_pc_in),
.inst_rd_en(rd_inst_ena_out),
.stall(stall_out),
.general_flush(general_flush_out),
.decode_flush(decode_flush_out)
);
// -----------------------------------------------------------------------------
// Immediate value signal extend
// -----------------------------------------------------------------------------
signal_extend
#(
.OUT_DATA_WIDTH(32),
.IN_DATA_WIDTH(16)
)
signal_extend_u0
(
.signal_in(immediate),
.signal_out(constant_out)
);
// -----------------------------------------------------------------------------
// Pipeline registers ID/EX
// -----------------------------------------------------------------------------
// inst_decode_pipe
// #(
// .INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
// .PC_WIDTH(PC_WIDTH),
// .DATA_WIDTH(DATA_WIDTH),
// .OPCODE_WIDTH(OPCODE_WIDTH),
// .FUNCTION_WIDTH(FUNCTION_WIDTH),
// .REG_ADDR_WIDTH(REG_ADDR_WIDTH),
// .IMEDIATE_WIDTH(IMEDIATE_WIDTH),
// .PC_OFFSET_WIDTH(PC_OFFSET_WIDTH)
// )
// inst_decode_pipe_u0
// (
// .clk(clk),
// .rst_n(rst_n),
// .flush(decode_flush),
// .data_alu_a_in(data_alu_a),
// .data_alu_b_in(data_alu_b),
// .new_pc_in(new_pc_in),
// .instruction_in(instruction_in),
// .opcode_in(opcode),
// .inst_function_in(inst_function),
// .reg_rd_addr1_in(reg_rd_addr1),
// .reg_rd_addr2_in(reg_rd_addr2),
// .reg_wr_addr_in(reg_wr_addr),
// .reg_wr_en_in(reg_wr_en),
// .constant_in(constant),
// .imm_inst_in(imm_inst),
// .pc_offset_in(pc_offset),
// .mem_data_wr_en_in(mem_data_wr_en),
// .mem_data_rd_en_in(mem_data_rd_en),
// .write_back_mux_sel_in(write_back_mux_sel),
// .branch_inst_in(branch_inst),
// .jump_inst_in(jump_inst),
// .jump_use_r_in(jump_use_r),
// .data_alu_a_out(data_alu_a_out),
// .data_alu_b_out(data_alu_b_out),
// .new_pc_out(new_pc_out),
// .instruction_out(instruction_out),
// .opcode_out(opcode_out),
// .inst_function_out(inst_function_out),
// .reg_rd_addr1_out(reg_rd_addr1_out),
// .reg_rd_addr2_out(reg_rd_addr2_out),
// .reg_wr_addr_out(reg_wr_addr_out),
// .reg_wr_en_out(reg_wr_en_out),
// .constant_out(constant_out),
// .imm_inst_out(imm_inst_out),
// .pc_offset_out(pc_offset_out),
// .mem_data_wr_en_out(mem_data_wr_en_out),
// .mem_data_rd_en_out(mem_data_rd_en_out),
// .write_back_mux_sel_out(write_back_mux_sel_out),
// .branch_inst_out(branch_inst_out),
// .jump_inst_out(jump_inst_out),
// .jump_use_r_out(jump_use_r_out)
// );
endmodule
|
`timescale 1 ns / 1 ps
module sample_generator_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S_AXIS
parameter integer C_S_AXIS_TDATA_WIDTH = 32,
// Parameters of Axi Master Bus Interface M_AXIS
parameter integer C_M_AXIS_TDATA_WIDTH = 32,
parameter integer C_M_AXIS_START_COUNT = 32
)
(
// Users to add ports here
input [7:0] FrameSize,
input En,
input AXI_En,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S_AXIS
input wire s_axis_aclk,
input wire s_axis_aresetn,
output wire s_axis_tready,
input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] s_axis_tdata,
input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] s_axis_tstrb,
input wire s_axis_tlast,
input wire s_axis_tvalid,
// Ports of Axi Master Bus Interface M_AXIS
input wire m_axis_aclk,
input wire m_axis_aresetn,
output wire m_axis_tvalid,
output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] m_axis_tdata,
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] m_axis_tstrb,
output wire m_axis_tlast,
input wire m_axis_tready
);
wire m_axis_tvalidW;
wire [C_M_AXIS_TDATA_WIDTH-1 : 0] m_axis_tdataW;
wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] m_axis_tstrbW;
wire m_axis_tlastW;
// Instantiation of Axi Bus Interface S_AXIS
// sample_generator_v1_0_S_AXIS # (
// .C_S_AXIS_TDATA_WIDTH(C_S_AXIS_TDATA_WIDTH)
// ) sample_generator_v1_0_S_AXIS_inst (
// .En(En),
// .S_AXIS_ACLK(s_axis_aclk),
// .S_AXIS_ARESETN(s_axis_aresetn),
// .S_AXIS_TREADY(s_axis_tready),
// .S_AXIS_TDATA(s_axis_tdata),
// .S_AXIS_TSTRB(s_axis_tstrb),
/// .S_AXIS_TLAST(s_axis_tlast),
// .S_AXIS_TVALID(s_axis_tvalid)
// );
// Instantiation of Axi Bus Interface M_AXIS
sample_generator_v1_0_M_AXIS # (
.C_M_AXIS_TDATA_WIDTH(C_M_AXIS_TDATA_WIDTH),
.C_M_START_COUNT(C_M_AXIS_START_COUNT)
) sample_generator_v1_0_M_AXIS_inst (
.FrameSize(FrameSize),
.En(En),
.M_AXIS_ACLK(m_axis_aclk),
.M_AXIS_ARESETN(m_axis_aresetn),
.M_AXIS_TVALID(m_axis_tvalidW),
.M_AXIS_TDATA(m_axis_tdataW),
.M_AXIS_TSTRB(m_axis_tstrbW),
.M_AXIS_TLAST(m_axis_tlastW),
.M_AXIS_TREADY(m_axis_tready)
);
// Add user logic here
// adding mux
assign m_axis_tdata=(AXI_En) ? s_axis_tdata : m_axis_tdataW;
assign m_axis_tstrb=(AXI_En) ? s_axis_tstrb : m_axis_tstrbW;
assign m_axis_tlast=(AXI_En) ? s_axis_tlast: m_axis_tlastW;
assign m_axis_tvalid=(AXI_En)? s_axis_tvalid: m_axis_tvalidW;
assign s_axis_tready = m_axis_tready;
// User logic ends
endmodule
|
`ifndef _control
`define _control
`define BRANCH_BEQ 0
`define BRANCH_BNE 1
module control(
input wire [5:0] opcode,
output wire regdst, memread, memtoreg,
output wire [1:0] branch,
output wire [1:0] aluop,
output wire memwrite, alusrc, regwrite);
reg oc_lw, oc_addi, oc_beq, oc_sw, oc_bne, oc_add;
always @(*) begin
oc_lw <= 1'b0;
oc_addi <= 1'b0;
oc_beq <= 1'b0;
oc_sw <= 1'b0;
oc_bne <= 1'b0;
oc_add <= 1'b0;
case (opcode)
6'b100011: oc_lw <= 1'b1; /* lw */
6'b001000: oc_addi <= 1'b1; /* addi */
6'b000100: oc_beq <= 1'b1; /* beq */
6'b101011: oc_sw <= 1'b1; /* sw */
6'b000101: oc_bne <= 1'b1; /* bne */
6'b000000: oc_add <= 1'b1; /* add */
endcase
end
assign regdst = ~(oc_lw | oc_addi);
assign branch[`BRANCH_BEQ] = oc_beq;
assign branch[`BRANCH_BNE] = oc_bne;
assign memread = oc_lw;
assign memtoreg = oc_lw;
assign aluop[0] = oc_beq | oc_bne;
assign aluop[1] = ~(oc_lw | oc_addi | oc_beq | oc_sw | oc_bne);
assign memwrite = oc_sw;
assign alusrc = oc_lw | oc_addi | oc_sw;
assign regwrite = ~(oc_beq | oc_sw | oc_bne);
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; vector<vector<int>> segT; vector<int> lazy; long long n, m, l, r; string s; void buildT(int ss, int se, int si) { if (ss == se) { if (s[ss] == 4 ) segT[si][0] = 1; else segT[si][1] = 1; segT[si][2] = 1; segT[si][3] = 1; return; } int mid = (ss + se) / 2; buildT(ss, mid, 2 * si + 1); buildT(mid + 1, se, 2 * si + 2); segT[si][0] = segT[2 * si + 1][0] + segT[2 * si + 2][0]; segT[si][1] = segT[2 * si + 1][1] + segT[2 * si + 2][1]; segT[si][2] = max(segT[2 * si + 1][2] + segT[2 * si + 2][1], segT[2 * si + 1][0] + segT[2 * si + 2][2]); segT[si][3] = max(segT[2 * si + 1][3] + segT[2 * si + 2][0], segT[2 * si + 1][1] + segT[2 * si + 2][3]); } void upd(int ss, int se, int si) { if (lazy[si] == 1) { swap(segT[si][0], segT[si][1]); swap(segT[si][2], segT[si][3]); if (ss != se) { lazy[2 * si + 1] ^= 1; lazy[2 * si + 2] ^= 1; } lazy[si] = 0; } if (r < ss || l > se) return; if (ss >= l && se <= r) { swap(segT[si][0], segT[si][1]); swap(segT[si][2], segT[si][3]); if (ss != se) { lazy[2 * si + 1] ^= 1; lazy[2 * si + 2] ^= 1; } return; } int mid = (ss + se) / 2; upd(ss, mid, 2 * si + 1); upd(mid + 1, se, 2 * si + 2); segT[si][0] = segT[2 * si + 1][0] + segT[2 * si + 2][0]; segT[si][1] = segT[2 * si + 1][1] + segT[2 * si + 2][1]; segT[si][2] = max(segT[2 * si + 1][2] + segT[2 * si + 2][1], segT[2 * si + 1][0] + segT[2 * si + 2][2]); segT[si][3] = max(segT[2 * si + 1][3] + segT[2 * si + 2][0], segT[2 * si + 1][1] + segT[2 * si + 2][3]); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int i, j; cin >> n >> m; cin >> s; long long lim = 2 * pow(2, ceil(log(n) / log(2.0))) + 2; vector<int> temp(lim, 0); vector<vector<int>> temp2(lim, vector<int>(4, 0)); segT = temp2; lazy = temp; buildT(0, n - 1, 0); string typ; for (i = 0; i < m; i++) { cin >> typ; if (typ.compare( switch ) == 0) { cin >> l >> r; l -= 1; r -= 1; upd(0, n - 1, 0); } else { if (lazy[0] == 1) cout << segT[0][3] << endl; else cout << segT[0][2] << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const int V = 100100; int l[V], r[V], a[V], ret, n; int main() { while (~scanf( %d , &n)) { ret = 0; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) l[i] = r[i] = i; for (int i = 1; i <= n; i++) { while (l[i] != 1 && a[l[i] - 1] < a[i]) l[i] = l[l[i] - 1]; if (l[i] != 1) ret = max(ret, a[i] ^ a[l[i] - 1]); } for (int i = n; i >= 1; i--) { while (r[i] != n && a[r[i] + 1] < a[i]) r[i] = r[r[i] + 1]; if (r[i] != n) ret = max(ret, a[i] ^ a[r[i] + 1]); } printf( %d n , ret); } }
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Basic Function Block for BfbSetterResetter
//defines for state names used internally
`define STATE_s_init 0
`define STATE_s_reset 1
`define STATE_s_set 2
module FB_BfbSetterResetter
(
input wire clk,
//input events
input wire test_eI,
input wire set_eI,
input wire unsafe_eI,
//output events
output wire b_change_eO,
//output variables
output reg b_O ,
input reset
);
////BEGIN internal copies of I/O
//input events
wire test;
assign test = test_eI;
wire set;
assign set = set_eI;
wire unsafe;
assign unsafe = unsafe_eI;
//output events
reg b_change;
assign b_change_eO = b_change;
//output variables
reg b ;
////END internal copies of I/O
////BEGIN internal vars
////END internal vars
//BEGIN STATE variables
reg [1:0] state = `STATE_s_init;
reg entered = 1'b0;
//END STATE variables
//BEGIN algorithm triggers
reg s_reset_alg0_alg_en = 1'b0;
reg s_set_alg0_alg_en = 1'b0;
//END algorithm triggers
always@(posedge clk) begin
if(reset) begin
//reset state
state = `STATE_s_init;
//reset I/O registers
b_change = 1'b0;
b = 0;
//reset internal vars
end else begin
//BEGIN clear output events
b_change = 1'b0;
//END clear output events
//BEGIN update internal inputs on relevant events
//END update internal inputs
//BEGIN ecc
entered = 1'b0;
case(state)
default: begin
if(1) begin
state = `STATE_s_reset;
entered = 1'b1;
end
end
`STATE_s_reset: begin
if(set) begin
state = `STATE_s_set;
entered = 1'b1;
end
end
`STATE_s_set: begin
if(test || unsafe) begin
state = `STATE_s_reset;
entered = 1'b1;
end
end
endcase
//END ecc
//BEGIN triggers
s_reset_alg0_alg_en = 1'b0;
s_set_alg0_alg_en = 1'b0;
if(entered) begin
case(state)
default: begin
end
`STATE_s_reset: begin
b_change = 1'b1;
s_reset_alg0_alg_en = 1'b1;
end
`STATE_s_set: begin
b_change = 1'b1;
s_set_alg0_alg_en = 1'b1;
end
endcase
end
//END triggers
//BEGIN algorithms
if(s_reset_alg0_alg_en) begin
b = 0;
end
if(s_set_alg0_alg_en) begin
b = 1;
end
//END algorithms
//BEGIN update external output variables on relevant events
if(b_change) begin
b_O = b;
end
//END update external output variables
end
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Rotor_To_Electical_Velocity.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Rotor_To_Electical_Velocity
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Rotor_To_Electical_Velocity
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Rotor_To_Electical_Velocity
(
RV,
EV
);
input signed [31:0] RV; // sfix32_En22
output signed [17:0] EV; // sfix18_En6
wire signed [17:0] Convert_Data_Type_out1; // sfix18_En8
wire signed [35:0] number_of_pole_pairs_out1; // sfix36_En22
wire signed [17:0] Electrical_Velocity_Data_Type_out1; // sfix18_En6
// Rotor To Electrical Velocity
// <S23>/Convert_Data_Type
controllerHdl_Convert_Data_Type_block u_Convert_Data_Type (.In1(RV), // sfix32_En22
.Out1(Convert_Data_Type_out1) // sfix18_En8
);
// <S23>/number_of_pole_pairs
assign number_of_pole_pairs_out1 = {{2{Convert_Data_Type_out1[17]}}, {Convert_Data_Type_out1, 16'b0000000000000000}};
// <S23>/Electrical_Velocity_Data_Type
assign Electrical_Velocity_Data_Type_out1 = number_of_pole_pairs_out1[33:16];
assign EV = Electrical_Velocity_Data_Type_out1;
endmodule // controllerHdl_Rotor_To_Electical_Velocity
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long a, b, c; cin >> a >> b >> c; if (a < c) cout << 1 << ; else cout << -1 << ; if (c < a * b) cout << b << endl; else cout << -1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; string ar; string br; int n = 0, lst = 0, lstmin = 0, lp = 0, lpc = 0; int gzg = 0, rzg = 0, gzy2 = 0, rzy2 = 0; int gzf = 0, gzc = 0, rzf = 0, rzc = 0; int gzcc = 0, rzff = 0; int main() { int f = 0; cin >> n; ar.reserve(n + 1); br.reserve(n + 1); cin >> ar; for (f = 0; f < n; f++) { if (lst == lstmin) lpc++; if (ar[f] == ( ) lst++; else lst--; if (lst < lstmin) { lstmin = lst; lp = f + 1; lpc = 0; } } if (lst != 0) { cout << 0 n1 1 n ; return 0; } rzg = lpc; gzcc = lp; rzff = lp; for (f = lp; f < lp + n * 2 + 2; f++) { if (ar[f % n] == ( ) lst++; else lst--; switch (lst) { case 0: if (gzy2 <= gzg) { gzy2 = gzg; gzc = (gzcc + 1) % n + 1; gzf = f % n + 1; } gzg = 0; gzcc = f % n; break; case 1: gzg++; if (rzy2 <= rzg) { rzy2 = rzg; rzf = rzff % n + 1; rzc = f % n + 1; } rzff = f % n + 1; rzg = lpc; break; case 2: rzg++; break; } } if (rzy2 >= gzy2 && rzy2 > lpc) { cout << rzy2 << n << rzf << << rzc << n ; } else if (gzy2 > rzy2 && gzy2 > lpc) { cout << gzy2 << n << gzf << << gzc << n ; } else { cout << lpc << n1 1 n ; } return 0; }
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/12.1sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 59; const long long mod = 998244353; int add[maxn]; long long w[maxn]; long long dp[52][52][52]; long long val[52][52][52]; bool vis[52][52][52]; long long Pow(long long a, long long b) { long long res = 1; a %= mod; while (b) { if (b & 1) res = res * a % mod; b >>= 1; a = a * a % mod; } return res; } inline long long inv(long long a) { return Pow(a, mod - 2); } int flag; long long dfs(int step, long long p, int i, int j, int k, long long x, long long y, long long z) { if (step == 0) return p * x % mod; if (vis[i][j][k]) { return val[i][j][k] * inv(dp[i][j][k]) % mod * p % mod; } dp[i][j][k] = p; val[i][j][k] += dfs(step - 1, p * x % mod * inv(x + y + z) % mod, i + 1, j, k, max(0ll, x + flag), y, z); val[i][j][k] += dfs(step - 1, p * y % mod * inv(x + y + z) % mod, i, j + 1, k, x, y + 1, z); val[i][j][k] += dfs(step - 1, p * z % mod * inv(x + y + z) % mod, i, j, k + 1, x, y, max(0ll, z - 1)); val[i][j][k] %= mod; vis[i][j][k] = 1; return val[i][j][k]; } int main() { int n, m; scanf( %d%d , &n, &m); long long ori, s0 = 0, s1 = 0; for (int i = 1; i <= n; i++) scanf( %d , add + i); for (int i = 1; i <= n; i++) { scanf( %lld , w + i); if (add[i]) s1 += w[i]; else s0 += w[i]; } ori = s0 + s1; int x, y, z, step; for (int i = 1; i <= n; i++) { memset(dp, 0, sizeof dp); memset(val, 0, sizeof val); memset(vis, 0, sizeof vis); if (add[i]) flag = 1, val[0][0][0] = dfs(m, 1, 0, 0, 0, w[i], s1 - w[i], s0); else flag = -1, val[0][0][0] = dfs(m, 1, 0, 0, 0, w[i], s1, s0 - w[i]); printf( %lld n , val[0][0][0]); } }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_quiescent_state (clock, reset, enable, state_expr, check_value, sample_event, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input sample_event;
input [width-1:0] state_expr, check_value;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_QUIESCENT_STATE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_quiescent_state_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_quiescent_state_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_quiescent_state_psl_logic.v"
`else
`endmodule // ovl_quiescent_state
`endif
|
module test ();
parameter param = 3;
reg [2:0] dummy;
initial dummy = block.f(0);
generate
case (param)
1, 2: if (param==1) begin : block
function [2:0] f;
input i;
begin
$display ("if param==1");
f = param;
end
endfunction
end else begin : block
function [2:0] f;
input i;
begin
$display ("else if param==2");
f = param;
end
endfunction
end
4: begin : block
function [2:0] f;
input i;
begin
$display ("if param==4");
f = param;
end
endfunction // f
end
endcase
endgenerate
endmodule
module top ();
test #(1) a();
test #(2) b();
test #(4) c();
initial begin
#1 if (a.dummy !== 1) begin
$display("FAILED -- a.dummy = %d", a.dummy);
$finish;
end
if (b.dummy !== 2) begin
$display("FAILED -- b.dummy = %d", b.dummy);
$finish;
end
if (c.dummy !== 4) begin
$display("FAILED -- c.dummy = %d", c.dummy);
$finish;
end
$display("PASSED");
end // initial begin
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; template <class t, class u> void chmax(t& first, u second) { if (first < second) first = second; } template <class t, class u> void chmin(t& first, u second) { if (second < first) first = second; } template <class t> using vc = vector<t>; template <class t> using vvc = vc<vc<t>>; using pi = pair<ll, ll>; using vi = vc<ll>; template <class t, class u> ostream& operator<<(ostream& os, const pair<t, u>& p) { return os << { << p.first << , << p.second << } ; } template <class t> ostream& operator<<(ostream& os, const vc<t>& v) { os << { ; for (auto e : v) os << e << , ; return os << } ; } using uint = unsigned; using ull = unsigned long long; template <class t, size_t n> ostream& operator<<(ostream& os, const array<t, n>& first) { return os << vc<t>(first.begin(), first.end()); } template <ll i, class T> void print_tuple(ostream&, const T&) {} template <ll i, class T, class H, class... Args> void print_tuple(ostream& os, const T& t) { if (i) os << , ; os << get<i>(t); print_tuple<i + 1, T, Args...>(os, t); } template <class... Args> ostream& operator<<(ostream& os, const tuple<Args...>& t) { os << { ; print_tuple<0, tuple<Args...>, Args...>(os, t); return os << } ; } template <class t> void print(t x, ll suc = 1) { cout << x; if (suc == 1) cout << n ; if (suc == 2) cout << ; } ll read() { ll i; cin >> i; return i; } vi readvi(ll n, ll off = 0) { vi v(n); for (ll i = ll(0); i < ll(n); i++) v[i] = read() + off; return v; } pi readpi(ll off = 0) { ll first, second; cin >> first >> second; return pi(first + off, second + off); } template <class T> void print(const vector<T>& v, ll suc = 1) { for (ll i = ll(0); i < ll(v.size()); i++) print(v[i], i == ll(v.size()) - 1 ? suc : 2); } string readString() { string s; cin >> s; return s; } template <class T> T sq(const T& t) { return t * t; } void yes(bool ex = true) { cout << Yes << n ; if (ex) exit(0); } void no(bool ex = true) { cout << No << n ; if (ex) exit(0); } void possible(bool ex = true) { cout << Possible << n ; if (ex) exit(0); } void impossible(bool ex = true) { cout << Impossible << n ; if (ex) exit(0); } constexpr ll ten(ll n) { return n == 0 ? 1 : ten(n - 1) * 10; } const ll infLL = LLONG_MAX / 3; const ll inf = infLL; ll topbit(signed t) { return t == 0 ? -1 : 31 - __builtin_clz(t); } ll topbit(ll t) { return t == 0 ? -1 : 63 - __builtin_clzll(t); } ll botbit(signed first) { return first == 0 ? 32 : __builtin_ctz(first); } ll botbit(ll first) { return first == 0 ? 64 : __builtin_ctzll(first); } ll popcount(signed t) { return __builtin_popcount(t); } ll popcount(ll t) { return __builtin_popcountll(t); } bool ispow2(ll i) { return i && (i & -i) == i; } ll mask(ll i) { return (ll(1) << i) - 1; } bool inc(ll first, ll second, ll c) { return first <= second && second <= c; } template <class t> void mkuni(vc<t>& v) { sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); } ll rand_int(ll l, ll r) { static mt19937_64 gen(chrono::steady_clock::now().time_since_epoch().count()); return uniform_int_distribution<ll>(l, r)(gen); } template <class t> void myshuffle(vc<t>& first) { for (ll i = ll(0); i < ll(ll(first.size())); i++) swap(first[i], first[rand_int(0, i)]); } template <class t> ll lwb(const vc<t>& v, const t& first) { return lower_bound(v.begin(), v.end(), first) - v.begin(); } signed main() { cin.tie(0); ios::sync_with_stdio(0); cout << fixed << setprecision(20); ll n; cin >> n; ll k = n / 2; vi x(k), y(n - k); for (ll i = ll(0); i < ll(k); i++) x[i] = i + 1; for (ll i = ll(0); i < ll(n - k); i++) y[i] = k + i + 1; vvc<ll> ans; if (n % 2) { for (ll i = ll(0); i < ll(k); i++) for (ll j = ll(i + 1); j < ll(k); j++) for (ll _ = ll(0); _ < ll(2); _++) { ans.push_back({x[i], x[j], y[i], y[j]}); } for (ll i = ll(0); i < ll(k); i++) for (ll _ = ll(0); _ < ll(2); _++) ans.push_back({x[i], y[k], y[i]}); } else { for (ll i = ll(0); i < ll(k); i++) { for (ll j = ll(i + 2); j < ll(i == 0 ? k - 1 : k); j++) for (ll _ = ll(0); _ < ll(2); _++) { ans.push_back({x[i], x[j], y[i], y[j]}); } if (k >= 3) { if (i + 1 < k) { ll j = i + 1; ans.push_back({x[i], x[j], y[i], y[j]}); } if (i == 0) { ll j = k - 1; ans.push_back({x[i], x[j], y[i], y[j]}); } } { ans.push_back({x[i], x[(i + 1) % k], y[(i + 1) % k]}); ans.push_back({x[(i + 1) % k], y[i], y[(i + 1) % k]}); } } } print(ll(ans.size())); for (auto vs : ans) { print(ll(vs.size()), 2); print(vs); } vvc<ll> cnt(n, vi(n)); for (auto vs : ans) { for (ll i = ll(0); i < ll(ll(vs.size())); i++) { ll p = vs[i] - 1, q = vs[(i + 1) % ll(vs.size())] - 1; cnt[p][q]++; cnt[q][p]++; } } void(0); for (ll i = ll(0); i < ll(n); i++) for (ll j = ll(0); j < ll(n); j++) if (i != j) { assert(cnt[i][j] == 2); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_SYMBOL_V
`define SKY130_FD_SC_HS__A211O_SYMBOL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a211o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int x[55][55], a, b, n, m; int solve() { int res = 1000000000; for (int _n((n - a + 1) - 1), i(0); i <= _n; i++) for (int _n((m - b + 1) - 1), j(0); j <= _n; j++) { int cnt = 0; for (int _n((a)-1), k(0); k <= _n; k++) for (int _n((b)-1), t(0); t <= _n; t++) cnt += x[i + k][j + t]; res = min(res, cnt); } return res; } int main() { scanf( %d%d , &n, &m); for (int _n((n)-1), i(0); i <= _n; i++) for (int _n((m)-1), j(0); j <= _n; j++) scanf( %d , &x[i][j]); scanf( %d%d , &a, &b); int r1 = solve(); swap(a, b); int r2 = solve(); cout << min(r1, r2) << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__TAPVGND_FUNCTIONAL_PP_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.141592653589793238; long long powmod(long long a, long long b) { long long res = 1; a %= 1000000007; for (; b; b >>= 1) { if (b & 1) res = res * a % 1000000007; a = a * a % 1000000007; } return res; } char str[200005]; int lps[200005]; int kmp() { int i = 0, j = 1, m = strlen(str); lps[0] = 0; while (j < m) { while (i && str[i] != str[j]) { i = lps[i - 1]; } if (str[i] == str[j]) ++i; lps[j++] = i; } if (m % (m - i) == 0) return (m - i); return m; } int main() { scanf( %s , str); cout << kmp() << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = (int)(2e6 + 123); const int R = (int)(2e6); const long long inf = (long long)(1e12 + 7); long long pn, p[maxn], lp[maxn], b[maxn]; bool u[maxn]; void resheto(long long n) { for (long long i = 3; i * i <= n; i += 2) if (!u[i]) for (long long j = i * i; j <= n; j += 2 * i) u[j] = 1; p[pn++] = 2; for (long long i = 3; i <= n; i += 2) if (!u[i]) p[pn++] = i; for (long long i = 0; i < pn; ++i) { for (long long j = p[i]; j <= n; j += p[i]) lp[j] = p[i]; } } long long n, val, x, k, t, ans1; long long res(long long x) { long long ans = x; for (long long mask = 1; mask < (1 << n); ++mask) { long long cnt = 0, a = 1; for (long long i = 0; i < n; ++i) { if ((mask >> i) & 1) { cnt++; a *= b[i]; } } if (cnt & 1) ans -= x / a; else ans += x / a; } return ans - ans1; } long long bin(long long l, long long r, long long k) { while (r - l > 1) { long long m = (l + r) / 2; if (res(m) >= k) r = m; else l = m; } if (res(l) == k) return l; return r; } int main() { ios_base ::sync_with_stdio(NULL); resheto(R); cin >> t; for (long long cs = 1; cs <= t; ++cs) { cin >> x >> val >> k; n = ans1 = 0; while (val != 1) { b[n++] = lp[val]; long long y = lp[val]; while (val % y == 0) val /= y; } ans1 = res(x); cout << bin(x + 1, inf, k) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[20002][11] = {0}; int b[20002] = {0}; int c[11] = {0}; int main() { int n, m, k; cin >> n >> m >> k; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) scanf( %d , &a[i][j]); for (int i = 0; i < k; i++) { int x, y; cin >> x >> y; c[y - 1]++; b[x - 1] -= a[x - 1][y - 1]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { b[i] += c[j] * a[i][j]; } cout << b[i] << ; } }
|
#include <bits/stdc++.h> using namespace std; const int inf = 2000000000; int H, T, R, m, hi[205], ti[205], n, hj[205], tj[205], h[205][205], t[3000000][3], w, d[205][205]; void adde(int x, int y, int X, int Y) { t[w][0] = X; t[w][1] = Y; t[w][2] = h[x][y]; h[x][y] = w++; } struct node { int x, y, d; bool operator<(const node &t) const { return d > t.d; } } temp; priority_queue<node> q; bool dij() { for (int i = 0; i <= 200; i++) for (int j = 0; j <= 200; j++) d[i][j] = inf; d[H][T] = 0; temp.x = H; temp.y = T; temp.d = d[H][T]; q.push(temp); while (!q.empty()) { temp = q.top(); q.pop(); int x = temp.x, y = temp.y; if (temp.d == d[x][y]) { for (int i = h[x][y]; i != -1; i = t[i][2]) { int X = t[i][0], Y = t[i][1]; if (d[x][y] + 1 < d[X][Y]) { d[X][Y] = d[x][y] + 1; temp.x = X; temp.y = Y; temp.d = d[X][Y]; q.push(temp); } } } } return d[0][0] != inf; } bool spfa() { int q[21010][2], rq, wq, g[205][205]; bool b[205][205]; for (int i = 0; i <= 200; i++) for (int j = 0; j <= 200; j++) d[i][j] = 0; rq = wq = 0; q[wq][0] = H; q[wq][1] = T; wq++; memset(g, 0, sizeof(g)); g[H][T]++; memset(b, true, sizeof(b)); b[H][T] = false; while (wq--) { int x = q[wq][0], y = q[wq][1]; b[x][y] = true; for (int i = h[x][y]; i != -1; i = t[i][2]) { int X = t[i][0], Y = t[i][1]; if (d[x][y] + 1 > d[X][Y]) { d[X][Y] = d[x][y] + 1; if (b[X][Y]) { g[X][Y]++; if (g[X][Y] > 21000) return true; b[X][Y] = false; q[wq][0] = X; q[wq][1] = Y; wq++; } } } } return false; } int main() { scanf( %d%d%d , &H, &T, &R); scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &hi[i], &ti[i]); hi[i] -= i; } scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &hj[i], &tj[i]); tj[i] -= i; } memset(h, -1, sizeof(h)); w = 0; for (int i = 0; i <= R; i++) { for (int j = 0; i + j <= R; j++) { for (int k = 1; (k <= m) && (k <= i); k++) if (i + hi[k] + j + ti[k] > R) adde(i, j, 200, 200); else adde(i, j, i + hi[k], j + ti[k]); for (int k = 1; (k <= n) && (k <= j); k++) if (i + hj[k] + j + tj[k] > R) adde(i, j, 200, 200); else adde(i, j, i + hj[k], j + tj[k]); } } if (dij()) printf( Ivan n%d n , d[0][0]); else if (spfa()) printf( Draw n ); else printf( Zmey n%d n , d[200][200]); return 0; }
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Dual Port Synchronous RAM 64-Deep by 1-Wide
// /___/ /\ Filename : RAMD64.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 01/18/08 - Add support for negative setup/hold timing check (CR457308).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAM64X1D #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output DPO,
output SPO,
input A0,
input A1,
input A2,
input A3,
input A4,
input A5,
input D,
input DPRA0,
input DPRA1,
input DPRA2,
input DPRA3,
input DPRA4,
input DPRA5,
input WCLK,
input WE
);
reg [63:0] mem;
wire [5:0] A_dly, A_in;
wire WCLK_dly, WE_dly, D_dly;
wire WCLK_in, WE_in, D_in;
reg notifier;
assign SPO = mem[A_in];
assign DPO = mem[{DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}];
initial
mem = INIT;
always @(posedge WCLK_in)
if (WE_in == 1'b1)
mem[A_in] <= #100 D_in;
always @(notifier)
mem[A_in] = 1'bx;
`ifndef XIL_TIMING
assign A_dly = {A5, A4, A3, A2, A1, A0};
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = IS_WCLK_INVERTED ^ WCLK_dly;
assign WE_in = WE_dly;
assign D_in = D_dly;
assign A_in = A_dly;
`ifdef XIL_TIMING
specify
(WCLK => DPO) = (0:0:0, 0:0:0);
(WCLK => SPO) = (0:0:0, 0:0:0);
(A0 => SPO) = (0:0:0, 0:0:0);
(A1 => SPO) = (0:0:0, 0:0:0);
(A2 => SPO) = (0:0:0, 0:0:0);
(A3 => SPO) = (0:0:0, 0:0:0);
(A4 => SPO) = (0:0:0, 0:0:0);
(A5 => SPO) = (0:0:0, 0:0:0);
(DPRA0 => DPO) = (0:0:0, 0:0:0);
(DPRA1 => DPO) = (0:0:0, 0:0:0);
(DPRA2 => DPO) = (0:0:0, 0:0:0);
(DPRA3 => DPO) = (0:0:0, 0:0:0);
(DPRA4 => DPO) = (0:0:0, 0:0:0);
(DPRA5 => DPO) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> const long long mod = 1e9 + 7; using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long n, m; vector<long long> a, b, v, pat; long long cal() { v.clear(); for (long long i = 1; i < m; i++) v.push_back(a[i]); v.push_back(1e18); for (long long j = 1; j < n; j++) v.push_back(b[j]); long long sz = v.size(); long long ans = 0; pat.clear(); pat.resize(sz, 0); for (long long i = 1; i < sz; i++) { long long j = pat[i - 1]; while (j > 0 && v[j] != v[i]) j = pat[j - 1]; if (v[j] == v[i]) j++; pat[i] = j; if (j == m - 1) ans++; } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m; long long pre, cur; b.clear(); b.resize(n); for (long long i = 0; i < n; i++) { cin >> b[i]; cur = b[i]; if (i) b[i] -= pre; pre = cur; } a.clear(); a.resize(m); for (long long i = 0; i < m; i++) { cin >> a[i]; cur = a[i]; if (i) a[i] -= pre; pre = cur; } if (m == 1) { cout << n << n ; return 0; } cout << cal() << n ; }
|
#include <bits/stdc++.h> using namespace std; const int mxN = 1e5; int n; string ans; int kmp(string s) { vector<int> pf(s.size()); for (int j = 1; j < s.size(); ++j) { int k = pf[j - 1]; while (s[k] != s[j]) { if (!k) { k = -1; break; } k = pf[k - 1]; } pf[j] = k + 1; } return pf.back(); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; ++i) { if (!i) { cin >> ans; continue; } string s; cin >> s; string t = s; t += # ; int a = min((int)ans.size(), (int)s.size()); t.insert(t.end(), ans.end() - a, ans.end()); int x = kmp(t); while (x--) ans.pop_back(); ans.insert(ans.end(), s.begin(), s.end()); } cout << ans; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_SYMBOL_V
`define SKY130_FD_SC_LS__O32A_SYMBOL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o32a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:01:56 04/23/2017
// Design Name: decrypt
// Module Name: C:/Users/vkoro/Final_Project/project/des/DES/decrypt_tb.v
// Project Name: DES
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: decrypt
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module decrypt_tb;
// Inputs
reg [63:0] message;
reg [63:0] DESkey;
reg clk;
reg reset;
reg enable;
reg ack;
integer clk_cnt;
parameter CLK_PERIOD = 10;
// Outputs
wire [63:0] decrypted;
wire done;
// Instantiate the Unit Under Test (UUT)
decrypt_dumb uut (
.message(message),
.DESkey(DESkey),
.decrypted(decrypted),
.done(done),
.clk(clk),
.reset(reset),
.enable(enable),
.ack(ack)
);
initial
begin : CLK_GENERATOR
clk = 0;
forever
begin
#(CLK_PERIOD/2) clk = ~clk;
end
end
initial
begin : RESET_GENERATOR
reset = 1;
#(10 * CLK_PERIOD) reset = 0;
end
initial
begin : CLK_COUNTER
clk_cnt = 0;
forever
begin
#(CLK_PERIOD) clk_cnt = clk_cnt + 1;
end
end
initial begin
// Initialize Inputs
message = 0;
DESkey = 0;
enable = 0;
ack = 0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
message = 64'b1110000010100110111110111111100010010010011001011010011101100101;
DESkey = 64'h133457799BBCDFF1;
enable = 1;
wait(done);
ack = 1;
# 100;
DESkey = 64'h133457799BBCDFF0;
wait(done);
ack = 1;
# 100;
DESkey = 64'hab01986231bc8d01;
//ack = 1;
# 10;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long int> vec; bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } long long int mark[123]; int main() { std::ios::sync_with_stdio(false); string str; cin >> str; long long int n; cin >> n; if (str.size() < n) { cout << impossible ; return 0; } for (long long int i = 0; i < str.size(); i++) { mark[str[i]]++; } long long int ans = 0; for (long long int i = 0; i < 123; i++) { if (mark[i] > 0) ans++; } if (ans >= n) cout << 0 ; else cout << n - ans; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_bt656cap();
parameter fml_depth = 26;
reg sys_clk;
reg sys_rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
wire irq;
wire [fml_depth-1:0] fml_adr;
wire fml_stb;
reg fml_ack;
wire [63:0] fml_do;
reg vid_clk;
reg [7:0] p;
/* 100MHz system clock */
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
/* ~27MHz video clock */
initial vid_clk = 1'b0;
always #19 vid_clk = ~vid_clk;
reg field;
reg [19:0] inc;
initial field = 1'b0;
initial inc = 20'd0;
always @(posedge vid_clk) begin
inc <= inc + 20'd1;
case(inc[1:0])
2'd0: p <= inc % 720;
2'd1: p <= 8'hfe;
2'd2: p <= inc/720;
2'd3: p <= 8'hfe;
endcase
if(inc == 20'd414720) begin
field <= ~field;
p <= 8'hff;
end
if(inc == 20'd414721) p <= 8'h00;
if(inc == 20'd414722) p <= 8'h00;
if(inc == 20'd414723) begin
p <= {1'b1, field, 6'b00_0000};
inc <= 20'd0;
$display("** end of frame");
end
end
bt656cap #(
.fml_depth(fml_depth)
) dut (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.irq(irq),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_ack(fml_ack),
.fml_do(fml_do),
.vid_clk(vid_clk),
.p(p),
.sda(),
.sdc()
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("CSR write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("CSR read : %x=%x", address, csr_do);
end
endtask
/* Handle FML master for pixel writes */
integer write_burstcount;
integer write_addr;
task handle_write;
integer write_addr2;
integer x;
integer y;
begin
write_addr2 = write_addr[20:0]/2;
x = write_addr2 % 720;
y = write_addr2 / 720;
$display("W: %d %d", x, y);
$image_set(x + 0, y, fml_do[63:48]);
$image_set(x + 1, y, fml_do[47:32]);
$image_set(x + 2, y, fml_do[31:16]);
$image_set(x + 3, y, fml_do[15:0]);
end
endtask
initial write_burstcount = 0;
always @(posedge sys_clk) begin
fml_ack = 1'b0;
if(write_burstcount == 0) begin
if(fml_stb & (($random % 5) == 0)) begin
write_burstcount = 1;
write_addr = fml_adr;
$display("Starting FML burst WRITE at address %x data=%x", write_addr, fml_do);
handle_write;
fml_ack = 1'b1;
end
end else begin
write_addr = write_addr + 8;
write_burstcount = write_burstcount + 1;
$display("Continuing FML burst WRITE at address %x data=%x", write_addr, fml_do);
handle_write;
if(write_burstcount == 4)
write_burstcount = 0;
end
end
always begin
$image_open;
/* Reset / Initialize our logic */
sys_rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
fml_ack = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
/* Setup */
$display("Configuring DUT...");
csrwrite(32'h04, 32'h03);
csrread(32'h04);
@(posedge irq);
csrread(32'h04);
@(posedge irq);
csrread(32'h04);
@(posedge irq);
$image_close;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, x, res = 0, c = 0; cin >> n >> a >> b; for (int i = 0; i < n; i++) { cin >> x; if (x == 1) { if (a > 0) a--; else if (b > 0) { c++; b--; } else if (c > 0) c--; else res++; } else if (x == 2) { if (b > 0) b--; else res += 2; } } cout << res << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A22OI_BEHAVIORAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000000 + 10; long long a[MAXN]; long long b[MAXN]; void add(long long k, long long val, int start, int end) { if (start > end) return; a[start] += k; a[end + 1] -= k; long long bias = val - start * k; b[start] += bias; b[end + 1] -= bias; } int main() { int n, num; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &num); if (num >= i) { add(-1, num - i, 0, num - i); add(1, 1, num - i + 1, n - i); add(-1, num - 1, n - i + 1, n - 1); } else { add(1, i - num, 0, n - i); add(-1, num - 1, n - i + 1, n + num - i); add(1, 1, n + num - i + 1, n - 1); } } int pos = 0; long long val = b[0]; for (int i = 1; i < n; i++) { a[i] += a[i - 1]; b[i] += b[i - 1]; if (a[i] * i + b[i] < val) { val = a[i] * i + b[i]; pos = i; } } cout << val << << pos << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long k, m; string s; vector<int> rooms; cin >> k >> m; cin >> s; for (int i = 0; i < s.length(); i++) { if (s[i] == 0 ) { rooms.push_back(i); } } long select = k; k = 0; while (k + m < rooms.size()) { for (int i = k; i <= k + m; i++) { if (max(rooms[i] - rooms[k], rooms[k + m] - rooms[i]) < select) select = max(rooms[i] - rooms[k], rooms[k + m] - rooms[i]); } k++; } cout << select; }
|
/* Copyright 2015 TREVOR DAVID BLACK
* buffer.v
* buffer is designed to take the nibbles being sent from hf_decompression
* taking these nibbles and valids, it will then construct a buffer
* This buffer will shift out one bit at a time
* The problem with this implementation is that the buffer can fill up
* This is caused by 4 bits entering when 1 bit is shifted out
* The elegant solution to this problem is to also shift out 4 bits at a time
* This elegant solution reduces the buffer to meaninglessness
* So it will be deprecated from the final verilog build
*/
module buffer (
input wire [3:0] buff_in,
input wire buff_in_valid,
output reg buff_out,
output reg buff_out_valid,
output wire buffer_full,
input wire CLK,
input wire Reset
);
reg [31:0] buffer_array; // Effectively a shift register
reg [31:0] sp; // The stack pointer is grey coded for simplicity
assign buffer_full = sp[29]; // 4 bits beyond 29 would be an overflow
always @ (posedge CLK or negedge Reset) begin
if(~Reset) begin
buffer_array <= 32'b0;
end
else begin
if (buff_in_valid) begin
buffer_array <= (sp[28]) ? ({buff_in[3:0], buffer_array[28:1]}) : (
(sp[27]) ? ({01'b0, buff_in[3:0], buffer_array[27:1]}) :
(sp[26]) ? ({02'b0, buff_in[3:0], buffer_array[26:1]}) :
(sp[25]) ? ({03'b0, buff_in[3:0], buffer_array[25:1]}) :
(sp[24]) ? ({04'b0, buff_in[3:0], buffer_array[24:1]}) :
(sp[23]) ? ({05'b0, buff_in[3:0], buffer_array[23:1]}) :
(sp[22]) ? ({06'b0, buff_in[3:0], buffer_array[22:1]}) :
(sp[21]) ? ({07'b0, buff_in[3:0], buffer_array[21:1]}) :
(sp[20]) ? ({08'b0, buff_in[3:0], buffer_array[20:1]}) :
(sp[19]) ? ({09'b0, buff_in[3:0], buffer_array[19:1]}) :
(sp[18]) ? ({10'b0, buff_in[3:0], buffer_array[18:1]}) :
(sp[17]) ? ({11'b0, buff_in[3:0], buffer_array[17:1]}) :
(sp[16]) ? ({12'b0, buff_in[3:0], buffer_array[16:1]}) :
(sp[15]) ? ({13'b0, buff_in[3:0], buffer_array[15:1]}) :
(sp[14]) ? ({14'b0, buff_in[3:0], buffer_array[14:1]}) :
(sp[13]) ? ({15'b0, buff_in[3:0], buffer_array[13:1]}) :
(sp[12]) ? ({16'b0, buff_in[3:0], buffer_array[12:1]}) :
(sp[11]) ? ({17'b0, buff_in[3:0], buffer_array[11:1]}) :
(sp[10]) ? ({18'b0, buff_in[3:0], buffer_array[10:1]}) :
(sp[09]) ? ({19'b0, buff_in[3:0], buffer_array[09:1]}) :
(sp[08]) ? ({20'b0, buff_in[3:0], buffer_array[08:1]}) :
(sp[07]) ? ({21'b0, buff_in[3:0], buffer_array[07:1]}) :
(sp[06]) ? ({22'b0, buff_in[3:0], buffer_array[06:1]}) :
(sp[05]) ? ({23'b0, buff_in[3:0], buffer_array[05:1]}) :
(sp[04]) ? ({24'b0, buff_in[3:0], buffer_array[04:1]}) :
(sp[03]) ? ({25'b0, buff_in[3:0], buffer_array[03:1]}) :
(sp[02]) ? ({26'b0, buff_in[3:0], buffer_array[02:1]}) :
(sp[01]) ? ({27'b0, buff_in[3:0], buffer_array[01:1]}) :
(sp[00]) ? ({28'b0, buff_in[3:0]}) : {29'b0, buff_in[3:1]} );
end
else begin
buffer_array <= {1'b0, buffer_array[31:1]};
end
end
end
always @ (posedge CLK or negedge Reset) begin
if(~Reset) begin
buff_out <= 0;
buff_out_valid <= 0;
end
else begin
if(buff_in_valid) begin
buff_out_valid <= 1'b1;
buff_out <= (sp[0]) ? (buffer_array[0]) : (buff_in);
end else begin
buff_out_valid <= sp[0];
buff_out <= buffer_array[0];
end
end
end
always @ (posedge CLK or negedge Reset) begin
if(~Reset) begin
sp <= 32'b0;
end
else begin
if(buff_in_valid) begin
sp <= {sp[28:0] ,3'b0};
end
else begin
sp <= {1'b0, sp[31:1]};
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A221O_PP_BLACKBOX_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_hvl__udp_dff_p.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_FUNCTIONAL_V
|
`define STATE_INIT 2'b00
`define STATE_W_FETCH 2'b01
`define STATE_END 2'b10
module FETCH(
input clk,
input f_enable,
input write_mode,
input [31:0] addr,
input [31:0] data_i,
input [1:0] thread,
output reg [31:0] data_o,
output reg ack,
input W_CLK,
input W_ACK,
input [31:0] W_DATA_I,
output reg [31:0] W_DATA_O,
output reg [31:0] W_ADDR,
output reg W_WRITE
);
reg read_from_bus;
reg [1:0] state; // 0: 0 -- read input | 1 -- fetch; 1: 00
reg [1:0] w_state;
reg w_buff;
reg w_ack_local;
wire [4:0] reg_select;
reg [31:0] registers[0:32];
assign reg_select = {thread, addr[2:0]};
initial
begin
state <= `STATE_INIT;
w_state <= 2'b00;
data_o <= 0;
ack <= 0;
end
always @(posedge clk)
begin
case (state)
`STATE_INIT:
if (f_enable)
begin
if (addr[31:28] == 4'hF)
begin
if (write_mode)
registers[reg_select] <= data_i;
else
data_o <= registers[reg_select];
ack <= 1;
end
else
begin
read_from_bus <= 1;
state <= `STATE_W_FETCH;
end
end
else
ack <= 0;
`STATE_W_FETCH: // load from WBUS
begin
if (w_ack_local)
begin
data_o <= w_buff;
ack <= 1;
state <= `STATE_INIT;
end
end
endcase
end
always @(posedge W_CLK)
begin
if (read_from_bus)
case (w_state)
2'b00:
begin
W_ADDR <= addr;
w_state <= 2'b01;
W_DATA_O <= data_i;
W_WRITE <= write_mode;
end
2'b01:
if (W_ACK) // wait W_BUS ack
begin
w_buff <= W_DATA_I;
w_ack_local <= 1;
w_state <= 2'b10;
end
2'b10:
begin
w_ack_local <= 0;
w_state <= 2'b00;
W_ADDR <= 32'hz;
end
default:
w_ack_local <= 0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long int n, a, b, i = 0, cnt = 0, y; cin >> n >> a >> b; while (n >= 0) { if (i == 0) { n = n; } else { n = n - a; } if (n % b == 0 && n >= 0) { y = n / b; cnt++; break; } i++; } if (cnt > 0) { cout << YES << endl; cout << i << << y; } else if (cnt == 0) { cout << NO ; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 2000100; const int inf = 1000000007; int dp[N][2], n, m[2], t, tot = 0, g[N][2], path[N], ans[N]; struct nd { int d, id; } a[N][2]; struct element { int d, id[2]; } b[N]; struct point { int x, y; } po[N]; inline int read() { int x = 0; char ch = getchar(); while ((ch < 0 ) || (ch > 9 )) ch = getchar(); while ((ch >= 0 ) && (ch <= 9 )) { x = x * 10 + ch - 0 ; ch = getchar(); } return x; } void calc(int i, int j) { if (dp[i - 1][j] == -1) { g[i][j] = -1; return; } if (!b[i].id[j]) g[i][j] = dp[i - 1][j] + b[i].d - b[i - 1].d; else if (dp[i - 1][j] + b[i].d - b[i - 1].d <= t) g[i][j] = -1; else g[i][j] = dp[i - 1][j] + b[i].d - b[i - 1].d - t; } void upd(int i, int j) { dp[i][j] = g[i][j]; if (!b[i].id[j]) dp[i][j] = max(dp[i][j], min(g[i][j ^ 1], t)); } int main() { int i, j, k, nw, x, len[2], p[2], tmp, st; scanf( %d%d%d%d , &n, &m[0], &m[1], &t); if (m[0] + m[1] == 0) { printf( Yes n0 n n0 n n ); return 0; } for (i = 0; i <= 1; i++) { len[i] = 0; for (j = 1; j <= m[i]; j++) { x = read(); if (a[len[i]][i].d == x) a[len[i]][i].id = 1; else a[++len[i]][i] = (nd){x, 1}; a[++len[i]][i] = (nd){x + 1, 0}; } a[len[i] + 1][i] = (nd){inf, 0}; } tot = 0; memset(b, 0, sizeof(b)); for (p[0] = p[1] = 1; ((p[0] <= len[0]) || (p[1] <= len[1]));) { if (a[p[0]][0].d <= a[p[1]][1].d) nw = 0; else nw = 1; if (b[tot].d != a[p[nw]][nw].d) b[++tot].d = a[p[nw]][nw].d; b[tot].id[nw] = a[p[nw]][nw].id; p[nw]++; } dp[0][0] = dp[0][1] = 0; for (i = 1; i <= tot; i++) { for (j = 0; j <= 1; j++) calc(i, j); for (j = 0; j <= 1; j++) upd(i, j); } if ((dp[tot][0] == -1) && (dp[tot][1] == -1)) printf( No n ); else { printf( Yes n ); if (g[tot][0] != -1) path[tot] = 0; else path[tot] = 1; for (i = tot - 1; i; i--) if ((g[i][path[i + 1]] != -1) && (b[i + 1].d - b[i].d + g[i][path[i + 1]] - b[i + 1].id[path[i + 1]] * t == g[i + 1][path[i + 1]])) path[i] = path[i + 1]; else path[i] = path[i + 1] ^ 1; ans[0] = 0; for (i = 1; i <= tot; i++) if (path[i - 1] ^ path[i]) ans[++ans[0]] = b[i - 1].d; printf( %d n , ans[0]); for (i = 1; i <= ans[0]; i++) printf( %d , ans[i]); printf( n ); ans[0] = 0; for (i = 1; i <= tot; i = j + 1) { j = i; while ((j <= tot) && (path[j + 1] == path[i])) j++; tmp = 0; for (k = i; k <= j; k++) tmp += b[k].id[path[i]]; st = b[i - 1].d + t - dp[i - 1][path[i]]; for (k = 1; k <= tmp; k++, st += t) po[++ans[0]] = (point){st, path[i] + 1}; } printf( %d n , ans[0]); for (i = 1; i <= ans[0]; i++) printf( %d %d n , po[i].x, po[i].y); } return 0; }
|
#include <bits/stdc++.h> using namespace std; class qry { public: int l, r, idx; qry(int l, int r, int idx) : l(l), r(r), idx(idx) {} }; int a[500001], n, m, res[500001]; vector<qry> q; int getans(vector<int> b) { int res = 0; for (int i = 0; i < b.size(); i++) { if ((res ^ b[i]) > res) res ^= b[i]; } return res; } void ins(vector<int>& b, int x) { for (int i = 0; i < b.size(); i++) { if ((b[i] ^ x) < x) x ^= b[i]; } if (!x) return; int t = 31 - __builtin_clz(x); for (int i = 0; i < b.size(); i++) { if (b[i] & (1 << t)) b[i] ^= x; } b.push_back(x); } vector<int> merge(vector<int>& a, vector<int>& b) { vector<int> ret = a; for (int i = 0; i < b.size(); i++) ins(ret, b[i]); return ret; } void solve(vector<qry>& q, int L, int R) { if (q.empty()) return; if (q.size() <= 3 || R - L <= 3) { for (int i = 0; i < q.size(); i++) { int l = q[i].l, r = q[i].r; vector<int> bs; for (int j = l; j <= r; j++) ins(bs, a[j]); res[q[i].idx] = getans(bs); } return; } vector<qry> l, r, my; int mid = (L + R) / 2; for (int i = 0; i < q.size(); i++) { if (q[i].r <= mid) l.push_back(q[i]); else if (q[i].l >= mid + 1) r.push_back(q[i]); else my.push_back(q[i]); } solve(l, L, mid); solve(r, mid + 1, R); sort(my.begin(), my.end(), [](const qry& i, const qry& j) { if (i.l != j.l) return i.l > j.l; else return i.r < j.r; }); vector<int> lb; int cur = 0, pt = mid; vector<vector<int> > rb; vector<int> t; for (int i = mid + 1; i <= R; i++) { ins(t, a[i]); rb.push_back(t); } while (cur < my.size()) { bool found = false; while (my[cur].l <= pt) { found = true; ins(lb, a[pt--]); } res[my[cur].idx] = getans(merge(lb, rb[my[cur].r - mid - 1])); cur++; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); scanf( %d , &m); for (int i = 1; i <= m; i++) { int l, r; scanf( %d %d , &l, &r); q.push_back(qry(l, r, i)); } solve(q, 1, n); for (int i = 1; i <= m; i++) printf( %d n , res[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; constexpr int maxn = 2e5 + 100; int n, val[maxn]; void solve() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , val + i); set<int> s; for (int i = 0; i < n; i++) s.insert((((i + val[i]) % n) + n) % n); puts((s.size() == n) ? YES : NO ); } int main() { int t = 1; scanf( %d , &t); while (t--) solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n, k; cin >> n >> k; set<long long> myset; for (int i = 0; i < n; i++) { int c; cin >> c; myset.insert(c); } auto it = myset.begin(); int ans = 0; do { long long x = (*it) * k; if (x != *it) { if (myset.count(x)) myset.erase(x); } ans++; if (it != myset.end()) it++; } while (it != myset.end()); cout << ans; }
|
#include <bits/stdc++.h> int max(int x, int y) { return (x > y ? x : y); } int geGcd(int a, int b) { if (a == 0 || b == 0) return 0; for (int i = max(a, b); i >= 1; i--) if (a % i == 0 && b % i == 0) return i; } using namespace std; int main() { int a, b, n; cin >> a >> b >> n; int cnt = 0; while (n > 0) { if (geGcd(a, n)) { n -= geGcd(a, n); cnt++; } if (geGcd(b, n)) { n -= geGcd(b, n); cnt++; } } if (cnt % 2 == 0) cout << 1 ; else cout << 0 ; }
|
module demo_sound1(
input clock,
output [7:0]key_code,
input k_tr
);
reg [15:0]tmp;
wire[15:0]tmpa;
reg tr;
reg [15:0]step;
wire[15:0]step_r;
reg [15:0]TT;
reg[5:0]st;
reg go_end;
////////Music-processing////////
always @(negedge k_tr or posedge clock) begin
if (!k_tr) begin
step=0;
st=0;
tr=0;
end
else
if (step<step_r) begin
case (st)
0: st=st+1;
1: begin tr=0; st=st+1;end
2: begin tr=1;st=st+1;end
3: if(go_end) st=st+1;
4: begin st=0;step=step+1;end
endcase
end
end
/////////////// pitch //////////////////
wire [7:0]key_code1=(
(TT[3:0]==1)?8'h2b:(//1
(TT[3:0]==2)?8'h34:(//2
(TT[3:0]==3)?8'h33:(//3
(TT[3:0]==4)?8'h3b:(//4
(TT[3:0]==5)?8'h42:(//5
(TT[3:0]==6)?8'h4b:(//6
(TT[3:0]==7)?8'h4c:(//7
(TT[3:0]==10)?8'h52:(//1
(TT[3:0]==15)?8'hf0:8'hf0
))))))))
);
/////////////// paddle ///////////////////
assign tmpa[15:0]=(
(TT[7:4]==15)?16'h10:(
(TT[7:4]==8)? 16'h20:(
(TT[7:4]==9)? 16'h30:(
(TT[7:4]==1)? 16'h40:(
(TT[7:4]==3)? 16'h60:(
(TT[7:4]==2)? 16'h80:(
(TT[7:4]==4)? 16'h100:0
))))))
);
/////////// note list ///////////
always @(step) begin
case (step)
0:TT=8'hfa;
1:TT=8'h1f;//end
endcase
end
assign step_r=1;///Total note
/////////////KEY release & code-out ////////////////
always @(negedge tr or posedge clock)begin
if(!tr) begin tmp=0;go_end=0 ;end
else if (tmp>tmpa)go_end=1;
else tmp=tmp+1;
end
assign key_code=(tmp<(tmpa-1))?key_code1:8'hf0;
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 25; int main() { int n, m, l, r, t, c; cin >> n >> m; pair<int, int> s[n + 1]; for (int i = (1), _b = (n + 1); i < (_b); ++i) s[i] = make_pair(0, 0); for (int i = (0), _b = (m); i < (_b); ++i) { cin >> l >> r >> t >> c; for (int j = (l), _b = (r + 1); j < (_b); ++j) { if (!s[j].second) s[j] = make_pair(t, c); else { if (t < s[j].first) { s[j] = make_pair(t, c); } } } } int ret = 0; for (int i = (1), _b = (n + 1); i < (_b); ++i) { ret += s[i].second; } cout << ret << endl; return 0; }
|
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/05/Memory.hdl
/**
* The complete address space of the Hack computer's memory,
* including RAM and memory-mapped I/O.
* The chip facilitates read and write operations, as follows:
* Read: out(t) = Memory[address(t)](t)
* Write: if load(t-1) then Memory[address(t-1)](t) = in(t-1)
* In words: the chip always outputs the value stored at the memory
* location specified by address. If load==1, the in value is loaded
* into the memory location specified by address. This value becomes
* available through the out output from the next time step onward.
* Address space rules:
* Only the upper 16K+8K+1 words of the Memory chip are used.
* Access to address>0x6000 is invalid. Access to any address in
* the range 0x4000-0x5FFF results in accessing the screen memory
* map. Access to address 0x6000 results in accessing the keyboard
* memory map. The behavior in these addresses is described in the
* Screen and Keyboard chip specifications given in the book.
*/
CHIP Memory {
IN in[16], load, address[15];
OUT out[16];
PARTS:
Not(in=address[14], out=N14);
And(a=N14, b=load, out=Mload);
And(a=address[14], b=load, out=Sload);
RAM16K(in=in, load=Mload, address=address[0..13], out=outM);
Screen(in=in, load=Sload, address=address[0..12], out=outS);
Keyboard(out=outK);
Mux16(a=outM, b=outSK, sel=address[14], out=out);
Mux16(a=outS, b=outK, sel=address[13], out=outSK);
}
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
// megafunction wizard: %DDR3 SDRAM High Performance Controller v11.0%
//GENERATION: XML
//Generated by DDR3 SDRAM High Performance Controller 11.0
//IPFS_FILES:
//RELATED_FILES:
//<< MEGAWIZARD PARSE FILE DDR311.0
//.
//<< START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top (
// inputs:
clock_source,
global_reset_n,
// outputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
pnf,
pnf_per_byte,
test_complete,
test_status
)
;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 3: 0] mem_dm;
inout [ 31: 0] mem_dq;
inout [ 3: 0] mem_dqs;
inout [ 3: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output pnf;
output [ 15: 0] pnf_per_byte;
output test_complete;
output [ 7: 0] test_status;
input clock_source;
input global_reset_n;
wire [ 0: 0] cs_n;
wire dll_reference_clk_sig;
wire [ 5: 0] dqs_delay_ctrl_export_sig;
wire local_burstbegin_sig;
wire [ 12: 0] mem_addr;
wire mem_aux_full_rate_clk;
wire mem_aux_half_rate_clk;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 3: 0] mem_dm;
wire [ 31: 0] mem_dq;
wire [ 3: 0] mem_dqs;
wire [ 3: 0] mem_dqsn;
wire [ 23: 0] mem_local_addr;
wire [ 15: 0] mem_local_be;
wire [ 9: 0] mem_local_col_addr;
wire mem_local_cs_addr;
wire [127: 0] mem_local_rdata;
wire mem_local_rdata_valid;
wire mem_local_read_req;
wire mem_local_ready;
wire [ 5: 0] mem_local_size;
wire [127: 0] mem_local_wdata;
wire mem_local_write_req;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pnf;
wire [ 15: 0] pnf_per_byte;
wire reset_phy_clk_n;
wire test_complete;
wire [ 7: 0] test_status;
wire tie_high;
wire tie_low;
//
//
assign mem_cs_n = cs_n;
//<< END MEGAWIZARD INSERT MODULE
assign tie_high = 1'b1;
assign tie_low = 1'b0;
//<< START MEGAWIZARD INSERT WRAPPER_NAME
ddr3_int ddr3_int_inst
(
.aux_full_rate_clk (mem_aux_full_rate_clk),
.aux_half_rate_clk (mem_aux_half_rate_clk),
.dll_reference_clk (dll_reference_clk_sig),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export_sig),
.global_reset_n (global_reset_n),
.local_address (mem_local_addr),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_init_done (),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_refresh_ack (),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.mem_addr (mem_addr[12 : 0]),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (cs_n),
.mem_dm (mem_dm[3 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[3 : 0]),
.mem_dqsn (mem_dqsn[3 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.phy_clk (phy_clk),
.pll_ref_clk (clock_source),
.reset_phy_clk_n (reset_phy_clk_n),
.reset_request_n (),
.soft_reset_n (tie_high)
);
//<< END MEGAWIZARD INSERT WRAPPER_NAME
//<< START MEGAWIZARD INSERT CS_ADDR_MAP
//connect up the column address bits, dropping 2 bits from example driver output because of 4:1 data rate
assign mem_local_addr[7 : 0] = mem_local_col_addr[9 : 2];
//<< END MEGAWIZARD INSERT CS_ADDR_MAP
//<< START MEGAWIZARD INSERT EXAMPLE_DRIVER
//Self-test, synthesisable code to exercise the DDR SDRAM Controller
ddr3_int_example_driver driver
(
.clk (phy_clk),
.local_bank_addr (mem_local_addr[23 : 21]),
.local_be (mem_local_be),
.local_burstbegin (local_burstbegin_sig),
.local_col_addr (mem_local_col_addr),
.local_cs_addr (mem_local_cs_addr),
.local_rdata (mem_local_rdata),
.local_rdata_valid (mem_local_rdata_valid),
.local_read_req (mem_local_read_req),
.local_ready (mem_local_ready),
.local_row_addr (mem_local_addr[20 : 8]),
.local_size (mem_local_size),
.local_wdata (mem_local_wdata),
.local_write_req (mem_local_write_req),
.pnf_per_byte (pnf_per_byte[15 : 0]),
.pnf_persist (pnf),
.reset_n (reset_phy_clk_n),
.test_complete (test_complete),
.test_status (test_status)
);
//<< END MEGAWIZARD INSERT EXAMPLE_DRIVER
//<< START MEGAWIZARD INSERT DLL
//<< END MEGAWIZARD INSERT DLL
//<< start europa
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate the ? operator
module main;
reg globvar;
reg [3:0] bvec;
reg [3:0] var1,var2,var3;
reg cond, a,b,out1,out2;
reg error;
initial
begin
error = 0;
bvec = 4'bzx10 ;
for(var1 = 0;var1 <= 4'h3; var1 = var1+1)
begin
for(var2 = 0;var2 <= 4'h3;var2 = var2+1)
begin
for(var3= 0; var3 <= 4'h3;var3 = var3+1)
begin
cond = bvec[var1];
a = bvec[var2];
b = bvec[var3];
out1 = cond ? a: b ;
if(cond)
out2 = a ;
else
out2 = b;
if(out1 != out2)
begin
$display("FAILED - qmark2 - %b %b %b %b %b",
cond,a,b,out1,out2);
error = 1;
end
end
end
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const int NUM = 2e5 + 10; struct node { int index, q; bool operator<(const node &a) const { return index + q < a.index + a.q; } } no[NUM]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d%d , &no[i].index, &no[i].q); sort(no, no + n); int ans = 1, last = 0; for (int i = 1; i < n; i++) { if (no[i].index - no[i].q >= no[last].index + no[last].q) { last = i; ans++; } } printf( %d n , ans); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2014/05/23 15:11:30
// Design Name:
// Module Name: ov7725_capture
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ov7670_capture(
input pclk,
input vsync,
input href,
input[7:0] d,
output[16:0] addr,
output reg[15:0] dout,
output reg we
);
reg [15:0] d_latch;
reg [16:0] address;
reg [16:0] address_next;
reg [1:0] wr_hold;
reg [1:0] cnt;
initial d_latch = 16'b0;
initial address = 19'b0;
initial address_next = 19'b0;
initial wr_hold = 2'b0;
initial cnt = 2'b0;
assign addr = address;
always@(posedge pclk)begin
if( vsync ==1) begin
address <=17'b0;
address_next <= 17'b0;
wr_hold <= 2'b0;
cnt <= 2'b0;
end
else begin
if(address<76800) // Check if at end of frame buffer
address <= address_next;
else
address <= 76800;
// Get 1 byte from camera each cycle. Have to get two bytes to form a pixel.
// wr_hold is used to generate the write enable every other cycle.
// No changes until href = 1 indicating valid data
we <= wr_hold[1]; // Set to 1 one cycle after dout is updated
wr_hold <= {wr_hold[0] , (href &&( ! wr_hold[0])) };
d_latch <= {d_latch[7:0] , d};
if (wr_hold[1] ==1 )begin // increment write address and output new pixel
address_next <=address_next+1;
dout[15:0] <= {d_latch[15:11] , d_latch[10:5] , d_latch[4:0] };
end
end;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double PI = acos(-1.0); const double E = exp(1); const int N = 1e5 + 5; int n; map<long long, long long> m; int main(void) { ios_base::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) { long long a; cin >> a; if (!m.count(a)) m[a] = 0; m[a]++; } long long at = 0; long long s; long long f = 0; for (map<long long, long long>::iterator it = m.begin(); it != m.end(); it++) { s = it->first; long long x = it->second; at += s - f; at = max(0LL, at - x); f = s; } cout << s - at + 1 << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; map<long long int, vector<long long int>> v; map<long long int, long long int> vis; void dfs(long long int n) { long long int i; cout << n << ; vis[n] = 1; for (i = 0; i < v[n].size(); i++) { if (!vis[v[n][i]]) { vis[v[n][i]] = 1; dfs(v[n][i]); } } } int main() { long long int n, i, j, k, p, q, ans = 0; cin >> n; map<long long int, long long int> make_pair; for (i = 1; i <= n; i++) { cin >> p >> q; v[p].push_back(q); v[q].push_back(p); make_pair[p]++; make_pair[q]++; } for (auto it : make_pair) { if (it.second == 1) { ans = it.first; break; } } dfs(ans); }
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/****************************************************************************** Online C++ Compiler. Code, Compile, Run and Debug C++ program online. Write your code in this editor and press Run button to compile and execute it. *******************************************************************************/ #include <bits/stdc++.h> using namespace std; #define ll long long int main() { int t; cin >> t; while (t--){ int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; int check = 1; for (int i = 0; i < n - 1; i++) if (a[i] > a[i + 1]) check = 0; if (check) cout << 0 << endl; else if (a[0] == 1 || a[n - 1] == n) cout << 1 << endl; else if (a[0] == n && a[n - 1] == 1) cout << 3 << endl; else cout << 2 << endl; } return 0; }
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//-----------------------------------------------------------------------------
// The way that we connect things in low-frequency read mode. In this case
// we are generating the unmodulated low frequency carrier.
// The A/D samples at that same rate and the result is serialized.
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module lo_read(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
lo_is_125khz, divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input lo_is_125khz; // redundant signal, no longer used anywhere
input [7:0] divisor;
reg [7:0] to_arm_shiftreg;
reg [7:0] pck_divider;
reg ant_lo;
// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo
// which is high for (divisor+1) pck0 cycles and low for the same duration
// ant_lo is therefore a 50% duty cycle clock signal with a frequency of
// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
ant_lo = !ant_lo;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
// this task also runs at pck0 frequency (24Mhz) and is used to serialize
// the ADC output which is then clocked into the ARM SSP.
// because ant_lo always transitions when pck_divider = 0 we use the
// pck_divider counter to sync our other signals off it
// we read the ADC value when pck_divider=7 and shift it out on counts 8..15
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !ant_lo)
to_arm_shiftreg <= adc_d;
else
begin
to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
// simulation showed a glitch occuring due to the LSB of the shifter
// not being set as we shift bits out
// this ensures the ssp_din remains low after a transfer and suppresses
// the glitch that would occur when the last data shifted out ended in
// a 1 bit and the next data shifted out started with a 0 bit
to_arm_shiftreg[0] <= 1'b0;
end
end
// ADC samples on falling edge of adc_clk, data available on the rising edge
// example of ssp transfer of binary value
// start of transfer is indicated by the rise of the ssp_frame signal
// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
// the ARM by the falling edge of ssp_clk
// _______________________________
// ssp_frame__| |__
// _______ ___ ___
// ssp_din __| |_______| |___| |______
// _ _ _ _ _ _ _ _ _ _
// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
// serialized SSP data is gated by ant_lo to suppress unwanted signal
assign ssp_din = to_arm_shiftreg[7] && !ant_lo;
// SSP clock always runs at 24Mhz
assign ssp_clk = pck0;
// SSP frame is gated by ant_lo and goes high when pck_divider=8..15
assign ssp_frame = (pck_divider[7:3] == 5'd1) && !ant_lo;
// unused signals tied low
assign pwr_hi = 1'b0;
assign pwr_oe1 = 1'b0;
assign pwr_oe2 = 1'b0;
assign pwr_oe3 = 1'b0;
assign pwr_oe4 = 1'b0;
// this is the antenna driver signal
assign pwr_lo = ant_lo;
// ADC clock out of phase with antenna driver
assign adc_clk = ~ant_lo;
// ADC clock also routed to debug pin
assign dbg = adc_clk;
endmodule
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#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > changes; vector<int> norm(vector<int> x) { int i = -1; for (int bit = 30; bit >= 0; bit--) { for (int pos = i + 1; pos < x.size(); pos++) if (x[pos] & (1 << bit)) { if (pos != ++i) { changes.push_back(pair<int, int>(pos, i)); x[pos] ^= x[i]; changes.push_back(pair<int, int>(i, pos)); x[i] ^= x[pos]; } for (int pos = 0; pos < x.size(); pos++) if (pos != i) { if (x[pos] & (1 << bit)) { changes.push_back(pair<int, int>(pos, i)); x[pos] ^= x[i]; } } break; } } return x; } int used[33]; int main() { int n; cin >> n; vector<int> x(n), y(n); for (int i = 0; i < n; i++) scanf( %d , &x[i]); for (int i = 0; i < n; i++) scanf( %d , &y[i]); vector<pair<int, int> > a, b; vector<int> bx = norm(x); a = changes; changes.clear(); vector<int> by = norm(y); b = changes; reverse(b.begin(), b.end()); for (int i = 0; i < n; i++) if (by[i]) used[__builtin_clz(by[i])] = 1; for (int i = 0; i < n; i++) if (bx[i] && used[__builtin_clz(bx[i])]) { for (int j = i - 1; j >= 0; j--) { if (bx[j] && used[__builtin_clz(bx[j])]) break; a.push_back(pair<int, int>(j, j + 1)); bx[j + 1] ^= bx[j]; a.push_back(pair<int, int>(j + 1, j)); bx[j] ^= bx[j + 1]; a.push_back(pair<int, int>(j, j + 1)); bx[j + 1] ^= bx[j]; } } for (int i = 0; i < n; i++) { if (by[i] != bx[i]) { if (!by[i]) { bx[i] = 0; a.push_back(pair<int, int>(i, i)); } else { for (int j = i + 1; j < n; j++) if (bx[j] && (by[i] & (1 << (31 - __builtin_clz(bx[j]))))) { bx[i] ^= bx[j]; a.push_back(pair<int, int>(i, j)); } if (by[i] != bx[i]) { cout << -1 << endl; return 0; } } } } vector<int> aux = x; cout << a.size() + b.size() << endl; for (int i = 0; i < a.size(); i++) { cout << a[i].first + 1 << << a[i].second + 1 << endl; aux[a[i].first] ^= aux[a[i].second]; } for (int i = 0; i < b.size(); i++) { cout << b[i].first + 1 << << b[i].second + 1 << endl; aux[b[i].first] ^= aux[b[i].second]; } return 0; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/27/2016 10:10:41 PM
// Design Name:
// Module Name: KOA
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module KOA_1
#(parameter SW = 24)
// #(parameter SW = 54)
(
input wire [SW-1:0] Data_A_i, //lenght = SW
input wire [SW-1:0] Data_B_i, //lenght = SW
output wire [2*SW-1:0] sgf_result_o //lenght = 2*SW
);
//wire [SW-1:0] result_left_mult;
//wire [2*(SW/2+1)-1:0] result_right_mult;
wire [SW/2+1:0] result_A_adder;
//wire [SW/2+1:0] Q_result_A_adder;
wire [SW/2+1:0] result_B_adder;
//wire [SW/2+1:0] Q_result_B_adder;
//wire [2*(SW/2+2)-1:0] result_middle_mult;
wire [SW-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2-1:0] leftside1;
wire fill;
assign fill = 1'b0;
wire [SW/2:0] rightside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign leftside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
localparam half = SW/2;
localparam full_port = SW - 1;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
// wire [SW-1:0] Q_left;
multiplier_C #(.W(half)/*,.level(level1)*/) left(
.Data_A_i(Data_A_i[full_port:half]), //Port width is SW/2
.Data_B_i(Data_B_i[full_port:half]), //Port width is SW/2
.Data_S_o(Q_left) /*result_left_mult[SW-1:0]*/
);
// wire [2*(SW/2+1)-1:0] Q_right;
multiplier_C #(.W(half)/*,.level(level1)*/) right(
.Data_A_i(Data_A_i[half-1:0]), //Port width is SW/2
.Data_B_i(Data_B_i[half-1:0]), //Port width is SW/2
.Data_S_o(/*result_right_mult[SW-1:0]*/Q_right[SW-1:0]) //Port width is SW
);
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW/2]), //Port width is SW/2
.Data_B_i(Data_A_i[SW/2-1:0]), //Port width is SW/2
.Data_S_o(result_A_adder[SW/2:0]) //Port width is SW
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW/2]), //Port width is SW/2
.Data_B_i(Data_B_i[SW/2-1:0]), //Port width is SW/2
.Data_S_o(result_B_adder[SW/2:0]) //Port width is SW+1
);
// wire [2*(SW/2+2)-1:0] Q_middle;
multiplier_C #(.W(SW/2+1)/*,.level(level1)*/) middle (
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]), //Port width is SW/2+1
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]), //Port width is SW/2+1
.Data_S_o(/*result_middle_mult[SW+1:0]*/Q_middle[SW+1:0]) //Port width is SW+2
);
//Recordar que:
// ///////////////////////////////////////////////////////////
// wire [1:0] zero1;
// wire [3:0] zero2;
// assign zero1 =2'b00;
// assign zero2 =4'b0000;
// ///////////////////////////////////////////////////////////
// wire [SW-1:0] Q_left;
// wire [2*(SW/2+1)-1:0] Q_right;
// wire [2*(SW/2+2)-1:0] Q_middle;
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(Q_middle[SW+1:0]/*P=SW+2*/), //Port width is SW+2 result_middle_mult//*
.Data_B_i({zero1/*P=2*/, Q_left/*P=SW*/}), //Port width is SW+2 result_left_mult
.Data_S_o(S_A[SW+1:0])
);
// wire [2*(SW/2+1)-1:0] Q_right;
// wire [1:0] zero1;
// wire [3:0] zero2;
// assign zero1 =2'b00;
// assign zero2 =4'b0000;
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[SW+1:0]/*P=SW+2*/),
.Data_B_i({zero1/*P=2*/,Q_right[SW-1:0]/*P=SW*/}), //result_right_mult
.Data_S_o(S_B[SW+1:0]/*P=2*/)
);
//
// tambien tomar en cuenta que:
// assign rightside1 = (SW/2) *1'b0;
// assign rightside2 = (SW/2+1)*1'b0;
// assign leftside1 = (SW/2-2) *1'b0;
//Final adder of lenght 2*SW
adder #(.W(2*SW)) Final(
.Data_A_i({Q_left,Q_right[SW-1:0]}/*result_left_mult[SW-1:0],result_right_mult[SW-1:0]*/),
.Data_B_i({leftside1,S_B[SW+1:0],rightside1}),
//Rellenamos con ceros el resto de el bus.
.Data_S_o(Result[2*SW:0]) //Output Port lenght 2*SW+1
);
assign sgf_result_o = Result[(2*SW):0];
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
//Multiplier for left side and right side
multiplier_C #(.W(SW/2)/*,.level(level2)*/) left(
.Data_A_i(Data_A_i[SW-1:SW/2]),
.Data_B_i(Data_B_i[SW-1:SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
multiplier_C #(.W((SW/2)+1)/*,.level(level2)*/) right(
.Data_A_i(Data_A_i[SW/2-1:0]),
.Data_B_i(Data_B_i[SW/2-1:0]),
.Data_S_o(/*result_right_mult*/Q_right)
);
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({fill,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({fill,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW/2-1:0]),
.Data_S_o(result_B_adder)
);
multiplier_C #(.W(SW/2+2)/*,.level(level2)*/) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.Data_S_o(/*result_middle_mult*/Q_middle)
);
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
endcase
endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; map<pair<long long, long long>, long long> ma; void put(long long u, long long v, long long w) { while (v != u) { long long par; if (v > u) { par = v / 2; ma[make_pair(par, v)] += w; ma[make_pair(v, par)] += w; v /= 2; } else { par = u / 2; ma[make_pair(par, u)] += w; ma[make_pair(u, par)] += w; u /= 2; } } } long long solve(long long u, long long v) { long long ans = 0; while (v != u) { long long par; if (v > u) { par = v / 2; ans += ma[make_pair(par, v)]; v /= 2; } else { par = u / 2; ans += ma[make_pair(par, u)]; u /= 2; } } return ans; } int main() { long long u, v, w, ans; int q, ty; cin >> q; while (q--) { cin >> ty; if (ty == 1) { cin >> u >> v >> w; put(u, v, w); } else { cin >> u >> v; cout << solve(u, v) << endl; } } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module hls_gamma_correction_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 6,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
// user signals
output wire [7:0] gamma,
output wire [15:0] height,
output wire [15:0] width
);
//------------------------Address Info-------------------
// 0x00 : reserved
// 0x04 : reserved
// 0x08 : reserved
// 0x0c : reserved
// 0x10 : Data signal of gamma
// bit 7~0 - gamma[7:0] (Read/Write)
// others - reserved
// 0x14 : reserved
// 0x18 : Data signal of height
// bit 15~0 - height[15:0] (Read/Write)
// others - reserved
// 0x1c : reserved
// 0x20 : Data signal of width
// bit 15~0 - width[15:0] (Read/Write)
// others - reserved
// 0x24 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_GAMMA_DATA_0 = 6'h10,
ADDR_GAMMA_CTRL = 6'h14,
ADDR_HEIGHT_DATA_0 = 6'h18,
ADDR_HEIGHT_CTRL = 6'h1c,
ADDR_WIDTH_DATA_0 = 6'h20,
ADDR_WIDTH_CTRL = 6'h24,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 6;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg [7:0] int_gamma = 'b0;
reg [15:0] int_height = 'b0;
reg [15:0] int_width = 'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_GAMMA_DATA_0: begin
rdata <= int_gamma[7:0];
end
ADDR_HEIGHT_DATA_0: begin
rdata <= int_height[15:0];
end
ADDR_WIDTH_DATA_0: begin
rdata <= int_width[15:0];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign gamma = int_gamma;
assign height = int_height;
assign width = int_width;
// int_gamma[7:0]
always @(posedge ACLK) begin
if (ARESET)
int_gamma[7:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GAMMA_DATA_0)
int_gamma[7:0] <= (WDATA[31:0] & wmask) | (int_gamma[7:0] & ~wmask);
end
end
// int_height[15:0]
always @(posedge ACLK) begin
if (ARESET)
int_height[15:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_HEIGHT_DATA_0)
int_height[15:0] <= (WDATA[31:0] & wmask) | (int_height[15:0] & ~wmask);
end
end
// int_width[15:0]
always @(posedge ACLK) begin
if (ARESET)
int_width[15:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_WIDTH_DATA_0)
int_width[15:0] <= (WDATA[31:0] & wmask) | (int_width[15:0] & ~wmask);
end
end
//------------------------Memory logic-------------------
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_BLACKBOX_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlpsleep (
Z ,
A ,
TE_B ,
SLEEP
);
output Z ;
input A ;
input TE_B ;
input SLEEP;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_BLACKBOX_V
|
module rc_pcs_pipe_top (
input wire refclkp,
input wire refclkn,
input wire RESET_n,
input wire ffc_quad_rst,
input wire [1:0] PowerDown,
input wire TxDetectRx_Loopback,
output wire PCLK,
output wire PCLK_by_2,
output reg PhyStatus,
output wire ffs_plol,
input wire hdinp0,
input wire hdinn0,
output wire hdoutp0,
output wire hdoutn0,
input wire [7:0] TxData_0,
input wire [0:0] TxDataK_0,
input wire TxCompliance_0,
input wire TxElecIdle_0,
input wire RxPolarity_0,
input wire scisel_0,
input wire scien_0,
output wire [7:0] RxData_0,
output wire [0:0] RxDataK_0,
output wire RxValid_0,
output wire RxElecIdle_0,
output wire [2:0] RxStatus_0,
output wire ffs_rlol_ch0,
input [7:0] sciwritedata,
input [5:0] sciaddress,
input sciselaux,
input scienaux,
input scird,
input sciwstn,
output[7:0] scireaddata,
input wire phy_l0,
input wire [3:0] phy_cfgln,
input wire ctc_disable,
input wire flip_lanes
)
/*synthesis syn_black_box black_box_pad_pin = "refclkp, refclkn, hdinp0, hdinn0, hdoutp0, hdoutn0" */
/*synthesis black_box black_box_pad = "refclkp, refclkn, hdinp0, hdinn0, hdoutp0, hdoutn0" */
/*synthesis UGROUP="RC_PIPE" PBBOX="20,20" */
;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<int> balance(n, 0); for (int i = 0; i < m; i++) { int a, b, c; cin >> a >> b >> c; balance[a - 1] -= c; balance[b - 1] += c; } int total = 0; for (int i = 0; i < n; i++) { total += balance[i] > 0 ? balance[i] : 0; } cout << total << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
// Date: October 15, 2015
// Summary: The top level module for Phase 1
//////////////////////////////////////////////////////////////////////////////////
module lab4part2phase1(DataIn, Clock, NextAddress, Reset, WriteOrRead, Display, RAMaddress, Transistors, Locked);
input [6:0] DataIn;
input Clock, NextAddress, Reset, WriteOrRead;
output [7:0] Display;
output [5:0] RAMaddress;
output [3:0] Transistors;
output Locked;
wire DebouncedNextAddress;
wire OneshotNextAddress;
wire [6:0] RAMUnitDout;
wire ClockOut;
wire [7:0] segDout;
wire [7:0] segZero;
RAM40x7bits RAMUnit(RAMaddress,DataIn,ClockOut,Reset,WriteOrRead,RAMUnitDout);
HEXto7Segment Bit3_0Unit(RAMUnitDout[3:0],segDout);
Clock70MHz ClockUnit(Clock,ClockOut,Locked);
HEXto7Segment Bit7_4Unit({1'b0,RAMUnitDout[6:4]},segZero);
DebouncerWithoutLatch PrintDebounceUnit(NextAddress,DebouncedNextAddress,Reset,ClockOut);
ClockedOneShot PrintOneShot(DebouncedNextAddress,OneshotNextAddress,Reset,ClockOut);
SevenSegDriver DisplayUnit(8'b11111111,8'b11111111,segZero,segDout,Display,Reset,ClockOut,Transistors);
RAMAddressUpdate UpdateAddress(ClockOut,OneshotNextAddress,Reset,RAMaddress);
endmodule
|
#include <bits/stdc++.h> long long MOD = 1000000007; long long C[2000 + 200][2000 + 200]; int pos = 0; bool notfree[2000 + 200]; int n; void combin() { C[0][0] = 1; for (int i = 1; i <= 2000; i++) { C[0][i] = 1; C[i][i] = 1; for (int j = 1; j < i; j++) C[j][i] = (C[j][i - 1] + C[j - 1][i - 1]) % MOD; } } long long f[2000 + 200]; int cpos = 0; void init() { f[0] = 1; for (int i = 1; i <= 2000; i++) f[i] = (f[i - 1] * i) % MOD; } int a[2000 + 200]; void fix(long long &n) { if (n < 0) n += MOD; } void solve() { for (int i = 1; i <= n; i++) if (a[i] != -1) notfree[a[i]] = true; for (int i = 1; i <= n; i++) if (a[i] == -1) pos++; for (int i = 1; i <= n; i++) if (a[i] == -1 && !notfree[i]) cpos++; init(); long long res = 0; for (int i = 1; i <= cpos; i++) { if (i % 2) res = (res + C[i][cpos] * f[pos - i]) % MOD; else { res = (res - C[i][cpos] * f[pos - i]) % MOD; fix(res); } } res = (f[pos] - res) % MOD; fix(res); printf( %I64d , res); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); combin(); solve(); }
|
//#############################################################################
//# Function: Dual Ported Memory #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_memory_dp
#(parameter DW = 104, // FIFO width
parameter DEPTH = 32, // FIFO depth
parameter REG = 1, // Register fifo output
parameter AW = $clog2(DEPTH),// rd_count width (derived)
parameter TYPE = "soft", // hard (macro) or soft (rtl)
parameter SHAPE = "square" // hard macro shape (square, tall, wide)
)
(// Memory interface (dual port)
input wr_clk, //write clock
input wr_en, //write enable
input [DW-1:0] wr_wem, //per bit write enable
input [AW-1:0] wr_addr,//write address
input [DW-1:0] wr_din, //write data
input rd_clk, //read clock
input rd_en, //read enable
input [AW-1:0] rd_addr,//read address
output [DW-1:0] rd_dout,//read output data
// BIST interface
input bist_en, // bist enable
input bist_we, // write enable global signal
input [DW-1:0] bist_wem, // write enable vector
input [AW-1:0] bist_addr, // address
input [DW-1:0] bist_din, // data input
// Power/repair (hard macro only)
input shutdown, // shutdown signal
input vss, // ground signal
input vdd, // memory array power
input vddio, // periphery/io power
input [7:0] memconfig, // generic memory config
input [7:0] memrepair // repair vector
);
generate
if(TYPE=="soft") begin: soft
oh_memory_soft
//#########################################
// Generic RAM for synthesis
//#########################################
//local variables
reg [DW-1:0] ram [0:DEPTH-1];
wire [DW-1:0] rdata;
integer i;
//write port
always @(posedge wr_clk)
for (i=0;i<DW;i=i+1)
if (wr_en & wr_wem[i])
ram[wr_addr[AW-1:0]][i] <= wr_din[i];
//read port
assign rdata[DW-1:0] = ram[rd_addr[AW-1:0]];
//Configurable output register
reg [DW-1:0] rd_reg;
always @ (posedge rd_clk)
if(rd_en)
rd_reg[DW-1:0] <= rdata[DW-1:0];
//Drive output from register or RAM directly
assign rd_dout[DW-1:0] = (REG==1) ? rd_reg[DW-1:0] :
rdata[DW-1:0];
end // block: soft
else begin: hard
//#########################################
// Hard coded RAM Macros
//#########################################
oh_memory_hard #(.DW(DW),
.DEPTH(DEPTH),
.SHAPE(SHAPE)
.REG(REG))
asic_mem_dp (//read port
.rd_dout (rd_dout[DW-1:0]),
.rd_clk (rd_clk),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]),
//write port
.wr_en (wr_en),
.wr_clk (wr_clk),
.wr_addr (wr_addr[AW-1:0]),
.wr_wem (wr_wem[DW-1:0]),
.wr_din (wr_din[DW-1:0]));
else
begin
endmodule // oh_memory_dp
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 25753 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w16,
w17,
w2176,
w2193,
w1024,
w3217,
w25736,
w25753;
assign w1 = i_data0;
assign w1024 = w1 << 10;
assign w16 = w1 << 4;
assign w17 = w1 + w16;
assign w2176 = w17 << 7;
assign w2193 = w17 + w2176;
assign w25736 = w3217 << 3;
assign w25753 = w17 + w25736;
assign w3217 = w2193 + w1024;
assign o_data0 = w25753;
//multiplier_block area estimate = 5987.52014169412;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; bool is[1000001 + 1]; long long int g1(long long int x, long long int y) { long long int res = 1; x = x; while (y > 0) { if (y & 1) res = (res * x); y = y >> 1; x = (x * x); } return res; } long long int g(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long int GCD(long long int A, long long int B) { if (B == 0) { return A; } else { return GCD(B, A % B); } } long long int isMultipleOf3(long long int n) { long long int odd_count = 0; long long int even_count = 0; if (n < 0) n = -n; if (n == 0) return 1; if (n == 1) return 0; while (n) { if (n & 1) odd_count++; n = n >> 1; if (n & 1) even_count++; n = n >> 1; } return isMultipleOf3(abs(odd_count - even_count)); } int main() { long long int n, x, m = 0, t, a = 0, b = 0, f = 0; string s, str; set<int> v; cin >> s; long long int c = 0; n = s.length(); long long int row = 1; long long int col = 1; for (int i = 0; i < s.length(); i++) { if (s[i] == 1 ) { cout << 3 << << col << n ; col += 2; if (col > 4) col = 1; } else { cout << 1 << << row++ << n ; if (row == 5) row = 1; } } }
|
#include <bits/stdc++.h> struct val { long long x; int y, d; val *p, *l, *r; } g1[100001], g2[100001], *rt1[100001], *rt2[100001], *nil = g1; struct node { long long x; int y; bool operator<(const node &b) const { return x < b.x; } } a[100001]; struct vale { long long x; int y; bool operator<(const vale &b) const { return x > b.x; } } c[100001]; using namespace std; int n, g[100001], h[100001], fa[100001], d[100001], wt, ss[19]; char fl[1 << 23], *A = fl; long long f[100001], e[100001], b[100001]; void read(int &x) { char c; for (x = 0; 0 > (c = *A++) || c > 9 ;) ; while ( 0 <= c && c <= 9 ) x = (x << 3) + (x << 1) + c - 48, (c = *A++); } void read(long long &x) { char c; for (x = 0; 0 > (c = *A++) || c > 9 ;) ; while ( 0 <= c && c <= 9 ) x = (x << 3) + (x << 1) + c - 48, (c = *A++); } void print(long long x) { if (!x) putchar(48); else { for (wt = 0; x; ss[++wt] = x % 10, x /= 10) ; for (; wt; putchar(ss[wt--] + 48)) ; } } val *mg1(val *x, val *y) { return x == nil ? y : (y == nil ? x : (x->x < y->x ? ((x->r = mg1(x->r, y))->p = x, x->l->d < x->r->d ? (swap(x->l, x->r), 0) : 0, x->d = x->l->d + 1, x) : ((y->r = mg1(y->r, x))->p = y, y->l->d < y->r->d ? (swap(y->l, y->r), 0) : 0, y->d = y->l->d + 1, y))); } val *mg2(val *x, val *y) { return x == nil ? y : (y == nil ? x : (x->x > y->x ? ((x->r = mg2(x->r, y))->p = x, x->l->d < x->r->d ? (swap(x->l, x->r), 0) : 0, x->d = x->l->d + 1, x) : ((y->r = mg2(y->r, x))->p = y, y->l->d < y->r->d ? (swap(y->l, y->r), 0) : 0, y->d = y->l->d + 1, y))); } void fix_min(long long t1, int z) { int tmp, x, LIA; if (a[x = g[z]].x != t1) if (a[x].x = t1, x > 1 && a[x] < a[x >> 1]) for (; x > 1 && a[x] < a[x >> 1]; swap(a[x], a[x >> 1]), swap(g[a[x].y], g[a[x >> 1].y]), x >>= 1) ; else for (; (x << 1) <= n;) { if (a[tmp = x << 1] < a[LIA = x]) LIA = tmp; if ((tmp |= 1) <= n && a[tmp] < a[LIA]) LIA = tmp; if (LIA != x) swap(a[LIA], a[x]), swap(g[a[LIA].y], g[a[x].y]), x = LIA; else break; } } void fix_max(long long t1, int z) { int tmp, x, LIA; if (c[x = h[z]].x != t1) if (c[x].x = t1, x > 1 && c[x] < c[x >> 1]) for (; x > 1 && c[x] < c[x >> 1]; swap(c[x], c[x >> 1]), swap(h[c[x].y], h[c[x >> 1].y]), x >>= 1) ; else for (; (x << 1) <= n;) { if (c[tmp = x << 1] < c[LIA = x]) LIA = tmp; if ((tmp |= 1) <= n && c[tmp] < c[LIA]) LIA = tmp; if (LIA != x) swap(c[LIA], c[x]), swap(h[c[LIA].y], h[c[x].y]), x = LIA; else break; } } void fix(int x) { if (g1[x].p == nil) (rt1[fa[x]] = mg1(g1[x].l, g1[x].r))->p = nil; else if (g1[x].p->l == &g1[x]) (g1[x].p->l = mg1(g1[x].l, g1[x].r))->p = g1[x].p; else (g1[x].p->r = mg1(g1[x].l, g1[x].r))->p = g1[x].p; g1[x].x = f[x], g1[x].l = g1[x].r = nil, (rt1[fa[x]] = mg1(rt1[fa[x]], &g1[x]))->p = nil; if (g2[x].p == nil) (rt2[fa[x]] = mg2(g2[x].l, g2[x].r))->p = nil; else if (g2[x].p->l == &g2[x]) (g2[x].p->l = mg2(g2[x].l, g2[x].r))->p = g2[x].p; else (g2[x].p->r = mg2(g2[x].l, g2[x].r))->p = g2[x].p; g2[x].x = f[x], g2[x].l = g2[x].r = nil, (rt2[fa[x]] = mg2(rt2[fa[x]], &g2[x]))->p = nil; } void alter(int z, int x, int y, int LAx, int LAy) { long long t1 = e[x], t3 = e[y]; int t2 = b[x] % d[x], t4 = b[y] % d[y]; f[y] += b[y] % (++d[y]) + e[z] - t4, e[y] = b[y] / d[y], f[LAy] += e[y] - t3, f[y] += e[y] - t3; f[x] += b[x] % (--d[x]) - e[z] - t2, e[x] = b[x] / d[x], f[LAx] += e[x] - t1, f[x] += e[x] - t1; if (LAx == LAy) { if (e[y] + e[x] != t1 + t3) fix(LAx); } else { if (e[y] != t3) fix(LAy); if (e[x] != t1) fix(LAx); } fix(x), fix(y); if (g1[z].p == nil) (rt1[x] = mg1(g1[z].l, g1[z].r))->p = nil; else if (g1[z].p->l == &g1[z]) (g1[z].p->l = mg1(g1[z].l, g1[z].r))->p = g1[z].p; else (g1[z].p->r = mg1(g1[z].l, g1[z].r))->p = g1[z].p; g1[z].x = f[z], g1[z].l = g1[z].r = nil, (rt1[fa[z] = y] = mg1(rt1[y], &g1[z]))->p = nil; if (g2[z].p == nil) (rt2[x] = mg2(g2[z].l, g2[z].r))->p = nil; else if (g2[z].p->l == &g2[z]) (g2[z].p->l = mg2(g2[z].l, g2[z].r))->p = g2[z].p; else (g2[z].p->r = mg2(g2[z].l, g2[z].r))->p = g2[z].p; g2[z].x = f[z], g2[z].l = g2[z].r = nil, (rt2[y] = mg2(rt2[y], &g2[z]))->p = nil; fix_max(e[fa[LAx]] + rt2[fa[LAx]]->x, rt2[fa[LAx]]->y); fix_max(e[fa[LAy]] + rt2[fa[LAy]]->x, rt2[fa[LAy]]->y); fix_max(rt2[LAx]->x + e[LAx], rt2[LAx]->y); fix_max(rt2[LAy]->x + e[LAy], rt2[LAy]->y); if (rt2[x] != nil) fix_max(rt2[x]->x + e[x], rt2[x]->y); fix_max(rt2[y]->x + e[y], rt2[y]->y); fix_min(e[fa[LAx]] + rt1[fa[LAx]]->x, rt1[fa[LAx]]->y); fix_min(e[fa[LAy]] + rt1[fa[LAy]]->x, rt1[fa[LAy]]->y); fix_min(rt1[LAx]->x + e[LAx], rt1[LAx]->y); fix_min(rt1[LAy]->x + e[LAy], rt1[LAy]->y); if (rt1[x] != nil) fix_min(rt1[x]->x + e[x], rt1[x]->y); fix_min(rt1[y]->x + e[y], rt1[y]->y); } void dfs(int x) { long long t1 = e[fa[a[x].y]] + f[a[x].y]; int tmp = a[x].y; if (a[x].x != t1) { if ((x << 1) <= n) dfs(x << 1); if ((x << 1 | 1) <= n) dfs(x << 1 | 1); fix_min(t1, tmp); } } void vfs(int x) { long long t1 = e[fa[c[x].y]] + f[c[x].y]; int tmp = c[x].y; if (c[x].x != t1) { if ((x << 1) <= n) vfs(x << 1); if ((x << 1 | 1) <= n) vfs(x << 1 | 1); fix_max(t1, tmp); } } int main() { int test, i, x, y, tmp, LIA; for (*(fl + fread(fl, 1, 1 << 23, stdin)) = EOF, read(n), read(test), i = 1; i <= n; d[i] = 2, rt1[i] = rt2[i] = nil, read(b[i++])) ; for (i = 1; i <= n; read(fa[i]), d[fa[i]]++, i++) ; for (i = 1; i <= n; f[i] += b[i] % d[i] + (e[i] = b[i] / d[i]), f[fa[i]] += e[i], i++) ; for (i = 1; i <= n; g1[i] = g2[i] = (val){f[i], i, 1, nil, nil, nil}, (rt1[fa[i]] = mg1(rt1[fa[i]], &g1[i]))->p = nil, (rt2[fa[i]] = mg2(rt2[fa[i]], &g2[i]))->p = nil, a[i] = (node){f[i] + e[fa[i]], i}, c[i] = (vale){f[i] + e[fa[i]], i}, i++) ; for (sort(a + 1, a + n + 1), sort(c + 1, c + n + 1), i = 1; i <= n; g[a[i].y] = i, h[c[i].y] = i, i++) ; for (; test--;) switch (read(x), x) { case 1: if (read(x), read(y), fa[x] != y) alter(x, fa[x], y, fa[fa[x]], fa[y]); break; case 2: read(x), print(e[fa[x]] + f[x]), putchar( n ); break; case 3: dfs(1), vfs(1), print(a[1].x), putchar( ), print(c[1].x), putchar( n ); break; } }
|
#include <bits/stdc++.h> using namespace std; int n; long long a[30]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); long long now = a[n - 1]; long long ans = 0; for (int i = n - 1; i >= 0; i--) { now = min(now, a[i]); ans += now; now--; if (now < 0) break; } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_4_V
`define SKY130_FD_SC_HS__EBUFN_4_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__ebufn_4 (
A ,
TE_B,
Z ,
VPWR,
VGND
);
input A ;
input TE_B;
output Z ;
input VPWR;
input VGND;
sky130_fd_sc_hs__ebufn base (
.A(A),
.TE_B(TE_B),
.Z(Z),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__ebufn_4 (
A ,
TE_B,
Z
);
input A ;
input TE_B;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__ebufn base (
.A(A),
.TE_B(TE_B),
.Z(Z)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_4_V
|
#include <bits/stdc++.h> using namespace std; int v[112345]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &v[i]); sort(v, v + n); int res = 1; for (int i = 0; i < n; i++) { if (v[i] >= res) { v[i] = res; res++; } } printf( %d n , res); return 0; }
|
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