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#include <bits/stdc++.h> using namespace std; const long long inf = 1000000000000000000; int c[1001][1001]; int main(void) { int n, m; scanf( %d %d , &n, &m); long long s = 0, sij = 0, si = 0, sj = 0; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { int p = (i - 1) * 4 + 2, q = (j - 1) * 4 + 2; scanf( %d , &c[i][j]); s += c[i][j]; sij += (long long)c[i][j] * (p * p + q * q); si += c[i][j] * p; sj += c[i][j] * q; } } int x, y; long long ans = inf; for (int i = 0; i <= n; ++i) { for (int j = 0; j <= m; ++j) { int p = i * 4, q = j * 4; long long temp = s * (p * p + q * q) - 2 * si * p - 2 * sj * q + sij; if (temp < ans) { ans = temp; x = i; y = j; } } } printf( %I64d n%d %d n , ans, x, y); return 0; }
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#include <bits/stdc++.h> using namespace std; long long n, cr; bool f = 0; pair<long long, long long> a[25], b[25], c[25]; void gen(long long i, long long s1, long long s2) { if (i == n) { if (s1 != s2) cr++; } else { gen(i + 1, s1 + a[i].first, s2 + c[i].first); gen(i + 1, s1, s2); } } int main() { ios::sync_with_stdio(0); cin >> n; for (long long i = 0; i < n; i++) { cin >> a[i].first; a[i].second = i; c[i] = a[i]; } sort(a, a + n); sort(c, c + n); for (long long k = 0; k < n; k++) { for (long long i = 0; i < n; i++) { b[i] = a[i]; } a[0] = b[n - 1]; for (long long i = 1; i < n; i++) { a[i] = b[i - 1]; } cr = 0; gen(0, 0, 0); if (cr == ((1 << n) - 2)) { f = 1; for (long long i = 0; i < n; i++) { c[i].first = c[i].second; c[i].second = a[i].first; } break; } } if (!f) { cout << -1; return 0; } sort(c, c + n); for (long long i = 0; i < n; i++) { cout << c[i].second << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; unsigned long xor128() { static unsigned long x = time(NULL), y = 362436069, z = 521288629, w = 88675123; unsigned long t = (x ^ (x << 11)); x = y; y = z; z = w; return (w = (w ^ (w >> 19)) ^ (t ^ (t >> 8))); } double dot(complex<double> a, complex<double> b) { return a.real() * b.real() + a.imag() * b.imag(); } double gyaku_dot(complex<double> a, complex<double> b) { return a.real() * b.imag() - a.imag() * b.real(); } double leng(complex<double> a) { return sqrt(a.real() * a.real() + a.imag() * a.imag()); } double angles(complex<double> a, complex<double> b) { double cosine = dot(a, b) / (leng(a) * leng(b)); double sine = gyaku_dot(a, b) / (leng(a) * leng(b)); double kaku = acos(min((double)1.0, max((double)-1.0, cosine))); if (sine <= 0) { kaku = 2 * 3.141592653589793 - kaku; } return kaku; } vector<int> convex_hull(vector<complex<double>> a) { vector<int> ans; double now_minnest = a[0].real(); int now_itr = 0; for (long long i = 0; i < a.size(); ++i) { if (now_minnest > a[i].real()) { now_minnest = a[i].real(); now_itr = i; } } ans.push_back(now_itr); complex<double> ba(0, 1); while (true) { int now_go = 0; double now_min = 0; double now_length = 0; int starter = ans[ans.size() - 1]; for (int i = 0; i < a.size(); ++i) { if (i != starter) { double goa = angles(ba, a[i] - a[starter]); if (goa - now_min >= 1e-5 || (abs(goa - now_min) <= 1e-5 && (abs(a[i] - a[starter]) - now_length) >= 1e-5)) { now_min = goa; now_go = i; now_length = abs(a[i] - a[starter]); } } } if (now_go == ans[0]) break; ans.push_back(now_go); ba = complex<double>(a[now_go] - a[starter]); } return ans; } int ruiseki[1000000]; int main() { int test_case; cin >> test_case; for (long long i = 0; i < test_case; ++i) { string s; cin >> s; int ans = 0; ruiseki[0] = 0; for (int i = 0; i < s.length(); ++i) { if (i != 0) ruiseki[i] = ruiseki[i - 1]; if (s[i] == 1 ) { ruiseki[i]++; } } for (int i = 0; i < s.length(); ++i) { int now = 0; for (int q = i; q >= 0; --q) { if (i - q > 25) { int now_back = i - now + 1; int now_front = q; if (now_back > now_front) break; if (now_back < 0) break; int hoge = ruiseki[now_front]; if (now_back != 0) { hoge -= ruiseki[now_back - 1]; } if (hoge == 0) ans++; break; } if (s[q] == 1 ) { now += (1 << (i - q)); } if (now == i - q + 1) ans++; } } cout << ans << endl; } }
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//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Data TLB ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of DTLB. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Data TLB
//
module or1200_dmmu_tlb(
// Rst and clk
clk, rst,
// I/F for translation
tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// I/F for translation
//
input tlb_en;
input [aw-1:0] vaddr;
output hit;
output [31:`OR1200_DMMU_PS] ppn;
output uwe;
output ure;
output swe;
output sre;
output ci;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
wire [`OR1200_DTLB_TAG] vpn;
wire v;
wire [`OR1200_DTLB_INDXW-1:0] tlb_index;
wire tlb_mr_en;
wire tlb_mr_we;
wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_in;
wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out;
wire tlb_tr_en;
wire tlb_tr_we;
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_mr_so;
wire mbist_tr_so;
wire mbist_mr_si = mbist_si_i;
wire mbist_tr_si = mbist_mr_so;
assign mbist_so_o = mbist_tr_so;
`endif
//
// Implemented bits inside match and translate registers
//
// dtlbwYmrX: vpn 31-19 v 0
// dtlbwYtrX: ppn 31-13 swe 9 sre 8 uwe 7 ure 6
//
// dtlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 4 bits for protection
// 1 bit for cache inhibit
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_DTLB_TM_ADDR]);
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR];
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_DTLB_TM_ADDR]);
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_DTLB_TM_ADDR];
//
// Output to SPRS unit
//
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
{vpn, tlb_index & {`OR1200_DTLB_INDXW{v}}, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
(spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
{ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
32'h00000000;
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]};
//
// Assign outputs from Translate registers
//
assign {ppn, swe, sre, uwe, ure, ci} = tlb_tr_ram_out;
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_DMMU_PS],
spr_dat_i[`OR1200_DTLBTR_SWE_BITS],
spr_dat_i[`OR1200_DTLBTR_SRE_BITS],
spr_dat_i[`OR1200_DTLBTR_UWE_BITS],
spr_dat_i[`OR1200_DTLBTR_URE_BITS],
spr_dat_i[`OR1200_DTLBTR_CI_BITS]};
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v;
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
//
// Instantiation of DTLB Match Registers
//
or1200_spram_64x14 dtlb_mr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_mr_si),
.mbist_so_o(mbist_mr_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_mr_ram_in),
.doq(tlb_mr_ram_out)
);
//
// Instantiation of DTLB Translate Registers
//
or1200_spram_64x24 dtlb_tr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_tr_si),
.mbist_so_o(mbist_tr_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_tr_ram_in),
.doq(tlb_tr_ram_out)
);
endmodule
|
//--------------------------------------------------------------------------------
// flags.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Flags register.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module flags(
clock, wrFlags, config_data,
finish_now,
// outputs
flags_reg);
input clock;
input wrFlags;
input [31:0] config_data;
input finish_now;
output [31:0] flags_reg;
reg [31:0] flags_reg, next_flags_reg;
//
// Write flags register...
//
initial flags_reg = 0;
always @(posedge clock)
begin
flags_reg = next_flags_reg;
end
always @*
begin
#1;
next_flags_reg = (wrFlags) ? config_data : flags_reg;
if (finish_now) next_flags_reg[8] = 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[200020], b[200020], c[200020]; int main(void) { int n, k; int m; int i; int o; scanf( %d %d , &n, &k); for (i = 1; i <= n; i++) scanf( %d , &a[i]); for (i = 1; i <= n; i++) scanf( %d , &b[i]); for (i = 1, m = o = 0; i <= n; i++) if (a[i] < b[i]) { o += a[i]; --k; } else { o += b[i]; c[m++] = a[i] - b[i]; } if (k > 0) { sort(c, c + m); for (i = 0; i < k; i++) o += c[i]; } printf( %d n , o); return 0; }
|
`include "defines.v"
module data_ram(
input wire clk,
input wire ce,
input wire we,
input wire[`RegBus] addr,
input wire[3:0] sel,
input wire[`RegBus] data_i,
output reg[`RegBus] data_o
);
// 定义四个字节数组
reg[`ByteWidth] data_mem0[0:`DataMemNumber - 1];
reg[`ByteWidth] data_mem1[0:`DataMemNumber - 1];
reg[`ByteWidth] data_mem2[0:`DataMemNumber - 1];
reg[`ByteWidth] data_mem3[0:`DataMemNumber - 1];
// 写操作
always @(posedge clk) begin
if (ce == `ChipDisable) begin
end
else if (we == `WriteEnable) begin
if (sel[3] == 1'b1) begin
data_mem3[addr[`DataMemNumberLog2 + 1 : 2]] <= data_i[31:24];
end
if (sel[2] == 1'b1) begin
data_mem2[addr[`DataMemNumberLog2 + 1 : 2]] <= data_i[23:16];
end
if (sel[1] == 1'b1) begin
data_mem1[addr[`DataMemNumberLog2 + 1 : 2]] <= data_i[15:8];
end
if (sel[0] == 1'b1) begin
data_mem0[addr[`DataMemNumberLog2 + 1 : 2]] <= data_i[7:0];
end
end
end
// 读操作
always @(*) begin
if (ce == `ChipDisable) begin
data_o <= `ZeroWord;
end
else if (we == `WriteDisable) begin
data_o <= {data_mem3[addr[`DataMemNumberLog2 + 1 : 2]],
data_mem2[addr[`DataMemNumberLog2 + 1 : 2]],
data_mem1[addr[`DataMemNumberLog2 + 1 : 2]],
data_mem0[addr[`DataMemNumberLog2 + 1 : 2]]};
end
else begin
data_o <= `ZeroWord;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; map<string, int> mp; int t, x; string s; char ch; string transform(string x) { string s = ; for (char ch : x) if ((ch - 0 ) % 2) s += 1 ; else s += 0 ; while (s.size() < 20) s = 0 + s; return s; } int main() { ios::sync_with_stdio(false); cin >> t; for (int i = 0; i < t; i++) { cin >> ch >> s; s = transform(s); if (ch == ? ) { cout << mp[s] << endl; } else { if (ch == + ) mp[s]++; if (ch == - ) mp[s]--; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 7; int n, m; vector<int> d[MAXN]; int r[MAXN]; vector<pair<int, int> > g[MAXN]; inline void add_edge(int u, int v, int c) { g[u].push_back(make_pair(c, v)); g[v].push_back(make_pair(c, u)); } int col[MAXN]; inline bool dfs(int u, int c) { if (col[u] != -1) return col[u] == c; col[u] = c; for (auto e : (g[u])) { if (!dfs(e.second, c ^ e.first)) return 0; } return 1; } inline void read(int &x) { x = 0; int f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= f; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); read(n); read(m); for (int i = (1); i <= (n); ++i) read(r[i]); for (int i = (1); i <= (m); ++i) { int x; read(x); for (int j = (1); j <= (x); ++j) { int p; read(p); d[p].push_back(i); } } for (int i = (1); i <= (n); ++i) add_edge(d[i][0], d[i][1], r[i] ^ 1); memset(col, -1, sizeof col); bool ans = 1; for (int i = 1; i <= m && ans; ++i) if (col[i] == -1) ans &= dfs(i, 0); cout << (ans ? YES : NO ) << n ; return 0; }
|
module hydra_pll(PACKAGEPIN,
PLLOUTCORE,
PLLOUTGLOBAL,
DYNAMICDELAY,
RESET,
LOCK);
input PACKAGEPIN;
input [7:0] DYNAMICDELAY;
input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
output PLLOUTCORE;
output PLLOUTGLOBAL;
output LOCK;
SB_PLL40_PAD hydra_pll_inst(.PACKAGEPIN(PACKAGEPIN),
.PLLOUTCORE(PLLOUTCORE),
.PLLOUTGLOBAL(PLLOUTGLOBAL),
.EXTFEEDBACK(),
.DYNAMICDELAY(DYNAMICDELAY),
.RESETB(RESET),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(LOCK),
.SDI(),
.SDO(),
.SCLK());
//\\ Fin=10, Fout=100;
defparam hydra_pll_inst.DIVR = 4'b0000;
defparam hydra_pll_inst.DIVF = 7'b0001001;
defparam hydra_pll_inst.DIVQ = 3'b011;
defparam hydra_pll_inst.FILTER_RANGE = 3'b001;
defparam hydra_pll_inst.FEEDBACK_PATH = "DELAY";
defparam hydra_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "DYNAMIC";
defparam hydra_pll_inst.FDA_FEEDBACK = 4'b0000;
defparam hydra_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
defparam hydra_pll_inst.FDA_RELATIVE = 4'b0000;
defparam hydra_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
defparam hydra_pll_inst.PLLOUT_SELECT = "GENCLK";
defparam hydra_pll_inst.ENABLE_ICEGATE = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i, u, v, a, b, A, B, C; A = B = C = 0; cin >> a >> b; for (i = 1; i <= 6; i++) { u = abs(i - a); v = abs(i - b); if (u < v) A++; else if (u == v) B++; else C++; } cout << A << << B << << C; return 0; }
|
`timescale 1ns / 1ps
module quick_spi_hard_le_msb_testbench;
reg clk;
reg rst_n;
wire end_of_transaction;
wire[7:0] incoming_data;
reg[15:0] outgoing_data;
wire mosi;
reg miso;
wire sclk;
wire[1:0] ss_n;
reg enable;
reg start_transaction;
reg operation;
integer sclk_toggle_count;
reg[8:0] incoming_data_buffer;
reg spi_clock_phase;
initial begin
clk <= 1'b0;
rst_n <= 1'b0;
rst_n <= #50 1'b1;
outgoing_data <= {8'b11001100, 8'b10000010};
end
always @ (posedge clk)
begin
if(!rst_n)
begin
outgoing_data <= {8'b11001100, 8'b10000010};
enable <= 1'b1;
start_transaction <= 1'b1;
operation <= 1'b0;
miso <= 1'b0;
sclk_toggle_count <= 0;
incoming_data_buffer <= {8'b10010101, 1'b1};
spi_clock_phase <= 1'b1;
end
else
begin
if(end_of_transaction)
begin
operation <= ~operation;
sclk_toggle_count <= 0;
spi_clock_phase <= 1'b1;
incoming_data_buffer <= {8'b10010101, 1'b1};
miso <= 1'b0;
end
else
begin
if(sclk_toggle_count > 36)
begin
if(!spi_clock_phase)
begin
miso <= incoming_data_buffer[0];
incoming_data_buffer <= incoming_data_buffer >> 1;
end
end
sclk_toggle_count <= sclk_toggle_count + 1;
spi_clock_phase <= ~spi_clock_phase;
end
end
end
quick_spi_hard #
(
.BYTES_ORDER(0), // little endian,
.BITS_ORDER(1) // MSB First
)
spi
(
.clk(clk),
.reset_n(rst_n),
.enable(enable),
.start_transaction(start_transaction),
.slave(2'b01),
.operation(operation),
.end_of_transaction(end_of_transaction),
.incoming_data(incoming_data),
.outgoing_data(outgoing_data),
.mosi(mosi),
.miso(miso),
.sclk(sclk),
.ss_n(ss_n)
);
always #25 clk <= ~clk;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// - Igor Mohor () ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_tfifo.v.rca $
//
// Revision: 1.1.1.1 Tue Jun 7 09:39:01 2011 copew1
// first stab at merging s0903a branch.
//
// Revision: 1.1 Fri Jun 3 12:44:14 2011 tractp1
// UART in test bench to send/receive ASCII bytes with FPGA UART and
// command processing task in firmware
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
if (fifo_reset) begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= #1 top_plus_1;
count <= #1 count + 1'b1;
end
2'b01 : if(count>0)
begin
bottom <= #1 bottom + 1'b1;
count <= #1 count - 1'b1;
end
2'b11 : begin
bottom <= #1 bottom + 1'b1;
top <= #1 top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= #1 1'b0;
else
if(fifo_reset | reset_status)
overrun <= #1 1'b0;
else
if(push & (count==fifo_depth))
overrun <= #1 1'b1;
end // always
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2_2_V
`define SKY130_FD_SC_HD__AND2_2_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(); string s, mx; cin >> s; int len = s.length(); for (int i = 1; i < 1 << len; i++) { string foo; for (int j = 0; j < len; j++) if (i & (1 << j)) foo += s[j]; bool flag = 1; for (int k = 0; k <= foo.length() / 2; k++) if (foo[k] != foo[foo.length() - k - 1]) flag = 0; if (flag && foo > mx) mx = foo; } cout << mx; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Function with if clause
//
// D:
//
module main ();
reg [3:0] global_var;
reg [3:0] result;
// Interesting because 2 * 0 is 0 ;-)
function [3:0] my_func ;
input [3:0] a;
begin
if(a == 4'b0)
my_func = 4'b0;
else
my_func = a + a;
end
endfunction
initial
begin
global_var = 2;
result = my_func(global_var);
if(result != 4)
begin
$display("FAILED - function didn't function!\n");
$finish ;
end
$display("PASSED\n");
$finish ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 2e5 + 100; int a[M], b[M]; int n, x, y; int di[4][2] = {{1, 0}, {-1, 0}, {0, 1}, {0, -1}}; bool check(int xx, int yy) { if (xx < 1 || xx > x || yy < 1 || yy > y) return 0; return 1; } bool bfs() { queue<int> q; int l = 0; q.push(a[l]); l++; while (q.size()) { if (l == n) return 1; int ans = q.front(); int y1, x1; if (ans % y == 0) { y1 = y; x1 = ans / y; } else { y1 = ans % y; x1 = ans / y + 1; } q.pop(); for (int i = 0; i < 4; i++) { int nx = x1 + di[i][0], ny = y1 + di[i][1]; int res = (nx - 1) * y + ny; if (check(nx, ny) && res == a[l]) { q.push(a[l]); l++; break; } } } if (l == n + 1) return 1; else return 0; } int main() { while (~scanf( %d , &n)) { int mac = 0; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); mac = max(a[i], mac); } int l = 0; bool f = 1; for (int i = 0; i < n - 1; i++) { if (l == 0 && abs(a[i] - a[i + 1]) > 1) l = abs(a[i] - a[i + 1]); if (l && abs(a[i] - a[i + 1]) > 1) if (l != abs(a[i] - a[i + 1])) { f = 0; break; } } if (!f) printf( NO n ); else { if (l == 0) { x = 1; y = mac; } else { y = l; x = mac / l + 1; } bool tt = bfs(); if (tt) { printf( YES n ); printf( %d %d n , x, y); } else printf( NO n ); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A2111OI_PP_BLACKBOX_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_PP_BLACKBOX_V
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/sprdma.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Sprite DMA control block.
***************************************************************************************************/
`timescale 1ps / 1ps
module sprdma
(
input wire clk_in, // 100MHz system clock signal
input wire rst_in, // reset signal
input wire [15:0] cpumc_a_in, // cpu address bus in (to snoop cpu writes of 0x4014)
input wire [ 7:0] cpumc_din_in, // cpumc din bus in (to snoop cpu writes of 0x4014)
input wire [ 7:0] cpumc_dout_in, // cpumc dout bus in (to receive sprdma read data)
input wire cpu_r_nw_in, // cpu write enable (to snoop cpu writes of 0x4014)
output wire active_out, // high when sprdma is active (de-assert cpu ready signal)
output reg [15:0] cpumc_a_out, // cpu address bus out (for dma cpu mem reads/writes)
output reg [ 7:0] cpumc_d_out, // cpu data bus out (for dma mem writes)
output reg cpumc_r_nw_out // cpu r_nw signal out (for dma mem writes)
);
// Symbolic state representations.
localparam [1:0] S_READY = 2'h0,
S_ACTIVE = 2'h1,
S_COOLDOWN = 2'h2;
reg [ 1:0] q_state, d_state; // current fsm state
reg [15:0] q_addr, d_addr; // current cpu address to be copied to sprite ram
reg [ 1:0] q_cnt, d_cnt; // counter to manage stages of dma copies
reg [ 7:0] q_data, d_data; // latch for data read from cpu mem
// Update FF state.
always @(posedge clk_in)
begin
if (rst_in)
begin
q_state <= S_READY;
q_addr <= 16'h0000;
q_cnt <= 2'h0;
q_data <= 8'h00;
end
else
begin
q_state <= d_state;
q_addr <= d_addr;
q_cnt <= d_cnt;
q_data <= d_data;
end
end
always @*
begin
// Default regs to current state.
d_state = q_state;
d_addr = q_addr;
d_cnt = q_cnt;
d_data = q_data;
// Default to no memory action.
cpumc_a_out = 16'h00;
cpumc_d_out = 8'h00;
cpumc_r_nw_out = 1'b1;
if (q_state == S_READY)
begin
// Detect write to 0x4014 to begin DMA.
if ((cpumc_a_in == 16'h4014) && !cpu_r_nw_in)
begin
d_state = S_ACTIVE;
d_addr = { cpumc_din_in, 8'h00 };
end
end
else if (q_state == S_ACTIVE)
begin
case (q_cnt)
2'h0:
begin
cpumc_a_out = q_addr;
d_cnt = 2'h1;
end
2'h1:
begin
cpumc_a_out = q_addr;
d_data = cpumc_dout_in;
d_cnt = 2'h2;
end
2'h2:
begin
cpumc_a_out = 16'h2004;
cpumc_d_out = q_data;
cpumc_r_nw_out = 1'b0;
d_cnt = 2'h0;
if (q_addr[7:0] == 8'hff)
d_state = S_COOLDOWN;
else
d_addr = q_addr + 16'h0001;
end
endcase
end
else if (q_state == S_COOLDOWN)
begin
if (cpu_r_nw_in)
d_state = S_READY;
end
end
assign active_out = (q_state == S_ACTIVE);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const int MOD = 1e9 + 7; int aa[N]; int tree[4 * N]; int query(int v, int l, int r, int L, int R) { if (l > r || l > R || r < L) return 0; if (L <= l && r <= R) return tree[v]; int v1 = 2 * v + 1; int v2 = 2 * v + 2; int mid = (l + r) / 2; int q1 = query(v1, l, mid, L, R); int q2 = query(v2, mid + 1, r, L, R); return (q1 + q2) % MOD; } void update(int v, int l, int r, int pos, int newVal) { if (l > r || l > pos || r < pos) return; if (l == r && l == pos) { tree[v] = newVal; return; } int v1 = 2 * v + 1; int v2 = 2 * v + 2; int mid = (l + r) / 2; update(v1, l, mid, pos, newVal); update(v2, mid + 1, r, pos, newVal); tree[v] = (tree[v1] + tree[v2]) % MOD; } int bpow(long long bb, int ee) { if (ee < 0) return 0; int res = 1; while (ee > 0) { if (ee % 2 == 1) res = res * bb % MOD; bb = bb * bb % MOD; ee >= 1; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) cin >> aa[i]; const int ml = 1e6; update(0, 0, ml, 0, 1); long long ans = 0; for (int i = 1; i <= n; i++) { int s = query(0, 0, ml, 0, aa[i]); int hm = (s * 1LL * aa[i]) % MOD; update(0, 0, ml, aa[i], hm); } set<int> dict; for (int i = 1; i <= n; i++) dict.insert(aa[i]); for (int i : dict) ans += query(0, 0, ml, i, i); cout << ans % MOD << n ; return 0; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_implication (clock, reset, enable, antecedent_expr, consequent_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input antecedent_expr, consequent_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_IMPLICATION";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/ovl_implication_logic.v"
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_implication_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_implication_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endmodule // ovl_implication
`endif
|
#include <bits/stdc++.h> using namespace std; long long t, n, i, j, k, b[200005], a[200005], x, m, l, r, mid, ans, s; vector<long long> u, v; int main() { ios::sync_with_stdio(NULL); cin.tie(0); cout.tie(0); cin >> n; for (i = 0; i < n; i++) { cin >> x; if (x % 2) v.push_back(x); else u.push_back(x); s += x; } sort(u.begin(), u.end(), greater<long long>()); sort(v.begin(), v.end(), greater<long long>()); n = v.size(); m = u.size(); n = min(n, m); for (i = 0; i < n; i++) s -= u[i] + v[i]; if (u.size() > v.size()) s -= u[i]; if (u.size() < v.size()) s -= v[i]; cout << s; }
|
#include <bits/stdc++.h> using namespace std; vector<int> a = vector<int>(10, 0); vector<int> b; int main() { srand(time(NULL)); for (int i = 0; i < 6; i++) { int x; cin >> x; a[x]++; } bool f = false; for (int i = 0; i < 10; i++) { if (a[i] != 0) { b.push_back(a[i]); } if (a[i] >= 4) { f = true; } } if (b.size() > 3 || f == false) { cout << Alien << endl; return 0; } sort(b.begin(), b.end()); if (b.size() == 3 || (b[0] == 1 && b[1] == 5)) { cout << Bear << endl; return 0; } if (b.size() <= 2) { cout << Elephant << endl; return 0; } return 0; }
|
#include <bits/stdc++.h> using namespace std; #define F first #define S second #define pb push_back #define ll long long #define all(x) x.begin() , x.end() #define rep(i,s,e) for (int i = s; i < e; ++i) #define rev(i,s,e) for (int i = s; i > e; --i) const int N = 2e5 + 99 ; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); #ifdef CLion freopen( input.txt , r , stdin); // freopen( output.txt , w , stdout); #endif int t; cin >> t; while ( t-- ){ int n ; cin >> n; vector<int> vec(n); for ( int &i : vec ){ cin >> i; } sort( all(vec) ); cout << n - (upper_bound(all(vec) , vec.front()) - vec.begin()) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 50; deque<int> dq; bool is[N], can[N]; vector<vector<int> > adj(N); int n, m, d, cur, mx, ans[N], x; void dfs(int u, int p) { ans[u] = ans[p] + 1; can[u] &= (ans[u] <= d); if (ans[u] > mx && is[u]) mx = ans[u], x = u; for (auto v : adj[u]) if (v != p) dfs(v, u); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m >> d; ans[0] = -1; memset(can, 1, sizeof can); for (int i = 0; i < m; i++) cin >> x, is[x] = 1; for (int i = 1, u, v; i < n; i++) { cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dq.push_front(x); while (dq.size()) { int now = dq.front(); dfs(now, 0); dq.pop_front(); if (now != x) dq.push_front(x); } int s = 0; for (int i = 1; i <= n; i++) s += can[i]; cout << s; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const long long N = 1e6 + 1; long long pre[N], sub[N]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; string str; cin >> str; long long a = 0, b = 0, c = 0; for (long long i = 0; i < str.size(); i++) { if (str[i] == o ) { b += a; } else if (i > 0 && str[i - 1] == v ) { a++; c += b; } } cout << c << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O221AI_FUNCTIONAL_PP_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221AI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, s = 0; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; s += a[i]; } sort(begin(a), end(a)); if (s % 2 == 0 && 2 * a[n - 1] <= s) cout << YES ; else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[300005]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int Sum = 0; for (int i = 1; i <= n; i++) Sum += a[i]; int indx = 0; int Taken = 0; while (Sum > 2 * Taken) { indx++; Taken += a[indx]; } cout << indx << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; #define ll long long #define ull unsigned long long #define uint unsigned int #define loop(n) for(int i=1;i<=n;i++) int main() { ios_base::sync_with_stdio(false); cout.tie(NULL); cin.tie(NULL); uint t; cin>>t; while(t--) { int n,temp,tem; ll min=INT_MAX; cin>>n; map<int,int> a; vector<int> s; set<int> st; loop(n) { cin>>temp; tem=a[temp]; a[temp]=tem+1; } for(auto i:a) { //cout<<i.second<< ; s.push_back(i.second); st.insert(i.second); } for(auto mid:st) { ll sum=0; for(auto i:s) if(i<mid) sum+=i; else sum+=i-mid; if(min>sum) min=sum; } cout<<min<<endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1005; const int MOD = 1000000007; int N, P; int dp[MAXN][4]; int a[MAXN], b[MAXN]; int cnt[3]; void load() { scanf( %d%d , &N, &P); } inline int add(int x, int y) { x += y; if (x >= MOD) x -= MOD; else if (x < 0) x += MOD; return x; } inline int mul(int x, int y) { return (long long)x * y % MOD; } void add(int lo, int hi, int val) { cnt[val] = add(cnt[val], mul(hi - lo + 1, add(P, -mul(add(lo, hi), (MOD + 1) / 2)))); } int solve() { if (P == 1) return 0; a[0] = 1; b[0] = 0; a[1] = 3; b[1] = 1; a[2] = 4; b[2] = 2; a[3] = 5; b[3] = 1; a[4] = 7; b[4] = 2; a[5] = 9; b[5] = 0; a[6] = 13; b[6] = 1; a[7] = 15; b[7] = 2; a[8] = 19; b[8] = 0; a[9] = 27; b[9] = 1; a[10] = 39; b[10] = 2; a[11] = 40; b[11] = 0; a[12] = 57; b[12] = 2; a[13] = 58; b[13] = 1; a[14] = 81; b[14] = 2; a[15] = 85; b[15] = 0; a[16] = 120; b[16] = 2; a[17] = 121; b[17] = 1; a[18] = 174; b[18] = 2; a[19] = 179; b[19] = 0; a[20] = 255; b[20] = 2; a[21] = 260; b[21] = 1; a[22] = 363; b[22] = 2; a[23] = 382; b[23] = 0; a[24] = 537; b[24] = 2; a[25] = 544; b[25] = 1; a[26] = 780; b[26] = 2; a[27] = 805; b[27] = 0; a[28] = 1146; b[28] = 2; a[29] = 1169; b[29] = 1; a[30] = 1632; b[30] = 2; a[31] = 1718; b[31] = 0; a[32] = 2415; b[32] = 2; a[33] = 2447; b[33] = 1; a[34] = 3507; b[34] = 2; a[35] = 3622; b[35] = 0; a[36] = 5154; b[36] = 2; a[37] = 5260; b[37] = 1; a[38] = 7341; b[38] = 2; a[39] = 7730; b[39] = 0; a[40] = 10866; b[40] = 2; a[41] = 11011; b[41] = 1; a[42] = 15780; b[42] = 2; a[43] = 16298; b[43] = 0; a[44] = 23190; b[44] = 2; a[45] = 23669; b[45] = 1; a[46] = 33033; b[46] = 2; a[47] = 34784; b[47] = 0; a[48] = 48894; b[48] = 2; a[49] = 49549; b[49] = 1; a[50] = 71007; b[50] = 2; a[51] = 73340; b[51] = 0; a[52] = 104352; b[52] = 2; a[53] = 106510; b[53] = 1; a[54] = 148647; b[54] = 2; a[55] = 156527; b[55] = 0; a[56] = 220020; b[56] = 2; a[57] = 222970; b[57] = 1; a[58] = 319530; b[58] = 2; a[59] = 330029; b[59] = 0; a[60] = 469581; b[60] = 2; a[61] = 479294; b[61] = 1; a[62] = 668910; b[62] = 2; a[63] = 704371; b[63] = 0; a[64] = 990087; b[64] = 2; a[65] = 1003364; b[65] = 1; a[66] = 1437882; b[66] = 2; a[67] = 1485130; b[67] = 0; a[68] = 2113113; b[68] = 2; a[69] = 2156822; b[69] = 1; a[70] = 3010092; b[70] = 2; a[71] = 3169669; b[71] = 0; a[72] = 4455390; b[72] = 2; a[73] = 4515137; b[73] = 1; a[74] = 6470466; b[74] = 2; a[75] = 6683084; b[75] = 0; a[76] = 9509007; b[76] = 2; a[77] = 9705698; b[77] = 1; a[78] = 13545411; b[78] = 2; a[79] = 14263510; b[79] = 0; a[80] = 20049252; b[80] = 2; a[81] = 20318116; b[81] = 1; a[82] = 29117094; b[82] = 2; a[83] = 30073877; b[83] = 0; a[84] = 42790530; b[84] = 2; a[85] = 43675640; b[85] = 1; a[86] = 60954348; b[86] = 2; a[87] = 64185794; b[87] = 0; a[88] = 90221631; b[88] = 2; a[89] = 91431521; b[89] = 1; a[90] = 131026920; b[90] = 2; a[91] = 135332446; b[91] = 0; a[92] = 192557382; b[92] = 2; a[93] = 196540379; b[93] = 1; a[94] = 274294563; b[94] = 2; a[95] = 288836072; b[95] = 0; a[96] = 405997338; b[96] = 2; a[97] = 411441844; b[97] = 1; a[98] = 589621137; b[98] = 2; a[99] = 608996006; b[99] = 0; a[100] = 866508216; b[100] = 2; a[101] = 884431705; b[101] = 1; a[102] = 1000000000; b[102] = 0; for (int i = 0; i < MAXN; i++) { if (a[i + 1] >= P) { add(a[i], P - 1, b[i]); break; } add(a[i], a[i + 1] - 1, b[i]); } dp[0][0] = 1; for (int i = 1; i <= N; i++) for (int j = 0; j < 4; j++) for (int k = 0; k < 3; k++) dp[i][j] = add(dp[i][j], mul(cnt[k], dp[i - 1][j ^ k])); int sol = 0; for (int i = 1; i < 4; i++) sol = add(sol, dp[N][i]); return sol; } int main() { load(); printf( %d n , solve()); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 400010; inline int max(int a, int b) { return a > b ? a : b; } int head[maxn], cnt, sz[maxn], n, mx_sz, top[maxn], ans[maxn]; vector<int> vt; struct ed { int to, next; } e[maxn * 2]; void ad(int x, int y) { e[cnt] = (ed){y, head[x]}; head[x] = cnt++; e[cnt] = (ed){x, head[y]}; head[y] = cnt++; } void get_vt(int u, int last) { sz[u] = 1; int mx = 0; for (int k = head[u]; ~k; k = e[k].next) { int v = e[k].to; if (v != last) { get_vt(v, u); sz[u] += sz[v]; mx = max(mx, sz[v]); } } mx = max(mx, n - sz[u]); if (mx <= mx_sz) vt.push_back(u); } void dfs(int u, int last, int tp) { sz[u] = 1, top[u] = tp; for (int k = head[u]; ~k; k = e[k].next) { int v = e[k].to; if (v != last) { dfs(v, u, tp); sz[u] += sz[v]; } } } void work(int u) { ans[u] = 1; memset(sz, 0, sizeof(sz)); int mx = 0, _mx = 0; for (int k = head[u]; ~k; k = e[k].next) { int v = e[k].to; dfs(v, u, v); if (sz[v] >= sz[mx]) _mx = mx, mx = v; else if (sz[v] > sz[_mx]) _mx = v; } for (int i = 1; i <= n; i++) { if (top[i] == mx) ans[i] |= (n - sz[i] - sz[_mx] <= mx_sz); else ans[i] |= (n - sz[i] - sz[mx] <= mx_sz); } } int main() { while (~scanf( %d , &n)) { cnt = 0; mx_sz = n / 2; vt.clear(); memset(sz, 0, sizeof(sz)); memset(ans, 0, sizeof(ans)); memset(head, -1, sizeof(head)); int u, v; for (int i = 1; i < n; i++) { scanf( %d%d , &u, &v); ad(u, v); } get_vt(1, 0); for (int i = 0; i < vt.size(); i++) work(vt[i]); for (int i = 1; i <= n; i++) printf( %d , ans[i]); } return 0; }
|
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : v7_enet_top.v
// Version : 0.2
// Author : Shreejith S
//
// Description: Merged Ethernet Controller Top File for V7
//
//--------------------------------------------------------------------------------
module ethernet_top(
input i_rst,
input i_clk_125,
input i_clk_200,
output phy_resetn,
// V6 GMII I/F
output [7:0] gmii_txd,
output gmii_tx_en,
output gmii_tx_er,
output gmii_tx_clk,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_er,
input gmii_rx_clk,
input gmii_col,
input gmii_crs,
input mii_tx_clk,
// V7 SGMII I/F
// Commom I/F for V7 Enet - Not used here
input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality.
input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality.
output txp, // Differential +ve of serial transmission from PMA to PMD.
output txn, // Differential -ve of serial transmission from PMA to PMD.
input rxp, // Differential +ve for serial reception from PMD to PMA.
input rxn, // Differential -ve for serial reception from PMD to PMA.
output synchronization_done,
output linkup,
// PHY MDIO I/F
output mdio_out,
input mdio_in,
output mdc_out,
output mdio_t,
//Reg file
input i_enet_enable, // Enable the ethernet core
input i_enet_loopback, // Enable loopback mode
input [31:0] i_enet_ddr_source_addr, // Where is data for ethernet
input [31:0] i_enet_ddr_dest_addr, // Where to store ethernet data
input [31:0] i_enet_rcv_data_size, // How much data should be received from enet
input [31:0] i_enet_snd_data_size, // How much data should be sent through enet
output [31:0] o_enet_rx_cnt, // Ethernet RX Performance Counter
output [31:0] o_enet_tx_cnt, // Ethernet TX Performance Counter
output o_enet_rx_done, // Ethernet RX Completed
output o_enet_tx_done, // Ethernet TX Completed
//To DDR controller
output o_ddr_wr_req,
output o_ddr_rd_req,
output [255:0] o_ddr_wr_data,
output [31:0] o_ddr_wr_be,
output [31:0] o_ddr_wr_addr,
output [31:0] o_ddr_rd_addr,
input [255:0] i_ddr_rd_data,
input i_ddr_wr_ack,
input i_ddr_rd_ack,
input i_ddr_rd_data_valid
);
// Instantiate V7 Top File
v7_ethernet_top v7_et
(
.glbl_rst(i_rst),
.i_clk_200(i_clk_200),
.phy_resetn(phy_resetn),
.gtrefclk_p(gtrefclk_p),
.gtrefclk_n(gtrefclk_n),
.txp(txp),
.txn(txn),
.rxp(rxp),
.rxn(rxn),
.synchronization_done(synchronization_done),
.linkup(linkup),
.mdio_i(mdio_in),
.mdio_o(mdio_out),
.mdio_t(mdio_t),
.mdc(mdc_out),
.i_enet_enable(i_enet_enable),
.i_enet_loopback(i_enet_loopback),
.i_enet_ddr_source_addr(i_enet_ddr_source_addr),
.i_enet_ddr_dest_addr(i_enet_ddr_dest_addr),
.i_enet_rcv_data_size(i_enet_rcv_data_size),
.i_enet_snd_data_size(i_enet_snd_data_size),
.o_enet_rx_cnt(o_enet_rx_cnt),
.o_enet_tx_cnt(o_enet_tx_cnt),
.o_enet_rx_done(o_enet_rx_done),
.o_enet_tx_done(o_enet_tx_done),
.o_ddr_wr_req(o_ddr_wr_req),
.o_ddr_rd_req(o_ddr_rd_req),
.o_ddr_wr_data(o_ddr_wr_data),
.o_ddr_wr_be(o_ddr_wr_be),
.o_ddr_wr_addr(o_ddr_wr_addr),
.o_ddr_rd_addr(o_ddr_rd_addr),
.i_ddr_rd_data(i_ddr_rd_data),
.i_ddr_wr_ack(i_ddr_wr_ack),
.i_ddr_rd_ack(i_ddr_rd_ack),
.i_ddr_rd_data_valid(i_ddr_rd_data_valid)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int N = 5e5 + 5; long long l[N], r[N], x[N], d[N], s[N], pre[N], dp[N]; int n, m; inline long long solve(int u) { for (int i = 1; i <= n; i++) d[i] = s[i] = pre[i] = 0; for (int i = 1; i <= m; i++) { if (x[i] >> u & 1) { d[r[i] + 1]--; d[l[i]]++; } else { pre[r[i]] = max(pre[r[i]], l[i]); } } dp[0] = s[0] = 1; for (int i = 1; i <= n; i++) { d[i] += d[i - 1]; pre[i] = max(pre[i], pre[i - 1]); if (d[i] > 0) dp[i] = 0; else if (pre[i - 1] > 0) dp[i] = (s[i - 1] - s[pre[i - 1] - 1]) % mod; else dp[i] = s[i - 1]; s[i] = (s[i] + s[i - 1] + dp[i]) % mod; } return pre[n] == 0 ? s[n] % mod : (s[n] - s[pre[n] - 1]) % mod; } int main() { int k; scanf( %d%d%d , &n, &k, &m); for (int i = 1; i <= m; i++) scanf( %lld%lld%lld , &l[i], &r[i], &x[i]); long long ans = 1; for (int i = 0; i < k; i++) ans = ans * solve(i) % mod; printf( %lld n , (ans + mod) % mod); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_2_V
`define SKY130_FD_SC_HDLL__O21BAI_2_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_2_V
|
#include <bits/stdc++.h> using namespace std; int n; vector<string> cards; map<vector<string>, bool> used; void rec(vector<string>& x) { if (x.size() == 1) { puts( YES ); exit(0); } if (used[x] == true) return; used[x] = true; int p = x.size() - 1; if (x[p][0] == x[p - 1][0] || x[p][1] == x[p - 1][1]) { string s = x[p - 1]; string c = x[p]; x[p - 1] = x[p]; x.pop_back(); rec(x); x[p - 1] = s; x.push_back(c); } if (p > 2 && (x[p][0] == x[p - 3][0] || x[p][1] == x[p - 3][1])) { string s = x[p - 3]; string c = x[p]; x[p - 3] = x[p]; x.pop_back(); rec(x); x[p - 3] = s; x.push_back(c); } } int main() { cin >> n; for (int i = 0; i < n; i++) { string s; cin >> s; cards.push_back(s); } rec(cards); puts( NO ); return 0; }
|
`timescale 1ns/10ps
module soc_system_pll_stream(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("130.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_64
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_64(
input wire [54:0] Data_Dec_i,
output reg [5:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
Data_Bin_o=6'b000000;
if(~Data_Dec_i[54]) begin Data_Bin_o = 6'b000000;//0
end else if(~Data_Dec_i[53]) begin Data_Bin_o = 6'b000001;//1
end else if(~Data_Dec_i[52]) begin Data_Bin_o = 6'b000010;//2
end else if(~Data_Dec_i[51]) begin Data_Bin_o = 6'b000011;//3
end else if(~Data_Dec_i[50]) begin Data_Bin_o = 6'b000100;//4
end else if(~Data_Dec_i[49]) begin Data_Bin_o = 6'b000101;//5
end else if(~Data_Dec_i[48]) begin Data_Bin_o = 6'b000110;//6
end else if(~Data_Dec_i[47]) begin Data_Bin_o = 6'b000111;//7
end else if(~Data_Dec_i[46]) begin Data_Bin_o = 6'b001000;//8
end else if(~Data_Dec_i[45]) begin Data_Bin_o = 6'b001001;//9
end else if(~Data_Dec_i[44]) begin Data_Bin_o = 6'b001010;//10
end else if(~Data_Dec_i[43]) begin Data_Bin_o = 6'b001011;//11
end else if(~Data_Dec_i[42]) begin Data_Bin_o = 6'b001100;//12
end else if(~Data_Dec_i[41]) begin Data_Bin_o = 6'b001101;//13
end else if(~Data_Dec_i[40]) begin Data_Bin_o = 6'b001110;//14
end else if(~Data_Dec_i[39]) begin Data_Bin_o = 6'b001111;//15
end else if(~Data_Dec_i[38]) begin Data_Bin_o = 6'b010000;//16
end else if(~Data_Dec_i[37]) begin Data_Bin_o = 6'b010001;//17
end else if(~Data_Dec_i[36]) begin Data_Bin_o = 6'b010010;//18
end else if(~Data_Dec_i[35]) begin Data_Bin_o = 6'b010011;//19
end else if(~Data_Dec_i[34]) begin Data_Bin_o = 6'b010100;//20
end else if(~Data_Dec_i[33]) begin Data_Bin_o = 6'b010101;//21
end else if(~Data_Dec_i[32]) begin Data_Bin_o = 6'b010110;//22
end else if(~Data_Dec_i[31]) begin Data_Bin_o = 6'b010111;//23
end else if(~Data_Dec_i[30]) begin Data_Bin_o = 6'b011000;//24
end else if(~Data_Dec_i[29]) begin Data_Bin_o = 6'b010101;//25
end else if(~Data_Dec_i[28]) begin Data_Bin_o = 6'b010110;//26
end else if(~Data_Dec_i[27]) begin Data_Bin_o = 6'b010111;//27
end else if(~Data_Dec_i[26]) begin Data_Bin_o = 6'b011000;//28
end else if(~Data_Dec_i[25]) begin Data_Bin_o = 6'b011001;//29
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 6'b011010;//30
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 6'b011011;//31
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 6'b011100;//32
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 6'b011101;//33
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 6'b011110;//34
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 6'b011111;//35
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 6'b100000;//36
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 6'b100001;//37
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 6'b100010;//38
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 6'b100011;//39
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 6'b100100;//40
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 6'b100101;//41
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 6'b100110;//42
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 6'b100111;//43
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 6'b101000;//44
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 6'b101001;//45
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 6'b101010;//46
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 6'b101011;//47
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 6'b101100;//48
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 6'b101101;//49
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 6'b101110;//50
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 6'b101111;//51
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 6'b110000;//52
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 6'b110001;//53
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 6'b110010;//54
end else begin Data_Bin_o = 6'b000000;//zero value
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, s; const int N = 1e5 + 10; int v[N]; int ans; bool check(int x, int &res) { int k[n]; for (int i = 0; i < n; i++) { k[i] = v[i] + (i + 1) * x; } sort(k, k + n); for (int i = 0; i < x; i++) if (res <= s) res += k[i]; return res <= s; } int main() { cin >> n >> s; for (int i = 0; i < n; i++) { cin >> v[i]; } int hi = n + 1; int lo = 0; for (int i = 0; i < 100; i++) { int mid = (hi + lo) >> 1; int valor = 0; if (check(mid, valor)) { ans = valor; lo = mid; } else hi = mid; } cout << lo << << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); int R, C; string t[2222]; int s1[2222][2222]; int main() { memset(s1, 0, sizeof(s1)); cin >> R >> C; for (int r = 0; r < (int)R; r++) { cin >> t[r]; for (int c = 0; c < (int)C; c++) { if (t[r][c] == w ) { s1[r + 1][c + 1]++; } } } for (int r = 0; r < (int)2221; r++) { for (int c = 0; c < (int)2221; c++) { s1[r + 1][c + 1] += (s1[r + 1][c] + s1[r][c + 1] - s1[r][c]); } } int lo = 0; int hi = max(R, C); while (lo < hi - 1) { int len = (lo + hi) / 2; bool isSome = false; for (int r = 0; r + len - 1 < max(R, C); r++) { for (int c = 0; c + len - 1 < max(R, C); c++) { if (s1[r + len][c + len] - s1[r + len][c] - s1[r][c + len] + s1[r][c] == s1[2221][2221]) { isSome = true; break; } } if (isSome) break; } if (isSome) hi = len; else lo = len; } cerr << hi << endl; bool done = false; for (int r = 0; r + hi - 1 < R; r++) { for (int c = 0; c + hi - 1 < C; c++) { int big = s1[r + hi][c + hi] - s1[r][c + hi] - s1[r + hi][c] + s1[r][c]; int small = 0; if (hi != 1 && hi != 2) { small = s1[r + hi - 1][c + hi - 1] - s1[r + 1][c + hi - 1] - s1[r + hi - 1][c + 1] + s1[r + 1][c + 1]; } if (big - small == s1[2221][2221]) { for (int i = 0; i < hi; i++) { if (t[r][c + i] == . ) t[r][c + i] = + ; if (t[r + hi - 1][c + i] == . ) t[r + hi - 1][c + i] = + ; if (t[r + i][c] == . ) t[r + i][c] = + ; if (t[r + i][c + hi - 1] == . ) t[r + i][c + hi - 1] = + ; } done = true; break; } if (done) break; } if (done) break; } if (done) { for (int r = 0; r < (int)R; r++) { for (int c = 0; c < (int)C; c++) { cout << t[r][c]; } cout << endl; } cout << endl; } else { cout << -1 << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND4_PP_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n; int a[2000010]; int main() { while (~scanf( %d , &n)) { for (int i = 1; i <= n; i++) a[i] = i; for (int k = 2; k <= n; k++) { int ed = n + k - 1, rp = n / k + (n % k != 0); for (int t = k - 1 + (rp - 1) * k; t >= k - 1; t -= k) { swap(a[ed], a[t]); ed = t; } } for (int i = n; i <= 2 * n - 1; i++) printf( %d , a[i]); puts( ); } }
|
#include <bits/stdc++.h> using namespace std; double x[101010], y[101010]; double maxn[101010], minn[101010]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lf , &maxn[i]); for (int i = 1; i <= n; i++) scanf( %lf , &minn[i]); for (int i = n - 1; i >= 1; i--) minn[i] += minn[i + 1]; double resx = 1, resy = 1, getx = 0, gety = 0; maxn[0] = 0; bool key = false; for (int i = 1; i < n; i++) { maxn[i] += maxn[i - 1]; double k1 = maxn[i]; double k2 = minn[i]; double a = 0, b = 0, c = 0; a += 1; b += minn[i + 1] - maxn[i] - 1; c += maxn[i]; double det = b * b - 4 * a * c; if (det < 0) { if (det < -0.01) { printf( %.3f-- n , det); key = true; } det = 0; } double ans1 = (-b + sqrt(det)) / (2 * a); double ans2 = (-b - sqrt(det)) / (2 * a); x[i] = ans1; y[i] = ans2; } y[n] = x[n] = 1; for (int i = n; i >= 1; i--) { x[i] = x[i] - x[i - 1]; y[i] -= y[i - 1]; } for (int i = 1; i <= n; i++) { printf( %.8f , y[i]); if (i == n) printf( n ); else printf( ); } for (int i = 1; i <= n; i++) { printf( %.8f , x[i]); if (i == n) printf( n ); else printf( ); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[1000]; int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int res = 0; int sum = 10; int ress = 0; for (int i = 0; i < n; i++) { sum += a[i]; if (sum <= 720) { res++; if (sum > 360) { ress += sum - 360; } } } cout << res << << ress; return 0; }
|
#include <bits/stdc++.h> using namespace std; #define ll long long const int N = 3e5+10, oo = 1e9+10; void solve() { int n; cin >> n; vector<ll> a(n+1); ll ans = 0; vector<ll> answers; answers.reserve(n-1); for(int i = 1; i <= n; ++i) { cin >> a[i]; ans += a[i]; } answers.push_back(ans); vector<vector<ll>> edges(n+1); vector<ll> deg(n+1); for(int i = 0; i < n - 1; ++i) { ll u, v; cin >> u >> v; ++deg[u]; ++deg[v]; } vector<ll> can_take; for(int i = 1; i <= n; ++i) { for(int x = 0; x < deg[i] - 1; ++x) { can_take.push_back(a[i]); } } sort(can_take.begin(), can_take.end()); while(answers.size() < n - 1) { answers.push_back(can_take.back() + answers.back()); can_take.pop_back(); } assert(answers.size() == n - 1); for(ll x : answers) { cout << x << ; } cout << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); int T = 1; cin >> T; while(T--) { solve(); } }
|
module peripheral_crc_7(clk , rst , d_in , cs , addr , rd , wr, d_out );
//entradas y salidas j1
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
//------------------------------------ regs and wires-------------------------------
//registros modulo peripheral
reg [3:0] s; //selector mux_4 and write registers
reg [16:0] data_in=0;
reg start=0;
wire [6:0] data_out;
wire done;
//------------------------------------ regs and wires-------------------------------
always @(*) begin//------address_decoder------------------------------
case (addr)
//se asignan direcciones
//direcciones de escritura
4'h0:begin s = (cs && wr) ? 4'b0001 : 4'b0000 ;end //data_in
4'h2:begin s = (cs && wr) ? 4'b0010 : 4'b0000 ;end //start
//direcciones de lectura
4'h4:begin s = (cs && rd) ? 4'b0100 : 4'b0000 ;end //done
4'h6:begin s = (cs && rd) ? 4'b1000 : 4'b0000 ;end //data_out
default:begin s = 4'b0000 ; end
endcase
end//------------------address_decoder--------------------------------
always @(negedge clk) begin//-------------------- escritura de registros
data_in = (s[0]) ? d_in : data_in; //Write Registers
start = s[1]; //Write Registers
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s[3:2])
2'b01: d_out[0] = done ;
2'b10: d_out[6:0] = data_out ;
default: d_out = 0 ;
endcase
end//-----------------------------------------------mux_4
crc_7 c_7 ( .clk(clk), .rst(rst), .data_in(data_in), .start(start), .data_out(data_out), .done(done) ); // se instancia modulo crc7
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
assign valid_test_expr = ~((^test_expr) ^ (^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
reg [width-1:0] last_test_expr;
reg [width:0] temp_expr1;
reg [width:0] temp_expr2;
reg r_reset_n;
`ifdef OVL_SYNTHESIS
`else
initial begin
r_reset_n = 1'b0;
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
r_reset_n <= `OVL_RESET_SIGNAL;
last_test_expr <= test_expr;
// check second clock afer reset
if (r_reset_n && (last_test_expr != test_expr)) begin
temp_expr1 = {1'b0,last_test_expr} - {1'b0,test_expr};
temp_expr2 = {1'b0,test_expr} - {1'b0,last_test_expr};
// 2's complement result
if (!((temp_expr1 >= min && temp_expr1 <= max) ||
(temp_expr2 >= min && temp_expr2 <=max)))
begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression changed by a delta value not in the range specified by min and max");
end
end
end
else begin
r_reset_n <= 0;
`ifdef OVL_INIT_REG
last_test_expr <= {width{1'b0}};
temp_expr1 = {(width+1){1'b0}};
temp_expr2 = {(width+1){1'b0}};
`endif
end
end // always
`endif // ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @(posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
reg [width-1:0] prev_test_expr;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
if (test_expr != prev_test_expr) begin
ovl_cover_t("test_expr_change covered");
end
prev_test_expr <= test_expr;
end //basic coverage
end // OVL_COVER_NONE
end
else begin
`ifdef OVL_INIT_REG
prev_test_expr <= {width{1'b0}};
`endif
end
end //always
`endif // OVL_COVER_ON
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); double h, w; cin >> h >> w; int ans1, ans2, mx = 0; long long int i = 1; while (i * 2 <= h && i * 2 <= w) { i *= 2; } ans1 = min((long long int)h, (long long int)(1.25 * i)); ans2 = min((long long int)w, (long long int)(1.25 * i)); if (ans1 >= ans2) cout << ans1 << << i; else cout << i << << ans2; return 0; }
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Thu May 1 14:18:52 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_193MHz/clk_193MHz_funcsim.v
// Design : clk_193MHz
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_193MHz,clk_wiz_v5_1,{component_name=clk_193MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_193MHz
(clk_100MHz,
clk_193MHz,
locked);
input clk_100MHz;
output clk_193MHz;
output locked;
(* IBUF_LOW_PWR *) wire clk_100MHz;
wire clk_193MHz;
wire locked;
clk_193MHzclk_193MHz_clk_wiz U0
(.clk_100MHz(clk_100MHz),
.clk_193MHz(clk_193MHz),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "clk_193MHz_clk_wiz" *)
module clk_193MHzclk_193MHz_clk_wiz
(clk_100MHz,
clk_193MHz,
locked);
input clk_100MHz;
output clk_193MHz;
output locked;
(* IBUF_LOW_PWR *) wire clk_100MHz;
wire clk_100MHz_clk_193MHz;
wire clk_193MHz;
wire clk_193MHz_clk_193MHz;
wire clkfbout_buf_clk_193MHz;
wire clkfbout_clk_193MHz;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_193MHz),
.O(clkfbout_buf_clk_193MHz));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_100MHz),
.O(clk_100MHz_clk_193MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_193MHz_clk_193MHz),
.O(clk_193MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(45.875000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(4.750000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_193MHz),
.CLKFBOUT(clkfbout_clk_193MHz),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_100MHz_clk_193MHz),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_193MHz_clk_193MHz),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; typedef struct edge { int a; int b; int c; }; int n, m; edge roads[10000]; vector<int> out[200]; double matrix[200][200]; double const eps = 1e-10; double val[200]; bool isZero(double r) { return r < eps && r > -eps; } void flip(int r1, int r2) { for (int i = 1; i <= n; i++) { double fill = matrix[r1][i]; matrix[r1][i] = matrix[r2][i]; matrix[r2][i] = fill; } } void scale(int r1, double c) { for (int i = 1; i <= n; i++) { matrix[r1][i] *= c; } } void add(int r1, int r2, double c) { for (int i = 1; i <= n; i++) { matrix[r1][i] += matrix[r2][i] * c; } } void solve_system() { for (int cur = 2; cur <= n - 1; cur++) { int i; for (i = cur; i <= n - 1; i++) { if (!isZero(matrix[i][cur])) { swap(i, cur); break; } } if (i == n) continue; scale(cur, 1 / matrix[cur][cur]); for (int j = cur + 1; j <= n - 1; j++) { if (!isZero(matrix[j][cur])) { add(j, cur, -matrix[j][cur]); } } } for (int cur = n - 1; cur >= 2; cur--) { if (isZero(matrix[cur][cur])) continue; else { val[cur] = -matrix[cur][1]; } for (int j = cur - 1; j >= 2; j--) { add(j, cur, -matrix[j][cur]); } } } void set_up() { for (int i = 0; i < 200; i++) { val[i] = 0; for (int j = 0; j < 200; j++) { matrix[i][j] = 0; } } val[1] = 1; for (int i = 2; i <= n - 1; i++) { matrix[i][i] = out[i].size(); for (int j = 0; j < out[i].size(); j++) { matrix[i][out[i][j]] -= 1; } } } void print_mat() { for (int i = 2; i <= n - 1; i++) { for (int j = 1; j <= n; j++) { printf( %f , matrix[i][j]); } printf( n ); } } int main() { scanf( %d , &n); scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d %d %d , &roads[i].a, &roads[i].b, &roads[i].c); out[roads[i].a].push_back(roads[i].b); out[roads[i].b].push_back(roads[i].a); } set_up(); solve_system(); double scale = 1e10; for (int i = 0; i < m; i++) { double dif = val[roads[i].a] - val[roads[i].b]; if (isZero(dif)) continue; else { scale = min(scale, abs(roads[i].c / dif)); } } double total = 0; for (int i = 0; i < out[1].size(); i++) { total += val[1] - val[out[1][i]]; } printf( %.10f n , total * scale); for (int i = 0; i < m; i++) { double dif = val[roads[i].a] - val[roads[i].b]; printf( %.10f n , scale * dif); } }
|
`timescale 1ns / 1ps
module rx_tb();
reg reset;
wire [7:0] data_out;
wire data_out_enable;
wire data_out_start;
wire data_out_end;
wire error;
reg clock;
reg rx_data_valid;
reg rx_error;
reg [7:0] rx_data;
reg fifo_full;
reg [7:0] packet [0:1518];
integer i;
rx U_rx (
.reset(reset),
.clock(clock),
.rx_data_valid(rx_data_valid),
.rx_data(rx_data),
.rx_error(rx_error),
.data_out(data_out),
.data_out_enable(data_out_enable),
.data_out_start(data_out_start),
.data_out_end(data_out_end),
.fifo_full(fifo_full),
.error(error)
);
initial
begin
$dumpfile("test.vcd");
$dumpvars(0, rx_tb);
end
initial
begin
reset = 1;
clock = 0;
rx_data = 0;
fifo_full = 0;
$readmemh("packet.hex", packet);
#15 reset = 0;
// Send a packet
for(i = 0; i < 104; i = i + 1)
begin
push(packet[i], 1, 0);
end
#100
$finish;
end
always
#2 clock = ~clock;
task push;
input [7:0] data;
input data_valid;
input data_error;
begin
rx_data = data;
rx_data_valid = data_valid;
rx_error = data_error;
@(posedge clock);
#1 rx_data_valid = 0;
rx_error = 0;
$display("Pushed: %x Valid: %b Error: %b",data, data_valid, data_error );
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVP_1_V
`define SKY130_FD_SC_LS__EINVP_1_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvp_1 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvp_1 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_SYMBOL_V
`define SKY130_FD_SC_HVL__NOR3_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, A[100001], Ans[100001]; bool k[100001]; int solve(int x) { if (Ans[x]) return Ans[x]; int tmp = 0, cnt = 0, pre = 1; for (int i = 1; i <= n; i++) { if (!k[A[i]]) { if (cnt == x) { tmp++; cnt = 1; for (int j = pre; j < i; j++) { k[A[j]] = 0; } pre = i; k[A[i]] = 1; } else { cnt++; k[A[i]] = 1; } } } if (cnt) { tmp++; for (int i = pre; i <= n; i++) k[A[i]] = 0; } return Ans[x] = tmp; } void work(int x, int y) { int l = solve(x), r = solve(y); if (l == r) { for (int i = x; i <= y; i++) { Ans[i] = l; } return; } int mid = (x + y) / 2; work(x, mid); work(mid + 1, y); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &A[i]); work(1, n); for (int i = 1; i <= n; i++) printf( %d , Ans[i]); }
|
#include <bits/stdc++.h> using namespace std; long long a[200010]; int main() { long long n, k; cin >> n >> k; n -= k * (k + 1) / 2; if (n < 0) { cout << NO << endl; return 0; } for (int i = 0; i < k; i++) { a[i] = i + 1 + n / k + (i >= (k - n % k)); } bool ok = 1; for (int i = 1; i < k; i++) { if (a[i] > a[i - 1] * 2) { if (i == k - 1) ok = 0; a[k - 1]++; a[i]--; } } if (ok) { cout << YES << endl; for (int i = 0; i < k; i++) cout << a[i] << endl; } else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int NM_MAX = 82; const int U_MAX = 6404; int U; vector<int> edges[U_MAX]; short int C[U_MAX][U_MAX]; short int R[U_MAX][U_MAX]; short int F[U_MAX][U_MAX]; int dist[U_MAX]; int parent[U_MAX]; queue<int> q; bool BellmanFord() { for (int i = 1; i <= U; i++) { dist[i] = INT_MAX; parent[i] = -1; } parent[1] = 0; dist[1] = 0; q.push(1); while (q.empty() == false) { int u = q.front(); q.pop(); for (int v : edges[u]) if (R[u][v] > 0 && dist[u] + C[u][v] < dist[v]) { dist[v] = dist[u] + C[u][v]; parent[v] = u; q.push(v); } } return (parent[U] != -1); } void pushFlow(int u, int v, int flow) { R[u][v] -= flow; R[v][u] += flow; F[u][v] += flow; F[v][u] -= flow; } int minCostMaxFlow() { while (BellmanFord() == true) { int u; u = U; int flow = INT_MAX; while (u != 1) { flow = min(flow, (int)R[parent[u]][u]); u = parent[u]; } u = U; while (u != 1) { pushFlow(parent[u], u, flow); u = parent[u]; } } int ans = 0; for (int i = 1; i <= U; i++) for (int j = 1; j <= U; j++) ans += C[i][j] * F[i][j]; return ans; } int n, m; int ma[NM_MAX][NM_MAX]; int da[] = {-1, 0, 1, 0}, db[] = {0, 1, 0, -1}; bool inside(int a, int b) { return (1 <= a && a <= n && 1 <= b && b <= m); } int codif(int a, int b) { return (a - 1) * m + b + 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> ma[i][j]; U = 1 + n * m + 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) for (int d = 0; d < 4; d++) { int i1 = i + da[d], j1 = j + db[d]; if (inside(i1, j1)) { int u = codif(i, j), v = codif(i1, j1); if ((i + j) & 1) swap(u, v); edges[u].push_back(v); edges[v].push_back(u); C[u][v] = (ma[i][j] != ma[i1][j1]); R[u][v] = 1; F[u][v] = 0; C[v][u] = -(ma[i][j] != ma[i1][j1]); R[v][u] = 0; F[v][u] = 0; } } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if ((i + j) & 1) { int u = codif(i, j); edges[u].push_back(U); edges[U].push_back(u); C[u][U] = 0; R[u][U] = 1; F[u][U] = 0; C[U][u] = 0; R[U][u] = 0; F[U][u] = 0; } else { int u = codif(i, j); edges[1].push_back(u); edges[u].push_back(1); C[1][u] = 0; R[1][u] = 1; F[1][u] = 0; C[u][1] = 0; R[u][1] = 0; F[u][1] = 0; } cout << minCostMaxFlow() / 2 << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_TB_V
`define SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_TB_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 UDP_IN = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 UDP_IN = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 UDP_IN = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 UDP_IN = 1'bx;
end
sky130_fd_sc_hdll__udp_pwrgood_pp$PG dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; scanf( %d , &t); int ji = 0; while (t--) { int n; scanf( %d , &n); int arr[n + 1]; int brr[n + 1]; memset(arr, 0, sizeof(arr)); memset(brr, 0, sizeof(brr)); int ls; int size = 0; for (int a = 0; a < n; a++) { scanf( %d , &ls); if (arr[ls] == 0) { brr[size] = ls; size++; } arr[ls]++; } int min = n; for (int a = 0; a < size; a++) { if (arr[brr[a]] < min) { min = arr[brr[a]]; } } int num = n; int bo = true; for (int a = 2; a < min + 2; a++) { ls = 0; bo = true; for (int b = 0; b < size; b++) { int tt = arr[brr[b]] / a + 1; if (arr[brr[b]] % a == 0) { ls = ls + arr[brr[b]] / a; } else if (arr[brr[b]] >= (tt * (a - 1)) && arr[brr[b]] <= (tt * a)) { ls = ls + tt; } else { bo = false; break; } } if (bo && num > ls) { num = ls; } } printf( %d n , num); } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; signed main() { long long n, k; cin >> n >> k; if (k <= (n + 1) / 2) { cout << 2 * k - 1; } else { cout << 2 * (k - (n + 1) / 2); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR3_2_V
`define SKY130_FD_SC_MS__XOR3_2_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xor3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR3_2_V
|
// megafunction wizard: %LPM_COUNTER%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: four_digit_counter_enable.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module four_bit_counter_enable (
aclr,
clock,
cnt_en,
q);
input aclr;
input clock;
input cnt_en;
output [3:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Direction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "4"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
// Retrieval info: CONNECT: q 0 0 4 0 @q 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL four_digit_counter_enable_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; int min_dist[3005][3005]; vector<int> furthest_out[3005]; vector<pair<int, int> > X; vector<pair<int, int> > furthest_in[3005]; vector<int> E[3005]; int n; void bfs(int source) { for (int j = 1; j <= n; j++) min_dist[source][j] = 1 << 30; min_dist[source][source] = 0; queue<int> Q; Q.push(source); while (!Q.empty()) { int v = Q.front(); Q.pop(); int d = min_dist[source][v]; for (int i = 0; i < E[v].size(); i++) { int to = E[v][i]; if (min_dist[source][to] >= (1 << 30)) { min_dist[source][to] = d + 1; Q.push(to); } } } X.clear(); for (int i = 1; i <= n; i++) { if (i == source) continue; if (min_dist[source][i] >= (1 << 30)) continue; X.push_back(make_pair(min_dist[source][i], i)); furthest_in[i].push_back(make_pair(min_dist[source][i], source)); } sort(X.begin(), X.end()); reverse(X.begin(), X.end()); for (int i = 0; i < X.size() && i < 5; i++) { furthest_out[source].push_back(X[i].second); } } long long v[222222]; int main() { ios::sync_with_stdio(false); cout.tie(0); cin.tie(0); int m; cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; E[u].push_back(v); } for (int i = 1; i <= n; i++) bfs(i); for (int i = 1; i <= n; i++) { sort(furthest_in[i].begin(), furthest_in[i].end()); reverse(furthest_in[i].begin(), furthest_in[i].end()); } long long ans = 0; int x = -1, y = -1, z = -1, dd = -1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (i == j) continue; if (min_dist[i][j] == (1 << 30)) { continue; } for (int k = 0; k < furthest_in[i].size() && k < 6; k++) { int a = furthest_in[i][k].second; if (i == a || j == a) continue; for (int p = 0; p < furthest_out[j].size() && p < 6; p++) { int b = furthest_out[j][p]; if (a == b) continue; if (i == b || j == b) continue; long long cur = min_dist[a][i] + min_dist[i][j] + min_dist[j][b]; if (cur > ans) { ans = cur; x = i; y = j; z = a; dd = b; } } } } } cout << z << << x << << y << << dd << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios::sync_with_stdio(false); int n; cin >> n; int i, j; vector<int> vec1, vec2, vec3; vec1.push_back(0); vec2.push_back(1); vec1.push_back(1); n--; for (j = 0; j < n; j++) { vec3.push_back(0); for (i = 0; i < vec1.size(); i++) { vec3.push_back(vec1[i] % 2); } for (i = 0; i < vec2.size(); i++) { vec3[i] += vec2[i]; vec3[i] %= 2; } vec2.clear(); for (i = 0; i < vec1.size(); i++) { vec2.push_back(vec1[i] % 2); } vec1.clear(); for (i = 0; i < vec3.size(); i++) { vec1.push_back(vec3[i] % 2); } vec3.clear(); } cout << vec1.size() - 1 << endl; for (i = 0; i < vec1.size(); i++) { cout << vec1[i] << ; } cout << endl; cout << vec2.size() - 1 << endl; for (i = 0; i < vec2.size(); i++) { cout << vec2[i] << ; } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// RX_LL
//
//
// Description: The RX_LL module receives data from the Aurora Channel,
// converts it to LocalLink and sends it to the user interface.
//
//
//
`timescale 1 ps / 1 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_RX_LL
(
//AXI4-Stream Interface
m_axi_rx_tdata,
m_axi_rx_tvalid,
m_axi_rx_tkeep,
m_axi_rx_tlast,
// Aurora Lane Interface
RX_PE_DATA,
RX_PE_DATA_V,
RX_SEP,
RX_SEP7,
RX_SEP_NB,
RXDATAVALID_TO_LL,
RX_CC,
RX_IDLE,
// Global Logic
CHANNEL_UP,
// System Interface
USER_CLK,
RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
//AXI4-Stream Interface
output [0:63] m_axi_rx_tdata;
output m_axi_rx_tvalid;
output [0:7] m_axi_rx_tkeep;
output m_axi_rx_tlast;
// Aurora Lane Interface
input [0:63] RX_PE_DATA;
input RX_PE_DATA_V;
input RX_SEP;
input RX_SEP7;
input [0:2] RX_SEP_NB;
input RX_CC;
input RXDATAVALID_TO_LL;
input RX_IDLE;
// Global Logic
input CHANNEL_UP;
// System Interface
input USER_CLK;
input RESET;
//*********************************Main Body of Code**********************************
//____________________________RX LL Datapath _____________________________
aurora_64b66b_25p4G_RX_LL_DATAPATH rx_ll_datapath_i
(
// Aurora lane Interface
.RX_PE_DATA(RX_PE_DATA),
.RX_PE_DATA_V(RX_PE_DATA_V),
.RX_SEP(RX_SEP),
.RX_SEP7(RX_SEP7),
.RX_SEP_NB(RX_SEP_NB),
.RX_CC(RX_CC),
.RXDATAVALID_TO_LL(RXDATAVALID_TO_LL),
.RX_IDLE(RX_IDLE),
//Gobal Interface
.CHANNEL_UP(CHANNEL_UP),
//AXI4-Stream Interface
.m_axi_rx_tdata (m_axi_rx_tdata),
.m_axi_rx_tvalid (m_axi_rx_tvalid),
.m_axi_rx_tkeep (m_axi_rx_tkeep),
.m_axi_rx_tlast (m_axi_rx_tlast),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET)
);
endmodule
|
//-------------------------------------------------------------------------------------------------
// I2S CODEC slave module: The I2S bus is over-sampled using the FPGA clock to allow the logic run
// in the FPGA clock domain. Note FPGA clock must be at least 2x the I2S. Clock to synchronize
// the signals using the FPGA clock and shift registers.
//
// I2S Interface structure: 16 bit interface, Bits are sent in most to least significant order
// command, then address and finally data bits as follows:
//
//
// +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+
// TK| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
// + +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +
//
// + +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ +
// TF| | | |
// +--+ +--+
//
// |<------------------ Left Channel ------------->|<--------------- Right Channel --------------->|
// 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// TD| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
//
//-------------------------------------------------------------------------------------------------
module I2S_slave16 (
input clk, // Main Clock
input FRM, // I2S Framing Input
input BCK, // I2S Sample bit clock input
input DIN, // I2S Serial audio data input
output [15:0] out_L, // Left output
output [15:0] out_R, // Right output
output ready_L, // Signal that data is ready to be sent out
output ready_R // Signal that data is ready to be sent out
);
//-----------------------------------------------------------------------------
// Assign output
//-----------------------------------------------------------------------------
assign out_L = data_L[15:0]; // Left Channel Data bits
assign out_R = data_R[15:0]; // Right Channel Data bits
assign ready_L = FRM_Rise; // Data is ready pulse
assign ready_R = FRM_Fall; // Data is ready pulse
//-----------------------------------------------------------------------------
// Sync BCK to the FPGA clock using a 3-bits shift register
//-----------------------------------------------------------------------------
reg [2:0] FRM_1;
always @(posedge BCK) FRM_1 <= {FRM_1[1:0], FRM};
wire FRM_delayed = FRM_1[1];
//-----------------------------------------------------------------------------
// Sync FRM to the FPGA clock using a 3-bits shift register
//-----------------------------------------------------------------------------
reg [2:0] FRMr;
always @(posedge clk) FRMr <= {FRMr[1:0], FRM_delayed};
wire FRM_Rise = (FRMr[2:1] == 2'b01); // Message starts at rising edge
wire FRM_Fall = (FRMr[2:1] == 2'b10); // Message stops at falling edge
//-----------------------------------------------------------------------------
// I2S receiver:
// This is a 32 bit I2S format, 16 bits data for each channel.
// FPGA is only one slave on the bus so we don't bother with a tri-state buffer
// for MISO otherwise we would need to tri-state MISO when SSEL is inactive
//-----------------------------------------------------------------------------
reg [16:0] data_R; // Shift register of output data
reg [16:0] data_L; // Shift register of output data
always @(posedge BCK) begin
if(FRM_delayed) begin // If Frame not active
data_R <= {data_R[15:0], DIN}; // Input shift-left register
end
else begin
data_L <= {data_L[15:0], DIN}; // Input shift-left register
end
end
//-----------------------------------------------------------------------------
endmodule
//-----------------------------------------------------------------------------
|
module ram0(
// Read port
input rdclk,
input [9:0] rdaddr,
output reg [15:0] do);
(* ram_style = "block" *) reg [15:0] ram[0:1023];
genvar i;
generate
for (i=0; i<1024; i=i+1)
begin
initial begin
ram[i] <= i;
end
end
endgenerate
always @ (posedge rdclk) begin
do <= ram[rdaddr];
end
endmodule
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
reg nrst = 0;
wire tx_baud_edge;
wire rx_baud_edge;
// Data in.
wire [7:0] rx_data_wire;
wire rx_data_ready_wire;
// Data out.
wire tx_data_ready;
wire tx_data_accepted;
wire [7:0] tx_data;
assign led[14:0] = sw[14:0];
assign led[15] = rx_data_ready_wire ^ sw[15];
UART #(
.COUNTER(25),
.OVERSAMPLE(8)
) uart (
.clk(clk),
.rst(!nrst),
.rx(rx),
.tx(tx),
.tx_data_ready(tx_data_ready),
.tx_data(tx_data),
.tx_data_accepted(tx_data_accepted),
.rx_data(rx_data_wire),
.rx_data_ready(rx_data_ready_wire)
);
wire [9:0] read_address;
wire [15:0] read_data;
wire [9:0] rom_read_address;
reg [15:0] rom_read_data;
always @(posedge clk) begin
rom_read_data[9:0] <= rom_read_address;
rom_read_data[15:10] <= 1'b0;
end
wire loop_complete;
wire error_detected;
wire [7:0] error_state;
wire [9:0] error_address;
wire [15:0] expected_data;
wire [15:0] actual_data;
ROM_TEST #(
.ADDR_WIDTH(10),
.DATA_WIDTH(16),
.ADDRESS_STEP(1),
.MAX_ADDRESS(1023)
) dram_test (
.rst(!nrst),
.clk(clk),
// Memory connection
.read_data(read_data),
.read_address(read_address),
// INIT ROM connection
.rom_read_data(rom_read_data),
.rom_read_address(rom_read_address),
// Reporting
.loop_complete(loop_complete),
.error(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data)
);
ram0 #(
) bram (
// Read port
.rdclk(clk),
.rdaddr(read_address),
.do(read_data)
);
ERROR_OUTPUT_LOGIC #(
.DATA_WIDTH(16),
.ADDR_WIDTH(10)
) output_logic (
.clk(clk),
.rst(!nrst),
.loop_complete(loop_complete),
.error_detected(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data),
.tx_data(tx_data),
.tx_data_ready(tx_data_ready),
.tx_data_accepted(tx_data_accepted)
);
always @(posedge clk) begin
nrst <= 1;
end
endmodule
|
#include <bits/stdc++.h> struct Edge { int u, v, next; } edge[100000]; int head[105], num[105]; bool visited[105]; int en, cnt, tt; void add_edge(int u, int v) { edge[en].u = u; edge[en].v = v; edge[en].next = head[u]; head[u] = en++; } void DFS1(int u) { int v; visited[u] = true; for (int id = head[u]; id != -1; id = edge[id].next) { v = edge[id].v; if (!visited[v]) DFS1(v); } } void DFS2(int u, int p) { int v; num[u] = tt++; visited[u] = true; for (int id = head[u]; id != -1; id = edge[id].next) { v = edge[id].v; if (v == p) continue; if (!visited[v]) DFS2(v, u); else if (num[v] < num[u]) cnt++; } } int main() { int n, m, u, v; en = 0; memset(head, 0xff, sizeof head); scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d%d , &u, &v); add_edge(u, v); add_edge(v, u); } memset(visited, false, sizeof visited); DFS1(1); cnt = 0; for (int i = 1; i <= n; i++) if (!visited[i]) cnt++; if (cnt) puts( NO ); else { memset(visited, false, sizeof visited); cnt = tt = 0; DFS2(1, -1); if (cnt == 1) puts( FHTAGN! ); else puts( NO ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct wektor { int roz; int *tab; int roztab; wektor() { tab = new int[1]; roz = 0; roztab = 1; } ~wektor() { delete[] tab; } int size() { return roz; } bool empty() { return roz == 0; } void pop_back() { roz--; } int &operator[](int ind) { return tab[ind]; } int operator[](int ind) const { return tab[ind]; } int back() { return tab[roz - 1]; } void resize(int cos) { if (cos > roztab) { int *tmp; tmp = new int[2 * cos]; for (int i = 0; i < roz; i++) { tmp[i] = tab[i]; } delete[] tab; tab = tmp; roztab = 2 * cos; } else { if (cos < roz) { roz = cos; } } } void push_back(int elem) { resize(roz + 1); tab[roz] = elem; roz = roz + 1; ; } }; wektor slo[100005]; int vis[100005]; int gleb[100005]; double wynik; void dfs(int v, int g) { wynik += double(1) / g; vis[v] = 1; for (int i = 0; i < slo[v].size(); i++) { int aktv = slo[v][i]; if (vis[aktv] == 0) { dfs(aktv, g + 1); } } } int main() { int n; cin >> n; for (int i = 1; i <= n - 1; i++) { int a, b; cin >> a >> b; slo[a].push_back(b); slo[b].push_back(a); } dfs(1, 1); printf( %.7lf n , wynik); return 0; }
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#include <bits/stdc++.h> using namespace std; const long double eps = 1e-10; struct Tpoint { long double x, y; void input() { double _x, _y; scanf( %lf%lf , &_x, &_y); x = _x; y = _y; } } C, H, S; double t1, t2; long double T1, T2; long double ret; long double Fabs(long double x) { return x < 0 ? -x : x; } long double Fmin(long double x, long double y) { return x < y ? x : y; } long double Fmax(long double x, long double y) { return x > y ? x : y; } long double dist2(Tpoint a, Tpoint b) { return (a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y); } long double dist(Tpoint a, Tpoint b) { return sqrt(Fabs(dist2(a, b))); } void init() { scanf( %lf%lf , &t1, &t2); C.input(); H.input(); S.input(); } bool Inside(Tpoint A, long double r, Tpoint p) { return dist2(A, p) < r * r + eps; } bool inter(Tpoint A, Tpoint B, long double ra, long double rb) { return dist(A, B) < ra + rb + eps; } void Normalize(long double &x) { if (x > 1.0) x = 1.0; if (x < -1.0) x = -1.0; } bool inter(Tpoint A, Tpoint B, Tpoint C, long double ra, long double rb, long double rc) { if (dist(A, B) < Fabs(ra - rb) + eps) return 1; long double alpha = atan2(B.y - A.y, B.x - A.x); long double dis2 = dist2(A, B); long double cosine = (ra * ra + dis2 - rb * rb) / (2.0 * ra * sqrt(Fabs(dis2))); Normalize(cosine); long double beta = acos(cosine); Tpoint p; p.x = A.x + ra * cos(alpha + beta); p.y = A.y + ra * sin(alpha + beta); if (Inside(C, rc, p)) return 1; p.x = A.x + ra * cos(alpha - beta); p.y = A.y + ra * sin(alpha - beta); if (Inside(C, rc, p)) return 1; return 0; } bool check(long double cur) { long double rc = cur, rh = Fmax(0, T2 - cur), rs = Fmax(0, T1 - cur - dist(S, H)); if (!inter(C, H, rc, rh) || !inter(C, S, rc, rs) || !inter(H, S, rh, rs)) return 0; if (inter(C, H, S, rc, rh, rs)) return 1; if (inter(C, S, H, rc, rs, rh)) return 1; if (inter(H, S, C, rh, rs, rc)) return 1; return 0; } long double solve() { T1 = dist(C, S) + dist(S, H) + t1; T2 = dist(C, H) + t2; if (T1 - t1 < T2 + eps) return Fmin(T1, T2); long double L = 0, r = Fmin(T1, T2); for (int it = 0; it < 100; it++) { long double mid = (L + r) / 2; if (check(mid)) L = mid; else r = mid; } return L; } void print() { printf( %.10lf n , (double)solve()); } int main() { init(); print(); return 0; }
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//#############################################################################
//# Purpose: DMA registers #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see below) #
//#############################################################################
`include "edma_regmap.vh"
module edma_regs (/*AUTOARG*/
// Outputs
reg_wait_out, reg_access_out, reg_packet_out, dma_en, mastermode,
manualmode, datamode, ctrlmode, chainmode, irq, next_descr,
curr_descr, stride_reg, count_reg, dstaddr_reg, srcaddr_reg,
// Inputs
clk, nreset, reg_access_in, reg_packet_in, reg_wait_in,
fetch_access, fetch_packet, count, dstaddr, srcaddr, dma_state,
update
);
// parameters
parameter AW = 8; // address width
parameter PW = 2*AW+40; // emesh packet width
parameter DEF_CFG = 0; // default config after reset
// clk, reset
input clk; // main clock
input nreset; // async active low reset
// config interface
input reg_access_in; // config register access
input [PW-1:0] reg_packet_in; // config register packet
output reg_wait_out; // pushback by register read
output reg_access_out; // config readback
output [PW-1:0] reg_packet_out; // config reacback packet
input reg_wait_in; // pushback for readback
// descriptor fetch interface
input fetch_access; // fetch descriptor
input [PW-1:0] fetch_packet; // fetch packet (mux with readback)
// config outputs
output dma_en; // enable dma
output mastermode; // dma in master mode
output manualmode; // 0=fetch descriptor, 1=assume config ready
output [1:0] datamode; // transfer size (8,16,32,64 bits)
output [4:0] ctrlmode; // ctrlmode
output chainmode; // auto wrap around
output irq; // interrupt output
output [15:0] next_descr; // pointer to next descriptor
output [15:0] curr_descr; // pointer to current descriptor
// datapath regs
output [31:0] stride_reg; // stride
output [31:0] count_reg; // register transfer count
output [63:0] dstaddr_reg; // register destination address
output [63:0] srcaddr_reg; // register source address
// datapath inputs
input [31:0] count; // current count
input [AW-1:0] dstaddr; // current destination address
input [AW-1:0] srcaddr; // current source address
// status
input [3:0] dma_state; // dma sequencer state
input update; // update registers
//######################################################################
//# BODY
//######################################################################
// regs
reg [31:0] config_reg;
reg [31:0] count_reg;
reg [31:0] stride_reg;
reg [63:0] dstaddr_reg;
reg [63:0] srcaddr_reg;
reg [31:0] status_reg;
// wires
wire reg_write;
wire config_write;
wire stride_write;
wire count_write;
wire srcaddr0_write;
wire srcaddr1_write;
wire dstaddr0_write;
wire dstaddr1_write;
wire status_write;
wire irqmode;
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
wire [AW-1:0] data_in; // From p2e of packet2emesh.v
wire [1:0] datamode_in; // From p2e of packet2emesh.v
wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
wire write_in; // From p2e of packet2emesh.v
// End of automatics
//################################
//# DECODE
//################################
packet2emesh #(.AW(AW),
.PW(PW))
p2e (.packet_in (reg_packet_in[PW-1:0]),
/*AUTOINST*/
// Outputs
.write_in (write_in),
.datamode_in (datamode_in[1:0]),
.ctrlmode_in (ctrlmode_in[4:0]),
.dstaddr_in (dstaddr_in[AW-1:0]),
.srcaddr_in (srcaddr_in[AW-1:0]),
.data_in (data_in[AW-1:0]));
assign reg_write = write_in & reg_access_in;
assign config_write = reg_write & (dstaddr_in[6:2]==`EDMA_CONFIG);
assign stride_write = reg_write & (dstaddr_in[6:2]==`EDMA_STRIDE);
assign count_write = reg_write & (dstaddr_in[6:2]==`EDMA_COUNT);
assign srcaddr0_write = reg_write & (dstaddr_in[6:2]==`EDMA_SRCADDR);
assign srcaddr1_write = reg_write & (dstaddr_in[6:2]==`EDMA_SRCADDR64);
assign dstaddr0_write = reg_write & (dstaddr_in[6:2]==`EDMA_DSTADDR);
assign dstaddr1_write = reg_write & (dstaddr_in[6:2]==`EDMA_DSTADDR64);
assign status_write = reg_write & (dstaddr_in[6:2]==`EDMA_STATUS);
//################################
//# CONFIG
//################################
always @ (posedge clk or negedge nreset)
if(!nreset)
config_reg[31:0] <= DEF_CFG;
else if(config_write)
config_reg[31:0] <= data_in[31:0];
assign dma_en = config_reg[0]; // dma enabled
assign mastermode = config_reg[1]; // dma in master mode
assign chainmode = config_reg[2]; // autostart when done
assign manualmode = ~config_reg[3]; // fetch descriptor if=1
assign irqmode = config_reg[4]; // enable irq at end of transfer
assign datamode[1:0] = config_reg[6:5]; // datamode (8/16/32/64 bits)
assign ctrlmode[4:0] = 5'b0; // bits 10-11 reserved
assign next_descr[15:0] = config_reg[31:16];// pointer to fetch descriptor
//################################
//# STRIDE
//################################
always @ (posedge clk)
if(stride_write)
stride_reg[31:0] <= data_in[31:0];
//################################
//# COUNT
//################################
always @ (posedge clk)
if(count_write)
count_reg[31:0] <= data_in[31:0];
else if (update)
count_reg[31:0] <= count[31:0];
//################################
//# SRCADDR
//################################
always @ (posedge clk)
if(srcaddr0_write)
srcaddr_reg[31:0] <= data_in[31:0];
else if(srcaddr1_write)
srcaddr_reg[63:32] <= data_in[31:0];
else if (update)
srcaddr_reg[AW-1:0] <= srcaddr[AW-1:0];
//################################
//# DSTADDR
//################################
always @ (posedge clk)
if(dstaddr0_write)
dstaddr_reg[31:0] <= data_in[31:0];
else if(dstaddr1_write)
dstaddr_reg[63:32] <= data_in[31:0];
else if (update)
dstaddr_reg[AW-1:0] <= dstaddr[AW-1:0];
//################################
//# STATUS
//################################
always @ (posedge clk)
if(status_write)
status_reg[31:0] <= data_in[31:0];
else if (config_write)
status_reg[31:0] <= {next_descr[15:0],
12'b0,
dma_state[3:0]};
assign curr_descr[15:0] = status_reg[31:16];
//################################
//# READBACK CIRCUIT
//################################
//TODO: no readback for now
assign reg_wait_out = 1'b0 ;
assign reg_access_out = fetch_access;
assign reg_packet_out[PW-1:0] = fetch_packet[PW-1:0];
//################################
//# READBACK CIRCUIT
//################################
assign irq = 1'b0;
endmodule // edma_regs
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
///////////////////////////////////////////////////////////////////////////////
// The MIT License (MIT) //
// //
// Copyright (c) 2015-2016, Adapteva, Inc. //
// //
// Permission is hereby granted, free of charge, to any person obtaining a //
// copy of this software and associated documentation files (the "Software") //
// to deal in the Software without restriction, including without limitation //
// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
// and/or sell copies of the Software, and to permit persons to whom the //
// Software is furnished to do so, subject to the following conditions: //
// //
// The above copyright notice and this permission notice shall be included //
// in all copies or substantial portions of the Software. //
// //
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
// //
///////////////////////////////////////////////////////////////////////////////
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#include <bits/stdc++.h> using namespace std; const int MAXN = 4000010; long long f[MAXN], sum[MAXN], MOD; int main() { int n; scanf( %d %lld , &n, &MOD); f[n] = 1; sum[n] = 1; for (int i = n - 1; i; --i) { f[i] = (f[i] + sum[i + 1]) % MOD; for (int j = 2; j * i <= n; ++j) { int l = j * i, r = min(n, i * j + j - 1); f[i] += sum[l] - sum[r + 1]; f[i] = (f[i] % MOD + MOD) % MOD; } sum[i] = (sum[i + 1] + f[i]) % MOD; } printf( %lld n , f[1]); return 0; }
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#include <bits/stdc++.h> using namespace std; char s[12000]; int n, i, j; vector<int> ans; int cek(int v, int t, string e) { if (v >= strlen(s) - 1) return v; int i = v; do { string tmp = ; for (i = i;; i++) { tmp.push_back(s[i]); if (s[i] == > ) break; } i++; if (e == <table> && tmp == </table> ) break; if (e == <tr> && tmp == </tr> ) break; if (e == <td> && tmp == </td> ) { ans[t]++; break; } if (tmp == <table> ) { ans.push_back(0); i = cek(i, ans.size() - 1, tmp); } else if (tmp == <tr> ) { i = cek(i, t, tmp); } else if (tmp == <td> ) { i = cek(i, t, tmp); } } while (i < strlen(s)); return i; } int main() { n = 0; bool f = 1; while (scanf( %c , &s[n]) != EOF) { if (s[n] != n ) n++; } int k = cek(0, -1, ); sort(ans.begin(), ans.end()); for (i = 0; i < ans.size(); i++) { if (f) f = 0; else printf( ); cout << ans[i]; } cout << endl; return 0; }
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//-------------------------------------------------------------------
//-- counter_tb.v
//-- Banco de pruebas para el contador
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
module counter_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Datos de salida del contador
wire [25:0] data;
//-- Registro para comprobar si el contador cuenta correctamente
reg [25:0] counter_check = 1;
//-- Instanciar el contador
counter C1(
.clk(clk),
.data(data)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
//-- Comprobacion del valor del contador
//-- En cada flanco de bajada se comprueba la salida del contador
//-- y se incrementa el valor esperado
always @(negedge clk) begin
if (counter_check != data)
$display("-->ERROR!. Esperado: %d. Leido: %d",counter_check, data);
counter_check <= counter_check + 1;
end
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("counter_tb.vcd");
$dumpvars(0, counter_tb);
//-- Comprobación del reset.
# 0.5 if (data != 0)
$display("ERROR! Contador NO está a 0!");
else
$display("Contador inicializado. OK.");
# 99 $display("FIN de la simulacion");
# 100 $finish;
end
endmodule
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//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_alu_carry_out (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n], b[n], c = 0, d = 0, e = 0, i; for (i = 0; i < n; i++) { cin >> a[i] >> b[i]; if (a[i] > b[i]) c++; else if (b[i] > a[i]) d++; else e++; } if (c > d) cout << Mishka << endl; else if (d > c) cout << Chris << endl; else cout << Friendship is magic!^^ << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { double v1, v2, s1, s2, t, f, c; double m; int co; while (cin >> v1 >> v2 >> t >> f >> c) { if (v2 <= v1) cout << 0 << endl; else { s1 = t * v1; s2 = 0; m = v2 - v1; co = 0; while (s1 < c) { s1 += (s1 / m) * v1; if (s1 >= c) break; co++; s1 += (s1 / v2 + f) * v1; } cout << co << endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; void solve() { string S; cin >> S; int M; cin >> M; for (int i = 0; i < M; i++) { int l, r, k; cin >> l >> r >> k; l--; rotate(S.begin() + l, S.begin() + r - k % (r - l), S.begin() + r); } cout << S << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) solve(); return 0; }
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#include <bits/stdc++.h> int next[1 + (1000 * (1000 - 1)) * 2], hh[1 + (1000 * (1000 - 1)) * 2], l_; int link(int l, int h) { next[l_] = l; hh[l_] = h; return l_++; } int ij[(1000 * (1000 - 1))], ww[(1000 * (1000 - 1))], ao[1000]; long long ww_[1000][1000]; int pq[1 + 1000], iq[1000], cnt; long long *dd; int less(int u, int v) { return dd[u] < dd[v]; } int i2(int i) { return (i *= 2) > cnt ? 0 : i < cnt && less(pq[i + 1], pq[i]) ? i + 1 : i; } void pq_up(int u) { int i, j, v; for (i = iq[u]; (j = i / 2) && less(u, v = pq[j]); i = j) pq[iq[v] = i] = v; pq[iq[u] = i] = u; } void pq_dn(int u) { int i, j, v; for (i = iq[u]; (j = i2(i)) && less(v = pq[j], u); i = j) pq[iq[v] = i] = v; pq[iq[u] = i] = u; } void pq_add_last(int u) { iq[u] = ++cnt; } int pq_remove_first() { int u = pq[1], v = pq[cnt--]; iq[v] = 1; pq_dn(v); return u; } void dijkstra(int s, int n) { int h, i, j, l, w; memset(dd, 0x3f, n * sizeof *dd), dd[s] = 0; pq_add_last(s), pq_up(s); while (cnt) { i = pq_remove_first(); for (l = ao[i]; l; l = next[l]) { h = hh[l]; j = i ^ ij[h]; w = ww[h]; if (dd[j] > dd[i] + w) { if (dd[j] == 0x3f3f3f3f3f3f3f3fLL) pq_add_last(j); dd[j] = dd[i] + w; pq_up(j); } } } } int main() { int n, m, s, t, h, i, j, w, d, c; scanf( %d%d%d%d , &n, &m, &s, &t), s--, t--; l_ = 1; for (h = 0; h < m; h++) { scanf( %d%d%d , &i, &j, &w), i--, j--; ij[h] = i ^ j; ww[h] = w; ao[i] = link(ao[i], h); ao[j] = link(ao[j], h); } for (i = 0; i < n; i++) { dd = ww_[i]; dijkstra(i, n); } l_ = 1; m = 0; for (i = 0; i < n; i++) { scanf( %d%d , &d, &c); dd = ww_[i]; ao[i] = 0; for (j = 0; j < n; j++) if (j != i && dd[j] <= d) { ij[m] = i ^ j; ww[m] = c; ao[i] = link(ao[i], m++); } } dijkstra(s, n); printf( %lld n , dd[t] == 0x3f3f3f3f3f3f3f3fLL ? -1 : dd[t]); return 0; }
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#include <bits/stdc++.h> using namespace std; signed main() { long long n; cin >> n; n /= 2; vector<long long> x(n); for (long long i = 0; i < n; ++i) { cin >> x[i]; } vector<vector<pair<long long, long long>>> as(n); for (long long i = 0; i < n; ++i) { for (long long a = 1; a * a < x[i]; ++a) { if (x[i] % a) { continue; } long long b = x[i] / a; if ((b + a) % 2) { continue; } as[i].emplace_back((b - a) / 2, (b + a) / 2); } reverse(as[i].begin(), as[i].end()); } vector<long long> y(n); long long last = 0; for (long long i = 0; i < n; ++i) { pair<long long, long long> tf = {last, 0}; long long j = lower_bound(as[i].begin(), as[i].end(), tf) - as[i].begin(); if (j >= as[i].size()) { cout << No ; return 0; } tf = as[i][j]; y[i] = tf.first * tf.first - last * last; last = tf.second; } for (long long i = 0; i < n; ++i) { if (y[i] < 1) { cout << No ; return 0; } } cout << Yes << n ; for (long long i = 0; i < n; ++i) { cout << y[i] << << x[i] << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<long long int> odds; int main() { int n; scanf( %d , &n); long long int sum = 0; int length_odds = 0; for (int x = 0; x < n; x++) { long long int num; scanf( %lld , &num); if (num % 2 == 0) { sum += num; } else { odds.push_back(num); length_odds++; } } sort(odds.begin(), odds.end()); reverse(odds.begin(), odds.end()); for (int x = 1; x < length_odds;) { sum += odds[0] + odds[1]; odds.erase(odds.begin()); odds.erase(odds.begin()); x += 2; } printf( %lld , sum); return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> inline void chkmin(T1 &x, T2 y) { if (x > y) x = y; } template <typename T1, typename T2> inline void chkmax(T1 &x, T2 y) { if (x < y) x = y; } template <typename T, typename U> inline ostream &operator<<(ostream &_out, const pair<T, U> &_p) { _out << _p.first << << _p.second; return _out; } template <typename T, typename U> inline istream &operator>>(istream &_in, pair<T, U> &_p) { _in >> _p.first >> _p.second; return _in; } template <typename T> inline ostream &operator<<(ostream &_out, const vector<T> &_v) { if (_v.empty()) { return _out; } _out << _v.front(); for (auto _it = ++_v.begin(); _it != _v.end(); ++_it) { _out << << *_it; } return _out; } template <typename T> inline istream &operator>>(istream &_in, vector<T> &_v) { for (auto &_i : _v) { _in >> _i; } return _in; } template <typename T> inline ostream &operator<<(ostream &_out, const set<T> &_s) { if (_s.empty()) { return _out; } _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) { _out << << *_it; } return _out; } template <typename T> inline ostream &operator<<(ostream &_out, const multiset<T> &_s) { if (_s.empty()) { return _out; } _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) { _out << << *_it; } return _out; } template <typename T> inline ostream &operator<<(ostream &_out, const unordered_set<T> &_s) { if (_s.empty()) { return _out; } _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) { _out << << *_it; } return _out; } template <typename T> inline ostream &operator<<(ostream &_out, const unordered_multiset<T> &_s) { if (_s.empty()) { return _out; } _out << *_s.begin(); for (auto _it = ++_s.begin(); _it != _s.end(); ++_it) { _out << << *_it; } return _out; } template <typename T, typename U> inline ostream &operator<<(ostream &_out, const map<T, U> &_m) { if (_m.empty()) { return _out; } _out << ( << _m.begin()->first << : << _m.begin()->second << ) ; for (auto _it = ++_m.begin(); _it != _m.end(); ++_it) { _out << , ( << _it->first << : << _it->second << ) ; } return _out; } template <typename T, typename U> inline ostream &operator<<(ostream &_out, const unordered_map<T, U> &_m) { if (_m.empty()) { return _out; } _out << ( << _m.begin()->first << : << _m.begin()->second << ) ; for (auto _it = ++_m.begin(); _it != _m.end(); ++_it) { _out << , ( << _it->first << : << _it->second << ) ; } return _out; } const string FILENAME = input ; const int MAXN = 100001; int n; int x[MAXN], y[MAXN]; int c[MAXN]; int a[MAXN]; int id[MAXN]; int reals[MAXN]; int xs[MAXN], ys[MAXN]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; int curx = 0, cury = 0; int last = 0; int st = 0; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i]; id[i] = i; xs[i] = x[i]; ys[i] = y[i]; } while (true) { random_shuffle(id, id + n); for (int i = 0; i < n; i++) { x[i] = xs[i]; y[i] = ys[i]; } long long lst = 0; curx = 0; cury = 0; last = 0; st = 0; for (int i1 = 0; i1 < n; i1++) { int i = id[i1]; long long res = 1e18; for (int t = 0; t < 2; t++) { for (int t1 = 0; t1 < 2; t1++) { int nx = curx + x[i]; int ny = cury + y[i]; chkmin(res, 1LL * nx * nx + 1LL * ny * ny); x[i] *= -1; y[i] *= -1; } curx *= -1; cury *= -1; } bool was = false; for (int t = 0; t < 2; t++) { int nx = curx + x[i]; int ny = cury + y[i]; if ((1LL * nx * nx + 1LL * ny * ny) == res) { c[i1] = last ^ t; if (i == 0) { st = t; } was = true; curx = nx; cury = ny; last = t; break; } x[i] *= -1; y[i] *= -1; } if (!was) { st ^= 1; last ^= 1; curx *= -1; cury *= -1; for (int t = 0; t < 2; t++) { int nx = curx + x[i]; int ny = cury + y[i]; if ((1LL * nx * nx + 1LL * ny * ny) == res) { c[i1] = t ^ last; if (i == 0) { st = t; } was = true; curx = nx; cury = ny; last = t; break; } x[i] *= -1; y[i] *= -1; } } lst = res; } if (lst <= 1500000LL * 1500000LL) { break; } } for (int i = 0; i < n; i++) { if (i == 0) { a[i] = st; } else { if (c[i]) { a[i] = a[i - 1] ^ 1; } else { a[i] = a[i - 1]; } } reals[id[i]] = a[i]; } for (int i = 0; i < n; i++) { if (reals[i] == 0) { cout << 1 << ; } else { cout << -1 << ; } } cout << n ; return 0; }
|
#include <bits/stdc++.h> const int N = 3200; using namespace std; int n, l; int a[N][3], b[N][3]; int dp[N][105][3]; void add(int &a, int &b) { a += b; if (a >= 1000000007) a -= 1000000007; } int main() { ios_base::sync_with_stdio(0); cin >> n >> l; for (int i = 1; i <= n; i++) { cin >> a[i][0] >> b[i][0]; a[i][1] = b[i][0]; b[i][1] = a[i][0]; } for (int i = 1; i <= n; i++) { dp[a[i][0]][i][0] += 1; if (a[i][0] != b[i][0]) dp[b[i][0]][i][1] += 1; } for (int i = 1; i <= l; i++) { for (int cur = 1; cur <= n; cur++) { for (int rot1 = 0; rot1 <= 1; rot1++) { for (int to = 1; to <= n; to++) { if (to != cur) for (int rot2 = 0; rot2 <= 1; rot2++) { if (a[to][0] == b[to][0] && rot2 == 1) continue; if (b[cur][rot1] == a[to][rot2]) add(dp[i + a[to][rot2]][to][rot2], dp[i][cur][rot1]); } } } } } int ans = 0; for (int i = 1; i <= n; i++) { for (int j = 0; j <= 1; j++) { add(ans, dp[l][i][j]); } } cout << ans << endl; cin.get(); cin.get(); return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Mon Oct 24 10:52:44 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.1 2005/10/25 13:15:36 wig Exp $
// $Date: 2005/10/25 13:15:36 $
// $Log: ent_ab.v,v $
// Revision 1.1 2005/10/25 13:15:36 wig
// Testcase result update
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.38 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No `defines in this module
module ent_ab
//
// Generated module inst_ab
//
(
input wire port_ab_1, // Use internally test1
output wire port_ab_2, // Use internally test2, no port generated
input wire [4:0] sig_13, // Create internal signal name
input wire [6:0] sig_14 // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int maxdp[27]; int dp[N]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; string str; cin >> n >> str; for (int i = 0; i < n; ++i) { for (int c = 26; c > str[i] - a ; --c) maxdp[str[i] - a ] = max(maxdp[c] + 1, maxdp[str[i] - a ]); dp[i] = maxdp[str[i] - a ]; } cout << *max_element(dp, dp + n) << endl; for (int i = 0; i < n; ++i) { cout << dp[i] << ; } return 0; }
|
`timescale 1 ps / 1 ps
module mux_2_to_1
(
input sel_i,
input [1:0] dat_i,
output dat_o
);
assign dat_o = sel_i && dat_i[1] || ~sel_i && dat_i[0];
endmodule
module mux_n_to_1
#(
parameter sel_w = 4,
parameter n_inputs = 2**sel_w
)
(
input [n_inputs-1:0] inputs_i,
input [sel_w-1:0] sel_i,
output output_o
);
genvar i,j;
generate
if(sel_w == 1) begin
mux_2_to_1 mux_simple
(
.sel_i(sel_i),
.dat_i(inputs_i),
.dat_o(output_o)
);
end else begin
wire [n_inputs-2:0] inter_w;
for(i=0; i<sel_w; i=i+1) begin : SELECT_STAGE
if(i==0) begin
for(j=0; j<n_inputs/2; j=j+1) begin : FIRST_STAGE
mux_2_to_1 mux_first_stage
(
.sel_i(sel_i[i]),
.dat_i(inputs_i[2*j+1:2*j]),
.dat_o(inter_w[j])
);
end
end else begin
for(j=0; j<(n_inputs/(2**(i+1))); j=j+1) begin : INTERMEDIARY_STAGE
mux_2_to_1 mux_intermediary_stages
(
.sel_i(sel_i[i]),
.dat_i(inter_w[ (n_inputs/(2**(i-1)))*((2**(i-1))-1) + 2*j + 1 : (n_inputs/(2**(i-1)))*((2**(i-1))-1) + 2*j ]),
.dat_o(inter_w[ (n_inputs/(2**i))*((2**i)-1) + j ])
);
end
end
end
assign output_o = inter_w[ (n_inputs/(2**(sel_w-1)))*((2**(sel_w-1))-1) ];
end
endgenerate
endmodule
module top;
parameter sel_wid = 3;
parameter num_inputs = 2**sel_wid;
reg [num_inputs-1:0] in;
reg [sel_wid-1:0] sel;
wire out;
integer lp;
reg pass;
mux_n_to_1
#(
.sel_w(sel_wid),
.n_inputs(num_inputs)
)
dut
(
.inputs_i(in),
.sel_i(sel),
.output_o(out)
);
initial begin
pass = 1'b1;
for (lp = 0; lp < num_inputs; lp = lp + 1) begin
sel = lp;
in = 2**lp;
$display("Checking input %0d;", sel);
#1;
if (out !== 1'b1) begin
$display(" Failed input high (%b), got %b", in, out);
pass = 1'b0;
end
in = ~in;
#1;
if (out !== 1'b0) begin
$display(" Failed input low (%b), got %b", in, out);
pass = 1'b0;
end
end
if (pass) $display("PASSED");
end
endmodule
|
module muladd_wrap (
input ck,
input rst,
input [63:0] i_a, i_b, i_c, //a + b * c
input i_vld,
output o_rdy,
output [63:0] o_res,
output o_vld
);
parameter ENTRY_DEPTH = 32;
wire ef_afull;
wire ef_pop;
wire ef_empty;
wire [63:0] ef_a, ef_b, ef_c;
fifo #(
.WIDTH(64+64+64),
.DEPTH(ENTRY_DEPTH),
.PIPE(1),
.AFULLCNT(ENTRY_DEPTH - 2)
) entry_fifo (
.clk(ck),
.reset(rst),
.push(i_vld),
.din({i_a, i_b, i_c}),
.afull(ef_afull),
.oclk(ck),
.pop(ef_pop),
.dout({ef_a, ef_b, ef_c}),
.empty(ef_empty)
);
wire mult_rdy;
wire [63:0] mult_res;
wire mult_vld;
assign ef_pop = !ef_empty & mult_rdy;
// Black box instantiation
mul_64b_dp multiplier (.clk(ck), .a(ef_b), .b(ef_c), .operation_nd(ef_pop), .operation_rfd(mult_rdy), .result(mult_res), .rdy(mult_vld));
reg [63:0] r_t2_a, r_t3_a, r_t4_a, r_t5_a, r_t6_a, r_t7_a;
// The following example uses a fixed-length pipeline,
// but could be used with any length or a variable length pipeline.
always @(posedge ck) begin
if (ef_pop) begin
r_t2_a <= ef_a;
end else begin
r_t2_a <= r_t2_a;
end
r_t3_a <= r_t2_a;
r_t4_a <= r_t3_a;
r_t5_a <= r_t4_a;
r_t6_a <= r_t5_a;
r_t7_a <= r_t6_a;
end
parameter MID_DEPTH = 32;
wire mf_afull;
wire mf_pop;
wire mf_empty;
wire [63:0] mf_a, mf_bc;
fifo #(
.WIDTH(64+64),
.DEPTH(MID_DEPTH),
.PIPE(1),
.AFULLCNT(MID_DEPTH - 2)
) mid_fifo (
.clk(ck),
.reset(rst),
.push(mult_vld),
.din({r_t7_a, mult_res}),
.afull(mf_afull),
.oclk(ck),
.pop(mf_pop),
.dout({mf_a, mf_bc}),
.empty(mf_empty)
);
wire add_rdy;
wire [63:0] add_res;
wire add_vld;
assign mf_pop = !mf_empty & add_rdy;
// Black box instantiation
add_64b_dp adder (.clk(ck), .a(mf_a), .b(mf_bc), .operation_nd(mf_pop), .operation_rfd(add_rdy), .result(add_res), .rdy(add_vld));
// Outputs
assign o_rdy = !ef_afull;
assign o_res = add_res;
assign o_vld = add_vld;
endmodule
|
#include <bits/stdc++.h> int ways[37 * 2 + 1][37 * 2 + 1], k; void init() { int i, j; ways[0][0] = 1; for (i = 0; i <= k * 2; i++) for (j = 0; j <= k * 2; j++) ways[i][j] = i == 0 || j == 0 ? 1 : (ways[i - 1][j] + ways[i][j - 1]) % 998244353; } int oo[1 + (4000 - 1) * 4], oj[1 + (4000 - 1) * 4]; int link(int o, int j) { static int _ = 1; oo[_] = o, oj[_] = j; return _++; } int *ae, *xx, dp[4000][37 + 1], dq[4000][37 + 1]; void dfs(int p, int i) { int o, l, c; memset(dq[i], 0, (k + 1) * sizeof *dq[i]); for (o = ae[i]; o; o = oo[o]) { int j = oj[o]; if (j != p) { dfs(i, j); for (l = 0; l <= k; l++) dq[i][l] = (dq[i][l] + dp[j][l]) % 998244353; } } xx[0] = (xx[0] + 1) % 998244353; memset(dp[i], 0, (k + 1) * sizeof *dp[i]), dp[i][0] = 1; for (l = 1; l <= k; l++) for (c = 1; c <= l; c++) { int x = (long long)dq[i][c - 1] * dp[i][l - c] % 998244353; dp[i][l] = (dp[i][l] + x) % 998244353; xx[l] = (xx[l] + (long long)x * c * 2) % 998244353; } } int main() { static int ae1[4000], xx1[37 + 1], ae2[4000], xx2[37 + 1]; int n1, n2, h, i, j, l, ans; scanf( %d%d%d , &n1, &n2, &k); if (k % 2 != 0) { printf( 0 n ); return 0; } k /= 2; init(); for (h = 0; h < n1 - 1; h++) { scanf( %d%d , &i, &j), i--, j--; ae1[i] = link(ae1[i], j), ae1[j] = link(ae1[j], i); } for (h = 0; h < n2 - 1; h++) { scanf( %d%d , &i, &j), i--, j--; ae2[i] = link(ae2[i], j), ae2[j] = link(ae2[j], i); } ae = ae1, xx = xx1, dfs(-1, 0); ae = ae2, xx = xx2, dfs(-1, 0); ans = 0; for (l = 0; l <= k; l++) { assert(xx1[l] > 0); ans = (ans + (long long)xx1[l] * xx2[k - l] % 998244353 * ways[l * 2][(k - l) * 2]) % 998244353; } printf( %d n , ans); return 0; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_stack (clock, reset, enable, push, push_data, pop, pop_data, full, empty, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter depth = 2;
parameter width = 1;
parameter high_water_mark = 0;
parameter push_latency = 0;
parameter pop_latency = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input pop, push, full, empty;
input [width-1:0] pop_data, push_data;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_STACK";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_stack_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_stack
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Mark_Extract_Bits_block.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Mark_Extract_Bits_block
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Sin_Cos/Mark_Extract_Bits
// Hierarchy Level: 5
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Mark_Extract_Bits_block
(
In1,
Out1
);
input [17:0] In1; // ufix18
output [8:0] Out1; // ufix9
wire [8:0] MATLAB_Function_out1; // ufix9
// <S35>/MATLAB Function
controllerHdl_MATLAB_Function_block u_MATLAB_Function (.u(In1), // ufix18
.y(MATLAB_Function_out1) // ufix9
);
assign Out1 = MATLAB_Function_out1;
endmodule // controllerHdl_Mark_Extract_Bits_block
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007LL; long long large = 2000000000000000000LL; vector<int> dp; vector<vector<int> > adj; int f(int u) { if (dp[u] != -1) return dp[u]; vector<int> ch; for (int j = 0; j < (int)adj[u].size(); j++) { int v = adj[u][j]; ch.push_back(f(v)); } sort(ch.begin(), ch.end()); int re = 0; for (int i = 0; i < (int)ch.size(); i++) { if (ch[i] == re) re++; else if (ch[i] > re) break; } dp[u] = re; return dp[u]; } int main() { int n, m; cin >> n >> m; vector<int> h(n, 0); for (int i = 0; i < n; i++) scanf( %d , &h[i]); adj.assign(n, vector<int>()); for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); x--; y--; adj[x].push_back(y); } dp.assign(n, -1); int ans = 0; int sz = 0; for (int i = 0; i < n; i++) sz = max(sz, f(i) + 1); vector<int> tp(sz, 0); for (int i = 0; i < n; i++) tp[f(i)] ^= h[i]; for (int i = 0; i < sz; i++) ans |= tp[i]; if (ans == 0) { cout << LOSE << endl; return 0; } int p = -1; for (int i = 0; i < sz; i++) { if (tp[i]) p = i; } for (int i = 0; i < n; i++) if (f(i) == p && (h[i] ^ tp[p]) < h[i]) { h[i] ^= tp[p]; tp[p] = 0; for (int j = 0; j < (int)adj[i].size(); j++) { int v = adj[i][j]; h[v] ^= tp[f(v)]; tp[f(v)] = 0; } break; } cout << WIN << endl; for (int i = 0; i < n; i++) cout << h[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MAX = 100005; const long long mod = 1000000007; const double PI = 2 * acos(0.0); const double EPS = 0.00000000001; int main() { long long n; cin >> n; string a, b; cin >> a >> b; long long OO = 0, II = 0, IO = 0, OI = 0; for (long long i = 0; i < n; i++) { if (a[i] == 1 and b[i] == 1 ) II++; else if (a[i] == 0 and b[i] == 0 ) OO++; else if (a[i] == 1 and b[i] == 0 ) IO++; else if (a[i] == 0 and b[i] == 1 ) OI++; } long long ans = (OO * II) + (OI * IO) + (OO * IO); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) const long long INF = 1e9 + 7; const long long maxn = 2e5 + 7; using namespace std; void solve() { long long a, b, c, d; cin >> a >> b >> c >> d; long long ans = 0; for (long long z = c; z < d + 1; z++) { long long r1 = z - c + 1; long long r2 = z - b + 1; if (r1 > b) continue; long long sStart = 1; if (r2 < b) { sStart += (b - r2); } r2 = max(r2, b); long long numTerms = c - r2 + 1; long long whichTermGreater = b - a + 2 - sStart; long long numGreater = max(min(numTerms - whichTermGreater, numTerms), 0LL); ans += numGreater * (b - a + 1); numTerms -= numGreater; long long finalTerm = sStart + numTerms - 1; long long summn = (numTerms) * (sStart + finalTerm); summn /= 2; ans += summn; } cout << ans << n ; } int main(int argc, char** argv) { ios_base::sync_with_stdio(false); cin.tie(NULL); int T = 1; while (T--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; int cnt = 0; string ans = 1 ; for (int i = 0; i < n; i++) { string str; cin >> str; while (str.size() && str.back() == 0 ) str.pop_back(), cnt++; if (str.size() == 0) { cout << 0 ; exit(0); } if (str.size() != 1 || str.back() != 1 ) ans = str; } cout << ans; for (int i = 0; i < cnt; i++) cout << 0 ; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 14:35:07 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 1000 + 7; int n; char s[N]; struct edge { int to, nex, wei; } e[N << 1]; int fir[N], eid; int deg[N], dis[N]; int fa[N]; queue<int> q; int getfa(int x) { return fa[x] == x ? x : fa[x] = getfa(fa[x]); } void addedge(int u, int v, int w) { e[++eid] = (edge){v, fir[u], w}; fir[u] = eid; ++deg[v]; } int main() { scanf( %d%s , &n, s + 1); for (int i = 1; i <= n; ++i) fa[i] = i; for (int i = 1; i < n; ++i) if (s[i] == = ) fa[getfa(i)] = getfa(i + 1); for (int i = 1; i < n; ++i) { if (s[i] == R ) addedge(getfa(i), getfa(i + 1), 1); if (s[i] == L ) addedge(getfa(i + 1), getfa(i), 1); } for (int i = 1; i <= n; ++i) { dis[i] = 1; if (deg[i] == 0) q.push(i); } while (!q.empty()) { int s = q.front(); q.pop(); for (int i = fir[s]; i; i = e[i].nex) { dis[e[i].to] = max(dis[e[i].to], dis[s] + e[i].wei); if (--deg[e[i].to] == 0) q.push(e[i].to); } } for (int i = 1; i <= n; ++i) printf( %d , dis[getfa(i)]); return 0; }
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#include <bits/stdc++.h> using namespace std; pair<long long, long long> sn[100005], sp[100005]; bool myfunction(pair<long long, long long> i, pair<long long, long long> j) { return (i.first > j.first); } int main() { int n, p, a, first = 0, second = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &p, &a); if (p < 0) { first++; sn[first] = make_pair(p, a); } else { second++; sp[second] = make_pair(p, a); } } sort(sn, sn + first + 1, myfunction); sort(sp, sp + second + 1); for (int i = 1; i <= first; i++) sn[i].second += sn[i - 1].second; for (int i = 1; i <= second; i++) sp[i].second += sp[i - 1].second; sn[first + 1] = sn[first]; sp[second + 1] = sp[second]; int m = min(first, second); long long ans = sp[m + 1].second + sn[m].second; ans = max(ans, sp[m].second + sn[m + 1].second); printf( %I64d n , ans); return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32O_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A32O_FUNCTIONAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32O_FUNCTIONAL_V
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// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 160;
localparam integer DOUT_N = 160;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [159:0] din, output [159:0] dout);
my_ISERDES
#(
.LOC("BITSLICE_RX_TX_X0Y305"),
.DATA_WIDTH(8),
.FIFO_ENABLE("FALSE"),
.FIFO_SYNC_MODE("FALSE"),
.IS_CLK_B_INVERTED(1'b0),
.IS_CLK_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.SIM_DEVICE("ULTRASCALE_PLUS")
)
inst_0 (
.clk(clk),
.din(din[ 0 +: 3]),
.dout(dout[ 0 +: 2])
);
endmodule
// ---------------------------------------------------------------------
module my_ISERDES (input clk, input [2:0] din, output [1:0] dout);
parameter LOC = "";
parameter DATA_WIDTH = 8;
parameter FIFO_ENABLE = "FALSE";
parameter FIFO_SYNC_MODE = "FALSE";
parameter IS_CLK_B_INVERTED = 1'b0;
parameter IS_CLK_INVERTED = 1'b0;
parameter IS_RST_INVERTED = 1'b0;
parameter SIM_DEVICE = "ULTRASCALE";
(* LOC=LOC *)
ISERDESE3 #(
.DATA_WIDTH(DATA_WIDTH), // Parallel data width (4,8)
.FIFO_ENABLE(FIFO_ENABLE), // Enables the use of the FIFO
.FIFO_SYNC_MODE(FIFO_SYNC_MODE), // Always set to FALSE. TRUE is reserved for later use.
.IS_CLK_B_INVERTED(IS_CLK_B_INVERTED), // Optional inversion for CLK_B
.IS_CLK_INVERTED(IS_CLK_INVERTED), // Optional inversion for CLK
.IS_RST_INVERTED(IS_RST_INVERTED), // Optional inversion for RST
.SIM_DEVICE(SIM_DEVICE) // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
// ULTRASCALE_PLUS_ES2)
)
ISERDESE3_inst (
.FIFO_EMPTY(dout[1]), // 1-bit output: FIFO empty flag
.INTERNAL_DIVCLK(), // 1-bit output: Internally divided down clock used when FIFO is
// disabled (do not connect)
.Q(dout[0]), // 8-bit registered output
.CLK(clk), // 1-bit input: High-speed clock
.CLKDIV(din[0]), // 1-bit input: Divided Clock
.CLK_B(~clk), // 1-bit input: Inversion of High-speed clock CLK
.D(din[1]), // 1-bit input: Serial Data Input
.FIFO_RD_CLK(1'b0), // 1-bit input: FIFO read clock
.FIFO_RD_EN(1'b0), // 1-bit input: Enables reading the FIFO when asserted
.RST(din[2]) // 1-bit input: Asynchronous Reset
);
endmodule
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