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#include<iostream> #include<bits/stdc++.h> using namespace std; #define ll long long #define pb push_back #define mp make_pair #define ff first #define ss second #define MOD 1000000007 // void func(){ // } void solution(){ ll a,b; cin>>a>>b; ll val = abs(a-b); if(val==0){ cout<< 0 0 <<endl; return; } ll count = min(val-(a%val),a%val); cout<<val<< <<count<<endl; } int main(){ ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif int t; cin>>t; // func(); while(t--){ solution(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, q, e[65][65][65], d[65][65][65]; int main() { scanf( %d %d %d , &n, &m, &q); for (int i = (1); i <= (n); i++) for (int j = (1); j <= (n); j++) for (int k = (0); k <= (n); k++) d[i][j][k] = 1e9; for (int i = (1); i <= (m); i++) { for (int j = (1); j <= (n); j++) for (int k = (1); k <= (n); k++) scanf( %d , &e[i][j][k]); for (int w = (1); w <= (n); w++) for (int j = (1); j <= (n); j++) for (int k = (1); k <= (n); k++) e[i][j][k] = min(e[i][j][k], e[i][j][w] + e[i][w][k]); for (int j = (1); j <= (n); j++) for (int k = (1); k <= (n); k++) d[j][k][0] = min(d[j][k][0], e[i][j][k]); } for (int z = (1); z <= (n); z++) for (int k = (1); k <= (n); k++) for (int i = (1); i <= (n); i++) for (int j = (1); j <= (n); j++) d[i][j][z] = min(d[i][j][z], min(d[i][k][z - 1] + d[k][j][0], d[i][k][0] + d[k][j][z - 1])); while (q--) { int a, b, c; scanf( %d %d %d , &a, &b, &c); c = min(c, n); printf( %d n , d[a][b][c]); } scanf( n ); }
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: Alok:user:sample_generator:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_sample_generator_0_1 (
FrameSize,
En,
AXI_En,
m_axis_tdata,
m_axis_tstrb,
m_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_aclk,
m_axis_aresetn,
s_axis_tdata,
s_axis_tstrb,
s_axis_tlast,
s_axis_tvalid,
s_axis_tready,
s_axis_aclk,
s_axis_aresetn
);
input wire [7 : 0] FrameSize;
input wire En;
input wire AXI_En;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TSTRB" *)
output wire [3 : 0] m_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXIS_CLK CLK" *)
input wire m_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_AXIS_RST RST" *)
input wire m_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TSTRB" *)
input wire [3 : 0] s_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXIS_CLK CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_AXIS_RST RST" *)
input wire s_axis_aresetn;
sample_generator_v1_0 #(
.C_M_AXIS_TDATA_WIDTH(32), // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
.C_M_AXIS_START_COUNT(32), // Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
.C_S_AXIS_TDATA_WIDTH(32) // AXI4Stream sink: Data Width
) inst (
.FrameSize(FrameSize),
.En(En),
.AXI_En(AXI_En),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(m_axis_tstrb),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(s_axis_tstrb),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_hd__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hd__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long long n; long long Tree[1000001]; long long arr[200001]; void add(long long x, long long val) { for (; x <= n; x += x & (-x)) Tree[x] += val; return; } long long get(long long x) { long long sum = 0; for (; x > 0; x -= x & (-x)) sum += Tree[x]; return sum; } void solve() { long long x = 1; if (get(1) == 0) { cout << 1 << n ; return; } while (x < n) { long long curr_val = get(x) * 2; if (get(x + 1) == curr_val) { cout << x + 1 << n ; return; } long long lo = x + 1; long long hi = n; long long lo_bound; while (lo <= hi) { if (lo == hi) { lo_bound = lo; break; } long long mi = (lo + hi) / 2; if (get(mi) < curr_val) lo = mi + 1; else hi = mi; } long long k = lo_bound - 1; x = (x == k) ? (k + 1) : k; } cout << -1 << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); long long q; memset(Tree, 0, sizeof Tree); cin >> n >> q; for (long long i = 1; i <= n; i++) { cin >> arr[i]; add(i, arr[i]); } long long x, y; while (q--) { cin >> x >> y; add(x, y - arr[x]); arr[x] = y; solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline char nc() { return getchar(); static char buf[100000], *l = buf, *r = buf; return l == r && (r = (l = buf) + fread(buf, 1, 100000, stdin), l == r) ? EOF : *l++; } template <class T> void read(T &x) { x = 0; int f = 1, ch = nc(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = nc(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 - 0 + ch; ch = nc(); } x *= f; } int N, M, D, A[100050][50]; int cnt, id[100050][50]; pair<int, int> bel[5000050]; int head[5000050]; int head1[5000050]; struct edge { int to, nex; edge(int to = 0, int nex = 0) : to(to), nex(nex) {} }; vector<edge> G; vector<edge> G1; inline void addedge(int u, int v) { G.push_back(edge(v, head[u])), head[u] = G.size() - 1; } inline void addedge1(int u, int v) { G1.push_back(edge(v, head1[u])), head1[u] = G1.size() - 1; } int dfn[5000050], low[5000050], dfc; int sccno[5000050], val[5000050], scnt; int vis[100050]; int stk[5000050], top; void tarjan(int u) { low[u] = dfn[u] = ++dfc; stk[++top] = u; for (int i = head[u]; ~i; i = G[i].nex) { int v = G[i].to; if (!dfn[v]) { tarjan(v); low[u] = min(low[u], low[v]); } else if (!sccno[v]) { low[u] = min(low[u], dfn[v]); } } if (low[u] == dfn[u]) { ++scnt; while (true) { int x = stk[top--]; sccno[x] = scnt; int a = bel[x].first, b = bel[x].second; if (A[a][b] && vis[a] != scnt) { vis[a] = scnt; ++val[scnt]; } if (x == u) break; } } } void find_scc() { for (int i = 1; i <= cnt; ++i) if (!dfn[i]) { tarjan(i); } memset(head1, -1, sizeof(head1)); for (int u = 1; u <= cnt; ++u) { for (int i = head[u]; ~i; i = G[i].nex) { int v = G[i].to; if (sccno[u] != sccno[v]) { addedge1(sccno[u], sccno[v]); } } } } int f[5000050]; void dp(int u) { if (f[u]) return; for (int i = head1[u]; ~i; i = G1[i].nex) { int v = G1[i].to; dp(v); f[u] = max(f[u], f[v]); } f[u] += val[u]; } int solve() { find_scc(); int u = sccno[id[1][0]]; dp(u); return f[u]; } char str[60]; int main() { read(N), read(M), read(D); for (int i = 1; i <= N; ++i) { for (int j = 0; j < D; ++j) { id[i][j] = ++cnt; bel[cnt] = pair<int, int>(i, j); } } memset(head, -1, sizeof(head)); for (int i = 1; i <= M; ++i) { int u, v; read(u), read(v); for (int j = 1; j < D; ++j) { addedge(id[u][j - 1], id[v][j]); } addedge(id[u][D - 1], id[v][0]); } for (int i = 1; i <= N; ++i) { scanf( %s , str); for (int j = 0; j < D; ++j) { A[i][j] = str[j] == 1 ; } } printf( %d n , solve()); return 0; }
|
`timescale 1ns / 1ps
module gost89_mac_tb;
reg clk;
always
#1 clk = ~clk;
reg [511:0] sbox = 512'h 4a92d80e6b1c7f53eb4c6dfa23810759581da342efc7609b7da1089fe46cb2536c715fd84a9e03b24ba0721d36859cfedb413f590ae7682c1fd057a4923e6b8c;
reg [255:0] key = 256'h 0475f6e05038fbfad2c7c390edb3ca3d1547124291ae1e8a2f79cd9ed2bcefbd;
reg reset, load_data;
reg [63:0] in;
wire [31:0] out;
wire busy;
wire [31:0] result = out[31:0];
gost89_mac mac1(clk, reset, load_data, sbox, key, in, out, busy);
initial begin
$dumpfile("gost89_mac_tb.vcd");
$dumpvars(0, gost89_mac_tb);
clk = 0;
reset = 0;
load_data = 0;
/* Normal usage
4b657e2ef0d2dfa2 af36b591bbd96c85 3569faad243d6fa4
b4a50c2c00000000
*/
#1
reset = 1;
#2
reset = 0;
#2
in = 64'h 4b657e2ef0d2dfa2;
load_data = 1;
#2;
load_data = 0;
#34;
in = 64'h af36b591bbd96c85;
load_data = 1;
#2;
load_data = 0;
#34;
in = 64'h 3569faad243d6fa4;
load_data = 1;
#2;
load_data = 0;
#34;
if (result !== 32'h b4a50c2c)
begin $display("E"); $finish; end
$display("OK");
/* Reset in processing
845fbd32d185bbf2 387172424b8518a3 ba95eadaa69ed200
7acc77a200000000
*/
reset = 1;
#2
reset = 0;
#2
in = 64'h 4b657e2ef0d2dfa2;
load_data = 1;
#2;
load_data = 0;
#10
reset = 1;
#2
reset = 0;
#4
in = 64'h 845fbd32d185bbf2;
load_data = 1;
#2;
load_data = 0;
#34;
in = 64'h 387172424b8518a3;
load_data = 1;
#2;
load_data = 0;
#34;
in = 64'h ba95eadaa69ed200;
load_data = 1;
#2;
load_data = 0;
#34;
if (result !== 32'h 7acc77a2)
begin $display("E"); $finish; end
$display("OK");
/* Start with reset
ba3d8a2c8fe0307a c1fe2bf562c45b53 c066169b334014e0
c9541f2800000000
*/
#2
in = 64'h ba3d8a2c8fe0307a;
load_data = 1;
reset = 1;
#2;
load_data = 0;
reset = 0;
#34;
in = 64'h c1fe2bf562c45b53;
load_data = 1;
#2;
load_data = 0;
#34;
in = 64'h c066169b334014e0;
load_data = 1;
#2;
load_data = 0;
#34;
if (result !== 32'h c9541f28)
begin $display("E"); $finish; end
$display("OK");
#10;
$display("All passed");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int N; signed long long W[303030]; vector<pair<int, int>> E[303030]; signed long long best[303030]; signed long long ma; void dfs(int cur, int pre) { vector<signed long long> C; for (auto& e : E[cur]) if (e.first != pre) { dfs(e.first, cur); if (best[e.first] - e.second > 0) C.push_back(best[e.first] - e.second); } C.push_back(0); C.push_back(0); sort((C.begin()), (C.end())); reverse((C.begin()), (C.end())); ma = max(ma, W[cur] + C[0] + C[1]); best[cur] = W[cur] + C[0]; } void solve() { int i, j, k, l, r, x, y; string s; cin >> N; for (i = 0; i < (N); i++) cin >> W[i]; for (i = 0; i < (N - 1); i++) { cin >> x >> y >> r; E[x - 1].push_back({y - 1, r}); E[y - 1].push_back({x - 1, r}); } dfs(0, -1); cout << ma << endl; } int main(int argc, char** argv) { string s; int i; if (argc == 1) ios::sync_with_stdio(false), cin.tie(0); for (i = 0; i < (argc - 1); i++) s += argv[i + 1], s += n ; for (i = 0; i < (s.size()); i++) ungetc(s[s.size() - 1 - i], stdin); cout.tie(0); solve(); return 0; }
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2010/11/09 17:40:54 $
// \ \ / \ Date Created: 05/12/10
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: This PRBS module uses many to one feedback mechanism for 2^n
// sequence generation because the levels of logic are the same
// compared to one to many feedback mechanism for 2^n sequence
// generation. The advantage with many to one is that all 8 bits
// can be accessed for staggered output generation. The feedback
// TAP is chosen from the table that is listed in xapp052.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: prbs_gen.v,v 1.1 2010/11/09 17:40:54 mishra Exp $
**$Date: 2010/11/09 17:40:54 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_1/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/prbs_gen.v,v $
******************************************************************************/
`timescale 1ps/1ps
module prbs_gen #
(
parameter PRBS_WIDTH = 4
)
(
input clk,
input clk_en,
input rst,
output [PRBS_WIDTH-1:0] prbs_o
// output reg [3:0] prbs_shift_value
);
localparam PRBS_OFFSET = 0;
reg [PRBS_WIDTH - 1:0] Next_LFSR_Reg;
reg [PRBS_WIDTH - 1:0] LFSR_Reg;
reg [3:0] prbs_shift_value;
reg Bits_all, Feedback;
integer i;
always @ (posedge clk)
begin
if (rst )
LFSR_Reg <= {{PRBS_WIDTH-1{1'b0}},1'b1};
else if (clk_en) begin
if ( PRBS_OFFSET == 0)
// $display("prbs_value = 0x%h",LFSR_Reg);
LFSR_Reg <= Next_LFSR_Reg;
prbs_shift_value <= {prbs_shift_value[2:0],LFSR_Reg[PRBS_WIDTH-1]};
end
end
always @ (LFSR_Reg)
begin :LFSR_Next
Bits_all = ~| LFSR_Reg[PRBS_WIDTH-2:0];
Feedback = LFSR_Reg[PRBS_WIDTH-1]^Bits_all;
for (i = PRBS_WIDTH - 1; i >= 1 ; i = i-1)
Next_LFSR_Reg[i] = LFSR_Reg[i-1];
// Many to one feedback taps for 2^n sequence
// 4 logic levels required for PRBS_WIDTH = 64
case (PRBS_WIDTH)
32'd4:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[2];
32'd8:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[3]^LFSR_Reg[4]^LFSR_Reg[5];
32'd10:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[6];
32'd14:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[0]^LFSR_Reg[2]^LFSR_Reg[4];
32'd24:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[16]^LFSR_Reg[21]^LFSR_Reg[22];
32'd32:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[0]^LFSR_Reg[1]^LFSR_Reg[21];
32'd42:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[18]^LFSR_Reg[19]^LFSR_Reg[40];
32'd56:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[33]^LFSR_Reg[34]^LFSR_Reg[54];
32'd64:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[59]^LFSR_Reg[60]^LFSR_Reg[62];
32'd72:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[18]^LFSR_Reg[24]^LFSR_Reg[65];
default:
Next_LFSR_Reg[0] = Feedback^LFSR_Reg[59]^LFSR_Reg[60]^LFSR_Reg[62];
endcase
end
assign prbs_o = LFSR_Reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxlongint = 2147483647; const int inf = 1000000000; char s[10], a[1000][1100]; ; int main() { scanf( %s , s); int n; cin >> n; for (int i = 1; i <= n; i++) scanf( %s , a[i]); int ans = 0; for (int i = 1; i <= n; i++) { if (a[i][0] == s[0] && a[i][1] == s[1]) ans = 1; for (int j = 1; j <= n; j++) if (a[i][1] == s[0] && a[j][0] == s[1]) ans = 1; } if (ans) printf( YES ); else printf( NO ); }
|
#include <bits/stdc++.h> using namespace std; struct Person { int a; int id; }; bool operator<(Person a, Person b) { return a.a < b.a; } class TSolver { public: int n; vector<Person> persons; explicit TSolver(std::istream& in) { in >> n; persons.resize(n); for (int i = 0; i < n; ++i) { in >> persons[i].a; persons[i].id = i; } } bool ok = true; vector<int> ans; void Solve() { sort((persons).begin(), (persons).end()); ans.resize(n); int color = 1; for (int i = 0; ok && i < n;) { int same = n - persons[i].a; ok = ok && i + same <= n; for (int j = 0; ok && j < same; ++j) { if (persons[i + j].a != persons[i].a) { ok = false; } ans[persons[i + j].id] = color; } i += same; ++color; } } void PrintAnswer(std::ostream& out) const { if (ok) { out << Possible n ; for (int i = 0; i < n; ++i) { out << ans[i] << n [i + 1 == n]; } } else { out << Impossible n ; } } }; int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); std::cout.tie(nullptr); { auto solver = std::make_shared<TSolver>(std::cin); solver->Solve(); solver->PrintAnswer(std::cout); } do { } while (false); return 0; }
|
//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: $Name: i+IP+125372 $
// \ \ Application: MIG
// / / Filename: mem_interface_top.v
// /___/ /\ Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// Top-level module. Simple model for what the user might use
// Typically, the user will only instantiate MEM_INTERFACE_TOP in their
// code, and generate all the other infrastructure and backend logic
// separately. This module serves both as an example, and allows the user
// to synthesize a self-contained design, which they can use to test their
// hardware.
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Synthesizable testbench - used to model user's backend logic
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module mem_interface_top #
(
parameter BANK_WIDTH = 3, // # of memory bank addr bits
parameter CKE_WIDTH = 1, // # of memory clock enable outputs
parameter CLK_WIDTH = 1, // # of clock outputs
parameter COL_WIDTH = 10, // # of memory column bits
parameter CS_NUM = 1, // # of separate memory chip selects
parameter CS_WIDTH = 1, // # of total memory chip selects
parameter CS_BITS = 0, // set to log2(CS_NUM) (rounded up)
parameter DM_WIDTH = 9, // # of data mask bits
parameter DQ_WIDTH = 72, // # of data width
parameter DQ_PER_DQS = 8, // # of DQ data bits per strobe
parameter DQS_WIDTH = 9, // # of DQS strobes
parameter DQ_BITS = 7, // set to log2(DQS_WIDTH*DQ_PER_DQS)
parameter DQS_BITS = 4, // set to log2(DQS_WIDTH)
parameter ODT_WIDTH = 1, // # of memory on-die term enables
parameter ROW_WIDTH = 14, // # of memory row and # of addr bits
parameter ADDITIVE_LAT = 0, // additive write latency
parameter BURST_LEN = 4, // burst length (in double words)
parameter BURST_TYPE = 0, // burst type (=0 seq; =1 interleaved)
parameter CAS_LAT = 3, // CAS latency
parameter ECC_ENABLE = 0, // enable ECC (=1 enable)
parameter MULTI_BANK_EN = 1, // Keeps multiple banks open. (= 1 enable)
parameter ODT_TYPE = 0, // ODT (=0(none),=1(75),=2(150),=3(50))
parameter REDUCE_DRV = 0, // reduced strength mem I/O (=1 yes)
parameter REG_ENABLE = 1, // registered addr/ctrl (=1 yes)
parameter TREFI_NS = 7800, // auto refresh interval (uS)
parameter TRAS = 40000, // active->precharge delay
parameter TRCD = 15000, // active->read/write delay
parameter TRFC = 127500, // refresh->refresh, refresh->active delay
parameter TRP = 15000, // precharge->command delay
parameter TRTP = 7500, // read->precharge delay
parameter TWR = 15000, // used to determine write->precharge
parameter TWTR = 10000, // write->read delay
parameter IDEL_HIGH_PERF = "TRUE", // # initial # taps for DQ IDELAY
parameter SIM_ONLY = 0, // = 1 to skip SDRAM power up delay
parameter CLK_PERIOD = 5000, // Core/Memory clock period (in ps)
parameter RST_ACT_LOW = 1, // =1 for active low reset, =0 for active high
parameter DLL_FREQ_MODE = "HIGH" // DCM Frequency range
)
(
inout [DQ_WIDTH-1:0] ddr2_dq,
output [ROW_WIDTH-1:0] ddr2_a,
output [BANK_WIDTH-1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [CS_WIDTH-1:0] ddr2_cs_n,
output [ODT_WIDTH-1:0] ddr2_odt,
output [CKE_WIDTH-1:0] ddr2_cke,
output ddr2_reset_n,
output [DM_WIDTH-1:0] ddr2_dm,
//// input sys_clk_p,
//// input sys_clk_n,
input sys_clk,
input clk200_p,
input clk200_n,
/// Jiansong: 200MHz clock output
output clk200_o,
input sys_rst_n,
output phy_init_done,
output rst0_tb,
output clk0_tb,
output app_wdf_afull,
output app_af_afull,
output rd_data_valid,
input app_wdf_wren,
input app_af_wren,
input [30:0] app_af_addr,
input [2:0] app_af_cmd,
output [(2*DQ_WIDTH)-1:0] rd_data_fifo_out,
input [(2*DQ_WIDTH)-1:0] app_wdf_data,
input [(2*DM_WIDTH)-1:0] app_wdf_mask_data,
inout [DQS_WIDTH-1:0] ddr2_dqs,
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
output [CLK_WIDTH-1:0] ddr2_ck,
output [CLK_WIDTH-1:0] ddr2_ck_n
);
wire rst0;
wire rst90;
wire rst200;
wire clk0;
wire clk90;
wire clk200;
wire idelay_ctrl_rdy;
//***************************************************************************
assign rst0_tb = rst0;
assign clk0_tb = clk0;
assign ddr2_reset_n= ~rst0;
/// Jiansong:
assign clk200_o = clk200;
mem_interface_top_idelay_ctrl u_idelay_ctrl
(
.rst200(rst200),
.clk200(clk200),
.idelay_ctrl_rdy(idelay_ctrl_rdy)
);
mem_interface_top_infrastructure #
(
.CLK_PERIOD(CLK_PERIOD),
.RST_ACT_LOW(RST_ACT_LOW),
.DLL_FREQ_MODE(DLL_FREQ_MODE)
)
u_infrastructure
(
//// .sys_clk_p(sys_clk_p),
//// .sys_clk_n(sys_clk_n),
.sys_clk(sys_clk),
.clk200_p(clk200_p),
.clk200_n(clk200_n),
.sys_rst_n(sys_rst_n),
.rst0(rst0),
.rst90(rst90),
.rst200(rst200),
.clk0(clk0),
.clk90(clk90),
.clk200(clk200),
.idelay_ctrl_rdy(idelay_ctrl_rdy)
);
mem_interface_top_ddr2_top_0 #
(
.BANK_WIDTH(BANK_WIDTH),
.CKE_WIDTH(CKE_WIDTH),
.CLK_WIDTH(CLK_WIDTH),
.COL_WIDTH(COL_WIDTH),
.CS_NUM(CS_NUM),
.CS_WIDTH(CS_WIDTH),
.CS_BITS(CS_BITS),
.DM_WIDTH(DM_WIDTH),
.DQ_WIDTH(DQ_WIDTH),
.DQ_PER_DQS(DQ_PER_DQS),
.DQS_WIDTH(DQS_WIDTH),
.DQ_BITS(DQ_BITS),
.DQS_BITS(DQS_BITS),
.ODT_WIDTH(ODT_WIDTH),
.ROW_WIDTH(ROW_WIDTH),
.ADDITIVE_LAT(ADDITIVE_LAT),
.BURST_LEN(BURST_LEN),
.BURST_TYPE(BURST_TYPE),
.CAS_LAT(CAS_LAT),
.ECC_ENABLE(ECC_ENABLE),
.MULTI_BANK_EN(MULTI_BANK_EN),
.ODT_TYPE(ODT_TYPE),
.REDUCE_DRV(REDUCE_DRV),
.REG_ENABLE(REG_ENABLE),
.TREFI_NS(TREFI_NS),
.TRAS(TRAS),
.TRCD(TRCD),
.TRFC(TRFC),
.TRP(TRP),
.TRTP(TRTP),
.TWR(TWR),
.TWTR(TWTR),
.IDEL_HIGH_PERF(IDEL_HIGH_PERF),
.SIM_ONLY(SIM_ONLY),
.CLK_PERIOD(CLK_PERIOD)
)
u_ddr2_top_0
(
.ddr2_dq(ddr2_dq),
.ddr2_a(ddr2_a),
.ddr2_ba(ddr2_ba),
.ddr2_ras_n(ddr2_ras_n),
.ddr2_cas_n(ddr2_cas_n),
.ddr2_we_n(ddr2_we_n),
.ddr2_cs_n(ddr2_cs_n),
.ddr2_odt(ddr2_odt),
.ddr2_cke(ddr2_cke),
.ddr2_dm(ddr2_dm),
.phy_init_done(phy_init_done),
.rst0(rst0),
.rst90(rst90),
.clk0(clk0),
.clk90(clk90),
.app_wdf_afull(app_wdf_afull),
.app_af_afull(app_af_afull),
.rd_data_valid(rd_data_valid),
.app_wdf_wren(app_wdf_wren),
.app_af_wren(app_af_wren),
.app_af_addr(app_af_addr),
.app_af_cmd(app_af_cmd),
.rd_data_fifo_out(rd_data_fifo_out),
.app_wdf_data(app_wdf_data),
.app_wdf_mask_data(app_wdf_mask_data),
.ddr2_dqs(ddr2_dqs),
.ddr2_dqs_n(ddr2_dqs_n),
.ddr2_ck(ddr2_ck),
.ddr2_ck_n(ddr2_ck_n)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2000010; long long n, m, s, l; vector<pair<long long, long long> > Adj[N]; long long Dis[N], Ans; set<pair<long long, long long> > Res; vector<pair<long long, pair<long long, long long> > > Edges; void Dik() { for (int i = 0; i <= n; i++) Dis[i] = 1e18; Dis[s] = 0; set<pair<long long, long long> > S; S.insert({0, s}); while (!S.empty()) { auto Cur = *S.begin(); S.erase(S.begin()); for (int i = 0; i < Adj[Cur.second].size(); i++) { int to = Adj[Cur.second][i].first; long long w = Adj[Cur.second][i].second; if (Dis[to] > Cur.first + w) { Dis[to] = Cur.first + w; S.insert({Dis[to], to}); } } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m >> s; for (int i = 0; i < m; i++) { int a, b, w; cin >> a >> b >> w; Edges.push_back({w, {a, b}}); Adj[a].push_back({b, w}); Adj[b].push_back({a, w}); } cin >> l; if (l == 0) { cout << 1 << endl; return 0; } Dik(); for (int i = 1; i <= n; i++) if (Dis[i] == l) Ans++; for (int i = 0; i < Edges.size(); i++) { int a = Edges[i].second.first; int b = Edges[i].second.second; long long w = Edges[i].first; if (Dis[a] < l && Dis[a] + w > l && (w - (l - Dis[a])) + Dis[b] >= l) { Ans++; } if (Dis[b] < l && Dis[b] + w > l && (w - (l - Dis[b])) + Dis[a] >= l) { Ans++; } if (Dis[a] < l && Dis[a] + w > l && (w - (l - Dis[a])) + Dis[b] >= l) { if (Dis[b] < l && Dis[b] + w > l && (w - (l - Dis[b])) + Dis[a] >= l) { if (w - (l - Dis[a]) == (l - Dis[b])) Ans--; } } } cout << Ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Tree { static const int MAXN = 500010; struct Edge { int son, dis; Edge *pre; void add(int _s, int _d, Edge *_p) { son = _s, dis = _d, pre = _p; } } edge[MAXN << 1], *pos[MAXN]; int sum; void clear() { sum = 0; memset(pos, 0, sizeof(pos)); } void add(int a, int b, int c) { edge[++sum].add(b, c, pos[a]); pos[a] = edge + sum; } } T; const int MAXN = 500010, MAXK = 500010, MAXM = 500010; struct Edge { int from, to, price; } E[MAXK + MAXM]; int n, m, k; void init() { scanf( %d%d%d , &n, &k, &m); for (int i = 1; i <= k + m; ++i) { int u, v, w; scanf( %d%d , &u, &v); if (i <= k) w = -1; else scanf( %d , &w); E[i] = (Edge){u, v, w}; } } struct DisjointSet { static const int MAXN = 500010; int fa[MAXN], n; void clear(int _n) { n = _n; for (int i = 1; i <= n; ++i) fa[i] = i; } int find(int x) { if (fa[x] == x) return x; return fa[x] = find(fa[x]); } bool merge(int u, int v) { int fx = find(u), fy = find(v); if (fx == fy) return false; fa[fx] = fy; return true; } } DS; void buildTree() { DS.clear(n); T.clear(); for (int i = 1; i <= k + m; ++i) if (DS.merge(E[i].from, E[i].to)) { T.add(E[i].from, E[i].to, E[i].price); T.add(E[i].to, E[i].from, E[i].price); } } const int MAXL = 20; int fa[MAXN][MAXL], l2[MAXN], dep[MAXN]; void dfs(int x, int f) { for (int l = 1; l <= l2[dep[x]]; ++l) fa[x][l] = fa[fa[x][l - 1]][l - 1]; for (Tree::Edge *i = T.pos[x]; i; i = i->pre) if (i->son != f) { fa[i->son][0] = x; dep[i->son] = dep[x] + 1; dfs(i->son, x); } } void preset() { l2[0] = -1, l2[1] = 0; for (int i = 2; i <= n; ++i) l2[i] = l2[i >> 1] + 1; memset(fa, 0, sizeof(fa)), dep[1] = 1; dfs(1, 0); } int lca(int u, int v) { if (dep[u] > dep[v]) swap(u, v); for (int l = l2[dep[v] - dep[u]]; l >= 0; --l) if (dep[v] - (1 << l) >= dep[u]) v = fa[v][l]; if (u == v) return u; for (int l = l2[dep[u]]; l >= 0; --l) if (fa[u][l] != fa[v][l]) u = fa[u][l], v = fa[v][l]; return fa[u][0]; } const long long INF = ~0ull >> 3; multiset<int> F[MAXN]; vector<int> ins[MAXN]; long long solve(int x, int f, bool mask) { long long ans = 0; for (Tree::Edge *i = T.pos[x]; i; i = i->pre) if (i->son != f) { long long ret = solve(i->son, x, (i->dis == -1)); if (ret == INF) return INF; ans += ret; if (F[x].size() < F[i->son].size()) F[x].swap(F[i->son]); F[x].insert(F[i->son].begin(), F[i->son].end()); } for (int val : ins[x]) if (val > 0) F[x].insert(val); else F[x].erase(F[x].find(-val)); if (!mask) return ans; if (x > 1 && F[x].empty()) return INF; ans += *F[x].begin(); return ans; } int main() { init(); buildTree(); preset(); for (int i = k + 1; i <= k + m; ++i) { int u = E[i].from, v = E[i].to, w = E[i].price; int z = lca(u, v); if (u != z) ins[u].push_back(w), ins[z].push_back(-w); if (v != z) ins[v].push_back(w), ins[z].push_back(-w); } long long ans = solve(1, 0, false); if (ans == INF) cout << -1 << endl; else cout << ans << endl; return 0; }
|
#include<bits/stdc++.h> using namespace std; #define pb push_back #define reg register #define int long long #define For(i,a,b) for(reg int i=a;i<=b;++i) #define Down(i,a,b) for(reg int i=a;i>=b;--i) #define ull unsigned long long #define rep(i,a,b) for(reg int i=a;i<=b;++i) #define ll long long inline int max(int x,int y){return x>y?x:y;} inline int min(int x,int y){return x<y?x:y;} inline void ckmin(int &x,int y){x=x<y?x:y; return ;} inline void ckmax(int &x,int y){x=x>y?x:y; return ;} inline int gcd(int n,int m){return m?gcd(m,n%m):n;} inline int lcm(int x,int y){return x/gcd(x,y)*y;} inline void swap(int &x,int &y){int t=x; x=y; y=t; return ;} namespace yspm{ inline int read(){ int res=0,f=1; char k; while(!isdigit(k=getchar())) if(k== - ) f=-1; while(isdigit(k)) res=res*10+k- 0 ,k=getchar(); return res*f; } char out[100]; inline void print(int x){ if(!x) return putchar( 0 ),putchar( n ),void(); if(x<0) putchar( - ),x=-x; int cnt=0; while(x) out[++cnt]=x%10,x/=10; Down(i,cnt,1) putchar(out[i]+ 0 ); putchar( n ); return ; } const int N=1e5+10,bl=510; vector<int>f[N<<2]; int n,a[N],p,v; inline void push_up(int x){ int rpos=0,lsz=f[x<<1].size(),rsz=f[x<<1|1].size(); f[x].clear(); for(reg int i=0;i<lsz;){ if(rpos==rsz||(f[x<<1][i]<f[x<<1|1][rpos]-i)) f[x].push_back(f[x<<1][i++]); else f[x].push_back(f[x<<1|1][rpos++]-i); } for(reg int j=rpos;j<rsz;++j) f[x].push_back(f[x<<1|1][j]-lsz); return ; } inline void build(int p,int l,int r){ if(l==r) return f[p].resize(1),f[p][0]=a[l],void(); int mid=(l+r)>>1; build(p<<1,l,mid); build(p<<1|1,mid+1,r); if(r-l+1<=bl) push_up(p); return ; } inline void modify(int x,int l,int r){ if(l==r) return f[x][0]=a[l],void(); int mid=(l+r)>>1; if(p<=mid) modify(x<<1,l,mid); else modify(x<<1|1,mid+1,r); if(r-l+1<=bl) push_up(x); return ; } inline void query(int x,int l,int r){ if(l>=p&&r-l+1<=bl) return v+=upper_bound(f[x].begin(),f[x].end(),v)-f[x].begin(),void(); int mid=(l+r)>>1; if(mid>=p) query(x<<1,l,mid); return query(x<<1|1,mid+1,r); } signed main(){ n=read(); rep(i,1,n) a[i]=i-read(); build(1,1,n); int Q=read(); while(Q--){ if(read()==1){ int x=read(),y=read(); a[x]=x-y; p=x; modify(1,1,n); }else{ p=read(); if(p==n) print(a[n]); else v=a[p],++p,query(1,1,n),print(v); } } return 0; } }signed main(){return yspm::main();} //Use The Time To Enrich This Selfclosing Youth
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<pair<int, int> > e; bool check(vector<pair<int, int> > res) { if (res.size() > (n + m + 1) / 2) return false; vector<int> d(n, 0), d2(n, 0); for (pair<int, int> i : res) { d[--i.first]++; d[--i.second]++; } for (pair<int, int> i : e) { d2[--i.first]++; d2[--i.second]++; } for (int i = 0; i < n; i++) { if ((d2[i] + 1) / 2 > d[i]) return false; } return true; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; e.resize(m); vector<set<int> > g(n + 1); for (int i = 0; i < m; i++) { cin >> e[i].first >> e[i].second; g[e[i].first].insert(e[i].second); g[e[i].second].insert(e[i].first); } for (int i = 1; i <= n; i++) { if ((int)(g[i].size()) & 1) { g[i].insert(0); g[0].insert(i); } } vector<int> c(n + 1, 0); vector<pair<int, int> > res; for (int s = 1; s <= n; s++) { if (!c[s]) { vector<int> st, ep; st.push_back(s); while (!st.empty()) { int f = st.back(); c[f] = 1; if (g[f].empty()) { st.pop_back(); ep.push_back(f); } else { int v = *g[f].begin(); g[f].erase(v); g[v].erase(f); st.push_back(v); } } ep.pop_back(); for (int i = 0; i < (int)ep.size(); i++) { int v0 = ep[(ep.size() + i - 1) % ep.size()], v1 = ep[i], v2 = ep[(i + 1) % ep.size()], v3 = ep[(i + 2) % ep.size()]; if (!v1 || !v2) continue; if (!v0 || !v3 || !(i & 1)) { res.push_back({v1, v2}); } } } } cout << res.size() << n ; for (pair<int, int> i : res) { cout << i.first << << i.second << n ; } return 0; }
|
//**************************************************************************
// ph_byte.v - single byte buffer for transfers in parasite to host direction
//
// COPYRIGHT 2010 Richard Evans, Ed Spittles
//
// This file is part of tube - an Acorn Tube ULA compatible system.
//
// tube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// tube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with tube. If not, see <http://www.gnu.org/licenses/>.
//
// **************************************************************************
`timescale 1ns / 1ns
module ph_byte (
input h_rst_b,
input h_rd,
input h_selectData,
input h_phi2,
input [7:0] p_data,
input p_selectData,
input p_phi2,
input p_rdnw,
output [7:0] h_data,
output h_data_available,
output p_full
);
reg [7:0] fifo_q_r ;
wire [7:0] fifo_d_r ;
assign h_data = fifo_q_r;
assign fifo_d_r = ( p_selectData & !p_rdnw) ? p_data : fifo_q_r;
ph_flag_m flag_0 (
.rst_b(h_rst_b),
.p2_rdnw(h_rd),
.p2_select(h_selectData),
.p2_clk(h_phi2),
.p1_select(p_selectData),
.p1_rdnw(p_rdnw),
.p1_clk(p_phi2),
.p2_data_available(h_data_available),
.p1_full(p_full)
);
// Infer all state
always @ ( posedge p_phi2 or negedge h_rst_b )
begin
if ( ! h_rst_b)
fifo_q_r <= 8'h41;
else
fifo_q_r <= fifo_d_r ;
end
endmodule // ph_byte
|
module register_set #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 8,
parameter MEM_DEPTH = 1 << ADDR_WIDTH
)
(
input logic clk,
input logic reset,
input logic wnr,
input logic [1:0] req,
input logic [ADDR_WIDTH-1:0] address,
input logic [4*DATA_WIDTH-1:0] data_in,
//Output ports
output logic ack,
output logic [4*DATA_WIDTH-1:0] data_out,
output logic [DATA_WIDTH*MEM_DEPTH-1:0] mem_data_out
);
reg [DATA_WIDTH - 1: 0] mem [0 : MEM_DEPTH - 1];
integer j;
genvar i;
for(i=0; i<MEM_DEPTH;i=i+1) begin
assign mem_data_out[DATA_WIDTH*i+:DATA_WIDTH] = mem[i];
end
always @(posedge clk) begin
if(reset) begin
for(j=0; j<256;j=j+1)
mem[j]=0;
data_out=0;
ack=0;
end
else begin
ack <= 0;
data_out <= 0;
if(wnr) begin
if(req == 1) begin
mem[address] <= data_in[DATA_WIDTH-1:0];
ack <= 1;
end
if(req == 2) begin
mem[address] <= data_in[DATA_WIDTH-1:0];
mem[address+1] <= data_in[2*DATA_WIDTH-1:DATA_WIDTH];
ack <= 1;
end
if(req == 3) begin
mem[address] <= data_in[DATA_WIDTH-1:0];
mem[address+1] <= data_in[2*DATA_WIDTH-1:DATA_WIDTH];
mem[address+2] <= data_in[3*DATA_WIDTH-1:2*DATA_WIDTH];
mem[address+3] <= data_in[4*DATA_WIDTH-1:3*DATA_WIDTH];
ack <= 1;
end
end
else begin
if (req == 1) begin
data_out[DATA_WIDTH-1:0] <= mem[address];
ack <= 1;
end
if(req == 2) begin
data_out[DATA_WIDTH-1:0] <= mem[address];
data_out[2*DATA_WIDTH-1:DATA_WIDTH] <= mem[address+1];
ack <= 1;
end
if(req == 3) begin
data_out[DATA_WIDTH-1:0] <= mem[address];
data_out[2*DATA_WIDTH-1:DATA_WIDTH] <= mem[address+1];
data_out[3*DATA_WIDTH-1:2*DATA_WIDTH] <= mem[address+2];
data_out[4*DATA_WIDTH-1:3*DATA_WIDTH] <= mem[address+3];
ack <= 1;
end // if req == 3
end // else (wnr)
end // else (reset)
end // always
endmodule // register_set
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:18:02 06/09/2015
// Design Name: aesmodule
// Module Name: F:/Projects/Xilinx/Rijndael/test_aesmodule.v
// Project Name: Rijndael
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: aesmodule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_aesmodule;
// Inputs
reg [127:0] in;
reg decr;
reg clk;
reg reset;
// Outputs
wire [127:0] out;
wire ready;
// Instantiate the Unit Under Test (UUT)
aesmodule uut (
.out(out),
.ready(ready),
.in(in),
.decr(decr),
.clk(clk),
.reset(reset)
);
always begin
clk = 0;
#10;
clk = 1;
#10;
end
initial begin
// Initialize Inputs
decr = 0;
reset = 0;
in = 128'h3243f6a8_885a308d_313198a2_e0370734;
//in = 128'h3925841d_02dc09fb_dc118597_196a0b32;
#2;
reset = 1;
#3;
reset = 0;
#5;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long fib[50010]; int main() { long long n; cin >> n; fib[0] = 1; fib[1] = 2; if (n == 1) { cout << 0; return 0; } else if (n == 2) { cout << 1; return 0; } int i = 1; while (fib[i] <= n) { ++i; fib[i] = fib[i - 2] + fib[i - 1]; } --i; cout << i; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 2000000000; const int MOD = 1000000007; int n, m, k = 0, c = 0, q; map<int, char> mp; map<char, int> cnt; int main() { string s; cin >> s; bool f1 = 0, f2 = 0, f3 = 0, f4 = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == G ) { f1 = 1; mp[i % 4] = s[i]; } if (s[i] == Y ) { f2 = 1; mp[i % 4] = s[i]; } if (s[i] == R ) { f3 = 1; mp[i % 4] = s[i]; } if (s[i] == B ) { f4 = 1; mp[i % 4] = s[i]; } } if (!f1) { for (int i = 0; i < 4; i++) { if (mp.find(i) == mp.end()) { mp[i] = G ; break; } } } if (!f2) { for (int i = 0; i < 4; i++) { if (mp.find(i) == mp.end()) { mp[i] = Y ; break; } } } if (!f3) { for (int i = 0; i < 4; i++) { if (mp.find(i) == mp.end()) { mp[i] = R ; break; } } } if (!f4) { for (int i = 0; i < 4; i++) { if (mp.find(i) == mp.end()) { mp[i] = B ; break; } } } string s1 = ; for (int i = 0; i < s.length(); i++) { if (s[i] == ! ) { cnt[mp[i % 4]]++; } } cout << cnt[ R ] << << cnt[ B ] << << cnt[ Y ] << << cnt[ G ]; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 0x3f3f3f3f3f3f3f3f; long long n, m, mod, a[1000010]; inline long long max(long long x, long long y) { return (x > y ? x : y); } inline long long min(long long x, long long y) { return (x < y ? x : y); } struct Segment_Tree { vector<long long> T[1000010 << 2]; long long bas[1000010 << 2], len[1000010 << 2]; inline void pushup(long long x) { bas[x] = bas[(x << 1)] + bas[(x << 1 | 1)]; register long long i = 0, j = 0; for (; i <= len[(x << 1)]; ++i) { if (j) --j; for (; j <= len[(x << 1 | 1)]; ++j) { if (T[(x << 1)][i + 1] - i * mod + bas[(x << 1)] <= T[(x << 1 | 1)][j]) { if (j) --j; break; } T[x][i + j] = min( T[x][i + j], max(T[(x << 1)][i], T[(x << 1 | 1)][j] + i * mod - bas[(x << 1)])); } } return; } inline void build(long long x, long long l, long long r) { long long mid = (l + r) >> 1; len[x] = r - l + 1; T[x].resize(r - l + 3); for (register long long i = 0; i < r - l + 3; ++i) T[x][i] = inf; if (l == r) { T[x][0] = -inf; T[x][1] = -a[l] + mod; T[x][2] = inf; bas[x] = a[l]; return; } build((x << 1), l, mid); build((x << 1 | 1), mid + 1, r); pushup(x); return; } inline void query(long long x, long long l, long long r, long long lx, long long rx, long long &ans) { if (lx <= l && r <= rx) { long long L = 0, R = len[x] + 1; while (L < R) { long long mid = (L + R + 1) >> 1; if (T[x][mid] <= ans) L = mid; else R = mid - 1; } ans = ans + bas[x] - L * mod; return; } long long mid = (l + r) >> 1; if (lx <= mid) query((x << 1), l, mid, lx, rx, ans); if (rx > mid) query((x << 1 | 1), mid + 1, r, lx, rx, ans); return; } } tree; inline long long read() { long long x = 0; char c = getchar(); bool y = 1; for (; c < 0 || c > 9 ; c = getchar()) if (c == - ) y = 0; for (; c >= 0 && c <= 9 ; c = getchar()) x = (x << 1) + (x << 3) + c - 48; if (y) return x; return -x; } inline void Input() { n = read(), m = read(), mod = read(); for (register long long i = 1; i <= n; ++i) a[i] = read(); tree.build(1, 1, n); return; } inline void solve() { for (register long long i = 1; i <= m; ++i) { long long l = read(), r = read(), ans = 0; tree.query(1, 1, n, l, r, ans); printf( %lld n , ans); } return; } signed main() { Input(); solve(); return 0; }
|
`include "core.h"
`default_nettype none
module pipeline_control_spr_exchange(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//System Register
input wire [31:0] iSYSREG_SPR,
input wire [31:0] iSYSREG_TISR,
input wire [31:0] iSYSREG_TIDR,
//Request
input wire iRD_START,
input wire iRD_KERNEL, //0:User Mode(Kernel -> User) | 1 : Kernel Mode(User -> Kernel)
//FInish
output wire oFINISH,
output wire [31:0] oFINISH_SPR,
//Load Store
output wire oLDST_USE,
output wire oLDST_REQ,
input wire iLDST_BUSY,
output wire [1:0] oLDST_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire oLDST_RW, //0=Read 1=Write
output wire [13:0] oLDST_ASID,
output wire [1:0] oLDST_MMUMOD,
output wire [31:0] oLDST_PDT,
output wire [31:0] oLDST_ADDR,
output wire [31:0] oLDST_DATA,
input wire iLDST_REQ,
input wire [31:0] iLDST_DATA
);
/***************************************************************************
State
***************************************************************************/
localparam L_PARAM_IDLE = 3'h0;
localparam L_PARAM_LOAD_REQ = 3'h1;
localparam L_PARAM_LOAD_ACK = 3'h2;
localparam L_PARAM_STORE_REQ = 3'h3;
localparam L_PARAM_STORE_ACK = 3'h4;
reg [2:0] state;
reg [2:0] b_state;
always@*begin
case(b_state)
L_PARAM_IDLE:
begin
if(iRD_START)begin
state = L_PARAM_LOAD_REQ;
end
else begin
state = L_PARAM_IDLE;
end
end
L_PARAM_LOAD_REQ:
begin
if(!iLDST_BUSY)begin
state = L_PARAM_LOAD_ACK;
end
else begin
state = L_PARAM_LOAD_REQ;
end
end
L_PARAM_LOAD_ACK:
begin
//Get Check
if(iLDST_REQ)begin
state = L_PARAM_STORE_REQ;
end
else begin
state = L_PARAM_LOAD_ACK;
end
end
L_PARAM_STORE_REQ:
begin
if(!iLDST_BUSY)begin
state = L_PARAM_STORE_ACK;
end
else begin
state = L_PARAM_STORE_REQ;
end
end
L_PARAM_STORE_ACK:
begin
//Get Check
if(iLDST_REQ)begin
state = L_PARAM_IDLE;
end
else begin
state = L_PARAM_STORE_ACK;
end
end
default:
begin
state = L_PARAM_IDLE;
end
endcase
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_IDLE;
end
else if(iRESET_SYNC)begin
b_state <= L_PARAM_IDLE;
end
else begin
b_state <= state;
end
end
reg b_finish;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_finish <= 1'b0;
end
else if(iRESET_SYNC)begin
b_finish <= 1'b0;
end
else begin
b_finish <= (state == L_PARAM_STORE_ACK) && iLDST_REQ;
end
end
/***************************************************************************
Load Data Buffer
***************************************************************************/
reg [31:0] b_load_data;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_load_data <= 32'h0;
end
else if(iRESET_SYNC)begin
b_load_data <= 32'h0;
end
else begin
if((state == L_PARAM_LOAD_ACK) && iLDST_REQ)begin
b_load_data <= iLDST_DATA;
end
end
end
/***************************************************************************
Load Store Pipe
***************************************************************************/
reg b_ldst_use;
reg b_ldst_req;
reg [31:0] b_ldst_data;
wire [31:0] uspr_addr = iSYSREG_TISR + {iSYSREG_TIDR[13:0], 8'h0} + `TST_USPR;
wire [31:0] kspr_addr = iSYSREG_TISR + {iSYSREG_TIDR[13:0], 8'h0} + `TST_KSPR;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ldst_use <= 1'b0;
b_ldst_req <= 1'b0;
b_ldst_data <= 32'h0;
end
else if(iRESET_SYNC)begin
b_ldst_use <= 1'b0;
b_ldst_req <= 1'b0;
b_ldst_data <= 32'h0;
end
else begin
b_ldst_use <= state != L_PARAM_IDLE;
b_ldst_req <= state == L_PARAM_STORE_REQ || state == L_PARAM_LOAD_REQ;
b_ldst_data <= iSYSREG_SPR;
end
end
reg [31:0] b_ldst_addr;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ldst_addr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_ldst_addr <= 32'h0;
end
else begin
if(iRD_KERNEL)begin
if(state == L_PARAM_STORE_REQ)begin
b_ldst_addr <= uspr_addr;
end
else begin
b_ldst_addr <= kspr_addr;
end
end
else begin
if(state == L_PARAM_STORE_REQ)begin
b_ldst_addr <= kspr_addr;
end
else begin
b_ldst_addr <= uspr_addr;
end
end
end
end
/***************************************************************************
Assign
***************************************************************************/
assign oFINISH = b_finish;
assign oFINISH_SPR = b_load_data;
assign oLDST_USE = b_ldst_use;
assign oLDST_REQ = b_ldst_req;
assign oLDST_ORDER = 2'h2; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
assign oLDST_RW = 1'b0; //0=Read 1=Write
assign oLDST_ASID = 14'h0;
assign oLDST_MMUMOD = 2'h0;
assign oLDST_PDT = 32'h0;
assign oLDST_ADDR = b_ldst_addr;
assign oLDST_DATA = b_ldst_data;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; unordered_set<long long int> s; void fun(long long int l, long long int r, long long int n) { if (n > r) return; else if (n <= r and n >= l) { s.insert(n); } fun(l, r, n * 2); fun(l, r, n * 3); } void solve() { long long int l, r; cin >> l >> r; fun(l, r, 1); cout << s.size() << endl; } signed main() { long long int t = 1; while (t--) { solve(); } return 0; }
|
// Copyright (c) 2000 Steve Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: First test for Procedural continuous assignment
module test;
//
// Define a procedural assignment based mux.
//
reg [1:0] sel;
reg [1:0] out, a,b,c,d;
reg error;
always @ (sel)
case (sel)
2'b00: assign out = a;
2'b01: assign out = b;
2'b10: assign out = c;
2'b11: assign out = d;
endcase
initial
begin
error = 0;
#1 ;
sel = 0;
a = 0;
#1;
if(out !== 2'b00)
begin
$display("FAILED - Procedural assignment out != 0 (1)");
error =1;
end
#1;
a = 1;
#1;
if(out !== 2'b01)
begin
$display("FAILED - Procedural assignment out != 1 (2)");
error =1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
Require Import Coq.Lists.List.
(* type level existential quantifier *)
Notation "'existsT' x .. y , p" :=
(sigT (fun x => .. (sigT (fun y => p)) ..))
(at level 200, x binder, right associativity,
format "'[' 'existsT' '/ ' x .. y , '/ ' p ']'")
: type_scope.
(* the following shows that a decidable (or boolean valued) predicate on a finite list
can always be reified in terms of strong existence *)
Theorem reify {A: Type} (l: list A) (P: A -> bool) :
(exists x, In x l /\ P x = true) -> existsT x, P x = true.
Proof.
intro H.
induction l.
contradict H.
intro H0.
destruct H0 as [x Hx].
destruct Hx as [H1 H2].
inversion H1.
(* list not nil *)
assert (Hbiv: {P a = true} + {P a <> true}).
decide equality.
destruct Hbiv as [Htrue | Hfalse].
exists a.
assumption.
(* the element is in the tail *)
apply IHl.
destruct H as [x Hx].
destruct Hx as [Hl Hr].
assert (Hin: a = x \/ In x l). apply in_inv. assumption.
destruct Hin as [Hin1 | Hin2].
(* case a = x: impossible *)
subst.
contradict Hr. assumption.
exists x. split. assumption. assumption.
Qed.
Program Fixpoint addlist (ls1 ls2 : list nat) : list nat :=
match ls1, ls2 with
| n1 :: ls1',n2 :: ls2' => n1 + n2 :: addlist ls1' ls2'
|_, _ => nil
end.
Eval compute in fun ls => addlist nil ls.
Eval compute in fun ls => addlist ls nil.
Definition one_plus_one : 1 + 1 = 2 := eq_refl.
Definition zero_plus_n n : 0 + n = n := eq_refl.
Compute (zero_plus_n 10).
Eval compute in (zero_plus_n 10).
Fail Definition n_plus_zero n : n + 0 = n := eq_refl.
Program Definition n_plus_zero n : n + 0 = n.
induction n.
+ auto.
+ simpl. rewrite IHn. apply eq_refl.
Defined.
Print n_plus_zero.
Inductive expr :=
| Var : nat -> expr
| Add : expr -> expr -> expr
| Mul : expr -> expr -> expr.
Example expr_ex :=
Mul (Var 0) (Add (Var 0) (Var 1)).
Inductive isEven : nat -> Prop :=
| Even_O : isEven 0
| Even_SS n : isEven n -> isEven (S (S n)).
Ltac prove_even := repeat constructor.
Theorem even_256 : isEven 256.
Proof.
prove_even.
Qed.
Print even_256.
|
Section Foo.
Variable X : Type.
Polymorphic Section Bar.
Variable A : Type.
Definition id (a:A) := a.
End Bar.
Check id@{_}.
End Foo.
Check id@{_}.
Polymorphic Section Foo.
Variable A : Type.
Section Bar.
Variable B : Type.
Inductive prod := Prod : A -> B -> prod.
End Bar.
Check prod@{_}.
End Foo.
Check prod@{_ _}.
Section Foo.
Universe K.
Inductive bla := Bla : Type@{K} -> bla.
Polymorphic Definition bli@{j} := Type@{j} -> bla.
Definition bloo := bli@{_}.
Polymorphic Universe i.
Fail Definition x := Type.
Fail Inductive x : Type := .
Polymorphic Definition x := Type.
Polymorphic Inductive y : x := .
Variable A : Type. (* adds a mono univ for the Type, which is unrelated to the others *)
Fail Variable B : (y : Type@{i}).
(* not allowed: mono constraint (about a fresh univ for y) regarding
poly univ i *)
Polymorphic Variable B : Type. (* new polymorphic stuff always OK *)
Variable C : Type@{i}. (* no new univs so no problems *)
Polymorphic Definition thing := bloo -> y -> A -> B.
End Foo.
Check bli@{_}.
Check bloo@{}.
Check thing@{_ _ _}.
Section Foo.
Polymorphic Universes i k.
Universe j.
Fail Constraint i < j.
Fail Constraint i < k.
(* referring to mono univs in poly constraints is OK. *)
Polymorphic Constraint i < j. Polymorphic Constraint j < k.
Polymorphic Definition foo := Type@{j}.
End Foo.
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i32.eqz1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i32.eqz1_tb.vcd");
$dumpvars(0, cpu_tb);
#18
`assert(result, 1);
`assert(result_empty, 0);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); int a, b, c, d; cin >> a >> b >> c >> d; if (a + b <= max(c, d)) cout << Polycarp ; else if (a <= c && b <= d) cout << Polycarp ; else cout << Vasiliy ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 200010; const long long MOD = (int)1e9 + 7; const int INF = 1e9; const long long LLINF = 0x3f3f3f3f3f3f3f3f; const long double EPS = 1e-8; int r, g, h, total; inline int add(int a, int b) { return (a + b) % MOD; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; cin >> r >> g; total = r + g; vector<int> ant(MAX, 0); if (g) ant[r] = 1; if (r) ant[r - 1] = 1; int res = 0; for (int l = 2; true; l++) { vector<int> cur(MAX, 0); bool eita = false; for (int red = 0; red <= r; red++) { long long minus = (l * (l - 1)) / 2 - (r - red); if (minus < 0) continue; int green = g - minus; if (red - l >= 0 and ant[red]) { eita = true; cur[red - l] = add(cur[red - l], ant[red]); } if (green - l >= 0 and ant[red]) { eita = true; cur[red] = add(cur[red], ant[red]); } } if (!eita) break; swap(ant, cur); } for (int red = 0; red <= r; red++) { res = (res + ant[red]) % MOD; } cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int MAXN = (int)5e5 + 5; int n; struct node { int x, y; } a[MAXN]; struct BIT { long long sum[MAXN]; int n; void init(int _n) { n = _n; memset(sum, 0, sizeof(sum)); ; } int lowbit(int x) { return x & -x; } void update(int x, long long num) { while (x <= n) { sum[x] += num; x += lowbit(x); } return; } long long query(int x) { long long ans = 0; while (x) { ans += sum[x]; x -= lowbit(x); } return ans; } } bita; vector<int> v; int getid(int x) { return lower_bound(v.begin(), v.end(), x) - v.begin() + 1; } map<int, int> mpx; int main() { while (~scanf( %d , &n)) { for (int i = 1; i <= n; i++) scanf( %d%d , &a[i].x, &a[i].y), v.push_back(a[i].x), v.push_back(a[i].y); sort(v.begin(), v.end()), v.erase(unique(v.begin(), v.end()), v.end()); for (int i = 1; i <= n; i++) { a[i].x = getid(a[i].x); a[i].y = getid(a[i].y); } sort(a + 1, a + 1 + n, [](node a, node b) { if (a.y != b.y) return a.y > b.y; return a.x < b.x; }); mpx.clear(); bita.init(MAXN); long long ans = 0; for (int i = 1; i <= n; i++) { int xx = a[i].x, yy = a[i].y, pre = 0; int now = i; while (a[now].y == a[i].y && now <= n) { if (!mpx[a[now].x]) { mpx[a[now].x] = 1; bita.update(a[now].x, 1ll); } now++; } now--; for (int j = i; j <= now; j++) { long long l = bita.query(a[j].x - 1) - bita.query(pre); long long r = bita.query(2 * n + 1) - bita.query(a[j].x); pre = a[j].x; ans += (long long)l * r + l + r + 1; } i = now; } printf( %lld n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long int Maxn3 = 1e3 + 10; const long long int Maxn4 = 1e4 + 10; const long long int Maxn5 = 1e5 + 10; const long long int Maxn6 = 1e6 + 10; const long long int Maxn7 = 1e7 + 10; const long long int Maxn8 = 1e8 + 10; const long long int Maxn9 = 1e9 + 10; const long long int Maxn18 = 1e18 + 10; const long long int Mod1 = 1e7 + 7; const long long int Mod2 = 1e9 + 7; const long long int LLMax = LLONG_MAX; const long long int LLMin = LLONG_MIN; const long long int INTMax = INT_MAX; const long long int INTMin = INT_MIN; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long int a, b, n; cin >> a >> b >> n; bool mark[n + 1]; for (long long int i = 0; i <= n; i++) mark[i] = 0; for (long long int i = a; i <= n; i += a) mark[i] = 1; long long int res = 0; for (long long int i = b; i <= n; i += b) if (mark[i]) res++; return cout << res, 0; }
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#include <bits/stdc++.h> using namespace std; bool tep(pair<string, int> a, pair<string, int> b) { return a.second > b.second; } bool f(string s) { for (int i = 0; i < 10; i++) { if ((i == 2 || i == 5) && s[i] != - ) return 0; if ((i != 2 && i != 5) && s[i] == - ) return 0; } if (s.substr(6) != 2013 && s.substr(6) != 2014 && s.substr(6) != 2015 ) return 0; if ((s[3] != 0 && s[4] != 0 && s[4] != 1 && s[4] != 2 ) || s[3] > 1 || (s[3] == 0 && s[4] == 0 )) return 0; if (s.substr(0, 2) == 00 ) return 0; if (s.substr(3, 2) == 02 && (s[0] >= 3 || (s[0] == 2 && s[1] > 8 ))) return 0; if ((s.substr(3, 2) == 04 || s.substr(3, 2) == 06 || s.substr(3, 2) == 09 || s.substr(3, 2) == 11 ) && (s[0] > 3 || (s[0] == 3 && s[1] > 0 ))) return 0; else if (s.substr(3, 2) != 02 && (s[0] > 3 || (s[0] == 3 && s[1] > 1 ))) return 0; return 1; } int main() { string str; vector<pair<string, int> > x; int xn = 0; cin >> str; for (int i = 0; i < str.length() - 9; i++) { string ss = str.substr(i, 10); if (f(ss)) { int j; for (j = 0; j < xn; j++) if (ss == x[j].first) { x[j].second++; break; } if (j == xn) { xn++; x.push_back(make_pair(ss, 1)); } } } pair<string, int> xx[xn]; for (int i = 0; i < xn; i++) { xx[i].first = x[i].first; xx[i].second = x[i].second; } sort(xx, xx + xn, tep); cout << xx[0].first << endl; return 0; }
|
module inst_memory_controll
#(
parameter DATA_WIDTH = 32,
parameter DATA_ADDR_WIDTH = 32,
parameter SRAM_ADDR_WIDTH = 20,
parameter SRAM_DATA_WIDTH = 16
)
(/*autoport*/
input clk,
input rst_n,
output data_rd_en,
output data_wr_en,
output [DATA_ADDR_WIDTH-1:0] data_addr,
input [DATA_WIDTH-1:0] data_in,
output [DATA_WIDTH-1:0] data_out,
//SRAM
output [SRAM_ADDR_WIDTH-1:0] sram_addr,
output sram_ce_n,
inout [SRAM_DATA_WIDTH-1:0] sram_dq,
output sram_lb_n,
output sram_oe_n,
output sram_ub_n,
output sram_we_n
);
//*******************************************************
//Internal
//*******************************************************
//Local Parameters
//Wires
//Registers
//*******************************************************
//General Purpose Signals
//*******************************************************
//*******************************************************
//Outputs
//*******************************************************
//*******************************************************
//Instantiations
//*******************************************************
endmodule
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 20:17:03 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_axi_dma_0_0/system_axi_dma_0_0_stub.v
// Design : system_axi_dma_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_dma,Vivado 2016.4" *)
module system_axi_dma_0_0(s_axi_lite_aclk, m_axi_sg_aclk,
m_axi_mm2s_aclk, m_axi_s2mm_aclk, axi_resetn, s_axi_lite_awvalid, s_axi_lite_awready,
s_axi_lite_awaddr, s_axi_lite_wvalid, s_axi_lite_wready, s_axi_lite_wdata,
s_axi_lite_bresp, s_axi_lite_bvalid, s_axi_lite_bready, s_axi_lite_arvalid,
s_axi_lite_arready, s_axi_lite_araddr, s_axi_lite_rvalid, s_axi_lite_rready,
s_axi_lite_rdata, s_axi_lite_rresp, m_axi_sg_awaddr, m_axi_sg_awlen, m_axi_sg_awsize,
m_axi_sg_awburst, m_axi_sg_awprot, m_axi_sg_awcache, m_axi_sg_awvalid, m_axi_sg_awready,
m_axi_sg_wdata, m_axi_sg_wstrb, m_axi_sg_wlast, m_axi_sg_wvalid, m_axi_sg_wready,
m_axi_sg_bresp, m_axi_sg_bvalid, m_axi_sg_bready, m_axi_sg_araddr, m_axi_sg_arlen,
m_axi_sg_arsize, m_axi_sg_arburst, m_axi_sg_arprot, m_axi_sg_arcache, m_axi_sg_arvalid,
m_axi_sg_arready, m_axi_sg_rdata, m_axi_sg_rresp, m_axi_sg_rlast, m_axi_sg_rvalid,
m_axi_sg_rready, m_axi_mm2s_araddr, m_axi_mm2s_arlen, m_axi_mm2s_arsize,
m_axi_mm2s_arburst, m_axi_mm2s_arprot, m_axi_mm2s_arcache, m_axi_mm2s_arvalid,
m_axi_mm2s_arready, m_axi_mm2s_rdata, m_axi_mm2s_rresp, m_axi_mm2s_rlast,
m_axi_mm2s_rvalid, m_axi_mm2s_rready, mm2s_prmry_reset_out_n, m_axis_mm2s_tdata,
m_axis_mm2s_tkeep, m_axis_mm2s_tvalid, m_axis_mm2s_tready, m_axis_mm2s_tlast,
m_axi_s2mm_awaddr, m_axi_s2mm_awlen, m_axi_s2mm_awsize, m_axi_s2mm_awburst,
m_axi_s2mm_awprot, m_axi_s2mm_awcache, m_axi_s2mm_awvalid, m_axi_s2mm_awready,
m_axi_s2mm_wdata, m_axi_s2mm_wstrb, m_axi_s2mm_wlast, m_axi_s2mm_wvalid,
m_axi_s2mm_wready, m_axi_s2mm_bresp, m_axi_s2mm_bvalid, m_axi_s2mm_bready,
s2mm_prmry_reset_out_n, s_axis_s2mm_tdata, s_axis_s2mm_tkeep, s_axis_s2mm_tvalid,
s_axis_s2mm_tready, s_axis_s2mm_tlast, mm2s_introut, s2mm_introut, axi_dma_tstvec)
/* synthesis syn_black_box black_box_pad_pin="s_axi_lite_aclk,m_axi_sg_aclk,m_axi_mm2s_aclk,m_axi_s2mm_aclk,axi_resetn,s_axi_lite_awvalid,s_axi_lite_awready,s_axi_lite_awaddr[9:0],s_axi_lite_wvalid,s_axi_lite_wready,s_axi_lite_wdata[31:0],s_axi_lite_bresp[1:0],s_axi_lite_bvalid,s_axi_lite_bready,s_axi_lite_arvalid,s_axi_lite_arready,s_axi_lite_araddr[9:0],s_axi_lite_rvalid,s_axi_lite_rready,s_axi_lite_rdata[31:0],s_axi_lite_rresp[1:0],m_axi_sg_awaddr[31:0],m_axi_sg_awlen[7:0],m_axi_sg_awsize[2:0],m_axi_sg_awburst[1:0],m_axi_sg_awprot[2:0],m_axi_sg_awcache[3:0],m_axi_sg_awvalid,m_axi_sg_awready,m_axi_sg_wdata[31:0],m_axi_sg_wstrb[3:0],m_axi_sg_wlast,m_axi_sg_wvalid,m_axi_sg_wready,m_axi_sg_bresp[1:0],m_axi_sg_bvalid,m_axi_sg_bready,m_axi_sg_araddr[31:0],m_axi_sg_arlen[7:0],m_axi_sg_arsize[2:0],m_axi_sg_arburst[1:0],m_axi_sg_arprot[2:0],m_axi_sg_arcache[3:0],m_axi_sg_arvalid,m_axi_sg_arready,m_axi_sg_rdata[31:0],m_axi_sg_rresp[1:0],m_axi_sg_rlast,m_axi_sg_rvalid,m_axi_sg_rready,m_axi_mm2s_araddr[31:0],m_axi_mm2s_arlen[7:0],m_axi_mm2s_arsize[2:0],m_axi_mm2s_arburst[1:0],m_axi_mm2s_arprot[2:0],m_axi_mm2s_arcache[3:0],m_axi_mm2s_arvalid,m_axi_mm2s_arready,m_axi_mm2s_rdata[31:0],m_axi_mm2s_rresp[1:0],m_axi_mm2s_rlast,m_axi_mm2s_rvalid,m_axi_mm2s_rready,mm2s_prmry_reset_out_n,m_axis_mm2s_tdata[31:0],m_axis_mm2s_tkeep[3:0],m_axis_mm2s_tvalid,m_axis_mm2s_tready,m_axis_mm2s_tlast,m_axi_s2mm_awaddr[31:0],m_axi_s2mm_awlen[7:0],m_axi_s2mm_awsize[2:0],m_axi_s2mm_awburst[1:0],m_axi_s2mm_awprot[2:0],m_axi_s2mm_awcache[3:0],m_axi_s2mm_awvalid,m_axi_s2mm_awready,m_axi_s2mm_wdata[31:0],m_axi_s2mm_wstrb[3:0],m_axi_s2mm_wlast,m_axi_s2mm_wvalid,m_axi_s2mm_wready,m_axi_s2mm_bresp[1:0],m_axi_s2mm_bvalid,m_axi_s2mm_bready,s2mm_prmry_reset_out_n,s_axis_s2mm_tdata[31:0],s_axis_s2mm_tkeep[3:0],s_axis_s2mm_tvalid,s_axis_s2mm_tready,s_axis_s2mm_tlast,mm2s_introut,s2mm_introut,axi_dma_tstvec[31:0]" */;
input s_axi_lite_aclk;
input m_axi_sg_aclk;
input m_axi_mm2s_aclk;
input m_axi_s2mm_aclk;
input axi_resetn;
input s_axi_lite_awvalid;
output s_axi_lite_awready;
input [9:0]s_axi_lite_awaddr;
input s_axi_lite_wvalid;
output s_axi_lite_wready;
input [31:0]s_axi_lite_wdata;
output [1:0]s_axi_lite_bresp;
output s_axi_lite_bvalid;
input s_axi_lite_bready;
input s_axi_lite_arvalid;
output s_axi_lite_arready;
input [9:0]s_axi_lite_araddr;
output s_axi_lite_rvalid;
input s_axi_lite_rready;
output [31:0]s_axi_lite_rdata;
output [1:0]s_axi_lite_rresp;
output [31:0]m_axi_sg_awaddr;
output [7:0]m_axi_sg_awlen;
output [2:0]m_axi_sg_awsize;
output [1:0]m_axi_sg_awburst;
output [2:0]m_axi_sg_awprot;
output [3:0]m_axi_sg_awcache;
output m_axi_sg_awvalid;
input m_axi_sg_awready;
output [31:0]m_axi_sg_wdata;
output [3:0]m_axi_sg_wstrb;
output m_axi_sg_wlast;
output m_axi_sg_wvalid;
input m_axi_sg_wready;
input [1:0]m_axi_sg_bresp;
input m_axi_sg_bvalid;
output m_axi_sg_bready;
output [31:0]m_axi_sg_araddr;
output [7:0]m_axi_sg_arlen;
output [2:0]m_axi_sg_arsize;
output [1:0]m_axi_sg_arburst;
output [2:0]m_axi_sg_arprot;
output [3:0]m_axi_sg_arcache;
output m_axi_sg_arvalid;
input m_axi_sg_arready;
input [31:0]m_axi_sg_rdata;
input [1:0]m_axi_sg_rresp;
input m_axi_sg_rlast;
input m_axi_sg_rvalid;
output m_axi_sg_rready;
output [31:0]m_axi_mm2s_araddr;
output [7:0]m_axi_mm2s_arlen;
output [2:0]m_axi_mm2s_arsize;
output [1:0]m_axi_mm2s_arburst;
output [2:0]m_axi_mm2s_arprot;
output [3:0]m_axi_mm2s_arcache;
output m_axi_mm2s_arvalid;
input m_axi_mm2s_arready;
input [31:0]m_axi_mm2s_rdata;
input [1:0]m_axi_mm2s_rresp;
input m_axi_mm2s_rlast;
input m_axi_mm2s_rvalid;
output m_axi_mm2s_rready;
output mm2s_prmry_reset_out_n;
output [31:0]m_axis_mm2s_tdata;
output [3:0]m_axis_mm2s_tkeep;
output m_axis_mm2s_tvalid;
input m_axis_mm2s_tready;
output m_axis_mm2s_tlast;
output [31:0]m_axi_s2mm_awaddr;
output [7:0]m_axi_s2mm_awlen;
output [2:0]m_axi_s2mm_awsize;
output [1:0]m_axi_s2mm_awburst;
output [2:0]m_axi_s2mm_awprot;
output [3:0]m_axi_s2mm_awcache;
output m_axi_s2mm_awvalid;
input m_axi_s2mm_awready;
output [31:0]m_axi_s2mm_wdata;
output [3:0]m_axi_s2mm_wstrb;
output m_axi_s2mm_wlast;
output m_axi_s2mm_wvalid;
input m_axi_s2mm_wready;
input [1:0]m_axi_s2mm_bresp;
input m_axi_s2mm_bvalid;
output m_axi_s2mm_bready;
output s2mm_prmry_reset_out_n;
input [31:0]s_axis_s2mm_tdata;
input [3:0]s_axis_s2mm_tkeep;
input s_axis_s2mm_tvalid;
output s_axis_s2mm_tready;
input s_axis_s2mm_tlast;
output mm2s_introut;
output s2mm_introut;
output [31:0]axi_dma_tstvec;
endmodule
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
`define SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__maj3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X, and1_out, and0_out);
buf buf0 (X , or1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MAJ3_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 0; cin >> t; for (int i = 0; i < t; i++) { long long m = 0; int n = 0; cin >> n; for (int j = n; j > 2; j -= 2) { m += (2 * pow((j - 1), 2)); } cout << m << endl; } }
|
`timescale 1ns / 1ps
// @module
// decode 8421 bcd code to segment code
// seg_data[7:0]a: dp-G-F-E-D-C-B-A
// @input
// bcd_data: raw bcd(8421) code
// @output
// seg_data: 8 bit seg_data binding to board
module bcd_to_segment
(
input [3:0] bcd_data,
output reg [7:0] seg_data
);
always @(bcd_data) begin
case (bcd_data)
4'b0000: seg_data <= 8'b11000000; // 0
4'b0001: seg_data <= 8'b11111001; // 1
4'b0010: seg_data <= 8'b10100100; // 2
4'b0011: seg_data <= 8'b10110000; // 3
4'b0100: seg_data <= 8'b10011001; // 4
4'b0101: seg_data <= 8'b10010010; // 5
4'b0110: seg_data <= 8'b10000010; // 6
4'b0111: seg_data <= 8'b11111000; // 7
4'b1000: seg_data <= 8'b10000000; // 8
4'b1001: seg_data <= 8'b10010000; // 9
4'b1010: seg_data <= 8'b01111111; // dp
default: seg_data <= 8'b11111111; // off
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const int TMXN = 1e6 * 4 + 1; const int INF = 1e9 + 7; const long long INFL = 1e18; int n, k; char a[N]; int mink = INF; int pref[N]; int main() { cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; if (!(a[i] - 48)) { pref[i] = pref[i - 1] + 1; } else { pref[i] = pref[i - 1]; } } for (int i = n + 1; i <= N; i++) { pref[i] = pref[i - 1]; } for (int i = 1; i <= n; i++) { int l = 0; int r = max(n - i, i - 1) + 1; if (a[i] == 0 ) { while (r - l > 1) { int mid = (r + l) / 2; if (pref[i + mid] - pref[max(i - mid - 1, 0)] >= k + 1) { r = mid; } else { l = mid; } } if (pref[i + r] - pref[max(i - r - 1, 0)] >= k + 1) { mink = min(mink, r); } if (pref[i + l] - pref[max(i - l - 1, 0)] >= k + 1) { mink = min(mink, l); } } } cout << mink; return 0; }
|
// psi2c_bitsend.v
`timescale 1 ns / 1 ps
module psi2c_bitsend
(
input clk,
input sync,
input reset,
input phase,
input go,
input empty,
output rd,
output busy,
input [11:0]d,
output reg sda
);
reg goff;
wire hold;
// latch = {empty, d[10]=p, d[1:0] = data[1:0]}
reg [3:0]latch;
always @(*) if (!hold) latch <= reset ? 4'b0000 : {!empty, d[10], d[1:0]};
wire s = d[11]; // i2c start
wire p = latch[2]; // i2c stop
wire [9:0]data = {d[9:2], latch[1:0]}; // i2c data (10 bit)
wire em = !latch[3]; // empty
// state machine
localparam sm_idle = 6'b000000; // idle
localparam sm_load = 6'b010000; // read fifo
localparam sm_wait = 6'b010001; // wait for go
localparam sm_start1 = 6'b010010; // generate i2c start
localparam sm_start2 = 6'b010011; // i2c start -> i2c stop
localparam sm_bit0 = 6'b100000; // send bit0 (last)
localparam sm_bit1 = 6'b100001;
localparam sm_bit2 = 6'b100010;
localparam sm_bit3 = 6'b100011;
localparam sm_bit4 = 6'b100100;
localparam sm_bit5 = 6'b100101;
localparam sm_bit6 = 6'b100110;
localparam sm_bit7 = 6'b100111;
localparam sm_bit8 = 6'b101000;
localparam sm_bit9 = 6'b101001; // send bit 9 (first)
localparam sm_stop = 6'b010100; // generate i2c stop
// sequencer
reg [5:0]sm;
always @(posedge clk or posedge reset)
begin
if (reset) sm <= sm_idle;
else if (sync)
case (sm)
sm_idle: if (goff && em) sm <= sm_start2; // start-stop sequence
else if (!em) sm <= sm_load; // regular data sequence
sm_start2: sm <= sm_stop;
sm_load: sm <= sm_wait;
sm_wait: if (goff) sm <= s ? sm_start1 : sm_bit9;
sm_start1: sm <= sm_bit9;
sm_bit9: sm <= sm_bit8;
sm_bit8: sm <= sm_bit7;
sm_bit7: sm <= sm_bit6;
sm_bit6: sm <= sm_bit5;
sm_bit5: sm <= sm_bit4;
sm_bit4: sm <= sm_bit3;
sm_bit3: sm <= sm_bit2;
sm_bit2: sm <= sm_bit1;
sm_bit1: sm <= sm_bit0;
sm_bit0: if (p) sm <= sm_stop;
else if (em) sm <= sm_idle;
else sm <= s ? sm_start1 : sm_bit9;
sm_stop: if (em) sm <= sm_idle;
else sm <= s ? sm_start1 : sm_bit9;
default: sm <= sm_idle;
endcase
end
// sda assignment
always @(*)
begin
case (sm)
sm_start1: sda <= phase;
sm_start2: sda <= phase;
sm_bit0: sda <= data[0];
sm_bit1: sda <= data[1];
sm_bit2: sda <= data[2];
sm_bit3: sda <= data[3];
sm_bit4: sda <= data[4];
sm_bit5: sda <= data[5];
sm_bit6: sda <= data[6];
sm_bit7: sda <= data[7];
sm_bit8: sda <= data[8];
sm_bit9: sda <= data[9];
sm_stop: sda <= !phase;
default: sda <= 1;
endcase
end
assign hold = (sm == sm_bit1) || (sm == sm_bit0);
assign busy = (sm != sm_idle) && (sm != sm_load) && (sm != sm_wait);
// go srff
always @(posedge clk or posedge reset)
begin
if (reset) goff <= 0;
else if ((sm == sm_bit9) || (sm == sm_start2)) goff <= 0;
else if (go) goff <= 1;
end
// fifo read ff
reg rdff;
always @(posedge clk or posedge reset)
begin
if (reset) rdff <= 0;
else rdff <= (sm == sm_load) || (sm == sm_bit1);
end
assign rd = rdff && sync;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:50:20 11/21/2016
// Design Name:
// Module Name: num_chooser
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module num_chooser(
output reg [4:0] res_out_code,
input wire [2:0] res_in_row,
input wire [3:0] num_salida
);
wire [4:0] d0, d1, d2, d3, d4, d5, d6, d7, d8, d9;
num_0 n0 (
.in_row(res_in_row),
.out_code(d0)
);
num_1 n1 (
.in_row(res_in_row),
.out_code(d1)
);
num_2 n2 (
.in_row(res_in_row),
.out_code(d2)
);
num_3 n3 (
.in_row(res_in_row),
.out_code(d3)
);
num_4 n4 (
.in_row(res_in_row),
.out_code(d4)
);
num_5 n5 (
.in_row(res_in_row),
.out_code(d5)
);
num_6 n6 (
.in_row(res_in_row),
.out_code(d6)
);
num_7 n7 (
.in_row(res_in_row),
.out_code(d7)
);
num_8 n8 (
.in_row(res_in_row),
.out_code(d8)
);
num_9 n9 (
.in_row(res_in_row),
.out_code(d9)
);
always @ *
begin
case (num_salida)
4'b0000: res_out_code = d0;
4'b0001: res_out_code = d1;
4'b0010: res_out_code = d2;
4'b0011: res_out_code = d3;
4'b0100: res_out_code = d4;
4'b0101: res_out_code = d5;
4'b0110: res_out_code = d6;
4'b0111: res_out_code = d7;
4'b1000: res_out_code = d8;
4'b1001: res_out_code = d9;
default: res_out_code = 5'b0;
endcase
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Module: meter_lite
//
// Description:
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module meter_lite#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2
)(
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
output out_wr,
input out_rdy,
input [31:0] data_meter_i,
input [31:0] addr_meter_i,
input req_meter_i,
input rw_meter_i,
output ack_meter_o,
output [31:0] data_meter_o,
input clk,
input reset
);
localparam NUM_QUEUES = 4;
wire [DATA_WIDTH-1:0] rate_limiter_in_data [NUM_QUEUES - 1 : 0];
wire [CTRL_WIDTH-1:0] rate_limiter_in_ctrl [NUM_QUEUES - 1 : 0];
wire [NUM_QUEUES - 1 : 0] rate_limiter_in_wr;
wire [NUM_QUEUES - 1 : 0] rate_limiter_in_rdy;
wire [DATA_WIDTH-1:0] rate_limiter_pass_data;
wire [CTRL_WIDTH-1:0] rate_limiter_pass_ctrl;
wire rate_limiter_pass_wr;
wire rate_limiter_pass_rdy;
wire [DATA_WIDTH-1:0] rate_limiter_out_data [NUM_QUEUES - 1 : 0];
wire [CTRL_WIDTH-1:0] rate_limiter_out_ctrl [NUM_QUEUES - 1 : 0];
wire [NUM_QUEUES - 1 : 0] rate_limiter_out_wr;
wire [NUM_QUEUES - 1 : 0] rate_limiter_out_rdy;
wire [19:0] token_interval ;
wire [7:0] token_increment ;
wire [NUM_QUEUES-1:0] token_interval_vld;
wire [NUM_QUEUES-1:0] token_increment_vld;
wire [31:0] pass_pkt_counter_0 ;
wire [31:0] pass_pkt_counter_1 ;
wire [31:0] pass_pkt_counter_2 ;
wire [31:0] pass_pkt_counter_3 ;
wire [31:0] pass_pkt_counter_4 ;
wire [31:0] pass_byte_counter_0 ;
wire [31:0] pass_byte_counter_1 ;
wire [31:0] pass_byte_counter_2 ;
wire [31:0] pass_byte_counter_3 ;
wire [31:0] pass_byte_counter_4 ;
wire [31:0] drop_pkt_counter_0 ;
wire [31:0] drop_pkt_counter_1 ;
wire [31:0] drop_pkt_counter_2 ;
wire [31:0] drop_pkt_counter_3 ;
wire [31:0] drop_pkt_counter_4 ;
wire [31:0] drop_byte_counter_0 ;
wire [31:0] drop_byte_counter_1 ;
wire [31:0] drop_byte_counter_2 ;
wire [31:0] drop_byte_counter_3 ;
wire [31:0] drop_byte_counter_4 ;
queue_splitter #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_QUEUES(NUM_QUEUES+1)
) queue_splitter (
// --- Interface to the previous module
.in_data (in_data),
.in_ctrl (in_ctrl),
.in_rdy (in_rdy),
.in_wr (in_wr),
.out_data_0 (rate_limiter_in_data[0]),
.out_ctrl_0 (rate_limiter_in_ctrl[0]),
.out_wr_0 (rate_limiter_in_wr[0]),
.out_rdy_0 (rate_limiter_in_rdy[0]),
.out_data_1 (rate_limiter_in_data[1]),
.out_ctrl_1 (rate_limiter_in_ctrl[1]),
.out_wr_1 (rate_limiter_in_wr[1]),
.out_rdy_1 (rate_limiter_in_rdy[1]),
.out_data_2 (rate_limiter_in_data[2]),
.out_ctrl_2 (rate_limiter_in_ctrl[2]),
.out_wr_2 (rate_limiter_in_wr[2]),
.out_rdy_2 (rate_limiter_in_rdy[2]),
.out_data_3 (rate_limiter_in_data[3]),
.out_ctrl_3 (rate_limiter_in_ctrl[3]),
.out_wr_3 (rate_limiter_in_wr[3]),
.out_rdy_3 (rate_limiter_in_rdy[3]),
.out_data_4 (rate_limiter_pass_data),
.out_ctrl_4 (rate_limiter_pass_ctrl),
.out_wr_4 (rate_limiter_pass_wr),
.out_rdy_4 (rate_limiter_pass_rdy),
// --- Misc
.clk (clk),
.reset (reset),
.pass_pkt_counter_0 (pass_pkt_counter_0 ),
.pass_pkt_counter_1 (pass_pkt_counter_1 ),
.pass_pkt_counter_2 (pass_pkt_counter_2 ),
.pass_pkt_counter_3 (pass_pkt_counter_3 ),
.pass_pkt_counter_4 (pass_pkt_counter_4 ),
.pass_byte_counter_0 (pass_byte_counter_0),
.pass_byte_counter_1 (pass_byte_counter_1),
.pass_byte_counter_2 (pass_byte_counter_2),
.pass_byte_counter_3 (pass_byte_counter_3),
.pass_byte_counter_4 (pass_byte_counter_4),
.drop_pkt_counter_0 (drop_pkt_counter_0 ),
.drop_pkt_counter_1 (drop_pkt_counter_1 ),
.drop_pkt_counter_2 (drop_pkt_counter_2 ),
.drop_pkt_counter_3 (drop_pkt_counter_3 ),
.drop_pkt_counter_4 (drop_pkt_counter_4 ),
.drop_byte_counter_0 (drop_byte_counter_0),
.drop_byte_counter_1 (drop_byte_counter_1),
.drop_byte_counter_2 (drop_byte_counter_2),
.drop_byte_counter_3 (drop_byte_counter_3),
.drop_byte_counter_4 (drop_byte_counter_4)
);
generate
genvar i;
for (i = 0; i < NUM_QUEUES; i = i + 1) begin : rate_limiter_modules
rate_limiter #(
.DATA_WIDTH (DATA_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.RATE_LIMIT_BLOCK_TAG ( i),
.DEFAULT_TOKEN_INTERVAL (1 + i)
) rate_limiter
(
.out_data (rate_limiter_out_data[i]),
.out_ctrl (rate_limiter_out_ctrl[i]),
.out_wr (rate_limiter_out_wr[i]),
.out_rdy (rate_limiter_out_rdy[i]),
.in_data (rate_limiter_in_data[i]),
.in_ctrl (rate_limiter_in_ctrl[i]),
.in_wr (rate_limiter_in_wr[i]),
.in_rdy (rate_limiter_in_rdy[i]),
.token_interval_vld (token_interval_vld[i]),
.token_increment_vld (token_increment_vld[i]),
.token_interval_reg (token_interval ),
.token_increment_reg (token_increment ),
// --- Misc
.clk (clk),
.reset (reset)
);
end
endgenerate
rate_limiter_regs
#(
.NUM_QUEUES(NUM_QUEUES)
)
rate_limiter_regs
(
.data_meter_i (data_meter_i) ,
.addr_meter_i (addr_meter_i) ,
.req_meter_i (req_meter_i ) ,
.rw_meter_i (rw_meter_i ) ,
.ack_meter_o (ack_meter_o ) ,
.data_meter_o (data_meter_o) ,
// Outputs
.token_interval (token_interval),
.token_increment (token_increment),
.token_interval_vld (token_interval_vld),
.token_increment_vld (token_increment_vld),
//.include_overhead (include_overhead),
// Inputs
.clk (clk),
.reset (reset),
.pass_pkt_counter_0 (pass_pkt_counter_0 ),
.pass_pkt_counter_1 (pass_pkt_counter_1 ),
.pass_pkt_counter_2 (pass_pkt_counter_2 ),
.pass_pkt_counter_3 (pass_pkt_counter_3 ),
.pass_pkt_counter_4 (pass_pkt_counter_4 ),
.pass_byte_counter_0 (pass_byte_counter_0),
.pass_byte_counter_1 (pass_byte_counter_1),
.pass_byte_counter_2 (pass_byte_counter_2),
.pass_byte_counter_3 (pass_byte_counter_3),
.pass_byte_counter_4 (pass_byte_counter_4),
.drop_pkt_counter_0 (drop_pkt_counter_0 ),
.drop_pkt_counter_1 (drop_pkt_counter_1 ),
.drop_pkt_counter_2 (drop_pkt_counter_2 ),
.drop_pkt_counter_3 (drop_pkt_counter_3 ),
.drop_pkt_counter_4 (drop_pkt_counter_4 ),
.drop_byte_counter_0 (drop_byte_counter_0),
.drop_byte_counter_1 (drop_byte_counter_1),
.drop_byte_counter_2 (drop_byte_counter_2),
.drop_byte_counter_3 (drop_byte_counter_3),
.drop_byte_counter_4 (drop_byte_counter_4)
);
queue_aggr #(
.NUM_QUEUES(NUM_QUEUES+1),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH)
) queue_aggr (
.out_data (out_data),
.out_ctrl (out_ctrl),
.out_wr (out_wr),
.out_rdy (out_rdy),
// --- Interface to the input queues
.in_data_0 (rate_limiter_out_data[0]),
.in_ctrl_0 (rate_limiter_out_ctrl[0]),
.in_wr_0 (rate_limiter_out_wr[0]),
.in_rdy_0 (rate_limiter_out_rdy[0]),
.in_data_1 (rate_limiter_out_data[1]),
.in_ctrl_1 (rate_limiter_out_ctrl[1]),
.in_wr_1 (rate_limiter_out_wr[1]),
.in_rdy_1 (rate_limiter_out_rdy[1]),
.in_data_2 (rate_limiter_out_data[2]),
.in_ctrl_2 (rate_limiter_out_ctrl[2]),
.in_wr_2 (rate_limiter_out_wr[2]),
.in_rdy_2 (rate_limiter_out_rdy[2]),
.in_data_3 (rate_limiter_out_data[3]),
.in_ctrl_3 (rate_limiter_out_ctrl[3]),
.in_wr_3 (rate_limiter_out_wr[3]),
.in_rdy_3 (rate_limiter_out_rdy[3]),
.in_data_4 (rate_limiter_pass_data),
.in_ctrl_4 (rate_limiter_pass_ctrl),
.in_wr_4 (rate_limiter_pass_wr),
.in_rdy_4 (rate_limiter_pass_rdy),
/*
.in_data_5 (in_data_5),
.in_ctrl_5 (in_ctrl_5),
.in_wr_5 (in_wr_5),
.in_rdy_5 (in_rdy_5),
.in_data_6 (in_data_6),
.in_ctrl_6 (in_ctrl_6),
.in_wr_6 (in_wr_6),
.in_rdy_6 (in_rdy_6),
.in_data_7 (in_data_7),
.in_ctrl_7 (in_ctrl_7),
.in_wr_7 (in_wr_7),
.in_rdy_7 (in_rdy_7),
*/
// --- Misc
.reset (reset),
.clk (clk)
);
endmodule // meter_lite
|
#include <bits/stdc++.h> using namespace std; inline long long sum(long long x) { x %= 1000000007; return (1LL * x * (x + 1) / 2) % 1000000007; } int main() { long long n, m; ios::sync_with_stdio(false); cin >> n >> m; long long ans = ((n % 1000000007) * (m % 1000000007)) % 1000000007; int rad = sqrt(n); for (int i = 1; i <= n / (rad + 1) && i <= m; i++) { ans -= (1LL * i * (n / i)) % 1000000007; if (ans < 0) ans += 1000000007; } for (int i = 1; i <= rad; i++) { ans -= (1LL * i * (sum(min(n / i, m)) - sum(min(n / (i + 1), m)) + 1000000007)) % 1000000007; if (ans < 0) ans += 1000000007; } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4BB_1_V
`define SKY130_FD_SC_HS__OR4BB_1_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4bb_1 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4bb_1 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4BB_1_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module feedforward_p_uOut_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk);
parameter DWIDTH = 32;
parameter AWIDTH = 8;
parameter MEM_SIZE = 140;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module feedforward_p_uOut(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd140;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
feedforward_p_uOut_ram feedforward_p_uOut_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long binpow(long long a, long long b) { a = a % 1000000007; long long res = 1; while (b > 0) { if (b & 1) res *= a % 1000000007; a = a * a % 1000000007; b = b >> 1; } return res; } void speedup() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } int dx[] = {1, -1, 2, 2, -2, -2, 1, -1}; int dy[] = {2, 2, 1, -1, 1, -1, -2, -2}; int bfs(int sx, int sy, int desx, int desy) { int vis[9][9]; int d[9][9]; for (int i = 1; i <= 8; i++) { for (int j = 1; j <= 8; j++) { vis[i][j] = 0; d[i][j] = 0; } } vis[sx][sy] = 1; queue<pair<int, int> > q; q.push(pair<int, int>(sx, sy)); while (!q.empty()) { pair<int, int> top = q.front(); q.pop(); for (int i = 0; i < 8; i++) { int tx = top.first + dx[i]; int ty = top.second + dy[i]; if (tx >= 1 && tx <= 8 && ty >= 1 && ty <= 8 && vis[tx][ty] == 0) { vis[tx][ty] = 1; d[tx][ty] = d[top.first][top.second] + 1; q.push(pair<int, int>(tx, ty)); } } } return d[desx][desy]; } int main() { speedup(); int n; cin >> n; int a[n], l[n], r[n]; for (int i = 0; i < n; i++) cin >> l[i]; for (int i = 0; i < n; i++) cin >> r[i]; for (int i = 0; i < n; i++) a[i] = n - l[i] - r[i]; for (int i = 0; i < n; i++) { for (int j = 0; j < i; j++) { l[i] -= (a[j] > a[i]); } } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { r[i] -= (a[j] > a[i]); } } for (int i = 0; i < n; i++) { if (l[i] != 0 || r[i] != 0) { cout << NO n ; return 0; } } cout << YES n ; for (int i = 0; i < n; i++) cout << a[i] << ; cout << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__CLKINVLP_BEHAVIORAL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; vector<long long> v(2000000); for (long long i = 0; i < 2000000; i++) v[i] = 0; for (long long i = 0; i < n; i++) { long long t1; cin >> t1; v[t1]++; } long long t = 0; long long l = 1; long long r = 1000000; while (n > 0) { t++; l++; r--; if (v[l]) n--; if (v[r]) n--; } cout << t; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_SYMBOL_V
`define SKY130_FD_SC_MS__NOR4BB_SYMBOL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/);
initial begin
int q[int];
int qe[int]; // Empty
int qv[$]; // Value returns
int qi[$]; // Index returns
int i;
string v;
q = '{10:1, 11:2, 12:2, 13:4, 14:3};
v = $sformatf("%p", q); `checks(v, "'{'ha:'h1, 'hb:'h2, 'hc:'h2, 'hd:'h4, 'he:'h3} ");
// NOT tested: with ... selectors
//q.sort; // Not legal on assoc - see t_assoc_meth_bad
//q.rsort; // Not legal on assoc - see t_assoc_meth_bad
//q.reverse; // Not legal on assoc - see t_assoc_meth_bad
//q.shuffle; // Not legal on assoc - see t_assoc_meth_bad
v = $sformatf("%p", qe); `checks(v, "'{}");
qv = q.unique;
v = $sformatf("%p", qv); `checks(v, "'{'h1, 'h2, 'h4, 'h3} ");
qv = qe.unique;
v = $sformatf("%p", qv); `checks(v, "'{}");
qi = q.unique_index; qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{'ha, 'hb, 'hd, 'he} ");
qi = qe.unique_index;
v = $sformatf("%p", qi); `checks(v, "'{}");
// These require an with clause or are illegal
// TODO add a lint check that with clause is provided
qv = q.find with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2, 'h2} ");
qv = q.find_first with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
qv = q.find_last with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
qv = q.find with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = q.find_first with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = q.find_last with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qi = q.find_index with (item == 2); qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{'hb, 'hc} ");
qi = q.find_first_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{'hb} ");
qi = q.find_last_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{'hc} ");
qi = q.find_index with (item == 20); qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_first_index with (item == 20);
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_last_index with (item == 20);
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_index with (item.index == 12);
v = $sformatf("%p", qi); `checks(v, "'{'hc} ");
qi = q.find with (item.index == 12);
v = $sformatf("%p", qi); `checks(v, "'{'h2} ");
qv = q.min;
v = $sformatf("%p", qv); `checks(v, "'{'h1} ");
qv = q.max;
v = $sformatf("%p", qv); `checks(v, "'{'h4} ");
qv = qe.min;
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = qe.max;
v = $sformatf("%p", qv); `checks(v, "'{}");
// Reduction methods
i = q.sum;
`checkh(i, 32'hc);
i = q.sum with (item + 1);
`checkh(i, 32'h11);
i = q.product;
`checkh(i, 32'h30);
i = q.product with (item + 1);
`checkh(i, 32'h168);
i = qe.sum;
`checkh(i, 32'h0);
i = qe.product;
`checkh(i, 32'h0);
q = '{10:32'b1100, 11:32'b1010};
i = q.and;
`checkh(i, 32'b1000);
i = q.and with (item + 1);
`checkh(i, 32'b1001);
i = q.or;
`checkh(i, 32'b1110);
i = q.or with (item + 1);
`checkh(i, 32'b1111);
i = q.xor;
`checkh(i, 32'b0110);
i = q.xor with (item + 1);
`checkh(i, 32'b0110);
i = qe.and;
`checkh(i, 32'b0);
i = qe.or;
`checkh(i, 32'b0);
i = qe.xor;
`checkh(i, 32'b0);
i = q.and();
`checkh(i, 32'b1000);
i = q.and() with (item + 1);
`checkh(i, 32'b1001);
i = q.or();
`checkh(i, 32'b1110);
i = q.or() with (item + 1);
`checkh(i, 32'b1111);
i = q.xor();
`checkh(i, 32'b0110);
i = q.xor() with (item + 1);
`checkh(i, 32'b0110);
i = qe.and();
`checkh(i, 32'b0);
i = qe.or();
`checkh(i, 32'b0);
i = qe.xor();
`checkh(i, 32'b0);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, sum = 1; cin >> n; sum += 6 * ((n * (n + 1)) / 2); cout << sum << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BO_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A21BO_FUNCTIONAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BO_FUNCTIONAL_PP_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
// Very simple test for interface pathclearing
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc #(2) itopa();
ifc #(4) itopb();
sub ca (.isub(itopa.out_modport),
.clk);
sub cb (.isub(itopb.out_modport),
.clk);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d result=%b %b\n",$time, cyc, itopa.valueo, itopb.valueo);
`endif
cyc <= cyc + 1;
itopa.valuei <= cyc[1:0];
itopb.valuei <= cyc[3:0];
if (cyc==1) begin
if (itopa.WIDTH != 2) $stop;
if (itopb.WIDTH != 4) $stop;
if ($bits(itopa.valueo) != 2) $stop;
if ($bits(itopb.valueo) != 4) $stop;
if ($bits(itopa.out_modport.valueo) != 2) $stop;
if ($bits(itopb.out_modport.valueo) != 4) $stop;
end
if (cyc==4) begin
if (itopa.valueo != 2'b11) $stop;
if (itopb.valueo != 4'b0011) $stop;
end
if (cyc==5) begin
if (itopa.valueo != 2'b00) $stop;
if (itopb.valueo != 4'b0100) $stop;
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
interface ifc
#(parameter WIDTH = 1);
// verilator lint_off MULTIDRIVEN
logic [WIDTH-1:0] valuei;
logic [WIDTH-1:0] valueo;
// verilator lint_on MULTIDRIVEN
modport out_modport (input valuei, output valueo);
endinterface
// Note not parameterized
module sub
(
ifc.out_modport isub,
input clk
);
always @(posedge clk) isub.valueo <= isub.valuei + 1;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013.
// SPDX-License-Identifier: CC0-1.0
// bug648
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] datai = crc[7:0];
wire enable = crc[8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [7:0] datao; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.datao (datao[7:0]),
// Inputs
.clk (clk),
.datai (datai[7:0]),
.enable (enable));
// Aggregate outputs into a single result vector
wire [63:0] result = {56'h0, datao};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h9d550d82d38926fa
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`define FAIL 1
module Nested
(
input logic clk,
input logic x,
output logic y
);
logic t;
always_comb t = x ^ 1'b1;
always_ff @(posedge clk) begin
if (clk)
y <= t;
end
endmodule
module Test
(
input logic clk,
input logic [7:0] datai,
input logic enable,
output logic [7:0] datao
);
// verilator lint_off BLKANDNBLK
logic [7:0] datat;
// verilator lint_on BLKANDNBLK
for (genvar i = 0; i < 8; i++) begin
if (i%4 != 3) begin
`ifndef FAIL
logic t;
always_comb begin
t = datai[i] ^ 1'b1;
end
always_ff @(posedge clk) begin
if (clk)
datat[i] <= t;
end
`else
Nested nested_i
(
.clk(clk),
.x(datai[i]),
.y(datat[i]) //<== via Vcellout wire
);
`endif
always_comb begin
casez (enable)
1'b1: datao[i] = datat[i];
1'b0: datao[i] = '0;
default: datao[i] = 'x;
endcase
end
end
else begin
always_ff @(posedge clk) begin
if (clk)
datat[i] <= 0; //<== assign delayed
end
always_comb begin
casez (enable)
1'b1: datao[i] = datat[i] ^ 1'b1;
1'b0: datao[i] = '1;
default: datao[i] = 'x;
endcase
end
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_fsub(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, o_dataout_valid, i_stall);
parameter DATA_WIDTH = 32;
parameter LATENCY = 8;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
wire [DATA_WIDTH-1:0] dataa, datab, datab_neg;
wire is_fifo_a_valid, is_fifo_b_valid;
wire is_fifo_stalled, is_fsub_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_fifo_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_fifo_stalled = ~(is_fifo_a_valid & is_fifo_b_valid) | is_fsub_stalled;
assign datab_neg = {~datab[DATA_WIDTH-1],datab[DATA_WIDTH-2:0]};
acl_fp_custom_add_ll_hc fsub_unit(
.clock(clock), .resetn(resetn), .dataa(dataa), .datab(datab_neg),
.result(o_dataout), .valid_in(is_fifo_a_valid & is_fifo_b_valid),
.valid_out(o_dataout_valid),
.stall_in(i_stall), .stall_out(is_fsub_stalled));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__BUFBUF_PP_BLACKBOX_V
/**
* bufbuf: Double buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__bufbuf (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_PP_BLACKBOX_V
|
// ghrd_10as066n2_pr_region_controller_0_altera_pr_region_controller_171_lvntgla.v
// This file was auto-generated from altera_pr_region_controller_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_pr_region_controller_0_altera_pr_region_controller_171_lvntgla (
input wire avl_csr_read, // avl_csr.read
input wire avl_csr_write, // .write
input wire [1:0] avl_csr_address, // .address
input wire [31:0] avl_csr_writedata, // .writedata
output wire [31:0] avl_csr_readdata, // .readdata
output wire bridge_freeze0_freeze, // bridge_freeze0.freeze
input wire bridge_freeze0_illegal_request, // .illegal_request
output wire bridge_freeze1_freeze, // bridge_freeze1.freeze
input wire bridge_freeze1_illegal_request, // .illegal_request
input wire clock_clk, // clock.clk
output wire pr_handshake_start_req, // pr_handshake.start_req
input wire pr_handshake_start_ack, // .start_ack
output wire pr_handshake_stop_req, // .stop_req
input wire pr_handshake_stop_ack, // .stop_ack
input wire reset_reset, // reset.reset
output wire reset_source_reset // reset_source.reset
);
wire freeze_control_freeze_if_freeze_in; // freeze_control:freeze -> conduit_merger:freeze_in
wire [1:0] conduit_merger_conduit_ctrl_if_illegal_request_out; // conduit_merger:illegal_request_out -> freeze_control:illegal_request
wire [1:0] freeze_control_conduit_control_illegal_req; // freeze_control:illegal_req -> freeze_csr:illegal_req
wire freeze_csr_conduit_control_freeze_req; // freeze_csr:freeze_req -> freeze_control:freeze_req
wire freeze_csr_conduit_control_unfreeze_req; // freeze_csr:unfreeze_req -> freeze_control:unfreeze_req
wire freeze_control_conduit_control_unfreeze_status; // freeze_control:unfreeze_status -> freeze_csr:unfreeze_status
wire freeze_csr_conduit_control_reset; // freeze_csr:reset_req -> freeze_control:reset_req
wire freeze_control_conduit_control_freeze_status; // freeze_control:freeze_status -> freeze_csr:freeze_status
altera_freeze_control #(
.NUM_INTF_BRIDGE (2)
) freeze_control (
.clk (clock_clk), // input, width = 1, clock_sink.clk
.reset_n (~reset_reset), // input, width = 1, reset.reset_n
.start_req (pr_handshake_start_req), // output, width = 1, pr_handshake.start_req
.start_ack (pr_handshake_start_ack), // input, width = 1, .start_ack
.stop_req (pr_handshake_stop_req), // output, width = 1, .stop_req
.stop_ack (pr_handshake_stop_ack), // input, width = 1, .stop_ack
.freeze_status (freeze_control_conduit_control_freeze_status), // output, width = 1, conduit_control.freeze_status
.freeze_req (freeze_csr_conduit_control_freeze_req), // input, width = 1, .freeze_req
.unfreeze_req (freeze_csr_conduit_control_unfreeze_req), // input, width = 1, .unfreeze_req
.unfreeze_status (freeze_control_conduit_control_unfreeze_status), // output, width = 1, .unfreeze_status
.reset_req (freeze_csr_conduit_control_reset), // input, width = 1, .reset
.illegal_req (freeze_control_conduit_control_illegal_req), // output, width = 2, .illegal_req
.freeze (freeze_control_freeze_if_freeze_in), // output, width = 1, freeze_if.freeze_in
.illegal_request (conduit_merger_conduit_ctrl_if_illegal_request_out), // input, width = 2, .illegal_request_out
.region_reset (reset_source_reset) // output, width = 1, reset_source.reset
);
ghrd_10as066n2_pr_region_controller_0_altera_conduit_merger_171_nva7cjy #(
.NUM_INTF_BRIDGE (2)
) conduit_merger (
.freeze_in (freeze_control_freeze_if_freeze_in), // input, width = 1, conduit_ctrl_if.freeze_in
.illegal_request_out (conduit_merger_conduit_ctrl_if_illegal_request_out), // output, width = 2, .illegal_request_out
.freeze0 (bridge_freeze0_freeze), // output, width = 1, conduit_bridge_if0.freeze
.illegal_request0 (bridge_freeze0_illegal_request), // input, width = 1, .illegal_request
.freeze1 (bridge_freeze1_freeze), // output, width = 1, conduit_bridge_if1.freeze
.illegal_request1 (bridge_freeze1_illegal_request), // input, width = 1, .illegal_request
.pr_freeze0 () // (terminated),
);
altera_freeze_csr #(
.NUM_INTF_BRIDGE (2)
) freeze_csr (
.clk (clock_clk), // input, width = 1, clock_sink.clk
.reset_n (~reset_reset), // input, width = 1, reset.reset_n
.avl_csr_read (avl_csr_read), // input, width = 1, avl_csr.read
.avl_csr_write (avl_csr_write), // input, width = 1, .write
.avl_csr_addr (avl_csr_address), // input, width = 2, .address
.avl_csr_wrdata (avl_csr_writedata), // input, width = 32, .writedata
.avl_csr_rddata (avl_csr_readdata), // output, width = 32, .readdata
.freeze_status (freeze_control_conduit_control_freeze_status), // input, width = 1, conduit_control.freeze_status
.freeze_req (freeze_csr_conduit_control_freeze_req), // output, width = 1, .freeze_req
.unfreeze_req (freeze_csr_conduit_control_unfreeze_req), // output, width = 1, .unfreeze_req
.reset_req (freeze_csr_conduit_control_reset), // output, width = 1, .reset
.unfreeze_status (freeze_control_conduit_control_unfreeze_status), // input, width = 1, .unfreeze_status
.illegal_req (freeze_control_conduit_control_illegal_req), // input, width = 2, .illegal_req
.irq () // (terminated),
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; vector<int> edges[(200 * 1000 + 5)]; vector<int> f; vector<int> a; int dp[(200 * 1000 + 5)][5]; void read_data() { cin >> n; int u, v; for (int i = 1; i < n; i++) { scanf( %d %d , &u, &v); edges[u].push_back(v); edges[v].push_back(u); } } void bfs() { int qf, ql; a.resize(n); f.resize(n + 1); vector<int> isv; isv.resize(n + 1); qf = ql = 0; a[ql++] = 1; isv[1] = true; while (qf != ql) { int u = a[qf++]; for (auto &v : edges[u]) if (!isv[v]) { f[v] = u; isv[v] = true; a[ql++] = v; } } } void deal() { int sum[5]; for (int i = n - 1; i > 0; i--) { int u = a[i]; if (edges[u].size() == 1 && u != 1) { memset(dp[u], 0, sizeof(dp[u])); dp[u][0] = 1; dp[u][1] = 0; dp[u][2] = 1; } else { memset(sum, 0, sizeof(sum)); for (auto &v : edges[u]) if (v != f[u]) { sum[2] += dp[v][2]; sum[1] += dp[v][1]; } memset(dp[u], 0xff, sizeof(dp[u])); dp[u][1] = sum[2]; dp[u][0] = sum[1] + 1; for (auto &v : edges[u]) if (v != f[u]) { if (dp[u][2] == -1) { dp[u][2] = sum[2] - dp[v][2] + dp[v][0]; } else { dp[u][2] = min(dp[u][2], sum[2] - dp[v][2] + dp[v][0]); } } dp[u][2] = min(dp[u][2], dp[u][0]); dp[u][1] = min(dp[u][1], dp[u][2]); } } int ans = 0; for (auto &v : edges[1]) ans += dp[v][0]; ans -= edges[1].size(); cout << ans << endl; } int main() { read_data(); bfs(); deal(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 9223372036854775807; const long long N = 500005; const long long mod = 1e9 + 7; void start(); struct p { long long a, b; }; bool comp1(p p1, p p2) { if (p1.a < p2.a) { return true; } if (p1.a == p2.a) { return (p1.b < p2.b); } }; struct CompareHeight { bool operator()(struct p const& p1, struct p const& p2) { return p1.a < p2.a; } }; long long vis[N], weight[N]; long long a[N], ans; void dfs(long long node, long long target, long long m, vector<pair<long long, long long> > adj[]) { vis[node] = 1; for (long long i = 0; i <= adj[node].size() - 1; i++) { long long child = adj[node][i].first; long long w = adj[node][i].second; if (vis[child] == 1) { continue; } vis[child] = 1; weight[child] = weight[node] + w; dfs(child, target, m + w, adj); } } long long x; void solve() { long long n, m, o, p, q, r, t; string second; cin >> n; cin >> second; long long c = 0; for (long long(i) = 0; (i) <= (n - 1); (i) += (1)) { if (i + 1 < n && second[i] == 1 && second[i + 1] == 0 ) { c++; i++; } } long long ans = c; c = 0; for (long long(i) = 0; (i) <= (n - 1); (i) += (1)) { if (i + 1 < n && second[i] == 0 && second[i + 1] == 1 ) { c++; } } ans = max(ans, c); n = n - 2 * ans; cout << n / 2 << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; start(); long long query; cin >> query; while (query--) { x++; solve(); } } void start() {}
|
#include <bits/stdc++.h> using namespace std; vector<int> graph[100005]; int a[100005], b[100005]; vector<int> ans; void dfs(int source, int parent, int oddlevel, int evenlevel, int depth) { if (depth % 2 == 1) a[source] ^= oddlevel; else a[source] ^= evenlevel; if (a[source] != b[source]) { a[source] ^= 1; if (depth % 2 == 1) oddlevel++; else evenlevel++; oddlevel %= 2, evenlevel %= 2; ans.push_back(source); } for (int i = 0; i < graph[source].size(); i++) { int child = graph[source][i]; if (child == parent) continue; dfs(child, source, oddlevel, evenlevel, depth + 1); } } int main() { int n; cin >> n; for (int i = 1; i < n; i++) { int x, y; cin >> x >> y; graph[x].push_back(y); graph[y].push_back(x); } for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= n; i++) cin >> b[i]; dfs(1, 0, 0, 0, 0); cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) { cout << ans[i] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 212345; int seg[4 * N], v[N], tin[N], tout[N], ans[N]; int a, b, n, q; void init(int r, int i, int j) { if (i == j) { seg[r] = v[i]; } else { init(2 * r, i, (i + j) / 2); init(2 * r + 1, (i + j) / 2 + 1, j); seg[r] = min(seg[2 * r], seg[2 * r + 1]); } } int query(int r, int i, int j) { if (b < i || a > j) return 0x3f3f3f3f; if (i >= a && j <= b) { return seg[r]; } else { int L = query(2 * r, i, (i + j) / 2); int R = query(2 * r + 1, (i + j) / 2 + 1, j); return min(L, R); } } void update(int r, int i, int j, int pos, int val) { if (pos < i || pos > j) return; if (i == j) { seg[r] = val; } else { update(2 * r, i, (i + j) / 2, pos, val); update(2 * r + 1, (i + j) / 2 + 1, j, pos, val); seg[r] = min(seg[2 * r], seg[2 * r + 1]); } } set<int> zeros; int main(void) { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> q; int mx = 0; for (int i = 1; i <= n; i++) { cin >> v[i]; if (v[i] == 0) { zeros.emplace(i); v[i] = 0x3f3f3f3f; } else { if (tin[v[i]] == 0) tin[v[i]] = i; tout[v[i]] = i; mx = max(mx, v[i]); } } if (zeros.size() == n) { cout << YES << endl; for (int i = 1; i <= n; i++) cout << q << ; cout << endl; return 0; } if (mx != q and zeros.size() == 0) { cout << NO << endl; return 0; } init(1, 1, n); if (mx != q and zeros.size()) { auto it = zeros.begin(); update(1, 1, n, *it, q); zeros.erase(it); } for (int i = q; i >= 1; i--) { if (tin[i] == 0) continue; a = tin[i]; b = tout[i]; if (query(1, 1, n) < i) { cout << NO << endl; return 0; } auto it = zeros.lower_bound(tin[i]); while (it != zeros.end() and *it <= tout[i]) { update(1, 1, n, *it, i); it = zeros.erase(it); } } for (int i = 1; i <= n; i++) { a = i; b = i; ans[i] = query(1, 1, n); } for (int i = 2; i <= n; i++) { if (ans[i] == 0x3f3f3f3f and ans[i - 1] != 0x3f3f3f3f) ans[i] = ans[i - 1]; } for (int i = n - 1; i >= 1; i--) { if (ans[i] == 0x3f3f3f3f and ans[i + 1] != 0x3f3f3f3f) ans[i] = ans[i + 1]; } cout << YES << endl; for (int i = 1; i <= n; i++) { assert(ans[i] != 0x3f3f3f3f); cout << ans[i] << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const double PI = acos(-1.0); const int MAXN = 1e6 + 5; char arr[8][8]; bool vis[8][8]; int dx[] = {0, 0, 1, -1, -1, 1, -1, 1, 0}; int dy[] = {1, -1, 0, 0, 1, 1, -1, -1, 0}; bool dfs(int x, int y, int steps) { if (steps > 8) return true; vis[x][y] = true; if (arr[x][y] == A ) return true; bool ok = false; for (int i = 0; i < 9; i++) { int nx = x + dx[i], ny = y + dy[i]; if (nx < 0 || nx >= 8 || ny < 0 || ny >= 8) continue; if (nx - steps >= 0 && arr[nx - steps][ny] == S ) continue; if (nx - steps - 1 >= 0 && arr[nx - steps - 1][ny] == S ) continue; if (dfs(nx, ny, steps + 1)) return true; } return false; } void cp() { for (int i = 0; i < 8; i++) for (int j = 0; j < 8; j++) cin >> arr[i][j]; bool win = dfs(7, 0, 0); if (win) cout << WIN ; else cout << LOSE ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int t; t = 1; while (t--) { cp(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long read() { long long ans = 0; char last = , ch = getchar(); while (ch < 0 || ch > 9 ) last = ch, ch = getchar(); while (ch >= 0 && ch <= 9 ) ans = ans * 10 + ch - 0 , ch = getchar(); if (last == - ) ans = -ans; return ans; } const int N = 2e5 + 5; int n; long long k, sum, tmp, suf[N], a[N], c, ans; long long accCeil(long long a, long long b) { long long res = a / b; if (res * b < a) res++; return res; } int main() { int T = read(); while (T--) { n = read(), k = read(); sum = 0; for (int i = 1; i <= n; ++i) { a[i] = read(); sum += a[i]; } if (sum <= k) { printf( 0 n ); continue; } if (n == 1) { printf( %lld n , sum - k); continue; } sort(a + 1, a + n + 1); suf[n + 1] = 0; ans = 1e18; for (int i = n; i > 1; --i) { suf[i] = suf[i + 1] + a[i]; tmp = sum - k - suf[i] + (n - i + 1) * a[1]; c = max(accCeil(tmp, n - i + 2), 0ll); ans = min(ans, n - i + 1 + c); } printf( %lld n , min(ans, sum - k)); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:34:34 09/03/2015
// Design Name:
// Module Name: TP1_ALU
// Project Name:
// Target Devices:
// Tool veoperand1ions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALU #(parameter N=32)(
input [3:0] op_code,
input signed [N-1:0] operand1,
input signed [N-1:0] operand2,
output reg signed [N-1:0] result,
output reg zero,
output reg overflow
);
always @(*) begin
/*El op_code para cada operacion debe definirse*/
case(op_code)
0: {overflow,result} = operand2 << operand1[4:0]; //SLL
1: {overflow,result} = operand2 >> operand1[4:0]; //SRL
2: {overflow,result} = operand2 >>> operand1[4:0]; //SRA
3: {overflow,result} = operand1 + operand2 ; //ADD
4: {overflow,result} = operand1 - operand2; //SUB
5: {overflow,result} = operand1 & operand2; //AND
6: {overflow,result} = operand1 | operand2; //OR
7: {overflow,result} = operand1 ^ operand2; //XOR
8: {overflow,result} = ~(operand1 | operand2); //NOR
9: {overflow,result} = (operand1 < operand2); //SLT
default: {overflow,result} = 0;
endcase
zero= (result==0)? 1'b1:1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 1e6 + 6; const int inf = 0x3f3f3f3f; long long a[M], sum[M]; int main() { int t; scanf( %d , &t); while (t--) { int n, p, k; scanf( %d%d%d , &n, &p, &k); for (int i = 1; i <= n; i++) scanf( %I64d , &a[i]); sort(a + 1, a + 1 + n); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + a[i]; int ans = 0; for (int i = 0; i < k; i++) { long long now = sum[i]; int num = i; if (now > p) { num--; ans = max(ans, num); break; } for (int j = i + k; j <= n; j += k) { now += a[j]; num += k; if (now > p) { num -= k; break; } } ans = max(ans, num); } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int>> L[1000005]; long long fac[1000005]; const long long MOD = 1000000007; int main() { int N, M; scanf( %d%d , &N, &M); for (int i = 0; i < N; ++i) { int g; scanf( %d , &g); map<int, int> cnt; for (int j = 0; j < g; ++j) { int a; scanf( %d , &a); ++cnt[a]; } for (auto x : cnt) { L[x.first].push_back({i, x.second}); } } map<vector<pair<int, int>>, int> mp; for (int i = 1; i <= M; ++i) ++mp[L[i]]; fac[0] = 1; for (int i = 1; i <= M; ++i) fac[i] = (fac[i - 1] * i) % MOD; long long ans = 1; for (auto &x : mp) ans = (ans * fac[x.second]) % MOD; printf( %I64d n , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_SYMBOL_V
`define SKY130_FD_SC_HS__O221A_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o221a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; int a[n], s = 0; for (int i = 0; i < n; i++) { cin >> a[i]; s += a[i]; } if (s >= m) cout << m << endl; else cout << s << endl; } }
|
//-------------------------------------------------------------------
//-- sectones_tb.v
//-- Banco de pruebas para el secuenciador de 4 notas
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
module secnotas_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Salidas de los canales
wire ch_out;
//-- Instanciar el componente y establecer el valor del divisor
//-- Se pone un valor bajo para simular (de lo contrario tardaria mucho)
secnotas #(.N0(2), .N1(3), .N2(4), .DUR(10))
dut(
.clk(clk),
.ch_out(ch_out)
);
//-- Generador de reloj. Periodo 2 unidades
always
# 1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("secnotas_tb.vcd");
$dumpvars(0, secnotas_tb);
# 200 $display("FIN de la simulacion");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool equal(string s) { int n = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == a ) n++; } if (n * 2 != s.length()) return false; return true; } string s, s1, sex; int n, d, k; int main() { cin >> k; cin >> s; n = s.length(); sex = s; for (int i = 2; i <= n; i = i + 2) { for (int j = 0; j <= n - i; j++) { s1 = s.substr(j, i); if (equal(s1)) { while (s.find(s1) != -1) { s.erase(s.find(s1), 1); d++; } } } } cout << 25 ; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_sincos_double(clock, resetn, enable, dataa, result_a, result_b);
// This is a module intended for Stratix IV family
// Latency = 71.
input clock, resetn, enable;
input [63:0] dataa;
output [63:0] result_a; // sin
output [63:0] result_b; // cos
FPSinCosXDPS4f375 core(
.xIn_v(1'b1),
.xIn_c(8'd0),
.xIn_0(dataa),
.en(enable),
.xOut_v(),
.xOut_c(),
.xOut_0(result_a),
.xOut_1(result_b),
.clk(clock),
.areset(~resetn));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; long long n; int Q; void ReadInput() { cin >> n >> Q; n *= 2LL; } long long Get(long long first) { if (first % 2 == 1) return (first + 1) / 2; return Get(first + (n - first) / 2); } void Solve() { while (Q-- > 0) { long long first; cin >> first; cout << Get(first) << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); ReadInput(); Solve(); }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 2e5 + 7; struct Node { long long x, y; } node[maxn]; bool cmp(Node a, Node b) { return a.x < b.x; } long long n, k; long long len[maxn]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t; cin >> t; while (t--) { cin >> n >> k; for (int i = 0; i < n; i++) cin >> node[i].x; for (int i = 0; i < n; i++) cin >> node[i].y; sort(node, node + n, cmp); long long tarl, tarr; for (tarr = tarl = 0; tarr < n; tarr++) { while (node[tarl].x < node[tarr].x - k) tarl++; len[tarr] = tarr - tarl + 1; } long long ans = 0, Max = 0; for (tarr = tarl = 0; tarr < n; tarr++) { while (node[tarl].x < node[tarr].x - k) { Max = max(Max, len[tarl]); tarl++; } ans = max(Max + len[tarr], ans); } cout << ans << endl; for (int i = 0; i < n; i++) len[i] = 0; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int l, r; cin >> l >> r; cout << l << << l * 2 << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A21OI_FUNCTIONAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_FUNCTIONAL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_drv_zctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// bw_io_dtl_drv -- DTL Driver.
// _____________________________________________________________________________
module bw_io_dtl_drv_zctl (/*AUTOARG*/
// Outputs
pad,
// Inputs
cbu, cbd, sel_data_n, pad_up, pad_dn_l, pad_dn25_l, por, bsr_up, bsr_dn_l,
bsr_dn25_l, vddo
);
output pad;
input [8:1] cbu;
input [8:1] cbd;
input sel_data_n;
input pad_up;
input pad_dn_l;
input pad_dn25_l;
input por;
input bsr_up;
input bsr_dn_l;
input bsr_dn25_l;
input vddo;
reg /*4value*/ pad_reg;
always @(por or sel_data_n or pad_up or pad_dn_l or pad_dn25_l or bsr_up or bsr_dn_l or bsr_dn25_l) begin
casex ({por, sel_data_n, pad_up, pad_dn_l,pad_dn25_l, bsr_up, bsr_dn_l, bsr_dn25_l})
8'b1xxxxxxx: pad_reg = 1'bz; // normal path (pad) reset
8'b00001xxx: pad_reg = 1'b0; // normal path (pad) write 0, 50 ohms
8'b00000xxx: pad_reg = 1'b0; // normal path (pad) write 0, 25 ohms
8'b00011xxx: pad_reg = 1'bz; // normal path (pad) hi-Z
8'b00111xxx: pad_reg = 1'b1; // normal path (pad) write 1
8'b01xxx001: pad_reg = 1'b0; // boundary scan (bsr) write 0, 50 ohms
8'b01xxx000: pad_reg = 1'b0; // boundary scan (bsr) write 0, 25 ohms
8'b01xxx011: pad_reg = 1'bz; // boundary scan (bsr) hi-Z
8'b01xxx111: pad_reg = 1'b1; // boundary scan (bsr) write 1
default: pad_reg = 1'bx; // all other cases illegal and not defined
endcase
end
assign (pull1, strong0) #1 pad = pad_reg;
endmodule
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXTP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFXTP_SYMBOL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void init_code() {} long long int c[207]; bool adj[207][207]; long long int n; void dfs(long long int u, long long int cu) { if (~c[u]) { if (c[u] ^ cu) { cout << NO << n ; exit(0); } return; } c[u] = cu; for (long long int v = 0; v < n; v++) if (adj[u][v]) dfs(v, cu ^ 1); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); init_code(); cin >> n; string str; cin >> str; for (long long int i = 0; i < n; i++) { for (long long int j = i + 1; j < n; j++) { if (str[j] < str[i]) adj[i][j] = adj[j][i] = 1; } } memset(c, -1, sizeof(c)); for (long long int i = 0; i < n; i++) { if (c[i] < 0) dfs(i, 0); } cout << YES << n ; for (long long int i = 0; i < n; i++) cout << c[i]; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD2_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD2_BLACKBOX_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv3sd2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 300005; int n, tt, rt, ans, ls[N], rs[N], val[N], tg[N], rd[N]; inline int nw(int v) { val[++tt] = v; rd[tt] = rand(); return tt; } inline void add(int x, int v) { val[x] += v; tg[x] += v; } inline void dn(int x) { add(ls[x], tg[x]); add(rs[x], tg[x]); tg[x] = 0; } void split(int x, int k, int& a, int& b) { if (!x) { a = b = 0; return; } dn(x); val[x] < k ? (a = x, split(rs[x], k, rs[a], b)) : (b = x, split(ls[x], k, a, ls[b])); } int merge(int x, int y) { if (!x || !y) return x | y; else if (rd[x] < rd[y]) { dn(x); rs[x] = merge(rs[x], y); return x; } else { dn(y); ls[y] = merge(x, ls[y]); return y; } } int main() { scanf( %d , &n); while (n--) { int l, r, x, y, z; scanf( %d%d , &l, &r); split(rt, r, x, z); split(x, l, x, y); add(y, 1); if (z) { int w = z; while (ls[w]) dn(w), w = ls[w]; split(z, val[w] + 1, w, z); } else ans++; rt = merge(merge(x, nw(l)), merge(y, z)); } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { double a1, a2; double b1, b2; double c1, c2; cin >> a1 >> b1 >> c1; cin >> a2 >> b2 >> c2; if (fabs(a1) < 1e-14 && fabs(b1) < 1e-14 && fabs(c1) > 1e-14 || fabs(a2) < 1e-14 && fabs(b2) < 1e-14 && fabs(c2) > 1e-14) { cout << 0; return 0; } if (fabs(a1) < 1e-14 && fabs(b1) < 1e-14 && fabs(c1) < 1e-14 || fabs(a2) < 1e-14 && fabs(b2) < 1e-14 && fabs(c2) < 1e-14) { cout << -1; return 0; } if ((fabs(b1) < 1e-14 && fabs(b2) > 1e-14) || (fabs(b2) < 1e-14 && fabs(b1) > 1e-14)) cout << 1; else if (fabs(b1) < 1e-14 && fabs(b2) < 1e-14) { a1 /= c1; a2 /= c2; if (fabs(a1 - a2) < 1e-14 || (fabs(a1) == INFINITY && fabs(a2) == INFINITY)) cout << -1; else cout << 0; } else { a1 /= b1; a2 /= b2; c1 /= b1; c2 /= b2; if (fabs(a1 - a2) < 1e-14) { if (fabs(c1 - c2) < 1e-14) cout << -1; else cout << 0; } else cout << 1; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DLRTP_FUNCTIONAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_ls__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_ls__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_FUNCTIONAL_V
|
#include<map> #include<set> #include <vector> #include<stack> #include<queue> #include<cmath> #include<string> #include<cstdio> #include<cstring> #include<cstdlib> #include<iostream> #include <numeric> // #include <boost/multiprecision/cpp_dec_float_50.hpp> // using namespace boost::multiprecision; // #include <boost/multiprecision/cpp_dec_float.hpp> // #include <boost/math/constants/constants.hpp> // using boost::multiprecision::cpp_dec_float_50; using namespace std; #define ll long long #define llf long long float #define pl pair<ll,ll> #define test() ll t;cin>>t;while(t--) #define FOR(i,a,b) for(ll i=a;i<b;i++) #define ROF(i,a,b) for(ll i=a;i>=b;i--) #define endl n #define modulus 1000000007 //fast the code #define fast ios_base::sync_with_stdio(false);cin.tie(NULL); // void fastscan(int &number){ bool negative = false;register int c;number = 0; c = getchar();if (c== - ){negative = true;c = getchar();}for (; (c>47 && c<58); c=getchar())number = number *10 + c - 48;if (negative)number *= -1;} typedef vector<ll> vi ; typedef vector<bool> vb ; #define PB push_back ll Gcd(ll a, ll b) { if (b == 0) return a; return Gcd(b, a % b); } bool isPrime(int n){ // Corner cases if(n==1) return true; if (n < 1) return false; if (n <= 3) return true; // This is checked so that we can skip // middle five numbers in below loop if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } // ll power(ll a,ll b){ // if(b==0) return 1; // ll res=1; // while(b>0){ // if(b&1) res*=a; // a*=a; // b>>=1; // } // return res; // } // ll gcd(ll a,ll b,ll &x,ll &y){ // if(b==0){ // x=1;y=0; // return a; // } // ll x1,y1; // ll d=gcd(b,a%b,x1,y1); // x=y1; // y=x1-y1*(a/b); // return d; // } // ll get(ll a,ll b, ll c,ll d){ // ll x,y; // gcd(a,c) // } int main(){ fast test(){ ll n;cin>>n; ll a[n]; map<ll,ll>m; FOR(i,0,n) {cin>>a[i];m[a[i]]++;} map<ll,ll>::iterator itr=m.begin(); itr++; ll res=0; for(itr;itr!=m.end();itr++) res+=itr->second; cout<<res<<endl; } }
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Top of the IEC61499 network
module top
(
input wire clk,
//input events
input wire tick_eI,
input wire i_measured_eI,
input wire test_eI,
input wire set_eI,
input wire iSet_change_eI,
//output events
output wire b_change_eO,
//input variables
input wire unsigned [7:0] i_I,
input wire unsigned [7:0] iSet_I,
//output variables
output wire b_O ,
input reset
);
// I/O
FB_CfbOvercurrentDetector iec61499_network_top (
.clk(clk),
//input events
.tick_eI(tick_eI),
.i_measured_eI(i_measured_eI),
.test_eI(test_eI),
.set_eI(set_eI),
.iSet_change_eI(iSet_change_eI),
//output events
.b_change_eO(b_change_eO),
//input variables
.i_I(i_I),
.iSet_I(iSet_I),
//output variables
.b_O(b_O),
.reset(reset)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; string s, ans, temp; cin >> s; int flag = 0; for (int i = 0; i < k; i++) { for (int j = i; j < n; j += k) { if (s[i] != s[j]) { flag = 1; break; } } if (flag) break; } if (!flag) { cout << s.length() << endl; cout << s << endl; return 0; } for (int i = 0; i < k; i++) temp += s[i]; for (int i = 0; i < n / k; i++) ans += temp; int i = 0; while (ans.length() < s.length()) { ans += temp[i]; i++; } if (ans >= s) { cout << ans.length() << endl; cout << ans << endl; return 0; } i = 0, flag = 0; for (i = k - 1; i >= 0; i--) { if (s[i] < 9 ) { s[i] = s[i] + 1; flag = 1; break; } } if (flag) { i++; for (i; i < k; i++) s[i] = 0 ; } temp.clear(), ans.clear(); for (int i = 0; i < k; i++) temp += s[i]; for (int i = 0; i < n / k; i++) ans += temp; i = 0; while (ans.length() < s.length()) { ans += temp[i]; i++; } cout << ans.length() << endl; cout << ans << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// This checks IEEE ports work correctly, we use XML output to make it easy to
// see all attributes are propagated
// verilator lint_off MULTITOP
`ifndef VERILATOR
module mh0 (wire x_inout_wire_logic);
endmodule
module mh1 (integer x_inout_wire_integer);
endmodule
`endif
module mh2 (inout integer x_inout_wire_integer);
endmodule
`ifndef VERILATOR
module mh3 ([5:0] x_inout_wire_logic_p6);
endmodule
`endif
module mh5 (input x_input_wire_logic);
endmodule
module mh6 (input var x_input_var_logic);
endmodule
module mh7 (input var integer x_input_var_integer);
endmodule
module mh8 (output x_output_wire_logic);
endmodule
module mh9 (output var x_output_var_logic);
endmodule
module mh10(output signed [5:0] x_output_wire_logic_signed_p6);
endmodule
module mh11(output integer x_output_var_integer);
endmodule
module mh12(ref [5:0] x_ref_logic_p6);
endmodule
module mh13(ref x_ref_var_logic_u6 [5:0]);
endmodule
`ifndef VERILATOR
module mh14(wire x_inout_wire_logic, y_inout_wire_logic_p8 [7:0]);
endmodule
module mh15(integer x_inout_wire_integer, signed [5:0] y_inout_wire_logic_signed6);
endmodule
module mh16([5:0] x_inout_wire_logic_p6, wire y_inout_wire_logic);
endmodule
`endif
module mh17(input var integer x_input_var_integer, wire y_input_wire_logic);
endmodule
module mh18(output var x_output_var_logic, input y_input_wire_logic);
endmodule
module mh19(output signed [5:0] x_output_wire_logic_signed_p6, integer y_output_var_integer);
endmodule
module mh20(ref [5:0] x_ref_var_logic_p6, y_ref_var_logic_p6);
endmodule
module mh21(ref ref_var_logic_u6 [5:0], y_ref_var_logic);
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: io_mux.v
//
// *Module Description:
// I/O mux for port function selection.
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 104 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $
//----------------------------------------------------------------------------
module io_mux (
// Function A (typically GPIO)
a_din,
a_dout,
a_dout_en,
// Function B (Timer A, ...)
b_din,
b_dout,
b_dout_en,
// IO Cell
io_din,
io_dout,
io_dout_en,
// Function selection (0=A, 1=B)
sel
);
// PARAMETERs
//============
parameter WIDTH = 8;
// Function A (typically GPIO)
//===============================
output [WIDTH-1:0] a_din;
input [WIDTH-1:0] a_dout;
input [WIDTH-1:0] a_dout_en;
// Function B (Timer A, ...)
//===============================
output [WIDTH-1:0] b_din;
input [WIDTH-1:0] b_dout;
input [WIDTH-1:0] b_dout_en;
// IO Cell
//===============================
input [WIDTH-1:0] io_din;
output [WIDTH-1:0] io_dout;
output [WIDTH-1:0] io_dout_en;
// Function selection (0=A, 1=B)
//===============================
input [WIDTH-1:0] sel;
//=============================================================================
// 1) I/O FUNCTION SELECTION MUX
//=============================================================================
function [WIDTH-1:0] mux (
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
input [WIDTH-1:0] SEL
);
integer i;
begin
mux = {WIDTH{1'b0}};
for (i = 0; i < WIDTH; i = i + 1)
mux[i] = sel[i] ? B[i] : A[i];
end
endfunction
assign a_din = mux( io_din, {WIDTH{1'b0}}, sel);
assign b_din = mux({WIDTH{1'b0}}, io_din, sel);
assign io_dout = mux( a_dout, b_dout, sel);
assign io_dout_en = mux( a_dout_en, b_dout_en, sel);
endmodule // io_mux
|
#include <bits/stdc++.h> using namespace std; long long n, m; struct pt { long long x, y; pt() {} pt(long long x, long long y) : x(x), y(y) {} }; vector<vector<long long>> used; vector<vector<long long>> g; void parasha(pt q, pt p, long long weight, deque<pt>& bfs, vector<vector<long long>>& w) { if (q.x < 0 || q.y < 0 || q.x >= n || q.y >= m) return; if (g[q.x][q.y] == * ) return; if (w[q.x][q.y] > w[p.x][p.y] + weight) { w[q.x][q.y] = w[p.x][p.y] + weight; if (weight == 1) bfs.push_back(q); else bfs.push_front(q); } } int32_t main() { deque<pt> bfs; cin >> n >> m; vector<vector<long long>> w(n, vector<long long>(m, 3e9)); g.assign(n, vector<long long>(m)); used.assign(n, vector<long long>(m, 0)); long long r, c; cin >> r >> c; --r; --c; long long x, y; cin >> x >> y; for (long long i = 0; i < n; ++i) { for (long long j = 0; j < m; ++j) { char x; cin >> x; g[i][j] = x; } } bfs.push_back(pt(r, c)); w[r][c] = 0; while (!bfs.empty()) { pt q = bfs.front(); bfs.pop_front(); if (used[q.x][q.y] == 1) { continue; } used[q.x][q.y] = 1; parasha(pt(q.x, q.y + 1), q, 0, bfs, w); parasha(pt(q.x + 1, q.y), q, 0, bfs, w); parasha(pt(q.x - 1, q.y), q, 0, bfs, w); parasha(pt(q.x, q.y - 1), q, 1, bfs, w); } long long ans = 0; for (long long i = 0; i < n; ++i) { for (long long j = 0; j < m; ++j) { if (w[i][j] <= x && w[i][j] - (c - j) <= y) ++ans; } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; string arf[1005], ars[1005]; string ans[1005]; void solve() { int n; cin >> n; map<string, vector<int> > f, s; int done[n]; memset(done, 0, sizeof(done)); ; for (int i = 0; i < (int)(n); i++) { string s1, s2; cin >> s1 >> s2; arf[i] = s1.substr(0, 3); ars[i] = s1.substr(0, 2) + s2.substr(0, 1); f[arf[i]].push_back(i); s[ars[i]].push_back(i); } map<string, int> final; for (auto i = f.begin(); i != f.end(); i++) { if (i->second.size() > 1) { for (int k = 0; k < i->second.size(); k++) { final[ars[i->second[k]]]++; ans[i->second[k]] = ars[i->second[k]]; done[i->second[k]] = 1; } } } for (int i = 0; i < n; i++) { if (done[i] == 0) { if (final[ars[i]] == 0) { final[ars[i]] = 1; ans[i] = ars[i]; } else if (final[arf[i]] == 0) { final[arf[i]] = 1; ans[i] = arf[i]; } else { cout << NO ; return; } } } for (auto i = final.begin(); i != final.end(); i++) { if (i->second > 1) { cout << NO ; return; } } cout << YES n ; for (int i = 0; i < (int)(n); i++) { cout << ans[i] << n ; } } int main() { cin.tie(0); cout.tie(0); cin.sync_with_stdio(0); cout.sync_with_stdio(0); int TC = 1; for (int ZZ = 1; ZZ <= TC; ZZ++) { clock_t start = clock(); solve(); clock_t end = clock(); cerr << Time: << (double)(end - start) / CLOCKS_PER_SEC << seconds << n ; } return 0; }
|
module test;
reg signed [3:0] a;
reg signed [3:0] b;
reg [3:0] u;
reg [3:0] r;
reg fail;
initial begin
fail = 0;
a = 4'b1000;
b = 4'b0010;
u = 4'b0001;
r = ((a >>> 1) | b ) | u;
$display("step 1 expected '0111', got '%b'", r);
if (r !== 4'b0111) fail = 1;
r = ((4'b1000 >>> 1) | b ) | u;
$display("step 2 expected '0111', got '%b'", r);
if (r !== 4'b0111) fail = 1;
r = ((a >>> 1) | 4'b0010) | u;
$display("step 3 expected '0111', got '%b'", r);
if (r !== 4'b0111) fail = 1;
r = ((a >>> 1) | b ) | 4'b0001;
$display("step 4 expected '0111', got '%b'", r);
if (r !== 4'b0111) fail = 1;
r = ((4'b1000 >>> 1) | 4'b0010) | u;
$display("step 5 expected '0111', got '%b'", r);
if (r !== 4'b0111) fail = 1;
r = ((a >>> 1) | 4'b0010) | 4'b0001;
$display("step 6 expected '0111', got '%b'", r);
if (r !== 4'b0111) fail = 1;
r = ((4'b1000 >>> 1) | 4'b0010) | 4'b0001;
$display("step 7 expected '0111', got '%b'", r);
if (r !== 4'b0111) fail = 1;
if (fail)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/11/2016 11:27:29 AM
// Design Name:
// Module Name: Barrel_shifter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Barrel_Shifter
#(parameter SWR=26, parameter EWR=5) //Implicit bit + Significand Width (23 bits for simple format, 52 bits for Double format)
//+ guard Bit + round bit
/*#(parameter SWR=55, parameter EWR=6)*/
(
input wire clk,
input wire rst,
input wire load_i,
input wire [EWR-1:0] Shift_Value_i,
input wire [SWR-1:0] Shift_Data_i,
input wire Left_Right_i,
input wire Bit_Shift_i,
/////////////////////////////////////////////7
output wire [SWR-1:0] N_mant_o
);
wire [SWR-1:0] Data_Reg;
////////////////////////////////////////////////////7
Mux_Array #(.SWR(SWR),.EWR(EWR)) Mux_Array(
.clk(clk),
.rst(rst),
.load_i(load_i),
.Data_i(Shift_Data_i),
.FSM_left_right_i(Left_Right_i),
.Shift_Value_i(Shift_Value_i),
.bit_shift_i(Bit_Shift_i),
.Data_o(Data_Reg)
);
RegisterAdd #(.W(SWR)) Output_Reg(
.clk(clk),
.rst(rst),
.load(load_i),
.D(Data_Reg),
.Q(N_mant_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = (1 << 30) - 1; const long long linf = (1ll << 62) - 1; const int N = 1e6; int n; int p[N]; int division[2][N]; int dln[2]; bool u[N]; int main() { cin >> n; for (int i = 0; i < n; i++) { scanf( %d , &p[i]); p[i]--; } int index1 = -1, index2 = -1; for (int i = 0; i < n; i++) { if (p[i] == i) index1 = i; if (p[p[i]] == i) index2 = i; } if (index1 != -1) { puts( YES ); for (int i = 0; i < n; i++) if (index1 != i) printf( %d %d n , index1 + 1, i + 1); return 0; } if (index2 != -1) { bool flag = true; dln[0] = dln[1] = 0; fill_n(u, n, 0); u[index2] = u[p[index2]] = 1; for (int i = 0; i < n; i++) if (!u[i]) { u[i] = 1; division[0][dln[0]++] = i; int curI = p[i], step = 1; while (curI != i) { u[curI] = 1; division[step][dln[step]++] = curI; step ^= 1; curI = p[curI]; } if (step == 1) { flag = false; break; } } if (!flag) { puts( NO ); return 0; } puts( YES ); printf( %d %d n , index2 + 1, p[index2] + 1); for (int i = 0; i < dln[0]; i++) printf( %d %d n , index2 + 1, division[0][i] + 1); for (int i = 0; i < dln[1]; i++) printf( %d %d n , p[index2] + 1, division[1][i] + 1); return 0; } puts( NO ); return 0; }
|
module rf(clk,p0_addr,p1_addr,p0,p1,re0,re1,dst_addr,dst,we,hlt);
//////////////////////////////////////////////////////////////////
// Triple ported register file. Two read ports (p0 & p1), and //
// one write port (dst). Data is written on clock high, and //
// read on clock low //////////////////////////////////////////
//////////////////////
input clk;
input [3:0] p0_addr, p1_addr; // two read port addresses
input re0,re1; // read enables (power not functionality)
input [3:0] dst_addr; // write address
input [15:0] dst; // dst bus
input we; // write enable
input hlt; // not a functional input. Used to dump register contents when
// test is halted.
output reg [15:0] p0,p1; //output read ports
integer indx;
reg [15:0]mem[0:15];
/*
reg [3:0] dst_addr_lat; // have to capture dst_addr from previous cycle
reg [15:0] dst_lat; // have to capture write data from previous cycle
reg we_lat; // have to capture we from previous cycle
*/
//////////////////////////////////////////////////////////
// Register file will come up uninitialized except for //
// register zero which is hardwired to be zero. //
///////////////////////////////////////////////////////
initial begin
mem[0] = 16'h0000; // reg0 is always 0,
end
/*
//////////////////////////////////////////////////
// dst_addr, dst, & we all need to be latched //
// on clock low of previous cycle to maintain //
// in clock high write of next cycle. //
//////////////////////////////////////////////
always @(clk,dst_addr,dst,we)
if (~clk)
begin
dst_addr_lat <= dst_addr;
dst_lat <= dst;
we_lat <= we;
end
*/
//////////////////////////////////
// RF is written on clock high //
////////////////////////////////
always @(clk,we,dst_addr,dst)
if (clk && we && |dst_addr)
mem[dst_addr] <= dst;
//////////////////////////////
// RF is read on clock low //
////////////////////////////
always @(clk,re0,p0_addr)
if (~clk && re0)
p0 <= mem[p0_addr];
//////////////////////////////
// RF is read on clock low //
////////////////////////////
always @(clk,re1,p1_addr)
if (~clk && re1)
p1 <= mem[p1_addr];
////////////////////////////////////////
// Dump register contents at program //
// halt for debug purposes //
/////////////////////////////////////
always @(posedge hlt)
for(indx=1; indx<16; indx = indx+1)
$display("R%1h = %h",indx,mem[indx]);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This mode performs signed number computations in the case of a particular
// interface definition.
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Raynard Qiao.
// SPDX-License-Identifier: CC0-1.0
// issure 3294
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] in0;
reg [7:0] in1;
reg [15:0] out;
initial begin
in0 = 'h2;
in1 = 'hff;
end
Test test(.in0, .in1, .out);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$display("[%0t] clk @ out 'h%0x, expect value='hfffe", $time, out);
`endif
if (out !== 'hfffe) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module Test(in0, in1, out);
input [7:0] in0;
input [7:0] in1;
output [15:0] out;
wire signed [7:0] in1;
wire signed [7:0] in0;
wire signed [15:0] out;
assign out = $signed({1'b0, in0}) * in1; // this operator should be signed multiplication
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__FA_PP_BLACKBOX_V
/**
* fa: Full adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_PP_BLACKBOX_V
|
//Listing 9.1
module ps2_rx
(
input wire clk, reset,
inout wire ps2d, ps2c,
input wire rx_en,
output reg rx_done_tick,
output wire [7:0] dout
);
// symbolic state declaration
localparam [1:0]
idle = 2'b00,
dps = 2'b01,
load = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
reg [7:0] filter_reg;
wire [7:0] filter_next;
reg f_ps2c_reg;
wire f_ps2c_next;
reg [3:0] n_reg, n_next;
reg [10:0] b_reg, b_next;
wire fall_edge;
// body
//=================================================
// filter and falling-edge tick generation for ps2c
//=================================================
always @(posedge clk, posedge reset)
if (reset)
begin
filter_reg <= 0;
f_ps2c_reg <= 0;
end
else
begin
filter_reg <= filter_next;
f_ps2c_reg <= f_ps2c_next;
end
assign filter_next = {ps2c, filter_reg[7:1]};
assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
(filter_reg==8'b00000000) ? 1'b0 :
f_ps2c_reg;
assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
//=================================================
// FSMD
//=================================================
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
n_reg <= 0;
b_reg <= 0;
end
else
begin
state_reg <= state_next;
n_reg <= n_next;
b_reg <= b_next;
end
// FSMD next-state logic
always @*
begin
state_next = state_reg;
rx_done_tick = 1'b0;
n_next = n_reg;
b_next = b_reg;
case (state_reg)
idle:
if (fall_edge & rx_en)
begin
// shift in start bit
b_next = {ps2d, b_reg[10:1]};
n_next = 4'b1001;
state_next = dps;
end
dps: // 8 data + 1 parity + 1 stop
if (fall_edge)
begin
b_next = {ps2d, b_reg[10:1]};
if (n_reg==0)
state_next = load;
else
n_next = n_reg - 1'b1;
end
load: // 1 extra clock to complete the last shift
begin
state_next = idle;
rx_done_tick = 1'b1;
end
endcase
end
// output
assign dout = b_reg[8:1]; // data bits
endmodule
|
#include <bits/stdc++.h> using namespace std; int L[1220], R[1220], s[1220], pos[1220]; char ans[1220]; int main() { int n, ok = 1, all = 0, top = 0; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d%d , &L[i], &R[i]); if (!ok) continue; pos[i] = all; ans[all++] = ( ; s[++top] = i; while (top > 0 && pos[s[top]] + L[s[top]] <= all) { if (pos[s[top]] + R[s[top]] >= all) ans[all++] = ) ; else { ok = 0; break; } top--; } } if (top > 0) ok = 0; if (ok) printf( %s n , ans); else puts( IMPOSSIBLE ); return 0; }
|
//==================================================================================================
// Filename : Testbench_simpleAdders.v
// Created On : 2016-11-18 02:54:20
// Last Modified : 2016-11-26 01:24:32
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : Testbench for different approximate
//
//
//==================================================================================================
`timescale 1ns / 1ps
module Testbench_Multi();
parameter PERIOD = 10;
parameter W = 24;
reg clk;
//Oper_Start_in signals
reg [W-1:0] in1;
reg [W-1:0] in2;
wire [2*W-1:0] res;
integer FileResHex;
integer FileResDec;
reg [2*W-1:0] ValTeorico;
reg signed [2*W:0] Error = 0;
localparam STRINGHEX = "ResultsFileH.txt";
localparam STRINGDEC = "ResultsFileDec.txt";
ETM_Multiplier #(.W(W)) inst_ETM_Multiplier (.in1(in1), .in2(in2), .res(res));
real floatERROR = 0;
real sumErrors = 0;
initial begin
// Initialize Inputs
// $vcdpluson;
clk = 0;
in1 = 0;
in2 = 0;
#100;
FileResHex = $fopen(STRINGHEX,"w");
FileResDec = $fopen(STRINGDEC,"w");
runAdder(FileResHex,FileResDec,(1024));
$finish;
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
task runAdder;
input integer ResultsFileH;
input integer ResultsFileD;
input integer Vector_size;
begin
$fwrite(ResultsFileH, "Entrada 1, Entrada 2, Resultado, Teorico, Error\n");
$fwrite(ResultsFileD, "Entrada 1, Entrada 2, Resultado, Teorico, Error\n");
repeat(Vector_size) @(posedge clk) begin
//input the new values inside the operator
#5;
in1 = $random;
in2 = $random;
ValTeorico = in1 * in2;
Error = (res - ValTeorico);
if (0>Error) begin
Error = (ValTeorico - res);
end
floatERROR = $bitstoreal(Error)/$bitstoreal(ValTeorico);
floatERROR = floatERROR*$itor(100);
sumErrors = sumErrors + floatERROR;
$fwrite(ResultsFileH, "%h, %h, %h, %h, %h\n", in1, in2, res, ValTeorico, Error);
$fwrite(ResultsFileD, "%d, %d, %d, %d, %d, %f\n", in1, in2, res, ValTeorico, Error, floatERROR);
end
$fwrite(ResultsFileD, "La suma de los errores es > %f\n", sumErrors);
$fwrite(ResultsFileD, "El numero de elementos es > %f\n", $itor(Vector_size));
$fwrite(ResultsFileD, "La media del error es> %f\n", sumErrors/$itor(Vector_size));
$fclose(ResultsFileH);
$fclose(ResultsFileD);
end
endtask
endmodule
|
/*
Copyright (c) 2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* LED shift register driver
*/
module led_sreg_driver #(
// number of LEDs
parameter COUNT = 8,
// invert output
parameter INVERT = 0,
// clock prescale
parameter PRESCALE = 31
)
(
input wire clk,
input wire rst,
input wire [COUNT-1:0] led,
output wire sreg_d,
output wire sreg_ld,
output wire sreg_clk
);
localparam CL_COUNT = $clog2(COUNT+1);
localparam CL_PRESCALE = $clog2(PRESCALE+1);
reg [CL_COUNT-1:0] count_reg = 0;
reg [CL_PRESCALE-1:0] prescale_count_reg = 0;
reg enable_reg = 1'b0;
reg update_reg = 1'b1;
reg cycle_reg = 1'b0;
reg [COUNT-1:0] led_sync_reg_1 = 0;
reg [COUNT-1:0] led_sync_reg_2 = 0;
reg [COUNT-1:0] led_reg = 0;
reg sreg_d_reg = 1'b0;
reg sreg_ld_reg = 1'b0;
reg sreg_clk_reg = 1'b0;
assign sreg_d = INVERT ? !sreg_d_reg : sreg_d_reg;
assign sreg_ld = sreg_ld_reg;
assign sreg_clk = sreg_clk_reg;
always @(posedge clk) begin
led_sync_reg_1 <= led;
led_sync_reg_2 <= led_sync_reg_1;
enable_reg <= 1'b0;
if (prescale_count_reg) begin
prescale_count_reg <= prescale_count_reg - 1;
end else begin
enable_reg <= 1'b1;
prescale_count_reg <= PRESCALE;
end
if (enable_reg) begin
if (cycle_reg) begin
cycle_reg <= 1'b0;
sreg_clk_reg <= 1'b1;
end else if (count_reg) begin
sreg_clk_reg <= 1'b0;
sreg_ld_reg <= 1'b0;
if (count_reg < COUNT) begin
count_reg <= count_reg + 1;
cycle_reg <= 1'b1;
sreg_d_reg <= led_reg[count_reg];
end else begin
count_reg <= 0;
cycle_reg <= 1'b0;
sreg_d_reg <= 1'b0;
sreg_ld_reg <= 1'b1;
end
end else begin
sreg_clk_reg <= 1'b0;
sreg_ld_reg <= 1'b0;
if (update_reg) begin
update_reg <= 1'b0;
count_reg <= 1;
cycle_reg <= 1'b1;
sreg_d_reg <= led_reg[0];
end
end
end
if (led_sync_reg_2 != led_reg) begin
led_reg <= led_sync_reg_2;
update_reg <= 1'b1;
end
if (rst) begin
count_reg <= 0;
prescale_count_reg <= 0;
enable_reg <= 1'b0;
update_reg <= 1'b1;
cycle_reg <= 1'b0;
led_reg <= 0;
sreg_d_reg <= 1'b0;
sreg_ld_reg <= 1'b0;
sreg_clk_reg <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, i, j, v[1005]; char s[1005]; int main() { scanf( %d n , &n); scanf( %s , s + 1); s[0] = L ; s[n] = R ; for (i = 1; i <= n; ++i) { j = i - 1; while (s[j] != L ) { if (s[j] == R ) ++v[i]; --j; } int aux = 0; j = i; while (s[j] != R ) { if (s[j] == L ) ++aux; ++j; } v[i] = max(v[i], aux); ++v[i]; } for (i = 1; i <= n; ++i) printf( %d , v[i]); }
|
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