text
stringlengths 59
71.4k
|
|---|
#include <bits/stdc++.h> using namespace std; void A() { cout << tokitsukaze << endl; exit(0); } void B() { cout << quailty << endl; exit(0); } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, k; cin >> n >> k; string s; cin >> s; set<int> p[2]; for (int i = 0; i < n; ++i) { p[s[i] - 0 ].insert(i); } int m[2], M[2]; if (p[0].empty() || p[1].empty()) { A(); } m[0] = *p[0].begin(); M[0] = *--p[0].end(); m[1] = *p[1].begin(); M[1] = *--p[1].end(); if (M[0] - m[0] + 1 <= k || M[1] - m[1] + 1 <= k) { A(); } bool b = true; for (int i = 0; i < n - k + 1; ++i) { bool ok = false; int l, r; l = min(m[0], i); r = max(M[0], i + k - 1); if (r - l + 1 <= k) { ok = true; } if (m[1] < i) { l = m[1]; } else { l = *p[1].lower_bound(i + k); } if (M[1] >= i + k) { r = M[1]; } else { r = *--p[1].lower_bound(i); } if (r - l + 1 <= k) { ok = true; } if (!ok) { b = false; } ok = false; l = min(m[1], i); r = max(M[1], i + k - 1); if (r - l + 1 <= k) { ok = true; } if (m[0] < i) { l = m[0]; } else { l = *p[0].lower_bound(i + k); } if (M[0] >= i + k) { r = M[0]; } else { r = *--p[0].lower_bound(i); } if (r - l + 1 <= k) { ok = true; } if (!ok) { ok = false; } } if (b) { B(); } cout << once again << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; bool op = false; char c = getchar(); while (!isdigit(c)) op |= (c == - ), c = getchar(); while (isdigit(c)) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); return op ? -x : x; } const int N = 2e5 + 10; int n, m, B; int dif[N], d[500][500], lst[N]; struct Node { int x, y; Node() {} Node(int x, int y) : x(x), y(y) {} } a[N]; void update(int t, int x, int v) { int p = a[x].x + a[x].y; int l = (t + a[x].x) % p, r = (t - 1) % p; if (l <= r) for (int i = l; i <= r; i++) d[p][i] += v; else { for (int i = 0; i <= r; i++) d[p][i] += v; for (int i = l; i < p; i++) d[p][i] += v; } } int main() { n = read(); m = read(); B = sqrt(m); for (int i = 1; i <= n; i++) { int x = read(), y = read(); a[i] = Node(x, y); } int ans = 0; for (int t = 1; t <= m; t++) { int op = read(), x = read(); if (op == 1) { if (a[x].x + a[x].y > B) { for (int i = t + a[x].x; i <= m; i += a[x].x + a[x].y) { dif[i]++; if (i + a[x].y <= m) dif[i + a[x].y]--; } } else update(t, x, 1); lst[x] = t; } else { if (a[x].x + a[x].y > B) { for (int i = lst[x] + a[x].x; i <= m; i += a[x].x + a[x].y) { dif[i]--; if (i + a[x].y <= m) dif[i + a[x].y]++; if (i < t && i + a[x].y >= t) ans--; } } else update(lst[x], x, -1); } int res = 0; ans += dif[t]; for (int i = 1; i <= B; i++) res += d[i][t % i]; printf( %d n , res + ans); } }
|
/*
* Copyright 2013-2016 Colin Weltin-Wu ()
* UC San Diego Integrated Signal Processing Group
*
* Licensed under GNU General Public License 3.0 or later.
* Some rights reserved. See LICENSE.
*
* negedge_sync.v
* Used to synchronize a signal coming from an async domain. Signal is
* sampled on the rising edge, but changes only on falling edges. Used
* for synchronizing control signals that go to rising edge logic. This
* block has no reset.
*
* The idea behind allowing its output to change on the falling edge of the
* clock is that it is more likely for there to be positive clock skew in
* downstream logic so having a signal change on the rising edge risks
* impinging on the data hold window.
*
* 1/2 clock period delay.
*/
module negedge_sync (i_clk, i_async, o_sync);
input i_clk;
input i_async;
output o_sync;
reg samp_rising;
reg o_sync;
initial begin
samp_rising <= 1'b0;
o_sync <= 1'b0;
end
always @( posedge i_clk )
samp_rising <= i_async;
always @( negedge i_clk )
o_sync <= samp_rising;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CONB_SYMBOL_V
`define SKY130_FD_SC_LS__CONB_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__conb (
//# {{data|Data Signals}}
output HI,
output LO
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CONB_SYMBOL_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream SRL-based FIFO register
*/
module axis_srl_register #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser
);
localparam KEEP_OFFSET = DATA_WIDTH;
localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0);
localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
reg [WIDTH-1:0] data_reg[1:0];
reg valid_reg[1:0];
reg ptr_reg = 0;
reg full_reg = 0;
wire [WIDTH-1:0] s_axis;
wire [WIDTH-1:0] m_axis = data_reg[ptr_reg];
assign s_axis_tready = !full_reg;
generate
assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata;
if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep;
if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast;
if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid;
if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest;
if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser;
endgenerate
assign m_axis_tvalid = valid_reg[ptr_reg];
assign m_axis_tdata = m_axis[DATA_WIDTH-1:0];
assign m_axis_tkeep = KEEP_ENABLE ? m_axis[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
assign m_axis_tlast = LAST_ENABLE ? m_axis[LAST_OFFSET] : 1'b1;
assign m_axis_tid = ID_ENABLE ? m_axis[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
integer i;
initial begin
for (i = 0; i < 2; i = i + 1) begin
data_reg[i] <= 0;
valid_reg[i] <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
full_reg <= 0;
end else begin
// transfer empty to full
full_reg <= !m_axis_tready && m_axis_tvalid;
// transfer in if not full
if (s_axis_tready) begin
data_reg[0] <= s_axis;
valid_reg[0] <= s_axis_tvalid;
for (i = 0; i < 1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
valid_reg[i+1] <= valid_reg[i];
end
ptr_reg <= valid_reg[0];
end
if (m_axis_tready) begin
ptr_reg <= 0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module RAM1(CLK,RST,ED,START,DReal,DImag,RDY,DOReal,DOImag);
parameter total_bits = 32;
input CLK;
input RST;
input ED;
input START;
input [total_bits-1:0] DReal;
input [total_bits-1:0] DImag;
output reg RDY;
output [total_bits-1:0] DOReal;
output [total_bits-1:0] DOImag;
reg [total_bits-1:0] DATAReal [0:31];
reg [total_bits-1:0] DATAImag [0:31];
reg [5:0] addr;
reg [6:0] count;
reg delay;
reg flag;
always @(posedge CLK)
begin
if (RST) begin
addr<=6'b000000;
count<= 7'b0000000;
flag<=0;
delay<=0;
RDY<=1'b0; end
else if (START) begin
addr<=6'b000000;
count<= 7'b0000000;
flag<=0;
delay<=0;
RDY<=1'b0;end
else if (ED) begin
RDY<=1'b0;
if(count<=31)
begin
DATAReal[{addr[0],addr[4:1]}] <= DReal;
DATAImag[{addr[0],addr[4:1]}] <= DImag;
end
if (count!=127)
count<=count+1;
if (count==31||count==126) // Optimaization possible
begin
RDY<=1'b1;
delay<=1'b1;
if(flag == 0) begin addr<=0; flag<=1; end
else addr<=16;
end
else
if(delay)
delay<=0;
else
addr<=addr+1;
end
end
assign DOReal = DATAReal[addr[4:0]];
assign DOImag = DATAImag[addr[4:0]];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1 << 21; int n, m; char s[maxn]; char cmd[maxn]; struct lucky { int c4, c7, c47, c74; lucky() { c4 = 0, c7 = 0, c47 = 0, c74 = 0; } void merge(lucky a, lucky b) { c4 = a.c4 + b.c4; c7 = a.c7 + b.c7; c47 = max(a.c47 + b.c7, a.c4 + b.c47); c74 = max(a.c74 + b.c4, a.c7 + b.c74); } void reset(char c) { if (c == 7 ) c7 = 1; else c4 = 1; c47 = 1; c74 = 1; } void chng() { swap(c4, c7); swap(c47, c74); } void recieve(bool bb) { if (bb) chng(); } }; lucky seg[maxn]; bool lazy[maxn]; lucky build(int rt, int lp, int rp) { if (lp + 1 == rp) { seg[rt].reset(s[lp]); } else { int mid = (lp + rp) / 2; seg[rt].merge(build(rt * 2, lp, mid), build(rt * 2 + 1, mid, rp)); } return seg[rt]; } int qa, qb; lucky update(int rt, int lp, int rp) { if (lp >= qb || rp <= qa) return seg[rt]; if (qa <= lp && rp <= qb) { lazy[rt] ^= true; seg[rt].chng(); } else { int mid = (lp + rp) / 2; seg[rt].merge(update(rt * 2, lp, mid), update(rt * 2 + 1, mid, rp)); seg[rt].recieve(lazy[rt]); } return seg[rt]; } int main() { scanf( %d%d%s , &n, &m, s); build(1, 0, n); for (int i = 0; i < m; i++) { scanf( %s , cmd); if (cmd[0] == c ) { printf( %d n , seg[1].c47); } else { scanf( %d%d , &qa, &qb); qa--; update(1, 0, n); } } }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1100; const long long MOD = 998244353; int N, K; int arr[MAXN]; int dp[MAXN][MAXN]; int ps[MAXN][MAXN]; long long figure(int k) { if (k * (K - 1) > arr[N - 1]) return 0; for (int i = 0; i <= N; i++) for (int j = 0; j <= K; j++) dp[i][j] = ps[i][j] = 0; for (int i = 1; i <= N; i++) dp[i][1] = 1; int cstop = 0; for (int i = 0; i < N; i++) { while (cstop < i && arr[i] - arr[cstop] >= k) cstop++; for (int j = 1; j < K; j++) { dp[i + 1][j + 1] = ps[cstop][j]; } for (int j = 0; j <= K; j++) { ps[i + 1][j] = (ps[i][j] + dp[i + 1][j]) % MOD; } } return ps[N][K]; } int main() { ios_base::sync_with_stdio(0); cin >> N >> K; for (int i = 0; i < N; i++) cin >> arr[i]; sort(arr, arr + N); long long ans = 0; for (int i = 1; i <= 100000; i++) ans = (ans + figure(i)) % MOD; cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; vector<long long int> v; long long int a[120100], n, dd; map<int, int> mp; int main() { for (long long int i = 1; i <= 2000000000; i *= 2) { v.push_back(i); } cin >> n; for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); mp[a[i]]++; } sort(a, a + n); int f, res = 0; for (int i = 0; i < n; i++) { f = 0; for (int j = 0; j < v.size(); j++) { if (v[j] <= a[i]) continue; dd = v[j] - a[i]; if (dd == a[i]) { if (mp[a[i]] >= 2) { f = 1; break; } continue; } if (mp[dd] >= 1) { f = 1; break; } } if (f == 0) res++; } cout << res << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; void print(int base) { if (base == 4) cout << 4 * 3 = 12 n12 * 2 = 24 n24 * 1 = 24 << endl; if (base == 5) cout << 5 * 4 = 20 n3 + 2 = 5 n5 - 1 = 4 n20 + 4 = 24 << endl; if (base == 6) cout << 4 * 3 = 12 n12 * 2 = 24 n5 + 1 = 6 n6 - 6 = 0 n24 + 0 = 24 << endl; if (base == 7) cout << 5 * 3 = 15 n15 + 7 = 22 n2 - 1 = 1 n22 * 1 = 22 n6 - 4 = 2 n22 + 2 = 24 << endl; } void solve(int n, int base) { print(base); if (n == base) return; cout << base + 1 << + << base + 4 << = << 2 * base + 5 << n ; cout << base + 2 << + << base + 3 << = << 2 * base + 5 << n ; long long sm1 = 2 * base + 5, sm2 = 2 * base + 5, cs = 0; for (int i = base + 5; i <= n; i += 2) { if (cs) { cout << sm1 << + << i << = << sm1 + i << n ; cout << sm2 << + << i + 1 << = << sm2 + i + 1 << n ; cs = 0; sm1 += i; sm2 += i + 1; } else { cout << sm1 << + << i + 1 << = << sm1 + i + 1 << n ; cout << sm2 << + << i << = << sm2 + i << n ; cs = 1; sm1 += i + 1; sm2 += i; } } cout << sm1 << - << sm2 << = << 0 n ; cout << 24 + 0 = 24 n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n; cin >> n; if (n < 4) return puts( NO ), 0; cout << YES << endl; for (int i = 4; i <= 7; ++i) { if ((((n - i) / 2) % 2 == 0) && (n - i) % 2 == 0) solve(n, i); } }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; long long int ara[N]; int main() { long long int n, i, j, k, s = 0, ts; cin >> n; for (i = 1; i <= n; i++) cin >> ara[i]; for (i = 1; i < n; i++) { for (j = 30; ara[i] > 0 && j >= 0; j--) { if ((i + (1 << j)) > n) continue; s += ara[i]; ara[(i + (1 << j))] += ara[i]; ara[i] = 0; } cout << s << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, c, b, ans = 0; cin >> n; int a[n + 1]; for (int i = 1; i <= n - 1; i++) cin >> a[i]; cin >> c >> b; for (int i = c; i <= b - 1; i++) ans += a[i]; cout << ans; }
|
#include <bits/stdc++.h> using namespace std; char a[55][55]; int n, m, x; int dist(int p, int q, int r, int s) { return (p - r) * (p - r) + (q - s) * (q - s); } int ok[128] = {}, appear[128] = {}; char s[1000000]; int main(void) { scanf( %d%d%d , &n, &m, &x); for (int i = 0; i < n; i++) scanf( %s , a[i]); int S = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (a[i][j] == S ) { S = 1; for (int u = 0; u < n; u++) for (int v = 0; v < m; v++) if (dist(i, j, u, v) <= x * x) { ok[(int)a[u][v]] = 1; } } else appear[(int)a[i][j]] = 1; scanf( %d , &n); scanf( %s , s); int ans = 0, f = 0; for (int i = 0; s[i]; i++) if (s[i] >= A && s[i] <= Z ) { if (!S || !appear[s[i] + 32]) f = 1; ans += !ok[s[i] + 32]; } else if (!appear[(int)s[i]]) f = 1; if (f) ans = -1; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast,no-stack-protector ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) #pragma GCC optimize( unroll-loops ) int on_bit(int N, int pos) { return N = N | (1 << pos); } int off_bit(int N, int pos) { return N = N & ~(1 << pos); } bool check_bit(long long int N, int pos) { return (bool)(N & (1 << pos)); } template <class T> inline bool read(T &x) { int c = getchar(); int sgn = 1; while (~c && c < 0 || c > 9 ) { if (c == - ) sgn = -1; c = getchar(); } for (x = 0; ~c && 0 <= c && c <= 9 ; c = getchar()) x = x * 10 + c - 0 ; x *= sgn; return ~c; } int main() { unsigned long long ar[500005]; memset((ar), 0, sizeof((ar))); for (unsigned long long i = 3, j = 1; i <= 500001; i += 2, j++) { ar[i] = ((i * 4) - 4) * j; } for (int i = 5; i <= 500001; i += 2) { ar[i] += ar[i - 2]; } int ___T; cin >> ___T; for (int cs = 1; cs <= ___T; cs++) { int n; cin >> n; cout << ar[n] << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBP_TB_V
`define SKY130_FD_SC_MS__DLRBP_TB_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlrbp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ms__dlrbp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A221OI_PP_BLACKBOX_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long n, x, cnt; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); cin >> n >> x; for (int i = 1; i <= n; i++) { if (x % i == 0 && x / i <= n) { cnt++; } } cout << cnt; return 0; }
|
#include <bits/stdc++.h> using namespace std; int T, a, b, c, d, k; int main() { cin >> T; for (; T--;) { cin >> a >> b >> c >> d >> k; int sol1 = 0; int sol2 = 0; if (a % c == 0) sol1 = a / c; else sol1 = a / c + 1; if (b % d == 0) sol2 = b / d; else sol2 = b / d + 1; if (sol1 + sol2 <= k) cout << sol1 << << sol2 << n ; else cout << -1 << n ; } return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:26:55 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.2 2006/06/22 07:20:00 wig Exp $
// $Date: 2006/06/22 07:20:00 $
// $Log: inst_t_e.v,v $
// Revision 1.2 2006/06/22 07:20:00 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No user `defines in this module
module inst_t_e
//
// Generated module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire test1;
wire [127:0] unsplice_a1_no3;
wire [127:0] unsplice_a2_all128;
wire [127:0] unsplice_a3_up100;
wire [127:0] unsplice_a4_mid100;
wire [127:0] unsplice_a5_midp100;
wire [127:0] unsplice_bad_a;
wire [127:0] unsplice_bad_b;
wire [31:0] widemerge_a1;
wire [31:0] widesig;
wire widesig_r_0;
wire widesig_r_1;
wire widesig_r_10;
wire widesig_r_11;
wire widesig_r_12;
wire widesig_r_13;
wire widesig_r_14;
wire widesig_r_15;
wire widesig_r_16;
wire widesig_r_17;
wire widesig_r_18;
wire widesig_r_19;
wire widesig_r_2;
wire widesig_r_20;
wire widesig_r_21;
wire widesig_r_22;
wire widesig_r_23;
wire widesig_r_24;
wire widesig_r_25;
wire widesig_r_26;
wire widesig_r_27;
wire widesig_r_28;
wire widesig_r_29;
wire widesig_r_3;
wire widesig_r_30;
wire widesig_r_4;
wire widesig_r_5;
wire widesig_r_6;
wire widesig_r_7;
wire widesig_r_8;
wire widesig_r_9;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_a
inst_a_e inst_a (
.p_mix_test1_go(test1), // Use internally test1
.unsplice_a1_no3(unsplice_a1_no3), // leaves 3 unconnected
.unsplice_a2_all128(unsplice_a2_all128), // full 128 bit port
.unsplice_a3_up100(unsplice_a3_up100), // connect 100 bits from 0
.unsplice_a4_mid100(unsplice_a4_mid100), // connect mid 100 bits
.unsplice_a5_midp100(unsplice_a5_midp100), // connect mid 100 bits
.unsplice_bad_a(unsplice_bad_a),
.unsplice_bad_b(unsplice_bad_b), // # conflict
.widemerge_a1(widemerge_a1),
.widesig_o(widesig),
.widesig_r_0(widesig_r_0),
.widesig_r_1(widesig_r_1),
.widesig_r_10(widesig_r_10),
.widesig_r_11(widesig_r_11),
.widesig_r_12(widesig_r_12),
.widesig_r_13(widesig_r_13),
.widesig_r_14(widesig_r_14),
.widesig_r_15(widesig_r_15),
.widesig_r_16(widesig_r_16),
.widesig_r_17(widesig_r_17),
.widesig_r_18(widesig_r_18),
.widesig_r_19(widesig_r_19),
.widesig_r_2(widesig_r_2),
.widesig_r_20(widesig_r_20),
.widesig_r_21(widesig_r_21),
.widesig_r_22(widesig_r_22),
.widesig_r_23(widesig_r_23),
.widesig_r_24(widesig_r_24),
.widesig_r_25(widesig_r_25),
.widesig_r_26(widesig_r_26),
.widesig_r_27(widesig_r_27),
.widesig_r_28(widesig_r_28),
.widesig_r_29(widesig_r_29),
.widesig_r_3(widesig_r_3),
.widesig_r_30(widesig_r_30),
.widesig_r_4(widesig_r_4),
.widesig_r_5(widesig_r_5),
.widesig_r_6(widesig_r_6),
.widesig_r_7(widesig_r_7),
.widesig_r_8(widesig_r_8),
.widesig_r_9(widesig_r_9)
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
inst_b_e inst_b (
.port_b_1(test1) // Use internally test1
);
// End of Generated Instance Port Map for inst_b
// Generated Instance Port Map for inst_c
inst_c_e inst_c (
);
// End of Generated Instance Port Map for inst_c
// Generated Instance Port Map for inst_d
inst_d_e inst_d (
);
// End of Generated Instance Port Map for inst_d
// Generated Instance Port Map for inst_e
inst_e_e inst_e (
.p_mix_unsplice_a1_no3_125_0_gi(unsplice_a1_no3[125:0]), // leaves 3 unconnected
.p_mix_unsplice_a1_no3_127_127_gi(unsplice_a1_no3[127]), // leaves 3 unconnected
.p_mix_unsplice_a2_all128_127_0_gi(unsplice_a2_all128), // full 128 bit port
.p_mix_unsplice_a3_up100_100_0_gi(unsplice_a3_up100[100:0]), // connect 100 bits from 0
.p_mix_unsplice_a4_mid100_99_2_gi(unsplice_a4_mid100[99:2]), // connect mid 100 bits
.p_mix_unsplice_a5_midp100_99_2_gi(unsplice_a5_midp100[99:2]), // connect mid 100 bits
.p_mix_unsplice_bad_a_1_1_gi(unsplice_bad_a[1]),
.p_mix_unsplice_bad_b_1_0_gi(unsplice_bad_b[1:0]), // # conflict
.p_mix_widemerge_a1_31_0_gi(widemerge_a1),
.p_mix_widesig_r_0_gi(widesig_r_0),
.p_mix_widesig_r_10_gi(widesig_r_10),
.p_mix_widesig_r_11_gi(widesig_r_11),
.p_mix_widesig_r_12_gi(widesig_r_12),
.p_mix_widesig_r_13_gi(widesig_r_13),
.p_mix_widesig_r_14_gi(widesig_r_14),
.p_mix_widesig_r_15_gi(widesig_r_15),
.p_mix_widesig_r_16_gi(widesig_r_16),
.p_mix_widesig_r_17_gi(widesig_r_17),
.p_mix_widesig_r_18_gi(widesig_r_18),
.p_mix_widesig_r_19_gi(widesig_r_19),
.p_mix_widesig_r_1_gi(widesig_r_1),
.p_mix_widesig_r_20_gi(widesig_r_20),
.p_mix_widesig_r_21_gi(widesig_r_21),
.p_mix_widesig_r_22_gi(widesig_r_22),
.p_mix_widesig_r_23_gi(widesig_r_23),
.p_mix_widesig_r_24_gi(widesig_r_24),
.p_mix_widesig_r_25_gi(widesig_r_25),
.p_mix_widesig_r_26_gi(widesig_r_26),
.p_mix_widesig_r_27_gi(widesig_r_27),
.p_mix_widesig_r_28_gi(widesig_r_28),
.p_mix_widesig_r_29_gi(widesig_r_29),
.p_mix_widesig_r_2_gi(widesig_r_2),
.p_mix_widesig_r_30_gi(widesig_r_30),
.p_mix_widesig_r_3_gi(widesig_r_3),
.p_mix_widesig_r_4_gi(widesig_r_4),
.p_mix_widesig_r_5_gi(widesig_r_5),
.p_mix_widesig_r_6_gi(widesig_r_6),
.p_mix_widesig_r_7_gi(widesig_r_7),
.p_mix_widesig_r_8_gi(widesig_r_8),
.p_mix_widesig_r_9_gi(widesig_r_9),
.widesig_i(widesig)
);
// End of Generated Instance Port Map for inst_e
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
module tiny1_core(
input clk, // clock
input rst, // reset (neg)
input irq, // interrupt requested
output reg irqack, // interrupt acknowledged
// A single memory port for both reading and writing
output [15:0] mem_addr,
output [15:0] mem_data_o,
input [15:0] mem_data_i,
input [15:0] ram_data_i, // bypass, to avoid circular deps
output mem_wr,
output mem_rd);
parameter FSM_FETCH_ISRC = 0; // macro instruction fetch mode
parameter FSM_FETCH_MPC = 1; // microcode address table lookup
parameter FSM_FETCH_MUOP = 2; // micro instruction fetch mode
parameter FSM_EXEC_MUOP = 3; // micro instruction execution
parameter FSM_MPC_FINISH = 4;
// Memory map:
// 0 - 31: slots for vregs
// 32 - 63: IRQ mode vregs
// 64 - 127: microcode handlers table
// 128 - 139: IRQ handler entry, one for all, must fit 12 bytes
// 140 - 151: Entry point
// 152 - MUEND: mucode
// MUEND+1 - 16383: code + data
// 16384 - 65535: memory-mapped area (handled outside of the core)
// Magic numbers:
parameter ADDR_ENTRY_POINT = 140;
parameter ADDR_IRQ_ENTRY = 128;
// Internal registers:
reg [15:0] PC; // Program counter, visible from the macrocode
reg [15:0] A; // Microcode-visible accumulator
reg [15:0] B; // Microcode-visible accumulator
reg [15:0] C; // Microcode address register
reg [15:0] MPC; // Microcode program counter
reg [15:0] ISRC; // Macrocode instruction source
reg CR; // Carry bit from the previous ALU cycle
// Special registers:
reg [15:0] MuOP; // Current microinstruction (if in an after-read stage)
reg firstMuOP; // Is it the first muOP of an instruction?
// Offset register, if in an IRQ
reg O;
// Macro program counter stored for an IRQ handler
reg [15:0] savedPC;
// Indicates an after-read state
reg afterRead;
// Combinatorial logic: MuOP decoding
wire [15:0] effMuOP;
assign effMuOP = (afterRead)?MuOP:ram_data_i; // never from mmap io
// For convenience, decoding a muOP
wire [1:0] AL = effMuOP[15:14];
wire [1:0] SH = effMuOP[13:12];
wire [1:0] DS = effMuOP[11:10];
wire [1:0] MM = effMuOP[9:8];
wire [1:0] CN = effMuOP[7:6];
wire [1:0] IS = effMuOP[5:4];
wire [3:0] IMMD = effMuOP[3:0];
wire [5:0] SIMMED = effMuOP[5:0];
wire [1:0] IS1 = (CN==0)?IS:0;
// Computing an address: special handling for vregs
wire [15:0] effC;
wire longconst;
assign longconst = (IS==0 && (IMMD&2)) && MM==1;
assign effC = (IS==0 && (IMMD&1))?{O,C[3:0],1'b0}:
(IS==0 && (IMMD&2))?{MPC[15:2],2'b10}:C;
// MPC comes from either memory read or from a register, if it is not the first muOP
wire [15:0] effMPC;
assign effMPC = (firstMuOP)?ram_data_i:MPC;
// Memory read or write address computation
assign mem_addr =
(cpu_state == FSM_FETCH_ISRC)?PC:
(cpu_state == FSM_FETCH_MPC)?{10'b1,ram_data_i[15:11],1'b0}:
(cpu_state == FSM_FETCH_MUOP)?effMPC:
/*(cpu_state == FSM_EXEC_MUOP)?*/ effC;
// Write flag: can only write in exec stage
assign mem_wr = (cpu_state == FSM_EXEC_MUOP &&
MM == 2)?1:0;
// Read flag: always reading something, unless explicitly not reading in
// a muop exec stage
assign mem_rd = (cpu_state == FSM_EXEC_MUOP &&
(MM!=1 || afterRead))?0:1;
// ALU: select source
wire [15:0] SRC;
assign SRC = (MM==1 && afterRead)?mem_data_i:
(MM==3)?((IMMD&1)?CR:ISRC):
(IS1==1)?IMMD:
(IS1==2)?PC:
(IS1==3)?C:A;
// May consider a multi-stage 4-bit adder instead
wire [15:0] ALU1;
wire CR0;
// ALU: select operation
assign {CR0,ALU1} = (AL==0)?SRC+B:
(AL==1)?{1'b0,SRC&B}:
(AL==2)?{1'b0,SRC}:{1'b0,~SRC};
// ALU2 holds the ALU result
wire [15:0] ALU2;
reg ALU2Z;
assign ALU2 = (SH==0)?ALU1:
(SH==1)?ALU1<<1:
(SH==2)?ALU1>>1:
ALU1>>4;
// Computing the next microcode PC (should not really be 16bits)
wire [15:0] MPCdelta;
wire [15:0] ExtSIMMED;
assign ExtSIMMED = (SIMMED[5]==1)?{9'h1ff, SIMMED[5:0], 1'b0}:
/* else */ {9'h0, SIMMED[5:0], 1'b0};
wire [15:0] MPCdeltaDefault;
assign MPCdeltaDefault = longconst?4:2;
assign MPCdelta = (CN==0)?MPCdeltaDefault:
(CN==1)?((ALU2Z)?ExtSIMMED:MPCdeltaDefault):
(CN==2)?((ALU2Z)?MPCdeltaDefault:ExtSIMMED):
ExtSIMMED;
// Memory write
assign mem_data_o = ALU2;
// Main FSM loop
reg [2:0] cpu_state;
always @(posedge clk)
if (!rst) begin
firstMuOP <= 1;
PC <= ADDR_ENTRY_POINT; // FIXED ENTRY POINT
savedPC <= 0;
irqack <= 0;
cpu_state <= FSM_FETCH_ISRC;
afterRead <= 0;
A <= 0;
B <= 0;
C <= 0;
O <= 0;
CR <= 0;
MuOP <= 0;
ALU2Z <= 0;
end else begin
case (cpu_state)
// Fetch the macro opcode from PC,
// or switch to or from the IRQ handling
// and repeat fetching
FSM_FETCH_ISRC: begin
firstMuOP <= 1;
if (irq && !O) begin
savedPC <= PC;
PC <= ADDR_IRQ_ENTRY;
O <= 1;
irqack <= 1;
cpu_state <= FSM_FETCH_ISRC;
end else if(PC == 0 && O) begin
PC <= savedPC;
O <= 0;
irqack <= 0;
cpu_state <= FSM_FETCH_ISRC;
end else begin
cpu_state <= FSM_FETCH_MPC;
end
end // case: FSM_FETCH_ISRC
// Fetch the microcode PC for the current macro opcode
FSM_FETCH_MPC: begin
ISRC <= ram_data_i;
cpu_state <= FSM_FETCH_MUOP;
end
// Fetch the microcode opcode for the current MPC
FSM_FETCH_MUOP: begin
if(firstMuOP) begin
MPC <= ram_data_i;
firstMuOP <= 0;
end
afterRead <= 0;
cpu_state <= FSM_EXEC_MUOP;
end
// Execute the muOP, may take two cycles if reading a memory
FSM_EXEC_MUOP: begin
if (MM == 1 && !afterRead) begin
afterRead <= 1;
cpu_state <= FSM_EXEC_MUOP; // skip one cycle to get the value
MuOP <= effMuOP;
end else begin
// only commit the ALU result if not writing to memory and
// not jumping
if (MM!=2 && CN==0) begin
A <= (DS==0)?ALU2: A;
B <= (DS==1)?ALU2: B;
C <= (DS==2)?ALU2: C;
PC <= (DS==3)?ALU2:PC;
CR <= CR0;
end
ALU2Z <= ALU2==0;
cpu_state <= FSM_MPC_FINISH;
end // else: !if(MM == 1 && !afterRead)
end
FSM_MPC_FINISH: begin
MPC <= MPC + MPCdelta;
// Jumping with 0 offset is a special case, forcing a return to the macro
// instruction mode.
if (MPCdelta == 0) begin
cpu_state <= FSM_FETCH_ISRC;
end else begin
cpu_state <= FSM_FETCH_MUOP;
end
end
endcase
end
endmodule // tiny1_core
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFRTN_PP_SYMBOL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 32; int n, u, r, a[N][N], b[N], p[N], k[N]; long long ans = -1e18; void dfs(int x, bool z) { int i; if (x % 2 == u % 2) { long long t = 0; for (i = 1; i <= n; i = i + 1) t += (long long)a[i][x] * k[i]; ans = max(ans, t); } if (x >= u) return; for (i = 1; i <= n; i = i + 1) a[i][x + 1] = a[p[i]][x] + r; dfs(x + 1, 1); if (z) { for (i = 1; i <= n; i = i + 1) a[i][x + 1] = a[i][x] ^ b[i]; dfs(x + 1, 0); } } int main() { int i, j; cin >> n >> u >> r; for (i = 1; i <= n; i = i + 1) cin >> a[i][0]; for (i = 1; i <= n; i = i + 1) cin >> b[i]; for (i = 1; i <= n; i = i + 1) cin >> k[i]; for (i = 1; i <= n; i = i + 1) cin >> p[i]; dfs(0, 1); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k; string s1, s2; vector<pair<string, string> > ans; map<string, int> u; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> s1 >> s2; map<string, int>::iterator it = u.find(s1); if (it == u.end()) { u[s1] = k, u[s2] = k; ans.push_back(make_pair(s1, s2)); k++; } else { u[s2] = it->second; ans[it->second].second = s2; } } cout << ans.size() << endl; for (size_t i = 0; i < ans.size(); i++) { cout << ans[i].first << << ans[i].second << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = n - 1; i >= 0; i--) cout << a[i] << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = 4e18; const int MAX_LOG = 21; const int MAX_N = (1 << 17); int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, k, a, b, c, d; cin >> n >> k >> a >> b >> c >> d; if (n < 5 || k < n + 1) { cout << -1 << endl; } else { int arr[n]; arr[0] = a, arr[n - 1] = b, arr[1] = c, arr[n - 2] = d; vector<bool> taken(n + 1); taken[a] = taken[b] = taken[c] = taken[d] = true; int id = 1; for (int i = 2; i < n - 2; i++) { while (taken[id]) { id++; } arr[i] = id; taken[id] = true; } for (int i = 0; i < n; i++) { cout << arr[i] << ; } cout << endl; vector<int> v; v.push_back(c); v.push_back(a); v.push_back(arr[2]); for (int i = 3; i <= n - 3; i++) { v.push_back(arr[i]); } v.push_back(b); v.push_back(d); for (int x : v) { cout << x << ; } cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> v, v1; int a, b, c, d, e, f, g, h, i, j, k, l; cin >> a; for (i = 0; i < a; i++) { v.clear(); v1.clear(); cin >> c >> d >> b; map<int, int> m; for (j = 0; j < b; j++) { cin >> e; m[e]++; v.push_back(e); } f = 0; g = -1; h = -1; int min1 = INT_MAX; for (j = 0; j < v.size(); j++) { for (k = d; k <= c; k++) { if (!m.count(k)) { min1 = min(k - d, min1); break; } } for (k = d; k >= 1; k--) { if (!m.count(k)) { min1 = min(d - k, min1); break; } } } cout << min1 << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O221A_PP_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o221a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_PP_SYMBOL_V
|
module mlvds_rx
#(parameter VENDOR="LATTICE",
parameter FILTER_ON_ADDR="YES")
( input c,
input [4:0] mcb_addr,
input [2:0] mlvds_ro, input tx_active,
output [15:0] rxlen, output [7:0] rxd, output rxdv,
output rx_active);
wire [2:0] mlvds_ro_sync;
sync #(.W(3), .S(3)) mlvds_ro_sync_r
(.clk(c), .in(mlvds_ro), .out(mlvds_ro_sync));
wire rxclk = mlvds_ro_sync[0];
wire rxclk_d1;
d1 rxclk_d1_r(.c(c), .d(rxclk) , .q(rxclk_d1));
wire [7:0] rxclk_shift;
wire rxclk_active = |rxclk_shift & ~tx_active;
r #(8) rxclk_shift_r
(.c(c), .rst(1'b0), .en(1'b1),
.d({rxclk_shift[6:0], rxclk}), .q(rxclk_shift));
wire rxclk_posedge = rxclk & ~rxclk_d1 & ~tx_active;
wire rxclk_negedge = ~rxclk & rxclk_d1 & ~tx_active;
wire rxclk_edge = (rxclk_posedge | rxclk_negedge) & ~tx_active;
wire [2:0] mlvds_ro_sync_d1;
d1 #(3) mlvds_ro_sync_d1_r
(.c(c), .d(mlvds_ro_sync), .q(mlvds_ro_sync_d1));
wire [1:0] rxd_posedge;
r #(2) rxd_posedge_r
(.c(c), .rst(1'b0), .en(rxclk_posedge),
.d(mlvds_ro_sync_d1[2:1]), .q(rxd_posedge));
wire [1:0] rxd_negedge;
r #(2) rxd_negedge_r
(.c(c), .rst(1'b0), .en(rxclk_negedge),
.d(mlvds_ro_sync_d1[2:1]), .q(rxd_negedge));
wire [3:0] nibble = { rxd_posedge, rxd_negedge };
wire nibble_dv;
d1 rx_negedge_d1_r(.c(c), .d(rxclk_negedge), .q(nibble_dv));
///////////////////////////////////////////////////////////////////////////
// below here, everything is in the on-chip clk domain
localparam ST_IDLE = 3'd0;
localparam ST_PREAMBLE = 3'd1;
localparam ST_LEN = 3'd2;
localparam ST_ADDR = 3'd3;
localparam ST_FRAME = 3'd4;
localparam ST_CRC = 3'd5;
localparam ST_CHECK = 3'd6;
localparam ST_DRAIN = 3'd7;
localparam SW = 3, CW = 6;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
wire state_rst = (state <= ST_CRC & ~rxclk_active);
r #(SW) state_r
(.c(c), .rst(state_rst), .en(1'b1), .d(next_state), .q(state));
wire nibble_cnt_rst = ctrl[3];
wire [15:0] nibble_cnt;
r #(16) nibble_cnt_r
(.c(c), .rst(nibble_cnt_rst), .en(nibble_dv),
.d(nibble_cnt + 1'b1), .q(nibble_cnt));
// add another stage here to help with timing...
wire [15:0] nibble_cnt_plus4;
r #(16) nibble_cnt_plus4_r
(.c(c), .rst(next_state != state), .en(1'b1),
.d(nibble_cnt + 3'h4), .q(nibble_cnt_plus4));
wire [15:0] rx16;
wire [15:0] rx16_next = { rx16[12:0], nibble };
r #(16) rx16_r(.c(c), .rst(1'b0), .en(nibble_dv), .d(rx16_next), .q(rx16));
wire [14:0] len;
r #(15) len_r
( .c(c), .rst(1'b0), .en(state == ST_LEN & next_state == ST_ADDR),
.d(rx16[14:0]), .q(len));
wire [15:0] len_nibbles = {len, 1'b0};
assign rxlen = {1'b0, len};
wire [15:0] rx_crc;
r #(16) rx_crc_r
( .c(c), .rst(1'b0), .en(state == ST_CRC & next_state == ST_CHECK),
.d(rx16), .q(rx_crc));
wire [7:0] rx_addr;
r #(8) rx_addr_r
(.c(c), .rst(1'b0), .en(state == ST_ADDR & next_state == ST_FRAME),
.d(rx16[7:0]), .q(rx_addr));
// compute the crc byte-wise
wire nibble_dv_d1;
d1 nibble_dv_d1_r(.c(c), .d(nibble_dv), .q(nibble_dv_d1));
wire ctrl_0_d1;
d1 ctrl_0_d1_r(.c(c), .d(ctrl[0]), .q(ctrl_0_d1));
wire rx_byte_dv = ctrl_0_d1 & nibble_dv_d1 & ~nibble_cnt[0];
wire [7:0] rx_byte = rx16[7:0];
wire [15:0] calc_crc;
crc_ccitt crc_ccitt_inst
(.clk(c), .rst(state == ST_IDLE), .d(rx_byte),
.dv(rx_byte_dv), .crc(calc_crc));
wire rxfifo_almost_empty;
wire check_passed;
generate
if (FILTER_ON_ADDR == "YES") begin
assign check_passed = (rx_crc == calc_crc) &
(rx_addr == mcb_addr | rx_addr == 8'hff); // bcast
end else begin
assign check_passed = rx_crc == calc_crc;
end
endgenerate
always @* begin
case (state)
ST_IDLE:
if (nibble_dv)
ctrl = { ST_PREAMBLE, 6'b001000 };
else ctrl = { ST_IDLE , 6'b000000 };
ST_PREAMBLE:
if (rx16_next[7:0] == 8'h16) ctrl = { ST_LEN , 6'b001010 };
else ctrl = { ST_PREAMBLE, 6'b000000 };
ST_LEN:
if (nibble_cnt == 16'd4) ctrl = { ST_ADDR , 6'b001011 };
else ctrl = { ST_LEN , 6'b000001 };
ST_ADDR:
if (nibble_cnt == 16'd2) ctrl = { ST_FRAME , 6'b001001 };
else ctrl = { ST_ADDR , 6'b000001 };
ST_FRAME:
if (nibble_cnt + 16'd2 == len_nibbles) ctrl = { ST_CRC , 6'b001001 };
else ctrl = { ST_FRAME , 6'b000001 };
ST_CRC:
if (nibble_cnt == 16'd4) ctrl = { ST_CHECK , 6'b001010 };
else ctrl = { ST_CRC , 6'b000000 };
ST_CHECK:
if (check_passed) ctrl = { ST_DRAIN , 6'b001000 };
else ctrl = { ST_IDLE , 6'b001000 };
ST_DRAIN:
if (rxfifo_almost_empty) ctrl = { ST_IDLE , 6'b001100 };
else ctrl = { ST_DRAIN , 6'b000100 };
default: ctrl = { ST_IDLE , 6'b001000 };
endcase
end
//assign rxfifo_rst = tx_active | ctrl[3];
assign rx_active = state != ST_IDLE;
generate
if (VENDOR == "LATTICE") begin
wire rxdv_early = state == ST_DRAIN;
d1 rxdv_d1(.c(c), .d(rxdv_early), .q(rxdv));
wire rxfifo_read = ctrl[2];
wire [8:0] rxfifo_count;
fifo_512x8 rxfifo
(.c(c), .rst(state == ST_IDLE),
.d(rx_byte), .dv(rx_byte_dv & state == ST_FRAME),
.q(rxd), .read(rxfifo_read), .count(rxfifo_count),
.almost_empty(rxfifo_almost_empty));
end else if (VENDOR == "ALTERA") begin
assign rxdv = state == ST_DRAIN;
//assign mlvds_rxfifo_rst = tx_active | ctrl[3];
wire rxfifo_read = ctrl[2];
wire [8:0] rxfifo_count;
scfifo #(.lpm_width(8), .lpm_numwords(512), .lpm_widthu(9),
.lpm_showahead("ON"), .intended_device_family("CYCLONE V"),
.use_eab("ON")) rxfifo
(.clock(c),
.wrreq(rx_byte_dv & ((state == ST_ADDR) | (state == ST_FRAME))),
.rdreq(rxfifo_read),
.data(rx_byte), .q(rxd),
.sclr(state == ST_IDLE),
.usedw(rxfifo_count));
assign rxfifo_almost_empty = rxfifo_count == 9'h1 | rxfifo_count == 9'h0;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void splitstr(const string &s, vector<T> &out) { istringstream in(s); out.clear(); copy(istream_iterator<T>(in), istream_iterator<T>(), back_inserter(out)); } static void redirect(int argc, const char **argv) { ios::sync_with_stdio(false); cin.tie(NULL); if (argc > 1) { static filebuf f; f.open(argv[1], ios::in); cin.rdbuf(&f); if (!cin) { cerr << Failed to open << argv[1] << << endl; exit(1); } } if (argc > 2) { static filebuf f; f.open(argv[2], ios::out | ios::trunc); cout.rdbuf(&f); if (!cout) { cerr << Failed to open << argv[2] << << endl; } } } template <typename T> static T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <typename T> static T mod(T a, T m) { a %= m; if (a < 0) a += m; return a; } template <typename T> static T inverse(T a, T m) { a = mod(a, m); if (a <= 1) return a; return mod((1 - inverse(m, a) * m) / a, m); } template <typename T, typename C, T Modulus> class MR { private: struct tag_plus {}; struct tag_minus {}; struct tag_good {}; T value; static_assert(std::numeric_limits<C>::max() / Modulus / Modulus > 0, compute type is too small ); static_assert(Modulus < std::numeric_limits<T>::max() / 2, storage type is too small ); void reduce(tag_plus) { if (value >= Modulus) value -= Modulus; } void reduce(tag_minus) { if (value < 0) value += Modulus; } void reduce(tag_good) {} public: static const T modulus = Modulus; MR() : value(0) {} MR(C value) : value(value % Modulus) { reduce(tag_minus()); } template <typename tag_t> MR(T value, tag_t tag) : value(value) { reduce(tag); } MR &operator=(C value) { this->value = value % Modulus; reduce(tag_minus()); return *this; } MR operator+(MR b) const { return MR(value + b.value, tag_plus()); } MR operator-(MR b) const { return MR(value - b.value, tag_minus()); } MR operator*(MR b) const { return MR(C(value) * C(b.value) % Modulus, tag_good()); } MR operator-() const { return MR(-value, tag_minus()); } MR &operator+=(MR b) { value += b.value; reduce(tag_plus()); return *this; } MR &operator-=(MR b) { value -= b.value; reduce(tag_minus()); return *this; } MR &operator*=(MR b) { value = C(value) * C(b.value) % Modulus; return *this; } bool operator==(MR b) const { return value == b.value; } bool operator!=(MR b) const { return value != b.value; } T get() const { return value; } MR inverse() const { assert(value); return MR(::inverse(C(value), C(Modulus)), tag_good()); } MR operator/(MR b) const { return *this * b.inverse(); } MR &operator/=(MR b) { return *this *= b.inverse(); } }; template <typename T, typename C, T Modulus> static inline std::ostream &operator<<(std::ostream &o, MR<T, C, Modulus> mr) { return o << mr.get(); } int main(int argc, const char **argv) { redirect(argc, argv); int K, pas, pbs; cin >> K >> pas >> pbs; MR<int, long long, 1000000007> pa = MR<int, long long, 1000000007>(pas) / MR<int, long long, 1000000007>(pas + pbs); MR<int, long long, 1000000007> pb = MR<int, long long, 1000000007>(pbs) / MR<int, long long, 1000000007>(pas + pbs); vector<vector<MR<int, long long, 1000000007>>> state( K + 1, vector<MR<int, long long, 1000000007>>(K + 1)); MR<int, long long, 1000000007> scale1 = pa / pb; state[1][0] = 1; MR<int, long long, 1000000007> ans; for (int a = 1; a <= K; a++) for (int s = 0; s <= K; s++) { if (state[a][s] == 0) continue; if (s + a >= K) { MR<int, long long, 1000000007> t = s + a; ans += (scale1 + t) * state[a][s]; } else { state[a + 1][s] += pa * state[a][s]; state[a][s + a] += pb * state[a][s]; } } cout << ans << n ; return 0; }
|
module alt_vipvfr131_common_stream_output
#(parameter
DATA_WIDTH = 10)
(
input wire rst,
input wire clk,
// dout
input wire dout_ready,
output wire dout_valid,
output reg [DATA_WIDTH-1:0] dout_data,
output reg dout_sop,
output reg dout_eop,
// internal
output wire int_ready,
input wire int_valid,
input wire [DATA_WIDTH-1:0] int_data,
input wire int_sop,
input wire int_eop,
// control signals
input wire enable,
output wire synced);
// Simple decode to detect the end of image packets. This allows us to
// synch multiple inputs.
reg image_packet;
reg synced_int;
reg enable_synced_reg;
wire image_packet_nxt;
wire synced_int_nxt;
wire enable_synced;
wire eop;
wire sop;
always @ (posedge clk or posedge rst) begin
if(rst) begin
image_packet <= 1'b0;
synced_int <= 1'b1;
enable_synced_reg <= 1'b0;
end else begin
image_packet <= image_packet_nxt;
synced_int <= synced_int_nxt;
enable_synced_reg <= enable_synced;
end
end
assign sop = dout_valid & dout_sop;
assign eop = dout_valid & dout_eop;
assign image_packet_nxt = (sop && dout_data == 0) || (image_packet && ~eop);
assign synced_int_nxt = (image_packet & eop) | (synced_int & ~sop);
assign enable_synced = (synced_int_nxt) ? enable : enable_synced_reg;
assign synced = ~enable_synced;
// Register outputs and ready input
reg int_valid_reg;
reg int_ready_reg;
always @ (posedge clk or posedge rst) begin
if(rst) begin
int_valid_reg <= 1'b0;
dout_data <= {DATA_WIDTH{1'b0}};
dout_sop <= 1'b0;
dout_eop <= 1'b0;
int_ready_reg <= 1'b0;
end else begin
if(int_ready_reg) begin
if(enable_synced) begin
int_valid_reg <= int_valid;
dout_data <= int_data;
dout_sop <= int_sop;
dout_eop <= int_eop;
end else begin
int_valid_reg <= 1'b0;
end
end
int_ready_reg <= dout_ready;
end
end
assign dout_valid = int_valid_reg & int_ready_reg;
assign int_ready = int_ready_reg & enable_synced;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:37:12 05/18/2016
// Design Name: IF_M
// Module Name: Y:/TEOCOA/EXPR8/TESTIFM.v
// Project Name: EXPR8
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: IF_M
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TESTIFM;
// Inputs
reg [0:0] clka;
reg [0:0] rst;
// Outputs
wire [31:0] Inst_code;
// Instantiate the Unit Under Test (UUT)
IF_M uut (
.clka(clka),
.rst(rst),
.Inst_code(Inst_code)
);
always #50 clka = ~clka;
initial begin
// Initialize Inputs
clka = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 1;
// Add stimulus here
#100;
rst = 0;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AxiLite Slave Conversion
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axilite_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_axilite_conv #
(
parameter C_FAMILY = "virtex6",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [3-1:0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, // Constant =0
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [3-1:0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST, // Constant =1
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, // Constant =0
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] M_AXI_AWPROT,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [3-1:0] M_AXI_ARPROT,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
wire s_awvalid_i;
wire s_arvalid_i;
wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr;
// Arbiter
reg read_active;
reg write_active;
reg busy;
wire read_req;
wire write_req;
wire read_complete;
wire write_complete;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ~ARESETN};
end
assign s_awvalid_i = S_AXI_AWVALID & (C_AXI_SUPPORTS_WRITE != 0);
assign s_arvalid_i = S_AXI_ARVALID & (C_AXI_SUPPORTS_READ != 0);
assign read_req = s_arvalid_i & ~busy & ~|areset_d & ~write_active;
assign write_req = s_awvalid_i & ~busy & ~|areset_d & ((~read_active & ~s_arvalid_i) | write_active);
assign read_complete = M_AXI_RVALID & S_AXI_RREADY;
assign write_complete = M_AXI_BVALID & S_AXI_BREADY;
always @(posedge ACLK) begin : arbiter_read_ff
if (|areset_d)
read_active <= 1'b0;
else if (read_complete)
read_active <= 1'b0;
else if (read_req)
read_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_write_ff
if (|areset_d)
write_active <= 1'b0;
else if (write_complete)
write_active <= 1'b0;
else if (write_req)
write_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_busy_ff
if (|areset_d)
busy <= 1'b0;
else if (read_complete | write_complete)
busy <= 1'b0;
else if ((write_req & M_AXI_AWREADY) | (read_req & M_AXI_ARREADY))
busy <= 1'b1;
end
assign M_AXI_ARVALID = read_req;
assign S_AXI_ARREADY = M_AXI_ARREADY & read_req;
assign M_AXI_AWVALID = write_req;
assign S_AXI_AWREADY = M_AXI_AWREADY & write_req;
assign M_AXI_RREADY = S_AXI_RREADY & read_active;
assign S_AXI_RVALID = M_AXI_RVALID & read_active;
assign M_AXI_BREADY = S_AXI_BREADY & write_active;
assign S_AXI_BVALID = M_AXI_BVALID & write_active;
// Address multiplexer
assign m_axaddr = (read_req | (C_AXI_SUPPORTS_WRITE == 0)) ? S_AXI_ARADDR : S_AXI_AWADDR;
// Id multiplexer and flip-flop
reg [C_AXI_ID_WIDTH-1:0] s_axid;
always @(posedge ACLK) begin : axid
if (read_req) s_axid <= S_AXI_ARID;
else if (write_req) s_axid <= S_AXI_AWID;
end
assign S_AXI_BID = s_axid;
assign S_AXI_RID = s_axid;
assign M_AXI_AWADDR = m_axaddr;
assign M_AXI_ARADDR = m_axaddr;
// Feed-through signals
assign S_AXI_WREADY = M_AXI_WREADY & ~|areset_d;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_WVALID = S_AXI_WVALID & ~|areset_d;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_ARPROT = S_AXI_ARPROT;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__FA_FUNCTIONAL_PP_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> namespace _ { const int inf = 1e9 + 7; namespace _in { template <class T> inline T read() { char ch; bool flag = 0; T x = 0; while (ch = getchar(), !isdigit(ch)) if (ch == - ) flag = 1; while (isdigit(ch)) x = x * 10 + ch - 48, ch = getchar(); return flag ? -x : x; } struct { inline operator long long() { return read<long long>(); } inline operator int() { return read<int>(); } inline operator bool() { return read<bool>(); } template <class T> inline void operator()(T &x) { x = *this; } template <class T, class... A> inline void operator()(T &x, A &...a) { x = *this, this->operator()(a...); } } IN; } // namespace _in using namespace _in; namespace _std { template <class T> inline void swap(T &x, T &y) { x ^= y ^= x ^= y; } template <class T> inline T max(T x, T y) { if (x < y) x = y; return x; } template <class T> inline T min(T x, T y) { if (x > y) x = y; return x; } template <class T> inline void chkmax(T &x, T y) { if (x < y) x = y; } template <class T> inline void chkmin(T &x, T y) { if (x > y) x = y; } } // namespace _std using namespace _std; } // namespace _ using namespace _; const int N = 1e5 + 2; const int LogN = 18; struct Edge_Node { int to, val; }; struct Query { int id1, id2, typ, val; }; char tmp_str[N]; int n, m, q, ans[N], fa_ch[N], len_str[N]; int *str[N]; std::vector<Edge_Node> son[N]; std::vector<Query> que_nod[N]; namespace Hash { const std::pair<unsigned int, unsigned int> base = std::pair<unsigned int, unsigned int>(7, 23); inline std::pair<unsigned int, unsigned int> operator+( const std::pair<unsigned int, unsigned int> &a, const std::pair<unsigned int, unsigned int> &b) { return std::pair<unsigned int, unsigned int>(a.first + b.first, a.second + b.second); } inline std::pair<unsigned int, unsigned int> operator-( const std::pair<unsigned int, unsigned int> &a, const std::pair<unsigned int, unsigned int> &b) { return std::pair<unsigned int, unsigned int>(a.first - b.first, a.second - b.second); } inline std::pair<unsigned int, unsigned int> operator*( const std::pair<unsigned int, unsigned int> &a, const std::pair<unsigned int, unsigned int> &b) { return std::pair<unsigned int, unsigned int>(a.first * b.first, a.second * b.second); } inline bool operator==(const std::pair<unsigned int, unsigned int> &a, const std::pair<unsigned int, unsigned int> &b) { return (a.first == b.first) && (a.second == b.second); } } // namespace Hash using namespace Hash; struct BIT { int lim, res, c[N]; inline int lowbit(int x) { return x & (-x); } inline void update(int x, int y) { for (; x <= lim; x += lowbit(x)) c[x] += y; } inline int _sum(int x) { res = 0; for (; x; x -= lowbit(x)) res += c[x]; return res; } inline int query(int l, int r) { return _sum(r) - _sum(l - 1); } } bit[2]; struct AC_AutoMaton { std::queue<int> que; std::vector<int> son[N]; int tot, tim, ch[N][26], fail[N], pos[N], dfn[N], siz[N]; inline void build() { for (int i = 0; i < 26; ++i) if (ch[0][i]) fail[ch[0][i]] = 0, que.push(ch[0][i]); while (!que.empty()) { int u = que.front(); que.pop(); for (int c = 0; c < 26; ++c) if (ch[u][c]) fail[ch[u][c]] = ch[fail[u]][c], que.push(ch[u][c]); else ch[u][c] = ch[fail[u]][c]; } } inline void insert(int id) { int now = 0, len = len_str[id]; for (int i = 1; i <= len; ++i) { if (!ch[now][str[id][i]]) ch[now][str[id][i]] = ++tot; now = ch[now][str[id][i]]; } pos[id] = now; } void get_son() { for (int i = 1; i <= tot; ++i) son[fail[i]].push_back(i); } void pre_dfn(int u) { dfn[u] = ++tim, siz[u] = 1; for (int v : son[u]) pre_dfn(v), siz[u] += siz[v]; } } acm[2]; namespace LCA { int dep[N], fa[N][LogN]; void get_fa(int u, int f) { fa[u][0] = f, dep[u] = dep[f] + 1; for (int i = 1; i < 18; ++i) fa[u][i] = fa[fa[u][i - 1]][i - 1]; for (Edge_Node now : son[u]) if (now.to != f) get_fa(now.to, u), fa_ch[now.to] = now.val; } inline int Lca(int x, int y) { if (x == y) return x; if (dep[x] < dep[y]) swap(x, y); for (int i = 17; ~i; --i) if (dep[fa[x][i]] >= dep[y]) x = fa[x][i]; if (x == y) return x; for (int i = 17; ~i; --i) if (fa[x][i] != fa[y][i]) x = fa[x][i], y = fa[y][i]; return fa[x][0]; } inline int kth(int x, int d) { if (dep[x] < d) return -1; for (int i = 17; ~i; --i) if (dep[fa[x][i]] >= d) x = fa[x][i]; return x; } } // namespace LCA using namespace LCA; std::pair<unsigned int, unsigned int> sum[N], has_pow[N]; inline std::pair<unsigned int, unsigned int> tree_calc(int x, int y) { return sum[x] - sum[y] * has_pow[dep[x] - dep[y]]; } int tot_bor[2]; struct Border { int s, t, d; } border[N][2]; struct KMP { int n, *las, *nxt, *del; inline void build(int id) { n = len_str[id], nxt = new int[(n + 2)](), las = new int[(n + 2)](), del = new int[(n + 2)](); del[1] = las[1] = 1; for (int i = 2, t = 0; i <= n; ++i) { while (t && str[id][i] != str[id][t + 1]) t = nxt[t]; if (str[id][i] == str[id][t + 1]) ++t; nxt[i] = t, del[i] = i - t, las[i] = (del[i] == del[t]) ? las[t] : i; } } inline void get_border(int pos, int len, int typ) { while (pos > len) pos = nxt[pos]; while (pos > 0) { border[++tot_bor[typ]][typ] = (Border){las[pos], pos, del[pos]}; pos = nxt[las[pos]]; } } } kmp[N][2]; int hep[N]; struct Suffix_Array { std::pair<unsigned int, unsigned int> *has; int n, m, *x, *y, *sa, *ch; inline std::pair<unsigned int, unsigned int> sa_calc(int l, int r) { return has[r] - has[l - 1] * has_pow[r - l + 1]; } inline void sort() { for (int i = 0; i <= m; ++i) hep[i] = 0; for (int i = 1; i <= n; ++i) ++hep[x[i]]; for (int i = 1; i <= m; ++i) hep[i] += hep[i - 1]; for (int i = n; i >= 1; --i) sa[hep[x[y[i]]]--] = y[i]; } inline void build(int id) { n = len_str[id], m = 27; x = new int[(n + 2)](), y = new int[(n + 2)](), sa = new int[(n + 2)](), ch = new int[(n + 2)](); has = new std::pair<unsigned int, unsigned int>[(n + 2)](); has[0] = std::pair<unsigned int, unsigned int>(1, 1); for (int i = 1; i <= n; ++i) has[i] = has[i - 1] * base + std::pair<unsigned int, unsigned int>(str[id][i], str[id][i]); for (int i = 1; i <= n; ++i) x[y[i] = i] = str[id][i] + 1, ch[i] = str[id][i]; sort(); for (int w = 1, p = 0; m = p, p < n; w <<= 1) { for (int i = 1; i <= w; ++i) y[p = i] = n - w + i; for (int i = 1; i <= n; ++i) if (sa[i] > w) y[++p] = sa[i] - w; sort(), std::swap(x, y), x[sa[1]] = p = 1; for (int i = 2; i <= n; ++i) x[sa[i]] = (y[sa[i]] == y[sa[i - 1]] && y[sa[i] + w] == y[sa[i - 1] + w]) ? p : ++p; } } inline int lcp(int p, int u, int lca, int len = 0) { if (u == lca) return 0; p = sa[p], len = n - p + 1; if (len >= dep[u] - dep[lca] && tree_calc(u, lca) == sa_calc(p, p + dep[u] - dep[lca] - 1)) return dep[u] - dep[lca]; else { int las; for (int i = 17; ~i; --i) if (dep[u] - dep[lca] > (1 << i)) { las = u, u = fa[u][i]; if (len >= dep[u] - dep[lca] && tree_calc(u, lca) == sa_calc(p, p + dep[u] - dep[lca] - 1)) u = las; } u = fa[u][0]; return dep[u] - dep[lca]; } } inline bool check(int mid, int u, int lca) { int now = lcp(mid, u, lca); if (now == n - sa[mid] + 1) return true; if (now == dep[u] - dep[lca]) return false; return ch[sa[mid] + now] < fa_ch[kth(u, dep[lca] + now + 1)]; } inline void get_maxlen(int u, int lca, int id, int typ) { int l = 1, r = n, mid, ans = 0; while (l <= r) check(mid = (l + r) >> 1, u, lca) ? ans = mid, l = mid + 1 : r = mid - 1; if (!ans) return; int len = lcp(ans, u, lca), pos = n - sa[ans] + 1; kmp[id][typ].get_border(pos, len, typ); } } sa[N][2]; inline void addedge(int u = 0, int v = 0) { IN(u, v), scanf( %s , tmp_str); son[u].push_back((Edge_Node){v, tmp_str[0] - a }), son[v].push_back((Edge_Node){u, tmp_str[0] - a }); } void get_ac_ans(int u, int t1, int t2) { bit[0].update(acm[0].dfn[t1], 1); bit[1].update(acm[1].dfn[t2], 1); for (Query now : que_nod[u]) { int id = now.id2, p = now.typ, v = now.val, k = acm[p].pos[now.id1]; ans[id] += v * bit[p].query(acm[p].dfn[k], acm[p].dfn[k] + acm[p].siz[k] - 1); } for (Edge_Node now : son[u]) { int v = now.to, c = now.val; if (v == fa[u][0]) continue; get_ac_ans(v, acm[0].ch[t1][c], acm[1].ch[t2][c]); } bit[0].update(acm[0].dfn[t1], -1); bit[1].update(acm[1].dfn[t2], -1); } void get_hash(int u) { for (Edge_Node now : son[u]) { int v = now.to, c = now.val; if (v == fa[u][0]) continue; sum[v] = sum[u] * base + std::pair<unsigned int, unsigned int>(c, c), get_hash(v); } } inline int exgcd(int a, int b, int &x, int &y) { if (!b) return x = 1, y = 0, a; int t = exgcd(b, a % b, y, x); return y -= a / b * x, t; } inline int get_ans(int a, int b, int la, int lb, int c) { int x, y, gcd = exgcd(a, b, x, y); if (c % gcd) return 0; x *= c / gcd, y *= c / gcd; int _a = a / gcd, _b = b / gcd, _x = (x % _b + _b) % _b; y += ((x - _x) / _b) * _a, x = _x; if (y < 0) return 0; if (y > lb) { int t = (y - lb - 1) / _a + 1; y -= t * _a, x += t * _b; } if (x < 0 || y < 0 || x > la || y > lb) return 0; return min((la - x) / _b + 1, y / _a + 1); } inline int kmp_solve(int u, int v, int lca, int id) { tot_bor[0] = tot_bor[1] = 0; sa[id][1].get_maxlen(u, lca, id, 0); sa[id][0].get_maxlen(v, lca, id, 1); int res = 0; for (int i = 1; i <= tot_bor[0]; ++i) for (int j = 1; j <= tot_bor[1]; ++j) if (border[i][0].s + border[j][1].s <= len_str[id] && border[i][0].t + border[j][1].t >= len_str[id]) { int la = (border[i][0].t - border[i][0].s) / border[i][0].d; int lb = (border[j][1].t - border[j][1].s) / border[j][1].d; res += get_ans(border[i][0].d, border[j][1].d, la, lb, len_str[id] - border[i][0].s - border[j][1].s); } return res; } int u, v, id; int main() { IN(n, m, q); for (int i = 2; i <= n; ++i) addedge(); get_fa(1, 0), get_hash(1); has_pow[0] = std::pair<unsigned int, unsigned int>(1, 1); for (int i = 1; i < N; ++i) has_pow[i] = has_pow[i - 1] * base; for (int i = 1; i <= m; ++i) { scanf( %s , tmp_str), len_str[i] = strlen(tmp_str); str[i] = new int[len_str[i] + 2](); for (int j = 1; j <= len_str[i]; ++j) str[i][j] = tmp_str[j - 1] - a ; str[i][0] = str[i][len_str[i] + 1] = -1; acm[0].insert(i); sa[i][0].build(i); kmp[i][0].build(i); std::reverse(str[i] + 1, str[i] + 1 + len_str[i]); acm[1].insert(i); sa[i][1].build(i); kmp[i][1].build(i); std::reverse(str[i] + 1, str[i] + 1 + len_str[i]); } acm[0].build(), acm[0].get_son(), acm[0].pre_dfn(0); acm[1].build(), acm[1].get_son(), acm[1].pre_dfn(0); bit[0].lim = acm[0].tim, bit[1].lim = acm[1].tim; for (int t = 1; t <= q; ++t) { IN(u, v, id); int lca = Lca(u, v); ans[t] = kmp_solve(u, v, lca, id); int t1 = kth(u, min(dep[u], dep[lca] + len_str[id] - 1)); int t2 = kth(v, min(dep[v], dep[lca] + len_str[id] - 1)); if (t1 != u) que_nod[u].push_back((Query){id, t, 1, 1}), que_nod[t1].push_back((Query){id, t, 1, -1}); if (t2 != v) que_nod[v].push_back((Query){id, t, 0, 1}), que_nod[t2].push_back((Query){id, t, 0, -1}); } get_ac_ans(1, 0, 0); for (int i = 1; i <= q; ++i) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct s { long long x; long long y; }; vector<s> v; bool cmp(s a, s b) { if (a.x == b.x) return a.y < b.y; return a.x > b.x; } int main() { long long a, b, c, d, e, i, j, k, xx, yy; s aa, bb; scanf( %lld %lld , &a, &b); for (i = 0; i < a; i++) { scanf( %lld %lld , &aa.x, &aa.y); v.push_back(aa); } sort(v.begin(), v.end(), cmp); xx = v[b - 1].x; yy = v[b - 1].y; long long count = 0; for (i = 0; i < a; i++) { if (xx == v[i].x && yy == v[i].y) { count++; } } cout << count << endl; return 0; }
|
/*
Is not working :-(
*/
/*
`include "DEF.v"
module dcachel2(clock, address, data, read, write, rs_ex_ok, out_address, out_data, out_read, out_write, in_databus, out_databus, write_databus);
input [31:0] address;
inout [31:0] data, out_data;
input read, write;
input [63:0] in_databus;
input clock;
output [31:0] out_address;
output out_read, out_write;
output [63:0] out_databus;
output write_databus;
output rs_ex_ok;
reg [31:0] dcache [19'h7FFFF:0];
reg [31:0] tag [19'h7FFFF:0];
reg dirty [19'h7FFFF:0];
reg [31:0] r_out_address;
reg [31:0] r_out_data;
reg r_out_read, r_out_write;
reg [31:0] r_data;
reg [63:0] r_out_databus;
reg r_write_databus;
reg signed [31:0] r_status;
reg [31:0] r_address;
reg r_lw_or_sw;
reg r_rs_ex_ok;
integer i;
assign data = r_data;
assign out_read = r_out_read;
assign out_write = r_out_write;
assign out_address = r_out_address;
assign out_data = r_out_data;
assign out_databus = r_out_databus;
assign write_databus = r_write_databus;
assign rs_ex_ok = r_rs_ex_ok;
always @(negedge clock)
begin
if(r_status === `DELAY_MEMORY)
begin
r_write_databus <= 1;
end
#0.001
r_status = r_status - 1;
//#0.001 $display("r_status: %d\n", r_status);
#0.001
if(r_status <= 0)
begin
r_write_databus <= 0;
r_out_databus <= 64'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
#0.001
r_write_databus <= 1;
end
end
always @(posedge read)
begin
r_out_read <= 0;
r_out_write <= 0;
r_write_databus <= 0;
if(tag[address % 20'h80000] === address)
begin
r_data <= dcache[address % 20'h80000];
r_out_databus <= 64'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= 1;
r_address <= address;
r_lw_or_sw <= 0;
r_rs_ex_ok <= 1;
end
else
begin
r_rs_ex_ok <= 0;
//$display("miss \n");
//$stop;
if(dirty[address % 20'h80000] === 1)
begin
r_out_address <= tag[address % 20'h80000];
r_out_data <= dcache[address % 20'h80000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address;
r_out_write <= 0;
r_out_data <= 32'hz;
r_out_read <= 1;
#0.001
dcache[address % 20'h80000] <= out_data;
tag[address % 20'h80000] <= address;
dirty[address % 20'h80000] <= 0;
r_data <= out_data;
for(i=0; i<64; i=i+1)
begin
#0.001
r_out_read <= 0;
#0.001
if(dirty[address / 64 * 64 + i] === 1)
begin
r_out_address <= tag[(address / 64 * 64 + i) % 20'h80000];
r_out_data <= dcache[(address / 64 * 64 + i) % 20'h80000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address / 64 * 64 + i;
r_out_write <= 0;
r_out_data <= 32'hz;
r_out_read <= 1;
#0.001
dcache[out_address % 20'h80000] <= out_data;
tag[out_address % 20'h80000] <= out_address;
dirty[out_address % 20'h80000] <= 0;
end
r_out_databus <= 64'b100000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
//r_out_databus <= 64'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= `DELAY_MEMORY;
r_address <= address;
r_lw_or_sw <= 0;
end
end
always @(negedge read)
begin
r_data <= 32'hz;
end
always @(posedge write)
begin
r_write_databus <= 0;
if(tag[address % 20'h80000] === address)
begin
dcache[address % 20'h80000] <= data;
dirty[address % 20'h80000] <= 1;
r_out_databus <= 64'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= 1;
r_address <= address;
r_lw_or_sw <= 1;
r_rs_ex_ok <= 1;
end
else
begin
r_rs_ex_ok <= 0;
if(dirty[address % 20'h80000] === 1)
begin
r_out_address <= tag[address % 20'h80000];
r_out_data <= dcache[address % 20'h80000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_write <= 0;
dcache[address % 20'h80000] <= data;
tag[address % 20'h80000] <= address;
dirty[address % 20'h80000] <= 0;
for(i=0; i<64; i=i+1)
begin
if(address / 64 * 64 + i !== address)
begin
#0.001
if(dirty[address / 64 * 64 + i] === 1)
begin
r_out_address <= tag[(address / 64 * 64 + i) % 20'h80000];
r_out_data <= dcache[(address / 64 * 64 + i) % 20'h80000];
#0.001
r_out_write <= 1;
end
#0.001
r_out_address <= address / 64 * 64 + i;
r_out_write <= 0;
r_out_data <= 32'hz;
r_out_read <= 1;
#0.001
dcache[out_address % 20'h80000] <= out_data;
tag[out_address % 20'h80000] <= out_address;
dirty[address % 20'h80000] <= 0;
end
end
r_out_databus <= 64'b100000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
//r_out_databus <= 64'b000000_00000_00000_00000_00000_000000_000000_00000_00000_00000_00000_000000;
r_status <= `DELAY_MEMORY;
r_address <= address;
r_lw_or_sw <= 1;
end
end
endmodule
*/
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > data; vector<bool> parallel; vector<int> father; vector<int> spec; vector<int> opt; vector<long long> ans; void dfs(int vertex) { if (parallel[vertex]) { int tot = 0; for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; dfs(to); tot += opt[to]; } opt[vertex] = tot; } else { if (spec[vertex] != -1) { opt[vertex] = 1; return; } int mn = 1e9; for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; dfs(to); mn = min(mn, opt[to]); } opt[vertex] = mn; } } void dfs2(int vertex, long long need) { if (parallel[vertex]) { for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; dfs2(to, need); } } else { if (spec[vertex] != -1) { ans[spec[vertex]] = need; return; } for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; if (opt[to] == opt[vertex]) { dfs2(to, need); return; } } } } void solve() { int first; cin >> first; data = {{}}, father = {-1}, spec = {-1}, parallel = {false}; int cur = 0, u = 0; while (true) { char ch = ; while (ch == ) cin >> ch; if (ch == ( ) { data.push_back({}); father.push_back(cur), parallel.push_back(false), spec.push_back(-1); int index = data.size() - 1; data[cur].push_back(index); cur = index; } if (ch == * ) { data.push_back({}); father.push_back(cur), parallel.push_back(false), spec.push_back(u++); int index = data.size() - 1; data[cur].push_back(index); } if (ch == P ) parallel[cur] = true; if (ch == ) ) { cur = father[cur]; } if (cur == 0) break; } ans.assign(u, 0); opt.assign(data.size(), -1); dfs(1); long long need = (long long)first * opt[1]; dfs2(1, need); cout << REVOLTING ; for (int i = 0; i < ans.size(); ++i) cout << ans[i] << ; cout << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; for (int i = 0; i < t; ++i) solve(); }
|
#include <bits/stdc++.h> using namespace std; long long a, b, c, d, ans; char signs[3]; void r1(long long a) { ans = min(ans, a); } void r2(long long a, long long b) { if (signs[2] == * ) { r1(a * b); } else { r1(a + b); } } void r3(long long a, long long b, long long c) { if (signs[1] == * ) { r2(a * b, c); r2(a * c, b); r2(b * c, a); } else { r2(a + b, c); r2(a + c, b); r2(b + c, a); } } void r4(long long a, long long b, long long c, long long d) { if (signs[0] == * ) { r3(a * b, c, d); r3(a * c, b, d); r3(a * d, b, c); r3(b * c, a, d); r3(b * d, a, c); r3(c * d, a, b); } else { r3(a + b, c, d); r3(a + c, b, d); r3(a + d, b, c); r3(b + c, a, d); r3(b + d, a, c); r3(c + d, a, b); } } int main() { cin >> a >> b >> c >> d >> signs[0] >> signs[1] >> signs[2]; ans = 1000000000001; r4(a, b, c, d); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; double pi = acos(-1); struct point { int x, y; } p[2005]; vector<double> v; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d%d , &p[i].x, &p[i].y); long long ans = 0; for (int i = 1; i <= n; i++) { v.clear(); for (int j = 1; j <= n; j++) if (j != i) v.push_back(atan2(p[j].y - p[i].y, p[j].x - p[i].x)); sort(v.begin(), v.end()); int k = 0; int now = 0; for (int j = 0; j < v.size(); j++) { while (v[k] + now * pi < v[j] + pi) { k++; if (k >= v.size()) k = 0, now += 2; } int w = (j - k >= 0 ? j - k : k - j - 1); ans += 1ll * w * (w - 1) / 2 * (n - w - 2) * (n - w - 3) / 2; } } printf( %lld n , ans / 2); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int pwr(long long int base, long long int p) { long long int ans = 1; while (p) { if (p & 1) ans = (ans * base) % 1000000007; base = (base * base) % 1000000007; p /= 2; } return ans; } long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } long long int n; int dyn[5005][5005][2]; char ch[5001][2]; int dp(int neww, int val, int cont) { dyn[neww][val][cont] %= 1000000007; if (neww == n && !val) return 1; if (dyn[neww][val][cont] != -1) return dyn[neww][val][cont]; if (val < 0 || neww > n) return 0; int final = 0; if (ch[neww][0] != f ) { final += dp(neww + 1, val, 0); final = final % 1000000007; } else { final += dp(neww + 1, val + 1, 1); final = final % 1000000007; } if (cont == 0) { final += dp(neww, val - 1, 0); final = final % 1000000007; } final = final % 1000000007; return dyn[neww][val][cont] = final; } int main() { int i, j, k, m; memset(dyn, -1, sizeof dyn); scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %s , &ch[i]); } int ans = dp(0, 0, 0); printf( %d n , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_1_V
`define SKY130_FD_SC_HD__A22OI_1_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22oi_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_1_V
|
//------------------------------------------------------------------------
// ok_wbm.v
//
// $Rev$ $Date$
//------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module ok_wbm (
input wire [7:0] hi_in,
output wire [1:0] hi_out,
inout wire [15:0] hi_inout,
inout wire hi_aa,
output wire hi_muxsel,
input wire clk1,
output wire [7:0] led,
output wire [15:0] jp1,
input wire [3:0] button
);
wire ti_clk;
wire [30:0] ok1;
wire [16:0] ok2;
// Endpoint connections:
wire [15:0] ep00wire;
wire [15:0] ep01wire;
wire [15:0] ep20wire;
wire [15:0] ep21wire;
wire [15:0] ep40trig;
wire [15:0] ep60trig;
// Data
wire ep80_write;
wire ep80_ready;
wire ep80_stb;
wire [15:0] ep80_data;
wire epA0_read;
wire epA0_ready;
wire epA0_stb;
wire [15:0] epA0_data;
// Opal Kelly stuff
assign hi_muxsel = 1'b0;
// Main clock DCM - copied from okLibrary.v
wire dcm_clk1, rstin;
DCM_SP hi_dcm ( .CLKIN (clk1),
.CLKFB (clk),
.CLK0 (dcm_clk1),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.RST (rstin),
.DSSEN (1'b0));
BUFG clk1_buf (.I(dcm_clk1), .O(clk));
// Shift register to implement 4xclk1 reset pulse
SRL16 #(.INIT(16'hF000))
SRL16_inst (.CLK(clk1),.Q(rstin),.D(1'b0),
.A0(1'b1),.A1(1'b1),.A2(1'b1),.A3(1'b1));
// Physical debug IO
wire [15:0] debug_out;
assign jp1 = {debug_out};
assign led = ~{debug_out[7:0]};
// System wires
wire clk;
// Opal Kelly host interface wires
wire rst;
wire irq;
wire done;
wire busy;
// Opal Kelly host interface
assign rst = ep40trig[0];
assign ep21wire = debug_out;
assign ep60trig = {14'd0, irq, done};
// Wishbone Master
wire wb_clk_i;
wire wb_rst_i;
wire wb_ack_i;
wire wb_int_i;
wire wb_cyc_o;
wire wb_stb_o;
wire wb_we_o;
wire [1:0] wb_sel_o;
wire [2:0] wb_cti_o;
wire [15:0] wb_data_i;
wire [15:0] wb_data_o;
wire [4:0] wb_addr_o;
assign wb_clk_i = ti_clk;
assign wb_rst_i = rst;
ok2wbm inst_ok2wbm(
.debug_out(),
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i),
.wb_ack_i(wb_ack_i), .wb_int_i(wb_int_i),
.wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
.wb_addr_o(wb_addr_o), .wb_data_o(wb_data_o), .wb_data_i(wb_data_i),
.wb_sel_o(wb_sel_o), .wb_cti_o(wb_cti_o),
.trg_irq(irq), .trg_done(done), .busy(busy),
.trg_sngl_rd(ep40trig[1]), .trg_sngl_wr(ep40trig[2]),
.trg_brst_rd(epA0_stb), .trg_brst_wr(ep80_stb), .brst_rd(epA0_read), .brst_wr(ep80_write),
.addr_in(ep00wire),
.sngl_data_in(ep01wire), .sngl_data_out(ep20wire),
.brst_data_in(ep80_data), .brst_data_out(epA0_data)
);
// Wishbone Slave Register Map
wb_regmap inst_regmap(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i),
.wb_adr_i(wb_addr_o), .wb_dat_i(wb_data_o), .wb_dat_o(wb_data_i),
.wb_sel_i(wb_sel_o), .wb_cti_i(wb_cti_o),
.wb_we_i(wb_we_o), .wb_stb_i(wb_stb_o), .wb_cyc_i(wb_cyc_o), .wb_ack_o(wb_ack_i),
.wb_err_o(), .wb_int_o(wb_int_i),
.debug_out(debug_out)
);
// Instantiate the okHost and connect endpoints.
wire [17*5-1:0] ok2x;
okHost okHI(
.hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout), .hi_aa(hi_aa), .ti_clk(ti_clk),
.ok1(ok1), .ok2(ok2));
okWireOR # (.N(5)) wireOR (ok2, ok2x);
okWireIn ep00(.ok1(ok1), .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireIn ep01(.ok1(ok1), .ep_addr(8'h01), .ep_dataout(ep01wire));
okWireOut wo20(.ok1(ok1), .ok2(ok2x[ 0*17 +: 17 ]), .ep_addr(8'h20), .ep_datain(ep20wire));
okWireOut wo21(.ok1(ok1), .ok2(ok2x[ 1*17 +: 17 ]), .ep_addr(8'h21), .ep_datain(ep21wire));
okTriggerIn ti40(.ok1(ok1), .ep_addr(8'h40), .ep_clk(wb_clk_i), .ep_trigger(ep40trig));
okTriggerOut to60(.ok1(ok1), .ok2(ok2x[ 2*17 +: 17 ]), .ep_addr(8'h60), .ep_clk(wb_clk_i), .ep_trigger(ep60trig));
okBTPipeIn ep80(.ok1(ok1), .ok2(ok2x[ 3*17 +: 17 ]), .ep_addr(8'h80), .ep_write(ep80_write), .ep_dataout(ep80_data), .ep_blockstrobe(ep80_stb), .ep_ready(~busy));
okBTPipeOut epA0(.ok1(ok1), .ok2(ok2x[ 4*17 +: 17 ]), .ep_addr(8'hA0), .ep_read(epA0_read), .ep_datain(epA0_data), .ep_blockstrobe(epA0_stb), .ep_ready(~busy));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return (b == 0) ? a : gcd(b, a % b); } long long power(long long x, long long p) { if (p == 0) return 1; if (p == 1) return x; if (p % 2) return x * power(x, p - 1); long long y = power(x, p / 2); return y * y; } void solve() { long long n; cin >> n; long long arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } pair<long long, long long> modd, meven; long long odd = 0, even = 0, l = -1, r = -1, res = 0; for (int i = 0; i < n; i++) { if (i % 2) odd += arr[i]; else even += arr[i]; long long cur = odd - even; pair<long long, long long> p; if (i % 2) p = meven; else p = modd; long long val = cur - p.first; if (val > res) { l = p.second; r = i; res = val; } long long x = odd - even + arr[i] * (i % 2 ? -1 : 1); if (i % 2 == 0) { if (x < meven.first) meven = make_pair(x, i); } else { if (x < modd.first) modd = make_pair(x, i); } } if (l != -1) { for (int i = 0; i < (r - l + 1) / 2; i++) { swap(arr[l + i], arr[r - i]); } } odd = 0; even = 0; for (int i = 0; i < n; i++) { if (i % 2) odd += arr[i]; else even += arr[i]; } cout << max(odd, even) << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; const int imax = 1e9 + 7; const long long lmax = 1e18; const int maxn = 2005; int P[maxn], C[maxn], A[maxn]; vector<int> adj[maxn]; vector<int> dfs(int cur) { vector<int> ans(0), v(0); for (int next : adj[cur]) { v = dfs(next); ans.insert(ans.end(), v.begin(), v.end()); } if (((int)ans.size()) < C[cur]) { cout << NO n ; exit(0); } ans.insert(ans.begin() + C[cur], cur); return ans; } int calc() { int i, n; cin >> n; for (i = 0; i < maxn; ++i) adj[i].clear(); for (i = 1; i < n + 1; ++i) { cin >> P[i] >> C[i]; adj[P[i]].push_back(i); } vector<int> v = dfs(adj[0][0]); for (i = 0; i < ((int)v.size()); ++i) { A[v[i]] = i + 1; } cout << YES n ; for (i = 1; i < n + 1; ++i) cout << A[i] << n [i == n]; return 0; } int main() { ios::sync_with_stdio(false); cin.tie(0); calc(); return 0; }
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// valid O 1
// word_fst O 64
// word_snd O 5
// verbosity I 4
// CLK I 1 clock
// RST_N I 1 reset
// req_opcode I 7
// req_f7 I 7
// req_rm I 3
// req_rs2 I 5
// req_v1 I 64
// req_v2 I 64
// req_v3 I 64
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFBox_Top(verbosity,
CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_opcode,
req_f7,
req_rm,
req_rs2,
req_v1,
req_v2,
req_v3,
EN_req,
valid,
word_fst,
word_snd);
input [3 : 0] verbosity;
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [6 : 0] req_opcode;
input [6 : 0] req_f7;
input [2 : 0] req_rm;
input [4 : 0] req_rs2;
input [63 : 0] req_v1;
input [63 : 0] req_v2;
input [63 : 0] req_v3;
input EN_req;
// value method valid
output valid;
// value method word_fst
output [63 : 0] word_fst;
// value method word_snd
output [4 : 0] word_snd;
// signals for module outputs
wire [63 : 0] word_fst;
wire [4 : 0] word_snd;
wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid;
// ports of submodule fbox_core
wire [63 : 0] fbox_core$req_v1,
fbox_core$req_v2,
fbox_core$req_v3,
fbox_core$word_fst;
wire [6 : 0] fbox_core$req_f7, fbox_core$req_opcode;
wire [4 : 0] fbox_core$req_rs2, fbox_core$word_snd;
wire [2 : 0] fbox_core$req_rm;
wire fbox_core$EN_req,
fbox_core$EN_server_reset_request_put,
fbox_core$EN_server_reset_response_get,
fbox_core$RDY_server_reset_request_put,
fbox_core$RDY_server_reset_response_get,
fbox_core$valid;
// rule scheduling signals
wire CAN_FIRE_req,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
WILL_FIRE_req,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get;
// action method server_reset_request_put
assign RDY_server_reset_request_put =
fbox_core$RDY_server_reset_request_put ;
assign CAN_FIRE_server_reset_request_put =
fbox_core$RDY_server_reset_request_put ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
fbox_core$RDY_server_reset_response_get ;
assign CAN_FIRE_server_reset_response_get =
fbox_core$RDY_server_reset_response_get ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = fbox_core$valid ;
// value method word_fst
assign word_fst = fbox_core$word_fst ;
// value method word_snd
assign word_snd = fbox_core$word_snd ;
// submodule fbox_core
mkFBox_Core fbox_core(.verbosity(verbosity),
.CLK(CLK),
.RST_N(RST_N),
.req_f7(fbox_core$req_f7),
.req_opcode(fbox_core$req_opcode),
.req_rm(fbox_core$req_rm),
.req_rs2(fbox_core$req_rs2),
.req_v1(fbox_core$req_v1),
.req_v2(fbox_core$req_v2),
.req_v3(fbox_core$req_v3),
.EN_server_reset_request_put(fbox_core$EN_server_reset_request_put),
.EN_server_reset_response_get(fbox_core$EN_server_reset_response_get),
.EN_req(fbox_core$EN_req),
.RDY_server_reset_request_put(fbox_core$RDY_server_reset_request_put),
.RDY_server_reset_response_get(fbox_core$RDY_server_reset_response_get),
.valid(fbox_core$valid),
.word_fst(fbox_core$word_fst),
.word_snd(fbox_core$word_snd));
// submodule fbox_core
assign fbox_core$req_f7 = req_f7 ;
assign fbox_core$req_opcode = req_opcode ;
assign fbox_core$req_rm = req_rm ;
assign fbox_core$req_rs2 = req_rs2 ;
assign fbox_core$req_v1 = req_v1 ;
assign fbox_core$req_v2 = req_v2 ;
assign fbox_core$req_v3 = req_v3 ;
assign fbox_core$EN_server_reset_request_put = EN_server_reset_request_put ;
assign fbox_core$EN_server_reset_response_get =
EN_server_reset_response_get ;
assign fbox_core$EN_req = EN_req ;
endmodule // mkFBox_Top
|
// MBT 4/1/2014
//
// 2 read-port, 1 write-port ram
//
// reads are asynchronous
//
`include "bsg_defines.v"
module bsg_mem_2r1w #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r1_data_o
);
bsg_mem_2r1w_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
) synth
(.*);
// synopsys translate_off
always_ff @(negedge w_clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (!(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
assert (!(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d (%m)",width_p,els_p,read_write_same_addr_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_2r1w)
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: clock_generator_sdr_s8_diff.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: September 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: BUFIO2 Based SDR clock generator. Takes in a differential clock
// and instantiates two sets of 2 BUFIO2s, one for data transmission
// at input clock rate for one half bank using one BUFIO2, and one for
// clock transmission at double the input clock rate (to get the
// original clock back) using 2 BUFIO2 in the other half bank
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module clock_generator_sdr_s8_diff (clkin_p, clkin_n, ioclka, serdesstrobea, ioclkbp, ioclkbn, serdesstrobeb, gclk) ;
parameter integer S = 8 ; // Parameter to set the serdes factor 1..8
parameter DIFF_TERM = "FALSE" ; // Parameter to enable internal differential termination
input clkin_p, clkin_n ; // differential clock input
output ioclka ; // A ioclock from BUFIO2 for data transmission
output serdesstrobea ; // A serdes strobe from BUFIO2 for data transmission
output ioclkbp ; // B P ioclock from BUFIO2 - for clock transmission
output ioclkbn ; // B N ioclock from BUFIO2 - for clock transmission
output serdesstrobeb ; // B serdes strobe from BUFIO2 - for clock transmission
output gclk ; // global clock output from BUFIO2
wire clkint ; //
wire gclk_int ; //
wire freqgen_in_p ; //
wire tx_bufio2_x1 ; //
assign gclk = gclk_int ;
IBUFGDS #(
.DIFF_TERM (DIFF_TERM))
clk_iob_in (
.I (clkin_p),
.IB (clkin_n),
.O (freqgen_in_p));
BUFIO2 #(
.DIVIDE (S), // The DIVCLK divider divide-by value; default 1
.I_INVERT ("FALSE"), //
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("FALSE"))
bufio2_inst1 (
.I (freqgen_in_p), // Input source clock 0 degrees
.IOCLK (ioclka), // Output Clock for IO
.DIVCLK (tx_bufio2_x1), // Output Divided Clock
.SERDESSTROBE (serdesstrobea)) ; // Output SERDES strobe (Clock Enable)
BUFIO2 #(
.DIVIDE (S), // The DIVCLK divider divide-by value; default 1
.I_INVERT ("FALSE"), //
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("TRUE")) //
bufio2_inst2 (
.I (freqgen_in_p), // Input source clock 0 degrees
.IOCLK (ioclkbp), // Output Clock for IO
.DIVCLK (), // Output Divided Clock
.SERDESSTROBE (serdesstrobeb)) ; // Output SERDES strobe (Clock Enable)
BUFIO2 #(
.I_INVERT ("TRUE"),
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("FALSE")) //
bufio2_inst3 (
.I (freqgen_in_p), // N_clk input from IDELAY
.IOCLK (ioclkbn), // Output Clock
.DIVCLK (), // Output Divided Clock
.SERDESSTROBE ()) ; // Output SERDES strobe (Clock Enable)
BUFG bufg_tx (.I (tx_bufio2_x1), .O (gclk_int)) ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2000005; int lp[N + 1]; vector<int> pr, adj[100005]; vector<int> v[N]; int a[N], ans[100005], depth[100005]; void seive() { for (int i = 2; i <= N; ++i) { if (lp[i] == 0) { lp[i] = i; pr.push_back(i); } for (int j = 0; j < (int)pr.size() && pr[j] <= lp[i] && i * pr[j] <= N; ++j) lp[i * pr[j]] = pr[j]; } } void dfs(int s, int p) { int x = a[s]; while (x > 1) { int te = lp[x]; while (x % te == 0) x /= te; int sz = v[te].size(); if (sz > 0) { ; if (ans[s] == -1 || depth[ans[s]] < depth[v[te][sz - 1]]) ans[s] = v[te][sz - 1]; } v[te].push_back(s); } for (auto it : adj[s]) { if (it != p) { depth[it] = depth[s] + 1; dfs(it, s); } } x = a[s]; while (x > 1) { int te = lp[x]; while (x % te == 0) x /= te; v[te].pop_back(); } } int main() { int n, q, i; seive(); scanf( %d%d , &n, &q); memset(ans, -1, sizeof(ans)); for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i < n - 1; i++) { int a, b; scanf( %d%d , &a, &b); adj[a - 1].push_back(b - 1); adj[b - 1].push_back(a - 1); } dfs(0, -1); while (q--) { int type, v; scanf( %d%d , &type, &v); if (type == 1) { if (ans[v - 1] == -1) ans[v - 1] = -2; printf( %d n , ans[v - 1] + 1); } else { int w; scanf( %d , &w); a[v - 1] = w; memset(ans, -1, sizeof(ans)); dfs(0, -1); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_BLACKBOX_V
`define SKY130_FD_SC_HS__DLXBN_BLACKBOX_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long a[2000], dp[2000]; long long qmod(long long y) { long long res = 1, two = (long long)2; for (; y; y >>= 1) { if (y & 1) res = res * two % mod; two = two * two % mod; } return res; } int main() { long long x, y; int cnt = 0; scanf( %lld%lld , &x, &y); if (y % x) return 0 * puts( 0 ); for (long long i = 1; i <= sqrt(y); ++i) { if (y % i == 0) { if (i % x == 0) a[++cnt] = i; if (i * i != y && y / i % x == 0) a[++cnt] = y / i; } } sort(a + 1, a + 1 + cnt); for (int i = cnt; i > 0; --i) { dp[i] = qmod(y / a[i] - 1); for (int j = i + 1; j <= cnt; ++j) if (a[j] % a[i] == 0) dp[i] = ((dp[i] - dp[j]) % mod + mod) % mod; } printf( %lld n , dp[1]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> v; int n, a, b; while (scanf( %d , &n) != EOF) { v.assign(n, 0); for (int i = 0; i < n; i++) { scanf( %d , &v[i]); } sort(v.begin(), v.end()); a = 1; b = n - 1; while (a < n && v[a] == v[0]) a++; while (b >= 0 && v[b] == v[n - 1]) b--; if (a > b) printf( 0 n ); else printf( %d n , b - a + 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, K; int T[200005]; vector<int> danger; vector<pair<int, int> > v; bool cf(pair<int, int> x, pair<int, int> y) { return x.second * y.first > y.second * x.first; } int main() { scanf( %d %d , &N, &K); for (int i = 0; i < N; i++) { scanf( %d , &T[i]); if (T[i] < 0) { danger.push_back(i); } } if (danger.size() > K) puts( -1 ); else { int change = danger.size() * 2; K -= danger.size(); for (int i = 0; i < (int)danger.size(); i++) { if (i == danger.size() - 1) v.push_back(make_pair(N - danger[i] - 1, 1)); else v.push_back(make_pair(danger[i + 1] - danger[i] - 1, 2)); } sort(v.begin(), v.end(), cf); int idx = 0; while (idx < v.size()) { if (K - v[idx].first >= 0) { K -= v[idx].first; change -= v[idx].second; } idx++; } printf( %d n , change); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int mod = 1e6 + 3; string mm(char c) { if (c == > ) return 1000 ; if (c == < ) return 1001 ; if (c == + ) return 1010 ; if (c == - ) return 1011 ; if (c == . ) return 1100 ; if (c == , ) return 1101 ; if (c == [ ) return 1110 ; if (c == ] ) return 1111 ; } long long pow2(long long a, long long b, long long c = 0) { c = mod; long long res = 1; a %= c; while (b) { if (b & 1) res = (res * a) % c; a = (a * a) % c; b >>= 1; } return res; } int main() { string tmp; cin >> tmp; string ans = ; for (auto &i : tmp) { ans += mm(i); } int sz = ans.length(); int cnt = 0; long long res = 0; for (int i = sz - 1; i >= 0; i--) { if (ans[i] == 1 ) { res += pow2(2, cnt); res %= mod; } cnt++; } cout << res << endl; return 0; }
|
`include "macro.v"
module mem_wb_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire mem_write_enable,
input wire[`REGS_ADDR_BUS] mem_write_addr,
input wire[`REGS_DATA_BUS] mem_write_data,
input wire mem_write_hilo_enable,
input wire[`REGS_DATA_BUS] mem_write_hi_data,
input wire[`REGS_DATA_BUS] mem_write_lo_data,
output reg wb_write_enable,
output reg[`REGS_ADDR_BUS] wb_write_addr,
output reg[`REGS_DATA_BUS] wb_write_data,
output reg wb_write_hilo_enable,
output reg[`REGS_DATA_BUS] wb_write_hi_data,
output reg[`REGS_DATA_BUS] wb_write_lo_data
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
wb_write_enable <= `DISABLE;
wb_write_addr <= 0; // FIXME: 0 is used, but expected NOPRegAddr
wb_write_data <= 0; // FIXME: 0 is used, but expected ZERO_WORD
wb_write_hilo_enable <= `DISABLE;
wb_write_hi_data <= 0; // FIXME: 0 is used, but expected NOPRegAddr
wb_write_lo_data <= 0; // FIXME: 0 is used, but expected ZERO_WORD
end else if (stall[4] == `ENABLE && stall[5] == `DISABLE) begin
wb_write_enable <= `DISABLE;
wb_write_addr <= 0; // FIXME: 0 is used, but expected NOPRegAddr
wb_write_data <= 0; // FIXME: 0 is used, but expected ZERO_WORD
wb_write_hilo_enable <= `DISABLE;
wb_write_hi_data <= 0; // FIXME: 0 is used, but expected NOPRegAddr
wb_write_lo_data <= 0; // FIXME: 0 is used, but expected ZERO_WORD
end else if (stall[4] == `DISABLE) begin
wb_write_enable <= mem_write_enable;
wb_write_addr <= mem_write_addr;
wb_write_data <= mem_write_data;
wb_write_hilo_enable <= mem_write_hilo_enable;
wb_write_hi_data <= mem_write_hi_data;
wb_write_lo_data <= mem_write_lo_data;
end
end
endmodule // mem_wb_buffer
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_ldc
(
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk ({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_dqs),
.delayctrlin (dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin (phy_clk_hr),
.delayctrlin (),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin(leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin (leveled_hr_clocks[0]),
`else
.clkin (leveled_hr_clocks),
`endif
.clkout (hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true")
begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; string ans[N]; int len[N]; int dp[N]; string get_ans(const string &add) { if (add.size() <= 10) { auto res = add; reverse(res.begin(), res.end()); return res; } string res; int t = add.size(); for (int i = t - 1; i >= t - 5; i--) { res += add[i]; } res += ... ; res += add[1]; res += add[0]; return res; } bool check(const string &a) { int t = a.size(); if (a[t - 3] < a[t - 1]) return true; else if (a[t - 3] > a[t - 1]) return false; return dp[t - 1] < 0 || a[dp[t - 1]] < a[t - 1]; } int main() { string s; cin >> s; string a; bool pre = 0; memset(dp, -1, sizeof(dp)); for (int i = s.size() - 1; i >= 0; i--) { a += s[i]; int t = a.size(); if (t > 1) { if (a[t - 1] == a[t - 2]) { dp[t - 1] = dp[t - 2]; } else { dp[t - 1] = t - 2; } } if (!pre) { if (t >= 2) { if (a[t - 1] == a[t - 2] && (i + 1 == s.size() || s[i] == s[i + 1]) && (t == 2 || check(a))) { a.pop_back(); a.pop_back(); pre = 1; } } } else { pre = 0; } len[i] = a.size(); ans[i] = get_ans(a); } for (int i = 0; i < s.size(); i++) { cout << len[i] << << ans[i] << endl; } return 0; }
|
#include<bits/stdc++.h> using namespace std; #define FASTio ios::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL); #define ll long long int #define all(v) (v).begin(), (v).end() #define mp make_pair #define pb push_back #define pf push_front #define ff first #define ss second #define lcm(a, b) ((a) * (b)) / __gcd(a, b) #define umpit unordered_map<ll,ll>::iterator #define mpit map<ll,ll>::iterator #define setit set<ll>::iterator #define mx(a) *max_element(all(a)) #define mn(a) *min_element(all(a)) #define yes cout<< YES n #define no cout<< NO n const ll INF = LLONG_MAX / 2; #define PI 3.1415926535897932384626433832795 #define mod 1000000007 ll bin_exp_mod(ll a,ll n) { ll res=1; a%=mod; if(a==0) return 0; while(n) { if(n&1) res=((res%mod)*(a%mod))%mod; n=n>>1; a=((a%mod)*(a%mod))%mod; } res%=mod; return res; } int main() { FASTio; #ifndef ONLINE_JUDGE //file start freopen( input.txt , r ,stdin); freopen( output.txt , w ,stdout); #endif //file end ll t,i,j; cin>>t; while(t--) { ll n,k; cin>>n>>k; while(k>3) { cout<< 1 ; k--; n--; } vector<ll>arr(k); if(n%3 == 0) { arr[0] = n/3; arr[1] = n/3; arr[2] = n/3; for(auto x : arr) cout<<x<< ; cout<< n ; continue; } if(n%4 == 0) { arr[0] = n/2; arr[1] = n/4; arr[2] = n/4; for(auto x : arr) cout<<x<< ; cout<< n ; continue; } if(n%2 == 0) { arr[0] = n/2 -1; arr[1] = n/2 - 1; arr[2] = 2; for(auto x : arr) cout<<x<< ; cout<< n ; continue; } if(n%2 == 1) { arr[0] = n/2; arr[1] = n/2; arr[2] = 1; for(auto x : arr) cout<<x<< ; cout<< n ; continue; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { list<int> L; int N, M; cin >> N >> M; set<pair<int, int> > S; for (int i = 0; i < M; ++i) { int u, v; cin >> u >> v; S.insert(pair<int, int>(u, v)); } L.push_back(1); for (int i = 2; i <= N; ++i) { list<int>::iterator it = L.begin(); while (it != L.end() && S.count(pair<int, int>(i, *it))) it++; L.insert(it, i); } for (list<int>::iterator it = L.begin(); it != L.end(); ++it) { cout << *it << ; } cout << endl; }
|
#include <bits/stdc++.h> using namespace std; map<char, int> tile = { { + , 15}, { - , 8 + 2}, { | , 1 + 4}, { ^ , 1}, { v , 4}, { > , 2}, { < , 8}, { L , 15 - 8}, { R , 15 - 2}, { U , 15 - 1}, { D , 15 - 4}, { * , 0}, }; int n, m, xt, yt, xm, ym; vector<string> laby; bool ok(char t, int d, int l, int x, int y) { if (x < 0 || x >= n) return false; if (y < 0 || y >= m) return false; int t1 = tile[t], t2 = ((((((((tile[laby[x][y]]) << 1) & 15) + ((tile[laby[x][y]]) >> 3))) << 1) & 15) + ((((((tile[laby[x][y]]) << 1) & 15) + ((tile[laby[x][y]]) >> 3))) >> 3)); for (__typeof(l) _i = 0; _i < (l); ++_i) { t1 = ((((t1) << 1) & 15) + ((t1) >> 3)); t2 = ((((t2) << 1) & 15) + ((t2) >> 3)); } return t1 & t2 & d; } int main() { cin >> n >> m; laby.resize(n); for (__typeof(n) i = 0; i < n; ++i) cin >> laby[i]; cin >> xt >> yt >> xm >> ym; xt--, yt--, xm--, ym--; vector<bool> seen(n * m * 4); deque<pair<int, int>> q = {{0, ((0) * n * m + (xt)*m + yt)}}; while (q.size()) { pair<int, int> p = q.front(); q.pop_front(); int t = p.first, pos = p.second; if (seen[pos]) continue; seen[pos] = true; int l = pos / n / m, y = pos % m, x = pos / m % n; if (x == xm && y == ym) { cout << t << endl; return 0; } q.push_back({t + 1, ((l + 1 & 3) * n * m + (x)*m + y)}); if (ok(laby[x][y], 1, l, x - 1, y)) { q.push_back({t + 1, ((l)*n * m + (x - 1) * m + y)}); } if (ok(laby[x][y], 4, l, x + 1, y)) { q.push_back({t + 1, ((l)*n * m + (x + 1) * m + y)}); } if (ok(laby[x][y], 8, l, x, y - 1)) { q.push_back({t + 1, ((l)*n * m + (x)*m + y - 1)}); } if (ok(laby[x][y], 2, l, x, y + 1)) { q.push_back({t + 1, ((l)*n * m + (x)*m + y + 1)}); } } cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long int i, j, n, m, k; cin >> n; long long int a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } cin >> m; long long int b[m]; for (i = 0; i < m; i++) { cin >> b[i]; } sort(a, a + n); sort(b, b + m); long long int c = 0; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (abs(a[i] - b[j]) <= 1) { b[j] = 1005; c++; break; } } } cout << c << endl; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int tst, t = 1; for (tst = 1; tst <= t; tst++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> a[1000100], b[1000100], ans; stack<int> st; int n, m; bool del[1000100], used[1001000]; int main() { scanf( %d%d , &n, &m); int i; for (i = 1; i <= m; i++) { int u, v; scanf( %d%d , &u, &v); a[u].push_back(v); b[v].push_back(u); } memset(del, 0, sizeof(del)); for (i = 1; i <= n; i++) { if (del[i]) continue; del[i] = 1; st.push(i); int len = a[i].size(), j; for (j = 0; j < len; j++) del[a[i][j]] = 1; } memset(used, 0, sizeof(used)); while (!st.empty()) { int u = st.top(); st.pop(); used[u] = 1; int j, len = b[u].size(); for (j = 0; j < len; j++) if (used[b[u][j]]) { used[u] = 0; break; } if (used[u]) ans.push_back(u); } int len = ans.size(); printf( %d n , ans.size()); for (i = 0; i < len; i++) printf( %d , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 2e5 + 10; const long long oo = 1e18; char s[maxN]; long long cost[maxN][2]; int main() { int test; scanf( %d , &test); while (test--) { int n, a, b; scanf( %d%d%d%*c , &n, &a, &b); gets(s); cost[0][0] = b; cost[0][1] = oo; for (int i = 0; i < n; i++) { if (s[i] == 0 ) { cost[i + 1][0] = min(cost[i][0] + a + b, cost[i][1] + a * 2 + b); cost[i + 1][1] = min(cost[i][0] + 2 * (a + b), cost[i][1] + a + b * 2); } else { cost[i + 1][1] = cost[i][1] + a + b * 2; cost[i + 1][0] = oo; } } printf( %lld n , cost[n][0]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[2505][5005]; int a[5000]; int c1[30], c2[30]; int dif[2505]; int main() { int k, n; scanf( %d%d , &k, &n); scanf( %s , s[0]); bool flag = false; for (int i = 0; i < n; ++i) { c1[s[0][i] - a ]++; if (c1[s[0][i] - a ] > 1) flag = true; } for (int i = 1; i < k; ++i) { scanf( %s , s[i]); memset(c2, 0, sizeof(c2)); for (int j = 0; j < n; ++j) { c2[s[i][j] - a ]++; if (s[i][j] != s[0][j]) dif[i]++; } if (dif[i] > 4) { cout << -1 n ; return 0; } for (int j = 0; j < 26; ++j) { if (c1[j] != c2[j]) { cout << -1 n ; return 0; } } } for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { bool ok = true; for (int l = 1; l < k; ++l) { a[l] = dif[l]; a[l] -= (s[0][i] != s[l][i]); a[l] -= (s[0][j] != s[l][j]); a[l] += (s[0][i] != s[l][j]); a[l] += (s[0][j] != s[l][i]); if ((a[l] == 0 && flag) || a[l] == 2) continue; ok = false; break; } if (ok) { swap(s[0][i], s[0][j]); cout << s[0] << endl; return 0; } } } cout << -1 n ; return 0; }
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
/*
* Wishbone 3 port multiplexer
*/
module wb_mux_3 #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
input wire clk,
input wire rst,
/*
* Wishbone master input
*/
input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
input wire wbm_we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
input wire wbm_stb_i, // STB_I strobe input
output wire wbm_ack_o, // ACK_O acknowledge output
output wire wbm_err_o, // ERR_O error output
output wire wbm_rty_o, // RTY_O retry output
input wire wbm_cyc_i, // CYC_I cycle input
/*
* Wishbone slave 0 output
*/
output wire [ADDR_WIDTH-1:0] wbs0_adr_o, // ADR_O() address output
input wire [DATA_WIDTH-1:0] wbs0_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs0_dat_o, // DAT_O() data out
output wire wbs0_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs0_sel_o, // SEL_O() select output
output wire wbs0_stb_o, // STB_O strobe output
input wire wbs0_ack_i, // ACK_I acknowledge input
input wire wbs0_err_i, // ERR_I error input
input wire wbs0_rty_i, // RTY_I retry input
output wire wbs0_cyc_o, // CYC_O cycle output
/*
* Wishbone slave 0 address configuration
*/
input wire [ADDR_WIDTH-1:0] wbs0_addr, // Slave address prefix
input wire [ADDR_WIDTH-1:0] wbs0_addr_msk, // Slave address prefix mask
/*
* Wishbone slave 1 output
*/
output wire [ADDR_WIDTH-1:0] wbs1_adr_o, // ADR_O() address output
input wire [DATA_WIDTH-1:0] wbs1_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs1_dat_o, // DAT_O() data out
output wire wbs1_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs1_sel_o, // SEL_O() select output
output wire wbs1_stb_o, // STB_O strobe output
input wire wbs1_ack_i, // ACK_I acknowledge input
input wire wbs1_err_i, // ERR_I error input
input wire wbs1_rty_i, // RTY_I retry input
output wire wbs1_cyc_o, // CYC_O cycle output
/*
* Wishbone slave 1 address configuration
*/
input wire [ADDR_WIDTH-1:0] wbs1_addr, // Slave address prefix
input wire [ADDR_WIDTH-1:0] wbs1_addr_msk, // Slave address prefix mask
/*
* Wishbone slave 2 output
*/
output wire [ADDR_WIDTH-1:0] wbs2_adr_o, // ADR_O() address output
input wire [DATA_WIDTH-1:0] wbs2_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs2_dat_o, // DAT_O() data out
output wire wbs2_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs2_sel_o, // SEL_O() select output
output wire wbs2_stb_o, // STB_O strobe output
input wire wbs2_ack_i, // ACK_I acknowledge input
input wire wbs2_err_i, // ERR_I error input
input wire wbs2_rty_i, // RTY_I retry input
output wire wbs2_cyc_o, // CYC_O cycle output
/*
* Wishbone slave 2 address configuration
*/
input wire [ADDR_WIDTH-1:0] wbs2_addr, // Slave address prefix
input wire [ADDR_WIDTH-1:0] wbs2_addr_msk // Slave address prefix mask
);
wire wbs0_match = ~|((wbm_adr_i ^ wbs0_addr) & wbs0_addr_msk);
wire wbs1_match = ~|((wbm_adr_i ^ wbs1_addr) & wbs1_addr_msk);
wire wbs2_match = ~|((wbm_adr_i ^ wbs2_addr) & wbs2_addr_msk);
wire wbs0_sel = wbs0_match;
wire wbs1_sel = wbs1_match & ~(wbs0_match);
wire wbs2_sel = wbs2_match & ~(wbs0_match | wbs1_match);
wire master_cycle = wbm_cyc_i & wbm_stb_i;
wire select_error = ~(wbs0_sel | wbs1_sel | wbs2_sel) & master_cycle;
// master
assign wbm_dat_o = wbs0_sel ? wbs0_dat_i :
wbs1_sel ? wbs1_dat_i :
wbs2_sel ? wbs2_dat_i :
{DATA_WIDTH{1'b0}};
assign wbm_ack_o = wbs0_ack_i |
wbs1_ack_i |
wbs2_ack_i;
assign wbm_err_o = wbs0_err_i |
wbs1_err_i |
wbs2_err_i |
select_error;
assign wbm_rty_o = wbs0_rty_i |
wbs1_rty_i |
wbs2_rty_i;
// slave 0
assign wbs0_adr_o = wbm_adr_i;
assign wbs0_dat_o = wbm_dat_i;
assign wbs0_we_o = wbm_we_i & wbs0_sel;
assign wbs0_sel_o = wbm_sel_i;
assign wbs0_stb_o = wbm_stb_i & wbs0_sel;
assign wbs0_cyc_o = wbm_cyc_i & wbs0_sel;
// slave 1
assign wbs1_adr_o = wbm_adr_i;
assign wbs1_dat_o = wbm_dat_i;
assign wbs1_we_o = wbm_we_i & wbs1_sel;
assign wbs1_sel_o = wbm_sel_i;
assign wbs1_stb_o = wbm_stb_i & wbs1_sel;
assign wbs1_cyc_o = wbm_cyc_i & wbs1_sel;
// slave 2
assign wbs2_adr_o = wbm_adr_i;
assign wbs2_dat_o = wbm_dat_i;
assign wbs2_we_o = wbm_we_i & wbs2_sel;
assign wbs2_sel_o = wbm_sel_i;
assign wbs2_stb_o = wbm_stb_i & wbs2_sel;
assign wbs2_cyc_o = wbm_cyc_i & wbs2_sel;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:44:25 01/22/2017
// Design Name:
// Module Name: bi_directional_shift
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// An 8-Bit Barrel Shifter designed to work off of only a reverse filter and
// a left-barrel shift. The shift_direction is used to determine if the left_barrel_shifter
// is returned of if the right_shift is returned via a path of:
// bit_reverse,left_shift,bit_reverse
//////////////////////////////////////////////////////////////////////////////////
module bi_directional_shift(
input wire [7:0] d_in,
input wire [2:0] shift_amount,
input wire shift_direction, // 0 = left, 1 = right
output wire [7:0] shifter_out
);
wire [7:0] pre_reverse;
wire [7:0] l_d_out;
wire [7:0] post_reverse;
wire [7:0] mux1_out;
//wire [7:0] mux2_out;
bit_reverse pre (
.d_in (d_in),
.d_out (pre_reverse)
);
mux2_1 mux1 (
.input1 (d_in),
.input2 (pre_reverse),
.select (shift_direction),
.selected_out (mux1_out)
);
left_barrel_shifter left_1 (
.d_in (mux1_out),
.shift_amount (shift_amount),
.d_out (l_d_out)
);
bit_reverse post (
.d_in (l_d_out),
.d_out (post_reverse)
);
mux2_1 mux2 (
.input1 (l_d_out),
.input2 (post_reverse),
.select (shift_direction),
.selected_out (shifter_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = (1e6) + 5; const int IT_MAX = 1 << 20; const int INF = -1; int bit[IT_MAX + 10]; void update(int p, int dv) { for (; p <= IT_MAX; p += p & (-p)) bit[p] += dv; } int query(int p) { int rv = 0; for (; p; p -= p & (-p)) rv += bit[p]; return rv; } int largerpos(int v) { if (bit[IT_MAX] <= v) return INF; int p = 0; int s = 0; for (int i = 19; i >= 0; i--) { if (s + bit[p + (1 << i)] <= v) { s += bit[p + (1 << i)]; p |= (1 << i); } } return p + 1; } vector<int> st[MAX], en[MAX]; int l[MAX], r[MAX]; int pa[MAX], sz[MAX]; int finPa(int p) { return pa[p] == p ? p : pa[p] = finPa(pa[p]); } bool mergeNode(int u, int v) { int r1 = finPa(u), r2 = finPa(v); if (sz[r1] < sz[r2]) { swap(r1, r2); } pa[r2] = r1; sz[r1] += sz[r2]; return (r1 == r2); } int main() { ios::sync_with_stdio(false); for (int i = 1; i <= MAX; i++) { sz[i] = 1; pa[i] = i; } int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> l[i] >> r[i]; st[l[i]].push_back(i); en[r[i]].push_back(i); } for (int i = 1; i <= 2 * n; i++) { for (int s : st[i]) { update(l[s], 1); } for (int s : en[i]) { int nex = largerpos(query(l[s])); while (nex != -1) { for (int ns : st[nex]) { if (mergeNode(s, ns)) { cout << NO << endl; return 0; } } nex = largerpos(query(nex)); } } for (int s : en[i]) { update(l[s], -1); } } int p = finPa(1); cout << ((sz[p] == n) ? YES : NO ) << endl; return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: note2dds_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module note2dds_rom (
address,
clock,
q);
input [3:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../../modules/note2dds.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 4,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../modules/note2dds.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "4"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../modules/note2dds.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL "address[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL note2dds_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL note2dds_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL note2dds_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL note2dds_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL note2dds_rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL note2dds_rom_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int maxn = 500010; int m, k, n, s, a[maxn], b[maxn], c[maxn], maxx, tong[maxn], ansl, ansr, vis[maxn]; bool check(int l, int r) { memcpy(c, tong, sizeof(c)); for (int i = l; i <= r; i++) c[a[i]]--; for (int i = 1; i <= maxx; i++) if (c[i] > 0) { return false; } return true; } void gen(int l, int r) { int temp = l - (min(n - 1, (l - 1) / k) * k + 1); temp += max(0, r - l + 1 - k); if (temp <= m - n * k) { printf( %d n , temp); int num = 0; for (int i = min(n - 1, (l - 1) / k) * k + 1; i < l; i++) { printf( %d , i); num++; } int num2 = 0; memset(c, 0, sizeof(c)); for (int i = l; i <= r; i++) if (c[a[i]] + 1 <= tong[a[i]]) { vis[i] = 1; c[a[i]]++; num2++; } num2 = r - l + 1 - num2; num += num2; for (int i = l; i <= r; i++) if (!vis[i] && num > temp) { num--; vis[i] = 1; } for (int i = l; i <= r; i++) if (!vis[i]) printf( %d , i); exit(0); } } void solve(int x) { memset(c, 0, sizeof(c)); int cur = m; for (int i = x; i <= m; i++) c[a[i]]++; for (int i = x - 1; i >= 1; i--) { c[a[i]]++; while (cur > i) { if (c[a[cur]] - 1 >= tong[a[cur]] && c[a[cur - 1]] + 1 >= tong[a[cur - 1]]) { c[a[cur]]--; cur--; } else break; } gen(i, cur); } } int main() { scanf( %d%d%d%d , &m, &k, &n, &s); for (int i = 1; i <= m; i++) scanf( %d , &a[i]); for (int i = 1; i <= s; i++) { scanf( %d , &b[i]); maxx = max(maxx, b[i]); tong[b[i]]++; } int l = 1, r = m, res = 0; while (l <= r) { int mid = (l + r) >> 1; if (check(mid, m)) { res = mid; l = mid + 1; } else r = mid - 1; } if (res) { gen(res, m); solve(res); puts( -1 ); } else puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 5e3 + 5, mod = 1e9 + 7, mod1 = 998244353, mod2 = 1e9 + 9, inf = 1e18 + 7; const long long infll = 1e18 + 7; long long n, k, X, Y, Z; long long a[(long long)3e5 + 5]; long long dp[N][N]; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; Y = n % k; X = k - Y; Z = n / k; for (long long i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + 1 + n); for (long long i = 0; i <= X; i++) { for (long long j = 0; j <= Y; j++) { if (i == 0 && j == 0) { dp[i][j] = 0; continue; } dp[i][j] = inf; long long t = i * Z + j * (Z + 1); if (i) { dp[i][j] = min(dp[i][j], dp[i - 1][j] + a[t] - a[t - Z + 1]); } if (j) { dp[i][j] = min(dp[i][j], dp[i][j - 1] + a[t] - a[t - Z]); } } } cout << dp[X][Y]; }
|
#include <bits/stdc++.h> using namespace std; void fastInOut(); unsigned long long power(unsigned long long b, unsigned long long pow) { if (b == 0) return 0; else if (pow == 1) return b; else if (pow % 2 == 0) return power(b * b, pow / 2); else return b * power(b * b, pow / 2); } int power(int z, int i) { int zz = 1; for (int k = 0; k < i; k++) { zz *= z; } return zz; } long long power(long long x, long long y) { long long z = 1; for (long long i = 0; i < y; i++) z *= x; return z; } bool right(int arr[]) { int a[3]; a[0] = power(arr[3] - arr[1], 2) + power(arr[2] - arr[0], 2); a[1] = power(arr[5] - arr[1], 2) + power(arr[4] - arr[0], 2); a[2] = power(arr[5] - arr[3], 2) + power(arr[4] - arr[2], 2); sort(a, a + 3); if (a[0] + a[1] == a[2] && (sqrt(a[0]) * sqrt(a[1]) * sqrt(a[2])) / 2) return true; return false; } bool fed(int k, int f, int test) { if (f < test) swap(f, test); int c = 0; while (f) { if ((f & 1) != (test & 1)) c++; f = f >> 1; test = test >> 1; if (c > k) return false; } if (c > k) return false; return true; } unsigned long long fact(long long a) { unsigned long long res = 1; for (long long i = a; i > 0; i--) res *= i; return res; } unsigned long long comb(long long a, long long b) { if ((a - b) < b) b = a - b; if (a <= 19) return fact(a) / (fact(a - b) * fact(b)); if (a == b || b == 0) return 1; if (b == 1) return a; return comb(a - 1, b - 1) + comb(a - 1, b); } bool palind(string s) { for (unsigned int i = 0, f = s.size() - 1; i < s.size() / 2; i++, f--) if (s[i] != s[f]) return false; return true; } int div(long long x) { double SqrtOfnumber; SqrtOfnumber = sqrt(x); int counter = 1; int i; for (i = 2; i < SqrtOfnumber; i++) { if (x % i == 0) counter++; } counter = counter * 2; if (i * i == x) counter++; return counter; } bool isprim(int x) { for (int i = x - 1; i > 1; i--) { if (x % i == 0) return false; } return true; } set<long long> prim(int n) { n++; bool *arr = new bool[n]; for (int i = 0; i < n; i++) arr[i] = true; set<long long> se; for (int i = 2; i * i < n; i++) if (arr[i]) for (int k = i * i; k < n; k += i) arr[k] = false; for (int i = 2; i < n; i++) if (arr[i]) se.insert(i); return se; } int n, m; char arr[1010][1010]; bool pash(int x, int y) { int s; s = 1; if (x + 1 < n && arr[x + 1][y] == b ) s++; if (x + 1 < n && y + 1 < m && arr[x + 1][y + 1] == b ) s++; if (y + 1 < m && arr[x][y + 1] == b ) s++; if (s == 4) return true; s = 1; if (x - 1 >= 0 && arr[x - 1][y] == b ) s++; if (x - 1 >= 0 && y + 1 < m && arr[x - 1][y + 1] == b ) s++; if (y + 1 < m && arr[x][y + 1] == b ) s++; if (s == 4) return true; s = 1; if (x - 1 >= 0 && arr[x - 1][y] == b ) s++; if (x - 1 >= 0 && y - 1 >= 0 && arr[x - 1][y - 1] == b ) s++; if (y - 1 >= 0 && arr[x][y - 1] == b ) s++; if (s == 4) return true; s = 1; if (x + 1 < n && arr[x + 1][y] == b ) s++; if (x + 1 < n && y - 1 >= 0 && arr[x + 1][y - 1] == b ) s++; if (y - 1 >= 0 && arr[x][y - 1] == b ) s++; if (s == 4) return true; return false; } int main() { fastInOut(); int n, m, x; string res = YES ; cin >> n >> m; vector<int> v; for (int i = 0; i < m; i++) { cin >> x; v.push_back(x); } sort(v.begin(), v.end()); if (v.size()) { if (*min_element(v.begin(), v.end()) == 1 || *max_element(v.begin(), v.end()) == n) res = NO ; else for (int i = 0; i < m - 2; i++) if (v[i + 1] - v[i] == 1 && v[i + 2] - v[i] == 2) { res = NO ; break; } } cout << res; return 0; } void fastInOut() { ios_base::sync_with_stdio(0); cin.tie(NULL), cout.tie(NULL); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Rod Steward.
module IOBUF ( input T, input I, output O, inout IO );
assign O = IO;
assign IO = T ? 1'bz : I;
endmodule
module t
(
input [7:0] inlines,
output [7:0] outlines,
inout [7:0] iolines,
input inctrl
);
generate for (genvar i = 4; i < 8; i = i+1) begin: Gen_D
IOBUF d ( .T(inctrl), .I(inlines[i]), .O(outlines[i]), .IO(iolines[i]) );
pullup d_pup (iolines[i]);
end
endgenerate
IOBUF d_0 ( .T(inctrl), .I(inlines[0]), .O(outlines[0]), .IO(iolines[0]) );
pullup d_0_pup (iolines[0]);
IOBUF d_1 ( .T(inctrl), .I(inlines[1]), .O(outlines[1]), .IO(iolines[1]) );
pullup d_1_pup (iolines[1]);
IOBUF d_2 ( .T(inctrl), .I(inlines[2]), .O(outlines[2]), .IO(iolines[2]) );
pullup d_2_pup (iolines[2]);
IOBUF d_3 ( .T(inctrl), .I(inlines[3]), .O(outlines[3]), .IO(iolines[3]) );
pullup d_3_pup (iolines[3]);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_2_V
`define SKY130_FD_SC_HD__A31O_2_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31o_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_2_V
|
module digit_state_machine(
input clk,
input reset_n,
input [3:0] units,
input [3:0] tens,
input [3:0] hundreds,
input [3:0] thousands,
output reg [2:0] digit_select,
output reg [3:0] data,
output reg decimal_point
);
reg [1:0] state;
reg [1:0] state_n;
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
always @ (posedge clk, negedge reset_n)
begin
if(!reset_n)
state <= S0;
else
state <= state_n;
end
always @ (*)
begin
case(state)
S0: state_n = S1;
S1: state_n = S2;
S2: state_n = S3;
S3: state_n = S0;
default: state_n = S0;
endcase
end
always @ (*)
begin
case(state)
S0: begin
decimal_point = 1;
digit_select = 3'b000;
data = units;
end
S1: begin
decimal_point = 1;
digit_select = 3'b001;
data = tens;
end
S2: begin
decimal_point = 1;
digit_select = 3'b011;
data = hundreds;
end
S3: begin
decimal_point = 0;
digit_select = 3'b100;
data = thousands;
end
endcase
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_70x256.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_70x256 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input [69:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [69:0] q;
output rdempty;
output wrfull;
wire sub_wire0;
wire sub_wire1;
wire [69:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [69:0] q = sub_wire2[69:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone III",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 70,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "70"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "70"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "70"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 70 0 INPUT NODEFVAL data[69..0]
// Retrieval info: USED_PORT: q 0 0 70 0 OUTPUT NODEFVAL q[69..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 70 0 data 0 0 70 0
// Retrieval info: CONNECT: q 0 0 70 0 @q 0 0 70 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; signed main() { ios::sync_with_stdio(NULL); cin.tie(0); cout.tie(0); int a, b, c; cin >> a >> b >> c; c -= 2; b -= 1; int ans = min({a, b, c}); if (ans < 0) { cout << 0; } else { ans = ans * 3 + 3; cout << ans; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, w, l; cin >> n >> l >> w; long double p[n + 1]; long long int b[n + 1]; for (long long int i = 1; i <= n; i++) { cin >> p[i]; p[i] /= 100; } for (long long int i = 1; i <= n; i++) { cin >> b[i]; b[i]++; } long double a[n + 1][n + 1][n + 1]; for (long long int i = 0; i <= n; i++) { for (long long int j = 0; j <= n; j++) { for (long long int k = 0; k <= n; k++) { a[i][j][k] = 0; } } } long double x, y; long long int z = 0; if (w > n) w = n; a[0][0][w] = 1; for (long long int i = 1; i <= n; i++) { for (long long int j = 0; j <= i; j++) { for (long long int k = 0; k <= n; k++) { z = b[i]; z += k; if (z > n) z = n; if (j > 0) a[j][i - j][z] += ((a[j - 1][i - j][k]) * (p[i])); if ((i - j) > 0) a[j][i - j][k] += ((a[j][i - j - 1][k]) * (1.0 - p[i])); } } } long double ans = 0.0; for (long long int i = 0; i <= n; i++) { for (long long int j = 0; j <= n; j++) { for (long long int k = 0; k <= n; k++) { if ((k >= i) && (i >= l) && ((i + j) == n)) { ans += a[i][j][k]; } } } } cout << fixed << setprecision(6) << ans; }
|
#include <bits/stdc++.h> using namespace std; int n; long long ans, sum[300030], cnt[300030], tot[3]; int main() { scanf( %d , &n); tot[0] = 1; for (int i = 1; i <= n; i++) { long long x; scanf( %lld , &x); while (x) { cnt[i] += x % 2; x >>= 1; } sum[i] = sum[i - 1] + cnt[i]; ans += tot[sum[i] % 2]; for (int j = i, k = i + 1, maxx = 0; j >= 1 && j >= i - 64; j--) { while (k > j) maxx = max(1ll * maxx, cnt[k - 1]), k--; if (maxx * 2 > sum[i] - sum[j - 1] && ((sum[i] % 2) == (sum[j - 1] % 2))) ans--; } ++tot[sum[i] % 2]; } printf( %lld , ans); return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_fpext_32ns_64_1
#(parameter
ID = 4,
NUM_STAGE = 1,
din0_WIDTH = 32,
dout_WIDTH = 64
)(
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire a_tvalid;
wire [31:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
//------------------------Instantiation------------------
ANN_ap_fpext_0_no_dsp_32 ANN_ap_fpext_0_no_dsp_32_u (
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata = din0==='bx ? 'b0 : din0;
assign dout = r_tdata;
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module gpmc_model_sync
(output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6,
output reg EM_NWE, output reg EM_NOE );
reg [15:0] EM_D_int;
assign EM_D = EM_D_int;
initial
begin
EM_CLK <= 0;
EM_A <= 10'bz;
EM_NBE <= 2'b11;
EM_NWE <= 1;
EM_NOE <= 1;
EM_NCS4 <= 1;
EM_NCS6 <= 1;
EM_D_int <= 16'bz;
EM_WAIT0 <= 0; // FIXME this is actually an input
end
task GPMC_Write;
input ctrl;
input [10:0] addr;
input [15:0] data;
begin
EM_CLK <= 1;
#10;
EM_CLK <= 0;
EM_NWE <= 0;
if(ctrl)
EM_NCS6 <= 0;
else
EM_NCS4 <= 0;
EM_A <= addr[10:1];
EM_D_int <= data;
#10;
EM_CLK <= 1;
#10;
EM_CLK <= 0;
EM_NWE <= 1;
EM_NCS4 <= 1;
EM_NCS6 <= 1;
EM_A <= 10'bz;
EM_D_int <= 16'bz;
#100;
end
endtask // GPMC_Write
task GPMC_Read;
input ctrl;
input [10:0] addr;
begin
#1.3;
EM_A <= addr[10:1];
#3;
if(ctrl)
EM_NCS6 <= 0;
else
EM_NCS4 <= 0;
#14;
EM_NOE <= 0;
#77.5;
EM_NCS4 <= 1;
EM_NCS6 <= 1;
//#1.5;
$display("Data Read from GPMC: %X",EM_D);
EM_NOE <= 1;
#254;
EM_A <= 10'bz;
end
endtask // GPMC_Read
initial
begin
#1000;
GPMC_Write(1,36,16'hF00D);
#1000;
GPMC_Read(1,36);
#1000;
GPMC_Write(0,36,16'h1234);
GPMC_Write(0,38,16'h5678);
GPMC_Write(0,40,16'h9abc);
GPMC_Write(0,11'h2F4,16'hF00D);
GPMC_Write(0,11'h7FE,16'hDEAD);
GPMC_Write(0,11'h7FE,16'hDEAD);
GPMC_Write(0,11'h7FE,16'hDEAD);
GPMC_Write(0,11'h7FE,16'hDEAD);
GPMC_Write(0,11'h7FE,16'hDEAD);
GPMC_Write(0,11'h7FE,16'hDEAD);
#100000;
$finish;
end
endmodule // gpmc_model
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, k, minn = 10000, a[1000], temp = 0; cin >> n >> m >> k; for (long long i = 0; i < n; i++) { cin >> a[i]; if (a[i] <= k && a[i] != 0) { temp = abs(i + 1 - m) * 10; if (temp < minn) minn = temp; } } cout << minn; return 0; }
|
#include <bits/stdc++.h> using namespace std; #define int long long struct node{ int x, y, id; bool operator <(const node& W) const{ if (W.x != x) return x < W.x; else return y < W.y; } }; void work() { int n; cin >> n; vector<node> v(n); for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; if (x > y) swap(x, y); v[i] = {x, y, i + 1}; } sort(v.begin(), v.end()); vector<int> res(n + 1); int pos = -1; for (int i = 0; i < v.size(); i++) { int j = i; while (j < v.size() && v[i].x == v[j].x) j++; j--; if (pos == -1) for (int k = i; k <= j; k++) res[v[k].id] = -1; else { for (int k = i; k <= j; k++) if (v[k].y > v[pos].y) res[v[k].id] = v[pos].id; else res[v[k].id] = -1; } if (pos == -1) pos = 0; else if (v[i].y < v[pos].y) pos = i; i = j; } for (int i = 1; i < res.size(); i++) cout << res[i] << ; cout << endl; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); int cas; cin >> cas; while (cas--) work(); return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RAM.v when simulating
// the core, RAM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RAM(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [3 : 0] dina;
output [3 : 0] douta;
input clkb;
input [0 : 0] web;
input [9 : 0] addrb;
input [3 : 0] dinb;
output [3 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("RAM.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(768),
.C_READ_DEPTH_B(768),
.C_READ_WIDTH_A(4),
.C_READ_WIDTH_B(4),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(768),
.C_WRITE_DEPTH_B(768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(4),
.C_WRITE_WIDTH_B(4),
.C_XDEVICEFAMILY("spartan3e")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 4e6 + 10; const int p = 1009; int raw[maxn], cnt[maxn]; complex<double> F1[maxn], F2[maxn]; const double PI = acos(-1.0); int rev[maxn]; void init(vector<complex<double> >& A, int n) { A.clear(); A.shrink_to_fit(); int size = 1; while (size <= n) size *= 2; A.assign(size * 2, 0); } void FFT_init(int n) { int S = log2(n); for (int i = 0; i < n; i++) rev[i] = (rev[i >> 1] >> 1) | ((i & 1) << (S - 1)); } void FFT(complex<double>* A, int siz, int type) { int n = siz; FFT_init(n); for (int i = 0; i < n; i++) if (i < rev[i]) swap(A[i], A[rev[i]]); for (int i = 1; i < n; i *= 2) { complex<double> Wn(cos(PI / i), type * sin(PI / i)); for (int j = 0; j < n; j += i * 2) { complex<double> W(1, 0); for (int k = 0; k < i; k++) { complex<double> facx = A[j + k], facy = W * A[j + k + i]; A[j + k] = facx + facy; A[j + k + i] = facx - facy; W *= Wn; } } } if (type == -1) for (int i = 0; i < n; i++) A[i].real((A[i].real() / n + 0.5)); } vector<complex<double> > mul(vector<complex<double> > A, vector<complex<double> > B) { int n = A.size(), m = B.size(); int siz = n + m - 1; vector<complex<double> > C(siz); int fsiz = 1; while (fsiz <= siz) fsiz *= 2; fsiz *= 2; for (int i = 0; i < fsiz; i++) F1[i] = F2[i] = 0; for (int i = 0; i < n; i++) F1[i] = A[i]; for (int i = 0; i < m; i++) F2[i] = B[i]; FFT(F1, fsiz, 1); FFT(F2, fsiz, 1); for (int i = 0; i < fsiz; i++) F1[i] *= F2[i]; FFT(F1, fsiz, -1); for (int i = 0; i < siz; i++) { C[i] = ((long long)F1[i].real()) % p; } return C; } vector<complex<double> > solve(int l, int r) { if (l == r) { return vector<complex<double> >(cnt[l] + 1, 1); } int m = (l + r) / 2; return mul(solve(l, m), solve(m + 1, r)); } struct Node { int w; vector<complex<double> > P; Node(int w = 0, vector<complex<double> > P = {}) : w(w), P(P) {} bool operator<(const Node& X) const { return w > X.w; } }; priority_queue<Node> pq; vector<complex<double> > ans; signed main() { ios::sync_with_stdio(0); cin.tie(0); int n, m, k; cin >> n >> m >> k; for (int i = 1; i <= n; i++) { int x; cin >> x; cnt[x]++; } vector<complex<double> > ans = solve(1, m); cout << ((int)ans[k].real() + p) % p << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 20071027; const double pi = acos(1.0 * (-1)); int p[1001111]; long long fun(long long x) { long long dt = 1 + 8 * x; long long t = sqrt(dt * 1.0) + 0.0000001; if (t * t != dt) return -1; return (1 + t) / 2; } int main() { ios::sync_with_stdio(false); cin.tie(0); long long n00, n01, n10, n11; cin >> n00 >> n01 >> n10 >> n11; long long n1, n0; n1 = fun(n11); n0 = fun(n00); if (n00 + n01 + n10 + n11 == 0) { cout << 1 ; return 0; } if (n1 == -1 || n0 == -1) { cout << Impossible ; return 0; } if (n01 + n10 == 0) { if (n0 == 1) for (int i = 0; i < n1; i++) cout << 1 ; else if (n1 == 1) for (int i = 0; i < n0; i++) cout << 0 ; else cout << Impossible ; return 0; } if (n01 + n10 != n0 * n1) { cout << Impossible ; return 0; } if (n01 > n0) { p[n0] = n01 / n0; n01 -= n0 * p[n0]; n1 -= p[n0]; } if (n1) { p[n01]++; n1--; } p[0] += n1; for (int i = 0; i < n0; i++) { for (int j = 0; j < p[i]; j++) cout << 1 ; cout << 0 ; } for (int i = 0; i < p[n0]; i++) cout << 1 ; return 0; }
|
#include <bits/stdc++.h> int d[1000]; void Qsort(int, int); bool Checked(int, int); int main(int argc, char** argv) { char a[10000]; std ::cin >> a; int id = 0; int k = 0; while (a[k] != 0 ) { int num = 0; while ((a[k] != 0 ) && (a[k] != , )) { num = (num * 10) + (a[k] - 0 ); k++; } k++; if (Checked(num, id) == true) d[id++] = num; } bool flag = false; Qsort(0, id - 1); int cnt = 0; int index = 0; for (int i = 1; i <= id; i++) { if (d[i - 1] + 1 == d[i]) { if (cnt == 0) index = i - 1; cnt++; } else { if (cnt != 0) { if (flag == true) { std ::cout << , << d[index] << - << d[index + cnt]; } else { std ::cout << d[index] << - << d[index + cnt]; flag = true; } cnt = 0; } else { if (flag == true) { std ::cout << , << d[i - 1]; } else { std ::cout << d[i - 1]; flag = true; } cnt = 0; } } } if (flag == true) { if (cnt != 0) std ::cout << , << d[index] << - << d[index + cnt]; } else { if (cnt != 0) std ::cout << d[index] << - << d[index + cnt]; } return 0; } void Qsort(int l, int r) { if (l > r) return; int i = l; int j = r; int m = d[(l + r) / 2]; while (i <= j) { while (d[i] < m) i++; while (d[j] > m) j--; if (i <= j) { int temp = d[i]; d[i] = d[j]; d[j] = temp; i++; j--; } } Qsort(l, j); Qsort(i, r); } bool Checked(int key, int n) { for (int i = 0; i < n; i++) { if (d[i] == key) return false; } return true; }
|
#include <bits/stdc++.h> using namespace std; int n; pair<long long, long long> P, d[100000]; double rm, rM; int main() { scanf( %d%I64d%I64d , &n, &P.first, &P.second); for (int i = 0; i < n; i++) { pair<long long, long long> Q; scanf( %I64d%I64d , &Q.first, &Q.second); double t = (P.first - Q.first) * (P.first - Q.first) + (P.second - Q.second) * (P.second - Q.second); if (i == 0) rm = rM = t; else { if (rm > t) rm = t; if (rM < t) rM = t; } d[i] = Q; } for (int i = 0; i < n; i++) { int j = (i + 1) % n; pair<long long, long long> Q = make_pair(d[j].first - d[i].first, d[j].second - d[i].second); double t = Q.first * (P.first - d[i].first) + Q.second * (P.second - d[i].second); t /= (Q.first * Q.first + Q.second * Q.second); if (0 <= t && t <= 1) { long long a = d[j].second - d[i].second; long long b = -(d[j].first - d[i].first); long long c = -(a * d[i].first + b * d[i].second); double t = (a * P.first + b * P.second + c); t = t * t / (a * a + b * b); if (t < rm) rm = t; } } double r = rM - rm; printf( %.9f n , r * 3.1415926535897932384626433832795); return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_ll(clock, enable, resetn, dataa, datab, result);
// This is a version of the adder with reduced latency.
input clock, enable, resetn;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
// Total Latency = 8.
acl_fp_custom_add_core core(
.clock(clock),
.resetn(resetn),
.dataa(dataa),
.datab(datab),
.result(result),
.valid_in(),
.valid_out(),
.stall_in(),
.stall_out(),
.enable(enable));
defparam core.HIGH_LATENCY = 0;
defparam core.HIGH_CAPACITY = 0;
defparam core.FLUSH_DENORMS = 0;
defparam core.ROUNDING_MODE = 0;
defparam core.FINITE_MATH_ONLY = 0;
defparam core.REMOVE_STICKY = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int n = 2; struct Matrix { long long matrix[5][5]; }; Matrix unit; int m; long long cnt[1000005], MOD; void initUnit() { memset(unit.matrix, 0, sizeof(unit.matrix)); int i; for (i = 1; i <= n; i++) unit.matrix[i][i] = 1; } Matrix matrixMulti(Matrix x, Matrix y) { Matrix ret; int i, j, k; for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { ret.matrix[i][j] = 0; for (k = 1; k <= n; k++) { ret.matrix[i][j] = (ret.matrix[i][j] + x.matrix[i][k] * y.matrix[k][j] % MOD) % MOD; } ret.matrix[i][j] = (ret.matrix[i][j] % MOD + MOD) % MOD; } } return ret; } Matrix matrixPow(Matrix x, long long k) { Matrix ret = unit; while (k) { if (k & 1) ret = matrixMulti(ret, x); x = matrixMulti(x, x); k >>= 1; } return ret; } long long mpow(long long a, long long p) { long long ret = 1; while (p) { if (p & 1) ret = (ret * a) % MOD; a = (a * a) % MOD; p = p >> 1; } return ret; } long long solve(long long minv, long long maxv, long long sum, long long k) { long long pw = mpow(3, k); long long ret = (2 * pw * sum % MOD - (pw - 1) * (minv + maxv) % MOD) % MOD; ret = (ret / 2) % MOD; return (ret % MOD + MOD) % MOD; } int main() { long long x, y, sum, minv, maxv; int i, j, k; initUnit(); while (scanf( %d%I64d%I64d%I64d , &m, &x, &y, &MOD) != EOF) { for (i = 1, sum = 0; i <= m; i++) { scanf( %I64d , &cnt[i]); sum += cnt[i]; } minv = cnt[1], maxv = cnt[m]; if (m == 1) { printf( %I64d n , sum % MOD); } else { MOD *= 2; sum = solve(minv % MOD, maxv % MOD, sum % MOD, x); Matrix mt; mt.matrix[1][1] = 0, mt.matrix[1][2] = mt.matrix[2][1] = mt.matrix[2][2] = 1; mt = matrixPow(mt, x); maxv = (mt.matrix[2][1] * cnt[m - 1] % MOD + mt.matrix[2][2] * cnt[m] % MOD) % MOD; sum = solve(minv % MOD, maxv % MOD, sum % MOD, y); MOD /= 2; printf( %I64d n , sum % MOD); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; ll cnt_inv[30][2]; void rec(vector<int>& a, int b) { if (b < 0 || a.empty()) return; vector<int> s, us; for (int& i : a) { int val = i & (1 << b); if (val) cnt_inv[b][1] += us.size(), s.push_back(i); else cnt_inv[b][0] += s.size(), us.push_back(i); } rec(s, b - 1); rec(us, b - 1); } void solve() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < int(n); i++) cin >> a[i]; memset(cnt_inv, 0, sizeof cnt_inv); rec(a, 29); ll inv = 0, x = 0; for (int b = 29; b >= 0; b--) { inv += min(cnt_inv[b][0], cnt_inv[b][1]); int val = 1; if (cnt_inv[b][0] <= cnt_inv[b][1]) val = 0; x += (val << b); } cout << inv << << x << n ; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); solve(); }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 2000000000000000000LL; const int inf = 0x3f3f3f3f; const long double EPS = 1e-9; string a, b; inline void solve() { vector<long long> mapa(26); for (long long i = 0; i < a.size(); i++) { mapa[a[i] - a ]++; } for (int i = 0; i < b.size(); i++) { vector<long long> mapb(26); for (long long j = i; j < b.size(); j++) { mapb[b[j] - a ]++; if (mapa == mapb) { printf( YES n ); return; } } } printf( NO n ); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int test, tc = 0; cin >> test; while (test--) { cin >> a >> b; solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout << fixed; int a1, a2; cin >> a1 >> a2; int minutes = 0; while (a1 > 0 && a2 > 0) { if (a1 == 1 && a2 == 1) { break; } if (a1 <= 2) { a1 += 1; a2 -= 2; } else if (a2 <= 2) { a2 += 1; a1 -= 2; } else { a1 += 1; a2 -= 2; } minutes++; } cout << minutes; return 0; }
|
// Quartus Prime Verilog Template
// Single port RAM with single read/write address and initial contents
// specified with an initial block
module phyIniCommand0
#(parameter DATA_WIDTH=32, parameter ADDR_WIDTH=4)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we, clk,
output [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// Variable to hold the registered read address
reg [ADDR_WIDTH-1:0] addr_reg;
// Specify the initial contents. You can also use the $readmemb
// system task to initialize the RAM variable from a text file.
// See the $readmemb template page for details.
initial
begin : INIT
$readmemb("C:/altera/16.0/myProjects/PHYctrl_100Mbps_Slave/ram_init0.txt", ram);
end
always @ (posedge clk)
begin
// Write
if (we)
ram[addr] <= data;
addr_reg <= addr;
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ram[addr_reg];
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> class graph { public: struct edge { int from; int to; T cost; }; vector<edge> edges; vector<vector<int>> g; int n; graph(int _n) : n(_n) { g.resize(n); } virtual int add(int from, int to, T cost) = 0; }; template <typename T> class undigraph : public graph<T> { public: using graph<T>::edges; using graph<T>::g; using graph<T>::n; undigraph(int _n) : graph<T>(_n) {} int add(int from, int to, T cost = 1) { assert(0 <= from && from < n && 0 <= to && to < n); int id = (int)edges.size(); g[from].push_back(id); g[to].push_back(id); edges.push_back({from, to, cost}); return id; } }; template <typename T> vector<vector<int>> find_cycles(const graph<T> &g, int bound_cnt = 1 << 30, int bound_size = 1 << 30) { vector<int> was(g.n, -1); vector<int> st; vector<vector<int>> cycles; int total_size = 0; function<void(int, int)> dfs = [&](int v, int pe) { if ((int)cycles.size() >= bound_cnt || total_size >= bound_size) { return; } was[v] = (int)st.size(); for (int id : g.g[v]) { if (id == pe) { continue; } auto &e = g.edges[id]; int to = e.from ^ e.to ^ v; if (was[to] >= 0) { vector<int> cycle(1, id); for (int j = was[to]; j < (int)st.size(); j++) { cycle.push_back(st[j]); } cycles.push_back(cycle); total_size += (int)cycle.size(); if ((int)cycles.size() >= bound_cnt || total_size >= bound_size) { return; } continue; } if (was[to] == -1) { st.push_back(id); dfs(to, id); st.pop_back(); } } was[v] = -2; }; for (int i = 0; i < g.n; i++) { if (was[i] == -1) { dfs(i, -1); } } return cycles; } template <typename T> vector<int> edges_to_vertices(const graph<T> &g, const vector<int> &edge_cycle) { int sz = (int)edge_cycle.size(); vector<int> vertex_cycle; if (sz <= 2) { vertex_cycle.push_back(g.edges[edge_cycle[0]].from); if (sz == 2) { vertex_cycle.push_back(g.edges[edge_cycle[0]].to); } } else { for (int i = 0; i < sz; i++) { int j = (i + 1) % sz; auto &e = g.edges[edge_cycle[i]]; auto &other = g.edges[edge_cycle[j]]; if (other.from == e.from || other.to == e.from) { vertex_cycle.push_back(e.to); } else { vertex_cycle.push_back(e.from); } } } return vertex_cycle; } int main() { ios::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; undigraph<int> g(n); for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; --x; --y; g.add(x, y); } vector<vector<int>> cycles = find_cycles(g); vector<vector<int>> events(m); for (auto &cycle : cycles) { int sz = (int)cycle.size(); int pos = (int)(min_element(cycle.begin(), cycle.end()) - cycle.begin()); rotate(cycle.begin(), cycle.begin() + pos, cycle.end()); pos = (int)(max_element(cycle.begin(), cycle.end()) - cycle.begin()); bool ok = true; for (int i = 0; i < pos - 1; i++) { if (cycle[i] > cycle[i + 1]) { ok = false; break; } } for (int i = pos; i < sz - 1; i++) { if (cycle[i] < cycle[i + 1]) { ok = false; break; } } if (ok) { events[cycle[pos]].push_back(cycle[0]); } } vector<int> sub(m, 0); vector<int> ans(n, 1); for (int i = m - 1; i >= 0; i--) { auto &e = g.edges[i]; int x = e.from; int y = e.to; int cur = ans[x] + ans[y] - sub[i]; ans[x] = ans[y] = cur; for (int j : events[i]) { sub[j] += cur; } } for (int i = 0; i < n; i++) { if (i > 0) { cout << ; } cout << ans[i] - 1; } cout << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 31.03.2016 12:23:12
// Design Name:
// Module Name: sample_generator_testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sample_generator_testbench();
reg AXI_En;
reg En;
reg [7:0] FrameSize;
wire [31:0] M_AXIS_tdata;
wire M_AXIS_tlast;
reg M_AXIS_tready;
wire [3:0] M_AXIS_tstrb;
wire M_AXIS_tvalid;
reg [31:0] S_AXIS_tdata;
reg S_AXIS_tlast;
wire S_AXIS_tready;
reg [3:0] S_AXIS_tstrb;
reg S_AXIS_tvalid;
reg Clk;
reg ResetN;
initial begin
AXI_En=0;
FrameSize=16;
S_AXIS_tdata=0;
S_AXIS_tlast=0;
S_AXIS_tstrb=0;
S_AXIS_tvalid=0;
end
initial begin
Clk = 0;
forever #5 Clk= ~Clk;
end
initial begin
ResetN=0;
#100 ResetN = 1;
end
initial begin
En = 1;
#1000 En = 0;
#100 En = 1;
end
initial begin
M_AXIS_tready = 0;
#200 M_AXIS_tready=1;
#2000 M_AXIS_tready=0;
#200 M_AXIS_tready = 1;
end
design_1_wrapper dut
(.AXI_En(AXI_En),
.En(En),
.FrameSize(FrameSize),
.M_AXIS_tdata(M_AXIS_tdata),
.M_AXIS_tlast(M_AXIS_tlast),
.M_AXIS_tready(M_AXIS_tready),
.M_AXIS_tstrb(M_AXIS_tstrb),
.M_AXIS_tvalid(M_AXIS_tvalid),
.S_AXIS_tdata(S_AXIS_tdata),
.S_AXIS_tlast(S_AXIS_tlast),
.S_AXIS_tready(S_AXIS_tready),
.S_AXIS_tstrb(S_AXIS_tstrb),
.S_AXIS_tvalid(S_AXIS_tvalid),
.m_axis_aclk(Clk),
.m_axis_aresetn(ResetN));
endmodule
|
#include <bits/stdc++.h> int main() { int n, t, i; scanf( %d%d , &n, &t); if (n == 1 && t == 10) printf( -1 ); else { if (t == 10) { printf( 1 ); for (i = 0; i < n - 1; i++) printf( 0 ); } else for (i = 0; i < n; i++) printf( %d , t); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int cost; double amount; cin >> cost; string s[n]; for (int i = 0; i < n; i++) { cin >> s[i]; } int counter = 0; double sum = 0.0; for (int i = n - 1; i >= 0; i--) { if (s[i] == halfplus ) { counter++; sum = (sum + 0.5) * 2; } else if (s[i] == half ) { sum = sum * 2; } } double num; num = sum - (0.5 * counter); amount = cost * num; cout << (long long int)amount << endl; }
|
#include <bits/stdc++.h> using namespace std; struct Edge { int64_t v, f, c; Edge(int64_t v, int64_t f, int64_t c) : v(v), f(f), c(c) {} int64_t get_capacity() { return c - f; } }; const int64_t INF = (int64_t)(1e9) + 666; const int64_t N = 10000; const int64_t S = N - 2; const int64_t T = N - 1; vector<Edge> edges; vector<int64_t> g[N]; int64_t dist[N]; int64_t ptr[N]; void add_edge(int64_t v, int64_t u, int64_t c) { g[v].emplace_back(edges.size()); edges.emplace_back(u, 0, c); g[u].emplace_back(edges.size()); edges.emplace_back(v, 0, 0); } bool bfs() { fill(dist, dist + N, INF); dist[S] = 0; queue<int64_t> q; q.push(S); while (!q.empty()) { int64_t v = q.front(); q.pop(); for (int64_t id : g[v]) { if (edges[id].get_capacity() < 1) { continue; } if (dist[edges[id].v] > dist[v] + 1) { dist[edges[id].v] = dist[v] + 1; q.push(edges[id].v); } } } return dist[T] != INF; } int64_t dfs(int64_t v, int64_t min_c) { if (v == T) { return min_c; } while (ptr[v] < g[v].size()) { int64_t id = g[v][ptr[v]]; ++ptr[v]; if (edges[id].get_capacity() < 1) { continue; } if (dist[edges[id].v] != dist[v] + 1) { continue; } int64_t x = dfs(edges[id].v, min(min_c, edges[id].get_capacity())); if (x) { --ptr[v]; edges[id].f += x; edges[id ^ 1].f -= x; return x; } } return 0; } int main() { int64_t n, h, m; cin >> n >> h >> m; int64_t sum = 0; for (int64_t i = 0; i < n; ++i) { for (int64_t j = 0; j < h; ++j) { sum += 2 * (j + 1) - 1; add_edge(S, i * h + j, 2 * (j + 1) - 1); } } for (int64_t q = 0; q < m; ++q) { int64_t left, right, x, c; cin >> left >> right >> x >> c; add_edge(q + N / 2, T, c); for (int64_t i = left - 1; i < right; ++i) { for (int64_t j = x; j < h; ++j) { add_edge(i * h + j, q + N / 2, INF); } } } while (bfs()) { fill(ptr, ptr + N, 0); while (dfs(S, INF)) { } } for (int64_t id : g[S]) { sum -= edges[id].f; } cout << sum << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_BLACKBOX_V
`define SKY130_FD_SC_LP__INVLP_BLACKBOX_V
/**
* invlp: Low Power Inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__invlp (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long a, b, n, ret; long long retr(long long x) { long long t = 0; while (x > 0) { t = 10 * t + (x % 10); x /= 10; } return t; } int main() { int i; cin >> a >> b; ret = retr(b); ret += a; cout << ret; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using uint = unsigned int; template <class T> using V = vector<T>; template <class T> using VV = vector<vector<T>>; template <class T, class U> void chmax(T& x, U y) { if (x < y) x = y; } template <class T, class U> void chmin(T& x, U y) { if (y < x) x = y; } template <class T> void mkuni(V<T>& v) { sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); } template <class S, class T> ostream& operator<<(ostream& o, const pair<S, T>& p) { return o << ( << p.first << , << p.second << ) ; } template <class T> ostream& operator<<(ostream& o, const vector<T>& vc) { o << { ; for (const T& v : vc) o << v << , ; o << } ; return o; } constexpr ll TEN(int n) { return (n == 0) ? 1 : 10 * TEN(n - 1); } template <unsigned int mod_> struct ModInt { using uint = unsigned int; using ll = long long; using ull = unsigned long long; constexpr static uint mod = mod_; uint v; ModInt() : v(0) {} ModInt(ll _v) : v(normS(_v % mod + mod)) {} explicit operator bool() const { return v != 0; } static uint normS(const uint& x) { return (x < mod) ? x : x - mod; } static ModInt make(const uint& x) { ModInt m; m.v = x; return m; } ModInt operator+(const ModInt& b) const { return make(normS(v + b.v)); } ModInt operator-(const ModInt& b) const { return make(normS(v + mod - b.v)); } ModInt operator-() const { return make(normS(mod - v)); } ModInt operator*(const ModInt& b) const { return make((ull)v * b.v % mod); } ModInt operator/(const ModInt& b) const { return *this * b.inv(); } ModInt& operator+=(const ModInt& b) { return *this = *this + b; } ModInt& operator-=(const ModInt& b) { return *this = *this - b; } ModInt& operator*=(const ModInt& b) { return *this = *this * b; } ModInt& operator/=(const ModInt& b) { return *this = *this / b; } ModInt& operator++(int) { return *this = *this + 1; } ModInt& operator--(int) { return *this = *this - 1; } ll extgcd(ll a, ll b, ll& x, ll& y) const { ll p[] = {a, 1, 0}, q[] = {b, 0, 1}; while (*q) { ll t = *p / *q; for (int i = 0; i < int(3); i++) swap(p[i] -= t * q[i], q[i]); } if (p[0] < 0) for (int i = 0; i < int(3); i++) p[i] = -p[i]; x = p[1], y = p[2]; return p[0]; } ModInt inv() const { ll x, y; extgcd(v, mod, x, y); return make(normS(x + mod)); } ModInt pow(ll p) const { if (p < 0) return inv().pow(-p); ModInt a = 1; ModInt x = *this; while (p) { if (p & 1) a *= x; x *= x; p >>= 1; } return a; } bool operator==(const ModInt& b) const { return v == b.v; } bool operator!=(const ModInt& b) const { return v != b.v; } friend istream& operator>>(istream& o, ModInt& x) { ll tmp; o >> tmp; x = ModInt(tmp); return o; } friend ostream& operator<<(ostream& o, const ModInt& x) { return o << x.v; } }; using mint = ModInt<998244353>; V<mint> fact, ifact; mint Choose(int a, int b) { if (b < 0 || a < b) return 0; return fact[a] * ifact[b] * ifact[a - b]; } void InitFact(int N) { fact.resize(N); ifact.resize(N); fact[0] = 1; for (int i = 1; i <= int(N - 1); i++) fact[i] = fact[i - 1] * i; ifact[N - 1] = fact[N - 1].inv(); for (int i = N - 2; i >= 0; i--) ifact[i] = ifact[i + 1] * (i + 1); } void test() { int N, M; cin >> N >> M; V<mint> f(N + 1); for (int x = int(N) - 1; x >= 0; x--) { void(0); mint sum_pi = 0; V<mint> p(N - x + 1), q(N - x + 1); for (int i = 0; i < int(N - x + 1); i++) { mint pi = 0; mint qi = 0; for (int j = 0; j < int(x + 1); j++) { mint pij = ifact[N + M] * fact[N + M - (i + j) - 1] * M * fact[i + j] * Choose(N - x, i) * Choose(x, j); pi += pij; qi += pij * (i + j + 1); } p[i] = pi, q[i] = qi; void(0); void(0); void(0); sum_pi += pi; } { mint sum = 0; for (int i = 0; i < int(N - x + 1); i++) { sum += q[i]; if (i) sum += p[i] * f[x + i]; } f[x] = sum / (mint(1) - p[0]); } assert(sum_pi == 1); } V<mint> df(N); for (int i = 0; i < int(N); i++) df[i] = f[i] - f[i + 1]; reverse(df.begin(), df.end()); for (int i = int(N) - 1; i >= 0; i--) df[i] /= df[0]; cout << df << endl; } int main() { cin.tie(0); ios::sync_with_stdio(false); cout << fixed << setprecision(20); InitFact(3000000); int N, M; cin >> N >> M; mint ans = 0; for (int i = 0; i < int(N); i++) { if (i == 0) ans += mint(M).inv(); else ans += (mint(M + 1) * (i + 1)).inv(); } ans *= M; ans *= N + M + 1; cout << ans << endl; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.