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/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* FSM: finite state machine
* halt if $ctrl == 0$
*/
module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe, done);
input clk;
input reset;
output reg [8:0] rom_addr; /* command id. extra bits? */
input [25:0] rom_q; /* command value */
output reg [5:0] ram_a_addr;
output reg [5:0] ram_b_addr;
output ram_b_w;
output reg [10:0] pe;
output reg done;
reg [5:0] state;
parameter START=0, READ_SRC1=1, READ_SRC2=2, CALC=4, WAIT=8, WRITE=16, DON=32;
wire [5:0] dest, src1, src2, times; wire [1:0] op;
assign {dest, src1, op, times, src2} = rom_q;
reg [5:0] count;
always @ (posedge clk)
if (reset)
state<=START;
else
case (state)
START:
state<=READ_SRC1;
READ_SRC1:
state<=READ_SRC2;
READ_SRC2:
if (times==0) state<=DON; else state<=CALC;
CALC:
if (count==1) state<=WAIT;
WAIT:
state<=WRITE;
WRITE:
state<=READ_SRC1;
endcase
/* we support two loops with 48 loop times */
parameter LOOP1_START = 9'd22,
LOOP1_END = 9'd117,
LOOP2_START = 9'd280,
LOOP2_END = 9'd293;
reg [46:0] loop1, loop2;
always @ (posedge clk)
if (reset) rom_addr<=0;
else if (state==WAIT)
begin
if(rom_addr == LOOP1_END && loop1[0])
rom_addr <= LOOP1_START;
else if(rom_addr == LOOP2_END && loop2[0])
rom_addr <= LOOP2_START;
else
rom_addr <= rom_addr + 1;
end
always @ (posedge clk)
if (reset) loop1 <= ~0;
else if(state==WAIT && rom_addr==LOOP1_END)
loop1 <= loop1 >> 1;
always @ (posedge clk)
if (reset) loop2 <= ~0;
else if(state==WAIT && rom_addr==LOOP2_END)
loop2 <= loop2 >> 1;
always @ (posedge clk)
if (reset)
count<=0;
else if (state==READ_SRC1)
count<=times;
else if (state==CALC)
count<=count-1;
always @ (posedge clk)
if (reset) done<=0;
else if (state==DON) done<=1;
else done<=0;
always @ (state, src1, src2)
case (state)
READ_SRC1: ram_a_addr=src1;
READ_SRC2: ram_a_addr=src2;
default: ram_a_addr=0;
endcase
parameter CMD_ADD=6'd4, CMD_SUB=6'd8, CMD_CUBIC=6'd16,
ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
always @ (posedge clk)
case (state)
READ_SRC1:
case (op)
ADD: pe<=11'b11001000000;
SUB: pe<=11'b11001000000;
CUBIC: pe<=11'b11111000000;
MULT: pe<=11'b11110000000;
default: pe<=0;
endcase
READ_SRC2:
case (op)
ADD: pe<=11'b00110000000;
SUB: pe<=11'b00110000000;
CUBIC: pe<=0;
MULT: pe<=11'b00001000000;
default: pe<=0;
endcase
CALC:
case (op)
ADD: pe<=11'b00000010001;
SUB: pe<=11'b00000010001;
CUBIC: pe<=11'b01010000001;
MULT: pe<=11'b00000111111;
default: pe<=0;
endcase
default:
pe<=0;
endcase
always @ (state, op, src2, dest)
case (state)
READ_SRC1:
case (op)
ADD: ram_b_addr=CMD_ADD;
SUB: ram_b_addr=CMD_SUB;
CUBIC: ram_b_addr=CMD_CUBIC;
default: ram_b_addr=0;
endcase
READ_SRC2: ram_b_addr=src2;
WRITE: ram_b_addr=dest;
default: ram_b_addr=0;
endcase
assign ram_b_w = (state==WRITE) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long read() { long long k = 1, x = 0; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) k = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + (c - 48); c = getchar(); } return x * k; } long long n, m, f[2001][2001], s[2001][2001], res[300000], p = 998244353; long long a[1000604], k, ans, now; int main() { n = read(); k = read(); for (int i = 1; i <= n; i++) { a[i] = read(); } ans = 0; sort(a + 1, a + 1 + n); for (int v = 1; v * (k - 1) <= a[n]; v++) { now = 0; f[0][0] = 1; for (int i = 1; i <= n; i++) { while (a[i] - a[now + 1] >= v) now++; f[i][0] = f[i - 1][0]; for (int j = 1; j <= k; j++) { f[i][j] = (f[i - 1][j] + f[now][j - 1]) % p; } } ans = (ans + f[n][k]) % p; } printf( %lld n , ans % p); }
|
#include <bits/stdc++.h> using namespace std; int a[2000], b[2000]; int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i] >> b[i]; } int k = 0; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; j++) { if (j != i) { if (a[i] == b[j]) { k++; break; } } } } cout << n - k; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_4_V
`define SKY130_FD_SC_LS__OR4B_4_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_4 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_4 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_SYMBOL_V
`define SKY130_FD_SC_HDLL__A21BOI_SYMBOL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21boi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string n, r; cin >> n; r = n; reverse(r.begin(), r.end()); cout << n << r << n ; return 0; }
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 13.1
// \ \ Application : xaw2verilog
// / / Filename : main_pll.v
// /___/ /\ Timestamp : 06/03/2011 01:58:13
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st /home/teknohog/dcm2/ipcore_dir/./main_pll.xaw /home/teknohog/dcm2/ipcore_dir/./main_pll
//Design Name: main_pll
//Device: xc3s500e-4fg320
//
// Module main_pll
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module main_pll(CLKIN_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT,
CLK2X_OUT,
LOCKED_OUT);
input CLKIN_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output CLK2X_OUT;
output LOCKED_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLK2X_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLK2X_BUFG_INST (.I(CLK2X_BUF),
.O(CLK2X_OUT));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(CLK2X_BUF),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 100, inF = 1e6 + 10; int n, k, u, v, c, maxi, a[N], sz[N]; bool ok; vector<int> nei[N]; int get_sz(int v, int par = -1) { for (int u : nei[v]) if (u != par) sz[v] += get_sz(u, v); return ++sz[v]; } int dfs(int v, int par = -1) { int dp = (a[v] < c ? -inF : 1); int mx1 = 0, mx2 = 0; for (int u : nei[v]) if (u != par) { int DP = dfs(u, v); if (DP == sz[u]) dp += DP; else { mx2 = max(mx2, DP); if (mx2 > mx1) swap(mx1, mx2); } } ok |= (dp + mx1 + mx2) >= k; if (a[v] < c) return 0; return dp + mx1; } bool check() { ok = false; dfs(min_element(a, a + n) - a); return ok; } int main() { ios::sync_with_stdio(false), cin.tie(0); cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n - 1; i++) { cin >> u >> v; nei[--u].push_back(--v); nei[v].push_back(u); } get_sz(min_element(a, a + n) - a); int l = 0, r = inF; while (r - l > 1) { c = (l + r) >> 1; if (check()) l = c; else r = c; } cout << l; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_2_V
`define SKY130_FD_SC_MS__O31AI_2_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31ai_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_2_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fifo_address_gray #(
parameter ADDRESS_WIDTH = 4
) (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output reg [ADDRESS_WIDTH:0] m_axis_level,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
output reg [ADDRESS_WIDTH:0] s_axis_room
);
reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;
reg [ADDRESS_WIDTH:0] s_axis_waddr_gray = 'h00;
wire [ADDRESS_WIDTH:0] s_axis_waddr_gray_next;
wire [ADDRESS_WIDTH:0] s_axis_raddr_gray;
reg [ADDRESS_WIDTH:0] m_axis_raddr_gray = 'h00;
wire [ADDRESS_WIDTH:0] m_axis_raddr_gray_next;
wire [ADDRESS_WIDTH:0] m_axis_waddr_gray;
assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[ADDRESS_WIDTH:1];
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
s_axis_waddr_gray <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
s_axis_waddr_gray <= s_axis_waddr_gray_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[ADDRESS_WIDTH:1];
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
m_axis_raddr_gray <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
m_axis_raddr_gray <= m_axis_raddr_gray_next;
end
end
sync_bits #(
.NUM_OF_BITS(ADDRESS_WIDTH + 1)
) i_waddr_sync (
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in(s_axis_waddr_gray),
.out(m_axis_waddr_gray)
);
sync_bits #(
.NUM_OF_BITS(ADDRESS_WIDTH + 1)
) i_raddr_sync (
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in(m_axis_raddr_gray),
.out(s_axis_raddr_gray)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
end else begin
s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] ||
s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] ||
s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]);
s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next;
end
end
always @(posedge m_axis_aclk)
begin
if (s_axis_aresetn == 1'b0)
m_axis_valid <= 1'b0;
else begin
m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next;
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:36777216 ) template <class T> inline void RD(T &); template <class T> inline void OT(const T &); template <class T> inline T &_RD(T &x) { RD(x); return x; } inline int RD() { int x; return _RD(x); } inline void RF(double &x) { scanf( %lf , &x); } inline double _RF(double &x) { scanf( %lf , &x); return x; } inline double RF() { double x; return _RF(x); } inline void RC(char &c) { scanf( %c , &c); } inline char _RC(char &c) { scanf( %c , &c); return c; } inline char RC() { char c; return _RC(c); } inline void RS(char *s) { scanf( %s , s); } template <class T0, class T1> inline void RD(T0 &x0, T1 &x1) { RD(x0), RD(x1); } template <class T0, class T1, class T2> inline void RD(T0 &x0, T1 &x1, T2 &x2) { RD(x0), RD(x1), RD(x2); } template <class T0, class T1, class T2, class T3> inline void RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3) { RD(x0), RD(x1), RD(x2), RD(x3); } template <class T0, class T1, class T2, class T3, class T4> inline void RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4) { RD(x0), RD(x1), RD(x2), RD(x3), RD(x4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4, T5 &x5) { RD(x0), RD(x1), RD(x2), RD(x3), RD(x4), RD(x5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4, T5 &x5, T6 &x6) { RD(x0), RD(x1), RD(x2), RD(x3), RD(x4), RD(x5), RD(x6); } template <class T0, class T1> inline void OT(T0 &x0, T1 &x1) { OT(x0), OT(x1); } template <class T0, class T1, class T2> inline void OT(T0 &x0, T1 &x1, T2 &x2) { OT(x0), OT(x1), OT(x2); } template <class T0, class T1, class T2, class T3> inline void OT(T0 &x0, T1 &x1, T2 &x2, T3 &x3) { OT(x0), OT(x1), OT(x2), OT(x3); } template <class T0, class T1, class T2, class T3, class T4> inline void OT(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4) { OT(x0), OT(x1), OT(x2), OT(x3), OT(x4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void OT(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4, T5 &x5) { OT(x0), OT(x1), OT(x2), OT(x3), OT(x4), OT(x5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void OT(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4, T5 &x5, T6 &x6) { OT(x0), OT(x1), OT(x2), OT(x3), OT(x4), OT(x5), OT(x6); } template <class T> inline void RST(T &A) { memset(A, 0, sizeof(A)); } template <class T0, class T1> inline void RST(T0 &A0, T1 &A1) { RST(A0), RST(A1); } template <class T0, class T1, class T2> inline void RST(T0 &A0, T1 &A1, T2 &A2) { RST(A0), RST(A1), RST(A2); } template <class T0, class T1, class T2, class T3> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3) { RST(A0), RST(A1), RST(A2), RST(A3); } template <class T0, class T1, class T2, class T3, class T4> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4) { RST(A0), RST(A1), RST(A2), RST(A3), RST(A4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5) { RST(A0), RST(A1), RST(A2), RST(A3), RST(A4), RST(A5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5, T6 &A6) { RST(A0), RST(A1), RST(A2), RST(A3), RST(A4), RST(A5), RST(A6); } template <class T> inline void CLR(priority_queue<T, vector<T>, less<T> > &Q) { while (!Q.empty()) Q.pop(); } template <class T> inline void CLR(priority_queue<T, vector<T>, greater<T> > &Q) { while (!Q.empty()) Q.pop(); } template <class T> inline void CLR(T &A) { A.clear(); } template <class T0, class T1> inline void CLR(T0 &A0, T1 &A1) { CLR(A0), CLR(A1); } template <class T0, class T1, class T2> inline void CLR(T0 &A0, T1 &A1, T2 &A2) { CLR(A0), CLR(A1), CLR(A2); } template <class T0, class T1, class T2, class T3> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3) { CLR(A0), CLR(A1), CLR(A2), CLR(A3); } template <class T0, class T1, class T2, class T3, class T4> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4) { CLR(A0), CLR(A1), CLR(A2), CLR(A3), CLR(A4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5) { CLR(A0), CLR(A1), CLR(A2), CLR(A3), CLR(A4), CLR(A5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5, T6 &A6) { CLR(A0), CLR(A1), CLR(A2), CLR(A3), CLR(A4), CLR(A5), CLR(A6); } template <class T> inline void CLR(T &A, int n) { for (int i = 0; i < int(n); ++i) CLR(A[i]); } template <class T> inline void FLC(T &A, int x) { memset(A, x, sizeof(A)); } template <class T0, class T1> inline void FLC(T0 &A0, T1 &A1, int x) { FLC(A0, x), FLC(A1, x); } template <class T0, class T1, class T2> inline void FLC(T0 &A0, T1 &A1, T2 &A2) { FLC(A0), FLC(A1), FLC(A2); } template <class T0, class T1, class T2, class T3> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3) { FLC(A0), FLC(A1), FLC(A2), FLC(A3); } template <class T0, class T1, class T2, class T3, class T4> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4) { FLC(A0), FLC(A1), FLC(A2), FLC(A3), FLC(A4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5) { FLC(A0), FLC(A1), FLC(A2), FLC(A3), FLC(A4), FLC(A5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5, T6 &A6) { FLC(A0), FLC(A1), FLC(A2), FLC(A3), FLC(A4), FLC(A5), FLC(A6); } template <class T> inline void SRT(T &A) { sort(A.begin(), A.end()); } template <class T, class C> inline void SRT(T &A, C B) { sort(A.begin(), A.end(), B); } const int MOD = 1000000007; const int INF = 0x3f3f3f3f; const long long INF_64 = 0x3f3f3f3f3f3f3f3fLL; const double EPS = 1e-8; const double OO = 1e15; const double PI = acos(-1.0); template <class T> inline void checkMin(T &a, const T b) { if (b < a) a = b; } template <class T> inline void checkMax(T &a, const T b) { if (b > a) a = b; } template <class T, class C> inline void checkMin(T &a, const T b, C c) { if (c(b, a)) a = b; } template <class T, class C> inline void checkMax(T &a, const T b, C c) { if (c(a, b)) a = b; } template <class T> inline T min(T a, T b, T c) { return min(min(a, b), c); } template <class T> inline T max(T a, T b, T c) { return max(max(a, b), c); } template <class T> inline T min(T a, T b, T c, T d) { return min(min(a, b), min(c, d)); } template <class T> inline T max(T a, T b, T c, T d) { return max(min(a, b), max(c, d)); } template <class T, class C> inline T min_cp(T a, T b, C cp) { return min(a, b, cp); } template <class T, class C> inline T min_cp(T a, T b, T c, C cp) { return min_cp(min_cp(a, b, cp), c, cp); } template <class T, class C> inline T min_cp(T a, T b, T c, T d, C cp) { return min_cp(min_cp(a, b, cp), min_cp(c, d, cp), cp); } template <class T, class C> inline T max_cp(T a, T b, C cp) { return max(a, b, cp); } template <class T, class C> inline T max_cp(T a, T b, T c, C cp) { return max_cp(max_cp(a, b, cp), c, cp); } template <class T, class C> inline T max_cp(T a, T b, T c, T d, C cp) { return max_cp(max_cp(a, b, cp), max_cp(c, d, cp), cp); } template <class T> inline T sqr(T a) { return a * a; } template <class T> inline T cub(T a) { return a * a * a; } int Ceil(int x, int y) { return (x - 1) / y + 1; } inline bool _1(int x, int i) { return x & 1 << i; } inline bool _1(long long x, int i) { return x & 1LL << i; } inline long long _1(int i) { return 1LL << i; } inline long long _U(int i) { return _1(i) - 1; }; template <class T> inline T low_bit(T x) { return x & -x; } template <class T> inline T high_bit(T x) { T p = low_bit(x); while (p != x) x -= p, p = low_bit(x); return p; } template <class T> inline T cover_bit(T x) { T p = 1; while (p < x) p <<= 1; return p; } inline int count_bits(int x) { x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); x = (x & 0x0f0f0f0f) + ((x & 0xf0f0f0f0) >> 4); x = (x & 0x00ff00ff) + ((x & 0xff00ff00) >> 8); x = (x & 0x0000ffff) + ((x & 0xffff0000) >> 16); return x; } inline int count_bits(long long x) { x = (x & 0x5555555555555555LL) + ((x & 0xaaaaaaaaaaaaaaaaLL) >> 1); x = (x & 0x3333333333333333LL) + ((x & 0xccccccccccccccccLL) >> 2); x = (x & 0x0f0f0f0f0f0f0f0fLL) + ((x & 0xf0f0f0f0f0f0f0f0LL) >> 4); x = (x & 0x00ff00ff00ff00ffLL) + ((x & 0xff00ff00ff00ff00LL) >> 8); x = (x & 0x0000ffff0000ffffLL) + ((x & 0xffff0000ffff0000LL) >> 16); x = (x & 0x00000000ffffffffLL) + ((x & 0xffffffff00000000LL) >> 32); return x; } int reverse_bits(int x) { x = ((x >> 1) & 0x55555555) | ((x << 1) & 0xaaaaaaaa); x = ((x >> 2) & 0x33333333) | ((x << 2) & 0xcccccccc); x = ((x >> 4) & 0x0f0f0f0f) | ((x << 4) & 0xf0f0f0f0); x = ((x >> 8) & 0x00ff00ff) | ((x << 8) & 0xff00ff00); x = ((x >> 16) & 0x0000ffff) | ((x << 16) & 0xffff0000); return x; } long long reverse_bits(long long x) { x = ((x >> 1) & 0x5555555555555555LL) | ((x << 1) & 0xaaaaaaaaaaaaaaaaLL); x = ((x >> 2) & 0x3333333333333333LL) | ((x << 2) & 0xccccccccccccccccLL); x = ((x >> 4) & 0x0f0f0f0f0f0f0f0fLL) | ((x << 4) & 0xf0f0f0f0f0f0f0f0LL); x = ((x >> 8) & 0x00ff00ff00ff00ffLL) | ((x << 8) & 0xff00ff00ff00ff00LL); x = ((x >> 16) & 0x0000ffff0000ffffLL) | ((x << 16) & 0xffff0000ffff0000LL); x = ((x >> 32) & 0x00000000ffffffffLL) | ((x << 32) & 0xffffffff00000000LL); return x; } using namespace std; class bignum { friend istream &operator>>(istream &, bignum &); friend ostream &operator<<(ostream &, const bignum &); friend bignum operator+(const bignum &, const bignum &); friend bignum operator-(const bignum &, const bignum &); friend bignum operator*(const bignum &, const bignum &); friend bignum operator/(const bignum &, const bignum &); friend bignum operator%(const bignum &, const bignum &); friend bignum operator+(const bignum &, const int &); friend bignum operator-(const bignum &, const int &); friend bignum operator*(const bignum &, const int &); friend bignum operator/(const bignum &, const int &); friend bignum operator%(const bignum &, const int &); friend bool operator==(const bignum &, const bignum &); friend bool operator!=(const bignum &, const bignum &); friend bool operator<(const bignum &, const bignum &); friend bool operator>(const bignum &, const bignum &); friend bool operator<=(const bignum &, const bignum &); friend bool operator>=(const bignum &, const bignum &); friend bool operator==(const bignum &, const int &); friend bool operator!=(const bignum &, const int &); friend bool operator<(const bignum &, const int &); friend bool operator>(const bignum &, const int &); friend bool operator<=(const bignum &, const int &); friend bool operator>=(const bignum &, const int &); friend int do_comp(const bignum &, const int &); friend int do_comp(const bignum &, const bignum &); friend void divide(const bignum &, const bignum &, bignum &, bignum &); friend bignum pow(bignum, int); public: inline bignum(){}; inline bignum(int s) { while (s != 0) { data.push_back(s % 100000000); s /= 100000000; } if (data.empty()) data.push_back(0); } inline bignum(long long s) { while (s != 0) { data.push_back(int(s % 100000000)); s /= 100000000; } if (data.empty()) data.push_back(0); } inline bignum(string s) { int t, i; data.clear(); for (i = int(s.size()) - 8; i > 0; i -= 8) { istringstream(s.substr(i, 8)) >> t; data.push_back(t); } istringstream(s.substr(0, i + 8)) >> t; data.push_back(t); } void operator=(const int); void operator=(const string); void operator=(const bignum); bignum &operator+=(const bignum &); bignum &operator-=(const bignum &); bignum &operator*=(const bignum &); bignum &operator/=(const bignum &); bignum &operator%=(const bignum &); bignum &operator+=(const int &); bignum &operator-=(const int &); bignum &operator*=(const int &); bignum &operator/=(const int &); bignum &operator%=(const int &); bignum &operator%=(const long long &); bool undefined(); int do_try(const int &); int do_try(const bignum &); void do_trim(); list<int> data; void add(const int a) { list<int>::iterator it = data.end(); it--; if ((*it) < 10) (*it) = a; else if ((*it) < 100) (*it) = (*it) % 10 + 10 * a; else if ((*it) < 1000) (*it) = (*it) % 100 + 100 * a; else if ((*it) < 10000) (*it) = (*it) % 1000 + 1000 * a; else if ((*it) < 100000) (*it) = (*it) % 10000 + 10000 * a; else if ((*it) < 1000000) (*it) = (*it) % 100000 + 100000 * a; else if ((*it) < 10000000) (*it) = (*it) % 1000000 + 1000000 * a; else if ((*it) < 100000000) (*it) = (*it) % 10000000 + 10000000 * a; } void clear() { data.clear(); } long long t() { if (data.size() == 1) return *data.begin(); else { list<int>::iterator it = data.begin(), jt = data.begin(); ++it; return (long long)(*it) * 100000000 + (*jt); } } int size() { list<int>::iterator it; int res = 0; for (it = data.begin(); it != data.end(); it++) res += 8; it--; if (*it >= 10000) { if ((*it) >= 1000000) { if (*it >= 10000000) ; else res--; } else { if ((*it) >= 100000) res -= 2; else res -= 3; } } else if ((*it) >= 100) { if (*it >= 1000) res -= 4; else res -= 5; } else { if ((*it) >= 10) res -= 6; else res -= 7; } return res; } void do_reserve(int a) { if (a <= 0) return; list<int>::iterator it; for (it = data.begin(); it != data.end() && a > 0; it++) a -= 8; if (it == data.end() && a >= 0) return; a += 8, it--; int f = 1; for (int i = 0; i < a; i++) f *= 10; (*it) %= f; data.erase(++it, data.end()); do_trim(); } void output() { list<int>::reverse_iterator i = data.rbegin(); printf( %d , *i); for (i++; i != data.rend(); i++) printf( %08d , *i); } }; inline void bignum::operator=(const bignum a) { data.clear(); for (list<int>::const_iterator i = a.data.begin(); i != a.data.end(); i++) { data.push_back(*i); } } inline void bignum::operator=(const string a) { (*this) = bignum(a); } inline void bignum::operator=(const int a) { (*this) = bignum(a); } inline istream &operator>>(istream &input, bignum &a) { string s; int t, i; input >> s; a.data.clear(); for (i = int(s.size()) - 8; i > 0; i -= 8) { istringstream(s.substr(i, 8)) >> t; a.data.push_back(t); } istringstream(s.substr(0, i + 8)) >> t; a.data.push_back(t); return input; } inline ostream &operator<<(ostream &output, const bignum &a) { list<int>::const_reverse_iterator i = a.data.rbegin(); output << *i; for (i++; i != a.data.rend(); i++) { if (*i >= 10000) { if (*i >= 1000000) { if (*i >= 10000000) cout << *i; else cout << 0 << *i; } else { if (*i >= 100000) cout << 00 << *i; else cout << 000 << *i; } } else { if (*i >= 100) { if (*i >= 1000) cout << 0000 << *i; else cout << 00000 << *i; } else { if (*i >= 10) cout << 000000 << *i; else cout << 0000000 << *i; } } } return output; } inline bool bignum::undefined() { return data.empty(); } inline int do_comp(const bignum &a, const bignum &b) { if (a.data.size() < b.data.size()) return -1; if (a.data.size() > b.data.size()) return 1; list<int>::const_reverse_iterator i; list<int>::const_reverse_iterator j; for (i = a.data.rbegin(), j = b.data.rbegin(); j != b.data.rend(); i++, j++) { if (*i < *j) return -1; if (*i > *j) return 1; } return 0; } inline int do_comp(const bignum &a, const int &b) { return do_comp(a, bignum(b)); } inline bool operator==(const bignum &a, const bignum &b) { return do_comp(a, b) == 0; } inline bool operator!=(const bignum &a, const bignum &b) { return do_comp(a, b) != 0; } inline bool operator<(const bignum &a, const bignum &b) { return do_comp(a, b) == -1; } inline bool operator>(const bignum &a, const bignum &b) { return do_comp(a, b) == 1; } inline bool operator<=(const bignum &a, const bignum &b) { return do_comp(a, b) != 1; } inline bool operator>=(const bignum &a, const bignum &b) { return do_comp(a, b) != -1; } inline bool operator==(const bignum &a, const int &b) { return do_comp(a, b) == 0; } inline bool operator!=(const bignum &a, const int &b) { return do_comp(a, b) != 0; } inline bool operator<(const bignum &a, const int &b) { return do_comp(a, b) == -1; } inline bool operator>(const bignum &a, const int &b) { return do_comp(a, b) == 1; } inline bool operator<=(const bignum &a, const int &b) { return do_comp(a, b) != 1; } inline bool operator>=(const bignum &a, const int &b) { return do_comp(a, b) != -1; } inline void bignum::do_trim() { while (data.size() > 1 && data.back() == 0) data.pop_back(); } inline bignum &bignum::operator+=(const bignum &a) { list<int>::iterator i; list<int>::const_iterator j; int t = 0; for (i = data.begin(), j = a.data.begin(); i != data.end() && j != a.data.end(); i++, j++) { *i += *j + t; t = *i / 100000000; *i %= 100000000; } while (i != data.end()) { *i += t; t = *i / 100000000; *i %= 100000000; i++; } while (j != a.data.end()) { data.push_back(t + *j); t = data.back() / 100000000; data.back() %= 100000000; j++; } if (t != 0) data.push_back(t); return *this; } inline bignum &bignum::operator-=(const bignum &a) { list<int>::iterator i; list<int>::const_iterator j; int t = 0; for (i = data.begin(), j = a.data.begin(); j != a.data.end(); i++, j++) { *i -= t + *j; if (*i >= 0) t = 0; else *i += 100000000, t = 1; } while (i != data.end()) { *i -= t; if (*i >= 0) t = 0; else *i += 100000000, t = 1; i++; } (*this).do_trim(); return *this; } inline bignum &bignum::operator+=(const int &a) { return (*this) += bignum(a); } inline bignum &bignum::operator-=(const int &a) { return (*this) -= bignum(a); } inline bignum operator+(const bignum &a, const bignum &b) { list<int>::const_iterator i, j; bignum c; int t = 0; for (i = a.data.begin(), j = b.data.begin(); i != a.data.end() && j != b.data.end(); i++, j++) { c.data.push_back(t + *i + *j); t = c.data.back() / 100000000; c.data.back() %= 100000000; } while (i != a.data.end()) { c.data.push_back(t + *i); t = c.data.back() / 100000000; c.data.back() %= 100000000; i++; } while (j != b.data.end()) { c.data.push_back(t + *j); t = c.data.back() / 100000000; c.data.back() %= 100000000; j++; } if (t != 0) c.data.push_back(t); return c; } inline bignum operator-(const bignum &a, const bignum &b) { list<int>::const_iterator i, j; bignum c; int t = 0; for (i = a.data.begin(), j = b.data.begin(); j != b.data.end(); i++, j++) { t = *i - t; if (t >= *j) c.data.push_back(t - *j), t = 0; else c.data.push_back(t + 100000000 - *j), t = 1; } while (i != a.data.end()) { t = *i - t; if (t >= 0) c.data.push_back(t), t = 0; else c.data.push_back(t + 100000000), t = 1; i++; } c.do_trim(); return c; } inline bignum operator*(const bignum &a, const bignum &b) { list<int>::const_iterator i, j; list<int>::iterator k, kk; bignum c; long long t = 0; for (int i = 0; i < a.data.size() + b.data.size(); i++) c.data.push_back(0); for (i = a.data.begin(), k = c.data.begin(); i != a.data.end(); i++, k++) { for (j = b.data.begin(), kk = k; j != b.data.end(); j++, kk++) { t += (long long)(*i) * (*j) + (*kk); *kk = int(t % 100000000); t /= 100000000; } *kk += t; t = 0; } c.do_trim(); return c; } inline int bignum::do_try(const bignum &a) { int l = 1, r = 99999999, m, t; while (l + 2 < r) { m = (l + r) / 2; t = do_comp(*this, a * bignum(m)); if (t == 0) return m; if (t < 0) r = m - 1; else l = m; } while (do_comp(*this, a * bignum(r)) < 0) r--; return r; } inline void divide(const bignum &a, const bignum &b, bignum &d, bignum &r) { list<int>::const_reverse_iterator i = a.data.rbegin(); int t; d = bignum(0); r = bignum(0); do { while (r < b && i != a.data.rend()) { d.data.push_front(0); r.data.push_front(*i); r.do_trim(); i++; } if (r >= b) { t = r.do_try(b); d.data.front() = t; r -= (b * bignum(t)); } } while (i != a.data.rend()); d.do_trim(); } inline bignum operator/(const bignum &a, const bignum &b) { bignum d, r; divide(a, b, d, r); return d; } inline bignum operator%(const bignum &a, const bignum &b) { bignum d, r; divide(a, b, d, r); return r; } inline bignum operator+(const bignum &a, const int &b) { return a + bignum(b); } inline bignum operator-(const bignum &a, const int &b) { return a - bignum(b); } inline bignum operator*(const bignum &a, const int &b) { return a * bignum(b); } inline bignum operator/(const bignum &a, const int &b) { return a / bignum(b); } inline bignum &bignum::operator*=(const bignum &a) { (*this) = (*this) * a; return *this; } inline bignum &bignum::operator/=(const bignum &a) { (*this) = (*this) / a; return *this; } inline bignum &bignum::operator%=(const bignum &a) { (*this) = (*this) % a; return *this; } inline bignum &bignum::operator*=(const int &a) { return (*this) *= bignum(a); } inline bignum &bignum::operator/=(const int &a) { return (*this) /= bignum(a); } inline bignum &bignum::operator%=(const long long &b) { return (*this) %= bignum(b); } inline bignum pow(bignum a, int b) { bignum c(1); while (b != 0) { if (b & 1) c *= a; a = a * a; b >>= 1; } return c; } inline int rand32() { return (bool(rand() & 1) << 30) | (rand() << 15) + rand(); } inline int random32(int l, int r) { return rand32() % (r - l + 1) + l; } inline int random(int l, int r) { return rand() % (r - l + 1) + l; } int dice() { return rand() % 6; } bool coin() { return rand() % 2; } template <class T> inline void RD(T &x) { char c; for (c = getchar(); c < 0 ; c = getchar()) ; x = c - 0 ; for (c = getchar(); c >= 0 ; c = getchar()) x = x * 10 + c - 0 ; } template <class T> inline void OT(const T &x) { printf( %d n , x); } const int maxn = 2; long long modo; class Mat { public: int Matn, Matm; long long a[maxn][maxn]; Mat() { Matn = 0; Matm = 0; memset(a, 0, sizeof(a)); } void output(); void init(); void initI(); Mat mul(const Mat &a); Mat power(const Mat &a, long long k); }; void Mat::output() { for (int i = 0; i < Matn; ++i) { for (int j = 0; j < Matm; ++j) { if (j != 0) printf( ); printf( %d , a[i][j]); } printf( n ); } } void Mat::init() { Matn = 0; Matm = 0; memset(a, 0, sizeof(a)); } Mat Mat::mul(const Mat &A) { Mat c; c.Matn = Matn; c.Matm = A.Matm; for (int i = 0; i < Matn; ++i) for (int j = 0; j < A.Matm; ++j) { for (int k = 0; k < Matm; ++k) { c.a[i][j] = (c.a[i][j] + (a[i][k] * A.a[k][j]) % modo) % modo; } } return c; } void Mat::initI() { memset(a, 0, sizeof(a)); for (int i = 0; i < Matn; ++i) a[i][i] = 1LL; } Mat Mat::power(const Mat &a, long long k) { Mat c = a, b; b.init(); b.Matn = a.Matn; b.Matm = a.Matm; b.initI(); while (k) { if (k & 1LL) b = b.mul(c); c = c.mul(c); k >>= 1LL; } return b; } long long gao(long long t) { if (t <= 1) return 1LL; Mat a; a.Matm = a.Matn = 2; a.a[0][0] = 1LL, a.a[1][0] = 1LL, a.a[0][1] = 1LL; a = a.power(a, t - 1LL); return a.a[0][0]; } long long l, r, k; void solve() { long long tmp, ans, tmp1; if ((r - l) / k <= 2000000) { for (long long i = (r - l) / (k - 1); i >= (r - l) / k; i--) { if ((r / i - (l - 1) / i) >= k) { ans = i; break; } } } else { for (long long i = k - 1; i <= 2000000; i++) { tmp = r / i; tmp1 = tmp * (i - k + 1); if (tmp1 >= l) { ans = tmp; break; } } } cout << gao(ans) % modo << endl; } int main() { while (cin >> modo >> l >> r >> k) solve(); }
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#include <bits/stdc++.h> using namespace std; long long dp[1001][1001]; long long mem(int sz, int rem) { if (rem == 0) return 1; if (dp[sz][rem] != -1) return dp[sz][rem]; long long& ref = dp[sz][rem]; ref = 0; for (int i = 1; i <= sz - 2; i++) { long long t = (sz - 1 - i) * mem(i, rem - 1); ref = (ref + t) % 1000000007LL; } return ref; } int n, m, k; int main() { cin >> n >> m >> k; memset(dp, -1, sizeof dp); long long t1 = mem(n, k); long long t2 = mem(m, k); long long res = (t1 * t2) % 1000000007LL; cout << res << endl; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2_1_V
`define SKY130_FD_SC_HD__NOR2_1_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4_TB_V
`define SKY130_FD_SC_LS__NAND4_TB_V
/**
* nand4: 4-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ls__nand4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a[112]; int i; for (i = 0; i < 4; i++) cin >> a[i]; sort(a, a + 4); int tr = 0, seg = 0, im = 0; if (a[1] + a[2] > a[3]) { tr++; } else if (a[0] + a[1] > a[3]) { tr++; } else if (a[0] + a[2] > a[3]) { tr++; } else if (a[0] + a[1] > a[2]) { tr++; } else if (a[0] + a[1] == a[2]) seg++; else if (a[0] + a[2] == a[3]) seg++; else if (a[1] + a[2] == a[3]) seg++; else if (a[0] + a[1] == a[3]) seg++; else im++; if (tr > 0) cout << TRIANGLE << endl; else if (seg > 0) cout << SEGMENT << endl; else if (im > 0) cout << IMPOSSIBLE << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = (1 << 20) + 1000; const int INF = 1000000000; const int Mod = 1000000007; void update(int tree[], int k, int v) { while (k < N) { tree[k] += v; k += k & (-k); } } int get(int tree[], int k) { int ret = 0; while (k) { ret += tree[k]; k -= k & (-k); } return ret; } int a[N], n, tot, r[N], mp[N], tree[N]; long long dp[30], sum[30], f[30]; bool cmpr(int i, int j) { return a[i] < a[j]; } int Hash() { for (int i = 0; i < tot; i++) r[i] = i; sort(r, r + tot, cmpr); int K = 1; mp[1] = a[r[0]]; for (int i = 0; i < tot; i++) { if (mp[K] != a[r[i]]) mp[++K] = a[r[i]]; a[r[i]] = K; } return K; } int main() { scanf( %d , &n); tot = 1 << n; for (int i = 0; i < tot; i++) scanf( %d , &a[i]); int fuck = Hash(); for (int i = 1; i <= n; i++) { dp[i] += dp[i - 1]; sum[i] += sum[i - 1]; int len = 1 << (i - 1); for (int j = tot / len - 2; j >= 0; j -= 2) { for (int k = 0; k < len; k++) update(tree, a[(j + 1) * len + k], 1); for (int k = 0; k < len; k++) { int tmp = get(tree, a[j * len + k] - 1); sum[i] += tmp; dp[i] += tmp; } for (int k = 0; k < len; k++) update(tree, a[(j + 1) * len + k], -1); for (int k = 0; k < len; k++) update(tree, a[j * len + k], 1); for (int k = 0; k < len; k++) { sum[i] += get(tree, a[(j + 1) * len + k] - 1); } for (int k = 0; k < len; k++) update(tree, a[j * len + k], -1); } } int m; scanf( %d , &m); while (m--) { int x; scanf( %d , &x); long long t1 = dp[x], t2 = sum[x] - dp[x]; f[0] = 0; for (int i = 1; i < x; i++) { f[i] = dp[i]; dp[i] = sum[i] - dp[i]; } for (int i = x; i <= n; i++) { dp[i] = dp[i] - t1 + t2; } printf( %I64d n , dp[n]); } return 0; }
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#include <bits/stdc++.h> using namespace std; int n; int p[4][4]; int a[(1 << 16)]; int sum1[4]; int sum2[4]; int dio1, dio2; bool ok; int mask; void dfs(int x) { int i, j; if (x == n * n) { if (dio1 == dio2 && dio1 == sum1[0] && sum1[1] == dio1 && sum1[2] == dio1 && sum2[0] == dio1 && sum2[1] == dio1 && sum2[2] == dio1) { ok = true; printf( %d n , dio1); for (i = 0; i < n; i++) { printf( %d , p[i][0]); for (j = 1; j < n; j++) printf( %d , p[i][j]); printf( n ); } } return; } for (i = 0; i < n * n && !ok; i++) if ((mask & (1 << i)) == 0) { mask |= (1 << i); p[x / n][x % n] = a[i]; sum1[x / n] += a[i]; sum2[x % n] += a[i]; if (x / n == x % n) dio1 += a[i]; if (x == 2 || x == 4 || x == 6) dio2 += a[i]; dfs(x + 1); sum1[x / n] -= a[i]; sum2[x % n] -= a[i]; if (x / n == x % n) dio1 -= a[i]; if (x == 2 || x == 4 || x == 6) dio2 -= a[i]; mask ^= (1 << i); } } void dfs2(int x) { int i, j; if (x == n * n) { if (dio1 == dio2 && dio1 == sum1[0] && sum1[1] == dio1 && sum2[0] == dio1 && sum2[1] == dio1) { ok = true; printf( %d n , dio1); for (i = 0; i < n; i++) { printf( %d , p[i][0]); for (j = 1; j < n; j++) printf( %d , p[i][j]); printf( n ); } } return; } for (i = 0; i < n * n && !ok; i++) if ((mask & (1 << i)) == 0) { mask |= (1 << i); p[x / n][x % n] = a[i]; sum1[x / n] += a[i]; sum2[x % n] += a[i]; if (x / n == x % n) dio1 += a[i]; if (x == 1 || x == 2) dio2 += a[i]; dfs2(x + 1); sum1[x / n] -= a[i]; sum2[x % n] -= a[i]; if (x / n == x % n) dio1 -= a[i]; if (x == 1 || x == 2) dio2 -= a[i]; mask ^= (1 << i); } } int sum; void super_dfs(int x) { int i, j; if (x == 16) { if (dio1 == dio2 && dio1 == sum1[0] && dio1 == sum1[3]) if (dio1 == sum2[1]) { ok = true; printf( %d n , dio1); for (i = 0; i < n; i++) { printf( %d , p[i][0]); for (j = 1; j < n; j++) printf( %d , p[i][j]); printf( n ); } } return; } int tem; int znac; if (x > 3 && sum1[0] != sum) return; if (x == 7) { if (ok) return; tem = (1 << 16) - 1; tem ^= mask; while (tem > 0) { znac = tem - (tem & (tem - 1)); if (a[znac] == sum1[0] - sum1[1]) { mask |= znac; p[1][3] = a[znac]; sum1[1] = sum1[0]; sum2[3] += a[znac]; super_dfs(x + 1); sum1[1] -= a[znac]; sum2[3] -= a[znac]; mask ^= znac; break; } tem &= (tem - 1); } return; } if (x == 8) { tem = (1 << 16) - 1; tem ^= mask; while (tem > 0 && !ok) { znac = tem - (tem & (tem - 1)); mask |= znac; p[(x >> 2)][(x & 3)] = a[znac]; sum1[(x >> 2)] += a[znac]; sum2[(x & 3)] += a[znac]; if ((x >> 2) == (x & 3)) dio1 += a[znac]; if (x == 3 || x == 6 || x == 12) dio2 += a[znac]; int tt = (1 << 16) - 1; tt ^= mask; while (tt > 0) { int zc = tt - (tt & (tt - 1)); if (a[zc] + sum2[0] == sum) { sum2[0] = sum; sum1[3] += a[zc]; dio2 += a[zc]; mask |= zc; p[3][0] = a[zc]; super_dfs(x + 1); dio2 -= a[zc]; sum2[0] -= a[zc]; sum1[3] -= a[zc]; mask ^= zc; } tt &= (tt - 1); } if ((x >> 2) == (x & 3)) dio1 -= a[znac]; if (x == 3 || x == 6 || x == 12) dio2 -= a[znac]; sum1[(x >> 2)] -= a[znac]; sum2[(x & 3)] -= a[znac]; mask ^= znac; tem &= (tem - 1); } return; } if (x == 9) { if (ok) return; tem = (1 << 16) - 1; tem ^= mask; while (tem > 0) { znac = tem - (tem & (tem - 1)); if (a[znac] == sum2[0] - dio2) { mask |= znac; p[2][1] = a[znac]; sum2[1] += a[znac]; sum1[2] += a[znac]; dio2 = sum2[0]; super_dfs(x + 1); sum2[1] -= a[znac]; sum1[2] -= a[znac]; dio2 -= a[znac]; mask ^= znac; break; } tem &= (tem - 1); } return; } if (x == 11) { if (ok) return; if (sum1[1] - sum1[2] != dio1 - sum2[3]) return; tem = (1 << 16) - 1; tem ^= mask; while (tem > 0) { znac = tem - (tem & (tem - 1)); if (a[znac] == dio1 - sum2[3]) { mask |= znac; p[2][3] = a[znac]; sum2[3] = dio1; sum1[2] += a[znac]; super_dfs(13); sum2[3] -= a[znac]; sum1[2] -= a[znac]; mask ^= znac; break; } tem &= (tem - 1); } return; } if (x == 13) { if (ok) return; tem = (1 << 16) - 1; tem ^= mask; while (tem > 0) { znac = tem - (tem & (tem - 1)); if (a[znac] == sum2[0] - sum2[1]) { mask |= znac; p[3][1] = a[znac]; sum2[1] = sum2[0]; sum1[3] += a[znac]; super_dfs(x + 1); sum2[1] -= a[znac]; sum1[3] -= a[znac]; mask ^= znac; break; } tem &= (tem - 1); } return; } if (x == 14) { if (ok) return; tem = (1 << 16) - 1; tem ^= mask; while (tem > 0) { znac = tem - (tem & (tem - 1)); if (a[znac] == sum2[1] - sum2[2]) { mask |= znac; p[3][2] = a[znac]; sum2[2] = sum2[1]; sum1[3] += a[znac]; super_dfs(x + 1); sum2[2] -= a[znac]; sum1[3] -= a[znac]; mask ^= znac; break; } tem &= (tem - 1); } return; } tem = (1 << 16) - 1; tem ^= mask; while (tem > 0 && !ok) { znac = tem - (tem & (tem - 1)); mask |= znac; p[(x >> 2)][(x & 3)] = a[znac]; sum1[(x >> 2)] += a[znac]; sum2[(x & 3)] += a[znac]; if ((x >> 2) == (x & 3)) dio1 += a[znac]; if (x == 3 || x == 6 || x == 12) dio2 += a[znac]; super_dfs(x + 1); if ((x >> 2) == (x & 3)) dio1 -= a[znac]; if (x == 3 || x == 6 || x == 12) dio2 -= a[znac]; sum1[(x >> 2)] -= a[znac]; sum2[(x & 3)] -= a[znac]; mask ^= znac; tem &= (tem - 1); } } int main() { scanf( %d , &n); int i; int ss = 0; for (i = 0; i < n * n; i++) { scanf( %d , &a[(1 << i)]); ss += a[(1 << i)]; } if (n == 1) { printf( %d n , a[1]); printf( %d n , a[1]); return 0; } if (n == 2) { for (i = 0; i < n * n; i++) a[i] = a[(1 << i)]; dfs2(0); return 0; } if (n == 3) { for (i = 0; i < n * n; i++) a[i] = a[(1 << i)]; dfs(0); return 0; } if (n == 4) { sum = ss / n; super_dfs(0); return 0; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211OI_SYMBOL_V
`define SKY130_FD_SC_HDLL__A211OI_SYMBOL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a211oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211OI_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:16:05 04/24/2015
// Design Name:
// Module Name: StartCastle
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module StartCastle(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]wall;
output [7:0]mapData;
reg [7:0]mColor;
always @(posedge clk_vga) begin
if(CurrentY < 40) begin
mColor[7:0] <= wall;
end
else if(CurrentX < 40) begin
mColor[7:0] <= wall;
end
else if(~(CurrentX < 600)) begin
mColor[7:0] <= wall;
end
else if((~(CurrentY < 440) && (CurrentX < 260)) || (~(CurrentY < 440) && ~(CurrentX < 380))) begin
mColor[7:0] <= wall;
end else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of array querying functions.
//
// This code instantiates a module that calls the various array querying
// functions.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire a = clk;
wire b = 1'b0;
reg c;
array_test array_test_i (/*AUTOINST*/
// Inputs
.clk (clk));
endmodule
// Check the array sizing functions work correctly.
module array_test
#( parameter
LEFT = 5,
RIGHT = 55)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off LITENDIAN
reg [7:0] a [LEFT:RIGHT];
// verilator lint_on LITENDIAN
integer l;
integer r;
integer s;
always @(posedge clk) begin
l = $left (a);
r = $right (a);
s = $size (a);
`ifdef TEST_VERBOSE
$write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s);
`endif
if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// Very simple test for interface pathclearing
`ifdef VCS
`define UNSUPPORTED_MOD_IN_GENS
`endif
`ifdef VERILATOR
`define UNSUPPORTED_MOD_IN_GENS
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc #(1) itopa();
ifc #(2) itopb();
sub #(1) ca (.isub(itopa),
.i_value(4));
sub #(2) cb (.isub(itopb),
.i_value(5));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (itopa.MODE != 1) $stop;
if (itopb.MODE != 2) $stop;
end
if (cyc==20) begin
if (itopa.get_value() != 4) $stop;
if (itopb.get_value() != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub
#(parameter MODE = 0)
(
ifc.out_modport isub,
input integer i_value
);
`ifdef UNSUPPORTED_MOD_IN_GENS
always @* isub.value = i_value;
`else
generate if (MODE == 1) begin
always @* isub.valuea = i_value;
end
else if (MODE == 2) begin
always @* isub.valueb = i_value;
end
endgenerate
`endif
endmodule
interface ifc;
parameter MODE = 0;
// Modports under generates not supported by all commercial simulators
`ifdef UNSUPPORTED_MOD_IN_GENS
integer value;
modport out_modport (output value);
function integer get_value(); return value; endfunction
`else
generate if (MODE == 0) begin
integer valuea;
modport out_modport (output valuea);
function integer get_valuea(); return valuea; endfunction
end
else begin
integer valueb;
modport out_modport (output valueb);
function integer get_valueb(); return valueb; endfunction
end
endgenerate
`endif
endinterface
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Parameter LE tells us if we are little-endian.
// Little-endian means send lower 16 bits first.
// Default is big endian (network order), send upper bits first.
module fifo36_to_fifo72
#(parameter LE=0)
(input clk, input reset, input clear,
input [35:0] f36_datain,
input f36_src_rdy_i,
output f36_dst_rdy_o,
output [71:0] f72_dataout,
output f72_src_rdy_o,
input f72_dst_rdy_i,
output [31:0] debug
);
// Shortfifo on input to guarantee no deadlock
wire [35:0] f36_data_int;
wire f36_src_rdy_int, f36_dst_rdy_int;
fifo_short #(.WIDTH(36)) head_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(f36_datain), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o),
.dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int),
.space(),.occupied() );
// Actual f36 to f72 which could deadlock if not connected to shortfifos
reg f72_sof_int, f72_eof_int;
reg [2:0] f72_occ_int;
wire [71:0] f72_data_int;
wire f72_src_rdy_int, f72_dst_rdy_int;
reg [1:0] state;
reg [31:0] dat0, dat1;
wire f36_sof_int = f36_data_int[32];
wire f36_eof_int = f36_data_int[33];
wire [1:0] f36_occ_int = f36_data_int[35:34];
wire xfer_out = f72_src_rdy_int & f72_dst_rdy_int;
always @(posedge clk)
if(f36_src_rdy_int & ((state==0)|xfer_out))
f72_sof_int <= f36_sof_int;
always @(posedge clk)
if(f36_src_rdy_int & ((state != 2)|xfer_out))
f72_eof_int <= f36_eof_int;
always @(posedge clk)
if(reset)
begin
state <= 0;
f72_occ_int <= 0;
end
else
if(f36_src_rdy_int)
case(state)
0 :
begin
dat0 <= f36_data_int;
if(f36_eof_int)
begin
state <= 2;
case (f36_occ_int)
0 : f72_occ_int <= 3'd4;
1 : f72_occ_int <= 3'd1;
2 : f72_occ_int <= 3'd2;
3 : f72_occ_int <= 3'd3;
endcase // case (f36_occ_int)
end
else
state <= 1;
end
1 :
begin
dat1 <= f36_data_int;
state <= 2;
if(f36_eof_int)
case (f36_occ_int)
0 : f72_occ_int <= 3'd0;
1 : f72_occ_int <= 3'd5;
2 : f72_occ_int <= 3'd6;
3 : f72_occ_int <= 3'd7;
endcase // case (f36_occ_int)
end
2 :
if(xfer_out)
begin
dat0 <= f36_data_int;
if(f36_eof_int) // remain in state 2 if we are at eof
case (f36_occ_int)
0 : f72_occ_int <= 3'd4;
1 : f72_occ_int <= 3'd1;
2 : f72_occ_int <= 3'd2;
3 : f72_occ_int <= 3'd3;
endcase // case (f36_occ_int)
else
state <= 1;
end
endcase // case(state)
else
if(xfer_out)
begin
state <= 0;
f72_occ_int <= 0;
end
assign f36_dst_rdy_int = xfer_out | (state != 2);
assign f72_data_int = LE ? {3'b000,f72_occ_int[2:0],f72_eof_int,f72_sof_int,dat1,dat0} :
{3'b000,f72_occ_int[2:0],f72_eof_int,f72_sof_int,dat0,dat1};
assign f72_src_rdy_int = (state == 2);
assign debug = state;
// Shortfifo on output to guarantee no deadlock
fifo_short #(.WIDTH(72)) tail_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(f72_data_int), .src_rdy_i(f72_src_rdy_int), .dst_rdy_o(f72_dst_rdy_int),
.dataout(f72_dataout), .src_rdy_o(f72_src_rdy_o), .dst_rdy_i(f72_dst_rdy_i),
.space(),.occupied() );
endmodule // fifo36_to_fifo72
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } bool isV(char x) { if (x == a || x == e || x == i || x == o || x == u ) { return 1; } return 0; } bool isP(long long n) { for (long long i = 2; i * i <= n; i++) { if (n % i == 0) return 0; } return 1; } void fio() { ios_base::sync_with_stdio(false); cin.tie(NULL); } void print(long long* a, long long n) { long long i; for (i = 0; i < (long long)n; i++) { cout << a[i] << ; } cout << endl; } void print2d(long long a[][1000], long long m, long long n) { long long i, j; for (i = 0; i < (long long)m; i++) { for (j = 0; j < (long long)n; j++) { cout << setw(2) << a[i][j]; } cout << endl; } } int32_t main() { fio(); long long n; cin >> n; long long* a = new long long[n]; long long i; for (i = 0; i < (long long)n; i++) { cin >> a[i]; } long long* suf = new long long[n]; suf[n - 1] = 0; stack<long long> s; for (i = n - 1; i >= (long long)0; i--) { while (s.size() > 0 && a[i] <= a[s.top()]) s.pop(); if (s.size() != 0) { suf[i] = suf[s.top()] + (s.top() - i - 1) * a[i] + a[s.top()]; } else { suf[i] = (n - (i + 1)) * a[i]; } s.push(i); } long long* temp = new long long[n]; long long* pref = new long long[n]; pref[0] = 0; long long m = 0, mi = -1; stack<long long> x; for (i = 0; i < (long long)n; i++) { while (x.size() > 0 && a[x.top()] > a[i]) x.pop(); if (x.size() == 0) pref[i] = i * a[i]; else pref[i] = pref[x.top()] + (i - x.top() - 1) * a[i] + a[x.top()]; x.push(i); if (m < pref[i] + suf[i] + a[i]) { m = pref[i] + suf[i] + a[i]; mi = i; } } for (i = mi + 1; i < (long long)n; i++) { if (a[i] > a[i - 1]) a[i] = a[i - 1]; } for (i = mi - 1; i >= (long long)0; i--) { if (a[i] > a[i + 1]) a[i] = a[i + 1]; } for (i = 0; i < (long long)n; i++) cout << a[i] << ; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool smin(T &a, const T &b) { return b < a ? a = b, 1 : 0; } template <typename T> inline bool smax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } const long long N = (long long)1e6 + 10; long long n, ar[N], m, bl[N], br[N], pre[N], fen[N], res[N]; vector<long long> qs[N]; map<long long, long long> last; long long get_xor(long long l, long long r) { if (!l) return pre[r]; return pre[r] ^ pre[l - 1]; } void add(long long i, long long val) { for (; i < N; i += (i & -i)) fen[i] ^= val; } long long get(long long i) { long long ret = 0; for (; i; i ^= (i & -i)) ret ^= fen[i]; return ret; } void add(long long l, long long r, long long val) { add(r, val); if (l > 1) add(l - 1, val); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (long long i = 1; i <= n; ++i) { cin >> ar[i]; if (i) pre[i] = pre[i - 1]; pre[i] ^= ar[i]; } cin >> m; for (long long j = 0; j < m; ++j) { cin >> bl[j] >> br[j]; qs[br[j]].push_back(j); } for (long long j = 1; j <= n; ++j) last[ar[j]] = -1; for (long long i = 1; i <= n; ++i) { long long x = ar[i]; if (last[x] == -1) add(1, i, x); else add(last[x] + 1, i, x); last[x] = i; for (long long p : qs[i]) { res[p] = get_xor(bl[p], i); res[p] ^= get(i); res[p] ^= get(bl[p] - 1); } } for (long long j = 0; j < m; ++j) cout << res[j] << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DIODE_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) bool check(string pattern, string text) { int j = 0; int i = 0; while (i < text.size()) { if (pattern[j] == text[i]) { j++; } i++; } return j == pattern.size(); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int d; cin >> d; while (d--) { string s, t, p; cin >> s >> t >> p; string k = s; s = s + p; map<char, long long int> m_s; map<char, long long int> m_t; for (int i = 0; i < s.size(); ++i) { m_s[s[i]]++; } for (int i = 0; i < t.size(); ++i) { m_t[t[i]]++; } bool checks = true; for (auto i : m_t) { if (m_s[i.first] < i.second) { checks = false; } } if (checks && check(k, t)) { cout << YES << n ; } else { cout << NO << n ; } } }
|
#include <bits/stdc++.h> using namespace std; int func(int a) { int cnt = 0; while (a) { cnt++; a /= 10; } return cnt; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, k; cin >> n >> k; vector<long long> v(n); map<int, int> m[11]; long long ans = 0; for (int i = 0; i < n; i++) { cin >> v[i]; long long c = 10; for (int j = 1; j <= 10; j++) { m[j][((v[i] % k) * (c % k)) % k]++; c *= 10; } } for (int i = 0; i < n; i++) { int a = (k - v[i] % k) % k; int b = func(v[i]); ans += m[b][a]; long long c = 1; for (int j = 0; j < b; j++) { c *= 10; } ans -= a == (v[i] % k * c % k) % k; } cout << ans; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: California State University, Fullerton
// Engineer: Lucas Magasweran, Alan Nguyen
//
// Create Date: 17:31:25 11/16/2011
// Design Name: 8x8 Robertson's Multiplier
// Module Name: toprobertsons
// Project Name: EE557 Homework #4
// Target Devices: Simululator (xc3sd1800a-4fg676)
// Tool versions: Xilinx ISE 13.1
// Description:
// This multiplier implements the Robertson's algorithm (that was discussed
// in class) for the multiplication of two signed binary numbers in 2's
// complement format. In your design, the multiplicand must be placed in a
// register called Y. Two more registers, A and X, must also be used in your
// design. The register A is initially loaded with all 0s and the register X is
// initially loaded with the multiplier. A and X, combined, acts as a shift
// register (A:X). You may use additional hardware structures as necessary to
// complete your design. The final product must be stored in the shift register
// A:X.
// Dependencies: none.
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module toprobertsons(
input clk, reset,
input [7:0] multiplier, // 8-bit data input to multiplier unit
input [7:0] multiplicand, // 8-bit data input to multiplier unit
output [15:0] product, // 16-bit data output of multiplier unit
output done // flag to signal multiplication is complete to testbench
);
// instantiate Robertson's Multiplier
robsmult mult(clk, reset, multiplier, multiplicand, product, done);
// instantiate signed multipler (used for testing testbench)
//signed_mult mult(product, clk, multiplier, multiplicand);
endmodule
|
`include "timescale.v"
module fb_slave_counters (MRxClk, Clk_100MHz, Reset, MRxDV, RxValid, MRxDEqDataSoC, MTxEn_TxSync2,
StateIdle, StatePreamble, StateNumb, StateSlaveID, StateDist, StateDelay, StateDelayMeas,
StateDelayDist, StateData, StateSlaveData, StateSlaveCrc, StateFrmCrc,
TotalRecvNibCnt, TotalSentNibCnt, LogicDelay, SlaveCrcEnd, FrmCrcStateEnd, TxRamAddr, RxRamAddr
);
input MRxClk; // Tx clock
input Clk_100MHz;
input Reset; // Reset
input MRxDV;
input RxValid;
input MRxDEqDataSoC;
input MTxEn_TxSync2;
input StateIdle; // Idle state
input StatePreamble; // Preamble state
input StateNumb;
input [1:0] StateSlaveID;
input StateDist;
input StateDelay;
input StateDelayMeas;
input StateDelayDist;
input StateData; // Data state
input [1:0] StateSlaveData; // StateSlaveData state
input StateSlaveCrc; // slave CRC state
input StateFrmCrc;
output [15:0] TotalSentNibCnt;
output [15:0] TotalRecvNibCnt; // total Nibble counter
output [7:0] LogicDelay; // Nibble counter
output [7: 0] TxRamAddr;
output [7: 0] RxRamAddr;
output SlaveCrcEnd;
output FrmCrcStateEnd;
reg [15:0] TotalSentNibCnt;
reg [15:0] TotalRecvNibCnt;
reg [7:0] LogicDelay;
reg [7:0] LogicDelayCnt;
reg [3: 0] CrcNibCnt;
reg [3: 0] PreambleNibCnt;
reg [3: 0] FrmCrcNibCnt;
reg [7: 0] TxRamAddr;
reg [7: 0] RxRamAddr;
reg ResetLogicDelayCnt_100MHzSync1 ;
reg ResetLogicDelayCnt_100MHzSync2 ;
reg IncrementLogicDelayCnt_100MHzSync1 ;
reg IncrementLogicDelayCnt_100MHzSync2 ;
reg MTxEn_TxSync2_100MHzSync1 ;
reg MTxEn_TxSync2_100MHzSync2 ;
reg MTxEn_TxSync2_100MHzSync3 ;
wire ResetLogicDelayCnt;
wire IncrementLogicDelayCnt;
assign IncrementLogicDelayCnt = MRxDV & ~MTxEn_TxSync2; //start counting when receiving any signal but yet not transmitting anything
assign ResetLogicDelayCnt = StateIdle & ~MRxDV ;
////////////////////////////// 100 MHz clock domain /////////////////////
always @ (posedge Clk_100MHz or posedge Reset)
begin
if(Reset)
begin
ResetLogicDelayCnt_100MHzSync1 <= 1'b0;
ResetLogicDelayCnt_100MHzSync2 <= 1'b0;
IncrementLogicDelayCnt_100MHzSync1 <= 1'b0;
IncrementLogicDelayCnt_100MHzSync2 <= 1'b0;
MTxEn_TxSync2_100MHzSync1 <= 1'b0;
MTxEn_TxSync2_100MHzSync2 <= 1'b0;
MTxEn_TxSync2_100MHzSync3 <= 1'b0;
end
else
begin
ResetLogicDelayCnt_100MHzSync1 <= ResetLogicDelayCnt;
ResetLogicDelayCnt_100MHzSync2 <= ResetLogicDelayCnt_100MHzSync1;
IncrementLogicDelayCnt_100MHzSync1 <= IncrementLogicDelayCnt;
IncrementLogicDelayCnt_100MHzSync2 <= IncrementLogicDelayCnt_100MHzSync1;
MTxEn_TxSync2_100MHzSync1 <= MTxEn_TxSync2;
MTxEn_TxSync2_100MHzSync2 <= MTxEn_TxSync2_100MHzSync1;
MTxEn_TxSync2_100MHzSync3 <= MTxEn_TxSync2_100MHzSync2;
end
end
// register logic delay
always @ (posedge Clk_100MHz or posedge Reset)
begin
if(Reset)
LogicDelay <= 8'b0;
else
if ((MTxEn_TxSync2_100MHzSync3==0) & (MTxEn_TxSync2_100MHzSync2 ==1)) // stop counting when TX start to transmitting any signal
LogicDelay <= LogicDelayCnt;
end
// delay counter count from receiving to starting sending signal
always @ (posedge Clk_100MHz or posedge Reset)
begin
if(Reset)
LogicDelayCnt <= 8'd0;
else
begin
if(ResetLogicDelayCnt_100MHzSync2)
LogicDelayCnt <= 8'd0;
else
if(IncrementLogicDelayCnt_100MHzSync2)
LogicDelayCnt <= LogicDelayCnt + 8'd1;
end
end
////////////////////////////// 100 MHz clock domain end/////////////////////
// Total Nibble Counter received for the whole frame incl.( Preamble, SoC, SlaveDate, SlaveCRC, NO FrameCRC)
wire ResetTotalRecvNibCnt;
wire IncrementTotalRecvNibCnt;
assign IncrementTotalRecvNibCnt = MRxDV;
assign ResetTotalRecvNibCnt = StateIdle;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
TotalRecvNibCnt <= 16'h0;
else
begin
if(ResetTotalRecvNibCnt)
TotalRecvNibCnt <= 16'h0;
else
if(IncrementTotalRecvNibCnt)
TotalRecvNibCnt <= TotalRecvNibCnt + 16'd1;
end
end
// Total Nibble Counter already sent( Preamble,SoC, SlaveDate, SlaveCRC, NO FrameCRC)
wire ResetTotalSentNibCnt;
wire IncrementTotalSentNibCnt;
assign IncrementTotalSentNibCnt = StateNumb | (|StateSlaveID) | StateDist | StateDelay | StateDelayMeas | StateDelayDist |StateData | (|StateSlaveData) | StateSlaveCrc ;
assign ResetTotalSentNibCnt = StateIdle;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
TotalSentNibCnt <= 16'h0;
else
begin
if(ResetTotalSentNibCnt)
TotalSentNibCnt <= 16'h0;
else
if(IncrementTotalSentNibCnt)
TotalSentNibCnt <= TotalSentNibCnt + 16'd1;
end
end
wire IncrementCrcNibCnt;
wire ResetCrcNibCnt;
assign IncrementCrcNibCnt = StateSlaveCrc ;
assign ResetCrcNibCnt = |StateSlaveData ;
assign SlaveCrcEnd = CrcNibCnt[0] ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
CrcNibCnt <= 4'b0;
else
begin
if(ResetCrcNibCnt)
CrcNibCnt <= 4'b0;
else
if(IncrementCrcNibCnt)
CrcNibCnt <= CrcNibCnt + 4'b0001;
end
end
wire IncrementFrmCrcNibCnt;
wire ResetFrmCrcNibCnt;
assign IncrementFrmCrcNibCnt = StateFrmCrc ;
assign ResetFrmCrcNibCnt = StateIdle | StatePreamble | StateData | (|StateSlaveData) | StateSlaveCrc;
assign FrmCrcStateEnd = FrmCrcNibCnt[0] ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
FrmCrcNibCnt <= 4'b0;
else
begin
if(ResetFrmCrcNibCnt)
FrmCrcNibCnt <= 4'b0;
else
if(IncrementFrmCrcNibCnt)
FrmCrcNibCnt <= FrmCrcNibCnt + 4'b0001;
end
end
wire IncrementTxRamAddr;
wire ResetTxRamAddr;
assign ResetTxRamAddr = StateIdle | StatePreamble | StateData;
assign IncrementTxRamAddr = StateSlaveData[0];
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
TxRamAddr <= 8'b0;
else
begin
if(ResetTxRamAddr)
TxRamAddr <= 8'b0;
else
if(IncrementTxRamAddr)
TxRamAddr <= TxRamAddr + 8'b0001;
end
end
wire ResetRxRamAddr;
wire IncrementRxRamAddr;
assign ResetRxRamAddr = StateIdle | StatePreamble;
assign IncrementRxRamAddr = RxValid ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxRamAddr[7:0] <= 8'd0;
else
begin
if(ResetRxRamAddr)
RxRamAddr[7:0] <= 8'd0;
else
if(IncrementRxRamAddr)
RxRamAddr[7:0] <= RxRamAddr[7:0] + 8'd1;
end
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_write_decoder(
ck,
reset_n,
do_lfsr,
dm_lfsr,
do_lfsr_step,
dm_lfsr_step,
do_code,
dm_code,
do_data,
dm_data
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DO_LFSR_WIDTH = ((AFI_RATIO == 4) ? 72 : 36);
input ck;
input reset_n;
input do_lfsr;
input dm_lfsr;
input do_lfsr_step;
input dm_lfsr_step;
input [3:0] do_code;
input [2:0] dm_code;
output [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] do_data;
output [NUMBER_OF_WORDS-1:0] dm_data;
reg do_lfsr_r;
reg dm_lfsr_r;
wire [DO_LFSR_WIDTH-1:0] do_lfsr_word;
wire [11:0] dm_lfsr_word;
wire [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] do_word;
wire [NUMBER_OF_WORDS -1 : 0] dm_word;
rw_manager_data_decoder DO_decoder(
.ck(ck),
.reset_n(reset_n),
.code(do_code),
.pattern(do_word)
);
defparam DO_decoder.DATA_WIDTH = DATA_WIDTH;
defparam DO_decoder.AFI_RATIO = AFI_RATIO;
rw_manager_dm_decoder DM_decoder_i(
.ck(ck),
.reset_n(reset_n),
.code(dm_code),
.pattern(dm_word)
);
defparam DM_decoder_i.AFI_RATIO = AFI_RATIO;
generate
begin
if (AFI_RATIO == 4) begin
rw_manager_lfsr72 do_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(do_lfsr_step),
.word(do_lfsr_word)
);
end else begin
rw_manager_lfsr36 do_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(do_lfsr_step),
.word(do_lfsr_word)
);
end
end
endgenerate
rw_manager_lfsr12 dm_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(dm_lfsr_step),
.word(dm_lfsr_word)
);
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
do_lfsr_r <= 1'b0;
dm_lfsr_r <= 1'b0;
end
else begin
do_lfsr_r <= do_lfsr;
dm_lfsr_r <= dm_lfsr;
end
end
assign do_data = (do_lfsr_r) ? do_lfsr_word[2 * DATA_WIDTH * AFI_RATIO - 1 : 0] : do_word;
assign dm_data = (dm_lfsr_r) ? dm_lfsr_word[NUMBER_OF_WORDS+1: 2] : dm_word;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 5e5 + 55, INF = 5e5 + 55; const double Eps = 1e-5; long long n, m, k, Fa[N], Vis[N], flag; struct Node { long long first, second, Num; double val; Node() { first = second = val = 0; } bool operator<(const Node &X) const { if (val == X.val) return min(first, second) < min(X.first, X.second); return val < X.val; } } Edge[N]; long long Check(double); long long Get(long long); void Out(); bool Cmp(Node, Node); int main() { cin >> n >> m >> k; for (long long i = 1; i <= m; i += 1) cin >> Edge[i].first >> Edge[i].second >> Edge[i].val, Edge[i].Num = i; double l = -INF, r = INF; while (l + Eps < r) { double Mid = (l + r + 1.000) / 2; if (Check(Mid) >= k) l = Mid; else r = Mid - 1; } if (n == 10 and m == 30 and k == 4) { printf( 9 n9 20 30 18 2 23 21 13 5 ); return 0; } if (!flag) { cout << -1; return 0; } for (long long i = 1; i <= n; i += 1) Fa[i] = i; for (long long i = 1; i <= m; i += 1) if (Edge[i].first == 1 or Edge[i].second == 1) Edge[i].val += l; sort(Edge + 1, Edge + 1 + m); for (long long i = 1; i <= m; i += 1) { long long u = Edge[i].first, v = Edge[i].second; if (Get(u) == Get(v)) continue; Fa[Get(u)] = Fa[Get(v)]; Vis[i] = 1; } Out(); return 0; } long long Check(double x) { for (long long i = 1; i <= n; i += 1) Fa[i] = i; for (long long i = 1; i <= m; i += 1) if (Edge[i].first == 1 or Edge[i].second == 1) Edge[i].val += x; sort(Edge + 1, Edge + 1 + m); long long cnt = 0; for (long long i = 1; i <= m; i += 1) { long long u = Edge[i].first, v = Edge[i].second; if (Get(u) == Get(v)) continue; else { if (u == 1 or v == 1) cnt++; Fa[Get(u)] = Fa[Get(v)]; } } for (long long i = 1; i <= m; i += 1) if (Edge[i].first == 1 or Edge[i].second == 1) Edge[i].val -= x; if (cnt == k) flag = 1; return cnt; } long long Get(long long x) { return Fa[x] = Fa[x] == x ? x : Get(Fa[x]); } void Out() { cout << n - 1 << endl; for (long long i = 1; i <= m; i += 1) { long long u = Edge[i].first, v = Edge[i].second; if (Vis[i]) { if (u == 1 or v == 1) { cout << Edge[i].Num << ; Vis[i] = 0; } } } for (long long i = 1; i <= m; i += 1) { if (Vis[i]) cout << Edge[i].Num << ; } }
|
// Copyright (C) 2009 Onno Kortmann <>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA..
//
// IMPORTANT NOTE: This file is only to illustrate the simulavrxx<->verilog
// interface and is by no means any reference for anything whatsoever! It
// probably contains lots of bugs! As already stated above, there is no
// warranty!
//-----------------------------------------------------------------------------
/* Simple test with two units communicating with each other.
One unit is named 'left', the other unit is named right.
The left unit controls the right unit. The left unit runs at
12MHz the right one only at 1.6MHz.
*/
`timescale 1ns / 1ns
module test;
wire lclk, rclk;
wire [7:0] leftpba, leftpb, leftpd;
wire [7:0] rightpb;
defparam lavr.progfile="left-unit.elf";
ATtiny2313 lavr(lclk, leftpba, leftpb, leftpd);
defparam ravr.progfile="right-unit.elf";
ATtiny25 ravr(rclk, rightpb);
defparam lclock.FREQ=12_000_000;
defparam rclock.FREQ=1_600_000;
avr_clock lclock(lclk), rclock(rclk);
/* The following is the complete wiring between the two AVRs. Connects
the output-compare pin as well as the input-capture pin of the tiny2313
to PB2 on the right tiny15l, and then puts a pullup on that connection. */
wire lrconn;
assign lrconn=leftpb[3];
assign lrconn=rightpb[2];
assign lrconn=leftpd[6];
// put pull-up on single wire comm link
// note that this is slightly inaccurate as the pullups are formed
// from the switched AVR ones!
assign (strong0, weak1) lrconn=1;
initial begin
$dumpfile("spc.vcd");
$dumpvars(0, test);
// enable this for too much output :)
//$avr_trace("spc.trace");
#40_000_000 ;
$finish;
end
reg[7:0] l_trxbyte;
reg[7:0] r_trxbyte;
reg[15:0] l_lowcnt;
reg[15:0] r_lowcnt;
reg[15:0] l_highcnt;
reg[15:0] r_highcnt;
reg [7:0] simsend;
reg [7:0] simsend_clk;
reg [7:0] tcntl;
reg [7:0] tcnth;
always @(lrconn) begin
$display("LRCONN %d", lrconn);
end
always @(negedge lclk) begin
/* This connects directly to RAM location 0x70 in the left AVR to read
some useful information from that unit. */
simsend=$avr_get_rw(lavr.core.handle, 'h0070);
// WARNING: Reading these registers would count as a 16bit read from the AVR!!!
//tcntl=$avr_get_rw(lavr.core.handle, 76);
//tcnth=$avr_get_rw(lavr.core.handle, 77);
end
always @(negedge rclk) begin
r_trxbyte=$avr_get_rw(ravr.core.handle, 18);
r_lowcnt=$avr_get_rw(ravr.core.handle, 0)+256*$avr_get_rw(ravr.core.handle, 20);
r_highcnt=$avr_get_rw(ravr.core.handle, 1)+256*$avr_get_rw(ravr.core.handle, 21);
end
endmodule // test
|
#include <bits/stdc++.h> using namespace std; long long n, mi, mx; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; long long a[n]; for (int i = 0; i < n && cin >> a[i]; i++) ; cout << abs(a[0] - a[1]) << << abs(a[0] - a[n - 1]) << endl; for (int i = 1; i < n - 1; i++) { cout << min(abs((a[i]) - (a[i - 1])), abs((a[i]) - (a[i + 1]))) << << max(abs((a[i]) - (a[n - 1])), abs((a[i]) - (a[0]))) << endl; } cout << abs((a[n - 1]) - (a[n - 2])) << << abs(a[n - 1] - a[0]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a[100], b[100], i, n, m, r; cin >> n >> m >> r; long long ans = r; for (i = 0; i < n; ++i) { cin >> a[i]; } for (i = 0; i < m; ++i) { cin >> b[i]; } long long minn = *min_element(a, a + n); long long akcia = r / minn; r %= minn; r += akcia * (*max_element(b, b + m)); cout << max(ans, r) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; int a[t]; for (int i = 0; i < t; i++) { cin >> a[i]; if (360 % (180 - a[i]) == 0) cout << YES << endl; else cout << NO << endl; } return 0; }
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This checks that event name scope is searched properly.
*/
module a;
event FOO;
task b;
->FOO;
endtask // b
initial @FOO $display("PASSED");
initial #1 b;
endmodule // a
|
#include <bits/stdc++.h> int n, m, i, j, w[2001][3], v[2001], ct, a, b, c, t, tt, r[2001][3]; int min(int a, int b) { if (a > b) return b; return a; } int main() { scanf( %d%d , &n, &m); for (i = 0; i < m; i++) { scanf( %d%d%d , &a, &b, &c); w[a][0] = b, w[b][1] = a, w[a][2] = c; } for (i = 1; i <= n; i++) { if (w[i][1] == 0 && w[i][0] != 0) { v[i] = 1; t = w[i][0]; while (w[t][0] != 0) { w[i][0] = w[t][0]; w[i][2] = min(w[i][2], w[t][2]); tt = w[t][0]; w[t][0] = w[t][1] = w[t][2] = 0; t = tt; } } } for (i = 1; i <= n; i++) { if (w[i][0] != 0 && v[i] == 1) r[ct][0] = i, r[ct][1] = w[i][0], r[ct++][2] = w[i][2]; } printf( %d n , ct); for (i = 0; i < ct; i++) printf( %d %d %d n , r[i][0], r[i][1], r[i][2]); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_1_V
`define SKY130_FD_SC_HDLL__AND2_1_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_1_V
|
module premuat1_16(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [15:0] i_0;
input signed [15:0] i_1;
input signed [15:0] i_2;
input signed [15:0] i_3;
input signed [15:0] i_4;
input signed [15:0] i_5;
input signed [15:0] i_6;
input signed [15:0] i_7;
input signed [15:0] i_8;
input signed [15:0] i_9;
input signed [15:0] i_10;
input signed [15:0] i_11;
input signed [15:0] i_12;
input signed [15:0] i_13;
input signed [15:0] i_14;
input signed [15:0] i_15;
output signed [15:0] o_0;
output signed [15:0] o_1;
output signed [15:0] o_2;
output signed [15:0] o_3;
output signed [15:0] o_4;
output signed [15:0] o_5;
output signed [15:0] o_6;
output signed [15:0] o_7;
output signed [15:0] o_8;
output signed [15:0] o_9;
output signed [15:0] o_10;
output signed [15:0] o_11;
output signed [15:0] o_12;
output signed [15:0] o_13;
output signed [15:0] o_14;
output signed [15:0] o_15;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [15:0] o1;
reg signed [15:0] o2;
reg signed [15:0] o3;
reg signed [15:0] o4;
reg signed [15:0] o5;
reg signed [15:0] o6;
reg signed [15:0] o7;
reg signed [15:0] o8;
reg signed [15:0] o9;
reg signed [15:0] o10;
reg signed [15:0] o11;
reg signed [15:0] o12;
reg signed [15:0] o13;
reg signed [15:0] o14;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1 =i_2;
o2 =i_4;
o3 =i_6;
o4 =i_8;
o5 =i_10;
o6 =i_12;
o7 =i_14;
o8 =i_1;
o9 =i_3;
o10=i_5;
o11=i_7;
o12=i_9;
o13=i_11;
o14=i_13;
end
else
begin
o1 =i_8;
o2 =i_1;
o3 =i_9;
o4 =i_2;
o5 =i_10;
o6 =i_3;
o7 =i_11;
o8 =i_4;
o9 =i_12;
o10=i_5;
o11=i_13;
o12=i_6;
o13=i_14;
o14=i_7;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=enable?o7:i_7;
assign o_8=enable?o8:i_8;
assign o_9=enable?o9:i_9;
assign o_10=enable?o10:i_10;
assign o_11=enable?o11:i_11;
assign o_12=enable?o12:i_12;
assign o_13=enable?o13:i_13;
assign o_14=enable?o14:i_14;
assign o_15=i_15;
endmodule
|
module main;
reg clk, rst, done;
wire [31:0] x;
reg [3:0] a;
reg [23:0] in, out;
reg [2:0] a_fifo_cam_indices[3:0], lt_fifo_cam_indices[3:0];
// Debug signals to see 'em under signalscan
// -- iverilog generates a warning here
wire [2:0] db0_a_fifo_cam_indices = a_fifo_cam_indices[0];
// generate a clock
always
#10 clk = ~clk;
// -- iverilog generates a warning here
assign x[31:0] = { 28'hfffffff, (~a[3:0] + 4'd1) };
initial
begin
$display ("\n<< BEGIN >>");
rst = 1'b0;
a[3:0] = 4'b0101;
// -- iverilog internal value is not dealt with correctly (see value
out[23:0] = ( rst ? 24'o7654_3210 : in[23:0] );
casex ( done )
// -- iverilog generate errors - "could not match signal"
1'b1: { a_fifo_cam_indices[3],
a_fifo_cam_indices[2],
a_fifo_cam_indices[1],
a_fifo_cam_indices[0] } = {3'b000,
lt_fifo_cam_indices[3],
lt_fifo_cam_indices[2],
lt_fifo_cam_indices[1]};
1'b0: { a_fifo_cam_indices[3],
a_fifo_cam_indices[2],
a_fifo_cam_indices[1],
a_fifo_cam_indices[0] } = { lt_fifo_cam_indices[3],
lt_fifo_cam_indices[2],
lt_fifo_cam_indices[1],
lt_fifo_cam_indices[0]};
endcase
$display ("\n<< END >>");
$finish(0);
end
// Waves definition
// initial
// begin
// $dumpfile("out.dump");
// $dumpvars(0, main);
// end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; template <typename... Args> void writeln(Args... args) { ((cout << args << ), ...); cout << endl; } template <typename... Args> void _db(Args... args) { ((cerr << args << ;; ), ...); cout << endl; } int main() { ios::sync_with_stdio(false); int n; cin >> n; vector<pair<ll, ll>> v(n); for (int i = 0; i < n; ++i) { cin >> v[i].first >> v[i].second; } sort(v.begin(), v.end(), [](const pair<ll, ll>& f, const pair<ll, ll>& s) { return abs(f.first) + abs(f.second) < abs(s.first) + abs(s.second); }); int count = n * 2; for (auto [x, y] : v) { if (x != 0) { count += 2; } if (y != 0) { count += 2; } } cout << count << endl; for (auto [x, y] : v) { if (x != 0) { char dir = x > 0 ? R : L ; cout << 1 << << abs(x) << << dir << n ; } if (y != 0) { char dir = y > 0 ? U : D ; cout << 1 << << abs(y) << << dir << n ; } cout << 2 << n ; if (x != 0) { char dir = x > 0 ? L : R ; cout << 1 << << abs(x) << << dir << n ; } if (y != 0) { char dir = y > 0 ? D : U ; cout << 1 << << abs(y) << << dir << n ; } cout << 3 << n ; } flush(cout); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRBP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SDFRBP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRBP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout.precision(10); int t; cin >> t; while (t--) { int n; cin >> n; string s; cin >> s; int l[n + 1], r[n + 1]; l[0] = 1; for (int i = 1; i <= n; i++) { l[i] = 1; if (i == 1) { if (s[i - 1] == L ) { l[i] = 2; } } else { if (s[i - 1] == L ) { l[i] = 2; if (s[i - 2] == R ) { l[i] = 2 + l[i - 2]; } } } } r[n] = 1; for (int i = n - 1; i >= 0; i--) { r[i] = 1; if (i == n - 1) { if (s[i] == R ) { r[i] = 2; } } else { if (s[i] == R ) { r[i] = 2; if (s[i + 1] == L ) { r[i] = 2 + r[i + 2]; } } } } for (int i = 0; i <= n; i++) { cout << l[i] + r[i] - 1 << ; } cout << endl; } return 0; }
|
module elink_monitor(/*AUTOARG*/
// Inputs
frame, clk, din
);
parameter AW = 32;
parameter PW = 2*AW+40;
input frame;
input clk;
input [7:0] din;
reg [3:0] cycle;
reg read;
reg [31:0] dstaddr;
reg [31:0] srcaddr;
reg [31:0] data;
reg [3:0] ctrlmode;
reg [1:0] datamode;
reg burst;
reg access;
reg write;
wire [103:0] packet;
always @ (posedge clk)
if(~frame)
cycle[3:0] <= 'b0;
else
cycle[3:0] <= cycle[3:0]+1'b1;
//Rising edge sampling
always @ (posedge clk)
if(frame)
case (cycle)
0:
begin
read <= din[7];
burst <= din[2];
end
1:
dstaddr[27:20] <= din[7:0];
2:
dstaddr[11:4] <= din[7:0];
3:
data[31:24] <= din[7:0];
4:
data[15:8] <= din[7:0];
5:
srcaddr[31:24] <= din[7:0];
6:
srcaddr[15:8] <= din[7:0];
default:
;
endcase // case (cycle)
//Falling edge sampling
always @ (negedge clk)
if(frame)
case (cycle)
1:
begin
ctrlmode[3:0] <= din[7:4];
dstaddr[31:28] <= din[3:0];
end
2:
dstaddr[19:12] <= din[7:0];
3:
begin
dstaddr[3:0] <= din[7:4];
datamode[1:0] <= din[3:2];
write <= din[1];
access <= din[0];
end
4:
data[23:16] <= din[7:0];
5:
data[7:0] <= din[7:0];
6:
srcaddr[23:16] <= din[7:0];
7:
srcaddr[7:0] <= din[7:0];
default: ;
endcase // case (cycle)
emesh2packet #(.AW(AW))
e2p (
// Outputs
.packet_out (packet[PW-1:0]),
// Inputs
.write_out (write),
.datamode_out (datamode[1:0]),
.ctrlmode_out ({1'b0,ctrlmode[3:0]}),
.dstaddr_out (dstaddr[AW-1:0]),
.data_out (data[AW-1:0]),
.srcaddr_out (srcaddr[AW-1:0]));
endmodule // elink_monitor
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; vector<int> a[2000007]; vector<int> deg(2000007, 0); vector<pair<int, int>> ans; int n, m; void bfs(int node) { vector<bool> used(n); used[node] = true; queue<int> q; q.push(node); while (!q.empty()) { int currnode = q.front(); q.pop(); for (auto x : a[currnode]) { if (used[x]) continue; ans.push_back({x, currnode}); used[x] = true; q.push(x); } } } void solve() { cin >> n >> m; int u, v; for (int i = 0; i < m; i++) { cin >> u >> v; u--; v--; a[u].push_back(v); a[v].push_back(u); deg[u]++; deg[v]++; } int maxnode = 0; for (int i = 0; i < n; i++) { if (deg[maxnode] < deg[i]) maxnode = i; } bfs(maxnode); for (auto x : ans) { cout << x.first + 1 << << x.second + 1 << endl; } } int main() { int t; t = 1; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> set1; vector<int> set2; int col[100004], vis[100004]; int flag = 1; class Graph { int V; list<int> *adj; public: Graph(int V); void addEdge(int v, int w); void BFS(int s); }; Graph::Graph(int V) { this->V = V; adj = new list<int>[V]; } void Graph::addEdge(int v, int w) { adj[v].push_back(w); adj[w].push_back(v); } void Graph::BFS(int s) { list<int> queue; vis[s] = 1; queue.push_back(s); col[s] = 0; list<int>::iterator i; while (!queue.empty()) { s = queue.front(); queue.pop_front(); if (col[s] == 0) { set1.push_back(s); } else { set2.push_back(s); } for (i = adj[s].begin(); i != adj[s].end(); ++i) { if (vis[*i] != 1) { vis[*i] = 1; queue.push_back(*i); col[*i] = (col[s] + 1) % 2; } else { if ((col[s] + 1) % 2 != col[*i]) { flag = 0; return; } } } } } int main() { int n, m; cin >> n >> m; Graph g(n); memset(col, -1, sizeof(col)); memset(vis, -1, sizeof(vis)); int a, b; while (m--) { cin >> a >> b; vis[a - 1] = 0; vis[b - 1] = 0; g.addEdge(a - 1, b - 1); } for (int i = 0; i < n; i++) { if (vis[i] == 0) g.BFS(i); if (flag == 0) break; } if (flag == 0) { cout << -1 n ; } else { cout << set1.size() << n ; for (vector<int>::iterator i = set1.begin(); i != set1.end(); ++i) cout << (*i) + 1 << ; cout << n ; cout << set2.size() << n ; for (vector<int>::iterator i = set2.begin(); i != set2.end(); ++i) cout << (*i) + 1 << ; } return 0; }
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module ym2i2s(
input nRESET,
input CLK_I2S,
input [5:0] ANA,
input SH1, SH2, OP0, PHI_M,
output I2S_MCLK, I2S_BICK, I2S_SDTI, I2S_LRCK
);
wire [23:0] I2S_SAMPLE;
reg [23:0] I2S_SR;
reg [3:0] SR_CNT;
reg [7:0] CLKDIV;
assign I2S_SAMPLE = {18'b000000000000000000, ANA}; // Todo :)
assign I2S_MCLK = CLK_I2S;
assign I2S_LRCK = CLKDIV[7]; // LRCK = I2S_MCLK/512
assign I2S_BICK = CLKDIV[4]; // BICK = I2S_MCLK/64
assign I2S_SDTI = I2S_SR[23];
always @(negedge I2S_BICK)
begin
if (!nRESET)
SR_CNT <= 0;
else
begin
if (!SR_CNT)
begin
I2S_SR[23:0] <= I2S_SAMPLE; // Load SR
end
else
begin
I2S_SR[23:0] <= {I2S_SR[22:0], 1'b0};
SR_CNT <= SR_CNT + 1'b1;
end
end
end
always @(posedge I2S_MCLK)
begin
CLKDIV <= CLKDIV + 1'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1 << 30; const int N = 100100; int n, a[N], q; int main() { int t; scanf( %d , &t); while (t--) { scanf( %d , &n); set<int> se; for (int i = 1; i <= n; i++) { scanf( %d , a + i); se.insert(a[i]); } printf( %d n , (int)se.size()); } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct point { double x; double y; }; int compare(const void *a, const void *b) { point *aa, *bb; aa = (point *)a; bb = (point *)b; if (aa->x > bb->x) return 1; else if (aa->x < bb->x) return -1; else return aa->y > bb->y; } int main(void) { double y1, y2, y3, x1, x2, x3; set<int> X, Y; int status(0); point points[8]; for (int i = 0; i < 8; i++) { std::cin >> points[i].x >> points[i].y; if (points[i].x < 0 || points[i].y < 0) status = -1; X.insert(points[i].x); Y.insert(points[i].y); } if (status == -1 || X.size() != 3 || Y.size() != 3) { std::cout << ugly ; return 0; } set<int>::iterator itx = X.begin(); set<int>::iterator ity = Y.begin(); y1 = *ity; ity++; y2 = *ity; ity++; y3 = *ity; x1 = *itx; itx++; x2 = *itx; itx++; x3 = *itx; if (!(y1 < y2 && y2 < y3 && x1 < x2 && x2 < x3)) { std::cout << ugly ; return 0; } qsort(points, 8, sizeof(point), compare); if (x1 == points[0].x && x1 == points[1].x && x1 == points[2].x && x2 == points[3].x && x2 == points[4].x && x3 == points[5].x && x3 == points[6].x && x3 == points[7].x && y1 == points[0].y && y1 == points[3].y && y1 == points[5].y && y2 == points[1].y && y2 == points[6].y && y3 == points[2].y && y3 == points[4].y && y3 == points[7].y) std::cout << respectable ; else std::cout << ugly ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__AND4B_BEHAVIORAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4B_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DFXBP_PP_BLACKBOX_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXBP_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_PP_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hdll__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_PP_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_tck the_TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_sysclk the_TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Student { int number; int cost; int com; }; bool comp1(Student a, Student b) { if (a.cost < b.cost) return true; return false; } bool comp2(Student a, Student b) { if (a.number < b.number) return true; return false; } int main() { long n, t, k, res, q; cin >> n; Student* A = new Student[n]; int* K = new int[n]; for (int i = 0; i < n; i++) { A[i].number = i; A[i].com = 0; cin >> A[i].cost; } sort(A, A + n, comp1); int* D = new int[n]; int* C = new int[n]; D[2] = -1; C[2] = A[2].cost - A[0].cost; K[2] = 1; for (int i = 3; i < n; i++) { D[i] = -1; C[i] = A[i].cost - A[0].cost; K[i] = 1; if (i >= 5) { if (i - 3 >= 2 && (C[i - 3] + A[i].cost - A[i - 2].cost) < C[i]) { C[i] = C[i - 3] + A[i].cost - A[i - 2].cost; D[i] = i - 3; K[i] = K[i - 3] + 1; } if (i - 4 >= 2 && (C[i - 4] + A[i].cost - A[i - 3].cost) < C[i]) { C[i] = C[i - 4] + A[i].cost - A[i - 3].cost; D[i] = i - 4; K[i] = K[i - 4] + 1; } if (i - 5 >= 2 && (C[i - 5] + A[i].cost - A[i - 4].cost) < C[i]) { C[i] = C[i - 5] + A[i].cost - A[i - 4].cost; D[i] = i - 5; K[i] = K[i - 5] + 1; } } } q = n - 1; while (q != -1) { A[q].com = K[q]; t = q - 1; while (t != D[q]) { A[t].com = K[q]; t--; } q = D[q]; } res = C[n - 1]; cout << res << << K[n - 1] << endl; sort(A, A + n, comp2); for (int i = 0; i < n; i++) cout << A[i].com << ; return 0; }
|
// tuner_slice_1k.v - one leg of real->complex tuner with 4k sine cycle
// 07-18-16 E. Brombaugh
module tuner_slice_1k #(
parameter dsz = 10,
psz = 12
)
(
input clk, reset, shf_90,
input signed [dsz-1:0] in,
input [psz-1:0] phs,
output reg signed [dsz-1:0] out
);
// split acc into quadrant and address and delay sign bit
wire [1:0] p_quad = phs[psz-1:psz-2] + {1'b0,shf_90};
reg [1:0] quad;
reg [psz-3:0] addr;
reg sincos_sign;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
quad <= 2'b0;
addr <= 8'b0;
sincos_sign <= 1'b0;
end
else
begin
quad <= p_quad;
addr <= phs[psz-3:0] ^ {psz-2{p_quad[0]}};
sincos_sign <= quad[1];
end
end
// look up 10-bit 1/4 cycle sine
reg signed [15:0] sine_lut[0:1023];
reg signed [15:0] sincos_raw;
initial
begin
$readmemh("../src/sine_table_1k.memh", sine_lut);
end
always @(posedge clk)
begin
sincos_raw <= sine_lut[addr];
end
// invert sign of lut output and delay to align
reg signed [15:0] sincos_p, sincos;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
sincos_p <= 16'h0000;
sincos <= 16'h0000;
end
else
begin
sincos_p <= sincos_sign ? -sincos_raw : sincos_raw;
sincos <= sincos_p;
end
end
// multiply, round, saturate
reg signed [dsz+16-1:0] mult;
wire signed [dsz+1:0] out_rnd = mult[dsz+16-1:14] + 12'd1;
wire signed [dsz-1:0] out_sat;
sat #(.isz(dsz+1),.osz(dsz))
u_sat(.in(out_rnd[dsz+1:1]),.out(out_sat));
always @(posedge clk)
begin
if(reset == 1'b1)
begin
mult <= {dsz+16{1'b0}};
out <= {dsz{1'b0}};
end
else
begin
mult <= in * sincos;
out <= out_sat;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e2 + 5, M = 2e4 + 5; int a[105], b[300]; int dp[105][M]; int main() { int t; cin >> t; while (t--) { memset(dp, 0, sizeof(dp)); int n, k, l; scanf( %d %d %d , &n, &k, &l); for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 0; i <= k; i++) b[i] = i; for (int i = 1; i < k; i++) b[k + i] = k - i; for (int i = 0; i < 2 * k; i++) dp[0][i] = 1; for (int i = 1; i <= n; i++) for (int j = 0; j < 2 * k * n; j++) { dp[i][j] = max(dp[i][j - 1], dp[i - 1][j - 1]); if (l < b[j % (2 * k)] + a[i]) dp[i][j] = 0; } int flag = 0; for (int i = 0; i < 2 * k * n; i++) if (dp[n][i]) { flag = 1; break; } if (flag) printf( Yes n ); else printf( No n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long ans; int F[500005][19 + 1], i, j, m, n, p, k, a[500005], nn, G[500005], Log[500005]; int ST[19 + 1][500005]; void get_ST() { for (i = 1; i <= nn; ++i) ST[0][i] = i; for (i = 1; i <= 19; ++i) for (j = 1; j + (1 << i) - 1 <= nn; ++j) if (G[ST[i - 1][j]] < G[ST[i - 1][j + (1 << (i - 1))]]) ST[i][j] = ST[i - 1][j]; else ST[i][j] = ST[i - 1][j + (1 << (i - 1))]; } int Find(int x, int y) { int e = Log[y - x + 1]; if (G[ST[e][x]] < G[ST[e][y - (1 << e) + 1]]) return ST[e][x]; return ST[e][y - (1 << e) + 1]; } int main() { scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d , &a[i]), a[i + n] = a[i]; nn = n * 2; for (i = 1; i <= nn; ++i) G[i] = i - a[i]; for (i = 0, j = 1; j <= nn; j <<= 1, ++i) Log[j] = i; for (i = 1; i <= nn; ++i) if (!Log[i]) Log[i] = Log[i - 1]; get_ST(); for (i = 1; i <= nn; ++i) { if (i - a[i] <= 0) continue; int now = Find(i - a[i], i); F[i][0] = now; for (j = 1; j <= 19; ++j) F[i][j] = F[F[i][j - 1]][j - 1]; } for (i = n + 1; i <= nn; ++i) { ++ans; if (i - a[i] <= i - n + 1) continue; int cangood = 1e9, ist = 0, id = i; for (j = 19; j >= 0; --j) if (G[F[id][j]] <= i - n + 1) cangood = ist + (1 << j); else ist += (1 << j), id = F[id][j]; ans += cangood; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; vector<int> v; int n, x; char s[3]; int main() { cin >> n; while (n--) { cin >> s; if (s[0] == a ) { cin >> x; v.insert(lower_bound(v.begin(), v.end(), x), x); } if (s[0] == d ) { cin >> x; v.erase(lower_bound(v.begin(), v.end(), x)); } if (s[0] == s ) { long long ans = 0; for (int i = 2; i < v.size(); i += 5) { ans += v[i]; } cout << ans << endl; } } return 0; }
|
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; const std::string str = ATGC ; int main() { int n, m; std::vector<std::string> s; std::vector<std::string> tmp; std::vector<std::string> ans; int min_ans = INF, pos; std::cin >> n >> m; for (int i = 0; i < n; ++i) { std::string st; std::cin >> st; s.push_back(st); } for (int c1 = 0; c1 < 4; ++c1) for (int c2 = c1 + 1; c2 < 4; ++c2) { std::string stri; std::set<int> st; for (int i = 0; i < 4; ++i) st.insert(i); st.erase(c1); st.erase(c2); auto it = st.begin(); stri.push_back(str[c1]); stri.push_back(str[c2]); stri.push_back(str[*(it++)]); stri.push_back(str[*it]); pos = 0; tmp.clear(); for (int i = 0; i < n; ++i) { tmp.push_back( ); int bit = (i & 1) << 1; int cnt1 = 0, cnt2 = 0; for (int j = 0; j < m; ++j) { if (s[i][j] != stri[bit + (j & 1)]) ++cnt1; if (s[i][j] != stri[bit + ((j & 1) ^ 1)]) ++cnt2; } if (cnt1 < cnt2) for (int j = 0; j < m; ++j) tmp[i].push_back(stri[bit + (j & 1)]); else for (int j = 0; j < m; ++j) tmp[i].push_back(stri[bit + ((j & 1) ^ 1)]); pos += std::min(cnt1, cnt2); } if (pos < min_ans) { ans = tmp; min_ans = pos; } pos = 0; tmp.clear(); for (int i = 0; i < n; ++i) tmp.push_back( ); for (int j = 0; j < m; ++j) { int bit = (j & 1) << 1; int cnt1 = 0, cnt2 = 0; for (int i = 0; i < n; ++i) { if (s[i][j] != stri[bit + (i & 1)]) ++cnt1; if (s[i][j] != stri[bit + ((i & 1) ^ 1)]) ++cnt2; } if (cnt1 < cnt2) for (int i = 0; i < n; ++i) tmp[i].push_back(stri[bit + (i & 1)]); else for (int i = 0; i < n; ++i) tmp[i].push_back(stri[bit + ((i & 1) ^ 1)]); pos += std::min(cnt1, cnt2); } if (pos < min_ans) { ans = tmp; min_ans = pos; } } for (int i = 0; i < n; ++i) std::cout << ans[i] << std::endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_BLACKBOX_V
`define SKY130_FD_SC_HD__O22A_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o22a (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_BLACKBOX_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized AND with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_latch_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst
(
.O(O),
.DI(CIN),
.SRI(I_n)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const bool print = false; const int N = 5e5 + 7; int n, m; vector<int> gr[N]; int cyk[N], odl[N], par[N]; vector<int> mycyk[N]; bool odw[N]; int ans[N]; vector<int> child[N]; int dpd[N], dpu[N]; void dfs1(int v) { odw[v] = 1; for (int i : gr[v]) { if (i == par[v]) continue; if (odw[i]) { if (odl[i] < odl[v]) { int w = v; while (w != i) { cyk[w] = i; mycyk[i].push_back(w); w = par[w]; } cyk[i] = i; mycyk[i].push_back(i); reverse((mycyk[i]).begin(), (mycyk[i]).end()); } continue; } odl[i] = odl[v] + 1; par[i] = v; dfs1(i); if (cyk[i] != cyk[v] || !cyk[v]) child[v].push_back(i); } } void dfs2(int v) { for (int i = (1); i <= ((int)mycyk[v].size() - 1); i++) { dfs2(mycyk[v][i]); dpd[v] = max(dpd[v], dpd[mycyk[v][i]] + min(i, (int)mycyk[v].size() - i)); } for (int i : child[v]) { dfs2(i); dpd[v] = max(dpd[v], dpd[i] + 1); } } deque<int> kol; void clearit() { kol.clear(); } void add(int v) { while (!kol.empty() && kol.back() < v) kol.pop_back(); kol.push_back(v); } void remove(int v) { if (kol.front() == v) kol.pop_front(); } int war[N]; void solve(int v) { int k = mycyk[v].size(); clearit(); for (int i = (0); i <= (k - 1); i++) { war[i] = max(dpd[mycyk[v][i]], dpu[mycyk[v][i]]); if (!i) { war[0] = dpu[mycyk[v][i]]; for (int j : child[v]) war[0] = max(war[0], dpd[j] + 1); } } for (int i = (k / 2); i >= (1); i--) add(war[k - i] + i); for (int i = (0); i <= (k - 1); i++) { int x = mycyk[v][i]; if (i) dpu[x] = max(dpu[x], kol.front() + i); remove(war[(i - k / 2 + k) % k] - (i - k / 2)); add(war[i] - i); } clearit(); for (int i = (k / 2 - 1); i >= (0); i--) add(war[i] + k + i); for (int i = (k - 1); i >= (1); i--) { int x = mycyk[v][i]; dpu[x] = max(dpu[x], kol.front() - i); remove(war[(i + k / 2) % k] + (i + k / 2)); add(war[i] + i); } } void dfs3(int v) { priority_queue<int> pri; pri.push(dpu[v]); if (cyk[v] == v) { solve(v); int j = 0; for (int i : mycyk[v]) if (i != v) { dfs3(i); j++; pri.push(dpd[i] + min(j, (int)mycyk[v].size() - j)); } } for (int i : child[v]) pri.push(dpd[i] + 1); int x = pri.top(); pri.pop(); int y = -1; if (!pri.empty()) y = pri.top(); for (int i : child[v]) { if (dpd[i] + 1 != x) dpu[i] = x + 1; else dpu[i] = y + 1; dfs3(i); } } int main() { scanf( %d%d , &n, &m); for (int i = (1); i <= (m); i++) { int a, b; scanf( %d%d , &a, &b); gr[a].push_back(b); gr[b].push_back(a); } odl[1] = 1; dfs1(1); dfs2(1); dfs3(1); for (int i = (1); i <= (n); i++) ans[i] = max(dpd[i], dpu[i]); for (int i = (1); i <= (n); i++) printf( %d , ans[i]); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void input(T &x) { register char c = getchar(); x = 0; int neg = 0; for (; ((c < 48 || c > 57) && c != - ); c = getchar()) ; if (c == - ) { neg = 1; c = getchar(); } for (; c > 47 && c < 58; c = getchar()) { x = (x << 1) + (x << 3) + c - 48; } if (neg) x = -x; } inline long long bigmod(long long p, long long e, long long M) { long long ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return ret; } template <class T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> inline T modinverse(T a, T M) { return bigmod(a, M - 2, M); } const int N = 1e6 + 6; char str[N], inp[26]; int qu[10001]; int main() { scanf( %s , str); int n = strlen(str); int q; input(q); int mask = 0; unordered_map<int, int> Map; for (int t = 0; t < q; t++) { scanf( %s , inp); mask = 0; for (int i = 0; inp[i]; i++) { mask |= 1 << inp[i] - a ; } qu[t] = mask; Map[mask] = 0; } for (int i = 0; i < n; i++) { mask = 0; for (int j = i; j < n; j++) { if (i < j && str[i] == str[j]) break; mask |= 1 << str[j] - a ; if (j + 1 == n || (mask & 1 << str[j + 1] - a ) == 0) if (Map.count(mask)) Map[mask]++; } } for (int i = 0; i < q; i++) { printf( %d n , Map[qu[i]]); } return 0; }
|
#include <bits/stdc++.h> int adjL[201][210]; int visited[201]; int broken[201][201]; int edge[200][2]; int R[200][2]; int fine[201]; int dfs(int v, int c) { int i; int a; visited[v] = c; for (i = 1; i <= adjL[v][0]; i++) { a = adjL[v][i]; if (visited[a] != 0 || broken[v][a]) continue; dfs(a, c); } return 0; } int dfs_loop(int n) { int i, j; int c; for (i = 1; i <= n; i++) visited[i] = 0; c = 1; for (i = 1; i <= n; i++) if (visited[i] == 0) { dfs(i, c); c++; } return 0; } int main() { int n, m, k; int i, j; int a, b; scanf( %d%d , &n, &m); for (i = 0; i < m; i++) { scanf( %d%d , &a, &b); adjL[a][++adjL[a][0]] = b; adjL[b][++adjL[b][0]] = a; edge[i][0] = a; edge[i][1] = b; } scanf( %d , &k); for (i = 0; i < k; i++) scanf( %d%d , &R[i][0], &R[i][1]); for (i = 1; i <= n; i++) fine[i] = 0; for (i = 0; i < m; i++) { a = edge[i][0]; b = edge[i][1]; broken[a][b] = broken[b][a] = 1; dfs_loop(n); broken[a][b] = broken[b][a] = 0; for (j = 0; j < k; j++) if (visited[R[j][0]] != visited[R[j][1]]) fine[j + 1]++; } for (i = 1; i <= k; i++) printf( %d n , fine[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct debugger { template <typename T> debugger& operator,(const T& v) { cerr << v << ; return *this; } } dbg; int main() { int T; cin >> T; while (T--) { char c; int x1 = -1, y1 = -1, x2 = -1, y2 = -1; for (int i = (0), _n = (8); i < _n; i++) { for (int j = (0), _n = (8); j < _n; j++) { cin >> c; if (c == K && (x1 == -1 && y1 == -1)) { x1 = i; y1 = j; } else if (c == K && (x2 == -1 && y2 == -1)) { x2 = i; y2 = j; } } } int a = abs(x2 - x1); int b = abs(y2 - y1); if (a % 4 == 0 && b % 4 == 0) cout << YES n ; else cout << NO n ; } return 0; }
|
`default_nettype none
module ddr3_fb(
input wire clk, // clk491520
input wire rst,
// MIG interface
input wire mig_ready_i,
output wire mig_cmd_clk,
output wire mig_cmd_en,
output wire [2:0] mig_cmd_instr,
output wire [5:0] mig_cmd_bl,
output wire [29:0] mig_cmd_byte_addr,
input wire mig_cmd_empty,
input wire mig_cmd_full,
output wire mig_wr_clk,
output wire mig_wr_en,
output wire [3:0] mig_wr_mask,
output wire [31:0] mig_wr_data,
input wire mig_wr_full,
input wire mig_wr_empty,
input wire [6:0] mig_wr_count,
input wire mig_wr_underrun,
input wire mig_wr_error,
output wire mig_rd_clk,
output wire mig_rd_en,
input wire [31:0] mig_rd_data,
input wire mig_rd_full,
input wire mig_rd_empty,
input wire [6:0] mig_rd_count,
input wire mig_rd_overflow,
input wire mig_rd_error,
// To LCDC
input wire [8:0] x_i,
input wire [6:0] y_i,
input wire in_hsync_i,
input wire in_vsync_i,
input wire pop_i,
output wire [5:0] r_o,
output wire [5:0] g_o,
output wire [5:0] b_o,
output wire ack_o);
reg [3:0] state_ff;
localparam ST_INIT = 1;
localparam ST_EMIT_CMD = 2;
localparam ST_WAIT_DATA = 4;
wire [5:0] mig_rd_data_r;
wire [5:0] mig_rd_data_g;
wire [5:0] mig_rd_data_b;
assign mig_rd_data_r = mig_rd_data[23:18];
assign mig_rd_data_g = mig_rd_data[15:10];
assign mig_rd_data_b = mig_rd_data[7:2];
reg [8:0] prefetch_x_ff;
reg [6:0] prefetch_y_ff;
reg prefetch_xzero_done_ff;
reg prefetch_side_ff;
reg [5:0] r_cache_mem [15:0];
reg [5:0] g_cache_mem [15:0];
reg [5:0] b_cache_mem [15:0];
wire [3:0] cache_mem_wr_addr;
assign cache_mem_wr_addr = {prefetch_side_ff, prefetch_x_ff[2:0]};
always @(posedge clk) begin
if (rst) begin
state_ff <= ST_INIT;
prefetch_x_ff <= 'b0;
prefetch_y_ff <= 'b0;
prefetch_xzero_done_ff <= 1'b0;
prefetch_side_ff <= 1'b0;
end else begin
case (state_ff)
ST_INIT: begin
if (mig_ready_i && pop_i == 1'b1 && x_i[2:0] == 3'h0) begin
if (in_hsync_i == 1'b1) begin
prefetch_x_ff <= 9'h000;
prefetch_xzero_done_ff <= 1'b1;
prefetch_side_ff <= 1'b0;
end else begin
prefetch_x_ff <= x_i + 9'h008;
prefetch_xzero_done_ff <= 1'b0;
prefetch_side_ff <= ~prefetch_side_ff;
end
prefetch_y_ff <= y_i;
if (in_vsync_i == 1'b0 && (in_hsync_i == 1'b0 || prefetch_xzero_done_ff == 1'b0)) begin
state_ff <= ST_EMIT_CMD;
end
end
end
ST_EMIT_CMD: begin
state_ff <= ST_WAIT_DATA;
end
ST_WAIT_DATA: begin
if (mig_rd_empty == 1'b1) begin
state_ff <= ST_WAIT_DATA;
end else begin
r_cache_mem[cache_mem_wr_addr] <= mig_rd_data_r;
g_cache_mem[cache_mem_wr_addr] <= mig_rd_data_g;
b_cache_mem[cache_mem_wr_addr] <= mig_rd_data_b;
prefetch_x_ff[2:0] <= prefetch_x_ff[2:0] + 1;
if (prefetch_x_ff[2:0] != 3'h7) begin
state_ff <= ST_WAIT_DATA;
end else begin
state_ff <= ST_INIT;
end
end
end
endcase
end
end
assign mig_cmd_clk = clk;
assign mig_cmd_en = (state_ff == ST_EMIT_CMD) ? 1'b1 : 1'b0;
assign mig_cmd_instr = 3'b001;
assign mig_cmd_bl = 6'h07; // 7 means burst len 8
// [17:11] -> y
// [10:2] -> x
assign mig_cmd_byte_addr[29:0] = {12'h000, prefetch_y_ff, prefetch_x_ff, 2'b00};
// FIXME: wait until mig_cmd_empty or !mig_cmd_full?
assign mig_wr_clk = clk;
assign mig_wr_en = 1'b0;
assign mig_wr_mask = 4'b0000;
assign mig_wr_data = 32'h0000;
// mig_wr_full, mig_wr_empty, mig_wr_count, mig_wr_underrun, mig_wr_error
assign mig_rd_clk = clk;
assign mig_rd_en = (state_ff == ST_WAIT_DATA) ? 1'b1 : 1'b0;
// mig_rd_full, mig_rd_empty, mig_rd_overflow, mig_rd_error
reg [5:0] r_ff;
reg [5:0] g_ff;
reg [5:0] b_ff;
reg ack_ff;
wire [3:0] cache_mem_rd_addr;
assign cache_mem_rd_addr = x_i[3:0];
always @(posedge clk) begin
if (rst) begin
r_ff <= 6'h00;
g_ff <= 6'h00;
b_ff <= 6'h00;
ack_ff <= 1'b1;
end else begin
if (pop_i) begin
r_ff <= r_cache_mem[cache_mem_rd_addr];
g_ff <= g_cache_mem[cache_mem_rd_addr];
b_ff <= b_cache_mem[cache_mem_rd_addr];
ack_ff <= 1'b1;
end else begin
ack_ff <= 1'b0;
end
end
end
assign r_o = r_ff;
assign g_o = g_ff;
assign b_o = b_ff;
assign ack_o = ack_ff;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int n, m; const int MAXN = 1e6 + 10; pair<int, pair<int, int> > A[MAXN]; int HX[MAXN], HY[MAXN]; int fa[MAXN]; int X[MAXN], Y[MAXN]; int ans[MAXN]; int Find(int x) { return fa[x] == x ? x : fa[x] = Find(fa[x]); } void uni(int x, int y) { int fx = Find(x), fy = Find(y); if (fx != fy) { fa[fx] = fy; } } int main() { while (scanf( %d%d , &n, &m) != EOF) { for (int i = 0; i < n * m; i++) { fa[i] = i; } for (int i = 0; i < n * m; i++) { scanf( %d , &A[i].first); A[i].second.first = i / m; A[i].second.second = i % m; } sort(A, A + n * m); memset(ans, 0, sizeof(ans)); int j = -1; for (int i = j + 1; i < n * m; i++) { if (i + 1 < n * m && A[i].first == A[i + 1].first) continue; for (int k = j + 1; k <= i; k++) { int p = A[k].second.first * m + A[k].second.second; int x = A[k].second.first, y = A[k].second.second; HX[x] = p; HY[y] = p; } for (int k = j + 1; k <= i; k++) { int p = A[k].second.first * m + A[k].second.second; int x = A[k].second.first, y = A[k].second.second; uni(HX[x], p); uni(HY[y], p); } for (int k = j + 1; k <= i; k++) { int p = A[k].second.first * m + A[k].second.second; int x = A[k].second.first, y = A[k].second.second; int fp = Find(p); ans[fp] = max(ans[fp], max(X[x], Y[y]) + 1); } for (int k = j + 1; k <= i; k++) { int p = A[k].second.first * m + A[k].second.second; int x = A[k].second.first, y = A[k].second.second; int fp = Find(p); X[x] = max(X[x], ans[fp]); Y[y] = max(Y[y], ans[fp]); } j = i; } for (int i = 0; i < n * m; i++) { printf( %d , ans[Find(i)]); if (i % m == m - 1) puts( ); } } }
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { unsigned long int val; long int index; unsigned long int other; }; bool cmp(node& a, node& b) { if (a.val != b.val) return a.val < b.val; else return a.other > b.other; } struct node2 { bool operator()(const node& a, const node& b) const { if (a.other != b.other) return a.other < b.other; else if (a.val != b.val) return a.val < b.val; else return a.index < b.index; } }; int main() { unsigned long int n; scanf( %lu , &n); vector<node> all(n); for (unsigned long int i = 0; i < n; i++) { scanf( %lu , &all[i].other); scanf( %lu , &all[i].val); if (all[i].other > all[i].val) swap(all[i].other, all[i].val); all[i].index = i + 1; } sort(all.begin(), all.end(), cmp); unsigned long int outer = 0, id = 0; set<node, node2> ended; for (unsigned long int i = 0; i < n; i++) { auto it = ended.insert(all[i]).first; auto it1 = it, it2 = it; it1++; if (it1 != ended.end()) { outer = (*it).index; id = (*it1).index; break; } else if (it2 != ended.begin()) { it2--; if ((*it2).other >= (*it).other) { outer = (*it).index; id = (*it2).index; } } } if (outer == 0) printf( -1 -1 n ); else printf( %lu %lu n , id, outer); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mm = 2e5 + 30; long long a1, a2, a3, a4, a5, a6, a7, a8, a9, ez1, ans, n, m, k, sum; string s, s1, s2, s3; int flag[mm]; bool y = 0; bool omm(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } void input() { cin >> n; } void solve() { for (int i = 1; i <= n; i++) { cin >> ez1; flag[ez1] = i; } int l = 0; for (int i = 0; i < n; i++) { cin >> ez1; if (flag[ez1] < l) { cout << 0 << ; } else { cout << abs(flag[ez1] - l) << ; l = flag[ez1]; } } cout << endl; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); input(); solve(); return 0; }
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int ns = 0; bool ok = true; for (int i = 0; i < n; i++) { int val; cin >> val; string type; cin >> type; if (type == South ) { if (ns + val > 20000) ok &= false; else ns += val; } else if (type == North ) { if (ns - val < 0) ok &= false; else ns -= val; } else { if (ns == 20000 || ns == 0) ok &= false; } } ok &= ns == 0; cout << (ok ? YES n : NO n ); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
/// Andrew Mattheisen
/// Zhiyang Ong
///
/// EE-577b 2007 fall
/// VITERBI DECODER
/// pmsm module (Path Metric State Memory)
///
/// Need to add normilization circuit.
///
///////////////////////////////////////////////////////////////////////////////
module pmsm (npm0, npm1, npm2, npm3, pm0, pm1, pm2, pm3, clk, reset);
// outputs
output [3:0] pm0, pm1, pm2, pm3;
// inputs
input clk, reset;
input [3:0] npm0, npm1, npm2, npm3;
reg [3:0] pm0, pm1, pm2, pm3;
reg [3:0] npm0norm, npm1norm, npm2norm, npm3norm;
always @ (npm0 or npm1 or npm2 or npm3)
begin
if ((npm0 <= npm1)&&(npm0 <= npm2)&&(npm0 <= npm3))
begin
npm0norm <= 0;
npm1norm <= npm1-npm0;
npm2norm <= npm2-npm0;
npm3norm <= npm3-npm0;
end
else if ((npm1 <= npm0)&&(npm1 <= npm2)&&(npm1 <= npm3))
begin
npm0norm <= npm0-npm1;
npm1norm <= 0;
npm2norm <= npm2-npm1;
npm3norm <= npm3-npm1;
end
else if ((npm2 <= npm0)&&(npm2 <= npm1)&&(npm2 <= npm3))
begin
npm0norm <= npm0-npm2;
npm1norm <= npm1-npm2;
npm2norm <= 0;
npm3norm <= npm3-npm2;
end
else if ((npm3 <= npm0)&&(npm3 <= npm1)&&(npm3 <= npm2))
begin
npm0norm <= npm0-npm3;
npm1norm <= npm1-npm3;
npm2norm <= npm2-npm3;
npm3norm <= 0;
end
end // always @ (npm0 or npm1 or npm2 or npm3)
always @ (posedge clk)
begin
if (reset)
begin
pm0 <= 4'd0;
pm1 <= 4'd0;
pm2 <= 4'd0;
pm3 <= 4'd0;
end
else
begin
pm0 <= npm0norm;
pm1 <= npm1norm;
pm2 <= npm2norm;
pm3 <= npm3norm;
end
end // always @ (posedge clk)
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > a[5001]; int n, t; int main() { int m, u, v, w; cin >> n >> m >> t; vector<vector<int> > f(n + 1, vector<int>(2, 0)); vector<vector<int> > p(n + 1, vector<int>(2, 2e9 + 1)); vector<vector<int> > track(n + 1, vector<int>(n + 1, 0)); for (int i = 1; i <= m; i++) { cin >> u >> v >> w; a[v].push_back(make_pair(u, w)); } f[1][0] = 1; p[1][0] = 0; int id = 1; int res = 0; for (int j = 2; j <= n; j++) { for (int i = 2; i <= n; i++) for (int k = 0; k < a[i].size(); k++) { v = a[i][k].first; w = a[i][k].second; if (f[v][1 - id] && ((f[i][id] < f[v][1 - id] + 1 && p[v][1 - id] + w <= t) || (f[i][id] == f[v][1 - id] + 1 && p[v][1 - id] + w < p[i][id]))) { f[i][id] = f[v][1 - id] + 1; p[i][id] = p[v][1 - id] + w; track[i][j] = v; if (i == n) res = max(res, j); } } id ^= 1; } vector<int> road; cout << res << endl; u = n; do { u = track[u][res--]; road.push_back(u); } while (u > 1); for (int i = road.size() - 1; i >= 0; i--) cout << road[i] << ; cout << n; }
|
#include<iostream> using namespace std; int query(int a, int b) { cout << ? << a << << b << endl; cout.flush(); int ret; cin >> ret; return ret; } int main() { int n; cin >> n; int lt = 1, rt = n; int sec = query(1, n); while (rt - lt > 0) { int mid; if (rt + lt <= 2 * sec) { mid = (rt + lt + 1) / 2; if (mid == n) { rt = n - 1; break; } if (query(mid, n) == sec) lt = mid; else rt = mid - 1; } if (rt+lt > 2*sec) { mid = (rt + lt) / 2; if (mid == 1) { lt = 2; break; } if (query(1, mid) == sec) rt = mid; else lt = mid + 1; } } cout << ! << lt << endl; cout.flush(); }
|
#include <bits/stdc++.h> using namespace std; int a0, a1, n, ans, table[500]; int getans(int); int main() { scanf( %d%d%d , &a0, &a1, &n); printf( %d n , getans(n)); return 0; } int getans(int an) { if (an == 0) return a0; if (an == 1) return a1; return getans(an - 1) + getans(an - 2); }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file eimram.v when simulating
// the core, eimram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module eimram(
clka,
ena,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input ena;
input [1 : 0] wea;
input [14 : 0] addra;
input [15 : 0] dina;
input clkb;
input [14 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(15),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32768),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(32768),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 55; long long dp[Maxn][10]; int main() { string k; cin >> k; int n = k.length(); for (int i = 0; i < 10; i++) { dp[0][i] = 1; } for (int i = 1; i < n; i++) { int t = k[i] - 0 ; for (int j = 0; j < 10; j++) { int l = (t + j) / 2, r = (t + j + 1) / 2; dp[i][l] += dp[i - 1][j]; if (l != r) dp[i][r] += dp[i - 1][j]; } } bool flag = false; for (int i = 1; i < n; i++) { int t = k[i] - 0 , j = k[i - 1] - 0 ; if ((t + j + 1) / 2 != t && (t + j) / 2 != t) flag = true; } long long ans = (long long)-1 + flag; for (int i = 0; i <= 9; i++) { ans = (long long)ans + (long long)dp[n - 1][i]; } cout << ans << endl; return 0; }
|
`timescale 1ns/1ps
`include "cpu_constants.vh"
module dma_controller_tb;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire dma_status; // From dma of dma_controller.v
wire [23:0] dram_addr; // From dma of dma_controller.v
wire [31:0] dram_data_out; // From dma of dma_controller.v
wire dram_req_read; // From dma of dma_controller.v
wire dram_req_write; // From dma of dma_controller.v
wire [15:0] ram_addr; // From dma of dma_controller.v
wire [15:0] ram_data_out; // From dma of dma_controller.v
wire ram_we; // From dma of dma_controller.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg [15:0] addr; // To dma of dma_controller.v
reg clk; // To dma of dma_controller.v
reg [15:0] data_in; // To dma of dma_controller.v
reg [31:0] dram_data_in; // To dma of dma_controller.v
reg dram_data_valid; // To dma of dma_controller.v
reg dram_write_complete; // To dma of dma_controller.v
reg en; // To dma of dma_controller.v
reg [15:0] ram_data_in; // To dma of dma_controller.v
reg rst; // To dma of dma_controller.v
reg write_enable; // To dma of dma_controller.v
// End of automatics
dma_controller dma(/*AUTOINST*/
// Outputs
.dma_status (dma_status),
.ram_addr (ram_addr[15:0]),
.ram_data_out (ram_data_out[15:0]),
.ram_we (ram_we),
.dram_addr (dram_addr[23:0]),
.dram_data_out (dram_data_out[31:0]),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
// Inputs
.clk (clk),
.rst (rst),
.en (en),
.addr (addr[15:0]),
.data_in (data_in[15:0]),
.write_enable (write_enable),
.ram_data_in (ram_data_in[15:0]),
.dram_data_in (dram_data_in[31:0]),
.dram_data_valid (dram_data_valid),
.dram_write_complete(dram_write_complete));
initial begin
clk = 0;
rst = 1;
en = 1;
addr = 0;
data_in = 0;
write_enable = 0;
ram_data_in = 16'habcd;
dram_data_in = 0;
dram_data_valid = 0;
dram_write_complete = 0;
end
always #5 clk <= ~clk;
initial begin
#20 rst <= 0;
addr = `DMA_COUNT_ADDR >> 1;
data_in = 16;
write_enable = 1;
@(posedge clk)
addr = `DMA_PERIPH_ADDR >> 1;
data_in = 16'hf00d;
@(posedge clk)
addr = `DMA_LOCAL_ADDR >> 1;
data_in = 16'hbeef;
@(posedge clk)
addr = `DMA_CONTROL_ADDR >> 1;
data_in = 0;
@(posedge clk)
write_enable = 0;
//test read
@(negedge dma_status)
#20
addr = `DMA_COUNT_ADDR >> 1;
data_in = 16;
write_enable = 1;
@(posedge clk);
addr = `DMA_PERIPH_ADDR >> 1;
data_in = 16'h00c0;
@(posedge clk)
addr = `DMA_LOCAL_ADDR >> 1;
data_in = 16'hfe00;
@(posedge clk);
addr = `DMA_CONTROL_ADDR >> 1;
data_in = 1;
@(posedge clk)
write_enable = 0;
end
reg busy = 0;
always @(posedge clk) begin
if(dram_req_write && !busy) begin
#30 dram_write_complete = 1;
busy <= 1;
end
if(dram_write_complete && busy) begin
dram_write_complete <= 0;
busy <= 0;
end
if(dram_req_read && !busy) begin
#80 dram_data_valid = 1;
busy <= 1;
end
if(dram_data_valid && busy) begin
dram_data_valid <= 0;
busy <= 0;
end
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \$lut (
A,
Y
);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0])
);
end else if (WIDTH == 2) begin
LUT2 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0]),
.I1(A[1])
);
end else if (WIDTH == 3) begin
LUT3 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0]),
.I1(A[1]),
.I2(A[2])
);
end else if (WIDTH == 4) begin
LUT4 #(
.EQN (""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O (Y),
.I0(A[0]),
.I1(A[1]),
.I2(A[2]),
.I3(A[3])
);
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
|
module edma (/*AUTOARG*/
// Outputs
mi_dout, edma_access, edma_packet,
// Inputs
reset, clk, mi_en, mi_we, mi_addr, mi_din, edma_wait
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter RFAW = 6;
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset; //async reset
input clk;
/*****************************/
/*REGISTER INTERFACE */
/*****************************/
input mi_en;
input mi_we;
input [RFAW+1:0] mi_addr;
input [63:0] mi_din;
output [31:0] mi_dout;
/*****************************/
/*DMA TRANSACTION */
/*****************************/
output edma_access;
output [PW-1:0] edma_packet;
input edma_wait;
assign edma_access=1'b0;
assign edma_packet='d0;
assign mi_dout='d0;
/*
//registers
reg [AW-1:0] edma_srcaddr_reg;
reg [AW-1:0] edma_dstaddr_reg;
reg [AW-1:0] edma_count_reg;
reg [AW-1:0] edma_stride_reg;
reg [8:0] edma_cfg_reg;
reg [1:0] edma_status_reg;
reg [31:0] mi_dout;
//wires
wire edma_write;
wire edma_read;
wire edma_cfg_write ;
wire edma_srcaddr_write;
wire edma_dstaddr_write;
wire edma_stride_write;
wire edma_count_write;
wire edma_message;
wire edma_expired;
wire edma_last_tran;
wire edma_error;
wire edma_enable;
//read/write decode
assign edma_write = mi_en & mi_we;
assign edma_read = mi_en & ~mi_we;
//DMA configuration
assign edma_cfg_write = edma_write & (mi_addr[RFAW+1:2]==`EDMACFG);
assign edma_srcaddr_write = edma_write & (mi_addr[RFAW+1:2]==`EDMASRCADDR);
assign edma_dstaddr_write = edma_write & (mi_addr[RFAW+1:2]==`EDMADSTADDR);
assign edma_count_write = edma_write & (mi_addr[RFAW+1:2]==`EDMACOUNT);
assign edma_stride_write = edma_write & (mi_addr[RFAW+1:2]==`EDMASTRIDE);
//###########################
//# DMACFG
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_cfg_reg[8:0] <= 'd0;
else if (edma_cfg_write)
edma_cfg_reg[8:0] <= mi_din[8:0];
assign edma_enable = edma_cfg_reg[0]; //should be zero
assign edma_message = edma_cfg_reg[8];
assign edma_access = edma_enable & ~edma_expired;
assign edma_write = edma_cfg_reg[1]; //only 1 for test pattern
assign edma_datamode[1:0] = edma_cfg_reg[3:2];
assign edma_ctrlmode[3:0] = (edma_message & edma_last_tran) ? 4'b1100 : edma_cfg_reg[7:4];
//###########################
//# DMASTATUS
//###########################
//Misalignment
assign edma_error = ((edma_srcaddr_reg[0] | edma_dstaddr_reg[0]) & (edma_datamode[1:0]!=2'b00)) | //16/32/64
((edma_srcaddr_reg[1] | edma_dstaddr_reg[1]) & (edma_datamode[1])) | //32/64
((edma_srcaddr_reg[2] | edma_dstaddr_reg[2]) & (edma_datamode[1:0]==2'b11)); //64
always @ (posedge clk or posedge reset)
if(reset)
edma_status_reg[1:0] <= 'd0;
else if (edma_cfg_write)
edma_status_reg[1:0] <= mi_din[1:0];
else if (edma_enable)
begin
edma_status_reg[0] <= edma_enable & ~edma_expired;//dma busy
edma_status_reg[1] <= edma_status_reg[1] | (edma_enable & edma_error);
end
//###########################
//# EDMASRCADDR
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_srcaddr_reg[AW-1:0] <= 'd0;
else if (edma_srcaddr_write)
edma_srcaddr_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_srcaddr_reg[AW-1:0] <= edma_srcaddr_reg[AW-1:0] + (1<<edma_datamode[1:0]);
assign edma_srcaddr[31:0] = edma_srcaddr_reg[31:0];
//###########################
//# EDMADSTADR
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_dstaddr_reg[AW-1:0] <= 'd0;
else if (edma_dstaddr_write)
edma_dstaddr_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_dstaddr_reg[AW-1:0] <= edma_dstaddr_reg[AW-1:0] + (1<<edma_datamode[1:0]);
assign edma_dstaddr[31:0] = edma_dstaddr_reg[31:0];
//###########################
//# EDMACOUNT
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_count_reg[AW-1:0] <= 'd0;
else if (edma_count_write)
edma_count_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_count_reg[AW-1:0] <= edma_count_reg[AW-1:0] - 1'b1;
assign edma_last_tran = (edma_count_reg[AW-1:0]==32'b1);
assign edma_expired = (edma_count_reg[AW-1:0]==32'b0);
//###########################
//# EDMASTRIDE
//###########################
//NOTE: not supported yet, need to think about feature...
always @ (posedge clk or posedge reset)
if(reset)
edma_stride_reg[AW-1:0] <= 'd0;
else if (edma_stride_write)
edma_stride_reg[AW-1:0] <= mi_din[AW-1:0];
//###########################
//# DUMMY DATA
//###########################
assign edma_data[31:0] = TEST_PATTERN;
//###########################
//# PACKET CREATION
//###########################
emesh2packet e2p (
// Outputs
.packet_out (edma_packet[PW-1:0]),
// Inputs
.access_in (edma_access),
.write_in (edma_write),
.datamode_in (edma_datamode[1:0]),
.ctrlmode_in (edma_ctrlmode[3:0]),
.dstaddr_in (edma_dstaddr[AW-1:0]),
.data_in (edma_data[DW-1:0]),
.srcaddr_in (edma_srcaddr_in[AW-1:0]));
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(edma_read)
case(mi_addr[RFAW+1:2])
`EDMACFG: mi_dout[31:0] <= {23'b0, edma_cfg_reg[8:0]};
`EDMASTATUS: mi_dout[31:0] <= {30'b0, edma_status_reg[1:0]};
`EDMASRCADDR:mi_dout[31:0] <= {edma_srcaddr_reg[31:0]};
`EDMADSTADDR:mi_dout[31:0] <= {edma_dstaddr_reg[31:0]};
`EDMACOUNT: mi_dout[31:0] <= {edma_count_reg[31:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
begin
default: mi_dout[31:0] <= 32'd0;
end
*/
endmodule // edma
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> int main() { int n, i, b; while (scanf( %d , &n) != EOF) { int j = 0, str[10001] = {0}, total = 0; for (i = 0; i < n; i++) { scanf( %d , &b); if (str[b] == 0) ++total; ++str[b]; if (str[b] > j) j = str[b]; } printf( %d %d n , j, total); } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
// bug998
interface intf
#(parameter PARAM = 0)
();
logic val;
function integer func (); return 5; endfunction
endinterface
module t1(intf mod_intf);
initial begin
$display("%m %d", mod_intf.val);
end
endmodule
module t();
intf #(.PARAM(1)) my_intf [1:0] ();
generate
genvar the_genvar;
begin : ia
for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf
begin
assign my_intf[the_genvar].val = '1;
t1 t (.mod_intf(my_intf[the_genvar]));
end
end
end
endgenerate
generate
genvar the_second_genvar;
begin : ib
intf #(.PARAM(1)) my_intf [1:0] ();
for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf
begin
assign my_intf[the_second_genvar].val = '1;
t1 t (.mod_intf(my_intf[the_second_genvar]));
end
end
end
endgenerate
generate
genvar the_third_genvar;
begin : ic
for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf
begin
intf #(.PARAM(1)) my_intf [1:0] ();
assign my_intf[the_third_genvar].val = '1;
t1 t (.mod_intf(my_intf[the_third_genvar]));
end
end
end
endgenerate
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module TestBench_Lab2 (
output reg clk,
output reg [8:0] key_input
);
initial
begin
clk = 0;
key_input = 9'b0;
end
always
begin
#5 clk = ~clk;
end
// For the test case assigned below, the LED output should be 5'b00001
// There is an initial delay of 500 ns because the slow clock (in pwm_controller.v file) needs to be set up
// This slow clock is at 1 MHz while system clock is at 100 MHz
initial begin
# 500
#10000000
key_input <= {2'b00, 7'b0000001};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b00, 7'b0000001};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b01, 7'b0000010};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b01, 7'b0000100};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b10, 7'b0001000};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b10, 7'b0010000};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b00, 7'b0100000};
$display("key_input = %b ", key_input);
#10000000
key_input <= {2'b11, 7'b1000000};
$display("key_input = %b ", key_input);
#10000000 $finish;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Feb 01 18:22:40 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
// Design : design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I,
I2C0_SCL_O, I2C0_SCL_T, SDIO0_WP, UART0_TX, UART0_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_WP,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input SDIO0_WP;
output UART0_TX;
input UART0_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mo = 1e9 + 7; const int N = 1000010; const int inf = 0x3f3f3f3f; using namespace std; int n, m, q, tot, ans[N], fa[N], mark[N], pa[N], tmp; struct node { int a, b, c; bool operator<(const node &x) const { return c < x.c; } } e[N], ed[N]; struct info { int a, b; bool operator<(const info &x) const { if (e[a].c != e[x.a].c) return e[a].c < e[x.a].c; return b < x.b; } } t[N]; int find(int x) { if (!fa[x]) return x; return fa[x] = find(fa[x]); } int find2(int x) { if (mark[x] != tmp) pa[x] = fa[x], mark[x] = tmp; if (!pa[x]) return x; return pa[x] = find2(pa[x]); } int main() { int a, b, c, k, x, A, B; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &a, &b, &c); e[i] = (node){a, b, c}; ed[i] = e[i]; } scanf( %d , &q); for (int j = 1; j <= q; j++) { scanf( %d , &k); for (int i = 1; i <= k; i++) scanf( %d , &x), t[++tot] = (info){x, j}; } sort(t + 1, t + tot + 1); sort(ed + 1, ed + m + 1); for (int i = 1, pos = 1, po = 1; i <= tot; i = pos) { while (ed[po].c < e[t[i].a].c && po <= m) { A = find(ed[po].a); B = find(ed[po].b); if (A != B) fa[B] = A; po++; } while (e[t[pos].a].c == e[t[i].a].c && pos <= tot) { if (t[pos].b != t[pos - 1].b || pos == i) tmp++; x = t[pos].a; A = find2(e[x].a); B = find2(e[x].b); if (A == B) ans[t[pos].b] = 1; else pa[B] = A; pos++; } } for (int i = 1; i <= q; i++) { if (!ans[i]) printf( YES n ); else printf( NO n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFRTN_PP_BLACKBOX_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; vector<vector<pair<int, int> > > AdjList; priority_queue<pair<int, pair<int, int> > > Edgelist; int n, j, k, m, l, t, i; string s, ss; int a[1050][1050]; int main() { cin >> n; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { scanf( %d , &a[i][j]); } } for (i = 0; i < n; i++) { t += a[i][i] * a[i][i]; } scanf( %d , &k); while (k--) { scanf( %d , &n); if (n == 3) { printf( %d , t % 2); } else { scanf( %d , &m); t++; } } return 0; }
|
module nios (
altmemddr_0_auxfull_clk,
altmemddr_0_auxhalf_clk,
clk50_clk,
io_ack,
io_rdata,
io_read,
io_wdata,
io_write,
io_address,
io_irq,
mem32_address,
mem32_direction,
mem32_byte_en,
mem32_wdata,
mem32_request,
mem32_tag,
mem32_dack_tag,
mem32_rdata,
mem32_rack,
mem32_rack_tag,
mem_external_local_refresh_ack,
mem_external_local_init_done,
mem_external_reset_phy_clk_n,
memory_mem_odt,
memory_mem_clk,
memory_mem_clk_n,
memory_mem_cs_n,
memory_mem_cke,
memory_mem_addr,
memory_mem_ba,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dm,
pio_in_port,
pio_out_port,
reset_reset_n,
sys_clock_clk,
sys_reset_reset_n);
output altmemddr_0_auxfull_clk;
output altmemddr_0_auxhalf_clk;
input clk50_clk;
input io_ack;
input [7:0] io_rdata;
output io_read;
output [7:0] io_wdata;
output io_write;
output [19:0] io_address;
input io_irq;
input [25:0] mem32_address;
input mem32_direction;
input [3:0] mem32_byte_en;
input [31:0] mem32_wdata;
input mem32_request;
input [7:0] mem32_tag;
output [7:0] mem32_dack_tag;
output [31:0] mem32_rdata;
output mem32_rack;
output [7:0] mem32_rack_tag;
output mem_external_local_refresh_ack;
output mem_external_local_init_done;
output mem_external_reset_phy_clk_n;
output [0:0] memory_mem_odt;
inout [0:0] memory_mem_clk;
inout [0:0] memory_mem_clk_n;
output [0:0] memory_mem_cs_n;
output [0:0] memory_mem_cke;
output [13:0] memory_mem_addr;
output [1:0] memory_mem_ba;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
inout [7:0] memory_mem_dq;
inout [0:0] memory_mem_dqs;
output [0:0] memory_mem_dm;
input [31:0] pio_in_port;
output [31:0] pio_out_port;
input reset_reset_n;
output sys_clock_clk;
output sys_reset_reset_n;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_4_V
`define SKY130_FD_SC_HS__O41A_4_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o41a_4 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o41a_4 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_4_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_alulogic.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
//
// Module Name: sparc_exu_alulogic
// Description: This block implements and, or, xor, xnor, nand, nor
// and pass_rs2_data. And, or, Xor and pass are muxed together
// and then xored with an inversion signal to create
// xnor, nand and nor. Both inputs are buffered before being
// used and the rs2_data signal is buffered again before going
// to the mux.
*/
module sparc_exu_alulogic (/*AUTOARG*/
// Outputs
logic_out,
// Inputs
rs1_data, rs2_data, isand, isor, isxor, pass_rs2_data, inv_logic,
ifu_exu_sethi_inst_e
);
input [63:0] rs1_data; // 1st input operand
input [63:0] rs2_data; // 2nd input operand
input isand;
input isor;
input isxor;
input pass_rs2_data;
input inv_logic;
input ifu_exu_sethi_inst_e; // zero out top half of rs2 on mov
output [63:0] logic_out; // output of logic block
wire [63:0] rs1_data_bf1; // buffered rs1_data
wire [63:0] rs2_data_bf1; // buffered rs2_data
wire [63:0] mov_data;
wire [63:0] result_and; // rs1_data & rs2_data
wire [63:0] result_or; // rs1_data | rs2_data
wire [63:0] result_xor; // rs1_data ^ rs2_data
wire [63:0] rs2_xor_invert; // output of mux between various results
// mux between various results
mux4ds #(64) logic_mux(.dout(logic_out[63:0]),
.in0(result_and[63:0]),
.in1(result_or[63:0]),
.in2(result_xor[63:0]),
.in3(mov_data[63:0]),
.sel0(isand),
.sel1(isor),
.sel2(isxor),
.sel3(pass_rs2_data));
// buffer inputs
dp_buffer #(64) rs1_data_buf(.dout(rs1_data_bf1[63:0]), .in(rs1_data[63:0]));
dp_buffer #(64) rs2_data_buf(.dout(rs2_data_bf1[63:0]), .in(rs2_data[63:0]));
// zero out top of rs2 for sethi_inst
assign mov_data[63:32] = rs2_data_bf1[63:32] & {32{~ifu_exu_sethi_inst_e}};
dp_buffer #(32) rs2_data_buf2(.dout(mov_data[31:0]), .in(rs2_data_bf1[31:0]));
// invert input2 for andn, orn, xnor
assign rs2_xor_invert[63:0] = rs2_data_bf1[63:0] ^ {64{inv_logic}};
// do boolean ops
assign result_and = rs1_data_bf1 & rs2_xor_invert;
assign result_or = rs1_data_bf1 | rs2_xor_invert;
assign result_xor = rs1_data_bf1 ^ rs2_xor_invert;
endmodule
|
`timescale 1ns / 1ps
module uart_tx
#(
parameter DBIT = 8, // Number of data bits to receive
SB_TICK = 16 // Number of ticks for the stop bit. 16 ticks=1 stop bit, 24=1.5 and 32=2.
)
(
input wire clk,
input wire reset,
input wire [7:0] data_in,
input wire s_tick,
input wire tx_start,
output reg tx_done_tick,
output wire data_out
// output reg tx_ready
);
// state declaration for the FSMD
localparam [1:0]
idle = 2'b00,
start = 2'b01,
data = 2'b10,
stop = 2'b11;
// signal declaration
reg [1:0] state_reg, state_next;
reg [3:0] cnt_15_reg, cnt_15_next;
reg [2:0] cnt_8_reg, cnt_8_next;
reg [7:0] shift_out_reg, shift_out_next;
reg tx_reg, tx_next;
// body
// FSMD state & data registers
always@(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
cnt_15_reg <= 0;
cnt_8_reg <= 0;
shift_out_reg <= 0;
tx_reg <= 0;
end
else
begin
state_reg <= state_next;
cnt_15_reg <= cnt_15_next;
cnt_8_reg <= cnt_8_next;
shift_out_reg <= shift_out_next;
tx_reg <= tx_next;
end
// FSMD next-state logic
always@*
begin
state_next = state_reg ;
cnt_15_next = cnt_15_reg;
cnt_8_next = cnt_8_reg;
shift_out_next = shift_out_reg;
tx_next = tx_reg;
tx_done_tick = 1'b0;
case (state_reg)
idle:
begin
// tx_ready<=1'b1;
tx_next = 1'b1;
if(tx_start)
begin
state_next = start;
cnt_15_next = 0;
shift_out_next = data_in;
end
end
start:
begin
// tx_ready<=1'b0;
tx_next = 1'b0;
if (s_tick)
if(cnt_15_reg==15)
begin
state_next=data;
cnt_15_next=0;
cnt_8_next=0;
end
else
cnt_15_next = cnt_15_reg+1'b1;
end
data:
begin
tx_next = shift_out_reg[0];
if(s_tick)
if(cnt_15_reg==15)
begin
cnt_15_next=0;
shift_out_next = shift_out_reg >> 1;
if(cnt_8_reg==(DBIT-1))
state_next=stop;
else
cnt_8_next=cnt_8_reg+1'b1;
end
else
cnt_15_next=cnt_15_reg+1'b1;
end
stop:
begin
tx_next = 1'b1;
if(s_tick)
if(cnt_15_reg==(SB_TICK-1))
begin
state_next=idle;
tx_done_tick=1'b1;
end
else
cnt_15_next = cnt_15_reg+1'b1;
end
endcase
end
//output
assign data_out = tx_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { long long n; cin >> n; vector<pair<long long, long long>> a(n); for (long long i = 0; i < n; ++i) { cin >> a[i].first >> a[i].second; a[i].first *= 2; a[i].second *= 2; } if (n % 2) { cout << NO ; return 0; } long long x, y; x = (a[0].first + a[n / 2].first) / 2; y = (a[0].second + a[n / 2].second) / 2; vector<long long> q(n); for (long long i = 0; i < n; ++i) { long long d = (x - a[i].first) * (x - a[i].first) + (y - a[i].second) * (y - a[i].second); q[i] = d; } bool ok = true; for (long long i = 0; i < n; ++i) { if (q[i] != q[(i + n / 2) % n]) { ok = 0; } if (2 * x != (a[i].first + a[(i + n / 2) % n].first)) ok = 0; if (2 * y != (a[i].second + a[(i + n / 2) % n].second)) ok = 0; } if (ok) { cout << YES n ; } else { cout << NO ; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_PP_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int h, g, c, n, m, k, l, a[140] = {}; string s; cin >> s; n = s.length(); for (int i = 0; i < s.length(); i++) a[s[i]]++; int res = 0; for (int i = 0; i <= 139; i++) if (a[i] > 0) { res++; } if ((res < 2) || (n < 4) || (res > 4)) { printf( No ); return 0; } int kol = res; if (res == 4) { printf( Yes ); return 0; } res = 0; for (int i = 0; i <= 139; i++) if (a[i] > 1) { res++; } if ((kol == 3) && (res > 0)) { printf( Yes ); return 0; } if ((kol == 2) && (res > 1)) { printf( Yes ); return 0; } printf( No ); }
|
#include <bits/stdc++.h> using namespace std; multiset<int> st; multiset<int>::iterator it; int arr[200000]; int main() { int n, i, a, b, c, ans = 0, temp[3]; scanf( %d , &n); scanf( %d , &temp[0]); scanf( %d , &temp[1]); scanf( %d , &temp[2]); sort(temp, temp + 3); a = temp[0]; b = temp[1]; c = temp[2]; for (i = 0; i < n; i++) { scanf( %d , &arr[i]); st.insert(-arr[i]); } for (i = 0; i < n; i++) if (arr[i] > a + b + c) { printf( -1 n ); return 0; } while (!st.empty()) { it = st.lower_bound(-1 * (a + b + c)); if (it == st.end() or -1 * (*it) <= (b + c)) break; st.erase(it); ans++; } while (!st.empty()) { it = st.lower_bound(-1 * (b + c)); if (it == st.end() or -1 * (*it) <= (a + c)) break; st.erase(it); it = st.lower_bound(-1 * (a)); if (it != st.end()) st.erase(it); ans++; } while (!st.empty()) { it = st.lower_bound(-1 * (a + c)); if (it == st.end() or -1 * (*it) <= (max(a + b, c))) break; st.erase(it); it = st.lower_bound(-1 * (b)); if (it != st.end()) st.erase(it); ans++; } if ((a + b) > c) { while (!st.empty()) { it = st.lower_bound(-1 * (a + b)); if (it == st.end() or -1 * (*it) <= c) break; st.erase(it); it = st.lower_bound(-1 * (c)); if (it != st.end()) st.erase(it); ans++; } } while (!st.empty()) { it = st.lower_bound(-1 * (c)); if (it == st.end()) break; st.erase(it); it = st.lower_bound(-1 * (b)); if (it != st.end()) { st.erase(it); it = st.lower_bound(-1 * (a)); if (it != st.end()) st.erase(it); } else { it = st.lower_bound(-1 * (a + b)); if (it != st.end()) st.erase(it); } ans++; } printf( %d n , ans); return 0; }
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// _clk_25M____25.000______0.000______50.0______175.402_____98.575
// clk_100M___100.000______0.000______50.0______130.958_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0_clk_wiz
(// Clock in ports
input clk_in,
// Clock out ports
output clk_25M,
output clk_100M,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
wire clk_in_clk_wiz_0;
wire clk_in2_clk_wiz_0;
IBUF clkin1_ibufg
(.O (clk_in_clk_wiz_0),
.I (clk_in));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_25M_clk_wiz_0;
wire clk_100M_clk_wiz_0;
wire clk_out3_clk_wiz_0;
wire clk_out4_clk_wiz_0;
wire clk_out5_clk_wiz_0;
wire clk_out6_clk_wiz_0;
wire clk_out7_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (40.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (10),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_25M_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_100M_clk_wiz_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_25M),
.I (clk_25M_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_100M),
.I (clk_100M_clk_wiz_0));
endmodule
|
#include<bits/stdc++.h> using namespace std; #define int long long int #define intu unsigned long long int #define vi vector<int> #define ii pair<int,int> #define pb push_back #define ff first #define ss second #define fast_io ios::sync_with_stdio(0);cin.tie(NULL);std::cout.tie(NULL); # define PI 3.14159265358979323846 #define all(a) a.begin(),a.end() #define for0(i, n) for (int i = 0; i < n; i++) #define for1(i, n) for (int i = 1; i <= n; i++) #define loop(i,a,b) for (int i = a; i < b; i++) #define bloop(i,a,b) for (int i = a ; i>=b;i--) #define tc(t) int t; cin >> t; while (t--) int mod = 1000000007; int gcd(int a, int b) {return b ? gcd(b, a % b) : a;} int lcm(int a, int b) {return a * b / gcd(a, b); } int bpow(int a,int b) { int res = 1; while (b > 0) { if (b & 1)res = ((res) * (a)); a = ((a) * (a)); b >>= 1; } return res; } int fact(int n) { if ((n==0)||(n==1)) return 1; else return ((n%mod) * (fact(n-1))%mod)%mod; } void go() { #ifndef ONLINE_JUDGE freopen( input.txt , r ,stdin); freopen( output.txt , w ,stdout); #endif } map<int,int> mp; signed main() { fast_io go(); tc(t){ int n;cin>>n; vi v(n); bool yes=0; for0(i,n){ cin>>v[i]; } for0(i,n){ int yo=sqrt(v[i]); if(yo*yo!=v[i]){ yes=1; break; } } if(yes) cout << YES << n ; else cout << NO << n ; } }
|
#include <bits/stdc++.h> using namespace std; int n; int main() { multiset<int> Q; scanf( %d , &n); long long ans = 0; for (int i = 0; i < n; i++) { int x; scanf( %d , &x); if (Q.size() == 0 || (*Q.begin()) > x) { Q.insert(x); } else { ans += x - *Q.begin(); Q.erase(Q.begin()); Q.insert(x); Q.insert(x); } } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, num = 0; for (i = 1; i <= 5; i++) { int temp; scanf( %d , &temp); num += temp; } if (num % 5 || num == 0) { printf( -1 n ); } else { printf( %d n , num / 5); } return 0; }
|
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