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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_dcmp_64ns_64ns_1_1
#(parameter
ID = 3,
NUM_STAGE = 1,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 1
)(
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
input wire [4:0] opcode,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Parameter----------------------
// AutoESL opcode
localparam [4:0]
AP_OEQ = 5'b00001,
AP_OGT = 5'b00010,
AP_OGE = 5'b00011,
AP_OLT = 5'b00100,
AP_OLE = 5'b00101,
AP_ONE = 5'b00110,
AP_UNO = 5'b01000;
// FPV6 opcode
localparam [7:0]
OP_EQ = 8'b00010100,
OP_GT = 8'b00100100,
OP_GE = 8'b00110100,
OP_LT = 8'b00001100,
OP_LE = 8'b00011100,
OP_NE = 8'b00101100,
OP_UO = 8'b00000100;
//------------------------Local signal-------------------
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire op_tvalid;
reg [7:0] op_tdata;
wire r_tvalid;
wire [7:0] r_tdata;
//------------------------Instantiation------------------
feedforward_ap_dcmp_0_no_dsp_64 feedforward_ap_dcmp_0_no_dsp_64_u (
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.s_axis_operation_tvalid ( op_tvalid ),
.s_axis_operation_tdata ( op_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata = din0==='bx ? 'b0 : din0;
assign b_tvalid = 1'b1;
assign b_tdata = din1==='bx ? 'b0 : din1;
assign op_tvalid = 1'b1;
assign dout = r_tdata[0];
always @(*) begin
case (opcode)
AP_OEQ : op_tdata = OP_EQ;
AP_OGT : op_tdata = OP_GT;
AP_OGE : op_tdata = OP_GE;
AP_OLT : op_tdata = OP_LT;
AP_OLE : op_tdata = OP_LE;
AP_ONE : op_tdata = OP_NE;
AP_UNO : op_tdata = OP_UO;
default : op_tdata = OP_EQ;
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << n ; err(++it, args...); } long long powMod(long long x, long long y) { long long p = 1; while (y) { if (y % 2) { p = (p * (x % ((long long)1e9 + 7))) % ((long long)1e9 + 7); } y /= 2; x = ((x % ((long long)1e9 + 7)) * (x % ((long long)1e9 + 7))) % ((long long)1e9 + 7); } return p; } long long CpowMod(long long x, long long y, long long w) { long long p = 1; while (y) { if (y % 2) { p = (p * (x % w)) % w; } y /= 2; x = ((x % w) * (x % w)) % w; } return p; } long long invMod(long long x) { return powMod(x, ((long long)1e9 + 7) - 2); } long long CinvMod(long long x, long long w) { return CpowMod(x, w - 2, w); } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long totLeaf; vector<set<long long> > edges; long long bud = -1; long long n; void removeEdge(long long x, long long y) { {}; edges[x].erase(y); } void dfs(long long node, long long par) { for (auto &it : edges[node]) { if (it != par) { dfs(it, node); } } long long cnt = 0; for (auto &it : edges[node]) { if (it == par || edges[it].count(node) == 0) { continue; } cnt++; } if (cnt) { totLeaf += cnt; bud++; removeEdge(node, par); } } void solve() { long long T; cin >> T; while (T--) { totLeaf = 0; bud = -1; cin >> n; edges = vector<set<long long> >(n + 1); for (long long i = 0; i <= n - 2; i++) { long long x, y; cin >> x >> y; edges[x].insert(y); edges[y].insert(x); } dfs(1, 0); cout << totLeaf - (bud) << n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout.precision(10); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int dx[] = {-1, 1, 0, 0, -1, -1, 1, 1}; int dy[] = {0, 0, 1, -1, -1, 1, -1, 1}; int a[500], c[500]; int main() { int t = 0, z = 0, len; int n, k = 0, m = 0, bam = 0, dan = 0, ans = 0; scanf( %d %d , &n, &m); for (int l = 1; l < n + 1; l++) { scanf( %d , &a[l]); a[l] += a[l - 1]; } for (int l = 0; l < m; l++) { int x, y; scanf( %d %d , &x, &y); c[l] = a[y] - a[x - 1]; } k = 0; sort(c, c + m); for (int l = m - 1; l > -1; l--) { k += c[l]; ans = max(ans, k); } printf( %d , ans); return 0; }
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//
// pixel.v -- last stage in display pipeline
//
module pixel(clk, pixclk, attcode,
pixel, blank, hsync_in, vsync_in, blink,
hsync, vsync, r, g, b);
input clk;
input pixclk;
input [7:0] attcode;
input pixel;
input blank;
input hsync_in;
input vsync_in;
input blink;
output reg hsync;
output reg vsync;
output reg [2:0] r;
output reg [2:0] g;
output reg [2:0] b;
wire blink_bit;
wire bg_red;
wire bg_green;
wire bg_blue;
wire inten_bit;
wire fg_red;
wire fg_green;
wire fg_blue;
wire foreground;
wire intensify;
wire red;
wire green;
wire blue;
assign blink_bit = attcode[7];
assign bg_red = attcode[6];
assign bg_green = attcode[5];
assign bg_blue = attcode[4];
assign inten_bit = attcode[3];
assign fg_red = attcode[2];
assign fg_green = attcode[1];
assign fg_blue = attcode[0];
assign foreground = pixel & ~(blink_bit & blink);
assign intensify = foreground & inten_bit;
assign red = (foreground ? fg_red : bg_red);
assign green = (foreground ? fg_green : bg_green);
assign blue = (foreground ? fg_blue : bg_blue);
always @(posedge clk) begin
if (pixclk == 1) begin
hsync <= hsync_in;
vsync <= vsync_in;
r[2] <= blank & red;
r[1] <= blank & intensify;
r[0] <= blank & red & intensify;
g[2] <= blank & green;
g[1] <= blank & intensify;
g[0] <= blank & green & intensify;
b[2] <= blank & blue;
b[1] <= blank & intensify;
b[0] <= blank & blue & intensify;
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { return !b ? a : gcd(b, a % b); } template <typename T> T lcm(T a, T b) { return a * (b / gcd(a, b)); } template <typename T> T sqr(T a) { return a * a; } template <typename T> T cube(T a) { return a * a * a; } template <typename T> inline void smin(T &a, T b) { a = a < b ? a : b; } template <typename T> inline void smax(T &a, T b) { a = a > b ? a : b; } template <typename T> inline void Int(T &n) { n = 0; int f = 1; register int ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (; isdigit(ch); ch = getchar()) n = (n << 3) + (n << 1) + ch - 0 ; n = n * f; } vector<string> split(const string &s, char c) { vector<string> v; stringstream second(s); string x; while (getline(second, x, c)) v.emplace_back(x); return move(v); } void err(vector<string>::iterator it) {} template <typename T, typename... Args> void err(vector<string>::iterator it, T a, Args... args) { cout << it->substr((*it)[0] == , it->length()) << = << a << , ; err(++it, args...); } inline int in() { int n; scanf( %d , &n); return n; } inline long long Lin() { long long n; scanf( %lld , &n); return n; } inline double Din() { double n; scanf( %lf , &n); return n; } inline int add(int a, int b, int mod) { a += b; return a >= mod ? a - mod : a; } inline int sub(int a, int b, int mod) { a -= b; return a < 0 ? a + mod : a; } inline int mul(int a, int b, int mod) { return (long long)a * b % mod; } const int N = 2e5 + 5; const int inf = (int)2e9 + 5; const long long Inf = (long long)1e18 + 5; const int mod = (int)1e9 + 7; const long long Mod = (long long)1e9 + 7; vector<int> b[N]; int solve() { int n = in(), k = in(); vector<int> a(n); for (int i = 0; i < n; i++) { a[i] = in(); } for (int i = 0; i < n; i++) { int x = a[i], cur = 0; while (x >= 1) { b[x].push_back(cur); x /= 2; cur++; } } long long ans = Inf; for (int i = 0; i <= 2e5; i++) { sort(b[i].begin(), b[i].end()); if ((int)b[i].size() >= k) { long long cur = 0; for (int j = 0; j < k; j++) { cur += b[i][j]; } smin(ans, cur); } } printf( %lld n , ans); return 0; } int main() { int test = 1, tc = 0; while (test--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-11; const int INFINITE = 0x3f3f3f3f; template <class T> inline void checkmin(T &a, T b) { if (b < a) a = b; } template <class T> inline void checkmax(T &a, T b) { if (b > a) a = b; } template <class T> inline T sqr(T x) { return x * x; } template <class T> inline T lowbit(T n) { return (n ^ (n - 1)) & n; } template <class T> inline int countbit(T n) { return (n == 0) ? 0 : (1 + countbit(n & (n - 1))); } template <class T> inline T gcd(T a, T b) { T c; while (a != 0) { c = a; a = b % a; b = c; } return b; } typedef vector<int> VI; typedef vector<VI> VII; typedef vector<string> VS; inline void solve() { int n; scanf( %d , &n); bool f = true; for (int i = 20; i >= 0; i--) { if ((n & (1 << i)) > 0) { if (f) f = false; else printf( ); printf( %d , i + 1); } } printf( n ); } int main() { ios::sync_with_stdio(false); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; const double PI = 3.141592653589793238462643383279502884197169399375105820974944; long long dist(long long a, long long b, long long c, long long d) { return abs(a - c) + abs(b - d); } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long a, b, c, d; cin >> a >> b >> c >> d; long long ans = 1000000000; for (long long i = c - 1; i <= c + 1; i++) { for (long long j = d - 1; j <= d + 1; j++) { if (i != c or j != d) { ans = min(ans, dist(a, b, i, j)); } } } cout << 2 * ans + 8 << endl; }
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#include <bits/stdc++.h> void sc(int &x) { scanf( %d , &x); } void sc(int &x, int &y) { scanf( %d%d , &x, &y); } void sc(int &x, int &y, int &z) { scanf( %d%d%d , &x, &y, &z); } void sc(long long &x) { scanf( %lld , &x); } void sc(long long &x, long long &y) { scanf( %lld%lld , &x, &y); } void sc(long long &x, long long &y, long long &z) { scanf( %lld%lld%lld , &x, &y, &z); } void sc(char *x) { scanf( %s , x); } void sc(char *x, char *y) { scanf( %s%s , x, y); } void sc(char *x, char *y, char *z) { scanf( %s%s%s , x, y, z); } void out(int x) { printf( %d n , x); } void out(long long x) { printf( %lld n , x); } void out(int x, int y) { printf( %d %d n , x, y); } void out(long long x, long long y) { printf( %lld %lld n , x, y); } void out(int x, int y, int z) { printf( %d %d %d n , x, y, z); } void out(long long x, long long y, long long z) { printf( %lld %lld %lld n , x, y, z); } void ast(long long x, long long l, long long r) { assert(x >= l && x <= r); } using namespace std; const int N = 6e3 + 5, mod = 1e9 + 7; int n, x[N], y[N]; int vis[2][2]; int gcd(int x, int y) { return !y ? x : gcd(y, x % y); } int cal(int i, int j) { int xx = abs(x[i] - x[j]), yy = abs(y[i] - y[j]); xx = gcd(xx, yy); return xx * 2; } void sol(int cas) { sc(n); for (int i = 1; i <= n; i++) sc(x[i], y[i]); for (int i = 1; i <= n; i++) x[i] >>= 1, y[i] >>= 1, x[i] &= 1, y[i] &= 1; long long ans = 0; for (int i = 1; i <= n; i++) { memset(vis, 0, sizeof(vis)); for (int j = n; j >= i + 1; j--) { for (int h = 0; h <= 1; h++) for (int k = 0; k <= 1; k++) { int s = x[i] * y[j] + x[j] * y[i] + x[i] * k + h * y[i] + x[j] * k + h * y[j]; s &= 1; if (s == 0) ans += vis[h][k]; } vis[x[j]][y[j]]++; } } out(ans); } void init() {} int main() { srand(time(0)); init(); int t = 1, cas = 0; while (t--) { sol(++cas); } }
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int mod = (int)1e9 + 7; int sum(int a, int b) { int s = a + b; if (s >= mod) s -= mod; return s; } int mult(int a, int b) { return (1LL * a * b) % mod; } int pw(int a, int b) { if (b == 0) return 1; if (b & 1) return mult(a, pw(a, b - 1)); int res = pw(a, b / 2); return mult(res, res); } const int maxN = (int)1e5 + 100; int dp[maxN]; int calc(int x) { dp[0] = 2; dp[1] = 2; for (int i = 2; i <= x; i++) { dp[i] = 0; dp[i] = sum(dp[i], dp[i - 1]); dp[i] = sum(dp[i], dp[i - 2]); } return dp[x]; } int n, m; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> m; int f1 = calc(n); int f2 = calc(m); int ans = sum(f1, f2); ans -= 2; if (ans < 0) ans += mod; cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; const int INF = 1.01e9; const long long INF18 = 1.01e18; int main() { int n; long long C; scanf( %d%lld , &n, &C); vector<long long> a(n); vector<long long> b(n - 1); for (int i = 0; i < (n); i++) { scanf( %lld , &a[i]); if (i + 1 != n) { scanf( %lld , &b[i]); } } b.push_back(0); vector<long long> c(n); set<pair<long long, int>> q; long long shift = 0; vector<long long> hist(n); int cur = 0; vector<long long> prefB; prefB.push_back(0); for (int i = 0; i < n; i++) { prefB.push_back(prefB.back() + a[i] + b[i]); } vector<long long> prefC; prefC.push_back(0); for (int i = 0; i < n; i++) { if (i > 0) { long long diff = b[i - 1] - c[i - 1]; shift += diff; q.insert({-shift, i}); hist[i] = -shift; } if (i == 0) { q.insert({0, i}); hist[i] = 0; } for (; cur < i && (prefB[i] - prefB[cur]) + a[i] > C;) { assert(q.erase({hist[cur], cur})); cur++; } long long val = 0; if (!q.empty()) { val = max(q.rbegin()->first + shift, val); } val = max( min(prefB[i] + a[i], C) - ((prefC[i] - prefC[max(0, cur - 1)]) + a[i]), val); c[i] = val; prefC.push_back(prefC.back() + a[i] + c[i]); } long long answer = 0; for (auto x : c) { answer += x; } for (auto x : a) { answer += min(x, C); } cout << answer << endl; return 0; }
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// a barrel shifter to satisfy the single clock cycle constraint
// and yet support the multibit shift operation
// @requires: A 32-bit data input, a 32-bit control input;
// @returns: A 32-bit left shifted output to support shift by 7
module shiftll (busSLL, busA, sel);
output [31:0] busSLL;
input [31:0] busA, sel;
// output zSLL, oSLL, cSLL, nSLL;
// wire carryOut;
wire [31:0] Level1, Level2;
genvar i, j, k;
// 1-bit shift left
mux2_1 m00(busSLL[0], Level1[0], 0, sel[0]);
generate
for(i = 1; i < 32; i = i+1) begin: Level0Loop
mux2_1 m0x(busSLL[i], Level1[i], Level1[i-1], sel[0]);
end
endgenerate
// 2-bit shift left
mux2_1 m10(Level1[0], Level2[0], 0, sel[1]);
mux2_1 m11(Level1[1], Level2[1], 0, sel[1]);
generate
for(j = 2; j < 32; j = j+1) begin: Level1Loop
mux2_1 m1x(Level1[j], Level2[j], Level2[j-2], sel[1]);
end
endgenerate
// 4-bit shift left
mux2_1 m20(Level2[0], busA[0], 0, sel[2]);
mux2_1 m21(Level2[1], busA[1], 0, sel[2]);
mux2_1 m22(Level2[2], busA[2], 0, sel[2]);
mux2_1 m23(Level2[3], busA[3], 0, sel[2]);
generate
for(k = 4; k < 32; k = k+1) begin: Level2Loop
mux2_1 m2x(Level2[k], busA[k], busA[k-4], sel[2]);
end
endgenerate
// flag test(busSLL, busA, busB, carryOut, zSLL, oSLL, cSLL, nSLL);
endmodule
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// -----------------------------------------------------------------------
//
// Copyright 2004 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
/*
* Simulate a specific subset of the Altera Shift register
* (lpm_clshift).
*
* Not very ambitious, just the bare minimum.
*/
`timescale 1ns/10ps
module arithshiftbidir(distance,
data,
direction,
result);
parameter lpm_type = "LPM_CLSHIFT";
parameter lpm_shifttype = "ARITHMETIC";
parameter lpm_width = 32;
parameter lpm_widthdist = 5;
input wire [lpm_widthdist-1:0] distance;
input signed [lpm_width-1 :0] data;
input wire direction;
output wire [lpm_width-1 :0] result;
wire [lpm_width-1 :0] lsh = data << distance;
wire [lpm_width-1 :0] rsh = data >> distance;
wire [lpm_width-1 :0] rshN = ~(~data >> distance);
wire [lpm_width-1 :0] arsh = data[lpm_width-1] ? rshN : rsh;
assign result = direction ? arsh : lsh;
endmodule
`ifdef TEST_ARITHSHIFTBIDIR
module test_arithshiftbidir();
reg [31:0] data;
reg [ 4:0] dist;
reg dir;
wire [31:0] resulta, resultl;
arithshiftbidir a(dist, data, dir, resulta);
defparam a.lpm_shifttype = "ARITHMETIC";
initial begin
#0 data = 48; dir = 0; dist = 0;
$monitor("dir %d dist %2d A %8x", dir, dist, resulta);
repeat (2) begin
repeat (32)
#1 dist = dist + 1;
data = 32'h98765432;
dir = ~dir;
end
dir = 1;
data = 32'h08765432;
repeat (32)
#1 dist = dist + 1;
end
endmodule
`endif
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#include <bits/stdc++.h> using namespace std; int main() { int N; scanf( %d , &N); int neg = 0, sum = 0; int mini = 1005; for (int i = 1; i < 2 * N; i++) { int x; scanf( %d , &x); neg ^= x < 0; x = abs(x); mini = min(mini, x); sum += x; } printf( %d n , sum - (neg && !(N % 2) ? 2 * mini : 0)); return 0; }
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module wb_bfm_memory
#(//Wishbone parameters
parameter dw = 32,
parameter aw = 32,
parameter DEBUG = 0,
// Memory parameters
parameter memory_file = "",
parameter mem_size_bytes = 32'h0000_8000) // 32KBytes
(input wb_clk_i,
input wb_rst_i,
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [1:0] wb_bte_i,
input [2:0] wb_cti_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output wb_err_o,
output wb_rty_o,
output [dw-1:0] wb_dat_o);
`include "wb_bfm_params.v"
localparam bytes_per_dw = (dw/8);
localparam mem_words = (mem_size_bytes/bytes_per_dw);
//Counters for read and write accesses
integer reads = 0;
integer writes = 0;
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
wb_bfm_slave
#(.aw (aw))
bfm0
(.wb_clk (wb_clk_i),
.wb_rst (wb_rst_i),
.wb_adr_i (wb_adr_i),
.wb_dat_i (wb_dat_i),
.wb_sel_i (wb_sel_i),
.wb_we_i (wb_we_i),
.wb_cyc_i (wb_cyc_i),
.wb_stb_i (wb_stb_i),
.wb_cti_i (wb_cti_i),
.wb_bte_i (wb_bte_i),
.wb_dat_o (wb_dat_o),
.wb_ack_o (wb_ack_o),
.wb_err_o (wb_err_o),
.wb_rty_o (wb_rty_o));
reg [aw-1:0] address;
reg [dw-1:0] data;
integer i;
always begin
bfm0.init();
address = bfm0.address; //Fetch start address
if(bfm0.op === WRITE)
writes = writes + 1;
else
reads = reads + 1;
while(bfm0.has_next) begin
//Set error on out of range accesses
if(address[31:2] > mem_words) begin
$display("%0d : Error : Attempt to access %x, which is outside of memory", $time, address);
bfm0.error_response();
end else begin
if(bfm0.op === WRITE) begin
bfm0.write_ack(data);
if(DEBUG) $display("%d : ram Write 0x%h = 0x%h %b", $time, address, data, bfm0.mask);
for(i=0;i < 4; i=i+1)
if(bfm0.mask[i])
mem[address[31:2]][i*8+:8] = data[i*8+:8];
end else begin
data = {aw{1'b0}};
for(i=0;i < 4; i=i+1)
if(bfm0.mask[i])
data[i*8+:8] = mem[address[31:2]][i*8+:8];
if(DEBUG) $display("%d : ram Read 0x%h = 0x%h %b", $time, address, data, bfm0.mask);
bfm0.read_ack(data);
end
end
if(bfm0.cycle_type === BURST_CYCLE)
address = bfm0.next_addr(address, bfm0.burst_type);
end
end
endmodule // wb_bfm_memory
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int sum = 0, a; for (int i = 0; i < n; i++) { cin >> a; sum += a; } int m; cin >> m; vector<char> good(1e5 + 1, false); int l, r; for (int i = 0; i < m; i++) { cin >> l >> r; for (int j = l; j <= r; j++) { good[j] = true; } } for (int i = sum; i <= 1e5; i++) { if (good[i]) { cout << i << endl; return 0; } } cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> int t1, t2; inline int get() { char c[10]; scanf( %s , &c); if (!strcmp(c, monday )) return 1; if (!strcmp(c, tuesday )) return 2; if (!strcmp(c, wednesday )) return 3; if (!strcmp(c, thursday )) return 4; if (!strcmp(c, friday )) return 5; if (!strcmp(c, saturday )) return 6; if (!strcmp(c, sunday )) return 0; } int main() { t1 = get(), t2 = get(); if ((t1 == t2) || ((t1 + 2) % 7 == t2) || ((t1 + 3) % 7 == t2)) puts( YES ); else puts( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; int hm = 0, wm = 0; for (int i = 0; i < (int)(n); i++) { char c; int h, w; cin >> c >> h >> w; if (h < w) { swap(h, w); } if (c == + ) { hm = max(hm, h); wm = max(wm, w); } else { if (h >= hm && w >= wm) { cout << YES << endl; } else { cout << NO << endl; } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR2_PP_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor2 (
Y ,
A ,
B ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__CLKINV_BEHAVIORAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
module InstructionMemory(
output reg[31:0] RA, /* Read Data Output*/
input [31:0] A /* Adress */
);
always @ (*) begin
case (A)
32'h00000004: RA = 32'hE3A00000; //MOV R0, #0x0
32'h00000008: RA = 32'hE3A04004; //MOV R4, #0x00000004
32'h0000000c: RA = 32'hE3A05010; //MOV R5, #0x00000010
32'h00000010: RA = 32'hE3A06014; //MOV R6, #0x00000014
32'h00000014: RA = 32'hE3A07018; //MOV R7, #0x00000018
23'h00000018: RA = 32'hE3A0D024; //MOV R13, OPA
32'h0000001c: RA = 32'hE3A0801C; //MOV R8, #0x0000001c
//HEPHAESTUS
32'h00000020: RA = 32'hEAFFFFFE; //B HEPHAESTUS
//OPA
32'h00000024: RA = 32'hE5941000; //LDR R1, [R4, R0]
32'h00000028: RA = 32'hE351000A; //CMP R1, #10
32'h0000002c: RA = 32'hAA000006; //BGE SAVEOP
32'h00000030: RA = 32'hE5952000; //LDR R2, [R5, #0]
32'h00000034: RA = 32'hE1A03182; //LSL R3, R2, #3
32'h00000038: RA = 32'hE1A02082; //LSL R2, R2, #1
32'h0000003c: RA = 32'hE0822003; //ADD R2, R2, R3
32'h00000040: RA = 32'hE0822001; //ADD R2, R2, R1
32'h00000044: RA = 32'hE5852000; //STR R2, [R5, #0]
32'h00000048: RA = 32'hEAFFFFF4; //B HEPHAESTUS
//SAVEOP
32'h0000004c: RA = 32'hE7871000; //STR R1, [R7, R0]
32'h00000050: RA = 32'hE3A0D058; //MOV R13, #17
32'h00000054: RA = 32'hEAFFFFF1; //B HEPHAESTUS
//OPB
32'h00000058: RA = 32'hE7941000; //LDR R1, [R4, R0]
32'h0000005c: RA = 32'hE351000F; //CMP R1, #15
32'h00000060: RA = 32'h0A000006; //BEQ EXE
32'h00000064: RA = 32'hE7962000; //LDR R2, [R6, R0]
32'h00000068: RA = 32'hE1A03182; //LSL R3, R2, #3
32'h0000006c: RA = 32'hE1A02082; //LSL R2, R2, #1
32'h00000070: RA = 32'hE0822003; //ADD R2, R2, R3
32'h00000074: RA = 32'hE0822001; //ADD R2, R2, R1
32'h00000078: RA = 32'hE7861000; //STR R1, [R6, R0]
32'h0000007c: RA = 32'hEAFFFFE7; //B HEPHAESTUS
//EXE
32'h00000080: RA = 32'hE7971000; //LDR R1, [R7, R0]
32'h00000084: RA = 32'hE7952000; //LDR R2, [R5, R0]
32'h00000088: RA = 32'hE7963000; //LDR R3, [R6, R0]
32'h0000008c: RA = 32'hE351000A; //CMP R1, #10
32'h00000090: RA = 32'h0A000007; //B SUM
32'h00000094: RA = 32'hE351000B; //CMP R1, #11
32'h00000098: RA = 32'h0A000007; //B SUB
32'h0000009c: RA = 32'hE351000C; //CMP R1, #12
32'h000000a0: RA = 32'h0A000007; //B MUL
32'h000000a4: RA = 32'hE351000D; //CMP R1, #13
32'h000000a8: RA = 32'h0A00000A; //B DIV
32'h000000ac: RA = 32'hE351000E; //CMP R1, #14
32'h000000b0: RA = 32'h0A00000D; //B MOD
//SUM
32'h000000b4: RA = 32'hE0820003; //ADD R0, R2, R3
32'h000000b8: RA = 32'hEA000011; //B SAVEAN
//SUB
32'h000000bc: RA = 32'hE0420003; //SUB R0, R2, R3
32'h000000c0: RA = 32'hEA00000F; //B SAVEAN
//MUL
32'h000000c4: RA = 32'hE0800002; //ADD R0, R0, R2
32'h000000c8: RA = 32'hE2433001; //SUB R3, R3, #1
32'h000000cc: RA = 32'hE3530000; //CMP R3, #0
32'h000000d0: RA = 32'h0A00000B; //BEQ SAVEAN
32'h000000d4: RA = 32'hEAFFFFFA; //B MUL
//DIV
32'h000000d8: RA = 32'hE1520003; //CMP R2, R3
32'h000000dc: RA = 32'hBA000008; //BLT SAVEAN
32'h000000e0: RA = 32'hE2800001; //ADD R0, R0, #1
32'h000000e4: RA = 32'hE0422003; //SUB R2, R2, R3
32'h000000e8: RA = 32'hEAFFFFFA; //B DIV
//MOD
32'h000000ec: RA = 32'hE1520003; //CMP R2, R3
32'h000000f0: RA = 32'hB2820000; //ADDLT R0, R2, #0
32'h000000f4: RA = 32'hE1520003; //CMP R2, R3
32'h000000f8: RA = 32'hBA000001; //BLT SAVEAN
32'h000000fc: RA = 32'hE0422003; //SUB R2, R2, R3
32'h00000100: RA = 32'hEAFFFFF9; //B MOD
//SAVEAN
32'h00000104: RA = 32'hE5880000; //STR R0, [R8, #0]
32'h00000108: RA = 32'hE3A0D120; //MOV R13, CLEAR
32'h0000010c: RA = 32'hEAFFFFC3; //B HEPHAESTUS
//CLEAR
32'h00000120: RA = 32'h00000000;
default: RA = 32'b0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__AND2_PP_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int jie[2000050], i, ni[2000050], j, g[1000050], su[1000050], m; bool vis[1000050]; int qmi(int di, int zhi) { int ret = 1, x = di; while (zhi) { if (zhi & 1) ret = 1LL * ret * x % 1000000007; x = 1LL * x * x % 1000000007; zhi >>= 1; } return ret; } int main() { jie[0] = jie[1] = ni[1] = ni[0] = 1; for (i = 2; i <= 2000000; i++) jie[i] = 1LL * jie[i - 1] * i % 1000000007; for (i = 1; i <= 2000000; i++) ni[i] = qmi(jie[i], 1000000007 - 2); for (i = 2; i <= 1000000; i++) { if (!vis[i]) { g[i] = i; su[++m] = i; } for (j = 1; j <= m; j++) { if (i * su[j] > 1000000) break; if (i % su[j]) { g[i * su[j]] = su[j]; vis[i * su[j]] = true; } else { g[i * su[j]] = su[j]; vis[i * su[j]] = true; break; } } } int t; scanf( %d , &t); while (t--) { int r, x; scanf( %d%d , &r, &x); int ans = 1; while (x != 1) { int cnt = 0, psz = g[x]; while (x % psz == 0) x /= psz, cnt++; ans = 1LL * ans * (0LL + 2LL * (r + cnt >= cnt ? ((1LL * ni[r + cnt - cnt] * ni[cnt] % 1000000007) * jie[r + cnt] % 1000000007) : 0) - (r + cnt - 1 >= cnt ? ((1LL * ni[r + cnt - 1 - cnt] * ni[cnt] % 1000000007) * jie[r + cnt - 1] % 1000000007) : 0)) % 1000000007; } printf( %d n , (ans + 1000000007) % 1000000007); } return 0; }
|
#include <bits/stdc++.h> int n, p[4005], f[4005][4005], w[4005], tl; void solve() { scanf( %d , &n); n <<= 1; for (int i = 1; i <= n; ++i) scanf( %d , &p[i]); tl = 0; int pre = 1; w[++tl] = 1; for (int i = 2; i <= n; ++i) { if (p[i] < p[pre]) w[tl]++; else { pre = i; w[++tl] = 1; } } for (int i = 0; i <= n; ++i) for (int j = 0; j <= n; ++j) f[i][j] = 0; f[0][0] = 1; for (int i = 1; i <= tl; ++i) for (int j = 0; j <= n; ++j) f[i][j] = f[i - 1][j] | (j - w[i] >= 0 ? f[i - 1][j - w[i]] : 0); if (f[tl][n / 2]) puts( YES ); else puts( NO ); } int main() { int t; scanf( %d , &t); while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 10000000000; const int maxn = 5010; long long a[maxn]; long long last[maxn]; int dp[maxn]; long long s[maxn]; int n; int main(int argc, char *argv[]) { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %I64d , &a[i]); fill(last, last + maxn, INF); fill(dp, dp + maxn, maxn); s[0] = 0; for (int i = 1; i <= n; i++) s[i] = s[i - 1] + a[i]; dp[0] = 0; last[0] = 0; for (int i = 1; i <= n; i++) { for (int j = 0; j < i; j++) { if (s[i] - s[j] >= last[j]) { if (dp[i] >= dp[j] + i - j - 1) { dp[i] = dp[j] + i - j - 1; last[i] = min(last[i], s[i] - s[j]); } } } } cout << dp[n] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { printf( %d , i); for (int j = 1; j < n; j++) { int tmp = (i + j) % n; if (tmp == 0) tmp = n; printf( %d , j * n + tmp); } printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int mark[1000009]; int main() { long long n, m = 0, i, j, t; long long sum; cin >> n; long long a[n]; for (i = 0; i < n; i++) { scanf( %lld , &a[i]); } t = a[n - 1]; sum = t; for (j = n - 1; j > 0; j--) { if (a[j - 1] < t) { sum += a[j - 1]; t = a[j - 1]; } else { if (t - 1 >= 0) { sum += t - 1; t = t - 1; } else break; } } cout << sum; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; sort(arr, arr + n); int curr = 1; for (int i = 0; i < n; i++) { if (arr[i] >= curr) { curr++; } } cout << curr; return 0; }
|
#include <bits/stdc++.h> using namespace std; enum { UP, DOWN, LEFT, RIGHT }; const int MAX = 15500; struct Node { int dir; Node* pt[4]; } node[MAX], *cur, *row[MAX], *col[MAX], *st[MAX]; char s[MAX]; int r, c, top; int getDir(char c) { switch (c) { case U : return UP; case D : return DOWN; case L : return LEFT; case R : return RIGHT; } return -1; } void init() { cur = node; top = 0; for (int i = 0; i < r; i++) { row[i] = cur++; row[i]->pt[LEFT] = row[i]->pt[RIGHT] = row[i]; row[i]->pt[UP] = row[i]->pt[DOWN] = NULL; row[i]->dir = -1; } for (int i = 0; i < c; i++) { col[i] = cur++; col[i]->pt[UP] = col[i]->pt[DOWN] = col[i]; col[i]->pt[LEFT] = col[i]->pt[RIGHT] = NULL; col[i]->dir = -1; } } Node* add(int x, int y, int dir) { cur->pt[RIGHT] = row[x]->pt[RIGHT]; cur->pt[LEFT] = row[x]; cur->pt[DOWN] = col[y]->pt[DOWN]; cur->pt[UP] = col[y]; cur->pt[LEFT]->pt[RIGHT] = cur; cur->pt[RIGHT]->pt[LEFT] = cur; cur->pt[UP]->pt[DOWN] = cur; cur->pt[DOWN]->pt[UP] = cur; cur->dir = dir; return cur++; } int dfs(Node* t) { if (t->dir == -1) return 0; t->pt[LEFT]->pt[RIGHT] = t->pt[RIGHT]; t->pt[RIGHT]->pt[LEFT] = t->pt[LEFT]; t->pt[UP]->pt[DOWN] = t->pt[DOWN]; t->pt[DOWN]->pt[UP] = t->pt[UP]; int ret = dfs(t->pt[t->dir]) + 1; t->pt[LEFT]->pt[RIGHT] = t; t->pt[RIGHT]->pt[LEFT] = t; t->pt[UP]->pt[DOWN] = t; t->pt[DOWN]->pt[UP] = t; return ret; } int main() { int ret, cnt; while (scanf( %d%d , &r, &c) == 2) { ret = -1; cnt = 0; init(); for (int i = 0; i < r; i++) { scanf( %s , &s[i * c]); } for (int i = r - 1; i >= 0; i--) { for (int j = c - 1; j >= 0; j--) { if (s[i * c + j] != . ) st[top++] = add(i, j, getDir(s[i * c + j])); } } for (int i = 0; i < top; i++) { int sub = dfs(st[i]); if (sub > ret) { ret = sub; cnt = 1; } else if (sub == ret) { cnt++; } } printf( %d %d n , ret, cnt); } return 0; }
|
#include <bits/stdc++.h> int in[301]; int c[301]; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int main() { int n, i, j; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , in + i); for (i = 1; i <= n; i++) scanf( %d , c + i); for (i = 1; i <= n; i++) { for (j = 2; j * j <= in[i]; j++) { if (in[i] % j == 0) { while (in[i] % j == 0) in[i] /= j; in[i] *= j; } } } std::map<int, int> dp, dt; dp[0] = 0; for (i = 1; i <= n; i++) { for (auto t : dp) { int xx = gcd(t.first, in[i]); int xy = t.second + c[i]; if (dp.count(xx) == 0 || dp[xx] > xy) { if (dt.count(xx) == 0 || dt[xx] > xy) dt[xx] = xy; } } for (auto t : dt) { dp[t.first] = t.second; } dt.clear(); } if (dp.count(1) == 0) printf( -1 ); else printf( %d , dp[1]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mxn = 200000; int n; int a[mxn], b[mxn], first[mxn], ff[mxn]; vector<int> v[mxn]; auto cmp = [](int x, int y) { return b[x] > b[y]; }; priority_queue<int, vector<int>, decltype(cmp)> pq(cmp); map<int, int> second; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> a[i] >> b[i]; a[i]--, b[i]--; v[a[i]].push_back(i); } int p = -1, q = -1; for (int i = 0; i < n; i++) { for (int j : v[i]) pq.push(j); int x = pq.top(); pq.pop(); first[i] = x, ff[x] = i + 1; if (!~p) { auto it = second.lower_bound(i); if (it != second.end() && it->second >= a[x]) { p = first[it->second], q = x; } else { it = second.insert({b[x], i}).first; if (it->second < i) { if (next(it) != second.end() && i <= next(it)->second) it = second.erase(it); while (it != second.begin() && (--it)->second <= i) it = second.erase(it); } } } } cout << (!~p ? YES : NO ) << n ; for (int i = 0; i < 1 + !!~p; i++) { cout << ff[0]; for (int i = 1; i < n; i++) cout << << ff[i]; cout << n ; if (~p) swap(ff[p], ff[q]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 10, mod = 1e9 + 7; long long n, dp[2][N], d[2][N], t[2][N]; vector<long long> ch[N]; void dfs(long long v) { if (!ch[v].size()) { dp[0][v] = 0; dp[1][v] = 1; return; } for (long long i : ch[v]) dfs(i); d[0][0] = 1; for (long long i = 1; i <= ch[v].size(); i++) { long long u = ch[v][i - 1]; d[0][i] = ((dp[0][u] + 1) * d[0][i - 1] + dp[1][u] * d[1][i - 1]) % mod; d[1][i] = ((dp[0][u] + 1) * d[1][i - 1] + dp[1][u] * d[0][i - 1]) % mod; } dp[0][v] = (2 * d[0][ch[v].size()]) % mod; dp[1][v] = (2 * d[1][ch[v].size()]) % mod; long long bad = dp[0][ch[v][0]] + 1; for (long long i = 1; i < ch[v].size(); i++) bad = (bad * (dp[0][ch[v][i]] + 1)) % mod; dp[0][v] = (dp[0][v] - bad) % mod; t[0][0] = 1; t[1][0] = dp[1][ch[v][0]]; for (long long i = 1; i < ch[v].size(); i++) { t[0][i] = (t[0][i - 1] + t[1][i - 1] * dp[1][ch[v][i]]) % mod; t[1][i] = (t[1][i - 1] + t[0][i - 1] * dp[1][ch[v][i]]) % mod; } dp[1][v] = (dp[1][v] - t[1][(long long)ch[v].size() - 1]) % mod; swap(dp[0][v], dp[1][v]); } int32_t main() { cin >> n; for (long long i = 1; i < n; i++) { long long p; cin >> p; p--; ch[p].push_back(i); } dfs(0); cout << (((dp[0][0] + dp[1][0]) % mod) + mod) % mod; }
|
//==========================================
// Function : Code Gray counter.
// Coder : Alex Claros F.
// Date : 15/May/2005.
//=======================================
`timescale 1ns/1ps
module GrayCounter
#(parameter COUNTER_WIDTH = 4)
(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire Clear_in, //Count reset.
input wire Clk);
/////////Internal connections & variables///////
reg [COUNTER_WIDTH-1:0] BinaryCount;
/////////Code///////////////////////
always @ (posedge Clk)
if (Clear_in) begin
BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'.
end
else if (Enable_in) begin
BinaryCount <= BinaryCount + 1;
GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
end
endmodule
|
module score (
input wire clk,
input wire [10:0] PIXEL_H, PIXEL_V,
input wire [7:0] PLAYER_ONE, PLAYER_TWO,
output reg [2:0] PIXEL
);
// signal declaration
wire [10:0] rom_addr;
reg [6:0] char_addr;
reg [3:0] row_addr;
reg [2:0] bit_addr;
wire [7:0] font_word;
wire font_bit;
wire p1, p2;
// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));
// Location on the screen of the player one score.
reg [10:0] p1_v_start = 11'd10;
reg [10:0] p1_h_start = 11'd280;
// Location on the screen of the player two score.
reg [10:0] p2_v_start = 11'd10;
reg [10:0] p2_h_start = 11'd470;
// Check we are within the part of the screen that holds the player one score.
assign p1 = (
PIXEL_H >= p1_h_start && PIXEL_H <= p1_h_start + (8'd7 << 2)
&& PIXEL_V >= p1_v_start && PIXEL_V <= p1_v_start + (8'd15 << 2)
);
// Check we are within the part of the screen that holds the player two score.
assign p2 = (
PIXEL_H >= p2_h_start && PIXEL_H <= p2_h_start + (8'd7 << 2)
&& PIXEL_V >= p2_v_start && PIXEL_V <= p2_v_start + (8'd15 << 2)
);
// Mux for font ROM addresses and rgb
always @* begin
PIXEL = 3'b000;
if (p1) begin
// @todo Scores larger than 9!!!
char_addr = 7'h30 + PLAYER_ONE;
row_addr = (PIXEL_V - p1_v_start) >> 2;
bit_addr = (PIXEL_H - p1_h_start) >> 2;
if (font_bit)
PIXEL = 3'b111;
end else if (p2) begin
// @todo Scores larger than 9!!!
char_addr = 7'h30 + PLAYER_TWO;
row_addr = (PIXEL_V - p2_v_start) >> 2;
bit_addr = (PIXEL_H - p2_h_start) >> 2;
if (font_bit)
PIXEL = 3'b111;
end else begin
char_addr = 0;
row_addr = 0;
bit_addr = 0;
end
end
// Build the rom address of the current pixel.
assign rom_addr = {char_addr, row_addr};
// Get the on/off value of the bit at the current pixel from the rom.
assign font_bit = font_word[~bit_addr];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; long n, i, k = 0, u = 0, d = 0, l = 0, r = 0; cin >> n; cin >> s; for (i = 0; i < s.size(); i++) { if (s[i] == U ) u++; if (s[i] == D ) d++; if (s[i] == L ) l++; if (s[i] == R ) r++; } k += min(d, u) * 2; k += min(r, l) * 2; cout << k; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, r; cin >> n >> m >> r; int min1 = 1001; int max1 = 0; int a, b; for (int i = 0; i < n; i++) { cin >> a; min1 = min(a, min1); } for (int i = 0; i < m; i++) { cin >> b; max1 = max(b, max1); } int d = r / min1; if (min1 > max1) { cout << r << endl; return 0; } int cost = (d * max1 + r % min1); if (cost > r) { cout << cost << endl; } else { cout << r << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, a, t; while (cin >> n >> m >> a) { if (m < n) { t = m; m = n; n = t; } if (a >= m) cout << 1 << endl; if ((a < m) && (a >= n)) { if (m % a == 0) cout << m / a << endl; else cout << m / a + 1 << endl; } if ((a < n) && (m % a != 0) && (n % a != 0)) cout << (m / a + 1) * (n / a + 1) << endl; if ((a < n) && (m % a != 0) && (n % a == 0)) cout << (m / a + 1) * (n / a) << endl; if ((a < n) && (m % a == 0) && (n % a != 0)) cout << (m / a) * (n / a + 1) << endl; if ((a < n) && (m % a == 0) && (n % a == 0)) cout << (m / a) * (n / a) << endl; } }
|
/// date:2016/3/4
/// engineer: ZhaiShaoMin
/// module function : just combine memory_fsm and memory_state_data_ram
module memory (//input
clk,
rst,
//fsm state of rep paralle-serial port corresponding to mem
m_rep_fsm_state,
//fsm state of req paralle-serial port corresponding to mem
m_req_fsm_state,
// fsm state of req paralle-serial port corresponding to data cache
d_fsm_state,
// input from local d cache
v_d_req,
v_d_rep,
local_d_head_in,
local_d_addr_in,
local_d_data_in,
// input from local i cache
v_i_rep,
// local_i_head, // no need for local i cache miss
local_i_addr_in,
// input form INfifos
v_INfifos,
infifos_head_in,
infifos_addr_in,
infifos_data_in,
// output to local d cache
v_req_d,
v_rep_d,
head_out_local_d,
addr_out_local_d,
data_out_local_d,
// output to local i cahce
v_rep_i,
data_out_local_i,
// output to OUT req fifo
en_inv_ids,
inv_ids_in,
flit_max_req,
en_flit_max_req,
v_req_out,
head_out_req_out,
addr_out_req_out,
// data_out_req_out,
// output to OUT rep fifo
flit_max_rep,
en_flit_max_rep,
v_rep_out,
head_out_rep_out,
addr_out_rep_out,
data_out_rep_out,
mem_access_done
);
// input
input clk;
input rst;
//fsm state of rep paralle-serial port corresponding to mem
input [1:0] m_rep_fsm_state;
//fsm state of req paralle-serial port corresponding to mem
input [1:0] m_req_fsm_state;
// fsm state of req paralle-serial port corresponding to data cache
input [1:0] d_fsm_state;
// input from local d cache
input v_d_req;
input v_d_rep;
input [15:0] local_d_head_in;
input [31:0] local_d_addr_in;
input [127:0] local_d_data_in;
// input from local i cache
input v_i_rep;
// local_i_head, // no need for local i cache miss
input [31:0] local_i_addr_in;
// input form INfifos
input v_INfifos;
input [15:0] infifos_head_in;
input [31:0] infifos_addr_in;
input [127:0] infifos_data_in;
// output
// output to local d cache
output v_req_d;
output v_rep_d;
output [15:0] head_out_local_d;
output [31:0] addr_out_local_d;
output [127:0] data_out_local_d;
// output to local i cahce
output v_rep_i;
output [127:0] data_out_local_i;
// output to OUT req fifo
output en_inv_ids;
output [3:0] inv_ids_in;
output [1:0] flit_max_req;
output en_flit_max_req;
output v_req_out;
output [15:0] head_out_req_out;
output [31:0] addr_out_req_out;
//output [127:0] data_out_req_out;
// output to OUT rep fifo
output [3:0] flit_max_rep;
output en_flit_max_rep;
output v_rep_out;
output [15:0] head_out_rep_out;
output [31:0] addr_out_rep_out;
output [127:0] data_out_rep_out;
output mem_access_done;
wire state_we_net;
wire state_re_net;
wire data_we_net;
wire data_re_net;
wire [31:0] addr_net;
wire [127:0] data_in_net;
wire [127:0] data_out_net;
wire [5:0] state_in_net;
wire [5:0] state_out_net;
memory_state_data_ram mem_ram(// input
.clk(clk),
.state_we_in(state_we_net),
.state_re_in(state_re_net),
.addr_in(addr_net),
.state_in(state_in_net),
.data_we_in(data_we_net),
.data_re_in(data_re_net),
.data_in(data_in_net),
// output
.state_out(state_out_net),
.data_out(data_out_net));
memory_fsm mem_fsm(// global signals
.clk(clk),
.rst(rst),
//fsm state of rep paralle-serial port corresponding to mem
.m_rep_fsm_state(m_rep_fsm_state),
//fsm state of req paralle-serial port corresponding to mem
.m_req_fsm_state(m_req_fsm_state),
// fsm state of req paralle-serial port corresponding to data cache
.d_fsm_state(d_fsm_state),
// input from mem_ram
.mem_state_out(state_out_net),
.mem_data_in(data_out_net),
// input from local d cache
.v_d_req(v_d_req),
.v_d_rep(v_d_rep),
.local_d_head_in(local_d_head_in),
.local_d_addr_in(local_d_addr_in),
.local_d_data_in(local_d_data_in),
// input from local i cache
.v_i_rep(v_i_rep),
// local_i_head, // no need for local i cache miss
.local_i_addr_in(),
// input form INfifos
.v_INfifos(v_INfifos),
.infifos_head_in(infifos_head_in),
.infifos_addr_in(infifos_addr_in),
.infifos_data_in(infifos_data_in),
//output to mem_ram
.data_out_mem_ram(data_in_net),
.state_out_mem_ram(state_in_net),
.addr_out_mem_ram(addr_net),
.state_we_out(state_we_net),
.state_re_out(state_re_net),
.data_we_out(data_we_net),
.data_re_out(data_re_net),
// output to local d cache
.v_req_d(v_req_d),
.v_rep_d(v_rep_d),
.head_out_local_d(head_out_local_d),
.addr_out_local_d(addr_out_local_d),
.data_out_local_d(data_out_local_d),
// output to local i cahce
.v_rep_Icache(v_rep_i),
.data_out_local_i(data_out_local_i),
// output to OUT req fifo
.en_inv_ids(en_inv_ids),
.inv_ids_in(inv_ids_in),
.flit_max_req(flit_max_req),
.en_flit_max_req(en_flit_max_req),
.v_req_out(v_req_out),
.head_out_req_out(head_out_req_out),
.addr_out_req_out(addr_out_req_out),
//.data_out_req_out(data_out_req_out),
// output to OUT rep fifo
.flit_max_rep(flit_max_rep),
.en_flit_max_rep(en_flit_max_rep),
.v_rep_out(v_rep_out),
.head_out_rep_out(head_out_rep_out),
.addr_out_rep_out(addr_out_rep_out),
.data_out_rep_out(data_out_rep_out),
.mem_access_done(mem_access_done)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Node { int len, link; int nxt[26]; long long val; }; struct Automaton { int sz, last; Node s[200100 * 10]; void init() { sz = last = 0; s[0].len = 0; s[0].link = -1; s[0].val = 0; memset(s[0].nxt, 0, sizeof(s[0].nxt)); ++sz; } void extend(int c, int cost) { int cur, p; if (s[last].nxt[c]) { cur = s[last].nxt[c]; if (s[cur].len == s[last].len + 1) { s[cur].val += cost; last = cur; return; } int clone = sz++; s[clone] = s[cur]; s[clone].len = s[last].len + 1; s[clone].val = cost; s[cur].link = clone; for (p = last; p != -1 && s[p].nxt[c] == cur; p = s[p].link) s[p].nxt[c] = clone; last = clone; return; } cur = sz++; s[cur].len = s[last].len + 1; s[cur].val = cost; for (p = last; p != -1 && !s[p].nxt[c]; p = s[p].link) s[p].nxt[c] = cur; if (p == -1) s[cur].link = 0; else { int q = s[p].nxt[c]; if (s[p].len + 1 == s[q].len) s[cur].link = q; else { int clone = sz++; s[clone].len = s[p].len + 1; memcpy(s[clone].nxt, s[q].nxt, sizeof(s[q].nxt)); s[clone].link = s[q].link; s[clone].val = 0; for (; p != -1 && s[p].nxt[c] == q; p = s[p].link) s[p].nxt[c] = clone; s[q].link = s[cur].link = clone; } } last = cur; } int cnt[10 * 200100], st[10 * 200100]; long long solve(int len) { int i, j; for (j = 0; j <= len; j++) cnt[j] = 0; for (j = 0; j < sz; j++) cnt[s[j].len]++; for (j = 1; j <= len; j++) cnt[j] += cnt[j - 1]; for (j = 0; j < sz; j++) st[cnt[s[j].len]--] = j; long long ret = 0; for (i = sz; i >= 1; i--) { int x = st[i]; if (ret < s[x].val * s[x].len) ret = s[x].val * s[x].len; int p = s[x].link; if (p != -1) s[p].val += s[x].val; } return ret; } } sam; string str[200100]; int c[200100]; int main() { int N, i, len = 0; scanf( %d , &N); for (i = (0); i < (N); i++) cin >> str[i]; for (i = (0); i < (N); i++) scanf( %d , &c[i]); sam.init(); for (i = (0); i < (N); i++) { sam.last = 0; for (int j = 0; j < str[i].length(); j++) { sam.extend(str[i][j] - a , c[i]); } if (len < str[i].length()) len = str[i].length(); } long long ans = sam.solve(len); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long G[500][500], d[500][500]; long long x[500], n, m; void floyd(long long k) { for (long long i = 0; i < n; i++) if (i != k) { for (long long j = 0; j < n; j++) if (i != j && j != k) if (G[i][j] > G[i][k] + G[k][j]) { G[i][j] = G[i][k] + G[k][j]; } } } void build_graph() { for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { scanf( %I64d , &G[i][j]); } } for (long long i = 0; i < n; i++) { scanf( %I64d , &x[n - i - 1]); x[n - i - 1]--; } } void solve() { m = 0; long long ans[500] = {0}; memcpy(d, G, sizeof(G)); for (long long i = 0; i < n; i++) { m++; floyd(x[i]); for (long long j = 0; j < m; j++) { for (long long k = 0; k < m; k++) { ans[n - i - 1] += G[x[j]][x[k]]; } } } printf( %I64d , ans[0]); for (long long i = 1; i < n; i++) printf( %I64d , ans[i]); putchar(10); } int main() { while (~scanf( %I64d , &n)) { build_graph(); solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; int x[500010], y[500010]; bitset<2010 * 2> A[2010]; void Work() { for (int i = 1; i <= n; i++) { int t = i; for (int j = i + 1; j <= n; j++) if (A[j][i]) t = j; swap(A[i], A[t]); for (int j = 1; j <= n; j++) if (A[j][i] && j != i) A[j] ^= A[i]; } for (int i = 1; i <= m; i++) if (A[y[i]][x[i] + n]) puts( NO ); else puts( YES ); } void Init() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &x[i], &y[i]); A[x[i]][y[i]] = 1; } for (int i = 1; i <= n; i++) A[i][i + n] = 1; } int main() { Init(); Work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, a[1010], maxx = -1, res[1010], ans = 0; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a[i]; if (res[a[i]] > 0) res[a[i]]++; else res[a[i]] = 1; maxx = max(maxx, res[a[i]]); } maxx = maxx + ((k - (maxx % k)) % k); for (int i = 1; i < 101; i++) { if (res[i] > 100 || res[i] < 1) continue; ans += (maxx - res[i]); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, n, m, q, p; cin >> q; while (q--) { cin >> n; string s; cin >> s; p = 0; if (s.length() > 2) { cout << YES n2 n ; cout << s[0] << ; for (i = 1; i < n; i++) cout << s[i]; cout << endl; } else { if (s[0] < s[1]) cout << YES n2 n << s[0] << << s[1] << endl; else cout << NO << endl; } } return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_0_data_stream_0_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_0_data_stream_0_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_0_data_stream_0_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_0_data_stream_0_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`timescale 1ns / 1ps
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
module jt12_opram
(
input [4:0] wr_addr,
input [4:0] rd_addr,
input clk,
input clk_en,
input [43:0] data,
output reg [43:0] q
);
reg [43:0] ram[31:0];
always @ (posedge clk) if(clk_en) begin
q <= ram[rd_addr];
ram[wr_addr] <= data;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A2BB2O_BEHAVIORAL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &x) { x = 0; T f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) x = (x << 3) + (x << 1) + (c ^ 48); x *= f; } int main() { int n; read(n); for (int i = 1; i <= n; i++) { int x; read(x); cout << x / 6 + (x % 6 == 0 ? 0 : 1) << endl; } return 0; }
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_reg
*/
module test_wb_reg;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
wbm_adr_i,
wbm_dat_i,
wbm_we_i,
wbm_sel_i,
wbm_stb_i,
wbm_cyc_i,
wbs_dat_i,
wbs_ack_i,
wbs_err_i,
wbs_rty_i
);
$to_myhdl(
wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbm_rty_o,
wbs_adr_o,
wbs_dat_o,
wbs_we_o,
wbs_sel_o,
wbs_stb_o,
wbs_cyc_o
);
// dump file
$dumpfile("test_wb_reg.lxt");
$dumpvars(0, test_wb_reg);
end
wb_reg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
|
#include <bits/stdc++.h> const int MAXN = 1000001; int n, m, a[MAXN], b[MAXN]; int box[MAXN], axi[MAXN]; int n1, n2; int main() { std::cin >> n >> m; for (int i = 1; i <= n; i++) { std::scanf( %d , a + i); if (a[i] <= m) { b[++n1] = a[i]; box[a[i]]++; } } if (!n1) { std::puts( 1 0 ); return 0; } std::sort(b + 1, b + 1 + n1); int n2 = std::unique(b + 1, b + 1 + n1) - b - 1; for (int i = 1; i <= n2; i++) for (int j = 1; j <= m / b[i]; j++) axi[b[i] * j] += box[b[i]]; int sum = 0, lcm; for (int i = 1; i <= m; i++) { if (axi[i] > sum) sum = axi[i], lcm = i; } std::printf( %d %d n , lcm, sum); for (int i = 1; i <= n; i++) if (!(lcm % a[i])) std::printf( %d , i); std::putchar( n ); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:05:56 02/23/2015
// Design Name:
// Module Name: mult_descale_pipeline
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mult_descale_pipeline(
input [31:0] a_multiplicand,
input [31:0] b_multiplier,
input [31:0] z_scale,
input [7:0] InsTagScaleOut,
input ScaleValid,
input NatLogFlagScaleOut,
input reset,
input clock,
output [31:0] FinalProduct,
output done,
output [7:0] InsTagDescale,
output [31:0] z_out
);
wire idle_Special, idle_Multiply, idle_NormaliseProd;
wire [32:0] aout_Special,bout_Special;
wire [32:0] zout_Special,zout_Multiply,zout_NormaliseProd;
wire [49:0] productout_Multiply, productout_NormaliseProd;
wire [7:0] InsTagSpecial,InsTagMultiply,InsTagNormaliseProd;
wire ScaleValidSpecial,ScaleValidMultiply,ScaleValidNormaliseProd;
wire [31:0] z_Special,z_Multiply,z_NormaliseProd;
SpecialMultDescale Mult1 (
.ain_Special(a_multiplicand),
.bin_Special(b_multiplier),
.InsTagScaleOut(InsTagScaleOut),
.ScaleValid(ScaleValid),
.NatLogFlagScaleOut(NatLogFlagScaleOut),
.z_scale(z_scale),
.reset(reset),
.clock(clock),
.idle_Special(idle_Special),
.aout_Special(aout_Special),
.bout_Special(bout_Special),
.zout_Special(zout_Special),
.InsTagSpecial(InsTagSpecial),
.ScaleValidSpecial(ScaleValidSpecial),
.z_Special(z_Special)
);
MultiplyMultDescale Mult2 (
.aout_Special(aout_Special),
.bout_Special(bout_Special),
.zout_Special(zout_Special),
.idle_Special(idle_Special),
.InsTagSpecial(InsTagSpecial),
.ScaleValidSpecial(ScaleValidSpecial),
.z_Special(z_Special),
.clock(clock),
.idle_Multiply(idle_Multiply),
.zout_Multiply(zout_Multiply),
.productout_Multiply(productout_Multiply),
.InsTagMultiply(InsTagMultiply),
.ScaleValidMultiply(ScaleValidMultiply),
.z_Multiply(z_Multiply)
);
NormaliseProdMultDescale Mult3 (
.zout_Multiply(zout_Multiply),
.productout_Multiply(productout_Multiply),
.InsTagMultiply(InsTagMultiply),
.ScaleValidMultiply(ScaleValidMultiply),
.z_Multiply(z_Multiply),
.clock(clock),
.idle_Multiply(idle_Multiply),
.idle_NormaliseProd(idle_NormaliseProd),
.zout_NormaliseProd(zout_NormaliseProd),
.productout_NormaliseProd(productout_NormaliseProd),
.InsTagNormaliseProd(InsTagNormaliseProd),
.ScaleValidNormaliseProd(ScaleValidNormaliseProd),
.z_NormaliseProd(z_NormaliseProd)
);
Pack_z_descale Mult4 (
.idle_NormaliseProd(idle_NormaliseProd),
.zout_NormaliseProd(zout_NormaliseProd),
.productout_NormaliseProd(productout_NormaliseProd),
.InsTagNormaliseProd(InsTagNormaliseProd),
.ScaleValidNormaliseProd(ScaleValidNormaliseProd),
.z_NormaliseProd(z_NormaliseProd),
.reset(reset),
.clock(clock),
.done(done),
.FinalProduct(FinalProduct),
.InsTagPack(InsTagDescale),
.z_Descale(z_out)
);
endmodule
|
module check (input signed [22:0] a, b, c);
wire signed [22:0] int_AB;
assign int_AB = a - b;
always @(a, b, int_AB, c) begin
#1;
if (int_AB !== c) begin
$display("ERROR");
$finish;
end
end
endmodule
module stimulus (output reg signed [22:0] A, B);
parameter MAX = 1 << 23;
parameter S = 10000;
int unsigned i;
initial begin
A = 0; B= 0;
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
end
#1 A = 0;
B = 0;
#1 A = 23'h7fffff;
#1 B = 23'h7fffff;
#1 B = 0;
// x and z injected on A
for (i=0; i<S/2; i=i+1) begin
#1 A = $random % MAX;
A = xz_inject (A);
end
// x and z injected on B
#1 A = 1;
for (i=0; i<S/2; i=i+1) begin
#1 B = $random % MAX;
B = xz_inject (B);
end
// x and z injected on A, B
for (i=0; i<S; i=i+1) begin
#1 A = $random % MAX;
B = $random % MAX;
A = xz_inject (A);
B = xz_inject (B);
end
end
// injects some x, z values on 23 bits arguments
function [22:0] xz_inject (input signed [22:0] value);
integer i, temp;
begin
temp = {$random};
for (i=0; i<23; i=i+1)
begin
if (temp[i] == 1'b1)
begin
temp = $random;
if (temp <= 0)
value[i] = 1'bx; // 'x noise
else
value[i] = 1'bz; // 'z noise
end
end
xz_inject = value;
end
endfunction
endmodule
module test;
wire signed [22:0] a, b;
wire signed [22:0] r;
stimulus stim (.A(a), .B(b));
ssub23 duv (.a_i(a), .b_i(b), .c_o(r) );
check check (.a(a), .b(b), .c(r) );
initial begin
#40000;
$display("PASSED");
$finish;
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// The mini-decode module to decode the instruction in IFU
//
// ====================================================================
`include "e203_defines.v"
module e203_ifu_minidec(
//////////////////////////////////////////////////////////////
// The IR stage to Decoder
input [`E203_INSTR_SIZE-1:0] instr,
//////////////////////////////////////////////////////////////
// The Decoded Info-Bus
output dec_rs1en,
output dec_rs2en,
output [`E203_RFIDX_WIDTH-1:0] dec_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] dec_rs2idx,
output dec_mulhsu,
output dec_mul ,
output dec_div ,
output dec_rem ,
output dec_divu ,
output dec_remu ,
output dec_rv32,
output dec_bjp,
output dec_jal,
output dec_jalr,
output dec_bxx,
output [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx,
output [`E203_XLEN-1:0] dec_bjp_imm
);
e203_exu_decode u_e203_exu_decode(
.i_instr(instr),
.i_pc(`E203_PC_SIZE'b0),
.i_prdt_taken(1'b0),
.i_muldiv_b2b(1'b0),
.i_misalgn (1'b0),
.i_buserr (1'b0),
.dbg_mode (1'b0),
.dec_misalgn(),
.dec_buserr(),
.dec_ilegl(),
.dec_rs1x0(),
.dec_rs2x0(),
.dec_rs1en(dec_rs1en),
.dec_rs2en(dec_rs2en),
.dec_rdwen(),
.dec_rs1idx(dec_rs1idx),
.dec_rs2idx(dec_rs2idx),
.dec_rdidx(),
.dec_info(),
.dec_imm(),
.dec_pc(),
.dec_mulhsu(dec_mulhsu),
.dec_mul (dec_mul ),
.dec_div (dec_div ),
.dec_rem (dec_rem ),
.dec_divu (dec_divu ),
.dec_remu (dec_remu ),
.dec_rv32(dec_rv32),
.dec_bjp (dec_bjp ),
.dec_jal (dec_jal ),
.dec_jalr(dec_jalr),
.dec_bxx (dec_bxx ),
.dec_jalr_rs1idx(dec_jalr_rs1idx),
.dec_bjp_imm (dec_bjp_imm )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_2_V
`define SKY130_FD_SC_LP__A211OI_2_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_2_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using cd = complex<double>; ll base = 100; void fft(vector<cd>& a, bool inv) { int n = a.size(); int bits = __builtin_ctz(n); for (int i = 0; i < n; ++i) { int x = 0; for (int j = 0; j < bits; ++j) x = (x << 1) | (i >> j & 1); if (i > x) swap(a[i], a[x]); } for (int m = 2; m <= n; m *= 2) { auto alpha = (inv ? -2 : 2) * 3.14159265358979323846 / m; auto w = exp(cd(0, alpha)); for (int k = 0; k < n; k += m) { cd x = 1; for (int i = 0; i < m / 2; ++i) { auto u = a[k + i]; auto v = a[k + i + m / 2] * x; a[k + i] = u + v; a[k + i + m / 2] = u - v; x *= w; } } } if (inv) for (auto& x : a) x /= n; } void int_mul(vector<ll>& a, ll v) { ll carry = 0; for (int i = 0; i < a.size() || carry; ++i) { if (i >= a.size()) a.emplace_back(0ll); a[i] = a[i] * v + carry; carry = a[i] / base; a[i] %= base; } } void shrink(vector<ll>& a) { while (a.size() > 1 && a.back() == 0) a.pop_back(); } void normalize(vector<ll>& a) { ll carry = 0; for (int i = 0; i < a.size() || carry; ++i) { if (i >= a.size()) a.emplace_back(0); carry += a[i]; a[i] = carry % base; carry -= a[i]; carry /= base; } shrink(a); } void sqr(vector<ll>& a) { int n = a.size(); int m = 1; while (m < n + n) m *= 2; vector<cd> b(m); for (int i = 0; i < n; ++i) b[i] = a[i]; fft(b, false); for (auto& x : b) x *= x; fft(b, true); a.resize(b.size()); for (int i = 0; i < b.size(); ++i) a[i] = b[i].real() + 0.5; normalize(a); } vector<ll> bp(int e) { if (e == 0) return vector<ll>{1}; auto v = bp(e / 2); sqr(v); if (e & 1) int_mul(v, 3); return v; } int compare(vector<ll> const& a, vector<ll> const& b) { if (a.size() != b.size()) return a.size() < b.size() ? -1 : 1; for (int i = int(a.size()) - 1; i >= 0; --i) if (a[i] != b[i]) return a[i] < b[i] ? -1 : 1; return 0; } int main() { cin.tie(0); cin.sync_with_stdio(0); string number; cin >> number; vector<ll> num; int n = number.size(); int x = 2; num.reserve((n + x - 1) / x); reverse(number.begin(), number.end()); for (int i = 0; i < n; i += x) { auto s = number.substr(i, x); reverse(s.begin(), s.end()); num.emplace_back(stoll(s)); } int log3 = n / log10(3); int start = max(0, log3 - 3); int last = 5; auto A = bp(start); shrink(A); auto B = A; int_mul(B, 2); auto C = B; int_mul(C, 2); int ans = 3 * 10 * 1000 * 1000; for (int p = 0; p < last; ++p) { int v = 3 * (start + p); if (v < ans && compare(A, num) >= 0) { ans = min(ans, v); break; } else if (v + 3 < ans) { int_mul(A, 3); } else { break; } } for (int p = 0; p < last; ++p) { int v = 2 + 3 * (start + p); if (v < ans && compare(B, num) >= 0) { ans = min(ans, v); break; } else if (v + 3 < ans) { int_mul(B, 3); } else { break; } } for (int p = 0; p < last; ++p) { int v = 4 + 3 * (start + p); if (v < ans && compare(C, num) >= 0) { ans = min(ans, v); break; } else if (v + 3 < ans) { int_mul(C, 3); } else { break; } } cout << max(1, ans); }
|
#include <bits/stdc++.h> using namespace std; template <class T> void cmax(T &a, T b) { a = (a > b ? a : b); } template <class T> void cmin(T &a, T b) { a = (a > b ? b : a); } const long long maxn = 270000, base = 31, kcz = 1e9 + 7; long long inv; long long ksm(long long ds, long long zs = kcz - 2, long long mod = kcz) { long long res = 1; for (; zs; zs >>= 1, ds = ds * ds % mod) if (zs & 1) res = res * ds % kcz; return res; } struct node { long long len, l, r, val; } tr[maxn << 1]; long long p[maxn]; node merge(node a, node b) { node res; if (!a.len) return b; if (!b.len) return a; if (a.r && b.l) { a.val = (a.val + kcz - 1 - 1) * inv % kcz; b.val = (b.val + (kcz - p[b.len - 1]) * 2) % kcz; --b.len; --a.len; if (!a.len) { b.l = 0; return b; } if (!b.len) { a.r = 0; return a; } } res.l = a.l; res.r = b.r; res.len = a.len + b.len; res.val = (a.val * p[b.len] + b.val) % kcz; return res; } char s[maxn]; void build(long long l, long long r, long long now) { if (l == r) { tr[now].l = tr[now].r = s[l] - 0 ; tr[now].val = (s[l] - 0 + 1) * p[0]; tr[now].len = 1; return; } build(l, ((l + r) >> 1), (now << 1)); build(((l + r) >> 1) + 1, r, (now << 1 | 1)); tr[now] = merge(tr[(now << 1)], tr[(now << 1 | 1)]); } node get(long long l, long long r, long long now, long long x, long long y) { if (x <= l && r <= y) return tr[now]; if (y <= ((l + r) >> 1)) return get(l, ((l + r) >> 1), (now << 1), x, y); if (x > ((l + r) >> 1)) return get(((l + r) >> 1) + 1, r, (now << 1 | 1), x, y); return merge(get(l, ((l + r) >> 1), (now << 1), x, y), get(((l + r) >> 1) + 1, r, (now << 1 | 1), x, y)); } long long n, m; int main() { scanf( %lld , &n); inv = ksm(base); p[0] = 1; for (long long i = (1); i <= (n); ++i) p[i] = (p[i - 1] * base) % kcz; scanf( %s , s + 1); build(1, n, 1); scanf( %lld , &m); for (long long i = (1); i <= (m); ++i) { if (i == 28) { ++i; --i; } long long x, y, L; scanf( %lld%lld%lld , &x, &y, &L); node na = get(1, n, 1, x, x + L - 1), nb = get(1, n, 1, y, y + L - 1); if (na.val == nb.val) puts( YES ); else puts( NO ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; static const int MOD = 51123987; static const int MAXN = 150 + 10; char s[MAXN]; int p[MAXN][3]; int dp[MAXN][55][55][55]; int n, res; int main() { scanf( %d%s , &n, s + 1); p[n + 1][0] = p[n + 1][1] = p[n + 1][2] = n + 1; for (int i = n; i >= 1; i--) { p[i][0] = p[i + 1][0]; p[i][1] = p[i + 1][1]; p[i][2] = p[i + 1][2]; if (s[i] == a ) p[i][0] = i; if (s[i] == b ) p[i][1] = i; if (s[i] == c ) p[i][2] = i; } int k = (n + 2) / 3; dp[1][0][0][0] = 1; for (int i = 1; i <= n; i++) for (int a = 0; a <= k; a++) for (int b = 0; b <= k; b++) for (int c = 0; c <= k; c++) { if (a + b + c == n && abs(a - b) < 2 && abs(a - c) < 2 && abs(b - c) < 2) { res = (res + dp[i][a][b][c]) % MOD; continue; } dp[p[i][0]][a + 1][b][c] = (dp[p[i][0]][a + 1][b][c] + dp[i][a][b][c]) % MOD; dp[p[i][1]][a][b + 1][c] = (dp[p[i][1]][a][b + 1][c] + dp[i][a][b][c]) % MOD; dp[p[i][2]][a][b][c + 1] = (dp[p[i][2]][a][b][c + 1] + dp[i][a][b][c]) % MOD; } printf( %d n , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Point { long long x, y; void read() { scanf( %lld%lld , &x, &y); } }; long long product(const Point &o, const Point &a, const Point &b) { return (a.x - o.x) * (b.y - o.y) - (b.x - o.x) * (a.y - o.y); } bool intersect(const Point &a, const Point &b, const Point &c, const Point &d) { bool insect1 = product(a, c, d) * product(b, c, d) < 0; bool insect2 = product(c, a, b) * product(d, a, b) < 0; return insect1 && insect2; } int main() { ios ::sync_with_stdio(false); cout << fixed << setprecision(16); int R, B; scanf( %d%d , &R, &B); vector<Point> bases(B); vector<Point> ships(R); vector<int> b(R); for (int i = 0; i < R; i++) { ships[i].read(); } for (int i = 0; i < B; i++) { bases[i].read(); } if (B != R) { puts( No ); return 0; } for (int i = 0; i < R; i++) { b[i] = i; } bool yes = false; do { bool ok = true; for (int i = 0; i < B; i++) { for (int j = i + 1; j < B; j++) { if (intersect(ships[b[i]], bases[i], ships[b[j]], bases[j])) { ok = false; } } } if (ok) { yes = true; break; } } while (next_permutation(b.begin(), b.end())); puts(yes ? Yes : No ); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NOR4_BEHAVIORAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const long long pw10[] = {1, 10, 100, 1000, 10000, 100000}; long long K, F[7], Q, dp[7][2000000]; signed main() { cin >> K; for (long long i = 1; i <= 6; ++i) cin >> F[i]; memset(dp, -0x3f, sizeof(dp)); dp[0][0] = 0; for (long long i = 1; i <= 6; ++i) { for (long long j = 0; j < 3 * pw10[i - 1]; ++j) { deque<pair<long long, long long> > q; for (long long k = j, cnt = 0; k < 1e6; k += 3 * pw10[i - 1], ++cnt) { long long val = dp[i - 1][k] - cnt * F[i]; while (q.size() && q.back().first <= val) q.pop_back(); q.push_back(make_pair(val, cnt)); if (cnt - q.front().second > 3 * K) q.pop_front(); dp[i][k] = max(dp[i][k], cnt * F[i] + q.front().first); long long pos = 0; while (cnt - q[pos].second > 3 * (K - 1)) ++pos; long long v = cnt * F[i] + q[pos].first; for (long long t = 0; t < 10; ++t) dp[i][k + t * pw10[i - 1]] = max(dp[i][k + t * pw10[i - 1]], v); } } } for (cin >> Q; Q; --Q) { long long x; cin >> x; cout << max(0ll, dp[6][x]) << n ; } return 0; }
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: register_sync_2
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: universial
// Tool versions: Altera Quartus Prime
// Description: generates a reset signal (low-active by default) with duration of
// two clock cycles
//
//////////////////////////////////////////////////////////////////////////////////
module register_sync_2 #(
parameter reg_width = 16,
parameter reg_preset = {reg_width{1'b0}},
parameter resync_stages = 3,
parameter check_valid_data = "ON",
parameter use_valid_o = "ON"
) (
nrst,
clk_i,
clk_i_en,
reg_i,
clk_o,
clk_o_en,
reg_o
);
input nrst;
input clk_i;
input clk_i_en;
input [reg_width-1:0] reg_i;
input clk_o;
input clk_o_en;
output reg [reg_width-1:0] reg_o;
// misc
localparam IN_STATE_IDATA_WAIT = 2'b00;
localparam IN_STATE_ORDY_WAIT = 2'b01;
localparam IN_STATE_OACK_WAIT = 2'b10;
localparam OUT_STATE_IDATA_WAIT = 2'b00;
localparam OUT_STATE_ICONF_WAIT0 = 2'b01;
localparam OUT_STATE_ICONF_WAIT1 = 2'b10;
localparam OUT_STATE_ROUND_WAIT = 2'b11;
integer int_idx;
// wire
wire nrst_i, nrst_o;
wire reg_o_buf_valid_check_w;
// regs
reg [resync_stages-1:0] rdy_fb_i;
reg [resync_stages-1:0] ack_fb_i;
reg [1:0] in_state;
reg [reg_width-1:0] reg_i_buf [0:1] /* synthesis ramstyle = "logic" */;
reg req_i;
reg conf_i;
reg [resync_stages-1:0] req_fwd_o;
reg [resync_stages-1:0] conf_fwd_o;
reg [1:0] out_state;
reg rdy_o;
reg ack_o;
reg [reg_width-1:0] reg_o_buf [0:resync_stages-1] /* synthesis ramstyle = "logic" */;
reg reg_o_buf_valid;
// rtl
// generate reset signals first
reset_generator reset_clk_i_u(
.clk(clk_i),
.clk_en(clk_i_en),
.async_nrst_i(nrst),
.rst_o(nrst_i)
);
reset_generator reset_clk_o_u(
.clk(clk_o),
.clk_en(clk_o_en),
.async_nrst_i(nrst),
.rst_o(nrst_o)
);
// transfer logic with handshake
always @(posedge clk_i or negedge nrst_i)
if (!nrst_i) begin
rdy_fb_i <= {resync_stages{1'b0}};
ack_fb_i <= {resync_stages{1'b0}};
in_state <= IN_STATE_IDATA_WAIT;
reg_i_buf[1] <= reg_preset;
reg_i_buf[0] <= reg_preset;
req_i <= 1'b0;
conf_i <= 1'b0;
end else if (clk_i_en) begin
rdy_fb_i <= {rdy_fb_i[resync_stages-2:0],rdy_o};
ack_fb_i <= {ack_fb_i[resync_stages-2:0],ack_o};
case (in_state)
IN_STATE_IDATA_WAIT:
if (reg_i_buf[0] != reg_i && !ack_fb_i[resync_stages-1]) begin
in_state <= IN_STATE_ORDY_WAIT;
reg_i_buf[0] <= reg_i;
req_i <= 1'b1;
end
IN_STATE_ORDY_WAIT:
if (rdy_fb_i[resync_stages-1]) begin
in_state <= IN_STATE_OACK_WAIT;
reg_i_buf[1] <= reg_i_buf[0];
req_i <= 1'b0;
conf_i <= 1'b1;
end
IN_STATE_OACK_WAIT:
if (ack_fb_i[resync_stages-1]) begin
in_state <= IN_STATE_IDATA_WAIT;
conf_i <= 1'b0;
end
default:
in_state <= IN_STATE_IDATA_WAIT;
endcase
end
generate
if (check_valid_data == "ON" && resync_stages >= 3)
assign reg_o_buf_valid_check_w = reg_o_buf[resync_stages-1] == reg_o_buf[resync_stages-2];
else
assign reg_o_buf_valid_check_w = 1'b1;
endgenerate
always @(posedge clk_o or negedge nrst_o)
if (!nrst_o) begin
req_fwd_o <= {resync_stages{1'b0}};
conf_fwd_o <= {resync_stages{1'b0}};
out_state <= OUT_STATE_IDATA_WAIT;
rdy_o <= 1'b0;
ack_o <= 1'b0;
for (int_idx = 0; int_idx < resync_stages; int_idx = int_idx + 1)
reg_o_buf[int_idx] <= reg_preset;
reg_o_buf_valid <= 1'b0;
end else if (clk_o_en) begin
req_fwd_o <= {req_fwd_o[resync_stages-2:0],req_i};
conf_fwd_o <= {conf_fwd_o[resync_stages-2:0],conf_i};
case (out_state)
OUT_STATE_IDATA_WAIT: begin
if (req_fwd_o[resync_stages-1]) begin
out_state <= OUT_STATE_ICONF_WAIT0;
rdy_o <= 1'b1;
end
reg_o_buf_valid <= 1'b0;
end
OUT_STATE_ICONF_WAIT0:
if (conf_fwd_o[resync_stages-1]) begin
out_state <= OUT_STATE_ICONF_WAIT1;
rdy_o <= 1'b0;
reg_o_buf[0] <= reg_i_buf[1];
end
OUT_STATE_ICONF_WAIT1: begin
out_state <= OUT_STATE_ROUND_WAIT;
ack_o <= 1'b1;
reg_o_buf[0] <= reg_i_buf[1];
end
OUT_STATE_ROUND_WAIT:
if (!conf_fwd_o[resync_stages-1] &&
reg_o_buf_valid_check_w) begin
out_state <= OUT_STATE_IDATA_WAIT;
ack_o <= 1'b0;
reg_o_buf_valid <= 1'b1;
end
default:
out_state <= OUT_STATE_IDATA_WAIT;
endcase
for (int_idx = 1; int_idx < resync_stages; int_idx = int_idx + 1)
reg_o_buf[int_idx] <= reg_o_buf[int_idx-1];
end
generate
if (use_valid_o == "ON") begin
always @(posedge clk_o or negedge nrst_o)
if (!nrst_o) begin
reg_o <= reg_preset;
end else if (clk_o_en) begin
if (reg_o_buf_valid)
reg_o <= reg_o_buf[resync_stages-1];
end
end else begin
always @(*)
reg_o <= reg_o_buf[resync_stages-1];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, k, x, y, a, b, d[2010][2010], v[2010][2010]; bool solve(int x, int y, int k) { int l = max(1, x - k), r = min(x + k, n), t; for (int i = l; i < r + 1; i++) { t = k - abs(i - x); if (y - t > 0 && !v[i][y - t]) return a = i, b = y - t, 1; if (y + t <= m && !v[i][y + t]) return a = i, b = y + t, 1; } return 0; } int main() { cin >> n >> m >> k; for (int t = 0; t < k; t++) { cin >> x >> y; for (int i = -2; i < 3; i++) for (int j = -2; j < 3; j++) { if (x + i < 1 || x + i > n || y + j < 1 || y + j > m) continue; d[x][y] = max(d[x][y], d[x + i][y + j] - abs(i) - abs(j)); } while (!solve(x, y, d[x][y])) d[x][y]++; cout << a << << b << endl; v[a][b] = 1; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, a, cnt = 0, tmp; scanf( %lld%lld%lld , &n, &m, &a); cnt = (m / a) * (n / a); if (n % a != 0) cnt += (m / a); if (m % a != 0) cnt += (n / a); if (m % a != 0 && n % a != 0) cnt += 1; printf( %lld n , cnt); return 0; }
|
#include <bits/stdc++.h> using namespace std; void run(); int main() { ios::sync_with_stdio(0); run(); } int n; int v[5001]; char s[5001]; int grundy[5001]; void run() { cin >> s; n = strlen(s); vector<int> blob; for (int i = 0; i < n; i++) if (0 < i and i + 1 < n and s[i - 1] == s[i + 1]) blob.back()++; else if (blob.empty() or blob.back()) blob.push_back(0); if (not blob.empty() and blob.back() == 0) blob.pop_back(); static int can[5001]; for (int i = 1; i <= 5000; i++) { for (int j = 0; j < i; j++) { can[grundy[max(0, j - 1)] ^ grundy[max(0, i - j - 2)]] = i; } while (can[grundy[i]] == i) ++grundy[i]; } int good = 0; for (int i : blob) good ^= grundy[i]; cout << (good ? First : Second ) << endl; if (good) { int id = 0; for (int i = 1, x = 0; i + 1 < n; ++i, ++x) { if (s[i - 1] == s[i + 1]) { if (i > 1 and s[i - 2] != s[i + 0]) ++id, x = 0; int val = good ^ grundy[blob[id]]; if (val == (grundy[max(0, x - 1)] ^ grundy[max(0, blob[id] - x - 2)])) { cout << i + 1 << endl; return; } } } } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:57:02 11/23/2014
// Design Name:
// Module Name: counter_26bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module counter_26bit(clk, reset, clk_1ms, count_out);
parameter COUNTER=26;
input clk;
input reset;
output clk_1ms;
output wire [COUNTER-1:0] count_out;
reg [COUNTER-1:0] count;
reg second_m;
wire clk;
initial
count<=0;
always@(posedge clk)begin
if(!reset || (count[16:0]==99999))begin //reset==1
count[16:0]<=0;
count[25:17]<=count[25:17]+1;
second_m<=1; //if we consider the fpga as 50Mhz,then here becomes 1ms
end
else begin
count[16:0] <= count[16:0]+1;
second_m<=0;
end
end
assign clk_1ms=second_m;
assign count_out=count;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.06.2017 16:52:43
// Design Name:
// Module Name: Ps2Teclado
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Ps2Teclado(
input[3:0] h_p,
input [3:0] v_p,
output [4:0] num
);
reg[4:0] valor;
assign num=valor;
always @(*)begin
if (v_p==3'd0)begin
case (h_p)
3'd0:valor=5'd0;
3'd1:valor=5'd1;
3'd2:valor=5'd2;
3'd3:valor=5'd3;
default : valor = 5'd16;
endcase
end
if (v_p==3'd1)begin
case (h_p)
3'd0:valor=5'd4;
3'd1:valor=5'd5;
3'd2:valor=5'd6;
3'd3:valor=5'd7;
default : valor = 5'd16;
endcase
end
if (v_p==3'd2)begin
case (h_p)
3'd0:valor=5'd8;
3'd1:valor=5'd9;
3'd2:valor=5'd10;
3'd3:valor=5'd11;
default : valor = 5'd16;
endcase
end
if (v_p==3'd3)begin
case (h_p)
3'd0:valor=5'd12;
3'd1:valor=5'd13;
3'd2:valor=5'd14;
3'd3:valor=5'd15;
default : valor = 5'd16;
endcase
end
else valor=5'd16;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Chrisky HU
//
// Create Date: 21:35:40 10/01/2015
// Design Name:
// Module Name: ElbertV2_FPGA_Board
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ElbertV2_FPGA_Board(
input[5:0] BTN,
input clk,
output[7:0] LED,
output [7:0] SevenSegment,
output [2:0] SevenSegment_Enable,
output IO_P1_1,
output IO_P1_3,
inout IO_P1_5
);
wire rst_n;
wire inc_n_btn;
wire btn2_n;
wire dht11_dat;
reg [1:0] state_func;
wire inc_n_debounced;
wire btn2_n_debounced;
wire btn6_debounced;
wire select_onehot;
wire rst_debounced;
wire clk_div_1Hz;
wire clk_div_1MHZ;
wire clk_div_1kHZ;
wire [9:0] counter_4bit_out;
wire [9:0] counter_10bit_out;
wire dummy;
wire [9:0]humid;
wire [9:0]temp;
wire [3:0]status;
wire [3:0] HUNDREDS;
wire [3:0] TENS;
wire [3:0] ONES;
wire start_dht11_capture;
reg auto_capture;
reg [3:0] auto_capture_counter;
reg auto_capture_start;
reg auto_capture_rst_n;
wire [3:0] data0a;
wire [3:0] data1a;
wire [3:0] data2a;
wire [3:0] data0b;
wire [3:0] data1b;
wire [3:0] data2b;
reg [3:0] LCD_3;
reg [3:0] LCD_2;
reg [3:0] LCD_1;
wire dht11_start;
wire rst_n_dht11;
assign rst_n = BTN[4];
assign inc_n_btn = ~BTN[0];
assign btn2_n = ~BTN[1];
assign LED[7] = counter_4bit_out[0];
assign LED[6] = counter_4bit_out[1];
assign LED[5] = btn2_n_debounced;
assign LED[4] = inc_n_debounced;
assign LED[3] = status[0];
assign LED[2] = status[1];
assign LED[1] = status[2];
assign LED[0] = status[3];
assign SevenSegment[0] = ~clk_div_1Hz;
assign IO_P1_1 = 1'b0;
assign IO_P1_3 = 1'b1;
assign IO_P1_5 = dht11_dat;
assign start_dht11_capture = auto_capture? auto_capture_start:btn2_n_debounced;
assign rst_n_dht11 = btn6_debounced;//auto_capture? auto_capture_rst_n:btn6_debounced;
assign humid[9:8] = 2'b0;
assign temp[9:8] = 2'b0;
//assign SevenSegment = counter_10bit_out[7:0];
always@(posedge clk or negedge rst_debounced)
begin
if(~rst_debounced)
begin
state_func <=2'b0;
auto_capture<=1'b0;
end
else
begin
if(select_onehot==1'b1)
state_func <=state_func +1;
case(counter_4bit_out[1:0])
2'b0:
begin
LCD_1 <= ONES;
LCD_2 <= TENS;
LCD_3 <= HUNDREDS;
auto_capture<=1'b0;
end
2'b1:
begin
LCD_1 <= data0a;
LCD_2 <= data1a;
LCD_3 <= data2a;
auto_capture<=1'b0;
end
2'b10:
begin
LCD_1 <= data0b;
LCD_2 <= data1b;
LCD_3 <= data2b;
auto_capture<=1'b0;
end
2'b11:
begin
LCD_1 <= data0a;
LCD_2 <= data1a;
LCD_3 <= data2a;
auto_capture<=1'b1;
end
endcase
end
end
/*
always@(posedge clk_div_1Hz or negedge rst_n)
begin
if(~rst_n)
auto_capture_counter<=4'b0;
else
begin
auto_capture_counter<=auto_capture_counter+1;
if (auto_capture_counter == 4'b1101)
begin
auto_capture_rst_n <=1'b0;
end
else
begin
auto_capture_rst_n <=1'b1;
if(auto_capture_counter[2:0] == 3'b111)
begin
auto_capture_start<=1'b1;
end
else
begin
auto_capture_start<=1'b0;
end
end
end
end
*/
always@(posedge clk_div_1Hz or negedge rst_n)
begin
if(~rst_n)
begin
auto_capture_counter<=4'b0;
auto_capture_start<=1'b0;
end
else
begin
auto_capture_counter<=auto_capture_counter+1;
if(auto_capture_counter[2:0] == 3'b111)
auto_capture_start<=1'b1;
else
auto_capture_start<=1'b0;
end
end
freqdiv freqdiv1(clk,rst_n,clk_div_1Hz,2'b01);
freqdiv freqdiv2(clk,rst_n,clk_div_1MHZ,2'b00);
freqdiv freqdiv3(clk,rst_n,clk_div_1kHZ,2'b10);
debounce debounce_inc(clk_div_1kHZ,inc_n_btn,inc_n_debounced);
debounce debounce_start(clk_div_1kHZ,btn2_n,btn2_n_debounced);
debounce debounce_dht11_rst(clk_div_1kHZ,BTN[5],btn6_debounced);
debounce debounce_rst(clk_div_1kHZ,rst_n,rst_debounced);
new_counter theNewCounter(rst_n,inc_n_debounced,counter_4bit_out);
new_counter the10bitCounter(rst_n,clk_div_1Hz,counter_10bit_out);
mySevenSegment sevenSegementDec(clk,rst_debounced,LCD_1,LCD_2,LCD_3,SevenSegment[7:1],SevenSegment_Enable);
BINARY_TO_BCD theBinary2BCD(counter_10bit_out, HUNDREDS,TENS,ONES);
BINARY_TO_BCD theBinary2BCDhumid(humid, data2a,data1a,data0a);
BINARY_TO_BCD theBinary2BCDtemp(temp, data2b,data1b,data0b);
dht11_driver dht11_driver(clk_div_1MHZ,rst_n_dht11,start_dht11_capture,dht11_dat,humid[7:0],temp[7:0],status);
endmodule
|
/**
* $Id: red_pitaya_hk.v -01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya house keeping.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* House keeping module takes care of system identification.
*
*
* This module takes care of system identification via DNA readout at startup and
* ID register which user can define at compile time.
*
* Beside that it is currently also used to test expansion connector and for
* driving LEDs.
*
*/
module red_pitaya_hk #(
parameter DWL = 8, // data width for LED
parameter DWE = 8, // data width for extension
parameter [57-1:0] DNA = 57'h0823456789ABCDE
)(
// system signals
input clk_i , // clock
input rstn_i , // reset - active low
// LED
output reg [DWL-1:0] led_o , // LED output
// global configuration
output reg digital_loop,
// Expansion connector
input [DWE-1:0] exp_p_dat_i, // exp. con. input data
output reg [DWE-1:0] exp_p_dat_o, // exp. con. output data
output reg [DWE-1:0] exp_p_dir_o, // exp. con. 1-output enable
input [DWE-1:0] exp_n_dat_i, //
output reg [DWE-1:0] exp_n_dat_o, //
output reg [DWE-1:0] exp_n_dir_o, //
// System bus
input [ 32-1:0] sys_addr , // bus address
input [ 32-1:0] sys_wdata , // bus write data
input [ 4-1:0] sys_sel , // bus write byte select
input sys_wen , // bus write enable
input sys_ren , // bus read enable
output reg [ 32-1:0] sys_rdata , // bus read data
output reg sys_err , // bus error indicator
output reg sys_ack // bus acknowledge signal
);
//---------------------------------------------------------------------------------
//
// Read device DNA
wire dna_dout ;
reg dna_clk ;
reg dna_read ;
reg dna_shift;
reg [ 9-1: 0] dna_cnt ;
reg [57-1: 0] dna_value;
reg dna_done ;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
dna_clk <= 1'b0;
dna_read <= 1'b0;
dna_shift <= 1'b0;
dna_cnt <= 9'd0;
dna_value <= 57'd0;
dna_done <= 1'b0;
end else begin
if (!dna_done)
dna_cnt <= dna_cnt + 1'd1;
dna_clk <= dna_cnt[2] ;
dna_read <= (dna_cnt < 9'd10);
dna_shift <= (dna_cnt > 9'd18);
if ((dna_cnt[2:0]==3'h0) && !dna_done)
dna_value <= {dna_value[57-2:0], dna_dout};
if (dna_cnt > 9'd465)
dna_done <= 1'b1;
end
// parameter specifies a sample 57-bit DNA value for simulation
DNA_PORT #(.SIM_DNA_VALUE (DNA)) i_DNA (
.DOUT ( dna_dout ), // 1-bit output: DNA output data.
.CLK ( dna_clk ), // 1-bit input: Clock input.
.DIN ( 1'b0 ), // 1-bit input: User data input pin.
.READ ( dna_read ), // 1-bit input: Active high load DNA, active low read input.
.SHIFT ( dna_shift ) // 1-bit input: Active high shift enable input.
);
//---------------------------------------------------------------------------------
//
// Design identification
wire [32-1: 0] id_value;
assign id_value[31: 4] = 28'h0; // reserved
assign id_value[ 3: 0] = 4'h1; // board type 1 - release 1
//---------------------------------------------------------------------------------
//
// System bus connection
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
led_o <= {DWL{1'b0}};
exp_p_dat_o <= {DWE{1'b0}};
exp_p_dir_o <= {DWE{1'b0}};
exp_n_dat_o <= {DWE{1'b0}};
exp_n_dir_o <= {DWE{1'b0}};
end else if (sys_wen) begin
if (sys_addr[19:0]==20'h0c) digital_loop <= sys_wdata[0];
if (sys_addr[19:0]==20'h10) exp_p_dir_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h14) exp_n_dir_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h18) exp_p_dat_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h1C) exp_n_dat_o <= sys_wdata[DWE-1:0];
if (sys_addr[19:0]==20'h30) led_o <= sys_wdata[DWL-1:0];
end
wire sys_en;
assign sys_en = sys_wen | sys_ren;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
sys_err <= 1'b0;
sys_ack <= 1'b0;
end else begin
sys_err <= 1'b0;
casez (sys_addr[19:0])
20'h00000: begin sys_ack <= sys_en; sys_rdata <= { id_value }; end
20'h00004: begin sys_ack <= sys_en; sys_rdata <= { dna_value[32-1: 0]}; end
20'h00008: begin sys_ack <= sys_en; sys_rdata <= {{64- 57{1'b0}}, dna_value[57-1:32]}; end
20'h0000c: begin sys_ack <= sys_en; sys_rdata <= {{32- 1{1'b0}}, digital_loop }; end
20'h00010: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dir_o} ; end
20'h00014: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_n_dir_o} ; end
20'h00018: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_o} ; end
20'h0001C: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_n_dat_o} ; end
20'h00020: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_p_dat_i} ; end
20'h00024: begin sys_ack <= sys_en; sys_rdata <= {{32-DWE{1'b0}}, exp_n_dat_i} ; end
20'h00030: begin sys_ack <= sys_en; sys_rdata <= {{32-DWL{1'b0}}, led_o} ; end
default: begin sys_ack <= sys_en; sys_rdata <= 32'h0 ; end
endcase
end
endmodule
|
#include <bits/stdc++.h> int perm[100010 + 1]; using namespace std; int main() { int n; cin >> n; int s = 1; int e = n; while (e - s > 0) { perm[s] = s + 1; perm[s + 1] = e; perm[e] = e - 1; perm[e - 1] = s; s += 2; e -= 2; } if (s == e) perm[s] = s; if ((n % 4) > 1) cout << -1; else for (int i = 1; i <= n; i++) cout << perm[i] << ; }
|
#include <bits/stdc++.h> using namespace std; const int rozmiar_kubelka = 356; int n, m; vector<int> her; vector<pair<char, int> > mov; int dp[(1 << 20)]; void policz() { dp[0] = 0; int a = 1; for (; a < (1 << m); a++) { int c = __builtin_popcount(a); c = m - c; auto akt = mov[c]; if (akt.second == 1) dp[a] = -1000000000; else dp[a] = 1000000000; if (akt == make_pair( p , 1)) { int it = 0; for (int i = 1; true; i *= 2) { if (i & a) { dp[a] = dp[a ^ i] + her[it]; break; } it++; } } if (akt == make_pair( p , 2)) { int it = 0; for (int i = 1; true; i *= 2) { if (i & a) { dp[a] = dp[a ^ i] - her[it]; break; } it++; } } if (akt == make_pair( b , 1)) { int it = m - 1; for (int i = 1; i <= a; i *= 2) { it--; if (i & a) { dp[a] = max(dp[a], dp[a ^ i]); } } } if (akt == make_pair( b , 2)) { int it = m - 1; for (int i = 1; i <= a; i *= 2) { it--; if (i & a) { dp[a] = min(dp[a], dp[a ^ i]); } } } } } int main() { vector<int> vec; scanf( %d , &n); for (int i = 0; i < (n); ++i) { int a; scanf( %d , &a); vec.push_back(a); } scanf( %d , &m); sort(vec.begin(), vec.end()); for (int i = ((int)(n)) - 1; i >= (n - m); --i) her.push_back(vec[i]); for (int i = 0; i < (m); ++i) { char p; int a; scanf( %c%c%d , &p, &p, &a); mov.push_back({p, a}); } policz(); printf( %d , dp[(1 << m) - 1]); }
|
#include <bits/stdc++.h> int a[100010], b[100010]; bool check(int *a, int n, int id) { int cntt = 0; for (int i = 0; i < n; i++) { if (i == id) continue; b[cntt++] = a[i]; } if (cntt == 1) return true; for (int i = 1; i < cntt; i++) if (b[i - 1] == 0 && b[i] != 0) return false; if (cntt == 2) return true; for (int i = 1; i < cntt - 1; i++) { int num = b[i] * b[i]; if (num != b[i - 1] * b[i + 1]) return false; } return true; } bool check2(int *aa, int n) { for (int i = 0; i < n; i++) b[i] = aa[i]; int cntt = 0; if (b[0] == 0 && b[1] != 0) return false; if (b[1] == 0 && b[2] != 0) return false; if (b[1] * b[1] != b[0] * b[2]) return false; bool zero = true; int zeros = 0; for (int i = 0; i < 3; i++) { if (b[i] != 0) zero = false; else zeros++; } if (zeros != 0) { int cntt = 0; for (int i = 3; i < n; i++) if (b[i] != 0) cntt++; if (cntt == 1) return true; return false; } for (int i = 2; i < n; i++) { int next = b[i - 1] * b[i - 1]; if (next % b[i - 2] != 0) return false; next = next / b[i - 2]; if (next != b[i]) { cntt++; if (i != n - 1 && next != b[i + 1]) return false; i++; b[i - 1] = b[i - 2]; } } if (cntt == 1) return true; return false; } int main() { int n; while (scanf( %d , &n) == 1) { for (int i = 0; i < n; i++) scanf( %d , &a[i]); int zeros = 0; for (int i = 0; i < n; i++) if (a[i] == 0) zeros++; if (n == 1) { puts( 0 ); continue; } if (zeros == n) { puts( 0 ); continue; } if (zeros == n - 1 && a[0] == 0) { puts( 1 ); continue; } if (check(a, n, -1)) { puts( 0 ); continue; } if (check(a, n, 0) || check(a, n, 1) || check(a, n, 2)) { puts( 1 ); continue; } if (check2(a, n)) { puts( 1 ); continue; } puts( 2 ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int A[200005]; int lazy[600005], ma[600005], mi[600005]; long long sum[600005]; void push_up(int cur) { sum[cur] = sum[cur * 2] + sum[cur * 2 + 1]; ma[cur] = max(ma[cur * 2], ma[cur * 2 + 1]); mi[cur] = min(mi[cur * 2], mi[cur * 2 + 1]); } void push_down(int cur, int l, int r) { if (lazy[cur] == 0) return; int mid = (l + r) / 2; sum[cur * 2] = (lazy[cur] * 1ll * (mid - l + 1)); ma[cur * 2] = mi[cur * 2] = lazy[cur]; lazy[cur * 2] = lazy[cur]; sum[cur * 2 + 1] = (lazy[cur] * 1ll * (r - mid)); ma[cur * 2 + 1] = mi[cur * 2 + 1] = lazy[cur]; lazy[cur * 2 + 1] = lazy[cur]; lazy[cur] = 0; } int __ma; void build(int cur, int l, int r) { lazy[cur] = 0; __ma = max(__ma, cur); if (l == r) { sum[cur] = mi[cur] = ma[cur] = A[r]; return; } int mid = (l + r) / 2; build(cur * 2, l, mid); build(cur * 2 + 1, mid + 1, r); push_up(cur); } void modify_toMax(int cur, int l, int r, int cl, int cr, int Ma) { if (mi[cur] >= Ma) return; if (l >= cl && r <= cr) { if (ma[cur] <= Ma) { ma[cur] = mi[cur] = Ma; sum[cur] = Ma * 1ll * (r - l + 1); lazy[cur] = Ma; return; } } push_down(cur, l, r); int mid = (l + r) / 2; if (cl <= mid) modify_toMax(cur * 2, l, mid, cl, cr, Ma); if (cr > mid) modify_toMax(cur * 2 + 1, mid + 1, r, cl, cr, Ma); push_up(cur); } long long query_sum(int cur, int l, int r, int cl, int cr) { if (l >= cl && r <= cr) return sum[cur]; push_down(cur, l, r); int mid = (l + r) / 2; long long ans = 0; if (cl <= mid) ans += query_sum(cur * 2, l, mid, cl, cr); if (cr > mid) ans += query_sum(cur * 2 + 1, mid + 1, r, cl, cr); return ans; } int query_firSmallInd(int cur, int l, int r, int cl, int cr, int Ma) { if (mi[cur] > Ma) return -1; if (l == r) { if (ma[cur] <= Ma) return r; return -1; } push_down(cur, l, r); int mid = (l + r) / 2; if (cl <= mid) { int ind = query_firSmallInd(cur * 2, l, mid, cl, cr, Ma); if (ind != -1) return ind; } if (cr > mid) return query_firSmallInd(cur * 2 + 1, mid + 1, r, cl, cr, Ma); return -1; } int query_maxPresum(int cur, int l, int r, long long Ma) { if (l == r) { if (ma[cur] <= Ma) return r + 1; return r; } push_down(cur, l, r); int mid = (l + r) / 2; if (sum[cur * 2] <= Ma) return query_maxPresum(cur * 2 + 1, mid + 1, r, Ma - sum[cur * 2]); return query_maxPresum(cur * 2, l, mid, Ma); } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i += 1) scanf( %d , &A[i]); build(1, 1, n); int a, b, c; for (int i = 1; i <= m; i += 1) { scanf( %d%d%d , &a, &b, &c); if (a == 1) { modify_toMax(1, 1, n, 1, b, c); } else { int lef, rig, cur_ind = b, ans = 0; while (cur_ind <= n) { lef = query_firSmallInd(1, 1, n, cur_ind, n, c); if (lef == -1) break; long long pre = 0; if (lef > 1) pre = query_sum(1, 1, n, 1, lef - 1); rig = query_maxPresum(1, 1, n, pre + c); --rig; c -= query_sum(1, 1, n, lef, rig); ans += (rig - lef + 1); cur_ind = rig + 2; } printf( %d n , ans); } } return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file ramcart.v when simulating
// the core, ramcart. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module ramcart(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [14 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [12 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(15),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("ramcart.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32768),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(32768),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T, class U> bool cmp_second(const pair<T, U> &a, const pair<T, U> &b) { return a.second < b.second; } pair<int, int> operator+(const pair<int, int> &a, const pair<int, int> &b) { return make_pair(a.first + b.first, a.second + b.second); } pair<int, int> operator-(const pair<int, int> &a, const pair<int, int> &b) { return make_pair(a.first - b.first, a.second - b.second); } pair<int, int> &operator+=(pair<int, int> &a, const pair<int, int> &b) { a.first += b.first; a.second += b.second; return a; } pair<int, int> &operator-=(pair<int, int> &a, const pair<int, int> &b) { a.first -= b.first; a.second -= b.second; return a; } inline int sg(int x) { return x ? (x > 0 ? 1 : -1) : 0; } const double pi = acos(-1.0); int main(void) { double w, h, a; scanf( %lf %lf %lf , &w, &h, &a); if (a > 90.0) a = 180.0 - a; a = a / 180.0 * pi; double d = sqrt(w * w + h * h) * 0.5; double sol; if ((d * d + d * d - min(w, h) * min(w, h)) / (2 * d * d) <= cos(a)) { double A = 1 + cos(a); double B = sin(a); double x = (A * w - B * h) / (A * A - B * B); double y = (A * h - B * w) / (A * A - B * B); sol = w * h - (x * x + y * y) * sin(a) * cos(a); } else { double s = min(w, h); double z = s / sin(a); sol = z * z * sin(a); } printf( %.12lf n , sol); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_8_V
`define SKY130_FD_SC_LS__CLKBUF_8_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_8_V
|
module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 8;
parameter CFG_DBITS = 36;
parameter ABITS = 1;
parameter DBITS = 1;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
input CLK2;
input CLK3;
//Read data
output [CFG_DBITS-1:0] A1DATA;
input [CFG_ABITS-1:0] A1ADDR;
input A1EN;
//Write data
output [CFG_DBITS-1:0] B1DATA;
input [CFG_ABITS-1:0] B1ADDR;
input B1EN;
wire [CFG_DBITS-1:0] B1DATA_t;
localparam MODE = CFG_DBITS == 1 ? 1:
CFG_DBITS == 2 ? 2:
CFG_DBITS == 4 ? 3:
CFG_DBITS == 8 ? 4:
CFG_DBITS == 9 ? 5:
CFG_DBITS == 16 ? 6:
CFG_DBITS == 18 ? 7:
CFG_DBITS == 32 ? 8:
CFG_DBITS == 36 ? 9:
'bx;
localparam NUMWORDS = CFG_DBITS == 1 ? 8192:
CFG_DBITS == 2 ? 4096:
CFG_DBITS == 4 ? 2048:
CFG_DBITS == 8 ? 1024:
CFG_DBITS == 9 ? 1024:
CFG_DBITS == 16 ? 512:
CFG_DBITS == 18 ? 512:
CFG_DBITS == 32 ? 256:
CFG_DBITS == 36 ? 256:
'bx;
altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
.clock_enable_input_a ("ALTERNATE" ),
.clock_enable_output_b ("NORMAL" ),
.clock_enable_output_a ("NORMAL" ),
.wrcontrol_aclr_a ("NONE" ),
.indata_aclr_a ("NONE" ),
.address_aclr_a ("NONE" ),
.outdata_aclr_a ("NONE" ),
.outdata_reg_a ("UNREGISTERED"),
.operation_mode ("SINGLE_PORT" ),
.intended_device_family ("CYCLONE IVE" ),
.outdata_reg_a ("UNREGISTERED"),
.lpm_type ("altsyncram" ),
.init_type ("unused" ),
.ram_block_type ("AUTO" ),
.lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value
.power_up_uninitialized ("FALSE"),
.read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value
.width_byteena_a (1), // Forced value
.numwords_b ( NUMWORDS ),
.numwords_a ( NUMWORDS ),
.widthad_b ( CFG_DBITS ),
.width_b ( CFG_ABITS ),
.widthad_a ( CFG_DBITS ),
.width_a ( CFG_ABITS )
) _TECHMAP_REPLACE_ (
.data_a(B1DATA),
.address_a(B1ADDR),
.wren_a(B1EN),
.rden_a(A1EN),
.q_a(A1DATA),
.data_b(B1DATA),
.address_b(0),
.wren_b(1'b0),
.rden_b(1'b0),
.q_b(),
.clock0(CLK2),
.clock1(1'b1), // Unused in single port mode
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.aclr0(1'b0),
.aclr1(1'b0),
.addressstall_a(1'b0),
.addressstall_b(1'b0));
endmodule
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.2 (win64) Build Fri Jun 26 16:35:25 MDT 2015
//Date : Sun Mar 06 21:30:27 2016
//Host : raw-PC running 64-bit Service Pack 1 (build 7601)
//Command : generate_target system_wrapper.bd
//Design : system_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
btns_5bit_tri_i,
sw_8bit_tri_i);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [4:0]btns_5bit_tri_i;
input [7:0]sw_8bit_tri_i;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [4:0]btns_5bit_tri_i;
wire [7:0]sw_8bit_tri_i;
system system_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.btns_5bit_tri_i(btns_5bit_tri_i),
.sw_8bit_tri_i(sw_8bit_tri_i));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311AI_BLACKBOX_V
`define SKY130_FD_SC_LP__O311AI_BLACKBOX_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long double PI = acos(-1.0); template <typename T> T abs(T x) { return x > 0 ? x : -x; } template <typename T> T sqr(T x) { return x * x; } template <typename T> bool chmin(T &x, T y) { if (x > y) { x = y; return true; } return false; } template <typename T> bool chmax(T &x, T y) { if (x < y) { x = y; return true; } return false; } template <typename U, typename V> ostream &operator<<(ostream &s, const pair<U, V> &x) { s << ( << x.fst << , << x.snd << ) ; return s; } template <typename U> ostream &operator<<(ostream &s, const vector<U> &x) { s << [ ; bool was = false; for (auto it : x) { if (was) { s << , ; } was = true; s << it; } s << ] ; return s; } template <typename U> ostream &operator<<(ostream &s, const set<U> &x) { s << { ; bool was = false; for (auto it : x) { if (was) { s << , ; } was = true; s << it; } s << } ; return s; } template <int sz> ostream &operator<<(ostream &s, const bitset<sz> &x) { for (int i = 0; i < sz; i++) { s << x[i]; } return s; } int main() { srand(time(0)); int k; cin >> k; int maxi = 25; while (k--) { int p; cin >> p; chmax(maxi, p); } cout << maxi - 25 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; using VI = vector<int>; const int NN = 200011; int a[NN], b[NN], arr[NN]; VI vec[NN], cyc[NN]; int nc; int dp[NN], vst[NN]; int n, s; void dfs(int u) { while (not vec[u].empty()) { int v = vec[u].back(); vec[u].pop_back(); dfs(a[v]); cyc[nc].push_back(v); } } int solve() { cin >> n >> s; for (int i = 1; i <= n; i++) scanf( %d , a + i), arr[i] = a[i], dp[i] = i; sort(arr + 1, arr + n + 1); int m = unique(arr + 1, arr + n + 1) - arr - 1; for (int i = 1; i <= n; i++) { b[i] = a[i] = lower_bound(arr + 1, arr + m + 1, a[i]) - arr; } sort(b + 1, b + n + 1); for (int i = 1; i <= n; i++) if (a[i] ^ b[i]) { vec[b[i]].push_back(i); } for (int i = 1; i <= m; i++) { if (not vec[i].empty()) { dfs(i); int r = ((int)cyc[nc].size()); for (int j = 0; j < r; j++) { dp[cyc[nc][(j + 1) % r]] = cyc[nc][j]; s--; } nc++; } if (s < 0) return puts( -1 ); } s = min(s, nc); if (s >= 2) { cout << nc - s + 2 << endl; cout << s << endl; for (int i = 0; i < s; i++) printf( %d , cyc[i][0]); puts( ); int tmp = dp[cyc[s - 1][0]]; for (int i = s; --i;) { dp[cyc[i][0]] = dp[cyc[i - 1][0]]; } dp[cyc[0][0]] = tmp; } else cout << nc << endl; for (int i = 1; i <= n; i++) { if (dp[i] == i or vst[i]) continue; VI ans; for (int u = i; not vst[u];) { ans.push_back(u); vst[u] = 1; u = dp[u]; } printf( %d n , ans.size()); for (int u : ans) printf( %d , u); puts( ); } } int main() { solve(); }
|
module helloworld (
input clk,
input rst,
output [7:0] tx_data,
output reg new_tx_data,
input tx_busy,
input [7:0] rx_data,
input new_rx_data
);
localparam STATE_SIZE = 1;
localparam IDLE = 0,
PRINT_MESSAGE = 1;
localparam MESSAGE_LEN = 23;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [4:0] addr_d, addr_q;
rom_helloworld rom_helloworld (
.clk(clk),
.addr(addr_q),
.data(tx_data)
);
always @(*) begin
state_d = state_q; // default values
addr_d = addr_q; // needed to prevent latches
new_tx_data = 1'b0;
case (state_q)
IDLE: begin
addr_d = 4'd0;
if (new_rx_data && rx_data == "h")
state_d = PRINT_MESSAGE;
end
PRINT_MESSAGE: begin
if (!tx_busy) begin
new_tx_data = 1'b1;
addr_d = addr_q + 1'b1;
if (addr_q == MESSAGE_LEN-1)
state_d = IDLE;
end
end
default: state_d = IDLE;
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
addr_q <= addr_d;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; constexpr long long ROWS = 2; constexpr long long NMAX = 1e5; long long h[ROWS][NMAX]; long long dp[ROWS][NMAX]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long COLS; cin >> COLS; for (long long i = 0; i < ROWS; ++i) for (long long j = 0; j < COLS; ++j) cin >> h[i][j]; for (long long j = COLS - 1; j >= 0; --j) for (long long i = ROWS - 1; i >= 0; --i) { if (j == COLS - 1) dp[i][j] = h[i][j]; else if (j == COLS - 2) dp[i][j] = h[i][j] + h[i == 0 ? 1 : 0][j + 1]; else dp[i][j] = h[i][j] + max(dp[i == 0 ? 1 : 0][j + 1], dp[i == 0 ? 1 : 0][j + 2]); } cout << max(dp[0][0], dp[1][0]); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:11:08 08/25/2014
// Design Name:
// Module Name: conled
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module conled(
input clk,
output led0,
output led1,
output led2,
output led3,
output led4,
output led5
);
reg [25:0] counter;
reg [5:0] ledout;
//assign {led0,led1,led2,led3,led4,led5}=ledout;
assign {led0,led1,led2,led3,led4,led5}=6'b111111;
//generate 0,25,50,75, and 100% duty cycle signals
assign duty0=0;
assign duty1=counter[15]&counter[16]&counter[17];
assign duty2=counter[15]&counter[16];
assign duty3=counter[15];
assign duty4=1;
always @(posedge clk)
begin
//increment counter
counter<=counter+1;
//use high 3 bits as state, translate duty cycle accordingly
case (counter[25:23])
3'b000:ledout={duty0,duty4,duty3,duty2,duty1,duty0};
3'b001:ledout={duty4,duty3,duty2,duty1,duty0,duty0};
3'b010:ledout={duty3,duty2,duty1,duty0,duty0,duty0};
3'b011:ledout={duty2,duty1,duty0,duty0,duty0,duty0};
3'b100:ledout={duty1,duty0,duty0,duty0,duty0,duty4};
3'b101:ledout={duty0,duty0,duty0,duty0,duty4,duty3};
3'b110:ledout={duty0,duty0,duty0,duty4,duty3,duty2};
default:ledout={duty0,duty0,duty4,duty3,duty2,duty1};
// 3'b000:ledout={duty0,duty1,duty2,duty3,duty4,duty3};
// 3'b001:ledout={duty1,duty2,duty3,duty4,duty3,duty2};
// 3'b010:ledout={duty2,duty3,duty4,duty3,duty2,duty1};
// 3'b011:ledout={duty3,duty4,duty3,duty2,duty1,duty0};
// 3'b100:ledout={duty4,duty3,duty2,duty1,duty0,duty1};
// 3'b101:ledout={duty3,duty2,duty1,duty0,duty1,duty2};
// 3'b110:ledout={duty2,duty1,duty0,duty1,duty2,duty3};
// default:ledout={duty1,duty0,duty1,duty2,duty3,duty4};
endcase
end
endmodule
|
//a ruidmentary credit tracker for an entire router
module vcr_ugal_sniffer(/*autoarg*/
// Outputs
credit_count,
// Inputs
clk, reset, flit_ctrl, flow_ctrl
);
`include "c_functions.v"
`include "c_constants.v"
`include "vcr_constants.v"
// flit buffer entries per VC
parameter num_flit_buffers = 8;
// number of message classes (e.g. request, reply)
parameter num_message_classes = 1;
// nuber of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs per class
parameter num_vcs_per_class = 1;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// select packet format
parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + vc_idx_width + 1 + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + vc_idx_width + 1) :
-1;
// width of flow control signals
localparam flow_ctrl_width = 1 + vc_idx_width;
parameter reset_type = `RESET_TYPE_ASYNC;
parameter topology = `TOPOLOGY_FBFLY;
// total number of nodes
parameter num_nodes = 64;
// number of dimensions in network
parameter num_dimensions = 2;
// number of nodes per router (a.k.a. concentration factor)
parameter num_nodes_per_router = 4;
// total number of routers
localparam num_routers
= (num_nodes + num_nodes_per_router - 1) / num_nodes_per_router;
// number of routers in each dimension
localparam num_routers_per_dim = croot(num_routers, num_dimensions);
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= (topology == `TOPOLOGY_MESH) ?
2 :
(topology == `TOPOLOGY_FBFLY) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
localparam credit_count_width = clogb(num_vcs*num_flit_buffers)+1;
input clk;
input reset;
input [0:(num_ports-num_nodes_per_router)*flit_ctrl_width-1] flit_ctrl;
//this could be improved by grabbing the flow_ctrl after the flipflop,a dn not directly from the channels
input [0:(num_ports-num_nodes_per_router)*flow_ctrl_width-1] flow_ctrl;
output [0:(num_ports-num_nodes_per_router)*credit_count_width-1] credit_count;
generate
genvar port;
for(port = 0; port<num_ports-num_nodes_per_router; port=port+1)
begin:ports
wire [0:credit_count_width-1] count_q;
wire [0:credit_count_width-1] count_s;
c_dff
#(
// Parameters
.width (credit_count_width),
.reset_type (reset_type))
credit_ff
(
// Outputs
.q (count_q[0:credit_count_width-1]),
// Inputs
.clk (clk),
.reset (reset),
.d (count_s[0:credit_count_width-1]));
assign count_s = count_q
+flit_ctrl[port*flit_ctrl_width]
-flow_ctrl[port*flow_ctrl_width];
assign credit_count [port*credit_count_width:(port+1)*credit_count_width-1] = count_q[0:credit_count_width-1];
end
endgenerate
endmodule // vcr_ugal_sniffer
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND4_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100000 + 10; const long long CONST = 314000000LL; const long long inf = (1LL << 60); bool mark[MAXN], INF[MAXN], bad[MAXN]; int m, n, cntComp; long long cnt[MAXN], func[MAXN], deg[MAXN], comp[MAXN], type[MAXN], len[MAXN]; long long mini[MAXN], maxi[MAXN]; vector<int> topol; vector<int> adj[MAXN], bak[MAXN], Q[MAXN]; struct cmp { inline bool operator()(const int &A, const int &B) { return (mini[A] != mini[B]) ? (mini[A] < mini[B]) : (A < B); } }; inline void dfs(int v) { if (mini[v] == inf) return; mark[v] = true; for (int i = 0; i < (int)adj[v].size(); i++) if (!mark[adj[v][i]] && mini[adj[v][i]] != inf) dfs(adj[v][i]); topol.push_back(v); } inline void DFS(int v) { if (mini[v] == inf) return; mark[v] = true; comp[v] = cntComp; for (int i = 0; i < (int)bak[v].size(); i++) if (!mark[bak[v][i]] && mini[bak[v][i]] != inf) DFS(bak[v][i]); } inline bool cmp2(const int &A, const int &B) { return comp[type[A]] > comp[type[B]]; } int main() { cin >> m >> n; for (int i = 0; i < m; i++) { cin >> type[i] >> len[i]; type[i]--; for (int j = 0; j < len[i]; j++) { int temp; cin >> temp; if (temp == -1) deg[i]++, func[i]++; else { temp--; Q[i].push_back(temp); bak[temp].push_back(i); cnt[i]++; } } } for (int i = 0; i < n; i++) mini[i] = inf; set<int, cmp> SET; for (int i = 0; i < m; i++) if (cnt[i] == 0) { if (deg[i] < mini[type[i]]) { SET.erase(type[i]); mini[type[i]] = deg[i]; SET.insert(type[i]); } } while (!SET.empty()) { int begin = *SET.begin(); SET.erase(SET.begin()); for (int i = 0; i < (int)bak[begin].size(); i++) { int temp = bak[begin][i]; cnt[temp]--; deg[temp] = min(CONST, deg[temp] + mini[begin]); if (cnt[temp] == 0) { if (deg[temp] < mini[type[temp]]) { SET.erase(type[temp]); mini[type[temp]] = deg[temp]; SET.insert(type[temp]); } } } } for (int i = 0; i < n; i++) adj[i].clear(), bak[i].clear(); for (int i = 0; i < m; i++) if (mini[type[i]] != inf) { bad[i] = false; for (int j = 0; j < (int)Q[i].size(); j++) if (mini[Q[i][j]] == inf) bad[i] = true; if (!bad[i]) { for (int j = 0; j < (int)Q[i].size(); j++) { adj[type[i]].push_back(Q[i][j]); bak[Q[i][j]].push_back(type[i]); } } } for (int i = 0; i < n; i++) if (!mark[i]) dfs(i); memset(mark, false, sizeof mark); for (int i = (int)topol.size() - 1; i >= 0; i--) if (!mark[topol[i]]) { cntComp++; DFS(topol[i]); } vector<int> perm; for (int i = 0; i < m; i++) perm.push_back(i); sort(perm.begin(), perm.end(), cmp2); for (int o = 0; o < m; o++) if (!bad[perm[o]]) { int index = perm[o]; long long sum = min(CONST, func[index]); for (int j = 0; j < (int)Q[index].size(); j++) { int temp = Q[index][j]; if (comp[temp] == comp[type[index]]) INF[comp[type[index]]] = true; else if (INF[comp[temp]]) INF[comp[type[index]]] = true; else sum = min(CONST, sum + maxi[temp]); } maxi[type[index]] = max(maxi[type[index]], sum); } for (int i = 0; i < n; i++) { if (mini[i] == inf) { cout << -1 << << -1 << endl; continue; } cout << min(CONST, mini[i]) << ; if (INF[comp[i]]) cout << -2 << endl; else cout << min(CONST, maxi[i]) << endl; } return 0; }
|
// DESCRIPTION: Verilator: Unsupported tristate constructur error
//
// This is a compile only regression test of tristate handling for bug514
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Rob Stoddard.
module t (/*AUTOARG*/
// Outputs
out,
// Inputs
data, up_down, clk, reset
);
//----------Output Ports--------------
output [7:0] out;
//------------Input Ports--------------
//input [7:0] data ;
input [7:0] data;
input up_down, clk, reset;
//------------Internal Variables--------
reg [7:0] out;
logic [7:0] q_out;
//-------------Code Starts Here-------
always @(posedge clk)
if (reset) begin // active high reset
out <= 8'b0 ;
end else if (up_down) begin
out <= out + 1;
end else begin
out <= q_out;
end
// verilator lint_off PINMISSING
sub_mod sub_mod
(
.clk(clk),
.data(data),
.reset(reset),
.q(q_out)
);
// verilator lint_on PINMISSING
endmodule
module sub_mod (/*AUTOARG*/
// Outputs
q, test_out,
// Inouts
test_inout,
// Inputs
data, clk, reset
);
//-----------Input Ports---------------
input [7:0] data /*verilator public*/;
input clk, reset;
inout test_inout; // Get rid of this, the problem goes away.
//-----------Output Ports---------------
output [7:0] q;
output test_out; // Not assigned, no problem.
logic [7:0] que;
// Uncomment this line, the error goes away.
//assign test_inout = que;
assign q = que;
always @ ( posedge clk)
if (~reset) begin
que <= 8'b0;
end else begin
que <= data;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { return x > 0 ? x : (-x); } template <class T> T sqr(T x) { return x * x; } const double eps = 1E-8; struct P { double x, y; P(double x = 0.0, double y = 0.0) : x(x), y(y) {} P operator+(P a) { return P(x + a.x, y + a.y); } P operator-(P a) { return P(x - a.x, y - a.y); } P operator*(double k) { return P(x * k, y * k); } double operator*(P a) { return x * a.y - y * a.x; } double operator^(P a) { return x * a.x + y * a.y; } double len() { return sqrt(x * x + y * y); } P perp() { return P(y, -x); } P norm() { double l = len(); return abs(l) < eps ? P(x, y) : P(x / l, y / l); } bool operator==(P a) { return abs(x - a.x) < eps && abs(y - a.y) < eps; } void load() { cin >> x >> y; } }; int sgn(double x) { if (x > eps) return 1; if (x < -eps) return -1; return 0; } bool pointOnSegment(P p, P a, P b) { if (abs((a - p) * (b - p)) > eps) return false; return ((a - p) ^ (b - p)) < eps; } bool crossSegments1d(double a, double aa, double b, double bb) { return min(a, aa) < max(b, bb) + eps && min(b, bb) < max(a, aa) + eps; } bool crossSegments(P a, P aa, P b, P bb) { if (sgn((b - a) * (aa - a)) * sgn((aa - a) * (bb - a)) < 0) return false; if (sgn((a - b) * (bb - b)) * sgn((bb - b) * (aa - b)) < 0) return false; return crossSegments1d(a.x, aa.x, b.x, bb.x) && crossSegments1d(a.y, aa.y, b.y, bb.y); } struct L { double a, b, c; L(double a = 0.0, double b = 0.0, double c = 0.0) : a(a), b(b), c(c) {} bool operator||(L l) { return abs(a * l.b - b * l.a) < eps; } }; L getLine(P p1, P p2) { double x0 = p1.x, y0 = p1.y; double al = (p2 - p1).x, be = (p2 - p1).y; return L(be, -al, al * y0 - be * x0); } P getPoint(L l1, L l2) { double det = l1.a * l2.b - l1.b * l2.a; double det1 = -(l1.c * l2.b - l1.b * l2.c); double det2 = -(l1.a * l2.c - l1.c * l2.a); return P(det1 / det, det2 / det); } double h, f; pair<double, double> calc1(double y, double x1, double x2) { double l = x1 * (f - y) / (f - h); double r = x2 * (f - y) / (f - h); return make_pair(l, r); } pair<double, double> calc2(double y, double x1, double x2) { double l = x1 * (y + f) / (f - h); double r = x2 * (y + f) / (f - h); return make_pair(l, r); } int main() { int n; cin >> n; cin >> h >> f; vector<pair<int, int> > v(n); double res = 0.0; for (int i = 0; i < n; ++i) { scanf( %d%d , &v[i].first, &v[i].second); double l = abs(v[i].second - v[i].first); res += 2. * h * (l + l * (f + h) / (f - h)); } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { vector<P> V; L l11 = getLine(P(0, f), P(v[i].first, h)); L l12 = getLine(P(0, f), P(v[i].second, h)); L l21 = getLine(P(0, -f), P(v[j].first, -h)); L l22 = getLine(P(0, -f), P(v[j].second, -h)); if (!(l11 || l21)) V.push_back(getPoint(l11, l21)); if (!(l11 || l22)) V.push_back(getPoint(l11, l22)); if (!(l12 || l21)) V.push_back(getPoint(l12, l21)); if (!(l12 || l22)) V.push_back(getPoint(l12, l22)); vector<double> ev; ev.push_back(-h); ev.push_back(-h); ev.push_back(h); ev.push_back(h); for (int k = 0; k < ((int)(V).size()); ++k) { if (abs(V[k].y) < h + eps) ev.push_back(V[k].y); } sort((ev).begin(), (ev).end()); double cur = 0; double st = 0.0; for (int k = 1; k < ((int)(ev).size()); ++k) { pair<double, double> p = calc1(ev[k], v[i].first, v[i].second); pair<double, double> q = calc2(ev[k], v[j].first, v[j].second); double l = max(p.first, q.first); double r = min(p.second, q.second); double t = max(0.0, r - l); cur += (t + st) * 0.5 * (ev[k] - ev[k - 1]); st = t; } res -= abs(cur); } } printf( %.10lf n , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; char str[1000005 + 1]; int main() { int ans = 0, i; stack<int> S; scanf( %s , str); for (i = 0; str[i] != 0 ; ++i) { if (str[i] == ( ) S.push(i); if (str[i] == ) && !S.empty()) { S.pop(); ans += 2; } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long dp[1010][105], po[1010], po2[1010]; long long qui(long long a, long long n, long long m) { long long ans = 1; while (n) { if (n & 1) ans = (ans * a) % m; n >>= 1; a = (a * a) % m; } return ans; }; int main() { long long n, k, m; while (cin >> n >> k >> m) { po[0] = 1; for (int i = 1; i <= n; i++) po[i] = (po[i - 1] * 10) % m; po2[0] = 1; for (int i = 1; i <= n; i++) po2[i] = (po2[i - 1] * 10) % k; long long sum = 0; memset(dp, 0, sizeof(dp)); for (int i = 1; i < 10; i++) dp[1][i % k]++; if (n >= 2) sum = (sum + dp[1][0] * 9 * po[n - 2]) % m; for (int i = 1; i < n - 1; i++) { for (int j = 1; j < k; j++) for (int x = 0; x < 10; x++) dp[i + 1][(j + x * po2[i]) % k] = (dp[i + 1][(j + x * po2[i]) % k] + dp[i][j]) % m; for (int x = 1; x < 10; x++) dp[i + 1][x * po2[i] % k] = (dp[i + 1][x * po2[i] % k] + 1) % m; sum = (sum + ((dp[i + 1][0] * 9) % m) * po[n - i - 2]) % m; } if (n >= 2) { for (int j = 1; j < k; j++) for (int x = 1; x < 10; x++) dp[n][(j + x * po2[n - 1]) % k] = (dp[n][(j + x * po2[n - 1]) % k] + dp[n - 1][j]) % m; for (int x = 1; x < 10; x++) dp[n][x * po2[n - 1] % k] = (dp[n][x * po2[n - 1] % k] + 1) % m; } sum = (sum + dp[n][0] % m) % m; cout << sum << endl; } return 0; }
|
// cog_vid
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module cog_vid
(
input clk_cog,
input clk_vid,
input ena,
input setvid,
input setscl,
input [31:0] data,
input [31:0] pixel,
input [31:0] color,
input [7:0] aural,
input carrier,
output ack,
output [31:0] pin_out
);
// configuration
reg [31:0] vid;
reg [31:0] scl;
always @(posedge clk_cog or negedge ena)
if (!ena)
vid <= 32'b0;
else if (setvid)
vid <= data;
always @(posedge clk_cog)
if (setscl)
scl <= data;
// video shifter
reg [7:0] cnts;
reg [7:0] cnt;
reg [11:0] set;
reg [31:0] pixels;
reg [31:0] colors;
wire enable = |vid[30:29];
wire vclk = clk_vid && enable;
wire new_set = set == 1'b1;
wire new_cnt = cnt == 1'b1;
always @(posedge vclk)
if (new_set)
cnts <= scl[19:12];
always @(posedge vclk)
cnt <= new_set ? scl[19:12]
: new_cnt ? cnts
: cnt - 1'b1;
always @(posedge vclk)
set <= new_set ? scl[11:0]
: set - 1'b1;
always @(posedge vclk)
if (new_set || new_cnt)
pixels <= new_set ? pixel
: vid[28] ? {pixels[31:30], pixels[31:2]}
: {pixels[31], pixels[31:1]};
always @(posedge vclk)
if (new_set)
colors <= color;
// capture/acknowledge
reg cap;
reg [1:0] snc;
always @(posedge vclk or posedge snc[1])
if (snc[1])
cap <= 1'b0;
else if (new_set)
cap <= 1'b1;
always @(posedge clk_cog)
if (enable)
snc <= {snc[0], cap};
assign ack = snc[0];
// discrete output
reg [7:0] discrete;
wire [31:0] colorx = colors >> {vid[28] && pixels[1], pixels[0], 3'b000};
always @(posedge vclk)
discrete <= colorx[7:0];
// baseband output
//
// +-------------------------------+
// out 7 ! - + * !
// 6 ! + * - !
// 5 ! + * - !
// 4 ! + * - !
// 3 ! + * - !
// 2 ! + * - !
// 1 ! + * - !
// 0 ! * - + !
// +-------------------------------+
// in 0 1 2 3 4 5 6 7
reg [3:0] phase;
reg [3:0] baseband;
always @(posedge vclk)
phase <= phase + 1'b1;
wire [3:0] colorphs = discrete[7:4] + phase;
wire [2:0] colormod = discrete[2:0] + { discrete[3] && colorphs[3],
discrete[3] && colorphs[3],
discrete[3] };
always @(posedge vclk)
baseband <= {discrete[3] && colorphs[3], vid[26] ? colormod : discrete[2:0]};
// broadcast output
//
// +-------------------------------+
// out 7 ! * !
// 6 ! * * !
// 5 ! * * !
// 4 ! * * !
// 3 ! * * !
// 2 ! * * !
// 1 ! * * !
// 0 ! * * !
// +-------------------------------+
// in 0 1 2 3 4 5 6 7
reg [2:0] composite;
always @(posedge vclk)
composite <= vid[27] ? colormod : discrete[2:0];
wire [15:0][2:0] level = 48'b011_100_100_101_101_110_110_111_011_011_010_010_001_001_000_000;
wire [3:0] broadcast = {carrier ^ aural[vid[25:23]], level[{carrier, composite}]};
// output pins
wire [7:0] outp = vid[30] ? vid[29] ? {baseband, broadcast}
: {broadcast, baseband}
: discrete;
assign pin_out = enable ? {24'b0, outp & vid[7:0]} << {vid[10:9], 3'b000} : 32'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; double dp[200 + 50][200 + 50][200 + 50]; double p[200 + 50]; double res; int a[200 + 50]; int n, l, x, kol; int main() { scanf( %d%d%d , &n, &l, &kol); for (int i = 1; i <= n; i++) { scanf( %d , &x); p[i] = (x + 0.0) / 100; } for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); a[i]++; } memset(dp, 0, sizeof(dp)); dp[0][0][0] = 1; for (int i = 0; i < n; i++) { for (int j = 0; j <= i; j++) { for (int k = 0; k <= n; k++) { dp[i + 1][j + 1][min(n, k + a[i + 1])] += dp[i][j][k] * p[i + 1]; dp[i + 1][j][k] += dp[i][j][k] * (1 - p[i + 1]); } } } res = 0; for (int i = l; i <= n; i++) { for (int j = max(0, l - kol); j <= n; j++) { if (i <= j + kol) res += dp[n][i][j]; } } printf( %llf , res); return 0; }
|
module opicorv32_alu_wrap (
is_lui_auipc_jal_jalr_addi_add,
is_slti_blt_slt,
is_sltiu_bltu_sltu,
is_compare,
instr_beq,
instr_bne,
instr_bge,
instr_bgeu,
instr_xori,
instr_ori,
instr_andi,
instr_sub,
instr_xor,
instr_or,
instr_and,
reg_op2,
reg_op1,
alu_out,
alu_out_0
);
input is_lui_auipc_jal_jalr_addi_add;
input is_slti_blt_slt;
input is_sltiu_bltu_sltu;
input is_compare;
input instr_beq;
input instr_bne;
input instr_bge;
input instr_bgeu;
input instr_xori;
input instr_ori;
input instr_andi;
input instr_sub;
input instr_xor;
input instr_or;
input instr_and;
input [31:0] reg_op2;
input [31:0] reg_op1;
output [31:0] alu_out;
output alu_out_0;
/* signal declarations */
wire _1285;
wire _1283;
wire compare_alu_out_0;
wire _1287;
wire [32:0] _1241;
wire [31:0] _1288;
wire [5:0] _1279 = 6'b000000;
wire [3:0] _1274 = 4'b0000;
wire [14:0] _1280;
wire [3:0] _1270 = 4'b0000;
wire gnd = 1'b0;
wire [10:0] _1267 = 11'b00000000000;
wire [3:0] _1257 = 4'b0000;
wire [2:0] _1254 = 3'b000;
wire [1:0] _1252 = 2'b00;
wire [10:0] _1251 = 11'b00000000000;
wire [47:0] _1271;
wire [32:0] _1282;
wire [31:0] _1284;
wire [31:0] compare_alu_out;
wire [31:0] _1290;
/* logic */
assign _1285 = _1241[32:32];
assign _1283 = _1282[32:32];
assign compare_alu_out_0 = _1283 ^ _1285;
assign _1287 = compare_alu_out_0 ^ _1285;
picorv32_alu
the_picorv32_alu
( .reg_op1(reg_op1), .reg_op2(reg_op2), .instr_beq(instr_beq), .instr_bne(instr_bne), .instr_bge(instr_bge), .instr_bgeu(instr_bgeu), .instr_sub(instr_sub), .instr_xori(instr_xori), .instr_xor(instr_xor), .instr_ori(instr_ori), .instr_or(instr_or), .instr_andi(instr_andi), .instr_and(instr_and), .is_compare(is_compare), .is_slti_blt_slt(is_slti_blt_slt), .is_sltiu_bltu_sltu(is_sltiu_bltu_sltu), .is_lui_auipc_jal_jalr_addi_add(is_lui_auipc_jal_jalr_addi_add), .alu_out_0(_1241[32:32]), .alu_out(_1241[31:0]) );
assign _1288 = _1241[31:0];
assign _1280 = { gnd, is_compare, _1274, is_sltiu_bltu_sltu, is_slti_blt_slt, is_lui_auipc_jal_jalr_addi_add, _1279 };
assign _1271 = { _1251, instr_and, instr_or, _1252, instr_xor, _1254, instr_sub, _1257, instr_andi, instr_ori, instr_xori, _1267, instr_bgeu, gnd, instr_bge, gnd, instr_bne, instr_beq, _1270 };
opicorv32_alu
the_opicorv32_alu
( .reg_op1(reg_op1), .reg_op2(reg_op2), .instr(_1271), .is(_1280), .alu_out_0(_1282[32:32]), .alu_out(_1282[31:0]) );
assign _1284 = _1282[31:0];
assign compare_alu_out = _1284 ^ _1288;
assign _1290 = compare_alu_out ^ _1288;
/* aliases */
/* output assignments */
assign alu_out = _1290;
assign alu_out_0 = _1287;
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_async_reg
*/
module test_wb_async_reg;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg wbm_clk = 0;
reg wbm_rst = 0;
reg wbs_clk = 0;
reg wbs_rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(wbm_clk,
wbm_rst,
wbs_clk,
wbs_rst,
current_test,
wbm_adr_i,
wbm_dat_i,
wbm_we_i,
wbm_sel_i,
wbm_stb_i,
wbm_cyc_i,
wbs_dat_i,
wbs_ack_i,
wbs_err_i,
wbs_rty_i);
$to_myhdl(wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbm_rty_o,
wbs_adr_o,
wbs_dat_o,
wbs_we_o,
wbs_sel_o,
wbs_stb_o,
wbs_cyc_o);
// dump file
$dumpfile("test_wb_async_reg.lxt");
$dumpvars(0, test_wb_async_reg);
end
wb_async_reg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.wbm_clk(wbm_clk),
.wbm_rst(wbm_rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_clk(wbs_clk),
.wbs_rst(wbs_rst),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100005; int n, m; int t[MAX_N], x[MAX_N]; int nxt; int idx[MAX_N]; int res[MAX_N]; bool mycmp(const int a, const int b) { if (x[a] != x[b]) return x[a] < x[b]; return a < b; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) scanf( %d%d , &t[i], &x[i]); int time = 0; for (int step = 0; step < n; step += m) { nxt = 0; for (int i = step; i < min(step + m, n); ++i) idx[nxt++] = i; time += max(0, t[idx[nxt - 1]] - time); sort(idx, idx + nxt, mycmp); for (int i = 0; i < nxt;) { int j = i; for (; j < nxt && x[idx[i]] == x[idx[j]]; ++j) ; time += x[idx[i]]; if (i > 0) time -= x[idx[i - 1]]; for (int k = i; k < j; ++k) res[idx[k]] = time; time += 1 + (j - i) / 2; i = j; } time += x[idx[nxt - 1]]; } printf( %d , res[0]); for (int i = 1; i < n; ++i) printf( %d , res[i]); printf( n ); return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dp_ram.v when simulating
// the core, dp_ram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dp_ram(
s_aclk,
s_aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
axis_data_count
);
input s_aclk;
input s_aresetn;
input s_axis_tvalid;
output s_axis_tready;
input [7 : 0] s_axis_tdata;
output m_axis_tvalid;
input m_axis_tready;
output [7 : 0] m_axis_tdata;
output [11 : 0] axis_data_count;
endmodule
|
// finding a state for which valid=0 in the design below takes 26.5 second on ifv:
module lfsr15(clk, rst, ena, state);
// period = 32767
input clk, rst, ena;
output [14:0] state;
reg [14:0] state;
always @(posedge rst or posedge clk) begin
if (rst == 1) begin
state <= 1;
end else if (ena) begin
state[14:1] <= state[13:0];
state[0] <= state[13] ^ state[14];
end
end
endmodule
module lfsr13(clk, rst, ena, state);
// period = 8191
input clk, rst, ena;
output [12:0] state;
reg [12:0] state;
always @(posedge rst or posedge clk) begin
if (rst == 1) begin
state <= 1;
end else if (ena) begin
state[12:1] <= state[11:0];
state[0] <= state[7] ^ state[10] ^ state[11] ^ state[12];
end
end
endmodule
module lfsr12(clk, rst, ena, state);
// period = 4095
input clk, rst, ena;
output [11:0] state;
reg [11:0] state;
always @(posedge rst or posedge clk) begin
if (rst == 1) begin
state <= 1;
end else if (ena) begin
state[11:1] <= state[10:0];
state[0] <= state[3] ^ state[9] ^ state[10] ^ state[11];
end
end
endmodule
module lfsr4(clk, rst, ena, state);
// period = 15
input clk, rst, ena;
output [3:0] state;
reg [3:0] state;
always @(posedge rst or posedge clk) begin
if (rst == 1) begin
state <= 1;
end else if (ena) begin
state[3:1] <= state[2:0];
state[0] <= state[2] ^ state[3];
end
end
endmodule
module top (clk, rst, code, err, secret, state);
input clk, rst;
output err;
input [14:0] code;
output [11:0] state;
lfsr12 u1 (clk, rst, ena, state);
output [14:0] secret;
//lfsr13 u2 (clk, rst, ena, secret);
lfsr15 u2 (clk, rst, ena, secret);
wire ena;
assign ena = (code == secret);
assign err = state != 'b100000000000;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, t, ma, sum = 0; std::string s[1000]; cin >> n >> k; for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < k; i++) { cin >> t; ma = 1; map<char, int> m; for (int j = 0; j < n; j++) m[s[j][i]]++; for (map<char, int>::iterator it = m.begin(); it != m.end(); it++) ma = max(ma, it->second); sum += ma * t; } cout << sum; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [15:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// instantiations
ad_iobuf #(
.DATA_WIDTH(16)
) i_gpio_bd (
.dio_t(gpio_t[15:0]),
.dio_i(gpio_o[15:0]),
.dio_o(gpio_i[15:0]),
.dio_p(gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.ps_intr_13 (1'b0),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 1005; char a[MaxN]; int b[MaxN]; bool prime(int x) { for (int i = 2; i < x / 2; i++) { if (x % 2 == 0) { return false; } } return true; } int main() { string s; int i, n, Max, j; char v; Max = 0; for (i = 0; i < MaxN; i++) { a[i] = ; b[i] = 0; } cin >> s; for (i = 0; i < s.length(); i++) { b[s[i]]++; if (b[s[i]] > Max) { Max = b[s[i]]; v = s[i]; } } for (i = 2; i <= s.length(); i++) { if (prime(i)) { if (i == 2) { int ind = 1; while (ind * i <= s.length()) { if (a[ind * i] == ) { a[ind * i] = (char)v; b[v]--; if (b[v] < 0) { cout << NO << endl; return 0; } } ind++; } } else { if (i * 2 <= s.length()) { int ind = 1; while (ind * i <= s.length()) { if (a[ind * i] == ) { a[ind * i] = (char)v; b[v]--; if (b[v] < 0) { cout << NO << endl; return 0; } } ind++; } } } } } cout << YES << endl; for (i = 1; i <= s.length(); i++) { if (a[i] == ) { for (j = 0; j < MaxN; j++) { if (b[j]) { a[i] = (char)j; b[j]--; break; } } } cout << a[i]; } cin.get(); cin.get(); }
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; int n, k, p; int odd[N], even[N], po, pe; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> n >> k >> p; for (int i = 0; i < n; ++i) { int x; cin >> x; if (x & 1) odd[po++] = x; else even[pe++] = x; } int no = po, ne = pe; int more = no - (k - p); if (k > n || no < k - p || more & 1 || pe + more / 2 < p) cout << NO << endl; else { cout << YES << endl; int tot_odd = min(k - p, k - 1); for (int i = 0; i < tot_odd; ++i) cout << 1 << << odd[--po] << endl; int tot_even = min(p, k - 1 - tot_odd); int use_even = min(tot_even, pe); for (int i = 0; i < use_even; ++i) cout << 1 << << even[--pe] << endl; for (int i = use_even; i < tot_even; ++i) cout << 2 << << odd[--po] << << odd[--po] << endl; int t = po + pe; cout << t; while (po) cout << << odd[--po]; while (pe) { cout << << even[--pe]; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300000 + 3000; int n, m; int a[maxn], l[maxn], r[maxn], pos[maxn]; struct Segtree { int l, r; int val; } node[maxn << 3]; inline int read() { int x; scanf( %d , &x); return x; } inline void build(int p, int l, int r) { node[p].l = l, node[p].r = r; node[p].val = 0; if (l == r) return; int mid = (l + r) >> 1; build(p << 1, l, mid); build(p << 1 | 1, mid + 1, r); } inline void update(int p) { node[p].val = node[p << 1].val + node[p << 1 | 1].val; } inline void change(int p, int vl, int vr, int c) { if (node[p].l == vl && node[p].r == vr) { node[p].val += c; return; } int mid = (node[p].l + node[p].r) >> 1; if (vr <= mid) change(p << 1, vl, vr, c); else change(p << 1 | 1, vl, vr, c); update(p); } inline int query(int p, int vl, int vr) { if (node[p].l == vl && node[p].r == vr) return node[p].val; int mid = (node[p].l + node[p].r) >> 1; if (vr <= mid) return query(p << 1, vl, vr); else if (vl > mid) return query(p << 1 | 1, vl, vr); else return query(p << 1, vl, mid) + query(p << 1 | 1, mid + 1, vr); } int main() { n = read(), m = read(); build(1, 1, n + m); for (int i = 1; i <= n; ++i) change(1, m + i, m + i, 1), pos[i] = m + i, l[i] = r[i] = i; for (int i = 1; i <= m; ++i) { scanf( %d , &a[i]); l[a[i]] = min(1, l[a[i]]); r[a[i]] = max(r[a[i]], query(1, 1, pos[a[i]])); change(1, pos[a[i]], pos[a[i]], -1); pos[a[i]] = m - i + 1; change(1, pos[a[i]], pos[a[i]], 1); } for (int i = 1; i <= n; ++i) { r[i] = max(r[i], query(1, 1, pos[i])); printf( %d %d n , l[i], r[i]); } return 0; }
|
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