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#include <bits/stdc++.h> using namespace std; long long n, m, r, k, tot; int dx[] = {0, -1, 0, 1}; int dy[] = {-1, 0, 1, 0}; struct Cell { long long c, x, y; bool operator<(const Cell &oth) const { return c < oth.c; } }; class Map { private: set<long long> vis; public: bool isVisit(long long x, long long y) { return vis.count((x - 1) * m + y - 1); } void setVisit(long long x, long long y) { vis.insert((x - 1) * m + y - 1); } } mp; long long calc(long long x, long long y) { return min(r, min(n - r + 1, min(x, n - x + 1))) * min(r, min(m - r + 1, min(y, m - y + 1))); } priority_queue<Cell> pq; void solve() { scanf( %lld%lld%lld%lld , &n, &m, &r, &k); pq.push({calc(r, r), r, r}); mp.setVisit(r, r); while (!pq.empty() && k) { Cell cur = pq.top(); pq.pop(); k--; tot += cur.c; for (int i = 0; i < 4; i++) { int nx = cur.x + dx[i], ny = cur.y + dy[i]; if (0 < nx && nx <= n && 0 < ny && ny <= m && !mp.isVisit(nx, ny)) { pq.push({calc(nx, ny), nx, ny}); mp.setVisit(nx, ny); } } } printf( %.10f n , 1.0 * tot / (1.0 * (n - r + 1) * (m - r + 1))); } int main() { solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; char s[1010]; int a[1010], num[1010], b[30]; int prime[1010], notprime[1010]; priority_queue<pair<int, char> > pq; set<pair<int, int> > st; pair<int, int> c[1010]; int ans[1010]; int cnt; void init() { for (int i = 2; i <= 1000; i++) { if (!notprime[i]) prime[cnt++] = i; for (int j = 0; j < cnt && i * prime[j] <= 1000; j++) { notprime[i * prime[j]] = 1; if (i % prime[j] == 0) break; } } for (int i = 0; i <= 1000; i++) a[i] = i, num[i] = 1; } int get(int x) { return a[x] == x ? x : a[x] = get(a[x]); } void merge(int x, int y) { int t1 = get(x); int t2 = get(y); if (t1 != t2) { a[max(t1, t2)] = min(t1, t2); num[min(t1, t2)] += num[max(t1, t2)]; } } bool cmp(pair<int, int> x, pair<int, int> y) { return x.first > y.first; } int main() { init(); scanf( %s , s); int l = strlen(s); for (int i = 0; i < l; i++) b[s[i] - a ]++; for (int i = 0; i < 30; i++) if (b[i]) pq.push({b[i], i + a }); for (int i = 0; i < cnt && prime[i] <= l; i++) for (int j = 2; j <= l / prime[i]; j++) merge(prime[i], j * prime[i]); st.insert({1, 1}); for (int i = 0; i < cnt && prime[i] <= l; i++) { int r = get(prime[i]); st.insert({num[r], r}); } int num = 0, j = 0; for (auto i : st) c[num++] = i; sort(c, c + num, cmp); int flag = 0; while (pq.size() && j < num) { pair<int, char> t = pq.top(); pq.pop(); if (t.first >= c[j].first) ans[c[j].second] = t.second - a ; else { flag = 1; break; } if (t.first - c[j].first > 0) pq.push({t.first - c[j].first, t.second}); j++; } if (flag) printf( NO n ); else { printf( YES n ); for (int i = 1; i <= l; i++) printf( %c , ans[get(i)] + a ); } return 0; }
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//#############################################################################
//# Function: Dual data rate input buffer #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_iddr #(parameter DW = 1 // width of data inputs
)
(
input clk, // clock
input ce, // clock enable, set to high to clock in data
input [DW-1:0] din, // data input sampled on both edges of clock
output reg [DW-1:0] q1, // iddr rising edge sampled data
output reg [DW-1:0] q2 // iddr falling edge sampled data
);
//regs("sl"=stable low, "sh"=stable high)
reg [DW-1:0] q1_sl;
reg [DW-1:0] q2_sh;
// rising edge sample
always @ (posedge clk)
if(ce)
q1_sl[DW-1:0] <= din[DW-1:0];
// falling edge sample
always @ (negedge clk)
q2_sh[DW-1:0] <= din[DW-1:0];
// pipeline for alignment
always @ (posedge clk)
begin
q1[DW-1:0] <= q1_sl[DW-1:0];
q2[DW-1:0] <= q2_sh[DW-1:0];
end
endmodule // oh_iddr
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#include <bits/stdc++.h> using namespace std; const long long MAXN = 2e5 + 1; const long long LOG = 20; vector<pair<long long, long long> > edg[MAXN]; long long sz[MAXN]; long long link[MAXN]; long long ans[MAXN]; bool used[MAXN]; vector<pair<long long, long long> > ost[MAXN]; long long dp[MAXN][LOG]; long long mx[MAXN][LOG]; long long timein[MAXN]; long long timeout[MAXN]; long long timer = 0; long long first[MAXN]; vector<long long> h; long long pos = 0; bool cmp(tuple<long long, long long, long long, long long> a, tuple<long long, long long, long long, long long> b) { return get<2>(a) < get<2>(b); } long long fin(long long u) { if (u == link[u]) return u; return link[u] = fin(link[u]); } bool same(long long u, long long v) { return fin(u) == fin(v); } void unite(long long u, long long v) { u = fin(u); v = fin(v); if (sz[u] > sz[v]) swap(u, v); sz[v] += sz[u]; link[u] = link[v]; } void dfs(long long v, long long pred, long long w, long long ha) { timein[v] = timer++; mx[v][0] = w; dp[v][0] = pred; first[v] = pos; h.push_back(ha); pos++; for (long long i = 1; i < LOG; i++) { dp[v][i] = dp[dp[v][i - 1]][i - 1]; mx[v][i] = max(mx[v][i - 1], mx[dp[v][i - 1]][i - 1]); } for (auto u : ost[v]) if (u.first != pred) dfs(u.first, v, u.second, ha + 1); timeout[v] = timer++; } bool upper(long long u, long long v) { return timein[u] <= timein[v] && timeout[u] >= timeout[v]; } long long lca(long long u, long long v) { if (upper(u, v)) return u; if (upper(v, u)) return v; for (long long i = LOG - 1; i >= 0; i--) if (!upper(dp[u][i], v)) u = dp[u][i]; return dp[u][0]; } long long vis(long long u) { return h[first[u]]; } long long getmax(long long u, long long v) { long long ans = -1; if (vis(u) < vis(v)) swap(u, v); for (long long i = LOG - 1; i >= 0; i--) if (vis(dp[u][i]) >= vis(v)) { ans = max(ans, mx[u][i]); u = dp[u][i]; } return ans; } signed main() { ios::sync_with_stdio(0); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long ver, a, b, w, n, m, i, j, sum = 0, num, c, ves = -1; cin >> n >> m; vector<tuple<long long, long long, long long, long long> > reb(m); for (i = 0; i < m; i++) { cin >> a >> b >> w; edg[a].push_back({b, w}); edg[b].push_back({a, w}); reb[i] = make_tuple(a, b, w, i); } sort(reb.begin(), reb.end(), cmp); for (i = 1; i <= n; i++) { link[i] = i; sz[i] = 1; } vector<long long> made; for (i = 0; i < m; i++) { tie(a, b, w, num) = reb[i]; if (!same(a, b)) { unite(a, b); sum += w; made.push_back(num); used[num] = true; ost[a].push_back({b, w}); ost[b].push_back({a, w}); } } for (auto c : made) { ans[c] = sum; used[c] = true; } for (i = 0; i < LOG; i++) dp[1][i] = 1; dfs(1, 1, 0, 0); for (i = 0; i < m; i++) { tie(a, b, w, num) = reb[i]; if (used[num]) continue; c = lca(a, b); ves = max(getmax(a, c), getmax(b, c)); ans[num] = sum - ves + w; } for (i = 0; i < m; i++) cout << ans[i] << n ; }
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build Fri Jun 26 16:35:25 MDT 2015
// Date : Sat Oct 31 15:04:15 2015
// Host : cascade.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
// Command : write_verilog -force -mode synth_stub
// /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/Atari7800/Atari7800.srcs/sources_1/ip/BIOS_ROM/BIOS_ROM_stub.v
// Design : BIOS_ROM
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2015.2" *)
module BIOS_ROM(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[11:0],dina[7:0],douta[7:0]" */;
input clka;
input ena;
input [0:0]wea;
input [11:0]addra;
input [7:0]dina;
output [7:0]douta;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long abs2(long long a) { return a >= 0 ? a : -a; } long long calc(long long k, long long a) { if (k >= 0) return k / a; return (k - (a - 1)) / a; } long long calc2(long long a1, long long b1, long long a2, long long b2) { long long x = abs2(a1 - a2) + abs2(b2 - (a2 + (b1 - a1))); long long y = abs2(a1 - a2) + abs2(b2 - (-a2 + a1 + b1)); return min(x, y); } int main() { long long a, b, x1, x2, y1, y2; while (cin >> a >> b >> x1 >> y1 >> x2 >> y2) { long long a1, b1; long long a2, b2; a1 = calc(x1 + y1, 2 * a); b1 = calc(x1 - y1, 2 * b); a2 = calc(x2 + y2, 2 * a); b2 = calc(x2 - y2, 2 * b); long long x = calc2(a1, b1, a2, b2); long long y = calc2(b1, a1, b2, a2); cout << (int)min(x, y) << endl; } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_shiftreg.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/08/14 18:16:59 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.4 2002/03/02 21:06:01 mohor
// LinkFail signal was not latching appropriate bit.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
LatchByte, ShiftedBit, Prsd, LinkFail);
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
input Mdi; // MII input data
input [4:0] Fiad; // PHY address
input [4:0] Rgad; // Register address (within the selected PHY)
input [15:0]CtrlData; // Control data (data to be written to the PHY)
input WriteOp; // The current operation is a PHY register write operation
input [3:0] ByteSelect; // Byte select
input [1:0] LatchByte; // Byte select for latching (read operation)
output ShiftedBit; // Bit shifted out of the shift register
output[15:0]Prsd; // Read Status Data (data read from the PHY)
output LinkFail; // Link Integrity Signal
reg [7:0] ShiftReg; // Shift register for shifting the data in and out
reg [15:0]Prsd;
reg LinkFail;
// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
ShiftReg[7:0] <= 8'h0;
Prsd[15:0] <= 16'h0;
LinkFail <= 1'b0;
end
else
begin
if(MdcEn_n)
begin
if(|ByteSelect)
begin
/* verilator lint_off CASEINCOMPLETE */
case (ByteSelect[3:0]) // synopsys parallel_case full_case
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
endcase // case (ByteSelect[3:0])
/* verilator lint_on CASEINCOMPLETE */
end
else
begin
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
if(LatchByte[0])
begin
Prsd[7:0] <= {ShiftReg[6:0], Mdi};
if(Rgad == 5'h01)
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
end
else
begin
if(LatchByte[1])
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
end
end
end
end
end
assign ShiftedBit = ShiftReg[7];
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file BRAM.v when simulating
// the core, BRAM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module BRAM(
addra,
addrb,
clka,
clkb,
dina,
dinb,
doutb,
wea,
web);
input [9 : 0] addra;
input [9 : 0] addrb;
input clka;
input clkb;
input [31 : 0] dina;
input [31 : 0] dinb;
output [31 : 0] doutb;
input wea;
input web;
// synthesis translate_off
BLKMEMDP_V6_3 #(
.c_addra_width(10),
.c_addrb_width(10),
.c_default_data("0"),
.c_depth_a(1024),
.c_depth_b(1024),
.c_enable_rlocs(0),
.c_has_default_data(1),
.c_has_dina(1),
.c_has_dinb(1),
.c_has_douta(0),
.c_has_doutb(1),
.c_has_ena(0),
.c_has_enb(0),
.c_has_limit_data_pitch(0),
.c_has_nda(0),
.c_has_ndb(0),
.c_has_rdya(0),
.c_has_rdyb(0),
.c_has_rfda(0),
.c_has_rfdb(0),
.c_has_sinita(0),
.c_has_sinitb(0),
.c_has_wea(1),
.c_has_web(1),
.c_limit_data_pitch(18),
.c_mem_init_file("mif_file_16_1"),
.c_pipe_stages_a(0),
.c_pipe_stages_b(0),
.c_reg_inputsa(0),
.c_reg_inputsb(0),
.c_sim_collision_check("NONE"),
.c_sinita_value("0"),
.c_sinitb_value("0"),
.c_width_a(32),
.c_width_b(32),
.c_write_modea(0),
.c_write_modeb(0),
.c_ybottom_addr("0"),
.c_yclka_is_rising(1),
.c_yclkb_is_rising(1),
.c_yena_is_high(1),
.c_yenb_is_high(1),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("32kx1"),
.c_ysinita_is_high(1),
.c_ysinitb_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywea_is_high(1),
.c_yweb_is_high(1),
.c_yydisable_warnings(1))
inst (
.ADDRA(addra),
.ADDRB(addrb),
.CLKA(clka),
.CLKB(clkb),
.DINA(dina),
.DINB(dinb),
.DOUTB(doutb),
.WEA(wea),
.WEB(web),
.DOUTA(),
.ENA(),
.ENB(),
.NDA(),
.NDB(),
.RFDA(),
.RFDB(),
.RDYA(),
.RDYB(),
.SINITA(),
.SINITB());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of BRAM is "black_box"
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, sy, sx; cin >> n >> m >> sy >> sx; int up = sy; int down = sy + 1; int l = sx; int r = sx + 1; int k = 2; while (up >= 1) { while (l >= 1) { cout << up << << l << endl; l--; } while (r <= m) { cout << up << << r << endl; r++; } up--; if (k % 2 == 0) l = m; else r = 1; k++; } while (down <= n) { while (l >= 1) { cout << down << << l << endl; l--; } while (r <= m) { cout << down << << r << endl; r++; } down++; if (k % 2 == 0) l = m; else r = 1; k++; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SDFRTP_BEHAVIORAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_no_pg/sky130_fd_sc_hs__u_df_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrtp (
RESET_B,
CLK ,
D ,
Q ,
SCD ,
SCE ,
VPWR ,
VGND
);
// Module ports
input RESET_B;
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_r_no_pg u_df_p_r_no_pg0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100000 + 1; int n, m, s; int b[maxn]; int p[maxn]; int ansn, anst; bool ok(int k) { int i = n - 1; int j = k - 1; int tansn = 0, tanst = 0; int ss = s; while (j >= 0) { if (i >= 0 && b[i] >= p[j]) { tanst += p[j]; tansn++; j--; i--; } else if (i >= 0 && p[j] > b[i] && ss >= p[j] - b[i]) { tanst += b[i]; tansn++; ss -= (p[j] - b[i]); j--; i--; } else if (i >= 0) i--; else j--; } if (ss > 0) tanst = max(0, tanst - ss); if (tansn == k && tansn > ansn) { ansn = tansn; anst = tanst; } return tansn == k; } int main() { scanf( %d %d %d , &n, &m, &s); for (int i = 0; i < n; i++) scanf( %d , b + i); for (int i = 0; i < m; i++) scanf( %d , p + i); sort(b, b + n); sort(p, p + m); int l = 0; int r = m + 1; int mid; while (l + 1 < r) { mid = (l + r) / 2; if (ok(mid)) l = mid; else r = mid; } printf( %d %d n , ansn, anst); return 0; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_TB_V
`define SKY130_FD_SC_LP__SDFSTP_TB_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfstp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__sdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_TB_V
|
// soc_system_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 66,
parameter inUsePackets = 0,
parameter inDataWidth = 66,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 66,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [65:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [65:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 66)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 66)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 66)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// Directive indicates that 1ns is the time period used when specifying delays
// (i.e., #10 means 10ns); 100ps is the smallest unit of time precision that
// will be simulated (100ps = .1ns; thus #.1 is meaningful, #.00001 is equivalent
// to #0)
`timescale 1ns / 100ps
module testbench ();
reg clk;
reg reset_;
wire [7:0] led;
// Create an instance of the circuit under test
knightrider knightrider_0 (
.clk(clk),
.reset_(reset_),
.led(led)
);
// Initialize the clock signal to zero; drive reset_ active (low) for the
// first 100ns of the simulation.
initial begin
clk <= 1'b0;
reset_ <= 1'b0;
#100; reset_ <= 1'b1;
end
// Stop the simulation after 1100ms; note that simulations can run indefinitely
// (with waveforms loaded incrementally in the viewer.) Press ctrl-c to break
// iverilog, then enter '$finish' to stop the simulation.
initial begin
# $finish;
end
// Toggle the clock every 31.25ns (32 MHz frequency)
initial forever begin
#31.25; clk <= ~clk;
end
// Produce a waveform output of this simulation
initial begin
$dumpfile("waveform.vcd");
$dumpvars();
end
always@ (led)
$display("%t LEDs changed to %b", $time, led);
endmodule
|
#include <bits/stdc++.h> const int N = 200100; using namespace std; vector<long long int> v[N]; long long int n, down[N], up[N], k, s[N], a[N]; long long int ans; void f(long long int x, long long int p) { s[x] = a[x]; for (int i = 0; i < v[x].size(); i++) { long long int y = v[x][i]; if (y == p) continue; f(y, x); s[x] += s[y]; down[x] += down[y] + s[y]; } } void dfs(long long int x, long long int p) { long long int mx = k + k - s[x]; for (int i = 0; i < v[x].size(); i++) { long long int y = v[x][i]; if (y == p) continue; up[y] = up[x] + down[x] - down[y] - s[y] + k + k - s[y]; dfs(y, x); mx = max(mx, s[y]); } if (mx <= k) ans = max(ans, up[x] + down[x]); } int main() { ios_base::sync_with_stdio(0); cin >> n >> k; for (int i = 1; i <= k + k; i++) { long long int x; cin >> x; a[x] = 1; } for (int i = 1; i < n; i++) { long long int x, y; cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } f(1, -1); dfs(1, -1); cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; #define y1 temp_y1 #define all(x) x.begin(), x.end() const int N = 3e5 + 5; int n; int lst[N]; int fa[N]; vector<int> g[N]; int min_leaf = -1; int ext_cnt = 0; bool ok = true; void dfs1(int u, int k) { for (auto v : g[u]) { dfs1(v, k); } if (ext_cnt < k && lst[u] != ext_cnt) { ok = false; } if (ext_cnt == k) { min_leaf = u; } ++ext_cnt; } long long ans = 0; int seq[N]; int dfs_cnt = 0; int siz[N]; void dfs2(int u, int k, int dep) { seq[u] = dfs_cnt++; if (lst[u] < k) { ans += dep; siz[u]++; } for (auto v : g[u]) { dfs2(v, k, dep + 1); siz[u] += siz[v]; } if (lst[u] < k && lst[u] != ext_cnt) { ok = false; } if (lst[u] >= k && siz[u] + seq[u] != lst[u]) { ok = false; } ++ext_cnt; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 0; i < n; ++i) { cin >> lst[i]; --lst[i]; } for (int i = 0; i < n - 1; ++i) { int u, v; cin >> u >> v; --u; --v; fa[v] = u; g[u].push_back(v); } for (int i = 0; i < n; ++i) { sort(all(g[i]), [&](int x, int y) -> bool { return lst[x] < lst[y]; }); } if (lst[0] == 0) { dfs2(0, 0, 0); if (ok) { cout << YES << endl; cout << 0 << endl; for (int i = 0; i < n; ++i) { cout << lst[i] + 1 << ; } cout << endl; return 0; } else { cout << NO << endl; return 0; } } int v = lst[0] - 1; dfs1(0, v); int u = min_leaf; bool is_find = false; fa[0] = -1; //cerr << v + 1 << << u + 1 << << lst[u] + 1 <<endl; do { if (lst[u] == v) { is_find = true; } if (lst[u] == v && fa[u] != -1) { swap(lst[u], lst[fa[u]]); ++ans; } u = fa[u]; } while (u != -1); if (!is_find) { cout << NO << endl; return 0; } ext_cnt = 0; dfs2(0, v, 0); if (ok) { cout << YES << endl; cout << ans << endl; for (int i = 0; i < n; ++i) { cout << seq[i] + 1 << ; } cout << endl; } else { cout << NO << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; typedef long long ll; typedef __int128_t LL; typedef long double ld; typedef pair<int, int> pii; typedef pair<ll, ll> pll; #define F first #define S second #define pb push_back mt19937 rnd; const int N = 1e5 + 10; bool good[N], ban[N]; vector<int> get(const vector<int>& a) { vector<int> res; for (int i = 1; i < a.size(); i++) { res.pb(a[i] - a[i - 1] - 1); } return res; } bool solve0(int n) { for (int i = 1; i <= n; i++) { if (!good[i]) { return 0; } } return 1; } vector<int> solve1(int n) { if (good[1] || good[n]) { return {}; } for (int i = 1; i <= n - 1; i++) { if (good[i] && good[i + 1]) { return {}; } } vector<int> res; for (int i = 1, cnt = 0; i <= n; i++) { if (!good[i]) { cnt++; if (i == n || good[i + 1]) { res.pb(cnt); cnt = 0; } } } return res; } vector<int> solve2(int n) { if (!good[1] || !good[n]) { return {}; } vector<int> a = {0}; for (int i = 1, cnt = 0; i <= n; i++) { if (good[i]) { cnt++; if (i == n || !good[i + 1]) { if (i == cnt) { if (!(cnt & 1)) { return {}; } else { for (int j = 2; j <= i; j += 2) { a.pb(j); } } } else if (i == n) { if (!(cnt & 1)) { return {}; } else { for (int j = i - cnt + 1; j <= i; j += 2) { a.pb(j); } } } else { if (cnt & 1) { return {}; } else { for (int j = i - cnt + 1; j <= i; j += 2) { a.pb(j); } } } cnt = 0; } } } return get(a); } vector<int> solve3(int n) { vector<int> kek; for (int i = 1; i <= n; i++) { if (!good[i]) { ban[i] = 1; kek.pb(i); } } for (int j = 1; j <= kek.back(); j++) { ban[j] = 1; } for (int j = 1; j <= n + 2 - kek.front() - 1; j++) { ban[j] = 1; } ban[n - kek.front() + 3] = 1; for (int i = 1; i <= n - 1; i++) { if (!good[i] && good[i + 1]) { ban[i + 2] = 1; } } for (int i = 0; i + 1 < kek.size(); i++) { ban[n + kek[i] - kek[i + 1] + 4] = 1; } for (int s = n - 1; s >= 2; s--) { if (!ban[s]) { vector<int> a = {0}; for (int i = 1, cnt = 0; i <= n; i++) { if (good[i]) { cnt++; if (i == n) { int l = i - cnt + 1; int r = s; if (l <= r) { for (int j = l; j <= r; j += 2) { a.pb(j); } a.back() = r; } cnt = 0; } else if (!good[i + 1]) { int l = i - cnt + 1; int r = i + 1 - (n + 2 - s); if (i == cnt) { l = 2; } if (l <= r) { for (int j = l; j <= r; j += 2) { a.pb(j); } a.back() = r; } cnt = 0; } } } return get(a); } } return {}; } vector<int> solve(int n) { if (n == 1) { if (good[1]) { return {}; } else { return {1}; } } if (solve0(n)) { return {}; } vector<int> ans = solve1(n); if (!ans.empty()) return ans; ans = solve2(n); if (!ans.empty()) return ans; ans = solve3(n); if (!ans.empty()) return ans; return {-1}; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); #ifdef LOCAL freopen( input.txt , r , stdin); #endif string s; cin >> s; int n = s.size(); for (int i = 1; i <= n; i++) { good[i] = (s[i - 1] == _ ); } vector<int> ans = solve(n); if (!ans.empty() && ans.front() == -1) { cout << -1 n ; } else { cout << ans.size() << n ; for (int i : ans) { cout << i << ; } cout << n ; } #ifdef LOCAL cerr << nTime elapsed: << 1.0 * clock() / CLOCKS_PER_SEC << s. n ; #endif return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[101][101]; int main() { long long n, m; cin >> n >> m; long long mn = min(m, n); cout << mn + 1 << endl; for (long long i = 0; i <= mn; i++) cout << i << << (mn - i) % (mn + 1) << endl; }
|
/*
* super_memory_if - interface between the memory and
* the data bus of the supervisor CPU
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module support_memory_if //#( parameter wp_address = 0 )
(
input clk,
input [7:0] wp_address, // Upper 8-bits of non-write protected space
// ============= Internal support Ram =============
input [15:0] support_A,
input [7:0] support_Din,
output [7:0] support_Dout,
input support_wr,
// ============= Internal support Ram - Write interface =============
input sys_en,
input [15:0] sys_A,
input [7:0] sys_data,
input sys_wr
);
wire allow_write = (support_A[15:8] >= wp_address);
wire [15:0] adr;
wire [7:0] dat;
wire wr;
assign adr = (sys_en) ? sys_A : support_A;
assign dat = (sys_en) ? sys_data : support_Din;
assign wr = (sys_en) ? sys_wr : support_wr;
// Single port RAM
ram support_core_memory (
.address(adr),
.clock(clk),
.data(dat),
// Write protect doesn't apply to system interface
.wren(wr & (allow_write | sys_en)),
.q(support_Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long sum[2000005]; int main() { long long n; double k; cin >> n >> k; vector<long long> v; for (int i = 0; i < n; i++) { long long a; cin >> a; v.push_back(a); } for (int i = 1; i <= n; i++) { sum[i] = sum[i - 1] + v[i - 1]; } double total = 0; int go = n - k + 1; for (int i = 0; i < v.size(); i++) { if (go + i - 1 == v.size()) { break; } total += (sum[go + i] - sum[i]) / (double)go; } printf( %.10llf n , total); }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; const long long Mod = 1e9 + 7; const long double Pi = acos(-1); long long n, m, k; struct Weapon { long long Pow, Val; } a[200009], b[200009]; struct Monster { long long Att, Def, Val; } c[200009]; bool Cmp1(Weapon x, Weapon y) { return x.Pow < y.Pow; } bool Cmp2(Monster x, Monster y) { return x.Att < y.Att; } long long SufMin[200009]; long long Tree[800009], Lzy[800009]; void Merge(long long Node) { Tree[Node] = max(Tree[Node * 2], Tree[Node * 2 + 1]); } void Build(long long Node, long long l, long long r) { if (l == r) { Tree[Node] = -a[l].Val; return; } Build(Node * 2, l, (l + r) / 2); Build(Node * 2 + 1, (l + r) / 2 + 1, r); Merge(Node); } void LzyUpd(long long Node, long long l, long long r) { Tree[Node] += Lzy[Node]; if (l != r) { Lzy[Node * 2] += Lzy[Node]; Lzy[Node * 2 + 1] += Lzy[Node]; } Lzy[Node] = 0; } void Upd(long long Node, long long l, long long r, long long s, long long e, long long x) { if (l > r || s > e) return; LzyUpd(Node, l, r); if (s > r || e < l) return; if (s <= l && e >= r) { Lzy[Node] += x; LzyUpd(Node, l, r); return; } Upd(Node * 2, l, (l + r) / 2, s, e, x); Upd(Node * 2 + 1, (l + r) / 2 + 1, r, s, e, x); Merge(Node); } long long Query(long long Node, long long l, long long r) { LzyUpd(Node, l, r); return Tree[Node]; } long long Bin1(long long X) { long long l = -1, r = n; while (r - l > 1) { if (a[(l + r) / 2].Pow > X) r = (l + r) / 2; else l = (l + r) / 2; } return r; } long long Bin2(long long X) { long long l = -1, r = m; while (r - l > 1) { if (b[(l + r) / 2].Pow > X) r = (l + r) / 2; else l = (l + r) / 2; } return (r == m ? inf : SufMin[r]); } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m >> k; for (int i = 0; i < n; i++) { cin >> a[i].Pow >> a[i].Val; } for (int i = 0; i < m; i++) { cin >> b[i].Pow >> b[i].Val; } for (int i = 0; i < k; i++) { cin >> c[i].Def >> c[i].Att >> c[i].Val; } sort(a, a + n, Cmp1); sort(b, b + m, Cmp1); sort(c, c + k, Cmp2); for (int i = m - 1; i >= 0; i--) { SufMin[i] = b[i].Val; SufMin[i] = min(SufMin[i], (long long)(i == m - 1 ? inf : SufMin[i + 1])); } Build(1, 0, n - 1); long long Ans = -Bin2(0) + Query(1, 0, n - 1); for (int i = 0; i < k; i++) { long long Id = Bin1(c[i].Def); Upd(1, 0, n - 1, Id, n - 1, c[i].Val); long long Best1 = Bin2(c[i].Att); long long Best2 = Query(1, 0, n - 1); Ans = max(Ans, -Best1 + Best2); } cout << Ans << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Samuel A. Falvo II
//
// Create Date: 13:06:23 11/06/2011
// Design Name: Program Memory
// Module Name: M_mem
// Project Name: Kestrel-2
// Target Devices: NEXYS2
// Tool versions:
// Description:
// Program memory from $0000-$3FFF, which also holds the
// bootstrap code. This is the closest thing the Kestrel-2
// has to having firmware.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module M_mem(
input [13:1] ins_adr_i,
output [15:0] ins_dat_o,
input ins_cyc_i,
input ins_stb_i,
output ins_ack_o,
input [13:1] dat_adr_i,
output [15:0] dat_dat_o,
input [15:0] dat_dat_i,
input dat_we_i,
input dat_cyc_i,
input dat_stb_i,
output dat_ack_o,
input sys_clk_i,
input sys_rst_i
);
// Asynchronous address decoding logic. Note that we
// need separate logic for the instruction and data
// buses. We need to qualify our enables with the x_CYC_I
// and x_STB_I signals to be fully Wishbone compatible.
wire ins_active = ins_cyc_i & ins_stb_i;
wire dat_active = dat_cyc_i & dat_stb_i;
// We need at least two clocks for the Xilinx block RAMs
// to emulate an asynchronous RAM. Therefore, we need to
// introduce wait-states. It's yucky, but Forth chips don't
// pipeline well, so it is what it is.
reg dat_ack;
reg ins_ack;
assign dat_ack_o = dat_ack;
assign ins_ack_o = ins_ack;
always @(posedge sys_clk_i) begin
dat_ack <= (~dat_ack & dat_active & ~sys_rst_i);
ins_ack <= (~ins_ack & ins_active & ~sys_rst_i);
end
// Each RAM needs its own set of enable signals, one for
// the instruction bus, and one for the data bus.
// They need to be qualified against their respective bus
// cycles.
wire ien0 = (ins_adr_i[13:11] == 3'b000) & ins_active;
wire ien1 = (ins_adr_i[13:11] == 3'b001) & ins_active;
wire ien2 = (ins_adr_i[13:11] == 3'b010) & ins_active;
wire ien3 = (ins_adr_i[13:11] == 3'b011) & ins_active;
wire ien4 = (ins_adr_i[13:11] == 3'b100) & ins_active;
wire ien5 = (ins_adr_i[13:11] == 3'b101) & ins_active;
wire ien6 = (ins_adr_i[13:11] == 3'b110) & ins_active;
wire ien7 = (ins_adr_i[13:11] == 3'b111) & ins_active;
wire den0 = (dat_adr_i[13:11] == 3'b000) & dat_active;
wire den1 = (dat_adr_i[13:11] == 3'b001) & dat_active;
wire den2 = (dat_adr_i[13:11] == 3'b010) & dat_active;
wire den3 = (dat_adr_i[13:11] == 3'b011) & dat_active;
wire den4 = (dat_adr_i[13:11] == 3'b100) & dat_active;
wire den5 = (dat_adr_i[13:11] == 3'b101) & dat_active;
wire den6 = (dat_adr_i[13:11] == 3'b110) & dat_active;
wire den7 = (dat_adr_i[13:11] == 3'b111) & dat_active;
// Each RAM chunk has its own set of data outputs, which
// we multiplex onto x_DAT_O as needed.
wire [15:0] iq0, iq1, iq2, iq3, iq4, iq5, iq6, iq7;
wire [15:0] dq0, dq1, dq2, dq3, dq4, dq5, dq6, dq7;
reg [15:0] ins_dat;
reg [15:0] dat_dat;
assign ins_dat_o = ins_dat;
assign dat_dat_o = dat_dat;
// RAM data bus multiplexing logic
always @* begin
case (ins_adr_i[13:11])
3'b000: ins_dat <= iq0;
3'b001: ins_dat <= iq1;
3'b010: ins_dat <= iq2;
3'b011: ins_dat <= iq3;
3'b100: ins_dat <= iq4;
3'b101: ins_dat <= iq5;
3'b110: ins_dat <= iq6;
3'b111: ins_dat <= iq7;
default: ins_dat <= 16'hxxxx;
endcase
case(dat_adr_i[13:11])
3'b000: dat_dat <= dq0;
3'b001: dat_dat <= dq1;
3'b010: dat_dat <= dq2;
3'b011: dat_dat <= dq3;
3'b100: dat_dat <= dq4;
3'b101: dat_dat <= dq5;
3'b110: dat_dat <= dq6;
3'b111: dat_dat <= dq7;
default: dat_dat <= 16'hxxxx;
endcase
end
// RAM instances themselves. Eight instances
// times 2KB each equals 16KB total program memory.
RAMB16_S18_S18 ram00_07(
.WEA(1'b0), .WEB(dat_we_i),
.ENA(ien0), .ENB(den0),
.SSRA(1'b0), .SSRB(1'b0),
.CLKA(sys_clk_i), .CLKB(sys_clk_i),
.ADDRA(ins_adr_i[10:1]), .ADDRB(dat_adr_i[10:1]),
.DIA(16'h0000), .DIB(dat_dat_i),
.DOA(iq0), .DOB(dq0),
.DIPA(2'b00), .DIPB(2'b00)
);
RAMB16_S18_S18 ram08_0F(
.WEA(1'b0), .WEB(dat_we_i),
.ENA(ien1), .ENB(den1),
.SSRA(1'b0), .SSRB(1'b0),
.CLKA(sys_clk_i), .CLKB(sys_clk_i),
.ADDRA(ins_adr_i[10:1]), .ADDRB(dat_adr_i[10:1]),
.DIA(16'h0000), .DIB(dat_dat_i),
.DOA(iq1), .DOB(dq1),
.DIPA(2'b00), .DIPB(2'b00)
);
RAMB16_S18_S18 ram10_17(
.WEA(1'b0), .WEB(dat_we_i),
.ENA(ien2), .ENB(den2),
.SSRA(1'b0), .SSRB(1'b0),
.CLKA(sys_clk_i), .CLKB(sys_clk_i),
.ADDRA(ins_adr_i[10:1]), .ADDRB(dat_adr_i[10:1]),
.DIA(16'h0000), .DIB(dat_dat_i),
.DOA(iq2), .DOB(dq2),
.DIPA(2'b00), .DIPB(2'b00)
);
RAMB16_S18_S18 ram18_1F(
.WEA(1'b0), .WEB(dat_we_i),
.ENA(ien3), .ENB(den3),
.SSRA(1'b0), .SSRB(1'b0),
.CLKA(sys_clk_i), .CLKB(sys_clk_i),
.ADDRA(ins_adr_i[10:1]), .ADDRB(dat_adr_i[10:1]),
.DIA(16'h0000), .DIB(dat_dat_i),
.DOA(iq3), .DOB(dq3),
.DIPA(2'b00), .DIPB(2'b00)
);
RAMB16_S18_S18 ram20_27(
.WEA(1'b0), .WEB(dat_we_i),
.ENA(ien4), .ENB(den4),
.SSRA(1'b0), .SSRB(1'b0),
.CLKA(sys_clk_i), .CLKB(sys_clk_i),
.ADDRA(ins_adr_i[10:1]), .ADDRB(dat_adr_i[10:1]),
.DIA(16'h0000), .DIB(dat_dat_i),
.DOA(iq4), .DOB(dq4),
.DIPA(2'b00), .DIPB(2'b00)
);
RAMB16_S18_S18 ram28_2F(
.WEA(1'b0), .WEB(dat_we_i),
.ENA(ien5), .ENB(den5),
.SSRA(1'b0), .SSRB(1'b0),
.CLKA(sys_clk_i), .CLKB(sys_clk_i),
.ADDRA(ins_adr_i[10:1]), .ADDRB(dat_adr_i[10:1]),
.DIA(16'h0000), .DIB(dat_dat_i),
.DOA(iq5), .DOB(dq5),
.DIPA(2'b00), .DIPB(2'b00)
);
RAMB16_S18_S18 ram30_37(
.WEA(1'b0), .WEB(dat_we_i),
.ENA(ien6), .ENB(den6),
.SSRA(1'b0), .SSRB(1'b0),
.CLKA(sys_clk_i), .CLKB(sys_clk_i),
.ADDRA(ins_adr_i[10:1]), .ADDRB(dat_adr_i[10:1]),
.DIA(16'h0000), .DIB(dat_dat_i),
.DOA(iq6), .DOB(dq6),
.DIPA(2'b00), .DIPB(2'b00)
);
RAMB16_S18_S18 ram38_3F(
.WEA(1'b0), .WEB(dat_we_i),
.ENA(ien7), .ENB(den7),
.SSRA(1'b0), .SSRB(1'b0),
.CLKA(sys_clk_i), .CLKB(sys_clk_i),
.ADDRA(ins_adr_i[10:1]), .ADDRB(dat_adr_i[10:1]),
.DIA(16'h0000), .DIB(dat_dat_i),
.DOA(iq7), .DOB(dq7),
.DIPA(2'b00), .DIPB(2'b00)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND_BLACKBOX_V
`define SKY130_FD_SC_LS__TAPVGND_BLACKBOX_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int a, b[1000002], c = 0, d, e, f, g, h, i, j; int main() { cin >> a; for (i = 1; i <= a; i++) { cin >> d; b[d]++; if (b[d] > c) { c = b[d]; e = d; } } cout << e; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int info[200005], sz[200005], Prev[200005 << 1], to[200005 << 1], cst[200005 << 1], cnt_e; void Node(int u, int v, int c) { Prev[++cnt_e] = info[u], info[u] = cnt_e, to[cnt_e] = v, cst[cnt_e] = c; } long long G, B; void dfs(int u, int ff) { sz[u] = 1; for (int i = info[u], v; i; i = Prev[i]) if ((v = to[i]) != ff) { dfs(v, u), sz[u] += sz[v]; G += (sz[v] & 1) * cst[i], B += 1ll * cst[i] * min(sz[v], 2 * n - sz[v]); } } int main() { int T; scanf( %d , &T); for (; T--;) { scanf( %d , &n); for (int i = 1, u, v, c; i < 2 * n; i++) scanf( %d%d%d , &u, &v, &c), Node(u, v, c), Node(v, u, c); B = G = 0, dfs(1, 0); for (int i = 1; i <= 2 * n; i++) info[i] = 0; cnt_e = 0; printf( %lld %lld n , G, B); } }
|
module premuat1_8(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [15:0] i_0;
input signed [15:0] i_1;
input signed [15:0] i_2;
input signed [15:0] i_3;
input signed [15:0] i_4;
input signed [15:0] i_5;
input signed [15:0] i_6;
input signed [15:0] i_7;
output signed [15:0] o_0;
output signed [15:0] o_1;
output signed [15:0] o_2;
output signed [15:0] o_3;
output signed [15:0] o_4;
output signed [15:0] o_5;
output signed [15:0] o_6;
output signed [15:0] o_7;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [15:0] o1;
reg signed [15:0] o2;
reg signed [15:0] o3;
reg signed [15:0] o4;
reg signed [15:0] o5;
reg signed [15:0] o6;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1=i_2;
o2=i_4;
o3=i_6;
o4=i_1;
o5=i_3;
o6=i_5;
end
else
begin
o1=i_4;
o2=i_1;
o3=i_5;
o4=i_2;
o5=i_6;
o6=i_3;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=i_7;
endmodule
|
// This is a 4 bit serial adder, output will be ready after 4 clock cycles
// Assume a,b will change with the clock
// Assume carryin will NOT change with the clock i.e. it will remain constant over the 4 clock cycles
// The outputs y & carryout will keep changing at posedge to indicate the current state of calculation
module jserialadder(y,carryout,isValid,currentsum,currentcarryout,currentbitcount,clk,rst,a,b,carryin);
output reg [3:0]y;
output reg carryout;
output reg isValid; // This is a new functionality to indicate that the 4 bits were considered to produce the output
output reg currentsum, currentcarryout;
output reg [1:0]currentbitcount;// three bits enough to count till 4-bits for 4-bit serial adder
input clk,rst;
input a,b,carryin;
wire intermediatecarry;
// intermediatecarry should point to the carryin only for the 1st bit afterward it is previous bit's carryout
assign intermediatecarry = ( currentbitcount == 3'd0) ? carryin : currentcarryout;
// I have made even the Full adder to work on the posedge of the clock
// continuous assignment did not seem to work
always@(posedge clk)
begin
currentsum <= a ^ b ^ intermediatecarry;
currentcarryout <= ( a & b ) | ( a & intermediatecarry ) | ( b & intermediatecarry );
end
//assign currentsum = a ^ b ^ intermediatecarry;
//assign currentcarryout = ( a & b ) | ( a & intermediatecarry ) | ( b & intermediatecarry );
//assign carryout = ( currentbitcount == 3'd4 ) ? intermediatecarry : 0;
always@(posedge clk)
begin
if(rst)
begin
y <= 0;// other ways of assigning {0,0,0,0};//4'd0;
carryout <= 0;
end
else
begin
y <= {currentsum, y[3:1]};
carryout <= currentcarryout;//( currentbitcount == 3'd4 ) ? intermediatecarry : 0;
end
end
// Below block will keep track of the number of bits that have been added
// This is currently written for a 4 bit serial adder
always@(posedge clk)
begin
if(rst)
currentbitcount <= 0;
else
currentbitcount <= currentbitcount + 1; // already the 4 bit addition is completed
end
// isValid will provide the indication as to whether the addition is completed
// This is currently written for a 4 bit serial adder
always@(posedge clk)
begin
if(rst)
isValid <= 0;
else
isValid <= (currentbitcount == 3) ? 1 : 0; // at positive edge assume the 4 bit addition is completed without delay
end
endmodule
// Below is a simplistic approach to implement the serial adder
// Code given by the college lab
module jserialaddlab(a, b , clk, reset, sum, carry, cout, count, so);
input clk, reset, a, b;
output sum, carry;
reg cin;
output reg [3:0] so;
output reg [2:0] count;
output reg cout;
wire cut;
assign sum = a^b^cin;
assign carry = (count == 3'd4) ? 0 : cut;
assign cut = (a&b) | (a&cin) | (b&cin);
always@(posedge clk)
begin
if(reset)
cin <= 0;
else
cin <= carry;
end
always@(posedge clk)
begin
if(reset)
cout <= 0;
else
count <= cut;
end
always@(posedge clk)
begin
if(reset)
so <= 0;
else
so <= {sum, so[3:1]};
end
always@(posedge clk)
begin
if(reset)
count <= 0;
else
count <= (count ==4) ? 1 : count+1;
end
endmodule
|
// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
|
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* "is_last" == 0 means byte number is 8, no matter what value "byte_num" is. */
/* if "in_ready" == 0, then "is_last" should be 0. */
/* the user switch to next "in" only if "ack" == 1. */
`define low_pos(w,b) ((w)*64 + (b)*8)
`define low_pos2(w,b) `low_pos(w,7-b)
`define high_pos(w,b) (`low_pos(w,b) + 7)
`define high_pos2(w,b) (`low_pos2(w,b) + 7)
module keccak(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready);
input clk, reset;
input [31:0] in;
input in_ready, is_last;
input [1:0] byte_num;
output buffer_full; /* to "user" module */
output [511:0] out;
output reg out_ready;
reg state; /* state == 0: user will send more input data
* state == 1: user will not send any data */
wire [575:0] padder_out,
padder_out_1; /* before reorder byte */
wire padder_out_ready;
wire f_ack;
wire [1599:0] f_out;
wire f_out_ready;
wire [511:0] out1; /* before reorder byte */
reg [22:0] i; /* gen "out_ready" */
genvar w, b;
assign out1 = f_out[1599:1599-511];
always @ (posedge clk)
if (reset)
i <= 0;
else
i <= {i[21:0], state & f_ack};
always @ (posedge clk)
if (reset)
state <= 0;
else if (is_last)
state <= 1;
/* reorder byte ~ ~ */
generate
for(w=0; w<8; w=w+1)
begin : L0
for(b=0; b<8; b=b+1)
begin : L1
assign out[`high_pos(w,b):`low_pos(w,b)] = out1[`high_pos2(w,b):`low_pos2(w,b)];
end
end
endgenerate
/* reorder byte ~ ~ */
generate
for(w=0; w<9; w=w+1)
begin : L2
for(b=0; b<8; b=b+1)
begin : L3
assign padder_out[`high_pos(w,b):`low_pos(w,b)] = padder_out_1[`high_pos2(w,b):`low_pos2(w,b)];
end
end
endgenerate
always @ (posedge clk)
if (reset)
out_ready <= 0;
else if (i[22])
out_ready <= 1;
padder
padder_ (clk, reset, in, in_ready, is_last, byte_num, buffer_full, padder_out_1, padder_out_ready, f_ack);
f_permutation
f_permutation_ (clk, reset, padder_out, padder_out_ready, f_ack, f_out, f_out_ready);
endmodule
`undef low_pos
`undef low_pos2
`undef high_pos
`undef high_pos2
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4_FUNCTIONAL_V
`define SKY130_FD_SC_HS__AND4_FUNCTIONAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4 (
VPWR,
VGND,
X ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4_FUNCTIONAL_V
|
//////////////////////////////////////////////////////////////////////////
// Department of Computer Science
// National Tsing Hua University
// Project : FIFO for CS4125 Digital System Design
// Module : fifo_ctl.v
// Author : Chih-Tsun Huang
// E-mail :
// Revision : 4
// Date : 2014/04/28
// Abstract :
// FIFO controller is mainly the finite state machine and its
// control signals to manage the RAM module.
// Note :
// 1. The purpose of this version is to provide a design style. It is
// not a complete module. Please fix any *unexpected feature* by
// yourself if any.
// 2. Feel free to rewrite this file header to your own.
//
module fifo_ctr (
// inputs
input wire clk,
input wire rst_n,
input wire push,
input wire pop,
// outputs
output reg empty,
output reg almost_empty,
output reg full,
output reg almost_full,
output reg error,
output reg cen,
output reg wen,
output reg oen,
output reg [5:0] addr
);
parameter numOfRam = 64;
// small delay of flip-flop outputs
parameter delay = 1.5;
// state encoding
parameter EMPTY = 2'b00;
parameter BETWEEN = 2'b01;
parameter READOUT = 2'b10;
parameter FULL = 2'b11;
// state vector
reg [1:0] state;
reg [1:0] state_next;
// pointers
reg [5:0] head;
reg [5:0] head_next;
reg [5:0] tail;
reg [5:0] tail_next;
reg head_plus;
reg tail_plus;
reg addr_head;
reg addr_tail;
reg do_idle;
reg do_pop;
reg do_push;
reg do_push_pop;
// sequential part
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
state <= EMPTY;
head <= 6'b0;
tail <= 6'b0;
end else begin
state <= #(delay) state_next;
head <= #(delay) head_next;
tail <= #(delay) tail_next;
end
end
// combinational parts
// Lab Note:
// Complete your design here
always @(*) begin
do_idle = 1'b0;
do_pop = 1'b0;
do_push = 1'b0;
do_push_pop = 1'b0;
case ({push,pop})
2'b00: begin do_idle = 1'b1; end
2'b01: begin do_pop = 1'b1; end
2'b10: begin do_push = 1'b1; end
2'b11: begin do_push_pop = 1'b1; end
endcase
end
always @(*) begin
if (head_plus) begin
head_next = (head + 1'b1)%numOfRam;
end else begin
head_next = head;
end
if (tail_plus) begin
tail_next = (tail + 1'b1)%numOfRam;
end else begin
tail_next = tail;
end
end
always @(*) begin
if (tail == head - 1'b1) begin
almost_empty = 1'b1;
end else begin
almost_empty = 1'b0;
end
if (head == tail - 1'b1) begin
almost_full = 1'b1;
end else begin
almost_full = 1'b0;
end
oen = 1'b0;
end
// FSM
always @(*) begin
empty = 1'b0;
full = 1'b0;
error = 1'b0;
cen = 1'b0;
wen = 1'b0;
addr = 6'b0;
head_plus = 1'b0;
tail_plus = 1'b0;
addr_head = 1'b0;
addr_tail = 1'b0;
state_next = state;
case (state)
EMPTY: begin
if (do_idle || do_pop || do_push_pop) begin
error = (do_pop | do_push_pop);
state_next = EMPTY;
end else if (do_push) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = BETWEEN;
end
end
BETWEEN: begin
if (do_push && !almost_full) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = BETWEEN;
end else if (do_idle || do_push_pop) begin
error = do_push_pop;
state_next = BETWEEN;
end else if (do_pop) begin
addr = tail;
state_next = READOUT;
end else if (do_push && almost_full) begin
addr = head;
head_plus = 1'b1;
wen = 1'b0;
state_next = FULL;
end
end
READOUT: begin
if (!almost_empty) begin
tail_plus = 1'b1;
error = (do_push | do_pop);
state_next = BETWEEN;
end else begin
tail_plus = 1'b1;
error = (do_push | do_pop);
state_next = EMPTY;
end
end
FULL: begin
if (do_pop) begin
addr = tail;
state_next = READOUT;
end else if (do_idle || do_push || do_push_pop) begin
error = (do_push | do_push_pop);
state_next = FULL;
end
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221A_SYMBOL_V
`define SKY130_FD_SC_MS__O221A_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o221a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221A_SYMBOL_V
|
// divmmc
//
// Total refactoring. Made module synchroneous. (Sorgelig)
//
module divmmc
(
input clk_sys,
input [1:0] mode,
// CPU interface
input nWR,
input nRD,
input nMREQ,
input nRFSH,
input nIORQ,
input nM1,
input [15:0] addr,
input [7:0] din,
output [7:0] dout,
// control
input enable,
input disable_pagein,
output active_io,
output rom_active,
output ram_active,
output [3:0] ram_bank,
// SD/MMC SPI
output reg spi_ss,
output spi_clk,
input spi_di,
output spi_do
);
wire io_we = ~nIORQ & ~nWR & nM1;
wire io_rd = ~nIORQ & ~nRD & nM1;
wire m1 = ~nMREQ & ~nM1;
// Edge detectors
reg old_we, old_rd, old_m1;
always @(posedge clk_sys) begin
old_we <= io_we;
old_rd <= io_rd;
old_m1 <= m1;
end
// SPI handling
assign active_io = port_io;
wire port_cs = ((mode[0] ) && (addr[7:0] == 8'hE7)) ||
((mode == 2'b10) && (addr[7:0] == 8'h1F));
wire port_io = ((mode[0] ) && (addr[7:0] == 8'hEB)) ||
((mode == 2'b10) && (addr[7:0] == 8'h3F));
reg tx_strobe;
reg rx_strobe;
always @(posedge clk_sys) begin
reg m1_trigger;
rx_strobe <= 0;
tx_strobe <= 0;
if(enable) begin
if(io_we & ~old_we) begin
if (port_cs) spi_ss <= din[0]; // SPI enable
if (port_io) tx_strobe <= 1'b1; // SPI write
end
// SPI read
if(io_rd & ~old_rd & port_io) rx_strobe <= 1;
end else begin
spi_ss <= 1;
end
end
// DivMMC memory handling
wire page0 = addr[15:13] == 3'b000;
wire page1 = addr[15:13] == 3'b001;
assign rom_active = (nRFSH & page0 & (conmem | (!mapram & automap)));
assign ram_active = (nRFSH & page0 & !conmem & mapram & automap) | (page1 & (conmem | automap));
assign ram_bank = page0 ? 4'h3 : sram_page;
reg [3:0] sram_page;
reg conmem;
reg mapram;
reg automap;
always @(posedge clk_sys) begin
reg m1_trigger;
if(enable && mode == 2'b11) begin
if(io_we & ~old_we) begin
case(addr[7:0])
'hE3: {conmem, mapram, sram_page} <= {din[7:6], din[3:0]}; // divmmc memctl
default:;
endcase
end
if(m1 & ~old_m1) begin
casex(addr)
16'h0000, 16'h0008, 16'h0038, 16'h0066:
m1_trigger <= 1; // activate automapper after this cycle
16'h04C6, 16'h0562:
m1_trigger <= !disable_pagein; // disable tape traps when the built-in tape player is in use
16'h3DXX:
{automap, m1_trigger} <= 2'b11; // activate automapper immediately
16'b0001111111111XXX: // 1FF8...1FFF
m1_trigger <= 0; // deactivate automapper after this cycle
default: ;
endcase
end
if(~nRFSH) automap <= m1_trigger;
end else begin
m1_trigger <= 0;
automap <= 0;
conmem <= 0;
sram_page <= 0;
mapram <= 0;
end
end
// SPI
spi spi
(
.clk_sys(clk_sys),
.tx(tx_strobe),
.rx(rx_strobe),
.din(din),
.dout(dout),
.spi_clk(spi_clk),
.spi_di(spi_di),
.spi_do(spi_do)
);
endmodule
// SPI module
module spi
(
input clk_sys,
input tx, // Byte ready to be transmitted
input rx, // request to read one byte
input [7:0] din,
output [7:0] dout,
output spi_clk,
input spi_di,
output spi_do
);
assign spi_clk = counter[0];
assign spi_do = io_byte[7]; // data is shifted up during transfer
assign dout = data;
reg [4:0] counter = 5'b10000; // tx/rx counter is idle
reg [7:0] io_byte, data;
always @(negedge clk_sys) begin
if(counter[4]) begin
if(rx | tx) begin
counter <= 0;
data <= io_byte;
io_byte <= tx ? din : 8'hff;
end
end else begin
if(spi_clk) io_byte <= { io_byte[6:0], spi_di };
counter <= counter + 2'd1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() {} void no() { cout << NO << n ; exit(0); } const long long maxn = 100050; long long a[maxn]; long long psa[maxn]; signed main() { ios::sync_with_stdio(0); cin.tie(0); long long n; cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; } long long len = n; for (long long i = 1; i <= n; i++) { if (a[i] != a[1]) { len = i - 1; break; } } for (long long i = 1; i <= n; i++) { psa[i] = psa[i - 1] + a[i]; } if (n % len) no(); for (long long i = len; i <= n; i += len) { long long sum = psa[i] - psa[i - len]; if (sum and sum != len) { no(); } if (i >= len * 2) { if (sum == psa[i - len] - psa[i - 2 * len]) { no(); } } } cout << YES << n ; }
|
//axi_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2017 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1 ns/1 ps
module axi_interconnect #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32
)(
//control signals
input clk,
input rst,
//bus write addr path
output [3:0] i_awid, //Write ID
output [ADDR_WIDTH - 1:0] i_awaddr, //Write Addr Path Address
output [3:0] i_awlen, //Write Addr Path Burst Length
output [2:0] i_awsize, //Write Addr Path Burst Size
output [1:0] i_awburst, //Write Addr Path Burst Type
// 0 = Fixed
// 1 = Incrementing
// 2 = wrap
output [1:0] i_awlock, //Write Addr Path Lock (atomic) information
// 0 = Normal
// 1 = Exclusive
// 2 = Locked
output [3:0] i_awcache, //Write Addr Path Cache Type
output [2:0] i_awprot, //Write Addr Path Protection Type
output i_awvalid, //Write Addr Path Address Valid
input o_awready, //Write Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus write data
output reg [3:0] i_wid, //Write ID
output reg [DATA_WIDTH - 1: 0] i_wdata, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
output reg [DATA_WIDTH >> 3:0] i_wstrobe, //Write Strobe (a 1 in the write is associated with the byte to write)
output reg i_wlast, //Write Last transfer in a write burst
output reg i_wvalid, //Data through this bus is valid
input o_wready, //Slave is ready for data
//Write Response Channel
input [3:0] o_bid, //Response ID (this must match awid)
input [1:0] o_bresp, //Write Response
// 0 = OKAY
// 1 = EXOKAY
// 2 = SLVERR
// 3 = DECERR
input o_bvalid, //Write Response is:
// 1 = Available
// 0 = Not Available
output reg i_bready, //WBM Ready
//bus read addr path
output reg [3:0] i_arid, //Read ID
output [ADDR_WIDTH - 1:0] i_araddr, //Read Addr Path Address
output reg [3:0] i_arlen, //Read Addr Path Burst Length
output reg [2:0] i_arsize, //Read Addr Path Burst Size
output [1:0] i_arburst, //Read Addr Path Burst Type
output [1:0] i_arlock, //Read Addr Path Lock (atomic) information
output [3:0] i_arcache, //Read Addr Path Cache Type
output [2:0] i_arprot, //Read Addr Path Protection Type
output reg i_arvalid, //Read Addr Path Address Valid
input o_arready, //Read Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus read data
input [3:0] o_rid, //Write ID
input [DATA_WIDTH - 1: 0] o_rdata, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
input [DATA_WIDTH >> 3:0] o_rstrobe, //Write Strobe (a 1 in the write is associated with the byte to write)
input o_rlast, //Write Last transfer in a write burst
input o_rvalid, //Data through this bus is valid
output reg i_rready, //WBM is ready for data
// 1 = WBM Ready
// 0 = Slave Ready
${PORTS}
);
${ADDRESSES}
localparam ADDR_NO_SEL = ((1 << ADDR_WIDTH) - 1);
//state
//axi slave signals
//this should be parameterized
wire [3:0]slave_select;
assign slave_select = i_m_adr[31:24];
${DATA}
${ACK}
${ASSIGN}
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_2_V
`define SKY130_FD_SC_MS__DFRTP_2_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrtp_2 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrtp_2 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_2_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = (int)555; const int mod = (int)1e9 + 7; const int P = (int)1e6 + 7; const double pi = acos(-1.0); int a[maxn][maxn], b[maxn][maxn], n; vector<vector<int> > base{{1, 2, 4}, {5, 3, 8}, {9, 6, 7}}; void rec(int n) { if (n == 3) { for (int i = (0); i <= (n - 1); ++i) for (int j = (0); j <= (n - 1); ++j) a[i][j] = base[i][j]; return; } rec(n - 1); if (!(n & 1)) { int cur = 1; for (int i = (n - 1); i >= (1); --i) b[i][n - 1] = cur++; for (int i = (n - 1); i >= (0); --i) b[0][i] = cur++; for (int i = (1); i <= (n - 1); ++i) for (int j = (0); j <= (n - 2); ++j) b[i][j] = cur + a[i - 1][j] - 1; } else { int cur = 1; for (int i = (0); i <= (n - 1); ++i) b[0][i] = cur++; for (int i = (1); i <= (n - 1); ++i) b[i][n - 1] = cur++; for (int i = (1); i <= (n - 1); ++i) for (int j = (0); j <= (n - 2); ++j) b[i][j] = cur + a[i - 1][j] - 1; } for (int i = (0); i <= (n - 1); ++i) for (int j = (0); j <= (n - 1); ++j) a[i][j] = b[i][j]; } void solve() { scanf( %d , &n); if (n <= 2) { puts( -1 ); return; } rec(n); for (int i = (0); i <= (n - 1); ++i) { for (int j = (0); j <= (n - 1); ++j) printf( %d , a[i][j]); puts( ); } } int main() { int t = 1; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; struct Point { int x, y; Point() {} Point(int a, int b) { x = a; y = b; } }; double hypt(Point A, Point B) { return sqrt((B.x - A.x) * (B.x - A.x) + (B.y - A.y) * (B.y - A.y)); } int main() { int k, n; cin >> n >> k; vector<Point> v(n); for (int i = 0; i < n; i++) { cin >> v[i].x >> v[i].y; } double ans = 0; for (int i = 1; i < n; i++) { ans += hypt(v[i], v[i - 1]); } ans *= k; ans /= 50; printf( %.10lf , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int m, n; cin >> m >> n; if (m % 2 == 0) { cout << (m * n / 2); } else { cout << ((m / 2) * n + n / 2); } return 0; }
|
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=64 LPM_WIDTHN=64 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:07:21:01:49:21:SJ cbx_stratixii 2016:07:21:01:48:16:SJ cbx_util_mgl 2016:07:21:01:48:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mguik
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [63:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [63:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [63:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 64,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mguik
//VALID FILE
|
module signed_logic_operators_bug();
reg [7:0] a, b;
wire [15:0] yuu, yus, ysu, yss;
wire [15:0] zuu, zus, zsu, zss;
initial begin
// Example vector
a = 8'b10110110;
b = 8'b10010010;
// Wait for results to be calculated
#1;
// Display results
$display("a = %b", a);
$display("b = %b", b);
$display("yuu = %b", yuu);
$display("zuu = %b", zuu);
$display("yus = %b", yus);
$display("zus = %b", zus);
$display("ysu = %b", ysu);
$display("zsu = %b", zsu);
$display("yss = %b", yss);
$display("zss = %b", zss);
// Finished
$finish(0);
end
// Calculate signed logical OR
manually_extended_logical_or INST1(.a(a), .b(b), .yuu(yuu), .yus(yus), .ysu(ysu), .yss(yss));
signed_logical_or INST2(.a(a), .b(b), .yuu(zuu), .yus(zus), .ysu(zsu), .yss(zss));
endmodule
module manually_extended_logical_or(a, b, yuu, yus, ysu, yss);
input [7:0] a, b;
output [15:0] yuu, yus, ysu, yss;
// Manually zero or sign extend operands before logic OR
// - Note the operands are zero extended in "yuu", "yus" and "ysu"
// - The operands are sign extended in "yss"
assign yuu = {{8{1'b0}}, a} | {{8{1'b0}}, b};
assign yus = {{8{1'b0}}, a} | {{8{1'b0}}, b};
assign ysu = {{8{1'b0}}, a} | {{8{1'b0}}, b};
assign yss = {{8{a[7]}}, a} | {{8{b[7]}}, b};
endmodule
module signed_logical_or(a, b, yuu, yus, ysu, yss);
input [7:0] a, b;
output [15:0] yuu, yus, ysu, yss;
// Note that the operation is only consider signed if ALL data operands are signed
// - Therefore $signed(a) does NOT sign extend "a" in expression "ysu"
// - But "a" and "b" are both sign extended before the OR in expression "yss"
assign yuu = a | b ;
assign yus = a | $signed(b);
assign ysu = $signed(a) | b ;
assign yss = $signed(a) | $signed(b);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, b; int noOfDivisors(int n) { int till = sqrt(n); int c = 0; for (int i = 1; i < till + 1; i++) { if ((n % i) == 0) { if (i > b) c++; if ((n / i) > b && (n != i * i)) c++; } } return c; } int main() { scanf( %d%d , &a, &b); int ans = 0; if (a == b) { printf( infinity ); return 0; } else { printf( %d , noOfDivisors(a - b)); } }
|
module tacho_fpga(quadA, quadB, mosi, miso, sck, cs, dir, step);
parameter COUNT_BITS = 32;
input quadA, quadB;
output miso;
input mosi, sck, cs;
output dir, step;
wire clk;
OSCH #(
.NOM_FREQ("53.2")
) internal_oscillator_inst (
.STDBY(1'b0),
.OSC(clk)
);
reg [COUNT_BITS - 1: 0] step_period;
reg dir;
wire [COUNT_BITS * 2 - 1: 0] rx_data;
wire [COUNT_BITS - 1:0] encoder_position;
wire [COUNT_BITS - 1: 0] stepper_position;
wire [COUNT_BITS * 2 - 1: 0] tx_data;
assign tx_data[COUNT_BITS * 2 - 1:COUNT_BITS] = encoder_position;
assign tx_data[COUNT_BITS - 1:0] = stepper_position;
quad_counter #(COUNT_BITS) counter(clk, quadA, quadB, encoder_position);
step_pulse_generator #(COUNT_BITS) step_gen(clk, step_period, stepper_position, dir, step);
spi_slave #(COUNT_BITS * 2) spi(clk, mosi, miso, sck, cs, tx_data, rx_data, rx_ready);
// when received from master
always @(posedge rx_ready)
begin
// pick out stepper period part of the received data
step_period = rx_data[COUNT_BITS - 1:0];
dir = rx_data[COUNT_BITS];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> e[300020]; int f[300020][3]; inline int Mod(int x) { return x + ((x >> 31) & 998244353); } void DFS(int x, int p) { int i, v; f[x][0] = 1; f[x][1] = 1; f[x][2] = 1; for (i = 0; i < (signed)e[x].size(); i++) if ((v = e[x][i]) != p) { DFS(v, x); f[x][0] = (long long)f[x][0] * Mod(f[v][1] + 2 * Mod(f[v][0] + f[v][2] - 998244353) % 998244353 - 998244353) % 998244353; f[x][1] = (long long)f[x][1] * Mod(f[v][0] + f[v][2] - 998244353) % 998244353; f[x][2] = (long long)f[x][2] * Mod(2 * f[v][0] % 998244353 + f[v][2] - 998244353) % 998244353; } f[x][2] = Mod(f[x][2] - f[x][1]); return; } int main(void) { int n, u, v; int i; scanf( %d , &n); for (i = 1; i < n; i++) { scanf( %d %d , &u, &v); e[--u].push_back(--v); e[v].push_back(u); } DFS(0, 0); printf( %d n , Mod(Mod(f[0][0] + f[0][2] - 998244353) - 1)); return 0; }
|
#include <bits/stdc++.h> template <typename Arg1> void __f(const char* name, Arg1&& arg1) { std::cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); std::cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long i, j, n, m, k, cnt = 0, ans = 0, t = 1; cin >> n; long long a[n]; for (i = 0; i < n; i++) cin >> a[i]; priority_queue<long long, vector<long long>, greater<long long> > pq; for (i = 0; i < n; i++) { if (!pq.empty() && pq.top() < a[i]) { ans += (a[i] - pq.top()); pq.pop(); pq.push(a[i]); } pq.push(a[i]); } return cout << ans, 0; return 0; }
|
#include <bits/stdc++.h> using namespace std; char a[60][60]; int ch(int r, int c) { int i, j, f = 0; for (i = 0; i < c; i++) { if (a[0][i] == P ) f = 1; } if (f == 0) return 0; f = 0; for (i = 0; i < c; i++) { if (a[r - 1][i] == P ) f = 1; } if (f == 0) return 0; f = 0; for (i = 0; i < r; i++) { if (a[i][0] == P ) f = 1; } if (f == 0) return 0; f = 0; for (i = 0; i < r; i++) { if (a[i][c - 1] == P ) f = 1; } return f; } int chh(int r, int c) { int i, j, f = 0; for (i = 1; i < r - 1; i++) { f = 0; for (j = 0; j < c; j++) { if (a[i][j] == P ) f = 1; } if (f == 0) return 0; } for (i = 1; i < c - 1; i++) { f = 0; for (j = 0; j < r; j++) { if (a[j][i] == P ) f = 1; } if (f == 0) return 0; } return 1; } int al(int r, int c) { int i, j, f = 0; for (i = 0; i < r; i++) { for (j = 0; j < c; j++) { if (a[i][j] == P ) return 1; } } return 0; } int main() { int t; cin >> t; while (t--) { int r, c, i, j, f = 0; cin >> r >> c; cin.ignore(256, n ); for (i = 0; i < r; i++) { string s; getline(cin, s); for (j = 0; j < c; j++) a[i][j] = s[j]; } for (i = 0; i < r; i++) { for (j = 0; j < c; j++) { if (a[i][j] == A ) { f = 1; break; } } } if (f == 0) { cout << MORTAL n ; } else if (al(r, c) == 0) cout << 0 << endl; else { if (ch(r, c) == 0) cout << 1 << endl; else if (a[0][0] == A || a[0][c - 1] == A || a[r - 1][0] == A || a[r - 1][c - 1] == A || chh(r, c) == 0) cout << 2 << endl; else { f = 0; for (i = 1; i < c - 1; i++) { if (a[0][i] == A ) f = 1; if (a[r - 1][i] == A ) f = 1; } for (i = 1; i < r - 1; i++) { if (a[i][0] == A ) f = 1; if (a[i][c - 1] == A ) f = 1; } if (f == 1) cout << 3 << endl; else cout << 4 << endl; } } } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; while (t--) { long long n, g, b; cin >> n >> g >> b; if (g >= b) { cout << n << endl; continue; } long long good_need = n / 2; if (n % 2 == 1) good_need += 1; good_need -= g; long long bad_poss = n / 2; long long periods = bad_poss / b; if (good_need - periods * g <= 0) { cout << n << endl; continue; } good_need -= periods * g; long long restperiods = good_need / g; long long rest = 0; if (good_need % g != 0) { rest = good_need % g + b; } cout << g + (periods + restperiods) * (g + b) + rest << endl; } }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's register file read operands mux ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Mux for two register file read operands. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:05 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_operandmuxes(
// Clock and reset
clk, rst,
// Internal i/f
id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
simm, sel_a, sel_b, operand_a, operand_b, muxed_b
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input clk;
input rst;
input id_freeze;
input ex_freeze;
input [width-1:0] rf_dataa;
input [width-1:0] rf_datab;
input [width-1:0] ex_forw;
input [width-1:0] wb_forw;
input [width-1:0] simm;
input [`OR1200_SEL_WIDTH-1:0] sel_a;
input [`OR1200_SEL_WIDTH-1:0] sel_b;
output [width-1:0] operand_a;
output [width-1:0] operand_b;
output [width-1:0] muxed_b;
//
// Internal wires and regs
//
reg [width-1:0] operand_a;
reg [width-1:0] operand_b;
reg [width-1:0] muxed_a;
reg [width-1:0] muxed_b;
reg saved_a;
reg saved_b;
//
// Operand A register
//
always @(posedge clk or posedge rst) begin
if (rst) begin
operand_a <= #1 32'd0;
saved_a <= #1 1'b0;
end else if (!ex_freeze && id_freeze && !saved_a) begin
operand_a <= #1 muxed_a;
saved_a <= #1 1'b1;
end else if (!ex_freeze && !saved_a) begin
operand_a <= #1 muxed_a;
end else if (!ex_freeze && !id_freeze)
saved_a <= #1 1'b0;
end
//
// Operand B register
//
always @(posedge clk or posedge rst) begin
if (rst) begin
operand_b <= #1 32'd0;
saved_b <= #1 1'b0;
end else if (!ex_freeze && id_freeze && !saved_b) begin
operand_b <= #1 muxed_b;
saved_b <= #1 1'b1;
end else if (!ex_freeze && !saved_b) begin
operand_b <= #1 muxed_b;
end else if (!ex_freeze && !id_freeze)
saved_b <= #1 1'b0;
end
//
// Forwarding logic for operand A register
//
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_a) // synopsys parallel_case infer_mux
`else
casex (sel_a) // synopsys parallel_case
`endif
`OR1200_SEL_EX_FORW:
muxed_a = ex_forw;
`OR1200_SEL_WB_FORW:
muxed_a = wb_forw;
default:
muxed_a = rf_dataa;
endcase
end
//
// Forwarding logic for operand B register
//
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_b) // synopsys parallel_case infer_mux
`else
casex (sel_b) // synopsys parallel_case
`endif
`OR1200_SEL_IMM:
muxed_b = simm;
`OR1200_SEL_EX_FORW:
muxed_b = ex_forw;
`OR1200_SEL_WB_FORW:
muxed_b = wb_forw;
default:
muxed_b = rf_datab;
endcase
end
endmodule
|
// In the name of Allah. // We re nothing and you re everything. // Ya Ali! #include <bits/stdc++.h> using namespace std; typedef long long ll; const int maxn = 1e5 + 14, S = 2000; struct Block { int val, cnt; }; struct BlockManager { list<Block> l{{0, maxn}}; int cnt[maxn]; list<Block>::iterator where[maxn]; BlockManager() { where[0] = l.begin(); fill(where + 1, where + maxn, l.end()); } void add(int x) { int &c = cnt[x]; if (where[c + 1] == l.end()) where[c + 1] = l.insert(next(where[c]), {c + 1, 0}); if (!--where[c]->cnt) { l.erase(where[c]); where[c] = l.end(); } where[++c]->cnt++; } void remove(int x) { int &c = cnt[x]; if (where[c - 1] == l.end()) where[c - 1] = l.insert(where[c], {c - 1, 0}); if (!--where[c]->cnt) { l.erase(where[c]); where[c] = l.end(); } where[--c]->cnt++; } int get_ans(int k) { int ans = maxn; int seen = 0; for (auto it = next(l.begin()), jt = it; seen >= k or jt != l.end(); it++) { while (jt != l.end() and seen < k) seen += jt++->cnt; if (seen >= k) ans = min(ans, prev(jt)->val - it->val); seen -= it->cnt; } return ans == maxn ? -1 : ans; } } block_manager; struct Query { int t, l, r, k, i; array<int, 3> rank() const { return {t / S, (t / S % 2 ? -l : l) / S, l / S % 2 ? r : -r}; } } queries[maxn]; struct UpdQuery { int p, was, x; }; int n, m, a[maxn], ans[maxn]; int main() { ios::sync_with_stdio(0), cin.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; vector<UpdQuery> updates; int q = 0; for (int i = 0; i < m; i++) { int t; cin >> t; if (t == 1) { cin >> queries[q].l >> queries[q].r >> queries[q].k; queries[q].l--; queries[q].t = updates.size(); queries[q].i = q; q++; } else { int p, x; cin >> p >> x; p--; updates.push_back({p, a[p], x}); a[p] = x; } } sort(queries, queries + q, [](Query &a, Query &b) { return a.rank() < b.rank(); }); int l = 0, r = 0, t = updates.size(); for_each(queries, queries + q, [&](Query q) { while (l > q.l) block_manager.add(a[--l]); while (r < q.r) block_manager.add(a[r++]); while (r > q.r) block_manager.remove(a[--r]); while (l < q.l) block_manager.remove(a[l++]); while (t > q.t) { t--; a[updates[t].p] = updates[t].was; if (l <= updates[t].p and updates[t].p < r) { block_manager.add(updates[t].was); block_manager.remove(updates[t].x); } } while (t < q.t) { a[updates[t].p] = updates[t].x; if (l <= updates[t].p and updates[t].p < r) { block_manager.add(updates[t].x); block_manager.remove(updates[t].was); } t++; } ans[q.i] = block_manager.get_ans(q.k); }); for (int i = 0; i < q; i++) cout << ans[i] << n ; }
|
/*
* Redistributions of any form whatsoever must retain and/or include the
* following acknowledgment, notices and disclaimer:
*
* This product includes software developed by Carnegie Mellon University.
*
* Copyright (c) 2008 James C. Hoe,
* Computer Architecture Lab at Carnegie Mellon (CALCM),
* Carnegie Mellon University.
*
* This source file was modified by Xiao Bo Zhao for the class 18-447 in
* order to meet the requirements of an ARM processor.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* If you modify the software you must place a notice on or within any
* modified version provided or made available to any third party stating
* that you have modified the software. The notice shall include at least
* your name, address, phone number, email address and the date and purpose
* of the modification.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANYWARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*/
module regfile
(
// Outputs
rn_data, rm_data, rs_data, pc_out, cpsr_out,
// Inputs
rn_num, rm_num, rs_num, rd_num, rd_data, rd_we,
pc_in, pc_we, cpsr_in, cpsr_we,
clk, rst_b, halted
);
parameter text_start = 32'h00400000; /* Initial value of PC */
input [3:0] rn_num, rm_num, rs_num, rd_num;
input [31:0] rd_data, pc_in, cpsr_in;
input rd_we, pc_we, cpsr_we, clk, rst_b, halted;
output wire [31:0] rn_data, rm_data, rs_data, pc_out, cpsr_out;
reg [31:0] mem[0:15];
reg [31:0] cpsr;
integer i;
always @(posedge clk or negedge rst_b) begin
if (!rst_b) begin
for (i = 0; i < 15; i = i+1)
mem[i] <= 32'b0;
mem[15] <= text_start;
cpsr <= 32'b0;
end else begin
if (rd_we && (rd_num != 4'd15))
mem[rd_num] <= rd_data;
if (pc_we)
mem[4'd15] <= pc_in;
if (cpsr_we)
cpsr <= cpsr_in;
end
end
assign rn_data = mem[rn_num];
assign rm_data = mem[rm_num];
assign rs_data = mem[rs_num];
assign pc_out = mem[4'd15];
assign cpsr_out = cpsr;
// synthesis translate_off
//synopsys translate_off
integer fd;
always @(halted) begin
if (rst_b && halted) begin
fd = $fopen("regdump.txt");
$display("--- 18-447 Register file dump ---");
$display("=== Simulation Cycle %d ===", $time);
$fdisplay(fd, "--- 18-447 Register file dump ---");
$fdisplay(fd, "=== Simulation Cycle %d ===", $time);
for(i = 0; i < 16; i = i+1) begin
$display("R%d\t= 0x%8x\t( %0d )", i, mem[i], mem[i]);
$fdisplay(fd, "R%d\t= 0x%8h\t( %0d )", i, mem[i], mem[i]);
end
$display("CPSR\t= 0x%8x\t( %0d )", cpsr, cpsr);
$fdisplay(fd, "CPSR\t= 0x%8h\t( %0d )", cpsr, cpsr);
$display("--- End register file dump ---");
$fdisplay(fd, "--- End register file dump ---");
$fclose(fd);
end
end
//synopsys translate_on
// synthesis translate_on
endmodule
|
// --------------------------------------------------------------------
// ng_PAR Parity Generator Checker Module
// --------------------------------------------------------------------
`include "ControlPulses.h"
// --------------------------------------------------------------------
module ng_PAR(
input CLK2, // Clock Pulse 1
input CLR_PAR_ALM, // Clear Parity Alarm
input M_IN16, // Memory bit 16 input
input [100:0] CP, // Control Pulse
input [ 5:0] SELECT, // Select Input
input [ 15:0] WRITE_BUS, // Control Pulse
output M_OUT16, // Parity output
output PARALM // Parity Alarm Output
);
wire GENRST = CP[85]; // General reset signal
wire CLG = CP[`CPX(`CLG)]; // CP signal - Clear G
wire WGX = CP[36]; // CP signal - Write G (do not reset)
wire SBWG = CP[94]; // CP signal - Write G from memory
wire GP = CP[4]; // CP signal - Generate Parity
wire RP2 = CP[13]; // CP signal - Read parity 2
wire WP = CP[41]; // CP signal - Write P
wire WPX = CP[42]; // CP signal - Write P (do not reset)
wire WP2 = CP[43]; // CP signal - Write P2
wire TP = CP[29]; // CP signal - Test parity
wire WE = CP[96]; // CP signal - Write E-MEM from G
wire RG = CP[11]; // CP signal - Read G
wire GTR_27 = SELECT[4]; // Get SELECT signal
wire PR_RST = !(!GENRST & CLK2);
wire PR_CG15 = !(!CLG & CLK2);
wire PR_WG15 = !(!(WGX & SBWG & GP & RP2) & CLK2);
wire PR_WP = !(!(WP & WPX) & CLK2);
wire PR_WP2 = !(!WP2 & CLK2);
wire PR_WPLM = !(((TP | GTR_27 | !PR_P_15) | !PR_RST) & CLK2);
wire PR_D0 = !(!(!RP2 & PR_P2) & !(!GP & PR_1_15) & !(!SBWG & M_IN16) & !(!WGX & PR_1_15));
wire PR_D7 = !(!PR_G15 & RG);
// --------------------------------------------------------------------
// Register Storage
// --------------------------------------------------------------------
reg [ 15:0] P; // Parity Register
reg P2; // P2 Register
reg G15; // G15 Register
reg PALM; // PALM Register
// --------------------------------------------------------------------
// Instantiate Register P2 Latch
// --------------------------------------------------------------------
always @(negedge PR_WP2 or negedge PR_RST) begin
if(!PR_RST) P2 <= 1'b0;
else P2 <= PR_1_15;
end
wire PR_P2 = P2;
// --------------------------------------------------------------------
// Instantiate Register G15 Latch
// --------------------------------------------------------------------
always @(negedge PR_WG15 or negedge PR_CG15) begin
if(!PR_CG15) G15 <= 1'b0;
else G15 <= PR_D0;
end
wire PR_G15 = G15;
assign M_OUT16 = WE ? 1'bZ : PR_G15;
// --------------------------------------------------------------------
// Instantiate Register PALM Latch
// --------------------------------------------------------------------
always @(negedge PR_WPLM or negedge CLR_PAR_ALM) begin
if(!CLR_PAR_ALM) PALM <= 1'b0;
else PALM <= PR_RST & PR_P_15;
end
assign PARALM = PALM;
// --------------------------------------------------------------------
// Instantiate Register H Latch
// --------------------------------------------------------------------
always @(negedge PR_WP or negedge PR_RST) begin
if(!PR_RST) P <= 16'h0000;
else P <= {PR_D7,WRITE_BUS[14:0]};
end
wire PR_1_15 = ^P[14:0]; // Generate ODD Parity
wire PR_P_15 = PR_1_15 ^ P[15]; // Generate the alarm
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GPIOV2_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_GPIOV2_PP_BLACKBOX_V
/**
* top_gpiov2: General Purpose I/0.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_gpiov2 (
OUT ,
OE_N ,
HLD_H_N ,
ENABLE_H ,
ENABLE_INP_H ,
ENABLE_VDDA_H ,
ENABLE_VSWITCH_H,
ENABLE_VDDIO ,
INP_DIS ,
IB_MODE_SEL ,
VTRIP_SEL ,
SLOW ,
HLD_OVR ,
ANALOG_EN ,
ANALOG_SEL ,
ANALOG_POL ,
DM ,
PAD ,
PAD_A_NOESD_H ,
PAD_A_ESD_0_H ,
PAD_A_ESD_1_H ,
AMUXBUS_A ,
AMUXBUS_B ,
IN ,
IN_H ,
TIE_HI_ESD ,
TIE_LO_ESD ,
VDDIO ,
VDDIO_Q ,
VDDA ,
VCCD ,
VSWITCH ,
VCCHIB ,
VSSA ,
VSSD ,
VSSIO_Q ,
VSSIO
);
input OUT ;
input OE_N ;
input HLD_H_N ;
input ENABLE_H ;
input ENABLE_INP_H ;
input ENABLE_VDDA_H ;
input ENABLE_VSWITCH_H;
input ENABLE_VDDIO ;
input INP_DIS ;
input IB_MODE_SEL ;
input VTRIP_SEL ;
input SLOW ;
input HLD_OVR ;
input ANALOG_EN ;
input ANALOG_SEL ;
input ANALOG_POL ;
input [2:0] DM ;
inout PAD ;
inout PAD_A_NOESD_H ;
inout PAD_A_ESD_0_H ;
inout PAD_A_ESD_1_H ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
output IN ;
output IN_H ;
output TIE_HI_ESD ;
output TIE_LO_ESD ;
inout VDDIO ;
inout VDDIO_Q ;
inout VDDA ;
inout VCCD ;
inout VSWITCH ;
inout VCCHIB ;
inout VSSA ;
inout VSSD ;
inout VSSIO_Q ;
inout VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GPIOV2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> ostream& operator<<(ostream& os, const pair<T1, T2>& p) { os << { << p.first << , << p.second << } ; return os; } template <class T> ostream& operator<<(ostream& os, const vector<T>& p) { os << [ ; int i = 0; for (typename vector<T>::const_iterator it = p.begin(); it != p.end(); ++it) { os << (i == 0 ? : , ) << *it; i++; } os << ] ; return os; } template <class T> ostream& operator<<(ostream& os, const set<T>& p) { os << [ ; int i = 0; for (typename set<T>::const_iterator it = p.begin(); it != p.end(); ++it) { os << (i == 0 ? : , ) << *it; i++; } os << ] ; return os; } template <class K, class V> ostream& operator<<(ostream& os, const map<K, V>& p) { os << [ ; int i = 0; for (typename map<K, V>::const_iterator it = p.begin(); it != p.end(); ++it) { os << (i == 0 ? : , ) << *it; i++; } os << ] ; return os; } template <class T> string toString(const T& o) { stringstream ss; ss << o; string ret; getline(ss, ret); return ret; } template <class T> vector<T> subv(const vector<T>& v, int from, int to) { return vector<T>(v.begin() + min(max(0, from), (int)v.size()), v.begin() + min(max(0, to), (int)v.size())); } pair<int, int> operator+(const pair<int, int>& a, const pair<int, int>& b) { return make_pair(a.first + b.first, a.second + b.second); } pair<int, int> operator*(const int& a, const pair<int, int>& b) { return make_pair(a * b.first, a * b.second); } vector<int> sex, parent, used[2], path, bestw[2]; vector<int> was; vector<int> points; vector<vector<int> > adj; vector<pair<int, int> > w[2], o[2]; int k, mark, n; void dfs(int v, int color) { if (was[v] == color) { points.push_back(v); return; } if (was[v]) return; was[v] = color; for (int i = 0; i < adj[v].size(); ++i) dfs(adj[v][i], color); } void go(int v) { if (used[k][v]) return; used[k][v] = 1; w[k][v] = o[k][v] = make_pair(0, 0); for (int i = 0; i < adj[v].size(); ++i) { int to = adj[v][i]; go(to); if (mark != to) o[k][v] = o[k][v] + max(w[k][to], o[k][to]); } for (int i = 0; i < adj[v].size(); ++i) { int to = adj[v][i]; if (to == mark) continue; pair<int, int> val = o[k][v] + (-1) * max(w[k][to], o[k][to]) + o[k][to] + make_pair(1, sex[v] != sex[to]); if (w[k][v] < val) { bestw[k][v] = to; w[k][v] = val; } } } void make_path(int v, bool with) { int to = -1; if (with) { to = bestw[k][v]; path[to] = 1; } for (int i = 0; i < adj[v].size(); ++i) { int to2 = adj[v][i]; if (to2 != mark) make_path(to2, (to2 != to) && (w[k][to2] > o[k][to2])); } } int main() { cin >> n; adj.resize(n); sex.resize(n); path.resize(n, 0); parent.resize(n); was.resize(n, 0); for (int i = 0; i < 2; ++i) { bestw[i].resize(n, -1); w[i].resize(n); o[i].resize(n); used[i].resize(n, 0); } for (int i = 0; i < n; ++i) { int f, s; cin >> f >> s; f--, s--; parent[i] = f; sex[i] = s; adj[f].push_back(i); } for (int i = 0; i < n; ++i) if (!was[i]) dfs(i, i + 1); for (int i = 0; i < points.size(); ++i) { int v1 = points[i]; int v2 = parent[v1]; k = 0; mark = v1; go(v1); k = 1; mark = v2; go(v2); int v; if (max(o[0][v1], w[0][v1]) > max(o[1][v2], w[1][v2])) { k = 0; v = v1; mark = v1; } else { k = 1; v = v2; mark = v2; } make_path(v, w[k][v] > o[k][v]); } int all = 0, diff = 0; for (int i = 0; i < n; ++i) if (path[i]) { all++; diff += (sex[i] != sex[parent[i]]); } cout << all << << diff << endl; for (int i = 0; i < n; ++i) if (path[i]) cout << i + 1 << << parent[i] + 1 << endl; return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate a lval concat in a continuous assignment
//
// D: Validate that an lvalue can be a concatenation.
//
module main ();
wire a, b;
reg [1:0] c;
reg working;
assign {a,b} = c;
initial
begin
working = 1;
c = 2'b00 ;
#1 if( (a !== 0) & (b !== 0))
begin
$display("FAILED - {a,b} Expected 2'b00 - received %b%b",a,b);
working = 0;
end
c = 2'b01 ;
#1 if( (a !== 0) & (b !== 1))
begin
$display("FAILED {a,b} Expected 2'b01 - received %b%b",a,b);
working = 0;
end
c = 2'b10 ;
#1 if( (a !== 1) & (b !== 0))
begin
$display("FAILED {a,b} Expected 2'b10 - received %b%b",a,b);
working = 0;
end
c = 2'b11 ;
#1 if( (a !== 1) & (b !== 1))
begin
$display("FAILED {a,b} Expected 2'b11 - received %b%b",a,b);
working = 0;
end
#1 if(working)
$display("PASSED\n");
end
endmodule
|
//=================================================
// NORMALISED THRESHOLD DETECTOR MODULE
//=================================================
module DETECTOR(
input SYS_CLK,
input RST,
input [13:0] TIME,
input [23:0] THRESHOLD,
input [29:0] Y,
input [25:0] sumXsq,
output reg [59:0] Yn_NUM,
output reg [49:0] Yn_DEN,
output reg DETECTION
);
wire [59:0] CORRELATION_NUMERATOR;
wire [49:0] CORRELATION_DENOMINATOR;
MULT_FIRSQ MULT_FIRSQ_instant (
.dataa ( Y ),
.result ( CORRELATION_NUMERATOR )
);
MULT_sumXsq MULT_sumXsq_instant (
.dataa ( sumXsq ),
.datab ( THRESHOLD ),
.result ( CORRELATION_DENOMINATOR )
);
reg [29:0] Y_input;
always @(posedge SYS_CLK) begin
if (RST) begin
Y_input <= 0;
Yn_NUM <= 0;
Yn_DEN <= 0;
DETECTION <= 0;
end
else if (TIME > 274) begin
Y_input <= Y;
Yn_NUM <= CORRELATION_NUMERATOR;
Yn_DEN <= CORRELATION_DENOMINATOR;
DETECTION <= (Yn_NUM > Yn_DEN) & ~Y_input[29]; // Use > logic to avoid 0 = 0 case
end
else begin
DETECTION <= 0;
end
end
endmodule
//=================================================
// END NORMALISED THRESHOLD DETECTOR MODULE
//=================================================
|
#include <bits/stdc++.h> using namespace std; char ans[10][10]; long long dp[10][513][513]; pair<pair<long long, long long>, long long> recur[10][513][513]; long long insert[10][513][513]; long long curr, nexty, n, m; long long setBit(long long num, long long i) { return num | (1 << i); } long long unsetBit(long long num, long long i) { num ^= 1 << i; return num; } bool checkBit(long long num, long long i) { if (num & 1 << i) return true; else return false; } string binary(long long num, long long m) { string ans; for (long long i = 0; i < m; i++) { if (checkBit(num, i)) ans = 1 + ans; else ans = 0 + ans; } return ans; } void backtrack(long long j, long long mask1, long long mask2, long long mask3, long long newT, long long ogmask1, long long ogmask2, long long ts) { if (j == m) { if (dp[curr][ogmask1][ogmask2] + newT > dp[nexty][mask2][mask3]) { dp[nexty][mask2][mask3] = dp[curr][ogmask1][ogmask2] + newT; recur[nexty][mask2][mask3] = pair<pair<long long, long long>, long long>( pair<long long, long long>(ogmask1, ogmask2), mask1); insert[nexty][mask2][mask3] = ts; } return; } if (j > 1) { if (!checkBit(mask1, j) && !checkBit(mask1, j - 1) && !checkBit(mask1, j - 2) && !checkBit(mask2, j - 1) && !checkBit(mask3, j - 1)) { long long tempmask1 = setBit(mask1, j); tempmask1 = setBit(tempmask1, j - 1); tempmask1 = setBit(tempmask1, j - 2); backtrack(j + 1, tempmask1, setBit(mask2, j - 1), setBit(mask3, j - 1), newT + 1, ogmask1, ogmask2, ts); } } if (j > 1) { if (!checkBit(mask1, j - 1) && !checkBit(mask2, j - 1) && !checkBit(mask3, j - 1) && !checkBit(mask3, j) && !checkBit(mask3, j - 2)) { long long newmask = setBit(mask3, j - 1); newmask = setBit(newmask, j); newmask = setBit(newmask, j - 2); backtrack(j + 1, setBit(mask1, j - 1), setBit(mask2, j - 1), newmask, newT + 1, ogmask1, ogmask2, setBit(ts, 2 * (j - 1) + 1)); } } if (j > 1) { if (!checkBit(mask1, j - 2) && !checkBit(mask3, j - 2) && !checkBit(mask2, j) && !checkBit(mask2, j - 1) && !checkBit(mask2, j - 2)) { long long newmask = setBit(mask2, j); newmask = setBit(newmask, j - 1); newmask = setBit(newmask, j - 2); backtrack(j + 1, setBit(mask1, j - 2), newmask, setBit(mask3, j - 2), newT + 1, ogmask1, ogmask2, setBit(ts, 2 * (j - 2))); } } if (j > 1) { if (!checkBit(mask1, j) && !checkBit(mask3, j) && !checkBit(mask2, j) && !checkBit(mask2, j - 1) && !checkBit(mask2, j - 2)) { long long newmask = setBit(mask2, j); newmask = setBit(newmask, j - 1); newmask = setBit(newmask, j - 2); ts = setBit(ts, 2 * j); ts = setBit(ts, 2 * j + 1); backtrack(j + 1, setBit(mask1, j), newmask, setBit(mask3, j), newT + 1, ogmask1, ogmask2, ts); ts = unsetBit(ts, 2 * j); ts = unsetBit(ts, 2 * j + 1); } } backtrack(j + 1, mask1, mask2, mask3, newT, ogmask1, ogmask2, ts); } char currchar = A ; void recursion(long long i, long long mask1, long long mask2) { if (i == 0) return; recursion(i - 1, recur[i][mask1][mask2].first.first, recur[i][mask1][mask2].first.second); long long mask = insert[i][mask1][mask2]; for (long long j = 0; j < m; j++) { if (!checkBit(recur[i][mask1][mask2].second, j)) { ans[i][j] = . ; continue; } if (checkBit(mask, j * 2) && checkBit(mask, j * 2 + 1)) { ans[i][j] = ans[i + 1][j] = ans[i + 2][j] = ans[i + 1][j - 1] = ans[i + 1][j - 2] = currchar; currchar++; } else if (checkBit(mask, j * 2) && !checkBit(mask, j * 2 + 1)) { ans[i][j] = ans[i + 1][j + 2] = ans[i + 2][j] = ans[i + 1][j + 1] = ans[i + 1][j] = currchar; currchar++; } else if (!checkBit(mask, j * 2) && checkBit(mask, j * 2 + 1)) { ans[i][j] = ans[i + 1][j] = ans[i + 2][j + 1] = ans[i + 2][j - 1] = ans[i + 2][j] = currchar; currchar++; } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; memset(dp, -1, sizeof(dp)); memset(ans, 0, sizeof(ans)); dp[0][0][0] = 0; for (long long i = 0; i < n; i++) { curr = i; nexty = i + 1; for (long long mask1 = 0; mask1 < (1 << m); mask1++) { for (long long mask2 = 0; mask2 < (1 << m); mask2++) { if (dp[curr][mask1][mask2] != -1) { backtrack(0, mask1, mask2, 0, 0, mask1, mask2, 0); } } } } cout << dp[n][0][0] << n ; recursion(n, 0, 0); for (long long i = 1; i <= n; i++) { for (long long j = 0; j < m; j++) { if (ans[i][j] == 0 && ans[i][j - 1] == 0 && ans[i][j + 1] == 0 && ans[i + 1][j] == 0 && ans[i + 2][j] == 0) { ans[i][j] = ans[i][j - 1] = ans[i][j + 1] = ans[i + 1][j] = ans[i + 2][j] = currchar; currchar++; } } } for (long long i = 1; i <= n; i++) { for (long long j = 0; j < m; j++) cout << ans[i][j]; cout << n ; } }
|
module main;
wire [2:0] value1, value2, value3, value4;
dut #( .select(1) ) dut1(value1);
dut #( .select(2) ) dut2(value2);
dut #( .select(3) ) dut3(value3);
dut #( .select(4) ) dut4(value4);
initial begin
#1 $display("value1=%d, value2=%d, value3=%d, value4=%d",
value1, value2, value3, value4);
if (value1 !== 1) begin
$display("FAILED -- value1=%b", value1);
$finish;
end
if (value2 !== 2) begin
$display("FAILED -- value2=%b", value2);
$finish;
end
if (value3 !== 3) begin
$display("FAILED -- value3=%b", value3);
$finish;
end
if (value4 !== 7) begin
$display("FAILED -- value4=%b", value4);
$finish;
end
$display("PASSED");
end
endmodule // main
module dut(output wire [2:0] value);
parameter select = 0;
case (select)
0: begin
function [2:0] funfun;
input integer in;
funfun = in;
endfunction // funfun
assign value = funfun(select);
end
1: begin
function [2:0] funfun;
input integer in;
funfun = in;
endfunction // funfun
assign value = funfun(1);
end
2: assign value = 2;
3: assign value = 3;
default:
assign value = 7;
endcase // case endcase
endmodule // dut
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:26:35 03/30/2016
// Design Name:
// Module Name: MAIN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MAIN(ALU_OP, AB_SW, F_LED_SW, LED
);
// TOP MODULE FOR TEST
input wire [2:0] ALU_OP;
input wire [2:0] AB_SW;
input [2:0] F_LED_SW;
output reg [7:0] LED;
wire [31:0] F;
wire ZF, OF;
reg[31:0] A,B;
always@(*)
begin
case(AB_SW)
3'b000:begin A=32'h0000_0000; B=32'h0000_0000; end
3'b001:begin A=32'h0000_0003; B=32'h0000_0607; end
3'b010:begin A=32'h8000_0000; B=32'h8000_0000; end
3'b011:begin A=32'h7FFF_FFFF; B=32'h7FFF_FFFF; end
3'b100:begin A=32'hFFFF_FFFF; B=32'hFFFF_FFFF; end
3'b101:begin A=32'h8000_0000; B=32'hFFFF_FFFF; end
3'b110:begin A=32'hFFFF_FFFF; B=32'h8000_0000; end
3'b111:begin A=32'h1234_5678; B=32'h3333_2222; end
default:
begin A = 32'h9ABC_DEF0; B = 32'h1111_2222; end
endcase
end
ALU ALU (
.A(A),
.B(B),
.ZF(ZF),
.OF(OF),
.F(F),
.ALU_OP(ALU_OP)
);
always@(*)
begin
case(F_LED_SW)
3'b000: begin LED = F[7:0]; end
3'b001: begin LED = F[15:8]; end
3'b010: begin LED = F[23:16]; end
3'b011: begin LED = F[31:24]; end
default:begin LED[7] = ZF; LED[0] = OF; LED[6:1] = 6'b0; end
endcase
end
endmodule
module ALU(A, B, ZF, OF, F, ALU_OP);
input [2:0] ALU_OP;
input [31:0] A, B;
output reg [31:0] F;
output reg ZF, OF;
reg C32;
always @(*)
begin
case(ALU_OP)
3'd0:begin //and
F = A&B;
OF = 0;
end
3'd1:begin //or
F = A|B;
OF = 0;
end
3'd2:begin //xor
F = A^B;
OF = 0;
end
3'd3:begin //nor
F = ~(A|B);
OF = 0;
end
3'd4:begin //add
{C32, F} = A + B;
OF = A[31]^B[31]^F[31]^C32;
end
3'd5:begin //sub
{C32, F} = A - B;
OF = A[31]^B[31]^F[31]^C32;
end
3'd6:begin //slt
if (A<B)
begin
F = 32'd1;
end
else
begin
F = 32'd0;
end
OF = 0;
end
3'd7:begin //sll
F=B<<A;
OF=0;
end
default:begin
F=A;
OF = 0;
end
endcase
if (F == 32'd0)
begin
ZF = 1;
end
else
begin
ZF = 0;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// Very simple test for interface pathclearing
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc #(2) itopa();
ifc #(4) itopb();
sub ca (.isub(itopa),
.clk);
sub cb (.isub(itopb),
.clk);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo);
`endif
cyc <= cyc + 1;
itopa.valuei <= cyc[1:0];
itopb.valuei <= cyc[3:0];
if (cyc==1) begin
if (itopa.WIDTH != 2) $stop;
if (itopb.WIDTH != 4) $stop;
if ($bits(itopa.valueo) != 2) $stop;
if ($bits(itopb.valueo) != 4) $stop;
if ($bits(itopa.out_modport.valueo) != 2) $stop;
if ($bits(itopb.out_modport.valueo) != 4) $stop;
end
if (cyc==4) begin
if (itopa.valueo != 2'b11) $stop;
if (itopb.valueo != 4'b0011) $stop;
end
if (cyc==5) begin
if (itopa.valueo != 2'b00) $stop;
if (itopb.valueo != 4'b0100) $stop;
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
interface ifc
#(parameter WIDTH = 1);
// verilator lint_off MULTIDRIVEN
logic [WIDTH-1:0] valuei;
logic [WIDTH-1:0] valueo;
// verilator lint_on MULTIDRIVEN
modport out_modport (input valuei, output valueo);
endinterface
// Note not parameterized
module sub
(
ifc.out_modport isub,
input clk
);
always @(posedge clk) isub.valueo <= isub.valuei + 1;
endmodule
|
//
// Copyright (c) 2003 Launchbird Design Systems, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
// Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// Overview:
//
// Performs finite impulse response (FIR) filtering.
// The filter's sum of products is pipelined with a register after
// every multiplier and adder. The adder network is a balanced binary
// tree to minimize latency. The sum of products has no numeric loss because the
// multipliers keep all resulting bits and each adder extends the precision by 1.
//
// Interface:
//
// Synchronization:
// clock_c : Clock input.
// reset_i : Filter delay bank synchronous reset. Does not reset sum of products pipeline registers.
//
// Inputs:
// data_i : Input data.
// k0_i : Coefficient 0 multiplied by in_i(0).
// k1_i : Coefficient 1 multiplied by in_i(k-1).
// k2_i : Coefficient 2 multiplied by in_i(k-2).
// ...
// k<order>_i : Coefficient <order> multiplied by in_i(k-<order>).
//
// Outputs:
// data_o : Output data.
//
// Built In Parameters:
//
// Filter Order = 3
// Input Precision = 8
// Coefficient Precision = 8
// Sum of Products Latency = 3
//
//
//
//
// Generated by Confluence 0.6.3 -- Launchbird Design Systems, Inc. -- www.launchbird.com
//
// Build Date : Fri Aug 22 09:45:46 CDT 2003
//
// Interface
//
// Build Name : cf_fir_3_8_8
// Clock Domains : clock_c
// Vector Input : reset_i(1)
// Vector Input : data_i(8)
// Vector Input : k0_i(8)
// Vector Input : k1_i(8)
// Vector Input : k2_i(8)
// Vector Input : k3_i(8)
// Vector Output : data_o(18)
//
//
//
module cf_fir_3_8_8 (clock_c, reset_i, data_i, k0_i, k1_i, k2_i, k3_i, data_o);
input clock_c;
input reset_i;
input [7:0] data_i;
input [7:0] k0_i;
input [7:0] k1_i;
input [7:0] k2_i;
input [7:0] k3_i;
output [17:0] data_o;
wire [17:0] n1;
cf_fir_3_8_8_1 s1 (clock_c, reset_i, k0_i, k1_i, k2_i, k3_i, data_i, n1);
assign data_o = n1;
endmodule
module cf_fir_3_8_8_1 (clock_c, i1, i2, i3, i4, i5, i6, o1);
input clock_c;
input i1;
input [7:0] i2;
input [7:0] i3;
input [7:0] i4;
input [7:0] i5;
input [7:0] i6;
output [17:0] o1;
wire n1;
wire n2;
wire [17:0] s3_1;
assign n1 = 1'b1;
assign n2 = 1'b0;
cf_fir_3_8_8_2 s3 (clock_c, n1, n2, i1, i2, i3, i4, i5, i6, s3_1);
assign o1 = s3_1;
endmodule
module cf_fir_3_8_8_2 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, o1);
input clock_c;
input i1;
input i2;
input i3;
input [7:0] i4;
input [7:0] i5;
input [7:0] i6;
input [7:0] i7;
input [7:0] i8;
output [17:0] o1;
reg [7:0] n1;
reg [7:0] n2;
reg [7:0] n3;
reg [7:0] n4;
wire n5;
wire [17:0] n6;
wire n7;
wire [17:0] n8;
wire [17:0] n9;
reg [17:0] n10;
wire [16:0] s11_1;
wire [16:0] s11_2;
wire [15:0] s12_1;
wire [15:0] s12_2;
wire [15:0] s12_3;
wire [15:0] s12_4;
always @ (posedge clock_c)
begin
if (i3 == 1'b1)
n1 <= 8'b00000000;
else if (i1 == 1'b1)
n1 <= i8;
if (i3 == 1'b1)
n2 <= 8'b00000000;
else if (i1 == 1'b1)
n2 <= n1;
if (i3 == 1'b1)
n3 <= 8'b00000000;
else if (i1 == 1'b1)
n3 <= n2;
if (i3 == 1'b1)
n4 <= 8'b00000000;
else if (i1 == 1'b1)
n4 <= n3;
if (i2 == 1'b1)
n10 <= 18'b000000000000000000;
else if (i1 == 1'b1)
n10 <= n9;
end
assign n5 = s11_1[16];
assign n6 = {n5, s11_1};
assign n7 = s11_2[16];
assign n8 = {n7, s11_2};
assign n9 = n6 + n8;
cf_fir_3_8_8_4 s11 (clock_c, i1, i2, s12_1, s12_2, s12_3, s12_4, s11_1, s11_2);
cf_fir_3_8_8_3 s12 (clock_c, i1, i2, i4, i5, i6, i7, n1, n2, n3, n4, s12_1, s12_2, s12_3, s12_4);
assign o1 = n10;
endmodule
module cf_fir_3_8_8_3 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, o1, o2, o3, o4);
input clock_c;
input i1;
input i2;
input [7:0] i3;
input [7:0] i4;
input [7:0] i5;
input [7:0] i6;
input [7:0] i7;
input [7:0] i8;
input [7:0] i9;
input [7:0] i10;
output [15:0] o1;
output [15:0] o2;
output [15:0] o3;
output [15:0] o4;
wire [15:0] n1;
reg [15:0] n2;
wire [15:0] n3;
reg [15:0] n4;
wire [15:0] n5;
reg [15:0] n6;
wire [15:0] n7;
reg [15:0] n8;
assign n1 = {8'b00000000, i3} * {8'b00000000, i7};
always @ (posedge clock_c)
begin
if (i2 == 1'b1)
n2 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n2 <= n1;
if (i2 == 1'b1)
n4 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n4 <= n3;
if (i2 == 1'b1)
n6 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n6 <= n5;
if (i2 == 1'b1)
n8 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n8 <= n7;
end
assign n3 = {8'b00000000, i4} * {8'b00000000, i8};
assign n5 = {8'b00000000, i5} * {8'b00000000, i9};
assign n7 = {8'b00000000, i6} * {8'b00000000, i10};
assign o4 = n8;
assign o3 = n6;
assign o2 = n4;
assign o1 = n2;
endmodule
module cf_fir_3_8_8_4 (clock_c, i1, i2, i3, i4, i5, i6, o1, o2);
input clock_c;
input i1;
input i2;
input [15:0] i3;
input [15:0] i4;
input [15:0] i5;
input [15:0] i6;
output [16:0] o1;
output [16:0] o2;
wire n1;
wire [16:0] n2;
wire n3;
wire [16:0] n4;
wire [16:0] n5;
reg [16:0] n6;
wire n7;
wire [16:0] n8;
wire n9;
wire [16:0] n10;
wire [16:0] n11;
reg [16:0] n12;
assign n1 = i3[15];
assign n2 = {n1, i3};
assign n3 = i4[15];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
if (i2 == 1'b1)
n6 <= 17'b00000000000000000;
else if (i1 == 1'b1)
n6 <= n5;
if (i2 == 1'b1)
n12 <= 17'b00000000000000000;
else if (i1 == 1'b1)
n12 <= n11;
end
assign n7 = i5[15];
assign n8 = {n7, i5};
assign n9 = i6[15];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
assign o2 = n12;
assign o1 = n6;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int MAX = 1000005; int SetBit(int n, int x) { return n | (1 << x); } int ClearBit(int n, int x) { return n & ~(1 << x); } int ToggleBit(int n, int x) { return n ^ (1 << x); } bool CheckBit(int n, int x) { return (bool)(n & (1 << x)); } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int w, y, max; cin >> w >> y; int a; if (w > y) { max = w; } else if (w == y) { max = w; } else { max = y; } if ((w == 6 && y == 6)) { cout << 1 << / << 6 << endl; } else if ((w == 6 && (y == 1 || y == 2 || y == 3 || y == 4 || y == 5))) { cout << 1 << / << 6 << endl; } else if ((y == 6 && (w == 1 || w == 2 || w == 3 || w == 4 || w == 5))) { cout << 1 << / << 6 << endl; } else { a = 6 - max + 1; if (a == 2) { cout << 1 << / << 3 << endl; } if (a == 3) { cout << 1 << / << 2 << endl; } if (a == 4) { cout << 2 << / << 3 << endl; } if (a == 5 || a == 1) { cout << a << / << 6 << endl; } if (a == 6) { cout << 1 << / << 1 << endl; } } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; vector<vector<pair<int, int>>> g; vector<pair<int, pair<int, int>>> edg; int cp[100010]; int find(int x) { return cp[x] = cp[x] == x ? x : find(cp[x]); } void union_(int x, int y) { cp[find(x)] = find(y); } int h[100010]; int anc[100010][18]; int val[100010][18]; void dfs_preprocess(int u, int p = -1) { anc[u][0] = p; if (~p) { h[u] = h[p] + 1; } for (int i = 1; i < 18; ++i) { if (~anc[u][i - 1]) { anc[u][i] = anc[anc[u][i - 1]][i - 1]; val[u][i] = max(val[anc[u][i - 1]][i - 1], val[u][i - 1]); } } for (auto v : g[u]) { if (v.second != p) { val[v.second][0] = v.first; dfs_preprocess(v.second, u); } } } int LCA(int v, int u) { if (h[v] < h[u]) swap(u, v); int val_ans = 0; for (int i = 18 - 1; i >= 0; --i) { if (anc[v][i] + 1 && h[anc[v][i]] >= h[u]) { val_ans = max(val_ans, val[v][i]); v = anc[v][i]; } } if (v == u) return val_ans; for (int i = 18 - 1; i >= 0; --i) { if (anc[v][i] != anc[u][i]) { val_ans = max({val_ans, val[v][i], val[u][i]}); v = anc[v][i]; u = anc[u][i]; } } val_ans = max({val_ans, val[v][0], val[u][0]}); return val_ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < n; ++i) cp[i] = i; g.assign(n, vector<pair<int, int>>()); map<pair<int, int>, int> mp; int id = 0; for (int i = 0; i < m; ++i) { int u, v, w; cin >> u >> v >> w; u--, v--; mp[{u, v}] = id++; edg.push_back({w, {u, v}}); } sort((edg).begin(), (edg).end()); vector<int> mst(m, 0); memset(anc, -1, sizeof(anc)); for (int i = 0; i < m; ++i) { int u = edg[i].second.first, v = edg[i].second.second, w = edg[i].first; if (find(u) != find(v)) { union_(u, v); g[u].push_back({w, v}); g[v].push_back({w, u}); mst[i] = 1; } } dfs_preprocess(0); vector<int> ans(m, -1); for (int i = 0; i < m; ++i) { if (!mst[i]) { ans[mp[edg[i].second]] = LCA(edg[i].second.first, edg[i].second.second); } } for (int u : ans) { if (u + 1) cout << u << n ; } }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:12:26 12/16/2015
// Design Name: uart2_rx
// Module Name: H:/Firmware/font5_base_new/font5_base/font5-firmware/uart2_rx_tb.v
// Project Name: font5_base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: uart2_rx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module uart2_rx_tb;
//localparam real BAUD_PERIOD = 104166.667; // 9600 Baud
localparam real BAUD_PERIOD = 2170.139; // 460.8 kBaud
// Inputs
reg reset = 1'b0;
reg clk = 1'b0;
wire uld_rx_data;
reg rx_enable = 1'b1;
reg rx_in = 1'b1;
// Outputs
wire [7:0] rx_data;
wire byte_rdy;
// Instantiate the Unit Under Test (UUT)
uart2_rx #(8, 460800) uut (
.reset(reset),
.clk(clk),
.uld_rx_data(uld_rx_data),
.rx_data(rx_data),
.rx_enable(rx_enable),
.rx_in(rx_in),
.byte_rdy(byte_rdy)
);
uart_unload #(.BYTE_WIDTH(8),.WORD_WIDTH(13)) uart2_uld (.rst(reset), .clk(clk), .byte_rdy(byte_rdy), .unload_uart(uld_rx_data));
initial begin
// Initialize Inputs
reset = 1'b0;
//clk = 1'b0;
//uld_rx_data = 0;
//rx_enable = 0;
rx_in = 1'b1;
// Wait 100 ns for global reset to finish
#100 reset = 1;
// Add stimulus here
#100 reset = 0;
#50 rx_in = 0; //start bit
#BAUD_PERIOD rx_in = 0;
#BAUD_PERIOD rx_in = 1;
#BAUD_PERIOD rx_in = 0;
#BAUD_PERIOD rx_in = 1;
#BAUD_PERIOD rx_in = 0;
#BAUD_PERIOD rx_in = 1;
#BAUD_PERIOD rx_in = 0;
#BAUD_PERIOD rx_in = 0;
#BAUD_PERIOD rx_in = 1; //stop bit
end
initial forever #12.5 clk = ~clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211A_0_V
`define SKY130_FD_SC_LP__O211A_0_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211a_0 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211a_0 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211A_0_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_4_V
`define SKY130_FD_SC_HD__O21A_4_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21a_4 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21a_4 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_4_V
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 12818 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w8,
w9,
w16,
w25,
w6400,
w6409,
w12818;
assign w1 = i_data0;
assign w12818 = w6409 << 1;
assign w16 = w1 << 4;
assign w25 = w9 + w16;
assign w6400 = w25 << 8;
assign w6409 = w9 + w6400;
assign w8 = w1 << 3;
assign w9 = w1 + w8;
assign o_data0 = w12818;
//multiplier_block area estimate = 4211.22249727647;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module contact_discoverycud_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 15;
parameter MEM_SIZE = 19200;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./contact_discoverycud_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module contact_discoverycud(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd19200;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
contact_discoverycud_ram contact_discoverycud_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ));
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module altera_mem_if_ddr3_phy_0001_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe (probe_input),
.source ()
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
iss_probe_inst.enable_metastability = "NO",
iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH,
iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0,
iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
|
module gen_test1(clk, a, b, y);
input clk;
input [7:0] a, b;
output reg [7:0] y;
genvar i, j;
wire [15:0] tmp1;
generate
for (i = 0; i < 8; i = i + 1) begin:gen1
wire and_wire, or_wire;
assign and_wire = a[i] & b[i];
assign or_wire = a[i] | b[i];
if (i % 2 == 0) begin:gen2true
assign tmp1[i] = and_wire;
assign tmp1[i+8] = or_wire;
end else begin:gen2false
assign tmp1[i] = or_wire;
assign tmp1[i+8] = and_wire;
end
end
for (i = 0; i < 8; i = i + 1) begin:gen3
wire [4:0] tmp2;
for (j = 0; j <= 4; j = j + 1) begin:gen4
wire tmpbuf;
assign tmpbuf = tmp1[i+2*j];
assign tmp2[j] = tmpbuf;
end
always @(posedge clk)
y[i] <= ^tmp2;
end
endgenerate
endmodule
// ------------------------------------------
module gen_test2(clk, a, b, y);
input clk;
input [7:0] a, b;
output reg [8:0] y;
integer i;
reg [8:0] carry;
always @(posedge clk) begin
carry[0] = 0;
for (i = 0; i < 8; i = i + 1) begin
casez ({a[i], b[i], carry[i]})
3'b?11, 3'b1?1, 3'b11?:
carry[i+1] = 1;
default:
carry[i+1] = 0;
endcase
y[i] = a[i] ^ b[i] ^ carry[i];
end
y[8] = carry[8];
end
endmodule
// ------------------------------------------
module gen_test3(a, b, sel, y, z);
input [3:0] a, b;
input sel;
output [3:0] y, z;
genvar i;
generate
for (i=0; i < 2; i=i+1)
assign y[i] = sel ? a[i] : b[i], z[i] = sel ? b[i] : a[i];
for (i=0; i < 2; i=i+1) begin
if (i == 0)
assign y[2] = sel ? a[2] : b[2];
else
assign z[2] = sel ? a[2] : b[2];
case (i)
default:
assign z[3] = sel ? a[3] : b[3];
0:
assign y[3] = sel ? a[3] : b[3];
endcase
end
endgenerate
endmodule
// ------------------------------------------
module gen_test4(a, b);
input [3:0] a;
output [3:0] b;
genvar i;
generate
for (i=0; i < 3; i=i+1) begin : foo
localparam PREV = i - 1;
wire temp;
if (i == 0)
assign temp = a[0];
else
assign temp = foo[PREV].temp & a[i];
assign b[i] = temp;
end
endgenerate
endmodule
// ------------------------------------------
module gen_test5(input_bits, out);
parameter WIDTH = 256;
parameter CHUNK = 4;
input [WIDTH-1:0] input_bits;
output out;
genvar step, i, j;
generate
for (step = 1; step <= WIDTH; step = step * CHUNK) begin : steps
localparam PREV = step / CHUNK;
localparam DIM = WIDTH / step;
for (i = 0; i < DIM; i = i + 1) begin : outer
localparam LAST_START = i * CHUNK;
for (j = 0; j < CHUNK; j = j + 1) begin : inner
wire temp;
if (step == 1)
assign temp = input_bits[i];
else if (j == 0)
assign temp = steps[PREV].outer[LAST_START].val;
else
assign temp
= steps[step].outer[i].inner[j-1].temp
& steps[PREV].outer[LAST_START + j].val;
end
wire val;
assign val = steps[step].outer[i].inner[CHUNK - 1].temp;
end
end
endgenerate
assign out = steps[WIDTH].outer[0].val;
endmodule
// ------------------------------------------
module gen_test6(output [3:0] o);
generate
genvar i;
for (i = 3; i >= 0; i = i-1) begin
assign o[i] = 1'b0;
end
endgenerate
endmodule
// ------------------------------------------
module gen_test7;
reg [2:0] out1;
reg [2:0] out2;
wire [2:0] out3;
generate
if (1) begin : cond
reg [2:0] sub_out1;
reg [2:0] sub_out2;
wire [2:0] sub_out3;
initial begin : init
reg signed [31:0] x;
x = 2 ** 2;
out1 = x;
sub_out1 = x;
end
always @* begin : proc
reg signed [31:0] x;
x = 2 ** 1;
out2 = x;
sub_out2 = x;
end
genvar x;
for (x = 0; x < 3; x = x + 1) begin
assign out3[x] = 1;
assign sub_out3[x] = 1;
end
end
endgenerate
// `define VERIFY
`ifdef VERIFY
assert property (out1 == 4);
assert property (out2 == 2);
assert property (out3 == 7);
assert property (cond.sub_out1 == 4);
assert property (cond.sub_out2 == 2);
assert property (cond.sub_out3 == 7);
`endif
endmodule
// ------------------------------------------
module gen_test8;
// `define VERIFY
`ifdef VERIFY
`define ASSERT(expr) assert property (expr);
`else
`define ASSERT(expr)
`endif
wire [1:0] x = 2'b11;
generate
if (1) begin : A
wire [1:0] x;
if (1) begin : B
wire [1:0] x = 2'b00;
`ASSERT(x == 0)
`ASSERT(A.x == 2)
`ASSERT(A.C.x == 1)
`ASSERT(A.B.x == 0)
`ASSERT(gen_test8.x == 3)
`ASSERT(gen_test8.A.x == 2)
`ASSERT(gen_test8.A.C.x == 1)
`ASSERT(gen_test8.A.B.x == 0)
end
if (1) begin : C
wire [1:0] x = 2'b01;
`ASSERT(x == 1)
`ASSERT(A.x == 2)
`ASSERT(A.C.x == 1)
`ASSERT(A.B.x == 0)
`ASSERT(gen_test8.x == 3)
`ASSERT(gen_test8.A.x == 2)
`ASSERT(gen_test8.A.C.x == 1)
`ASSERT(gen_test8.A.B.x == 0)
end
assign x = B.x ^ 2'b11 ^ C.x;
`ASSERT(x == 2)
`ASSERT(A.x == 2)
`ASSERT(A.C.x == 1)
`ASSERT(A.B.x == 0)
`ASSERT(gen_test8.x == 3)
`ASSERT(gen_test8.A.x == 2)
`ASSERT(gen_test8.A.C.x == 1)
`ASSERT(gen_test8.A.B.x == 0)
end
endgenerate
`ASSERT(x == 3)
`ASSERT(A.x == 2)
`ASSERT(A.C.x == 1)
`ASSERT(A.B.x == 0)
`ASSERT(gen_test8.x == 3)
`ASSERT(gen_test8.A.x == 2)
`ASSERT(gen_test8.A.C.x == 1)
`ASSERT(gen_test8.A.B.x == 0)
endmodule
// ------------------------------------------
module gen_test9;
// `define VERIFY
`ifdef VERIFY
`define ASSERT(expr) assert property (expr);
`else
`define ASSERT(expr)
`endif
wire [1:0] w = 2'b11;
generate
begin : A
wire [1:0] x;
begin : B
wire [1:0] y = 2'b00;
`ASSERT(w == 3)
`ASSERT(x == 2)
`ASSERT(y == 0)
`ASSERT(A.x == 2)
`ASSERT(A.C.z == 1)
`ASSERT(A.B.y == 0)
`ASSERT(gen_test9.w == 3)
`ASSERT(gen_test9.A.x == 2)
`ASSERT(gen_test9.A.C.z == 1)
`ASSERT(gen_test9.A.B.y == 0)
end
begin : C
wire [1:0] z = 2'b01;
`ASSERT(w == 3)
`ASSERT(x == 2)
`ASSERT(z == 1)
`ASSERT(A.x == 2)
`ASSERT(A.C.z == 1)
`ASSERT(A.B.y == 0)
`ASSERT(gen_test9.w == 3)
`ASSERT(gen_test9.A.x == 2)
`ASSERT(gen_test9.A.C.z == 1)
`ASSERT(gen_test9.A.B.y == 0)
end
assign x = B.y ^ 2'b11 ^ C.z;
`ASSERT(x == 2)
`ASSERT(A.x == 2)
`ASSERT(A.C.z == 1)
`ASSERT(A.B.y == 0)
`ASSERT(gen_test9.w == 3)
`ASSERT(gen_test9.A.x == 2)
`ASSERT(gen_test9.A.C.z == 1)
`ASSERT(gen_test9.A.B.y == 0)
end
endgenerate
`ASSERT(w == 3)
`ASSERT(A.x == 2)
`ASSERT(A.C.z == 1)
`ASSERT(A.B.y == 0)
`ASSERT(gen_test9.w == 3)
`ASSERT(gen_test9.A.x == 2)
`ASSERT(gen_test9.A.C.z == 1)
`ASSERT(gen_test9.A.B.y == 0)
endmodule
|
#include <bits/stdc++.h> using namespace std; long long arr[200200]; int main() { string a, b; cin >> a >> b; long long x = 0, y = 0; for (int i = 0; i <= b.size() - a.size(); i++) x += (b[i] - 0 ); for (int i = 0; i < a.size(); i++) { y += (a[i] == 0 ) ? x : (b.size() - a.size() + 1) - x; x += b[b.size() - a.size() + 1 + i] - b[i]; } cout << y; return 0; }
|
//2048 words deep, 16 bits wide, fifo
//data is written into the fifo when wr=1
//reading is more or less asynchronous if you read during the rising edge of clk
//because the output data is updated at the falling edge of the clk
//when rd=1, the next data word is selected
module paula_floppy_fifo
(
input clk, //bus clock
input clk7_en,
input reset, //reset
input [15:0] in, //data in
output reg [15:0] out, //data out
input rd, //read from fifo
input wr, //write to fifo
output reg empty, //fifo is empty
output full, //fifo is full
output [11:0] cnt // number of entries in FIFO
);
//local signals and registers
reg [15:0] mem [2047:0]; // 2048 words by 16 bit wide fifo memory (for 2 MFM-encoded sectors)
reg [11:0] in_ptr; //fifo input pointer
reg [11:0] out_ptr; //fifo output pointer
wire equal; //lower 11 bits of in_ptr and out_ptr are equal
// count of FIFO entries
assign cnt = in_ptr - out_ptr;
//main fifo memory (implemented using synchronous block ram)
always @(posedge clk) begin
if (clk7_en) begin
if (wr)
mem[in_ptr[10:0]] <= in;
end
end
always @(posedge clk) begin
if (clk7_en) begin
out=mem[out_ptr[10:0]];
end
end
//fifo write pointer control
always @(posedge clk) begin
if (clk7_en) begin
if (reset)
in_ptr[11:0] <= 0;
else if(wr)
in_ptr[11:0] <= in_ptr[11:0] + 12'd1;
end
end
// fifo read pointer control
always @(posedge clk) begin
if (clk7_en) begin
if (reset)
out_ptr[11:0] <= 0;
else if (rd)
out_ptr[11:0] <= out_ptr[11:0] + 12'd1;
end
end
// check lower 11 bits of pointer to generate equal signal
assign equal = (in_ptr[10:0]==out_ptr[10:0]) ? 1'b1 : 1'b0;
// assign output flags, empty is delayed by one clock to handle ram delay
always @(posedge clk) begin
if (clk7_en) begin
if (equal && (in_ptr[11]==out_ptr[11]))
empty <= 1'b1;
else
empty <= 1'b0;
end
end
assign full = (equal && (in_ptr[11]!=out_ptr[11])) ? 1'b1 : 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFXTP_BEHAVIORAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; int n, x = 1, y = 1; cin >> n; while (n--) { cin >> s; if (s == ULDR ) x++, y++; else if (s == UR || s == DL ) x++; else y++; } cout << 1LL * x * y << endl; }
|
module top;
real rval1, rval2;
reg val1, val2;
reg [3:0] wval1, wval2;
reg [1:0] wres;
reg res;
reg pass;
initial begin
pass = 1'b1;
val1 = 1'b0;
val2 = 1'b0;
res = val1 <-> val2;
if (res !== 1'b1) begin
$display("FAILED: 1'b0 <-> 1'b0 returned %b not 1'b1", res);
pass = 1'b0;
end
val2 = 1'b1;
res = val1 <-> val2;
if (res !== 1'b0) begin
$display("FAILED: 1'b0 <-> 1'b1 returned %b not 1'b0", res);
pass = 1'b0;
end
val2 = 1'bx;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'b0 <-> 1'bx returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'bz;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'b0 <-> 1'bz returned %b not 1'bx", res);
pass = 1'b0;
end
val1 = 1'b1;
val2 = 1'b0;
res = val1 <-> val2;
if (res !== 1'b0) begin
$display("FAILED: 1'b1 <-> 1'b0 returned %b not 1'b0", res);
pass = 1'b0;
end
val2 = 1'b1;
res = val1 <-> val2;
if (res !== 1'b1) begin
$display("FAILED: 1'b1 <-> 1'b1 returned %b not 1'b1", res);
pass = 1'b0;
end
val2 = 1'bx;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'b1 <-> 1'bx returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'bz;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'b1 <-> 1'bz returned %b not 1'bx", res);
pass = 1'b0;
end
val1 = 1'bx;
val2 = 1'b0;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bx <-> 1'b0 returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'b1;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bx <-> 1'b1 returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'bx;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bx <-> 1'bx returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'bz;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bx <-> 1'bz returned %b not 1'bx", res);
pass = 1'b0;
end
val1 = 1'bz;
val2 = 1'b0;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bz <-> 1'b0 returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'b1;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bz <-> 1'b1 returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'bx;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bz <-> 1'bx returned %b not 1'bx", res);
pass = 1'b0;
end
val2 = 1'bz;
res = val1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 1'bz <-> 1'bz returned %b not 1'bx", res);
pass = 1'b0;
end
rval1 = 0.0;
val2 = 1'b0;
res = rval1 <-> val2;
if (res !== 1'b1) begin
$display("FAILED: 0.0 <-> 1'b0 returned %b not 1'b1", res);
pass = 1'b0;
end
val1 = 1'b0;
rval2 = 2.0;
res = val1 <-> rval2;
if (res !== 1'b0) begin
$display("FAILED: 1'b0 <-> 2.0 returned %b not 1'b0", res);
pass = 1'b0;
end
rval1 = 2.0;
val2 = 1'bx;
res = rval1 <-> val2;
if (res !== 1'bx) begin
$display("FAILED: 2.0 <-> 1'bx returned %b not 1'bx", res);
pass = 1'b0;
end
rval1 = -5.0;
rval2 = 2.0;
res = rval1 <-> rval2;
if (res !== 1'b1) begin
$display("FAILED: -5.0 <-> -2.0 returned %b not 1'b1", res);
pass = 1'b0;
end
wval1 = 4'b0110;
wval2 = 4'b1001;
wres = wval1 <-> wval2;
if (wres !== 2'b01) begin
$display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b01", wres);
pass = 1'b0;
end
wres = $signed(wval1 <-> wval2);
if (wres !== 2'b11) begin
$display("FAILED: 4'b0110 <-> 4'b1001 returned %b not 2'b11", wres);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long t, n, m; int a[200003]; pair<int, int> p[200003]; int main() { cin >> t; while (t--) { cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; } long long re = 0; for (int i = 1; i <= n;) { int val = a[i], j; for (j = i; j <= n && 1ll * a[j] * a[i] > 0; ++j) val = max(val, a[j]); re += val; i = j; } cout << re << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; char ans[444444], a[444444]; long long h1[444444], h2[444444], p[444444]; int d1, d2, n; bool check(int i, int e) { if (i > n) return e; int s = e ? a : a[i]; for (char x = s; x <= z ; ++x) { h1[i] = h1[i - 1] * 241 + x; h2[i] = h2[i - 1] + p[i] * x; h1[i] %= 1000000007; h2[i] %= 1000000007; if (i >= d1) { long long t = (h1[i] - h1[i - d1] * p[d1]) % 1000000007 * p[i + 1 - d1] % 1000000007; long long q = h2[i] - h2[i - d1]; if ((t - q) % 1000000007 == 0) continue; } if (i >= d1) { long long t = (h1[i] - h1[i - d2] * p[d2]) % 1000000007 * p[i + 1 - d2] % 1000000007; long long q = h2[i] - h2[i - d2]; if ((t - q) % 1000000007 == 0) continue; } ans[i] = x; if (check(i + 1, e || (x > a[i]))) return 1; } return 0; } int main() { scanf( %d , &d1); d2 = d1 + 1; scanf( %s , a + 1); n = strlen(a + 1); p[0] = 1; ans[n + 1] = 0 ; for (int i = 1; i <= n; ++i) p[i] = p[i - 1] * 241 % 1000000007; if (check(1, 0)) printf( %s n , ans + 1); else puts( Impossible ); }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) { long long n, m; cin >> n >> m; bool gt = true; long long mn = m, mx = m; long long curt = 0; for (long long i = 0; i < n; i++) { long long t, l, h; cin >> t >> l >> h; long long ti = t - curt; mn -= ti; mx += ti; if (l > mx || h < mn) gt = false; mn = max(mn, l); mx = min(mx, h); curt = t; } if (gt) cout << YES n ; else cout << NO n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_TB_V
`define SKY130_FD_SC_HS__FILL_TB_V
/**
* fill: Fill cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fill.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hs__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_PP_SYMBOL_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlpsleep (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B ,
//# {{power|Power}}
input SLEEP,
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const int S = 40; const unsigned long long mod = 998244353; struct poly { int a[S + 10]; inline int& operator[](const int& x) { return a[x]; } poly() { for (int i = 0; i < S; i++) a[i] = 0; } friend poly operator*(poly a, poly b) { poly c; for (int i = 0; i < S; i++) for (int j = 0; j < S && i + j < S; j++) c[i + j] += a[i] * b[j]; return c; } friend poly operator+(poly a, poly b) { poly c; for (int i = 0; i < S; i++) c[i] = a[i] + b[i]; return c; } friend poly operator-(poly a, poly b) { poly c; for (int i = 0; i < S; i++) c[i] = a[i] - b[i]; return c; } poly operator<<(const int& x) { poly c; for (int i = S - 1; i >= x; i--) c[i] = a[i - x]; return c; } } a, b, c, q, fz, fm, fz1, fm1; int n; unsigned long long f0[N]; unsigned long long c0[N]; unsigned long long f1[N]; unsigned long long c1[N]; unsigned long long f2[N]; unsigned long long c2[N]; unsigned long long g[N]; unsigned long long sqr[N]; inline void calc(poly& fz, poly& fm, unsigned long long* f, unsigned long long* c) { for (int i = 0; i < S; i++) f[i] = (mod + fz[i]) % mod; for (int i = 0; i < S; i++) c[i] = (mod - fm[i]) % mod; (c[0] += 1) %= mod; for (int i = 0; i <= n; i++) for (int j = 1; j < S && j <= i; j++) (f[i] += f[i - j] * c[j]) %= mod; } int main() { a[8] = 16; a[6] = 12; a[4] = 20; a[2] = 4; b[8] = 9; b[6] = 2; b[4] = 23; b[2] = 6; b[0] = 1; c[8] = 4; c[6] = -4; c[4] = 24; c[2] = 4; c[0] = 4; q[12] = -1; q[10] = -3; q[6] = +5; q[2] = -3; q[0] = +1; scanf( %d , &n); fz = ((b * b) << 3) - a * ((c << 3) - q); fm = ((c << 3) - q) * ((a << 1) - q) - ((b * b) << 4); calc(fz, fm, f0, c0); fz = b * q; fm = ((c << 3) - q) * ((a << 1) - q) - ((b * b) << 4); calc(fz, fm, f1, c1); fz1 = c * fm + ((b * fz) << 1); fm1 = fm * (q - (c << 3)); calc(fz1, fm1, f2, c2); g[0] = 1; g[2] = 1; for (int i = 4; i <= n; i++) g[i] = (g[i - 2] + g[i - 4]) % mod; for (int i = 1; i <= n; i++) sqr[i] = (unsigned long long)i * i % mod; unsigned long long ans = (g[n - 1] + g[n - 3]) * sqr[n - 1] % mod * n % mod; for (int i = 2; i <= n - 2; i++) { unsigned long long ret = 0; (ret += g[i - 1] * f0[n - i - 1]) %= mod; (ret += g[i - 2] * f1[n - i - 2] * 2) %= mod; if (3 <= i && i <= n - 3) (ret += g[i - 3] * f2[n - i - 3]) %= mod; (ans += ret * sqr[i - 1] % mod * i) %= mod; } printf( %I64d , ans); }
|
#include <bits/stdc++.h> using namespace std; int main() { int c, a, b; cin >> a >> b >> c; cout << a * b * c - (a - 1) * (b - 1) * (c - 1); return 0; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "utils/cdc_pulse_sync.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "seq_gen/seq_gen.v"
`include "seq_gen/seq_gen_core.v"
`include "utils/RAMB16_S1_S2_sim.v"
`include "seq_gen/seq_gen_blk_mem_16x8196.v"
`include "spi/spi.v"
`include "spi/spi_core.v"
`include "spi/blk_mem_gen_8_to_1_2k.v"
`include "utils/RAMB16_S1_S9_sim.v"
`include "utils/CG_MOD_pos.v"
`include "gpac_adc_rx/gpac_adc_rx_core.v"
`include "gpac_adc_rx/gpac_adc_rx.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "utils/generic_fifo.v"
//`include "utils/cdc_pulse_sync_cnt.v"
`include "utils/cdc_syncfifo.v"
`include "utils/pulse_gen_rising.v"
`include "utils/clock_divider.v"
`include "utils/cdc_reset_sync.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam PULSE_BASEADDR = 32'h0000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam SEQ_GEN_BASEADDR = 32'h1000; //0x1000
localparam SEQ_GEN_HIGHADDR = 32'h3000-1; //0x300f
localparam ADC_RX_BASEADDR = 32'h3000;
localparam ADC_RX_HIGHADDR = 32'h5000 - 1;
localparam SPI_ADC_BASEADDR = 32'h5000;
localparam SPI_ADC_HIGHADDR = 32'h6000-1;
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
wire DIV_CLK;
clock_divider #(
.DIVISOR(8)
) i_clock_divisor_spi (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(),
.CLOCK(DIV_CLK)
);
wire EX_START_PULSE;
pulse_gen
#(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(DIV_CLK),
.EXT_START(1'b0),
.PULSE(EX_START_PULSE)
);
wire [15:0] SEQ_OUT;
seq_gen
#(
.BASEADDR(SEQ_GEN_BASEADDR),
.HIGHADDR(SEQ_GEN_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(16*1024),
.OUT_BITS(16)
) i_seq_gen
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(EX_START_PULSE),
.SEQ_CLK(DIV_CLK),
.SEQ_OUT(SEQ_OUT)
);
wire SDI;
spi
#(
.BASEADDR(SPI_ADC_BASEADDR),
.HIGHADDR(SPI_ADC_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(2)
) i_spi
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SPI_CLK(DIV_CLK),
.SCLK(),
.SDI(SDI),
.SDO(SDI),
.SEN(),
.SLD()
);
wire FIFO_READ_ADC;
wire FIFO_EMPTY_ADC;
wire [31:0] FIFO_DATA_ADC;
gpac_adc_rx
#(
.BASEADDR(ADC_RX_BASEADDR),
.HIGHADDR(ADC_RX_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.ADC_ID(0),
.HEADER_ID(0)
) i_gpac_adc_rx
(
.ADC_ENC(DIV_CLK),
.ADC_IN(SEQ_OUT[13:0]),
.ADC_SYNC(EX_START_PULSE),
.ADC_TRIGGER(1'b0),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ(FIFO_READ_ADC),
.FIFO_EMPTY(FIFO_EMPTY_ADC),
.FIFO_DATA(FIFO_DATA_ADC),
.LOST_ERROR()
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
assign FIFO_DATA = FIFO_DATA_ADC;
assign FIFO_EMPTY = FIFO_EMPTY_ADC;
assign FIFO_READ_ADC = FIFO_READ;
bram_fifo
#(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
initial begin
$dumpfile("adcrx.vcd");
$dumpvars(0);
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; int t; void solve(); struct Node { long long q, w, e, r, t; }; int n; vector<Node> a; vector<bool> ans; int res = 0; int main() { ios_base::sync_with_stdio(false); cin.tie(0); t = 1; for (int i = 0; i < t; ++i) { solve(); } } void solve() { cin >> n; a.resize(n); ans.resize(n); for (int i = 0; i < int(n); ++i) { cin >> a[i].q >> a[i].w >> a[i].e >> a[i].r >> a[i].t; } if (n > 66) { cout << 0; return; } for (int i = 0; i < int(n); ++i) { for (int j = (0); j <= int(n - 1); ++j) { for (int k = (j + 1); k <= int(n - 1); ++k) { if (j == i || k == i) { continue; } if ((a[j].q - a[i].q) * (a[k].q - a[i].q) + (a[j].w - a[i].w) * (a[k].w - a[i].w) + (a[j].e - a[i].e) * (a[k].e - a[i].e) + (a[j].r - a[i].r) * (a[k].r - a[i].r) + (a[j].t - a[i].t) * (a[k].t - a[i].t) > 0) { ans[i] = true; break; } } if (ans[i]) break; } if (!ans[i]) res++; } cout << res << endl; for (int i = 0; i < int(n); ++i) { if (!ans[i]) { cout << i + 1 << endl; } } }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ea_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:31:57 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ea_e.v,v 1.5 2006/06/26 08:39:42 wig Exp $
// $Date: 2006/06/26 08:39:42 $
// $Log: inst_ea_e.v,v $
// Revision 1.5 2006/06/26 08:39:42 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ea_e
//
// No `defines in this module
module inst_ea_e
//
// Generated Module inst_ea
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_ea_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> namespace algo { using std::swap; const long double PI = 3.141592653589793238462643383279502884L; const long double E = 2.718281828459045235360287471352662498L; const long double EPS = 1e-12L; template <typename T1, typename T2> T1 bin_pow(T1 a, T2 n) { T1 r{1}; while (n > 0) { if (n % 2 == 1) r *= a; a *= a; n /= 2; } return r; } template <typename T1, typename T2> T1 bin_pow(T1 a, T2 n, const T1& m) { if (m == 1) return 0; T1 r{1}; while (n > 0) { if (n % 2 == 1) { r *= a; r %= m; } a *= a; a %= m; n /= 2; } return r; } template <typename T> T gcd(const T& a, const T& b) { if (b == 0) return a < 0 ? -a : a; return gcd(b, a % b); } template <typename T> T gcd(const T& a, const T& b, T& x, T& y) { if (b == 0) { x = a < 0 ? -1 : 1; y = 0; return x * a; } T d{gcd(b, a % b, y, x)}; y -= (a / b) * x; return d; } template <typename T> T lcm(const T& a, const T& b) { T r{a / gcd(a, b) * b}; return r < 0 ? -r : r; } template <typename T> T mod_add(const T& a, const T& b, const T& m) { if (a < m - b) return a + b; return a - (m - b); } template <typename T> T mod_sub(const T& a, const T& b, const T& m) { if (a < b) return a + (m - b); return a - b; } template <typename T> T mod_mul(T a, T b, const T& m) { if (b > a) swap(a, b); T r{0}; while (b > 0) { if (b % 2 == 1) r = mod_add(r, a, m); a = mod_add(a, a, m); b /= 2; } return r; } template <typename T1, typename T2> T1 mod_pow(T1 a, T2 n, const T1& m) { if (m == 1) return 0; T1 r{1}; while (n > 0) { if (n % 2 == 1) r = mod_mul(r, a, m); a = mod_mul(a, a, m); n /= 2; } return r; } template <typename T> T mod_inv(const T& a, const T& m) { T x, y; T d{gcd(a, m, x, y)}; if (d != 1) return 0; if (x < 0) x += m; return x; } template <typename T> T phi(T n) { T t = std::sqrt(n) + EPS; T r = n; for (T i = 2; i <= t; ++i) { if (n % i == 0) { r -= r / i; do { n /= i; } while (n % i == 0); t = std::sqrt(n) + EPS; } } if (n > 1) r -= r / n; return r; } class LinearPhi { public: LinearPhi(uint32_t n = 1 << 20) : size_{n} { assert(size_ > 0 && Size should be nonzero ); assert(size_ <= INT32_MAX && Size should fit into an 32-bit signed int ); uint32_t sz = (size_ + 1) / 2; phi_ = new int32_t[sz]; mark_.assign(sz, false); phi_[0] = 1; if (size_ > 1) primes_.push_back(2); for (uint32_t i = 1; i < sz; ++i) { uint32_t val = i << 1 | 1; if (!mark_[i]) { phi_[i] = val - 1; primes_.push_back(val); } if (val < sz) { for (uint32_t j = 1; j < primes_.size(); ++j) { uint32_t t = val * primes_[j]; if (t > size_) break; mark_[t >> 1] = true; if (val % primes_[j] == 0) { phi_[t >> 1] = phi_[i] * primes_[j]; break; } phi_[t >> 1] = phi_[i] * (primes_[j] - 1); } } } } LinearPhi(const LinearPhi&) = delete; LinearPhi& operator=(const LinearPhi&) = delete; ~LinearPhi() { delete[] phi_; phi_ = nullptr; } const uint32_t& size() const { return size_; } int32_t phi(int32_t i) const { int32_t r = 1; int k = __builtin_ctz(i); if (k > 0) { i >>= k; r <<= k - 1; } return r * phi_[i >> 1]; } int32_t operator[](int32_t i) const { return phi(i); } const std::vector<int32_t>& primes() const { return primes_; } private: int32_t* phi_ = nullptr; std::vector<bool> mark_; uint32_t size_; std::vector<int32_t> primes_; }; class Sieve { public: Sieve(uint32_t n = 1 << 20) : size_{n} { assert(size_ > 0 && Size should be nonzero ); assert(size_ <= INT32_MAX && Size should fit into an 32-bit signed int ); uint32_t sz = (size_ + 1) / 2; prime_.assign(sz, true); prime_[0] = false; for (uint32_t i = 1; i < sz; ++i) { uint32_t val = i << 1 | 1; if (prime_[i] && val * 1ULL * val <= size_) for (uint32_t j = val * val; j <= size_; j += 2 * val) prime_[j >> 1] = false; } } Sieve(const Sieve&) = delete; Sieve& operator=(const Sieve&) = delete; const uint32_t& size() const { return size_; } bool isPrime(const int32_t& i) const { if (i % 2 == 0) return i == 2; return prime_[i >> 1]; } bool operator[](const int32_t& i) const { return isPrime(i); } private: uint32_t size_; std::vector<bool> prime_; }; class LinearSieve { public: LinearSieve(uint32_t n = 1 << 20) : size_{n} { assert(size_ > 0 && Size should be nonzero ); assert(size_ <= INT32_MAX && Size should fit into an 32-bit signed int ); uint32_t sz = (size_ + 1) / 2; lpf_ = new uint16_t[sz]; std::fill(lpf_, lpf_ + sz, 0); lpf_[0] = 1; if (size_ > 1) primes_.push_back(2); for (uint32_t i = 1; i < sz; ++i) { uint32_t val = i << 1 | 1; if (!lpf_[i]) primes_.push_back(val); if (val < sz) { for (uint32_t j = 1; j < primes_.size(); ++j) { uint32_t t = val * primes_[j]; if (t > size_) break; lpf_[t >> 1] = static_cast<uint16_t>(primes_[j]); if (lpf_[t >> 1] == (lpf_[i] ? lpf_[i] : val)) break; } } } } LinearSieve(const LinearSieve&) = delete; LinearSieve& operator=(const LinearSieve&) = delete; ~LinearSieve() { delete[] lpf_; lpf_ = nullptr; } const uint32_t& size() const { return size_; } bool isPrime(const int32_t& i) const { if (i % 2 == 0) return i == 2; return !lpf_[i >> 1]; } bool operator[](const int32_t& i) const { return isPrime(i); } int32_t lpf(const int32_t& i) const { if (i % 2 == 0) return 2; if (!lpf_[i >> 1]) return i; return lpf_[i >> 1]; } int32_t phi(int32_t i) const { int32_t r = 1; int k = __builtin_ctz(i); if (k > 0) { i >>= k; r <<= k - 1; } int32_t n, t = lpf_[i >> 1] ? lpf_[i >> 1] : i; while (t != 1) { r *= (t - 1); i /= t; n = lpf_[i >> 1] ? lpf_[i >> 1] : i; while (n == t) { r *= n; i /= t; n = lpf_[i >> 1] ? lpf_[i >> 1] : i; } t = n; } return r; } const std::vector<int32_t>& primes() const { return primes_; } private: uint16_t* lpf_ = nullptr; uint32_t size_; std::vector<int32_t> primes_; }; } // namespace algo using namespace std; using namespace algo; namespace task { int x1, y1, x2, y2, x3, y3; int main() { cin >> x1 >> y1 >> x2 >> y2 >> x3 >> y3; cout << 3 << n ; cout << x3 - x1 + x2 << << y3 - y1 + y2 << n ; cout << x1 - x2 + x3 << << y1 - y2 + y3 << n ; cout << x2 - x3 + x1 << << y2 - y3 + y1 << n ; return 0; } } // namespace task int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.precision(11); cout.setf(ios::fixed); return task::main(); }
|
#include <bits/stdc++.h> using namespace std; int main() { long int n, m; cin >> n; cin >> m; char str[2002][2002]; long int A[10002][2]; long int cnt = 0; long int i, j; for (i = 0; i < n; i++) { cin >> str[i]; for (j = 0; j < m; j++) { if (str[i][j] == w ) { A[cnt][0] = i; A[cnt][1] = j; cnt++; } } } long int i_min = n, i_max = 0, j_min = m, j_max = 0; for (i = 0; i < cnt; i++) { if (A[i][0] < i_min) i_min = A[i][0]; if (A[i][0] > i_max) i_max = A[i][0]; if (A[i][1] < j_min) j_min = A[i][1]; if (A[i][1] > j_max) j_max = A[i][1]; } long int dim; long int Idy = -1; long int Idx = -1; if (i_max - i_min > j_max - j_min) { dim = i_max - i_min + 1; for (i = 0; i < cnt; i++) { if (A[i][0] != i_max && A[i][0] != i_min) { Idy = A[i][1]; break; } } if (Idy == -1) { if (m - j_min > dim) j_max = j_min + dim - 1; else { j_max = m - 1; j_min = j_max - dim + 1; } } else { if (j_max == j_min) { if (j_min + dim - 1 < m) j_max = j_min + dim - 1; else j_min = j_max - dim + 1; } else { if (Idy == j_min) j_max = j_min + dim - 1; else j_min = j_max - dim + 1; } } } else if (i_max - i_min < j_max - j_min) { dim = j_max - j_min + 1; for (i = 0; i < cnt; i++) { if (A[i][1] != j_max && A[i][1] != j_min) { Idx = A[i][0]; break; } } if (Idx == -1) { if (n - i_min > dim) i_max = i_min + dim - 1; else { i_max = n - 1; i_min = i_max - dim + 1; } } else { if (i_max == i_min) { if (i_min + dim - 1 < n) i_max = i_min + dim - 1; else i_min = i_max - dim + 1; } else { if (Idx == i_min) i_max = i_min + dim - 1; else i_min = i_max - dim + 1; } } } if (!((i_max < n) && (i_min >= 0) && (j_max < m) && (j_min >= 0))) { cout << -1 << n ; return 0; } long int cnt2 = 0; for (j = j_min; j <= j_max; j++) { if (str[i_min][j] == w ) cnt2++; else str[i_min][j] = + ; if (i_max == i_min) continue; if (str[i_max][j] == w ) cnt2++; else str[i_max][j] = + ; } for (i = i_min + 1; i < i_max; i++) { if (str[i][j_min] == w ) cnt2++; else str[i][j_min] = + ; if (j_max == j_min) continue; if (str[i][j_max] == w ) cnt2++; else str[i][j_max] = + ; } if (cnt == -1) { for (i = 0; i < 2000; i++) cout << w ; cout << endl; for (i = 1; i < 2000 - 1; i++) { cout << w ; for (j = 1; j < 1999; j++) cout << . ; cout << w ; cout << endl; } for (i = 0; i < 2000; i++) cout << w ; cout << endl; return 0; } if (cnt != cnt2) { cout << -1 n ; return 0; } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) cout << str[i][j]; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> (t); while (t--) { long long int n, k; cin >> n >> k; long long int a[n + 2]; memset(a, -1, sizeof a); bool ok = false; for (long long int i = 0; i < n; ++i) { cin >> a[i]; if (a[i] == k) ok = true; } if (n == 1 && ok) { cout << yes << n ; continue; } if (!ok) { cout << no << n ; continue; } ok = false; for (long long int i = 0; i < n; i++) { if ((a[i] >= k && a[i + 1] >= k) || (a[i] >= k && a[i + 2] >= k)) ok = true; } if (ok) cout << yes << n ; else cout << no << n ; } }
|
/***********************************************************************************************************************
* Copyright (C) 2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
INPUTS:
FIXME
OUTPUTS:
FIXME
TEST PROCEDURE:
FIXME
*/
module DCMP(muxsel, greater, equal, count_overflow);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P20 P19" *)
input wire[1:0] muxsel;
(* LOC = "P18" *)
output wire greater;
(* LOC = "P17" *)
output wire equal;
(* LOC = "P16" *)
output wire count_overflow;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// System reset stuff
//Power-on reset
wire por_done;
GP_POR #(
.POR_TIME(500)
) por (
.RST_DONE(por_done)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// RC oscillator clock
wire clk_2mhz;
GP_RCOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OSC_FREQ("2M"),
.HARDIP_DIV(1),
.FABRIC_DIV(1)
) rcosc (
.PWRDN(1'b0),
.CLKOUT_HARDIP(clk_2mhz),
.CLKOUT_FABRIC()
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Buffer the RC oscillator clock
//This drives the MuxedClockBuffer for the ADC/DCMP
wire clk_2mhz_buf;
GP_CLKBUF clkbuf (
.IN(clk_2mhz),
.OUT(clk_2mhz_buf));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// A counter driving the input of the DCMP/PWM
localparam COUNT_MAX = 255;
//Explicitly instantiated counter b/c we don't yet have inference support when using POUT
wire[7:0] count_pout;
GP_COUNT8 #(
.CLKIN_DIVIDE(1),
.COUNT_TO(COUNT_MAX),
.RESET_MODE("RISING")
) cnt (
.CLK(clk_2mhz),
.RST(1'b0),
.OUT(count_overflow),
.POUT(count_pout)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reference inputs to the DCMP
wire[7:0] ref0;
wire[7:0] ref1;
wire[7:0] ref2;
wire[7:0] ref3;
GP_DCMPREF #(.REF_VAL(8'h80)) rs0(.OUT(ref0));
GP_DCMPREF #(.REF_VAL(8'h40)) rs1(.OUT(ref1));
GP_DCMPREF #(.REF_VAL(8'hc0)) rs2(.OUT(ref2));
GP_DCMPREF #(.REF_VAL(8'hf0)) rs3(.OUT(ref3));
wire[7:0] muxouta;
wire[7:0] muxoutb;
GP_DCMPMUX mux(
.SEL(muxsel),
.OUTA(muxouta),
.OUTB(muxoutb),
.IN0(ref0),
.IN1(ref1),
.IN2(ref2),
.IN3(ref3));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The DCMP itself
GP_DCMP #(
.GREATER_OR_EQUAL(1'b0),
.CLK_EDGE("RISING"),
.PWRDN_SYNC(1'b1)
) dcmp(
.INP(muxouta),
.INN(count_pout),
.CLK(clk_2mhz_buf),
.PWRDN(1'b0),
.GREATER(greater),
.EQUAL(equal)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; struct Point { int x, y; Point(int x_ = 0, int y_ = 0) : x(x_), y(y_) {} Point(std::istream &in) { in >> x >> y; x *= 2; y *= 2; } }; bool operator<(const Point &a, const Point &b) { return (a.x < b.x) || (a.x == b.x && a.y < b.y); } bool cmp_sum(const Point &a, const Point &b) { return (a.x + a.y < b.x + b.y); } bool cmp_diff(const Point &a, const Point &b) { return (a.x - a.y < b.x - b.y); } int n, k; vector<Point> gnome, metro; vector<int> sorted_x, sorted_y; vector<int> tree; int curk; void upd_val(int x, int val, const vector<int> &coords) { x = lower_bound(coords.begin(), coords.end(), x) - coords.begin(); x += curk; tree[x] = min(tree[x], val); x /= 2; while (x != 1) { tree[x] = min(tree[x * 2], tree[x * 2 + 1]); x /= 2; } } int get_min_val(int l, int r, const vector<int> &coords) { l = lower_bound(coords.begin(), coords.end(), l) - coords.begin(); r = lower_bound(coords.begin(), coords.end(), r) - coords.begin(); l += curk; r += curk; int res = INF; while (l < r) { res = min(res, min(tree[l], tree[r])); l = (l + 1) / 2; r = (r - 1) / 2; } if (l == r) { res = min(res, tree[l]); } return res; } void shrink(vector<int> &coord) { sort(coord.begin(), coord.end()); coord.resize(unique(coord.begin(), coord.end()) - coord.begin()); } template <typename T> std::vector<int> argsort(const std::vector<T> &vals, bool reverse = false) { vector<int> result(vals.size()); for (int i = 0; i < int(vals.size()); ++i) { result[i] = i; } sort(result.begin(), result.end(), [&](int a, int b) -> bool { return (vals[a] < vals[b]); }); if (reverse) { std::reverse(result.begin(), result.end()); } return result; } void get_min_dist(const std::vector<Point> &gnome, std::vector<Point> metro, std::vector<int> &result) { sorted_x.clear(); sorted_y.clear(); for (auto &x : gnome) { sorted_x.push_back(x.x); sorted_y.push_back(x.y); } for (auto &x : metro) { sorted_x.push_back(x.x); sorted_y.push_back(x.y); } shrink(sorted_x); shrink(sorted_y); int nn = gnome.size(); result.assign(nn, INF); auto indices = argsort(gnome); sort(metro.begin(), metro.end()); curk = 2; while (int(sorted_y.size()) > curk) curk *= 2; { tree.assign(2 * curk, INF); int l = 0, r = 0; while (l < nn) { int ind = indices[l]; while (r < k && metro[r].x <= gnome[ind].x) { upd_val(metro[r].y, -metro[r].x - metro[r].y, sorted_y); ++r; } result[ind] = min(result[ind], get_min_val(sorted_y.front(), gnome[ind].y, sorted_y) + gnome[ind].x + gnome[ind].y); ++l; } } { tree.assign(2 * curk, INF); int l = 0, r = 0; while (l < nn) { int ind = indices[l]; while (r < k && metro[r].x <= gnome[ind].x) { upd_val(metro[r].y, -metro[r].x + metro[r].y, sorted_y); ++r; } result[ind] = min(result[ind], get_min_val(gnome[ind].y, sorted_y.back(), sorted_y) + gnome[ind].x - gnome[ind].y); ++l; } } reverse(metro.begin(), metro.end()); reverse(indices.begin(), indices.end()); { tree.assign(2 * curk, INF); int l = 0, r = 0; while (l < nn) { int ind = indices[l]; while (r < k && metro[r].x >= gnome[ind].x) { upd_val(metro[r].y, metro[r].x - metro[r].y, sorted_y); ++r; } result[ind] = min(result[ind], get_min_val(sorted_y.front(), gnome[ind].y, sorted_y) - gnome[ind].x + gnome[ind].y); ++l; } } { tree.assign(2 * curk, INF); int l = 0, r = 0; while (l < nn) { int ind = indices[l]; while (r < k && metro[r].x >= gnome[ind].x) { upd_val(metro[r].y, metro[r].x + metro[r].y, sorted_y); ++r; } result[ind] = min(result[ind], get_min_val(gnome[ind].y, sorted_y.back(), sorted_y) - gnome[ind].x - gnome[ind].y); ++l; } } } int find_dist(pair<pair<int, int>, pair<int, int> > rect, const Point &pnt) { int sum = pnt.x + pnt.y; int diff = pnt.x - pnt.y; int sum_dist = max(0, -min(rect.first.second, sum) + max(rect.first.first, sum)); int diff_dist = max(0, -min(rect.second.second, diff) + max(rect.second.first, diff)); return max(sum_dist, diff_dist); } void get_all_min_dist(vector<pair<pair<int, int>, pair<int, int> > > rect, vector<Point> metro, vector<int> &dist) { dist.assign(n, INF); vector<Point> ok_points; for (int i = 0; i < n; ++i) { const auto &cr = rect[i]; int a, b, c, d; tie(a, b) = cr.first; tie(c, d) = cr.second; ok_points.emplace_back((a + c) / 2, (a - c) / 2); ok_points.emplace_back((a + d) / 2, (a - d) / 2); ok_points.emplace_back((b + c) / 2, (b - c) / 2); ok_points.emplace_back((b + d) / 2, (b - d) / 2); } vector<int> tmp; get_min_dist(ok_points, metro, tmp); for (int i = 0; i < n * 4; ++i) { dist[i / 4] = min(dist[i / 4], tmp[i]); } vector<int> sorted_sum; vector<int> sorted_diff; for (auto &pnt : rect) { sorted_sum.push_back(pnt.first.first); sorted_sum.push_back(pnt.first.second); sorted_diff.push_back(pnt.second.first); sorted_diff.push_back(pnt.second.second); } for (auto &pnt : metro) { sorted_sum.push_back(pnt.x + pnt.y); sorted_diff.push_back(pnt.x - pnt.y); } shrink(sorted_sum); shrink(sorted_diff); sort(metro.begin(), metro.end(), cmp_sum); curk = 2; while (curk < int(sorted_diff.size())) curk *= 2; vector<pair<pair<int, int>, pair<int, int> > > segment; for (int i = 0; i < n; ++i) { segment.emplace_back(make_pair(rect[i].first.first, i), rect[i].second); if (rect[i].first.first != rect[i].first.second) { segment.emplace_back(make_pair(rect[i].first.second, i), rect[i].second); } } sort(segment.begin(), segment.end()); { tree.assign(curk * 2, INF); int nn = segment.size(); int l = 0, r = 0; while (l < nn) { while (r < k && metro[r].x + metro[r].y <= segment[l].first.first) { upd_val(metro[r].x - metro[r].y, -metro[r].y - metro[r].x, sorted_diff); ++r; } int ind = segment[l].first.second; dist[ind] = min(dist[ind], get_min_val(segment[l].second.first, segment[l].second.second, sorted_diff) + segment[l].first.first); ++l; } } reverse(metro.begin(), metro.end()); reverse(segment.begin(), segment.end()); { tree.assign(curk * 2, INF); int nn = segment.size(); int l = 0, r = 0; while (l < nn) { while (r < k && metro[r].x + metro[r].y >= segment[l].first.first) { upd_val(metro[r].x - metro[r].y, metro[r].x + metro[r].y, sorted_diff); ++r; } int ind = segment[l].first.second; dist[ind] = min(dist[ind], get_min_val(segment[l].second.first, segment[l].second.second, sorted_diff) - segment[l].first.first); ++l; } } sort(metro.begin(), metro.end(), cmp_diff); segment.clear(); for (int i = 0; i < n; ++i) { segment.emplace_back(make_pair(rect[i].second.first, i), rect[i].first); if (rect[i].second.first != rect[i].second.second) { segment.emplace_back(make_pair(rect[i].second.second, i), rect[i].first); } } sort(segment.begin(), segment.end()); curk = 2; while (curk < int(sorted_sum.size())) curk *= 2; { tree.assign(curk * 2, INF); int nn = segment.size(); int l = 0, r = 0; while (l < nn) { while (r < k && metro[r].x - metro[r].y <= segment[l].first.first) { upd_val(metro[r].x + metro[r].y, metro[r].y - metro[r].x, sorted_sum); ++r; } int ind = segment[l].first.second; dist[ind] = min(dist[ind], get_min_val(segment[l].second.first, segment[l].second.second, sorted_sum) + segment[l].first.first); ++l; } } reverse(metro.begin(), metro.end()); reverse(segment.begin(), segment.end()); { tree.assign(curk * 2, INF); int nn = segment.size(); int l = 0, r = 0; while (l < nn) { while (r < k && metro[r].x - metro[r].y >= segment[l].first.first) { upd_val(metro[r].x + metro[r].y, metro[r].x - metro[r].y, sorted_sum); ++r; } int ind = segment[l].first.second; dist[ind] = min(dist[ind], get_min_val(segment[l].second.first, segment[l].second.second, sorted_sum) - segment[l].first.first); ++l; } } } int main() { ios_base::sync_with_stdio(false); cin >> n >> k; for (int i = 0; i < n; ++i) { gnome.emplace_back(std::cin); } for (int i = 0; i < k; ++i) { metro.emplace_back(std::cin); } int min_x = INF, max_x = -INF; int min_y = INF, max_y = -INF; for (const auto &pnt : gnome) { min_x = min(min_x, pnt.x + pnt.y); max_x = max(max_x, pnt.x + pnt.y); min_y = min(min_y, pnt.x - pnt.y); max_y = max(max_y, pnt.x - pnt.y); } int result = (max(max_x - min_x, max_y - min_y) + 1) / 2; if (n > 1 && k) { vector<int> dist; get_min_dist(gnome, metro, dist); auto indices = argsort(dist, true); vector<pair<pair<int, int>, pair<int, int> > > all_rect; vector<int> add_dist; min_x = INF, max_x = -INF; min_y = INF, max_y = -INF; for (int i = 0; i < n; ++i) { const auto &pnt = gnome[indices[i]]; min_x = min(min_x, pnt.x + pnt.y); max_x = max(max_x, pnt.x + pnt.y); min_y = min(min_y, pnt.x - pnt.y); max_y = max(max_y, pnt.x - pnt.y); int dist = (max(max_x - min_x, max_y - min_y) + 1) / 2; add_dist.push_back(dist); all_rect.emplace_back(make_pair(max_x - dist, min_x + dist), make_pair(max_y - dist, min_y + dist)); } result = min(result, dist[indices[0]]); vector<int> new_dist; get_all_min_dist(all_rect, metro, new_dist); for (int i = 0; i < n - 1; ++i) { int t1 = add_dist[i]; int t2 = new_dist[i]; int t3 = dist[indices[i + 1]]; int x = (max(0, min(2 * t2, t3 + t2 - t1)) + 1) / 2; result = min(result, max(t1 + x, t3 + t2 - x)); } } result = (result + 1) / 2; cout << result << n ; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__OR4B_FUNCTIONAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_FUNCTIONAL_PP_V
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s, soln; cin >> s; soln = s; for (int i = 0, idx = (n - 1) / 2; i < n; i++) { soln[idx] = s[i]; if ((n + i) % 2 == 0) idx += (i + 1); else if ((n + i) % 2 == 1) idx -= (i + 1); } cout << soln << endl; return 0; }
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// Texas A&M University //
// cpsc350 Computer Architecture //
// $Id: IdealMemory.v,v 1.3 2002/11/19 00:58:22 miket Exp miket $ //
// InstrMem is an asynchronous read memory model //
// MemSize Wordise parameterize the memory module at instantiation time //
module InstrMem (Mem_Addr, Dout);
parameter T_rd = 10;
parameter MemSize = 1024, WordSize = 32;
input [WordSize-1:0] Mem_Addr;
output [WordSize-1:0] Dout;
reg [WordSize-1:0] Dout;
reg [WordSize-1:0] Mem[0:MemSize-1]; // register array (SRAM)
//`include "imeminit.v"
// Include your test program file here instead of "imeminit.v"
`include "imeminit_simple_test.v"
always
#T_rd assign Dout = Mem[ Mem_Addr >> 2 ];
endmodule // Imem
// DataMem is an asynchronous read, synchronous write memory model //
// This memory cannot be read and written to simultaneously //
/*module DataMem (Mem_Addr, CLK, Mem_rd, Mem_wr, Mem_DIN, Mem_DOUT);
parameter T_rd = 10, T_wr = 10;
parameter MemSize = 1024, WordSize = 32;
input [WordSize-1:0] Mem_Addr;
input CLK, Mem_rd, Mem_wr;
input [WordSize-1:0] Mem_DIN;
output [WordSize-1:0] Mem_DOUT;
reg [WordSize-1:0] Mem_DOUT;
reg [WordSize-1:0] Mem[0:MemSize-1];
integer i;
`include "dmeminit.v"
always @( Mem_Addr or Mem_rd )
if ( ~Mem_wr && Mem_rd )
Mem_DOUT <= #T_rd Mem[Mem_Addr >> 2];
always @(negedge CLK)
if (Mem_wr == 1)
begin
// $display ($time, " . . . ", ..., Mem_DIN);
Mem[Mem_Addr >> 2] <= #T_wr Mem_DIN;
end
endmodule // Dmem*/
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A221OI_BEHAVIORAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_BEHAVIORAL_V
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#include <bits/stdc++.h> inline int mymin(int x, int y) { return x < y ? x : y; } bool isprime[22000]; inline void init_prime() { memset(isprime, true, sizeof(isprime)); for (int i = 2; i <= (int)sqrt(20000 * 1.0); ++i) if (isprime[i]) for (int j = 2; i * j <= 20000; ++j) isprime[i * j] = false; } struct edge { int to, c, next; } e[22000]; int n, id[220], a[220], head[220], h[220], q[220], cnt, tot, num[55], path[55][220]; bool f[220]; inline void print() { printf( Impossible n ); } inline void ins(int u, int v, int c) { e[++cnt].to = v; e[cnt].c = c; e[cnt].next = head[u]; head[u] = cnt; e[++cnt].to = u; e[cnt].c = 0; e[cnt].next = head[v]; head[v] = cnt; } int dfs(int u, int in) { if (u == n + 1 || !in) return in; int out = 0; for (int i = head[u]; i; i = e[i].next) { int v = e[i].to, c = e[i].c; if (h[v] == h[u] + 1 && c) { int flow = dfs(v, mymin(in - out, c)); if (!flow) h[v] = 0; else out += flow; e[i].c -= flow; e[i ^ 1].c += flow; if (in == out) return out; } } return out; } inline bool bfs() { int op = 0, cl = 0; memset(h, 0, sizeof(h)); h[q[++cl] = 0] = 1; while (op < cl) { int u = q[++op]; if (u == n + 1) break; for (int i = head[u]; i; i = e[i].next) { int v = e[i].to, c = e[i].c; if (!h[v] && c) h[q[++cl] = v] = h[u] + 1; } } return h[n + 1]; } inline int Dinic() { int rec = 0; while (bfs()) rec += dfs(0, n); return rec; } int dfs_path(int x) { path[tot][++num[tot]] = x; int y; for (int i = head[x]; i; i = e[i].next) { if (e[i].c) continue; y = e[i].to; if (f[y]) continue; f[y] = true; path[tot][++num[tot]] = y; break; } for (int i = head[y]; i; i = e[i].next) { if (e[i ^ 1].c) continue; x = e[i].to; if (f[x]) continue; f[x] = true; dfs_path(x); } } int main() { scanf( %d , &n); if (n & 1) { print(); return 0; } int cnt1 = 0, cnt2 = n >> 1; for (int i = 1; i <= n; ++i) { int x; scanf( %d , &x); if (x & 1) { a[++cnt1] = x; id[cnt1] = i; } else { a[++cnt2] = x; id[cnt2] = i; } if (cnt1 > n >> 1 || cnt2 > n) { print(); return 0; } } init_prime(); memset(head, 0, sizeof(head)); cnt = 1; for (int i = 1; i <= (n >> 1); ++i) { ins(0, id[i], 2); for (int j = (n >> 1) + 1; j <= n; ++j) if (isprime[a[i] + a[j]]) ins(id[i], id[j], 1); } for (int i = (n >> 1) + 1; i <= n; ++i) ins(id[i], n + 1, 2); int maxflow = Dinic(); if (maxflow != n) { print(); return 0; } memset(f, false, sizeof(f)); f[0] = f[n + 1] = true; tot = 0; for (int i = 1; i <= (n >> 1); ++i) if (!f[id[i]]) { f[id[i]] = true; ++tot; num[tot] = 0; dfs_path(id[i]); } printf( %d n , tot); for (int i = 1; i <= tot; ++i) { printf( %d , num[i]); for (int j = 1; j <= num[i]; ++j) printf( %d , path[i][j]); if (i != tot) printf( n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int sz = 1500000; const long long MAX = 10000000000000000; template <typename T> T abs(T a) { return a < 0 ? -a : a; } int main() { int n, m; cin >> n >> m; vector<vector<int> > graph(n); for (long long i = 0; i < m; i++) { int u, v; cin >> u >> v; graph[u - 1].push_back(v - 1); graph[v - 1].push_back(u - 1); } vector<int> val(n, 0); set<int> q; vector<int> flag(n, 0); vector<int> a(n); for (long long i = 0; i < n; i++) { cin >> a[i]; if (!a[i]) { q.insert(i); } } vector<int> ans; while (!q.empty()) { int top = *q.begin(); q.erase(q.begin()); if (flag[top]) { return 1; } val[top]++; flag[top] = true; ans.push_back(top); for (vector<int>::iterator i = graph[top].begin(); i != graph[top].end(); i++) { val[*i]++; if (val[*i] == a[*i]) { q.insert(*i); } } } cout << ans.size() << endl; for (vector<int>::iterator i = ans.begin(); i != ans.end(); i++) { cout << (*i) + 1 << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n; char a[1000]; int mp[105][150]; int jishu[105][5]; int flag; int main() { scanf( %d , &n); memset(mp, 0, sizeof(mp)); getchar(); for (int i = 1; i <= n; i++) { memset(a, 0, sizeof(a)); gets(a); flag = 0; for (unsigned int j = 0; j < strlen(a); j++) { if (mp[i][a[j]] == 0) { jishu[i][flag] = a[j]; flag++; } mp[i][a[j]]++; if (flag > 2) { memset(mp[i], 0, sizeof(mp[i])); memset(jishu[i], 0, sizeof(jishu[i])); break; } } } int re = 0; int linshi = 0; for (int j = a ; j <= z ; j++) for (int k = a ; k <= z ; k++) { linshi = 0; for (int l = 1; l <= n; l++) { if ((jishu[l][0] == j && jishu[l][1] == k) || (jishu[l][0] == k && jishu[l][1] == j)) { linshi += (mp[l][j] + mp[l][k]); } else { if (jishu[l][1] < 97 || jishu[l][1] > 123) { if (jishu[l][0] == j) { linshi += mp[l][j]; } if (jishu[l][0] == k && j != k) { linshi += mp[l][k]; } } } } re = max(re, linshi); } cout << re << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int f[10000001]; int main() { int n, m, l, r; scanf( %d%d , &n, &m); long long ans = 0; int Max0 = max(n * 2, m); for (long long b = 1; b <= n; ++b) { ans += 2 * min(b * b, (long long)m); l = max(0, int(ceil(sqrt(b * b - m)))); r = int(floor(sqrt(b * b - 1))); ++f[-b - r + Max0], --f[-b - l + 1 + Max0], ++f[-b + l + Max0], --f[-b + r + 1 + Max0]; } int s = 0; for (int i = 0; i < Max0; ++i) { s += f[i]; if (s > 1) ans -= s - 1; } printf( %I64d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int N; pair<pair<int, int>, int> V[100005]; vector<int> r; bool cmp(pair<pair<int, int>, int> a, pair<pair<int, int>, int> b) { if (a.first.first != b.first.first) return a.first.first > b.first.first; return a.first.second > b.first.second; } int main() { cin.sync_with_stdio(false); cout.sync_with_stdio(false); cin >> N; for (int i = 1; i <= N; i++) cin >> V[i].first.first; for (int i = 1; i <= N; i++) { cin >> V[i].first.second; V[i].second = i; } sort(V + 1, V + 1 + N, cmp); r.push_back(V[1].second); for (int i = 2; i <= N; i += 2) { if (V[i].first.second > V[i + 1].first.second) r.push_back(V[i].second); else r.push_back(V[i + 1].second); } cout << r.size() << n ; for (auto it : r) cout << it << ; return 0; }
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// ledtest_ARM_MCU_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module ledtest_ARM_MCU_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3 // .hps_io_emac1_inst_RXD3
);
ledtest_ARM_MCU_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3) // .hps_io_emac1_inst_RXD3
);
endmodule
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