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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> h(n); for (int i = 0; i < n; i++) cin >> h[i]; vector<pair<int, int> > v(n); for (int i = 0; i < n; i++) { v[i] = make_pair(h[i], i); } sort(v.begin(), v.end()); sort(h.begin(), h.end()); h.erase(unique(h.begin(), h.end()), h.end()); if (n - h.size() < 2) { cout << NO << endl; return 0; } else { cout << YES << endl; } map<int, int> x; for (int i = 0; i + 1 < n; i++) { if (v[i].first == v[i + 1].first) { x[v[i].first] += 1; } } int type = x.size(); for (int i = 0; i < 3; i++) { if (i == 0) { for (int j = 0; j < n; j++) { printf( %d , v[j].second + 1); } printf( n ); } else { if (type == 1) { vector<pair<int, int> >::iterator it = lower_bound(v.begin(), v.end(), make_pair(x.begin()->first, -1)); swap(v[it - v.begin()], v[it - v.begin() + i]); for (int j = 0; j < n; j++) { printf( %d , v[j].second + 1); } printf( n ); } else { vector<pair<int, int> >::iterator it = lower_bound(v.begin(), v.end(), make_pair(x.begin()->first, -1)); x.erase(x.begin()); swap(v[it - v.begin()], v[it - v.begin() + 1]); for (int j = 0; j < n; j++) { printf( %d , v[j].second + 1); } printf( n ); } } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int MAXN = 1e6 + 10; int fac[MAXN], infac[MAXN]; long long pow_mod(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = res * a % MOD; a = a * a % MOD; b >>= 1; } return res; } int add(int a, int b) { return (a + b) % MOD; } int mul(int a, int b) { return 1LL * a * b % MOD; } int C(int a, int b) { return mul(fac[a], mul(infac[b], infac[a - b])); } int A(int a, int b) { return mul(fac[a], infac[a - b]); } int F(int a, int b) { if (a == b) return 1; return mul(b, pow_mod(a, a - b - 1)); } int main() { int n, m, a, b; fac[0] = 1; for (int i = 1; i <= 1000000; i++) { fac[i] = mul(i, fac[i - 1]); } infac[1000000] = pow_mod(fac[1000000], MOD - 2); for (int i = 1000000; i >= 1; i--) { infac[i - 1] = mul(infac[i], i); } scanf( %d%d%d%d , &n, &m, &a, &b); int ans = 0; for (int i = 1; i <= n - 1; i++) { if (i > m) { continue; } ans = add(ans, mul(mul(pow_mod(m, n - 1 - i), F(n, i + 1)), mul(A(n - 2, i - 1), C(m - 1, i - 1)))); } printf( %d , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; cin >> t; while (t--) { long long int n; cin >> n; long long int ar[n]; for (int i = 0; i < n; i++) cin >> ar[i]; for (int i = n - 1; i >= 0; i--) cout << ar[i] << ; cout << endl; } return 0; }
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#include <bits/stdc++.h> int main() { int a, b, i, d, c = 0, m = 0, j; scanf( %d %d , &a, &b); d = b; while (d != 0) { c++; d = d / 10; } for (j = 1, i = 1; j < c; j++) { i = i * 10; } while (b != 0) { m = m + (b % 10) * i; b = b / 10; i = i / 10; } printf( %d n , a + m); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 25; const int M = 505; int n, m, a, b; int i, j, k, u, v, con; int deg[N]; bool c[N][N]; double p[N], q[N][N]; double f[M][M]; int g(int i, int j) { return i * n - n + j; } int main() { scanf( %d%d%d%d , &n, &m, &a, &b); for (i = 1; i <= m; i++) { scanf( %d%d , &u, &v); c[u][v] = c[v][u] = 1; deg[u]++; deg[v]++; } for (i = 1; i <= n; i++) scanf( %lf , &p[i]); for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) if (i == j) q[i][j] = p[i]; else if (c[i][j]) q[i][j] = (1 - p[i]) / deg[i]; con = n * n; f[g(a, b)][con + 1] = -1; for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) { f[g(i, j)][g(i, j)]--; for (a = 1; a <= n; a++) for (b = 1; b <= n; b++) if (a != b) f[g(i, j)][g(a, b)] += q[a][i] * q[b][j]; } for (i = 1; i <= con; i++) { for (j = i; j <= con; j++) if (f[j][i] != 0) break; if (j > con) continue; if (j != i) for (k = i; k <= con + 1; k++) swap(f[i][k], f[j][k]); for (j = i + 1; j <= con; j++) for (k = con + 1; k >= i; k--) f[j][k] -= f[j][i] / f[i][i] * f[i][k]; } for (i = con; i; i--) { if (f[i][i] == 0) continue; f[i][con + 1] /= f[i][i]; for (j = i - 1; j; j--) f[j][con + 1] -= f[i][con + 1] * f[j][i]; } for (i = 1; i <= n; i++) printf(i < n ? %.6lf : %.6lf n , f[g(i, i)][con + 1]); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, q; int arr[123456]; int prW[123556]; int leNM[123456]; int main() { cin >> n >> q; n--; int a, b; cin >> a; for (int i = 1; i <= (n); ++i) { cin >> b; arr[i] = abs(a - b); a = b; } vector<pair<int, int> > stack; for (int i = 1; i <= (n); ++i) { pair<int, int> elt = make_pair(arr[i], -i); while (!stack.empty() && elt > stack.back()) { prW[-stack.back().second] = i; stack.pop_back(); } stack.push_back(elt); } while (!stack.empty()) { prW[-stack.back().second] = n + 1; stack.pop_back(); } stack.clear(); for (int i = n; i >= (1); --i) { pair<int, int> elt = make_pair(arr[i], -i); while (!stack.empty() && elt > stack.back()) { leNM[-stack.back().second] = i; stack.pop_back(); } stack.push_back(elt); } while (!stack.empty()) { leNM[-stack.back().second] = 0; stack.pop_back(); } int l, r; long long ans, cur; long long modl, modp; for (int x = 0; x < (q); ++x) { cin >> l >> r; --r; ans = 0; for (int i = l; i <= (r); ++i) { cur = arr[i]; if (leNM[i] < l) modl = i - l + 1; else modl = i - leNM[i]; if (prW[i] > r) modp = r - i + 1; else modp = prW[i] - i; cur *= modl; cur *= modp; ans += cur; } cout << ans << endl; } }
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#include <bits/stdc++.h> using namespace std; long long n, a[200002], v1, v2, ans[200002], mx, subtr[200002]; vector<long long> g[200002]; void dfs(int v, int d, int p) { ans[1] += a[v] * d; for (int to : g[v]) { if (to == p) continue; dfs(to, d + 1, v); } } void dfs2(int v, int p) { long long curr = a[v]; for (int to : g[v]) { if (to == p) continue; dfs2(to, v); curr += subtr[to]; } subtr[v] = curr; } void dfs3(int v, int p) { for (int to : g[v]) { if (to == p) continue; ans[to] = ans[v] + subtr[1] - 2 * subtr[to]; dfs3(to, v); } mx = max(mx, ans[v]); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n - 1; i++) { cin >> v1 >> v2; g[v1].push_back(v2); g[v2].push_back(v1); } dfs(1, 0, -1); dfs2(1, -1); dfs3(1, -1); cout << mx; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, q; char s2[10000006]; char s[205][205]; int vis[205][205]; int dp[205 * 205][20]; int dx[10]; int dy[10]; vector<int> Q; int id(int x, int y) { return x * m + y; } void dfs(int x, int y) { vis[x][y] = 1; int t = (s[x][y] - 0 ), p = id(x, y); int xx = x + dx[t], yy = y + dy[t]; if (xx < 0 || xx >= n || yy < 0 || yy >= m) dp[p][t] = p; else { int v = id(xx, yy); dp[p][t] = id(xx, yy); if (vis[xx][yy] == 0) dfs(xx, yy); for (int i = 0; i < 10; i++) if (i != t) dp[p][i] = dp[v][i]; } } int check(char s2[]) { int len = strlen(s2); for (int i = 0; i < Q.size(); i++) { int x = Q[i]; for (int j = 0; j < len; j++) { x = dp[x][s2[j] - 0 ]; if (x < 0) break; } if (x >= 0) return 1; } return 0; } int main() { memset(dp, -1, sizeof(dp)); scanf( %d%d%d , &n, &m, &q); for (int i = 0; i < n; i++) scanf( %s , s[i]); for (int i = 0; i < 10; i++) scanf( %d%d , &dx[i], &dy[i]); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (!vis[i][j]) { dfs(i, j); Q.push_back(id(i, j)); } } } for (int i = 0; i < q; i++) { scanf( %s , s2); if (check(s2)) printf( YES n ); else puts( NO ); } }
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#include <bits/stdc++.h> using namespace std; int t[111]; int main() { int n, k, m; cin >> n >> k >> m; int sum = 0; for (int i = 0; i < k; i++) { cin >> t[i]; sum += t[i]; } sort(t, t + k); int ans = 0; for (int i = 0; i <= n; i++) { int time = m - sum * i; if (time < 0) break; int cnt = (k + 1) * i; for (int j = 0; j < k; j++) { for (int q = 0; q < (n - i); q++) { if (time - t[j] >= 0) { cnt++; time -= t[j]; } } } ans = max(ans, cnt); } cout << ans << endl; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__XOR3_BEHAVIORAL_PP_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire xor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int r, b; cin >> r >> b; cout << max(r, b) - 1 << << min(r, b) << n ; return 0; }
|
module FF_scan8(
rclk,
rSE,
rSD,
rD,
Q8
);
wire [7:0] wQ ;
wire [7:0] OutInv ;
output reg Q8;
input wire rD;
input wire rSE;
input wire rclk;
input wire rSD;
always @(posedge rclk) begin
Q8 = wQ[7] ;
end
FF_scan FF_scan_intance0(
.clk(rclk),
.SE(rSE),
.SD(rSD),
.D(rD),
.Q(wQ[0])
);
inv intance0(
.in (wQ[0]),
.out (OutInv[0]
)
);
FF_scan FF_scan_intance1(
.clk(rclk),
.SE(rSE),
.SD(wQ[0]),
.D(OutInv[0]),
.Q(wQ[1])
);
inv intance1(
.in(wQ[1]),
.out(OutInv[1] )
);
FF_scan FF_scan_intance2(
.clk(rclk),
.SE(rSE),
.SD(wQ[1]),
.D(OutInv[1]),
.Q(wQ[2])
);
inv intance2(
.in(wQ[2]),
.out(OutInv[2] )
);
FF_scan FF_scan_intance3(
.clk(rclk),
.SE(rSE),
.SD(wQ[2]),
.D(OutInv[2]),
.Q(wQ[3])
);
inv intance3(
.in(wQ[3]),
.out(OutInv[3] )
);
FF_scan FF_scan_intance4(
.clk(rclk),
.SE(rSE),
.SD(wQ[3]),
.D(OutInv[3]),
.Q(wQ[4])
);
inv intance4(
.in(wQ[4]),
.out(OutInv[4])
);
FF_scan FF_scan_intance5(
.clk(rclk),
.SE(rSE),
.SD(wQ[4]),
.D(OutInv[4]),
.Q(wQ[5])
);
inv intance5(
.in(wQ[5]),
.out(OutInv[5])
);
FF_scan FF_scan_intance6(
.clk(rclk),
.SE(rSE),
.SD(wQ[5]),
.D(OutInv[5]),
.Q(wQ[6])
);
inv intance6(
.in(wQ[6]),
.out(OutInv[6])
);
FF_scan FF_scan_intance7(
.clk(rclk),
.SE(rSE),
.SD(wQ[6]),
.D(OutInv[6]),
.Q(wQ[7])
);
inv intance7(
.in(wQ[7]),
.out(OutInv[7])
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: ps2_cache.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ps2_cache (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input [21:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [21:0] q;
output rdempty;
output wrfull;
wire sub_wire0;
wire [21:0] sub_wire1;
wire sub_wire2;
wire wrfull = sub_wire0;
wire [21:0] q = sub_wire1[21:0];
wire rdempty = sub_wire2;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.aclr (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone III",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 22,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "22"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "22"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "22"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 22 0 INPUT NODEFVAL "data[21..0]"
// Retrieval info: USED_PORT: q 0 0 22 0 OUTPUT NODEFVAL "q[21..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @data 0 0 22 0 data 0 0 22 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 22 0 @q 0 0 22 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Antecedent does not have consequent");
end
end
end
assign fire_2state_1 = ((antecedent_expr == 1'b1) && (consequent_expr == 1'b0));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1, fire_xcheck_2;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"antecedent_expr contains X or Z");
end
if (fire_xcheck_2) begin
ovl_error_t(`OVL_FIRE_XCHECK,"consequent_expr contains X or Z");
end
end
end
wire valid_antecedent_expr = ((antecedent_expr ^ antecedent_expr) == 1'b0);
wire valid_consequent_expr = ((consequent_expr ^ consequent_expr) == 1'b0);
always @ (valid_antecedent_expr or consequent_expr) begin
if (valid_antecedent_expr || consequent_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1; // antecedent X when consequent is 0
end
end
always @ (antecedent_expr or valid_consequent_expr) begin
if ((antecedent_expr == 1'b0) || valid_consequent_expr) begin
fire_xcheck_2 = 1'b0;
end
else begin
fire_xcheck_2 = 1'b1; // consequent X when antecedent is 1
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
wire fire_cover_1;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("antecedent covered"); // basic
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (antecedent_expr == 1'b1));
`endif // OVL_COVER_ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_3_V
`define SKY130_FD_SC_LS__DECAPHE_3_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog wrapper for decaphe with size of 3 units (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphe.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_3 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__decaphe base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_3 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__decaphe base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_3_V
|
#include <bits/stdc++.h> using namespace std; template <typename... T> void show(T&&... args) { ((cerr << args << ), ...); } template <typename F, typename S> ostream& operator<<(ostream& os, const pair<F, S>& p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { os << { ; typename vector<T>::const_iterator it; for (it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } return os << } ; } template <typename T> ostream& operator<<(ostream& os, const set<T>& v) { os << [ ; typename set<T>::const_iterator it; for (it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename T> ostream& operator<<(ostream& os, const multiset<T>& v) { os << [ ; typename multiset<T>::const_iterator it; for (it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << *it; } return os << ] ; } template <typename F, typename S> ostream& operator<<(ostream& os, const map<F, S>& v) { os << [ ; typename map<F, S>::const_iterator it; for (it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << it->first << = << it->second; } return os << ] ; } template <typename F, typename S> ostream& operator<<(ostream& os, const unordered_map<F, S>& v) { os << [ ; typename unordered_map<F, S>::const_iterator it; for (it = v.begin(); it != v.end(); it++) { if (it != v.begin()) os << , ; os << it->first << = << it->second; } return os << ] ; } template <typename... T> void read(T&... args) { ((cin >> args), ...); } template <typename... T> void write(T&&... args) { ((cout << args << ), ...); } inline void file_io(string path1 = , string path2 = ) { if (path2.size() == 0) path2 = path1; freopen(path1.c_str(), r , stdin); freopen(path2.c_str(), w , stdout); } template <typename T> T egcd(T a, T b, T& x, T& y) { x = 1, y = 0; T x1 = 0, y1 = 1, a1 = a, b1 = b; while (b1) { T q = a1 / b1; tie(x, x1) = make_tuple(x1, x - q * x1); tie(y, y1) = make_tuple(y1, y - q * y1); tie(a1, b1) = make_tuple(b1, a1 - q * b1); } return a1; } template <typename F, typename S> F bigMod(F a, F b, S mod) { a %= mod; F res = 1; while (b > 0) { if (b & 1) res = ((long long)res * a) % mod; a = ((long long)a * a) % mod; b >>= 1; } return res; } inline int modAdd(long long _a, long long _b, long long mod) { if (_a < 0) { _a += mod; } if (_b < 0) { _b += mod; } if (_a + _b >= mod) return (_a + _b - mod); return (_a + _b); } inline int modMul(long long _a, long long _b, long long mod) { if (_a < 0) { _a += mod; } if (_b < 0) { _b += mod; } return (_a * _b) % mod; } inline int modInv(long long a, long long mod) { return bigMod(a, mod - 2, mod); } const long long mod = 998244353; int solve() { int n; cin >> n; int dp[n + 5][2], ans = 0; memset(dp, 0, sizeof dp); dp[0][0] = 1; for (int i = 0; i < n; i++) { int val; cin >> val; dp[val + 1][0] = modAdd(dp[val + 1][0], dp[val + 1][0], mod); dp[val + 1][0] = modAdd(dp[val + 1][0], dp[val][0], mod); if (val - 1 >= 0) dp[val - 1][1] = modAdd(dp[val - 1][1], dp[val - 1][1], mod); if (val - 1 >= 0) dp[val - 1][1] = modAdd(dp[val - 1][1], dp[val - 1][0], mod); dp[val + 1][1] = modAdd(dp[val + 1][1], dp[val + 1][1], mod); } for (int i = 0; i < n + 5; i++) { ans = modAdd(ans, dp[i][0], mod); ans = modAdd(ans, dp[i][1], mod); } ans = modAdd(ans, -1, mod); cout << ans << n ; return 0; } int main() { ios::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); ; ; int t = 1, cs = 0; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; string int_to_string(int a) { stringstream ss; ss << a; return ss.str(); } string double_to_string(double a) { stringstream ss; ss << a; return ss.str(); } string float_to_string(float a) { stringstream ss; ss << a; return ss.str(); } string long_to_string(long a) { stringstream ss; ss << a; return ss.str(); } string long_long_to_string(long long a) { stringstream ss; ss << a; return ss.str(); } int string_to_int(string s) { return atoi(s.c_str()); } float string_to_float(string s) { return atof(s.c_str()); } long string_to_long(string s) { return atol(s.c_str()); } long long string_to_long_long(string s) { return atoll(s.c_str()); } int main() { long long n, c = 0; cin >> n; for (long long i = 1; i <= n; i *= 10) c += (n - (i - 1)); cout << c; return 0; }
|
#include <bits/stdc++.h> using namespace std; set<int> s[40]; set<int>::iterator it, q; int n, m, k, sol, v[40]; int main() { int i, j; scanf( %d %d , &n, &m); for (i = 1; i <= n; i++) { scanf( %d , &v[i]); v[i] %= m; } if (n == 1) { printf( %d , v[1]); return 0; } if (n == 2) { printf( %d , max((v[1] + v[2]) % m, max(v[1], v[2]))); return 0; } k = n / 2; for (i = 1; i <= n; i++) { s[i].insert(v[i]); if (i != k + 1) { for (it = s[i - 1].begin(); it != s[i - 1].end(); it++) { j = *it; s[i].insert(j); j += v[i]; j %= m; s[i].insert(j); } s[i - 1].clear(); } } it = s[k].end(); it--; sol = *it; it = s[n].end(); it--; sol = max(sol, int(*it)); if (s[n].begin() != s[n].end()) for (it = s[k].begin(); it != s[k].end(); it++) { i = *it; j = m - i; q = s[n].lower_bound(j); if (q != s[n].begin()) { q--; sol = max(sol, (i + int(*q)) % m); } q = s[n].end(); q--; sol = max(sol, int((1LL * i + int(*q)) % m)); } printf( %d , sol); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_1_V
`define SKY130_FD_SC_LS__A221OI_1_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221oi_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// Receive HDMI, hdmi embedded syncs data in, video dma data out.
module axi_hdmi_rx_es (
// hdmi interface
hdmi_clk,
hdmi_data,
hdmi_vs_de,
hdmi_hs_de,
hdmi_data_de);
// parameters
parameter DATA_WIDTH = 32;
localparam BYTE_WIDTH = DATA_WIDTH/8;
// hdmi interface
input hdmi_clk;
input [(DATA_WIDTH-1):0] hdmi_data;
// dma interface
output hdmi_vs_de;
output hdmi_hs_de;
output [(DATA_WIDTH-1):0] hdmi_data_de;
// internal registers
reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0;
reg hdmi_hs_de_rcv_d = 'd0;
reg hdmi_vs_de_rcv_d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_2d = 'd0;
reg hdmi_hs_de_rcv_2d = 'd0;
reg hdmi_vs_de_rcv_2d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_3d = 'd0;
reg hdmi_hs_de_rcv_3d = 'd0;
reg hdmi_vs_de_rcv_3d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0;
reg hdmi_hs_de_rcv_4d = 'd0;
reg hdmi_vs_de_rcv_4d = 'd0;
reg [(DATA_WIDTH-1):0] hdmi_data_de = 'd0;
reg hdmi_hs_de = 'd0;
reg hdmi_vs_de = 'd0;
reg [ 1:0] hdmi_preamble_cnt = 'd0;
reg hdmi_hs_de_rcv = 'd0;
reg hdmi_vs_de_rcv = 'd0;
// internal signals
wire [(DATA_WIDTH-1):0] hdmi_ff_s;
wire [(DATA_WIDTH-1):0] hdmi_00_s;
wire [(DATA_WIDTH-1):0] hdmi_b6_s;
wire [(DATA_WIDTH-1):0] hdmi_9d_s;
wire [(DATA_WIDTH-1):0] hdmi_ab_s;
wire [(DATA_WIDTH-1):0] hdmi_80_s;
// es constants
assign hdmi_ff_s = {BYTE_WIDTH{8'hff}};
assign hdmi_00_s = {BYTE_WIDTH{8'h00}};
assign hdmi_b6_s = {BYTE_WIDTH{8'hb6}};
assign hdmi_9d_s = {BYTE_WIDTH{8'h9d}};
assign hdmi_ab_s = {BYTE_WIDTH{8'hab}};
assign hdmi_80_s = {BYTE_WIDTH{8'h80}};
// delay to get rid of eav's 4 bytes
always @(posedge hdmi_clk) begin
hdmi_data_d <= hdmi_data;
hdmi_hs_de_rcv_d <= hdmi_hs_de_rcv;
hdmi_vs_de_rcv_d <= hdmi_vs_de_rcv;
hdmi_data_2d <= hdmi_data_d;
hdmi_hs_de_rcv_2d <= hdmi_hs_de_rcv_d;
hdmi_vs_de_rcv_2d <= hdmi_vs_de_rcv_d;
hdmi_data_3d <= hdmi_data_2d;
hdmi_hs_de_rcv_3d <= hdmi_hs_de_rcv_2d;
hdmi_vs_de_rcv_3d <= hdmi_vs_de_rcv_2d;
hdmi_data_4d <= hdmi_data_3d;
hdmi_hs_de_rcv_4d <= hdmi_hs_de_rcv_3d;
hdmi_vs_de_rcv_4d <= hdmi_vs_de_rcv_3d;
hdmi_data_de <= hdmi_data_4d;
hdmi_hs_de <= hdmi_hs_de_rcv & hdmi_hs_de_rcv_4d;
hdmi_vs_de <= hdmi_vs_de_rcv & hdmi_vs_de_rcv_4d;
end
// check for sav and eav and generate the corresponding enables
always @(posedge hdmi_clk) begin
if ((hdmi_data == hdmi_ff_s) || (hdmi_data == hdmi_00_s)) begin
hdmi_preamble_cnt <= hdmi_preamble_cnt + 1'b1;
end else begin
hdmi_preamble_cnt <= 'd0;
end
if (hdmi_preamble_cnt == 3'b11) begin
if ((hdmi_data == hdmi_b6_s) || (hdmi_data == hdmi_9d_s)) begin
hdmi_hs_de_rcv <= 1'b0;
end else if ((hdmi_data == hdmi_ab_s) || (hdmi_data == hdmi_80_s)) begin
hdmi_hs_de_rcv <= 1'b1;
end
if (hdmi_data == hdmi_b6_s) begin
hdmi_vs_de_rcv <= 1'b0;
end else if (hdmi_data == hdmi_9d_s) begin
hdmi_vs_de_rcv <= 1'b1;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5, M = 1e9 + 7; const unsigned long long base = 13331; const double Pi = acos(-1.0); const long long C = 299792458; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } char a[505][505]; int n, m; bool check() { for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (a[i][j] == * ) { if (i - 1 < 1 || i + 1 > n || j - 1 < 1 || j + 1 > m) continue; if (a[i - 1][j] == * && a[i + 1][j] == * && a[i][j - 1] == * && a[i][j + 1] == * ) { a[i][j] = . ; for (int k = i - 1; k >= 1; k--) { if (a[k][j] == * ) a[k][j] = . ; else break; } for (int k = i + 1; k <= n; k++) { if (a[k][j] == * ) a[k][j] = . ; else break; } for (int k = j - 1; k >= 1; k--) { if (a[i][k] == * ) a[i][k] = . ; else break; } for (int k = j + 1; k <= m; k++) { if (a[i][k] == * ) a[i][k] = . ; else break; } return true; } } } } return false; } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> a[i][j]; } } if (!check()) { cout << NO << endl; } else { for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (a[i][j] == * ) { cout << NO << endl; return 0; } } } cout << YES << endl; } }
|
module top(...);
parameter LUT_WIDTH = 4; // Multiples of 2 only
input [LUT_WIDTH-1:0] a;
output o1_1 = {(LUT_WIDTH/2){2'b10}} <= a;
output o1_2 = {(LUT_WIDTH/2){2'b10}} < a;
output o1_3 = {(LUT_WIDTH/2){2'b10}} >= a;
output o1_4 = {(LUT_WIDTH/2){2'b10}} > a;
output o1_5 = {(LUT_WIDTH/2){2'b10}} == a;
output o1_6 = {(LUT_WIDTH/2){2'b10}} != a;
output o2_1 = a <= {(LUT_WIDTH/2){2'b10}};
output o2_2 = a < {(LUT_WIDTH/2){2'b10}};
output o2_3 = a >= {(LUT_WIDTH/2){2'b10}};
output o2_4 = a > {(LUT_WIDTH/2){2'b10}};
output o2_5 = a == {(LUT_WIDTH/2){2'b10}};
output o2_6 = a != {(LUT_WIDTH/2){2'b10}};
output o3_1 = {(LUT_WIDTH/2){2'sb01}} <= $signed(a);
output o3_2 = {(LUT_WIDTH/2){2'sb01}} < $signed(a);
output o3_3 = {(LUT_WIDTH/2){2'sb01}} >= $signed(a);
output o3_4 = {(LUT_WIDTH/2){2'sb01}} > $signed(a);
output o3_5 = {(LUT_WIDTH/2){2'sb01}} == $signed(a);
output o3_6 = {(LUT_WIDTH/2){2'sb01}} != $signed(a);
output o4_1 = $signed(a) <= {LUT_WIDTH{1'sb0}};
output o4_2 = $signed(a) < {LUT_WIDTH{1'sb0}};
output o4_3 = $signed(a) >= {LUT_WIDTH{1'sb0}};
output o4_4 = $signed(a) > {LUT_WIDTH{1'sb0}};
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_INT_OSC
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_int_osc
(
clkout,
oscena);
parameter DEVICE_FAMILY = "MAX 10";
parameter DEVICE_ID = "08";
parameter CLOCK_FREQUENCY = "dummy";
output clkout;
input oscena;
wire wire_clkout;
assign clkout = wire_clkout;
// -------------------------------------------------------------------
// Instantiate wysiwyg for chipidblock according to device family
// -------------------------------------------------------------------
generate
if (DEVICE_FAMILY == "MAX 10") begin
fiftyfivenm_oscillator # ( //MAX 10
.device_id(DEVICE_ID),
.clock_frequency(CLOCK_FREQUENCY)
) oscillator_dut (
.clkout(wire_clkout),
.clkout1(),
.oscena(oscena));
end
endgenerate
endmodule //altera_int_osc
//VALID FILE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SDFRTP_FUNCTIONAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_pg/sky130_fd_sc_hs__u_df_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrtp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_r_pg `UNIT_DELAY u_df_p_r_pg0 (buf_Q , mux_out, CLK, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_FUNCTIONAL_PP_V
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_design_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram3_ddr3_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram3_ddr3_rptr( /*AUTOARG*/
// Outputs
io_dram_data_valid_buf, io_dram_ecc_in_buf, io_dram_data_in_buf,
dram_io_cas_l_buf, dram_io_channel_disabled_buf, dram_io_cke_buf,
dram_io_clk_enable_buf, dram_io_drive_data_buf,
dram_io_drive_enable_buf, dram_io_pad_clk_inv_buf,
dram_io_pad_enable_buf, dram_io_ras_l_buf, dram_io_write_en_l_buf,
dram_io_addr_buf, dram_io_bank_buf, dram_io_cs_l_buf,
dram_io_data_out_buf, dram_io_ptr_clk_inv_buf,
// Inputs
io_dram_data_valid, io_dram_ecc_in, io_dram_data_in,
dram_io_cas_l, dram_io_channel_disabled, dram_io_cke,
dram_io_clk_enable, dram_io_drive_data, dram_io_drive_enable,
dram_io_pad_clk_inv, dram_io_pad_enable, dram_io_ras_l,
dram_io_write_en_l, dram_io_addr, dram_io_bank, dram_io_cs_l,
dram_io_data_out, dram_io_ptr_clk_inv
);
/*OUTPUTS*/
output io_dram_data_valid_buf;
output [31:0] io_dram_ecc_in_buf;
output [255:0] io_dram_data_in_buf;
output dram_io_cas_l_buf;
output dram_io_channel_disabled_buf;
output dram_io_cke_buf;
output dram_io_clk_enable_buf;
output dram_io_drive_data_buf;
output dram_io_drive_enable_buf;
output dram_io_pad_clk_inv_buf;
output dram_io_pad_enable_buf;
output dram_io_ras_l_buf;
output dram_io_write_en_l_buf;
output [14:0] dram_io_addr_buf;
output [2:0] dram_io_bank_buf;
output [3:0] dram_io_cs_l_buf;
output [287:0] dram_io_data_out_buf;
output [4:0] dram_io_ptr_clk_inv_buf;
/*INPUTS*/
input io_dram_data_valid;
input [31:0] io_dram_ecc_in;
input [255:0] io_dram_data_in;
input dram_io_cas_l;
input dram_io_channel_disabled;
input dram_io_cke;
input dram_io_clk_enable;
input dram_io_drive_data;
input dram_io_drive_enable;
input dram_io_pad_clk_inv;
input dram_io_pad_enable;
input dram_io_ras_l;
input dram_io_write_en_l;
input [14:0] dram_io_addr;
input [2:0] dram_io_bank;
input [3:0] dram_io_cs_l;
input [287:0] dram_io_data_out;
input [4:0] dram_io_ptr_clk_inv;
/************************* CODE *********************************/
assign io_dram_data_in_buf = io_dram_data_in[255:0];
assign io_dram_data_valid_buf = io_dram_data_valid;
assign io_dram_ecc_in_buf = io_dram_ecc_in[31:0];
assign dram_io_addr_buf = dram_io_addr[14:0];
assign dram_io_bank_buf = dram_io_bank[2:0];
assign dram_io_cas_l_buf = dram_io_cas_l;
assign dram_io_channel_disabled_buf = dram_io_channel_disabled;
assign dram_io_cke_buf = dram_io_cke;
assign dram_io_clk_enable_buf = dram_io_clk_enable;
assign dram_io_cs_l_buf = dram_io_cs_l[3:0];
assign dram_io_data_out_buf = dram_io_data_out[287:0];
assign dram_io_drive_data_buf = dram_io_drive_data;
assign dram_io_drive_enable_buf = dram_io_drive_enable;
assign dram_io_pad_clk_inv_buf = dram_io_pad_clk_inv;
assign dram_io_pad_enable_buf = dram_io_pad_enable;
assign dram_io_ptr_clk_inv_buf = dram_io_ptr_clk_inv[4:0];
assign dram_io_ras_l_buf = dram_io_ras_l;
assign dram_io_write_en_l_buf = dram_io_write_en_l;
endmodule
|
// Check that VAMS `abs()` functions works if its argument is a function call
module main;
function reg signed [7:0] fv(input reg signed [7:0] x);
fv = x;
endfunction
function real fr(input real x);
fr = x;
endfunction
reg signed [7:0] a;
wire signed [7:0] vala = abs(fv(a));
reg real b;
wire real valb = abs(fr(b));
initial begin
a = 0;
b = 0;
#1 if (vala !== 0) begin
$display("FAILED -- a=%b, vala=%b", a, vala);
$finish;
end
#1 if (valb != 0) begin
$display("FAILED -- b=%g valb=%g", b, valb);
$finish;
end
a = 1;
b = 1;
#1 if (vala !== 1) begin
$display("FAILED -- a=%b, vala=%b", a, vala);
$finish;
end
#1 if (valb != 1) begin
$display("FAILED -- b=%g valb=%g", b, valb);
$finish;
end
a = -1;
b = -1;
#1 if (vala !== 1) begin
$display("FAILED -- a=%b, vala=%b", a, vala);
$finish;
end
#1 if (valb != 1) begin
$display("FAILED -- b=%g valb=%g", b, valb);
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const long long INF = 1e12; const int MOD = 1e9 + 7; const unsigned long long BIT_FLAG_0 = (1 << 0); const unsigned long long BIT_FLAG_1 = (1 << 1); const unsigned long long BIT_FLAG_2 = (1 << 2); const unsigned long long BIT_FLAG_3 = (1 << 3); const unsigned long long BIT_FLAG_4 = (1 << 4); const unsigned long long BIT_FLAG_5 = (1 << 5); const unsigned long long BIT_FLAG_6 = (1 << 6); const unsigned long long BIT_FLAG_7 = (1 << 7); const long long dx[4] = {0, 1, 0, -1}, dy[4] = {-1, 0, 1, 0}; const long long Dx[8] = {0, 1, 1, 1, 0, -1, -1, -1}, Dy[8] = {-1, -1, 0, 1, 1, 1, 0, -1}; void print() { cout << n ; } template <class Head, class... Tail> void print(Head &&head, Tail &&...tail) { cout << head; if (sizeof...(tail) != 0) cout << ; print(forward<Tail>(tail)...); } template <class T> void print(vector<T> &vec) { for (auto &a : vec) { cout << a; if (&a != &vec.back()) cout << ; } cout << n ; } template <class T> void print(set<T> &set) { for (auto &a : set) { cout << a << ; } cout << n ; } template <class T> void print(vector<vector<T>> &df) { for (auto &vec : df) { print(vec); } } long long power(long long a, long long n) { long long res = 1; while (n > 0) { if (n & 1) res = res * a; a *= a; n >>= 1; } return res; } long long comb(long long n, long long k) { vector<vector<long long>> v(n + 1, vector<long long>(n + 1, 0)); for (long long i = 0; i < (long long)((v).size()); i++) { v[i][0] = 1; v[i][i] = 1; } for (long long k = 1; k < (long long)((v).size()); k++) { for (long long j = 1; j < k; j++) { v[k][j] = (v[k - 1][j - 1] + v[k - 1][j]); } } return v[n][k]; } void add(long long &a, long long b) { a += b; if (a >= MOD) a -= MOD; } template <class T> inline bool chmin(T &a, T b) { if (a > b) { a = b; return true; } return false; } template <class T> inline bool chmax(T &a, T b) { if (a < b) { a = b; return true; } return false; } __attribute__((constructor)) void faster_io() { ios_base::sync_with_stdio(false); cin.tie(nullptr); } long long n, k; map<long long, long long> got; pair<bool, multiset<long long>> isOK(long long idx) { multiset<long long> ans; multiset<long long> trueans; long long cnt = 0; for (const auto &[key, value] : got) { long long types = value / idx; cnt += types; for (long long ti = 0; ti < (long long)(types); ti++) { ans.insert(key); } } if (cnt >= k) { long long now = 0; for (auto i : ans) { trueans.insert(i); now++; if (now == k) { break; } } return make_pair(true, trueans); } else { return make_pair(false, trueans); } } multiset<long long> bin_search() { multiset<long long> finalans; long long ng = n + 1; long long ok = 0; while (abs(ok - ng) > 1) { long long mid = (ok + ng) / 2; long long bl = isOK(mid).first; auto nums = isOK(mid).second; if (bl) { ok = mid; finalans = nums; } else ng = mid; } return finalans; } signed main() { cin >> n >> k; vector<long long> A(n); for (long long ni = 0; ni < (long long)(n); ni++) { long long v; cin >> v; A[ni] = v; got[v]++; } auto ret = bin_search(); for (auto i : ret) { cout << i << ; } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB4_S16 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_64x22(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 22;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
wire [9:0] unconnected;
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x22_bist artisan_ssp(
`else
art_hssp_64x22 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x22 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x22_bist vs_ssp(
`else
vs_hdsp_64x22 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({unconnected, di[21:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[21:16]})
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB4_S16
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; while (t--) { long long int n, cnt = 0; cin >> n; string s[n]; long long int h1[10] = {}, h2[10] = {}; for (int i = 0; i < n; i++) { cin >> s[i]; h1[s[i][3] - 0 ]++; } for (int i = 0; i < n - 1; i++) { for (int j = i + 1; j < n; j++) { if (s[i].compare(s[j]) == 0) { int k; cnt++; for (k = 0; k < 10; k++) { if (h1[k] == 0) { break; } } h1[s[i][3] - 0 ]--; h1[k]++; s[i][3] = k + 0 ; } } } cout << cnt << endl; for (int i = 0; i < n; i++) { cout << s[i] << endl; } } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine Funnel Shifter and Color Selector
// File : ded_funcol.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module instantiates the funnel shifter and color selector
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_funcol
#(parameter BYTES = 4)
(
input mclock, // Clock for delaying RAD
input [1:0] stpl_4, // stipple mode bit 01 = planar, 10 = packed
input [1:0] apat_4, // should be moved to here from ded_top_misc
input ps8_4,
ps16_4,
ps32_4,
input lt_actv_4,
input [31:0] fore_4, // foreground register output
input [31:0] back_4, // foreground register output
input solid_4,
input [(BYTES<<3)-1:0] pc_col, // color select from pix cache
`ifdef BYTE16 input [6:0] rad,
`elsif BYTE8 input [5:0] rad,
`else input [4:0] rad, `endif
input [(BYTES<<3)-1:0] bsd0,bsd1, // cache data output
output [(BYTES<<3)-1:0] col_dat, // frame buffer data output
output [BYTES-1:0] trns_msk, // transparentcy mask
output [BYTES-1:0] cx_sel // color expand selector (for test)
);
wire [(BYTES<<3)-1:0] fs_dat; // funnel shift data to color selector
/****************************************************************/
/* DATAPATH FUNNEL SHIFTER */
/****************************************************************/
ded_funshf #
(
.BYTES (BYTES)
)
U_FUNSHF
(
.mclock (mclock),
.rad (rad),
.bsd0 (bsd0),
.bsd1 (bsd1),
.apat8_4 (apat_4[0]),
.apat32_4 (apat_4[1]),
.bsout (fs_dat),
.cx_sel (cx_sel)
);
/****************************************************************/
/* DATAPATH COLOR SELECTOR */
/****************************************************************/
ded_colsel #
(
.BYTES (BYTES)
)
U_COLSEL
(
.mclock (mclock),
.ps8_4 (ps8_4),
.ps16_4 (ps16_4),
.ps32_4 (ps32_4),
.stpl_4 (stpl_4),
.lt_actv_4 (lt_actv_4),
.fore_4 (fore_4),
.back_4 (back_4),
.fs_dat (fs_dat),
.cx_sel (cx_sel),
.pc_col (pc_col),
.solid_4 (solid_4),
.col_dat (col_dat),
.trns_msk (trns_msk));
endmodule // DED_FUNCOL
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200000; bool active[MAXN + 10]; int v[MAXN + 10]; vector<int> factors[MAXN + 10]; int cantidad[5000001]; int main() { int n, q; scanf( %d %d , &n, &q); for (int i = 0; i < n; i++) { scanf( %d , &v[i]); int aux = v[i]; for (int j = 2; j * j <= aux; j++) { if (aux % j == 0) { factors[i].push_back(j); while (aux % j == 0) aux /= j; } } if (aux > 1) factors[i].push_back(aux); } long long bad = 0; int cnt = 0, ones = 0; for (int i = 0; i < q; i++) { int x; scanf( %d , &x); x--; if (active[x]) { if (v[x] == 1) { ones--; } else { cnt--; int sz = factors[x].size(); for (int j = 1; j < (1 << sz); j++) { int counter = 0; int product = 1; for (int k = 0; k < sz; k++) { if (j & (1 << k)) { counter++; product = product * factors[x][k]; } } cantidad[product]--; if (counter & 1) bad -= cantidad[product]; else bad += cantidad[product]; } } } else { if (v[x] == 1) ones++; else { cnt++; int sz = (int)factors[x].size(); for (int j = 1; j < (1 << sz); j++) { int counter = 0; int product = 1; for (int k = 0; k < sz; k++) { if (j & (1 << k)) { counter++; product = product * factors[x][k]; } } if (counter & 1) bad += cantidad[product]; else bad -= cantidad[product]; cantidad[product]++; } } } active[x] = !active[x]; printf( %lld n , (1LL * cnt * (cnt - 1) / 2) - bad + (1LL * cnt * ones) + 1LL * ones * (ones - 1) / 2); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int r, n, d; int kol = 0; cin >> n >> d; int *a = new int[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (i != j && abs(a[i] - a[j]) <= d) { kol++; } cout << kol; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t, i, j; char c = W ; cin >> t; for (i = 0; i < t; i++) { for (j = 0; j < t; j++) { cout << c; if (c == B ) c = W ; else c = B ; } if (t % 2 == 0) { if (c == B ) c = W ; else c = B ; } cout << n ; } return 0; }
|
/*
* duty_cycle_check_tb.v: Test bench for duty_cycle_check.v
* author: Till Mahlburg
* year: 2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 1000
`endif
`ifndef DESIRED_DUTY_CYCLE
`define DESIRED_DUTY_CYCLE 0.5
`endif
`ifndef CLK_PERIOD
`define CLK_PERIOD 10
`endif
module duty_cycle_check_tb ();
reg rst;
reg clk;
reg LOCKED;
wire fail;
reg [31:0] duty_cycle_1000;
integer pass_count;
integer fail_count;
/* adjust according to the number of test cases */
localparam total = 4;
duty_cycle_check dut (
.desired_duty_cycle_1000(`DESIRED_DUTY_CYCLE * 1000),
.clk_period_1000(`CLK_PERIOD * 1000),
.clk(clk),
.reset(rst),
.LOCKED(LOCKED),
.fail(fail));
initial begin
$dumpfile("duty_cycle_check_tb.vcd");
$dumpvars(0, duty_cycle_check_tb);
duty_cycle_1000 = 1000 * `DESIRED_DUTY_CYCLE;
rst = 0;
clk = 0;
LOCKED = 0;
pass_count = 0;
fail_count = 0;
#1;
clk = 1;
#10;
rst = 1;
#10;
if (fail == 1'b0) begin
$display("PASSED: reset");
pass_count = pass_count + 1;
end else begin
$display("FAILED: reset");
fail_count = fail_count + 1;
end
rst = 0;
#(`CLK_PERIOD * 3);
if (fail == 1'b0) begin
$display("PASSED: LOCKED");
pass_count = pass_count + 1;
end else begin
$display("FAILED: LOCKED");
fail_count = fail_count + 1;
end
LOCKED = 1;
#`WAIT_INTERVAL;
if (fail == 1'b0) begin
$display("PASSED: duty cycle matches");
pass_count = pass_count + 1;
end else begin
$display("FAILED: duty cycle matches");
fail_count = fail_count + 1;
end
duty_cycle_1000 = duty_cycle_1000 - 100;
#`WAIT_INTERVAL;
if (fail == 1'b1) begin
$display("PASSED: duty cycle differs");
pass_count = pass_count + 1;
end else begin
$display("FAILED: duty cycle differs");
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always @(posedge clk) begin
#(`CLK_PERIOD * (duty_cycle_1000 / 1000.0)) clk <= ~clk;
end
always @(negedge clk) begin
#(`CLK_PERIOD * (1 - (duty_cycle_1000 / 1000.0))) clk <= ~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int d[200060], cost[200060]; long long int m, tank; vector<pair<int, int>> temp; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int src; cin >> src >> tank >> m; d[0] = 0; cost[0] = 0; d[m + 1] = src; cost[m + 1] = 0; for (int i = 0; i < m; i++) { pair<int, int> t; cin >> t.first >> t.second; temp.push_back(t); } sort(temp.begin(), temp.end()); for (int i = 0; i < m; i++) { d[i + 1] = temp[i].first; cost[i + 1] = temp[i].second; } int current = 0; long long int fuel = tank; int toAdd = 1; auto srt = [](int i, int j) { pair<int, int> a = make_pair(cost[i], d[i]); pair<int, int> b = make_pair(cost[j], d[j]); return a < b; }; multiset<int, function<bool(int, int)>> stations(srt); long long int ans = 0; while (true) { while (!stations.empty() && d[*stations.begin()] < d[current]) { stations.erase(stations.begin()); } while (toAdd <= m + 1 && (d[current] + tank) >= d[toAdd]) { stations.insert(toAdd); toAdd++; } auto it = stations.begin(); if (it == stations.end()) { cout << -1; return 0; } int minPricy = *it; if (cost[minPricy] >= cost[current]) { long long int fuelNeeded = d[minPricy] - d[current]; ans += max(0ll, (tank - fuel) * cost[current]); fuel = tank - fuelNeeded; current = minPricy; stations.erase(it); } else { int check = current + 1; while (cost[current] <= cost[check]) { check++; } int minPricy = check; long long int fuelNeeded = d[minPricy] - d[current]; ans += max(0ll, (fuelNeeded - fuel) * cost[current]); fuel = max(fuel - fuelNeeded, 0ll); current = minPricy; } if (current == m + 1) break; } cout << ans; return 0; }
|
module abc9_test001(input a, output o);
assign o = a;
endmodule
module abc9_test002(input [1:0] a, output o);
assign o = a[1];
endmodule
module abc9_test003(input [1:0] a, output [1:0] o);
assign o = a;
endmodule
module abc9_test004(input [1:0] a, output o);
assign o = ^a;
endmodule
module abc9_test005(input [1:0] a, output o, output p);
assign o = ^a;
assign p = ~o;
endmodule
module abc9_test006(input [1:0] a, output [2:0] o);
assign o[0] = ^a;
assign o[1] = ~o[0];
assign o[2] = o[1];
endmodule
module abc9_test007(input a, output o);
wire b, c;
assign c = ~a;
assign b = c;
abc9_test007_sub s(b, o);
endmodule
module abc9_test007_sub(input a, output b);
assign b = a;
endmodule
module abc9_test008(input a, output o);
wire b, c;
assign b = ~a;
assign c = b;
abc9_test008_sub s(b, o);
endmodule
module abc9_test008_sub(input a, output b);
assign b = ~a;
endmodule
module abc9_test009(inout io, input oe);
reg latch;
always @(io or oe)
if (!oe)
latch <= io;
assign io = oe ? ~latch : 1'bz;
endmodule
module abc9_test010(inout [7:0] io, input oe);
reg [7:0] latch;
always @(io or oe)
if (!oe)
latch <= io;
assign io = oe ? ~latch : 8'bz;
endmodule
module abc9_test011(inout io, input oe);
reg latch;
always @(io or oe)
if (!oe)
latch <= io;
//assign io = oe ? ~latch : 8'bz;
endmodule
module abc9_test012(inout io, input oe);
reg latch;
//always @(io or oe)
// if (!oe)
// latch <= io;
assign io = oe ? ~latch : 8'bz;
endmodule
module abc9_test013(inout [3:0] io, input oe);
reg [3:0] latch;
always @(io or oe)
if (!oe)
latch[3:0] <= io[3:0];
else
latch[7:4] <= io;
assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
endmodule
module abc9_test014(inout [7:0] io, input oe);
abc9_test012_sub sub(io, oe);
endmodule
module abc9_test012_sub(inout [7:0] io, input oe);
reg [7:0] latch;
always @(io or oe)
if (!oe)
latch[3:0] <= io;
else
latch[7:4] <= io;
assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
endmodule
module abc9_test015(input a, output b, input c);
assign b = ~a;
(* keep *) wire d;
assign d = ~c;
endmodule
module abc9_test016(input a, output b);
assign b = ~a;
(* keep *) reg c;
always @* c <= ~a;
endmodule
module abc9_test017(input a, output b);
assign b = ~a;
(* keep *) reg c;
always @* c = b;
endmodule
module abc9_test018(input a, output b, output c);
assign b = ~a;
(* keep *) wire [1:0] d;
assign c = &d;
endmodule
module abc9_test019(input a, output b);
assign b = ~a;
(* keep *) reg [1:0] c;
reg d;
always @* d <= &c;
endmodule
module abc9_test020(input a, output b);
assign b = ~a;
(* keep *) reg [1:0] c;
(* keep *) reg d;
always @* d <= &c;
endmodule
// Citation: https://github.com/alexforencich/verilog-ethernet
module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser);
input clk;
output [47:0] m_eth_dest_mac;
input m_eth_hdr_ready;
output m_eth_hdr_valid;
output [7:0] m_eth_payload_axis_tdata;
output [7:0] m_eth_payload_axis_tdest;
output [7:0] m_eth_payload_axis_tid;
output m_eth_payload_axis_tkeep;
output m_eth_payload_axis_tlast;
input m_eth_payload_axis_tready;
output m_eth_payload_axis_tuser;
output m_eth_payload_axis_tvalid;
output [47:0] m_eth_src_mac;
output [15:0] m_eth_type;
input rst;
input [191:0] s_eth_dest_mac;
output [3:0] s_eth_hdr_ready;
input [3:0] s_eth_hdr_valid;
input [31:0] s_eth_payload_axis_tdata;
input [31:0] s_eth_payload_axis_tdest;
input [31:0] s_eth_payload_axis_tid;
input [3:0] s_eth_payload_axis_tkeep;
input [3:0] s_eth_payload_axis_tlast;
output [3:0] s_eth_payload_axis_tready;
input [3:0] s_eth_payload_axis_tuser;
input [3:0] s_eth_payload_axis_tvalid;
input [191:0] s_eth_src_mac;
input [63:0] s_eth_type;
(* keep *)
wire [0:0] grant, request;
wire a;
not u0 (
a,
grant[0]
);
and u1 (
request[0],
s_eth_hdr_valid[0],
a
);
(* keep *)
MUXF8 u2 (
.I0(1'bx),
.I1(1'bx),
.O(o),
.S(1'bx)
);
arbiter arb_inst (
.acknowledge(acknowledge),
.clk(clk),
.grant(grant),
.grant_encoded(grant_encoded),
.grant_valid(grant_valid),
.request(request),
.rst(rst)
);
endmodule
module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encoded);
input [3:0] acknowledge;
input clk;
output [3:0] grant;
output [1:0] grant_encoded;
output grant_valid;
input [3:0] request;
input rst;
endmodule
(* abc9_box, blackbox *)
module MUXF8(input I0, I1, S, output O);
specify
(I0 => O) = 0;
(I1 => O) = 0;
(S => O) = 0;
endspecify
endmodule
// Citation: https://github.com/alexforencich/verilog-ethernet
module abc9_test022
(
input wire clk,
input wire i,
output wire [7:0] m_eth_payload_axis_tkeep
);
reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0;
assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
always @(posedge clk)
m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
endmodule
// Citation: https://github.com/riscv/riscv-bitmanip
module abc9_test023 #(
parameter integer N = 2,
parameter integer M = 2
) (
input [7:0] din,
output [M-1:0] dout
);
wire [2*M-1:0] mask = {M{1'b1}};
assign dout = (mask << din[N-1:0]) >> M;
endmodule
module abc9_test024(input [3:0] i, output [3:0] o);
abc9_test024_sub a(i[1:0], o[1:0]);
endmodule
module abc9_test024_sub(input [1:0] i, output [1:0] o);
assign o = i;
endmodule
module abc9_test025(input [3:0] i, output [3:0] o);
abc9_test024_sub a(i[2:1], o[2:1]);
endmodule
module abc9_test026(output [3:0] o, p);
assign o = { 1'b1, 1'bx };
assign p = { 1'b1, 1'bx, 1'b0 };
endmodule
module abc9_test030(input [3:0] d, input en, output reg [3:0] q);
always @*
if (en)
q <= d;
endmodule
module abc9_test031(input clk1, clk2, d, output reg q1, q2);
always @(posedge clk1) q1 <= d;
always @(negedge clk2) q2 <= q1;
endmodule
module abc9_test032(input clk, d, r, output reg q);
always @(posedge clk or posedge r)
if (r) q <= 1'b0;
else q <= d;
endmodule
module abc9_test033(input clk, d, r, output reg q);
always @(negedge clk or posedge r)
if (r) q <= 1'b1;
else q <= d;
endmodule
module abc9_test034(input clk, d, output reg q1, q2);
always @(posedge clk) q1 <= d;
always @(posedge clk) q2 <= q1;
endmodule
module abc9_test035(input clk, d, output reg [1:0] q);
always @(posedge clk) q[0] <= d;
always @(negedge clk) q[1] <= q[0];
endmodule
module abc9_test036(input A, B, S, output [1:0] O);
(* keep *)
MUXF8 m (
.I0(A),
.I1(B),
.O(O[0]),
.S(S)
);
MUXF8 m2 (
.I0(A),
.I1(B),
.O(O[1]),
.S(S)
);
endmodule
(* abc9_box, whitebox *)
module MUXF7(input I0, I1, S, output O);
assign O = S ? I1 : I0;
specify
(I0 => O) = 0;
(I1 => O) = 0;
(S => O) = 0;
endspecify
endmodule
module abc9_test037(output o);
MUXF7 m(.I0(1'b1), .I1(1'b0), .S(o), .O(o));
endmodule
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* FSM: finite state machine
* halt if $ctrl == 0$
*/
module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe, done);
input clk;
input reset;
output reg [8:0] rom_addr; /* command id. extra bits? */
input [28:0] rom_q; /* command value */
output reg [5:0] ram_a_addr;
output reg [5:0] ram_b_addr;
output ram_b_w;
output reg [10:0] pe;
output reg done;
reg [5:0] state;
parameter START=0, READ_SRC1=1, READ_SRC2=2, CALC=4, WAIT=8, WRITE=16, DON=32;
wire [5:0] dest, src1, src2; wire [8:0] times; wire [1:0] op;
assign {dest, src1, op, times, src2} = rom_q;
reg [8:0] count;
always @ (posedge clk)
if (reset)
state<=START;
else
case (state)
START:
state<=READ_SRC1;
READ_SRC1:
state<=READ_SRC2;
READ_SRC2:
if (times==0) state<=DON; else state<=CALC;
CALC:
if (count==1) state<=WAIT;
WAIT:
state<=WRITE;
WRITE:
state<=READ_SRC1;
endcase
/* we support two loops */
parameter LOOP1_START = 9'd21,
LOOP1_END = 9'd116,
LOOP2_START = 9'd288,
LOOP2_END = 9'd301;
reg [294:0] loop1, loop2;
always @ (posedge clk)
if (reset) rom_addr<=0;
else if (state==WAIT)
begin
if(rom_addr == LOOP1_END && loop1[0])
rom_addr <= LOOP1_START;
else if(rom_addr == LOOP2_END && loop2[0])
rom_addr <= LOOP2_START;
else
rom_addr <= rom_addr + 1'd1;
end
always @ (posedge clk)
if (reset) loop1 <= ~0;
else if(state==WAIT && rom_addr==LOOP1_END)
loop1 <= loop1 >> 1;
always @ (posedge clk)
if (reset) loop2 <= ~0;
else if(state==WAIT && rom_addr==LOOP2_END)
loop2 <= loop2 >> 1;
always @ (posedge clk)
if (reset)
count <= 0;
else if (state==READ_SRC1)
count <= times;
else if (state==CALC)
count <= count - 1'd1;
always @ (posedge clk)
if (reset) done<=0;
else if (state==DON) done<=1;
else done<=0;
always @ (state, src1, src2)
case (state)
READ_SRC1: ram_a_addr=src1;
READ_SRC2: ram_a_addr=src2;
default: ram_a_addr=0;
endcase
parameter CMD_ADD=6'd4, CMD_SUB=6'd8, CMD_CUBIC=6'd16,
ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
always @ (posedge clk)
case (state)
READ_SRC1:
case (op)
ADD: pe<=11'b11001000000;
SUB: pe<=11'b11001000000;
CUBIC: pe<=11'b11111000000;
MULT: pe<=11'b11110000000;
default: pe<=0;
endcase
READ_SRC2:
case (op)
ADD: pe<=11'b00110000000;
SUB: pe<=11'b00110000000;
CUBIC: pe<=0;
MULT: pe<=11'b00001000000;
default: pe<=0;
endcase
CALC:
case (op)
ADD: pe<=11'b00000010001;
SUB: pe<=11'b00000010001;
CUBIC: pe<=11'b01010000001;
MULT: pe<=11'b00000111111;
default: pe<=0;
endcase
default:
pe<=0;
endcase
always @ (state, op, src2, dest)
case (state)
READ_SRC1:
case (op)
ADD: ram_b_addr=CMD_ADD;
SUB: ram_b_addr=CMD_SUB;
CUBIC: ram_b_addr=CMD_CUBIC;
default: ram_b_addr=0;
endcase
READ_SRC2: ram_b_addr=src2;
WRITE: ram_b_addr=dest;
default: ram_b_addr=0;
endcase
assign ram_b_w = (state==WRITE) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline char get(void) { static char buf[100000], *S = buf, *T = buf; if (S == T) { T = (S = buf) + fread(buf, 1, 100000, stdin); if (T == S) return EOF; } return *S++; } inline void read(int& x) { static char c; x = 0; for (c = get(); c < 0 || c > 9 ; c = get()) ; for (; c >= 0 && c <= 9 ; c = get()) x = x * 10 + c - 0 ; } const int M = 500 * 1000 + 10; const int up = 300000 + 10; const int mod = 998244353; int n; int cnt[M] = {0}; bool vs[M] = {0}; int dp[M] = {0}; int fac[100]; int tp; int num[100]; int C[8][M] = {0}; void init() { C[0][0] = 1; for (int i = 1; i < up; ++i) { C[0][i] = 1; for (int j = 1; j < 8; ++j) C[j][i] = (C[j - 1][i - 1] + C[j][i - 1]) % mod; } } void dfs(int c, int al) { if (c == tp) { ++cnt[al]; return; } for (int i = 0; i < num[c] + 1; ++i) { dfs(c + 1, al); al *= fac[c]; } } void add(int a) { tp = 0; for (int i = 2; i * i <= a; ++i) { if (0 == a % i) { fac[tp] = i; num[tp] = 0; while (a % i == 0) ++num[tp], a /= i; ++tp; } } if (1 != a) { fac[tp] = a; num[tp++] = 1; } dfs(0, 1); } bool solve(int x) { for (int t = up; t; --t) { dp[t] = C[x][cnt[t]]; for (int i = 2; i * t < up; ++i) dp[t] = (dp[t] - dp[i * t] + mod) % mod; } return dp[1] > 0; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); init(); cin >> n; int a; for (int i = 0; i < n; ++i) { cin >> a; if (vs[a]) continue; vs[a] = 1; add(a); } bool fg = 1; if (vs[1]) { fg = 0; cout << 1 << endl; } for (int i = 2; i < 8; ++i) { if (!fg) break; if (solve(i)) { fg = 0; cout << i << endl; break; } } if (fg) cout << -1 << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_SYMBOL_V
`define SKY130_FD_SC_HS__EDFXTP_SYMBOL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__edfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_SYMBOL_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_src_data_stream_1_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_src_data_stream_1_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_src_data_stream_1_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_src_data_stream_1_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:33:57 03/02/2016
// Design Name: alu
// Module Name: G:/ceshi/lab3.3/test_for_alu.v
// Project Name: lab3.3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_alu;
// Inputs
reg [31:0] input1;
reg [31:0] input2;
reg [3:0] aluCtr;
// Outputs
wire zero;
wire [31:0] aluRes;
// Instantiate the Unit Under Test (UUT)
alu uut (
.zero(zero),
.aluRes(aluRes),
.input1(input1),
.input2(input2),
.aluCtr(aluCtr)
);
initial begin
// Initialize Inputs
input1 = 0;
input2 = 0;
aluCtr = 0;
// Wait 100 ns for global reset to finish
#100;
#100 input1 = 0; input2 = 0; aluCtr = 4'b0000;
#100 input1 = 0; input2 = 0; aluCtr = 4'b0000;
#100 input1 = 255; input2 = 170; aluCtr = 4'b0000;
#100 input1 = 255; input2 = 170; aluCtr = 4'b0001;
#100 input1 = 1; input2 = 1; aluCtr = 4'b0010;
#100 input1 = 255; input2 = 170; aluCtr = 4'b0110;
#100 input1 = 1; input2 = 1; aluCtr = 4'b0110;
#100 input1 = 255; input2 = 170; aluCtr = 4'b0111;
#100 input1 = 170; input2 = 255; aluCtr = 4'b0111;
#100 input1 = 0; input2 = 1; aluCtr = 4'b1100;
//Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int a1, a2; cin >> a1 >> a2; int res = 0; while (a1 && a2 && (a1 > 1 || a2 > 1)) { if (a1 > a2) swap(a1, a2); ++a1; a2 -= 2; ++res; } cout << res << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_4_V
`define SKY130_FD_SC_HDLL__NOR2B_4_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2b_4 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2b_4 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_4_V
|
`include "bsg_defines.v"
module bsg_fsb_to_htif_connector
import bsg_fsb_pkg::RingPacketType;
#(parameter htif_width_p
,parameter fsb_width_p=$size(RingPacketType)
,parameter `BSG_INV_PARAM(destid_p)
)
(input clk_i
,input reset_i
,input fsb_v_i
,input [fsb_width_p-1:0] fsb_data_i
,output fsb_ready_o
,output fsb_v_o
,output [fsb_width_p-1:0] fsb_data_o
,input fsb_yumi_i
// FROM htif
,input htif_v_i
,input [htif_width_p-1:0] htif_data_i
,output htif_ready_o
// TO htif
,output htif_v_o
,output [htif_width_p-1:0] htif_data_o
,input htif_ready_i
);
RingPacketType pkt_in = fsb_data_i;
RingPacketType pkt_out;
assign fsb_data_o = pkt_out;
assign htif_v_o = fsb_v_i;
// toss the rest
assign htif_data_o = pkt_in.data[htif_width_p-1:0];
assign fsb_ready_o = htif_ready_i;
bsg_two_fifo #(.width_p(htif_width_lp)
)
(.clk_i (clk_i )
,.reset_i (reset_i)
,.v_i ( htif_v_i )
,.data_i ( htif_data_i )
,.ready_o ( htif_ready_o )
,.v_o ( fsb_v_o )
,.data_o ( pkt_out.data[htif_width_p-1:0] )
,.yumi_i ( fsb_yumi_i )
);
assign pkt_out.srcid = 4'b0; // fixme
assign pkt_out.destid = destid_p;
assign pkt_out.cmd = 1'b0;
assign pkt_out.opcode = 7'b0;
assign pkt_out.data[63:htif_width_p] = '0;
endmodule
`BSG_ABSTRACT_MODULE(bsg_fsb_to_htif_connector)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__SDFSBP_FUNCTIONAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSBP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; set<int> b[127]; set<int>::iterator it, itt; int n, m, l, r, c[200005]; char s, ch[2], a[200005]; void upd(int v, int d) { while (v <= n) { c[v] += d; v += v & -v; } } int find(int x) { int cur = 0, ans = 0; for (int i = 20; i >= 0; i--) { ans += (1 << i); if (ans >= n || cur + c[ans] >= x) ans -= (1 << i); else cur += c[ans]; } return ans + 1; } int gsum(int v) { int sum = 0; while (v > 0) { sum += c[v]; v -= v & -v; } return sum; } int main() { scanf( %d%d , &n, &m); scanf( %s , a + 1); for (int i = 1; i <= n; i++) b[a[i]].insert(i); for (int i = 1; i <= n; i++) upd(i, 1); for (int i = 0; i < m; i++) { scanf( %d%d%s , &l, &r, ch); s = ch[0]; l = find(l); r = find(r); it = b[s].lower_bound(l); while (it != b[s].end() && *it <= r) upd(*it, -1), a[*it] = # , itt = it, it++, b[s].erase(itt); } for (int i = 1; i <= n; i++) if (gsum(i) - gsum(i - 1) == 1) printf( %c , a[i]); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[3]; for (int i = 0; i < 3; i++) cin >> a[i]; sort(a, a + 3); cout << a[2] - a[0]; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111A_4_V
`define SKY130_FD_SC_LS__O2111A_4_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111a_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111a_4 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111A_4_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
(* X_CORE_INFO = "xlconcat,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlconcat_1_0,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlconcat_1_0,xlconcat,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=7,IN1_WIDTH=16,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_W\
IDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=24,NUM_PORTS=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconcat_1_0 (
In0,
In1,
In2,
dout
);
input wire [6 : 0] In0;
input wire [15 : 0] In1;
input wire [0 : 0] In2;
output wire [23 : 0] dout;
xlconcat #(
.IN0_WIDTH(7),
.IN1_WIDTH(16),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(24),
.NUM_PORTS(3)
) inst (
.In0(In0),
.In1(In1),
.In2(In2),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void printPath(vector<pair<int, int>> &path) { for (auto it : path) cout << (it.first + 1) << << (it.second + 1) << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; long long arr[n][n]; memset(arr, 0, sizeof(arr)); pair<long long, long long> achieve[n][n]; arr[0][0] = 0; achieve[0][0] = {0, 0}; for (int k = 1; k < 2 * (n - 1); k++) { long long prev = 0; for (int i = 0; i < n; i++) { int j = k - i; if (j < 0 || j >= n) continue; pair<long long, long long> available = {2000000000000000000, -1}; if (i) { available.first = (available.first < achieve[i - 1][j].first ? available.first : achieve[i - 1][j].first); available.second = (available.second > achieve[i - 1][j].second ? available.second : achieve[i - 1][j].second); } if (j) { available.first = (available.first < achieve[i][j - 1].first ? available.first : achieve[i][j - 1].first); available.second = (available.second > achieve[i][j - 1].second ? available.second : achieve[i][j - 1].second); } long long diff = prev - available.first; arr[i][j] = diff; available.first += diff; available.second += diff; achieve[i][j] = available; prev = available.second + 1; } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) cout << arr[i][j] << ; cout << endl; } int q; cin >> q; vector<pair<int, int>> path; while (q--) { long long x; cin >> x; int i = n - 1, j = n - 1; while (i || j) { x -= arr[i][j]; path.push_back({i, j}); if (i == 0) { j--; continue; } if (j == 0) { i--; continue; } if (achieve[i - 1][j].first <= x && x <= achieve[i - 1][j].second) i--; else j--; } path.push_back({i, j}); reverse(path.begin(), path.end()); printPath(path); path.clear(); } }
|
#include <bits/stdc++.h> using namespace std; int n, k, m, ax, ay, cx, cy; int d[100][100], s[100][100]; void take(int ax, int ay, int m) { for (int y = ay; y < ay + m; ++y) { for (int i = y; i <= k; ++i) ++s[ax][i]; } } int main() { while (scanf( %d%d , &n, &k) != EOF) { cx = cy = (k + 1) / 2; memset(s, 0, sizeof(s)); for (int x = 1; x <= k; ++x) for (int y = 1; y <= k; ++y) d[x][y] = d[x][y - 1] + abs(x - cx) + abs(y - cy); for (int i = 0; i < n; ++i) { scanf( %d , &m); int ax = -1, ay = -1, mini = 1000000000; for (int x = 1; x <= k; ++x) { for (int y = 1; y + m - 1 <= k; ++y) { if (s[x][y + m - 1] - s[x][y - 1] == 0) { if (d[x][y + m - 1] - d[x][y - 1] < mini) { ax = x, ay = y; mini = d[x][y + m - 1] - d[x][y - 1]; } } } } if (ax == -1) { puts( -1 ); } else { take(ax, ay, m); printf( %d %d %d n , ax, ay, ay + m - 1); } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int i, j; int main() { int n, s, d, flag, last; cin >> n; cin >> s >> d; flag = s; n--; while (n--) { cin >> s >> d; while (flag >= s) s += d; flag = s; } cout << flag; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_1_V
`define SKY130_FD_SC_LP__DFXTP_1_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_1 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxtp_1 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFRBP_PP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; bool bo[1005][1005]; double ans[1005][1005]; double f(int n, int m) { if (m == 0) return 1; if (bo[n][m]) return ans[n][m]; if (n == 0) { return 1.0 / (m + 1); } double a = 1.0, b = 1 - f(m, n - 1); double c = 1.0 * m / (m + 1) * (1 - f(m - 1, n)), d = 1.0 / (m + 1) + c; double p = (d - c) / (a - c + d - b); bo[n][m] = true; return ans[n][m] = p * a + (1 - p) * c; } int main() { int n, m; scanf( %d%d , &n, &m); double x = f(n, m); printf( %.10f %.10f , x, 1 - x); }
|
/***************************************************************************************************
** fpga_nes/hw/src/vram.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Video RAM module; implements 2KB of on-board VRAM as fpga block RAM.
***************************************************************************************************/
module vram(
input clk_in, // system clock
input en_in, // chip enable
input r_nw_in, // read/write select (read: 0, write: 1)
input [10:0] a_in, // memory address
input [ 7:0] d_in, // data input
output [ 7:0] d_out // data output
);
wire vram_bram_we;
wire [7:0] vram_bram_dout;
single_port_ram_sync #(.ADDR_WIDTH(11),
.DATA_WIDTH(8)) vram_bram(
.clk(clk_in),
.we(vram_bram_we),
.addr_a(a_in),
.din_a(d_in),
.dout_a(vram_bram_dout)
);
assign vram_bram_we = (en_in) ? ~r_nw_in : 1'b0;
assign d_out = (en_in) ? vram_bram_dout : 8'h00;
endmodule
|
`timescale 1ns/10ps
module LedBankSim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [7:0] leds;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`LedBank_LDI,8'b00101100};
inst_en = 1;
#4 inst = {`LedBank_LD0,7'bxxxxxxx,1'b1};
inst_en = 1;
#4 inst = {`LedBank_LD1,7'bxxxxxxx,1'b1};
inst_en = 1;
#4 inst = {`LedBank_LD2,7'bxxxxxxx,1'b0};
inst_en = 1;
#4 inst = {`LedBank_LD3,7'bxxxxxxx,1'b0};
inst_en = 1;
#4 inst = {`LedBank_LD4,7'bxxxxxxx,1'b1};
inst_en = 1;
#4 inst = {`LedBank_LD5,7'bxxxxxxx,1'b0};
inst_en = 1;
#4 inst = {`LedBank_LD6,7'bxxxxxxx,1'b1};
inst_en = 1;
#4 inst = {`LedBank_LD7,7'bxxxxxxx,1'b1};
inst_en = 1;
#4 inst = {`LedBank_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`LedBank_LDI,8'b11001100};
inst_en = 0;
#4 inst = {`LedBank_LD1,7'bxxxxxxx,1'b0};
inst_en = 1;
// Test badinstruction.
#4 inst = {8'hF,8'h10};
inst_en = 1;
#4 inst = {`LedBank_LDI,8'b11010101};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`LedBank_LDI,8'b10100101};
inst_en = 1;
#4 inst = {`LedBank_NOP,8'bxxxxxxxx};
inst_en = 1;
end
LedBank
ledbank (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.leds(leds));
endmodule // SeqSim
|
`timescale 1ns/1ns
module udp_inbound_chain_writer
(input clk_100,
input [7:0] outbox_txd,
input outbox_txdv,
input outbox_txe, // end of TX burst to outbox. send the message.
// below here happens at 50 MHz, on the ethernet clock domain
input clk_50,
input [7:0] rxd,
input rxdv,
input rxe,
input is_chain,
input [7:0] hop_downcount,
input in_unused_block,
output phy_txen,
output [1:0] phy_txd);
// dfifo holds the messages we have that are waiting to be sent
wire [4:0] sfifo_wrusedw;
wire outbox_full;
r outbox_full_r
(.c(clk_100), .rst(~outbox_txdv & ~outbox_txe & sfifo_wrusedw < 5'h2),
.en(outbox_txe & sfifo_wrusedw >= 5'h2), .d(1'b1), .q(outbox_full));
wire dfifo_rdreq, dfifo_rdempty;
wire [8:0] dfifo_q;
dcfifo #(.lpm_width(9),
.lpm_numwords(4096),
.lpm_widthu(12),
.lpm_showahead("ON"),
.use_eab("ON"),
.intended_device_family("CYCLONE V")) dfifo // data fifo
(.wrclk(clk_100), .wrreq(~outbox_full & outbox_txdv),
.data({outbox_txe, outbox_txd}),
.rdclk(clk_50), .rdreq(dfifo_rdreq), .q(dfifo_q),
.rdempty(dfifo_rdempty), .aclr(1'b0));
// sfifo holds the sizes of the packets waiting in the dfifo
wire outbox_txe_d1;
d1 outbox_txe_d1_r(.c(clk_100), .d(outbox_txe), .q(outbox_txe_d1));
wire [15:0] sfifo_q, sfifo_d;
wire sfifo_rdreq, sfifo_rdempty;
r #(16) sfifo_d_r
(.c(clk_100), .rst(outbox_txe_d1), .en(outbox_txdv),
.d(sfifo_d+1'b1), .q(sfifo_d));
dcfifo #(.lpm_width(16),
.lpm_numwords(30),
.lpm_widthu(5),
.lpm_showahead("ON"),
.use_eab("ON"),
.intended_device_family("CYCLONE V")) sfifo
(.wrclk(clk_100), .wrreq(~outbox_full & outbox_txe), .data(sfifo_d+1'b1),
.wrusedw(sfifo_wrusedw),
.rdclk(clk_50), .rdreq(sfifo_rdreq), .q(sfifo_q),
.rdempty(sfifo_rdempty), .aclr(1'b0));
////////////////////////////////////////////////////////////////
// everything below here is in the clk50 (ethernet) domain
localparam SW = 4, CW = 4;
localparam ST_IDLE = 4'h0;
localparam ST_PREAMBLE = 4'h1;
localparam ST_DRIVETHRU = 4'h2;
localparam ST_WAIT_FOR_HOP_COUNT = 4'h3;
localparam ST_HOP_COUNT = 4'h4;
localparam ST_WAIT_FOR_UNUSED = 4'h5;
localparam ST_TX_MSG_SENDER_LO = 4'h6;
localparam ST_TX_MSG_SENDER_HI = 4'h7;
localparam ST_TX_MSG_LEN_LO = 4'h8;
localparam ST_TX_MSG_LEN_HI = 4'h9;
localparam ST_TX_MSG_PAYLOAD = 4'ha;
localparam ST_FLUSH = 4'hb;
localparam ST_WAIT_RXE = 4'hc;
localparam ST_LAST_4_BYTES = 4'hd;
localparam ST_FCS = 4'he;
localparam ST_DONE = 4'hf;
wire [23:0] eth_rxdv_cnt;
r #(24) eth_rxdv_cnt_r
(.c(clk_50), .en(1'b1), .rst(rxdv),
.d(eth_rxdv_cnt+1'b1), .q(eth_rxdv_cnt));
wire idle_reset = eth_rxdv_cnt == 24'hff_ffff; // sanity check state machine
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(clk_50), .rst(idle_reset), .en(1'b1), .d(next_state), .q(state));
wire idle = state == ST_IDLE;
wire [15:0] tx_dibit_cnt;
r #(16) tx_dibit_cnt_r
(.c(clk_50), .en(1'b1), .rst(ctrl[0]),
.d(tx_dibit_cnt+1'b1), .q(tx_dibit_cnt));
wire txdv = (~idle & tx_dibit_cnt[1:0] == 2'h0);
//wire rxd_shift_en = rxdv | txdv;
localparam DELAY_BYTES = 8;
wire [8*DELAY_BYTES-1:0] rxd_shift;
r #(8*DELAY_BYTES, 64'h5555_5555_5555_55d5) rxd_shift_r
(.c(clk_50), .rst(idle & ~rxdv), .en(rxdv),
.d({rxd_shift[8*(DELAY_BYTES-1)-1:0], rxd}),
.q(rxd_shift));
wire [7:0] rxd_d8 = rxd_shift[8*DELAY_BYTES-1:8*(DELAY_BYTES-1)];
wire [7:0] cnt;
r #(8) cnt_r(.c(clk_50), .rst(ctrl[1]), .en(1'b1), .d(cnt+1'b1), .q(cnt));
wire [5:0] in_unused_block_shift;
r #(6) in_unused_block_shift_r
(.c(clk_50), .rst(idle), .en(rxdv),
.d({in_unused_block_shift[4:0], in_unused_block}),
.q(in_unused_block_shift));
always @* begin
case (state)
ST_IDLE:
if (rxdv) ctrl = { ST_PREAMBLE , 4'b0000 };
else ctrl = { ST_IDLE , 4'b0001 };
ST_PREAMBLE:
if (tx_dibit_cnt == 16'd31) ctrl = { ST_DRIVETHRU , 4'b0000 };
else ctrl = { ST_PREAMBLE , 4'b0000 };
ST_DRIVETHRU:
if (is_chain) ctrl = { ST_WAIT_FOR_HOP_COUNT, 4'b0000 };
else if (rxe) ctrl = { ST_DONE , 4'b0000 };
else ctrl = { ST_DRIVETHRU , 4'b0000 };
ST_WAIT_FOR_HOP_COUNT:
if (tx_dibit_cnt == 16'hcc) ctrl = { ST_HOP_COUNT , 4'b0000 };
else ctrl = { ST_WAIT_FOR_HOP_COUNT, 4'b0000 };
ST_HOP_COUNT:
if (tx_dibit_cnt == 16'hd0) ctrl = { ST_WAIT_FOR_UNUSED , 4'b0000 };
else ctrl = { ST_HOP_COUNT , 4'b0000 };
ST_WAIT_FOR_UNUSED:
if (in_unused_block_shift[5])
if (sfifo_rdempty) ctrl = { ST_WAIT_RXE , 4'b0000 };
else ctrl = { ST_TX_MSG_SENDER_LO , 4'b0000 };
else ctrl = { ST_WAIT_FOR_UNUSED , 4'b0000 };
ST_TX_MSG_SENDER_LO:
if (txdv) ctrl = { ST_TX_MSG_SENDER_HI , 4'b0000 };
else ctrl = { ST_TX_MSG_SENDER_LO , 4'b0000 };
ST_TX_MSG_SENDER_HI:
if (txdv) ctrl = { ST_TX_MSG_LEN_LO , 4'b0000 };
else ctrl = { ST_TX_MSG_SENDER_HI , 4'b0000 };
ST_TX_MSG_LEN_LO:
if (txdv) ctrl = { ST_TX_MSG_LEN_HI , 4'b0000 };
else ctrl = { ST_TX_MSG_LEN_LO , 4'b0000 };
ST_TX_MSG_LEN_HI:
if (txdv) ctrl = { ST_TX_MSG_PAYLOAD , 4'b0100 };
else ctrl = { ST_TX_MSG_LEN_HI , 4'b0000 };
ST_TX_MSG_PAYLOAD:
if (txdv)
if (dfifo_q[8])
if (sfifo_rdempty) ctrl = { ST_WAIT_RXE , 4'b1000 };
else ctrl = { ST_TX_MSG_SENDER_LO , 4'b1000 };
else ctrl = { ST_TX_MSG_PAYLOAD , 4'b1000 };
else ctrl = { ST_TX_MSG_PAYLOAD , 4'b0000 };
ST_WAIT_RXE:
if (rxe) ctrl = { ST_LAST_4_BYTES , 4'b0010 };
else ctrl = { ST_WAIT_RXE , 4'b0000 };
ST_LAST_4_BYTES:
if (cnt == 16'hf) ctrl = { ST_FCS , 4'b0010 };
else ctrl = { ST_LAST_4_BYTES , 4'b0000 };
ST_FCS:
if (cnt == 16'h12) ctrl = { ST_IDLE , 4'b0000 };
else ctrl = { ST_FCS , 4'b0000 };
default: ctrl = { ST_IDLE , 4'b0000 };
endcase
end
assign sfifo_rdreq = ctrl[2];
assign dfifo_rdreq = ctrl[3];
reg [7:0] tx_dibit_shift_d;
wire fcs_dv = txdv & state > ST_PREAMBLE & state != ST_FCS;
wire [31:0] fcs_live;
eth_crc32 fcs_inst
(.c(clk_50), .r(idle), .dv(fcs_dv), .d(tx_dibit_shift_d), .crc(fcs_live));
wire [31:0] fcs;
r #(32) fcs_r
(.c(clk_50), .rst(idle),
.en(txdv),
.d(state == ST_FCS ? { fcs[23:0], 8'h0 } : fcs_live), .q(fcs));
always @* begin
case (state)
ST_HOP_COUNT: tx_dibit_shift_d = hop_downcount;
ST_TX_MSG_SENDER_LO: tx_dibit_shift_d = hop_downcount;
ST_TX_MSG_SENDER_HI: tx_dibit_shift_d = 8'h0;
ST_TX_MSG_LEN_LO: tx_dibit_shift_d = sfifo_q[7:0];
ST_TX_MSG_LEN_HI: tx_dibit_shift_d = sfifo_q[15:8];
ST_TX_MSG_PAYLOAD: tx_dibit_shift_d = dfifo_q[7:0];
ST_FCS: tx_dibit_shift_d = fcs[31:24];
default: tx_dibit_shift_d = rxd_d8;
endcase
end
wire phy_txen_posedge = ~idle;
/*
wire [7:0] tx_dibit_shift_d = state == ST_HOP_COUNT ? hop_downcount :
rxd_d8;
*/
wire [7:0] tx_dibit_shift;
r #(8) tx_dibit_shift_r
(.c(clk_50), .rst(1'b0), .en(1'b1),
.d(idle | txdv ? tx_dibit_shift_d : { 2'h0, tx_dibit_shift[7:2] }),
.q(tx_dibit_shift));
wire [1:0] phy_txd_posedge = tx_dibit_shift[1:0];
r #(3) phy_negedge_r
(.c(clk_50), .rst(1'b0), .en(1'b1),
.d({phy_txen_posedge, phy_txd_posedge}),
.q({phy_txen, phy_txd}));
/*
r #(3) phy_negedge_r
(.c(~clk_50), .rst(1'b0), .en(1'b1),
.d({phy_txen_posedge, phy_txd_posedge}),
.q({phy_txen, phy_txd}));
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10, mod = 1e9 + 7, INF = 0x3f3f3f3f; int main() { int T; cin >> T; while (T--) { int n, k; cin >> n >> k; int mn = INF, mx = -1; for (int i = 1; i <= n; ++i) { int x; scanf( %d , &x); mn = min(mn, x); mx = max(mx, x); } int m = (mx + mn) >> 1; printf( %d n , max(m - mn, mx - m) <= k ? mn + k : -1); } return 0; }
|
#include <bits/stdc++.h> int main() { int n, k, i; scanf( %d%d , &n, &k); while (n > k) { for (i = 1; i <= k; i++) { if (n % 10 > 0) n--; else n = n / 10; } printf( %d , n); n = 0; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXTP_1_V
`define SKY130_FD_SC_MS__SDFXTP_1_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXTP_1_V
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long a, b; cin >> a >> b; long long c = 1, i = 0; while (1) { if (i % 2 == 0 && a >= c) a -= c; else if (i & 1 && b >= c) b -= c; else break; c++; i++; } if (i & 1) cout << Valera n ; else cout << Vladik n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:45:22 07/05/2015
// Design Name:
// Module Name: Cache_Control
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Cache_Control(
input [29:0] CPU_Address_in,
input [3:0] CPU_Write_Data_in,
input CPU_Read_in,
output CPU_Ready_out,
input CPU_Flush_in,
output CPU_Flush_out,
output [29:0] MEM_Address_out,
output MEM_Write_Data_out,
output MEM_Read_out,
input MEM_Ready_in,
output [3:0] Index_out,
output [6:0] Offset_out,
output [3:0] Write_Data_out,
input Dirty_in,
output Dirty_out,
output Write_Dirty_out,
input Init_Dirty_in,
input [18:0] Tag_in,
output Write_Valid_Tag_out,
output Valid_out,
input Init_Valid_in,
input Hit_in,
input [7:0] Counter_in,
output Reset_Counter_out,
output Counter_Enable_out,
input [7:0] Flush_Count_in,
output Flush_Reset_Counter_out,
output Flush_Counter_Enable_out,
input Clock_in,
input Reset_in,
output Reset_Valid_Dirty_out,
output Fill_out
);
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// State Encoding
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
parameter STATE_CACHE_INIT = 4'b0000;
parameter STATE_CACHE_IDLE = 4'b0001;
parameter STATE_CACHE_REQUEST_ACK = 4'b0010;
parameter STATE_CACHE_ALLOCATE = 4'b0011;
parameter STATE_CACHE_ALLOCATE_ACK = 4'b0100;
parameter STATE_CACHE_WRITEBACK = 4'b0101;
parameter STATE_CACHE_WRITEBACK_ACK = 4'b0110;
parameter STATE_CACHE_FLUSH = 4'b1000;
parameter STATE_CACHE_FLUSH_ACK = 4'b1010;
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// State reg Declarations
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
reg [3:0] CurrentState ;
reg [3:0] NextState ;
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// Internal Signals
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
//wire Reset_FSM;
wire CPU_Request;
wire [14:0] Tag;
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// Outputs
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// Continuous Assignments
assign CPU_Request = CPU_Read_in || (|CPU_Write_Data_in) || CPU_Flush_in ;
//assign Reset_FSM = (CurrentState == STATE_CACHE_REQUEST_ACK && (~CPU_Request));
assign Tag = (CurrentState == STATE_CACHE_WRITEBACK || CurrentState == STATE_CACHE_WRITEBACK_ACK) ?
Tag_in : CPU_Address_in[29:11];
// State Outputs
//CPU Interface
assign CPU_Ready_out = Hit_in/*(CurrentState == STATE_CACHE_REQUEST_ACK) ? 1'b1 : 1'b0*/;
assign CPU_Flush_out = (CurrentState == STATE_CACHE_FLUSH_ACK) ? 1'b1 : 1'b0;
//MEM Interface
assign MEM_Address_out = {Tag, Index_out, 7'h0};
assign MEM_Write_Data_out = (CurrentState == STATE_CACHE_WRITEBACK) ? 1'b1 : 1'b0;
assign MEM_Read_out = (CurrentState == STATE_CACHE_ALLOCATE) ? 1'b1 : 1'b0;
assign Fill_out = (CurrentState == STATE_CACHE_ALLOCATE && MEM_Ready_in);
//Data RAM Interface
assign Index_out = ((CurrentState == STATE_CACHE_FLUSH) || ((CurrentState == STATE_CACHE_WRITEBACK || CurrentState == STATE_CACHE_WRITEBACK_ACK) &&
CPU_Flush_in)) ? Flush_Count_in : CPU_Address_in[10:7];
assign Offset_out = /*(CurrentState == STATE_CACHE_WRITEBACK || CurrentState == STATE_CACHE_WRITEBACK_ACK ||
CurrentState == STATE_CACHE_ALLOCATE || CurrentState == STATE_CACHE_ALLOCATE_ACK) ?
Counter_in : */CPU_Address_in[6:0];
assign Write_Data_out = (CurrentState == STATE_CACHE_IDLE && Hit_in) ? CPU_Write_Data_in : /*(CurrentState == STATE_CACHE_ALLOCATE && MEM_Ready_in) ?
4'b1111 :*/ 4'b0000;
//Dirty RAM Interface
assign Dirty_out = (CurrentState == STATE_CACHE_IDLE && (|CPU_Write_Data_in)) ? 1'b1 : 1'b0;
assign Write_Dirty_out = ((CurrentState == STATE_CACHE_IDLE && (|CPU_Write_Data_in) && Hit_in) || (CurrentState == STATE_CACHE_ALLOCATE_ACK &&
/*Counter_in == 8'b00001111 &&*/ ~MEM_Ready_in)) ? 1'b1 : 1'b0;
//Valid RAM Interface
assign Valid_out = (CurrentState == STATE_CACHE_ALLOCATE_ACK && /*Counter_in == 8'b00001111 &&*/ ~MEM_Ready_in) ? 1'b1 : 1'b0;
assign Write_Valid_Tag_out = (CurrentState == STATE_CACHE_ALLOCATE_ACK && /*Counter_in == 8'b00001111 &&*/ ~MEM_Ready_in) ? 1'b1 : 1'b0;
//Counter Interface
assign Reset_Counter_out = (Reset_in || CurrentState == STATE_CACHE_IDLE) ? 1'b1 : 1'b0;
assign Counter_Enable_out = (CurrentState == STATE_CACHE_INIT) ? 1'b1 : 1'b0;
//Flush Counter Interface
assign Flush_Reset_Counter_out = (CurrentState == STATE_CACHE_INIT) ? 1'b1 : 1'b0;
assign Flush_Counter_Enable_out = ((CPU_Flush_in && CurrentState == STATE_CACHE_WRITEBACK_ACK && /*Counter_in == 8'b00001111 &&*/ ~MEM_Ready_in) ||
(CurrentState == STATE_CACHE_FLUSH && ~Dirty_in)) ? 1'b1 : 1'b0;
assign Reset_Valid_Dirty_out = (CurrentState == STATE_CACHE_FLUSH_ACK) ? 1'b1: 1'b0;
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// Synchronous State - Transition always@ ( posedge Clock ) block
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
//Allow for asynchronous acknowledgement to the CPU.
always@ ( posedge Clock_in /*or posedge Reset_FSM*/) begin
// if (Reset_FSM) begin
// CurrentState = STATE_CACHE_IDLE;
// end
// else begin
CurrentState = NextState;
// end
end
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
// Conditional State - Transition always@ ( * ) block
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
always@ ( CurrentState, CPU_Request, MEM_Ready_in, Hit_in, Dirty_in,
Counter_in, Init_Valid_in, Init_Dirty_in, CPU_Flush_in,
Flush_Count_in, Reset_in) begin
NextState = CurrentState ;
case ( CurrentState )
STATE_CACHE_INIT : begin
NextState = (~Init_Valid_in && ~Init_Dirty_in) ? STATE_CACHE_IDLE : STATE_CACHE_INIT;
end
STATE_CACHE_IDLE : begin //Request
NextState = (Reset_in) ? STATE_CACHE_INIT : (CPU_Request) ? (CPU_Flush_in) ? STATE_CACHE_FLUSH : (Hit_in) ? CurrentState /*STATE_CACHE_REQUEST_ACK*/ : (Dirty_in) ?
STATE_CACHE_WRITEBACK : STATE_CACHE_ALLOCATE : CurrentState;
end
STATE_CACHE_REQUEST_ACK : begin
NextState = (Reset_in) ? STATE_CACHE_INIT : CurrentState;
end
STATE_CACHE_ALLOCATE : begin
NextState = (Reset_in) ? STATE_CACHE_INIT : ( MEM_Ready_in ) ? STATE_CACHE_ALLOCATE_ACK : CurrentState;
end
STATE_CACHE_ALLOCATE_ACK : begin
NextState = (Reset_in) ? STATE_CACHE_INIT : ( ~MEM_Ready_in ) ? /*( Counter_in == 8'b00001111) ?*/ STATE_CACHE_IDLE :
/*STATE_CACHE_ALLOCATE :*/ CurrentState;
end
STATE_CACHE_WRITEBACK : begin
NextState = (Reset_in) ? STATE_CACHE_INIT : ( MEM_Ready_in ) ? STATE_CACHE_WRITEBACK_ACK : CurrentState;
end
STATE_CACHE_WRITEBACK_ACK : begin
NextState = (Reset_in) ? STATE_CACHE_INIT : ( ~MEM_Ready_in ) ? /*( Counter_in == 8'b00001111 ) ?*/ (CPU_Flush_in) ?
STATE_CACHE_FLUSH : STATE_CACHE_ALLOCATE : /*STATE_CACHE_WRITEBACK :*/ CurrentState;
end
STATE_CACHE_FLUSH : begin
NextState = (Reset_in) ? STATE_CACHE_INIT : ( Flush_Count_in == 8'b00010000 ) ? STATE_CACHE_FLUSH_ACK : ( Dirty_in ) ?
STATE_CACHE_WRITEBACK : CurrentState ;
end
STATE_CACHE_FLUSH_ACK : begin
NextState = (Reset_in) ? STATE_CACHE_INIT : ( ~CPU_Flush_in ) ? STATE_CACHE_INIT : CurrentState;
end
default : begin
NextState = (Reset_in) ? STATE_CACHE_INIT : STATE_CACHE_IDLE;
end
endcase
end
// --- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- ----- ---- ---- -----
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int SIZE = 1e6 + 10; char A[SIZE]; long long d[SIZE]; int len; vector<long long> D; long long dp[2][4000][2][2]; void ADD(long long &x, long long v) { x = (x + v) % MOD; } long long CC(long long x) { return x * (x - 1) / 2 % MOD; } long long con(long long x, long long y) { if (x > y) return 0; return (x + y) * (y - x + 1) / 2 % MOD; } int main() { int p, a; scanf( %d%d , &p, &a); scanf( %s , (A)); len = strlen(A); for (int i = 0; i < (len); ++i) { d[len - 1 - i] = A[i] - 0 ; } int top = len - 1; while (top >= 0) { long long r = 0; for (int i = top; i >= 0; i--) { r *= 10; d[i] += r; r = d[i] % p; d[i] /= p; } D.push_back(r); while (top >= 0 && d[top] == 0) top--; } if (a >= ((int)(D).size())) return 0 * puts( 0 ); int now = 0, nxt = 1; dp[now][0][1][0] = 1; for (int i = ((int)(D).size()) - 1; i >= 0; i--) { memset((dp[nxt]), 0, sizeof((dp[nxt]))); for (int j = 0; j < (a + 1); ++j) { ADD(dp[nxt][j][1][0], dp[now][j][1][1] * (p - 1 - D[i])); ADD(dp[nxt][min(j + 1, a)][1][1], dp[now][j][1][1] * (p - D[i])); ADD(dp[nxt][j][0][0], dp[now][j][1][1] * con(p - D[i], p - 1)); ADD(dp[nxt][min(j + 1, a)][0][1], dp[now][j][1][1] * con(p - D[i] + 1, p)); ADD(dp[nxt][j][1][0], dp[now][j][1][0] * (D[i] + 1)); ADD(dp[nxt][min(j + 1, a)][1][1], dp[now][j][1][0] * D[i]); ADD(dp[nxt][j][0][0], dp[now][j][1][0] * con(1, D[i])); ADD(dp[nxt][min(j + 1, a)][0][1], dp[now][j][1][0] * con(1, D[i] - 1)); ADD(dp[nxt][j][0][0], dp[now][j][0][1] * con(1, p - 1)); ADD(dp[nxt][min(j + 1, a)][0][1], dp[now][j][0][1] * con(1, p)); ADD(dp[nxt][j][0][0], dp[now][j][0][0] * con(1, p)); ADD(dp[nxt][min(j + 1, a)][0][1], dp[now][j][0][0] * con(1, p - 1)); } swap(now, nxt); } long long an = 0; for (int j = 0; j < (2); ++j) ADD(an, dp[now][a][j][0]); cout << an; return 0; }
|
/* verilator lint_off STMTDLY */
module dv_driver #( parameter N = 1, // "N" packets wide
parameter AW = 32, // address width
parameter PW = 104, // packet width (derived)
parameter IDW = 12, // id width
parameter NAME = "none", // north, south etc
parameter STIMS = 1, // number of stimulus
parameter MAW = 16 // 64KB memory address width
)
(
//control signals
input clkin,
input clkout,
input nreset,
input start, //starts test
input [IDW-1:0] coreid, //everything has a coreid!
//inputs for monitoring
input [N-1:0] dut_access,
input [N*PW-1:0] dut_packet,
input [N-1:0] dut_wait,
//stimulus to drive
output [N-1:0] stim_access,
output [N*PW-1:0] stim_packet,
output [N-1:0] stim_wait,
output stim_done
);
//#############
//LOCAL WIRES
//#############
reg [IDW-1:0] offset;
wire [N*32-1:0] stim_count;
wire [N-1:0] stim_vec_done;
wire [N*IDW-1:0] coreid_array;
wire [N*PW-1:0] mem_packet_out;
wire [N-1:0] mem_access_out;
wire [N-1:0] mem_wait_out;
/*AUTOWIRE*/
//###########################################
//STIMULUS
//###########################################
assign stim_done = &(stim_vec_done[N-1:0]);
genvar i;
generate
for(i=0;i<N;i=i+1) begin : stim
if(i<STIMS) begin
stimulus #(.PW(PW),
.INDEX(i),
.NAME(NAME))
stimulus (// Outputs
.stim_access (stim_access[0]),
.stim_packet (stim_packet[(i+1)*PW-1:i*PW]),
.stim_count (stim_count[(i+1)*32-1:i*32]),
.stim_done (stim_vec_done[i]),
.stim_wait (stim_wait[i]),
// Inputs
.clk (clkin),
.nreset (nreset),
.start (start),
.dut_wait (dut_wait[i])
);
end // if (i<STIMS)
else
begin
assign stim_access[i] = 'b0;
assign stim_packet[(i+1)*PW-1:i*PW] = 'b0;
assign stim_count[(i+1)*32-1:i*32] = 'b0;
assign stim_vec_done[i] = 'b1;
assign stim_wait[i] = 'b0;
end
end // block: stim
endgenerate
//###########################################
//MONITORS (USE CLK2)
//###########################################
//Increment coreID depending on counter and orientation of side block
//TODO: parametrize
initial
begin
if(NAME=="north" | NAME=="south" )
offset=12'h001;
else
offset=12'h040;
end
genvar j;
generate
for(j=0;j<N;j=j+1) begin : mon
assign coreid_array[(j+1)*IDW-1:j*IDW] = coreid[IDW-1:0] + j*offset;
//MONITOR
emesh_monitor #(.PW(PW),
.NAME(NAME),
.IDW(IDW)
)
monitor (//inputs
.clk (clkout),
.nreset (nreset),
.dut_access (dut_access[j]),
.dut_packet (dut_packet[(j+1)*PW-1:j*PW]),
.coreid (coreid_array[(j+1)*IDW-1:j*IDW]),
.wait_in (stim_wait[j])
);
end // for (i=0;i<N;i=i+1)
endgenerate
//###########################################
//MEMORY
//###########################################
genvar k;
generate
for(j=0;j<N;j=j+1) begin : mem
ememory #(.NAME(NAME),
.IDW(IDW),
.PW(PW),
.AW(AW)
)
ememory(// Outputs
.wait_out (mem_wait_out[j]),
.access_out (mem_access_out[j]),
.packet_out (mem_packet_out[(j+1)*PW-1:j*PW]),
// Inputs
.clk (clkout),
.nreset (nreset),
.coreid (coreid[IDW-1:0]),
.access_in (dut_access[j]),
.packet_in (dut_packet[(j+1)*PW-1:j*PW]),
.wait_in (dut_wait[j])
);
end
endgenerate
//###########################################
//MUX BETWEEN STIMULUS AND MEMORY
//###########################################
//stimulus has higher priority
//TODO: Implement
endmodule // dv_driver
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
|
module basic_ShieldCtrl(
//Avalon System control signal.
input rsi_MRST_reset, // reset_n from MCU GPIO
input csi_MCLK_clk,
//Avalon-MM Control.
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
//Over current interrupt.
output ins_OC_irq,
input coe_A_OCN,
output coe_A_PWREN,
output coe_A_HOE,
output coe_A_LOE,
input coe_B_OCN,
output coe_B_PWREN,
output coe_B_HOE,
output coe_B_LOE
);
reg rMODA_PWREN = 1;
reg rMODA_HOE = 0;
reg rMODA_LOE = 0;
reg rMODB_PWREN = 1;
reg rMODB_HOE = 0;
reg rMODB_LOE = 0;
assign avs_ctrl_readdata = {6'b0, ~rMODB_PWREN, ~rMODA_PWREN, 6'b0, rMODB_HOE, rMODA_HOE, 6'b0, rMODB_LOE, rMODA_LOE, 6'b0, ~coe_B_OCN, ~coe_A_OCN};
assign avs_ctrl_waitrequest = 1'b0;
assign ins_OC_irq = ~(coe_A_OCN & coe_B_OCN);
assign coe_A_PWREN = rMODA_PWREN;
assign coe_A_HOE = rMODA_HOE;
assign coe_A_LOE = rMODA_LOE;
assign coe_B_PWREN = rMODB_PWREN;
assign coe_B_HOE = rMODB_HOE;
assign coe_B_LOE = rMODB_LOE;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
rMODA_PWREN <= 1;
rMODA_HOE <= 0;
rMODA_LOE <= 0;
rMODB_PWREN <= 1;
rMODB_HOE <= 0;
rMODB_LOE <= 0;
end
else begin
if(avs_ctrl_write) begin
if(avs_ctrl_byteenable[3]) begin rMODB_PWREN <= ~avs_ctrl_writedata[25]; rMODA_PWREN <= ~avs_ctrl_writedata[24]; end
if(avs_ctrl_byteenable[2]) begin rMODB_HOE <= avs_ctrl_writedata[17]; rMODA_HOE <= avs_ctrl_writedata[16]; end
if(avs_ctrl_byteenable[1]) begin rMODB_LOE <= avs_ctrl_writedata[9]; rMODA_LOE <= avs_ctrl_writedata[8]; end
end
end
end
endmodule
|
#include <bits/stdc++.h> const int N = 110; using namespace std; inline int read() { int x = 0, f = 1; int ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) { f = -1; } ch = getchar(); } while (ch <= 9 && ch >= 0 ) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return x * f; } int n, a[N]; int main() { int q = read(); while (q--) { bool flg = 0; n = read(); for (int i = 1; i <= n; i++) { a[i] = read(); } sort(a + 1, a + 1 + n); for (int i = 2; i <= n; i++) { if (a[i] == a[i - 1] + 1) { cout << 2 << endl; flg = 1; break; } } if (!flg) cout << 1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 1e9 + 7; int main() { long long int i, t, a = 0, k, b = 0, j = 0, l = 0, n, m, r = 0, c = 0, ct = 0, pos = 0, neg = 0, flag = 0, x, y, space, maxi, ans = 999999, ans2 = -100, avg, sum = 0; double d; long long int ar1[100005] = {0}, ar2[100005] = {0}; ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int ch, temp = 0; vector<long long int> v; string st, st2, st3; stack<char> s; vector<pair<string, string> > vp; queue<pair<long long int, long long int> > q; cin >> n; cout << 2 * n - 1 << << 2 << endl << 1 << << 2; return 0; }
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module memory_mux (
input select,
input enable_0,
input command_0,
input [31:0] address_0,
input [31:0] write_data_0,
input [3:0] write_mask_0,
output [31:0] read_data_0,
output valid_0,
input enable_1,
input command_1,
input [31:0] address_1,
input [31:0] write_data_1,
input [3:0] write_mask_1,
output [31:0] read_data_1,
output valid_1,
output enable,
output command,
output [31:0] address,
output [31:0] write_data,
output [3:0] write_mask,
input [31:0] read_data,
input valid
);
assign enable = select ? enable_1 : enable_0;
assign command = select ? command_1 : command_0;
assign address = select ? address_1 : address_0;
assign write_data = select ? write_data_1 : write_data_0;
assign write_mask = select ? write_mask_1 : write_mask_0;
assign read_data_1 = read_data;
assign read_data_0 = read_data;
assign valid_1 = select ? valid : 1'b0;
assign valid_0 = !select ? valid : 1'b0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 18:47:00 09/02/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: BCD_Binary_Encoder
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Binary to BCD Converter
//
// When the CONVERT signal asserts, the binary input BIN_IN is
// converted to BCD format. The BCD data is output at the end
// of the process on BCD_OUT and if an overflow occured then the
// BCD_OVERFLOW bit will be set. The conversion time depends on
// BIN_WINTH and is approximately BIN_WIDTH * 2 + 3 clock cycles.
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module BCD_Binary_Encoder
#(
parameter BIN_WIDTH = 8,
parameter BDC_DIGITS = 2
)
(
// Input Signals
input CONVERT,
output reg DONE,
input [BIN_WIDTH-1:0] BIN_IN,
// BCD Data Output Signals
output reg [BDC_DIGITS*4-1:0] BCD_OUT, // Packed Array
output reg BCD_OVERFLOW,
// System Signals
input CLK,
input RESET
);
// Include Standard Functions header file (needed for bit_index())
`include "StdFunctions.vh"
//
// BCD Register Width is 4-bits per BCD Digit
//
reg [4:0] State;
localparam [4:0]
S0 = 5'b00001,
S1 = 5'b00010,
S2 = 5'b00100,
S3 = 5'b01000,
S4 = 5'b10000;
localparam BCD_WIDTH = 4 * BDC_DIGITS;
reg [BIN_WIDTH-1:0] bin_shift_reg;
reg [BCD_WIDTH-1:0] bcd_shift_reg;
reg [BCD_WIDTH-1:0] bcd_adder_sum;
//
// Shift Counter tracks number of BIN_IN bits shifted (using a Rollover Counter)
//
localparam SHIFT_COUNTER_WIDTH = bit_index( BIN_WIDTH );
localparam [SHIFT_COUNTER_WIDTH:0] SHIFT_COUNTER_LOADVAL = { 1'b1, {SHIFT_COUNTER_WIDTH{1'b0}} } - BIN_WIDTH[SHIFT_COUNTER_WIDTH:0] + 1'b1;
reg [SHIFT_COUNTER_WIDTH:0] shift_counter_reg;
// Shift Count Done when the counter rollsover
wire shift_counter_done = shift_counter_reg[SHIFT_COUNTER_WIDTH];
//
// BCD Column Adders
// After each shift, add 3 to any column equaling 5 or greater.
// One adder will be generated per BCD Digit.
// The selective adding is done by LUT instead of an actual adder.
//
genvar i;
generate
begin
for (i = 0; i < BDC_DIGITS; i=i+1)
begin : bcd_adders
always @*
begin
case (bcd_shift_reg[i*4 +: 4])
// No Add
4'b0000 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 0 => 0
4'b0001 : bcd_adder_sum[i*4 +: 4] <= 4'b0001; // 1 => 1
4'b0010 : bcd_adder_sum[i*4 +: 4] <= 4'b0010; // 2 => 2
4'b0011 : bcd_adder_sum[i*4 +: 4] <= 4'b0011; // 3 => 3
4'b0100 : bcd_adder_sum[i*4 +: 4] <= 4'b0100; // 4 => 4
// Add 3
4'b0101 : bcd_adder_sum[i*4 +: 4] <= 4'b1000; // 5 => 8
4'b0110 : bcd_adder_sum[i*4 +: 4] <= 4'b1001; // 6 => 9
4'b0111 : bcd_adder_sum[i*4 +: 4] <= 4'b1010; // 7 => 10
4'b1000 : bcd_adder_sum[i*4 +: 4] <= 4'b1011; // 8 => 11
4'b1001 : bcd_adder_sum[i*4 +: 4] <= 4'b1100; // 9 => 12
// Invalid Inputs
4'b1010 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 10
4'b1011 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 11
4'b1100 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 12
4'b1101 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 13
4'b1110 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 14
4'b1111 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 15
endcase
end
end
end
endgenerate
//
// BCD Binary Encoder State Machine
//
reg overflow_flag;
// !! Lab 4: Implement the BCD Binary Encoder State Machine here !!
always @(posedge CLK, posedge RESET)
begin
if (RESET)
begin
State <= S0;
DONE <= 1'b0;
BCD_OUT <= {BDC_DIGITS*4{1'b0}};
BCD_OVERFLOW <= 1'b0;
shift_counter_reg <= {SHIFT_COUNTER_WIDTH+1{1'b0}};
bin_shift_reg <= {BIN_WIDTH{1'b0}};
bcd_shift_reg <= {BCD_WIDTH{1'b0}};
overflow_flag <= 1'b0;
end
else
begin
case (State)
S0 :
begin
DONE <= 1'b0;
if(CONVERT)
State <= S1;
end
S1 :
begin
bin_shift_reg <= BIN_IN;
bcd_shift_reg <= {BCD_WIDTH{1'b0}};
shift_counter_reg <= SHIFT_COUNTER_LOADVAL;
overflow_flag <= 1'b0;
State <= S2;
end
S2 :
begin
overflow_flag <= overflow_flag | bcd_shift_reg[BCD_WIDTH-1];
bcd_shift_reg <= { bcd_shift_reg[BCD_WIDTH-2:0], bin_shift_reg[BIN_WIDTH-1] };
bin_shift_reg <= { bin_shift_reg[BIN_WIDTH-2:0], 1'b0 };
if(shift_counter_done)
State <= S4;
else
State <= S3;
end
S3 :
begin
bcd_shift_reg <= bcd_adder_sum;
shift_counter_reg <= shift_counter_reg + 1'b1;
State <= S2;
end
S4:
begin
BCD_OUT <= bcd_shift_reg;
BCD_OVERFLOW <= overflow_flag;
DONE <= 1'b1;
State <= S0;
end
endcase
end
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_delta_assert #(
.width(width),
.min(min),
.max(max))
assert_delta_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_delta_assume #(
.width(width),
.min(min),
.max(max))
assert_delta_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_delta_cover #(
.width(width),
.min(min),
.max(max),
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON),
.OVL_COVER_CORNER_ON(OVL_COVER_CORNER_ON))
assert_delta_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_delta.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_delta_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 1;
parameter max = 2;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_delta_assume (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 1;
parameter max = 2;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_delta_cover (clk, reset_n, test_expr);
parameter width = 8;
parameter min = 1;
parameter max = 2;
parameter OVL_COVER_BASIC_ON = 1;
parameter OVL_COVER_CORNER_ON = 1;
input clk, reset_n;
input [width-1:0] test_expr;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000000 + 5; const int inf = 0x3f3f3f3f; int n; char y[maxn * 2], a[maxn * 2]; int main() { cin >> n; scanf( %s , y); scanf( %s , a); int ycnt = 0; for (int i = 0; i < n * 2; i++) { if (y[i] == 1 ) ycnt++; } int acnt = 0; for (int i = 0; i < n * 2; i++) { if (a[i] == 1 ) acnt++; } int ty = 0; int cnt = 0; for (int i = 0; i < n * 2; i++) { if (a[i] == 1 && y[i] == 1 ) cnt++; } if (cnt % 2 == 0) { if (acnt - ycnt >= 2) ty = 2; else if (acnt - ycnt < 2 && acnt - ycnt >= 0) ty = 0; else ty = 1; } else { if (acnt - ycnt > 3) ty = 2; else if (acnt - ycnt <= 3 && acnt - ycnt >= 1) ty = 0; else ty = 1; } if (ty == 1) printf( First n ); if (ty == 2) printf( Second n ); if (ty == 0) printf( Draw n ); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_1_V
`define SKY130_FD_SC_HS__NOR4BB_1_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor4bb_1 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor4bb_1 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_1_V
|
#include <bits/stdc++.h> using namespace std; int n, m, q; vector<int> w[400001]; int check[400001]; int ans; void input() { scanf( %d %d %d , &n, &m, &q); int x, y; for (int i = (0); i < (q); i++) { scanf( %d %d , &y, &x); x--; y--; x += n; w[x].push_back(y); w[y].push_back(x); } n = n + m; } void dfs(int node) { check[node] = 1; for (int i = (0); i < (w[node].size()); i++) { int next = w[node][i]; if (check[next] == 0) { dfs(next); } } } void process() { for (int i = (0); i < (n); i++) { if (check[i] == 0) { dfs(i); ans++; } } } void output() { printf( %d , ans - 1); } int main() { input(); process(); output(); return 0; }
|
#include <bits/stdc++.h> int main() { int n, i; char ch; char str[2010]; scanf( %d , &n); scanf( %c , &ch); if (n % 2 == 1) { scanf( %c , &str[n / 2]); for (i = 1; i <= n / 2; i++) { scanf( %c , &str[n / 2 - i]); scanf( %c , &str[n / 2 + i]); } } else { scanf( %c , &str[n / 2 - 1]); for (i = 1; i < n / 2; i++) { scanf( %c , &str[n / 2 - 1 + i]); scanf( %c , &str[n / 2 - 1 - i]); } scanf( %c , &str[n - 1]); } str[n] = 0 ; printf( %s n , str); return 0; }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_i2f(
input sys_clk,
input alu_rst,
input [31:0] a,
input valid_i,
output [31:0] r,
output valid_o
);
/* Stage 1 */
reg s1_valid;
reg s1_sign;
reg [30:0] s1_abs;
reg s1_zero;
always @(posedge sys_clk) begin
if(alu_rst)
s1_valid <= 1'b0;
else
s1_valid <= valid_i;
s1_sign <= a[31];
if(a[31])
s1_abs <= 31'd0 - a[30:0];
else
s1_abs <= a[30:0];
s1_zero <= a == 32'd0;
end
/* Stage 2 */
wire [4:0] s1_clz;
pfpu_clz32 clz32(
.d({s1_abs, 1'bx}),
.clz(s1_clz)
);
reg s2_valid;
reg s2_sign;
reg [7:0] s2_expn;
reg [30:0] s2_mant;
always @(posedge sys_clk) begin
if(alu_rst)
s2_valid <= 1'b0;
else
s2_valid <= s1_valid;
s2_sign <= s1_sign;
s2_mant <= s1_abs << s1_clz;
if(s1_zero)
s2_expn <= 8'd0;
else
s2_expn <= 8'd157 - {4'd0, s1_clz};
end
assign r = {s2_sign, s2_expn, s2_mant[29:7]};
assign valid_o = s2_valid;
endmodule
|
/*
-- ============================================================================
-- FILE NAME : rom.v
-- DESCRIPTION : Read Only Memory
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "rom.h"
/********** ¥â¥¸¥å©`¥ë **********/
module rom (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire cs_, // ¥Á¥Ã¥×¥»¥ì¥¯¥È
input wire as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
input wire [`RomAddrBus] addr, // ¥¢¥É¥ì¥¹
output wire [`WordDataBus] rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output reg rdy_ // ¥ì¥Ç¥£
);
/********** Xilinx FPGA Block RAM : -> altera sprom **********/
altera_sprom x_s3e_sprom (
.clock (clk), // ¥¯¥í¥Ã¥¯
.address (addr), // ¥¢¥É¥ì¥¹
.q (rd_data) // Õi¤ß³ö¤·¥Ç©`¥¿
);
/********** ¥ì¥Ç¥£¤ÎÉú³É **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ·ÇͬÆڥꥻ¥Ã¥È */
rdy_ <= #1 `DISABLE_;
end else begin
/* ¥ì¥Ç¥£¤ÎÉú³É */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin
rdy_ <= #1 `ENABLE_;
end else begin
rdy_ <= #1 `DISABLE_;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 100000000; const long long MAXN = 2e6 + 20; struct edge { long long from, to, cost; }; int main() { long long i, j, k, t1, t2, t3, n, m, t; std::ios::sync_with_stdio(0); cin >> n >> k; cout << (k + n - 1) / n << n ; }
|
#include <bits/stdc++.h> using namespace std; int read() { int f = 1, x = 0; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -f; c = getchar(); } while (c >= 0 && c <= 9 ) x = x * 10 + c - 0 , c = getchar(); return f * x; } inline int lowbit(int x) { return x & (-x); } inline int modadd(int x, int y) { return (x + y >= 1000000007 ? x + y - 1000000007 : x + y); } inline int sgn(int x) { return (x < 0 ? -1 : (x > 0 ? 1 : 0)); } template <typename T> T gcd(T a, T b) { return (!b) ? a : gcd(b, a % b); } int poww(int a, int b) { int res = 1; while (b > 0) { if (b & 1) res = 1ll * res * a % 1000000007; a = 1ll * a * a % 1000000007, b >>= 1; } return res; } const int dx[] = {-1, 0, 1, 0}, dy[] = {0, 1, 0, -1}; const int ddx[] = {-1, -1, -1, 0, 0, 1, 1, 1}, ddy[] = {-1, 0, 1, -1, 1, -1, 0, 1}; int n, a[100005]; void init() { n = read(); for (int i = 1; i <= n; ++i) a[i] = read(); } bool check1() { long long tot = 0; for (int i = n - 1; i >= 1; --i) { if (a[i] < tot) return false; if (a[i] > a[i + 1]) tot += a[i] - a[i + 1]; } return true; } bool check2() { long long tot = 0; for (int i = 2; i <= n; ++i) { if (a[i] < tot) return false; if (a[i] > a[i - 1]) tot += a[i] - a[i - 1]; } return true; } void solve() { if (check1()) printf( YES n ); else if (check2()) printf( YES n ); else printf( NO n ); } int main() { int T = read(); while (T--) { init(); solve(); } return 0; }
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads and writes data to the Audio chip on Altera's DE2 *
* Development and Education Board. The audio chip must be in master mode *
* and the digital format must be left justified. *
* *
******************************************************************************/
module wasca_audio_0 (
// Inputs
clk,
reset,
address,
chipselect,
read,
write,
writedata,
// Bidirectionals
AUD_BCLK,
AUD_DACLRCK,
// Outputs
irq,
readdata,
AUD_DACDAT
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 1: 0] address;
input chipselect;
input read;
input write;
input [31: 0] writedata;
input AUD_BCLK;
input AUD_DACLRCK;
// Bidirectionals
// Outputs
output reg irq;
output reg [31: 0] readdata;
output AUD_DACDAT;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam DW = 15;
localparam BIT_COUNTER_INIT = 5'd15;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire bclk_rising_edge;
wire bclk_falling_edge;
wire dac_lrclk_rising_edge;
wire dac_lrclk_falling_edge;
wire [ 7: 0] left_channel_write_space;
wire [ 7: 0] right_channel_write_space;
// Internal Registers
reg done_dac_channel_sync;
reg write_interrupt_en;
reg clear_write_fifos;
reg write_interrupt;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
irq <= 1'b0;
else
irq <=
write_interrupt |
1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
readdata <= 32'h00000000;
else if (chipselect == 1'b1)
begin
if (address == 2'h0)
readdata <=
{22'h000000,
write_interrupt,
1'b0,
4'h0,
clear_write_fifos,
1'b0,
write_interrupt_en,
1'b0};
else if (address == 2'h1)
begin
readdata[31:24] <= left_channel_write_space;
readdata[23:16] <= right_channel_write_space;
readdata[15: 8] <= 8'h00;
readdata[ 7: 0] <= 8'h00;
end
else
readdata <= 32'h00000000;
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_interrupt_en <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 2'h0))
write_interrupt_en <= writedata[1];
end
always @(posedge clk)
begin
if (reset == 1'b1)
clear_write_fifos <= 1'b0;
else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 2'h0))
clear_write_fifos <= writedata[3];
end
always @(posedge clk)
begin
if (reset == 1'b1)
write_interrupt <= 1'b0;
else if (write_interrupt_en == 1'b0)
write_interrupt <= 1'b0;
else
write_interrupt <=
(&(left_channel_write_space[6:5]) | left_channel_write_space[7]) |
(&(right_channel_write_space[6:5]) | right_channel_write_space[7]);
end
always @(posedge clk)
begin
if (reset == 1'b1)
done_dac_channel_sync <= 1'b0;
else if (dac_lrclk_falling_edge == 1'b1)
done_dac_channel_sync <= 1'b1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_clock_edge Bit_Clock_Edges (
// Inputs
.clk (clk),
.reset (reset),
.test_clk (AUD_BCLK),
// Bidirectionals
// Outputs
.rising_edge (bclk_rising_edge),
.falling_edge (bclk_falling_edge)
);
altera_up_clock_edge DAC_Left_Right_Clock_Edges (
// Inputs
.clk (clk),
.reset (reset),
.test_clk (AUD_DACLRCK),
// Bidirectionals
// Outputs
.rising_edge (dac_lrclk_rising_edge),
.falling_edge (dac_lrclk_falling_edge)
);
altera_up_audio_out_serializer Audio_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset | clear_write_fifos),
.bit_clk_rising_edge (bclk_rising_edge),
.bit_clk_falling_edge (bclk_falling_edge),
.left_right_clk_rising_edge (done_dac_channel_sync & dac_lrclk_rising_edge),
.left_right_clk_falling_edge (done_dac_channel_sync & dac_lrclk_falling_edge),
.left_channel_data (writedata[DW:0]),
.left_channel_data_en ((address == 2'h2) & chipselect & write),
.right_channel_data (writedata[DW:0]),
.right_channel_data_en ((address == 2'h3) & chipselect & write),
// Bidirectionals
// Outputs
.left_channel_fifo_write_space (left_channel_write_space),
.right_channel_fifo_write_space (right_channel_write_space),
.serial_audio_out_data (AUD_DACDAT)
);
defparam
Audio_Out_Serializer.DW = DW;
endmodule
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#include <bits/stdc++.h> using namespace std; int getChar(char c) { if (c == + ) return 1; return 0; } string s; stack<int> mystack; int main() { cin >> s; int n = s.size(); int temp; for (int i = 0; i < n; i++) { temp = getChar(s[i]); if (mystack.empty()) mystack.push(temp); else { if (mystack.top() == temp) mystack.pop(); else mystack.push(temp); } } if (mystack.empty()) { cout << Yes << endl; return 0; } cout << No << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; double dp[maxn], p[maxn]; int main() { int n; scanf( %d , &n); double ans = 0, d; for (int i = 1; i <= n; i++) { scanf( %lf , &p[i]); ans += p[i]; } for (int i = 2; i <= n; i++) { dp[i] = (dp[i - 1] + p[i - 1]) * p[i]; ans += 2 * dp[i]; } printf( %.10f n , ans); return 0; }
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#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; long long __gcd(long long a, long long b) { while (a != 0) { long long __t = b % a; b = a; a = __t; } return b; } bool isSimple(unsigned x) { for (unsigned i = 2; i < x; i++) if (x % i == 0) return false; return true; } int main() { cin.tie(0); cout.tie(0); cerr.tie(0); ios_base::sync_with_stdio(false); long long x; cin >> x; cout << x - x / 2 - x / 3 - x / 5 - x / 7 + x / 6 + x / 10 + x / 14 + x / 15 + x / 21 + x / 35 - x / 30 - x / 42 - x / 70 - x / 105 + x / 210; return 0; }
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#include <iostream> #include <vector> #define int long long const int DEN = 100000; const int INF = 100000000000000000; int ceild(int x) { if(x%DEN != 0) { x += DEN-x%DEN; } return x/DEN; } signed main() { std::ios::sync_with_stdio(false); std::cin.tie(0); int n, m; std::cin >> n >> m; std::vector<int> poss[n+1]; for(int i = 0; i <= m; i++) poss[0].push_back(i==0); for(int i = 1; i <= n; i++) { poss[i] = poss[i-1]; int t, x, y; std::cin >> t >> x >> y; if(t == 2) { for(int j = 0; j <= m; j++) { if(!poss[i-1][j]) continue; int next = j; int count = 0; while(next <= m && count <= y) { poss[i][next] = 1; next *= x; next = ceild(next); if(next <= m && poss[i-1][next]) break; count++; } } } else { x = ceild(x); std::vector<int> next(m+1, -INF); for(int j = 0; j <= m; j++) { if(j-x >= 0) next[j] = next[j-x]; if(poss[i-1][j]) next[j] = j; if(j-next[j] <= y*x) poss[i][j] = 1; } } } std::vector<int> answer(m+1, -1); for(int i = n; i > 0; i--) { for(int j = 1; j <= m; j++) if(poss[i][j]) answer[j] = i; } for(int j = 1; j <= m; j++) std::cout << answer[j] << ; std::cout << std::endl; return 0; }
|
module SPIFSM (
input Reset_n_i,
input Clk_i,
input In0_i,
input In1_i,
input In2_i,
input In3_i,
input In4_i,
input In5_i,
input In6_i,
input In7_i,
output Out0_o,
output Out1_o,
output Out2_o,
output Out3_o,
output Out4_o,
output Out5_o,
output Out6_o,
output Out7_o,
output Out8_o,
output Out9_o,
output Out10_o,
output Out11_o,
output Out12_o,
output Out13_o,
output Out14_o,
input CfgMode_i,
input CfgClk_i,
input CfgShift_i,
input CfgDataIn_i,
output CfgDataOut_o
);
wire [7:0] Input_s;
wire [14:0] Output_s;
wire ScanEnable_s;
wire ScanClk_s;
wire ScanDataIn_s;
wire ScanDataOut_s;
TRFSM #(
.InputWidth(8),
.OutputWidth(15),
.StateWidth(5),
.UseResetRow(0),
.NumRows0(5),
.NumRows1(10),
.NumRows2(10),
.NumRows3(5),
.NumRows4(5),
.NumRows5(0),
.NumRows6(0),
.NumRows7(0),
.NumRows8(0),
.NumRows9(0)
) TRFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Input_i(Input_s),
.Output_o(Output_s),
.CfgMode_i(CfgMode_i),
.CfgClk_i(CfgClk_i),
.CfgShift_i(CfgShift_i),
.CfgDataIn_i(CfgDataIn_i),
.CfgDataOut_o(CfgDataOut_o),
.ScanEnable_i(ScanEnable_s),
.ScanClk_i(ScanClk_s),
.ScanDataIn_i(ScanDataIn_s),
.ScanDataOut_o(ScanDataOut_s)
);
assign Input_s = { In7_i, In6_i, In5_i, In4_i, In3_i, In2_i, In1_i, In0_i };
assign Out0_o = Output_s[0];
assign Out1_o = Output_s[1];
assign Out2_o = Output_s[2];
assign Out3_o = Output_s[3];
assign Out4_o = Output_s[4];
assign Out5_o = Output_s[5];
assign Out6_o = Output_s[6];
assign Out7_o = Output_s[7];
assign Out8_o = Output_s[8];
assign Out9_o = Output_s[9];
assign Out10_o = Output_s[10];
assign Out11_o = Output_s[11];
assign Out12_o = Output_s[12];
assign Out13_o = Output_s[13];
assign Out14_o = Output_s[14];
assign ScanEnable_s = 1'b0;
assign ScanClk_s = 1'b0;
assign ScanDataIn_s = 1'b0;
endmodule
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:1024000000,1024000000 ) using namespace std; const int maxn = 1e5 + 7; int n, m; long long h[maxn], p[maxn]; bool ok(long long x) { long long cnt = 0; for (int i = 0; i < n; i++) { if (p[cnt] >= h[i]) { for (int j = cnt; j < m; j++) { if (h[i] + x >= p[j]) cnt++; else break; } } else { if (h[i] - p[cnt] > x) continue; long long t = max(x - (h[i] - p[cnt]) * 2, (x - (h[i] - p[cnt])) / 2); for (int j = cnt; j < m; j++) { if (h[i] + t >= p[j]) cnt++; else break; } } } if (cnt >= m) return true; else return false; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> h[i]; for (int i = 0; i < m; i++) cin >> p[i]; long long l = 0, r = 100000000000 + 7; ; while (l + 1 < r) { long long m = (l + r) >> 1; if (ok(m)) r = m; else l = m; } if (ok(l)) r = l; cout << r << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int a[202020], f[202020]; int s[202020]; bool br[202020]; int n, doe, ans; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]), ++f[a[i]]; doe = 1; while (f[doe] != 0) ++doe; for (int i = 1; i <= n; ++i) { if (f[a[i]] == 1 && br[a[i]] == 0) { s[i] = a[i]; br[a[i]] = 1; continue; } if (a[i] < doe && br[a[i]] == 0) { s[i] = a[i]; br[a[i]] = 1; --f[a[i]]; continue; } ++ans; s[i] = doe; --f[a[i]]; br[doe] = 1; ++doe; while (f[doe] != 0) ++doe; } printf( %d n , ans); printf( %d , s[1]); for (int i = 2; i <= n; ++i) printf( %d , s[i]); printf( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; int A[1000005], B[1000005]; int ans = 0; int C[35]; int main() { int n, m, i, j, k, l; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) { scanf( %d , &A[i]); long long t = 1; for (j = 0; j < 33; j++) { C[j] += ((A[i] & t) != 0); t = (t << 1); } } for (j = 1; j <= m; j++) { scanf( %d , &B[j]); } sort(B + 1, B + 1 + m); for (i = 1; i <= m; i++) { for (j = B[i]; j < 33; j++) if (C[j]) break; if (j < 33) { for (k = j - 1; k >= B[i]; k--) C[k]++; C[j]--; ans++; } } printf( %d n , ans); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O22A_PP_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_PP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) const long long mod = 1e9 + 7; inline long long add(long long a, long long b) { return (a % mod + b % mod) % mod; } inline long long sub(long long a, long long b) { return (a % mod - b % mod + mod) % mod; } inline long long mul(long long a, long long b) { return (a % mod * b % mod) % mod; } inline long long power(long long a, long long b, long long MOD) { long long res = 1; while (b) { if (b & 1) { res *= a; res %= MOD; } a = a * a; a %= MOD; b >>= 1; } return res; } clock_t time_p = clock(); void time() { time_p = clock() - time_p; cerr << Time elapsed : << (long double)(time_p) / CLOCKS_PER_SEC << n ; } bool go(string a, string b) { if (a == b) return true; long long n1 = a.length(); long long n2 = b.length(); if (n1 & 1 || n2 & 1) return false; string a1, a2, b1, b2; for (long long i = 0; i < n1 / 2; i++) a1 += a[i]; for (long long i = n1 / 2; i < n1; i++) a2 += a[i]; for (long long i = 0; i < n2 / 2; i++) b1 += b[i]; for (long long i = n2 / 2; i < n2; i++) b2 += b[i]; if (go(a1, b2) && go(a2, b1)) return true; if (go(a1, b1) && go(a2, b2)) return true; return false; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; string a, b; cin >> a >> b; cout << (go(a, b) ? YES : NO ) << n ; time(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int main() { cin.tie(0), cout.tie(0); ios::sync_with_stdio(false); int t; cin >> t; while (t--) { int u = 0, l = 0, d = 0; string s; cin >> s; for (int i = 0; i < s.size(); i++) { if (s[i] >= a && s[i] <= z ) { l++; } if (s[i] >= A && s[i] <= Z ) { u++; } if (s[i] >= 0 && s[i] <= 9 ) { d++; } } for (int i = 0; i < s.size(); i++) { if (s[i] >= a && s[i] <= z && l > 1) { if (!u) { s[i] = A ; u++; } else if (!d) { s[i] = 0 ; d++; } } else if (s[i] >= A && s[i] <= Z && u > 1) { if (!l) { s[i] = a ; l++; } else if (!d) { s[i] = 0 ; d++; } } else if (s[i] >= 0 && s[i] <= 9 && d > 1) { if (!l) { s[i] = a ; l++; } else if (!u) { s[i] = A ; u++; } } } cout << s << endl; } }
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#include <bits/stdc++.h> using namespace std; template <class T> int chkmax(T& a, T b) { if (b > a) { a = b; return 1; } return 0; } template <class T> int chkmin(T& a, T b) { if (b < a) { a = b; return 1; } return 0; } template <class iterator> void output(iterator begin, iterator end, ostream& out = cerr) { while (begin != end) { out << (*begin) << ; begin++; } out << endl; } template <class T> void output(T x, ostream& out = cerr) { output(x.begin(), x.end(), out); } void fast_io() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } const int mx = 1e6 + 228; int n; vector<vector<int> > g; long long t[mx], h[mx]; void read() { cin >> n; for (int i = 0; i < n; ++i) { cin >> t[i]; } for (int i = 0; i < n; ++i) { cin >> h[i]; } g.resize(n); for (int i = 0; i < n - 1; ++i) { int u, v; cin >> u >> v; u--; v--; g[u].push_back(v); g[v].push_back(u); } } const long long INF = 1e18; long long dp[mx][2][2]; long long sum_dp, dist0; int ch_eq, e_to_v, e_from_v; vector<long long> dist, delta; void calc_stuff(int v, int pv) { e_to_v = 0; e_from_v = 0; sum_dp = 0; ch_eq = 0; dist.clear(); delta.clear(); dist0 = 0; for (auto v1 : g[v]) { if (pv != v1) { if (h[v1] > h[v]) { e_from_v++; sum_dp += dp[v1][1][0]; } if (h[v1] < h[v]) { e_to_v++; sum_dp += dp[v1][0][1]; } if (h[v1] == h[v]) { ch_eq++; dist0 += dp[v1][0][1]; delta.push_back(dp[v1][1][0] - dp[v1][0][1]); } } } sort(delta.begin(), delta.end()); dist.push_back(dist0); for (int i = 0; i < ch_eq; ++i) { dist0 += delta[i]; dist.push_back(dist0); } } void calc_dp(int v, int down_e, int up_e) { int tot_to_v = e_to_v + down_e; int tot_from_v = e_from_v + up_e; dp[v][down_e][up_e] = INF; for (int i = 0; i <= ch_eq; ++i) { chkmin(dp[v][down_e][up_e], sum_dp + dist[i] + (long long)t[v] * (long long)max(tot_from_v + i, tot_to_v + ch_eq - i)); } } void calc_dp(int v, int pv) { for (auto v1 : g[v]) { if (v1 != pv) { calc_dp(v1, v); } } calc_stuff(v, pv); if (v == pv) { calc_dp(v, 0, 0); } else { if (h[pv] <= h[v]) { calc_dp(v, 1, 0); } else { dp[v][1][0] = INF; } if (h[pv] >= h[v]) { calc_dp(v, 0, 1); } else { dp[v][0][1] = INF; } } } signed main() { fast_io(); read(); calc_dp(0, 0); cout << dp[0][0][0] << n ; }
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#include <bits/stdc++.h> using namespace std; int cc[100002]; pair<int, int> in[100002]; vector<pair<int, int> > adj[100002]; int pos = 1; int l[100002], r[100002], label[100002]; long long d[100002]; void dfs(int node, int par, long long depth = 0) { l[node] = pos; d[node] = depth; int ch, w; for (pair<int, int> edge : adj[node]) { if (edge.first == par) { continue; } dfs(edge.first, node, depth + edge.second); } label[pos] = node; r[node] = pos++; } long long pen[100002]; void update(int ind, long long add) { while (ind < 100002) { pen[ind] += add; ind += ind & (-ind); } } long long query(int ind) { long long ret = 0; while (ind > 0) { ret = ret + pen[ind]; ind = ind & (ind - 1); } return ret; } pair<long long, int> seg[100002 * 4]; long long lazy[100002 * 4]; const long long inf = -4e18; void init(int pos, int l, int r) { lazy[pos] = 0; if (l == r) { seg[pos] = {d[label[l]], l}; return; } int mid = (l + r) / 2; init(pos * 2, l, mid); init(pos * 2 + 1, mid + 1, r); seg[pos] = max(seg[pos * 2], seg[pos * 2 + 1]); } void push(int pos, int l, int r) { if (lazy[pos] != 0) { seg[pos].first += lazy[pos]; if (l != r) { lazy[pos * 2] += lazy[pos]; lazy[pos * 2 + 1] += lazy[pos]; } lazy[pos] = 0; } } void update(int pos, int l, int r, int ql, int qr, long long val) { push(pos, l, r); if (r < ql || qr < l) { return; } if (ql <= l && r <= qr) { lazy[pos] = val; push(pos, l, r); return; } int mid = (l + r) / 2; update(pos * 2, l, mid, ql, qr, val); update(pos * 2 + 1, mid + 1, r, ql, qr, val); seg[pos] = max(seg[pos * 2], seg[pos * 2 + 1]); } pair<long long, int> query(int pos, int l, int r, int ql, int qr) { push(pos, l, r); if (r < ql || qr < l) { return {inf, 0}; } if (ql <= l && r <= qr) { return seg[pos]; } int mid = (l + r) / 2; return max(query(pos * 2, l, mid, ql, qr), query(pos * 2 + 1, mid + 1, r, ql, qr)); } long long w[100002]; long long dfs2(int node, int par) { priority_queue<long long> pq; for (pair<int, int> edge : adj[node]) { if (edge.first == par) { continue; } pq.push(dfs2(edge.first, node)); } long long ret = w[node]; if (node != 1) { if (pq.size() > 0) pq.pop(); } if (pq.size() > 0) { ret = max(ret, pq.top()); } return ret; } void solve() { int n; long long T; scanf( %d %lld , &n, &T); long long rb = 0; for (int i = 1; i <= n; ++i) { scanf( %d , &cc[i]); rb += cc[i]; } for (int i = 1; i <= n; ++i) { scanf( %d , &in[i].first); in[i].second = i; } sort(in + 1, in + n + 1); for (int i = 2; i <= n; ++i) { int p, l; scanf( %d %d , &p, &l); l *= 2; adj[p].push_back({i, l}); } dfs(1, 0); init(1, 1, n); for (int i = 1; i <= n; ++i) { int node, co, p, x, y; node = in[i].second; co = cc[node]; p = r[node]; x = l[node], y = p; long long val = (long long)co * in[i].first; while (true) { pair<long long, int> q = query(1, 1, n, x, y); if (q.first + val >= T) { long long remCC = min((T - q.first) / in[i].first, (long long)co); w[label[q.second]] = query(q.second) + remCC; update(1, 1, n, q.second, q.second, inf); } else { break; } } update(1, 1, n, x, y, val); update(x, co); update(y + 1, -co); } while (true) { pair<long long, int> q = query(1, 1, n, 1, n); if (q.first < 0) { break; } w[label[q.second]] = query(q.second); update(1, 1, n, q.second, q.second, inf); } printf( %lld n , dfs2(1, 0)); } int main() { solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, a[12345]; int calc(int x, int y) { int ret = 0; vector<int> v; for (int i = 0; i < 2 * n; ++i) { if (i != x && i != y) v.push_back(a[i]); } for (int i = 0; i < v.size(); i += 2) ret += abs(v[i] - v[i + 1]); return ret; } int main() { cin >> n; int mn = 1e9, i; for (i = 0; i < 2 * n; i++) cin >> a[i]; sort(a, a + 2 * n); for (int i = 0; i < n * 2; i++) { for (int j = i + 1; j < n * 2; j++) { mn = min(mn, calc(i, j)); } } cout << mn; }
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#include <bits/stdc++.h> using namespace std; const int NV = 105; const int LNV = 11; const int NE = 5015; const int NQ = 1000005; const int intmax = 0x7fffffff; int f[2005]; int a[2005]; int n, m; struct Edge { int ne, y, v; }; struct Edge2 { int x, y, v; }; bool cmp(Edge2 a, Edge2 b) { return a.v < b.v; } struct DisSet { int fa[NV], nv; void init(int n) { nv = n; for (int i = 0; i < n; i++) fa[i] = i; } int find(int x) { if (fa[x] == x) return x; return fa[x] = find(fa[x]); } void uni(int x, int y) { fa[find(x)] = find(y); } }; struct Graph { Edge e[NE]; int ep, h[NV], nv, ne; void init(int n, int m = NE) { ne = m; nv = n; ep = 2; memset(h, 0, 4 * nv); } void add(int a, int b, int v = 1) { e[ep].ne = h[a]; e[ep].y = b; e[ep].v = v; h[a] = ep; ep++; } bool dfs(int now, int d, int t) { if (t == m + 1) { if (d) return 1; return 0; } int ans = intmax; vector<pair<int, int> > p; for (int i = h[now]; i; i = e[i].ne) { if (!d) if (e[i].y < f[t]) continue; if (e[i].v) continue; p.push_back(make_pair(e[i].y, i)); } sort(p.begin(), p.end()); for (int i = 0; i < p.size(); i++) { int key = p[i].second; e[key].v = 1; e[key ^ 1].v = 1; if (dfs(e[key].y, (e[key].y > f[t]) | d, t + 1)) { a[t] = e[key].y; return 1; } e[key].v = 0; e[key ^ 1].v = 0; } return 0; } }; Graph g; int main() { scanf( %d%d , &n, &m); g.init(n, m); int la; scanf( %d , &la); f[0] = la; for (int i = 1; i <= m; i++) { int a; scanf( %d , &a); g.add(la, a, 0); g.add(a, la, 0); la = a; f[i] = a; } if (g.dfs(f[0], 0, 1)) { printf( %d , f[0]); for (int i = 1; i <= m; i++) printf( %d , a[i]); puts( ); } else puts( No solution ); }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue Feb 14 01:38:42 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
// Design : design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(GPIO_I, GPIO_O, GPIO_T, SDIO0_WP, TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
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#include <bits/stdc++.h> using namespace std; template <class T, class U> void Max(T &a, U b) { if (a < b) a = b; } template <class T, class U> void Min(T &a, U b) { if (a > b) a = b; } template <class T, class U> void add(T &a, U b) { a += b; if (a >= 1000000007) a -= 1000000007; } template <class T, class U> int min(T a, U b) { return a >= b ? b : a; } int ans, first[50010], second[50010], a[50010], b[50010], res[50010], g[10240]; void out(int i, int j) { cout << ? << i << << j << n ; cin >> ans; fflush(stdout); } int main() { int i, j, k, ca = 0, n, T, m = 0, K; scanf( %d , &n); for (int i = 0; i < n; i++) { out(i, i); b[i] = ans; out(i, 0); a[i] = ans; } ans = 0; int M = 4096 * 2; for (int i = 0; i < n; i++) { first[i] = 0; for (int j = 0; j < n; j++) g[j] = -1; int ok = 1; for (int j = 0; j < n; j++) { k = a[i] ^ a[j]; if (k >= n) { ok = 0; break; } g[k] = j; } if (!ok) continue; for (int j = 0; j < n; j++) { if (g[j] == -1) { ok = 0; break; } k = g[j]; first[k] = j; } if (!ok) continue; for (int j = 0; j < n; j++) second[first[j]] = j; for (int j = 0; j < n; j++) { if ((first[j] ^ second[j]) != b[j]) { ok = 0; break; } } if (!ok) continue; for (int j = 0; j < n; j++) { if ((first[j] ^ second[0]) != a[j]) { ok = 0; break; } } if (!ok) continue; ans++; for (int j = 0; j < n; j++) res[j] = first[j]; } printf( ! n%d n , ans); for (int i = 0; i < n; i++) printf( %d , res[i]); puts( ); }
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#include <bits/stdc++.h> using namespace std; char arr[500001]; char inv(char temp) { if (temp == 0 ) return 1 ; return 0 ; } string invert(string temp) { int n = temp.length(); if (n % 2 == 1) { for (int i = 1; i < n; i += 2) temp[i] = inv(temp[i]); } else { for (int i = 1; i < n / 2; i += 2) temp[i] = inv(temp[i]); for (int i = n - 2; i >= n / 2; i -= 2) temp[i] = inv(temp[i]); } return temp; } int main() { string ans = , cur; int n, a, b, c, i, j, temp = 1; long long res = 0; cin >> n; cin >> arr[0]; cur = arr[0]; for (i = 1; i < n; i++) { cin >> arr[i]; if (arr[i] != arr[i - 1]) { temp++; cur += arr[i]; } else { if (temp <= 2) ans += cur; else { res = fmax(res, (cur.length() - 1) / 2); ans += invert(cur); } temp = 1; cur = arr[i]; } } if (temp <= 2) ans += cur; else { ans += invert(cur); res = fmax(res, (cur.length() - 1) / 2); } cout << res << endl; for (i = 0; i < ans.size(); i++) cout << ans[i] << ; }
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; long long int a[n], b[n]; long long int sum = 0, suma = 0; for (int i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } for (int i = 0; i < n; i++) { cin >> b[i]; suma += b[i]; } long long int mina = *min_element(a, a + n); long long int mine = *min_element(b, b + n); long long int ans = 0; for (int i = 0; i < n; i++) { ans += min(abs(a[i] - mina), abs(b[i] - mine)); int aoeu = a[i]; a[i] -= min(abs(a[i] - mina), abs(b[i] - mine)); b[i] -= min(abs(aoeu - mina), abs(b[i] - mine)); ans += abs(a[i] - mina); ans += abs(b[i] - mine); } cout << ans << n ; } }
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