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#include <bits/stdc++.h> using namespace std; int t; vector<vector<int> > nod; vector<int> sol; void bfs(int n) { sol = vector<int>(n + 10); sol[1] = 1; queue<int> Q; Q.push(1); while (!Q.empty()) { int a = Q.front(); Q.pop(); for (int j = 0; j < nod[a].size(); j++) if (!sol[nod[a][j]]) { sol[nod[a][j]] = sol[a] + 1; Q.push(nod[a][j]); } } } int main() { cin >> t; while (t--) { int n, m; cin >> n >> m; nod = vector<vector<int> >(n + 5); for (int i = 1; i <= m; i++) { int nod1, nod2; cin >> nod1 >> nod2; nod[nod1].push_back(nod2); nod[nod2].push_back(nod1); } bfs(n); vector<int> nr1, nr2; for (int i = 1; i <= n; i++) { if (sol[i] & 1) nr1.push_back(i); else nr2.push_back(i); } if (nr1.size() < nr2.size()) { cout << nr1.size() << n ; for (int i = 0; i < nr1.size(); i++) cout << nr1[i] << ; cout << n ; } else { cout << nr2.size() << n ; for (int i = 0; i < nr2.size(); i++) cout << nr2[i] << ; cout << n ; } } return 0; }
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// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module store and retrieves video frames to and from memory. *
* *
******************************************************************************/
`undef USE_TO_MEMORY
`define USE_32BIT_MASTER
module Raster_Laser_Projector_Video_In_video_dma_controller_0 (
// Inputs
clk,
reset,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_waitrequest,
slave_address,
slave_byteenable,
slave_read,
slave_write,
slave_writedata,
// Bidirectional
// Outputs
stream_ready,
master_address,
master_write,
master_writedata,
slave_readdata
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 7; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter WIDTH = 640; // Frame's width in pixels
parameter HEIGHT = 480; // Frame's height in lines
parameter AW = 18; // Frame's address width
parameter WW = 9; // Frame width's address width
parameter HW = 8; // Frame height's address width
parameter MDW = 7; // Avalon master's datawidth
parameter DEFAULT_BUFFER_ADDRESS = 32'd9437184;
parameter DEFAULT_BACK_BUF_ADDRESS = 32'd0;
parameter ADDRESSING_BITS = 16'd19;
parameter COLOR_BITS = 4'd7;
parameter COLOR_PLANES = 2'd0;
parameter DEFAULT_DMA_ENABLED = 1'b1; // 0: OFF or 1: ON
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_data;
input stream_startofpacket;
input stream_endofpacket;
input [EW: 0] stream_empty;
input stream_valid;
input master_waitrequest;
input [ 1: 0] slave_address;
input [ 3: 0] slave_byteenable;
input slave_read;
input slave_write;
input [31: 0] slave_writedata;
// Bidirectional
// Outputs
output stream_ready;
output [31: 0] master_address;
output master_write;
output [MDW:0] master_writedata;
output [31: 0] slave_readdata;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire inc_address;
wire reset_address;
wire [31: 0] buffer_start_address;
wire dma_enabled;
// Internal Registers
reg [AW: 0] pixel_address;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset | ~dma_enabled)
pixel_address <= 'h0;
else if (reset_address)
pixel_address <= 'h0;
else if (inc_address)
pixel_address <= pixel_address + 1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign master_address = buffer_start_address +
pixel_address;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_dma_control_slave DMA_Control_Slave (
// Inputs
.clk (clk),
.reset (reset),
.address (slave_address),
.byteenable (slave_byteenable),
.read (slave_read),
.write (slave_write),
.writedata (slave_writedata),
.swap_addresses_enable (reset_address),
// Bi-Directional
// Outputs
.readdata (slave_readdata),
.current_start_address (buffer_start_address),
.dma_enabled (dma_enabled)
);
defparam
DMA_Control_Slave.DEFAULT_BUFFER_ADDRESS = DEFAULT_BUFFER_ADDRESS,
DMA_Control_Slave.DEFAULT_BACK_BUF_ADDRESS = DEFAULT_BACK_BUF_ADDRESS,
DMA_Control_Slave.WIDTH = WIDTH,
DMA_Control_Slave.HEIGHT = HEIGHT,
DMA_Control_Slave.ADDRESSING_BITS = ADDRESSING_BITS,
DMA_Control_Slave.COLOR_BITS = COLOR_BITS,
DMA_Control_Slave.COLOR_PLANES = COLOR_PLANES,
DMA_Control_Slave.ADDRESSING_MODE = 1'b1,
DMA_Control_Slave.DEFAULT_DMA_ENABLED = DEFAULT_DMA_ENABLED;
altera_up_video_dma_to_memory From_Stream_to_Memory (
// Inputs
.clk (clk),
.reset (reset | ~dma_enabled),
.stream_data (stream_data),
.stream_startofpacket (stream_startofpacket),
.stream_endofpacket (stream_endofpacket),
.stream_empty (stream_empty),
.stream_valid (stream_valid),
.master_waitrequest (master_waitrequest),
// Bidirectional
// Outputs
.stream_ready (stream_ready),
.master_write (master_write),
.master_writedata (master_writedata),
.inc_address (inc_address),
.reset_address (reset_address)
);
defparam
From_Stream_to_Memory.DW = DW,
From_Stream_to_Memory.EW = EW,
From_Stream_to_Memory.MDW = MDW;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int n, t; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> t; while (t--) { cin >> n; long long int a[n], x = 0; vector<long long int> ans; for (int i = 0; i < n; i++) { cin >> a[i]; if (i == 0) { ans.push_back(a[i]); continue; } long long int last = ans[ans.size() - 1]; if ((a[i] > 0 && last < 0) || (last > 0 && a[i] < 0)) ans.push_back(a[i]); else { ans[ans.size() - 1] = max(last, a[i]); } } long long int sum = 0; for (int i = 0; i < ans.size(); i++) { sum += ans[i]; } cout << sum << endl; } }
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#include <bits/stdc++.h> using namespace std; string s; bool atted, dotted, goned; int cntu, cnth = -1, cntr = -1, cntd = -1; int main() { cin >> s; for (int i = 0; i < ((int)(s).size()); i++) { if (!atted && s[i] == @ ) atted = 1; else if (atted && !goned && s[i] == . && s[i - 1] != . && s[i - 1] != @ && cntd <= 16) dotted = 1, cntd = -1; else if (atted && !goned && s[i] == / ) goned = 1; else if ((!atted || goned) && s[i] == . ) return puts( NO ), 0; else if (!isalnum(s[i]) && s[i] != _ ) return puts( NO ), 0; if (!atted) cntu++; else if (!goned) cnth++, cntd++; else cntr++; } if (cntd == 0) return puts( NO ), 0; if (cntu < 1 || cntu > 16 || cnth < 1 || cnth > 32 || goned && cntr < 1 || cntr > 32) return puts( NO ), 0; return puts( YES ), 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_gt_common.v
// Version : 3.0
`timescale 1ns / 1ps
module pcie3_7x_0_gt_common #(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_GT_DEVICE = "GTH", // PCIe GT device
parameter PCIE_USE_MODE = "2.1", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency
)
(
input PIPE_CLK,
input QPLL_QPLLPD,
input QPLL_QPLLRESET,
input QPLL_DRP_CLK,
input QPLL_DRP_RST_N,
input QPLL_DRP_OVRD,
input QPLL_DRP_GEN3,
input QPLL_DRP_START,
output [5:0] QPLL_DRP_CRSCODE,
output [8:0] QPLL_DRP_FSM,
output QPLL_DRP_DONE,
output QPLL_DRP_RESET,
output QPLL_QPLLLOCK,
output QPLL_QPLLOUTCLK,
output QPLL_QPLLOUTREFCLK
);
//---------- QPLL DRP Module Output --------------------
wire [7:0] qpll_drp_addr;
wire qpll_drp_en;
wire [15:0] qpll_drp_di;
wire qpll_drp_we;
//---------- QPLL Wrapper Output -----------------------
wire [15:0] qpll_drp_do;
wire qpll_drp_rdy;
//---------- QPLL Resets -----------------------
//---------- QPLL DRP Module ---------------------------------------
pcie3_7x_0_qpll_drp #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
qpll_drp_i
(
//---------- Input -------------------------
.DRP_CLK (QPLL_DRP_CLK),
.DRP_RST_N (!QPLL_DRP_RST_N),
.DRP_OVRD (QPLL_DRP_OVRD),
.DRP_GEN3 (&QPLL_DRP_GEN3),
.DRP_QPLLLOCK (QPLL_QPLLLOCK),
.DRP_START (QPLL_DRP_START),
.DRP_DO (qpll_drp_do),
.DRP_RDY (qpll_drp_rdy),
//---------- Output ------------------------
.DRP_ADDR (qpll_drp_addr),
.DRP_EN (qpll_drp_en),
.DRP_DI (qpll_drp_di),
.DRP_WE (qpll_drp_we),
.DRP_DONE (QPLL_DRP_DONE),
.DRP_QPLLRESET (QPLL_DRP_RESET),
.DRP_CRSCODE (QPLL_DRP_CRSCODE),
.DRP_FSM (QPLL_DRP_FSM)
);
//---------- QPLL Wrapper ------------------------------------------
pcie3_7x_0_qpll_wrapper #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
qpll_wrapper_i
(
//---------- QPLL Clock Ports --------------
.QPLL_GTGREFCLK (PIPE_CLK),
.QPLL_QPLLLOCKDETCLK (1'd0),
.QPLL_QPLLOUTCLK (QPLL_QPLLOUTCLK),
.QPLL_QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK),
.QPLL_QPLLLOCK (QPLL_QPLLLOCK),
//---------- QPLL Reset Ports --------------
.QPLL_QPLLPD (QPLL_QPLLPD),
.QPLL_QPLLRESET (QPLL_QPLLRESET),
//---------- QPLL DRP Ports ----------------
.QPLL_DRPCLK (QPLL_DRP_CLK),
.QPLL_DRPADDR (qpll_drp_addr),
.QPLL_DRPEN (qpll_drp_en),
.QPLL_DRPDI (qpll_drp_di),
.QPLL_DRPWE (qpll_drp_we),
.QPLL_DRPDO (qpll_drp_do),
.QPLL_DRPRDY (qpll_drp_rdy)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_TB_V
`define SKY130_FD_SC_LS__CLKINV_TB_V
/**
* clkinv: Clock tree inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkinv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x(0); cin >> n; string s; while (n--) { cin >> s; if (s[1] == + ) ++x; else --x; } cout << x << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX_N = 300000; const int MAX_E2 = 1 << 20; const long double PI = acosl(-1.0); struct Elm { long double x, y, th; Elm() : x(0.0), y(0.0), th(0.0) {} Elm(long double _x, long double _y, long double _th) : x(_x), y(_y), th(_th) {} Elm &extend(int l) { x += l * cosl(th), y += l * sinl(th); return *this; } Elm &rot(long double dth) { long double c = cosl(dth), s = sinl(dth); long double x0 = c * x - s * y; long double y0 = s * x + c * y; x = x0, y = y0; th += dth; return *this; } Elm operator+(const Elm &e) const { long double c = cosl(th), s = sinl(th); long double x0 = c * e.x - s * e.y; long double y0 = s * e.x + c * e.y; return Elm(x + x0, y + y0, th + e.th); } }; template <typename T, const int MAX_E2> struct SegTree { int e2; T nodes[MAX_E2], defv; SegTree() {} void init(int n, T _defv) { defv = _defv; for (e2 = 1; e2 < n; e2 <<= 1) ; fill(nodes, nodes + MAX_E2, defv); } T &get(int i) { return nodes[e2 - 1 + i]; } void seti(int i, T v) { get(i) = v; } void setall() { for (int j = e2 - 2; j >= 0; j--) nodes[j] = nodes[j * 2 + 1] + nodes[j * 2 + 2]; } void set(int i, T v) { int j = e2 - 1 + i; nodes[j] = v; while (j > 0) { j = (j - 1) / 2; nodes[j] = nodes[j * 2 + 1] + nodes[j * 2 + 2]; } } }; SegTree<Elm, MAX_E2> st; int main() { int n, m; scanf( %d%d , &n, &m); st.init(n, Elm(0.0, 0.0, 0.0)); for (int i = 0; i < n; i++) st.seti(i, Elm(1.0, 0.0, 0.0)); st.setall(); for (int i = 0; i < m; i++) { int x, y, z; scanf( %d%d%d , &x, &y, &z); y--; Elm e = st.get(y); if (x == 1) e.extend(z); else e.rot(-PI * z / 180); st.set(y, e); Elm r = st.nodes[0]; printf( %.10Lf %.10Lf n , r.x, r.y); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b; if (a >= b) { c = (a - b) / 2; cout << b << << c; } else { c = (b - a) / 2; cout << a << << c; } }
|
//Manages memory and
//dispatches instructions to the rest of
//the processor.
//This unit doesn't have a proper pipeline,
//rather it is mostly hard-wired combinational logic.
module dispatchu(
CLK,
MEMDAT,
ADAT,
BDAT,
CDAT,
addr,
memOut,
memWrite,
Cout,
cWrite,
Asel,
Bsel,
Csel,
intPipeOp,
intPipeA,
intPipeB,
intPipeC
);
input CLK;
input [15:0] MEMDAT;
input [15:0] ADAT;
input [15:0] BDAT;
input [15:0] CDAT;
output [31:0] addr;
output [15:0] memOut;
output memWrite;
output [15:0] Cout;
output cWrite;
output [2:0] Asel;
output [2:0] Bsel;
output [2:0] Csel;
output [3:0] intPipeOp;
output [2:0] intPipeA;
output [2:0] intPipeB;
output [2:0] intPipeC;
reg stkpInc, stkpDec, stkpWrite;
wire [31:0] ABBus;
wire [31:0] stkPtrBus;
pointer stackPointer(CLK, stkpInc, stkpDec, ABBus, stkpWrite, stkPtrBus);
reg pcWrite;
wire pcInc, pcDec;
wire [31:0] PCBus;
wire [31:0] pcInputBus [1:0];
wire [31:0] extendedMemoryInputBus; //Allows for rets.
assign extendedMemoryInputBus[31:16]=0;
assign extendedMemoryInputBus[15:0]=MEMDAT;
assign pcInputBus[0]=ABBus;
assign pcInputBus[1]=extendedMemoryInputBus;
reg pcInputSel;
pointer programCounter(CLK, pcInc, pcDec, pcInputBus[pcInputSel], pcWrite, PCBus);
assign ABBus[31:16]=ADAT;
assign ABBus[15:0]=BDAT;
reg [15:0] memOutReg;
assign memOut=memOutReg;
wire [31:0] addrMux[0:2];
//Addressing can either be from:
//1. The program counter.
//2. The AB bus.
//3. The the stack pointer.
assign addrMux[0]=PCBus;
assign addrMux[1]=ABBus;
assign addrMux[2]=stkPtrBus;
reg [1:0] addrMuxSelector;
assign addr=addrMux[addrMuxSelector];
reg [15:0] curVals;
wire [6:0] op;
wire [2:0] a;
wire [2:0] b;
wire [2:0] c;
assign op=curVals[15:9];
assign a=curVals[8:6];
assign b=curVals[5:3];
assign c=curVals[2:0];
assign Asel=a;
assign Bsel=b;
assign Csel=c;
assign intPipeA=a;
assign intPipeB=b;
assign intPipeC=c;
wire [15:0] cOutMux[2:0];
reg [1:0] cSelector;
assign cOutMux[0]=MEMDAT;
assign cOutMux[1]=curVals[14:0];
assign cOutMux[2]=stkPtrBus[15:0];
assign Cout=cOutMux[cSelector];
//Assign out an optyper to get operation types:
wire load, store, branch, cmp, stack, ldl, call, intOp;
optyper ot(op, load, store, branch, cmp, stack, ldl);//, call);
assign intOp=(~load)&&(~store)&&(~branch)&&(~cmp)&&(~stack)&&(~ldl);
//assign cWrite=ldl||(some representative combinational logic.
wire [3:0] intPipeOpSelector[3:0];
assign intPipeOpSelector[0]=0;
assign intPipeOpSelector[1]=op[3:0];
assign intPipeOp=intPipeOpSelector[intOp];
wire fetchNextOp;
assign fetchNextOp=intOp;
//assign pcInc=fetchNextOp;
//Build a comparator so that we can have flags.
wire greater, less, same;
comparator comp(ADAT, BDAT, greater, less, same);
reg gFlag, lFlag, sFlag;
reg memWriteReg;
assign memWrite=memWriteReg;
reg stateReg;
reg cWriteReg;
assign cWrite=cWriteReg;
assign pcInc=~stateReg&&fetchNextOp;
assign pcDec=0;
//This 1-state design is going to be the biggest bottleneck
//to reaching higher clockspeeds.
always@(posedge CLK) begin
if(stateReg) begin //Second state for actions that require another state.
stateReg<=1'b0;
//curVals<=0; //Reset the current thingy.
addrMuxSelector<=0;
if(op!=44&&op!=45) begin
curVals<=0; //Reset the current instruction to NOP.
end
if(op==44) begin //Second half of call; completes the jump.
end
else if(op==45) begin //Second half of ret; completes the jump.
pcWrite<=0;
end
else if(stack) begin //Be sure to do the stack register stuff:
if(store) begin
memWriteReg<=0;
stkpDec<=0;
end
else begin
stkpInc<=0;
cWriteReg<=1;
end
end
else if(~stack) begin
if(store) begin
memWriteReg<=0;
end
else begin //I don't think I actually have to do anything.
cWriteReg<=0;
end
end
end //End of state 1 stuff.
//Beginning of state 0 stuff:
else begin
if(fetchNextOp) begin
addrMuxSelector<=2'b00;
curVals<=MEMDAT;
cWriteReg<=0;
stkpWrite<=0;
//pcInc<=0;
pcInputSel<=0;
end
else if(ldl) begin
curVals<=0;//MEMDAT;
cSelector<=1;
cWriteReg<=1;
end
else if(cmp) begin
curVals<=0;//MEMDAT;
gFlag<=greater;
lFlag<=less;
sFlag<=same;
end
//Now for branches:
else if(branch) begin
if(op==51) begin//Unconditional jump
pcWrite<=1;
//curVals<=MEMDAT;
curVals<=0; //Insert a NOP so that we go back to the first state.
end
else if(op==52) begin //Jump on equal
if(same) begin
pcWrite<=1;
curVals<=0; //Same as above.
end
else begin
curVals<=MEMDAT;
end
end
else if(op==53) begin //Jump on positive
if(greater) begin
pcWrite<=1;
curVals<=0;
end
else begin
curVals<=MEMDAT;
end
end
else if(op==54) begin //Jump on negative
if(less) begin
pcWrite<=1;
curVals<=0;
end
else begin
curVals<=MEMDAT;
end
end
end
//Now catch any stack loads/stores:
else if(op==40) begin //Store Stack Register
cSelector<=2;
cWriteReg<=1;
curVals<=0;
end
else if(op==41) begin //Load Stack Register
stkpWrite<=1;
curVals<=0;
end
else if(op==44) begin //Call. This instruction will definitely
//Limit clockspeed potential.
addrMuxSelector<=2'b10;
stkpDec<=1;
//stateReg<=1;
memOutReg<=PCBus[15:0]; //Write the 16 lowest bits of the program counter.
memWriteReg<=1;
end
else if(op==55) begin //Ret
stkpInc<=1;
addrMuxSelector<=2'b10;
pcInputSel<=1; //Set the input to the memory bus.
pcWrite<=1;
curVals<=MEMDAT;
end
//Now for loads/stores:
else if(stack) begin
stateReg<=1;
addrMuxSelector<=2'b10;
if(store) begin
memWriteReg<=1'b1;
stkpDec<=1;
memOutReg<=CDAT;
end
else begin
stkpInc<=1;
end
end
else if(~stack) begin
stateReg<=1;
addrMuxSelector<=2'b01;
if(store) begin
memWriteReg<=1'b1;
memOutReg<=CDAT;
end
else begin
cSelector<=0;
cWriteReg<=1;
end
end
end //End of state 0 stuff.
end
initial begin
curVals<=0;
addrMuxSelector<=0;
stateReg<=0;
memWriteReg<=0;
memOutReg<=0;
cSelector<=0;
cWriteReg<=0;
pcWrite<=0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2007; const int mod = 1e9 + 7; int n, m; int dp[maxn][maxn][2], block[maxn][maxn][2], sum[maxn][maxn][2], vec[maxn][2]; char s[maxn][maxn]; int calc(int u, int v, int w) { if (w == 0) { for (; vec[v][1] < u; ++vec[v][1]) { if (block[vec[v][1] + 1][v][1] <= n - u) break; } return (sum[u - 1][v][1] - sum[vec[v][1] - 1][v][1] + mod) % mod; } else { for (; vec[u][0] < v; ++vec[u][0]) { if (block[u][vec[u][0] + 1][0] <= m - v) break; } return (sum[u][v - 1][0] - sum[u][vec[u][0] - 1][0] + mod) % mod; } } int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin >> n >> m; if (n == 1 && m == 1) { cout << 1 << endl; return 0; } for (int i = 1; i <= max(n, m); ++i) { vec[i][0] = vec[i][1] = 1; } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cin >> s[i][j]; if (s[i][j] == R ) block[i + 1][j + 1][0] = block[i + 1][j + 1][1] = 1; } } for (int i = 0; i <= n; ++i) { for (int j = m; j > 0; --j) { block[i][j - 1][0] += block[i][j][0]; } } for (int j = 0; j <= m; ++j) { for (int i = n; i > 0; --i) { block[i - 1][j][1] += block[i][j][1]; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (i == 0 && j == 0) { dp[0][0][0] = dp[0][0][1] = 1; sum[1][1][0] = sum[1][1][1] = 1; continue; } dp[i][j][0] = calc(i + 1, j + 1, 0); dp[i][j][1] = calc(i + 1, j + 1, 1); sum[i + 1][j + 1][0] = (sum[i + 1][j][0] + dp[i][j][0]) % mod; sum[i + 1][j + 1][1] = (sum[i][j + 1][1] + dp[i][j][1]) % mod; } } printf( %d n , (dp[n - 1][m - 1][0] + dp[n - 1][m - 1][1]) % mod); return 0; }
|
#include <bits/stdc++.h> struct el { int x, y, z; }; using namespace std; int cmp(el a, el b) { return a.x < b.x; } int cmp1(el a, el b) { return a.y < b.y; } int main(int argc, const char* argv[]) { int n, w; cin >> n >> w; vector<el> a; el b; int ans = 0; for (int i = 0; i < n; i++) { cin >> b.x; ans += b.x / 2 + b.x % 2; b.z = b.x / 2 + b.x % 2; b.y = i; a.push_back(b); } if (ans > w) { cout << -1; return 0; } int diff = w - ans; sort(a.begin(), a.end(), cmp); for (int i = (int)a.size() - 1; (i > -1) && (diff > 0); i--) { int tmp = min(diff, a[i].x - (a[i].x / 2 + a[i].x % 2)); a[i].z += tmp; diff -= tmp; } sort(a.begin(), a.end(), cmp1); for (auto i = a.begin(); i != a.end(); i++) { cout << (*i).z << ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_1_V
`define SKY130_FD_SC_LP__FA_1_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_1_V
|
#include <bits/stdc++.h> using namespace std; using Long = long long; int main() { int t; cin >> t; while (t--) { int d; cin >> d; if (d * d < 4 * d) { puts( N ); } else { double dis = sqrt(d * d - 4 * d); double x = (dis + d) / 2, y = (d - dis) / 2; printf( Y %0.10lf %0.10lf n , x, y); } } return 0; }
|
#include<bits/stdc++.h> #define pb push_back using namespace std; typedef long long ll; const int maxn=1e6+100; const int M=1000000007; typedef array<int,41> A; bool vis[50]; int f[50],n,mx,F[50][50],G[50][50],p[50],nf[50],inv[50]; int ways[50][50][50]; map<A,int> dp[41][41][41]; void add(int &x,int y){x+=y;if (x>=M)x-=M;} int C(int x,int y){ if (y<0||y>x) return 0; return 1ll*f[x]*nf[y]%M*nf[x-y]%M; } void init(){ inv[1]=1; for (int i=2;i<=n;i++) inv[i]=M-1ll*(M/i)*inv[M%i]%M; f[0]=nf[0]=1; for (int i=1;i<=n;i++) f[i]=1ll*f[i-1]*i%M,nf[i]=1ll*nf[i-1]*inv[i]%M; F[0][0]=f[n-1]; for (int i=0;i<=n-1;i++) for (int j=1;j+i<=n-1;j++){ F[i][j]=0; for (int x=0;x<=i;x++) for (int y=0;y<=j;y++){ add(F[i][j],1ll*C(i,x)*C(j,y)%M*f[n-1-x-y]%M*f[x+y]%M); if (!y) add(G[i][j],1ll*C(i,x)*C(j,y)%M*f[n-1-x-y]%M*f[x+y]%M); } } for (int i=0;i<=n-1;i++) for (int j=0;j+i<=n-1;j++){ int x=1,y=1; for (int k=1;k<=n;k++){ x=1ll*x*F[i][j]%M; y=1ll*y*G[i][j]%M; ways[i][j][k]=(x-y+M)%M; } } } int solve(int lasttot,int tot,int block,A a){ if (dp[lasttot][tot][block].find(a)!=dp[lasttot][tot][block].end()){ return dp[lasttot][tot][block][a]; } int ret=0,sum=n; for (int i=1;i<=mx;i++) sum-=a[i]*i; if (sum==n) return dp[lasttot][tot][block][a]=nf[block]; A tmp=a; for (int i=1;i<=mx;i++) { if (a[i]){ tmp[i]--; add(ret,1ll*ways[sum-tot-lasttot][lasttot][i]*a[i]%M*solve(lasttot,tot+i,block+1,tmp)%M); if (block) add(ret,1ll*ways[sum-tot][tot][i]*a[i]%M*nf[block]%M*solve(tot,i,1,tmp)%M); tmp[i]++; } } return dp[lasttot][tot][block][a]=ret; } int main(){ scanf( %d ,&n); init(); for (int i=1;i<=n;i++) scanf( %d ,&p[i]); A a; for (int i=0;i<=40;i++) a[i]=0; for (int i=1;i<=n;i++) if (!vis[i]){ int w=0,tmp=i; while (!vis[tmp]){ w++; vis[tmp]=1; tmp=p[tmp]; } a[w]++; mx=max(mx,w); } printf( %d n ,solve(0,0,0,a)); return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_ddr_rptr_south.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_ddr_rptr_south ( /*AUTOARG*/
// Outputs
io_dram_data_valid_buf, io_dram_ecc_in_buf, io_dram_data_in_buf,
dram_io_cas_l_buf, dram_io_channel_disabled_buf, dram_io_cke_buf,
dram_io_clk_enable_buf, dram_io_drive_data_buf,
dram_io_drive_enable_buf, dram_io_pad_clk_inv_buf,
dram_io_pad_enable_buf, dram_io_ras_l_buf, dram_io_write_en_l_buf,
dram_io_addr_buf, dram_io_bank_buf, dram_io_cs_l_buf,
dram_io_data_out_buf, dram_io_ptr_clk_inv_buf,
// Inputs
io_dram_data_valid, io_dram_ecc_in, io_dram_data_in,
dram_io_cas_l, dram_io_channel_disabled, dram_io_cke,
dram_io_clk_enable, dram_io_drive_data, dram_io_drive_enable,
dram_io_pad_clk_inv, dram_io_pad_enable, dram_io_ras_l,
dram_io_write_en_l, dram_io_addr, dram_io_bank, dram_io_cs_l,
dram_io_data_out, dram_io_ptr_clk_inv
);
/*OUTPUTS*/
output io_dram_data_valid_buf;
output [31:0] io_dram_ecc_in_buf;
output [255:0] io_dram_data_in_buf;
output dram_io_cas_l_buf;
output dram_io_channel_disabled_buf;
output dram_io_cke_buf;
output dram_io_clk_enable_buf;
output dram_io_drive_data_buf;
output dram_io_drive_enable_buf;
output dram_io_pad_clk_inv_buf;
output dram_io_pad_enable_buf;
output dram_io_ras_l_buf;
output dram_io_write_en_l_buf;
output [14:0] dram_io_addr_buf;
output [2:0] dram_io_bank_buf;
output [3:0] dram_io_cs_l_buf;
output [287:0] dram_io_data_out_buf;
output [4:0] dram_io_ptr_clk_inv_buf;
/*INPUTS*/
input io_dram_data_valid;
input [31:0] io_dram_ecc_in;
input [255:0] io_dram_data_in;
input dram_io_cas_l;
input dram_io_channel_disabled;
input dram_io_cke;
input dram_io_clk_enable;
input dram_io_drive_data;
input dram_io_drive_enable;
input dram_io_pad_clk_inv;
input dram_io_pad_enable;
input dram_io_ras_l;
input dram_io_write_en_l;
input [14:0] dram_io_addr;
input [2:0] dram_io_bank;
input [3:0] dram_io_cs_l;
input [287:0] dram_io_data_out;
input [4:0] dram_io_ptr_clk_inv;
/************************* CODE *********************************/
assign io_dram_data_in_buf = io_dram_data_in[255:0];
assign io_dram_data_valid_buf = io_dram_data_valid;
assign io_dram_ecc_in_buf = io_dram_ecc_in[31:0];
assign dram_io_addr_buf = dram_io_addr[14:0];
assign dram_io_bank_buf = dram_io_bank[2:0];
assign dram_io_cas_l_buf = dram_io_cas_l;
assign dram_io_channel_disabled_buf = dram_io_channel_disabled;
assign dram_io_cke_buf = dram_io_cke;
assign dram_io_clk_enable_buf = dram_io_clk_enable;
assign dram_io_cs_l_buf = dram_io_cs_l[3:0];
assign dram_io_data_out_buf = dram_io_data_out[287:0];
assign dram_io_drive_data_buf = dram_io_drive_data;
assign dram_io_drive_enable_buf = dram_io_drive_enable;
assign dram_io_pad_clk_inv_buf = dram_io_pad_clk_inv;
assign dram_io_pad_enable_buf = dram_io_pad_enable;
assign dram_io_ptr_clk_inv_buf = dram_io_ptr_clk_inv[4:0];
assign dram_io_ras_l_buf = dram_io_ras_l;
assign dram_io_write_en_l_buf = dram_io_write_en_l;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:53:07 07/01/2014
// Design Name:
// Module Name: cheat
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module cheat(
input clk,
input [7:0] SNES_PA,
input [23:0] SNES_ADDR,
input [7:0] SNES_DATA,
input SNES_wr_strobe,
input SNES_rd_strobe,
input SNES_reset_strobe,
input snescmd_enable,
input nmicmd_enable,
input return_vector_enable,
input reset_vector_enable,
input branch1_enable,
input branch2_enable,
input button_enable,
input button_addr,
input snescmd_rdy,
output snescmd_we_cheat,
output [8:0] snescmd_addr_cheat,
output [7:0] snescmd_data_cheat,
output button_ctx_valid,
output button_ctx_mode,
input [11:0] DBG_ADDR,
output [7:0] DBG_DATA_OUT,
input pad_latch,
input snes_ajr,
input SNES_cycle_start,
input [2:0] pgm_idx,
input pgm_we,
input [31:0] pgm_in,
output [7:0] data_out,
output cheat_hit,
output snescmd_unlock
);
wire snescmd_wr_strobe = snescmd_enable & SNES_wr_strobe;
reg cheat_enable = 0;
reg nmi_enable = 0;
reg irq_enable = 0;
reg holdoff_enable = 0; // temp disable hooks after reset
reg buttons_enable = 0;
reg wram_present = 0;
// SGB hooks rely on the use of the unmodified SGB2 SNES ROM to detect WRAM writes
// to store button data. This has several benefits over the existing NMI hook code
// for SGB:
// 1) No NMI needs to be enabled and V/H IRQ doesn't need to be used.
// 2) No SNES code overhead for recording button state.
// 3) Less FPGA code.
//
// This hook is not perfect and relies on hardcoded WRAM addresses for snooping the data. It's
// possible that these addresses match during an injected SNES ROM causing problems. But much like the original
// hooks the fix is simple: disable them. More address checks may be added to help avoid this (e.g. ROM addresses).
wire [1:0] rst_match_bits = {SNES_ADDR == 24'h00FFFC, SNES_ADDR == 24'h00FFFD};
reg [29:0] hook_enable_count = 0;
// support the reset hook for booting the SNES ROM
reg [1:0] reset_unlock_r = 2'b10;
wire reset_unlock = |reset_unlock_r;
wire rst_addr_match = |rst_match_bits;
wire hook_enable = ~|hook_enable_count;
reg snescmd_unlock_r = 0;
assign data_out = rst_match_bits[1] ? 8'h7d : 8'h2a;
assign cheat_hit = (reset_unlock & rst_addr_match);
assign snescmd_unlock = snescmd_unlock_r;
// make patched reset vector visible for first fetch only
// (including masked read by Ultra16)
always @(posedge clk) begin
if(SNES_reset_strobe) begin
reset_unlock_r <= 2'b11;
end else if(SNES_cycle_start) begin
if(rst_addr_match & |reset_unlock_r) begin
reset_unlock_r <= reset_unlock_r - 1;
end
end
end
// handle unlocks for reset
reg snescmd_unlock_disable_strobe = 1'b0;
reg [6:0] snescmd_unlock_disable_countdown = 0;
reg snescmd_unlock_disable = 0;
always @(posedge clk) begin
if(SNES_reset_strobe) begin
snescmd_unlock_r <= 0;
snescmd_unlock_disable <= 0;
end else begin
if(SNES_rd_strobe) begin
if(rst_match_bits[1] & |reset_unlock_r) begin
snescmd_unlock_r <= 1;
end
end
// give some time to exit snescmd memory and jump to original vector
if(SNES_cycle_start) begin
if(snescmd_unlock_disable) begin
if(|snescmd_unlock_disable_countdown) begin
snescmd_unlock_disable_countdown <= snescmd_unlock_disable_countdown - 1;
end else if(snescmd_unlock_disable_countdown == 0) begin
snescmd_unlock_r <= 0;
snescmd_unlock_disable <= 0;
end
end
end
if(snescmd_unlock_disable_strobe) begin
snescmd_unlock_disable_countdown <= 7'd6;
snescmd_unlock_disable <= 1;
end
end
end
// CMD 0x85: disable hooks for 10 seconds
always @(posedge clk) begin
if((snescmd_unlock & snescmd_wr_strobe & ~|SNES_ADDR[8:0] & (SNES_DATA == 8'h85))
| (holdoff_enable & SNES_reset_strobe)) begin
hook_enable_count <= 30'd840000000; // 10 seconds
end else if (snescmd_we_cheat | button_ctx_valid) begin
hook_enable_count <= 30'd42000000; // 0.5 seconds
end else if (|hook_enable_count) begin
hook_enable_count <= hook_enable_count - 1;
end
end
// MCU writes and internal updates
// Only need to support IRQ/NMI (now hook enable) buttons, and holdoff
always @(posedge clk) begin
if(SNES_reset_strobe) begin
snescmd_unlock_disable_strobe <= 1'b0;
end else begin
snescmd_unlock_disable_strobe <= 1'b0;
if(snescmd_unlock & snescmd_wr_strobe) begin
if(~|SNES_ADDR[8:0]) begin
case(SNES_DATA)
8'h82: cheat_enable <= 1;
8'h83: cheat_enable <= 0;
8'h84: {nmi_enable, irq_enable} <= 2'b00;
endcase
end else if(SNES_ADDR[8:0] == 9'h1fd) begin
snescmd_unlock_disable_strobe <= 1'b1;
end
end else if(pgm_we) begin
if(pgm_idx == 7) begin // set/reset global enable / hooks
// pgm_in[13:8] are reset bit flags
// pgm_in[5:0] are set bit flags
{wram_present, buttons_enable, holdoff_enable, irq_enable, nmi_enable, cheat_enable}
<= ({wram_present, buttons_enable, holdoff_enable, irq_enable, nmi_enable, cheat_enable}
& ~pgm_in[13:8])
| pgm_in[5:0];
end
end
end
end
// record buttons
reg pad_valid_r = 0;
reg [15:0] pad_data_r = 0;
reg cmd_valid_r;
reg [15:0] cmd_data_r;
// map controller input to cmd output
// check button combinations
// L+R+Start+Select : $3030
// L+R+Select+X : $2070
// L+R+Start+A : $10b0 // unsupported
// L+R+Start+B : $9030 // unsupported
// L+R+Start+Y : $5030
// L+R+Start+X : $1070
wire button_reset_game = (cmd_data_r == 16'h3030);
wire button_reset_menu = (cmd_data_r == 16'h2070);
wire button_hook_dis = (cmd_data_r == 16'h5030);
wire button_hook_dis_10 = (cmd_data_r == 16'h1070);
wire button_valid = button_reset_game | button_reset_menu | button_hook_dis | button_hook_dis_10;
// allow any directional buttons and yba values. anything involving select should press select first
wire button_state_save = ({2'b00,cmd_data_r[13:12],1'b0,cmd_data_r[6:4]} == 8'h05);
wire button_state_load = ({2'b00,cmd_data_r[13:12],1'b0,cmd_data_r[6:4]} == 8'h06);
wire button_state = button_state_save | button_state_load;
always @(posedge clk) begin
pad_valid_r <= 0;
if(SNES_wr_strobe & button_enable) begin
if (~button_addr) pad_data_r[7:0] <= SNES_DATA; else pad_data_r[15:8] <= SNES_DATA;
// enable the joypad state machine after lower order bytes are written second
if (~button_addr) pad_valid_r <= 1;
end
end
// generate SNESCMD operations to communicate back with the menu
always @(posedge clk) begin
if (SNES_reset_strobe) begin
cmd_valid_r <= 0;
end
else begin
if (cmd_valid_r & (snescmd_we_cheat | ~button_valid)) begin
cmd_valid_r <= 0;
end
// avoid writing when snescmd is unlocked to reduce races with snes communicating with MCU
// it may not matter because the buttons aren't read until out of reset when we should never get into
// the hook inside SNES Code
else if (~snescmd_unlock_r & pad_valid_r & hook_enable & (nmi_enable | irq_enable) & buttons_enable) begin
cmd_valid_r <= 1;
cmd_data_r <= pad_data_r;
end
end
end
assign snescmd_we_cheat = cmd_valid_r & button_valid & snescmd_rdy;
assign snescmd_addr_cheat = 9'h000;
assign snescmd_data_cheat = ( button_reset_game ? 8'h80 // reset to game
: button_reset_menu ? 8'h81 // reset to menu
: button_hook_dis ? 8'h84 // disable in-game hooks completely
: button_hook_dis_10 ? 8'h85 // disable in-game hooks for 10 seconds
: 8'h00
);
// These pulse for a single clock. The SGB CTX state machine decides whether to use or ignore them.
// override cheat bit to enable save states
assign button_ctx_valid = cheat_enable & cmd_valid_r & button_state;
assign button_ctx_mode = button_state_load; // 0=save 1=load
reg [7:0] dbg_data_r;
assign DBG_DATA_OUT = dbg_data_r;
always @(posedge clk) begin
casez(DBG_ADDR[3:0])
4'h0: dbg_data_r <= pad_valid_r;
4'h1: dbg_data_r <= cmd_valid_r;
4'h2: dbg_data_r <= pad_data_r[7:0];
4'h3: dbg_data_r <= pad_data_r[15:8];
4'h4: dbg_data_r <= cmd_data_r[7:0];
4'h5: dbg_data_r <= cmd_data_r[15:8];
4'h6: dbg_data_r <= snescmd_unlock_r;
4'h7: dbg_data_r <= hook_enable;
4'h8: dbg_data_r <= nmi_enable;
4'h9: dbg_data_r <= irq_enable;
4'hA: dbg_data_r <= buttons_enable;
4'hB: dbg_data_r <= cheat_enable;
4'hC: dbg_data_r <= snescmd_we_cheat;
4'hD: dbg_data_r <= snescmd_data_cheat;
4'hE: dbg_data_r <= button_state_save;
4'hF: dbg_data_r <= button_state_load;
default: dbg_data_r <= 0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x; int a; scanf( %d%d , &n, &x); int sum = 0; while (n--) { scanf( %d , &a); sum += a; } int count = 0; if (sum == 0) { } else { if (abs(sum) <= x) { count = 1; } else { count = abs(sum) / abs(x); if (abs(sum) % abs(x) != 0) count++; } } cout << count << endl; }
|
`timescale 1ns / 1ps
/*
Group Members: Thomas Hudson and Warren Seto
Lab Name: Combinational Logic
Project Name: eng312_proj2
Design Name: mux_four_to_one_test.v
Design Description: Verilog Test Fixture for a Four to One Multiplexer
*/
module mux_four_to_one_test;
// Inputs
reg [3:0] DIN;
reg [1:0] SEL;
// Outputs
wire DOUT;
// Instantiate two counter variables for both loop
integer count;
integer count2;
// Instantiate the Unit Under Test (UUT)
mux_four_to_one uut
(
.DIN(DIN),
.SEL(SEL),
.DOUT(DOUT)
);
initial begin
// Initialize Inputs
DIN = 0;
SEL = 0;
// Initialize counter variables
count = 0;
count2 = 0;
// Loops over the possible combinations for SEL and resets the value for DIN
for (count = 0; count < 4; count = count + 1) begin
SEL = count;
DIN = 0;
// Loops over the possible combinations for DIN for each SEL value
for (count2 = 0; count2 <= 16; count2 = count2 + 1) begin
#5 DIN = count2;
end
end
end
initial #340 $finish; // The test will run for a total interval of 340 nanoseconds
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SPI Slave Model ////
//// ////
//// ////
//// Authors: Richard Herveille () www.asics.ws ////
//// ////
//// http://www.opencores.org/projects/simple_spi/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: spi_slave_model.v,v 1.1 2004/02/28 15:32:54 rherveille Exp $
//
// $Date: 2004/02/28 15:32:54 $
// $Revision: 1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: spi_slave_model.v,v $
// Revision 1.1 2004/02/28 15:32:54 rherveille
// Added testbench
//
//
//
// Requires: Verilog2001
`include "timescale.v"
module spi_slave_model (
input wire csn;
input wire sck
input wire di;
output wire do
);
//
// Variable declaration
//
wire debug = 1'b1;
wire cpol = 1'b0;
wire cpha = 1'b0;
reg [7:0] mem [7:0]; // initiate memory
reg [2:0] mem_adr; // memory address
reg [7:0] mem_do; // memory data output
reg [7:0] sri, sro; // 8bit shift register
reg [2:0] bit_cnt;
reg ld;
wire clk;
//
// module body
//
assign clk = cpol ^ cpha ^ sck;
// generate shift registers
always @(posedge clk)
sri <= #1 {sri[6:0],di};
always @(posedge clk)
if (&bit_cnt)
sro <= #1 mem[mem_adr];
else
sro <= #1 {sro[6:0],1'bx};
assign do = sro[7];
//generate bit-counter
always @(posedge clk, posedge csn)
if(csn)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
//generate access done signal
always @(posedge clk)
ld <= #1 ~(|bit_cnt);
always @(negedge clk)
if (ld) begin
mem[mem_adr] <= #1 sri;
mem_adr <= #1 mem_adr + 1'b1;
end
initial
begin
bit_cnt=3'b111;
mem_adr = 0;
sro = mem[mem_adr];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_4_V
`define SKY130_FD_SC_LS__O22AI_4_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22ai_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_4_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 23:00:44 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_1_stub.v
// Design : zqynq_lab_1_design_xbar_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [95:0]m_axi_awaddr;
output [8:0]m_axi_awprot;
output [2:0]m_axi_awvalid;
input [2:0]m_axi_awready;
output [95:0]m_axi_wdata;
output [11:0]m_axi_wstrb;
output [2:0]m_axi_wvalid;
input [2:0]m_axi_wready;
input [5:0]m_axi_bresp;
input [2:0]m_axi_bvalid;
output [2:0]m_axi_bready;
output [95:0]m_axi_araddr;
output [8:0]m_axi_arprot;
output [2:0]m_axi_arvalid;
input [2:0]m_axi_arready;
input [95:0]m_axi_rdata;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rvalid;
output [2:0]m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int m = 0, k = 0, p = 0, i = 1; string s; cin >> s; int n, a[27]; cin >> n; for (i = 1; i < 27; i++) cin >> a[i], m = max(m, a[i]); for (i = 0; i < s.length(); i++) k += a[s[i] - 96] * (i + 1); while (n--) i++, p += i * m; cout << k + p; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int n; double p[maxn], dp[maxn]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lf , &p[i]); double sol = 0.; dp[0] = 0; for (int i = 1; i < n; i++) { dp[i] = (dp[i - 1] + p[i - 1]) * p[i]; sol += 2. * dp[i]; } for (int i = 0; i < n; i++) sol += p[i]; printf( %.9lf n , sol); return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; int a, b, c, d, i, j, n, m, k, ans, T; char str[200003]; int p[22], cs[22][22], dp[1 << 22]; pair<int, int> cur[26]; int main() { scanf( %d%d%d , &n, &k, &T); scanf( %s , str); for (int _n((k)-1), i(0); i <= _n; i++) scanf( %d , &p[i]); for (int _n((k)-1), i(0); i <= _n; i++) for (int _n((k)-1), j(0); j <= _n; j++) scanf( %d , &cs[i][j]); cur[0] = make_pair(-1, -1); int were = 0; for (int i = (n - 1), _b = (0); i >= _b; i--) { int mask = 0, t = str[i] - A ; were |= 1 << t; for (int _n((k)-1), j(0); j <= _n; j++) { if (cur[j].first == -1) break; dp[mask] += cs[t][cur[j].second]; dp[mask | 1 << t] -= cs[t][cur[j].second]; dp[mask | 1 << cur[j].second] -= cs[t][cur[j].second]; dp[mask | (1 << t) | (1 << cur[j].second)] += cs[t][cur[j].second]; mask |= 1 << cur[j].second; if (cur[j].second == t) break; } for (int _n((k)-1), j(0); j <= _n; j++) { if (cur[j].first == -1 || cur[j].second == t) { bool tt = 0; if (cur[j].first == -1) tt = 1; cur[j] = make_pair(i, t); for (int z = (j - 1), _b = (0); z >= _b; z--) swap(cur[z], cur[z + 1]); if (tt) cur[j + 1] = make_pair(-1, -1); break; } } } ans = 0; for (int _n((k)-1), i(0); i <= _n; i++) { for (int _n((were)-1), mask(0); mask <= _n; mask++) { if ((mask & were) != mask) continue; if (mask & 1 << i) dp[mask] += dp[mask ^ 1 << i]; } } for (int _n((were)-1), mask(0); mask <= _n; mask++) { if ((mask & were) != mask) continue; c = dp[mask]; for (int _n((k)-1), i(0); i <= _n; i++) if (mask & 1 << i) c += p[i]; if (c <= T) ++ans; } printf( %d n , ans); }
|
#include <iostream> #include <cstdio> #include <cassert> #include <cstring> #include <cmath> #include <functional> #include <algorithm> #include <utility> #include <vector> #include <string> #include <map> #include <set> using namespace std; using ll = long long; using PII = pair<int,int>; const ll inf = 1ll << 60; const int maxn = 200000 + 5; int n, s; struct DS { ll base = 0; map<int, ll> f; set<pair<ll,int> > bag; int size() { return f.size(); } bool count(int x) { return f.count(x); } ll get(int x) { if (f.count(x)) { return f[x] + base; } else { return inf; } } void set(int x, ll v) { if (f.count(x)) { v = std::min(v, erase(x)); } v -= base; f[x] = v; bag.emplace(v, x); } ll erase(int x) { if (f.count(x)) { ll val = f[x]; f.erase(x); bag.erase({ val, x }); return val + base; } else { return inf; } } ll min() { return bag.begin()->first + base; } }; int main() { scanf( %d%d , &n, &s); vector<DS> stk { {} }; vector<int> cond; stk.back().set(0, 0); for (int i = 1; i <= n; i++) { char op[8]; scanf( %s , op); if (op[0] == s ) { int x, v; scanf( %d%d , &x, &v); ll mn = stk.back().min(); stk.back().base += v; if (x != s) { stk.back().set(x, mn); } } else if (op[0] == i ) { int x; scanf( %d , &x); DS u; u.set(x, stk.back().get(x)); stk.back().erase(x); stk.push_back(u); cond.push_back(x); } else if (op[0] == e ) { int c = cond.back(); cond.pop_back(); int sz = stk.size(); auto& x = stk[sz - 1]; auto& y = stk[sz - 2]; if (x.size() > y.size()) swap(x, y); for (auto u: x.f) { y.set(u.first, x.get(u.first)); } stk.pop_back(); } } printf( %lld n , stk.back().min()); return 0; }
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/jp.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Joypad controller block.
***************************************************************************************************/
module jp(
input clk, // 100MHz system clock signal
input rst, // reset signal
input i_wr, // i_write enable signal
input [15:0] i_addr, // 16-bit memory i_address
input i_din, // data input bus
output reg [7:0] o_dout, // data output bus
input [7:0] i_jp1_state, //state of the joy pad 1
input [7:0] i_jp2_state //state of the joy pad 2
);
//Local Parameters
localparam [15:0] JOYPAD1_MMR_ADDR = 16'h4016;
localparam [15:0] JOYPAD2_MMR_ADDR = 16'h4017;
//Registers/Wires
reg [15:0] r_prev_addr;
wire w_new_addr;
reg r_wrote_1_flag;
reg [8:0] r_jp1_state;
reg [8:0] r_jp2_state;
//Submodules
//Asynchronous Logic
assign w_new_addr = (r_prev_addr != i_addr);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_dout <= 0;
r_prev_addr <= 0;
r_wrote_1_flag <= 0;
r_jp1_state <= 0;
r_jp2_state <= 0;
end
else begin
//Only process a command when i_address changes from not this i_address to this i_address
if (i_addr[15:1] == JOYPAD1_MMR_ADDR[15:1]) begin
//User has accessed the joypad register(s), depeni_ding on the last
//bit send the appropriate joystick information (1 or 2)
o_dout <= { 7'h00, ((i_addr[0]) ? r_jp2_state[0] : r_jp1_state[0]) };
if (w_new_addr) begin
if (i_wr && !i_addr[0]) begin
if (!r_wrote_1_flag) begin
if (i_din == 1'b1) begin
r_wrote_1_flag <= 1;
end
end
else begin
if (i_din == 1'b0) begin
r_wrote_1_flag <= 0;
r_jp1_state <= {i_jp1_state, 1'b0};
r_jp2_state <= {i_jp2_state, 1'b0};
end
end
end
//Shift appropriate JP read state on every read, after 8 reads, all subsequent reads should be 1
else if (!i_wr && !i_addr[0]) begin
r_jp1_state <= {1'b1, r_jp1_state[8:1]};
end
else if (!i_wr && i_addr[0]) begin
r_jp2_state <= {1'b1, r_jp2_state[8:1]};
end
end
end
r_prev_addr <= i_addr;
end
end
endmodule
|
#include <bits/stdc++.h> const int maxn = 100001; int n, i, u, v, top, a[maxn], spt[maxn], vt[maxn], st[maxn], l[maxn]; long long sum, ans, tmp, val[maxn], uc, bc, ss, min; std::vector<int> adj[maxn]; void dfs() { top = 1; st[1] = 1; while (top > 0) { u = st[top]; if (vt[u] < spt[u] && adj[u][vt[u]] == st[top - 1]) vt[u]++; if (vt[u] < spt[u]) { if (u == 1) tmp *= spt[u]; else tmp *= (spt[u] - 1); if (tmp > sum) { ans = -1; return; } st[++top] = adj[u][vt[u]]; vt[u]++; } else { if (spt[u] == 1 && u != 1) { val[u] = tmp; uc = tmp; l[++l[0]] = u; } top--; if (st[top] == 1) tmp /= spt[st[top]]; else tmp /= (spt[st[top]] - 1); } } } long long ucln(long long a, long long b) { while (a > 0 && b > 0) if (a > b) a %= b; else b %= a; if (a > 0) return a; else return b; } int main() { std::cin >> n; for (i = 1; i <= n; i++) { std::cin >> a[i]; sum += a[i]; } for (i = 1; i < n; i++) { std::cin >> u >> v; spt[u]++; spt[v]++; adj[u].push_back(v); adj[v].push_back(u); } tmp = 1; dfs(); if (ans == -1) { std::cout << sum; return 0; } bc = val[l[1]]; for (i = 2; i <= l[0]; i++) { uc = ucln(bc, val[l[i]]); bc /= uc; if (bc > double(sum) / val[i]) { std::cout << sum; return 0; } bc *= val[l[i]]; } min = 1000000000000000000; for (i = 1; i <= l[0]; i++) { val[l[i]] = bc / val[l[i]]; if (min > a[l[i]] / val[l[i]]) min = a[l[i]] / val[l[i]]; } if (min == 0) { std::cout << sum; return 0; } for (i = 1; i <= l[0]; i++) ans += a[l[i]] - val[l[i]] * min; std::cout << ans; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/03/2014 07:21:44 PM
// Design Name:
// Module Name: seven_seg
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seven_seg(
input clk,
input signed [5:0] shift_val,
input signed [5:0] vshift_val,
output reg [7:0] anode,
output reg [7:0] segments
);
reg [7:0] anodestate;
reg [7:0] gotostate;
reg [5:0] abs_shift_val;
reg [5:0] abs_vshift_val;
initial begin
anode = {8 {1'b1}};
anodestate = 8'b10111111;
gotostate = 8'b10111111;
end
always @(posedge clk) begin
abs_shift_val = (shift_val[5] ? ~shift_val+1 : shift_val);
abs_vshift_val = (vshift_val[5] ? ~vshift_val+1 : vshift_val);
anode = anodestate;
case (anode)
// vertical shift display
8'b10111111: begin
segments = (vshift_val < 0) ? 8'b1011_1111 : 8'b1111_1111;
gotostate = 8'b11011111;
anodestate = 8'b11111111;
end
8'b11011111: begin
case (abs_vshift_val)
4,
5,
6: segments = 8'b1111_1001; // 1
7,
8: segments = 8'b1010_0100; // 2
9,
10,
11: segments = 8'b1011_0000; // 3
12,
13: segments = 8'b1001_1001; // 4
14,
15: segments = 8'b1001_0010; // 5
16: segments = 8'b1000_0010; // 6
17: segments = 8'b1111_1000; // 7
endcase
//segments = (abs_vshift_val > 9) ? 8'b1111_1001 : 8'b1111_1111;
gotostate = 8'b11101111;
anodestate = 8'b11111111;
end
8'b11101111: begin
case (abs_vshift_val)
0,
9: segments = 8'b1100_0000; // 0
14,
17: segments = 8'b1111_1001; // 1
4,
12: segments = 8'b1010_0100; // 2 // saving donuts for friends
1,
7,
10,
16: segments = 8'b1011_0000; // 3
//: segments = 8'b1001_1001; // 4
//: segments = 8'b1001_0010; // 5
2,
5,
8,
13,
15: segments = 8'b1000_0010; // 6
11: segments = 8'b1111_1000; // 7
3,
6: segments = 8'b1001_0000; // 9
endcase
/*case (abs_vshift_val[2:0])
3'b000: segments = abs_vshift_val[3] ? 8'b1000_0000 : 8'b1100_0000; // 8 and 0
3'b001: segments = abs_vshift_val[3] ? 8'b1001_0000 : 8'b1111_1001; // 9 and 1
3'b010: segments = 8'b1010_0100; // 2
3'b011: segments = 8'b1011_0000; // 3
3'b100: segments = 8'b1001_1001; // 4
3'b101: segments = 8'b1001_0010; // 5
3'b110: segments = 8'b1000_0010; // 6
3'b111: segments = 8'b1111_1000; // 7
default: segments = 8'b1111_1111;
endcase*/
gotostate = 8'b11111011;
anodestate = 8'b11111111;
end
// horizontal shift display
8'b11111011: begin
segments = (shift_val < 0) ? 8'b1011_1111 : 8'b1111_1111;
gotostate = 8'b11111101;
anodestate = 8'b11111111;
end
8'b11111101: begin
case (abs_shift_val)
4,
5,
6: segments = 8'b1111_1001; // 1
7,
8: segments = 8'b1010_0100; // 2
9,
10,
11: segments = 8'b1011_0000; // 3
12,
13: segments = 8'b1001_1001; // 4
14,
15: segments = 8'b1001_0010; // 5
16: segments = 8'b1000_0010; // 6
17: segments = 8'b1111_1000; // 7
endcase
//segments = (abs_shift_val > 9) ? 8'b1111_1001 : 8'b1111_1111;
gotostate = 8'b11111110;
anodestate = 8'b11111111;
end
8'b11111110: begin
case (abs_shift_val)
0,
9: segments = 8'b1100_0000; // 0
14,
17: segments = 8'b1111_1001; // 1
4,
12: segments = 8'b1010_0100; // 2 // saving donuts for friends
1,
7,
10,
16: segments = 8'b1011_0000; // 3
//: segments = 8'b1001_1001; // 4
//: segments = 8'b1001_0010; // 5
2,
5,
8,
13,
15: segments = 8'b1000_0010; // 6
11: segments = 8'b1111_1000; // 7
3,
6: segments = 8'b1001_0000; // 9
endcase
/*case (abs_shift_val[2:0])
3'b000: segments = abs_shift_val[3] ? 8'b1000_0000 : 8'b1100_0000;
3'b001: segments = abs_shift_val[3] ? 8'b1001_0000 : 8'b1111_1001;
3'b010: segments = 8'b1010_0100;
3'b011: segments = 8'b1011_0000;
3'b100: segments = 8'b1001_1001;
3'b101: segments = 8'b1001_0010;
3'b110: segments = 8'b1000_0010;
3'b111: segments = 8'b1111_1000;
default: segments = 8'b1111_1111;
endcase*/
gotostate = 8'b10111111;
anodestate = 8'b11111111;
end
8'b11111111: begin
// clear cathodes between displays
segments = 8'b1111_1111;
anodestate = gotostate;
end
default: begin
segments = 8'b1111_1111;
anodestate = 8'b11111111;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, CA, CB; struct point { int x, y; bool operator<(const point &p) const { return x != p.x ? x < p.x : y < p.y; } } st[201000]; int BX[201000], EX[201000], BY[201000], EY[201000]; long long res; void Pro(vector<point> &w, int *B, int *E) { int i; int top = 0; for (auto &tp : w) { while (top && st[top].x + st[top].y >= tp.x + tp.y) top--; if (top && st[top].y - st[top].x <= tp.y - tp.x) continue; st[++top] = tp; } int pv = 1; for (i = 1; i <= 200020; i++) { while (pv < top && st[pv].y + abs(i - st[pv].x) >= st[pv + 1].y + abs(i - st[pv + 1].x)) pv++; B[i] = st[pv].y + abs(i - st[pv].x); } top = 0; for (auto &tp : w) { while (top && st[top].y - st[top].x <= tp.y - tp.x) top--; if (top && st[top].y + st[top].x >= tp.y + tp.x) continue; st[++top] = tp; } pv = 1; for (i = 1; i <= 200020; i++) { while (pv < top && st[pv].y - abs(i - st[pv].x) <= st[pv + 1].y - abs(i - st[pv + 1].x)) pv++; E[i] = st[pv].y - abs(i - st[pv].x); if (B[i] > E[i]) B[i] = 1, E[i] = 0; } } struct AA { int t, y, ck; bool operator<(const AA &p) const { return t < p.t; } } T[401000]; int BIT[201000][2]; void Add(int a, int ck, int b) { while (a <= 200020) { BIT[a][ck] += b; a += (a & -a); } } int Sum(int a, int ck) { if (a < 0) return 0; int r = 0; while (a) { r += BIT[a][ck]; a -= (a & -a); } return r; } void Do(vector<point> w, int ck) { if (w.empty()) return; int i; sort(w.begin(), w.end()); Pro(w, BX, EX); for (i = 0; i < w.size(); i++) swap(w[i].x, w[i].y); sort(w.begin(), w.end()); Pro(w, BY, EY); int cnt = 0; for (i = 1; i <= 200020; i++) { BIT[i][0] = BIT[i][1] = 0; T[cnt++] = {BY[i], i, 1}; T[cnt++] = {EY[i] + 1, i, -1}; } sort(T, T + cnt); int pv = 0; for (i = 1; i <= 200020; i++) { while (pv < cnt && T[pv].t <= i) { Add(T[pv].y, T[pv].y % 2, T[pv].ck); pv++; } if (BX[i] > EX[i]) continue; res += Sum(EX[i], (ck + i) % 2) - Sum(BX[i] - 1, (ck + i) % 2); } } int main() { int i, x, y; scanf( %d , &n); vector<point> A, B; for (i = 1; i <= n; i++) { scanf( %d%d , &x, &y); x += 1e5 + 10; y += 1e5 + 10; if ((x + y) % 2) { A.push_back({x, y}); } else { B.push_back({x, y}); } } Do(A, 0); Do(B, 1); printf( %lld n , res); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int x[n], y[n], h[n], a[n]; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i]; } for (int i = 0; i < n; i++) { h[i] = n - 1; a[i] = 0; } int home[1000000] = {0}, away[1000000] = {0}; for (int i = 0; i < n; i++) { home[x[i]]++; away[y[i]]++; } for (int i = 0; i < n; i++) { if (home[y[i]] > 0) h[i] += home[y[i]]; } for (int i = 0; i < n; i++) { a[i] = 2 * (n - 1) - h[i]; } for (int i = 0; i < n; i++) cout << h[i] << << a[i] << endl; return 0; }
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* CLOCK_SIGNAL = "yes", WAVEFORM = "0 5" *)
input clk,
input clk2,
input [1:0] in,
output [5:0] out
);
reg [1:0] cnt = 0;
wire clk_int_1, clk_int_2;
IBUF ibuf_proxy (
.I(clk),
.O(ibuf_proxy_out)
);
IBUF ibuf_inst (
.I(ibuf_proxy_out),
.O(ibuf_out)
);
assign clk_int_1 = ibuf_out;
assign clk_int_2 = clk_int_1;
always @(posedge clk_int_2) begin
cnt <= cnt + 1;
end
middle middle_inst_1 (
.clk(ibuf_out),
.out(out[2])
);
middle middle_inst_2 (
.clk(clk_int_1),
.out(out[3])
);
middle middle_inst_3 (
.clk(clk_int_2),
.out(out[4])
);
middle middle_inst_4 (
.clk(clk2),
.out(out[5])
);
assign out[1:0] = {cnt[0], in[0]};
endmodule
module middle (
input clk,
output out
);
reg [1:0] cnt = 0;
wire clk_int;
assign clk_int = clk;
always @(posedge clk_int) begin
cnt <= cnt + 1;
end
assign out = cnt[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, k; cin >> n >> k; vector<int> s[k]; for (int i = 0; i < k; ++i) { int c; cin >> c; for (int j = 0; j < c; ++j) { int p; cin >> p; s[i].push_back(p); } } cout << ? << n << ; for (int i = 1; i <= n; i++) cout << i << ; cout << n ; int max; cin >> max; int l = 1, r = n; while (l < r) { int mid = (l + r) / 2; cout << ? << mid - l + 1 << ; for (int i = l; i <= mid; i++) cout << i << ; cout << n ; int temp; cin >> temp; if (temp == max) r = mid; else l = mid + 1; } int sind = 0; for (int i = 0; i < k; ++i) { for (int j : s[i]) { if (j == l) { sind = i; break; } } } int smax; cout << ? << n - s[sind].size() << ; for (int i = 1; i <= n; i++) { bool flag = true; for (int j : s[sind]) if (j == i) flag = false; if (flag) cout << i << ; } cout << n ; cin >> smax; cout << ! ; for (int i = 0; i < k; i++) { if (i == sind) cout << smax << ; else cout << max << ; } cout << n ; string x; cin >> x; } }
|
#include <bits/stdc++.h> using namespace std; void qmax(long long &x, long long y) { if (x < y) x = y; } void qmin(long long &x, long long y) { if (x > y) x = y; } inline long long read() { char s; long long k = 0, base = 1; while ((s = getchar()) != - && s != EOF && !(isdigit(s))) ; if (s == EOF) exit(0); if (s == - ) base = -1, s = getchar(); while (isdigit(s)) { k = k * 10 + (s ^ 0 ); s = getchar(); } return k * base; } inline void write(long long x) { static char cnt, num[15]; cnt = 0; if (!x) { printf( 0 ); return; } for (; x; x /= 10) num[++cnt] = x % 10; for (; cnt; putchar(num[cnt--] + 48)) ; } long long n, l[70], x, f[70], ans[2001010]; vector<long long> a[70]; long long flag; signed main() { n = read(); for (long long i = 1; i <= n; i++) { x = read(); for (long long i = 59; i >= 0; i--) { if (x & (1ll << i)) { a[i].push_back(x); l[i]++; break; } } } long long lst = 0; for (long long i = 0; i < 60; i++) if (l[i] != 0) sort(a[i].begin(), a[i].end()); for (long long j = 1; j <= n; j++) { flag = 0; for (long long i = 0; i < 60; i++) { if (f[i] == l[i]) continue; if (((lst >> (long long)i) & 1ll) != 0) continue; f[i]++; ans[j] = a[i][f[i] - 1]; flag = 1; lst ^= ans[j]; break; } if (!flag) break; } if (!flag) { printf( No ); return 0; } printf( Yes n ); for (long long i = 1; i <= n; i++) { printf( %lld , ans[i]); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A221O_BEHAVIORAL_PP_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_BEHAVIORAL_PP_V
|
/* lab3_part3.v - Master Slave D latch
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
+--------------------------------------+
| +------+ Qm +------+ |
D --+-----+D Q+--------------+D Q+---+-- Q
| | | | | |
| ~ | _| | _| | _
Clk -+-+--- Clk Q| +--Clk Q+---+-- Q
| | +------+ | +------+ |
| | | |
| +-----------------------+ |
| |
+--------------------------------------+
+-------------+
|D Q > Qnext|
|0 X F 0 |
|1 X F 1 |
+-------------+
*/
module lab3_part3 (SW, LEDR, LEDG);
input [1:0] SW;
output [1:0] LEDR, LEDG;
assign LEDR = SW;
wire Q;
MSDF F0(SW[1],SW[0],LEDG[0]);
endmodule
module MSDF(Clk, D, Q);
input Clk, D;
output Q;
wire Qm;
Dflop D0 (~Clk, D, Qm);
Dflop D1 (Clk, Qm, Q);
endmodule
module Dflop (Clk, D, Q);
input Clk, D;
output Q;
wire S, R;
assign S = D;
assign R = ~D;
wire R_g, S_g, Qa, Qb /* synthesis keep */;
/* S_g truth table
+--+---+----+
| D|Clk|S_g |
| 0| 0 | 1 |
| 0| 1 | 1 |
| 1| 0 | 1 |
| 1| 1 | 0 |
+--+---+----+
*/
assign S_g = S & Clk;
/* R_g truth table
+--+---+----+
| D|Clk|R_g |
| 0| 0 | 1 |
| 0| 1 | 0 |
| 1| 0 | 1 |
| 1| 1 | 1 |
+--+---+----+
*/
assign R_g = R & Clk;
assign Qa = ~(R_g | Qb);
assign Qb = ~(S_g | Qa);
assign Q = Qa;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_1_V
`define SKY130_FD_SC_HD__NAND4B_1_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4b_1 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4b_1 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_1_V
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconstant_0_1 (
dout
);
output wire [7-1 : 0] dout;
xlconstant #(
.CONST_VAL(7'd0),
.CONST_WIDTH(7)
) inst (
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1e9 + 7; int dx[4] = {0, 1, 0, -1}; int dy[4] = {1, 0, -1, 0}; int main() { int n; cin >> n; string s; cin >> s; s += . ; n++; vector<pair<char, int>> a; int c = s[0]; int cnt = 1; for (int i = 1; i < n; i++) { if (c == s[i]) { cnt++; } else { a.push_back({c, cnt}); c = s[i]; cnt = 1; } } for (int i = 0; i < a.size(); i++) { if (a[i].first == a || a[i].first == e || a[i].first == i || a[i].first == o || a[i].first == u || a[i].first == y ) { if ((a[i].first == e || a[i].first == o ) && a[i].second == 2) { cout << a[i].first << a[i].first; } else { cout << a[i].first; } } else { for (int j = 0; j < a[i].second; j++) cout << a[i].first; } } cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S6S_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DLYMETAL6S6S_PP_SYMBOL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlymetal6s6s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S6S_PP_SYMBOL_V
|
`timescale 1ns / 1ps
// This module is a third order delta/sigma modulator
// It uses no multiply only shifts by 1, 2 or 13
// There are only 7 adders used, it takes around 110 LUTs
module hq_dac
(
input reset,
input clk,
input clk_ena,
input [19:0] pcm_in,
output reg dac_out
);
// ======================================
// ============== Stage #1 ==============
// ======================================
wire [23:0] w_data_in_p0;
wire [23:0] w_data_err_p0;
wire [23:0] w_data_int_p0;
reg [23:0] r_data_fwd_p1;
// PCM input extended to 24 bits
assign w_data_in_p0 = { {4{pcm_in[19]}}, pcm_in };
// Error between the input and the quantizer output
assign w_data_err_p0 = w_data_in_p0 - w_data_qt_p2;
// First integrator adder
assign w_data_int_p0 = { {3{w_data_err_p0[23]}}, w_data_err_p0[22:2] } // Divide by 4
+ r_data_fwd_p1;
// First integrator forward delay
always @(posedge reset or posedge clk)
if (reset)
r_data_fwd_p1 <= 24'd0;
else if (clk_ena)
r_data_fwd_p1 <= w_data_int_p0;
// ======================================
// ============== Stage #2 ==============
// ======================================
wire [23:0] w_data_fb1_p1;
wire [23:0] w_data_fb2_p1;
wire [23:0] w_data_lpf_p1;
reg [23:0] r_data_lpf_p2;
// Feedback from the quantizer output
assign w_data_fb1_p1 = { {3{r_data_fwd_p1[23]}}, r_data_fwd_p1[22:2] } // Divide by 4
- { {3{w_data_qt_p2[23]}}, w_data_qt_p2[22:2] }; // Divide by 4
// Feedback from the third stage
assign w_data_fb2_p1 = w_data_fb1_p1
- { {14{r_data_fwd_p2[23]}}, r_data_fwd_p2[22:13] }; // Divide by 8192
// Low pass filter
assign w_data_lpf_p1 = w_data_fb2_p1 + r_data_lpf_p2;
// Low pass filter feedback delay
always @(posedge reset or posedge clk)
if (reset)
r_data_lpf_p2 <= 24'd0;
else if (clk_ena)
r_data_lpf_p2 <= w_data_lpf_p1;
// ======================================
// ============== Stage #3 ==============
// ======================================
wire [23:0] w_data_fb3_p1;
wire [23:0] w_data_int_p1;
reg [23:0] r_data_fwd_p2;
// Feedback from the quantizer output
assign w_data_fb3_p1 = { {2{w_data_lpf_p1[23]}}, w_data_lpf_p1[22:1] } // Divide by 2
- { {2{w_data_qt_p2[23]}}, w_data_qt_p2[22:1] }; // Divide by 2
// Second integrator adder
assign w_data_int_p1 = w_data_fb3_p1 + r_data_fwd_p2;
// Second integrator forward delay
always @(posedge reset or posedge clk)
if (reset)
r_data_fwd_p2 <= 24'd0;
else if (clk_ena)
r_data_fwd_p2 <= w_data_int_p1;
// =====================================
// ========== 1-bit quantizer ==========
// =====================================
wire [23:0] w_data_qt_p2;
assign w_data_qt_p2 = (r_data_fwd_p2[23]) ? 24'hF00000 : 24'h100000;
always @(posedge reset or posedge clk)
if (reset)
dac_out <= 1'b0;
else if (clk_ena)
dac_out <= ~r_data_fwd_p2[23];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, h; bool ok(long long x) { long long ans = 0; if (x >= 2e9) return 1; if (x <= h) ans = x * (x + 1) / 2; else { ans = h * (h + 1) / 2 + (x - h) * h; long long high = x - h - 1; long long t1 = high / 2, t2 = high - t1; ans += t1 * (t1 + 1) / 2 + t2 * (t2 + 1) / 2; } if (ans >= n) return 1; else return 0; } int main() { cin >> n >> h; long long l = 1, r = 1e18 + 1; long long mid = (l + r) / 2; while (l < r) { mid = (l + r) / 2; if (ok(mid)) r = mid; else l = mid + 1; } printf( %lld n , l); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 4000010, maxm = 2010; long long s[maxn], f[maxn], P[maxm], Q[maxm]; int a, b, c, p[maxm], vis[maxm], mu[maxm]; void inc(long long &a, long long b) { a += b; if (a > (1ll << 30)) a -= (1ll << 30); } int main() { scanf( %d%d%d , &a, &b, &c); mu[1] = 1; for (int i = 2; i <= c; i++) { if (!vis[i]) p[++p[0]] = i, mu[i] = -1; for (int j = 1; j <= p[0] && i * p[j] <= c; j++) { vis[i * p[j]] = 1; if (i % p[j] == 0) { mu[i * p[j]] = 0; break; } else mu[i * p[j]] = -mu[i]; } } for (int i = 1; i <= a; i++) for (int j = 1; j <= b; j++) f[i * j]++; for (int i = 1; i <= a * b; i++) for (int j = 1; j <= a * b / i; j++) inc(s[i], f[i * j]); for (int i = 1; i <= c; i++) for (int j = 1; j <= a * b / i; j++) inc(P[i], s[i * j]); for (int i = 1; i <= c; i++) for (int j = 1; j <= i; j++) inc(Q[i], i / j); long long ans = 0; for (int i = 1; i <= c; i++) ans = (ans + mu[i] * P[i] * Q[c / i] % (1ll << 30)) % (1ll << 30); printf( %I64d , (ans + (1ll << 30)) % (1ll << 30)); return 0; }
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_id_track.v
// Version : v1.0
// Description: To track the id received against the stored id.
// ARID and RID are tracked in case of read operations.
// AWID and BID are tracked in case of write operations.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_id_track
#(
parameter ID_WIDTH = 1
) (
input Clk ,
input rst_l ,
input [ID_WIDTH-1:0] in_push_id ,
input in_push ,
input [ID_WIDTH-1:0] in_search_id ,
input [3:0] in_clear_pos ,
input in_only_entry0,
output [3:0] out_push_pos ,
output [3:0] out_search_hit,
output [3:0] out_free
);
reg [ID_WIDTH:0] id_arr0_ff, id_arr1_ff, id_arr2_ff, id_arr3_ff;
reg [3:0] push_pos_ff, push_pos_2ff;
reg [3:0] in_clear_pos_ff;
wire [ID_WIDTH:0] push_id = { 1'b1, in_push_id[ID_WIDTH-1:0] };
wire [3:0] push_search = { (push_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0]) };
wire [3:0] free_pre = { ~id_arr3_ff[ID_WIDTH], ~id_arr2_ff[ID_WIDTH],
~id_arr1_ff[ID_WIDTH], ~id_arr0_ff[ID_WIDTH] };
wire [3:0] free = (in_only_entry0) ? { 3'b000, free_pre[0] } : free_pre[3:0];
wire [3:0] first_free = (free[0]) ? 4'h1 :
(free[1]) ? 4'h2 :
(free[2]) ? 4'h4 :
(free[3]) ? 4'h8 : 4'h0;
wire [3:0] push_pos = (in_push == 1'b0) ? 4'h0 :
(push_search[3:0] != 4'h0) ? push_search[3:0] :
first_free[3:0];
wire [ID_WIDTH:0] search_id = { 1'b1, in_search_id[ID_WIDTH-1:0] };
wire [3:0] search_pos = { (search_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0]) };
wire [3:0] do_clear = ~push_pos_ff[3:0] & ~push_pos_2ff[3:0] &
in_clear_pos_ff[3:0];
wire [ID_WIDTH:0] id_arr0 = (push_pos[0]) ? push_id[ID_WIDTH:0] :
{ (do_clear[0]) ? 1'b0:id_arr0_ff[ID_WIDTH], id_arr0_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr1 = (push_pos[1]) ? push_id[ID_WIDTH:0] :
{ (do_clear[1]) ? 1'b0:id_arr1_ff[ID_WIDTH], id_arr1_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr2 = (push_pos[2]) ? push_id[ID_WIDTH:0] :
{ (do_clear[2]) ? 1'b0:id_arr2_ff[ID_WIDTH], id_arr2_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr3 = (push_pos[3]) ? push_id[ID_WIDTH:0] :
{ (do_clear[3]) ? 1'b0:id_arr3_ff[ID_WIDTH], id_arr3_ff[ID_WIDTH-1:0] };
always @(posedge Clk) begin
id_arr0_ff[ID_WIDTH:0] <= (rst_l) ? id_arr0[ID_WIDTH:0] : 1'b0;
id_arr1_ff[ID_WIDTH:0] <= (rst_l) ? id_arr1[ID_WIDTH:0] : 1'b0;
id_arr2_ff[ID_WIDTH:0] <= (rst_l) ? id_arr2[ID_WIDTH:0] : 1'b0;
id_arr3_ff[ID_WIDTH:0] <= (rst_l) ? id_arr3[ID_WIDTH:0] : 1'b0;
push_pos_ff[3:0] <= (rst_l) ? push_pos[3:0] : 4'h0;
push_pos_2ff[3:0] <= (rst_l) ? push_pos_ff[3:0] : 4'h0;
in_clear_pos_ff[3:0] <= (rst_l) ? in_clear_pos[3:0] : 4'h0;
end
assign out_search_hit[3:0] = search_pos[3:0];
assign out_push_pos[3:0] = push_pos[3:0];
assign out_free[3:0] = free[3:0];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 08/16/2011
// Module Name: display_clk
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: This module is a simple clock divider that produces the clock signal
// used in display controller.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module display_clk(
clk,
RST,
dclk
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input clk;
input RST;
output dclk;
// ==============================================================================
// Parameters, Registers, and Wires
// ==============================================================================
parameter [15:0] CNTENDVAL = 16'b1011011100110101;
reg [15:0] cntval;
// ==============================================================================
// Implementation
// ==============================================================================
//--------------------------------------
// Clock Divider Process
//--------------------------------------
always @(posedge clk)
begin
if (RST == 1'b1)
cntval <= {16{1'b0}};
else
if (cntval == CNTENDVAL)
cntval <= {16{1'b0}};
else
cntval <= cntval + 1'b1;
end
// Assign output clock
assign dclk = cntval[15];
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clamp.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Clamp
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current/Clamp
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Clamp
(
preIntegrator,
preSat,
saturated,
Clamp
);
input signed [35:0] preIntegrator; // sfix36_En29
input signed [35:0] preSat; // sfix36_En23
input saturated;
output Clamp;
wire Compare_To_Zero_out1;
wire Compare_To_Zero1_out1;
wire Compare_To_Zero_out1_1;
wire Logical_Operator_out1;
// <S9>/Compare To Zero
assign Compare_To_Zero_out1 = (preIntegrator <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S9>/Compare To Zero1
assign Compare_To_Zero1_out1 = (preSat <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S9>/Logical Operator
assign Compare_To_Zero_out1_1 = ~ (Compare_To_Zero_out1 ^ Compare_To_Zero1_out1);
// <S9>/AND
assign Logical_Operator_out1 = Compare_To_Zero_out1_1 & saturated;
assign Clamp = Logical_Operator_out1;
endmodule // velocityControlHdl_Clamp
|
/*
* Redistributions of any form whatsoever must retain and/or include the
* following acknowledgment, notices and disclaimer:
*
* This product includes software developed by Carnegie Mellon University.
*
* Copyright (c) 2004 by Babak Falsafi and James Hoe,
* Computer Architecture Lab at Carnegie Mellon (CALCM),
* Carnegie Mellon University.
*
* This source file was written and maintained by Jared Smolens
* as part of the Two-Way In-Order Superscalar project for Carnegie Mellon's
* Introduction to Computer Architecture course, 18-447. The source file
* is in part derived from code originally written by Herman Schmit and
* Diana Marculescu.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* If you modify the software you must place a notice on or within any
* modified version provided or made available to any third party stating
* that you have modified the software. The notice shall include at least
* your name, address, phone number, email address and the date and purpose
* of the modification.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANYWARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
`include "mips_defines.vh"
module mips_syscallUnit (/*AUTOARG*/
// Outputs
syscall_halt,
// Inputs
pc, r_v0, Sys, rst_b, clk
);
output wire syscall_halt;
input [31:0] pc, r_v0;
input Sys, rst_b, clk;
assign syscall_halt = rst_b && Sys && (r_v0 == `SYS_EXIT);
// synthesis translate_off
always @(posedge clk)
if (rst_b && Sys)
case(r_v0)
`SYS_EXIT: begin
$display(`MSG_EOP_S, pc);
end
endcase
// synthesis translate_on
endmodule
|
`timescale 1ns / 100ps
module QMFIR_uart_top(/*AUTOARG*/
// Outputs
uart_tx,
// Inputs
uart_rx, clk, arst_n
);
output uart_tx;
input uart_rx;
input clk;
input arst_n;
wire arst_n;
wire [15:0] MEMDAT;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire reg_we; // From uart_ of QMFIR_uart_if.v
wire [13:0] uart_addr; // From uart_ of QMFIR_uart_if.v
wire [31:0] uart_dout; // From uart_ of QMFIR_uart_if.v
wire uart_mem_re; // From uart_ of QMFIR_uart_if.v
wire uart_mem_we; // From uart_ of QMFIR_uart_if.v
// End of automatics
wire [23:0] uart_mem_i;
reg [23:0] uart_reg_i; //combinatory
//iReg
wire [15:0] ESCR;
wire [15:0] WPTR;
wire [15:0] ICNT;
wire [15:0] FREQ;
wire [15:0] OCNT;
wire [15:0] FCNT;
wire [31:0] firin;
//bram out
wire [15:0] MEMDATR1;
wire [15:0] MEMDATI1;
wire [15:0] MEMDATR2;
wire [15:0] MEMDATI2;
wire [15:0] MEMDATR3;
wire [15:0] MEMDATI3;
//bram in
wire [6:0] mem_addrr1;
wire [6:0] mem_addri1;
wire [6:0] mem_addrr2;
wire [6:0] mem_addri2;
wire [6:0] mem_addrr3;
wire [6:0] mem_addri3;
wire [13:0] bramin_addr;
assign arst = ~arst_n;
QMFIR_uart_if uart_(/*AUTOINST*/
// Outputs
.uart_dout (uart_dout[31:0]),
.uart_addr (uart_addr[13:0]),
.uart_mem_we (uart_mem_we),
.uart_mem_re (uart_mem_re),
.reg_we (reg_we),
.uart_tx (uart_tx),
// Inputs
.uart_mem_i (uart_mem_i[23:0]),
.uart_reg_i (uart_reg_i[23:0]),
.clk (clk),
.arst_n (arst_n),
.uart_rx (uart_rx));
BRAM_larg bramin_(//outputs
.doutb(firin), //32 bit
//inputs
.clka(clk),
.clkb(clk),
.addra(bramin_addr), //14 bit
.addrb(FCNT[13:0]), //14 bit
.dina(uart_dout), //32 bit
.wea(uart_mem_we));
QM_FIR QM_FIR(//outputs
.RealOut1 (RealOut1),
.RealOut2 (RealOut2),
.RealOut3 (RealOut2),
.ImagOut1 (ImagOut1),
.ImagOut2 (ImagOut2),
.ImagOut3 (ImagOut3),
.DataValid (DataValid),
//inputs
.CLK (clk),
.ARST (arst),
.InputValid (ESCR[3]),
.dsp_in0 (firin[31:24]),
.dsp_in1 (firin[23:16]),
.dsp_in2 (firin[15:8]),
.dsp_in3 (firin[7:0]),
.freq (ESCR[15]),
.newFreq (ESCR[6:0]));
iReg ireg_ (//outputs
.ESCR(ESCR),
.WPTR(WPTR),
.ICNT(ICNT),
.FREQ(FREQ),
.OCNT(OCNT),
.FCNT(FCNT),
//inputs
.clk(clk),
.arst(arst),
.idata(uart_dout),
.iaddr(uart_addr),
.iwe(reg_we),
.FIR_WE(DataValid),
.WFIFO_WE(uart_mem_we)
);
BRAM real1_ (//outputs
.doutb(MEMDATR1[15:0]),
//inputs
.clka(clk),
.clkb(clk),
.addra(WPTR[9:0]),
.addrb(mem_addrr1),
.dina(RealOut1),
.wea(DataValid));
BRAM imag1_ (//outputs
.doutb(MEMDATI1[15:0]),
//inputs
.clka(clk),
.clkb(clk),
.addra(WPTR[9:0]),
.addrb(mem_addri1),
.dina(ImagOut1),
.wea(DataValid));
BRAM real2_ (//outputs
.doutb(MEMDATR2[15:0]),
//inputs
.clka(clk),
.clkb(clk),
.addra(WPTR[9:0]),
.addrb(mem_addrr2),
.dina(RealOut2),
.wea(DataValid));
BRAM imag2_ (//outputs
.doutb(MEMDATI2[15:0]),
//inputs
.clka(clk),
.clkb(clk),
.addra(WPTR[9:0]),
.addrb(mem_addri2),
.dina(ImagOut2),
.wea(DataValid));
BRAM real3_ (//outputs
.doutb(MEMDATR3[15:0]),
//inputs
.clka(clk),
.clkb(clk),
.addra(WPTR[9:0]),
.addrb(mem_addrr3),
.dina(RealOut3),
.wea(DataValid));
BRAM imag3_ (//outputs
.doutb(MEMDATI3[15:0]),
//inputs
.clka(clk),
.clkb(clk),
.addra(WPTR[9:0]),
.addrb(mem_addri3),
.dina(ImagOut3),
.wea(DataValid));
// BRAM in interface
assign bramin_addr[13:0] = {(14){uart_mem_we}} & uart_addr[13:0];
//iReg interface
always @ (/*AS*/ESCR or FREQ or ICNT or OCNT or WPTR or uart_addr)
case (uart_addr[2:0])
3'b000: uart_reg_i = {8'd0, ESCR[15:0]};
3'b001: uart_reg_i = {8'd0, WPTR[15:0]};
3'b010: uart_reg_i = {8'd0, ICNT[15:0]};
3'b011: uart_reg_i = {8'd0, FREQ[15:0]};
3'b100: uart_reg_i = {8'd0, OCNT[15:0]};
default: uart_reg_i = 24'hDEA;
endcase // case (uart_addr[2:0])
// BRAM out interface
//read address
assign mem_addrr1[6:0] = uart_addr[13:11] == 3'h1 ? uart_addr[6:0] : 7'b111_1111;
assign mem_addri1[6:0] = uart_addr[13:11] == 3'h2 ? uart_addr[6:0] : 7'b111_1111;
assign mem_addrr2[6:0] = uart_addr[13:11] == 3'h3 ? uart_addr[6:0] : 7'b111_1111;
assign mem_addri2[6:0] = uart_addr[13:11] == 3'h4 ? uart_addr[6:0] : 7'b111_1111;
assign mem_addrr3[6:0] = uart_addr[13:11] == 3'h5 ? uart_addr[6:0] : 7'b111_1111;
assign mem_addri3[6:0] = uart_addr[13:11] == 3'h6 ? uart_addr[6:0] : 7'b111_1111;
//read data
assign MEMDAT[15:0] = MEMDATR1 | MEMDATR2 | MEMDATR3 |
MEMDATI1 | MEMDATI2 | MEMDATI3 ;
assign uart_mem_i[23:0] = {8'h0, MEMDAT[15:0]};
endmodule // QMFIR_uart_top
|
`timescale 1ns / 1ps
`define READ 2'b01
`define WRITE 2'b10
`define DO_NOTHING 2'b00
`define INVALID 2'b11
`define DATA_VALID 1'b1
`define DATA_INVALID 1'b0
`define FIFO_FULL 1'b1
`define FIFO_NOT_FULL 1'b0
`define FIFO_EMPTY 1'b1
`define FIFO_NOT_EMPTY 1'b0
`define LOG2(width) (width<=2)?1:\
(width<=4)?2:\
(width<=8)?3:\
(width<=16)?4:\
(width<=32)?5:\
(width<=64)?6:\
(width<=128)?7:\
(width<=256)?8:\
-1
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:33:56 03/25/2015
// Design Name:
// Module Name: fifo_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo_top(
data_out, empty_flag, full_flag,
vector_in, reset,
clk
);
parameter DATA_WIDTH = 4;
parameter NUM_ENTRIES = 8;
parameter OPCODE_WIDTH = 2;
parameter LINE_WIDTH = DATA_WIDTH+OPCODE_WIDTH; // length of the input vector
parameter INITIAL_VALUE = 'b0;
parameter NUM_ENTRIES_BIT = `LOG2(NUM_ENTRIES);
output reg [DATA_WIDTH-1:0]data_out;
output reg empty_flag;
output reg full_flag;
input [OPCODE_WIDTH+DATA_WIDTH-1:0]vector_in;
input reset;
input clk;
reg [DATA_WIDTH-1:0]fifo_data[NUM_ENTRIES-1:0];
reg [NUM_ENTRIES-1:0]fifo_valid_invalid_bit;
reg [OPCODE_WIDTH-1:0]control_in; // control bits for the module obtained from the input vector
reg [DATA_WIDTH-1:0]data_in; // data bits for the module obtained from the input vector
reg [NUM_ENTRIES_BIT-1:0]fifo_head_pos;
reg [NUM_ENTRIES_BIT-1:0]fifo_tail_pos;
reg [NUM_ENTRIES_BIT-1:0]loop_variable;
always@(posedge clk)
begin
if(reset)
begin
data_out = INITIAL_VALUE;
fifo_head_pos = INITIAL_VALUE;
fifo_tail_pos = INITIAL_VALUE;
loop_variable = INITIAL_VALUE;
control_in = INITIAL_VALUE;
data_in = INITIAL_VALUE;
fifo_valid_invalid_bit = INITIAL_VALUE;
empty_flag = `FIFO_NOT_EMPTY;
full_flag = `FIFO_NOT_FULL;
end else
begin
// if the tail and head are at the same location
if(fifo_tail_pos == fifo_head_pos)begin
// check if the data contained in that location is VALID/INVALID
if(fifo_valid_invalid_bit[fifo_tail_pos] == `DATA_INVALID && fifo_valid_invalid_bit[fifo_head_pos] == `DATA_INVALID)
begin
// if INVALID, fifo empty
// $display("INVALID, EMPTY");
empty_flag = `FIFO_EMPTY;
full_flag = `FIFO_NOT_FULL;
end else
begin
// else, fifo full
// $display("VALID, FULL");
empty_flag = `FIFO_NOT_EMPTY;
full_flag = `FIFO_FULL;
end
end else
begin
// $display("DIFFERENT LOCATIONS");
empty_flag = `FIFO_EMPTY;
full_flag = `FIFO_NOT_FULL;
end
// $display("fifo_head_pos:%d, fifo_tail_pos:%d, empty_flag:%d, full_flag:%d", fifo_head_pos, fifo_tail_pos, empty_flag,full_flag);
control_in = vector_in[LINE_WIDTH-1:LINE_WIDTH-OPCODE_WIDTH];
data_in = vector_in[LINE_WIDTH-OPCODE_WIDTH-1:LINE_WIDTH-OPCODE_WIDTH-DATA_WIDTH];
// $display("control: %d,data_in: %d",control_in, data_in);
case(control_in)
`READ:
begin
// $display("FIFO READ");
if(fifo_valid_invalid_bit[fifo_tail_pos] == `DATA_VALID)
begin
data_out = fifo_data[fifo_tail_pos];
fifo_valid_invalid_bit[fifo_tail_pos] = `DATA_INVALID;
fifo_tail_pos = fifo_tail_pos + 1'b1;
end else
begin
data_out = 'bx;
end
end
`WRITE:
begin
// $display("FIFO WRITE");
if(empty_flag == `FIFO_EMPTY && full_flag == `FIFO_NOT_FULL)
begin
fifo_data[fifo_head_pos] = data_in;
fifo_valid_invalid_bit[fifo_head_pos] = `DATA_VALID;
if(fifo_head_pos == NUM_ENTRIES-1)
fifo_head_pos = 0;
else
fifo_head_pos = fifo_head_pos + 1'b1;
end
// else
// $display("CACHE FULL, empty_flag:%d, full_flag:%d",empty_flag,full_flag);
end
// `INVALID: $display("INVLAID");
// `DO_NOTHING:
// begin
// repeat(NUM_ENTRIES)
// begin
// $display("loop_variable:%d, fifo_valid_invalid_bit:%d, fifo_data:%d", loop_variable, fifo_valid_invalid_bit[loop_variable], fifo_data[loop_variable]);
// loop_variable = loop_variable + 1'b1;
// end
// end
default: data_out = 'bx;
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
module ConcatenadorNumeros
#( parameter stateA = 5'b00001, //cargando datos en fifo
parameter stateB = 5'b00010, //calculando datos
parameter stateC = 5'b00100, //devuelvo
parameter stateD = 5'b01000, //reseteo
parameter stateE = 5'b10000)
(input clk, input reset, input [7:0] dato, input num_ready, input fin,
output integer resultado, output reg done
);
initial done = 0;
initial resultado = 0;
wire [7:0] fifo_data_out; //salida de la fifo
wire [5:0] fifo_data_count; //indica la cantidad de elementos dentro de la fifo
wire fifo_empty; //indica si esta vacio
wire fifo_full; //indica siesta lleno
reg [7:0] fifo_data_in = 0;
reg fifo_wr_en = 0; //escribe en la fifo lo que este en fifo_data_in cuando viene el posedge
reg fifo_rd_en = 0; //saca por fifo_data_out lo que este en la fifo cuando viene el posedge
reg fifo_n_reset = 1; //reset de la fifo. En 1 es NO RESET
reg [4:0] state = stateA;
reg [4:0] next_state = stateA;
reg flag_fin_carga; //flag que indica cuando se terminaron de cargar datos
reg flag_procesando = 0; //si estoy haciendo la cuenta
reg flag_dato_nuevo = 0; //flag para el estado B de ponderacion de numeros
reg end_proc = 0;
integer result_tmp = 0;
integer aux;
integer i;
//https://eewiki.net/pages/viewpage.action?pageId=20939499
FIFO_v fifo (
.data_out(fifo_data_out),
.data_count(fifo_data_count),
.empty(fifo_empty),
.full(fifo_full),
.almst_empty(),
.almst_full(),
.err(),
.data_in(fifo_data_in),
.wr_en(fifo_wr_en),
.rd_en(fifo_rd_en),
.n_reset(fifo_n_reset),
.clk(clk)
);
/*RESET Y NEXT STATE*/
reg [2:0] res_state = 0;
always@(posedge clk)
begin
if(res_state == 0)
begin
if (!reset)
begin
//next_state <= stateA;
fifo_n_reset <= 0;
res_state <= 1;
end
else state <= next_state;
end
else
begin
fifo_n_reset <= 1;
res_state <= 0;
end
end
/*CAMBIO DE ESTADOS*/
always@(posedge clk)
begin
case(state)
stateA:
begin
if(fin) //si llego fin
begin
flag_procesando <= 1; //cambio flag de procesamiento de datos
next_state <= stateB;
end
end
stateB:
begin
if(end_proc == 1) flag_procesando <= 0;
if(!flag_procesando) next_state <= stateC;
end
stateC: next_state <= stateD;
stateD: next_state <= stateA;
endcase
end
/*--------------------CARGA DE NUMEROS----------------------*/
reg [2:0] num_ready_state = 0;
always@(posedge clk)
begin
if(num_ready_state == 0)
begin
if(state == stateA)
begin
if(num_ready)
begin
fifo_data_in <= dato;
fifo_wr_en = 1;
num_ready_state = 1;
end
end
end
else begin
if(num_ready == 0)
begin
num_ready_state = 0;
fifo_wr_en = 0;
end
end
end
/*--------PROCESAMIENTO DE NUMEROS-------------------------*/
/*Primer always me extrae los numeros de la fifo*/
reg [2:0] rd_en_state = 0;
always@(posedge clk)
begin
if(rd_en_state == 0)
begin
if(state == stateB)
begin
if(!fifo_empty)
begin
fifo_rd_en <= 1;
rd_en_state <= 1;
end
else
begin
if(flag_procesando == 1) end_proc <= 1;
else end_proc <= 0;
end
end
end
if(rd_en_state == 1)
begin
rd_en_state <= 2;
fifo_rd_en <= 0;
flag_dato_nuevo <= 1;
end
if(rd_en_state == 2)
begin
flag_dato_nuevo <= 0;
rd_en_state <= 0;
end
end
/*Segundo always calcula el resultado ponderando los valores*/
always@(posedge clk)
begin
if(state == stateB)
if(flag_dato_nuevo == 1)
begin
aux = 1;
for(i = 0; i<16;i=i+1)
begin
if(i<fifo_data_count) aux = aux*10;
end
result_tmp = result_tmp + fifo_data_out*aux;
//result_tmp <= result_tmp + fifo_data_out*(10**fifo_data_count); //la magia
end
if(state == stateD) result_tmp = 0;
end
/*---------------------Envio de resultado------*/
reg [2:0] done_state = 0;
always@(posedge clk)
begin
if(done_state == 0)
begin
if(state == stateC)
begin
done_state <= 1;
resultado <= result_tmp;
done <= 1;
end
end
else
begin
done_state <= 0;
done <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long ans = 0; long long a, b, c, s; cin >> s >> a >> b >> c; ans = s / c + (s / c / a) * b; cout << ans << endl; } int main() { int T; cin >> T; while (T--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int k, n; cin >> n >> k; int x[n]; for (int i = 0; i < n; i++) { cin >> x[i]; } double m = -1, sum = 0; int c = 0; for (int i = 0; i < n; i++) { for (int j = i; j < n; j++) { c++; sum += x[j]; if (c >= k && (sum / c) > m) { m = sum / c; } } c = 0; sum = 0; } cout << setprecision(15) << fixed << m << endl; }
|
#include <bits/stdc++.h> using namespace std; long long a[100005], b[100005]; const long long INF = 1000000009; int main() { int n, x, y; cin >> n >> x >> y; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) b[i] = INF; for (int i = 0; i < n; i++) for (int j = i - y; j <= i + x && j < n; j++) if (j >= 0 && j != i) b[j] = min(a[i], b[j]); int k = 0; while (b[k] < a[k]) k++; cout << k + 1; return 0; }
|
#include <bits/stdc++.h> using namespace std; int b[1002][1002] = {0}; int main() { int a[8][3] = {{7, 3, 5}, {2, 6, 4}, {1, 5, 7}, {0, 4, 6}, {3, 7, 1}, {0, 2, 6}, {1, 3, 5}, {0, 2, 4}}; int x[8]; int y[8]; int d[8]; int n; int m; int tmpx, tmpy; int sum = 0; cin >> n >> m; if (n == 2) { cout << 0 n ; return 0; } for (int i = 0; i < m; ++i) { cin >> tmpx >> tmpy; b[tmpx][1] = 1; b[tmpx][n] = 1; b[1][tmpy] = 1; b[n][tmpy] = 1; } for (int i = 2; i <= n / 2; ++i) { x[0] = i; x[1] = n + 1 - i; x[2] = n; x[3] = n; x[4] = n + 1 - i; x[5] = i; x[6] = 1; x[7] = 1; y[0] = 1; y[1] = 1; y[2] = i; y[3] = n + 1 - i; y[4] = n; y[5] = n; y[6] = n + 1 - i; y[7] = i; bool g = false; int count; int mx = 0; for (int j = 0; j < 256; ++j) { count = 0; for (int k = 0; k < 8; ++k) { d[k] = ((j >> k) & 1); count += d[k]; } g = false; for (int k = 0; k < 8 && (!g); ++k) { if (d[k] == 1) { if (b[x[k]][y[k]] == 1) { g = true; break; } for (int u = 0; u < 3; ++u) { if (d[a[k][u]] == 1) { g = true; break; } } } } if (g) continue; if (count > mx) mx = count; } sum += mx; } if (n % 2 == 1) { if (b[n / 2 + 1][1] == 0 || b[n / 2 + 1][n] == 0 || b[1][n / 2 + 1] == 0 || b[n][n / 2 + 1] == 0) { ++sum; } } cout << sum << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using ull = unsigned long long; using pii = pair<int, int>; using C = complex<double>; const double PI = 3.14159265; const double eps = 1e-8; const int N = 1 << 17; const int M = 1e9 + 7; const int inf = 1e9 + 7; const ll INF = 1e18; ll pw(ll a, ll b) { ll t = 1; a %= M; for (; b; b >>= 1) { if (b & 1) { t = t * a % M; } a = a * a % M; } return t; } ll gcd(ll a, ll b) { return b ? gcd(b, a % b) : a; } int n; int num[N]; int mx[N << 1]; int seg[N << 1]; int find() { int u = 1, w = 0; while (u < N) { if (mx[u << 1 | 1] + w > 0) { u = u << 1 | 1; } else { w += seg[u << 1 | 1]; u <<= 1; } } return u - N; } void add(int p, int v) { p += N; seg[p] += v; mx[p] = seg[p] == 1; for (p >>= 1; p; p >>= 1) { seg[p] = seg[p << 1] + seg[p << 1 | 1]; mx[p] = max(mx[p << 1 | 1], mx[p << 1] + seg[p << 1 | 1]); } } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; int p, t, x; for (int i = 0; i < n; i++) { cin >> p >> t; if (t == 1) { cin >> num[p]; add(p, 1); } else { add(p, -1); } int ps = find(); if (mx[1] <= 0) { puts( -1 ); } else { printf( %d n , num[ps]); } } }
|
#include <iostream> #include <cmath> using namespace std; int main() { int t; cin >> t; while(t--) { int xa, ya, xb, yb, xf, yf; cin >> xa >> ya >> xb >> yb >> xf >> yf; if(xa==xb && xb==xf && yf > ya && yf < yb) { cout << abs(yb-ya) + 2 << endl; continue; } else if(xa==xb && xb==xf && yf < ya && yf > yb) { cout << abs(yb-ya) + 2 << endl; continue; } else if(ya==yb && yb==yf && xf>xa && xf<xb) { cout << abs(xb-xa) + 2 << endl; continue; } else if(ya==yb && yb==yf && xf<xa && xf>xb) { cout << abs(xb-xa) + 2 << endl; continue; } else { cout << abs(xb-xa) + abs(yb-ya) << endl; continue; } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int m, n, count = 0, count1 = 0, x = 0; cin >> m >> n; int a[m][n], b[m][n]; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { cin >> b[i][j]; a[i][j] = 1; } } for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { if (b[i][j] == 0) { for (int k = 0; k < n; k++) { if (a[i][k] == 1) { a[i][k] = 0; count++; if (count == n * m) break; } } for (int k = 0; k < m; k++) { if (a[k][j] == 1) { a[k][j] = 0; count++; if (count == n * m) break; } } } if (count == n * m) break; } if (count == n * m) break; } if (count == n * m) { for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { if (b[i][j] == 1) { cout << NO ; count = 0; break; } } if (count == 0) break; } if (count != 0) { cout << YES << endl; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) cout << a[i][j] << ; cout << endl; } } } else { for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { x = 0; if (b[i][j] == 1) { for (int k = 0; k < m; k++) x = x || a[k][j]; for (int k = 0; k < n; k++) x = x || a[i][k]; if (x != 1) { cout << NO ; count1++; break; } } } if (count1 > 0) break; } if (count1 == 0) { cout << YES << endl; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { cout << a[i][j] << ; } cout << endl; } } } }
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 5; char a[N], b[N]; int main() { int n, k; cin >> n >> k; scanf( %s %s , a + 1, b + 1); long long ans = 0, t = 1; for (int i = 1; i <= n; ++i) { t = t * 2; if (b[i] == a ) t--; if (a[i] == b ) t--; if (t > k) t = k + 1; ans += (t > k ? k : t); } printf( %lld n , ans); }
|
//==================================================================================================
// Filename : subRecursiveKOA.v
// Created On : 2016-10-27 23:29:14
// Last Modified : 2016-10-31 11:41:29
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module subRecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 8)
(
input wire clk,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] Data_S_o
);
localparam integer STOP_CONT = `STOP_CONT;
generate
//assign i = Stop_I;
if (SW <= STOP_CONT) begin : GENSTOP
mult #(.SW(SW))
inst_mult (
.clk(clk),
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(Data_S_o)
);
end else begin : RECURSIVE
reg [2*SW-1:0] sgf_result_o;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
localparam half = SW/2;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
wire [SW-1:0] Q_left;
wire [SW-1:0] Q_right;
wire [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
always @* begin : EVEN11
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW((SW/2)+1)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
assign Data_S_o = sgf_result_o;
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
always @* begin : ODD11
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
assign Data_S_o = sgf_result_o;
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW((SW/2)+1)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW((SW/2)+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
end
endcase
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n, m, k, t, mx; cin >> t; while (t--) { cin >> n >> m >> k; mx = min(n / k, m); cout << (m >= mx ? mx - ceil((long double)(m - mx) / (k - 1)) : mx) << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 50000 + 10; int n; int B[maxN]; vector<pair<int, int>> VB; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &B[i]); for (int i = 0; i < n; i++) { VB.push_back(make_pair(B[i] + B[(i + 1) % n], i)); } sort(VB.begin(), VB.end()); for (int i = 0; i < n; i++) { auto p = VB[i]; B[p.second] = i; } for (int i = 0; i < n; i++) printf( %d%c , B[i], (i == n - 1) ? n : ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, k; int X1[127], X2[128], Y1[111], Y2[105]; bool u[134][134]; vector<int> res; int check(int xx1, int yy1, int x2, int y2) { if (x2 < 0 || y2 < 0 || x2 >= n || y2 >= m || u[x2][y2]) return 0; if (xx1 > x2) swap(xx1, x2); if (yy1 > y2) swap(yy1, y2); if (xx1 != x2) { xx1++; y2++; } else { x2++; yy1++; } for (int i = 0; i < k; i++) { int x3 = max(xx1, X1[i]); int y3 = max(yy1, Y1[i]); int x4 = min(x2, X2[i]); int y4 = min(y2, Y2[i]); if (x3 < x4 && y3 <= y4 || x3 <= x4 && y3 < y4) return 0; } return 1; } int go(int i, int j) { int t = 1; u[i][j] = 1; if (check(i, j, i + 1, j)) t += go(i + 1, j); if (check(i, j, i - 1, j)) t += go(i - 1, j); if (check(i, j, i, j + 1)) t += go(i, j + 1); if (check(i, j, i, j - 1)) t += go(i, j - 1); return t; } int main() { cin >> n >> m >> k; for (int i = 0; i < k; i++) cin >> X1[i] >> Y1[i] >> X2[i] >> Y2[i]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (!u[i][j]) res.push_back(go(i, j)); sort(res.begin(), res.end()); for (int i = 0; i < res.size(); i++) cout << res[i] << ; return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Loop_loop_height_jbC_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_jbC_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_jbC(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
Loop_loop_height_jbC_rom Loop_loop_height_jbC_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; long long gcd(long long x, long long y) { if (x > y) swap(x, y); if (x == 0) return y; if (y % x == 0) return x; return gcd(y % x, x); } int main() { long long n, k, t; long long m, d, w, g; long long x, y, z; long long s, ans; bool v = true; ans = 0; scanf( %lld , &t); for (long long tt = 0; tt < (long long)(t); tt++) { scanf( %lld %lld %lld , &m, &d, &w); if ((m == 1) || (d == 1)) { printf( 0 n ); continue; } g = gcd(d - 1, w); k = w / g; x = min(m, d); y = x % k; x = x / k; s = (x + 1) * x; s /= 2; ans = s * y; s = x * (x - 1); s /= 2; ans += (s * (k - y)); printf( %lld n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long B = 360; const long long N = 100005; long long block(long long x) { return x / B; } long long offset(long long x) { return x % B; } deque<long long> a[B]; signed c[B][N]; long long n, q; signed main() { ios::sync_with_stdio(false); cin >> n; for (long long i = 0; i < n; i++) { long long x; cin >> x; a[block(i)].push_back(x); c[block(i)][x]++; } cin >> q; long long lastans = 0; for (long long i = 0; i < q; i++) { long long op, l, r, k; cin >> op >> l >> r; l = (l + lastans - 1) % n; r = (r + lastans - 1) % n; if (l > r) swap(l, r); if (op == 2) cin >> k; k = (k + lastans - 1) % n + 1; long long L = block(l); long long R = block(r); l = offset(l); r = offset(r); if (op == 1) { if (L == R) { long long x = a[R][r]; a[R].erase(a[R].begin() + r); a[L].insert(a[L].begin() + l, x); } else { for (long long i = L; i < R; i++) { long long x = a[i].back(); a[i].pop_back(); c[i][x]--; c[i + 1][x]++; a[i + 1].push_front(x); } long long x = a[R][r + 1]; a[R].erase(a[R].begin() + r + 1); a[L].insert(a[L].begin() + l, x); c[R][x]--; c[L][x]++; } } else { long long ans = 0; if (L == R) { for (long long i = l; i <= r; i++) ans += a[L][i] == k; } else { for (long long i = l; i < a[L].size(); i++) ans += a[L][i] == k; for (long long i = 0; i <= r; i++) ans += a[R][i] == k; for (long long i = L + 1; i <= R - 1; i++) ans += c[i][k]; } cout << (lastans = ans) << endl; } } }
|
#include <bits/stdc++.h> using namespace std; char ss[100010]; string s; string s1; pair<int, int> b[2000000]; int m[100100]; unsigned long long h[100100]; unsigned long long p[100100]; int main() { scanf( %s , &ss); s = (string)ss; h[0] = 0; p[0] = 1; for (int i = (1); i < (100100); ++i) p[i] = p[i - 1] * 257; for (int i = (0); i < (s.size()); ++i) h[i + 1] = h[i] + (unsigned int)s[i] * p[i]; int n; cin >> n; int sz = 0; for (int it = (0); it < (n); ++it) { cin >> s1; unsigned long long h1 = 0; for (int i = (0); i < (s1.size()); ++i) h1 += (unsigned int)s1[i] * p[i]; int pp = (int)(s.size()) - (int)s1.size(); for (int i = (0); i < (pp + 1); ++i) { if (h1 * p[i] == h[i + s1.size()] - h[i]) { b[sz] = make_pair(i, i + s1.size() - 1); sz++; } } } for (int i = (0); i < (s.size()); ++i) m[i] = (int)s.size(); for (int i = (0); i < (sz); ++i) m[b[i].first] = ((m[b[i].first] < b[i].second) ? (m[b[i].first]) : (b[i].second)); for (int i = (int)s.size() - 2; i >= 0; --i) m[i] = ((m[i] < m[i + 1]) ? (m[i]) : (m[i + 1])); int res = 0; int res1 = 0; for (int i = (0); i < (s.size()); ++i) { int len = m[i] - i; if (len > res) { res = len; res1 = i; } } printf( %d %d n , res, res1); return 0; }
|
#include <bits/stdc++.h> constexpr int Maxn = 1e5 + 7; constexpr int Mod = 1e9 + 7; int fac[Maxn], ifac[Maxn]; inline int fpm(int a, int b) { int res = 1; while (b) { if (b & 1) res = 1LL * res * a % Mod; a = 1LL * a * a % Mod; b >>= 1; } return res; } inline int C(int n, int m) { if (n < 0 || m < 0 || n < m) return 0; return 1LL * fac[n] * ifac[m] % Mod * ifac[n - m] % Mod; } std::unordered_map<int, int> cnt, mp; int n, m, k, f[Maxn], p[Maxn], s[Maxn]; int solve(int x) { if (mp.count(x)) return mp[x]; int res = 0; for (int i = 0; i <= m; ++i) res = (res + 1LL * p[i] * s[i + x] % Mod) % Mod; return mp[x] = res; } int main() { scanf( %d%d , &n, &k); fac[0] = 1; for (int i = 1; i <= n; ++i) fac[i] = 1LL * i * fac[i - 1] % Mod; ifac[n] = fpm(fac[n], Mod - 2); for (int i = n - 1; i >= 0; --i) ifac[i] = 1LL * (i + 1) * ifac[i + 1] % Mod; for (int i = 1, x; i <= n; ++i) { scanf( %d , &x); ++cnt[x]; } f[0] = k - 1; for (int i = 1; i < n; ++i) { int p = 1LL * i * fpm(n, Mod - 2) % Mod; int q = 1LL * (n - i) * fpm(n, Mod - 2) % Mod * fpm(k - 1, Mod - 2) % Mod; f[i] = (1LL * p * f[i - 1] % Mod + 1) * fpm(q, Mod - 2) % Mod; } for (int i = n; i; --i) s[i - 1] = (s[i] + f[i - 1]) % Mod; m = cnt[-1]; for (int i = 0; i <= m; ++i) p[i] = 1LL * C(m, i) * fpm(k - 1, m - i) % Mod * fpm(fpm(k, m), Mod - 2) % Mod; int res = 0, tot = k; for (auto x : cnt) if (x.first != -1) { res = (res + solve(x.second)) % Mod; --tot; } res = (res + 1LL * tot * solve(0) % Mod) % Mod; res = (res - 1LL * (k - 1) * s[0] % Mod + Mod) % Mod; printf( %d n , 1LL * res * fpm(k - 1, Mod - 2) % Mod); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFXTP_SYMBOL_V
`define SKY130_FD_SC_LP__SRSDFXTP_SYMBOL_V
/**
* srsdfxtp: Scan flop with sleep mode, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFXTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int N, M; int A[200], B[200], D[200]; map<int, vector<int>> MM; set<int> S; struct mat { signed long long v[150][3] = {}; }; struct vec { signed long long v[3] = {}; }; void print(mat a, int n) { int x, y; for (x = 0; x < n; x++) { (void)printf( %d: , x); for (y = 0; y < n; y++) (void)printf( %d , (a.v[x][y / 64] & (1LL << (y % 64))) != 0); (void)printf( n ); } } void print(vec a, int n) { int i; for (i = 0; i < n; i++) (void)printf( %d , (a.v[i / 64] & (1LL << (i % 64))) != 0); (void)printf( n ); } mat mult(mat a, mat b, int n) { mat c, d; int x, y, z; for (x = 0; x < n; x++) for (y = 0; y < n; y++) if (b.v[y][x / 64] & (1LL << (x % 64))) c.v[x][y / 64] |= 1LL << (y % 64); for (x = 0; x < n; x++) for (y = 0; y < n; y++) { signed long long v = 0; for (z = 0; z < (n + 63) / 64; z++) v |= a.v[x][z] & c.v[y][z]; v = (v != 0); d.v[x][y / 64] |= v << (y % 64); } return d; } mat init(int n) { mat r; int x; for (x = 0; x < n; x++) r.v[x][x / 64] |= 1LL << (x % 64); return r; } mat powm(mat a, int p, int n) { mat r = init(n); while (p) { if (p % 2) r = mult(r, a, n); a = mult(a, a, n); p /= 2; } return r; } vec mult(mat a, vec b, int n) { vec c; int x, y; for (x = 0; x < n; x++) if (b.v[x / 64] & (1LL << (x % 64))) for (y = 0; y < (n + 63) / 64; y++) c.v[y] |= a.v[x][y]; return c; } bool reachable(mat a, vec b) { int x, y; for (x = 0; x < 150; x++) { vec c = mult(a, b, N); b.v[0] |= c.v[0]; b.v[1] |= c.v[1]; b.v[2] |= c.v[2]; } int n = N - 1; return (b.v[n / 64] & (1LL << (n % 64))) != 0; } void solve() { int i, j, k, l, r, x, y; string s; cin >> N >> M; for (i = 0; i < M; i++) { cin >> A[i] >> B[i] >> D[i]; A[i]--; B[i]--; MM[D[i]].push_back(i); S.insert(D[i]); } int cur = 0; vec v; mat m; v.v[0] = 1; for (auto& r : MM) { v = mult(powm(m, r.first - cur, N), v, N); cur = r.first; for (auto& r2 : r.second) m.v[A[r2]][B[r2] / 64] |= 1LL << (B[r2] % 64); if (reachable(m, v)) break; } if (!reachable(m, v)) return (void)printf( Impossible n ); int n = N - 1; while ((v.v[n / 64] & (1LL << (n % 64))) == 0) { v = mult(m, v, N); cur++; if (S.count(cur)) for (auto& r2 : MM[cur]) m.v[A[r2]][B[r2] / 64] |= 1LL << (B[r2] % 64); } cout << cur << endl; } int main(int argc, char** argv) { string s; int i; if (argc == 1) ios::sync_with_stdio(false); for (i = 0; i < argc - 1; i++) s += argv[i + 1], s += n ; for (i = 0; i < s.size(); i++) ungetc(s[s.size() - 1 - i], stdin); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__BUFLP_PP_SYMBOL_V
/**
* buflp: Buffer, Low Power.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__buflp (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_BLACKBOX_V
`define SKY130_FD_SC_HVL__O22A_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o22a (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O21BAI_FUNCTIONAL_PP_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; long long ans = 0; for (long long i = n - 1; i >= 0; i--) { if (i == n - 1) ans += a[i]; else if (a[i] < a[i + 1]) ans += a[i]; else if (a[i] >= a[i + 1]) { if (a[i + 1] == 0) a[i] = 0; else { ans += a[i + 1] - 1; a[i] = a[i + 1] - 1; } } } cout << ans; return 0; }
|
// $Id: c_fp_arbiter.v 1625 2009-10-29 00:15:03Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// generic fixed-priority arbiter (port 0 has highest priority)
module c_fp_arbiter
(req, gnt);
`include "c_constants.v"
// number of input ports
parameter num_ports = 32;
// vector of requests
input [0:num_ports-1] req;
// vector of grants
output [0:num_ports-1] gnt;
wire [0:num_ports-1] gnt;
generate
if(num_ports > 1)
begin
// reversed request vector
wire [0:num_ports-1] req_rev;
c_reversor
#(.width(num_ports))
req_rev_revr
(.data_in(req),
.data_out(req_rev));
// This finds the first non-zero bit from the right (which is why we
// reverse the request vector in the first place).
wire [0:num_ports-1] gnt_rev;
assign gnt_rev = req_rev & -req_rev;
c_reversor
#(.width(num_ports))
gnt_revr
(.data_in(gnt_rev),
.data_out(gnt));
end
else
assign gnt = req;
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename A, size_t N, typename T> void Fill(A (&array)[N], const T &val) { std::fill((T *)array, (T *)(array + N), val); } template <class T> inline bool chmax(T &a, T b) { if (a < b) { a = b; return true; } return false; } template <class T> inline bool chmin(T &a, T b) { if (a > b) { a = b; return true; } return false; } int mi = 1000000007; map<pair<int, int>, int> mp; int minima[2000000]; int f(int a, int b) { if (mp.find(make_pair(a, b)) != mp.end()) { return mp[make_pair(a, b)]; } cout << ? << a << << b << endl; int s; cin >> s; chmin(mi, s); return mp[make_pair(a, b)] = s; } void SMAWK(vector<int> js, int ib, int ie, int id) { if (ib > ie) return; vector<int> js2; for (int q = 0, i = ib; q < js.size(); ++q) { while (!js2.empty() && f(i, js2.back()) >= f(i, js[q])) { js2.pop_back(); i -= id; } if (js2.size() != (ie - ib) / id) { js2.push_back(js[q]); i += id; } } SMAWK(js2, ib + id, ie, id * 2); for (int i = ib, q = 0; i <= ie; i += id * 2) { int jt = (i + id <= ie ? minima[i + id] : js.back()); int fm = 999999999 * 2, fq; for (; q < js.size(); ++q) { if (fm > (fq = f(i, js[q]))) { fm = fq; minima[i] = js[q]; } if (js[q] == jt) break; } } } void rowMinimaTM(int ib, int ie, int jb, int je) { vector<int> js; for (int j = jb; j <= je; ++j) js.push_back(j); SMAWK(js, ib, ie, 1); } int main() { int n, m; cin >> n >> m; rowMinimaTM(1, n, 1, m); cout << ! << mi << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e6; int a[maxn], ans; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; while (n--) { int tmp; cin >> tmp; a[tmp]++; } for (int i = 0; i < maxn; i++) { a[i + 1] += a[i] / 2; ans += a[i] % 2; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long oo = 1e18; struct dta { int u, id; dta(int _u = 0, int _id = 0) { u = _u; id = _id; } }; struct TDij { long long val; int x; TDij(long long _val = 0, int _x = 0) { x = _x; val = _val; } }; inline bool operator<(const TDij &a, const TDij &b) { return (a.val > b.val); } int n, m, k, cost[300010], trace[300010], delneed; bool flag[300010]; long long F[300010]; vector<dta> A[300010]; priority_queue<TDij> Q; void dijks() { memset(flag, true, sizeof(flag)); memset(trace, 0, sizeof(trace)); for (int i = 2; i <= n; ++i) F[i] = oo; F[1] = 0; Q.push(TDij(0, 1)); while (!Q.empty()) { TDij topx = Q.top(); Q.pop(); if (topx.val != F[topx.x]) continue; int u = topx.x; for (int i = 0; i <= A[u].size() - 1; ++i) { if (F[A[u][i].u] > F[u] + cost[A[u][i].id]) { F[A[u][i].u] = F[u] + cost[A[u][i].id]; flag[trace[A[u][i].u]] = true; trace[A[u][i].u] = A[u][i].id; flag[A[u][i].id] = false; Q.push(TDij(F[A[u][i].u], A[u][i].u)); } } } } void dfs(int x, int par, int pared) { for (int i = 0; i <= A[x].size() - 1; ++i) if (A[x][i].u != par && !flag[A[x][i].id]) { dfs(A[x][i].u, x, A[x][i].id); if (delneed == 0) return; } if (delneed > 0) { (--delneed); flag[pared] = true; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m >> k; for (int i = 1; i <= m; ++i) { int u, v; cin >> u >> v >> cost[i]; A[u].push_back(dta(v, i)); A[v].push_back(dta(u, i)); } dijks(); delneed = m - k; if (!delneed) { for (int i = 1; i <= m; ++i) delneed += (!flag[i]); cout << delneed << n ; for (int i = 1; i <= m; ++i) if (!flag[i]) cout << i << ; return 0; } for (int i = 1; i <= m; ++i) if (flag[i]) { if ((--delneed) == 0) { cout << k << n ; for (int j = 1; j <= i; ++j) if (!flag[j]) cout << j << ; for (int j = i + 1; j <= m; ++j) cout << j << ; return 0; } } dfs(1, 0, 0); cout << k << n ; for (int i = 1; i <= m; ++i) if (!flag[i]) cout << i << ; return 0; }
|
// File name : UniversalCounter.v
// Written by : Jianjian Song
// 4-bit universal bidirectional counter
`timescale 1ns / 1ps
module ClockedPositiveOneShot(InputPulse, OneShot, Reset, CLOCK) ;
input InputPulse, Reset, CLOCK;
output reg OneShot;
parameter State0=0, State1=1, State2=2, State3=3;
reg [1:0] State;
always@(State)
if(State==State1) OneShot<=1;
else OneShot<=0;
always @ (posedge CLOCK)
if(Reset==1) State <= 0; else
case (State)
0: if (InputPulse==0) State<=State0; else State<=State1;
1: if (InputPulse==0) State<=State0; else State<=State3;
2: State<=State0;
3: if (InputPulse==0) State<=State0; else State<=State3;
endcase
endmodule
module ClockedNegativeOneShot(InputPulse, OneShot, Reset, CLOCK) ;
input InputPulse, Reset, CLOCK;
output reg OneShot;
parameter State0=0, State1=1, State2=2, State3=3;
reg [1:0] State;
always@(State)
if(State==State1) OneShot<=0;
else OneShot<=1;
always @ (posedge CLOCK)
if(Reset==1) State <= 0; else
case (State)
0: if (InputPulse==1) State<=State0; else State<=State1;
1: if (InputPulse==1) State<=State0; else State<=State3;
2: State<=State0;
3: if (InputPulse==1) State<=State0; else State<=State3;
endcase
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; const int M = 1000005; const int nmax = 500010; const int MOD = (1e9) + 7; int nextX[] = {1, -1, 0, 0}; int nextY[] = {0, 0, 1, -1}; int n, m, t; int f[1010][1010]; char s[1010][1010]; bool good(int x, int y) { return (x >= 1 && x <= n && y >= 1 && y <= m); } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> m >> t; for (int i = 1; i <= n; i++) cin >> s[i] + 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) f[i][j] = -1; queue<pair<int, int> > que; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { int nr = 0; for (int k = 0; k < 4; k++) { int x = i + nextX[k]; int y = j + nextY[k]; if (!good(x, y)) continue; if (s[i][j] == s[x][y]) nr++; } if (nr > 0) { que.push({i, j}); f[i][j] = 0; } } while (!que.empty()) { int x = que.front().first; int y = que.front().second; que.pop(); for (int k = 0; k < 4; k++) { int nxt_x = x + nextX[k]; int nxt_y = y + nextY[k]; if (!good(nxt_x, nxt_y)) continue; if (s[nxt_x][nxt_y] != s[x][y] && f[nxt_x][nxt_y] == -1) { f[nxt_x][nxt_y] = f[x][y] + 1; que.push({nxt_x, nxt_y}); } } } for (int i = 1; i <= t; i++) { int x, y; long long int p; cin >> x >> y >> p; if (f[x][y] == -1 || p < f[x][y]) cout << s[x][y] << n ; else { long long int diff = p - f[x][y]; if (diff % 2 == 0) cout << s[x][y] << n ; else if (s[x][y] == 1 ) cout << 0 n ; else cout << 1 n ; } } return 0; }
|
module test();
localparam size1 = 4;
localparam size2 = 6;
localparam size3 = 8;
localparam [5:0] value1 = 6'h3f;
localparam signed [5:0] value2 = 6'h3f;
reg [31:0] result;
reg failed = 0;
initial begin
result = size1'(value1) + 'd0;
$display("%h", result);
if (result !== 32'h0000000f) failed = 1;
result = size1'(value1) + 'sd0;
$display("%h", result);
if (result !== 32'h0000000f) failed = 1;
result = size1'(value2) + 'd0;
$display("%h", result);
if (result !== 32'h0000000f) failed = 1;
result = size1'(value2) + 'sd0;
$display("%h", result);
if (result !== 32'hffffffff) failed = 1;
result = size2'(value1) + 'd0;
$display("%h", result);
if (result !== 32'h0000003f) failed = 1;
result = size2'(value1) + 'sd0;
$display("%h", result);
if (result !== 32'h0000003f) failed = 1;
result = size2'(value2) + 'd0;
$display("%h", result);
if (result !== 32'h0000003f) failed = 1;
result = size2'(value2) + 'sd0;
$display("%h", result);
if (result !== 32'hffffffff) failed = 1;
result = size3'(value1) + 'd0;
$display("%h", result);
if (result !== 32'h0000003f) failed = 1;
result = size3'(value1) + 'sd0;
$display("%h", result);
if (result !== 32'h0000003f) failed = 1;
result = size3'(value2) + 'd0;
$display("%h", result);
if (result !== 32'h000000ff) failed = 1;
result = size3'(value2) + 'sd0;
$display("%h", result);
if (result !== 32'hffffffff) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; inline int read() { int s = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = (s << 3) + (s << 1) + ch - 0 , ch = getchar(); return s * f; } const int N = 1e5 + 5, M = 320; int n, m, fa[N], top[N], t[N], sz[N], son[N]; struct Edge { int to, next; } e[N]; int head[N], ecnt, id[N], pos[N], L[M], R[M]; inline void adde(int u, int v) { e[++ecnt].next = head[u]; e[ecnt].to = v; head[u] = ecnt; } void dfs1(int u) { sz[u] = 1; for (int i = head[u], v; i; i = e[i].next) { v = e[i].to; dfs1(v); sz[u] += sz[v]; if (sz[son[u]] < sz[v]) son[u] = v; } } int inde, p[N], cnt[M][N], ans, tag[M], blk, blksz; void dfs2(int u, int fr) { id[u] = ++inde; p[inde] = u; top[u] = fr; ++cnt[pos[inde]][t[u]]; if (son[u]) dfs2(son[u], fr); for (int i = head[u], v; i; i = e[i].next) { v = e[i].to; if (v != son[u]) dfs2(v, v); } } bool black[N]; inline void modify_blk(int x, int l, int r, int val) { if (l <= L[x] && R[x] <= r) { if (val > 0) { ++tag[x]; ans += cnt[x][tag[x]]; } else { ans -= cnt[x][tag[x]]; --tag[x]; } } else { for (int i = max(l, L[x]), u; i <= min(r, R[x]); ++i) { u = p[i]; if (black[u]) { if (val > 0) --t[u]; else ++t[u]; continue; } if (val > 0) { --cnt[x][t[u]]; ++cnt[x][--t[u]]; if (t[u] == tag[x]) ++ans; } else { --cnt[x][t[u]]; if (t[u] == tag[x]) --ans; ++cnt[x][++t[u]]; } } } } inline void modify_node(int u, int val) { if (black[u] && !val) { ++cnt[pos[id[u]]][t[u]]; if (t[u] <= tag[pos[id[u]]]) ++ans; } else if (!black[u] && val) { --cnt[pos[id[u]]][t[u]]; if (t[u] <= tag[pos[id[u]]]) --ans; } black[u] = val; } inline void modify(int x, int val) { if (black[x] == val) return; modify_node(x, val); int u = fa[x], l, r; while (u) { l = id[top[u]]; r = id[u]; if (pos[l] == pos[r]) { modify_blk(pos[l], l, r, black[x]); } else { modify_blk(pos[l], l, r, black[x]); modify_blk(pos[r], l, r, black[x]); for (int i = pos[l] + 1; i < pos[r]; ++i) modify_blk(i, l, r, black[x]); } u = fa[top[u]]; } } int main() { n = read(); m = read(); for (int i = 2; i <= n; ++i) fa[i] = read(), adde(fa[i], i); for (int i = 1; i <= n; ++i) t[i] = read() + 1; blksz = min(N / (M - 2), int(sqrt(n))); blk = (n - 1) / blksz + 1; for (int i = 1; i <= n; ++i) pos[i] = (i - 1) / blksz + 1; for (int i = 1; i <= blk; ++i) L[i] = (i - 1) * blksz + 1, R[i] = i * blksz; R[blk] = n; dfs1(1); dfs2(1, 0); while (m--) { int node = read(), val = 1; if (node < 0) node = -node, val = 0; modify(node, val); printf( %d , ans); } return 0; }
|
#include <bits/stdc++.h> int s, i, e; int main() { int t; scanf( %d , &t); while (t--) { int ans = 0; scanf( %d%d%d , &s, &i, &e); if (s > i + e) { printf( %d n , e + 1); } else if (s + e <= i) { printf( %d n , 0); } else { int k = e - (i + e - s) / 2; printf( %d n , k); } } return 0; }
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description: PPFIFO -> BRAM and BRM -> PPFIFO
* Attaches two PPFIFO to a block RAM.
*
* How to use:
*
* PPFIFO (Read to the BRAM) Interface Attached to read_*
* PPFIFO (Write from the BRAM) Interface Attached to write_*
*
* Changes:
*/
`define MEM_WAIT 2
module adapter_dpb_ppfifo #(
parameter MEM_DEPTH = 9,
parameter DATA_WIDTH = 32
)(
input clk,
input rst,
input i_ppfifo_2_mem_en,
input i_mem_2_ppfifo_stb,
input i_cancel_write_stb,
output reg [31:0] o_num_reads,
output o_idle,
//User Memory Interface
input i_bram_we,
input [MEM_DEPTH - 1: 0] i_bram_addr,
input [DATA_WIDTH - 1: 0] i_bram_din,
output [DATA_WIDTH - 1: 0] o_bram_dout,
output o_bram_valid,
//Ping Pong FIFO Interface
input ppfifo_clk,
input [1:0] i_write_ready,
output reg [1:0] o_write_activate,
input [23:0] i_write_size,
output reg o_write_stb,
output [DATA_WIDTH - 1:0] o_write_data,
input i_read_ready,
output reg o_read_activate,
input [23:0] i_read_size,
input [DATA_WIDTH - 1:0] i_read_data,
output reg o_read_stb
);
//local parameters
localparam MEM_SIZE = (2 ** MEM_DEPTH);
//States
localparam IDLE = 0;
localparam WRITE_SETUP = 1;
localparam WRITE = 2;
localparam READ = 3;
//registes/wires
wire w_pf_rd_en;
wire w_pf_wr_stb;
wire w_pf_cancel_stb;
reg [3:0] state;
reg [23:0] count;
reg r_we;
reg [MEM_DEPTH - 1: 0] r_addr;
reg [3:0] mem_wait_count;
reg [23:0] prev_mem_addr;
//submodules
cross_clock_enable p_en_r (
.rst (rst ),
.in_en (i_ppfifo_2_mem_en ),
.out_clk (ppfifo_clk ),
.out_en (w_pf_rd_en )
);
cross_clock_strobe p_stb_w (
.rst (rst ),
.in_clk (clk ),
.in_stb (i_mem_2_ppfifo_stb ),
.out_clk (ppfifo_clk ),
.out_stb (w_pf_wr_stb )
);
cross_clock_strobe p_stb_cncl_w (
.rst (rst ),
.in_clk (clk ),
.in_stb (i_cancel_write_stb ),
.out_clk (ppfifo_clk ),
.out_stb (w_pf_cancel_stb )
);
//Read/Write Data to a local buffer
dpb #(
.DATA_WIDTH (DATA_WIDTH ),
.ADDR_WIDTH (MEM_DEPTH )
) local_buffer (
.clka (clk ),
.wea (i_bram_we ),
.addra (i_bram_addr ),
.douta (o_bram_dout ),
.dina (i_bram_din ),
.clkb (ppfifo_clk ),
.web (r_we ),
.addrb (r_addr ),
.dinb (i_read_data ),
.doutb (o_write_data )
);
//assign o_write_data = 32'h01234567;
//asynchronous logic
assign o_idle = (state == IDLE);
//synchronous logic
assign o_bram_valid = ((prev_mem_addr == i_bram_addr) && (mem_wait_count == `MEM_WAIT));
always @ (posedge clk) begin
if (rst) begin
mem_wait_count <= `MEM_WAIT;
prev_mem_addr <= 0;
end
else begin
if (prev_mem_addr != i_bram_addr) begin
mem_wait_count <= 0;
prev_mem_addr <= i_bram_addr;
end
else begin
if (mem_wait_count < `MEM_WAIT) begin
mem_wait_count <= mem_wait_count + 1;
end
end
end
end
always @ (posedge ppfifo_clk) begin
o_read_stb <= 0;
o_write_stb <= 0;
r_we <= 0;
if (rst || w_pf_cancel_stb) begin
o_write_activate <= 0;
o_read_activate <= 0;
o_num_reads <= 0;
count <= 0;
r_addr <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
o_read_activate <= 0;
o_write_activate <= 0;
r_addr <= 0;
count <= 0;
if (w_pf_wr_stb) begin
//Load the memory data into the PPFIFO
state <= WRITE_SETUP;
end
else if (w_pf_rd_en) begin
if (i_read_ready) begin
o_read_activate <= 1;
state <= READ;
end
end
end
WRITE_SETUP: begin
if ((i_write_ready > 0) && (o_write_activate == 0)) begin
if (i_write_ready[0]) begin
o_write_activate[0] <= 1;
end
else begin
o_write_activate[1] <= 1;
end
state <= WRITE;
end
end
WRITE: begin
if (count < i_write_size) begin
r_addr <= r_addr + 1;
o_write_stb <= 1;
count <= count + 1;
end
else begin
o_write_activate <= 0;
state <= IDLE;
end
end
READ: begin
//Memory Interface
r_we <= 1;
if (r_we) begin
if (count < i_read_size) begin
o_read_stb <= 1;
count <= count + 1;
o_num_reads <= o_num_reads + 1;
end
else begin
//Done Reading
o_read_activate <= 0;
state <= IDLE;
r_we <= 0;
end
end
if (o_read_stb) begin
//Delay incrementing the address
r_addr <= r_addr + 1;
end
end
default: begin
//Shouldn't get here
state <= IDLE;
end
endcase
end
end
endmodule
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG_SIM
`define TEST_PROG "prog_add.list"
`include "top.v"
module top_test_add;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = (1 << WIDTH) - 1;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH : 0] expected_output = 1;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output >= OUTPUT_CNT) begin
$display("Add test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Add test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n",
serial_data, expected_output);
$finish;
end
expected_output <= expected_output + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
//############################################################################
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// (C) Copyright Laboratory System Integration and Silicon Implementation
// All Right Reserved
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// ICLAB 2016 Fall
// Lab01-Practice : Polynomial Integrator
// Author : Chien-Tung, Shih ()
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// File Name : TESETBED.v
// Module Name : TESETBED
// Release version : V1.0 (Release Date: 2016-09)
//
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//############################################################################
`timescale 1ns/10ps
`include "PATTERN.v"
`ifdef RTL
`include "OT11_27.v"
`endif
`ifdef GATE
`include "OT11_27_SYN.v"
`endif
module TESTBED;
wire clk,rst_n,in_valid1,in_valid2;
wire [7:0]in,bomb;
wire [5:0]hit;
wire out_valid;
wire [6:0] out;
initial begin
`ifdef RTL
$fsdbDumpfile("OT11_27.fsdb");
$fsdbDumpvars();
`endif
`ifdef GATE
$sdf_annotate("OT11_27_SYN.sdf",U_OT11_27);
$fsdbDumpfile("OT11_27_SYN.fsdb");
$fsdbDumpvars();
`endif
end
OT11_27 U_OT11_27 (
clk,
rst_n,
in,
bomb,
in_valid1,
hit,
in_valid2,
// Input signals
out_valid,
out
);
PATTERN I_PATTERN(
clk,
rst_n,
in,
bomb,
in_valid1,
hit,
in_valid2,
// Input signals
out_valid,
out
);
endmodule
|
#include<bits/stdc++.h> #define ll long long int using namespace std; int main() { int t; cin>>t; while(t--) { ll a, b, c; cin>>a>>b>>c; if((a+b+c)%9 == 0 && min(a, min(b,c)) >= (a+b+c)/9) cout<< YES <<endl; else cout<< NO <<endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { size_t n, w, m; ios_base::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr), cin >> n >> w >> m; struct bottle_t { size_t amount, id; } bottle, poured; stack<bottle_t> bottles, non_empty; vector<bottle_t> cup[m]; for (bottle.amount = m, bottle.id = 1; bottle.id <= n; bottle.id++) bottles.push(bottle); for (size_t i = 0, unfilled = n; i < m; i++, unfilled = n) { while (!non_empty.empty()) bottles.push(non_empty.top()), non_empty.pop(); do { bottle = bottles.top(), bottles.pop(); if (bottle.amount > unfilled && bottle.amount < m) { cout << NO ; return 0; } poured = bottle; if (unfilled < poured.amount) poured.amount = unfilled; cup[i].push_back(poured); if ((bottle.amount -= poured.amount) > 0) non_empty.push(bottle); } while ((unfilled -= poured.amount) > 0); } cout << YES << n ; long double scale_factor = (long double)w / (long double)m; for (size_t i = 0; i < m; i++, cout << n ) for (size_t j = 0, k = cup[i].size(); j < k; j++) cout << cup[i][j].id << << fixed << setprecision(6) << scale_factor * cup[i][j].amount << ; }
|
#include <bits/stdc++.h> using namespace std; struct node { int u, s; node() { u = s = 0; } bool operator<(const node &temp) const { if (this->s < temp.s) return 1; return 0; } }; node black[100005]; node white[100005]; vector<vector<node> > adj; int main() { int n; scanf( %d , &n); adj.resize(n); bool allzero = true; int w, b; w = b = 0; for (int i = 0; i < n; ++i) { int c; scanf( %d , &c); if (c == 0) { white[w].u = i; scanf( %d , &white[w].s); if (white[w].s) allzero = false; ++w; } else { black[b].u = i; scanf( %d , &black[b].s); if (black[b].s) allzero = false; ++b; } } if (allzero) { if (w < b) { for (int i = 0; i < b; ++i) cout << white[0].u + 1 << << black[i].u + 1 << << 0 << endl; for (int i = 1; i < w; ++i) cout << white[i].u + 1 << << black[i].u + 1 << << 0 << endl; } else { for (int i = 0; i < w; ++i) cout << black[0].u + 1 << << white[i].u + 1 << << 0 << endl; for (int i = 1; i < b; ++i) cout << black[i].u + 1 << << white[i].u + 1 << << 0 << endl; } return 0; } sort(black, black + b); sort(white, white + w); for (int indb = 0, indw = 0; indb < b && indw < w;) { if (white[indw].s < black[indb].s) { black[indb].s -= white[indw].s; adj[black[indb].u].push_back(white[indw]); ++indw; } else { white[indw].s -= black[indb].s; adj[white[indw].u].push_back(black[indb]); ++indb; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < adj[i].size(); ++j) { printf( %d %d %d n , i + 1, adj[i][j].u + 1, adj[i][j].s); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__XNOR3_PP_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e10; void solve() { long long n, c; cin >> n >> c; long long a[n], b[n]; for (long long i = 0; i < n; i++) { cin >> a[i] >> b[i]; } long long low = -1, high = -1; for (long long i = 1; i <= 100000; i++) { long long cnt = 0; for (long long j = 0; j < n; j++) { cnt++; cnt += (a[j] * i) / b[j]; } if (cnt > c) break; if (cnt < c) continue; if (cnt == c) { if (low == -1) low = i; high = i; } } if (high == -1) cout << 0; else cout << high - low + 1; } int32_t main() { long long t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a[1000]; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } long int answer = 0; for (int i = 0; i < (n - 1); i++) { if (a[i] == 1 && a[i + 1] == 2) { answer += 3; } else if (a[i] == 1 && a[i + 1] == 3) { answer += 4; } else if (a[i] == 2 && a[i + 1] == 1) { answer += 3; } else if (a[i] == 2 && a[i + 1] == 3) { cout << Infinite ; return 0; } else if (a[i] == 3 && a[i + 1] == 1) { answer += 4; if (i < n - 2 && a[i + 2] == 2) { answer -= 1; } } else if (a[i] == 3 && a[i + 1] == 2) { cout << Infinite ; return 0; } } cout << Finite << endl; cout << answer; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> v; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; int flag = 0; int m; cin >> m; long long a[m]; for (int i = 0; i < m; i++) { cin >> a[i]; } sort(a, a + m); for (int i = 1; i < m - 1; i++) { if ((a[i] - a[i - 1] == 1) && (a[i + 1] - a[i] == 1)) { flag = 1; break; } } if (flag == 1 || a[m - 1] == n || a[0] == 1) cout << NO << n ; else cout << YES << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Max = 2e5 + 10; vector<int> A; int ok[Max]; int len; int seg[Max * 4]; int lazy[Max * 4]; void build(int tl = 0, int tr = len + 1, int idx = 1) { if (tr - tl == 1) { seg[idx] = len - tl; return; } int mid = (tl + tr) / 2; build(tl, mid, idx * 2); build(mid, tr, idx * 2 + 1); seg[idx] = min(seg[idx * 2], seg[idx * 2 + 1]); } void shift(int idx) { if (!lazy[idx]) return; lazy[idx * 2] += lazy[idx]; lazy[idx * 2 + 1] += lazy[idx]; seg[idx * 2] += lazy[idx]; seg[idx * 2 + 1] += lazy[idx]; lazy[idx] = 0; } void upd(int i, int val, int tl = 0, int tr = len + 1, int idx = 1) { if (tr - 1 <= i) { lazy[idx] += val; seg[idx] += val; return; } if (tl > i) return; shift(idx); int mid = (tl + tr) / 2; upd(i, val, tl, mid, idx * 2); upd(i, val, mid, tr, idx * 2 + 1); seg[idx] = min(seg[idx * 2], seg[idx * 2 + 1]); } int check() { return seg[1]; } int main() { int n, h; cin >> n >> len >> h; for (int i = 0; i < len; i++) { int a; cin >> a; A.push_back(a); } sort(A.begin(), A.end()); for (int i = 0; i < n; i++) { long long a; cin >> a; int l = -1, r = len; while (r - l > 1) { int idx = (l + r) / 2; if (a + A[idx] >= h) r = idx; else l = idx; } ok[i] = r; } int ans = 0; build(); for (int i = 0; i < len; i++) upd(ok[i], -1); if (check() >= 0) ans++; for (int i = len; i < n; i++) { upd(ok[i], -1); upd(ok[i - len], 1); if (check() >= 0) ans++; } cout << ans; }
|
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_ff
// ============================================================
// File Name: lpm_ff_v1.v
// Megafunction Name(s):
// lpm_ff
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lpm_ff_v1 (
clock,
data,
q);
input clock;
input [63:0] data;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
lpm_ff lpm_ff_component (
.clock (clock),
.data (data),
.q (sub_wire0)
// synopsys translate_off
,
.aclr (),
.aload (),
.aset (),
.enable (),
.sclr (),
.sload (),
.sset ()
// synopsys translate_on
);
defparam
lpm_ff_component.lpm_fftype = "DFF",
lpm_ff_component.lpm_type = "LPM_FF",
lpm_ff_component.lpm_width = 64;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: DFF NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "64"
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; template <class _T> inline _T sqr(const _T &first) { return first * first; } template <class _T> inline string tostr(const _T &a) { ostringstream os( ); os << a; return os.str(); } const long double PI = 3.1415926535897932384626433832795L; const long double EPS = 1e-12; char TEMPORARY_CHAR; const int INF = 1e9; inline void fft(vector<complex<long double> > &a, bool invert) { int n = (int)a.size(); for (int i = 1, j = 0; i < n; ++i) { int bit = n >> 1; for (; j >= bit; bit >>= 1) j -= bit; j += bit; if (i < j) swap(a[i], a[j]); } for (int len = 2; len <= n; len <<= 1) { long double ang = 2 * PI / len * (invert ? -1 : 1); complex<long double> wlen(cos(ang), sin(ang)); for (int i = 0; i < n; i += len) { complex<long double> w(1); for (int j = 0; j < len / 2; ++j) { complex<long double> u = a[i + j], v = a[i + j + len / 2] * w; a[i + j] = u + v; a[i + j + len / 2] = u - v; w *= wlen; } } } if (invert) for (int i = 0; i < n; ++i) a[i] /= n; } inline void input(int &a) { a = 0; while (((TEMPORARY_CHAR = getchar()) > 9 || TEMPORARY_CHAR < 0 ) && (TEMPORARY_CHAR != - )) { } char neg = 0; if (TEMPORARY_CHAR == - ) { neg = 1; TEMPORARY_CHAR = getchar(); } while (TEMPORARY_CHAR <= 9 && TEMPORARY_CHAR >= 0 ) { a = (a << 3) + (a << 1) + TEMPORARY_CHAR - 0 ; TEMPORARY_CHAR = getchar(); } if (neg) a = -a; } inline void out(long long a) { if (!a) putchar( 0 ); if (a < 0) { putchar( - ); a = -a; } char s[20]; int i; for (i = 0; a; ++i) { s[i] = 0 + a % 10; a /= 10; } for (int j = (i)-1; j >= 0; j--) putchar(s[j]); } inline int nxt() { int(ret); input((ret)); ; return ret; } struct lnum { vector<int> a; int base; lnum(int num = 0, int base = 1000000000) : base(base) { if (!num) a.resize(1); while (num) { a.push_back(num % base); num /= base; } } inline int len() const { return a.size(); } lnum &operator=(const lnum &l) { if (this != &l) { a = l.a; base = l.base; } return *this; } inline friend lnum operator+(const lnum &l, const lnum &r) { lnum ret(0, l.base); int base = l.base; int ln = l.len(), rn = r.len(); int n = max(ln, rn); ret.a.resize(n); int o = 0; for (int i = 0; i < n; ++i) { int s = o; if (i < ln) s += l.a[i]; if (i < rn) s += r.a[i]; o = s >= base; if (o) s -= base; ret.a[i] = s; } if (o) ret.a.push_back(1); return ret; } inline friend lnum operator-(const lnum &l, const lnum &r) { lnum ret(0, l.base); int base = l.base; int n = l.len(); int rn = r.len(); ret.a.resize(n); int o = 0; for (int i = 0; i < n; ++i) { int s = l.a[i] - o; if (i < rn) s -= r.a[i]; o = s < 0; if (o) s += base; ret.a[i] = s; } if (ret.len() > 1 && !ret.a.back()) ret.a.pop_back(); return ret; } inline friend lnum operator*(const lnum &l, const lnum &r) { lnum ret(0, l.base); int base = l.base; if (l.len() * r.len() > 1000000) { vector<complex<long double> > fa(l.a.begin(), l.a.end()), fb(r.a.begin(), r.a.end()); int n = 1; while (n < max(l.len(), r.len())) n <<= 1; n <<= 1; fa.resize(n), fb.resize(n); fft(fa, false), fft(fb, false); for (int i = 0; i < n; ++i) fa[i] *= fb[i]; fft(fa, true); ret.a.resize(n); for (int i = 0; i < n; ++i) ret.a[i] = int(fa[i].real() + 0.5); int carry = 0; for (int i = 0; i < n; ++i) { ret.a[i] += carry; carry = ret.a[i] / base; ret.a[i] %= base; } } else { ret.a.resize(l.len() + r.len()); for (int i = 0; i < l.len(); ++i) for (int j = 0, carry = 0; j < r.len() || carry; ++j) { long long cur = ret.a[i + j] + (long long)l.a[i] * (j < r.len() ? r.a[j] : 0) + carry; ret.a[i + j] = cur % base; carry = cur / base; } } while (ret.len() > 1 && !ret.a.back()) ret.a.pop_back(); return ret; } inline friend lnum operator/(const lnum &l, const int &r) { lnum ret(0, l.base); ret.a.resize(l.len()); int carry = 0; for (int i = l.len() - 1; i >= 0; --i) { long long cur = l.a[i] + (long long)carry * l.base; ret.a[i] = cur / r; carry = cur % r; } while (ret.len() > 1 && ret.a.back() == 0) ret.a.pop_back(); return ret; } inline friend bool operator<(const lnum &l, const lnum &r) { if (l.len() < r.len()) return true; if (l.len() > r.len()) return false; int n = l.len(); for (int i = n - 1; i >= 0; --i) { if (l.a[i] < r.a[i]) return true; if (l.a[i] > r.a[i]) return false; } return false; } inline friend bool operator>(const lnum &l, const lnum &r) { return r < l; } inline friend bool operator==(const lnum &l, const lnum &r) { if (l.len() != r.len()) return false; int n = l.len(); for (int i = n - 1; i; --i) { if (l.a[i] != r.a[i]) return false; } return true; } inline friend bool operator!=(const lnum &l, const lnum &r) { return !(l == r); } inline void print() { if (base == 1000000000) { printf( %d , a.back()); for (int i = a.size() - 2; i >= 0; --i) printf( %09d , a[i]); } else { for (int i = a.size() - 1; i >= 0; --i) printf( %d , a[i]); } } }; vector<int> get(int n, int len) { vector<int> ret; ret.push_back(n); ret.push_back(-n); for (int i = 1, p = 10; i < len; ++i, p *= 10) { vector<int> a = get(n % p, i); vector<int> b = get(n / p, len - i); for (int i = 0; i < (int)(a.size()); i++) { for (int j = 0; j < (int)(b.size()); j++) { ret.push_back(a[i] * b[j]); ret.push_back(a[i] + b[j]); ret.push_back(a[i] - b[j]); } } } sort((ret).begin(), (ret).end()); ret.resize(unique((ret).begin(), (ret).end()) - ret.begin()); return ret; } int main() { int(k); input((k)); ; int(m); input((m)); ; set<string> s; char buf[10]; for (int i = 0; i < (int)(10000); i++) { vector<int> cur = get(i, 4); for (int j = 0; j < (int)(cur.size()); j++) { if (abs(k - cur[j]) < 10000) { sprintf(buf, %04d%04d , abs(k - cur[j]), i); sprintf(buf, %04d%04d , i, abs(k - cur[j])); s.insert(string(buf)); if ((int)s.size() >= m) break; } } if ((int)s.size() >= m) break; } for (__typeof((s).begin()) i = (s).begin(); i != (s).end(); i++) { cout << *i << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int a[1005]; int main() { int x, y, n; cin >> x >> y; int a[10] = {-x, -y, x - y, x, y, y - x}; cin >> n; int ans = (n + 2) % 6; a[ans] %= mod; if (a[ans] < 0) a[ans] += mod; cout << a[ans] << endl; return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Wed Jun 7 16:54:20 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.4 2006/06/22 07:19:59 wig Exp $
// $Date: 2006/06/22 07:19:59 $
// $Log: inst_t_e.v,v $
// Revision 1.4 2006/06/22 07:19:59 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No user `defines in this module
module inst_t_e
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire test1;
wire [127:0] unsplice_a1_no3;
wire [127:0] unsplice_a2_all128;
wire [127:0] unsplice_a3_up100;
wire [127:0] unsplice_a4_mid100;
wire [127:0] unsplice_a5_midp100;
wire [127:0] unsplice_bad_a;
wire [127:0] unsplice_bad_b;
// __I_NODRV_I wire [3:0] video_i; // __W_BAD_BRANCH
wire [31:0] widemerge_a1;
wire [31:0] widesig;
wire widesig_r_0;
wire widesig_r_1;
wire widesig_r_10;
wire widesig_r_11;
wire widesig_r_12;
wire widesig_r_13;
wire widesig_r_14;
wire widesig_r_15;
wire widesig_r_16;
wire widesig_r_17;
wire widesig_r_18;
wire widesig_r_19;
wire widesig_r_2;
wire widesig_r_20;
wire widesig_r_21;
wire widesig_r_22;
wire widesig_r_23;
wire widesig_r_24;
wire widesig_r_25;
wire widesig_r_26;
wire widesig_r_27;
wire widesig_r_28;
wire widesig_r_29;
wire widesig_r_3;
wire widesig_r_30;
wire widesig_r_4;
wire widesig_r_5;
wire widesig_r_6;
wire widesig_r_7;
wire widesig_r_8;
wire widesig_r_9;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
inst_a_e inst_a (
.p_mix_test1_go(test1), // Use internally test1
.unsplice_a1_no3(unsplice_a1_no3), // leaves 3 unconnected
.unsplice_a2_all128(unsplice_a2_all128), // full 128 bit port
.unsplice_a3_up100(unsplice_a3_up100), // connect 100 bits from 0
.unsplice_a4_mid100(unsplice_a4_mid100), // connect mid 100 bits
.unsplice_a5_midp100(unsplice_a5_midp100), // connect mid 100 bits
.unsplice_bad_a(unsplice_bad_a),
.unsplice_bad_b(unsplice_bad_b), // # conflict
.widemerge_a1(widemerge_a1),
.widesig_o(widesig),
.widesig_r_0(widesig_r_0),
.widesig_r_1(widesig_r_1),
.widesig_r_10(widesig_r_10),
.widesig_r_11(widesig_r_11),
.widesig_r_12(widesig_r_12),
.widesig_r_13(widesig_r_13),
.widesig_r_14(widesig_r_14),
.widesig_r_15(widesig_r_15),
.widesig_r_16(widesig_r_16),
.widesig_r_17(widesig_r_17),
.widesig_r_18(widesig_r_18),
.widesig_r_19(widesig_r_19),
.widesig_r_2(widesig_r_2),
.widesig_r_20(widesig_r_20),
.widesig_r_21(widesig_r_21),
.widesig_r_22(widesig_r_22),
.widesig_r_23(widesig_r_23),
.widesig_r_24(widesig_r_24),
.widesig_r_25(widesig_r_25),
.widesig_r_26(widesig_r_26),
.widesig_r_27(widesig_r_27),
.widesig_r_28(widesig_r_28),
.widesig_r_29(widesig_r_29),
.widesig_r_3(widesig_r_3),
.widesig_r_30(widesig_r_30),
.widesig_r_4(widesig_r_4),
.widesig_r_5(widesig_r_5),
.widesig_r_6(widesig_r_6),
.widesig_r_7(widesig_r_7),
.widesig_r_8(widesig_r_8),
.widesig_r_9(widesig_r_9)
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
inst_b_e inst_b (
.port_b_1(test1) // Use internally test1
);
// End of Generated Instance Port Map for inst_b
// Generated Instance Port Map for inst_c
inst_c_e inst_c (
);
// End of Generated Instance Port Map for inst_c
// Generated Instance Port Map for inst_d
inst_d_e inst_d (
);
// End of Generated Instance Port Map for inst_d
// Generated Instance Port Map for inst_e
inst_e_e inst_e (
.p_mix_unsplice_a1_no3_125_0_gi(unsplice_a1_no3[125:0]), // leaves 3 unconnected
.p_mix_unsplice_a1_no3_127_127_gi(unsplice_a1_no3[127]), // leaves 3 unconnected
.p_mix_unsplice_a2_all128_127_0_gi(unsplice_a2_all128), // full 128 bit port
.p_mix_unsplice_a3_up100_100_0_gi(unsplice_a3_up100[100:0]), // connect 100 bits from 0
.p_mix_unsplice_a4_mid100_99_2_gi(unsplice_a4_mid100[99:2]), // connect mid 100 bits
.p_mix_unsplice_a5_midp100_99_2_gi(unsplice_a5_midp100[99:2]), // connect mid 100 bits
.p_mix_unsplice_bad_a_1_1_gi(unsplice_bad_a[1]),
.p_mix_unsplice_bad_b_1_0_gi(unsplice_bad_b[1:0]), // # conflict
.p_mix_widemerge_a1_31_0_gi(widemerge_a1),
.p_mix_widesig_r_0_gi(widesig_r_0),
.p_mix_widesig_r_10_gi(widesig_r_10),
.p_mix_widesig_r_11_gi(widesig_r_11),
.p_mix_widesig_r_12_gi(widesig_r_12),
.p_mix_widesig_r_13_gi(widesig_r_13),
.p_mix_widesig_r_14_gi(widesig_r_14),
.p_mix_widesig_r_15_gi(widesig_r_15),
.p_mix_widesig_r_16_gi(widesig_r_16),
.p_mix_widesig_r_17_gi(widesig_r_17),
.p_mix_widesig_r_18_gi(widesig_r_18),
.p_mix_widesig_r_19_gi(widesig_r_19),
.p_mix_widesig_r_1_gi(widesig_r_1),
.p_mix_widesig_r_20_gi(widesig_r_20),
.p_mix_widesig_r_21_gi(widesig_r_21),
.p_mix_widesig_r_22_gi(widesig_r_22),
.p_mix_widesig_r_23_gi(widesig_r_23),
.p_mix_widesig_r_24_gi(widesig_r_24),
.p_mix_widesig_r_25_gi(widesig_r_25),
.p_mix_widesig_r_26_gi(widesig_r_26),
.p_mix_widesig_r_27_gi(widesig_r_27),
.p_mix_widesig_r_28_gi(widesig_r_28),
.p_mix_widesig_r_29_gi(widesig_r_29),
.p_mix_widesig_r_2_gi(widesig_r_2),
.p_mix_widesig_r_30_gi(widesig_r_30),
.p_mix_widesig_r_3_gi(widesig_r_3),
.p_mix_widesig_r_4_gi(widesig_r_4),
.p_mix_widesig_r_5_gi(widesig_r_5),
.p_mix_widesig_r_6_gi(widesig_r_6),
.p_mix_widesig_r_7_gi(widesig_r_7),
.p_mix_widesig_r_8_gi(widesig_r_8),
.p_mix_widesig_r_9_gi(widesig_r_9),
// __I_NODRV_I .video_i(video_i/__nodrv__),
.widesig_i(widesig)
);
// End of Generated Instance Port Map for inst_e
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; long long inv[5050 + 10], fac[5050 + 10], ifac[5050 + 10]; void setComb() { inv[0] = 1; inv[1] = 1; fac[1] = 1; ifac[1] = 1; fac[0] = 1; ifac[0] = 1; for (int i = 2; i < 5050; i++) { inv[i] = (-MOD / i) * inv[MOD % i] % MOD; fac[i] = fac[i - 1] * i % MOD; ifac[i] = ifac[i - 1] * inv[i] % MOD; inv[i] = (inv[i] + MOD) % MOD; fac[i] = (fac[i] + MOD) % MOD; ifac[i] = (ifac[i] + MOD) % MOD; } return; } long long comb(long long n, long long k) { if (n < k || n < 0 || k < 0) return 0; else return ((fac[n] * ifac[k] % MOD * ifac[n - k] % MOD + MOD) % MOD); } long long hcomb(long long n, long long r) { if (n == 0 && r == 0) return 1; else if (n < 0 || r < 0) return 0; else return comb(n + r - 1, r - 1); } int N; vector<int> A; long long dp[5050][5050]; long long cnt[5050]; void add(long long &a, long long b) { a = (a + b) % MOD; } void mul(long long &a, long long b) { a = a * b % MOD; } int main() { cin.tie(0); ios::sync_with_stdio(false); cin >> N; A.resize(N); for (int i = 0; i < (N); ++i) cin >> A[i]; sort(A.begin(), A.end()); for (int i = 0; i < (N); ++i) cnt[A[i]]++; setComb(); dp[0][0] = 1; for (int i = 0; i < N; i++) { long long sum = 0; for (int j = 0; j <= 5000; j++) { long long res = sum; mul(res, cnt[j]); mul(res, inv[N - i]); add(dp[i + 1][j], res); sum += dp[i][j]; } } long long ans = 0; for (int i = 1; i < N; i++) { for (int j = 0; j <= 5000; j++) { long long res = dp[i][j]; mul(res, cnt[j] - 1); mul(res, inv[N - i]); add(ans, res); } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; string months[] = { January , February , March , April , May , June , July , August , September , October , November , December }; int main() { string x; int k; cin >> x >> k; int curr = 0; for (curr = 0; months[curr] != x; curr++) ; curr = (curr + k) % 12; cout << months[curr]; }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module controls VGA output for Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module Computer_System_VGA_Subsystem_VGA_Controller (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 7;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 22;
parameter G_UI = 19;
parameter G_LI = 12;
parameter B_UI = 9;
parameter B_LI = 2;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule
|
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