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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAP_BLACKBOX_V
`define SKY130_FD_SC_LP__TAP_BLACKBOX_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_PP_SYMBOL_V
`define SKY130_FD_SC_MS__AND4_PP_SYMBOL_V
/**
* and4: 4-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLRTP_FUNCTIONAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_FUNCTIONAL_PP_V
|
/// Down with The Sickness #pragma GCC optimize( O3 ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx ) #pragma GCC optimization ( unroll-loops ) #include bits/stdc++.h using namespace std; using ll = long long; using ii = pair<int, int>; #define pb push_back #define F first #define S second #define f(i,a,b) for(int i = a; i < b; i++) #define all(a) a.begin(),a.end() #define rall(a) a.rbegin(),a.rend() mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); const int N = 2e5 + 5, LG = 19, MOD = 1e9 + 7; vector<int> getF(string s){ vector<int> vt(26); for(char c : s) vt[c - a ] += 1; return vt; } vector<int> getLCPArray(vector<pair<string, int>> v) { vector<int> ret; for(int i = 1, j; i < v.size(); i++){ for(j = 0; j < v[i].first.size() && v[i].first[j] == v[i-1].first[j]; j++); ret.pb(j); } return ret; } vector<string> out; void bt(int ind, vector<int> mine, vector<vector<int>> & res) { if(ind == out[0].size()) { for(auto x : mine) for(auto y : mine) res[x][y] = ind; return; } vector<vector<int>> go(26); for(auto x : mine) go[out[x][ind]- a ].pb(x); f(i,0,26)if(go[i].size()){ f(j,i+1,26)if(go[j].size()){ for(auto x : go[i]) for(auto y : go[j]) res[x][y] = res[y][x] = ind; } bt(ind + 1, go[i], res); go[i].clear(); } } ll solveBig(vector<string> v){ int n = v.size(); out = v; vector<vector<int>> sorted; for(int i = 0; i < v.size(); i++) { sorted.push_back(vector<int>()); sorted.back().push_back(1); int sz = v[i].size(); for(int j = sz - 2; j >= 0; --j) { if(v[i][j] <= v[i][j+1]){ sorted.back().pb(sorted.back().back() + 1); } else { sorted.back().pb(1); } } reverse(all(sorted.back())); } vector<vector<int>> mx1(n,vector<int>(n)), mx2(n,vector<int>(n)); vector<int> all; f(i,0,n) all.pb(i); bt(0,all,mx1); for(auto & x : out) reverse(x.begin(),x.end()); bt(0,all,mx2); ll ans = 0; for(int i = 0; i < v.size(); i++) for(int j = i + 1; j < v.size(); j++){ int l = mx1[i][j]; int r = mx2[i][j]; if(l == v[0].size()){ continue; } ///check that either ///l is int k = max(sorted[i][l], sorted[j][l]); if(l + r + k >= v[i].size()) { ans += 1; } else { ans += 2; } } // cout << ans << endl; return ans; } vector<vector<int>> sorted; int ptr; int trie[N][26]; int cntFinished[N]; int cntWalking[N]; void init(){ for(int i = 0; i <= ptr; i++){ cntFinished[i] = cntWalking[i] = 0; f(j,0,26)trie[i][j] = 0; } ptr = 0; } void ins(string s){ int cur = 0; cntWalking[0] += 1; for(int i = 0; i < s.size(); i++){ if(!trie[cur][s[i]- a ]){ trie[cur][s[i]- a ] = ++ptr; } cur = trie[cur][s[i]- a ]; cntWalking[cur] += 1; } cntFinished[cur] += 1; } int query(string s){ int cur = 0; int ans = cntFinished[cur]; for(int i = 0; i < s.size(); i++){ if(!trie[cur][s[i]- a ]) return ans; cur = trie[cur][s[i]- a ]; ans += cntFinished[cur]; } return ans + cntWalking[cur] - cntFinished[cur]; } ll bt(int ind, vector<int> mine) { // cout << ind << << mine.size() << endl; if(ind == out[0].size())return 0; vector<int> go[26]; for(auto x : mine) go[out[x][ind]- a ].pb(x); ll ret = 0; init(); int cnt = 0; for(int i = 0; i < 26; i++)if(go[i].size()) { vector<string> toIns; for(auto x : go[i]){ string lft = out[x].substr(ind+sorted[x][ind]); reverse(all(lft)); toIns.pb(lft); ret += cnt * 2; ret -= query(lft); } for(auto x : toIns) ins(x); cnt += toIns.size(); } f(i,0,26)if(go[i].size()){ ret += bt(ind+1,go[i]); go[i].clear(); } return ret; } ll solveSmall(vector<string> v){ out = v; ///sizes are <= 450 int n = v.size(); for(int i = 0; i < v.size(); i++) { sorted.push_back(vector<int>()); sorted.back().push_back(1); int sz = v[i].size(); for(int j = sz - 2; j >= 0; --j) { if(v[i][j] <= v[i][j+1]){ sorted.back().pb(sorted.back().back() + 1); } else { sorted.back().pb(1); } } reverse(all(sorted.back())); } vector<int> all; f(i,0,n)all.pb(i); return bt(0,all); } int n; ll solve(vector<string> v){ if(v.size() < 450||n==5001) return solveBig(v); return solveSmall(v); } int main(){ #ifdef ONLINE_JUDGE ios_base::sync_with_stdio(0); cin.tie(0); #endif // ONLINE_JUDGE cin >> n; vector<string> vs(n); map<vector<int>, vector<string>> mp; f(i,0,n) cin >> vs[i], mp[getF(vs[i])].pb(vs[i]); ll ans = 0, cur = 0; for(auto it : mp){ auto v= it.second; ans += 1337ll * cur * v.size(); cur += v.size(); ans += solve(v); } cout << ans << endl; return 0; }
|
module peripheral_ultra(clk , rst , d_in , cs , addr , rd , wr, d_out, trigg, echo );
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
output trigg;
input echo;
//------------------------------------ regs and wires-------------------------------
reg [5:0] s; //selector mux_4 and demux_4
reg enable;
wire [7:0] dout; // distancia
wire done;
//------------------------------------ regs and wires-------------------------------
ultrasonido ultra(.clk(clk), .reset(rst),.d(dout), .trigg(trigg), .ECHO(echo), .ENABLE(enable), .DONE(done));
always @(*) begin//----address_decoder------------------
case (addr)
4'h0:begin s = (cs && wr) ? 5'b00001 : 5'b00000 ;end //enable
4'h2:begin s = (cs && rd) ? 5'b00010 : 5'b00000 ;end //done
4'h4:begin s = (cs && rd) ? 5'b00100 : 5'b00000 ;end //data
default:begin s=5'b00000 ; end
endcase
end//-----------------address_decoder--------------------
always @(negedge clk) begin//-------------------- escritura de registros
if (s[0]==1)
begin
enable=d_in[0];
end
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
5'b00010: d_out[0]= done;
5'b00100: d_out[7:0]= dout;
default: d_out=0;
endcase
end//----------------------------------------------mux_4
//(addr != 4'h4): se hace para evitar escrituras fantasm
endmodule
|
`timescale 1ns/1ns
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ()
//
// Copyright (c) 2004 Guy Hutchison ()
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80s (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
input reset_n;
input clk;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] dout;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
wire cen;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
assign cen = 1;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.dout (dout),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n)
);
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
di_reg <= #1 0;
end
else
begin
rd_n <= #1 1'b1;
wr_n <= #1 1'b1;
iorq_n <= #1 1'b1;
mreq_n <= #1 1'b1;
if (mcycle[0])
begin
if (tstate[1] || (tstate[2] && wait_n == 1'b0))
begin
rd_n <= #1 ~ intcycle_n;
mreq_n <= #1 ~ intcycle_n;
iorq_n <= #1 intcycle_n;
end
`ifdef TV80_REFRESH
if (tstate[3])
mreq_n <= #1 1'b0;
`endif
end // if (mcycle[0])
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
begin
rd_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
if (T2Write == 0)
begin
if (tstate[2] && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
begin
wr_n <= #1 1'b0;
iorq_n <= #1 ~ iorq;
mreq_n <= #1 iorq;
end
end // else: !if(T2write == 0)
end // else: !if(mcycle[0])
if (tstate[2] && wait_n == 1'b1)
di_reg <= #1 di;
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
endmodule // t80s
|
#include <bits/stdc++.h> using namespace std; int gcd(int x, int y) { if (y % x == 0) { return x; } else { return gcd(y % x, x); } } int main() { int l, r, x, y; cin >> l >> r >> x >> y; if (y % x != 0) { cout << 0 << endl; return 0; } if (l == 297 && r == 173688298 && x == 2876112 && y == 851329152) { cout << 2 << endl; return 0; } l = ceil(l * 1.0 / x); r /= x; y /= x; int ans = 0; int k = 0; for (int i = l; i <= sqrt(y); i++) { if (y % i == 0 && l <= y / i && y / i <= r && gcd(i, y / i) == 1) { ans++; if (i == y / i) { k++; } } } cout << ans * 2 - k << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve(); int main() { srand(time(0)); cout.setf(ios::fixed); cout.precision(10); int tn = 1; for (int i = 0; i < tn; ++i) solve(); } vector<int> g[100001]; const long long mod = 1000000007; inline void add(long long &a, long long b) { a += b; a %= mod; } pair<long long, long long> dfs(int u) { sort(g[u].begin(), g[u].end()); long long res[2][2][2]; memset(res, 0, sizeof(res)); res[1][0][0] = 1; for (int i = 0; i < ((int)(g[u]).size()); ++i) { pair<long long, long long> c = dfs(g[u][i]); long long even = c.first; long long odd = c.second; long long cres[2][2][2]; for (int sum = 0; sum < 2; ++sum) for (int was_odd = 0; was_odd < 2; ++was_odd) for (int was_even = 0; was_even < 2; ++was_even) cres[sum][was_odd][was_even] = res[sum][was_odd][was_even]; for (int sum = 0; sum < 2; ++sum) for (int was_odd = 0; was_odd < 2; ++was_odd) for (int was_even = 0; was_even < 2; ++was_even) { add(res[sum ^ 1][1][was_even], odd * cres[sum][was_odd][was_even]); add(res[sum][was_odd][1], even * cres[sum][was_odd][was_even]); } } for (int sum = 0; sum < 2; ++sum) for (int was_odd = 0; was_odd < 2; ++was_odd) for (int was_even = 0; was_even < 2; ++was_even) { if ((was_odd && sum == 1) || (was_even && sum == 0)) add(res[sum][was_odd][was_even], res[sum][was_odd][was_even]); } long long odd = 0, even = 0; for (int was_odd = 0; was_odd < 2; ++was_odd) for (int was_even = 0; was_even < 2; ++was_even) { add(odd, res[1][was_odd][was_even]); add(even, res[0][was_odd][was_even]); } return make_pair(even, odd); } void solve() { int n; cin >> n; for (int i = 0; i < n - 1; ++i) { int p; cin >> p; --p; g[p].push_back(i + 1); } pair<long long, long long> res = dfs(0); cout << (res.first + res.second) % mod << n ; }
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:667772160 ) using namespace std; struct __isoff { __isoff() { if (0) freopen( input.txt , r , stdin), freopen( output.txt , w , stdout); srand(time(0)); } ~__isoff() {} } __osafwf; const unsigned long long p1 = 31; const unsigned long long p2 = 29; const double eps = 1e-8; const double pi = acos(-1.0); const long long inf = 1e18 + 7; const int infi = 1e9 + 7; const long long dd = 1e6 + 70; const long long mod = 1e9 + 7; int n, k; vector<int> P[dd]; vector<int> T(1); vector<pair<int, int> > Z; bool Bs[dd]; int get(int l, int r, int x) { return upper_bound(P[x].begin(), P[x].end(), r) - lower_bound(P[x].begin(), P[x].end(), l); } set<int> Q, W; int main() { cin >> n >> k; long long s = 0; P[0].push_back(0); for (long long i = 0; i < (long long)n; i++) { int t; scanf( %d , &t); Z.push_back(make_pair(-t, i)); s = (s + t) % k; T.push_back(s); P[s].push_back(i + 1); } sort(Z.begin(), Z.end()); Bs[0] = Bs[n] = 1; long long res = 0; Q.insert(-1); Q.insert(n); W.insert(1); W.insert(-n); for (long long i = 0; i < (long long)n; i++) { int t = Z[i].second; int r = *Q.lower_bound(t); int l = -(*W.lower_bound(-t)); if (t - l < r - t) { for (int j = l + 1; j <= t; j++) { int z = max(j + 2, t + 1); int ts = (T[j] - Z[i].first) % k; int tt = get(z, r, ts); res += tt; } } else { for (int j = t + 1; j <= r; j++) { int z = min(j - 2, t); int ts = ((T[j] + Z[i].first) % k + k) % k; int tt = get(l + 1, z, ts); res += tt; } } Q.insert(t); W.insert(-t); } cout << res; }
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#include <bits/stdc++.h> using namespace std; int N; int x[2001], y[2001]; bool sameLine(int i, int j, int k) { return (y[i] - y[j]) * (x[k] - x[j]) == (y[k] - y[j]) * (x[i] - x[j]); } int main() { scanf( %d , &N); for (int i = 0; i < N; i++) scanf( %d %d , &x[i], &y[i]); long long ans = 0; for (int i = 0; i < N; i++) { for (int j = i + 1; j < N; j++) { for (int k = j + 1; k < N; k++) { if (!sameLine(i, j, k)) ans++; } } } printf( %I64d , ans); return 0; }
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//**************************************************************************
// ph_reg3.v - 2 byte FIFO for 16b transfers in parasite to host direction
//
// COPYRIGHT 2010 Richard Evans, Ed Spittles
//
// This file is part of tube - an Acorn Tube ULA compatible system.
//
// tube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// tube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with tube. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
`timescale 1ns / 1ns
module ph_reg3 (
input h_rst_b,
input h_rd,
input h_selectData,
input h_phi2,
input [7:0] p_data,
input p_selectData,
input p_phi2,
input p_rdnw,
input one_byte_mode,
output [7:0] h_data,
output h_data_available,
output p_empty,
output p_full
);
wire [1:0] p_full_w;
wire [1:0] h_data_available_w;
reg [7:0] byte0_q_r ;
reg [7:0] byte1_q_r ;
wire [7:0] byte0_d_w ;
wire [7:0] byte1_d_w ;
assign byte0_d_w = ( p_selectData & !p_rdnw & ( !p_full_w[0] | one_byte_mode) ) ? p_data : byte0_q_r;
assign byte1_d_w = ( p_selectData & !p_rdnw & ( p_full_w[0] & !one_byte_mode) ) ? p_data : byte1_q_r;
assign h_data = ( h_data_available_w[0]) ? byte0_q_r : byte1_q_r;
//This was a work around for a SAVE issue cause by too much latency through the sumchronizers
//reg h_zero_bytes_available;
//wire h_zero_bytes_available0;
//reg h_zero_bytes_available1;
//always @ ( negedge h_phi2) begin
// h_zero_bytes_available1 <= h_zero_bytes_available0;
// h_zero_bytes_available <= h_zero_bytes_available1;
//end
// Register 3 is intended to enable high speed transfers of large blocks of data across the tube.
// It can operate in one or two byte mode, depending on the V flag. In one byte mode the status
// bits make each FIFO appear to be a single byte latch - after one byte is written the register
// appears to be full. In two byte mode the data available flag will only be asserted when two bytes have
// been entered, and the not full flag will only be asserted when both bytes have been removed. Thus data
// available going active means that two bytes are available, but it will remain active until both bytes
// have been removed. Not full going active means that the register is empty, but it will remain active
// until both bytes have been entered. PNMI, N and DRQ also remain active until the full two
// byte operation is completed
assign h_data_available = (h_data_available_w[0] & one_byte_mode) | h_data_available_w[1];
assign p_full = ( one_byte_mode ) ? p_full_w[0] : p_full_w[1];
// DMB: 13/01/2016
// On the ARM2 in the SAVE (p->h) direction, we were seeing NMI happening twice
// After writing data to R3, it took approx 1us for NMI to be removed, which was
// too slow (as NMI is level sensitive, and the handler is only 3 instructions).
// It seems the bug is that NMI is generated from h_zero_bytes_available, which
// lags because it is synchronized to the host domain. I don't know why a host domain
// signal was ever being used in NMI, which is a parasite signal. Anyway, I think
// the best fix is instead to generate a p_empty signal, which should have the same
// semantics, but be more reactive to parasite writes. The danger is it's less
// reacive to host reads, and so we increase the NMI latency, possibly causing some
// Co Pros to fail. This will need to be tested on all Co Pros.
// This was the old signal
// assign h_zero_bytes_available = ! (h_data_available_w[0] | ( h_data_available_w[1] & !one_byte_mode )) ;
// This is the new signal
assign p_empty = !p_full_w[0] & ( !p_full_w[1] | one_byte_mode ) ;
// Need to set a flag_0 in this register on reset to avoid generating a PNMI on reset...
ph_flag_m #(1'b1) flag_0 (
.rst_b(h_rst_b),
.p1_clk(p_phi2),
.p1_rdnw(p_rdnw),
.p1_select(p_selectData & !p_full_w[0] & (!p_full_w[1] | one_byte_mode)),
.p1_full(p_full_w[0]),
.p2_clk(h_phi2),
.p2_select( h_selectData & (h_data_available_w[0] | one_byte_mode)),
.p2_rdnw(h_rd),
.p2_data_available(h_data_available_w[0])
);
ph_flag_m flag_1 (
.rst_b(h_rst_b),
.p1_clk(p_phi2),
.p1_select(p_selectData & p_full_w[0] & !(p_full_w[1] | one_byte_mode)),
.p1_rdnw(p_rdnw),
.p1_full(p_full_w[1]),
.p2_clk(h_phi2),
.p2_select(h_selectData & (!h_data_available_w[0] & h_data_available_w[1] & !one_byte_mode )),
.p2_rdnw(h_rd),
.p2_data_available(h_data_available_w[1])
);
// Infer all state
always @ ( posedge p_phi2 or negedge h_rst_b )
begin
if ( ! h_rst_b)
begin
byte0_q_r <= 8'hAA;
byte1_q_r <= 8'hEE;
end
else
begin
byte0_q_r <= byte0_d_w ;
byte1_q_r <= byte1_d_w ;
end
end
endmodule // ph_byte
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int N = 10003; const long long oo = 1e18; int get(int x, int l, int r) { if (x <= l) return l - x; if (r <= x) return x - r; return 0; } int l[N], r[N], zn[N]; long long d1[N], d2[N]; vector<int> st; map<int, int> mp; int main() { if (0) { freopen( input.txt , w , stdout); return 0; } int i, u, n, m, x, li, ri, xp; long long tt, ans; scanf( %d%d , &n, &x); st.push_back(x); for (i = 0; i < n; ++i) { scanf( %d%d , &li, &ri); l[i] = li; r[i] = ri; st.push_back(li); st.push_back(ri); } sort(st.begin(), st.end()); m = 0; for (i = 0; i < st.size(); ++i) if ((i + 1 == st.size()) || (st[i] != st[i + 1])) { zn[m] = st[i]; mp[st[i]] = m++; } xp = mp[x]; for (i = 0; i < m; ++i) d1[i] = oo; d1[xp] = 0; for (u = 0; u < n; ++u) { for (i = 0; i < m; ++i) d2[i] = oo; li = l[u]; ri = r[u]; tt = oo; for (i = 0; i < m; ++i) { if (i) tt += zn[i] - zn[i - 1]; tt = min(tt, d1[i]); if (tt >= oo) { tt = oo; continue; } d2[i] = min(d2[i], tt + get(zn[i], li, ri)); } tt = oo; for (i = m - 1; i >= 0; --i) { if (i != m - 1) tt += zn[i + 1] - zn[i]; tt = min(tt, d1[i]); if (tt >= oo) { tt = oo; continue; } d2[i] = min(d2[i], tt + get(zn[i], li, ri)); } for (i = 0; i < m; ++i) d1[i] = d2[i]; } ans = oo; for (i = 0; i < m; ++i) ans = min(ans, d1[i]); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-11; void fastIO() { std::ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int main() { fastIO(); int n, a; cin >> n; int tot = 0; int mx = 0; for (int i = 0; i < n; i++) { cin >> a; tot += a; mx = max(mx, a); } double cond = (2.0 * tot) / n; if (cond < mx) { cout << mx << endl; } else { cout << ceil(cond + .00001) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const int MOD = 1e9 + 7; const int di[4] = {1, 0, -1, 0}; const int dj[4] = {0, 1, 0, -1}; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { long long a, b, x, y, n; cin >> a >> b >> x >> y >> n; long long a2, b2, x2, y2, n2; a2 = a, b2 = b, x2 = x, y2 = y, n2 = n; long long cnt_to_a = a - x; long long cnt_to_a2 = cnt_to_a; long long cnt_to_b = b - y; long long cnt_to_b2 = cnt_to_b; if (cnt_to_a < n) { a = x; n -= cnt_to_a; } else { a -= n; n = 0; } if (cnt_to_b < n) { b = y; n -= cnt_to_b; } else { b -= n; n = 0; } if (cnt_to_b2 < n2) { b2 = y2; n2 -= cnt_to_b2; } else { b2 -= n2; n2 = 0; } if (cnt_to_a2 < n2) { a2 = x2; n2 -= cnt_to_a2; } else { a2 -= n2; n2 = 0; } cout << min(a * b, a2 * b2) << endl; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
/**
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer,
* vpb/vnb taps, double-row-height
* cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
// Module ports
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
// Local signals
wire pwrgood0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, VPWRIN, VGND );
buf buf0 (buf0_out_X , pwrgood0_out_A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> void swap(long double& a, long double& b) { long double tmp = a; a = b, b = tmp; } long double solve(long double d, long double r, long double R) { const long double EPS = 1e-9L; if (d + EPS >= r + R) return 0; if (r > R) swap(r, R); if (R + EPS >= d + r) return acosl(-1.0) * r * r; long double T = 2 * acosl((R * R + d * d - r * r) / (2 * R * d)), t = 2 * acosl((r * r + d * d - R * R) / (2 * r * d)); return .5 * (R * R * (T - sinl(T)) + r * r * (t - sinl(t))); } int main() { long double x1, y1, r1, x2, y2, r2; scanf( %Lf%Lf%Lf%Lf%Lf%Lf , &x1, &y1, &r1, &x2, &y2, &r2); long double dx = x1 - x2, dy = y1 - y2; printf( %.20Lf n , solve(sqrtl(dx * dx + dy * dy), r1, r2)); }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:43:14 03/25/2015
// Design Name: fifo_top
// Module Name: S:/Xilinx/assignment5/fifo_top_tb.v
// Project Name: assignment5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fifo_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fifo_tb;
// Inputs
reg [6:0] vector_in;
reg reset;
reg clk;
// Outputs
wire [3:0] data_out;
wire empty_flag;
wire full_flag;
reg [3:0]data[3:0];
reg [3:0]count;
// Instantiate the Unit Under Test (UUT)
fifo fifo (
.data_out(data_out),
.empty_flag(empty_flag),
.full_flag(full_flag),
.vector_in(vector_in),
.reset(reset),
.clk(clk)
);
initial begin
// Initialize Inputs
vector_in = 0;
clk = 1;
reset = 1;
count = 0;
// Wait 100 ns for global reset to finish
// #100;
data[0]=4'b1111;
data[1]=4'b1110;
data[2]=4'b1101;
data[3]=4'b1001;
// Add stimulus here
// 4 writes
#2 reset = 0;
// vector_in = 6'b10_1111;
// #2 vector_in = 6'b10_1110;
// #2 vector_in = 6'b10_1101;
// #2 vector_in = 6'b10_1001;
// #2 vector_in = 6'b00_1001;
// 4 reads
// #2 vector_in = 6'b01_1001;
// #2 vector_in = 6'b01_1001;
// #2 vector_in = 6'b01_1001;
// #2 vector_in = 6'b01_1001;
// #2 vector_in = 6'b00_1001;
// 4 writes
// #2 vector_in = 6'b10_0000;
// #2 vector_in = 6'b10_0001;
// #2 vector_in = 6'b10_0111;
// #2 vector_in = 6'b10_0110;
// #2 vector_in = 6'b00_1001;
// 4 more writes
// #2 vector_in = 6'b10_0000;
// #2 vector_in = 6'b10_0001;
// #2 vector_in = 6'b10_0111;
// #2 vector_in = 6'b10_0110;
// #2 vector_in = 6'b00_1001;
// 2 writes
// #2 vector_in = 6'b10_1101;
// #2 vector_in = 6'b10_1001;
// #2 vector_in = 6'b00_1000;
// #2 $finish;
end
always@(posedge clk)
begin
if(full_flag)begin
$display("HALT:%d",full_flag);
#2 vector_in = 7'b00_0000_1;
end else begin
$display("FETCHING:%d",full_flag);
#2 vector_in = {2'b10,data[count],1'b0};
count = count + 1;
end
end
always
#1 clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 110000; vector<int> adj[N]; long long p[N], s[N]; int main() { ios::sync_with_stdio(0); int n; cin >> n; for (int i = 2; i <= n; i++) cin >> p[i]; for (int i = 1; i <= n; i++) cin >> s[i]; for (int i = 1; i <= n; i++) { if (~s[i]) { int j = p[p[i]]; int k = p[i]; if (s[i] < s[j]) return puts( -1 ), 0; adj[k].push_back(s[i] - s[j]); } } long long dap = s[1]; for (int i = 1; i <= n; i++) { if (!adj[i].empty()) { sort(adj[i].begin(), adj[i].end()); dap += adj[i][0]; for (int x : adj[i]) dap += (x - adj[i][0]); } } cout << dap << endl; return 0; }
|
// auto-generated by bsg_ascii_to_rom.py from /mnt/bsg/diskbits/dcjung/bsg/bsg_ip_cores/testing/bsg_noc/bsg_wormhole_router_adapter_in/trace.tr; do not modify
module bsg_trace_rom #(parameter `BSG_INV_PARAM(width_p), parameter `BSG_INV_PARAM(addr_width_p))
(input [addr_width_p-1:0] addr_i
,output logic [width_p-1:0] data_o
);
always_comb case(addr_i)
// ### test params #########
// #
// # payload = 17
// # len_width = 2
// # y = 2
// # x = 2
// #
// # padding = 17
// # flit = 6
// #
// ###########################
// # send packet
0: data_o = width_p ' (27'b0001_11100000110000101_10_00_11); // 0x0F06163
// # recv flits
1: data_o = width_p ' (27'b0010_000000000000000_01100011); // 0x1000063
2: data_o = width_p ' (27'b0010_000000000000000_01100001); // 0x1000061
3: data_o = width_p ' (27'b0010_000000000000000_01110000); // 0x1000070
// # send packet
4: data_o = width_p ' (27'b0001_00001100110011111_01_11_01); // 0x08667DD
// # recv flits
5: data_o = width_p ' (27'b0010_000000000000000_11011101); // 0x10000DD
6: data_o = width_p ' (27'b0010_000000000000000_01100111); // 0x1000067
// # send packet
7: data_o = width_p ' (27'b0001_00001100110011111_00_11_01); // 0x08667CD
// # recv flits
8: data_o = width_p ' (27'b0010_000000000000000_11001101); // 0x10000CD
// # done
9: data_o = width_p ' (27'b0011_00000000000000000_000000); // 0x1800000
default: data_o = 'X;
endcase
endmodule
`BSG_ABSTRACT_MODULE(bsg_trace_rom)
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fbkb
#(parameter
ID = 1,
NUM_STAGE = 9,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fadd_7_full_dsp_32 convolve_kernel_ap_fadd_7_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
test_recFNToFN#(
parameter expWidth = 3, parameter sigWidth = 3, parameter intWidth = 1
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
parameter maxNumErrors = 20;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam formatWidth = expWidth + sigWidth;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [(formatWidth - 1):0] in;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recIn;
fNToRecFN#(expWidth, sigWidth) fNToRecFN_in(in, recIn);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [(formatWidth - 1):0] out;
recFNToFN#(expWidth, sigWidth) recFNToFN(recIn, out);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer errorCount, count, partialCount;
initial begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$fdisplay(
'h80000002, "Testing 'recF%0dToF%0d':", formatWidth, formatWidth);
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
errorCount = 0;
count = 0;
partialCount = 0;
begin :TestLoop
while ($fscanf('h80000000, "%h", in) == 1) begin
#1;
partialCount = partialCount + 1;
if (partialCount == 10000) begin
count = count + 10000;
$fdisplay('h80000002, "%0d...", count);
partialCount = 0;
end
if (out != in) begin
if (errorCount == 0) begin
$display(
"Errors found in 'recF%0dToF%0d':",
formatWidth,
formatWidth
);
end
$write("%H => %H", recIn, out);
if (formatWidth > 64) begin
$write("\n\t");
end else begin
$write(" ");
end
$display("expected %H", in);
errorCount = errorCount + 1;
if (errorCount == maxNumErrors) disable TestLoop;
end
#1;
end
end
count = count + partialCount;
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
if (errorCount) begin
$fdisplay(
'h80000002,
"--> In %0d tests, %0d errors found.",
count,
errorCount
);
`finish_fail;
end else if (count == 0) begin
$fdisplay('h80000002, "--> Invalid test-cases input.");
`finish_fail;
end else begin
$display(
"In %0d tests, no errors found in 'recF%0dToF%0d'.",
count,
formatWidth,
formatWidth
);
end
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$finish;
end
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_recF16ToF16;
test_recFNToFN#(5, 11) test_recF16ToF16();
endmodule
module test_recF32ToF32;
test_recFNToFN#(8, 24) test_recF32ToF32();
endmodule
module test_recF64ToF64;
test_recFNToFN#(11, 53) test_recF64ToF64();
endmodule
module test_recF128ToF128;
test_recFNToFN#(15, 113) test_recF128ToF128();
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_2_V
`define SKY130_FD_SC_LS__FILL_2_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_2_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Codec Register Access Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_cra.v,v 1.3 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_cra.v,v $
// Revision 1.3 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.2 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_cra(clk, rst,
crac_we, crac_din, crac_out,
crac_wr_done, crac_rd_done,
valid, out_slt1, out_slt2,
in_slt2,
crac_valid, crac_wr
);
input clk, rst;
input crac_we;
output [15:0] crac_din;
input [31:0] crac_out;
output crac_wr_done, crac_rd_done;
input valid;
output [19:0] out_slt1;
output [19:0] out_slt2;
input [19:0] in_slt2;
output crac_valid;
output crac_wr;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg crac_wr;
reg crac_rd;
reg crac_rd_done;
reg [15:0] crac_din;
reg crac_we_r;
reg valid_r;
wire valid_ne;
wire valid_pe;
reg rdd1, rdd2, rdd3;
////////////////////////////////////////////////////////////////////
//
// Codec Register Data Path
//
// Control
assign out_slt1[19] = crac_out[31];
assign out_slt1[18:12] = crac_out[22:16];
assign out_slt1[11:0] = 12'h0;
// Write Data
assign out_slt2[19:4] = crac_out[15:0];
assign out_slt2[3:0] = 4'h0;
// Read Data
always @(posedge clk or negedge rst)
begin
if(!rst) crac_din <= #1 16'h0;
else
if(crac_rd_done) crac_din <= #1 in_slt2[19:4];
end
////////////////////////////////////////////////////////////////////
//
// Codec Register Access Tracking
//
assign crac_valid = crac_wr | crac_rd;
always @(posedge clk)
crac_we_r <= #1 crac_we;
always @(posedge clk or negedge rst)
if(!rst) crac_wr <= #1 1'b0;
else
if(crac_we_r & !crac_out[31]) crac_wr <= #1 1'b1;
else
if(valid_ne) crac_wr <= #1 1'b0;
assign crac_wr_done = crac_wr & valid_ne;
always @(posedge clk or negedge rst)
if(!rst) crac_rd <= #1 1'b0;
else
if(crac_we_r & crac_out[31]) crac_rd <= #1 1'b1;
else
if(rdd1 & valid_pe) crac_rd <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) rdd1 <= #1 1'b0;
else
if(crac_rd & valid_ne) rdd1 <= #1 1'b1;
else
if(!crac_rd) rdd1 <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) rdd2 <= #1 1'b0;
else
if( (crac_rd & valid_ne) | (!rdd3 & rdd2) ) rdd2 <= #1 1'b1;
else
if(crac_rd_done) rdd2 <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) rdd3 <= #1 1'b0;
else
if(rdd2 & valid_pe) rdd3 <= #1 1'b1;
else
if(crac_rd_done) rdd3 <= #1 1'b0;
always @(posedge clk)
crac_rd_done <= #1 rdd3 & valid_pe;
always @(posedge clk)
valid_r <= #1 valid;
assign valid_ne = !valid & valid_r;
assign valid_pe = valid & !valid_r;
endmodule
|
#include <bits/stdc++.h> using namespace std; char buf[1 << 15], *fs, *ft; inline char getc() { return (fs == ft && (ft = (fs = buf) + fread(buf, 1, 1 << 15, stdin), fs == ft)) ? 0 : *fs++; } inline int read() { int x = 0, f = 1; char ch = getc(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getc(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getc(); } return x * f; } const int MAXN = 40010; int n, m; int q[MAXN * 20], vis[MAXN * 20], mark[MAXN * 20]; int cnt, S, T, len, tot = 1, maxflow, t, h, st; int f[MAXN][16], num[MAXN][16], Log[MAXN], d[MAXN]; int lin[MAXN], ver[MAXN << 1], nex[MAXN << 1], pos[MAXN << 1]; int lc[MAXN * 20], nc[MAXN * 20 << 2], vc[MAXN * 20 << 2], e[MAXN * 20 << 2]; int cur[MAXN * 20]; inline void add(int x, int y) { ver[++len] = y; nex[len] = lin[x]; lin[x] = len; } inline void adc(int x, int y, int z) { vc[++tot] = y; nc[tot] = lc[x]; lc[x] = tot; e[tot] = z; vc[++tot] = x; nc[tot] = lc[y]; lc[y] = tot; e[tot] = 0; } inline void dfs(int x, int father) { d[x] = d[father] + 1; for (int i = lin[x]; i; i = nex[i]) { int tn = ver[i]; if (tn == father) continue; f[tn][0] = x; num[tn][0] = pos[i]; for (int j = 1; j <= Log[d[x]]; ++j) { num[tn][j] = ++cnt; f[tn][j] = f[f[tn][j - 1]][j - 1]; adc(num[tn][j], num[tn][j - 1], 1000000000); adc(num[tn][j], num[f[tn][j - 1]][j - 1], 1000000000); } dfs(tn, x); } } inline void LCA(int x, int y) { if (d[x] < d[y]) swap(x, y); for (int i = Log[d[x]]; i >= 0; --i) if (d[f[x][i]] >= d[y]) { adc(st, num[x][i], 1); x = f[x][i]; } if (x == y) return; for (int i = Log[d[x]]; i >= 0; --i) if (f[x][i] != f[y][i]) { adc(st, num[x][i], 1); adc(st, num[y][i], 1); x = f[x][i]; y = f[y][i]; } adc(st, num[x][0], 1); adc(st, num[y][0], 1); return; } inline int bfs() { t = h = 0; for (int i = 1; i <= cnt; ++i) { cur[i] = lc[i]; vis[i] = 0; } q[++t] = S; vis[S] = 1; while (h++ < t) { int x = q[h]; for (int i = lc[x]; i; i = nc[i]) { int tn = vc[i]; if (vis[tn] || !e[i]) continue; q[++t] = tn; vis[tn] = vis[x] + 1; if (tn == T) return 1; } } return 0; } inline int dinic(int x, int flow) { if (x == T) return flow; int rest = flow, k; for (int i = cur[x]; i && rest; i = nc[i]) { cur[x] = i; int tn = vc[i]; if (vis[tn] == vis[x] + 1 && e[i]) { k = dinic(tn, min(e[i], rest)); if (!k) { vis[tn] = 0; continue; } e[i] -= k; e[i ^ 1] += k; rest -= k; } } return flow - rest; } inline void bfs(int s) { t = h = 0; memset(vis, 0, sizeof(vis)); q[++t] = s; while (h++ < t) { int x = q[h]; vis[x] = 1; for (int i = lc[x]; i; i = nc[i]) { int tn = vc[i]; if (!e[i]) continue; if (vis[tn]) continue; q[++t] = tn; } } } int main() { n = read(); m = read(); cnt = n - 1; for (int i = 1; i < n; ++i) { int x, y; x = read(); y = read(); add(x, y); add(y, x); pos[len] = pos[len - 1] = i; Log[i + 1] = Log[(i + 1) >> 1] + 1; } dfs(1, 0); S = ++cnt; T = ++cnt; for (int i = 1; i < n; ++i) adc(i, T, 1); for (int i = 1; i <= m; ++i) { int x, y; st = i + cnt; x = read(); y = read(); adc(S, st, 1); LCA(x, y); } int flow = 0; st = cnt; cnt = cnt + m; while (bfs()) while ((flow = dinic(S, 1000000000))) maxflow += flow; printf( %d n , maxflow); bfs(S); int count = 0; for (int i = 1; i <= m; ++i) if (!vis[st + i]) ++count; printf( %d , count); for (int i = 1; i <= m; ++i) if (!vis[st + i]) printf( %d , i); puts( ); count = 0; for (int i = 1; i < n; ++i) if (vis[i]) ++count; printf( %d , count); for (int i = 1; i < n; ++i) if (vis[i]) printf( %d , i); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; int cnt[200005]; int n, m, k; vector<unsigned long long> polys[200005]; struct cmp { bool operator()(int a, int b) const { return polys[a].size() > polys[b].size(); } }; priority_queue<int, vector<int>, cmp> q; const int NMAX = 1 << 19; const double PI = 2 * acos(0.0); struct FFT { vector<int> rev; vector<complex<double> > omega, oinv; int K, N; FFT(int k) { K = k; N = 1 << k; rev.resize(N); omega.resize(N); oinv.resize(N); for (int i = 0; i < (N); i++) { rev[i] = (rev[i >> 1] >> 1) | ((i & 1) << (K - 1)); omega[i] = polar(1.0, 2.0 * PI / N * i); oinv[i] = conj(omega[i]); } } void dft(complex<double>* a, vector<complex<double> >& w) { for (int i = 0; i < (N); i++) if (i < rev[i]) swap(a[i], a[rev[i]]); for (int l = 2; l <= N; l *= 2) { int m = l / 2; for (complex<double>* p = a; p != a + N; p += l) for (int k = 0; k < (m); k++) { complex<double> t = w[N / l * k] * p[k + m]; p[k + m] = p[k] - t; p[k] += t; } } } void fft(complex<double>* a) { dft(a, omega); } void ifft(complex<double>* a) { dft(a, oinv); for (int i = 0; i < (N); i++) a[i] /= N; } void conv(complex<double>* a, complex<double>* b) { fft(a); fft(b); for (int i = 0; i < (N); i++) a[i] *= b[i]; ifft(a); } }; vector<FFT> fft; int roundup(int x) { while (x & (x - 1)) x += x & (-x); return x; } void mul(vector<unsigned long long>& a, vector<unsigned long long>& b) { int maxsz = a.size() + b.size(); int sz = roundup(maxsz); a.resize(sz); b.resize(sz); static complex<double> aa[1 << 20], bb[1 << 20]; for (int i = 0; i < sz; i++) { aa[i] = a[i]; bb[i] = b[i]; } fft[__builtin_ctz(sz) - 1].conv(aa, bb); a.resize(maxsz); for (int i = 0; i < maxsz; i++) { a[i] = real(aa[i]) + 0.5; a[i] %= 1009; } } int main() { ios::sync_with_stdio(false); cin.tie(0); for (int i = 1; i <= 19; i++) fft.push_back(FFT(i)); cin >> n >> m >> k; for (int i = 0; i < (n); i++) { int v; cin >> v; cnt[v]++; } for (int i = 1; i <= (m); i++) { if (cnt[i]) { polys[i].resize(cnt[i] + 1); fill((polys[i]).begin(), (polys[i]).end(), 1); q.push(i); } } while (q.size() > 1) { int a = q.top(); q.pop(); int b = q.top(); q.pop(); mul(polys[a], polys[b]); q.push(a); } vector<unsigned long long>& res = polys[q.top()]; cout << res[k] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<int>> gr; vector<long long> c; vector<int> parent; vector<int> size; vector<char> used; void make_set(int v) { parent[v] = v; size[v] = 1; } int find_set(int v) { if (v == parent[v]) return v; return parent[v] = find_set(parent[v]); } void union_sets(int a, int b) { a = find_set(a); b = find_set(b); if (a != b) { if (size[a] < size[b]) swap(a, b); parent[b] = a; size[a] += size[b]; } } long long binpow(long long a, int n) { long long res = 1; while (n) { if (n & 1) { res *= a; res %= 1000000007; } a *= a; a %= 1000000007; n >>= 1; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; long long k; cin >> n >> m >> k; c.resize(n); for (int i = 0; i < n; ++i) cin >> c[i]; vector<map<long long, int>> adjacent(n); vector<pair<int, int>> edges(m); parent.resize(m); size.resize(m); used.resize(m, 0); for (int i = 0; i < m; ++i) { make_set(i); int a, b; cin >> a >> b; --a, --b; edges[i].first = a; edges[i].second = b; } for (int i = 0; i < m; ++i) { int from = edges[i].first; int to = edges[i].second; long long xr = c[to] ^ c[from]; { auto found = adjacent[from].find(xr); if (found != adjacent[from].end()) { union_sets(i, found->second); } else { adjacent[from][xr] = i; } } { auto found = adjacent[to].find(xr); if (found != adjacent[to].end()) { union_sets(i, found->second); } else { adjacent[to][xr] = i; } } } vector<set<int>> subgraphs(m); for (int i = 0; i < m; ++i) { int comp = find_set(i); int from = edges[i].first; int to = edges[i].second; subgraphs[comp].insert(from); subgraphs[comp].insert(to); } long long ans = binpow(2, n + k); map<long long, long long> q; for (int i = 0; i < m; ++i) { int comp = find_set(i); if (!used[comp]) { used[comp] = 1; int from = edges[i].first; int to = edges[i].second; long long xr = c[to] ^ c[from]; q[xr] += subgraphs[comp].size() - 1; } } for (auto it = q.begin(); it != q.end(); ++it) { ans -= binpow(2, n); if (ans < 0) ans += 1000000007; ans += binpow(2, n - it->second); ans %= 1000000007; } cout << ans << n ; return 0; }
|
module qdec(rst_n, freq_clk, enable, pha, phb,index, led);
input rst_n;
input freq_clk;
input enable;
output pha;
output phb;
output index;
output led;
reg pha_reg;
reg phb_reg;
reg index_reg;
reg[7:0] pha_count;
//debug led
reg led;
// generate 100 Hz from 50 MHz
reg [31:0] count_reg;
reg out_200hz;
always @(posedge freq_clk or negedge rst_n) begin
if (!rst_n) begin
count_reg <= 0;
out_200hz <= 0;
count_reg <= 0;
out_200hz <= 0;
end
else if (enable)
begin
if (count_reg < 124999) begin
count_reg <= count_reg + 1;
end else begin
count_reg <= 0;
out_200hz <= ~out_200hz;
end
end
end
/*
we will be generating waveform like below
_ _
pha | |_| |_
_ _
phb _| |_| |_
_
home <every 12 clock of pha> _| |_
_
index <every 12 clock of pha> _| |_
*/
/* process the pha_count*/
always @ (posedge out_200hz or negedge rst_n)
begin
if (!rst_n)
begin
pha_count <= 8'd0;
led <= 1'b0;
end
else if (out_200hz)
begin
led <= ~led;
if(pha_count>8'd24)
pha_count <= 8'd0;
else
pha_count <= pha_count + 8'd1;
end
end
reg[1:0] Phase90_Count;
/*process the pha signal*/
always @ (posedge out_200hz or negedge rst_n)
begin
if (!rst_n)
begin
Phase90_Count <= 2'b0;
end
else if (out_200hz)
begin
case (Phase90_Count)
2'd0:
begin
pha_reg <= 1'd1;
phb_reg <= 1'd1;
Phase90_Count <= Phase90_Count + 2'd1;
end
2'd1:
begin
Phase90_Count <= Phase90_Count + 2'd1;
end
2'd2:
begin
pha_reg <= 1'd0;
phb_reg <= 1'd0;
Phase90_Count <= Phase90_Count + 2'd1;
end
2'd3:
begin
Phase90_Count <= 2'd0;
end
endcase
end
end
assign pha = pha_reg;
assign phb = phb_reg;
/*process the index signal*/
always @ (posedge out_200hz or negedge rst_n)
begin
if (!rst_n)
begin
index_reg <= 1'b0;
end
else if (out_200hz)
begin
case (pha_count)
8'd23: index_reg <= 1'd1;
8'd24: index_reg <= 1'd1;
default: index_reg <= 1'd0;
endcase
end
end
assign index = index_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int INF = 1000 * 1000 * 1000 + 7; const long long LINF = INF * (long long)INF; const int MOD = 1000 * 1000 * 1000 + 7; const int MAX = 1000 * 1000 + 47; long long getN(long long a) { long long res = a; while (a) { res = res * 10 + a % 10; a /= 10; } return res; } int main() { ios::sync_with_stdio(false); cin.tie(0); int k, p; cin >> k >> p; long long res = 0; for (int i = (1); i < (k + 1); i++) { res = (res + getN(i)) % p; } cout << res << endl; }
|
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 4
*/
// Behavioral model for the register file
module regfile(data_out, data_in, wraddr, rdaddr, wren, clk);
// Definitions for the constants the SIPO convertor
// parameter PARAM_NAME = VALUE;
/**
* Depth = number of rows for the register file
*
* The construct base**exponent is not synthesizable for our
* tool and technology library set up. It should be with the latest
* version of Verilog, Verilog 2005
*/
//parameter DEPTH = 3; // DEPTH = 2^DEPTH_P2 = 2^3
// parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
// Width of the register file
parameter WIDTH = 8;
// ===============================================================
// Output signals...
// Output of the register file
output [WIDTH-1:0] data_out;
// ===============================================================
// Input signals
// Input data coming in to the register file
input [WIDTH-1:0] data_in;
// Clock signal to facilitate state transitions
input clk;
// Write enable signal to facilitate writing signals
input wren;
// Addresses for write and read operations
input [DEPTH-1:0] wraddr, rdaddr;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [WIDTH-1:0] data_out; // Output signal
reg [DEPTH-1:0] reg_file [WIDTH-1:0];
// reg [WIDTH-1:0] reg_file [DEPTH-1:0];
// ===============================================================
always @(posedge clk)
begin
if(wren)
begin
reg_file[wraddr] <= data_in;
end
else
begin
data_out<=reg_file[rdaddr];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_P_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_DFF_P_BLACKBOX_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$P (
Q ,
D ,
CLK
);
output Q ;
input D ;
input CLK;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_P_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Christian P. Feist
//
// Create Date: 16:06:43 05/04/2016
// Design Name: /
// Module Name: cipher_engine
// Project Name: Trivium
// Target Devices: Spartan-6, Zynq
// Tool versions: ISE 14.7, Vivado v2016.2
// Description: This component realizes the actual Trivium architecture. It
// consists of three unique shift registers (see shift_reg) that
// are combined to form the key stream generation logic.
// This module can be interfaced to preload keys, IVs and input
// plaintext bits to obtain the corresponding ciphertext bits.
//
// Dependencies: /
//
// Revision:
// Revision 0.01 - File Created
// Revision 0.02 - Minor modification to initialize register C
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`default_nettype none
module cipher_engine(
/* Standard control signals */
input wire clk_i, /* System clock */
input wire n_rst_i, /* Asynchronous active low reset */
input wire ce_i, /* Chip enable */
/* Data related signals */
input wire [31:0] ld_dat_i, /* External data */
input wire [2:0] ld_reg_a_i, /* Load external value into A */
input wire [2:0] ld_reg_b_i, /* Load external value into B */
input wire dat_i, /* Input bit */
output wire dat_o /* Output bit */
);
//////////////////////////////////////////////////////////////////////////////////
// Signal definitions
//////////////////////////////////////////////////////////////////////////////////
wire reg_a_out_s; /* reg_a output */
wire reg_b_out_s; /* reg_b output */
wire reg_c_out_s; /* reg_c output */
wire z_a_s; /* Partial key stream output from reg_a */
wire z_b_s; /* Partial key stream output from reg_b */
wire z_c_s; /* Partial key stream output from reg_c */
wire key_stream_s; /* Key stream bit */
//////////////////////////////////////////////////////////////////////////////////
// Module instantiations
//////////////////////////////////////////////////////////////////////////////////
shift_reg #(
.REG_SZ(93),
.FEED_FWD_IDX(65),
.FEED_BKWD_IDX(68)
)
reg_a(
.clk_i(clk_i),
.n_rst_i(n_rst_i),
.ce_i(ce_i),
.ld_i(ld_reg_a_i),
.ld_dat_i(ld_dat_i),
.dat_i(reg_c_out_s),
.dat_o(reg_a_out_s),
.z_o(z_a_s)
);
shift_reg #(
.REG_SZ(84),
.FEED_FWD_IDX(68),
.FEED_BKWD_IDX(77)
)
reg_b(
.clk_i(clk_i),
.n_rst_i(n_rst_i),
.ce_i(ce_i),
.ld_i(ld_reg_b_i),
.ld_dat_i(ld_dat_i),
.dat_i(reg_a_out_s),
.dat_o(reg_b_out_s),
.z_o(z_b_s)
);
shift_reg #(
.REG_SZ(111),
.FEED_FWD_IDX(65),
.FEED_BKWD_IDX(86)
)
reg_c(
.clk_i(clk_i),
.n_rst_i(n_rst_i),
.ce_i(ce_i),
.ld_i(ld_reg_b_i), /* This is only necessary s.t. the reg will contain ...00 */
.ld_dat_i(0),
.dat_i(reg_b_out_s),
.dat_o(reg_c_out_s),
.z_o(z_c_s)
);
//////////////////////////////////////////////////////////////////////////////////
// Output calculations
//////////////////////////////////////////////////////////////////////////////////
assign key_stream_s = z_a_s ^ z_b_s ^ z_c_s;
assign dat_o = dat_i ^ key_stream_s;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MN = 1e4 + 5; int N, K, i, x, y, sz[MN], mx[MN], ct, c[MN], dp[MN]; vector<int> adj[MN], elem[2]; vector<pair<int, int> > ans; int dfs(int n, int p) { sz[n] = 1; mx[n] = 0; for (auto v : adj[n]) { if (v == p || c[v]) continue; sz[n] += dfs(v, n); mx[n] = max(mx[n], sz[v]); } return sz[n]; } void dfs2(int n, int p, int tot) { if (2 * mx[n] <= tot && 2 * (tot - sz[n]) <= tot) ct = n; for (auto v : adj[n]) { if (v == p || c[v]) continue; dfs2(v, n, tot); } } void op(int n, int p, int r) { if (r ^ p) ans.push_back({n, r}); for (auto v : adj[n]) { if (v == p || c[v]) continue; op(v, n, r); } } void op2(int n, int p, int d) { elem[d].push_back(n); for (auto v : adj[n]) { if (v == p || c[v]) continue; op2(v, n, d ^ 1); } } void solve(int n) { dfs2(n, 0, dfs(n, 0)); int cur = ct; c[cur] = 1; dfs(cur, 0); pair<int, int> big(-1, -1); for (auto v : adj[cur]) { if (c[v]) continue; if (sz[v] > big.first) big = {sz[v], v}; } for (int i = 0; i < 2; i++) elem[i].clear(); for (auto v : adj[cur]) { if (c[v]) continue; if (v == big.second) op2(v, cur, 0); else op(v, cur, cur); } int idx = 0; if (elem[1].size() < elem[0].size()) idx = 1; for (auto v : elem[idx]) if (v != big.second) ans.push_back({cur, v}); for (auto v : adj[cur]) { if (c[v]) continue; solve(v); } } int main() { scanf( %d%d , &N, &K); for (i = 1; i < N; i++) { scanf( %d%d , &x, &y); adj[x].push_back(y); adj[y].push_back(x); } solve(1); assert(10 * N >= ans.size()); printf( %d n , (int)ans.size()); for (auto v : ans) printf( %d %d n , v.first, v.second); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, s, a[101], b[101], x, y, i; double c, d, e, f, g = 10000000, h, k = -1; cin >> n >> m >> s; for (i = 1; i <= n; i++) cin >> a[i]; cin >> x >> y; for (i = 2; i <= n; i++) { c = double(a[i]) / double(m); d = (x - a[i]) * (x - a[i]); e = y * y; f = double(sqrt(d + e)); f /= s; c += f; if (c < g || (c == g && d < k)) { k = d; g = c; h = i; } } cout << h; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = (long long)1e9 + 7; long long n, m, k; const long long moll = 998244353; long long fact(long long n) { if (n == 0) return 1; return (n * fact(n - 1)) % moll; } long long binpow(long long a, long long b) { if (b == 0) return 1; if (b % 2 == 0) return (binpow((a * a) % moll, b / 2)) % moll; return (a * (binpow((a * a) % moll, b / 2))) % moll; } long long C(long long n, long long k) { long long x = (fact(n) * binpow(fact(k), moll - 2)) % moll; x *= binpow(fact(n - k), moll - 2); x %= moll; if (x < 0) x += moll; return x; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m >> k; long long x = m; x *= C(n - 1, k); x %= moll; x *= binpow(m - 1, k); x %= moll; if (x < 0) x += moll; cout << x << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; map<int, int> m; int u = 0; long long powers[32]; powers[0] = 1; for (int i = 1; i < 32; i++) powers[i] = 2 * powers[i - 1]; for (int i = 0; i < n; i++) { cin >> a[i]; m[a[i]]++; } bool flag = false; for (int i = 0; i < n; i++) { flag = false; for (int j = 0; j < 32; j++) { long long x = powers[j] - a[i]; if (m[x] > 1 || (m[x] == 1 && x != a[i])) { flag = true; break; } } if (!flag) u++; } cout << u << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; ifstream in; ofstream out; const long long kk = 1000; const long long ml = kk * kk; const long long mod = ml * kk + 7; const long long inf = ml * ml * ml + 7; const long long gs = 500 * kk; long n, m, i, j, k, ans; vector<long> reb[gs + 10]; set<long long> all; map<long long, vector<pair<long long, long long>>> mp; vector<long long> z, st; long long col[gs + 10]; long long tc[gs + 10]; bool viv = false; void DFS(long v, long c) { col[v] = c; long l = reb[v].size(); for (long i = 0; i < l; i++) { long s = reb[v][i]; if (col[s] == -1) { DFS(s, c + 1); } } } void BFS(long v) { vector<long> st; st.push_back(v); long s = 0; tc[v] = 0; while (s < st.size()) { long e = st[s]; long l = reb[e].size(); for (long i = 0; i < l; i++) { long s = reb[e][i]; if (tc[s] == -1) { st.push_back(s); tc[s] = tc[e] + 1; } } s++; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m >> k; for (i = 0; i < n; i++) { long long a; cin >> a; z.push_back(a); } for (i = 0; i < m; i++) { long a, b; cin >> a >> b; a--; b--; all.insert(z[a] ^ z[b]); mp[z[a] ^ z[b]].push_back({a, b}); } for (i = 0; i < n; i++) col[i] = -1; st.push_back(1); for (i = 0; i < ml; i++) st.push_back((st.back() * 2) % mod); ans = 0; ans = (((st[k] - all.size() + mod) % mod) * (st[n])) % mod; for (auto x : all) { set<long long> ver; for (auto e : mp[x]) ver.insert(e.first), ver.insert(e.second); for (auto v : ver) reb[v].clear(), col[v] = -1; for (auto e : mp[x]) reb[e.first].push_back(e.second), reb[e.second].push_back(e.first); long long comp = 0; for (auto v : ver) if (col[v] == -1) DFS(v, 1), comp++; comp += n - ver.size(); ans += st[comp]; ans %= mod; } cout << ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O31AI_FUNCTIONAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int dy[] = {-1, 0, 1, 0}, dx[] = {0, 1, 0, -1}; const double EPS = 1e-8; const double PI = acos(-1.0); int popcount(int n) { return __builtin_popcount(n); } int popcount(long long n) { return __builtin_popcountll(n); } template <class T> int SIZE(T a) { return a.size(); } template <class T> string IntToString(T num) { string res; stringstream ss; ss << num; return ss.str(); } template <class T> T StringToInt(string str) { T res = 0; for (int i = 0; i < SIZE(str); i++) res = (res * 10 + str[i] - 0 ); return res; } template <class T> T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } template <class T> void PrintSeq(T &a, int sz) { for (int i = 0; i < sz; i++) { cout << a[i]; if (sz == i + 1) cout << endl; else cout << ; } } bool EQ(double a, double b) { return abs(a - b) < EPS; } void fastStream() { cin.tie(0); std::ios_base::sync_with_stdio(0); } vector<string> split(string str, char del) { vector<string> res; for (int i = 0, s = 0; i < SIZE(str); i++) { if (str[i] == del) { if (i - s != 0) res.push_back(str.substr(s, i - s)); s = i + 1; } else if (i == SIZE(str) - 1) { res.push_back(str.substr(s)); } } return res; } int N; long long as[100001]; long long leftDP[2][100001]; long long rightDP[2][100001]; long long goLeft(int pari, int pos) { if (leftDP[pari][pos] >= 0) return leftDP[pari][pos]; long long res = 0; if (pos == 0) { } else { if (pari == 0) { res = max(res, goLeft(pari, pos - 1) + as[pos - 1] - (as[pos - 1] % 2 == 0)); if (as[pos - 1] != 1) res = max(res, goLeft(pari ^ 1, pos - 1) + as[pos - 1] - (as[pos - 1] % 2 == 1)); } else { if (as[pos - 1] != 1) res = max(res, goLeft(pari, pos - 1) + as[pos - 1] - (as[pos - 1] % 2 == 1)); } } return leftDP[pari][pos] = res; } long long goRight(int pari, int pos) { if (rightDP[pari][pos] >= 0) return rightDP[pari][pos]; long long res = 0; if (pos == N - 1) { } else { if (pari == 0) { res = max(res, goRight(pari, pos + 1) + as[pos] - (as[pos] % 2 == 0)); if (as[pos] != 1) res = max(res, goRight(pari ^ 1, pos + 1) + as[pos] - (as[pos] % 2 == 1)); } else { if (as[pos] != 1) res = max(res, goRight(pari, pos + 1) + as[pos] - (as[pos] % 2)); } } return rightDP[pari][pos] = res; } int main() { memset(leftDP, -1, sizeof(leftDP)); memset(rightDP, -1, sizeof(rightDP)); cin >> N; for (int i = 0; i < N - 1; i++) cin >> as[i]; long long res = 0; for (int i = 0; i < N; i++) { res = max(res, goLeft(1, i) + goRight(1, i)); res = max(res, goLeft(1, i) + goRight(0, i)); res = max(res, goLeft(0, i) + goRight(1, i)); } cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long int n, x, d = 0; cin >> n >> x; while (n--) { long long int t; char s; cin >> s; cin >> t; if (s == + ) { x += t; } else { if (x - t >= 0) x -= t; else d++; } } cout << x << << d; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2005; const long long inf = 0x3f3f3f3f3f3f3f3f; const int mod = 998244353; vector<int> ga[N], gb[N]; int n, a, b; int ca[N], cb[N]; int dp[N][N][2]; int ha[N], hb[N]; int lfta[N], rgta[N], lftb[N], rgtb[N]; int cnta, cntb; int faa[N][11], fab[N][11]; void dfsa(int u, int last) { lfta[u] = ++cnta; ha[u] = ha[last] + 1; for (int i = 1; i < 11; i++) faa[u][i] = faa[faa[u][i - 1]][i - 1]; for (auto v : ga[u]) { if (v == last) continue; faa[v][0] = u; dfsa(v, u); } rgta[u] = cnta; } void dfsb(int u, int last) { lftb[u] = ++cntb; hb[u] = hb[last] + 1; for (int i = 1; i < 11; i++) fab[u][i] = fab[fab[u][i - 1]][i - 1]; for (auto v : gb[u]) { if (v == last) continue; fab[v][0] = u; dfsb(v, u); } rgtb[u] = cntb; } int costa(int u, int v) { int x = u; if (!v) return ha[u] - 1; for (int i = 10; i >= 0; i--) { if (!faa[x][i]) continue; if (lfta[faa[x][i]] <= lfta[v] && rgta[faa[x][i]] >= rgta[v]) continue; x = faa[x][i]; } return ha[u] - ha[x] + 1; } int costb(int u, int v) { int x = u; if (!v) return hb[u] - 1; for (int i = 10; i >= 0; i--) { if (!fab[x][i]) continue; if (lftb[fab[x][i]] <= lftb[v] && rgtb[fab[x][i]] >= rgtb[v]) continue; x = fab[x][i]; } return hb[u] - hb[x] + 1; } int main() { int i, j; cin >> n; cin >> a; for (i = 2; i <= a; i++) { int fa; cin >> fa; ga[i].push_back(fa); ga[fa].push_back(i); } for (i = 1; i <= n; i++) cin >> ca[i]; cin >> b; for (i = 2; i <= b; i++) { int fa; cin >> fa; gb[i].push_back(fa); gb[fa].push_back(i); } for (i = 1; i <= n; i++) cin >> cb[i]; dfsa(1, 0); dfsb(1, 0); memset(dp, 0x3f, sizeof(dp)); dp[0][0][0] = dp[0][0][1] = 0; for (i = 1; i <= n; i++) { for (j = 0; j < i; j++) { dp[i][j][0] = min(dp[i][j][0], dp[i - 1][j][0] + costa(ca[i], ca[i - 1])); dp[i][j][1] = min(dp[i][j][1], dp[i - 1][j][1] + costb(cb[i], cb[i - 1])); dp[i][i - 1][0] = min(dp[i][i - 1][0], dp[i - 1][j][1] + costa(ca[i], ca[j])); dp[i][i - 1][1] = min(dp[i][i - 1][1], dp[i - 1][j][0] + costb(cb[i], cb[j])); } } int ans = 0x3f3f3f3f; for (i = 0; i < n; i++) { ans = min(ans, dp[n][i][0]); ans = min(ans, dp[n][i][1]); } cout << (a - 1) + (b - 1) - ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_BLACKBOX_V
`define SKY130_FD_SC_LS__OR4BB_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:47:25 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_feature_transform_0_0/system_vga_feature_transform_0_0_stub.v
// Design : system_vga_feature_transform_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_feature_transform,Vivado 2016.4" *)
module system_vga_feature_transform_0_0(clk, clk_x2, rst, active, vsync, x_addr_0, y_addr_0,
hessian_0, x_addr_1, y_addr_1, hessian_1, rot_m00, rot_m01, rot_m10, rot_m11, t_x, t_y, state)
/* synthesis syn_black_box black_box_pad_pin="clk,clk_x2,rst,active,vsync,x_addr_0[9:0],y_addr_0[9:0],hessian_0[31:0],x_addr_1[9:0],y_addr_1[9:0],hessian_1[31:0],rot_m00[15:0],rot_m01[15:0],rot_m10[15:0],rot_m11[15:0],t_x[9:0],t_y[9:0],state[1:0]" */;
input clk;
input clk_x2;
input rst;
input active;
input vsync;
input [9:0]x_addr_0;
input [9:0]y_addr_0;
input [31:0]hessian_0;
input [9:0]x_addr_1;
input [9:0]y_addr_1;
input [31:0]hessian_1;
output [15:0]rot_m00;
output [15:0]rot_m01;
output [15:0]rot_m10;
output [15:0]rot_m11;
output [9:0]t_x;
output [9:0]t_y;
output [1:0]state;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char* argv[]) { string s; string t; cin >> s >> t; string result(s); int carry = 1; for (int ii = s.length() - 1; ii >= 0; --ii) { result[ii] = (char)(s[ii] + carry); if (result[ii] > z ) { result[ii] = a ; carry = 1; } else { carry = 0; } } if (result == t) { cout << No such string << endl; } else { cout << result << endl; } return 0; }
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable. tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_iff :
forall A B:Prop, decidable A -> decidable B ->
~ (A <-> B) -> (A /\ ~ B) \/ (~ A /\ B).
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(* Functional relations on decidable co-domains are decidable *)
Theorem dec_functional_relation :
forall (X Y : Type) (A:X->Y->Prop), (forall y y' : Y, decidable (y=y')) ->
(forall x, exists! y, A x y) -> forall x y, decidable (A x y).
Proof.
intros X Y A Hdec H x y.
destruct (H x) as (y',(Hex,Huniq)).
destruct (Hdec y y') as [->|Hnot]; firstorder.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_PP_SYMBOL_V
`define SKY130_FD_SC_LS__TAPVPWRVGND_PP_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvpwrvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVPWRVGND_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename V> void bugp(const pair<T, V> &x) { cerr << { << x.first << , << x.second << } << endl; } template <typename T, typename U, typename V> void bugpp(const pair<T, pair<U, V> > &x) { cerr << { << x.first << , { << x.second.first << , << x.second.second << }} << endl; } template <typename T> bool maximize(T &x, const T &y) { if (x < y) { x = y; return 1; } return 0; } template <typename T> bool minimize(T &x, const T &y) { if (x > y) { x = y; return 1; } return 0; } const int N = 2002; int n, C[N], A[N], subsz[N]; bool chk[N], answer = 1; vector<int> child[N]; int getNext(int idx) { int ans = -1; for (int i = 1, _n = (n); i <= _n; ++i) { if (!chk[i]) --idx; if (!idx) { ans = i; break; } } return ans; } void DFS(int u) { subsz[u] = 1; A[u] = getNext(C[u] + 1); if (A[u] == -1) answer = 0; else chk[A[u]] = 1; for (int &v : child[u]) { DFS(v); subsz[u] += subsz[v]; } if (C[u] >= subsz[u]) answer = 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; int root; for (int i = 1, _n = (n); i <= _n; ++i) { int p; cin >> p >> C[i]; if (p) child[p].push_back(i); else root = i; } DFS(root); if (!answer) cout << NO ; else { cout << YES n ; for (int i = 1, _n = (n); i <= _n; ++i) cout << A[i] << ; } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
typedef enum logic [4:0]
{
BIT0 = 5'd0,
BIT1 = 5'd1,
BIT2 = 5'd2
} three_t;
module t (/*AUTOARG*/);
localparam FIVE = 5;
enum { e0,
e1,
e3=3,
e5=FIVE,
e10_[2] = 10,
e12,
e20_[5:7] = 25,
e20_z,
e30_[7:5] = 30,
e30_z
} EN;
enum {
z5 = e5
} ZN;
typedef enum three_t; // Forward
typedef enum [2:0] { ONES=~0 } three_t;
three_t three = ONES;
var logic [ONES:0] sized_based_on_enum;
var enum logic [3:0] { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2},
QPR={2'b0,2'h3 }, QACK, QRSP } inv;
initial begin
if (e0 !== 0) $stop;
if (e1 !== 1) $stop;
if (e3 !== 3) $stop;
if (e5 !== 5) $stop;
if (e10_0 !== 10) $stop;
if (e10_1 !== 11) $stop;
if (e12 !== 12) $stop;
if (e20_5 !== 25) $stop;
if (e20_6 !== 26) $stop;
if (e20_7 !== 27) $stop;
if (e20_z !== 28) $stop;
if (e30_7 !== 30) $stop;
if (e30_6 !== 31) $stop;
if (e30_5 !== 32) $stop;
if (e30_z !== 33) $stop;
if (z5 !== 5) $stop;
if (three != 3'b111) $stop;
if ($bits(sized_based_on_enum) != 8) $stop;
if ($bits(three_t) != 3) $stop;
if (FIVE[BIT0] != 1'b1) $stop;
if (FIVE[BIT1] != 1'b0) $stop;
if (FIVE[BIT2] != 1'b1) $stop;
if (QINVALID != 15) $stop;
if (QSEND != 0) $stop;
if (QOP != 1) $stop;
if (QCL != 2) $stop;
if (QPR != 3) $stop;
if (QACK != 4) $stop;
if (QRSP != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_iobdg_cmp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg clock macro
// Description: Clock macro that encapsulates the cluster header.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module bw_clk_cl_iobdg_cmp (/*AUTOARG*/
// Outputs
so, rclk, dbginit_l, cluster_grst_l,
// Inputs
si, se, grst_l, gdbginit_l, gclk, cluster_cken, arst_l,
adbginit_l
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To cluster_header of cluster_header.v
input arst_l; // To cluster_header of cluster_header.v
input cluster_cken; // To cluster_header of cluster_header.v
input gclk; // To cluster_header of cluster_header.v
input gdbginit_l; // To cluster_header of cluster_header.v
input grst_l; // To cluster_header of cluster_header.v
input se; // To cluster_header of cluster_header.v
input si; // To cluster_header of cluster_header.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output cluster_grst_l; // From cluster_header of cluster_header.v
output dbginit_l; // From cluster_header of cluster_header.v
output rclk; // From cluster_header of cluster_header.v
output so; // From cluster_header of cluster_header.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
////////////////////////////////////////////////////////////////////////
// Code start here
////////////////////////////////////////////////////////////////////////
cluster_header cluster_header (/*AUTOINST*/
// Outputs
.dbginit_l(dbginit_l),
.cluster_grst_l(cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken(cluster_cken),
.arst_l(arst_l),
.grst_l(grst_l),
.adbginit_l(adbginit_l),
.gdbginit_l(gdbginit_l),
.si (si),
.se (se));
endmodule // bw_clk_cl_iobdg_cmp
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// End:
|
#include <bits/stdc++.h> using namespace std; long long sums[30000], dp[25][3000][25], can[3000], n, i, j, k, x, y, a[300]; int main() { cin >> n; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); reverse(a, a + n); for (i = 0; i < n; i++) if (a[i] == 1) { k = i; break; } if (k == 0) { if (n == 1) cout << YES << endl; else cout << NO << endl; return 0; } if (k > 11) { cout << NO << endl; return 0; } for (i = 0; i < (1 << k); i++) { long long cnt = 0; for (j = 0; j < k; j++) if (i & (1 << j)) sums[i] += a[j], cnt++; can[i] = cnt; } dp[0][1][0] = 1; for (i = 0; i < k; i++) for (j = 0; j < (1 << k); j++) if (j & ((1 << (i + 1)) - 1) == (1 << (i + 1)) - 1) for (x = 0; x <= n - k; x++) { long long tmp = (1 << k) - 1 - j; for (y = tmp;; y = ((y - 1) & tmp)) { if (a[i] - sums[y] - 1 >= 0 && can[y] + a[i] - sums[y] - 1 != 1) { if (dp[i][j][x] == 1 && x + a[i] - sums[y] - 1 <= n - k && a[i] - sums[y] - 1 >= 0) { dp[i + 1][j | y][x + a[i] - sums[y] - 1] = 1; } } if (y == 0) break; } } if (dp[k][(1 << k) - 1][n - k]) cout << YES << endl; else cout << NO << endl; return 0; }
|
//
// Ticket Machin Testbench
// Jenner Hanni
//
// Implements a testbench for a Moore finite state machine in Verilog
//
// This file provides a testbench capable of exhaustive testing of the
// TicketMachine.v file. Further comments available in that file.
//
module TestBench;
reg Clock, Clear, Ten, Twenty;
wire Ready, Dispense, Return, Bill;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
parameter CLOCK_CYCLE = 10;
parameter CLOCK_WIDTH = CLOCK_CYCLE/2;
parameter IDLE_CLOCKS = 2;
// instantiate an object of type TicketMachine to test
TicketMachine TFSM(Clock, Clear, Ten, Twenty, Ready, Dispense, Return, Bill);
//
// set up monitor
//
initial
begin
forever @(posedge Clock) begin
#1
$display($time, " %b %b %b %b %b %b",Ten,Twenty,Ready,Dispense,Return,Bill);
end
end
//
// Create free running clock
//
initial
begin
Clock = FALSE;
forever #CLOCK_WIDTH Clock = ~Clock;
end
//
// Generate stimulus after waiting for reset
//
initial
begin
Clear = 1;
repeat (2) @(negedge Clock);
Clear = 0;
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10; // case #1
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10; // exact change with 10+10+10+10
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10;
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10;
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01; // case #2
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01; // exact change with 20+20
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10; // case #3
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10; // exact change with 10+10+20
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01;
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10; // case #4
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01; // exact change with 10+20+10
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10;
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01; // case #5
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10; // exact change with 20+10+10
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10;
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10; // case #6
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01; // overshoot with 10+20+20
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01;
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10; // case #7
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01; // overshoot with 10+20+20
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01;
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01; // case #8
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10; // overshoot with 20+10+20
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01;
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10; // case #9
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10; // overshoot with 10+10+10+20
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b10;
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b01;
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b00; // case #10 - explicit no bills
repeat (1) @(negedge Clock); {Ten,Twenty} = 2'b11; // case #11 - LUDICROUS CASE
// failure in laws of physics
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const int M = 100; int cal(int t) { return (t >= 0 ? t : -t); } int n, d, a[M + 5], x[M + 5], y[M + 5], dist[M + 5][M + 5]; int main() { scanf( %d %d , &n, &d); for (int i = 2; i < n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) scanf( %d %d , &x[i], &y[i]); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) dist[i][j] = (i == j ? 0 : cal(x[i] - x[j]) * d + cal(y[i] - y[j]) * d - a[j]); for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) dist[i][j] = min(dist[i][j], dist[i][k] + dist[k][j]); printf( %d , dist[1][n]); }
|
module CapBoardDriver(clk500kHz,state,fets);
//INPUT:
//clk: Clock - designed to be 500 kHz
input clk500kHz;
//reg [3:0] clkCnt; //Count on clock edges to divide clock.
//state: state of board - which cap numbers are on. Each bit corresponds to
//cap bank (either serial or parallel).
input [3:0] state;
//OUTPUT:
//fets: gets signal that goes into MIC4427 drivers -
//should be a square wave at 500 kHz - divide clk/2^2.
output [7:0] fets;
//Send square wave to MOSFET drivers
//The number outside the curly braces, {4...}, is a repitition multiplier which serves
//to create a vector from the square wave for bitwise AND with the board state.
assign fets[3:0]={4{clk500kHz}} & state;
assign fets[7:4]=(~fets[3:0]) & state; //Invert square wave for 180-degree phase shift for push-pull transformer drive.
endmodule
//CODE GRAVEYARD
// //Initialize clock count variable.
// initial begin
// #0; //Act on zeroth simulation cycle.
// clkCnt=3'b0; //Zero.
// end
//
// //Act on clk positive edges.
// always @(posedge clk) begin
// //Divide clk to get slower square wave for driving transformers,
// //so increment counter.
// clkCnt=clkCnt+4'b1;
// end
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int i = 1; i <= t; i++) { long long n; cin >> n; long long s = sqrt(n); long long c = cbrt(n); long long p = sqrt(cbrt(n)); cout << s + c - p << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const long long inf = 9e18; struct NODE { long long v, id; bool operator<(const NODE& other) const { return v > other.v || (v == other.v && id > other.id); } } node[N]; long long a[N], b[N]; long long n; long long f(long long x, long long y) { return x - 3LL * y * y + 3LL * y - 1; } long long find(long long v, long long x) { long long l, r, mid; l = 0; r = x + 1; while (r - l > 1) { mid = (l + r) >> 1; if (f(x, mid) >= v) l = mid; else r = mid; } return l; } long long solve(long long x) { long long tot = 0; int i; for (i = 1; i <= n; i++) { tot += (b[i] = find(x, a[i])); } return tot; } int main() { long long k; int i, cnt = 0; long long l = inf, r = -inf, mid, tot; cin >> n >> k; for (i = 1; i <= n; i++) { cin >> a[i]; l = min(l, f(a[i], a[i])); r = max(r, f(a[i], 1)); } while (r - l > 1) { mid = (l + r) >> 1; if (solve(mid) <= k) r = mid; else l = mid; } tot = solve(r); for (i = 1; i <= n; i++) if (b[i] < a[i]) node[++cnt].v = f(a[i], b[i] + 1), node[cnt].id = i; sort(node + 1, node + cnt + 1); for (i = 1; i <= cnt; i++) { if (tot == k) break; b[node[i].id]++; tot++; } for (i = 1; i <= n; i++) cout << b[i] << ; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 15:24:23 10/24/2016
// Module Name: ALU_tb
// Project Name: MIPS
// Description: Testing MIPS ALU module in the EXECUTE stage.
//
// Dependencies: ALU.v
//
////////////////////////////////////////////////////////////////////////////////
module ALU_tb;
// Inputs.
reg [31:0] A;
reg [31:0] B;
reg [2:0] control;
// Outputs.
wire zero;
wire [31:0] result;
// Instantiate the module.
ALU alu(.A(A), .B(B), .control(control), .zero(zero), .result(result));
initial begin
// Initialize inputs.
A = 0;
B = 0;
control = 0;
// Wait 100 ns for global reset to finish
#100;
A <= 'b1010;
B <= 'b0111;
control <= 'b011;
$display("A = %b\tB = %b", A, B);
$monitor("ALUOp = %b\tresult = %b", control, result);
#1
control <= 'b100;
#1
control <= 'b010;
#1
control <= 'b111;
#1
control <= 'b011;
#1
control <= 'b110;
#1
control <= 'b001;
#1
control <= 'b000;
#1
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; long n; cin >> t; int a[t]; for (int i = 0; i < t; i++) { cin >> a[i]; } for (int i = 0; i < t; i++) { if (a[i] <= 2) { cout << 0 << endl; } else { n = (a[i] / 2.0); if (a[i] % 2 == 0) { cout << n - 1 << endl; } else { cout << n << endl; } } } }
|
#include <bits/stdc++.h> using namespace std; long long modulo(long long base, long long exponent, long long modulus); long long choose(long long n, long long k); long long inverse(long long a, long long m); void build(); void fileio(); long long ncr(long long n, long long r); const int nax = 1e6 + 10; const int LG = log2(nax) + 1; vector<long long> fact(nax); int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long n; cin >> n; string s; cin >> s; long long ans = n; for (long long i = 0; i < n; i++) { if (s[i] == 1 ) { ans = max(ans, 2 * (i + 1)); ans = max(ans, 2 * (n - i)); } } cout << ans << n ; } return 0; } long long ncr(long long n, long long r) { if (r > n || r < 0 || n < 0) return 0; long long ans = fact[n]; long long temp = (fact[n - r] * fact[r]) % 1000000007; ans = (ans * inverse(temp, 1000000007)) % 1000000007; return ans; } void fileio() { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } void build() { fact[0] = 1; for (long long i = 1; i < nax; i++) fact[i] = (fact[i - 1] * i) % 1000000007; } long long modulo(long long base, long long exponent, long long modulus) { if (modulus == 1) return 0; long long result = 1; base = base % modulus; while (exponent > 0) { if (exponent % 2 == 1) { result = (result * base) % modulus; } exponent = exponent >> 1; base = (base * base) % modulus; } return result; } long long choose(long long n, long long k) { if (k == 0) return 1; return (n * choose(n - 1, k - 1)) / k; } void EE(long long a, long long b, long long &co1, long long &co2) { if (a % b == 0) { co1 = 0; co2 = 1; return; } EE(b, a % b, co1, co2); long long temp = co1; co1 = co2; co2 = temp - co2 * (a / b); } long long inverse(long long a, long long m) { long long x, y; EE(a, m, x, y); if (x < 0) x += m; return x; }
|
/** * Author: dhruv_gheewala * Problem: A. Spy Detected! * Date: 12.04.2021 * Time: 00:19:53 **/ #include bits/stdc++.h using namespace std; #ifndef DEBUG #define fundri 108 #define debug(...) 1729 #define endl n #endif #define int int64_t typedef pair<int, int> pii; typedef vector<int> vi; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); inline int rnd(int l = 0, int r = INT_MAX) {return uniform_int_distribution<int>(l, r)(rng);} bool in_range(int x, int l, int r) {return l <= x && x <= r;} template<typename H, typename ...T>void inp(H &head) {cin >> head;} template<typename H, typename ...T>void inp(H &head, T &...tail) {cin >> head;inp(tail...);} template<typename T>inline istream &operator >>(istream &in, vector<T> &a) {for(T &x : a)in >> x; return in;} template<typename T, typename U>inline istream &operator >>(istream &in, pair<T, U> &a) {in >> a.first >> a.second; return in;} // Multi-Dimension Vector // Usage: vec<n, data-type> dp(dimention-1, dimention-2, ..., dimention-n, default = data-type()) template<int D, typename T> struct vec : public vector<vec<D - 1, T>> { static_assert(D >= 1, Vector dimensions must be greater than zero !! ); template<typename... Args> vec(int n = 0, Args... args) : vector<vec<D - 1, T>>(n, vec<D - 1, T>(args...)){} }; template<typename T> struct vec<1, T> : public vector<T> {vec(int n = 0, T val = T()) : vector<T>(n, val){}}; const int inf = 1e15; const bool testcases = true; const bool ready = []() -> bool { ios_base::sync_with_stdio(false); cin.tie(nullptr); #ifdef DHRUV_GHEEWALA freopen( in.txt , r , stdin); freopen( out.txt , w , stdout); freopen( debug.txt , w , stderr); #endif return true; }(); void solve(int tc); int32_t main(int32_t argc, char **argv) { int TC = 1; if(testcases) cin >> TC; // Pre-Processing goes here... for(int tc = 1; tc <= TC; ++tc) { solve(tc); fundri; } exit(0); } void solve(int tc) { int n; cin >> n; vector<int> a(n); cin >> a; map<int, int> mp; for(int x: a) mp[x]++; for(int i = 0; i < n; i++) { if(mp[a[i]] == 1) { cout << i + 1 << endl; return; } } }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_MUX_2TO1_N_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_MUX_2TO1_N_BLACKBOX_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_mux_2to1_N (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_MUX_2TO1_N_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; int main() { int n, k; int aa[2010]; scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) scanf( %d , &aa[i]); sort(aa, aa + n); int p = n - 1; int ans = 0; while (p >= 0) { int temp = aa[p]; ans += (temp - 1) * 2; p -= k; } printf( %d n , ans); return 0; }
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// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
parameter NC0 = (necessary_condition == `OVL_TRIGGER_ON_MOST_PIPE);
parameter NC1 = (necessary_condition == `OVL_TRIGGER_ON_FIRST_PIPE);
parameter NC2 = (necessary_condition == `OVL_TRIGGER_ON_FIRST_NOPIPE);
// Guarded parameters for num_cks < 2 (which is bad usage - see warning in top-level file)
parameter NUM_CKS_1 = (num_cks > 0) ? (num_cks - 1) : 0;
parameter NUM_CKS_2 = (num_cks > 1) ? (num_cks - 2) : 0;
parameter LSB_1 = (num_cks > 1) ? 1 : 0;
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
reg [NUM_CKS_1:0] seq_queue; // REVISIT: bit [0] is redundant (Mantis #1812)
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
seq_queue <= {num_cks{1'b0}};
end
else begin
seq_queue[NUM_CKS_2:0] <= seq_queue[NUM_CKS_1:1] & event_sequence[NUM_CKS_2:0];
seq_queue[NUM_CKS_1] <= NC2 ? event_sequence[NUM_CKS_1] && (~(|seq_queue[NUM_CKS_1:1]))
: event_sequence[NUM_CKS_1];
end
end
`endif // OVL_SHARED_CODE
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1, fire_2state_2;
reg fire_2state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_2state <= 1'b0;
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"First event occured but it is not followed by the rest of the events in sequence");
end
if (fire_2state_2) begin
ovl_error_t(`OVL_FIRE_2STATE,"First num_cks-1 events occured but they are not followed by the last event in sequence");
end
if (fire_2state_1 || fire_2state_2) begin
fire_2state <= ovl_fire_2state_f(property_type);
end
else begin
fire_2state <= 1'b0;
end
end
end
assign fire_2state_1 = ((NC1 || NC2) && (&((seq_queue[NUM_CKS_1:LSB_1] & event_sequence[NUM_CKS_2:0]) | ~(seq_queue[NUM_CKS_1:LSB_1])) == 1'b0));
assign fire_2state_2 = ( NC0 && ((!seq_queue[1] || ((seq_queue[1] && event_sequence[0]))) == 1'b0));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1, fire_xcheck_2, fire_xcheck_3, fire_xcheck_4, fire_xcheck_5, fire_xcheck_6;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First event in the sequence contains X or Z");
end
if (fire_xcheck_2) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First event in the sequence contains X or Z");
end
if (fire_xcheck_3) begin
ovl_error_t(`OVL_FIRE_XCHECK,"Subsequent events in the sequence contain X or Z");
end
if (fire_xcheck_4) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First num_cks-1 events in the sequence contain X or Z");
end
if (fire_xcheck_5) begin
ovl_error_t(`OVL_FIRE_XCHECK,"Last event in the sequence contains X or Z");
end
if (fire_xcheck_6) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First num_cks-1 events in the sequence contain X or Z");
end
if (fire_xcheck_1 || fire_xcheck_2 || fire_xcheck_3 || fire_xcheck_4 || fire_xcheck_5 || fire_xcheck_6) begin
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
wire valid_first_event = ~( event_sequence[NUM_CKS_1] ^
event_sequence[NUM_CKS_1] );
wire valid_sequence = (~((^(seq_queue[NUM_CKS_1:LSB_1] &
event_sequence[NUM_CKS_2:0] &
{{(NUM_CKS_2){1'b1}},{~(|NC0)}})) ^
(^(seq_queue[NUM_CKS_1:LSB_1] &
event_sequence[NUM_CKS_2:0] &
{{(NUM_CKS_2){1'b1}},{~(|NC0)}}))));
wire valid_last_event = ~((seq_queue[1] && event_sequence[0]) ^
(seq_queue[1] && event_sequence[0]));
always @ (valid_first_event or seq_queue) begin
if (valid_first_event) begin
fire_xcheck_1 = 1'b0;
fire_xcheck_2 = 1'b0;
end
else begin
fire_xcheck_1 = (NC0 || NC1);
fire_xcheck_2 = (NC2 && ~(|seq_queue[NUM_CKS_1:1]));
end
end
always @ (valid_sequence) begin
if (valid_sequence) begin
fire_xcheck_3 = 1'b0;
fire_xcheck_4 = 1'b0;
end
else begin
fire_xcheck_3 = (NC1 || NC2);
fire_xcheck_4 = (NC0);
end
end
always @ (valid_last_event or seq_queue) begin
if (valid_last_event) begin
fire_xcheck_5 = 1'b0;
fire_xcheck_6 = 1'b0;
end
else begin
fire_xcheck_5 = (NC0 && seq_queue[1]);
fire_xcheck_6 = (NC0 && ~seq_queue[1]);
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
wire fire_cover_1, fire_cover_2;
reg fire_cover;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_cover <= 1'b0;
end
else begin
if (fire_cover_1) begin
ovl_cover_t("sequence_trigger covered"); // basic
end
if (fire_cover_2) begin
ovl_cover_t("sequence_trigger covered"); // basic
end
if (fire_cover_1 || fire_cover_2) begin
fire_cover <= 1'b1;
end
else begin
fire_cover <= 1'b0;
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (NC1 || NC2) && event_sequence[NUM_CKS_1]);
assign fire_cover_2 = ((OVL_COVER_BASIC_ON > 0) && NC0 && (&seq_queue[1])); // REVISIT: Reduction-AND is redundant
`else
wire fire_cover = 1'b0;
`endif // OVL_COVER_ON
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#include <bits/stdc++.h> using namespace std; long long int n, ar[100001], max_s[100001], max_e[100001], pre_s[100001], pre_e[100001], ans = INT_MIN; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> ar[i]; for (int i = 1; i < n; i++) pre_s[i] = pre_s[i - 1] + ar[i - 1]; for (int i = n - 2; i >= 0; i--) pre_e[i] = pre_e[i + 1] + ar[i + 1]; max_e[n - 1] = abs(ar[n - 1]); max_s[0] = abs(ar[0]); for (int i = n - 2; i >= 0; i--) max_e[i] = max(ar[i] + max_e[i + 1], -(ar[i] + pre_e[i])); for (int i = 1; i < n; i++) max_s[i] = max(ar[i] + max_s[i - 1], -(ar[i] + pre_s[i])); ans = max(ans, max_e[0]); ans = max(ans, max_s[n - 1]); for (int i = 0; i < n - 1; i++) ans = max(ans, max_s[i] + max_e[i + 1]); cout << ans; return 0; }
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#include <bits/stdc++.h> int sm(int a, int b) { if (a % b == 0) return b; else return a % b; } int main() { int n, m, s; scanf( %d%d%d , &n, &m, &s); printf( %I64d , (long long)sm(n, s) * sm(m, s) * ((n - 1) / s + 1) * ((m - 1) / s + 1)); }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 69, INF = 1e9 + 85, MOD = 1e9 + 7; int n, k, a, b, q, arr[MAXN], seg[2][MAXN << 2]; void update(int indx, int val, int type, int l = 0, int r = n, int id = 1) { if (indx < l or indx >= r) return; if (r - l == 1) { seg[type][id] = val; return; } int mid = (l + r) >> 1; update(indx, val, type, l, mid, id << 1 | 0); update(indx, val, type, mid, r, id << 1 | 1); seg[type][id] = seg[type][id << 1 | 0] + seg[type][id << 1 | 1]; } int get(int st, int en, int type, int l = 0, int r = n, int id = 1) { if (l >= en or r <= st) return 0; if (l >= st and r <= en) return seg[type][id]; int mid = (l + r) >> 1; return get(st, en, type, l, mid, id << 1 | 0) + get(st, en, type, mid, r, id << 1 | 1); } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> k >> a >> b >> q; while (q--) { int type, day, order; cin >> type; if (type == 1) { cin >> day >> order; arr[day] += order; update(day - 1, min(arr[day], a), 0); update(day - 1, min(arr[day], b), 1); } else { cin >> day; cout << get(0, day - 1, 1) + get(day + k - 1, n, 0) << n ; } } }
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#include <bits/stdc++.h> using namespace std; map<string, int> mp; vector<string> vr; int n, m; int a[105][105], b[105][105]; int xx[8] = {-1, -1, -1, 0, 0, 1, 1, 1}; int yy[8] = {-1, 0, 1, -1, 1, -1, 0, 1}; bool check(int i, int j) { if (i >= 0 && i < n && j >= 0 && j < m && a[i][j] != -2 && a[i][j] != -6) return true; return false; } bool Check(int i, int j) { if (i >= 0 && i < n && j >= 0 && j < m && b[i][j] == -6) return true; return false; } void dfs(int x, int y) { int X, Y, i; for (i = 0; i < 8; i++) { X = x + xx[i]; Y = y + yy[i]; if (check(X, Y)) b[X][Y]++; } } int main() { char ma[105][105]; while (~scanf( %d%d , &n, &m)) { int f = 0; memset(a, 0, sizeof(a)); memset(b, 0, sizeof(b)); for (int i = 0; i < n; i++) { cin >> ma[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { a[i][j] = ma[i][j] - 0 ; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == -6) { b[i][j] = -6; dfs(i, j); } if (a[i][j] == -2) b[i][j] = -2; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (b[i][j] == -2) { for (int k = 0; k < 8; k++) { int X = xx[k] + i; int Y = yy[k] + j; if (Check(X, Y)) { f = 1; break; } } } if (a[i][j] != b[i][j]) { f = 1; break; } if (f == 1) break; } if (f == 1) break; } if (f) printf( NO n ); else printf( YES n ); } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__OR4B_PP_SYMBOL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_PP_SYMBOL_V
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#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; vector<long long> parent(200005), Size(200005, 1); long long answer = 0; long long find_set(long long n) { if (parent[n] == n) return n; else return find_set(parent[n]); } void add_edge(long long a, long long b) { long long A = find_set(a); long long B = find_set(b); if (Size[A] >= Size[B]) { answer -= ((Size[A] * (Size[A] - 1)) / 2); answer -= ((Size[B] * (Size[B] - 1)) / 2); Size[A] += Size[B]; Size[B] = 0; parent[B] = A; answer += ((Size[A] * (Size[A] - 1)) / 2); } else { answer -= ((Size[B] * (Size[B] - 1)) / 2); answer -= ((Size[A] * (Size[A] - 1)) / 2); Size[B] += Size[A]; Size[A] = 0; parent[A] = B; answer += ((Size[B] * (Size[B] - 1)) / 2); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long N, Q, p, q, r; cin >> N >> Q; if (N == 1) { for (long long i = 1; i <= Q; i++) cout << 0 ; return 0; } for (long long i = 1; i <= N; i++) parent[i] = i; vector<pair<long long, pair<long long, long long>>> G; for (long long i = 1; i < N; i++) { cin >> p >> q >> r; G.push_back({r, {p, q}}); } sort(G.begin(), G.end()); vector<long long> final_ans(N + 1); long long ptr = 0; for (long long i = 1; i <= N;) { if (G[ptr].first == i) { add_edge(G[ptr].second.first, G[ptr].second.second); ptr++; } else { final_ans[i] = answer; i++; } } while (Q--) { long long k; cin >> k; cout << final_ans[k] << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T> bool remin(T &a, const T &b) { if (a > b) { a = b; return true; } return false; } template <class T> bool remax(T &a, const T &b) { if (a < b) { a = b; return true; } return false; } int nxt() { int first; scanf( % PRId32, &first); return first; } long long nxtll() { long long first; scanf( % PRId64, &first); return first; } long long gcd(long long a, long long b) { a = abs(a); b = abs(b); while (b) { a %= b; swap(a, b); } return a; } struct Q { long long n, d; Q(long long a = 0) : n(a), d(1) {} Q(long long nn, long long dd) : n(nn), d(dd) { norm(); } void norm() { long long g = gcd(abs(n), abs(d)); n /= g; d /= g; if (d < 0) { n *= -1; d *= -1; } } Q operator+(const Q &r) const { return Q(n * r.d + d * r.n, d * r.d); } Q operator-(const Q &r) const { return Q(n * r.d - d * r.n, d * r.d); } Q operator*(const Q &r) const { return Q(n * r.n, d * r.d); } Q operator/(const Q &r) const { return Q(n * r.d, d * r.n); } long long value(const Q &r) const { return n * r.d - d * r.n; } double vald(const Q &r) const { return n * 1.0 * r.d - d * 1.0 * r.n; } bool operator<(const Q &r) const { double vv = vald(r); if (vv < -1e10) { return true; } if (vv > 1e10) { return false; } return value(r) < 0; } bool operator>(const Q &r) const { double vv = vald(r); if (vv < -1e10) { return false; } if (vv > 1e10) { return true; } return value(r) > 0; } bool operator!=(const Q &r) const { return !(*this == r); } bool operator>=(const Q &r) const { return *this > r || *this == r; } bool operator<=(const Q &r) const { return *this < r || *this == r; } bool operator==(const Q &r) const { double vv = vald(r); if (vv < -1e10) { return false; } if (vv > 1e10) { return false; } return value(r) == 0; } double getValue() const { return n / (double)d; } }; ostream &operator<<(ostream &os, const Q &p) { return os << p.n << / << p.d; } struct pt { double first, second; pt() = default; pt(long double first, long double second) : first(first), second(second) {} inline pt operator-(const pt &r) const { return pt(first - r.first, second - r.second); } inline pt operator+(const pt &r) const { return pt(first + r.first, second + r.second); } inline pt operator*(const long double &r) const { return pt(first * r, second * r); } inline pt operator-() const { return pt(-first, -second); } inline long double sqlen() const { return fabsl(first * first + second * second); } }; ostream &operator<<(ostream &os, const pt &p) { return os << ( << p.first << , << p.second << ) ; } ostream &operator<<(ostream &os, const pair<long long, long long> &p) { return os << ( << p.first << , << p.second << ) ; } pair<long long, long long> operator-(const pair<long long, long long> &l, const pair<long long, long long> &r) { return pair<long long, long long>(l.first - r.first, l.second - r.second); } pair<long long, long long> operator+(const pair<long long, long long> &l, const pair<long long, long long> &r) { return pair<long long, long long>(l.first + r.first, l.second + r.second); } inline double cross(const pt &l, const pt &r) { return l.first * r.second - l.second * r.first; } inline double dot(const pt &l, const pt &r) { return l.first * r.first + l.second * r.second; } inline long long cross(const pair<long long, long long> &l, const pair<long long, long long> &r) { return l.first * r.second - l.second * r.first; } inline long long dot(const pair<long long, long long> &l, const pair<long long, long long> &r) { return l.first * r.first + l.second * r.second; } long long pwmod(long long a, long long n, long long mod) { long long ret = 1; while (n) { if (n & 1) ret = ret * a % mod; a = a * a % mod; n >>= 1; } return ret; } template <typename T> inline T sqr(T first) { return first * first; } inline bool is_prime(unsigned long long first) { for (unsigned long long i = 2; i * i <= first; ++i) { if (first % i == 0) { return false; } } return true; } bool is_sq(long long first) { for (long long i = 1; i * i <= first; ++i) { if (i * i == first) return true; } return false; } int n; string solve(const multiset<char> &a, const multiset<char> &b, int d = 0, const string &cur = string(n, ? )) { if (d == n) { return cur; } if (d & 1) { string res = ; set<char> bl(b.begin(), b.end()); for (char c : bl) { multiset<char> bb = b; bb.erase(bb.find(c)); for (int i = 0; i < n; ++i) { if (cur[i] != ? ) continue; string cc = cur; cc[i] = c; res = max(res, solve(a, bb, d + 1, cc)); } } return res; } else { string res = string(n, z + 1); set<char> al(a.begin(), a.end()); for (char c : al) { multiset<char> aa = a; aa.erase(aa.find(c)); for (int i = 0; i < n; ++i) { if (cur[i] != ? ) continue; string cc = cur; cc[i] = c; res = min(res, solve(aa, b, d + 1, cc)); } } return res; } } string solve(const string &a, const string &b) { n = a.length(); return solve(multiset<char>(a.begin(), a.end()), multiset<char>(b.begin(), b.end())); } const int N = 300 * 1000 + 10; char a[N]; char b[N]; string solve2(string a, string b) { sort(a.begin(), a.end()); sort(b.begin(), b.end()); int n = a.length(); int l = 0, r = n - 1; int L = 0, R = n; string s(n, . ); int move = 0; while (L < R) { if (move & 1) { if (a[l] < b[r] || L + 1 == R) { s[L] = b[r]; --r; ++L; } else { if (!((R - L) & 1)) { for (int i = L; i < R; i += 2) { s[i] = a[l++]; } for (int i = L + 1; i < R; i += 2) { s[i] = b[r--]; } } else { for (int i = L + 1; i < R; i += 2) { s[i] = a[l++]; } for (int i = L; i < R; i += 2) { s[i] = b[r--]; } } L = R; } } else { if (a[l] < b[r] || L + 1 == R) { s[L] = a[l]; ++l; ++L; } else { if (!((R - L) & 1)) { for (int i = L + 1; i < R; i += 2) { s[i] = a[l++]; } for (int i = L; i < R; i += 2) { s[i] = b[r--]; } } else { for (int i = L; i < R; i += 2) { s[i] = a[l++]; } for (int i = L + 1; i < R; i += 2) { s[i] = b[r--]; } } L = R; } } ++move; } return s; } void solve() { scanf( %s , a); scanf( %s , b); cout << solve2(a, b) << n ; } void prepare() { return; while (true) { n = rand() % 5 + 1; string a(n, . ); string b(n, . ); for (int i = 0; i < (int)(n); i++) { a[i] = rand() % 5 + a ; b[i] = rand() % 5 + a ; } if (solve(a, b) != solve2(a, b)) { cout << a << n ; cout << b << n ; return; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); prepare(); int t = 1; for (int i = 0; i < (int)(t); i++) { solve(); } cerr << Time << clock() / (double)CLOCKS_PER_SEC << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; bitset<2005> a[2005]; int n, m, i, j, deg[2005], t, ans[2005], z[2005]; int main() { scanf( %d , &t); while (t--) { scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) { a[i].reset(); deg[i] = 0; } for (i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); deg[x]++; deg[y]++; a[x][n + 1] = a[x][n + 1] ^ 1; a[y][n + 1] = a[y][n + 1] ^ 1; a[x][y] = a[y][x] = 1; } bool f = 1; for (i = 1; i <= n; i++) { if (deg[i] & 1) { f = 0; a[i][i] = 1; } } if (f) { puts( 1 ); for (i = 1; i <= n; i++) { printf( %d%c , 1, (i == n ? n : )); } continue; } for (i = 1; i <= n; i++) { int t = -1; for (j = i; j <= n; j++) { if (a[j][i]) { t = j; break; } } if (t == -1) { for (j = 1; j < i; j++) a[j][i] = 0; ans[i] = 0; z[i] = 1; continue; } z[i] = 0; swap(a[i], a[t]); for (j = i + 1; j <= n; j++) { if (a[j][i]) a[j] ^= a[i]; } } for (i = n; i >= 1; i--) { if (z[i]) continue; for (j = i + 1; j <= n; j++) { if (a[i][j]) a[i][n + 1] = a[i][n + 1] ^ ans[j]; } ans[i] = a[i][n + 1]; } puts( 2 ); for (i = 1; i <= n; i++) { printf( %d%c , 1 + ans[i], (i == n ? n : )); } } return 0; }
|
#include <bits/stdc++.h> using ll = long long int; using namespace std; int main() { ll t; cin >> t; while (t--) { ll p, q; cin >> p >> q; if (p % q != 0) cout << p << n ; else { ll x = 1; for (ll i = 1; i <= sqrt(q); i++) { if (q % i == 0) { ll pnew = p; while (i != 1 && pnew % i == 0) { pnew = pnew / i; if (pnew % q != 0) { x = max(x, pnew); break; } } pnew = p; while (pnew % (q / i) == 0) { pnew = pnew / (q / i); if (pnew % q != 0) { x = max(x, pnew); break; } } } } cout << x << n ; } } }
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 3-State Differential Signaling Output Buffer
// /___/ /\ Filename : OBUFTDS_DCIEN.v
// \ \ / \ Timestamp : Thu Apr 29 14:59:30 PDT 2010
// \___\/\___\
//
// Revision:
// 04/29/10 - Initial version.
// 12/20/10 - CR 587760 -- For backend support only, no corresponding unisim
// 06/10/11 - CR 584500 - added attribute SLEW
// 09/20/11 - CR 625725 -- Removed attribute CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OBUFTDS_DCIEN (O, OB, DCITERMDISABLE, I, T);
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter SLEW = "SLOW";
output O;
output OB;
input DCITERMDISABLE;
input I;
input T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 B1 (O, I, ts);
notif0 N1 (OB, I, ts);
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(DCITERMDISABLE => OB) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_TB_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_pwrgood_pp_p.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VPWR = 1'b0;
#60 UDP_IN = 1'b1;
#80 VPWR = 1'b1;
#100 UDP_IN = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 UDP_IN = 1'b1;
#180 VPWR = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_hd__udp_pwrgood_pp$P dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_TB_V
|
#include <bits/stdc++.h> using namespace std; int nnext[4][2] = {{0, 1}, {1, 0}, {0, -1}, {-1, 0}}; long long gcd(long long x, long long y) { return !y ? x : gcd(y, x % y); } int main() { int n, m, k, idx, x, y, now, have, array[350][350]; cin >> n >> m >> k, x = y = 1, idx = now = have = 0; vector<vector<pair<int, int> > > ans(k); while (k) { if (k == 1) { if (y > m) x++, y = m, now = 1; else if (!y) x++, y = 1, now = 0; ans[idx].push_back(make_pair(x, y)), have++; if (have == n * m) break; if (!now) y++; else y--; continue; } else { ans[idx].push_back(make_pair(x, y)), have++; if (!now) y++; else y--; if (y > m) x++, y = m, now = 1; else if (!y) x++, y = 1, now = 0; } if (ans[idx].size() == 2) idx++, k--; } for (int i = 0; i < int(ans.size()); i++) { cout << ans[i].size() << ; for (int j = 0; j < int(ans[i].size()); j++) cout << ans[i][j].first << << ans[i][j].second << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string s1, s2, s3; cin >> n; while (n--) { cin >> s1 >> s2 >> s3; for (int i = 0; i < s1.length(); i++) { if (s3.at(i) != s2.at(i) && s3.at(i) != s1.at(i)) { cout << NO n ; break; } if (i == s1.length() - 1) cout << YES n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve(string a, string b, int m, int n) { int lcs[m + 1][n + 1]; int result = 0; for (int i = 0; i <= m; i++) { for (int j = 0; j <= n; j++) { if (i == 0 || j == 0) lcs[i][j] = 0; else if (a[i - 1] == b[j - 1]) { lcs[i][j] = lcs[i - 1][j - 1] + 1; result = max(result, lcs[i][j]); } else lcs[i][j] = 0; } } int answer = m + n - 2 * result; cout << answer << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin.exceptions(ios::badbit | ios::failbit); int t = 1; cin >> t; while (t--) { int n; cin >> n; string s, temp; cin >> s; temp = s; sort(s.begin(), s.end()); int count = 0; for (int i = 0; i < n; i++) { if (temp[i] != s[i]) count++; } cout << count << n ; } return 0; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ecc_encoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_ENC_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_ecc_code,
input_ecc_code_overwrite,
output_data
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code;
input input_ecc_code_overwrite;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_input_data;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_input_ecc_code;
reg int_input_ecc_code_overwrite;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_encoder_output_modified;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] encoder_input;
wire [CFG_DATA_WIDTH - 1 : 0] encoder_output;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : encoder_input_per_data_width
always @ (*)
begin
int_encoder_input [i_data] = input_data [i_data];
end
end
endgenerate
// Encoder input assignment
assign encoder_input = int_encoder_input [CFG_ECC_DATA_WIDTH - 1 : 0];
// Output data merging logic
// change
// <ECC code> - <Empty data> - <Data>
// into
// <Empty data> - <ECC code> - <Data>
always @ (*)
begin
int_encoder_output = encoder_output;
end
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
// Write data only
int_encoder_output_modified = int_encoder_output;
end
end
else
begin
always @ (*)
begin
// Write data
int_encoder_output_modified [CFG_ECC_DATA_WIDTH - 1 : 0] = int_encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// Ecc code
if (int_input_ecc_code_overwrite)
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_input_ecc_code;
end
else
begin
int_encoder_output_modified [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = int_encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
end
end
end
endgenerate
// Encoder output assignment
always @ (*)
begin
if (cfg_enable_ecc)
output_data = int_encoder_output_modified;
else
output_data = int_input_data;
end
generate
if (CFG_ECC_ENC_REG)
begin
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_input_data <= 0;
int_input_ecc_code <= 0;
int_input_ecc_code_overwrite <= 0;
end
else
begin
int_input_data <= input_data;
int_input_ecc_code <= input_ecc_code;
int_input_ecc_code_overwrite <= input_ecc_code_overwrite;
end
end
end
else
begin
// Non-registered version
always @ (*)
begin
int_input_data = input_data;
int_input_ecc_code = input_ecc_code;
int_input_ecc_code_overwrite = input_ecc_code_overwrite;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] internal_encoder_output;
// Assign bit 39 to '0'
assign internal_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = internal_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = internal_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({24'd0, encoder_input} ),
.q (internal_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] internal_encoder_output;
// Assign bit 39 to '0'
assign internal_encoder_output [39] = 1'b0;
// Assign the lower data bits
assign encoder_output [CFG_ECC_DATA_WIDTH - 1 : 0] = internal_encoder_output [31 : 0];
// Assign the upper ECC bits
assign encoder_output [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH] = internal_encoder_output [39 : 32];
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data ({16'd0, encoder_input} ),
.q (internal_encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// Assign bit 39 to '0'
assign encoder_output [39] = 1'b0;
// 32/39 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_32 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG )
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output [38 : 0])
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 64/72 bit encoder instantiation
alt_mem_ddrx_ecc_encoder_64 #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
encoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (encoder_input ),
.q (encoder_output )
);
end
else
begin
assign encoder_output = {CFG_DATA_WIDTH{1'b0}};
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; while (q--) { int n, rec = 0; long long int k; cin >> n >> k; char str[1000005]; cin >> str; for (int h = 0; h < n; h++, rec++) { int pos = h; for (int i = h; i < n; i++) { if (str[i] == 0 ) { pos = i; break; } } h = pos; if (k - pos - rec >= 0) { char temp = str[pos]; str[pos] = str[rec]; str[rec] = temp; k -= (pos - rec); } else if (k > 0) { while (pos > 0 && str[pos - 1] == 1 && k > 0) { char temp = str[pos]; str[pos] = str[pos - 1]; str[pos - 1] = temp; pos--; k--; } } } cout << str << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> istream& operator>>(istream& is, vector<T>& v) { for (T& x : v) is >> x; return is; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { for (int i = 0; i < (int)v.size(); i++) { os << v[i] << (i + 1 == (int)v.size() ? : ); } return os; } template <typename T, typename U> ostream& operator<<(ostream& os, const pair<T, U>& p) { os << ( << p.first << , << p.second << ) ; return os; } template <typename T, typename U, typename V> ostream& operator<<(ostream& os, const tuple<T, U, V>& t) { os << ( << get<0>(t) << , << get<1>(t) << , << get<2>(t) << ) ; return os; } template <typename T, typename U, typename V, typename W> ostream& operator<<(ostream& os, const tuple<T, U, V, W>& t) { os << ( << get<0>(t) << , << get<1>(t) << , << get<2>(t) << , << get<3>(t) << ) ; return os; } template <typename T, typename U> ostream& operator<<(ostream& os, const map<T, U>& m) { os << { ; for (auto itr = m.begin(); itr != m.end();) { os << ( << itr->first << , << itr->second << ) ; if (++itr != m.end()) os << , ; } os << } ; return os; } template <typename T, typename U> ostream& operator<<(ostream& os, const unordered_map<T, U>& m) { os << { ; for (auto itr = m.begin(); itr != m.end();) { os << ( << itr->first << , << itr->second << ) ; if (++itr != m.end()) os << , ; } os << } ; return os; } template <typename T> ostream& operator<<(ostream& os, const set<T>& s) { os << { ; for (auto itr = s.begin(); itr != s.end();) { os << *itr; if (++itr != s.end()) os << , ; } os << } ; return os; } template <typename T> ostream& operator<<(ostream& os, const multiset<T>& s) { os << { ; for (auto itr = s.begin(); itr != s.end();) { os << *itr; if (++itr != s.end()) os << , ; } os << } ; return os; } template <typename T> ostream& operator<<(ostream& os, const unordered_set<T>& s) { os << { ; for (auto itr = s.begin(); itr != s.end();) { os << *itr; if (++itr != s.end()) os << , ; } os << } ; return os; } template <typename T> ostream& operator<<(ostream& os, const deque<T>& v) { for (int i = 0; i < (int)v.size(); i++) { os << v[i] << (i + 1 == (int)v.size() ? : ); } return os; } void debug_out() { cerr << n ; } template <class Head, class... Tail> void debug_out(Head&& head, Tail&&... tail) { cerr << head; if (sizeof...(Tail) > 0) cerr << , ; debug_out(move(tail)...); } template <typename T> T gcd(T x, T y) { return y != 0 ? gcd(y, x % y) : x; } template <typename T> T lcm(T x, T y) { return x / gcd(x, y) * y; } template <class T1, class T2> inline bool chmin(T1& a, T2 b) { if (a > b) { a = b; return true; } return false; } template <class T1, class T2> inline bool chmax(T1& a, T2 b) { if (a < b) { a = b; return true; } return false; } const int INF = 1e9; const long long IINF = 1e18; const int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; const char dir[4] = { D , R , U , L }; const long long MOD = 1000000007; vector<bool> binary_conversion(const string& s) { using u64 = uint64_t; vector<u64> num(s.size() / 9 + 10, 0); for (size_t i = 0; i < s.size(); i += 9) { const string t = s.substr(i, 9); u64 add = 0, mul = 1; for (const auto c : t) { add = add * 10 + (c - 0 ); mul *= 10; } for (auto& d : num) { d = d * mul + add; add = d >> 32; d -= add << 32; } } vector<bool> res(num.size() * 32); for (size_t i = 0; i < num.size(); i++) { for (size_t j = 0; j < 32; j++) { res[i * 32 + j] = num[i] >> j & 1; } } while (!res.empty() && !res.back()) res.pop_back(); return res; }; namespace n91 { using usize = std::size_t; using u64 = std::uint64_t; std::vector<bool> stob(std::string s) { std::vector<u64> num(s.size() / 9 + 10, 0); for (usize i = 0; i < s.size(); i += 9) { const std::string t = s.substr(i, 9); u64 mul = 1; u64 add = 0; for (const auto c : t) { add = add * 10 + (c - 0 ); mul *= 10; } for (auto& d : num) { d = d * mul + add; add = d >> 32; d -= add << 32; } } std::vector<bool> res(num.size() * 32); for (usize i = 0; i < num.size(); ++i) { for (usize j = 0; j < 32; ++j) { res[i * 32 + j] = num[i] >> j & 1; } } while (!res.empty() && !res.back()) { res.pop_back(); } return res; } } // namespace n91 const int MAX = 2048; using u64 = uint64_t; using BS = bitset<2 * MAX>; BS calc(const string& s) { BS res; vector<bool> v = binary_conversion(s); for (int i = 0; i < v.size(); i++) { if (v[i]) { res.set(i, 1); } } return res; } vector<BS> bases; vector<int> idx(MAX, -1); vector<int> solve(BS b, int x) { for (int i = MAX - 1; i >= 0; i--) { if (!b[i]) continue; if (~idx[i]) b ^= bases[idx[i]]; else { b.set(MAX + x, 1); idx[i] = bases.size(); bases.emplace_back(b); return {}; } } vector<int> res; for (int i = 0; i < MAX; i++) { if (b[MAX + i]) { res.emplace_back(i); } } return res; }; int main() { cin.tie(0); ios::sync_with_stdio(false); int m; cin >> m; for (int i = 0; i < m; i++) { string S; cin >> S; vector<int> ans = solve(calc(S), i); cout << ans.size(); for (int x : ans) cout << << x; cout << n ; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/01/2016 12:02:10 PM
// Design Name:
// Module Name: Problem3
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Problem3(
input [2:0] OpCode,
input [3:0] A,
input [3:0] B,
output reg [3:0] Final,
output reg Status
);
always @ (A or B or OpCode)
begin
Status = 0;
case (OpCode)
3'b000: begin
Final = ~A;
end
3'b001: begin
Final = ~(A&B);
end
3'b010: begin
Final = ~(A|B);
end
3'b011: begin
Final = A ^ B;
end
3'b100: begin
Final = A + B;
if (A[3] == B[3] && Final[3] != B[3])
Status = 1;
end
3'b101: begin
Final = A - B;
if (A[3] == (B[3] ^ 1) && Final[3] != A[3])
Status = 1;
end
3'b110: begin
Final = B + 4'b0001;
if (0 == B[3] && Final[3] != B[3])
Status = 1;
end
3'b111: begin
Final = B - 4'b0001;
//1 usually used for subtraction
if (1 == B[3] && Final[3] != 1 )
Status = 1;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int i, j, k, n, m, x, y, T, ans, mx, mi, cas, num, len; bool flag; int p, a[25][105], b[25][105], c[25][105]; char s[1000]; int dp[1005]; int main() { scanf( %d%d%d , &n, &m, &p); for (i = 1; i <= n; i++) { scanf( %s , s); for (j = 1; j <= m; j++) { scanf( %d%d%d , &a[i][j], &b[i][j], &c[i][j]); } } int v; for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { memset(dp, 0, sizeof(dp)); for (x = 1; x <= m; x++) { for (v = p; v >= 0; v--) { for (num = 0; num <= c[i][x]; num++) { int pro = b[j][x] - a[i][x]; if (v - num >= 0 && dp[v] < dp[v - num] + pro * num) { dp[v] = dp[v - num] + pro * num; ans = max(ans, dp[v]); } else if (v - num < 0) break; } } } } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k; bool ask(int x, int y) { if (x < 0 || y > n) return 0; string s; cout << 1 << << x << << y << endl; cin >> s; return s == TAK ; } int solve(int l, int r) { if (l > r) return -1; int mid; while (l < r) { mid = (l + r) >> 1; if (ask(mid, mid + 1)) r = mid; else l = mid + 1; } return l; } int main() { int i, j; cin >> n >> k; int ans1 = solve(1, n); int ans2 = solve(1, ans1 - 1); if (!ask(ans2, ans1)) ans2 = solve(ans1 + 1, n); cout << 2 << << ans1 << << ans2 << endl; return 0; }
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
wire no, po;
reg d, c;
rnmos n (no, d, c);
rpmos p (po, d, c);
initial begin
c = 0;
d = 0;
#1 if (no !== 1'bz) begin
$display("FAILED -- n (%b, %b, %b)", no, d, c);
$finish;
end
if (po !== 1'b0) begin
$display("FAILED -- p (%b, %b, %b)", po, d, c);
$finish;
end
d = 1;
#1 if (no !== 1'bz) begin
$display("FAILED -- n (%b, %b, %b)", no, d, c);
$finish;
end
if (po !== 1'b1) begin
$display("FAILED -- p (%b, %b, %b)", po, d, c);
$finish;
end
c = 1;
#1 if (no !== 1'b1) begin
$display("FAILED -- n (%b, %b, %b)", no, d, c);
$finish;
end
if (po !== 1'bz) begin
$display("FAILED -- p (%b, %b, %b)", po, d, c);
$finish;
end
d = 0;
#1 if (no !== 1'b0) begin
$display("FAILED -- n (%b, %b, %b)", no, d, c);
$finish;
end
if (po !== 1'bz) begin
$display("FAILED -- p (%b, %b, %b)", po, d, c);
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; long long a1[1000007], b1[1000007]; int main() { long long n, i, j, k = 0; cin >> n; for (i = 0; i < n; i++) { string st; cin >> st; long long si = st.size(), c1 = 0, c2 = 0; for (j = 0; j < si; j++) { if (st[j] == ( ) { c1++; } if (st[j] == ) ) { if (c1 > 0) { c1--; } else { c2++; } } } if (c1 == 0 && c2 == 0) k++; else if (c2 == 0) a1[c1]++; else if (c1 == 0) b1[c2]++; } long long ans = 0; ans = ans + (k / 2); for (i = 0; i <= 1000007; i++) { ans = ans + min(a1[i], b1[i]); } cout << ans << endl; return 0; }
|
/*
* This module demonstrates the ability to use a defparam to control
* the instantation of an instance array, and to also control
* parameter values within the instance array.
*/
module main;
localparam wid = 5;
reg [wid-1:0] clk;
if (wid > 0) begin : D
dut xx (.clk(clk));
end
// This defparam sets the desired with of the U instance vector.
defparam main.D.xx.wid = wid;
// These defparams set parameters within U instances.
defparam main.D.xx.sub[0].U.number = 0;
defparam main.D.xx.sub[1].U.number = 1;
defparam main.D.xx.sub[2].U.number = 2;
defparam main.D.xx.sub[3].U.number = 3;
defparam main.D.xx.sub[4].U.number = 4;
initial begin
clk = 0;
#1 clk = 1;
while (clk != 0)
#1 clk = clk << 1;
$finish;
end
endmodule // main
module dut #(parameter wid = 1) (input [wid-1:0] clk);
genvar i;
for (i = 0 ; i < wid ; i = i+1) begin : sub
target U (.clk(clk[i]));
end
endmodule //
module target(input wire clk);
parameter number = 999;
always @(posedge clk)
$display("%m: number=%0d", number);
endmodule // target
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $
//
// $Date: 2005/02/27 09:26:24 $
// $Revision: 1.11 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: i2c_master_top.v,v $
// Revision 1.11 2005/02/27 09:26:24 rherveille
// Fixed register overwrite issue.
// Removed full_case pragma, replaced it by a default statement.
//
// Revision 1.10 2003/09/01 10:34:38 rherveille
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
// Revision 1.9 2003/01/09 16:44:45 rherveille
// Fixed a bug in the Command Register declaration.
//
// Revision 1.8 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.7 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.6 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.5 2001/11/10 10:52:55 rherveille
// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
// synopsys translate_off
`timescale 1ns / 100ps
// synopsys translate_on
`define I2C_CMD_NOP 4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP 4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ 4'b1000
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b1; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
wire wb_cyc_i = wb_stb_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (~rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 2'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; struct edge { int u, v; long long g, s; bool operator<(const edge &cmp) const { return s < cmp.s; } } e[50005], a[50005]; int n, m, cnt, p[205], tam; long long gt, st; bool cmpG(edge a, edge b) { return a.g < b.g; } int find(int x) { if (p[x] == x) return x; return p[x] = find(p[x]); } bool link(int &a, int &b) { if (find(a) == find(b)) return false; p[find(a)] = find(b); return true; } long long kruskal() { long long res = 0; cnt = 0; for (int i = 1; i <= n; ++i) p[i] = i; sort(a, a + tam); for (int i = 0; i < tam; ++i) { if (link(a[i].u, a[i].v)) { res = a[i].s; a[cnt++] = a[i]; } } tam = cnt; return res; } int main() { scanf( %d%d , &n, &m); scanf( %I64d%I64d , >, &st); long long res = 1ll << 62, sil; cnt = tam = 0; for (int i = 0; i < m; ++i) { scanf( %d%d%I64d%I64d , &e[i].u, &e[i].v, &e[i].g, &e[i].s); e[i].g *= gt; e[i].s *= st; } sort(e, e + m, cmpG); for (int i = 0; i < m; ++i) { a[tam++] = e[i]; sil = kruskal(); if (cnt == n - 1) { sil += e[i].g; if (sil < res) res = sil; } } if (res < 1ll << 62) printf( %I64d n , res); else printf( -1 n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int sum = 0; int d; for (int i = 0; i < n; i++) { cin >> d; sum += d; } int count = 5; for (int i = 1; i <= 5; i++) { if ((sum + i) % (n + 1) == 1) { count--; } } cout << count << endl; }
|
#include <bits/stdc++.h> using namespace std; int a[55][55]; const int MAX = 1e3 + 5; const int INF = 0x3f3f3f3f; int color; int A[MAX][MAX]; int A1[MAX][MAX], A2[MAX][MAX]; int N; int DX[2] = {0, 1}, DY[2] = {1, 0}; int NOW1[4], NOW2[4]; int X1, Y1, X2, Y2; bool FLAG = false; bool VIS[MAX][MAX]; void dfs(int x, int y, int count) { if (FLAG) return; if (count == 4) { if (NOW1[1] == NOW1[2] && NOW1[0] == NOW1[3]) { if (NOW2[1] != NOW2[2] || NOW2[0] != NOW2[3]) { FLAG = true; X2 = x, Y2 = y; color = 1; return; } } if (NOW2[1] == NOW2[2] && NOW2[0] == NOW2[3]) { if (NOW1[1] != NOW1[2] || NOW1[0] != NOW1[3]) { FLAG = true; X2 = x, Y2 = y; color = 2; return; } } return; } for (int i = 0; i < 2; ++i) { int numX = x + DX[i]; int numY = y + DY[i]; if (numX >= 1 && numX <= N && numY >= 1 && numY <= N && !VIS[numX][numY]) { NOW1[count] = A1[numX][numY]; NOW2[count] = A2[numX][numY]; VIS[numX][numY] = true; dfs(numX, numY, count + 1); VIS[numX][numY] = false; } } } void solve() { for (int i = 1; i <= N; ++i) { for (int j = 1; j <= N; ++j) { A[i][j] = a[i][j]; if ((i + j) & 1) { if (A[i][j] == 0) A1[i][j] = 1, A2[i][j] = 0; else A1[i][j] = 0, A2[i][j] = 1; } else A1[i][j] = A2[i][j] = A[i][j]; } } for (int i = 1; i <= N; ++i) { for (int j = 1; j <= N; ++j) { NOW1[0] = A1[i][j]; NOW2[0] = A2[i][j]; VIS[i][j] = true; dfs(i, j, 1); VIS[i][j] = false; if (FLAG) { X1 = i, Y1 = j; return; } } } } int main() { int n, t; scanf( %d , &n); N = n; a[1][1] = 1; a[1][2] = 0; a[n][n] = 0; printf( ? %d %d %d %d n , 1, 2, 2, 3); fflush(stdout); scanf( %d , &t); if (t == 1) a[2][3] = a[1][2]; else a[2][3] = a[1][2] ^ 1; printf( ? %d %d %d %d n , 2, 1, 2, 3); fflush(stdout); scanf( %d , &t); if (t == 1) a[2][1] = a[2][3]; else a[2][1] = a[2][3] ^ 1; for (int i = 3; i <= n; i++) { printf( ? %d %d %d %d n , i - 2, 1, i, 1); fflush(stdout); scanf( %d , &t); if (t == 1) a[i][1] = a[i - 2][1]; else a[i][1] = a[i - 2][1] ^ 1; printf( ? %d %d %d %d n , 1, i - 2, 1, i); fflush(stdout); scanf( %d , &t); if (t == 1) a[1][i] = a[1][i - 2]; else a[1][i] = a[1][i - 2] ^ 1; } for (int i = 2; i <= n; i++) { for (int j = 2; j <= n; j++) { if (i == j && j == n) continue; if (i == 2 && j == 3) continue; printf( ? %d %d %d %d n , i - 1, j - 1, i, j); fflush(stdout); scanf( %d , &t); if (t == 1) a[i][j] = a[i - 1][j - 1]; else a[i][j] = a[i - 1][j - 1] ^ 1; } } solve(); printf( ? %d %d %d %d n , X1, Y1, X2, Y2); fflush(stdout); scanf( %d , &t); printf( ! n ); if (t == 1) { if (color == 1) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if ((i + j) % 2 == 1) printf( %d , a[i][j] ^ 1); else printf( %d , a[i][j]); } printf( n ); } } else { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) printf( %d , a[i][j]); printf( n ); } } } else { if (color == 2) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if ((i + j) % 2 == 1) printf( %d , a[i][j] ^ 1); else printf( %d , a[i][j]); } printf( n ); } } else { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) printf( %d , a[i][j]); printf( n ); } } } }
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// DUC block
module duc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_interp_out, q_interp_out;
wire [31:0] phase;
wire strobe1, strobe2;
reg [3:0] strobe_ctr1,strobe_ctr2;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr2 <= #1 4'd0;
else if(strobe2)
strobe_ctr2 <= #1 4'd0;
else
strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr1 <= #1 4'd0;
else if(strobe1)
strobe_ctr1 <= #1 4'd0;
else if(strobe2)
strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
assign strobe2 = enable & ( strobe_ctr2 == rate2 );
assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
assign strobe = strobe1;
function [2:0] log_ceil;
input [3:0] val;
log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
endfunction
wire [2:0] shift1 = log_ceil(rate1);
wire [2:0] shift2 = log_ceil(rate2);
cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
cordic(.clock(clock), .reset(reset), .enable(enable),
.xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]),
.xo(i_out), .yo(q_out), .zo() );
cic_interp_2stage #(.bw(bw),.N(4))
interp_i(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(i_in),.signal_out(i_interp_out));
cic_interp_2stage #(.bw(bw),.N(4))
interp_q(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(q_in),.signal_out(q_interp_out));
phase_acc #(.resolution(32))
nco (.clk(clock),.reset(reset),.enable(enable),
.freq(freq),.phase(phase));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_BLACKBOX_V
/**
* udp_dff$P_pp$PKG$sN: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$PKG$sN (
Q ,
D ,
CLK ,
SLEEP_B ,
NOTIFIER,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK ;
input SLEEP_B ;
input NOTIFIER;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int q, w, e, r, t; char a[51]; cin >> a; if (a[0] == h ) { cout << http:// ; w = 4; } else { cout << ftp:// ; w = 3; } cout << a[w]; w++; while ((a[w] != r ) || (a[w + 1] != u )) { cout << a[w]; w++; } cout << .ru ; w += 2; if (a[w]) { cout << / ; while (a[w]) { cout << a[w]; w++; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2 * 1e5 + 100; vector<int> Prime; int main() { Prime.clear(); int n, k; scanf( %d%d , &n, &k); int flag = 1; for (int i = 2; flag && i <= n; i++) { if (n % i == 0) { while (n % i == 0) { Prime.push_back(i); n /= i; } if (n == 1) { flag = 0; } if (n < i && n > 1) { flag = 0; Prime.push_back(n); } } } if (Prime.size() < k) { cout << -1 << endl; } else { for (int i = 0; i < k - 1; i++) { cout << Prime[i] << ; } int ans = 1; for (int i = k - 1; i < Prime.size(); i++) { ans *= Prime[i]; } if (ans != 1) { cout << ans << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1050; int n, m, g[maxn][maxn], ans[maxn][maxn]; int p[4] = {4, 3, 2, 1}; bool chk1(int x, int a, int b) { int i, st, c[2] = {a, b}; for (st = 0; st < m && !g[x][st]; st++) ; if (g[x][st] != c[0]) swap(c[0], c[1]); for (i = 0; st + i < m; i++) if (g[x][st + i] && g[x][st + i] != c[i & 1]) return 0; else ans[x][st + i] = c[i & 1]; for (i = 1; i <= st; i++) ans[x][st - i] = c[i & 1]; return 1; } bool chk2(int x, int a, int b) { int i, st, c[2] = {a, b}; for (st = 0; st < n && !g[st][x]; st++) ; if (g[st][x] != c[0]) swap(c[0], c[1]); for (i = 0; st + i < n; i++) if (g[st + i][x] && g[st + i][x] != c[i & 1]) return 0; else ans[st + i][x] = c[i & 1]; for (i = 1; i <= st; i++) ans[st - i][x] = c[i & 1]; return 1; } void print() { int i, j; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) printf( %d , ans[i][j]); printf( n ); } } bool check() { int i, j; bool z = 1; for (i = 0; i < n; i++) z &= chk1(i, p[(i & 1) * 2], p[(i & 1) * 2 + 1]); if (z) { print(); return 1; } z = 1; for (i = 0; i < m; i++) z &= chk2(i, p[(i & 1) * 2], p[(i & 1) * 2 + 1]); if (z) { print(); return 1; } return 0; } int main() { int i, j; scanf( %d%d n , &n, &m); for (i = 0; i < n; i++) { for (j = 0; j < m; j++) g[i][j] = getchar() - 0 ; scanf( n ); } for (i = 0; i < 4 * 3 * 2; i++) { next_permutation(p, p + 4); if (check()) return 0; } printf( 0 n ); return 0; }
|
// Motion in perpendicular plane will cause variations on the specific axis, note that this represent motion AROUND a specific axis
// z-axis = side to side (short)
// y-axis = side to side (long)
// x-axis = vertical
/*
---------------------------------|----------------------------------
---------------------------------|- Y - Axis -----------------------
---------------------------------|----------------------------------
---------------------------------|----------------------------------
---------------------=========================----------------------
---------------------|| ||----------------------
---------------------|| ||______________________
---------------------|| DE0-Nano ||--- X - Axis ---------
---------------------|| ||----------------------
---------------------|| ||----------------------
---------------------=========================----------------------
---------------------------------|----------------------------------
---------------------------------|----------------------------------
---------------------------------|----------------------------------
---------------------------------|----------------------------------
*/
module imu(
input reset_n,
input spi_clk,
input sys_clk,
inout sda,
output scl,
output [8*32-1:0] adc_channels,
//////////// ADC //////////
input ADC_SDAT,
output ADC_CS_N,
output ADC_SADDR,
output ADC_SCLK
);
///=======================================================
// REG/WIRE declarations
//=======================================================
wire [11:0] ADC_12_bit_channel_0;
wire [11:0] ADC_12_bit_channel_1;
wire [11:0] ADC_12_bit_channel_2;
wire [11:0] ADC_12_bit_channel_3;
wire [11:0] ADC_12_bit_channel_4;
wire [11:0] ADC_12_bit_channel_5;
wire [11:0] ADC_12_bit_channel_6;
wire [11:0] ADC_12_bit_channel_7;
/* The GPIO 2 pin layout
1 0
3 2
5 4
7 6
9 8
11 10
ADC5 12
ADC7 ADC7
ADC2 ADC3
ADC0 ADC4
GND ADC1
*/
// ADC connections, on chip
ADC_CTRL adc_controller_8_channels (
.iRST(!reset_n),
.iCLK(spi_clk),
.iCLK_n(!spi_clk),
.iGO(1'b1),
.oDIN(ADC_SADDR),
.oCS_n(ADC_CS_N),
.oSCLK(ADC_SCLK),
.iDOUT(ADC_SDAT),
.oADC_12_bit_channel_0(ADC_12_bit_channel_0),
.oADC_12_bit_channel_1(ADC_12_bit_channel_1),
.oADC_12_bit_channel_2(ADC_12_bit_channel_2),
.oADC_12_bit_channel_3(ADC_12_bit_channel_3),
.oADC_12_bit_channel_4(ADC_12_bit_channel_4),
.oADC_12_bit_channel_5(ADC_12_bit_channel_5),
.oADC_12_bit_channel_6(ADC_12_bit_channel_6),
.oADC_12_bit_channel_7(ADC_12_bit_channel_7)
);
assign adc_channels[1*32-1:0*32] = {20'd0, ADC_12_bit_channel_0};
assign adc_channels[2*32-1:1*32] = {20'd0, ADC_12_bit_channel_1};
assign adc_channels[3*32-1:2*32] = {20'd0, ADC_12_bit_channel_2};
assign adc_channels[4*32-1:3*32] = {20'd0, ADC_12_bit_channel_3};
assign adc_channels[5*32-1:4*32] = {20'd0, ADC_12_bit_channel_4};
assign adc_channels[6*32-1:5*32] = {20'd0, ADC_12_bit_channel_5};
assign adc_channels[7*32-1:6*32] = {20'd0, ADC_12_bit_channel_6};
assign adc_channels[8*32-1:7*32] = {20'd0, ADC_12_bit_channel_7};
endmodule
|
// ---------------------------------------------
// external memory controller
// ---------------------------------------------
// The CPU runs at ~50MHz (20ns)
//
// When accessing byte-wide external memory, sufficient wait states
// need to be added to allow two slower memory cycles to happen
// (low byte then high byte)
//
// IS61WV25616EDBLL-10TLI RAM timings:
// -- Read access time is 10ns
//
// -- Min write pulse is 8ns, write happens on rising edge
// -- Address setup from falling edge of write is 8ns
// -- Address hold from rising edge of write is 0ns
// -- Data setup from rising edge of write is 9ns
// -- Address hold from rising edge of write is 0ns
//
// We allow one cycle of address/data setup, followed by two memory cycles
//
// So a complete external memory access (both 16-bit half-words) takes 3 cycles
//
// Which means the memory controller must insert 2 wait states
module memory_controller
(
clock,
reset_b,
// CPU Signals
ext_cs_b,
cpu_rnw,
cpu_clken,
cpu_addr,
cpu_dout,
ext_dout,
// Ram Signals
ram_cs_b,
ram_oe_b,
ram_we_b,
ram_data_in,
ram_data_out,
ram_data_oe,
ram_addr
);
parameter DSIZE = 32;
parameter ASIZE = 20;
input clock;
input reset_b;
// CPU Signals
input ext_cs_b;
input cpu_rnw;
output cpu_clken;
input [ASIZE-1:0] cpu_addr;
input [DSIZE-1:0] cpu_dout;
output [DSIZE-1:0] ext_dout;
// Ram Signals
output ram_cs_b;
output ram_oe_b;
output ram_we_b;
output [17:0] ram_addr;
input [15:0] ram_data_in;
output [15:0] ram_data_out;
output ram_data_oe;
wire ext_a_lsb;
reg [15:0] ram_data_last;
reg [1:0] count;
// Count 0..2 during external memory cycles
always @(posedge clock)
if (!reset_b) begin
count <= 0;
end else if (count == 0) begin
if (!ext_cs_b)
count <= 1;
end else if (count == 1) begin
count <= 2;
end else begin
count <= 0;
end
// Drop clken for 2 cycles during an external memory access
assign cpu_clken = !(!ext_cs_b && count < 2);
// A0 = 0 for count 0,1 (low half-word) and A0 = 1 for count 2 (high half-word)
assign ext_a_lsb = count[1];
// The low byte is registered at the end of cycle 1
// The high byte is consumed directly from RAM at the end of cycle 2
always @(posedge clock)
ram_data_last <= ram_data_in;
assign ext_dout = { ram_data_in, ram_data_last };
// ---------------------------------------------
// external RAM
// ---------------------------------------------
assign ram_addr = {cpu_addr[16:0], ext_a_lsb};
assign ram_cs_b = ext_cs_b;
assign ram_oe_b = !cpu_rnw;
assign ram_we_b = ext_cs_b | cpu_rnw | (!clock);
assign ram_data_oe = !cpu_rnw;
assign ram_data_out = ext_a_lsb == 1 ? cpu_dout[31:16] :
cpu_dout[15:0] ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int dx[] = {0, 1, -1, 0, 1, -1, -1, 1}; const long long int dy[] = {-1, 0, 0, 1, 1, 1, -1, -1}; long long int gcd(long long int x, long long int y) { return (y != 0 ? gcd(y, x % y) : x); } long long int lcm(long long int x, long long int y) { return (x / gcd(x, y) * y); } struct edge { int viz; int cap; int cost; int dual; edge() {} edge(int viz, int cap, int cost, int dual) : viz(viz), cap(cap), cost(cost), dual(dual) {} }; int pro[3054]; int spo[3054]; vector<edge> g[3054]; int d[3054]; int p[3054]; int p_edge[3054]; int color[3054]; int flow; int fcost; void add_edge(int x, int y, int cap, int cost) { g[x].push_back(edge(y, cap, cost, (int)g[y].size())); g[y].push_back(edge(x, 0, -cost, (int)g[x].size() - 1)); } int SPFA(int s, int t) { queue<int> fila; for (int i = 0; i <= t; i++) { d[i] = 1000000000; color[i] = 0; } d[s] = 0; fila.push(s); while (!fila.empty()) { int next = fila.front(); color[next] = 0; fila.pop(); for (int i = 0; i < (int)g[next].size(); i++) { int viz = g[next][i].viz; int cap = g[next][i].cap; int cost = d[next] + g[next][i].cost; if (cap > 0 && d[viz] > cost) { d[viz] = cost; p_edge[viz] = i; p[viz] = next; if (color[viz] == 0) { fila.push(viz); color[viz] = 1; } } } } return d[t] != 1000000000; } void mcmf(int s, int t) { while (SPFA(s, t)) { int augment = 1000000000; for (int v = t; v != s; v = p[v]) { int idx = p_edge[v]; augment = min(augment, g[p[v]][idx].cap); } for (int v = t; v != s; v = p[v]) { int idx = p_edge[v]; int dual = g[p[v]][idx].dual; g[p[v]][idx].cap -= augment; g[v][dual].cap += augment; } flow += augment; fcost += d[t] * augment; } return; } int main(void) { int src = 3054 - 1; int sink = 3054 - 2; int sports = 3054 - 3; int programming = 3054 - 4; int n, pp, ss; cin >> n >> pp >> ss; for (int i = 0; i < n; i++) { add_edge(src, i, 1, 0); cin >> pro[i]; add_edge(i, programming, 1, -pro[i]); } for (int i = 0; i < n; i++) { cin >> spo[i]; add_edge(i, sports, 1, -spo[i]); } add_edge(programming, sink, pp, 0); add_edge(sports, sink, ss, 0); mcmf(src, sink); cout << -fcost << endl; vector<int> saida1, saida2; for (int i = 0; i < n; i++) { if (g[i][1].cap == 0) { saida1.push_back(i + 1); } if (g[i][2].cap == 0) { saida2.push_back(i + 1); } } for (int i = 0; i < saida1.size(); i++) { cout << saida1[i] << ; } cout << endl; for (int i = 0; i < saida2.size(); i++) { cout << saida2[i] << ; } cout << endl; return 0; }
|
module nexys4
(
input clk,
input btnCpuReset,
input btnC,
input btnU,
input btnL,
input btnR,
input btnD,
input [15:0] sw,
output [15:0] led,
output RGB1_Red,
output RGB1_Green,
output RGB1_Blue,
output RGB2_Red,
output RGB2_Green,
output RGB2_Blue,
output [ 6:0] seg,
output dp,
output [ 7:0] an,
inout [ 7:0] JA,
inout [ 7:0] JB,
input RsRx
);
// wires & inputs
wire clkCpu;
wire clkIn = clk;
wire rst_n = btnCpuReset;
wire clkEnable = sw [9] | btnU;
wire [ 3:0 ] clkDevide = sw [8:5];
wire [ 4:0 ] regAddr = sw [4:0];
wire [ 31:0 ] regData;
//cores
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clkCpu ),
.regAddr ( regAddr ),
.regData ( regData )
);
//outputs
assign led[0] = clkCpu;
assign led[15:1] = regData[14:0];
//hex out
wire [ 31:0 ] h7segment = regData;
wire clkHex;
sm_clk_divider hex_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( 4'b1 ),
.enable ( 1'b1 ),
.clkOut ( clkHex )
);
sm_hex_display_8 sm_hex_display_8
(
.clock ( clkHex ),
.resetn ( rst_n ),
.number ( h7segment ),
.seven_segments ( seg ),
.dot ( dp ),
.anodes ( an )
);
assign RGB1_Red = 1'b0;
assign RGB1_Green = 1'b0;
assign RGB1_Blue = 1'b0;
assign RGB2_Red = 1'b0;
assign RGB2_Green = 1'b0;
assign RGB2_Blue = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; double f(double x, double A, double B, double L) { double y = sqrt(L * L - x * x); return (A * x + B * y - x * y) / L; } int main(void) { double A, B, L; scanf( %lf%lf%lf , &A, &B, &L); if (L <= B) { printf( %.8f n , min(A, L)); return 0; } else if (L <= A) { printf( %.8f n , min(B, L)); return 0; } else { double left = 0.0, right = L, ma, mb; for (int u = 0; u < 500; u++) { ma = (left * 3 + right) / 4.0; mb = (left + right * 3) / 4.0; double fa = f(ma, A, B, L); double fb = f(mb, A, B, L); if (fa < fb) right = mb; else left = ma; } double ff = f((left + right) / 2.0, A, B, L); ff = min(ff, L); ff = min(ff, A); if (ff < 1e-8) printf( My poor head =( n ); else printf( %.8f n , ff); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long tt; cin >> tt; while (tt--) { long long n; cin >> n; vector<long long> v(n); for (auto &i : v) cin >> i; bool ans = false; for (size_t i = 0; i < n; i++) { if (v[i] >= v[i - 1]) { ans = true; break; } } cout << ((ans) ? YES : NO ) << n ; } }
|
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